summaryrefslogtreecommitdiffstats
path: root/sys/contrib
diff options
context:
space:
mode:
authorjmallett <jmallett@FreeBSD.org>2012-03-13 06:48:26 +0000
committerjmallett <jmallett@FreeBSD.org>2012-03-13 06:48:26 +0000
commita97eb5970d0b089d451f035b04c5ac27e84607c8 (patch)
tree96de6c069c94516a8e4930408e2bc59badb2d8f3 /sys/contrib
parenta7180c207d84ff97a6de5317a6ac48b9c22cffa4 (diff)
downloadFreeBSD-src-a97eb5970d0b089d451f035b04c5ac27e84607c8.zip
FreeBSD-src-a97eb5970d0b089d451f035b04c5ac27e84607c8.tar.gz
Remove some files not used by the FreeBSD kernel which have been adding quite
a bit of bloat to the kernel source tree's size.
Diffstat (limited to 'sys/contrib')
-rw-r--r--sys/contrib/octeon-sdk/cvmx-csr-db-support.c264
-rw-r--r--sys/contrib/octeon-sdk/cvmx-csr-db.c234515
-rw-r--r--sys/contrib/octeon-sdk/cvmx-csr-db.h194
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-custom.c889
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-custom.h92
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c3504
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c3835
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c4866
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c4423
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c3606
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c6665
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c6564
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c7659
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c7210
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c4939
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c4922
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn61xx.c9132
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c7265
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c6761
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn66xx.c9166
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn68xx.c14045
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cn68xxp1.c14007
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error-init-cnf71xx.c5784
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error.c773
-rw-r--r--sys/contrib/octeon-sdk/cvmx-error.h330
-rw-r--r--sys/contrib/octeon-sdk/cvmx-pcie.c2
-rw-r--r--sys/contrib/octeon-sdk/cvmx-twsi.c2
-rw-r--r--sys/contrib/octeon-sdk/cvmx-usb.c2
28 files changed, 6 insertions, 361410 deletions
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-db-support.c b/sys/contrib/octeon-sdk/cvmx-csr-db-support.c
deleted file mode 100644
index 2638d09..0000000
--- a/sys/contrib/octeon-sdk/cvmx-csr-db-support.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-
-
-
-
-
-/**
- * @file
- *
- * Utility functions for working with the CSR database
- *
- * <hr>$Revision: 70030 $<hr>
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#define PRINTF printk
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-csr-db.h>
-#else
-#define PRINTF printf
-#include "cvmx.h"
-#include "cvmx-csr-db.h"
-#endif
-
-/**
- * Figure out which database to use for this chip. The passed
- * identifier can be a processor ID or a PCI ID.
- *
- * @param identifier processor ID or a PCI ID
- *
- * @return index into the csr db
- */
-int cvmx_db_get_chipindex(int identifier)
-{
- /* First try and see if the identifier is a Processor ID */
- switch (identifier & 0xffff00)
- {
- case 0x000d0600: /* CN50XX */
- return 8;
- case 0x000d0400: /* CN56XX */
- return 7;
- case 0x000d0300: /* CN58XX */
- return 5;
- case 0x000d0000: /* CN38XX */
- return 3;
- case 0x000d0100: /* CN31XX */
- return 1;
- case 0x000d0200: /* CN3010 */
- return 2;
- case 0x000d0700: /* CN52XX */
- return 10;
- case 0x000d9300: /* CN61XX */
- return 11;
- case 0x000d9000: /* CN63XX */
- return 13;
- case 0x000d9200: /* CN66XX */
- return 14;
- case 0x000d9100: /* CN68XX */
- return 16;
- case 0x000d9400: /* CNF71XX */
- return 17;
- }
-
- /* Next try PCI device IDs */
- switch (identifier)
- {
- case 0x0003177d: /* CN38XX Pass 1 */
- return 0;
- case 0x0004177d: /* CN38XX Pass 2 */
- return 0;
- case 0x0005177d: /* CN38XX Pass 3 */
- return 3;
- case 0x1001177d: /* Thunder */
- return 3;
- case 0x0020177d: /* CN31XX Pass 1 */
- return 1;
- case 0x0030177d: /* CN30XX Pass 1 */
- return 2;
- case 0x0040177d: /* CN58XX Pass 2 */
- return 5;
- case 0x0050177d: /* CN56XX Pass 2 */
- return 7;
- case 0x0070177d: /* CN50XX Pass 1 */
- return 8;
- case 0x0080177d: /* CN52XX Pass 2 */
- return 10;
- case 0x0093177d: /* CN61XX Pass 2 */
- return 11;
- case 0x0090177d: /* CN63XX Pass 2 */
- return 13;
- case 0x0092177d: /* CN66XX Pass 1 */
- return 14;
- case 0x0091177d: /* CN68XX Pass 2 */
- return 16;
- case 0x0094177d: /* CNF71XX Pass 1 */
- return 17;
- }
-
- /* Default to Pass 3 if we don't know */
- return 3;
-}
-
-
-#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
-/**
- * Get the CSR DB entry for the passed Octeon model and CSR name. The
- * model can either be specified as a processor id or PCI id.
- *
- * @param identifier Identifer to choose the CSR DB with
- * @param name CSR name to lookup
- *
- * @return CSR DB entry or NULL on failure
- */
-const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_get(int identifier, const char *name)
-{
- int chip = cvmx_db_get_chipindex(identifier);
- int i=0;
- if (strncasecmp(name, "CVMX_", 5) == 0)
- name += 5;
- while (cvmx_csr_db_addresses[chip][i].name)
- {
- if (strcasecmp(name, cvmx_csr_db_addresses[chip][i].name) == 0)
- return &(cvmx_csr_db_addresses[chip][i]);
- i++;
- }
- return NULL;
-}
-#endif
-
-static void __cvmx_csr_db_decode_csr(int chip, int index, uint64_t value)
-{
- int field;
- int csr = cvmx_csr_db_addresses[chip][index].csroff;
- PRINTF("%s(0x%016llx) = 0x%016llx\n", cvmx_csr_db_addresses[chip][index].name, (unsigned long long)cvmx_csr_db_addresses[chip][index].address, (unsigned long long)value);
- for (field=cvmx_csr_db[chip][csr].fieldoff+cvmx_csr_db[chip][csr].numfields-1; field>=cvmx_csr_db[chip][csr].fieldoff; field--)
- {
- uint64_t v = (value >> cvmx_csr_db_fields[chip][field].startbit);
- if(cvmx_csr_db_fields[chip][field].sizebits < 64)
- v = v & ~((~0x0ull) << cvmx_csr_db_fields[chip][field].sizebits);
- if (cvmx_csr_db_fields[chip][field].sizebits == 1)
- PRINTF(" [ %2d] %-20s = %10llu (0x%llx)\n",
- cvmx_csr_db_fields[chip][field].startbit, cvmx_csr_db_fields[chip][field].name,
- (unsigned long long)v, (unsigned long long)v);
- else
- PRINTF(" [%2d:%2d] %-20s = %10llu (0x%llx)\n",
- cvmx_csr_db_fields[chip][field].startbit + cvmx_csr_db_fields[chip][field].sizebits - 1,
- cvmx_csr_db_fields[chip][field].startbit,
- cvmx_csr_db_fields[chip][field].name,
- (unsigned long long)v, (unsigned long long)v);
- }
-}
-
-/**
- * Decode a CSR value into named bitfields. The model can either
- * be specified as a processor id or PCI id.
- *
- * @param identifier Identifer to choose the CSR DB with
- * @param address CSR address being decoded
- * @param value Value to decode
- */
-void cvmx_csr_db_decode(int identifier, uint64_t address, uint64_t value)
-{
- int chip = cvmx_db_get_chipindex(identifier);
- int index=0;
- /* Strip off the upper 8 bits since they are normally mips addressing
- modes */
- address &= (1ull<<56)-1;
- while (cvmx_csr_db_addresses[chip][index].name)
- {
- if (cvmx_csr_db_addresses[chip][index].address == address)
- __cvmx_csr_db_decode_csr(chip, index, value);
- index++;
- }
-}
-
-/**
- * Decode a CSR value into named bitfields. The model can either
- * be specified as a processor id or PCI id.
- *
- * @param identifier Identifer to choose the CSR DB with
- * @param name CSR name to decode
- * @param value Value to decode
- */
-void cvmx_csr_db_decode_by_name(int identifier, const char *name, uint64_t value)
-{
- int chip = cvmx_db_get_chipindex(identifier);
- int index=0;
- while (cvmx_csr_db_addresses[chip][index].name)
- {
- if (strcasecmp(name, cvmx_csr_db_addresses[chip][index].name) == 0)
- {
- __cvmx_csr_db_decode_csr(chip, index, value);
- break;
- }
- index++;
- }
-}
-
-
-#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
-/**
- * Print a list of csrs begimning with a prefix. The
- * model can either be specified as a processor id or PCI id.
- *
- * @param identifier Identifer to choose the CSR DB with
- * @param prefix Beginning prefix to look for
- */
-void cvmx_csr_db_display_list(int identifier, const char *prefix)
-{
- int i, len;
- int chip = cvmx_db_get_chipindex(identifier);
- if (prefix == NULL)
- prefix = "";
- if (strncasecmp(prefix, "CVMX_", 5) == 0)
- prefix += 5;
- len = strlen(prefix);
-
- i=0;
- while (cvmx_csr_db_addresses[chip][i].name)
- {
- if (strncasecmp(prefix, cvmx_csr_db_addresses[chip][i].name, len) == 0)
- PRINTF("%s\n", cvmx_csr_db_addresses[chip][i].name);
- i++;
- }
-}
-#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-db.c b/sys/contrib/octeon-sdk/cvmx-csr-db.c
deleted file mode 100644
index 3a83e22..0000000
--- a/sys/contrib/octeon-sdk/cvmx-csr-db.c
+++ /dev/null
@@ -1,234515 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Configuration and status register (CSR) address and type definitions for
- * Octeon.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision: 69515 $<hr>
- *
- */
-
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-csr-db.h>
-#else
-#include "cvmx-csr-db.h"
-#endif
-
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xxp2[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 4, 0},
- {"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 4, 4},
- {"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 3, 8},
- {"cvmx_asx#_rld_bypass" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 11},
- {"cvmx_asx#_rld_bypass_setting", CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 13},
- {"cvmx_asx#_rld_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 3, 15},
- {"cvmx_asx#_rld_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 3, 18},
- {"cvmx_asx#_rld_fcram_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 21},
- {"cvmx_asx#_rld_nctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 23},
- {"cvmx_asx#_rld_nctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 25},
- {"cvmx_asx#_rld_pctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 27},
- {"cvmx_asx#_rld_pctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 29},
- {"cvmx_asx#_rld_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 31},
- {"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 33},
- {"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 35},
- {"cvmx_asx#_rx_wol" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 3, 37},
- {"cvmx_asx#_rx_wol_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 1, 40},
- {"cvmx_asx#_rx_wol_powok" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 2, 41},
- {"cvmx_asx#_rx_wol_sig" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 43},
- {"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 45},
- {"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 3, 47},
- {"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 50},
- {"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 52},
- {"cvmx_asx0_dbg_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 3, 54},
- {"cvmx_asx0_dbg_data_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 2, 57},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 66, 2, 59},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 67, 2, 61},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 68, 2, 63},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 69, 2, 65},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 70, 15, 67},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 103, 2, 82},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 136, 15, 84},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 169, 2, 99},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 170, 2, 101},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 2, 103},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 202, 2, 105},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 203, 2, 107},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 204, 2, 109},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 205, 1, 111},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 221, 3, 112},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 222, 2, 115},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 223, 4, 117},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 2, 121},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 3, 123},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 229, 7, 126},
- {"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 245, 7, 133},
- {"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 3, 140},
- {"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 247, 10, 143},
- {"cvmx_dfa_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 248, 2, 153},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 249, 2, 155},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 250, 4, 157},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 251, 3, 161},
- {"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 21, 164},
- {"cvmx_dfa_memcfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 253, 16, 185},
- {"cvmx_dfa_memcfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 11, 201},
- {"cvmx_dfa_memcfg2" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 8, 212},
- {"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 256, 6, 220},
- {"cvmx_dfa_memfcr" , CVMX_CSR_DB_TYPE_RSL, 64, 257, 6, 226},
- {"cvmx_dfa_memrld" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 232},
- {"cvmx_dfa_ncbctl" , CVMX_CSR_DB_TYPE_RSL, 64, 259, 8, 234},
- {"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 260, 1, 242},
- {"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 1, 243},
- {"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 262, 1, 244},
- {"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 263, 1, 245},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 6, 246},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 265, 7, 252},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 266, 3, 259},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 2, 262},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 280, 3, 264},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 281, 2, 267},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 29, 269},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 283, 29, 298},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 284, 2, 327},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 2, 329},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 3, 331},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 301, 3, 334},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 2, 337},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 2, 339},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 304, 8, 341},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 306, 2, 349},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 3, 351},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 310, 2, 354},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 312, 5, 356},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 320, 1, 361},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 328, 1, 362},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 336, 1, 363},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 344, 1, 364},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 352, 1, 365},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 360, 1, 366},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 368, 2, 367},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 4, 369},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 384, 2, 373},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 11, 375},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 9, 386},
- {"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 395},
- {"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 2, 397},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 2, 399},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 20, 401},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 20, 421},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 441},
- {"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 4, 443},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 2, 447},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 2, 449},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 480, 2, 451},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 488, 2, 453},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 496, 2, 455},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 504, 2, 457},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 512, 2, 459},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 520, 2, 461},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 528, 2, 463},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 536, 2, 465},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 544, 4, 467},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 552, 2, 471},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 560, 2, 473},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 568, 2, 475},
- {"cvmx_gmx#_rx_pass_en" , CVMX_CSR_DB_TYPE_RSL, 64, 576, 2, 477},
- {"cvmx_gmx#_rx_pass_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 578, 2, 479},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 610, 2, 481},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 612, 2, 483},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 620, 3, 485},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 622, 5, 488},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 630, 2, 493},
- {"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 638, 2, 495},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 646, 3, 497},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 654, 2, 500},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 662, 2, 502},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 670, 2, 504},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 678, 2, 506},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 686, 2, 508},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 694, 2, 510},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 702, 2, 512},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 710, 2, 514},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 718, 2, 516},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 726, 2, 518},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 734, 2, 520},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 742, 2, 522},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 2, 524},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 2, 526},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 766, 2, 528},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 774, 2, 530},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 782, 2, 532},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 790, 2, 534},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 798, 2, 536},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 2, 538},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 2, 540},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 2, 542},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 3, 544},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 814, 7, 547},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 7, 554},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 818, 2, 561},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 2, 563},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 4, 565},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 2, 569},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 2, 571},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 2, 573},
- {"cvmx_gmx#_tx_spi_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 830, 3, 575},
- {"cvmx_gmx#_tx_spi_max" , CVMX_CSR_DB_TYPE_RSL, 64, 832, 3, 578},
- {"cvmx_gmx#_tx_spi_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 834, 2, 581},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 836, 7, 583},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 852, 2, 590},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 853, 2, 592},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 854, 2, 594},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 855, 2, 596},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 856, 19, 598},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 857, 6, 617},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 858, 3, 623},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 859, 3, 626},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 860, 3, 629},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 861, 5, 632},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 862, 5, 637},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 1, 642},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 864, 1, 643},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 5, 644},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 866, 5, 649},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 3, 654},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 868, 3, 657},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 869, 3, 660},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 870, 5, 663},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 871, 5, 668},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 872, 1, 673},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 873, 1, 674},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 874, 3, 675},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 3, 678},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 876, 3, 681},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 877, 2, 684},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 878, 2, 686},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 879, 2, 688},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 880, 2, 690},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 881, 17, 692},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 882, 2, 709},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 883, 1, 711},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 884, 9, 712},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 885, 6, 721},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 886, 6, 727},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 887, 2, 733},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 888, 2, 735},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 889, 3, 737},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 925, 2, 740},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 961, 6, 742},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 962, 2, 748},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 970, 2, 750},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 971, 3, 752},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 972, 5, 755},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 980, 3, 760},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 981, 2, 763},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 982, 2, 765},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 983, 4, 767},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 984, 3, 771},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 985, 5, 774},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 986, 5, 779},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 987, 5, 784},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 988, 5, 789},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 989, 8, 794},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 9, 802},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 991, 8, 811},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 5, 819},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 993, 4, 824},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 994, 2, 828},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 14, 830},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 996, 19, 844},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 997, 3, 863},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 3, 866},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 999, 2, 869},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 17, 871},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 5, 888},
- {"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1005, 5, 893},
- {"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 5, 898},
- {"cvmx_l2c_spar3" , CVMX_CSR_DB_TYPE_RSL, 64, 1007, 5, 903},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1008, 2, 908},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1009, 3, 910},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1010, 2, 913},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1011, 2, 915},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1012, 2, 917},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1013, 7, 919},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1014, 4, 926},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1015, 3, 930},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1016, 3, 933},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1017, 2, 936},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1018, 2, 938},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 2, 940},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1020, 4, 942},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1021, 13, 946},
- {"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1022, 2, 959},
- {"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 2, 961},
- {"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 2, 963},
- {"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 2, 965},
- {"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 2, 967},
- {"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 969},
- {"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 2, 971},
- {"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 2, 973},
- {"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 2, 975},
- {"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 2, 977},
- {"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 2, 979},
- {"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 2, 981},
- {"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 2, 983},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1046, 9, 985},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1047, 19, 994},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1048, 2, 1013},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1049, 2, 1015},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1050, 18, 1017},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 5, 1035},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1052, 6, 1040},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 2, 1046},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1054, 2, 1048},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 14, 1050},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1056, 9, 1064},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 2, 1073},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1058, 2, 1075},
- {"cvmx_lmc#_pll_bwctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 3, 1077},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1060, 9, 1080},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 9, 1089},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1062, 4, 1098},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1063, 3, 1102},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1064, 3, 1105},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1065, 3, 1108},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1066, 5, 1111},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1068, 1, 1116},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1069, 6, 1117},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1077, 13, 1123},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1085, 4, 1136},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1086, 2, 1140},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1087, 2, 1142},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1088, 8, 1144},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1089, 7, 1152},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1090, 2, 1159},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1091, 8, 1161},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1092, 2, 1169},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1093, 8, 1171},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1094, 12, 1179},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1095, 3, 1191},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1096, 3, 1194},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1097, 2, 1197},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1099, 2, 1199},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1101, 2, 1201},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 7, 1203},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 2, 1210},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 7, 1212},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 4, 1219},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1111, 8, 1223},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1113, 9, 1231},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1115, 7, 1240},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 9, 1247},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1119, 2, 1256},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1121, 2, 1258},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1123, 4, 1260},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1125, 2, 1264},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1127, 2, 1266},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1129, 2, 1268},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1131, 4, 1270},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1133, 2, 1274},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1135, 2, 1276},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1137, 2, 1278},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1139, 2, 1280},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1141, 2, 1282},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1143, 2, 1284},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 6, 1286},
- {"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1147, 2, 1292},
- {"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1151, 2, 1294},
- {"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1155, 21, 1296},
- {"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1156, 3, 1317},
- {"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1160, 21, 1320},
- {"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 1161, 2, 1341},
- {"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1162, 13, 1343},
- {"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1163, 3, 1356},
- {"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1164, 3, 1359},
- {"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1165, 3, 1362},
- {"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1166, 3, 1365},
- {"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1167, 2, 1368},
- {"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1168, 2, 1370},
- {"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1169, 9, 1372},
- {"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1170, 43, 1381},
- {"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1171, 43, 1424},
- {"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1172, 2, 1467},
- {"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1173, 2, 1469},
- {"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 1174, 8, 1471},
- {"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1178, 1, 1479},
- {"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1179, 2, 1480},
- {"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1183, 38, 1482},
- {"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1184, 3, 1520},
- {"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1188, 2, 1523},
- {"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1192, 3, 1525},
- {"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1196, 3, 1528},
- {"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1200, 3, 1531},
- {"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 1201, 4, 1534},
- {"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 1202, 2, 1538},
- {"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1203, 13, 1540},
- {"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1204, 13, 1553},
- {"cvmx_npi_port34_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1205, 13, 1566},
- {"cvmx_npi_port35_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1206, 13, 1579},
- {"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1207, 3, 1592},
- {"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 1208, 33, 1595},
- {"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1209, 2, 1628},
- {"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 1213, 2, 1630},
- {"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1214, 5, 1632},
- {"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1246, 2, 1637},
- {"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1247, 24, 1639},
- {"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1248, 2, 1663},
- {"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1249, 7, 1665},
- {"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1250, 5, 1672},
- {"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1251, 1, 1677},
- {"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1252, 5, 1678},
- {"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1253, 1, 1683},
- {"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1254, 4, 1684},
- {"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1255, 2, 1688},
- {"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1256, 1, 1690},
- {"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1257, 2, 1691},
- {"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1258, 4, 1693},
- {"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1259, 2, 1697},
- {"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1260, 4, 1699},
- {"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1261, 16, 1703},
- {"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1262, 1, 1719},
- {"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1263, 1, 1720},
- {"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1264, 18, 1721},
- {"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1265, 1, 1739},
- {"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1266, 1, 1740},
- {"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1267, 7, 1741},
- {"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1268, 7, 1748},
- {"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1269, 13, 1755},
- {"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1270, 10, 1768},
- {"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1271, 10, 1778},
- {"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1272, 7, 1788},
- {"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1273, 2, 1795},
- {"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1274, 1, 1797},
- {"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1275, 2, 1798},
- {"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1276, 16, 1800},
- {"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 1277, 2, 1816},
- {"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 1281, 1, 1818},
- {"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1283, 1, 1819},
- {"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1285, 1, 1820},
- {"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 1287, 1, 1821},
- {"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 1291, 35, 1822},
- {"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1292, 35, 1857},
- {"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 1293, 35, 1892},
- {"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1294, 35, 1927},
- {"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 1295, 2, 1962},
- {"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 1296, 2, 1964},
- {"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 1300, 1, 1966},
- {"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1304, 1, 1967},
- {"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1308, 1, 1968},
- {"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1312, 3, 1969},
- {"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1313, 3, 1972},
- {"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1314, 3, 1975},
- {"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 1315, 3, 1978},
- {"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1316, 2, 1981},
- {"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1317, 2, 1983},
- {"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1318, 4, 1985},
- {"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1319, 1, 1989},
- {"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1320, 4, 1990},
- {"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1321, 1, 1994},
- {"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 1322, 2, 1995},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1323, 5, 1997},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1324, 2, 2002},
- {"cvmx_pip_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 3, 2004},
- {"cvmx_pip_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 2, 2007},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 4, 2009},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1333, 8, 2013},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 16, 2021},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1335, 10, 2037},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1336, 10, 2047},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1337, 2, 2057},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1338, 18, 2059},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1374, 25, 2077},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1410, 2, 2102},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1474, 2, 2104},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1482, 9, 2106},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1486, 2, 2115},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1487, 2, 2117},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1523, 2, 2119},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1559, 2, 2121},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1595, 2, 2123},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1631, 2, 2125},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1667, 2, 2127},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1703, 2, 2129},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1739, 2, 2131},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1775, 2, 2133},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1811, 2, 2135},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1847, 2, 2137},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1848, 2, 2139},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1884, 2, 2141},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 1920, 2, 2143},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1956, 2, 2145},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2020, 2, 2147},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2021, 3, 2149},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2022, 3, 2152},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2023, 2, 2155},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2024, 2, 2157},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2025, 4, 2159},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2026, 5, 2163},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2027, 4, 2168},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2028, 5, 2172},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2029, 1, 2177},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2030, 4, 2178},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2031, 2, 2182},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2032, 5, 2184},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2033, 5, 2189},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2034, 1, 2194},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2035, 19, 2195},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2036, 7, 2214},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2037, 4, 2221},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2038, 6, 2225},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2039, 7, 2231},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2040, 9, 2238},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2041, 5, 2247},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2042, 13, 2252},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2043, 4, 2265},
- {"cvmx_pko_reg_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 2044, 3, 2269},
- {"cvmx_pko_reg_crc_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 2046, 2, 2272},
- {"cvmx_pko_reg_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 2047, 2, 2274},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2049, 2, 2276},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2050, 3, 2278},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2051, 5, 2281},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2052, 3, 2286},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2053, 3, 2289},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2054, 2, 2292},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2055, 3, 2294},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2056, 13, 2297},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2057, 2, 2310},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2058, 9, 2312},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2059, 3, 2321},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2060, 2, 2324},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2068, 2, 2326},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2069, 2, 2328},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2070, 2, 2330},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2071, 2, 2332},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2087, 5, 2334},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2095, 8, 2339},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2103, 2, 2347},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2104, 2, 2349},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2105, 2, 2351},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2113, 3, 2353},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2114, 4, 2356},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2130, 5, 2360},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2131, 7, 2365},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2147, 2, 2372},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2163, 3, 2374},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2164, 5, 2377},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2165, 8, 2382},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2166, 6, 2390},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2167, 2, 2396},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2168, 4, 2398},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2169, 4, 2402},
- {"cvmx_spx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2170, 2, 2406},
- {"cvmx_spx#_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2172, 4, 2408},
- {"cvmx_spx#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2174, 11, 2412},
- {"cvmx_spx#_clk_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 9, 2423},
- {"cvmx_spx#_dbg_deskew_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2178, 16, 2432},
- {"cvmx_spx#_dbg_deskew_state" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 5, 2448},
- {"cvmx_spx#_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 4, 2453},
- {"cvmx_spx#_err_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2184, 6, 2457},
- {"cvmx_spx#_int_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2186, 6, 2463},
- {"cvmx_spx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2188, 12, 2469},
- {"cvmx_spx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2190, 14, 2481},
- {"cvmx_spx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2192, 12, 2495},
- {"cvmx_spx#_tpa_acc" , CVMX_CSR_DB_TYPE_RSL, 64, 2194, 2, 2507},
- {"cvmx_spx#_tpa_max" , CVMX_CSR_DB_TYPE_RSL, 64, 2196, 2, 2509},
- {"cvmx_spx#_tpa_sel" , CVMX_CSR_DB_TYPE_RSL, 64, 2198, 2, 2511},
- {"cvmx_spx#_trn4_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2200, 8, 2513},
- {"cvmx_spx0_pll_bw_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2202, 2, 2521},
- {"cvmx_spx0_pll_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 2203, 2, 2523},
- {"cvmx_srx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2204, 5, 2525},
- {"cvmx_srx#_ign_rx_full" , CVMX_CSR_DB_TYPE_RSL, 64, 2206, 2, 2530},
- {"cvmx_srx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2208, 6, 2532},
- {"cvmx_srx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2272, 4, 2538},
- {"cvmx_stx#_arb_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2274, 5, 2542},
- {"cvmx_stx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2276, 2, 2547},
- {"cvmx_stx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2278, 4, 2549},
- {"cvmx_stx#_dip_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2280, 3, 2553},
- {"cvmx_stx#_ign_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 2282, 2, 2556},
- {"cvmx_stx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2284, 9, 2558},
- {"cvmx_stx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2286, 10, 2567},
- {"cvmx_stx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2288, 9, 2577},
- {"cvmx_stx#_min_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 2290, 2, 2586},
- {"cvmx_stx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2292, 6, 2588},
- {"cvmx_stx#_spi4_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2356, 3, 2594},
- {"cvmx_stx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2358, 4, 2597},
- {"cvmx_stx#_stat_bytes_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 2360, 2, 2601},
- {"cvmx_stx#_stat_bytes_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 2362, 2, 2603},
- {"cvmx_stx#_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2364, 3, 2605},
- {"cvmx_stx#_stat_pkt_xmt" , CVMX_CSR_DB_TYPE_RSL, 64, 2366, 2, 2608},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2368, 6, 2610},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2369, 3, 2616},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2370, 5, 2619},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2371, 4, 2624},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2372, 6, 2628},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2373, 4, 2634},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2374, 2, 2638},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2375, 4, 2640},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2376, 2, 2644},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2377, 3, 2646},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2378, 4, 2649},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2379, 12, 2653},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2380, 3, 2665},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2381, 2, 2668},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2382, 2, 2670},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2383, 17, 2672},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2384, 12, 2689},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2385, 6, 2701},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2386, 5, 2707},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2387, 1, 2712},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2388, 2, 2713},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2389, 2, 2715},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2390, 17, 2717},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2391, 12, 2734},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2392, 6, 2746},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2393, 2, 2752},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2394, 2, 2754},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2395, 17, 2756},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2396, 12, 2773},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2397, 6, 2785},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2398, 3, 2791},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2399, 5, 2794},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2400, 3, 2799},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2401, 6, 2802},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2402, 2, 2808},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2403, 2, 2810},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2404, 2, 2812},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"ASX0_INT_EN" , 0x11800b0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX1_INT_EN" , 0x11800b8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX0_INT_REG" , 0x11800b0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX1_INT_REG" , 0x11800b8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX0_PRT_LOOP" , 0x11800b0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX1_PRT_LOOP" , 0x11800b8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX0_RLD_BYPASS" , 0x11800b0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX1_RLD_BYPASS" , 0x11800b8000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX0_RLD_BYPASS_SETTING" , 0x11800b0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX1_RLD_BYPASS_SETTING" , 0x11800b8000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX0_RLD_COMP" , 0x11800b0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX1_RLD_COMP" , 0x11800b8000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX0_RLD_DATA_DRV" , 0x11800b0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX1_RLD_DATA_DRV" , 0x11800b8000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_RLD_FCRAM_MODE" , 0x11800b0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX1_RLD_FCRAM_MODE" , 0x11800b8000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX0_RLD_NCTL_STRONG" , 0x11800b0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX1_RLD_NCTL_STRONG" , 0x11800b8000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_RLD_NCTL_WEAK" , 0x11800b0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX1_RLD_NCTL_WEAK" , 0x11800b8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX0_RLD_PCTL_STRONG" , 0x11800b0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX1_RLD_PCTL_STRONG" , 0x11800b8000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX0_RLD_PCTL_WEAK" , 0x11800b0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"ASX1_RLD_PCTL_WEAK" , 0x11800b8000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"ASX0_RLD_SETTING" , 0x11800b0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX1_RLD_SETTING" , 0x11800b8000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX0_RX_CLK_SET000" , 0x11800b0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX0_RX_CLK_SET001" , 0x11800b0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX0_RX_CLK_SET002" , 0x11800b0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX0_RX_CLK_SET003" , 0x11800b0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX1_RX_CLK_SET000" , 0x11800b8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX1_RX_CLK_SET001" , 0x11800b8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX1_RX_CLK_SET002" , 0x11800b8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX1_RX_CLK_SET003" , 0x11800b8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX0_RX_PRT_EN" , 0x11800b0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX1_RX_PRT_EN" , 0x11800b8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX0_RX_WOL" , 0x11800b0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"ASX1_RX_WOL" , 0x11800b8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"ASX0_RX_WOL_MSK" , 0x11800b0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX1_RX_WOL_MSK" , 0x11800b8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX0_RX_WOL_POWOK" , 0x11800b0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"ASX1_RX_WOL_POWOK" , 0x11800b8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"ASX0_RX_WOL_SIG" , 0x11800b0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"ASX1_RX_WOL_SIG" , 0x11800b8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"ASX0_TX_CLK_SET000" , 0x11800b0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX0_TX_CLK_SET001" , 0x11800b0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX0_TX_CLK_SET002" , 0x11800b0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX0_TX_CLK_SET003" , 0x11800b0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX1_TX_CLK_SET000" , 0x11800b8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX1_TX_CLK_SET001" , 0x11800b8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX1_TX_CLK_SET002" , 0x11800b8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX1_TX_CLK_SET003" , 0x11800b8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX0_TX_COMP_BYP" , 0x11800b0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"ASX1_TX_COMP_BYP" , 0x11800b8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"ASX0_TX_HI_WATER000" , 0x11800b0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX0_TX_HI_WATER001" , 0x11800b0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX0_TX_HI_WATER002" , 0x11800b0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX0_TX_HI_WATER003" , 0x11800b0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX1_TX_HI_WATER000" , 0x11800b8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX1_TX_HI_WATER001" , 0x11800b8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX1_TX_HI_WATER002" , 0x11800b8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX1_TX_HI_WATER003" , 0x11800b8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX0_TX_PRT_EN" , 0x11800b0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"ASX1_TX_PRT_EN" , 0x11800b8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"ASX0_DBG_DATA_DRV" , 0x11800b0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"ASX0_DBG_DATA_ENABLE" , 0x11800b0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT10_EN0" , 0x10700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT11_EN0" , 0x10700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT12_EN0" , 0x10700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT13_EN0" , 0x10700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT14_EN0" , 0x10700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT15_EN0" , 0x10700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT24_EN0" , 0x1070000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT25_EN0" , 0x1070000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT26_EN0" , 0x10700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT27_EN0" , 0x10700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT28_EN0" , 0x10700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT29_EN0" , 0x10700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT30_EN0" , 0x10700000003e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT31_EN0" , 0x10700000003f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT10_EN1" , 0x10700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT11_EN1" , 0x10700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT12_EN1" , 0x10700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT13_EN1" , 0x10700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT14_EN1" , 0x10700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT15_EN1" , 0x10700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT24_EN1" , 0x1070000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT25_EN1" , 0x1070000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT26_EN1" , 0x10700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT27_EN1" , 0x10700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT28_EN1" , 0x10700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT29_EN1" , 0x10700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT30_EN1" , 0x10700000003e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT31_EN1" , 0x10700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT20_SUM0" , 0x10700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT21_SUM0" , 0x10700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT22_SUM0" , 0x10700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT23_SUM0" , 0x10700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT24_SUM0" , 0x10700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT25_SUM0" , 0x10700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT26_SUM0" , 0x10700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT27_SUM0" , 0x10700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT28_SUM0" , 0x10700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT29_SUM0" , 0x10700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT30_SUM0" , 0x10700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT31_SUM0" , 0x10700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR4" , 0x10700000006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR5" , 0x10700000006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR6" , 0x10700000006b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR7" , 0x10700000006b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR8" , 0x10700000006c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR9" , 0x10700000006c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR10" , 0x10700000006d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR11" , 0x10700000006d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR12" , 0x10700000006e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR13" , 0x10700000006e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR14" , 0x10700000006f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR15" , 0x10700000006f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET12" , 0x1070000000660ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET13" , 0x1070000000668ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET14" , 0x1070000000670ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET15" , 0x1070000000678ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE4" , 0x10700000005a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE5" , 0x10700000005a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE6" , 0x10700000005b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE7" , 0x10700000005b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE8" , 0x10700000005c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE9" , 0x10700000005c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE10" , 0x10700000005d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE11" , 0x10700000005d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE12" , 0x10700000005e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE13" , 0x10700000005e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE14" , 0x10700000005f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE15" , 0x10700000005f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG12" , 0x1070000000560ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG13" , 0x1070000000568ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG14" , 0x1070000000570ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG15" , 0x1070000000578ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"DBG_DATA" , 0x11f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
- {"DFA_BST0" , 0x11800300007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"DFA_BST1" , 0x11800300007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"DFA_CFG" , 0x1180030000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
- {"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"DFA_MEMCFG0" , 0x1180030000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"DFA_MEMCFG1" , 0x1180030000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"DFA_MEMCFG2" , 0x1180030000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"DFA_MEMFCR" , 0x1180030000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"DFA_MEMRLD" , 0x1180030000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"DFA_NCBCTL" , 0x1180030000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX1_INF_MODE" , 0x11800100007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX000_ADR_CAM4" , 0x11800100001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX001_ADR_CAM4" , 0x11800100009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX002_ADR_CAM4" , 0x11800100011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX003_ADR_CAM4" , 0x11800100019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX000_ADR_CAM5" , 0x11800100001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX001_ADR_CAM5" , 0x11800100009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX002_ADR_CAM5" , 0x11800100011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX003_ADR_CAM5" , 0x11800100019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX003_FRM_MAX" , 0x1180008001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX000_FRM_MAX" , 0x1180010000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX001_FRM_MAX" , 0x1180010000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX002_FRM_MAX" , 0x1180010001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX003_FRM_MAX" , 0x1180010001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX003_FRM_MIN" , 0x1180008001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX000_FRM_MIN" , 0x1180010000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX001_FRM_MIN" , 0x1180010000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX002_FRM_MIN" , 0x1180010001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX003_FRM_MIN" , 0x1180010001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX003_RX_INBND" , 0x1180008001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX000_RX_INBND" , 0x1180010000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX001_RX_INBND" , 0x1180010000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX002_RX_INBND" , 0x1180010001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX003_RX_INBND" , 0x1180010001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_PASS_EN" , 0x11800080005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX1_RX_PASS_EN" , 0x11800100005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX_PASS_MAP000" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP001" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP002" , 0x1180008000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP003" , 0x1180008000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP004" , 0x1180008000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP005" , 0x1180008000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP006" , 0x1180008000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP007" , 0x1180008000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP008" , 0x1180008000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP009" , 0x1180008000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP010" , 0x1180008000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP011" , 0x1180008000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP012" , 0x1180008000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP013" , 0x1180008000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP014" , 0x1180008000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP015" , 0x1180008000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP000" , 0x1180010000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP001" , 0x1180010000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP002" , 0x1180010000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP003" , 0x1180010000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP004" , 0x1180010000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP005" , 0x1180010000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP006" , 0x1180010000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP007" , 0x1180010000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP008" , 0x1180010000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP009" , 0x1180010000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP010" , 0x1180010000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP011" , 0x1180010000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP012" , 0x1180010000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP013" , 0x1180010000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP014" , 0x1180010000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP015" , 0x1180010000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_SMAC001" , 0x1180010000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_SMAC003" , 0x1180010001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_TX001_APPEND" , 0x1180010000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_TX003_APPEND" , 0x1180010001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX001_BURST" , 0x1180010000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX003_BURST" , 0x1180010001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX001_CLK" , 0x1180008000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX003_CLK" , 0x1180008001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX000_CLK" , 0x1180010000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX001_CLK" , 0x1180010000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX002_CLK" , 0x1180010001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX003_CLK" , 0x1180010001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX001_CTL" , 0x1180010000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX003_CTL" , 0x1180010001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX001_MIN_PKT" , 0x1180010000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX003_MIN_PKT" , 0x1180010001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX001_PAUSE_TOGO" , 0x1180010000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX003_PAUSE_TOGO" , 0x1180010001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX001_PAUSE_ZERO" , 0x1180010000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX003_PAUSE_ZERO" , 0x1180010001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX001_SLOT" , 0x1180010000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX003_SLOT" , 0x1180010001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX001_SOFT_PAUSE" , 0x1180010000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX003_SOFT_PAUSE" , 0x1180010001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX001_STAT0" , 0x1180010000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX003_STAT0" , 0x1180010001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX001_STAT1" , 0x1180010000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX003_STAT1" , 0x1180010001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX001_STAT2" , 0x1180010000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX003_STAT2" , 0x1180010001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX001_STAT3" , 0x1180010000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX003_STAT3" , 0x1180010001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX000_STAT4" , 0x11800100002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX001_STAT4" , 0x1180010000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX002_STAT4" , 0x11800100012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX003_STAT4" , 0x1180010001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX000_STAT5" , 0x11800100002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX001_STAT5" , 0x1180010000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX002_STAT5" , 0x11800100012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX003_STAT5" , 0x1180010001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX000_STAT6" , 0x11800100002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX001_STAT6" , 0x1180010000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX002_STAT6" , 0x11800100012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX003_STAT6" , 0x1180010001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX000_STAT7" , 0x11800100002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX001_STAT7" , 0x1180010000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX002_STAT7" , 0x11800100012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX003_STAT7" , 0x1180010001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX000_STAT8" , 0x11800100002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX001_STAT8" , 0x1180010000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX002_STAT8" , 0x11800100012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX003_STAT8" , 0x1180010001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX000_STAT9" , 0x11800100002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX001_STAT9" , 0x1180010000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX002_STAT9" , 0x11800100012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX003_STAT9" , 0x1180010001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX001_STATS_CTL" , 0x1180010000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX003_STATS_CTL" , 0x1180010001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX001_THRESH" , 0x1180010000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX003_THRESH" , 0x1180010001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX_BP" , 0x11800100004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_TX_CORRUPT" , 0x11800100004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_TX_LFSR" , 0x11800100004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_TX_OVR_BP" , 0x11800100004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX_SPI_CTL" , 0x11800080004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_TX_SPI_CTL" , 0x11800100004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX_SPI_MAX" , 0x11800080004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_TX_SPI_MAX" , 0x11800100004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX_SPI_THRESH" , 0x11800080004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_TX_SPI_THRESH" , 0x11800100004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 186},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT4_BP_PAGE_CNT" , 0x14f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT5_BP_PAGE_CNT" , 0x14f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT6_BP_PAGE_CNT" , 0x14f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT7_BP_PAGE_CNT" , 0x14f0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT8_BP_PAGE_CNT" , 0x14f0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT9_BP_PAGE_CNT" , 0x14f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT10_BP_PAGE_CNT" , 0x14f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT11_BP_PAGE_CNT" , 0x14f0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT12_BP_PAGE_CNT" , 0x14f0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT13_BP_PAGE_CNT" , 0x14f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT14_BP_PAGE_CNT" , 0x14f0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT15_BP_PAGE_CNT" , 0x14f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT16_BP_PAGE_CNT" , 0x14f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT17_BP_PAGE_CNT" , 0x14f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT18_BP_PAGE_CNT" , 0x14f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT19_BP_PAGE_CNT" , 0x14f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT20_BP_PAGE_CNT" , 0x14f00000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT21_BP_PAGE_CNT" , 0x14f00000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT22_BP_PAGE_CNT" , 0x14f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT23_BP_PAGE_CNT" , 0x14f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT24_BP_PAGE_CNT" , 0x14f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT25_BP_PAGE_CNT" , 0x14f00000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT26_BP_PAGE_CNT" , 0x14f00000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT27_BP_PAGE_CNT" , 0x14f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT28_BP_PAGE_CNT" , 0x14f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT29_BP_PAGE_CNT" , 0x14f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT30_BP_PAGE_CNT" , 0x14f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT31_BP_PAGE_CNT" , 0x14f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR4" , 0x14f00000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR5" , 0x14f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR6" , 0x14f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR7" , 0x14f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR8" , 0x14f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR9" , 0x14f0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR10" , 0x14f0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR11" , 0x14f0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR12" , 0x14f0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR13" , 0x14f0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR14" , 0x14f0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR15" , 0x14f0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14f0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14f0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14f0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14f0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR20" , 0x14f0000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR21" , 0x14f0000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR22" , 0x14f0000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR23" , 0x14f0000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR24" , 0x14f0000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR25" , 0x14f0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR26" , 0x14f0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR27" , 0x14f0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR28" , 0x14f0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR29" , 0x14f00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR30" , 0x14f00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR31" , 0x14f00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"L2C_SPAR3" , 0x1180080000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"LED_BLINK" , 0x1180000001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"LED_CLK_PHASE" , 0x1180000001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"LED_CYLON" , 0x1180000001af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"LED_DBG" , 0x1180000001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"LED_EN" , 0x1180000001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"LED_POLARITY" , 0x1180000001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"LED_PRT" , 0x1180000001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"LED_PRT_FMT" , 0x1180000001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"LED_PRT_STATUS0" , 0x1180000001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"LED_PRT_STATUS1" , 0x1180000001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"LED_PRT_STATUS2" , 0x1180000001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"LED_PRT_STATUS3" , 0x1180000001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"LED_PRT_STATUS4" , 0x1180000001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"LED_PRT_STATUS5" , 0x1180000001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"LED_PRT_STATUS6" , 0x1180000001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"LED_PRT_STATUS7" , 0x1180000001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"LED_UDD_CNT0" , 0x1180000001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"LED_UDD_CNT1" , 0x1180000001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"LED_UDD_DAT0" , 0x1180000001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"LED_UDD_DAT1" , 0x1180000001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"LED_UDD_DAT_CLR0" , 0x1180000001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"LED_UDD_DAT_CLR1" , 0x1180000001ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"LED_UDD_DAT_SET0" , 0x1180000001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"LED_UDD_DAT_SET1" , 0x1180000001ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"LMC0_PLL_BWCTL" , 0x1180088000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"NPI_BASE_ADDR_INPUT0" , 0x11f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
- {"NPI_BASE_ADDR_INPUT1" , 0x11f0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
- {"NPI_BASE_ADDR_INPUT2" , 0x11f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
- {"NPI_BASE_ADDR_INPUT3" , 0x11f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
- {"NPI_BASE_ADDR_OUTPUT0" , 0x11f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"NPI_BASE_ADDR_OUTPUT1" , 0x11f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"NPI_BASE_ADDR_OUTPUT2" , 0x11f00000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"NPI_BASE_ADDR_OUTPUT3" , 0x11f00000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"NPI_BIST_STATUS" , 0x11f00000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"NPI_BUFF_SIZE_OUTPUT0" , 0x11f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"NPI_BUFF_SIZE_OUTPUT1" , 0x11f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"NPI_BUFF_SIZE_OUTPUT2" , 0x11f00000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"NPI_BUFF_SIZE_OUTPUT3" , 0x11f00000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"NPI_CTL_STATUS" , 0x11f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"NPI_DBG_SELECT" , 0x11f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"NPI_DMA_CONTROL" , 0x11f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"NPI_DMA_HIGHP_COUNTS" , 0x11f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"NPI_DMA_HIGHP_NADDR" , 0x11f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"NPI_DMA_LOWP_COUNTS" , 0x11f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 325},
- {"NPI_DMA_LOWP_NADDR" , 0x11f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"NPI_HIGHP_DBELL" , 0x11f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"NPI_HIGHP_IBUFF_SADDR" , 0x11f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"NPI_INPUT_CONTROL" , 0x11f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"NPI_INT_ENB" , 0x11f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
- {"NPI_INT_SUM" , 0x11f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
- {"NPI_LOWP_DBELL" , 0x11f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"NPI_LOWP_IBUFF_SADDR" , 0x11f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"NPI_MEM_ACCESS_SUBID3" , 0x11f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"NPI_MEM_ACCESS_SUBID4" , 0x11f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"NPI_MEM_ACCESS_SUBID5" , 0x11f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"NPI_MEM_ACCESS_SUBID6" , 0x11f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"NPI_MSI_RCV" , 0x11f0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 335},
- {"NPI_NUM_DESC_OUTPUT0" , 0x11f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"NPI_NUM_DESC_OUTPUT1" , 0x11f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"NPI_NUM_DESC_OUTPUT2" , 0x11f0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"NPI_NUM_DESC_OUTPUT3" , 0x11f0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"NPI_OUTPUT_CONTROL" , 0x11f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"NPI_P0_DBPAIR_ADDR" , 0x11f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"NPI_P1_DBPAIR_ADDR" , 0x11f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"NPI_P2_DBPAIR_ADDR" , 0x11f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"NPI_P3_DBPAIR_ADDR" , 0x11f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"NPI_P0_INSTR_ADDR" , 0x11f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"NPI_P1_INSTR_ADDR" , 0x11f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"NPI_P2_INSTR_ADDR" , 0x11f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"NPI_P3_INSTR_ADDR" , 0x11f00000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"NPI_P0_INSTR_CNTS" , 0x11f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"NPI_P1_INSTR_CNTS" , 0x11f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"NPI_P2_INSTR_CNTS" , 0x11f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"NPI_P3_INSTR_CNTS" , 0x11f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"NPI_P0_PAIR_CNTS" , 0x11f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"NPI_P1_PAIR_CNTS" , 0x11f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"NPI_P2_PAIR_CNTS" , 0x11f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"NPI_P3_PAIR_CNTS" , 0x11f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"NPI_PCI_BURST_SIZE" , 0x11f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"NPI_PCI_INT_ARB_CFG" , 0x11f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"NPI_PCI_READ_CMD" , 0x11f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"NPI_PORT32_INSTR_HDR" , 0x11f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"NPI_PORT33_INSTR_HDR" , 0x11f0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"NPI_PORT34_INSTR_HDR" , 0x11f0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
- {"NPI_PORT35_INSTR_HDR" , 0x11f0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"NPI_PORT_BP_CONTROL" , 0x11f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"NPI_RSL_INT_BLOCKS" , 0x11f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"NPI_SIZE_INPUT0" , 0x11f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"NPI_SIZE_INPUT1" , 0x11f0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"NPI_SIZE_INPUT2" , 0x11f0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"NPI_SIZE_INPUT3" , 0x11f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"NPI_WIN_READ_TO" , 0x11f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
- {"PCI_BAR1_INDEX0" , 0x11f0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX1" , 0x11f0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX2" , 0x11f0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX3" , 0x11f000000110cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX4" , 0x11f0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX5" , 0x11f0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX6" , 0x11f0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX7" , 0x11f000000111cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX8" , 0x11f0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX9" , 0x11f0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX10" , 0x11f0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX11" , 0x11f000000112cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX12" , 0x11f0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX13" , 0x11f0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX14" , 0x11f0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX15" , 0x11f000000113cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX16" , 0x11f0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX17" , 0x11f0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX18" , 0x11f0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX19" , 0x11f000000114cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX20" , 0x11f0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX21" , 0x11f0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX22" , 0x11f0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX23" , 0x11f000000115cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX24" , 0x11f0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX25" , 0x11f0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX26" , 0x11f0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX27" , 0x11f000000116cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX28" , 0x11f0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX29" , 0x11f0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX30" , 0x11f0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_BAR1_INDEX31" , 0x11f000000117cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_CFG00" , 0x11f0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 354},
- {"PCI_CFG01" , 0x11f0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 355},
- {"PCI_CFG02" , 0x11f0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 356},
- {"PCI_CFG03" , 0x11f000000180cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 357},
- {"PCI_CFG04" , 0x11f0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 358},
- {"PCI_CFG05" , 0x11f0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 359},
- {"PCI_CFG06" , 0x11f0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 360},
- {"PCI_CFG07" , 0x11f000000181cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 361},
- {"PCI_CFG08" , 0x11f0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 362},
- {"PCI_CFG09" , 0x11f0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 363},
- {"PCI_CFG10" , 0x11f0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 364},
- {"PCI_CFG11" , 0x11f000000182cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 365},
- {"PCI_CFG12" , 0x11f0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 366},
- {"PCI_CFG13" , 0x11f0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 367},
- {"PCI_CFG15" , 0x11f000000183cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 368},
- {"PCI_CFG16" , 0x11f0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 369},
- {"PCI_CFG17" , 0x11f0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 370},
- {"PCI_CFG18" , 0x11f0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 371},
- {"PCI_CFG19" , 0x11f000000184cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 372},
- {"PCI_CFG20" , 0x11f0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 373},
- {"PCI_CFG21" , 0x11f0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 374},
- {"PCI_CFG22" , 0x11f0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 375},
- {"PCI_CFG56" , 0x11f00000018e0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 376},
- {"PCI_CFG57" , 0x11f00000018e4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 377},
- {"PCI_CFG58" , 0x11f00000018e8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 378},
- {"PCI_CFG59" , 0x11f00000018ecull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 379},
- {"PCI_CFG60" , 0x11f00000018f0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 380},
- {"PCI_CFG61" , 0x11f00000018f4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 381},
- {"PCI_CFG62" , 0x11f00000018f8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 382},
- {"PCI_CFG63" , 0x11f00000018fcull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 383},
- {"PCI_CTL_STATUS_2" , 0x11f000000118cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 384},
- {"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
- {"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
- {"PCI_DBELL2" , 0x90ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
- {"PCI_DBELL3" , 0x98ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
- {"PCI_DMA_CNT0" , 0xa0ull, CVMX_CSR_DB_TYPE_PCI, 32, 386},
- {"PCI_DMA_CNT1" , 0xa8ull, CVMX_CSR_DB_TYPE_PCI, 32, 386},
- {"PCI_DMA_INT_LEV0" , 0xa4ull, CVMX_CSR_DB_TYPE_PCI, 32, 387},
- {"PCI_DMA_INT_LEV1" , 0xacull, CVMX_CSR_DB_TYPE_PCI, 32, 387},
- {"PCI_DMA_TIME0" , 0xb0ull, CVMX_CSR_DB_TYPE_PCI, 32, 388},
- {"PCI_DMA_TIME1" , 0xb4ull, CVMX_CSR_DB_TYPE_PCI, 32, 388},
- {"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
- {"PCI_INSTR_COUNT1" , 0x8cull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
- {"PCI_INSTR_COUNT2" , 0x94ull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
- {"PCI_INSTR_COUNT3" , 0x9cull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
- {"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 390},
- {"PCI_INT_ENB2" , 0x11f00000011a0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 391},
- {"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 392},
- {"PCI_INT_SUM2" , 0x11f0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 393},
- {"PCI_MSI_RCV" , 0xf0ull, CVMX_CSR_DB_TYPE_PCI, 32, 394},
- {"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
- {"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
- {"PCI_PKT_CREDITS2" , 0x64ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
- {"PCI_PKT_CREDITS3" , 0x74ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
- {"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
- {"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
- {"PCI_PKTS_SENT2" , 0x60ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
- {"PCI_PKTS_SENT3" , 0x70ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
- {"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
- {"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
- {"PCI_PKTS_SENT_INT_LEV2" , 0x68ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
- {"PCI_PKTS_SENT_INT_LEV3" , 0x78ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
- {"PCI_PKTS_SENT_TIME0" , 0x4cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
- {"PCI_PKTS_SENT_TIME1" , 0x5cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
- {"PCI_PKTS_SENT_TIME2" , 0x6cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
- {"PCI_PKTS_SENT_TIME3" , 0x7cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
- {"PCI_READ_CMD_6" , 0x11f0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 399},
- {"PCI_READ_CMD_C" , 0x11f0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 400},
- {"PCI_READ_CMD_E" , 0x11f0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 401},
- {"PCI_READ_TIMEOUT" , 0x11f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"PCI_SCM_REG" , 0x11f00000011a8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 403},
- {"PCI_TSR_REG" , 0x11f00000011b0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 404},
- {"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 405},
- {"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 406},
- {"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 407},
- {"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 408},
- {"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 409},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"PIP_CRC_CTL0" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_CRC_CTL1" , 0x11800a0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_CRC_IV0" , 0x11800a0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_CRC_IV1" , 0x11800a0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG4" , 0x11800a0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG5" , 0x11800a0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG6" , 0x11800a0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG7" , 0x11800a0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG8" , 0x11800a0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG9" , 0x11800a0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG10" , 0x11800a0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG11" , 0x11800a0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG12" , 0x11800a0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG13" , 0x11800a0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG14" , 0x11800a0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG15" , 0x11800a0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG16" , 0x11800a0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG17" , 0x11800a0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG18" , 0x11800a0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG19" , 0x11800a0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG20" , 0x11800a00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG21" , 0x11800a00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG22" , 0x11800a00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG23" , 0x11800a00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG24" , 0x11800a00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG25" , 0x11800a00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG26" , 0x11800a00002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG27" , 0x11800a00002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG28" , 0x11800a00002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG29" , 0x11800a00002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG30" , 0x11800a00002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG31" , 0x11800a00002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG4" , 0x11800a0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG5" , 0x11800a0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG6" , 0x11800a0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG7" , 0x11800a0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG8" , 0x11800a0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG9" , 0x11800a0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG10" , 0x11800a0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG11" , 0x11800a0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG12" , 0x11800a0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG13" , 0x11800a0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG14" , 0x11800a0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG15" , 0x11800a0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG16" , 0x11800a0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG17" , 0x11800a0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG18" , 0x11800a0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG19" , 0x11800a0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG20" , 0x11800a00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG21" , 0x11800a00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG22" , 0x11800a00004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG23" , 0x11800a00004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG24" , 0x11800a00004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG25" , 0x11800a00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG26" , 0x11800a00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG27" , 0x11800a00004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG28" , 0x11800a00004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG29" , 0x11800a00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG30" , 0x11800a00004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG31" , 0x11800a00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT4" , 0x11800a0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT5" , 0x11800a0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT6" , 0x11800a00009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT7" , 0x11800a0000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT8" , 0x11800a0000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT9" , 0x11800a0000ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT10" , 0x11800a0000b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT11" , 0x11800a0000b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT12" , 0x11800a0000bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT13" , 0x11800a0000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT14" , 0x11800a0000c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT15" , 0x11800a0000cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT16" , 0x11800a0000d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT17" , 0x11800a0000d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT18" , 0x11800a0000da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT19" , 0x11800a0000df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT20" , 0x11800a0000e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT21" , 0x11800a0000e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT22" , 0x11800a0000ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT23" , 0x11800a0000f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT24" , 0x11800a0000f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT25" , 0x11800a0000fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT26" , 0x11800a0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT27" , 0x11800a0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT28" , 0x11800a00010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT29" , 0x11800a0001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT30" , 0x11800a0001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT31" , 0x11800a00011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT4" , 0x11800a0000948ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT5" , 0x11800a0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT6" , 0x11800a00009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT7" , 0x11800a0000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT8" , 0x11800a0000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT9" , 0x11800a0000ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT10" , 0x11800a0000b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT11" , 0x11800a0000b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT12" , 0x11800a0000bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT13" , 0x11800a0000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT14" , 0x11800a0000c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT15" , 0x11800a0000cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT16" , 0x11800a0000d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT17" , 0x11800a0000d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT18" , 0x11800a0000da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT19" , 0x11800a0000df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT20" , 0x11800a0000e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT21" , 0x11800a0000e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT22" , 0x11800a0000ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT23" , 0x11800a0000f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT24" , 0x11800a0000f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT25" , 0x11800a0000fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT26" , 0x11800a0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT27" , 0x11800a0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT28" , 0x11800a00010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT29" , 0x11800a0001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT30" , 0x11800a0001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT31" , 0x11800a00011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT4" , 0x11800a0000950ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT5" , 0x11800a00009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT6" , 0x11800a00009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT7" , 0x11800a0000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT8" , 0x11800a0000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT9" , 0x11800a0000ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT10" , 0x11800a0000b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT11" , 0x11800a0000b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT12" , 0x11800a0000bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT13" , 0x11800a0000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT14" , 0x11800a0000c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT15" , 0x11800a0000cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT16" , 0x11800a0000d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT17" , 0x11800a0000d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT18" , 0x11800a0000db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT19" , 0x11800a0000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT20" , 0x11800a0000e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT21" , 0x11800a0000ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT22" , 0x11800a0000ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT23" , 0x11800a0000f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT24" , 0x11800a0000f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT25" , 0x11800a0000fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT26" , 0x11800a0001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT27" , 0x11800a0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT28" , 0x11800a00010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT29" , 0x11800a0001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT30" , 0x11800a0001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT31" , 0x11800a00011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT4" , 0x11800a0000958ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT5" , 0x11800a00009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT6" , 0x11800a00009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT7" , 0x11800a0000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT8" , 0x11800a0000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT9" , 0x11800a0000ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT10" , 0x11800a0000b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT11" , 0x11800a0000b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT12" , 0x11800a0000bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT13" , 0x11800a0000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT14" , 0x11800a0000c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT15" , 0x11800a0000cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT16" , 0x11800a0000d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT17" , 0x11800a0000d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT18" , 0x11800a0000db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT19" , 0x11800a0000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT20" , 0x11800a0000e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT21" , 0x11800a0000ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT22" , 0x11800a0000ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT23" , 0x11800a0000f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT24" , 0x11800a0000f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT25" , 0x11800a0000fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT26" , 0x11800a0001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT27" , 0x11800a0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT28" , 0x11800a00010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT29" , 0x11800a0001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT30" , 0x11800a0001178ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT31" , 0x11800a00011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT4" , 0x11800a0000960ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT5" , 0x11800a00009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT6" , 0x11800a0000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT7" , 0x11800a0000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT8" , 0x11800a0000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT9" , 0x11800a0000af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT10" , 0x11800a0000b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT11" , 0x11800a0000b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT12" , 0x11800a0000be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT13" , 0x11800a0000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT14" , 0x11800a0000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT15" , 0x11800a0000cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT16" , 0x11800a0000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT17" , 0x11800a0000d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT18" , 0x11800a0000dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT19" , 0x11800a0000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT20" , 0x11800a0000e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT21" , 0x11800a0000eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT22" , 0x11800a0000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT23" , 0x11800a0000f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT24" , 0x11800a0000fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT25" , 0x11800a0000ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT26" , 0x11800a0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT27" , 0x11800a0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT28" , 0x11800a00010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT29" , 0x11800a0001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT30" , 0x11800a0001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT31" , 0x11800a00011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT4" , 0x11800a0000968ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT5" , 0x11800a00009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT6" , 0x11800a0000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT7" , 0x11800a0000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT8" , 0x11800a0000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT9" , 0x11800a0000af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT10" , 0x11800a0000b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT11" , 0x11800a0000b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT12" , 0x11800a0000be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT13" , 0x11800a0000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT14" , 0x11800a0000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT15" , 0x11800a0000cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT16" , 0x11800a0000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT17" , 0x11800a0000d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT18" , 0x11800a0000dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT19" , 0x11800a0000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT20" , 0x11800a0000e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT21" , 0x11800a0000eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT22" , 0x11800a0000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT23" , 0x11800a0000f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT24" , 0x11800a0000fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT25" , 0x11800a0000ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT26" , 0x11800a0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT27" , 0x11800a0001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT28" , 0x11800a00010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT29" , 0x11800a0001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT30" , 0x11800a0001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT31" , 0x11800a00011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT4" , 0x11800a0000970ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT5" , 0x11800a00009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT6" , 0x11800a0000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT7" , 0x11800a0000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT8" , 0x11800a0000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT9" , 0x11800a0000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT10" , 0x11800a0000b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT11" , 0x11800a0000ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT12" , 0x11800a0000bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT13" , 0x11800a0000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT14" , 0x11800a0000c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT15" , 0x11800a0000ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT16" , 0x11800a0000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT17" , 0x11800a0000d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT18" , 0x11800a0000dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT19" , 0x11800a0000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT20" , 0x11800a0000e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT21" , 0x11800a0000ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT22" , 0x11800a0000f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT23" , 0x11800a0000f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT24" , 0x11800a0000fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT25" , 0x11800a0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT26" , 0x11800a0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT27" , 0x11800a00010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT28" , 0x11800a00010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT29" , 0x11800a0001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT30" , 0x11800a0001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT31" , 0x11800a00011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT4" , 0x11800a0000978ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT5" , 0x11800a00009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT6" , 0x11800a0000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT7" , 0x11800a0000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT8" , 0x11800a0000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT9" , 0x11800a0000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT10" , 0x11800a0000b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT11" , 0x11800a0000ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT12" , 0x11800a0000bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT13" , 0x11800a0000c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT14" , 0x11800a0000c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT15" , 0x11800a0000ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT16" , 0x11800a0000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT17" , 0x11800a0000d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT18" , 0x11800a0000dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT19" , 0x11800a0000e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT20" , 0x11800a0000e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT21" , 0x11800a0000ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT22" , 0x11800a0000f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT23" , 0x11800a0000f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT24" , 0x11800a0000fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT25" , 0x11800a0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT26" , 0x11800a0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT27" , 0x11800a00010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT28" , 0x11800a00010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT29" , 0x11800a0001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT30" , 0x11800a0001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT31" , 0x11800a00011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT4" , 0x11800a0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT5" , 0x11800a00009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT6" , 0x11800a0000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT7" , 0x11800a0000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT8" , 0x11800a0000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT9" , 0x11800a0000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT10" , 0x11800a0000b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT11" , 0x11800a0000bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT12" , 0x11800a0000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT13" , 0x11800a0000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT14" , 0x11800a0000ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT15" , 0x11800a0000cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT16" , 0x11800a0000d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT17" , 0x11800a0000d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT18" , 0x11800a0000de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT19" , 0x11800a0000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT20" , 0x11800a0000e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT21" , 0x11800a0000ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT22" , 0x11800a0000f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT23" , 0x11800a0000f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT24" , 0x11800a0000fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT25" , 0x11800a0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT26" , 0x11800a0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT27" , 0x11800a00010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT28" , 0x11800a0001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT29" , 0x11800a0001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT30" , 0x11800a00011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT31" , 0x11800a00011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT4" , 0x11800a0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT5" , 0x11800a00009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT6" , 0x11800a0000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT7" , 0x11800a0000a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT8" , 0x11800a0000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT9" , 0x11800a0000b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT10" , 0x11800a0000b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT11" , 0x11800a0000bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT12" , 0x11800a0000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT13" , 0x11800a0000c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT14" , 0x11800a0000ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT15" , 0x11800a0000cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT16" , 0x11800a0000d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT17" , 0x11800a0000d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT18" , 0x11800a0000de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT19" , 0x11800a0000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT20" , 0x11800a0000e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT21" , 0x11800a0000ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT22" , 0x11800a0000f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT23" , 0x11800a0000f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT24" , 0x11800a0000fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT25" , 0x11800a0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT26" , 0x11800a0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT27" , 0x11800a00010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT28" , 0x11800a0001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT29" , 0x11800a0001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT30" , 0x11800a00011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT31" , 0x11800a00011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS4" , 0x11800a0001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS5" , 0x11800a0001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS6" , 0x11800a0001ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS7" , 0x11800a0001af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS8" , 0x11800a0001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS9" , 0x11800a0001b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS10" , 0x11800a0001b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS11" , 0x11800a0001b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS12" , 0x11800a0001b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS13" , 0x11800a0001bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS14" , 0x11800a0001bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS15" , 0x11800a0001bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS16" , 0x11800a0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS17" , 0x11800a0001c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS18" , 0x11800a0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS19" , 0x11800a0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS20" , 0x11800a0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS21" , 0x11800a0001cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS22" , 0x11800a0001cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS23" , 0x11800a0001cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS24" , 0x11800a0001d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS25" , 0x11800a0001d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS26" , 0x11800a0001d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS27" , 0x11800a0001d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS28" , 0x11800a0001d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS29" , 0x11800a0001db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS30" , 0x11800a0001dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS31" , 0x11800a0001df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS4" , 0x11800a0001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS5" , 0x11800a0001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS6" , 0x11800a0001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS7" , 0x11800a0001ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS8" , 0x11800a0001b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS9" , 0x11800a0001b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS10" , 0x11800a0001b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS11" , 0x11800a0001b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS12" , 0x11800a0001b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS13" , 0x11800a0001ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS14" , 0x11800a0001bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS15" , 0x11800a0001be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS16" , 0x11800a0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS17" , 0x11800a0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS18" , 0x11800a0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS19" , 0x11800a0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS20" , 0x11800a0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS21" , 0x11800a0001ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS22" , 0x11800a0001cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS23" , 0x11800a0001ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS24" , 0x11800a0001d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS25" , 0x11800a0001d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS26" , 0x11800a0001d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS27" , 0x11800a0001d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS28" , 0x11800a0001d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS29" , 0x11800a0001da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS30" , 0x11800a0001dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS31" , 0x11800a0001de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS4" , 0x11800a0001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS5" , 0x11800a0001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS6" , 0x11800a0001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS7" , 0x11800a0001ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS8" , 0x11800a0001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS9" , 0x11800a0001b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS10" , 0x11800a0001b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS11" , 0x11800a0001b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS12" , 0x11800a0001b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS13" , 0x11800a0001ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS14" , 0x11800a0001bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS15" , 0x11800a0001be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS16" , 0x11800a0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS17" , 0x11800a0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS18" , 0x11800a0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS19" , 0x11800a0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS20" , 0x11800a0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS21" , 0x11800a0001ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS22" , 0x11800a0001cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS23" , 0x11800a0001ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS24" , 0x11800a0001d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS25" , 0x11800a0001d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS26" , 0x11800a0001d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS27" , 0x11800a0001d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS28" , 0x11800a0001d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS29" , 0x11800a0001da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS30" , 0x11800a0001dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS31" , 0x11800a0001de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PKO_REG_CRC_CTL0" , 0x1180050000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PKO_REG_CRC_CTL1" , 0x1180050000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PKO_REG_CRC_ENABLE" , 0x1180050000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PKO_REG_CRC_IV0" , 0x1180050000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PKO_REG_CRC_IV1" , 0x1180050000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 476},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 477},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 478},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 482},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK12" , 0x1670000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK13" , 0x1670000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK14" , 0x1670000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_PP_GRP_MSK15" , 0x1670000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 491},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"SPX0_BCKPRS_CNT" , 0x1180090000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"SPX1_BCKPRS_CNT" , 0x1180098000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"SPX0_BIST_STAT" , 0x11800900007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"SPX1_BIST_STAT" , 0x11800980007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"SPX0_CLK_CTL" , 0x1180090000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"SPX1_CLK_CTL" , 0x1180098000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"SPX0_CLK_STAT" , 0x1180090000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"SPX1_CLK_STAT" , 0x1180098000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"SPX0_DBG_DESKEW_CTL" , 0x1180090000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"SPX1_DBG_DESKEW_CTL" , 0x1180098000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"SPX0_DBG_DESKEW_STATE" , 0x1180090000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"SPX1_DBG_DESKEW_STATE" , 0x1180098000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"SPX0_DRV_CTL" , 0x1180090000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"SPX1_DRV_CTL" , 0x1180098000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"SPX0_ERR_CTL" , 0x1180090000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"SPX1_ERR_CTL" , 0x1180098000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"SPX0_INT_DAT" , 0x1180090000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"SPX1_INT_DAT" , 0x1180098000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"SPX0_INT_MSK" , 0x1180090000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"SPX1_INT_MSK" , 0x1180098000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"SPX0_INT_REG" , 0x1180090000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"SPX1_INT_REG" , 0x1180098000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"SPX0_INT_SYNC" , 0x1180090000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"SPX1_INT_SYNC" , 0x1180098000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"SPX0_TPA_ACC" , 0x1180090000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"SPX1_TPA_ACC" , 0x1180098000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"SPX0_TPA_MAX" , 0x1180090000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"SPX1_TPA_MAX" , 0x1180098000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"SPX0_TPA_SEL" , 0x1180090000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"SPX1_TPA_SEL" , 0x1180098000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"SPX0_TRN4_CTL" , 0x1180090000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"SPX1_TRN4_CTL" , 0x1180098000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"SPX0_PLL_BW_CTL" , 0x1180090000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"SPX0_PLL_SETTING" , 0x1180090000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"SRX0_COM_CTL" , 0x1180090000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"SRX1_COM_CTL" , 0x1180098000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"SRX0_IGN_RX_FULL" , 0x1180090000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"SRX1_IGN_RX_FULL" , 0x1180098000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"SRX0_SPI4_CAL000" , 0x1180090000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL001" , 0x1180090000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL002" , 0x1180090000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL003" , 0x1180090000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL004" , 0x1180090000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL005" , 0x1180090000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL006" , 0x1180090000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL007" , 0x1180090000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL008" , 0x1180090000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL009" , 0x1180090000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL010" , 0x1180090000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL011" , 0x1180090000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL012" , 0x1180090000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL013" , 0x1180090000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL014" , 0x1180090000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL015" , 0x1180090000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL016" , 0x1180090000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL017" , 0x1180090000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL018" , 0x1180090000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL019" , 0x1180090000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL020" , 0x11800900000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL021" , 0x11800900000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL022" , 0x11800900000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL023" , 0x11800900000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL024" , 0x11800900000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL025" , 0x11800900000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL026" , 0x11800900000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL027" , 0x11800900000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL028" , 0x11800900000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL029" , 0x11800900000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL030" , 0x11800900000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_CAL031" , 0x11800900000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL000" , 0x1180098000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL001" , 0x1180098000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL002" , 0x1180098000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL003" , 0x1180098000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL004" , 0x1180098000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL005" , 0x1180098000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL006" , 0x1180098000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL007" , 0x1180098000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL008" , 0x1180098000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL009" , 0x1180098000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL010" , 0x1180098000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL011" , 0x1180098000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL012" , 0x1180098000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL013" , 0x1180098000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL014" , 0x1180098000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL015" , 0x1180098000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL016" , 0x1180098000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL017" , 0x1180098000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL018" , 0x1180098000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL019" , 0x1180098000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL020" , 0x11800980000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL021" , 0x11800980000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL022" , 0x11800980000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL023" , 0x11800980000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL024" , 0x11800980000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL025" , 0x11800980000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL026" , 0x11800980000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL027" , 0x11800980000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL028" , 0x11800980000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL029" , 0x11800980000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL030" , 0x11800980000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX1_SPI4_CAL031" , 0x11800980000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SRX0_SPI4_STAT" , 0x1180090000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"SRX1_SPI4_STAT" , 0x1180098000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"STX0_ARB_CTL" , 0x1180090000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"STX1_ARB_CTL" , 0x1180098000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"STX0_BCKPRS_CNT" , 0x1180090000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"STX1_BCKPRS_CNT" , 0x1180098000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"STX0_COM_CTL" , 0x1180090000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"STX1_COM_CTL" , 0x1180098000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"STX0_DIP_CNT" , 0x1180090000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"STX1_DIP_CNT" , 0x1180098000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"STX0_IGN_CAL" , 0x1180090000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"STX1_IGN_CAL" , 0x1180098000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"STX0_INT_MSK" , 0x11800900006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"STX1_INT_MSK" , 0x11800980006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"STX0_INT_REG" , 0x1180090000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"STX1_INT_REG" , 0x1180098000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"STX0_INT_SYNC" , 0x11800900006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"STX1_INT_SYNC" , 0x11800980006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"STX0_MIN_BST" , 0x1180090000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"STX1_MIN_BST" , 0x1180098000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"STX0_SPI4_CAL000" , 0x1180090000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL001" , 0x1180090000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL002" , 0x1180090000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL003" , 0x1180090000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL004" , 0x1180090000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL005" , 0x1180090000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL006" , 0x1180090000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL007" , 0x1180090000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL008" , 0x1180090000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL009" , 0x1180090000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL010" , 0x1180090000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL011" , 0x1180090000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL012" , 0x1180090000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL013" , 0x1180090000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL014" , 0x1180090000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL015" , 0x1180090000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL016" , 0x1180090000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL017" , 0x1180090000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL018" , 0x1180090000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL019" , 0x1180090000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL020" , 0x11800900004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL021" , 0x11800900004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL022" , 0x11800900004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL023" , 0x11800900004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL024" , 0x11800900004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL025" , 0x11800900004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL026" , 0x11800900004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL027" , 0x11800900004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL028" , 0x11800900004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL029" , 0x11800900004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL030" , 0x11800900004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_CAL031" , 0x11800900004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL000" , 0x1180098000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL001" , 0x1180098000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL002" , 0x1180098000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL003" , 0x1180098000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL004" , 0x1180098000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL005" , 0x1180098000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL006" , 0x1180098000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL007" , 0x1180098000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL008" , 0x1180098000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL009" , 0x1180098000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL010" , 0x1180098000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL011" , 0x1180098000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL012" , 0x1180098000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL013" , 0x1180098000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL014" , 0x1180098000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL015" , 0x1180098000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL016" , 0x1180098000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL017" , 0x1180098000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL018" , 0x1180098000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL019" , 0x1180098000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL020" , 0x11800980004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL021" , 0x11800980004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL022" , 0x11800980004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL023" , 0x11800980004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL024" , 0x11800980004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL025" , 0x11800980004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL026" , 0x11800980004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL027" , 0x11800980004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL028" , 0x11800980004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL029" , 0x11800980004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL030" , 0x11800980004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX1_SPI4_CAL031" , 0x11800980004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"STX0_SPI4_DAT" , 0x1180090000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"STX1_SPI4_DAT" , 0x1180098000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"STX0_SPI4_STAT" , 0x1180090000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"STX1_SPI4_STAT" , 0x1180098000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"STX0_STAT_BYTES_HI" , 0x1180090000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"STX1_STAT_BYTES_HI" , 0x1180098000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"STX0_STAT_BYTES_LO" , 0x1180090000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"STX1_STAT_BYTES_LO" , 0x1180098000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"STX0_STAT_CTL" , 0x1180090000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"STX1_STAT_CTL" , 0x1180098000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"STX0_STAT_PKT_XMT" , 0x1180090000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"STX1_STAT_PKT_XMT" , 0x1180098000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"OVRFLW" , 0, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"TXPOP" , 4, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"TXPSH" , 8, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_12_63" , 12, 52, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 0, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 4, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 8, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 1, "RAZ", 1, 1, 0, 0},
- {"INT_LOOP" , 0, 4, 2, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_LOOP" , 4, 4, 2, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 2, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 1, 3, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 3, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 4, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 5, "RO", 0, 1, 0ull, 0},
- {"PCTL" , 4, 4, 5, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 5, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 6, "R/W", 0, 1, 0ull, 0},
- {"PCTL" , 4, 4, 6, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 6, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 1, 7, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 7, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 8, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 9, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 10, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 10, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 11, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 12, "RO", 1, 1, 0, 0},
- {"RESERVED_5_63" , 5, 59, 12, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 4, 14, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 14, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 15, "RO", 1, 1, 0, 0},
- {"STATUS" , 1, 1, 15, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 15, "RAZ", 1, 1, 0, 0},
- {"MSK" , 0, 64, 16, "R/W", 0, 1, 0ull, 0},
- {"POWEROK" , 0, 1, 17, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_1_63" , 1, 63, 17, "RAZ", 1, 1, 0, 0},
- {"SIG" , 0, 32, 18, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 18, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 19, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 19, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 20, "R/W", 0, 0, 8ull, 8ull},
- {"PCTL" , 4, 4, 20, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_8_63" , 8, 56, 20, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 4, 21, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 4, 22, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 22, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 23, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 4, 4, 23, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_8_63" , 8, 56, 23, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 24, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_1_63" , 1, 63, 24, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 4, 25, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 25, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 16, 26, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 26, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 16, 27, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 27, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 28, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 28, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 29, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 29, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 29, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 29, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 29, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 29, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 29, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 29, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 29, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 29, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 30, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 30, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 31, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 31, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 31, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 31, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 31, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 31, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 31, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 32, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 32, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 33, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 33, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 34, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 34, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 16, 35, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 35, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 36, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 36, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 16, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 37, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 38, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 39, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 15, 39, "R/W", 0, 0, 32767ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 39, "RAZ", 1, 1, 0, 0},
- {"SOFT_BIST" , 0, 1, 40, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 40, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 41, "R/W", 0, 0, 1ull, 0ull},
- {"NPI" , 1, 1, 41, "R/W", 0, 0, 0ull, 0ull},
- {"HOST64" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 41, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 42, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 42, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 43, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 43, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 43, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 44, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 44, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 44, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 44, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 44, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 45, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 45, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 45, "RO", 1, 1, 0, 0},
- {"CCLK_DIV2" , 23, 1, 45, "RO", 1, 1, 0, 0},
- {"DCLK_MUL2" , 24, 1, 45, "RO", 1, 1, 0, 0},
- {"D_MUL" , 25, 4, 45, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 45, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 16, 46, "RO", 0, 0, 0ull, 0ull},
- {"RDF" , 16, 16, 46, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 46, "RAZ", 0, 0, 0ull, 0ull},
- {"P1_BRF" , 0, 8, 47, "RO", 0, 0, 0ull, 0ull},
- {"P0_BRF" , 8, 8, 47, "RO", 0, 0, 0ull, 0ull},
- {"P1_BWB" , 16, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"P0_BWB" , 17, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"CRF" , 18, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"DRF" , 19, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"GFU" , 20, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"IFU" , 21, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 22, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 47, "RAZ", 0, 0, 0ull, 0ull},
- {"SARB" , 0, 1, 48, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 48, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 20, 49, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 49, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 9, 50, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 50, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 50, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_20_63" , 20, 44, 50, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 51, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 31, 51, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 51, "RAZ", 1, 1, 0, 0},
- {"CP2ECCENA" , 0, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"CP2SBE" , 1, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2DBE" , 2, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2SBINA" , 3, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"CP2DBINA" , 4, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"CP2SYN" , 5, 8, 52, "RO", 0, 0, 0ull, 0ull},
- {"DTEECCENA" , 13, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"DTESBE" , 14, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTEDBE" , 15, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTESBINA" , 16, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"DTEDBINA" , 17, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"DTESYN" , 18, 7, 52, "RO", 0, 0, 0ull, 0ull},
- {"DTEPARENA" , 25, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"DTEPERR" , 26, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTEPINA" , 27, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"CP2PARENA" , 28, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"CP2PERR" , 29, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2PINA" , 30, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"DBLOVF" , 31, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBLINA" , 32, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 52, "RAZ", 1, 1, 0, 0},
- {"ENA_P1" , 0, 1, 53, "R/W", 0, 0, 1ull, 1ull},
- {"ENA_P0" , 1, 1, 53, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 53, "RAZ", 1, 1, 0, 0},
- {"MTYPE" , 3, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_LAT" , 4, 2, 53, "R/W", 0, 0, 0ull, 0ull},
- {"RW_DLY" , 6, 4, 53, "R/W", 0, 0, 1ull, 1ull},
- {"WR_DLY" , 10, 4, 53, "R/W", 0, 0, 2ull, 2ull},
- {"FPRCH" , 14, 2, 53, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 16, 2, 53, "R/W", 0, 0, 0ull, 0ull},
- {"BLEN" , 18, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"PBUNK" , 19, 3, 53, "R/W", 0, 0, 2ull, 2ull},
- {"R2R_PBUNK" , 22, 1, 53, "R/W", 0, 0, 1ull, 1ull},
- {"INIT_P1" , 23, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"INIT_P0" , 24, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"BUNK_INIT" , 25, 2, 53, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_27_63" , 27, 37, 53, "RAZ", 1, 1, 0, 0},
- {"REF_INT" , 0, 4, 54, "R/W", 0, 0, 3ull, 3ull},
- {"TSKW" , 4, 2, 54, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 54, "RAZ", 0, 0, 0ull, 0ull},
- {"TRL" , 8, 4, 54, "R/W", 0, 0, 6ull, 6ull},
- {"TWL" , 12, 4, 54, "R/W", 0, 0, 7ull, 7ull},
- {"TRC" , 16, 4, 54, "R/W", 0, 0, 6ull, 6ull},
- {"TMRSC" , 20, 3, 54, "R/W", 0, 0, 6ull, 6ull},
- {"MRS_ENA" , 23, 1, 54, "R/W", 0, 0, 0ull, 0ull},
- {"AREF_ENA" , 24, 1, 54, "R/W", 0, 0, 0ull, 0ull},
- {"REF_INTLO" , 25, 9, 54, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 54, "RAZ", 1, 1, 0, 0},
- {"FCRAM2P" , 0, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"MAXBNK" , 1, 1, 55, "R/W", 0, 0, 1ull, 1ull},
- {"UA_START" , 2, 2, 55, "R/W", 0, 0, 1ull, 1ull},
- {"REFSHORT" , 4, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"TRFC" , 5, 5, 55, "R/W", 0, 0, 9ull, 9ull},
- {"SILRST" , 10, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"DTECLKDIS" , 11, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 55, "RAZ", 1, 1, 0, 0},
- {"MADDR" , 0, 24, 56, "RO", 0, 0, 0ull, 0ull},
- {"BNUM" , 24, 3, 56, "RO", 0, 0, 0ull, 0ull},
- {"PNUM" , 27, 1, 56, "RO", 0, 0, 0ull, 0ull},
- {"FSRC" , 28, 2, 56, "RO", 0, 0, 0ull, 0ull},
- {"FDST" , 30, 9, 56, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 56, "RAZ", 1, 1, 0, 0},
- {"MRS" , 0, 15, 57, "R/W", 0, 0, 66ull, 66ull},
- {"RESERVED_15_15" , 15, 1, 57, "RAZ", 1, 1, 0, 0},
- {"EMRS" , 16, 15, 57, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_31_31" , 31, 1, 57, "RAZ", 1, 1, 0, 0},
- {"EMRS2" , 32, 15, 57, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 57, "RAZ", 1, 1, 0, 0},
- {"MRSDAT" , 0, 23, 58, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_23_63" , 23, 41, 58, "RAZ", 1, 1, 0, 0},
- {"IMODE" , 0, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 1, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 2, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"DTMODE" , 3, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"DCMODE" , 4, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"SBDLCK" , 5, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"SBDNUM" , 6, 4, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 59, "RAZ", 1, 1, 0, 0},
- {"SBD0" , 0, 64, 60, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 61, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 62, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 63, "RO", 1, 1, 0, 0},
- {"FDR" , 0, 1, 64, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 64, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 64, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 64, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 64, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 64, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 65, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 65, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 65, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 65, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 65, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 65, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 65, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 66, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 66, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 66, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 67, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 67, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 68, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 68, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 68, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 69, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 69, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 70, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 71, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 72, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 72, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 73, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 73, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 74, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 74, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 74, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 75, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 75, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 75, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 76, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 76, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 77, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 77, "RAZ", 1, 1, 0, 0},
- {"OUT_COL" , 0, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB_OVR" , 1, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 16, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_21" , 18, 4, 78, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 78, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 10, 79, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 79, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 80, "RO", 1, 1, 0, 0},
- {"EN" , 1, 1, 80, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 80, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 81, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 81, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 82, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 82, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 82, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 82, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_63" , 4, 60, 82, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 83, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 84, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 85, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 86, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 87, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 88, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 89, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 89, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 90, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 90, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 90, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 90, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 91, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 91, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 92, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_FREE" , 6, 1, 93, "R/W", 0, 0, 0ull, 0ull},
- {"VLAN_LEN" , 7, 1, 93, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 93, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 94, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 94, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 95, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 95, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 96, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 96, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 97, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 98, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 99, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 99, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 100, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 100, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 100, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 100, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 101, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 102, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 102, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 103, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 103, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 104, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 104, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 105, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 105, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 106, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 106, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 107, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 108, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 108, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 109, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 109, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 110, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 110, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 111, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 111, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 112, "R/W", 1, 1, 0, 0},
- {"RESERVED_6_63" , 6, 58, 112, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 113, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 113, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 114, "R/W", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 114, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 16, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 115, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 4, 116, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 116, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 117, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 117, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 118, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 118, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 119, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 119, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 120, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 120, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 120, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 120, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 120, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 121, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 121, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 122, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 122, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 123, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 123, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 123, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 124, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 124, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 125, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 125, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 126, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 126, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 127, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 127, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 128, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 128, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 129, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 129, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 130, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 130, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 131, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 131, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 132, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 132, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 133, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 133, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 134, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 134, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 135, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 135, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 136, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 136, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 137, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 137, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 138, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 138, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 139, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 140, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 141, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 142, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 142, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 143, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 143, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 144, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 144, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 145, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 145, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 146, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 146, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 146, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 147, "R/W", 0, 0, 0ull, 0ull},
- {"NCB_NXA" , 1, 1, 147, "R/W", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 147, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 147, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 147, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 147, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 147, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 148, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB_NXA" , 1, 1, 148, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 148, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 148, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 148, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 148, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 148, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 149, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 149, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 150, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 150, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 151, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 151, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 151, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 152, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 152, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 153, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 153, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 154, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_5_63" , 5, 59, 154, "RAZ", 1, 1, 0, 0},
- {"CONT_PKT" , 0, 1, 155, "R/W", 0, 1, 0ull, 0},
- {"TPA_CLR" , 1, 1, 155, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 155, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX1" , 0, 8, 156, "R/W", 0, 1, 8ull, 0},
- {"MAX2" , 8, 8, 156, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_16_63" , 16, 48, 156, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 6, 157, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_6_63" , 6, 58, 157, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 158, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 158, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 159, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 159, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 160, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 160, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 161, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 161, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 162, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 163, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 163, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 164, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 164, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 164, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 164, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 164, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 164, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 165, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 165, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 166, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 166, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 166, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 167, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 168, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 168, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 168, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 168, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 168, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 169, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 169, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 169, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 169, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 169, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 170, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 171, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 172, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 173, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 174, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 174, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 174, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 175, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 175, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 176, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 176, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 177, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 177, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 177, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 177, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 177, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 178, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 178, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 178, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 178, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 178, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 179, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 180, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 181, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 181, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 182, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 183, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 183, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 184, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 184, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 185, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 186, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 186, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 187, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 187, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 188, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 189, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 190, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 191, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 191, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 192, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 193, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 194, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 194, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 195, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 195, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 196, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 196, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 196, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 197, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 197, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 198, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 198, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 198, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 198, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 199, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 199, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 200, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 200, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 201, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 201, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 201, "R/W", 0, 0, 0ull, 0ull},
- {"PRB_CON" , 0, 32, 202, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 202, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 202, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 202, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 203, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 203, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 203, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 204, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 204, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 205, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 205, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 206, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 207, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 207, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 207, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 208, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 208, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 208, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 208, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 209, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 210, "RO", 0, 0, 0ull, 0ull},
- {"STIN_MSK" , 4, 1, 210, "RO", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 210, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 13, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 210, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 9, 211, "RO", 0, 0, 0ull, 0ull},
- {"VAB_VWCF" , 9, 1, 211, "RO", 0, 0, 0ull, 0ull},
- {"LRF" , 10, 2, 211, "RO", 0, 0, 0ull, 0ull},
- {"VWDF" , 12, 4, 211, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 211, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"PICBST" , 2, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"RHDF" , 4, 4, 212, "RO", 0, 0, 0ull, 0ull},
- {"RMDF" , 8, 4, 212, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 212, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 213, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 213, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 213, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 213, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 213, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 213, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 213, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 213, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 213, "RAZ", 1, 1, 0, 0},
- {"L2T" , 0, 1, 214, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 214, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 214, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 3, 214, "R/W", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 4, 214, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 214, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 4, 214, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 214, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 215, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 215, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 215, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 215, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 215, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 216, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 216, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 216, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 216, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 217, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 217, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 218, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 218, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 4, 218, "RO", 0, 0, 0ull, 0ull},
- {"SET" , 18, 3, 218, "RO", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 4, 218, "RO", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 218, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 219, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 219, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 10, 220, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 10, 17, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 220, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 4, 221, "R/W", 0, 0, 15ull, 15ull},
- {"STPARTDIS" , 4, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 221, "RAZ", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 222, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 223, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 8, 224, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK1" , 8, 8, 224, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK2" , 16, 8, 224, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK3" , 24, 8, 224, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 224, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK4" , 0, 8, 225, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK5" , 8, 8, 225, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK6" , 16, 8, 225, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK7" , 24, 8, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 225, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK8" , 0, 8, 226, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK9" , 8, 8, 226, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK10" , 16, 8, 226, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK11" , 24, 8, 226, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 226, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK12" , 0, 8, 227, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK13" , 8, 8, 227, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK14" , 16, 8, 227, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK15" , 24, 8, 227, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 227, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 8, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 228, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 229, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 229, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 230, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 231, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 232, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 232, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 233, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 233, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 233, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 233, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 233, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 233, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 233, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 11, 234, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 3, 234, "RO", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 234, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 234, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 235, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 235, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 236, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 236, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 236, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 237, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 237, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 238, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 239, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 240, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_512K" , 34, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_256K" , 35, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 240, "RO", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 241, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 241, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 241, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 241, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 10, 241, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 3, 241, "RO", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 241, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 241, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_28_63" , 28, 36, 241, "RAZ", 0, 0, 0ull, 0ull},
- {"RATE" , 0, 8, 242, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_63" , 8, 56, 242, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 7, 243, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_7_63" , 7, 57, 243, "RAZ", 1, 1, 0, 0},
- {"RATE" , 0, 16, 244, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 244, "RAZ", 1, 1, 0, 0},
- {"DBG_EN" , 0, 1, 245, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 245, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 246, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 246, "RAZ", 1, 1, 0, 0},
- {"POLARITY" , 0, 1, 247, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 247, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 8, 248, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 248, "RAZ", 1, 1, 0, 0},
- {"FORMAT" , 0, 4, 249, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 249, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 250, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 250, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 251, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 251, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 32, 252, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 252, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 32, 253, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 253, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 32, 254, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 254, "RAZ", 1, 1, 0, 0},
- {"PCTL_DAT" , 0, 4, 255, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CMD" , 4, 4, 255, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CLK" , 8, 4, 255, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 255, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 255, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CMD" , 20, 4, 255, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CLK" , 24, 4, 255, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 255, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 255, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 256, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 256, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 256, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 256, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 256, "R/W", 0, 0, 0ull, 1ull},
- {"MODE128B" , 10, 1, 256, "R/W", 0, 0, 1ull, 1ull},
- {"SET_ZERO" , 11, 1, 256, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MRF" , 12, 1, 256, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 256, "R/W", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 256, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_17" , 16, 2, 256, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 256, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 256, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 256, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 256, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 256, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 256, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 257, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 258, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 259, "R/W", 0, 0, 1ull, 1ull},
- {"RDQS" , 1, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 259, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 259, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 259, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 259, "R/W", 0, 0, 2ull, 2ull},
- {"SILO_HC" , 21, 1, 259, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 259, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 259, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 259, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 259, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 259, "RAZ", 0, 0, 0ull, 0ull},
- {"MRDSYN0" , 0, 8, 260, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 260, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 260, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 260, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 260, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 261, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 261, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 261, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 261, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 261, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 262, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 262, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 263, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 263, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 264, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 264, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 264, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 264, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 264, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 264, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 264, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 264, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 264, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 264, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 264, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 265, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 265, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 265, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 265, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 265, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 265, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 265, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 265, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_31_63" , 31, 33, 265, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 266, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 266, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 267, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 267, "RAZ", 1, 1, 0, 0},
- {"BWCTL" , 0, 4, 268, "R/W", 0, 0, 0ull, 0ull},
- {"BWUPD" , 4, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 268, "RAZ", 1, 1, 0, 0},
- {"RODT_LO0" , 0, 4, 269, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO1" , 4, 4, 269, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO2" , 8, 4, 269, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO3" , 12, 4, 269, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI0" , 16, 4, 269, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI1" , 20, 4, 269, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI2" , 24, 4, 269, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI3" , 28, 4, 269, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 269, "RAZ", 1, 1, 0, 0},
- {"WODT_LO0" , 0, 4, 270, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO1" , 4, 4, 270, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO2" , 8, 4, 270, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO3" , 12, 4, 270, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI0" , 16, 4, 270, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI1" , 20, 4, 270, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI2" , 24, 4, 270, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI3" , 28, 4, 270, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
- {"NCBI" , 0, 1, 271, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 271, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 2, 1, 271, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 271, "RAZ", 1, 1, 0, 0},
- {"ADR_ERR" , 0, 1, 272, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 272, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 272, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 273, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 273, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 273, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 274, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 274, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 274, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 275, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 275, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 275, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 275, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 276, "R/W", 1, 1, 0, 0},
- {"BASE" , 0, 16, 277, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 277, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_29" , 28, 2, 277, "RAZ", 1, 1, 0, 0},
- {"ORBIT" , 30, 1, 277, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 277, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 277, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 278, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 278, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 278, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 278, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 278, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 278, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 278, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 278, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 278, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_54_59" , 54, 6, 278, "RAZ", 1, 1, 0, 0},
- {"PAGES" , 60, 2, 278, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 278, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 278, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 279, "R/W", 0, 0, 26ull, 26ull},
- {"RESERVED_6_7" , 6, 2, 279, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 279, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 279, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 280, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 280, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 281, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 281, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 16, 282, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 282, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 282, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 282, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 282, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 282, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 282, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 282, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 283, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 283, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 283, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 283, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 283, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 283, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 283, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 284, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 284, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 7, 285, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 285, "RAZ", 1, 1, 0, 0},
- {"EFUSE" , 8, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 285, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 285, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 285, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 285, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 10, 286, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 286, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 287, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 287, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 287, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 287, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 287, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 287, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 287, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 287, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 288, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 288, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 288, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 288, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 288, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 288, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 288, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 288, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 288, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 288, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 288, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 288, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 289, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 289, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 289, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 290, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 290, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 290, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 291, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 291, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 292, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 292, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 293, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 293, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 294, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 294, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 294, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 294, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 294, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 294, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 294, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 295, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 295, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 296, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 296, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 296, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 296, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 296, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 296, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 296, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 297, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 297, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 297, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 297, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 298, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 298, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 298, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 299, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 299, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 299, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 299, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 299, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 299, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 299, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 299, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 299, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 300, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 301, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 301, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 301, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 301, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 301, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 301, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 301, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 301, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 301, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 302, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 302, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 303, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 303, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 304, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 304, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 304, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 304, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 305, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 305, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 306, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 306, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 307, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 307, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 308, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 308, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 308, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 308, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 309, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 309, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 310, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 311, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 311, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 312, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 312, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 313, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 313, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 314, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 314, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 315, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 315, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 315, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 315, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 315, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 315, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 316, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 316, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 317, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 317, "R/W", 0, 1, 0ull, 0},
- {"DPI_BS" , 0, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"PDF_BS" , 1, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"DOB_BS" , 2, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"NUS_BS" , 3, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"POS_BS" , 4, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"POF3_BS" , 5, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"POF2_BS" , 6, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"POF1_BS" , 7, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"POF0_BS" , 8, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"PIG_BS" , 9, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"PGF_BS" , 10, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"RDNL_BS" , 11, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"PCAD_BS" , 12, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"PCAC_BS" , 13, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"RDN_BS" , 14, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"PCN_BS" , 15, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"PCNC_BS" , 16, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"RDP_BS" , 17, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"DIF_BS" , 18, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"CSR_BS" , 19, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 318, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 319, "R/W", 0, 1, 1024ull, 0},
- {"ISIZE" , 16, 7, 319, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 319, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 320, "R/W", 0, 0, 0ull, 50ull},
- {"RESERVED_10_31" , 10, 22, 320, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_WORD" , 32, 5, 320, "R/W", 0, 0, 2ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 320, "RAZ", 0, 0, 0ull, 0ull},
- {"WAIT_COM" , 40, 1, 320, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_WDIS" , 41, 1, 320, "R/W", 0, 0, 0ull, 0ull},
- {"INS0_64B" , 42, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"INS1_64B" , 43, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"INS2_64B" , 44, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"INS3_64B" , 45, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"INS0_ENB" , 46, 1, 320, "R/W", 0, 0, 0ull, 1ull},
- {"INS1_ENB" , 47, 1, 320, "R/W", 0, 0, 0ull, 1ull},
- {"INS2_ENB" , 48, 1, 320, "R/W", 0, 0, 0ull, 1ull},
- {"INS3_ENB" , 49, 1, 320, "R/W", 0, 0, 0ull, 1ull},
- {"OUT0_ENB" , 50, 1, 320, "R/W", 0, 0, 0ull, 1ull},
- {"OUT1_ENB" , 51, 1, 320, "R/W", 0, 0, 0ull, 1ull},
- {"OUT2_ENB" , 52, 1, 320, "R/W", 0, 0, 0ull, 1ull},
- {"OUT3_ENB" , 53, 1, 320, "R/W", 0, 0, 0ull, 1ull},
- {"DIS_PNIW" , 54, 1, 320, "R/W", 0, 0, 0ull, 1ull},
- {"CHIP_REV" , 55, 8, 320, "RO", 1, 1, 0, 0},
- {"RESERVED_63_63" , 63, 1, 320, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 321, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 321, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 0, 14, 322, "R/W", 0, 1, 0ull, 0},
- {"LP_ENB" , 14, 1, 322, "R/W", 0, 0, 0ull, 1ull},
- {"HP_ENB" , 15, 1, 322, "R/W", 0, 0, 0ull, 1ull},
- {"O_MODE" , 16, 1, 322, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 17, 2, 322, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 19, 1, 322, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 20, 1, 322, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 21, 1, 322, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 22, 3, 322, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 25, 9, 322, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 34, 1, 322, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 35, 1, 322, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 322, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 323, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 323, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 323, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 324, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 324, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 324, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 325, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 325, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 325, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 326, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 326, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 326, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 327, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 327, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 328, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 328, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 329, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 329, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 329, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 329, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 329, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_RSL" , 2, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"PO0_2SML" , 3, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"PO1_2SML" , 4, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"PO2_2SML" , 5, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"PO3_2SML" , 6, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I0_RTOUT" , 7, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I1_RTOUT" , 8, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I2_RTOUT" , 9, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I3_RTOUT" , 10, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I0_OVERF" , 11, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I1_OVERF" , 12, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I2_OVERF" , 13, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I3_OVERF" , 14, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P0_RTOUT" , 15, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P1_RTOUT" , 16, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P2_RTOUT" , 17, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P3_RTOUT" , 18, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PERR" , 19, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PERR" , 20, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PERR" , 21, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PERR" , 22, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"G0_RTOUT" , 23, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"G1_RTOUT" , 24, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"G2_RTOUT" , 25, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"G3_RTOUT" , 26, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PPERR" , 27, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PPERR" , 28, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PPERR" , 29, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PPERR" , 30, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PTOUT" , 31, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PTOUT" , 32, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PTOUT" , 33, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PTOUT" , 34, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I0_PPERR" , 35, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I1_PPERR" , 36, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I2_PPERR" , 37, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"I3_PPERR" , 38, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"WIN_RTO" , 39, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"P_DPERR" , 40, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 41, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_42_63" , 42, 22, 330, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_RSL" , 2, 1, 331, "RO", 0, 0, 0ull, 0ull},
- {"PO0_2SML" , 3, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO1_2SML" , 4, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO2_2SML" , 5, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO3_2SML" , 6, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_RTOUT" , 7, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_RTOUT" , 8, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_RTOUT" , 9, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_RTOUT" , 10, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_OVERF" , 11, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_OVERF" , 12, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_OVERF" , 13, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_OVERF" , 14, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_RTOUT" , 15, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_RTOUT" , 16, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_RTOUT" , 17, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_RTOUT" , 18, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PERR" , 19, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PERR" , 20, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PERR" , 21, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PERR" , 22, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"G0_RTOUT" , 23, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"G1_RTOUT" , 24, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"G2_RTOUT" , 25, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"G3_RTOUT" , 26, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PPERR" , 27, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PPERR" , 28, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PPERR" , 29, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PPERR" , 30, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PTOUT" , 31, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PTOUT" , 32, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PTOUT" , 33, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PTOUT" , 34, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_PPERR" , 35, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_PPERR" , 36, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_PPERR" , 37, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_PPERR" , 38, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_RTO" , 39, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DPERR" , 40, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 41, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 331, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 332, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 332, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 333, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 333, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 28, 334, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 28, 1, 334, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 29, 1, 334, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 30, 1, 334, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 31, 1, 334, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 32, 2, 334, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 34, 2, 334, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 334, "RAZ", 1, 1, 0, 0},
- {"INT_VEC" , 0, 64, 335, "R/W1C", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 32, 336, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 336, "RAZ", 1, 1, 0, 0},
- {"ROR_SL0" , 0, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL0" , 1, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL0" , 2, 2, 337, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL1" , 4, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL1" , 5, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL1" , 6, 2, 337, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL2" , 8, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL2" , 9, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL2" , 10, 2, 337, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL3" , 12, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL3" , 13, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL3" , 14, 2, 337, "R/W", 0, 1, 0ull, 0},
- {"IPTR_O0" , 16, 1, 337, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O1" , 17, 1, 337, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O2" , 18, 1, 337, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O3" , 19, 1, 337, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_23" , 20, 4, 337, "RAZ", 0, 0, 0ull, 0ull},
- {"O0_CSRM" , 24, 1, 337, "R/W", 0, 0, 0ull, 1ull},
- {"O1_CSRM" , 25, 1, 337, "R/W", 0, 0, 0ull, 1ull},
- {"O2_CSRM" , 26, 1, 337, "R/W", 0, 0, 0ull, 1ull},
- {"O3_CSRM" , 27, 1, 337, "R/W", 0, 0, 0ull, 1ull},
- {"O0_RO" , 28, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"O0_NS" , 29, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"O0_ES" , 30, 2, 337, "R/W", 0, 1, 0ull, 0},
- {"O1_RO" , 32, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"O1_NS" , 33, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"O1_ES" , 34, 2, 337, "R/W", 0, 1, 0ull, 0},
- {"O2_RO" , 36, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"O2_NS" , 37, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"O2_ES" , 38, 2, 337, "R/W", 0, 1, 0ull, 0},
- {"O3_RO" , 40, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"O3_NS" , 41, 1, 337, "R/W", 0, 1, 0ull, 0},
- {"O3_ES" , 42, 2, 337, "R/W", 0, 1, 0ull, 0},
- {"P0_BMODE" , 44, 1, 337, "R/W", 0, 0, 0ull, 0ull},
- {"P1_BMODE" , 45, 1, 337, "R/W", 0, 0, 0ull, 0ull},
- {"P2_BMODE" , 46, 1, 337, "R/W", 0, 0, 0ull, 0ull},
- {"P3_BMODE" , 47, 1, 337, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 337, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 338, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 2, 338, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_63_63" , 63, 1, 338, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 339, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 3, 339, "RO", 0, 0, 0ull, 0ull},
- {"AVAIL" , 0, 32, 340, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 6, 340, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 340, "RAZ", 1, 1, 0, 0},
- {"AVAIL" , 0, 32, 341, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 5, 341, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 341, "RAZ", 1, 1, 0, 0},
- {"RD_BRST" , 0, 7, 342, "R/W", 0, 0, 17ull, 64ull},
- {"WR_BRST" , 7, 7, 342, "R/W", 0, 0, 16ull, 64ull},
- {"RESERVED_14_63" , 14, 50, 342, "RAZ", 1, 1, 0, 0},
- {"PARK_DEV" , 0, 3, 343, "R/W", 0, 1, 0ull, 0},
- {"PARK_MOD" , 3, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"EN" , 4, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 343, "RAZ", 1, 1, 0, 0},
- {"CMD_SIZE" , 0, 11, 344, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_11_63" , 11, 53, 344, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 345, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 345, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 345, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 345, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 345, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 345, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 345, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 345, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 345, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 346, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 346, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 346, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 346, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 346, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 346, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 346, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 346, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 346, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 346, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 346, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 346, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 346, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 347, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 347, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 347, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 347, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 347, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 347, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 347, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 348, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 348, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 348, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 348, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 348, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 348, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 348, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 348, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 348, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 348, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 348, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 348, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 348, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 4, 349, "R/W", 0, 0, 15ull, 15ull},
- {"BP_ON" , 4, 4, 349, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 349, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"NPI" , 3, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_8" , 8, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_13" , 13, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_14" , 14, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_15" , 15, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"LMC" , 17, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_21" , 21, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"ASX0" , 22, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"ASX1" , 23, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_24" , 24, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_25" , 25, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_26" , 26, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_27" , 27, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_28" , 28, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_29" , 29, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RINT_31" , 31, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 350, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 32, 351, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 351, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 352, "R/W", 0, 0, 0ull, 131072ull},
- {"RESERVED_32_63" , 32, 32, 352, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 353, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 353, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 353, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 353, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 354, "RO", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 354, "RO", 0, 0, 4ull, 4ull},
- {"ISAE" , 0, 1, 355, "RO", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 355, "R/W", 0, 0, 0ull, 1ull},
- {"ME" , 2, 1, 355, "R/W", 0, 0, 0ull, 1ull},
- {"SCSE" , 3, 1, 355, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 355, "R/W", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 355, "RO", 0, 0, 0ull, 0ull},
- {"PEE" , 6, 1, 355, "R/W", 0, 0, 0ull, 1ull},
- {"ADS" , 7, 1, 355, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 355, "R/W", 0, 0, 0ull, 1ull},
- {"FBBE" , 9, 1, 355, "R/W", 0, 0, 0ull, 1ull},
- {"I_DIS" , 10, 1, 355, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 355, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 355, "RO", 0, 0, 0ull, 0ull},
- {"CLE" , 20, 1, 355, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 355, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_22" , 22, 1, 355, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 355, "RO", 0, 1, 1ull, 0},
- {"MDPE" , 24, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 355, "RO", 0, 0, 1ull, 1ull},
- {"STA" , 27, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 356, "RO", 0, 0, 1ull, 1ull},
- {"CC" , 8, 24, 356, "RO", 0, 0, 1048576ull, 1048576ull},
- {"CLS" , 0, 8, 357, "R/W", 0, 1, 0ull, 0},
- {"LT" , 8, 8, 357, "R/W", 0, 0, 0ull, 64ull},
- {"HT" , 16, 8, 357, "RO", 0, 0, 0ull, 0ull},
- {"BCOD" , 24, 4, 357, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_29" , 28, 2, 357, "RAZ", 1, 1, 0, 0},
- {"BRB" , 30, 1, 357, "R/W", 0, 0, 0ull, 0ull},
- {"BCAP" , 31, 1, 357, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 358, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 358, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 358, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 8, 358, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 12, 20, 358, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 359, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 360, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 360, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 23, 360, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 27, 5, 360, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 361, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 362, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 362, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 28, 362, "RO", 0, 0, 0ull, 0ull},
- {"HBASEZ" , 0, 7, 363, "RO", 0, 0, 0ull, 0ull},
- {"HBASE" , 7, 25, 363, "R/W", 0, 1, 0ull, 0},
- {"CISP" , 0, 32, 364, "RO", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 365, "RO", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 365, "RO", 0, 0, 1ull, 1ull},
- {"ERBAR_EN" , 0, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_10" , 1, 10, 366, "RAZ", 1, 1, 0, 0},
- {"ERBARZ" , 11, 5, 366, "RO", 0, 0, 0ull, 0ull},
- {"ERBAR" , 16, 16, 366, "R/W", 0, 1, 0ull, 0},
- {"CP" , 0, 8, 367, "RO", 0, 0, 224ull, 224ull},
- {"RESERVED_8_31" , 8, 24, 367, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 368, "R/W", 0, 1, 0ull, 0},
- {"INTA" , 8, 8, 368, "RO", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 368, "RO", 0, 0, 64ull, 64ull},
- {"ML" , 24, 8, 368, "RO", 0, 0, 64ull, 64ull},
- {"MLTD" , 0, 1, 369, "R/W", 0, 0, 0ull, 1ull},
- {"TSWC" , 1, 1, 369, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 369, "RAZ", 1, 1, 0, 0},
- {"DPPMR" , 3, 1, 369, "R/W", 0, 0, 0ull, 0ull},
- {"PBE" , 4, 12, 369, "R/W", 0, 0, 0ull, 0ull},
- {"TILT" , 16, 4, 369, "R/W", 0, 0, 0ull, 0ull},
- {"TSLTE" , 20, 3, 369, "R/W", 0, 0, 0ull, 0ull},
- {"TMAE" , 23, 1, 369, "R/W", 0, 0, 0ull, 0ull},
- {"TWTAE" , 24, 1, 369, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEN" , 25, 1, 369, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEI" , 26, 1, 369, "R/W", 0, 0, 0ull, 0ull},
- {"TRTAE" , 27, 1, 369, "R/W", 0, 0, 0ull, 0ull},
- {"TRDRS" , 28, 1, 369, "R/W", 0, 0, 0ull, 0ull},
- {"RDSATI" , 29, 1, 369, "R/W", 0, 0, 0ull, 0ull},
- {"TRDARD" , 30, 1, 369, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRDNPR" , 31, 1, 369, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSCME" , 0, 32, 370, "R/W1C", 0, 1, 0ull, 0},
- {"TDSRPS" , 0, 32, 371, "R/W1C", 0, 0, 0ull, 0ull},
- {"TDOMC" , 0, 5, 372, "R/W", 0, 0, 1ull, 1ull},
- {"TIDOMC" , 5, 1, 372, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 372, "RAZ", 1, 1, 0, 0},
- {"TIBDE" , 7, 1, 372, "R/W", 0, 0, 0ull, 0ull},
- {"TIBCD" , 8, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_10" , 9, 2, 372, "RAZ", 1, 1, 0, 0},
- {"TMAPES" , 11, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMDPES" , 12, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMSE" , 13, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMEI" , 14, 1, 372, "RO", 0, 0, 0ull, 0ull},
- {"TECI" , 15, 1, 372, "RO", 0, 0, 0ull, 0ull},
- {"TMES" , 16, 8, 372, "RO", 0, 0, 0ull, 0ull},
- {"MDRRMC" , 24, 3, 372, "R/W", 0, 0, 2ull, 2ull},
- {"MDRIMC" , 27, 1, 372, "R/W", 0, 0, 0ull, 0ull},
- {"MDRE" , 28, 1, 372, "R/W", 0, 0, 0ull, 0ull},
- {"MDWE" , 29, 1, 372, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCI" , 30, 1, 372, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCM" , 31, 1, 372, "R/W", 0, 0, 1ull, 1ull},
- {"MDSP" , 0, 32, 373, "R/W1C", 0, 1, 0ull, 0},
- {"SCMRE" , 0, 32, 374, "R/W1C", 0, 1, 0ull, 0},
- {"MTTV" , 0, 8, 375, "R/W", 0, 0, 0ull, 0ull},
- {"MRV" , 8, 8, 375, "R/W", 0, 0, 0ull, 255ull},
- {"MTTA" , 16, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRA" , 17, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLUSH" , 18, 1, 375, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_19_24" , 19, 6, 375, "RAZ", 1, 1, 0, 0},
- {"MAC" , 25, 7, 375, "R/W", 0, 0, 0ull, 0ull},
- {"PXCID" , 0, 8, 376, "RO", 0, 0, 7ull, 7ull},
- {"NCP" , 8, 8, 376, "RO", 0, 0, 232ull, 232ull},
- {"DPERE" , 16, 1, 376, "R/W", 0, 0, 0ull, 0ull},
- {"ROE" , 17, 1, 376, "R/W", 0, 0, 1ull, 1ull},
- {"MMBC" , 18, 2, 376, "R/W", 0, 0, 0ull, 0ull},
- {"MOST" , 20, 3, 376, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_23_31" , 23, 9, 376, "RAZ", 1, 1, 0, 0},
- {"FN" , 0, 3, 377, "RO", 0, 0, 0ull, 0ull},
- {"DN" , 3, 5, 377, "RO", 0, 0, 31ull, 31ull},
- {"BN" , 8, 8, 377, "RO", 0, 1, 17ull, 0},
- {"W64" , 16, 1, 377, "RO", 0, 0, 1ull, 1ull},
- {"M133" , 17, 1, 377, "RO", 0, 0, 1ull, 1ull},
- {"SCD" , 18, 1, 377, "R/W1C", 0, 1, 0ull, 0},
- {"USC" , 19, 1, 377, "R/W1C", 0, 1, 0ull, 0},
- {"DC" , 20, 1, 377, "RO", 0, 0, 0ull, 0ull},
- {"MMRBCD" , 21, 2, 377, "RO", 0, 0, 2ull, 2ull},
- {"MOSTD" , 23, 3, 377, "RO", 0, 0, 3ull, 3ull},
- {"MCRSD" , 26, 3, 377, "RO", 0, 0, 7ull, 7ull},
- {"SCEMR" , 29, 1, 377, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 377, "RAZ", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 378, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 378, "RO", 0, 0, 240ull, 240ull},
- {"PCIMIV" , 16, 3, 378, "RO", 0, 0, 2ull, 2ull},
- {"PMEC" , 19, 1, 378, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 378, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 378, "RO", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 378, "RO", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 378, "RO", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 378, "RO", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 378, "RO", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 379, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 379, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 379, "R/W", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 379, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 379, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 379, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 379, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEN" , 23, 1, 379, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 379, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 380, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 380, "RO", 0, 0, 0ull, 0ull},
- {"MSIEN" , 16, 1, 380, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 380, "RO", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 380, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 380, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 380, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 381, "RAZ", 1, 1, 0, 0},
- {"MSI31T2" , 2, 30, 381, "R/W", 0, 1, 0ull, 0},
- {"MSI" , 0, 32, 382, "R/W", 0, 1, 0ull, 0},
- {"MSIMD" , 0, 16, 383, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 383, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 384, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 384, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 384, "R/W", 0, 0, 0ull, 1ull},
- {"TSR_HWM" , 4, 3, 384, "R/W", 0, 1, 1ull, 0},
- {"PMO_FPC" , 7, 3, 384, "R/W", 0, 0, 0ull, 0ull},
- {"PMO_AMOD" , 10, 1, 384, "R/W", 0, 0, 0ull, 0ull},
- {"B12_BIST" , 11, 1, 384, "RO", 0, 0, 0ull, 0ull},
- {"AP_64AD" , 12, 1, 384, "RO", 1, 1, 0, 0},
- {"AP_PCIX" , 13, 1, 384, "RO", 1, 1, 0, 0},
- {"RESERVED_14_14" , 14, 1, 384, "RAZ", 0, 0, 0ull, 0ull},
- {"EN_WFILT" , 15, 1, 384, "R/W", 0, 0, 0ull, 1ull},
- {"SCM" , 16, 1, 384, "RO", 0, 1, 0ull, 0},
- {"SCMTYP" , 17, 1, 384, "RO", 0, 1, 0ull, 0},
- {"BAR2PRES" , 18, 1, 384, "R/W", 1, 1, 0, 0},
- {"ERST_N" , 19, 1, 384, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_20_31" , 20, 12, 384, "RAZ", 1, 1, 0, 0},
- {"INC_VAL" , 0, 16, 385, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 385, "RAZ", 1, 1, 0, 0},
- {"DMA_CNT" , 0, 32, 386, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 387, "R/W", 0, 1, 0ull, 0},
- {"DMA_TIME" , 0, 32, 388, "R/W", 0, 1, 0ull, 0},
- {"ICNT" , 0, 32, 389, "RO", 0, 0, 0ull, 0ull},
- {"ITR_WABT" , 0, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IMR_WABT" , 1, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IMR_WTTO" , 2, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"ITR_ABT" , 3, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IMR_ABT" , 4, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IMR_TTO" , 5, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IMSI_PER" , 6, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IMSI_TABT" , 7, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IMSI_MABT" , 8, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IMSC_MSG" , 9, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"ITSR_ABT" , 10, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"ISERR" , 11, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IAPERR" , 12, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IDPERR" , 13, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IRSL_INT" , 16, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IPCNT0" , 17, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IPCNT1" , 18, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IPCNT2" , 19, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IPCNT3" , 20, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IPTIME0" , 21, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IPTIME1" , 22, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IPTIME2" , 23, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IPTIME3" , 24, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IDCNT0" , 25, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IDCNT1" , 26, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IDTIME0" , 27, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"IDTIME1" , 28, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 390, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 390, "RAZ", 1, 1, 0, 0},
- {"RTR_WABT" , 0, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RMR_WABT" , 1, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RMR_WTTO" , 2, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RTR_ABT" , 3, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RMR_ABT" , 4, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RMR_TTO" , 5, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RMSI_PER" , 6, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RMSI_TABT" , 7, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RMSI_MABT" , 8, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RMSC_MSG" , 9, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RTSR_ABT" , 10, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RSERR" , 11, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RAPERR" , 12, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RDPERR" , 13, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RRSL_INT" , 16, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RPCNT0" , 17, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RPCNT1" , 18, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RPCNT2" , 19, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RPCNT3" , 20, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RPTIME0" , 21, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RPTIME1" , 22, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RPTIME2" , 23, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RPTIME3" , 24, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RDCNT0" , 25, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RDCNT1" , 26, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RDTIME0" , 27, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RDTIME1" , 28, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 391, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 392, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT2" , 19, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT3" , 20, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME2" , 23, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME3" , 24, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 392, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 393, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT2" , 19, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT3" , 20, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME2" , 23, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME3" , 24, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 393, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 6, 394, "WO", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 394, "R/W", 1, 1, 0, 0},
- {"PTR_CNT" , 0, 16, 395, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 16, 16, 395, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 0, 32, 396, "RO", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 397, "R/W", 0, 1, 0ull, 0},
- {"PKT_TIME" , 0, 32, 398, "R/W", 0, 1, 0ull, 0},
- {"PREFETCH" , 0, 3, 399, "R/W", 0, 0, 0ull, 2ull},
- {"MIN_DATA" , 3, 6, 399, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_9_31" , 9, 23, 399, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 400, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 400, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 400, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 401, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 401, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 401, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 31, 402, "R/W", 0, 0, 10000ull, 10000ull},
- {"ENB" , 31, 1, 402, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 402, "RAZ", 1, 1, 0, 0},
- {"SCM" , 0, 32, 403, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 403, "RAZ", 1, 1, 0, 0},
- {"TSR" , 0, 36, 404, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 404, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 405, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 3, 45, 405, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 405, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 405, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 406, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 407, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 407, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 407, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 407, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 408, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 409, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 409, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 410, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 410, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 410, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 410, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 410, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 18, 411, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 411, "RAZ", 1, 1, 0, 0},
- {"REFLECT" , 0, 1, 412, "R/W", 0, 0, 1ull, 1ull},
- {"INVRES" , 1, 1, 412, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 412, "RAZ", 1, 1, 0, 0},
- {"IV" , 0, 32, 413, "R/W", 0, 0, 1185899593ull, 1185899593ull},
- {"RESERVED_32_63" , 32, 32, 413, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 414, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 414, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 415, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 415, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 415, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 415, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 416, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 416, "RAZ", 0, 1, 0ull, 0},
- {"L4_MAL" , 8, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 416, "RAZ", 0, 1, 0ull, 0},
- {"PKTDRP" , 0, 1, 417, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 417, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 417, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 417, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 417, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 417, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 417, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 417, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 417, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 417, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 418, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 419, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 420, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 420, "RAZ", 1, 1, 0, 0},
- {"CRC_EN" , 12, 1, 420, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_15" , 13, 3, 420, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 420, "RAZ", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 420, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 420, "RAZ", 1, 1, 0, 0},
- {"GRP_WAT" , 28, 4, 420, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 420, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 421, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 421, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 421, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 421, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 421, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 421, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 421, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 421, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 421, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 422, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 423, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 423, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 424, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 2, 424, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 424, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 424, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 424, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 424, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 424, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 424, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 424, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 425, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 425, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 426, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 426, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 427, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 427, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 428, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 429, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 429, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 430, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 430, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 431, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 431, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 432, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 432, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 433, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 433, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 434, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 434, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 435, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 435, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 436, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 436, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 437, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 437, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 438, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 438, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 439, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 439, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 440, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 440, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 441, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 441, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 442, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 442, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 442, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 443, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 443, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 443, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 444, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 444, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 445, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 445, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 446, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 446, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 446, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 446, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 447, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 447, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 447, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 447, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 447, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 0, 16, 448, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 448, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 448, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 448, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 449, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 449, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 449, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 449, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 449, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 450, "RO", 1, 0, 0, 0ull},
- {"WIDX2" , 0, 17, 451, "RO", 1, 0, 0, 0ull},
- {"RIDX2" , 17, 17, 451, "RO", 1, 0, 0, 0ull},
- {"WIDX" , 34, 17, 451, "RO", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 451, "RAZ", 1, 1, 0, 0},
- {"RIDX" , 0, 17, 452, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 452, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 453, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 453, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 453, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 453, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 453, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 454, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 454, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 454, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 454, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 454, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 455, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 4, 456, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 4, 2, 456, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 6, 1, 456, "RO", 1, 0, 0, 0ull},
- {"QID_BASE" , 7, 7, 456, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 14, 3, 456, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 17, 5, 456, "RO", 1, 0, 0, 0ull},
- {"QOS" , 22, 3, 456, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 456, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 26, 1, 456, "RO", 1, 0, 0, 0ull},
- {"RESERVED_27_27" , 27, 1, 456, "RO", 1, 0, 0, 0ull},
- {"CBUF_FRE" , 28, 1, 456, "RO", 1, 0, 0, 0ull},
- {"XFER_DWR" , 29, 1, 456, "RO", 1, 0, 0, 0ull},
- {"XFER_WOR" , 30, 1, 456, "RO", 1, 0, 0, 0ull},
- {"UID" , 31, 1, 456, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 32, 16, 456, "RO", 1, 0, 0, 0ull},
- {"DWRI_CNT" , 48, 13, 456, "RO", 1, 0, 0, 0ull},
- {"DWRI_LEN" , 61, 1, 456, "RO", 1, 0, 0, 0ull},
- {"DWRI_SOP" , 62, 1, 456, "RO", 1, 0, 0, 0ull},
- {"DWRI_MOD" , 63, 1, 456, "RO", 1, 0, 0, 0ull},
- {"DWRI_MOD" , 0, 2, 457, "RO", 1, 0, 0, 0ull},
- {"DWRI_UID" , 2, 1, 457, "RO", 1, 0, 0, 0ull},
- {"DWRI_CHK" , 3, 1, 457, "RO", 1, 0, 0, 0ull},
- {"WORK_MIN" , 4, 3, 457, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 7, 1, 457, "RO", 1, 0, 0, 0ull},
- {"QID_OFFM" , 8, 3, 457, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 457, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 458, "RO", 1, 0, 0, 0ull},
- {"START" , 16, 33, 458, "RO", 1, 0, 0, 0ull},
- {"DWB" , 49, 9, 458, "RO", 1, 0, 0, 0ull},
- {"RESERVED_58_63" , 58, 6, 458, "RO", 1, 1, 0, 0},
- {"QCB_RIDX" , 0, 6, 459, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 459, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 459, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 459, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 459, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 459, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 460, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 460, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 460, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 460, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 460, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 460, "RO", 1, 0, 0, 0ull},
- {"RESERVED_28_63" , 28, 36, 460, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 461, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 461, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 461, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 461, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 461, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 461, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 461, "WR0", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 461, "WR0", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 461, "WR0", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 462, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 462, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 462, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 462, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 462, "RAZ", 1, 1, 0, 0},
- {"PSB" , 0, 7, 463, "RO", 1, 0, 0, 0ull},
- {"PDB" , 7, 4, 463, "RO", 1, 0, 0, 0ull},
- {"QCB" , 11, 2, 463, "RO", 1, 0, 0, 0ull},
- {"QSB" , 13, 2, 463, "RO", 1, 0, 0, 0ull},
- {"CHK" , 15, 1, 463, "RO", 1, 0, 0, 0ull},
- {"CRC" , 16, 1, 463, "RO", 1, 0, 0, 0ull},
- {"OUT" , 17, 1, 463, "RO", 1, 0, 0, 0ull},
- {"NCB" , 18, 1, 463, "RO", 1, 0, 0, 0ull},
- {"WIF" , 19, 1, 463, "RO", 1, 0, 0, 0ull},
- {"RIF" , 20, 1, 463, "RO", 1, 0, 0, 0ull},
- {"COUNT" , 21, 1, 463, "RO", 1, 0, 0, 0ull},
- {"PSB2" , 22, 5, 463, "RO", 1, 0, 0, 0ull},
- {"RESERVED_27_63" , 27, 37, 463, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 464, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 464, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 464, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 464, "RAZ", 1, 1, 0, 0},
- {"REFIN" , 0, 1, 465, "R/W", 0, 0, 1ull, 1ull},
- {"INVRES" , 1, 1, 465, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 465, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 32, 466, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 466, "RAZ", 1, 1, 0, 0},
- {"IV" , 0, 32, 467, "R/W", 0, 0, 1185899593ull, 1185899593ull},
- {"RESERVED_32_63" , 32, 32, 467, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 17, 468, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 468, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 469, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 469, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 469, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 470, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 470, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 470, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 470, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 470, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 471, "R/W", 0, 0, 0ull, 0ull},
- {"MODE1" , 3, 3, 471, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 471, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 472, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 473, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 473, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 474, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 474, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 474, "RAZ", 1, 1, 0, 0},
- {"ADR0" , 0, 1, 475, "RO", 0, 0, 0ull, 0ull},
- {"ADR1" , 1, 1, 475, "RO", 0, 0, 0ull, 0ull},
- {"PEND0" , 2, 1, 475, "RO", 0, 0, 0ull, 0ull},
- {"PEND1" , 3, 1, 475, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 4, 1, 475, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 5, 1, 475, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 6, 1, 475, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 7, 1, 475, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 8, 1, 475, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 9, 1, 475, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 475, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 16, 475, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 475, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 476, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 476, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 477, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 477, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 477, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 477, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 477, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 477, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 477, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 477, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 477, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 478, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 478, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 478, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 479, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 479, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 480, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 480, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 12, 481, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 481, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 482, "R/W", 0, 0, 0ull, 1023ull},
- {"RESERVED_10_63" , 10, 54, 482, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 483, "R/W", 0, 0, 65535ull, 65535ull},
- {"RESERVED_16_63" , 16, 48, 483, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 484, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 484, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 484, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 484, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 484, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 11, 485, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 485, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 11, 485, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_23_23" , 23, 1, 485, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 12, 485, "RO", 0, 1, 2027ull, 0},
- {"BUF_CNT" , 36, 12, 485, "RO", 0, 1, 0ull, 0},
- {"DES_CNT" , 48, 12, 485, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 485, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 486, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 486, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 487, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 487, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 488, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 488, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 489, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 489, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 489, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 12, 490, "RO", 0, 1, 0ull, 0},
- {"DS_CNT" , 12, 12, 490, "RO", 0, 1, 0ull, 0},
- {"TC_CNT" , 24, 4, 490, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 490, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 491, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 491, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 491, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 491, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 491, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 11, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 492, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 11, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 492, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 492, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 492, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 493, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 493, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 494, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 494, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 494, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 495, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 495, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 495, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 495, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 495, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 496, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 496, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 496, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 496, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 496, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 496, "RAZ", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 496, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 496, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 497, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 497, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 497, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 497, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 1, 497, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 497, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 498, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 498, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 499, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 499, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 499, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 499, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 500, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 500, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 500, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 500, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 501, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 501, "RAZ", 0, 0, 0ull, 0ull},
- {"STAT0" , 0, 1, 502, "RO", 0, 0, 0ull, 0ull},
- {"STAT1" , 1, 1, 502, "RO", 0, 0, 0ull, 0ull},
- {"STAT2" , 2, 1, 502, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 502, "RAZ", 0, 0, 0ull, 0ull},
- {"SRXDLCK" , 0, 1, 503, "R/W", 0, 0, 0ull, 1ull},
- {"RCVTRN" , 1, 1, 503, "R/W", 0, 0, 0ull, 1ull},
- {"DRPTRN" , 2, 1, 503, "R/W", 0, 0, 0ull, 1ull},
- {"SNDTRN" , 3, 1, 503, "R/W", 0, 0, 0ull, 1ull},
- {"STATRCV" , 4, 1, 503, "R/W", 0, 0, 0ull, 0ull},
- {"STATDRV" , 5, 1, 503, "R/W", 0, 0, 0ull, 0ull},
- {"RUNBIST" , 6, 1, 503, "R/W", 0, 0, 0ull, 0ull},
- {"CLKDLY" , 7, 5, 503, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_12_15" , 12, 4, 503, "RAZ", 0, 0, 0ull, 0ull},
- {"SEETRN" , 16, 1, 503, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 503, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 504, "RAZ", 0, 1, 0ull, 0},
- {"D4CLK0" , 4, 1, 504, "R/W1C", 0, 1, 0ull, 0},
- {"D4CLK1" , 5, 1, 504, "R/W1C", 0, 1, 0ull, 0},
- {"S4CLK0" , 6, 1, 504, "R/W1C", 0, 1, 0ull, 0},
- {"S4CLK1" , 7, 1, 504, "R/W1C", 0, 1, 0ull, 0},
- {"SRXTRN" , 8, 1, 504, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_9_9" , 9, 1, 504, "RAZ", 0, 1, 0ull, 0},
- {"STXCAL" , 10, 1, 504, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 504, "RAZ", 0, 0, 0ull, 0ull},
- {"DLLDIS" , 0, 1, 505, "R/W", 1, 0, 0, 0ull},
- {"DLLFRC" , 1, 1, 505, "WR0", 1, 0, 0, 0ull},
- {"OFFDLY" , 2, 6, 505, "R/W", 1, 0, 0, 0ull},
- {"BITSEL" , 8, 5, 505, "R/W", 1, 1, 0, 0},
- {"OFFSET" , 13, 5, 505, "R/W", 1, 1, 0, 0},
- {"MUX" , 18, 1, 505, "WR0", 1, 1, 0, 0},
- {"INC" , 19, 1, 505, "WR0", 1, 1, 0, 0},
- {"DEC" , 20, 1, 505, "WR0", 1, 1, 0, 0},
- {"CLRDLY" , 21, 1, 505, "WR0", 1, 1, 0, 0},
- {"RESERVED_22_23" , 22, 2, 505, "RAZ", 0, 0, 0ull, 0ull},
- {"SSTEP" , 24, 1, 505, "R/W", 1, 0, 0, 0ull},
- {"SSTEP_GO" , 25, 1, 505, "WR0", 1, 1, 0, 0},
- {"RESERVED_26_27" , 26, 2, 505, "RAZ", 0, 0, 0ull, 0ull},
- {"FALL8" , 28, 1, 505, "R/W", 0, 0, 0ull, 0ull},
- {"FALLNOP" , 29, 1, 505, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 505, "RAZ", 0, 0, 0ull, 0ull},
- {"OFFSET" , 0, 5, 506, "RO", 0, 1, 0ull, 0},
- {"MUXSEL" , 5, 2, 506, "RO", 0, 1, 0ull, 0},
- {"UNXTERM" , 7, 1, 506, "R/W1C", 0, 0, 0ull, 0ull},
- {"TESTRES" , 8, 1, 506, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 506, "RAZ", 0, 0, 0ull, 0ull},
- {"SRX4CMP" , 0, 8, 507, "R/W", 0, 1, 0ull, 0},
- {"STX4PCMP" , 8, 4, 507, "R/W", 0, 1, 0ull, 0},
- {"STX4NCMP" , 12, 4, 507, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 507, "RAZ", 0, 0, 0ull, 0ull},
- {"ERRCNT" , 0, 4, 508, "R/W", 0, 0, 0ull, 3ull},
- {"RESERVED_4_5" , 4, 2, 508, "RAZ", 0, 0, 0ull, 0ull},
- {"DIPPAY" , 6, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"DIPCLS" , 7, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 8, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 508, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT" , 0, 8, 509, "RO", 0, 0, 0ull, 0ull},
- {"RSVOP" , 8, 4, 509, "RO", 0, 0, 0ull, 0ull},
- {"CALBNK" , 12, 2, 509, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_30" , 14, 17, 509, "RAZ", 0, 0, 0ull, 0ull},
- {"MUL" , 31, 1, 509, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 509, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 510, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 510, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 511, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_30" , 12, 19, 511, "RAZ", 0, 0, 0ull, 0ull},
- {"SPF" , 31, 1, 511, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 511, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 512, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 512, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 513, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 513, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX" , 0, 32, 514, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 514, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTSEL" , 0, 4, 515, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"MUX_EN" , 0, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"MACRO_EN" , 1, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"MAXDIST" , 2, 5, 516, "R/W", 0, 0, 0ull, 8ull},
- {"SET_BOOT" , 7, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"CLR_BOOT" , 8, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"JITTER" , 9, 3, 516, "R/W", 0, 0, 0ull, 1ull},
- {"TRNTEST" , 12, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 516, "RAZ", 0, 0, 0ull, 0ull},
- {"BW_CTL" , 0, 5, 517, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 517, "RAZ", 0, 0, 0ull, 0ull},
- {"SETTING" , 0, 17, 518, "RO", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 518, "RAZ", 0, 0, 0ull, 0ull},
- {"INF_EN" , 0, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_2" , 1, 2, 519, "RAZ", 0, 0, 0ull, 0ull},
- {"ST_EN" , 3, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"PRTS" , 4, 4, 519, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 519, "RAZ", 0, 0, 0ull, 0ull},
- {"IGNORE" , 0, 16, 520, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 520, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT0" , 0, 4, 521, "R/W", 1, 1, 0, 0},
- {"PRT1" , 4, 4, 521, "R/W", 1, 1, 0, 0},
- {"PRT2" , 8, 4, 521, "R/W", 1, 1, 0, 0},
- {"PRT3" , 12, 4, 521, "R/W", 1, 1, 0, 0},
- {"ODDPAR" , 16, 1, 521, "R/W", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 521, "RAZ", 0, 0, 0ull, 0ull},
- {"LEN" , 0, 7, 522, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 522, "RAZ", 0, 0, 0ull, 0ull},
- {"M" , 8, 8, 522, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 522, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_0_2" , 0, 3, 523, "R/W", 0, 0, 0ull, 0ull},
- {"IGNTPA" , 3, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"MINTRN" , 5, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 523, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 524, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 524, "RAZ", 0, 0, 0ull, 0ull},
- {"INF_EN" , 0, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_2" , 1, 2, 525, "RAZ", 0, 0, 0ull, 0ull},
- {"ST_EN" , 3, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 525, "RAZ", 0, 0, 0ull, 0ull},
- {"DIPMAX" , 0, 4, 526, "R/W", 0, 0, 0ull, 0ull},
- {"FRMMAX" , 4, 4, 526, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 526, "RAZ", 0, 0, 0ull, 0ull},
- {"IGNTPA" , 0, 16, 527, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 527, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 528, "R/W", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 528, "R/W", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 528, "R/W", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 528, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 528, "R/W", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 528, "R/W", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 528, "R/W", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 528, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 528, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 8, 1, 529, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 529, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"MINB" , 0, 9, 531, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 531, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT0" , 0, 4, 532, "R/W", 1, 1, 0, 0},
- {"PRT1" , 4, 4, 532, "R/W", 1, 1, 0, 0},
- {"PRT2" , 8, 4, 532, "R/W", 1, 1, 0, 0},
- {"PRT3" , 12, 4, 532, "R/W", 1, 1, 0, 0},
- {"ODDPAR" , 16, 1, 532, "R/W", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 532, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_T" , 0, 16, 533, "R/W", 0, 1, 0ull, 0},
- {"ALPHA" , 16, 16, 533, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 533, "RAZ", 0, 0, 0ull, 0ull},
- {"LEN" , 0, 7, 534, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 534, "RAZ", 0, 0, 0ull, 0ull},
- {"M" , 8, 8, 534, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 534, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 535, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 535, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 536, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 536, "RAZ", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 0, 4, 537, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 4, 1, 537, "WR0", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 537, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 538, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 538, "RAZ", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 0, 22, 539, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 539, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 539, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 539, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 539, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 539, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 540, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 540, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 540, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 541, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 541, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 541, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 541, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 541, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 542, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 542, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 542, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 542, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 543, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 543, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 543, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 543, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 543, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 543, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 544, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 544, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 544, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 544, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 545, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 545, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 546, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 546, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 547, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 547, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 548, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 548, "RAZ", 1, 1, 0, 0},
- {"TDF0" , 0, 1, 549, "RO", 0, 0, 0ull, 0ull},
- {"TDF1" , 1, 1, 549, "RO", 0, 0, 0ull, 0ull},
- {"TCF" , 2, 1, 549, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 549, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 550, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 550, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 550, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 550, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 551, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 551, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 551, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 552, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 552, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 553, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 553, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 554, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 554, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 555, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 555, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 555, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 555, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 555, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 555, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 555, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 555, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 555, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 555, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 555, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 555, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 556, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 556, "RAZ", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 557, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 558, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 559, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 559, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 560, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 561, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 562, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 562, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 562, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 562, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 562, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 562, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 562, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 562, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 562, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 562, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 562, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 562, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 563, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 563, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 564, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 564, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 565, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 565, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 566, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 566, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 567, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 567, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 567, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 567, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 568, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 568, "RAZ", 0, 0, 0ull, 0ull},
- {"ZIP_CTL" , 0, 4, 569, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 27, 569, "RO", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 569, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 570, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 570, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 570, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 570, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 570, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 571, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 571, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 572, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 572, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 572, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 572, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 572, "RO", 0, 0, 15360ull, 15360ull},
- {"RESERVED_48_63" , 48, 16, 572, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 14, 573, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 573, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 574, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 575, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn31xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_asx#_gmii_rx_clk_set" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 2, 0},
- {"cvmx_asx#_gmii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 2},
- {"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 4},
- {"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 6, 10},
- {"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 4, 16},
- {"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 2, 20},
- {"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 22},
- {"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 2, 24},
- {"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 4, 26},
- {"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 2, 30},
- {"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 32},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 17, 2, 34},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 18, 2, 36},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 19, 2, 38},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 20, 2, 40},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 21, 19, 42},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 26, 2, 61},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 31, 19, 63},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 36, 2, 82},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 37, 2, 84},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 39, 2, 86},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 41, 2, 88},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 42, 2, 90},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 43, 2, 92},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 44, 1, 94},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 46, 3, 95},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 47, 2, 98},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 48, 4, 100},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 49, 2, 104},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 50, 3, 106},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 54, 7, 109},
- {"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 56, 6, 116},
- {"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 57, 3, 122},
- {"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 58, 7, 125},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 59, 2, 132},
- {"cvmx_dfa_ddr2_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 6, 134},
- {"cvmx_dfa_ddr2_bus" , CVMX_CSR_DB_TYPE_RSL, 64, 61, 2, 140},
- {"cvmx_dfa_ddr2_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 16, 142},
- {"cvmx_dfa_ddr2_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 63, 6, 158},
- {"cvmx_dfa_ddr2_emrs" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 4, 164},
- {"cvmx_dfa_ddr2_fcnt" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 2, 168},
- {"cvmx_dfa_ddr2_mrs" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 4, 170},
- {"cvmx_dfa_ddr2_opt" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 3, 174},
- {"cvmx_dfa_ddr2_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 14, 177},
- {"cvmx_dfa_ddr2_tmg" , CVMX_CSR_DB_TYPE_RSL, 64, 69, 21, 191},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 70, 4, 212},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 71, 3, 216},
- {"cvmx_dfa_eclkcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 14, 219},
- {"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 73, 21, 233},
- {"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 6, 254},
- {"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 1, 260},
- {"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 76, 1, 261},
- {"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 1, 262},
- {"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 78, 1, 263},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 6, 264},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 80, 7, 270},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 81, 29, 277},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 82, 29, 306},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 335},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 337},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 3, 339},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 100, 3, 342},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 345},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 102, 2, 347},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 8, 349},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 104, 2, 357},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 3, 359},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 106, 2, 362},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 5, 364},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 110, 1, 369},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 1, 370},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 116, 1, 371},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 1, 372},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 1, 373},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 125, 1, 374},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 128, 2, 375},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 131, 4, 377},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 134, 2, 381},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 137, 11, 383},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 140, 9, 394},
- {"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 143, 2, 403},
- {"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 146, 2, 405},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 149, 2, 407},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 152, 20, 409},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 155, 20, 429},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 158, 2, 449},
- {"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 161, 4, 451},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 164, 2, 455},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 167, 2, 457},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 170, 2, 459},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 173, 2, 461},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 176, 2, 463},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 179, 2, 465},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 182, 2, 467},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 185, 2, 469},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 188, 2, 471},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 191, 2, 473},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 194, 4, 475},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 197, 2, 479},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 200, 2, 481},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 203, 2, 483},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 206, 4, 485},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 207, 2, 489},
- {"cvmx_gmx#_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 208, 4, 491},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 209, 2, 495},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 212, 3, 497},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 213, 5, 500},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 216, 2, 505},
- {"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 219, 2, 507},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 222, 3, 509},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 225, 2, 512},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 228, 2, 514},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 231, 2, 516},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 234, 2, 518},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 237, 2, 520},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 240, 2, 522},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 243, 2, 524},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 2, 526},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 249, 2, 528},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 2, 530},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 2, 532},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 534},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 2, 536},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 2, 538},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 267, 2, 540},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 270, 2, 542},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 2, 544},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 276, 2, 546},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 279, 2, 548},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 2, 550},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 283, 2, 552},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 284, 2, 554},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 285, 3, 556},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 286, 8, 559},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 287, 8, 567},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 288, 2, 575},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 289, 2, 577},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 290, 6, 579},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 291, 2, 585},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 2, 587},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 293, 2, 589},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 294, 7, 591},
- {"cvmx_gpio_boot_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 310, 3, 598},
- {"cvmx_gpio_dbg_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 311, 2, 601},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 312, 2, 603},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 313, 2, 605},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 314, 2, 607},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 315, 2, 609},
- {"cvmx_gpio_xbit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 316, 6, 611},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 324, 19, 617},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 325, 6, 636},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 326, 3, 642},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 327, 5, 645},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 328, 5, 650},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 329, 1, 655},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 330, 1, 656},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 331, 5, 657},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 332, 5, 662},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 333, 5, 667},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 334, 5, 672},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 335, 1, 677},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 336, 1, 678},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 337, 2, 679},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 338, 2, 681},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 339, 2, 683},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 340, 2, 685},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 341, 17, 687},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 342, 2, 704},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 343, 1, 706},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 344, 10, 707},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 345, 6, 717},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 346, 6, 723},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 347, 2, 729},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 348, 2, 731},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 349, 2, 733},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 350, 3, 735},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 355, 2, 738},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 360, 6, 740},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 361, 5, 746},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 362, 6, 751},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 363, 7, 757},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 364, 2, 764},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 372, 2, 766},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 373, 3, 768},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 374, 5, 771},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 382, 3, 776},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 383, 2, 779},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 384, 2, 781},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 385, 2, 783},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 386, 7, 785},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 387, 6, 792},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 8, 798},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 389, 9, 806},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 390, 10, 815},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 5, 825},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 4, 830},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 393, 2, 834},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 394, 17, 836},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 395, 19, 853},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 3, 872},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 397, 4, 875},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 398, 2, 879},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 402, 17, 881},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 403, 4, 898},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 2, 902},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 405, 3, 904},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 406, 2, 907},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 2, 909},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 911},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 409, 7, 913},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 410, 6, 920},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 411, 3, 926},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 3, 929},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 413, 2, 932},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 414, 2, 934},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 415, 2, 936},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 3, 938},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 417, 15, 941},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 418, 9, 956},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 419, 20, 965},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 420, 2, 985},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 421, 2, 987},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 422, 18, 989},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 423, 5, 1007},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 6, 1012},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 425, 2, 1018},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 426, 2, 1020},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 427, 14, 1022},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 428, 10, 1036},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 429, 2, 1046},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 430, 2, 1048},
- {"cvmx_lmc#_pll_bwctl" , CVMX_CSR_DB_TYPE_RSL, 64, 431, 3, 1050},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 9, 1053},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 433, 5, 1062},
- {"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 434, 5, 1067},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 435, 5, 1072},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 3, 1077},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 437, 3, 1080},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 438, 3, 1083},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 439, 5, 1086},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 441, 1, 1091},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 442, 10, 1092},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 450, 13, 1102},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 458, 4, 1115},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 459, 2, 1119},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 2, 1121},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 461, 10, 1123},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 462, 9, 1133},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 2, 1142},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 8, 1144},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 465, 4, 1152},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 466, 2, 1156},
- {"cvmx_mio_fus_unlock" , CVMX_CSR_DB_TYPE_RSL, 64, 467, 2, 1158},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 2, 1160},
- {"cvmx_mio_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 469, 2, 1162},
- {"cvmx_mio_pll_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 2, 1164},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 13, 1166},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 12, 1179},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 473, 3, 1191},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 474, 3, 1194},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 475, 2, 1197},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 477, 2, 1199},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 479, 2, 1201},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 481, 7, 1203},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 483, 2, 1210},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 485, 7, 1212},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 4, 1219},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 489, 8, 1223},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 9, 1231},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 493, 7, 1240},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 495, 9, 1247},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 497, 2, 1256},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 2, 1258},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 501, 4, 1260},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 2, 1264},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 505, 2, 1266},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 2, 1268},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 509, 4, 1270},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 511, 2, 1274},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 513, 2, 1276},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 2, 1278},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 2, 1280},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 2, 1282},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 521, 2, 1284},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 523, 6, 1286},
- {"cvmx_mpi_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 525, 13, 1292},
- {"cvmx_mpi_dat#" , CVMX_CSR_DB_TYPE_NCB, 64, 526, 2, 1305},
- {"cvmx_mpi_sts" , CVMX_CSR_DB_TYPE_NCB, 64, 535, 4, 1307},
- {"cvmx_mpi_tx" , CVMX_CSR_DB_TYPE_NCB, 64, 536, 6, 1311},
- {"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 537, 2, 1317},
- {"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 539, 2, 1319},
- {"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 541, 21, 1321},
- {"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 542, 3, 1342},
- {"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 544, 18, 1345},
- {"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 545, 2, 1363},
- {"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 546, 13, 1365},
- {"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 547, 3, 1378},
- {"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 548, 3, 1381},
- {"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 549, 3, 1384},
- {"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 550, 3, 1387},
- {"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 551, 2, 1390},
- {"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 552, 2, 1392},
- {"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 553, 9, 1394},
- {"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 554, 54, 1403},
- {"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 555, 54, 1457},
- {"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 556, 2, 1511},
- {"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 557, 2, 1513},
- {"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 558, 8, 1515},
- {"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 562, 1, 1523},
- {"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 563, 2, 1524},
- {"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 565, 23, 1526},
- {"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 566, 3, 1549},
- {"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 568, 2, 1552},
- {"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 570, 3, 1554},
- {"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 572, 3, 1557},
- {"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 574, 3, 1560},
- {"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 575, 4, 1563},
- {"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 576, 2, 1567},
- {"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 577, 13, 1569},
- {"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 578, 13, 1582},
- {"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 579, 3, 1595},
- {"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 580, 33, 1598},
- {"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 581, 2, 1631},
- {"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 583, 2, 1633},
- {"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 584, 5, 1635},
- {"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 616, 2, 1640},
- {"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 617, 24, 1642},
- {"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 618, 2, 1666},
- {"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 619, 7, 1668},
- {"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 620, 5, 1675},
- {"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 621, 1, 1680},
- {"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 622, 5, 1681},
- {"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 623, 1, 1686},
- {"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 624, 4, 1687},
- {"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 625, 2, 1691},
- {"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 626, 1, 1693},
- {"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 627, 2, 1694},
- {"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 628, 4, 1696},
- {"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 629, 2, 1700},
- {"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 630, 4, 1702},
- {"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 631, 16, 1706},
- {"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 632, 1, 1722},
- {"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 633, 1, 1723},
- {"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 634, 18, 1724},
- {"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 635, 1, 1742},
- {"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 636, 1, 1743},
- {"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 637, 7, 1744},
- {"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 638, 7, 1751},
- {"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 639, 13, 1758},
- {"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 640, 10, 1771},
- {"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 641, 10, 1781},
- {"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 642, 7, 1791},
- {"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 643, 2, 1798},
- {"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 644, 1, 1800},
- {"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 645, 2, 1801},
- {"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 646, 16, 1803},
- {"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 647, 2, 1819},
- {"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 649, 1, 1821},
- {"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 651, 1, 1822},
- {"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 653, 1, 1823},
- {"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 655, 1, 1824},
- {"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 657, 33, 1825},
- {"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 658, 33, 1858},
- {"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 659, 33, 1891},
- {"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 660, 33, 1924},
- {"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 661, 2, 1957},
- {"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 662, 2, 1959},
- {"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 664, 1, 1961},
- {"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 666, 1, 1962},
- {"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 668, 1, 1963},
- {"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 670, 3, 1964},
- {"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 671, 3, 1967},
- {"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 672, 3, 1970},
- {"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 673, 3, 1973},
- {"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 674, 2, 1976},
- {"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 675, 2, 1978},
- {"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 676, 4, 1980},
- {"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 677, 1, 1984},
- {"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 678, 4, 1985},
- {"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 679, 1, 1989},
- {"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 680, 2, 1990},
- {"cvmx_pcm#_dma_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 681, 12, 1992},
- {"cvmx_pcm#_int_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 685, 9, 2004},
- {"cvmx_pcm#_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 689, 9, 2013},
- {"cvmx_pcm#_rxaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 693, 2, 2022},
- {"cvmx_pcm#_rxcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 697, 2, 2024},
- {"cvmx_pcm#_rxmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 701, 1, 2026},
- {"cvmx_pcm#_rxmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 705, 1, 2027},
- {"cvmx_pcm#_rxmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 709, 1, 2028},
- {"cvmx_pcm#_rxmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 713, 1, 2029},
- {"cvmx_pcm#_rxmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 717, 1, 2030},
- {"cvmx_pcm#_rxmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 721, 1, 2031},
- {"cvmx_pcm#_rxmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 725, 1, 2032},
- {"cvmx_pcm#_rxmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 729, 1, 2033},
- {"cvmx_pcm#_rxstart" , CVMX_CSR_DB_TYPE_NCB, 64, 733, 3, 2034},
- {"cvmx_pcm#_tdm_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 737, 6, 2037},
- {"cvmx_pcm#_tdm_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 741, 1, 2043},
- {"cvmx_pcm#_txaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 745, 3, 2044},
- {"cvmx_pcm#_txcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 749, 2, 2047},
- {"cvmx_pcm#_txmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 753, 1, 2049},
- {"cvmx_pcm#_txmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 757, 1, 2050},
- {"cvmx_pcm#_txmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 761, 1, 2051},
- {"cvmx_pcm#_txmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 765, 1, 2052},
- {"cvmx_pcm#_txmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 769, 1, 2053},
- {"cvmx_pcm#_txmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 773, 1, 2054},
- {"cvmx_pcm#_txmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 777, 1, 2055},
- {"cvmx_pcm#_txmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 781, 1, 2056},
- {"cvmx_pcm#_txstart" , CVMX_CSR_DB_TYPE_NCB, 64, 785, 3, 2057},
- {"cvmx_pcm_clk#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 789, 12, 2060},
- {"cvmx_pcm_clk#_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 791, 1, 2072},
- {"cvmx_pcm_clk#_gen" , CVMX_CSR_DB_TYPE_NCB, 64, 793, 3, 2073},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 2, 2076},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 4, 2078},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 800, 8, 2082},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 801, 16, 2090},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 10, 2106},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 10, 2116},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 2, 2126},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 805, 16, 2128},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 25, 2144},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 815, 2, 2169},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 879, 2, 2171},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 887, 9, 2173},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 891, 2, 2182},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 892, 2, 2184},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 893, 2, 2186},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 898, 2, 2188},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 903, 2, 2190},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 908, 2, 2192},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 913, 2, 2194},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 918, 2, 2196},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 2, 2198},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 928, 2, 2200},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 933, 2, 2202},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 938, 2, 2204},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 943, 2, 2206},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 944, 2, 2208},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 949, 2, 2210},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 954, 2, 2212},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 959, 2, 2214},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 2, 2216},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 3, 2218},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 3, 2221},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 2, 2224},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 2226},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 4, 2228},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 5, 2232},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 4, 2237},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 1031, 5, 2241},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 1032, 1, 2246},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 1033, 4, 2247},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 1034, 2, 2251},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 5, 2253},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1036, 5, 2258},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 1037, 1, 2263},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 19, 2264},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 1039, 7, 2283},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 4, 2290},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 1041, 6, 2294},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 6, 2300},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 1043, 9, 2306},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 5, 2315},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1045, 13, 2320},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1046, 4, 2333},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1047, 2, 2337},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1048, 3, 2339},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1049, 5, 2342},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1050, 3, 2347},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 3, 2350},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1052, 2, 2353},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 3, 2355},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 1054, 12, 2358},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1055, 2, 2370},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 1056, 9, 2372},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1057, 3, 2381},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1058, 2, 2384},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1066, 2, 2386},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1067, 2, 2388},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 1068, 2, 2390},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 1069, 2, 2392},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 1071, 5, 2394},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1079, 10, 2399},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1087, 2, 2409},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1088, 2, 2411},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1089, 2, 2413},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1097, 3, 2415},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1098, 6, 2418},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1114, 5, 2424},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1115, 7, 2429},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1131, 2, 2436},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1147, 3, 2438},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1148, 5, 2441},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 1149, 8, 2446},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1150, 6, 2454},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1151, 2, 2460},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1152, 4, 2462},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1153, 4, 2466},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1154, 6, 2470},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1155, 3, 2476},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1156, 5, 2479},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 1157, 4, 2484},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 1158, 6, 2488},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1159, 4, 2494},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1160, 2, 2498},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1161, 4, 2500},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1162, 2, 2504},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1163, 3, 2506},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1164, 4, 2509},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1165, 12, 2513},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 1166, 3, 2525},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 2, 2528},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 2, 2530},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 17, 2532},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 12, 2549},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 6, 2561},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 5, 2567},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1173, 1, 2572},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1174, 2, 2573},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1175, 2, 2575},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1176, 17, 2577},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1177, 12, 2594},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1178, 6, 2606},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1179, 2, 2612},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1180, 2, 2614},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1181, 17, 2616},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1182, 12, 2633},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1183, 6, 2645},
- {"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 1184, 2, 2651},
- {"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1185, 2, 2653},
- {"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1186, 8, 2655},
- {"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1187, 11, 2663},
- {"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1188, 15, 2674},
- {"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1193, 8, 2689},
- {"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1198, 8, 2697},
- {"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1199, 4, 2705},
- {"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1204, 15, 2709},
- {"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1209, 6, 2724},
- {"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1214, 6, 2730},
- {"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1215, 4, 2736},
- {"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1220, 2, 2740},
- {"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1224, 6, 2742},
- {"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 1225, 4, 2748},
- {"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 1226, 1, 2752},
- {"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 1227, 1, 2753},
- {"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 1228, 1, 2754},
- {"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1229, 7, 2755},
- {"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 1230, 1, 2762},
- {"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 1231, 14, 2763},
- {"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 1232, 10, 2777},
- {"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 1233, 12, 2787},
- {"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1234, 32, 2799},
- {"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1235, 32, 2831},
- {"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1236, 2, 2863},
- {"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1237, 4, 2865},
- {"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1238, 13, 2869},
- {"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 1239, 10, 2882},
- {"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1240, 10, 2892},
- {"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1241, 2, 2902},
- {"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 1242, 6, 2904},
- {"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 1243, 5, 2910},
- {"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 1244, 6, 2915},
- {"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 1245, 5, 2921},
- {"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 1246, 1, 2926},
- {"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1247, 13, 2927},
- {"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 1248, 2, 2940},
- {"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1249, 2, 2942},
- {"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 1250, 11, 2944},
- {"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1258, 3, 2955},
- {"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1259, 12, 2958},
- {"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 1267, 12, 2970},
- {"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 1275, 6, 2982},
- {"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1283, 4, 2988},
- {"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 1291, 2, 2992},
- {"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 1292, 2, 2994},
- {"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 1293, 15, 2996},
- {"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1294, 2, 3011},
- {"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1295, 3, 3013},
- {"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 1296, 1, 3016},
- {"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1304, 6, 3017},
- {"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1305, 4, 3023},
- {"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1306, 15, 3027},
- {"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1307, 6, 3042},
- {"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1308, 2, 3048},
- {"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1309, 2, 3050},
- {"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1310, 2, 3052},
- {"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1311, 2, 3054},
- {"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1312, 2, 3056},
- {"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1313, 2, 3058},
- {"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1314, 2, 3060},
- {"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1315, 2, 3062},
- {"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1316, 2, 3064},
- {"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1317, 2, 3066},
- {"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1318, 2, 3068},
- {"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1319, 2, 3070},
- {"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1320, 2, 3072},
- {"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1321, 2, 3074},
- {"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1322, 2, 3076},
- {"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1323, 2, 3078},
- {"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 1324, 7, 3080},
- {"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 39, 3087},
- {"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1326, 39, 3126},
- {"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 22, 3165},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1328, 3, 3187},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 5, 3190},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1330, 3, 3195},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 1331, 6, 3198},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1332, 2, 3204},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1333, 2, 3206},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 2, 3208},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"ASX0_GMII_RX_CLK_SET" , 0x11800b0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX0_GMII_RX_DAT_SET" , 0x11800b0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX0_INT_EN" , 0x11800b0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX0_INT_REG" , 0x11800b0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX0_PRT_LOOP" , 0x11800b0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX0_RX_CLK_SET000" , 0x11800b0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX0_RX_CLK_SET001" , 0x11800b0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX0_RX_CLK_SET002" , 0x11800b0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX0_RX_PRT_EN" , 0x11800b0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_TX_CLK_SET000" , 0x11800b0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX0_TX_CLK_SET001" , 0x11800b0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX0_TX_CLK_SET002" , 0x11800b0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX0_TX_COMP_BYP" , 0x11800b0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_TX_HI_WATER000" , 0x11800b0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX0_TX_HI_WATER001" , 0x11800b0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX0_TX_HI_WATER002" , 0x11800b0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX0_TX_PRT_EN" , 0x11800b0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 11},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"DBG_DATA" , 0x11f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"DFA_BST0" , 0x11800300007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"DFA_BST1" , 0x11800300007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"DFA_DDR2_ADDR" , 0x1180030000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"DFA_DDR2_BUS" , 0x1180030000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"DFA_DDR2_CFG" , 0x1180030000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"DFA_DDR2_COMP" , 0x1180030000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"DFA_DDR2_EMRS" , 0x1180030000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"DFA_DDR2_FCNT" , 0x1180030000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"DFA_DDR2_MRS" , 0x1180030000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"DFA_DDR2_OPT" , 0x1180030000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"DFA_DDR2_PLL" , 0x1180030000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"DFA_DDR2_TMG" , 0x1180030000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 46},
- {"DFA_ECLKCFG" , 0x1180030000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX_TX_STATUS" , 0x11800080007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_TX001_CLK" , 0x1180008000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"GPIO_BOOT_ENA" , 0x10700000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"GPIO_DBG_ENA" , 0x10700000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"GPIO_XBIT_CFG16" , 0x1070000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"GPIO_XBIT_CFG17" , 0x1070000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"GPIO_XBIT_CFG18" , 0x1070000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"GPIO_XBIT_CFG19" , 0x1070000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"GPIO_XBIT_CFG20" , 0x1070000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"GPIO_XBIT_CFG21" , 0x1070000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"GPIO_XBIT_CFG22" , 0x1070000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"GPIO_XBIT_CFG23" , 0x1070000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 186},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"LMC0_PLL_BWCTL" , 0x1180088000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"MIO_FUS_UNLOCK" , 0x1180000001578ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"MIO_PLL_CTL" , 0x1180000001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"MIO_PLL_SETTING" , 0x1180000001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"MPI_CFG" , 0x1070000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 285},
- {"MPI_DAT0" , 0x1070000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"MPI_DAT1" , 0x1070000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"MPI_DAT2" , 0x1070000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"MPI_DAT3" , 0x1070000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"MPI_DAT4" , 0x10700000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"MPI_DAT5" , 0x10700000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"MPI_DAT6" , 0x10700000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"MPI_DAT7" , 0x10700000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"MPI_DAT8" , 0x10700000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"MPI_STS" , 0x1070000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 287},
- {"MPI_TX" , 0x1070000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 288},
- {"NPI_BASE_ADDR_INPUT0" , 0x11f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"NPI_BASE_ADDR_INPUT1" , 0x11f0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"NPI_BASE_ADDR_OUTPUT0" , 0x11f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"NPI_BASE_ADDR_OUTPUT1" , 0x11f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"NPI_BIST_STATUS" , 0x11f00000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
- {"NPI_BUFF_SIZE_OUTPUT0" , 0x11f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"NPI_BUFF_SIZE_OUTPUT1" , 0x11f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"NPI_CTL_STATUS" , 0x11f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
- {"NPI_DBG_SELECT" , 0x11f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 294},
- {"NPI_DMA_CONTROL" , 0x11f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"NPI_DMA_HIGHP_COUNTS" , 0x11f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
- {"NPI_DMA_HIGHP_NADDR" , 0x11f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 297},
- {"NPI_DMA_LOWP_COUNTS" , 0x11f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 298},
- {"NPI_DMA_LOWP_NADDR" , 0x11f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
- {"NPI_HIGHP_DBELL" , 0x11f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
- {"NPI_HIGHP_IBUFF_SADDR" , 0x11f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
- {"NPI_INPUT_CONTROL" , 0x11f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 302},
- {"NPI_INT_ENB" , 0x11f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 303},
- {"NPI_INT_SUM" , 0x11f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 304},
- {"NPI_LOWP_DBELL" , 0x11f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 305},
- {"NPI_LOWP_IBUFF_SADDR" , 0x11f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 306},
- {"NPI_MEM_ACCESS_SUBID3" , 0x11f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
- {"NPI_MEM_ACCESS_SUBID4" , 0x11f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
- {"NPI_MEM_ACCESS_SUBID5" , 0x11f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
- {"NPI_MEM_ACCESS_SUBID6" , 0x11f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
- {"NPI_MSI_RCV" , 0x11f0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 308},
- {"NPI_NUM_DESC_OUTPUT0" , 0x11f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 309},
- {"NPI_NUM_DESC_OUTPUT1" , 0x11f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 309},
- {"NPI_OUTPUT_CONTROL" , 0x11f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 310},
- {"NPI_P0_DBPAIR_ADDR" , 0x11f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 311},
- {"NPI_P1_DBPAIR_ADDR" , 0x11f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 311},
- {"NPI_P0_INSTR_ADDR" , 0x11f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 312},
- {"NPI_P1_INSTR_ADDR" , 0x11f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 312},
- {"NPI_P0_INSTR_CNTS" , 0x11f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 313},
- {"NPI_P1_INSTR_CNTS" , 0x11f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 313},
- {"NPI_P0_PAIR_CNTS" , 0x11f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 314},
- {"NPI_P1_PAIR_CNTS" , 0x11f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 314},
- {"NPI_PCI_BURST_SIZE" , 0x11f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 315},
- {"NPI_PCI_INT_ARB_CFG" , 0x11f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
- {"NPI_PCI_READ_CMD" , 0x11f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"NPI_PORT32_INSTR_HDR" , 0x11f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"NPI_PORT33_INSTR_HDR" , 0x11f0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"NPI_PORT_BP_CONTROL" , 0x11f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"NPI_RSL_INT_BLOCKS" , 0x11f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"NPI_SIZE_INPUT0" , 0x11f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"NPI_SIZE_INPUT1" , 0x11f0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"NPI_WIN_READ_TO" , 0x11f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"PCI_BAR1_INDEX0" , 0x11f0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX1" , 0x11f0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX2" , 0x11f0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX3" , 0x11f000000110cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX4" , 0x11f0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX5" , 0x11f0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX6" , 0x11f0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX7" , 0x11f000000111cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX8" , 0x11f0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX9" , 0x11f0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX10" , 0x11f0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX11" , 0x11f000000112cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX12" , 0x11f0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX13" , 0x11f0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX14" , 0x11f0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX15" , 0x11f000000113cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX16" , 0x11f0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX17" , 0x11f0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX18" , 0x11f0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX19" , 0x11f000000114cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX20" , 0x11f0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX21" , 0x11f0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX22" , 0x11f0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX23" , 0x11f000000115cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX24" , 0x11f0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX25" , 0x11f0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX26" , 0x11f0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX27" , 0x11f000000116cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX28" , 0x11f0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX29" , 0x11f0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX30" , 0x11f0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_BAR1_INDEX31" , 0x11f000000117cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
- {"PCI_CFG00" , 0x11f0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 325},
- {"PCI_CFG01" , 0x11f0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 326},
- {"PCI_CFG02" , 0x11f0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 327},
- {"PCI_CFG03" , 0x11f000000180cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 328},
- {"PCI_CFG04" , 0x11f0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 329},
- {"PCI_CFG05" , 0x11f0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 330},
- {"PCI_CFG06" , 0x11f0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 331},
- {"PCI_CFG07" , 0x11f000000181cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 332},
- {"PCI_CFG08" , 0x11f0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 333},
- {"PCI_CFG09" , 0x11f0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 334},
- {"PCI_CFG10" , 0x11f0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 335},
- {"PCI_CFG11" , 0x11f000000182cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 336},
- {"PCI_CFG12" , 0x11f0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 337},
- {"PCI_CFG13" , 0x11f0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 338},
- {"PCI_CFG15" , 0x11f000000183cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 339},
- {"PCI_CFG16" , 0x11f0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 340},
- {"PCI_CFG17" , 0x11f0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 341},
- {"PCI_CFG18" , 0x11f0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 342},
- {"PCI_CFG19" , 0x11f000000184cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 343},
- {"PCI_CFG20" , 0x11f0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 344},
- {"PCI_CFG21" , 0x11f0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 345},
- {"PCI_CFG22" , 0x11f0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 346},
- {"PCI_CFG56" , 0x11f00000018e0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 347},
- {"PCI_CFG57" , 0x11f00000018e4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 348},
- {"PCI_CFG58" , 0x11f00000018e8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 349},
- {"PCI_CFG59" , 0x11f00000018ecull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 350},
- {"PCI_CFG60" , 0x11f00000018f0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 351},
- {"PCI_CFG61" , 0x11f00000018f4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 352},
- {"PCI_CFG62" , 0x11f00000018f8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 353},
- {"PCI_CFG63" , 0x11f00000018fcull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 354},
- {"PCI_CTL_STATUS_2" , 0x11f000000118cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 355},
- {"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 356},
- {"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 356},
- {"PCI_DMA_CNT0" , 0xa0ull, CVMX_CSR_DB_TYPE_PCI, 32, 357},
- {"PCI_DMA_CNT1" , 0xa8ull, CVMX_CSR_DB_TYPE_PCI, 32, 357},
- {"PCI_DMA_INT_LEV0" , 0xa4ull, CVMX_CSR_DB_TYPE_PCI, 32, 358},
- {"PCI_DMA_INT_LEV1" , 0xacull, CVMX_CSR_DB_TYPE_PCI, 32, 358},
- {"PCI_DMA_TIME0" , 0xb0ull, CVMX_CSR_DB_TYPE_PCI, 32, 359},
- {"PCI_DMA_TIME1" , 0xb4ull, CVMX_CSR_DB_TYPE_PCI, 32, 359},
- {"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 360},
- {"PCI_INSTR_COUNT1" , 0x8cull, CVMX_CSR_DB_TYPE_PCI, 32, 360},
- {"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 361},
- {"PCI_INT_ENB2" , 0x11f00000011a0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 362},
- {"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 363},
- {"PCI_INT_SUM2" , 0x11f0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 364},
- {"PCI_MSI_RCV" , 0xf0ull, CVMX_CSR_DB_TYPE_PCI, 32, 365},
- {"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 366},
- {"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 366},
- {"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 367},
- {"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 367},
- {"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 368},
- {"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 368},
- {"PCI_PKTS_SENT_TIME0" , 0x4cull, CVMX_CSR_DB_TYPE_PCI, 32, 369},
- {"PCI_PKTS_SENT_TIME1" , 0x5cull, CVMX_CSR_DB_TYPE_PCI, 32, 369},
- {"PCI_READ_CMD_6" , 0x11f0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 370},
- {"PCI_READ_CMD_C" , 0x11f0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 371},
- {"PCI_READ_CMD_E" , 0x11f0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 372},
- {"PCI_READ_TIMEOUT" , 0x11f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"PCI_SCM_REG" , 0x11f00000011a8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 374},
- {"PCI_TSR_REG" , 0x11f00000011b0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 375},
- {"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 376},
- {"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 377},
- {"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 378},
- {"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 379},
- {"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 380},
- {"PCM0_DMA_CFG" , 0x1070000010018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM1_DMA_CFG" , 0x1070000014018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM2_DMA_CFG" , 0x1070000018018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM3_DMA_CFG" , 0x107000001c018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM0_INT_ENA" , 0x1070000010020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM1_INT_ENA" , 0x1070000014020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM2_INT_ENA" , 0x1070000018020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM3_INT_ENA" , 0x107000001c020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM0_INT_SUM" , 0x1070000010028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM1_INT_SUM" , 0x1070000014028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM2_INT_SUM" , 0x1070000018028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM3_INT_SUM" , 0x107000001c028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM0_RXADDR" , 0x1070000010068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM1_RXADDR" , 0x1070000014068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM2_RXADDR" , 0x1070000018068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM3_RXADDR" , 0x107000001c068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM0_RXCNT" , 0x1070000010060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM1_RXCNT" , 0x1070000014060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM2_RXCNT" , 0x1070000018060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM3_RXCNT" , 0x107000001c060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM0_RXMSK0" , 0x10700000100c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM1_RXMSK0" , 0x10700000140c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM2_RXMSK0" , 0x10700000180c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM3_RXMSK0" , 0x107000001c0c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM0_RXMSK1" , 0x10700000100c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM1_RXMSK1" , 0x10700000140c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM2_RXMSK1" , 0x10700000180c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM3_RXMSK1" , 0x107000001c0c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM0_RXMSK2" , 0x10700000100d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM1_RXMSK2" , 0x10700000140d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM2_RXMSK2" , 0x10700000180d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM3_RXMSK2" , 0x107000001c0d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM0_RXMSK3" , 0x10700000100d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"PCM1_RXMSK3" , 0x10700000140d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"PCM2_RXMSK3" , 0x10700000180d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"PCM3_RXMSK3" , 0x107000001c0d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"PCM0_RXMSK4" , 0x10700000100e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"PCM1_RXMSK4" , 0x10700000140e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"PCM2_RXMSK4" , 0x10700000180e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"PCM3_RXMSK4" , 0x107000001c0e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"PCM0_RXMSK5" , 0x10700000100e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"PCM1_RXMSK5" , 0x10700000140e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"PCM2_RXMSK5" , 0x10700000180e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"PCM3_RXMSK5" , 0x107000001c0e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"PCM0_RXMSK6" , 0x10700000100f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
- {"PCM1_RXMSK6" , 0x10700000140f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
- {"PCM2_RXMSK6" , 0x10700000180f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
- {"PCM3_RXMSK6" , 0x107000001c0f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
- {"PCM0_RXMSK7" , 0x10700000100f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
- {"PCM1_RXMSK7" , 0x10700000140f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
- {"PCM2_RXMSK7" , 0x10700000180f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
- {"PCM3_RXMSK7" , 0x107000001c0f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
- {"PCM0_RXSTART" , 0x1070000010058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
- {"PCM1_RXSTART" , 0x1070000014058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
- {"PCM2_RXSTART" , 0x1070000018058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
- {"PCM3_RXSTART" , 0x107000001c058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
- {"PCM0_TDM_CFG" , 0x1070000010010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
- {"PCM1_TDM_CFG" , 0x1070000014010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
- {"PCM2_TDM_CFG" , 0x1070000018010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
- {"PCM3_TDM_CFG" , 0x107000001c010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
- {"PCM0_TDM_DBG" , 0x1070000010030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
- {"PCM1_TDM_DBG" , 0x1070000014030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
- {"PCM2_TDM_DBG" , 0x1070000018030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
- {"PCM3_TDM_DBG" , 0x107000001c030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
- {"PCM0_TXADDR" , 0x1070000010050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
- {"PCM1_TXADDR" , 0x1070000014050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
- {"PCM2_TXADDR" , 0x1070000018050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
- {"PCM3_TXADDR" , 0x107000001c050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
- {"PCM0_TXCNT" , 0x1070000010048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
- {"PCM1_TXCNT" , 0x1070000014048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
- {"PCM2_TXCNT" , 0x1070000018048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
- {"PCM3_TXCNT" , 0x107000001c048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
- {"PCM0_TXMSK0" , 0x1070000010080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
- {"PCM1_TXMSK0" , 0x1070000014080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
- {"PCM2_TXMSK0" , 0x1070000018080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
- {"PCM3_TXMSK0" , 0x107000001c080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
- {"PCM0_TXMSK1" , 0x1070000010088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"PCM1_TXMSK1" , 0x1070000014088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"PCM2_TXMSK1" , 0x1070000018088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"PCM3_TXMSK1" , 0x107000001c088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"PCM0_TXMSK2" , 0x1070000010090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"PCM1_TXMSK2" , 0x1070000014090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"PCM2_TXMSK2" , 0x1070000018090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"PCM3_TXMSK2" , 0x107000001c090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"PCM0_TXMSK3" , 0x1070000010098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"PCM1_TXMSK3" , 0x1070000014098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"PCM2_TXMSK3" , 0x1070000018098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"PCM3_TXMSK3" , 0x107000001c098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"PCM0_TXMSK4" , 0x10700000100a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"PCM1_TXMSK4" , 0x10700000140a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"PCM2_TXMSK4" , 0x10700000180a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"PCM3_TXMSK4" , 0x107000001c0a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"PCM0_TXMSK5" , 0x10700000100a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"PCM1_TXMSK5" , 0x10700000140a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"PCM2_TXMSK5" , 0x10700000180a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"PCM3_TXMSK5" , 0x107000001c0a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"PCM0_TXMSK6" , 0x10700000100b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
- {"PCM1_TXMSK6" , 0x10700000140b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
- {"PCM2_TXMSK6" , 0x10700000180b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
- {"PCM3_TXMSK6" , 0x107000001c0b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
- {"PCM0_TXMSK7" , 0x10700000100b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
- {"PCM1_TXMSK7" , 0x10700000140b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
- {"PCM2_TXMSK7" , 0x10700000180b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
- {"PCM3_TXMSK7" , 0x107000001c0b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
- {"PCM0_TXSTART" , 0x1070000010040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
- {"PCM1_TXSTART" , 0x1070000014040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
- {"PCM2_TXSTART" , 0x1070000018040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
- {"PCM3_TXSTART" , 0x107000001c040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
- {"PCM_CLK0_CFG" , 0x1070000010000ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
- {"PCM_CLK1_CFG" , 0x1070000014000ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
- {"PCM_CLK0_DBG" , 0x1070000010038ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
- {"PCM_CLK1_DBG" , 0x1070000014038ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
- {"PCM_CLK0_GEN" , 0x1070000010008ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
- {"PCM_CLK1_GEN" , 0x1070000014008ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 471},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 472},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 474},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 476},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 477},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 478},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 482},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"USBC0_DAINT" , 0x16f0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
- {"USBC0_DAINTMSK" , 0x16f001000081cull, CVMX_CSR_DB_TYPE_NCB, 32, 528},
- {"USBC0_DCFG" , 0x16f0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
- {"USBC0_DCTL" , 0x16f0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
- {"USBC0_DIEPCTL000" , 0x16f0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_DIEPCTL001" , 0x16f0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_DIEPCTL002" , 0x16f0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_DIEPCTL003" , 0x16f0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_DIEPCTL004" , 0x16f0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_DIEPINT000" , 0x16f0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_DIEPINT001" , 0x16f0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_DIEPINT002" , 0x16f0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_DIEPINT003" , 0x16f0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_DIEPINT004" , 0x16f0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_DIEPMSK" , 0x16f0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 533},
- {"USBC0_DIEPTSIZ000" , 0x16f0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
- {"USBC0_DIEPTSIZ001" , 0x16f0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
- {"USBC0_DIEPTSIZ002" , 0x16f0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
- {"USBC0_DIEPTSIZ003" , 0x16f0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
- {"USBC0_DIEPTSIZ004" , 0x16f0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
- {"USBC0_DOEPCTL000" , 0x16f0010000b00ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
- {"USBC0_DOEPCTL001" , 0x16f0010000b20ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
- {"USBC0_DOEPCTL002" , 0x16f0010000b40ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
- {"USBC0_DOEPCTL003" , 0x16f0010000b60ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
- {"USBC0_DOEPCTL004" , 0x16f0010000b80ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
- {"USBC0_DOEPINT000" , 0x16f0010000b08ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
- {"USBC0_DOEPINT001" , 0x16f0010000b28ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
- {"USBC0_DOEPINT002" , 0x16f0010000b48ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
- {"USBC0_DOEPINT003" , 0x16f0010000b68ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
- {"USBC0_DOEPINT004" , 0x16f0010000b88ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
- {"USBC0_DOEPMSK" , 0x16f0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 537},
- {"USBC0_DOEPTSIZ000" , 0x16f0010000b10ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_DOEPTSIZ001" , 0x16f0010000b30ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_DOEPTSIZ002" , 0x16f0010000b50ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_DOEPTSIZ003" , 0x16f0010000b70ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_DOEPTSIZ004" , 0x16f0010000b90ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_DPTXFSIZ001" , 0x16f0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
- {"USBC0_DPTXFSIZ002" , 0x16f0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
- {"USBC0_DPTXFSIZ003" , 0x16f001000010cull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
- {"USBC0_DPTXFSIZ004" , 0x16f0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
- {"USBC0_DSTS" , 0x16f0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 540},
- {"USBC0_DTKNQR1" , 0x16f0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 541},
- {"USBC0_DTKNQR2" , 0x16f0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 542},
- {"USBC0_DTKNQR3" , 0x16f0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 543},
- {"USBC0_DTKNQR4" , 0x16f0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 544},
- {"USBC0_GAHBCFG" , 0x16f0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
- {"USBC0_GHWCFG1" , 0x16f0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 546},
- {"USBC0_GHWCFG2" , 0x16f0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
- {"USBC0_GHWCFG3" , 0x16f001000004cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
- {"USBC0_GHWCFG4" , 0x16f0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
- {"USBC0_GINTMSK" , 0x16f0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
- {"USBC0_GINTSTS" , 0x16f0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 551},
- {"USBC0_GNPTXFSIZ" , 0x16f0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 552},
- {"USBC0_GNPTXSTS" , 0x16f001000002cull, CVMX_CSR_DB_TYPE_NCB, 32, 553},
- {"USBC0_GOTGCTL" , 0x16f0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 554},
- {"USBC0_GOTGINT" , 0x16f0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 555},
- {"USBC0_GRSTCTL" , 0x16f0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
- {"USBC0_GRXFSIZ" , 0x16f0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 557},
- {"USBC0_GRXSTSPD" , 0x16f0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 558},
- {"USBC0_GRXSTSPH" , 0x16f0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 559},
- {"USBC0_GRXSTSRD" , 0x16f001004001cull, CVMX_CSR_DB_TYPE_NCB, 32, 560},
- {"USBC0_GRXSTSRH" , 0x16f001000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 561},
- {"USBC0_GSNPSID" , 0x16f0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 562},
- {"USBC0_GUSBCFG" , 0x16f001000000cull, CVMX_CSR_DB_TYPE_NCB, 32, 563},
- {"USBC0_HAINT" , 0x16f0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 564},
- {"USBC0_HAINTMSK" , 0x16f0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 565},
- {"USBC0_HCCHAR000" , 0x16f0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
- {"USBC0_HCCHAR001" , 0x16f0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
- {"USBC0_HCCHAR002" , 0x16f0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
- {"USBC0_HCCHAR003" , 0x16f0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
- {"USBC0_HCCHAR004" , 0x16f0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
- {"USBC0_HCCHAR005" , 0x16f00100005a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
- {"USBC0_HCCHAR006" , 0x16f00100005c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
- {"USBC0_HCCHAR007" , 0x16f00100005e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
- {"USBC0_HCFG" , 0x16f0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 567},
- {"USBC0_HCINT000" , 0x16f0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
- {"USBC0_HCINT001" , 0x16f0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
- {"USBC0_HCINT002" , 0x16f0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
- {"USBC0_HCINT003" , 0x16f0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
- {"USBC0_HCINT004" , 0x16f0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
- {"USBC0_HCINT005" , 0x16f00100005a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
- {"USBC0_HCINT006" , 0x16f00100005c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
- {"USBC0_HCINT007" , 0x16f00100005e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
- {"USBC0_HCINTMSK000" , 0x16f001000050cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
- {"USBC0_HCINTMSK001" , 0x16f001000052cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
- {"USBC0_HCINTMSK002" , 0x16f001000054cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
- {"USBC0_HCINTMSK003" , 0x16f001000056cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
- {"USBC0_HCINTMSK004" , 0x16f001000058cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
- {"USBC0_HCINTMSK005" , 0x16f00100005acull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
- {"USBC0_HCINTMSK006" , 0x16f00100005ccull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
- {"USBC0_HCINTMSK007" , 0x16f00100005ecull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
- {"USBC0_HCSPLT000" , 0x16f0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
- {"USBC0_HCSPLT001" , 0x16f0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
- {"USBC0_HCSPLT002" , 0x16f0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
- {"USBC0_HCSPLT003" , 0x16f0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
- {"USBC0_HCSPLT004" , 0x16f0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
- {"USBC0_HCSPLT005" , 0x16f00100005a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
- {"USBC0_HCSPLT006" , 0x16f00100005c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
- {"USBC0_HCSPLT007" , 0x16f00100005e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
- {"USBC0_HCTSIZ000" , 0x16f0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
- {"USBC0_HCTSIZ001" , 0x16f0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
- {"USBC0_HCTSIZ002" , 0x16f0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
- {"USBC0_HCTSIZ003" , 0x16f0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
- {"USBC0_HCTSIZ004" , 0x16f0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
- {"USBC0_HCTSIZ005" , 0x16f00100005b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
- {"USBC0_HCTSIZ006" , 0x16f00100005d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
- {"USBC0_HCTSIZ007" , 0x16f00100005f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
- {"USBC0_HFIR" , 0x16f0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 572},
- {"USBC0_HFNUM" , 0x16f0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 573},
- {"USBC0_HPRT" , 0x16f0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 574},
- {"USBC0_HPTXFSIZ" , 0x16f0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 575},
- {"USBC0_HPTXSTS" , 0x16f0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 576},
- {"USBC0_NPTXDFIFO000" , 0x16f0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
- {"USBC0_NPTXDFIFO001" , 0x16f0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
- {"USBC0_NPTXDFIFO002" , 0x16f0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
- {"USBC0_NPTXDFIFO003" , 0x16f0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
- {"USBC0_NPTXDFIFO004" , 0x16f0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
- {"USBC0_NPTXDFIFO005" , 0x16f0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
- {"USBC0_NPTXDFIFO006" , 0x16f0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
- {"USBC0_NPTXDFIFO007" , 0x16f0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
- {"USBC0_PCGCCTL" , 0x16f0010000e00ull, CVMX_CSR_DB_TYPE_NCB, 32, 578},
- {"USBN0_BIST_STATUS" , 0x11800680007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
- {"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
- {"USBN0_CTL_STATUS" , 0x16f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 581},
- {"USBN0_DMA0_INB_CHN0" , 0x16f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 582},
- {"USBN0_DMA0_INB_CHN1" , 0x16f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"USBN0_DMA0_INB_CHN2" , 0x16f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"USBN0_DMA0_INB_CHN3" , 0x16f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"USBN0_DMA0_INB_CHN4" , 0x16f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 586},
- {"USBN0_DMA0_INB_CHN5" , 0x16f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 587},
- {"USBN0_DMA0_INB_CHN6" , 0x16f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"USBN0_DMA0_INB_CHN7" , 0x16f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"USBN0_DMA0_OUTB_CHN0" , 0x16f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"USBN0_DMA0_OUTB_CHN1" , 0x16f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 591},
- {"USBN0_DMA0_OUTB_CHN2" , 0x16f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"USBN0_DMA0_OUTB_CHN3" , 0x16f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"USBN0_DMA0_OUTB_CHN4" , 0x16f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"USBN0_DMA0_OUTB_CHN5" , 0x16f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 595},
- {"USBN0_DMA0_OUTB_CHN6" , 0x16f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 596},
- {"USBN0_DMA0_OUTB_CHN7" , 0x16f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
- {"USBN0_DMA_TEST" , 0x16f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 598},
- {"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 599},
- {"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 600},
- {"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 601},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 606},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"SETTING" , 0, 5, 0, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 0, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 1, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 0, 3, 2, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_3" , 3, 1, 2, "RAZ", 1, 1, 0, 0},
- {"TXPOP" , 4, 3, 2, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
- {"TXPSH" , 8, 3, 2, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_11_63" , 11, 53, 2, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 0, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 3, "RAZ", 1, 1, 0, 0},
- {"TXPOP" , 4, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 3, "RAZ", 1, 1, 0, 0},
- {"TXPSH" , 8, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 3, "RAZ", 1, 1, 0, 0},
- {"INT_LOOP" , 0, 3, 4, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 4, "RAZ", 1, 1, 0, 0},
- {"EXT_LOOP" , 4, 3, 4, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 4, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 5, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 5, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 3, 6, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 6, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 7, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 7, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 8, "R/W", 0, 0, 8ull, 8ull},
- {"PCTL" , 4, 4, 8, "R/W", 0, 0, 8ull, 8ull},
- {"BYPASS" , 8, 1, 8, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 8, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 3, 9, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 9, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 3, 10, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 10, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 4, 11, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 11, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 2, 12, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 12, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 2, 13, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 13, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 14, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 14, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 15, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 15, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 15, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 15, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 15, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 15, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 2, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 16, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 17, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 17, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 17, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 17, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 17, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 17, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 17, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 17, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 17, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 17, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 17, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 17, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 17, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 17, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 52, 4, 17, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 17, "RO", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 17, "RO", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 17, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 17, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 2, 18, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 18, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 19, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 19, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 20, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 20, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 2, 21, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 21, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 22, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 22, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 2, 23, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 23, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 24, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 25, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 1, 25, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 25, "RAZ", 1, 1, 0, 0},
- {"SOFT_BIST" , 0, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 26, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 27, "R/W", 0, 0, 1ull, 0ull},
- {"NPI" , 1, 1, 27, "R/W", 0, 0, 0ull, 0ull},
- {"HOST64" , 2, 1, 27, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 27, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 28, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 28, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 29, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 29, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 30, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 30, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 30, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 30, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 30, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 30, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 30, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 31, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 31, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 31, "RO", 1, 1, 0, 0},
- {"RESERVED_23_27" , 23, 5, 31, "RAZ", 1, 1, 0, 0},
- {"PLL_MUL" , 28, 3, 31, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 31, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 16, 32, "RO", 0, 0, 0ull, 0ull},
- {"RDF" , 16, 16, 32, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 32, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_0_17" , 0, 18, 33, "RAZ", 0, 0, 0ull, 0ull},
- {"CRF" , 18, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"DRF" , 19, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"GFU" , 20, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"IFU" , 21, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 22, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 33, "RAZ", 0, 0, 0ull, 0ull},
- {"DBELL" , 0, 20, 34, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 34, "RAZ", 1, 1, 0, 0},
- {"NUM_COLS" , 0, 2, 35, "R/W", 0, 0, 1ull, 1ull},
- {"NUM_COLROWS" , 2, 3, 35, "R/W", 0, 0, 1ull, 1ull},
- {"RNK_LO" , 5, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_RNKS" , 6, 2, 35, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 8, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 35, "RAZ", 1, 1, 0, 0},
- {"BUS_CNT" , 0, 47, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 36, "RAZ", 1, 1, 0, 0},
- {"PRTENA" , 0, 1, 37, "R/W", 0, 0, 0ull, 1ull},
- {"INIT" , 1, 1, 37, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH" , 2, 1, 37, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 3, 1, 37, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_LAT" , 4, 2, 37, "R/W", 0, 0, 1ull, 1ull},
- {"SILO_HC" , 6, 1, 37, "R/W", 0, 0, 0ull, 0ull},
- {"SILO_QC" , 7, 1, 37, "R/W", 0, 0, 0ull, 0ull},
- {"RNK_MSK" , 8, 4, 37, "R/W", 0, 0, 0ull, 15ull},
- {"TSKW" , 12, 2, 37, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 37, "RAZ", 0, 0, 0ull, 0ull},
- {"REF_INT" , 16, 13, 37, "R/W", 0, 0, 780ull, 780ull},
- {"RESERVED_29_31" , 29, 3, 37, "RAZ", 1, 1, 0, 0},
- {"FPIP" , 32, 3, 37, "R/W", 0, 0, 0ull, 0ull},
- {"MRS_PGM" , 35, 1, 37, "R/W", 0, 0, 0ull, 0ull},
- {"TRFC" , 36, 5, 37, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_41_63" , 41, 23, 37, "RAZ", 1, 1, 0, 0},
- {"COMP_BYPASS" , 0, 1, 38, "R/W", 0, 0, 0ull, 1ull},
- {"NCTL_CSR" , 1, 4, 38, "R/W", 0, 1, 13ull, 0},
- {"PCTL_CSR" , 5, 4, 38, "R/W", 0, 1, 13ull, 0},
- {"RESERVED_9_55" , 9, 47, 38, "RAZ", 1, 1, 0, 0},
- {"DFA__NCTL" , 56, 4, 38, "RO", 1, 1, 0, 0},
- {"DFA__PCTL" , 60, 4, 38, "RO", 1, 1, 0, 0},
- {"EMRS1" , 0, 15, 39, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 39, "RAZ", 1, 1, 0, 0},
- {"EMRS1_OCD" , 16, 15, 39, "R/W", 0, 0, 896ull, 896ull},
- {"RESERVED_31_63" , 31, 33, 39, "RAZ", 1, 1, 0, 0},
- {"FCYC_CNT" , 0, 47, 40, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 40, "RAZ", 1, 1, 0, 0},
- {"MRS_DLL" , 0, 15, 41, "R/W", 0, 0, 1858ull, 1858ull},
- {"RESERVED_15_15" , 15, 1, 41, "RAZ", 1, 1, 0, 0},
- {"MRS" , 16, 15, 41, "R/W", 0, 0, 1602ull, 1602ull},
- {"RESERVED_31_63" , 31, 33, 41, "RAZ", 1, 1, 0, 0},
- {"MAX_WRITE_BATCH" , 0, 5, 42, "R/W", 0, 0, 31ull, 31ull},
- {"MAX_READ_BATCH" , 5, 5, 42, "R/W", 0, 0, 31ull, 31ull},
- {"RESERVED_10_63" , 10, 54, 42, "RAZ", 1, 1, 0, 0},
- {"PLL_INIT" , 0, 1, 43, "R/W", 0, 0, 0ull, 1ull},
- {"PLL_BYPASS" , 1, 1, 43, "R/W", 0, 0, 0ull, 0ull},
- {"PLL_RATIO" , 2, 5, 43, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 43, "RAZ", 1, 1, 0, 0},
- {"PLL_DIV2" , 8, 1, 43, "R/W", 0, 0, 0ull, 0ull},
- {"BW_UPD" , 9, 1, 43, "R/W", 0, 0, 0ull, 0ull},
- {"BW_CTL" , 10, 4, 43, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 14, 1, 43, "R/W", 0, 0, 0ull, 1ull},
- {"DLL_BYP" , 15, 1, 43, "R/W", 0, 1, 0ull, 0},
- {"DLL_SETTING" , 16, 5, 43, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_26" , 21, 6, 43, "RAZ", 1, 1, 0, 0},
- {"SETTING90" , 27, 5, 43, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_46" , 32, 15, 43, "RAZ", 1, 1, 0, 0},
- {"PLL_SETTING" , 47, 17, 43, "RO", 0, 0, 0ull, 0ull},
- {"DDR2T" , 0, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"TMRD" , 1, 2, 44, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 3, 3, 44, "R/W", 0, 0, 4ull, 4ull},
- {"POCAS" , 6, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 7, 3, 44, "R/W", 0, 0, 0ull, 0ull},
- {"TRCD" , 10, 4, 44, "R/W", 0, 0, 2ull, 2ull},
- {"TRRD" , 14, 3, 44, "R/W", 0, 0, 2ull, 2ull},
- {"TRAS" , 17, 5, 44, "R/W", 0, 0, 10ull, 10ull},
- {"TRP" , 22, 4, 44, "R/W", 0, 0, 4ull, 4ull},
- {"TWR" , 26, 3, 44, "R/W", 0, 0, 3ull, 3ull},
- {"TWTR" , 29, 4, 44, "R/W", 0, 0, 2ull, 2ull},
- {"TFAW" , 33, 5, 44, "R/W", 0, 0, 9ull, 9ull},
- {"R2R_SLOT" , 38, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"DIC" , 39, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"DQSN_ENA" , 40, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_RTT" , 41, 2, 44, "R/W", 0, 0, 2ull, 2ull},
- {"CTR_RST" , 43, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"CAVMIPO" , 44, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_CLR" , 45, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"FCNT_MODE" , 46, 1, 44, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 44, "RAZ", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 9, 45, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 45, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 45, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_20_63" , 20, 44, 45, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 46, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 31, 46, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 46, "RAZ", 1, 1, 0, 0},
- {"DFA_FRSTN" , 0, 1, 47, "R/W", 0, 0, 0ull, 1ull},
- {"MAXBNK" , 1, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"DTECLKDIS" , 2, 1, 47, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 47, "RAZ", 0, 0, 0ull, 9ull},
- {"SARB" , 8, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"IMODE" , 9, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 10, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 11, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"DTMODE" , 12, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"DCMODE" , 13, 1, 47, "R/W", 0, 0, 0ull, 0ull},
- {"SBDLCK" , 14, 1, 47, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 47, "RAZ", 1, 1, 0, 0},
- {"SBDNUM" , 16, 3, 47, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 47, "RAZ", 1, 1, 0, 0},
- {"CP2ECCENA" , 0, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"CP2SBE" , 1, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2DBE" , 2, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2SBINA" , 3, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"CP2DBINA" , 4, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"CP2SYN" , 5, 8, 48, "RO", 0, 0, 0ull, 0ull},
- {"DTEECCENA" , 13, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"DTESBE" , 14, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTEDBE" , 15, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTESBINA" , 16, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"DTEDBINA" , 17, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"DTESYN" , 18, 7, 48, "RO", 0, 0, 0ull, 0ull},
- {"DTEPARENA" , 25, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"DTEPERR" , 26, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTEPINA" , 27, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"CP2PARENA" , 28, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"CP2PERR" , 29, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2PINA" , 30, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"DBLOVF" , 31, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBLINA" , 32, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 48, "RAZ", 1, 1, 0, 0},
- {"MADDR" , 0, 25, 49, "RO", 0, 0, 0ull, 0ull},
- {"BNUM" , 25, 3, 49, "RO", 0, 0, 0ull, 0ull},
- {"PNUM" , 28, 1, 49, "RO", 0, 0, 0ull, 0ull},
- {"FSRC" , 29, 2, 49, "RO", 0, 0, 0ull, 0ull},
- {"FDST" , 31, 9, 49, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 49, "RAZ", 1, 1, 0, 0},
- {"SBD0" , 0, 64, 50, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 51, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 52, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 53, "RO", 1, 1, 0, 0},
- {"FDR" , 0, 1, 54, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 54, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 54, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 54, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 54, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 54, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 55, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 55, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 55, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 56, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 56, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 57, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 58, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 58, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 59, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 59, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 60, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 60, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 60, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 61, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 61, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 61, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 62, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 62, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 63, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 63, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 3, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_21" , 5, 17, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 3, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_25" , 25, 1, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 64, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 10, 65, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 65, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 66, "R/W", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 66, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 66, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 67, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 67, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 68, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 68, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 68, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 68, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_63" , 4, 60, 68, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 69, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 70, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 71, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 72, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 73, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 74, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 75, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 75, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 76, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 76, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 76, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 76, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 77, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 77, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 78, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 78, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 78, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 78, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 78, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 78, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 78, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 78, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 78, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 78, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 78, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 79, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 79, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 79, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 79, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 79, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 79, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_FREE" , 6, 1, 79, "R/W", 0, 0, 0ull, 0ull},
- {"VLAN_LEN" , 7, 1, 79, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 79, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 80, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 80, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 81, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 81, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 82, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 82, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 83, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 84, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 85, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 85, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 86, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 86, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 86, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 86, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 87, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 87, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 88, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 88, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 89, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 89, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 90, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 90, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 91, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 91, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 92, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 92, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 93, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 93, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 94, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 94, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 95, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 95, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 96, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 96, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 97, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 97, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 98, "R/W", 1, 1, 0, 0},
- {"RESERVED_6_63" , 6, 58, 98, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 99, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 99, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 100, "R/W", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 100, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 3, 101, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_15" , 3, 13, 101, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 3, 101, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 101, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 102, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_3_63" , 3, 61, 102, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 3, 103, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 103, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 3, 103, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 103, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 104, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 105, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 106, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 106, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 106, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 106, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 106, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 107, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 107, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 108, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 108, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 109, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 109, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 109, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 110, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 110, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 111, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 111, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 112, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 112, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 113, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 113, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 114, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 114, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 115, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 115, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 116, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 116, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 117, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 117, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 118, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 118, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 119, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 119, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 120, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 120, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 121, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 121, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 122, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 122, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 123, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 123, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 124, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 124, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 125, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 125, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 126, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 126, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 127, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 7, 128, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_7_63" , 7, 57, 128, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 3, 129, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 129, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 130, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 130, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 3, 131, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_3_63" , 3, 61, 131, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 132, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 132, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 132, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 133, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 3, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 133, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 3, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 133, "RAZ", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 3, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 133, "RAZ", 0, 0, 0ull, 0ull},
- {"PKO_NXA" , 0, 1, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 134, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 3, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 134, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 3, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 134, "RAZ", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 3, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 134, "RAZ", 0, 0, 0ull, 0ull},
- {"JAM" , 0, 8, 135, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 135, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 136, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 136, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 3, 137, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 137, "RAZ", 0, 0, 0ull, 0ull},
- {"BP" , 4, 3, 137, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 137, "RAZ", 0, 0, 0ull, 0ull},
- {"EN" , 8, 3, 137, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 137, "RAZ", 0, 0, 0ull, 0ull},
- {"DMAC" , 0, 48, 138, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 138, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 139, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 139, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 140, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_5_63" , 5, 59, 140, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 141, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 141, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 141, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 142, "RAZ", 1, 1, 0, 0},
- {"BOOT_ENA" , 8, 4, 142, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 142, "RAZ", 1, 1, 0, 0},
- {"DBG_ENA" , 0, 21, 143, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 143, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 144, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 144, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 24, 145, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 145, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 24, 146, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 146, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 24, 147, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 147, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 148, "RAZ", 1, 1, 0, 0},
- {"FIL_CNT" , 4, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 148, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 149, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 149, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 150, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 150, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 150, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 150, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 151, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 151, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 151, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 152, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 152, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 152, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 152, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 152, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 153, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 153, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 153, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 153, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 153, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 154, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 155, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 156, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 157, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 158, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 158, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 158, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 158, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 158, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 159, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 159, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 159, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 159, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 159, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 160, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 161, "R/W", 0, 1, 0ull, 0},
- {"PORT" , 0, 6, 162, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 162, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 163, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 163, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 164, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 164, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 165, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 165, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 166, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 167, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 167, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 168, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 169, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 169, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 169, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 170, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 170, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 170, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 170, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 170, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 170, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 171, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 172, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 173, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 173, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 174, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 174, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 175, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 175, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 176, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 176, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 3, 177, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 177, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 177, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 177, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 177, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 177, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 178, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 178, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 178, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 178, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_44_63" , 44, 20, 178, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 179, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 179, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 179, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 179, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 179, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 179, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 180, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 180, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 180, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 180, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 180, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 180, "RO", 0, 0, 8ull, 8ull},
- {"RESERVED_61_63" , 61, 3, 180, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 181, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 181, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 182, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 182, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 183, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 183, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 183, "R/W", 0, 0, 0ull, 0ull},
- {"PRB_CON" , 0, 32, 184, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 184, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 184, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 184, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 185, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 185, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 185, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 3, 186, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_3_63" , 3, 61, 186, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 187, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 187, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 188, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 188, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 189, "RO", 0, 0, 0ull, 0ull},
- {"STIN_MSK" , 4, 1, 189, "RO", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 189, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 10, 189, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 189, "RAZ", 0, 0, 0ull, 0ull},
- {"WLB_MSK" , 19, 4, 189, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 189, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 5, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_8" , 5, 4, 190, "RAZ", 0, 0, 0ull, 0ull},
- {"VAB_VWCF" , 9, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"LRF" , 10, 2, 190, "RO", 0, 0, 0ull, 0ull},
- {"VWDF" , 12, 4, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 190, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 191, "RAZ", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 191, "RAZ", 0, 0, 0ull, 0ull},
- {"RMDF" , 8, 4, 191, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 191, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 192, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 192, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 192, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 192, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 192, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 192, "RAZ", 1, 1, 0, 0},
- {"L2T" , 0, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 2, 193, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_5" , 5, 1, 193, "RAZ", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_9" , 7, 3, 193, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 3, 193, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 193, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 194, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 194, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 194, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 195, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 195, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 195, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 196, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 196, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 197, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 197, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 3, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_17" , 17, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
- {"SET" , 18, 2, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 3, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 197, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 198, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 198, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 10, 199, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 10, 17, 199, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 199, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 3, 200, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_3_3" , 3, 1, 200, "RAZ", 0, 0, 0ull, 0ull},
- {"STPARTDIS" , 4, 1, 200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 200, "RAZ", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 201, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 201, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 202, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 4, 203, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 203, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK1" , 8, 4, 203, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 203, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 4, 204, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 204, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 205, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 205, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 206, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 207, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 207, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 208, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 208, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 209, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 209, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 209, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 209, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 10, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 210, "RAZ", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 2, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_13" , 13, 1, 210, "RAZ", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 210, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 211, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 211, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 211, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 212, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 212, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 213, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 214, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 215, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 215, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 216, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_128K" , 34, 1, 216, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 216, "RO", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 217, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 217, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 217, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 217, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 9, 217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 217, "RAZ", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 2, 217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 217, "RAZ", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 217, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 217, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_28_63" , 28, 36, 217, "RAZ", 0, 0, 0ull, 0ull},
- {"PCTL_DAT" , 0, 4, 218, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CMD" , 4, 4, 218, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CLK" , 8, 4, 218, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 218, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 218, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CMD" , 20, 4, 218, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CLK" , 24, 4, 218, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 218, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 218, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 219, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 219, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 219, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 219, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 219, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 219, "R/W", 0, 0, 0ull, 1ull},
- {"MODE32B" , 10, 1, 219, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 11, 1, 219, "R/W", 0, 0, 1ull, 0ull},
- {"INORDER_MRF" , 12, 1, 219, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 219, "RAZ", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 219, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 219, "R/W", 0, 1, 0ull, 0},
- {"PLL_BYPASS" , 16, 1, 219, "R/W", 0, 0, 1ull, 1ull},
- {"PLL_DIV2" , 17, 1, 219, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 219, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 219, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 219, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 219, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 219, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 219, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 220, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 221, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 222, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 222, "RAZ", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 222, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 222, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 222, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 222, "R/W", 0, 0, 2ull, 2ull},
- {"SILO_HC" , 21, 1, 222, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 222, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 222, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 222, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 222, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 222, "RAZ", 0, 0, 0ull, 0ull},
- {"MRDSYN0" , 0, 8, 223, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 223, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 223, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 223, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 223, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 224, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 224, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 224, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 224, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 224, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 224, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 225, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 226, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 227, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 227, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 227, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 227, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 227, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 227, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 227, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 227, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 227, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 227, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 227, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 228, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 228, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 228, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 228, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 228, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 228, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 228, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 228, "R/W", 0, 0, 2ull, 2ull},
- {"COMP_BYPASS" , 31, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 228, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 229, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 230, "RAZ", 1, 1, 0, 0},
- {"BWCTL" , 0, 4, 231, "R/W", 0, 0, 0ull, 0ull},
- {"BWUPD" , 4, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 231, "RAZ", 1, 1, 0, 0},
- {"RODT_LO0" , 0, 4, 232, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO1" , 4, 4, 232, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO2" , 8, 4, 232, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO3" , 12, 4, 232, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI0" , 16, 4, 232, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI1" , 20, 4, 232, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI2" , 24, 4, 232, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI3" , 28, 4, 232, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 232, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 233, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D0_R1" , 8, 8, 233, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R0" , 16, 8, 233, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R1" , 24, 8, 233, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 233, "RAZ", 0, 0, 0ull, 0ull},
- {"WODT_D2_R0" , 0, 8, 234, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R1" , 8, 8, 234, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R0" , 16, 8, 234, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R1" , 24, 8, 234, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 234, "RAZ", 0, 0, 0ull, 0ull},
- {"NCBI" , 0, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 2, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_1" , 3, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 235, "RAZ", 1, 1, 0, 0},
- {"ADR_ERR" , 0, 1, 236, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 236, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 236, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 237, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 237, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 237, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 238, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 238, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 238, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 239, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 239, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 239, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 239, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 239, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 240, "R/W", 1, 1, 0, 0},
- {"BASE" , 0, 16, 241, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 241, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 241, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 241, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 241, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 241, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 241, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 241, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 241, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_63" , 37, 27, 241, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 242, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 242, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 242, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 242, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 242, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 242, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 242, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 242, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 242, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 242, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 242, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 242, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 242, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 243, "R/W", 0, 0, 26ull, 26ull},
- {"RESERVED_6_7" , 6, 2, 243, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 243, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 243, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 244, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 244, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 245, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 245, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 2, 246, "RO", 1, 1, 0, 0},
- {"RESERVED_2_11" , 2, 10, 246, "RAZ", 1, 1, 0, 0},
- {"PLL_OFF" , 12, 4, 246, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 246, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 246, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 246, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 246, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 246, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 246, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 246, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 247, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 247, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 247, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 247, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 247, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 247, "RO", 1, 1, 0, 0},
- {"ZIP_CRIP" , 29, 2, 247, "RO", 1, 1, 0, 0},
- {"PLL_DIV4" , 31, 1, 247, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 247, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 248, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 248, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 7, 249, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 249, "RAZ", 1, 1, 0, 0},
- {"EFUSE" , 8, 1, 249, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 249, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 249, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 249, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 249, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 249, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 250, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 14, 14, 250, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 28, 14, 250, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 250, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 251, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 251, "RAZ", 1, 1, 0, 0},
- {"KEY" , 0, 24, 252, "R/W", 0, 0, 0ull, 5071723ull},
- {"RESERVED_24_63" , 24, 40, 252, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 10, 253, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 253, "RAZ", 1, 1, 0, 0},
- {"BW_CTL" , 0, 5, 254, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 254, "RAZ", 0, 0, 0ull, 0ull},
- {"SETTING" , 0, 17, 255, "RO", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 255, "RAZ", 0, 0, 0ull, 0ull},
- {"ST_INT" , 0, 1, 256, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 256, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 256, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 256, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 256, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 256, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 256, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 256, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 257, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 257, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 257, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 257, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 257, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 257, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 257, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 257, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 257, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 257, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 257, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 257, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 258, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 258, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 258, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 259, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 259, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 259, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 260, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 260, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 261, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 261, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 262, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 262, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 263, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 263, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 263, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 263, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 263, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 263, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 263, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 264, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 264, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 265, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 265, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 265, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 265, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 265, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 265, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 265, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 266, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 266, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 266, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 266, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 267, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 267, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 267, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 267, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 267, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 267, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 267, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 267, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 268, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 268, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 268, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 268, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 268, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 268, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 268, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 268, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 268, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 269, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 269, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 269, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 269, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 269, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 269, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 269, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 270, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 270, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 270, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 270, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 270, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 270, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 270, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 270, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 270, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 271, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 271, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 272, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 272, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 273, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 273, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 273, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 273, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 274, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 274, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 275, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 275, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 276, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 276, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 277, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 277, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 277, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 277, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 278, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 278, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 279, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 280, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 281, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 281, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 282, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 282, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 283, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 283, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 284, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 284, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 284, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 284, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 284, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 284, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"IDLELO" , 1, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_CONT" , 2, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"WIREOR" , 3, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 4, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"INT_ENA" , 5, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CSENA" , 6, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"CSHI" , 7, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"IDLECLKS" , 8, 2, 285, "R/W", 0, 0, 0ull, 0ull},
- {"TRITX" , 10, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 285, "RAZ", 1, 1, 0, 0},
- {"CLKDIV" , 16, 13, 285, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 285, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 8, 286, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 286, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 287, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 287, "RAZ", 1, 1, 0, 0},
- {"RXNUM" , 8, 5, 287, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 287, "RAZ", 1, 1, 0, 0},
- {"TOTNUM" , 0, 5, 288, "WO", 1, 0, 0, 2ull},
- {"RESERVED_5_7" , 5, 3, 288, "RAZ", 1, 1, 0, 0},
- {"TXNUM" , 8, 5, 288, "WO", 1, 0, 0, 1ull},
- {"RESERVED_13_15" , 13, 3, 288, "RAZ", 1, 1, 0, 0},
- {"LEAVECS" , 16, 1, 288, "WO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 288, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 289, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 289, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 290, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 290, "R/W", 0, 1, 0ull, 0},
- {"DPI_BS" , 0, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"PDF_BS" , 1, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"DOB_BS" , 2, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"NUS_BS" , 3, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"POS_BS" , 4, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"POF3_BS" , 5, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"POF2_BS" , 6, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"POF1_BS" , 7, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"POF0_BS" , 8, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"PIG_BS" , 9, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"PGF_BS" , 10, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"RDNL_BS" , 11, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"PCAD_BS" , 12, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"PCAC_BS" , 13, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"RDN_BS" , 14, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"PCN_BS" , 15, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"PCNC_BS" , 16, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"RDP_BS" , 17, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"DIF_BS" , 18, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"CSR_BS" , 19, 1, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 291, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 292, "R/W", 0, 1, 1024ull, 0},
- {"ISIZE" , 16, 7, 292, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 292, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 293, "R/W", 0, 0, 0ull, 50ull},
- {"RESERVED_10_31" , 10, 22, 293, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_WORD" , 32, 5, 293, "R/W", 0, 0, 2ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 293, "RAZ", 0, 0, 0ull, 0ull},
- {"WAIT_COM" , 40, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_WDIS" , 41, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"INS0_64B" , 42, 1, 293, "R/W", 0, 1, 0ull, 0},
- {"INS1_64B" , 43, 1, 293, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_45" , 44, 2, 293, "RAZ", 0, 0, 0ull, 0ull},
- {"INS0_ENB" , 46, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"INS1_ENB" , 47, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_48_49" , 48, 2, 293, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT0_ENB" , 50, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"OUT1_ENB" , 51, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_52_53" , 52, 2, 293, "RAZ", 0, 0, 0ull, 0ull},
- {"DIS_PNIW" , 54, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"CHIP_REV" , 55, 8, 293, "RO", 1, 1, 0, 0},
- {"RESERVED_63_63" , 63, 1, 293, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 294, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 294, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 0, 14, 295, "R/W", 0, 1, 0ull, 0},
- {"LP_ENB" , 14, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"HP_ENB" , 15, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"O_MODE" , 16, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 17, 2, 295, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 19, 1, 295, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 20, 1, 295, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 21, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 22, 3, 295, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 25, 9, 295, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 34, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 35, 1, 295, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 295, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 296, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 296, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 296, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 297, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 297, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 297, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 298, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 298, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 298, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 299, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 299, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 299, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 300, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 300, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 301, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 301, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 302, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 302, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 302, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 302, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 302, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_RSL" , 2, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PO0_2SML" , 3, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PO1_2SML" , 4, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
- {"I0_RTOUT" , 7, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"I1_RTOUT" , 8, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_10" , 9, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
- {"I0_OVERF" , 11, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"I1_OVERF" , 12, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_RTOUT" , 15, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"P1_RTOUT" , 16, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_18" , 17, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_PERR" , 19, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PERR" , 20, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_22" , 21, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
- {"G0_RTOUT" , 23, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"G1_RTOUT" , 24, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_25_26" , 25, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_PPERR" , 27, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PPERR" , 28, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_29_30" , 29, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_PTOUT" , 31, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PTOUT" , 32, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_33_34" , 33, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
- {"I0_PPERR" , 35, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"I1_PPERR" , 36, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_37_38" , 37, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
- {"WIN_RTO" , 39, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"P_DPERR" , 40, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 41, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_S_E" , 42, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_A_F" , 43, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_S_E" , 44, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_A_F" , 45, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_S_E" , 46, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_A_F" , 47, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_S_E" , 48, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_A_F" , 49, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"COM_S_E" , 50, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"COM_A_F" , 51, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_S_E" , 52, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_A_F" , 53, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RWX_S_E" , 54, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RDX_S_E" , 55, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_E" , 56, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_F" , 57, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_E" , 58, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_F" , 59, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_S_E" , 60, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_A_F" , 61, 1, 303, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_62_63" , 62, 2, 303, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_RSL" , 2, 1, 304, "RO", 0, 0, 0ull, 0ull},
- {"PO0_2SML" , 3, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO1_2SML" , 4, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"I0_RTOUT" , 7, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_RTOUT" , 8, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_10" , 9, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"I0_OVERF" , 11, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_OVERF" , 12, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_14" , 13, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_RTOUT" , 15, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_RTOUT" , 16, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_18" , 17, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_PERR" , 19, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PERR" , 20, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_22" , 21, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"G0_RTOUT" , 23, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"G1_RTOUT" , 24, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_26" , 25, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_PPERR" , 27, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PPERR" , 28, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_30" , 29, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_PTOUT" , 31, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PTOUT" , 32, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_33_34" , 33, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"I0_PPERR" , 35, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_PPERR" , 36, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_38" , 37, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"WIN_RTO" , 39, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DPERR" , 40, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 41, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_S_E" , 42, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_A_F" , 43, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_S_E" , 44, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_A_F" , 45, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_S_E" , 46, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_A_F" , 47, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_S_E" , 48, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_A_F" , 49, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_S_E" , 50, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_A_F" , 51, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_S_E" , 52, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_A_F" , 53, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RWX_S_E" , 54, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDX_S_E" , 55, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_E" , 56, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_F" , 57, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_E" , 58, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_F" , 59, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_S_E" , 60, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_A_F" , 61, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 304, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 305, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 305, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 306, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 306, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 28, 307, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 28, 1, 307, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 29, 1, 307, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 30, 1, 307, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 31, 1, 307, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 32, 2, 307, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 34, 2, 307, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 307, "RAZ", 1, 1, 0, 0},
- {"INT_VEC" , 0, 64, 308, "R/W1C", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 32, 309, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 309, "RAZ", 1, 1, 0, 0},
- {"ROR_SL0" , 0, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL0" , 1, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL0" , 2, 2, 310, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL1" , 4, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL1" , 5, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL1" , 6, 2, 310, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 310, "RAZ", 0, 0, 0ull, 0ull},
- {"IPTR_O0" , 16, 1, 310, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O1" , 17, 1, 310, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_18_23" , 18, 6, 310, "RAZ", 0, 0, 0ull, 0ull},
- {"O0_CSRM" , 24, 1, 310, "R/W", 0, 0, 0ull, 1ull},
- {"O1_CSRM" , 25, 1, 310, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_26_27" , 26, 2, 310, "RAZ", 0, 0, 0ull, 0ull},
- {"O0_RO" , 28, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"O0_NS" , 29, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"O0_ES" , 30, 2, 310, "R/W", 0, 1, 0ull, 0},
- {"O1_RO" , 32, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"O1_NS" , 33, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"O1_ES" , 34, 2, 310, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_43" , 36, 8, 310, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_BMODE" , 44, 1, 310, "R/W", 0, 0, 0ull, 0ull},
- {"P1_BMODE" , 45, 1, 310, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 310, "RAZ", 0, 0, 0ull, 0ull},
- {"NADDR" , 0, 61, 311, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 2, 311, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_63_63" , 63, 1, 311, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 312, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 3, 312, "RO", 0, 0, 0ull, 0ull},
- {"AVAIL" , 0, 32, 313, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 6, 313, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 313, "RAZ", 1, 1, 0, 0},
- {"AVAIL" , 0, 32, 314, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 5, 314, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 314, "RAZ", 1, 1, 0, 0},
- {"RD_BRST" , 0, 7, 315, "R/W", 0, 0, 17ull, 64ull},
- {"WR_BRST" , 7, 7, 315, "R/W", 0, 0, 16ull, 64ull},
- {"RESERVED_14_63" , 14, 50, 315, "RAZ", 1, 1, 0, 0},
- {"PARK_DEV" , 0, 3, 316, "R/W", 0, 1, 0ull, 0},
- {"PARK_MOD" , 3, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"EN" , 4, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 316, "RAZ", 1, 1, 0, 0},
- {"CMD_SIZE" , 0, 11, 317, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_11_63" , 11, 53, 317, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 318, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 318, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 318, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 318, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 318, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 318, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 318, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 318, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 318, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 318, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 318, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 318, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 318, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 319, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 319, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 319, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 319, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 319, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 319, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 319, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 319, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 319, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 319, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 319, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 319, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 319, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 4, 320, "R/W", 0, 0, 15ull, 15ull},
- {"BP_ON" , 4, 4, 320, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 320, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"NPI" , 3, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_8" , 8, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_14" , 14, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_15" , 15, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"LMC" , 17, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_21" , 21, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"ASX0" , 22, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"ASX1" , 23, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_24" , 24, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_25" , 25, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_26" , 26, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_27" , 27, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_28" , 28, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_29" , 29, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RINT_31" , 31, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 321, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 32, 322, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 322, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 323, "R/W", 0, 0, 0ull, 131072ull},
- {"RESERVED_32_63" , 32, 32, 323, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 324, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 324, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 324, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 324, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 324, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 325, "RO", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 325, "RO", 0, 0, 32ull, 32ull},
- {"ISAE" , 0, 1, 326, "RO", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 326, "R/W", 0, 0, 0ull, 1ull},
- {"ME" , 2, 1, 326, "R/W", 0, 0, 0ull, 1ull},
- {"SCSE" , 3, 1, 326, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 326, "RO", 0, 0, 0ull, 0ull},
- {"PEE" , 6, 1, 326, "R/W", 0, 0, 0ull, 1ull},
- {"ADS" , 7, 1, 326, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 326, "R/W", 0, 0, 0ull, 1ull},
- {"FBBE" , 9, 1, 326, "R/W", 0, 0, 0ull, 1ull},
- {"I_DIS" , 10, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 326, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 326, "RO", 0, 0, 0ull, 0ull},
- {"CLE" , 20, 1, 326, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 326, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_22" , 22, 1, 326, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 326, "RO", 0, 1, 1ull, 0},
- {"MDPE" , 24, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 326, "RO", 0, 0, 1ull, 1ull},
- {"STA" , 27, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 327, "RO", 0, 0, 0ull, 0ull},
- {"CC" , 8, 24, 327, "RO", 0, 0, 1048576ull, 1048576ull},
- {"CLS" , 0, 8, 328, "R/W", 0, 1, 0ull, 0},
- {"LT" , 8, 8, 328, "R/W", 0, 0, 0ull, 64ull},
- {"HT" , 16, 8, 328, "RO", 0, 0, 0ull, 0ull},
- {"BCOD" , 24, 4, 328, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_29" , 28, 2, 328, "RAZ", 1, 1, 0, 0},
- {"BRB" , 30, 1, 328, "R/W", 0, 0, 0ull, 0ull},
- {"BCAP" , 31, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 329, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 329, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 329, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 8, 329, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 12, 20, 329, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 330, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 331, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 331, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 331, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 23, 331, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 27, 5, 331, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 332, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 333, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 333, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 333, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 28, 333, "RO", 0, 0, 0ull, 0ull},
- {"HBASEZ" , 0, 7, 334, "RO", 0, 0, 0ull, 0ull},
- {"HBASE" , 7, 25, 334, "R/W", 0, 1, 0ull, 0},
- {"CISP" , 0, 32, 335, "RO", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 336, "RO", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 336, "RO", 0, 0, 1ull, 1ull},
- {"ERBAR_EN" , 0, 1, 337, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_10" , 1, 10, 337, "RAZ", 1, 1, 0, 0},
- {"ERBARZ" , 11, 5, 337, "RO", 0, 0, 0ull, 0ull},
- {"ERBAR" , 16, 16, 337, "R/W", 0, 1, 0ull, 0},
- {"CP" , 0, 8, 338, "RO", 0, 0, 224ull, 224ull},
- {"RESERVED_8_31" , 8, 24, 338, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 339, "R/W", 0, 1, 0ull, 0},
- {"INTA" , 8, 8, 339, "RO", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 339, "RO", 0, 0, 64ull, 64ull},
- {"ML" , 24, 8, 339, "RO", 0, 0, 64ull, 64ull},
- {"MLTD" , 0, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"TSWC" , 1, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 340, "RAZ", 1, 1, 0, 0},
- {"DPPMR" , 3, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"PBE" , 4, 12, 340, "R/W", 0, 0, 0ull, 0ull},
- {"TILT" , 16, 4, 340, "R/W", 0, 0, 0ull, 0ull},
- {"TSLTE" , 20, 3, 340, "R/W", 0, 0, 0ull, 0ull},
- {"TMAE" , 23, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"TWTAE" , 24, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEN" , 25, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEI" , 26, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"TRTAE" , 27, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"TRDRS" , 28, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"RDSATI" , 29, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"TRDARD" , 30, 1, 340, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRDNPR" , 31, 1, 340, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSCME" , 0, 32, 341, "R/W1C", 0, 1, 0ull, 0},
- {"TDSRPS" , 0, 32, 342, "R/W1C", 0, 0, 0ull, 0ull},
- {"TDOMC" , 0, 5, 343, "R/W", 0, 0, 1ull, 1ull},
- {"TIDOMC" , 5, 1, 343, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 343, "RAZ", 1, 1, 0, 0},
- {"TIBDE" , 7, 1, 343, "R/W", 0, 0, 0ull, 0ull},
- {"TIBCD" , 8, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_10" , 9, 2, 343, "RAZ", 1, 1, 0, 0},
- {"TMAPES" , 11, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMDPES" , 12, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMSE" , 13, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMEI" , 14, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"TECI" , 15, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"TMES" , 16, 8, 343, "RO", 0, 0, 0ull, 0ull},
- {"MDRRMC" , 24, 3, 343, "R/W", 0, 0, 2ull, 2ull},
- {"MDRIMC" , 27, 1, 343, "R/W", 0, 0, 0ull, 0ull},
- {"MDRE" , 28, 1, 343, "R/W", 0, 0, 0ull, 0ull},
- {"MDWE" , 29, 1, 343, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCI" , 30, 1, 343, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCM" , 31, 1, 343, "R/W", 0, 0, 1ull, 1ull},
- {"MDSP" , 0, 32, 344, "R/W1C", 0, 1, 0ull, 0},
- {"SCMRE" , 0, 32, 345, "R/W1C", 0, 1, 0ull, 0},
- {"MTTV" , 0, 8, 346, "R/W", 0, 0, 0ull, 0ull},
- {"MRV" , 8, 8, 346, "R/W", 0, 0, 0ull, 255ull},
- {"MTTA" , 16, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRA" , 17, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLUSH" , 18, 1, 346, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_19_24" , 19, 6, 346, "RAZ", 1, 1, 0, 0},
- {"MAC" , 25, 7, 346, "R/W", 0, 0, 0ull, 0ull},
- {"PXCID" , 0, 8, 347, "RO", 0, 0, 7ull, 7ull},
- {"NCP" , 8, 8, 347, "RO", 0, 0, 232ull, 232ull},
- {"DPERE" , 16, 1, 347, "R/W", 0, 0, 0ull, 0ull},
- {"ROE" , 17, 1, 347, "R/W", 0, 0, 1ull, 1ull},
- {"MMBC" , 18, 2, 347, "R/W", 0, 0, 0ull, 0ull},
- {"MOST" , 20, 3, 347, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_23_31" , 23, 9, 347, "RAZ", 1, 1, 0, 0},
- {"FN" , 0, 3, 348, "RO", 0, 0, 0ull, 0ull},
- {"DN" , 3, 5, 348, "RO", 0, 0, 31ull, 31ull},
- {"BN" , 8, 8, 348, "RO", 0, 1, 17ull, 0},
- {"W64" , 16, 1, 348, "RO", 0, 0, 1ull, 1ull},
- {"M133" , 17, 1, 348, "RO", 0, 0, 1ull, 1ull},
- {"SCD" , 18, 1, 348, "R/W1C", 0, 1, 0ull, 0},
- {"USC" , 19, 1, 348, "R/W1C", 0, 1, 0ull, 0},
- {"DC" , 20, 1, 348, "RO", 0, 0, 0ull, 0ull},
- {"MMRBCD" , 21, 2, 348, "RO", 0, 0, 2ull, 2ull},
- {"MOSTD" , 23, 3, 348, "RO", 0, 0, 3ull, 3ull},
- {"MCRSD" , 26, 3, 348, "RO", 0, 0, 7ull, 7ull},
- {"SCEMR" , 29, 1, 348, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 348, "RAZ", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 349, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 349, "RO", 0, 0, 240ull, 240ull},
- {"PCIMIV" , 16, 3, 349, "RO", 0, 0, 2ull, 2ull},
- {"PMEC" , 19, 1, 349, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 349, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 349, "RO", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 349, "RO", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 349, "RO", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 349, "RO", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 349, "RO", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 350, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 350, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 350, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 350, "R/W", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 350, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 350, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 350, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEN" , 23, 1, 350, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 350, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 351, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 351, "RO", 0, 0, 0ull, 0ull},
- {"MSIEN" , 16, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 351, "RO", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 351, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 351, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 351, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 352, "RAZ", 1, 1, 0, 0},
- {"MSI31T2" , 2, 30, 352, "R/W", 0, 1, 0ull, 0},
- {"MSI" , 0, 32, 353, "R/W", 0, 1, 0ull, 0},
- {"MSIMD" , 0, 16, 354, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 354, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 355, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 355, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 355, "R/W", 0, 0, 0ull, 1ull},
- {"TSR_HWM" , 4, 3, 355, "R/W", 0, 1, 1ull, 0},
- {"PMO_FPC" , 7, 3, 355, "R/W", 0, 0, 0ull, 0ull},
- {"PMO_AMOD" , 10, 1, 355, "R/W", 0, 0, 0ull, 0ull},
- {"B12_BIST" , 11, 1, 355, "RO", 0, 0, 0ull, 0ull},
- {"AP_64AD" , 12, 1, 355, "RO", 0, 1, 0ull, 0},
- {"AP_PCIX" , 13, 1, 355, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_14" , 14, 1, 355, "RAZ", 0, 0, 0ull, 0ull},
- {"EN_WFILT" , 15, 1, 355, "R/W", 0, 0, 0ull, 1ull},
- {"SCM" , 16, 1, 355, "RO", 0, 1, 0ull, 0},
- {"SCMTYP" , 17, 1, 355, "RO", 0, 1, 0ull, 0},
- {"BAR2PRES" , 18, 1, 355, "R/W", 1, 1, 0, 0},
- {"ERST_N" , 19, 1, 355, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_20_31" , 20, 12, 355, "RAZ", 1, 1, 0, 0},
- {"INC_VAL" , 0, 16, 356, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 356, "RAZ", 1, 1, 0, 0},
- {"DMA_CNT" , 0, 32, 357, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 358, "R/W", 0, 1, 0ull, 0},
- {"DMA_TIME" , 0, 32, 359, "R/W", 0, 1, 0ull, 0},
- {"ICNT" , 0, 32, 360, "RO", 0, 0, 0ull, 0ull},
- {"ITR_WABT" , 0, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IMR_WABT" , 1, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IMR_WTTO" , 2, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"ITR_ABT" , 3, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IMR_ABT" , 4, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IMR_TTO" , 5, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IMSI_PER" , 6, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IMSI_TABT" , 7, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IMSI_MABT" , 8, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IMSC_MSG" , 9, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"ITSR_ABT" , 10, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"ISERR" , 11, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IAPERR" , 12, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IDPERR" , 13, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IRSL_INT" , 16, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IPCNT0" , 17, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IPCNT1" , 18, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_19_20" , 19, 2, 361, "RAZ", 0, 1, 0ull, 0},
- {"IPTIME0" , 21, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IPTIME1" , 22, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_24" , 23, 2, 361, "RAZ", 0, 1, 0ull, 0},
- {"IDCNT0" , 25, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IDCNT1" , 26, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IDTIME0" , 27, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"IDTIME1" , 28, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 361, "RAZ", 1, 1, 0, 0},
- {"RTR_WABT" , 0, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RMR_WABT" , 1, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RMR_WTTO" , 2, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RTR_ABT" , 3, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RMR_ABT" , 4, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RMR_TTO" , 5, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RMSI_PER" , 6, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RMSI_TABT" , 7, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RMSI_MABT" , 8, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RMSC_MSG" , 9, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RTSR_ABT" , 10, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RSERR" , 11, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RAPERR" , 12, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RDPERR" , 13, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RRSL_INT" , 16, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RPCNT0" , 17, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RPCNT1" , 18, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_19_20" , 19, 2, 362, "RAZ", 0, 1, 0ull, 0},
- {"RPTIME0" , 21, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RPTIME1" , 22, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_24" , 23, 2, 362, "RAZ", 0, 1, 0ull, 0},
- {"RDCNT0" , 25, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RDCNT1" , 26, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RDTIME0" , 27, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RDTIME1" , 28, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 362, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 363, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_20" , 19, 2, 363, "RAZ", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_24" , 23, 2, 363, "RAZ", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 363, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 364, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_20" , 19, 2, 364, "RAZ", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_24" , 23, 2, 364, "RAZ", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 364, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 6, 365, "WO", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 365, "R/W", 1, 1, 0, 0},
- {"PTR_CNT" , 0, 16, 366, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 16, 16, 366, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 0, 32, 367, "RO", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 368, "R/W", 0, 1, 0ull, 0},
- {"PKT_TIME" , 0, 32, 369, "R/W", 0, 1, 0ull, 0},
- {"PREFETCH" , 0, 3, 370, "R/W", 0, 0, 0ull, 2ull},
- {"MIN_DATA" , 3, 6, 370, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_9_31" , 9, 23, 370, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 371, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 371, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 371, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 372, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 372, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 372, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 31, 373, "R/W", 0, 0, 10000ull, 10000ull},
- {"ENB" , 31, 1, 373, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 373, "RAZ", 1, 1, 0, 0},
- {"SCM" , 0, 32, 374, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 374, "RAZ", 1, 1, 0, 0},
- {"TSR" , 0, 36, 375, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 375, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 376, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 2, 46, 376, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 376, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 376, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 377, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 378, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 378, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 378, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 378, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 379, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 380, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 380, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 381, "R/W", 0, 0, 0ull, 8ull},
- {"FETCHSIZ" , 4, 4, 381, "R/W", 0, 0, 0ull, 7ull},
- {"TXRD" , 8, 10, 381, "R/W", 0, 0, 0ull, 1ull},
- {"USELDT" , 18, 1, 381, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 381, "RAZ", 1, 1, 0, 0},
- {"RXST" , 20, 10, 381, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_30_31" , 30, 2, 381, "RAZ", 1, 1, 0, 0},
- {"TXSLOTS" , 32, 10, 381, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_42_43" , 42, 2, 381, "RAZ", 1, 1, 0, 0},
- {"RXSLOTS" , 44, 10, 381, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_62" , 54, 9, 381, "RAZ", 1, 1, 0, 0},
- {"RDPEND" , 63, 1, 381, "RO", 0, 0, 0ull, 0ull},
- {"FSYNCMISSED" , 0, 1, 382, "R/W", 0, 0, 0ull, 1ull},
- {"FSYNCEXTRA" , 1, 1, 382, "R/W", 0, 0, 0ull, 1ull},
- {"RXWRAP" , 2, 1, 382, "R/W", 0, 0, 0ull, 1ull},
- {"RXST" , 3, 1, 382, "R/W", 0, 0, 0ull, 1ull},
- {"TXWRAP" , 4, 1, 382, "R/W", 0, 0, 0ull, 1ull},
- {"TXRD" , 5, 1, 382, "R/W", 0, 0, 0ull, 1ull},
- {"TXEMPTY" , 6, 1, 382, "R/W", 0, 0, 0ull, 1ull},
- {"RXOVF" , 7, 1, 382, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 382, "RAZ", 1, 1, 0, 0},
- {"FSYNCMISSED" , 0, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYNCEXTRA" , 1, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXWRAP" , 2, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXST" , 3, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXWRAP" , 4, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXRD" , 5, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXEMPTY" , 6, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXOVF" , 7, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 383, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 384, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 384, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 385, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 385, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 386, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 387, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 388, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 389, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 390, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 391, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 392, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 393, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 394, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 394, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 394, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 395, "R/W", 0, 0, 0ull, 0ull},
- {"USECLK1" , 1, 1, 395, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 2, 1, 395, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 395, "RAZ", 1, 1, 0, 0},
- {"SAMPPT" , 32, 16, 395, "R/W", 0, 1, 0ull, 0},
- {"DRVTIM" , 48, 16, 395, "R/W", 0, 1, 0ull, 0},
- {"DEBUGINFO" , 0, 64, 396, "RO", 1, 1, 0, 0},
- {"FRAM" , 0, 3, 397, "R/W", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 397, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 397, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 398, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 398, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 399, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 400, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 401, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 402, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 403, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 404, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 405, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 406, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 407, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 407, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 407, "RAZ", 1, 1, 0, 0},
- {"ENA" , 0, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"FSYNCPOL" , 1, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"BCLKPOL" , 2, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"BITLEN" , 3, 2, 408, "R/W", 0, 0, 0ull, 0ull},
- {"EXTRABIT" , 5, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"NUMSLOTS" , 6, 10, 408, "R/W", 0, 1, 0ull, 0},
- {"FSYNCLOC" , 16, 5, 408, "R/W", 0, 0, 0ull, 0ull},
- {"FSYNCLEN" , 21, 5, 408, "R/W", 0, 0, 0ull, 2ull},
- {"RESERVED_26_31" , 26, 6, 408, "RAZ", 1, 1, 0, 0},
- {"FSYNCSAMP" , 32, 16, 408, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_62" , 48, 15, 408, "RAZ", 1, 1, 0, 0},
- {"FSYNCGOOD" , 63, 1, 408, "RO", 0, 0, 0ull, 1ull},
- {"DEBUGINFO" , 0, 64, 409, "RO", 1, 1, 0, 0},
- {"N" , 0, 32, 410, "R/W", 0, 1, 0ull, 0},
- {"NUMSAMP" , 32, 16, 410, "R/W", 0, 1, 0ull, 0},
- {"DELTASAMP" , 48, 16, 410, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 18, 411, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 411, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 412, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 412, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 412, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 412, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 413, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 413, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 413, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 413, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 414, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 414, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 414, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 414, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 414, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 414, "RAZ", 0, 1, 0ull, 0},
- {"L4_MAL" , 8, 1, 414, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 414, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 414, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 414, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 414, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 414, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 414, "RAZ", 0, 0, 0ull, 0ull},
- {"PKTDRP" , 0, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 415, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 416, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 417, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 417, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 418, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 418, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 418, "RAZ", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 418, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 418, "RAZ", 1, 1, 0, 0},
- {"GRP_WAT" , 28, 4, 418, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 418, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 419, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 419, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 419, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 419, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 419, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 420, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 421, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 421, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 422, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 422, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 422, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 422, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 422, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 423, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 423, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 424, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 424, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 425, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 425, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 426, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 426, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 427, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 427, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 428, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 429, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 429, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 430, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 430, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 431, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 431, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 432, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 432, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 433, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 433, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 434, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 434, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 435, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 435, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 436, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 436, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 437, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 437, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 438, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 438, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 439, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 439, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 440, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 440, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 441, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 441, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 441, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 442, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 442, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 442, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 443, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 443, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 444, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 444, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 445, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 445, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 445, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 445, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 446, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 446, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 446, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 446, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 446, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 0, 16, 447, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 447, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 447, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 447, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 448, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 448, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 448, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 448, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 448, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 449, "RO", 1, 0, 0, 0ull},
- {"WIDX2" , 0, 17, 450, "RO", 1, 0, 0, 0ull},
- {"RIDX2" , 17, 17, 450, "RO", 1, 0, 0, 0ull},
- {"WIDX" , 34, 17, 450, "RO", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 450, "RO", 1, 0, 0, 0ull},
- {"RIDX" , 0, 17, 451, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 451, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 452, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 452, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 452, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 452, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 452, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 453, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 453, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 453, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 453, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 453, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 454, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 4, 455, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 4, 2, 455, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 6, 1, 455, "RO", 1, 0, 0, 0ull},
- {"QID_BASE" , 7, 7, 455, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 14, 3, 455, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 17, 5, 455, "RO", 1, 0, 0, 0ull},
- {"QOS" , 22, 3, 455, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 455, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 26, 1, 455, "RO", 1, 0, 0, 0ull},
- {"RESERVED_27_27" , 27, 1, 455, "RO", 1, 0, 0, 0ull},
- {"CBUF_FRE" , 28, 1, 455, "RO", 1, 0, 0, 0ull},
- {"XFER_DWR" , 29, 1, 455, "RO", 1, 0, 0, 0ull},
- {"XFER_WOR" , 30, 1, 455, "RO", 1, 0, 0, 0ull},
- {"UID" , 31, 1, 455, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 32, 16, 455, "RO", 1, 0, 0, 0ull},
- {"DWRI_CNT" , 48, 13, 455, "RO", 1, 0, 0, 0ull},
- {"DWRI_LEN" , 61, 1, 455, "RO", 1, 0, 0, 0ull},
- {"DWRI_SOP" , 62, 1, 455, "RO", 1, 0, 0, 0ull},
- {"DWRI_MOD" , 63, 1, 455, "RO", 1, 0, 0, 0ull},
- {"DWRI_MOD" , 0, 2, 456, "RO", 1, 0, 0, 0ull},
- {"DWRI_UID" , 2, 1, 456, "RO", 1, 0, 0, 0ull},
- {"DWRI_CHK" , 3, 1, 456, "RO", 1, 0, 0, 0ull},
- {"WORK_MIN" , 4, 3, 456, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 7, 1, 456, "RO", 1, 0, 0, 0ull},
- {"QID_OFFM" , 8, 3, 456, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 456, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 0, 16, 457, "RO", 1, 0, 0, 0ull},
- {"START" , 16, 33, 457, "RO", 1, 0, 0, 0ull},
- {"DWB" , 49, 9, 457, "RO", 1, 0, 0, 0ull},
- {"RESERVED_58_63" , 58, 6, 457, "RO", 1, 1, 0, 0},
- {"QCB_RIDX" , 0, 6, 458, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 458, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 458, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 458, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 458, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 458, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 459, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 459, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 459, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_7" , 5, 3, 459, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 459, "RO", 1, 0, 0, 0ull},
- {"RESERVED_28_63" , 28, 36, 459, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 460, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 460, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 460, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 460, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 460, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 460, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 460, "WR0", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 460, "WR0", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 460, "WR0", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 461, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 461, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 461, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 461, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 461, "RAZ", 1, 1, 0, 0},
- {"PSB" , 0, 7, 462, "RO", 1, 0, 0, 0ull},
- {"PDB" , 7, 4, 462, "RO", 1, 0, 0, 0ull},
- {"QCB" , 11, 2, 462, "RO", 1, 0, 0, 0ull},
- {"QSB" , 13, 2, 462, "RO", 1, 0, 0, 0ull},
- {"CHK" , 15, 1, 462, "RO", 1, 0, 0, 0ull},
- {"CRC" , 16, 1, 462, "RO", 1, 0, 0, 0ull},
- {"OUT" , 17, 1, 462, "RO", 1, 0, 0, 0ull},
- {"NCB" , 18, 1, 462, "RO", 1, 0, 0, 0ull},
- {"WIF" , 19, 1, 462, "RO", 1, 0, 0, 0ull},
- {"RIF" , 20, 1, 462, "RO", 1, 0, 0, 0ull},
- {"COUNT" , 21, 1, 462, "RO", 1, 0, 0, 0ull},
- {"PSB2" , 22, 5, 462, "RO", 1, 0, 0, 0ull},
- {"RESERVED_27_63" , 27, 37, 462, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 463, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 463, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 463, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 463, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 17, 464, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 464, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 465, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 466, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 466, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 466, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 466, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 466, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 467, "R/W", 0, 0, 0ull, 0ull},
- {"MODE1" , 3, 3, 467, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 467, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 468, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 468, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 468, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 469, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 469, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 470, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 470, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 470, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"PEND" , 1, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 2, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 3, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 4, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 5, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"NBT0" , 6, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"NBT1" , 7, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 8, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 471, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 2, 471, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 471, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 472, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 472, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 473, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 473, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 473, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 473, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 473, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 473, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 474, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 474, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 474, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 475, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 475, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 476, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 476, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 9, 477, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 477, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 478, "R/W", 0, 0, 0ull, 1023ull},
- {"RESERVED_10_63" , 10, 54, 478, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 479, "R/W", 0, 0, 65535ull, 65535ull},
- {"RESERVED_16_63" , 16, 48, 479, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 480, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 480, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 480, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 480, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 480, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 8, 481, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_11" , 8, 4, 481, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 8, 481, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_20_23" , 20, 4, 481, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 9, 481, "RO", 0, 1, 249ull, 0},
- {"RESERVED_33_35" , 33, 3, 481, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 36, 9, 481, "RO", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 481, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 48, 9, 481, "RO", 0, 1, 0ull, 0},
- {"RESERVED_57_63" , 57, 7, 481, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 482, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 482, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 483, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 483, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 484, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 484, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 485, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 485, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 485, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 9, 486, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 486, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 12, 9, 486, "RO", 0, 1, 0ull, 0},
- {"RESERVED_21_23" , 21, 3, 486, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 24, 4, 486, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 486, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 487, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 487, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 487, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 487, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 487, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 8, 488, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_11" , 8, 4, 488, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 8, 488, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_23" , 20, 4, 488, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 488, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 488, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 488, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 489, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 489, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 490, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 490, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 490, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 491, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 491, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 491, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 491, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 491, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 492, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 492, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 492, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 492, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 492, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 492, "RAZ", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 492, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 492, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 493, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 493, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 493, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 493, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 1, 493, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 493, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 494, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 494, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 495, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 495, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 495, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 495, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 496, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 496, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 496, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 496, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 497, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 497, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 497, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 497, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 497, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 497, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 498, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 498, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 498, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 499, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 499, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 499, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 499, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 499, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 500, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 500, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 500, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 500, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 501, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 501, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 501, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 501, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 501, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 501, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 502, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 502, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 502, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 502, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 503, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 503, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 504, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 504, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 505, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 505, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 506, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 506, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 506, "RAZ", 1, 1, 0, 0},
- {"TDF0" , 0, 1, 507, "RO", 0, 0, 0ull, 0ull},
- {"TDF1" , 1, 1, 507, "RO", 0, 0, 0ull, 0ull},
- {"TCF" , 2, 1, 507, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 507, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 508, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 508, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 508, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 508, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 509, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 509, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 509, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 510, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 510, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 511, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 511, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 512, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 512, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 513, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 513, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 513, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 513, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 513, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 513, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 513, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 513, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 513, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 513, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 513, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 513, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 514, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 514, "RAZ", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 516, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 517, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 517, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 518, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 518, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 519, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 519, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 520, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 520, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 520, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 520, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 520, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 520, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 520, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 520, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 520, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 520, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 520, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 520, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 521, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 521, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 522, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 522, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 523, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 523, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 524, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 525, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 525, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 525, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 525, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 526, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 526, "RAZ", 0, 0, 0ull, 0ull},
- {"INEPINT" , 0, 16, 527, "RO", 0, 0, 0ull, 0ull},
- {"OUTEPINT" , 16, 16, 527, "RO", 0, 0, 0ull, 0ull},
- {"INEPMSK" , 0, 16, 528, "R/W", 0, 0, 0ull, 0ull},
- {"OUTEPMSK" , 16, 16, 528, "R/W", 0, 0, 0ull, 0ull},
- {"DEVSPD" , 0, 2, 529, "R/W", 0, 0, 0ull, 0ull},
- {"NZSTSOUTHSHK" , 2, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 529, "RAZ", 1, 1, 0, 0},
- {"DEVADDR" , 4, 7, 529, "R/W", 0, 0, 0ull, 0ull},
- {"PERFRINT" , 11, 2, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_17" , 13, 5, 529, "RAZ", 1, 1, 0, 0},
- {"EPMISCNT" , 18, 5, 529, "R/W", 0, 0, 8ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 529, "RAZ", 1, 1, 0, 0},
- {"RMTWKUPSIG" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"SFTDISCON" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"GNPINNAKSTS" , 2, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKSTS" , 3, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"TSTCTL" , 4, 3, 530, "R/W", 0, 0, 0ull, 0ull},
- {"SGNPINNAK" , 7, 1, 530, "WO", 0, 0, 0ull, 0ull},
- {"CGNPINNAK" , 8, 1, 530, "WO", 0, 0, 0ull, 0ull},
- {"SGOUTNAK" , 9, 1, 530, "WO", 0, 0, 0ull, 0ull},
- {"CGOUTNAK" , 10, 1, 530, "WO", 0, 0, 0ull, 0ull},
- {"PWRONPRGDONE" , 11, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 530, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 531, "R/W", 0, 0, 0ull, 0ull},
- {"NEXTEP" , 11, 4, 531, "R/W", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 531, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 531, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 531, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 531, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 531, "RAZ", 1, 1, 0, 0},
- {"STALL" , 21, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 22, 4, 531, "R/W", 0, 0, 0ull, 0ull},
- {"CNAK" , 26, 1, 531, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 531, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 531, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 531, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMEOUT" , 3, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMP" , 4, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNEPMIS" , 5, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
- {"INEPNAKEFF" , 6, 1, 532, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 532, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"TIMEOUTMSK" , 3, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMPMSK" , 4, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNEPMISMSK" , 5, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"INEPNAKEFFMSK" , 6, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 533, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 534, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 534, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 534, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 534, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 535, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_14" , 11, 4, 535, "RAZ", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 535, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 535, "R/W", 0, 0, 0ull, 0ull},
- {"SNP" , 20, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"STALL" , 21, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_25" , 22, 4, 535, "RAZ", 1, 1, 0, 0},
- {"CNAK" , 26, 1, 535, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 535, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 535, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 535, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 536, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 536, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 536, "R/W1C", 0, 0, 0ull, 0ull},
- {"SETUP" , 3, 1, 536, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDIS" , 4, 1, 536, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 536, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 537, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 537, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 537, "R/W", 0, 0, 0ull, 0ull},
- {"SETUPMSK" , 3, 1, 537, "R/W", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDISMSK" , 4, 1, 537, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 537, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 538, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 538, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 538, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 538, "RAZ", 1, 1, 0, 0},
- {"DPTXFSTADDR" , 0, 16, 539, "RO", 0, 0, 0ull, 0ull},
- {"DPTXFSIZE" , 16, 16, 539, "RO", 0, 0, 1896ull, 1896ull},
- {"SUSPSTS" , 0, 1, 540, "RO", 0, 0, 0ull, 0ull},
- {"ENUMSPD" , 1, 2, 540, "RO", 0, 0, 0ull, 0ull},
- {"ERRTICERR" , 3, 1, 540, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 540, "RAZ", 1, 1, 0, 0},
- {"SOFFN" , 8, 14, 540, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 540, "RAZ", 1, 1, 0, 0},
- {"INTKNWPTR" , 0, 5, 541, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 541, "RAZ", 1, 1, 0, 0},
- {"WRAPBIT" , 7, 1, 541, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 8, 24, 541, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 542, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 543, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 544, "RO", 0, 0, 0ull, 0ull},
- {"GLBLINTRMSK" , 0, 1, 545, "R/W", 0, 0, 0ull, 1ull},
- {"HBSTLEN" , 1, 4, 545, "R/W", 0, 0, 0ull, 0ull},
- {"DMAEN" , 5, 1, 545, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 545, "RAZ", 1, 1, 0, 0},
- {"NPTXFEMPLVL" , 7, 1, 545, "R/W", 0, 0, 0ull, 1ull},
- {"PTXFEMPLVL" , 8, 1, 545, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_31" , 9, 23, 545, "RAZ", 1, 1, 0, 0},
- {"EPDIR" , 0, 32, 546, "RO", 0, 0, 0ull, 0ull},
- {"OTGMODE" , 0, 3, 547, "RO", 0, 0, 2ull, 2ull},
- {"OTGARCH" , 3, 2, 547, "RO", 0, 0, 1ull, 1ull},
- {"SINGPNT" , 5, 1, 547, "RO", 0, 0, 0ull, 0ull},
- {"HSPHYTYPE" , 6, 2, 547, "RO", 0, 0, 1ull, 1ull},
- {"FSPHYTYPE" , 8, 2, 547, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVEPS" , 10, 4, 547, "RO", 0, 0, 4ull, 4ull},
- {"NUMHSTCHNL" , 14, 4, 547, "RO", 0, 0, 7ull, 7ull},
- {"PERIOSUPPORT" , 18, 1, 547, "RO", 0, 0, 1ull, 1ull},
- {"DYNFIFOSIZING" , 19, 1, 547, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_20_21" , 20, 2, 547, "RAZ", 1, 1, 0, 0},
- {"NPTXQDEPTH" , 22, 2, 547, "RO", 0, 0, 2ull, 2ull},
- {"PTXQDEPTH" , 24, 2, 547, "RO", 0, 0, 2ull, 2ull},
- {"TKNQDEPTH" , 26, 5, 547, "RO", 0, 0, 30ull, 30ull},
- {"RESERVED_31_31" , 31, 1, 547, "RAZ", 1, 1, 0, 0},
- {"XFERSIZEWIDTH" , 0, 4, 548, "RO", 0, 0, 8ull, 8ull},
- {"PKTSIZEWIDTH" , 4, 3, 548, "RO", 0, 0, 6ull, 6ull},
- {"OTGEN" , 7, 1, 548, "RO", 0, 0, 1ull, 1ull},
- {"I2C_SELECTION" , 8, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"OPTFEATURE" , 10, 1, 548, "RO", 0, 0, 1ull, 1ull},
- {"RSTTYPE" , 11, 1, 548, "RO", 0, 0, 1ull, 1ull},
- {"AHBPHYSYNC" , 12, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 548, "RAZ", 1, 1, 0, 0},
- {"DFIFODEPTH" , 16, 16, 548, "RO", 0, 0, 1824ull, 1824ull},
- {"NUMDEVPERIOEPS" , 0, 4, 549, "RO", 0, 0, 4ull, 4ull},
- {"ENABLEPWROPT" , 4, 1, 549, "RO", 0, 0, 0ull, 0ull},
- {"AHBFREQ" , 5, 1, 549, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_13" , 6, 8, 549, "RAZ", 1, 1, 0, 0},
- {"PHYDATAWIDTH" , 14, 2, 549, "RO", 0, 0, 1ull, 1ull},
- {"NUMCTLEPS" , 16, 4, 549, "RO", 0, 0, 4ull, 4ull},
- {"IDDGFLTR" , 20, 1, 549, "RO", 0, 0, 0ull, 0ull},
- {"VBUSVALIDFLTR" , 21, 1, 549, "RO", 0, 0, 0ull, 0ull},
- {"AVALIDFLTR" , 22, 1, 549, "RO", 0, 0, 1ull, 1ull},
- {"BVALIDFLTR" , 23, 1, 549, "RO", 0, 0, 1ull, 1ull},
- {"SESSENDFLTR" , 24, 1, 549, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_25_31" , 25, 7, 549, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 550, "RAZ", 1, 1, 0, 0},
- {"MODEMISMSK" , 1, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"OTGINTMSK" , 2, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"SOFMSK" , 3, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"RXFLVLMSK" , 4, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"NPTXFEMPMSK" , 5, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"GINNAKEFFMSK" , 6, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFFMSK" , 7, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"ULPICKINTMSK" , 8, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"ERLYSUSPMSK" , 10, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"USBSUSPMSK" , 11, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"USBRSTMSK" , 12, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"ENUMDONEMSK" , 13, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"ISOOUTDROPMSK" , 14, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"EOPFMSK" , 15, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 550, "RAZ", 1, 1, 0, 0},
- {"EPMISMSK" , 17, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"INEPINTMSK" , 18, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"OEPINTMSK" , 19, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPISOINMSK" , 20, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPLPMSK" , 21, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"FETSUSPMSK" , 22, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 550, "RAZ", 1, 1, 0, 0},
- {"PRTINTMSK" , 24, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"HCHINTMSK" , 25, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"PTXFEMPMSK" , 26, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 550, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNGMSK" , 28, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"DISCONNINTMSK" , 29, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"SESSREQINTMSK" , 30, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"WKUPINTMSK" , 31, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"CURMOD" , 0, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"MODEMIS" , 1, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"OTGINT" , 2, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"SOF" , 3, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXFLVL" , 4, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"NPTXFEMP" , 5, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"GINNAKEFF" , 6, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFF" , 7, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"ULPICKINT" , 8, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"ERLYSUSP" , 10, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBSUSP" , 11, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBRST" , 12, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENUMDONE" , 13, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"ISOOUTDROP" , 14, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"EOPF" , 15, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 551, "RAZ", 1, 1, 0, 0},
- {"EPMIS" , 17, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"IEPINT" , 18, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"OEPINT" , 19, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"INCOMPISOIN" , 20, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"INCOMPLP" , 21, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"FETSUSP" , 22, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 551, "RAZ", 1, 1, 0, 0},
- {"PRTINT" , 24, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"HCHINT" , 25, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"PTXFEMP" , 26, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 551, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNG" , 28, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"DISCONNINT" , 29, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"SESSREQINT" , 30, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"WKUPINT" , 31, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
- {"NPTXFSTADDR" , 0, 16, 552, "R/W", 0, 0, 1824ull, 456ull},
- {"NPTXFDEP" , 16, 16, 552, "R/W", 0, 0, 1824ull, 912ull},
- {"NPTXFSPCAVAIL" , 0, 16, 553, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQSPCAVAIL" , 16, 8, 553, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQTOP" , 24, 7, 553, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 553, "RAZ", 1, 1, 0, 0},
- {"SESREQSCS" , 0, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"SESREQ" , 1, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 554, "RAZ", 1, 1, 0, 0},
- {"HSTNEGSCS" , 8, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"HNPREQ" , 9, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"HSTSETHNPEN" , 10, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"DEVHNPEN" , 11, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 554, "RAZ", 1, 1, 0, 0},
- {"CONIDSTS" , 16, 1, 554, "RO", 1, 1, 0, 0},
- {"DBNCTIME" , 17, 1, 554, "RO", 0, 0, 0ull, 0ull},
- {"ASESVLD" , 18, 1, 554, "RO", 1, 1, 0, 0},
- {"BSESVLD" , 19, 1, 554, "RO", 1, 1, 0, 0},
- {"RESERVED_20_31" , 20, 12, 554, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 555, "RAZ", 1, 1, 0, 0},
- {"SESENDDET" , 2, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 555, "RAZ", 1, 1, 0, 0},
- {"SESREQSUCSTSCHNG" , 8, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSTNEGSUCSTSCHNG" , 9, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_16" , 10, 7, 555, "RAZ", 1, 1, 0, 0},
- {"HSTNEGDET" , 17, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"ADEVTOUTCHG" , 18, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBNCEDONE" , 19, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 555, "RAZ", 1, 1, 0, 0},
- {"CSFTRST" , 0, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"HSFTRST" , 1, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"FRMCNTRRST" , 2, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNQFLSH" , 3, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"RXFFLSH" , 4, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"TXFFLSH" , 5, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 6, 5, 556, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_29" , 11, 19, 556, "RAZ", 1, 1, 0, 0},
- {"DMAREQ" , 30, 1, 556, "RO", 0, 0, 0ull, 0ull},
- {"AHBIDLE" , 31, 1, 556, "RO", 0, 0, 1ull, 1ull},
- {"RXFDEP" , 0, 16, 557, "R/W", 0, 0, 1824ull, 456ull},
- {"RESERVED_16_31" , 16, 16, 557, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 558, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 558, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 558, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 558, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 558, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 558, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 559, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 559, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 559, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 559, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 559, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 560, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 560, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 560, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 560, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 560, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 560, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 561, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 561, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 561, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 561, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 561, "RAZ", 1, 1, 0, 0},
- {"SYNOPSYSID" , 0, 32, 562, "RO", 1, 1, 0, 0},
- {"TOUTCAL" , 0, 3, 563, "R/W", 0, 0, 0ull, 0ull},
- {"PHYIF" , 3, 1, 563, "RO", 0, 0, 1ull, 1ull},
- {"ULPI_UTMI_SEL" , 4, 1, 563, "RO", 0, 0, 0ull, 0ull},
- {"FSINTF" , 5, 1, 563, "WO", 0, 0, 0ull, 0ull},
- {"PHYSEL" , 6, 1, 563, "WO", 0, 0, 0ull, 0ull},
- {"DDRSEL" , 7, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"SRPCAP" , 8, 1, 563, "RO", 0, 0, 0ull, 0ull},
- {"HNPCAP" , 9, 1, 563, "RO", 0, 0, 0ull, 0ull},
- {"USBTRDTIM" , 10, 4, 563, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_14_14" , 14, 1, 563, "RAZ", 1, 1, 0, 0},
- {"PHYLPWRCLKSEL" , 15, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"OTGI2CSEL" , 16, 1, 563, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 563, "RAZ", 1, 1, 0, 0},
- {"HAINT" , 0, 16, 564, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 564, "RAZ", 1, 1, 0, 0},
- {"HAINTMSK" , 0, 16, 565, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 565, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 566, "R/W", 0, 0, 0ull, 0ull},
- {"EPNUM" , 11, 4, 566, "R/W", 0, 0, 0ull, 0ull},
- {"EPDIR" , 15, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 566, "RAZ", 1, 1, 0, 0},
- {"LSPDDEV" , 17, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 566, "R/W", 0, 0, 0ull, 0ull},
- {"EC" , 20, 2, 566, "R/W", 0, 0, 0ull, 0ull},
- {"DEVADDR" , 22, 7, 566, "R/W", 0, 0, 0ull, 0ull},
- {"ODDFRM" , 29, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"CHDIS" , 30, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"CHENA" , 31, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSPCLKSEL" , 0, 2, 567, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSSUPP" , 2, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 567, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPL" , 0, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"CHHLTD" , 1, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"STALL" , 3, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAK" , 4, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACK" , 5, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"NYET" , 6, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"XACTERR" , 7, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"BBLERR" , 8, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMOVRUN" , 9, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATATGLERR" , 10, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 568, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"CHHLTDMSK" , 1, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"STALLMSK" , 3, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"NAKMSK" , 4, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"ACKMSK" , 5, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"NYETMSK" , 6, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"XACTERRMSK" , 7, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"BBLERRMSK" , 8, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"FRMOVRUNMSK" , 9, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"DATATGLERRMSK" , 10, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 569, "RAZ", 1, 1, 0, 0},
- {"PRTADDR" , 0, 7, 570, "R/W", 0, 0, 0ull, 0ull},
- {"HUBADDR" , 7, 7, 570, "R/W", 0, 0, 0ull, 0ull},
- {"XACTPOS" , 14, 2, 570, "R/W", 0, 0, 0ull, 0ull},
- {"COMPSPLT" , 16, 1, 570, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_30" , 17, 14, 570, "RAZ", 1, 1, 0, 0},
- {"SPLTENA" , 31, 1, 570, "R/W", 0, 0, 0ull, 0ull},
- {"XFERSIZE" , 0, 19, 571, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 571, "R/W", 0, 0, 0ull, 0ull},
- {"PID" , 29, 2, 571, "R/W", 0, 0, 0ull, 0ull},
- {"DOPNG" , 31, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"FRINT" , 0, 16, 572, "R/W", 0, 0, 2959ull, 3750ull},
- {"RESERVED_16_31" , 16, 16, 572, "RAZ", 1, 1, 0, 0},
- {"FRNUM" , 0, 16, 573, "RO", 0, 0, 16383ull, 0ull},
- {"FRREM" , 16, 16, 573, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNSTS" , 0, 1, 574, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNDET" , 1, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENA" , 2, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENCHNG" , 3, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRACT" , 4, 1, 574, "RO", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRCHNG" , 5, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTRES" , 6, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSUSP" , 7, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PRTRST" , 8, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 574, "RAZ", 1, 1, 0, 0},
- {"PRTLNSTS" , 10, 2, 574, "RO", 0, 0, 0ull, 0ull},
- {"PRTPWR" , 12, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PRTTSTCTL" , 13, 4, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSPD" , 17, 2, 574, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 574, "RAZ", 1, 1, 0, 0},
- {"PTXFSTADDR" , 0, 16, 575, "R/W", 0, 0, 3648ull, 912ull},
- {"PTXFSIZE" , 16, 16, 575, "R/W", 0, 0, 1824ull, 456ull},
- {"PTXFSPCAVAIL" , 0, 16, 576, "RO", 0, 0, 0ull, 0ull},
- {"PTXQSPCAVAIL" , 16, 8, 576, "RO", 0, 0, 0ull, 0ull},
- {"PTXQTOP" , 24, 8, 576, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 32, 577, "R/W", 0, 0, 0ull, 0ull},
- {"STOPPCLK" , 0, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"GATEHCLK" , 1, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"PWRCLMP" , 2, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RSTPDWNMODULE" , 3, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"PHYSUSPENDED" , 4, 1, 578, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 578, "RAZ", 1, 1, 0, 0},
- {"NOF_BIS" , 0, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"NIF_BIS" , 1, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"USBC_BIS" , 2, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 579, "RAZ", 1, 1, 0, 0},
- {"DIVIDE" , 0, 3, 580, "R/W", 0, 0, 4ull, 4ull},
- {"HRST" , 3, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"PRST" , 4, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"ENABLE" , 5, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"POR" , 6, 1, 580, "R/W", 0, 0, 1ull, 0ull},
- {"S_BIST" , 7, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"SD_MODE" , 8, 2, 580, "R/W", 0, 0, 0ull, 0ull},
- {"CDIV_BYP" , 10, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"P_C_SEL" , 11, 2, 580, "R/W", 0, 0, 2ull, 2ull},
- {"P_COM_ON" , 13, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"P_XENBN" , 14, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"P_RCLK" , 15, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"P_X_ON" , 16, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"HCLK_RST" , 17, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_18_63" , 18, 46, 580, "RAZ", 1, 1, 0, 0},
- {"L2C_EMOD" , 0, 2, 581, "R/W", 0, 0, 1ull, 1ull},
- {"INV_A2" , 2, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_TEST" , 3, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_STT" , 4, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_0PAG" , 5, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 581, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 582, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 582, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 583, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 583, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 584, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 584, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 585, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 585, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 586, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 586, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 587, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 587, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 588, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 588, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 589, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 589, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 590, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 590, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 591, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 591, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 592, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 592, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 593, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 593, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 594, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 594, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 595, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 595, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 596, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 596, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 597, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 597, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 4, 598, "R/W", 0, 0, 0ull, 0ull},
- {"CHANNEL" , 4, 5, 598, "R/W", 0, 0, 0ull, 0ull},
- {"COUNT" , 9, 11, 598, "R/W", 0, 0, 0ull, 0ull},
- {"F_ADDR" , 20, 18, 598, "R/W", 0, 0, 0ull, 0ull},
- {"REQ" , 38, 1, 598, "R/W1C", 0, 0, 0ull, 0ull},
- {"DONE" , 39, 1, 598, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 598, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_A_F" , 15, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_E" , 16, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_F" , 17, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PF" , 25, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"N2U_PF" , 26, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"N2U_PE" , 27, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"U2N_D_PE" , 28, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"U2N_D_PF" , 29, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"U2N_C_PF" , 30, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"U2N_C_PE" , 31, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"LTL_F_PE" , 32, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPF" , 35, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPE" , 36, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPF" , 37, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 599, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"L2C_A_F" , 15, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"LT_FI_E" , 16, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_FI_F" , 17, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"UOD_PF" , 25, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"N2U_PF" , 26, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"N2U_PE" , 27, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"U2N_D_PE" , 28, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"U2N_D_PF" , 29, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"U2N_C_PF" , 30, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"U2N_C_PE" , 31, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"LTL_F_PE" , 32, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_RPF" , 35, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPE" , 36, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPF" , 37, 1, 600, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_38_63" , 38, 26, 600, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_IN" , 1, 8, 601, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 9, 4, 601, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 13, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ENB" , 14, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_ENB" , 15, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_ENB" , 16, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_EN" , 17, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_ENH" , 18, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"TUNING" , 19, 4, 601, "R/W", 0, 0, 9ull, 0ull},
- {"HST_MODE" , 23, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"DM_PULLD" , 24, 1, 601, "R/W", 0, 0, 1ull, 1ull},
- {"DP_PULLD" , 25, 1, 601, "R/W", 0, 0, 1ull, 1ull},
- {"TCLK" , 26, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"USBP_BIST" , 27, 1, 601, "R/W", 0, 0, 1ull, 1ull},
- {"USBC_END" , 28, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_BMODE" , 29, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 601, "RAZ", 0, 0, 0ull, 0ull},
- {"TDATA_OUT" , 32, 4, 601, "RO", 1, 1, 0, 0},
- {"BIST_ERR" , 36, 1, 601, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 37, 1, 601, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 601, "RAZ", 1, 1, 0, 0},
- {"ZIP_CTL" , 0, 4, 602, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 27, 602, "RO", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 602, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 603, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 603, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 603, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 603, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 603, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 604, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 604, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 605, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 605, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 605, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 605, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 605, "RO", 0, 0, 31744ull, 31744ull},
- {"RESERVED_48_63" , 48, 16, 605, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 14, 606, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 606, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 607, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 607, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 608, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn30xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_asx#_gmii_rx_clk_set" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 2, 0},
- {"cvmx_asx#_gmii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 2},
- {"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 4},
- {"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 6, 10},
- {"cvmx_asx#_mii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 2, 16},
- {"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 4, 18},
- {"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 22},
- {"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 2, 24},
- {"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 2, 26},
- {"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 4, 28},
- {"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 32},
- {"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 17, 2, 34},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 18, 2, 36},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 19, 2, 38},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 20, 2, 40},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 21, 2, 42},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 22, 19, 44},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 25, 2, 63},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 28, 19, 65},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 31, 2, 84},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 32, 2, 86},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 33, 2, 88},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 34, 2, 90},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 35, 2, 92},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 36, 2, 94},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 37, 1, 96},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 38, 2, 97},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 39, 2, 99},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 40, 4, 101},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 41, 2, 105},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 42, 3, 107},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 46, 7, 110},
- {"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 47, 6, 117},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 48, 6, 123},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 49, 7, 129},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 50, 29, 136},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 51, 29, 165},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 194},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 196},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 3, 198},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 69, 3, 201},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 70, 2, 204},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 2, 206},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 8, 208},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 73, 2, 216},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 4, 218},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 2, 222},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 76, 5, 224},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 1, 229},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 82, 1, 230},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 85, 1, 231},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 88, 1, 232},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 1, 233},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 94, 1, 234},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 97, 2, 235},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 100, 4, 237},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 2, 241},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 106, 11, 243},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 109, 10, 254},
- {"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 112, 2, 264},
- {"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 115, 2, 266},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 118, 2, 268},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 121, 20, 270},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 124, 20, 290},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 127, 2, 310},
- {"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 130, 4, 312},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 133, 2, 316},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 136, 2, 318},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 139, 2, 320},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 142, 2, 322},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 145, 2, 324},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 148, 2, 326},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 151, 2, 328},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 154, 2, 330},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 157, 2, 332},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 160, 2, 334},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 163, 4, 336},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 166, 2, 340},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 169, 2, 342},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 172, 2, 344},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 175, 4, 346},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 176, 2, 350},
- {"cvmx_gmx#_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 177, 4, 352},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 178, 2, 356},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 181, 3, 358},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 182, 5, 361},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 185, 2, 366},
- {"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 188, 2, 368},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 191, 3, 370},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 194, 2, 373},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 197, 2, 375},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 200, 2, 377},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 203, 2, 379},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 206, 2, 381},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 209, 2, 383},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 212, 2, 385},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 215, 2, 387},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 218, 2, 389},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 221, 2, 391},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 224, 2, 393},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 227, 2, 395},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 230, 2, 397},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 233, 2, 399},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 236, 2, 401},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 239, 2, 403},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 242, 2, 405},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 245, 2, 407},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 248, 2, 409},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 251, 2, 411},
- {"cvmx_gmx#_tx_clk_msk#" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 2, 413},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 2, 415},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 2, 417},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 256, 3, 419},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 257, 10, 422},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 10, 432},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 259, 2, 442},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 260, 2, 444},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 6, 446},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 262, 2, 452},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 263, 2, 454},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 2, 456},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 265, 7, 458},
- {"cvmx_gpio_boot_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 281, 3, 465},
- {"cvmx_gpio_dbg_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 282, 2, 468},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 283, 2, 470},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 284, 2, 472},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 285, 2, 474},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 286, 2, 476},
- {"cvmx_gpio_xbit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 287, 6, 478},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 295, 19, 484},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 296, 6, 503},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 297, 3, 509},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 298, 5, 512},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 299, 5, 517},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 1, 522},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 301, 1, 523},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 5, 524},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 5, 529},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 304, 5, 534},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 305, 5, 539},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 306, 1, 544},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 307, 1, 545},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 2, 546},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 309, 2, 548},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 310, 2, 550},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 311, 2, 552},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 312, 17, 554},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 313, 2, 571},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 314, 1, 573},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 315, 10, 574},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 316, 6, 584},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 317, 6, 590},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 318, 2, 596},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 319, 2, 598},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 320, 2, 600},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 321, 3, 602},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 325, 2, 605},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 329, 6, 607},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 330, 5, 613},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 331, 6, 618},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 332, 7, 624},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 333, 2, 631},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 341, 2, 633},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 342, 3, 635},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 343, 5, 638},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 351, 3, 643},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 352, 2, 646},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 353, 2, 648},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 354, 2, 650},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 355, 7, 652},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 356, 6, 659},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 357, 8, 665},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 358, 9, 673},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 359, 10, 682},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 360, 5, 692},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 361, 4, 697},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 362, 2, 701},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 363, 17, 703},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 364, 19, 720},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 365, 3, 739},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 366, 4, 742},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 367, 2, 746},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 371, 17, 748},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 372, 2, 765},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 373, 2, 767},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 374, 3, 769},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 375, 2, 772},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 2, 774},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 377, 2, 776},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 378, 7, 778},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 379, 6, 785},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 380, 3, 791},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 381, 3, 794},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 382, 2, 797},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 383, 2, 799},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 384, 2, 801},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 385, 3, 803},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 386, 15, 806},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 387, 9, 821},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 20, 830},
- {"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 389, 2, 850},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 390, 2, 852},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 2, 854},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 18, 856},
- {"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 393, 4, 874},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 394, 5, 878},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 395, 6, 883},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 2, 889},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 397, 2, 891},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 398, 14, 893},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 399, 10, 907},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 2, 917},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 401, 2, 919},
- {"cvmx_lmc#_pll_bwctl" , CVMX_CSR_DB_TYPE_RSL, 64, 402, 3, 921},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 403, 9, 924},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 5, 933},
- {"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 405, 5, 938},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 406, 5, 943},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 3, 948},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 3, 951},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 409, 3, 954},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 410, 5, 957},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 1, 962},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 413, 10, 963},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 421, 13, 973},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 429, 4, 986},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 430, 2, 990},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 431, 2, 992},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 10, 994},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 433, 9, 1004},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 434, 2, 1013},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 435, 8, 1015},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 4, 1023},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 437, 2, 1027},
- {"cvmx_mio_fus_unlock" , CVMX_CSR_DB_TYPE_RSL, 64, 438, 2, 1029},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 439, 2, 1031},
- {"cvmx_mio_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 2, 1033},
- {"cvmx_mio_pll_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 441, 2, 1035},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 442, 13, 1037},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 443, 12, 1050},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 444, 3, 1062},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 445, 3, 1065},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 446, 2, 1068},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 1070},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 450, 2, 1072},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 452, 7, 1074},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 454, 2, 1081},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 7, 1083},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 458, 4, 1090},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 8, 1094},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 462, 9, 1102},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 7, 1111},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 466, 9, 1118},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 2, 1127},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 2, 1129},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 4, 1131},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 474, 2, 1135},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 476, 2, 1137},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 478, 2, 1139},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 480, 4, 1141},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 482, 2, 1145},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 484, 2, 1147},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 486, 2, 1149},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 488, 2, 1151},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 490, 2, 1153},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 492, 2, 1155},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 494, 6, 1157},
- {"cvmx_mpi_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 496, 14, 1163},
- {"cvmx_mpi_dat#" , CVMX_CSR_DB_TYPE_NCB, 64, 497, 2, 1177},
- {"cvmx_mpi_sts" , CVMX_CSR_DB_TYPE_NCB, 64, 506, 4, 1179},
- {"cvmx_mpi_tx" , CVMX_CSR_DB_TYPE_NCB, 64, 507, 6, 1183},
- {"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 508, 2, 1189},
- {"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 509, 2, 1191},
- {"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 510, 19, 1193},
- {"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 511, 3, 1212},
- {"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 512, 15, 1215},
- {"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 513, 2, 1230},
- {"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 514, 13, 1232},
- {"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 515, 3, 1245},
- {"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 516, 3, 1248},
- {"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 517, 3, 1251},
- {"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 518, 3, 1254},
- {"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 519, 2, 1257},
- {"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 520, 2, 1259},
- {"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 521, 9, 1261},
- {"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 522, 45, 1270},
- {"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 523, 45, 1315},
- {"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 524, 2, 1360},
- {"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 525, 2, 1362},
- {"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 526, 10, 1364},
- {"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 530, 1, 1374},
- {"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 531, 2, 1375},
- {"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 532, 14, 1377},
- {"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 533, 3, 1391},
- {"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 534, 2, 1394},
- {"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 535, 3, 1396},
- {"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 536, 3, 1399},
- {"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 537, 3, 1402},
- {"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 538, 4, 1405},
- {"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 539, 2, 1409},
- {"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 540, 13, 1411},
- {"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 541, 3, 1424},
- {"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 542, 33, 1427},
- {"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 543, 2, 1460},
- {"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 544, 2, 1462},
- {"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 545, 5, 1464},
- {"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 577, 2, 1469},
- {"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 578, 24, 1471},
- {"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 579, 2, 1495},
- {"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 580, 7, 1497},
- {"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 581, 5, 1504},
- {"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 582, 1, 1509},
- {"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 583, 5, 1510},
- {"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 584, 1, 1515},
- {"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 585, 4, 1516},
- {"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 586, 2, 1520},
- {"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 587, 1, 1522},
- {"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 588, 2, 1523},
- {"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 589, 4, 1525},
- {"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 590, 2, 1529},
- {"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 591, 4, 1531},
- {"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 592, 16, 1535},
- {"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 593, 1, 1551},
- {"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 594, 1, 1552},
- {"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 595, 18, 1553},
- {"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 596, 1, 1571},
- {"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 597, 1, 1572},
- {"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 598, 7, 1573},
- {"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 599, 7, 1580},
- {"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 600, 13, 1587},
- {"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 601, 10, 1600},
- {"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 602, 10, 1610},
- {"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 603, 7, 1620},
- {"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 604, 2, 1627},
- {"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 605, 1, 1629},
- {"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 606, 2, 1630},
- {"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 607, 22, 1632},
- {"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 608, 2, 1654},
- {"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 609, 1, 1656},
- {"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 611, 1, 1657},
- {"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 613, 1, 1658},
- {"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 615, 1, 1659},
- {"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 616, 31, 1660},
- {"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 617, 31, 1691},
- {"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 618, 31, 1722},
- {"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 619, 31, 1753},
- {"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 620, 2, 1784},
- {"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 621, 2, 1786},
- {"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 622, 1, 1788},
- {"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 623, 1, 1789},
- {"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 624, 1, 1790},
- {"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 625, 3, 1791},
- {"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 626, 3, 1794},
- {"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 627, 3, 1797},
- {"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 628, 3, 1800},
- {"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 629, 2, 1803},
- {"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 630, 2, 1805},
- {"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 631, 4, 1807},
- {"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 632, 1, 1811},
- {"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 633, 4, 1812},
- {"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 634, 1, 1816},
- {"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 635, 2, 1817},
- {"cvmx_pcm#_dma_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 636, 12, 1819},
- {"cvmx_pcm#_int_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 640, 9, 1831},
- {"cvmx_pcm#_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 644, 9, 1840},
- {"cvmx_pcm#_rxaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 648, 2, 1849},
- {"cvmx_pcm#_rxcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 652, 2, 1851},
- {"cvmx_pcm#_rxmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 656, 1, 1853},
- {"cvmx_pcm#_rxmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 660, 1, 1854},
- {"cvmx_pcm#_rxmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 664, 1, 1855},
- {"cvmx_pcm#_rxmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 668, 1, 1856},
- {"cvmx_pcm#_rxmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 672, 1, 1857},
- {"cvmx_pcm#_rxmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 676, 1, 1858},
- {"cvmx_pcm#_rxmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 680, 1, 1859},
- {"cvmx_pcm#_rxmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 684, 1, 1860},
- {"cvmx_pcm#_rxstart" , CVMX_CSR_DB_TYPE_NCB, 64, 688, 3, 1861},
- {"cvmx_pcm#_tdm_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 692, 6, 1864},
- {"cvmx_pcm#_tdm_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 696, 1, 1870},
- {"cvmx_pcm#_txaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 700, 3, 1871},
- {"cvmx_pcm#_txcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 704, 2, 1874},
- {"cvmx_pcm#_txmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 708, 1, 1876},
- {"cvmx_pcm#_txmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 712, 1, 1877},
- {"cvmx_pcm#_txmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 716, 1, 1878},
- {"cvmx_pcm#_txmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 720, 1, 1879},
- {"cvmx_pcm#_txmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 724, 1, 1880},
- {"cvmx_pcm#_txmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 728, 1, 1881},
- {"cvmx_pcm#_txmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 732, 1, 1882},
- {"cvmx_pcm#_txmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 736, 1, 1883},
- {"cvmx_pcm#_txstart" , CVMX_CSR_DB_TYPE_NCB, 64, 740, 3, 1884},
- {"cvmx_pcm_clk#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 744, 12, 1887},
- {"cvmx_pcm_clk#_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 746, 1, 1899},
- {"cvmx_pcm_clk#_gen" , CVMX_CSR_DB_TYPE_NCB, 64, 748, 3, 1900},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 2, 1903},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 751, 4, 1905},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 755, 8, 1909},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 756, 16, 1917},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 757, 10, 1933},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 10, 1943},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 759, 2, 1953},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 760, 16, 1955},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 765, 25, 1971},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 770, 2, 1996},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 834, 2, 1998},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 842, 9, 2000},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 846, 2, 2009},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 847, 2, 2011},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 848, 2, 2013},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 853, 2, 2015},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 858, 2, 2017},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 2, 2019},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 868, 2, 2021},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 873, 2, 2023},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 878, 2, 2025},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 883, 2, 2027},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 888, 2, 2029},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 893, 2, 2031},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 898, 2, 2033},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 899, 2, 2035},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 904, 2, 2037},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 909, 2, 2039},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 914, 2, 2041},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 978, 2, 2043},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 979, 3, 2045},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 980, 3, 2048},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 981, 2, 2051},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 982, 2, 2053},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 983, 4, 2055},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 984, 5, 2059},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 985, 4, 2064},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 986, 5, 2068},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 987, 1, 2073},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 988, 4, 2074},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 989, 2, 2078},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 5, 2080},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 991, 5, 2085},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 1, 2090},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 993, 19, 2091},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 994, 7, 2110},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 4, 2117},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 996, 6, 2121},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 997, 6, 2127},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 9, 2133},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 999, 5, 2142},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1000, 13, 2147},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1001, 4, 2160},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1002, 2, 2164},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 3, 2166},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 5, 2169},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1005, 3, 2174},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 3, 2177},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1007, 2, 2180},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1008, 3, 2182},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 1009, 12, 2185},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1010, 2, 2197},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 1011, 13, 2199},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1012, 3, 2212},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1013, 2, 2215},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1021, 2, 2217},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1022, 2, 2219},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 1023, 2, 2221},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 1024, 2, 2223},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 1025, 5, 2225},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1033, 10, 2230},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1041, 2, 2240},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1042, 2, 2242},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1043, 2, 2244},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1051, 3, 2246},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1052, 6, 2249},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1068, 5, 2255},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1069, 7, 2260},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1085, 2, 2267},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1101, 3, 2269},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1102, 5, 2272},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 8, 2277},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1104, 6, 2285},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 2, 2291},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1106, 4, 2293},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 4, 2297},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1108, 6, 2301},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 3, 2307},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1110, 5, 2310},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 1111, 4, 2315},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 1112, 6, 2319},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1113, 4, 2325},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1114, 2, 2329},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1115, 4, 2331},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1116, 2, 2335},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 3, 2337},
- {"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 1118, 2, 2340},
- {"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1119, 2, 2342},
- {"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1120, 8, 2344},
- {"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1121, 11, 2352},
- {"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1122, 15, 2363},
- {"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1127, 8, 2378},
- {"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1132, 8, 2386},
- {"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1133, 4, 2394},
- {"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1138, 15, 2398},
- {"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1143, 6, 2413},
- {"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1148, 6, 2419},
- {"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1149, 4, 2425},
- {"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1154, 2, 2429},
- {"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1158, 6, 2431},
- {"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 1159, 4, 2437},
- {"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 1160, 1, 2441},
- {"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 1161, 1, 2442},
- {"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 1162, 1, 2443},
- {"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1163, 7, 2444},
- {"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 1164, 1, 2451},
- {"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 1165, 14, 2452},
- {"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 1166, 10, 2466},
- {"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 1167, 12, 2476},
- {"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1168, 32, 2488},
- {"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1169, 32, 2520},
- {"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1170, 2, 2552},
- {"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1171, 4, 2554},
- {"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1172, 13, 2558},
- {"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 1173, 10, 2571},
- {"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1174, 10, 2581},
- {"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1175, 2, 2591},
- {"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 1176, 6, 2593},
- {"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 1177, 5, 2599},
- {"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 1178, 6, 2604},
- {"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 1179, 5, 2610},
- {"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 1180, 1, 2615},
- {"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1181, 13, 2616},
- {"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 1182, 2, 2629},
- {"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1183, 2, 2631},
- {"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 1184, 11, 2633},
- {"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1192, 3, 2644},
- {"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1193, 12, 2647},
- {"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 1201, 12, 2659},
- {"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 1209, 6, 2671},
- {"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1217, 4, 2677},
- {"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 1225, 2, 2681},
- {"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 1226, 2, 2683},
- {"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 1227, 15, 2685},
- {"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1228, 2, 2700},
- {"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1229, 3, 2702},
- {"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 1230, 1, 2705},
- {"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1238, 6, 2706},
- {"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1239, 4, 2712},
- {"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1240, 15, 2716},
- {"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1241, 6, 2731},
- {"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1242, 2, 2737},
- {"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1243, 2, 2739},
- {"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1244, 2, 2741},
- {"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1245, 2, 2743},
- {"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1246, 2, 2745},
- {"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1247, 2, 2747},
- {"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1248, 2, 2749},
- {"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1249, 2, 2751},
- {"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1250, 2, 2753},
- {"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1251, 2, 2755},
- {"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1252, 2, 2757},
- {"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1253, 2, 2759},
- {"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1254, 2, 2761},
- {"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1255, 2, 2763},
- {"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1256, 2, 2765},
- {"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1257, 2, 2767},
- {"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 1258, 7, 2769},
- {"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1259, 39, 2776},
- {"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1260, 39, 2815},
- {"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1261, 22, 2854},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"ASX0_GMII_RX_CLK_SET" , 0x11800b0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX0_GMII_RX_DAT_SET" , 0x11800b0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX0_INT_EN" , 0x11800b0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX0_INT_REG" , 0x11800b0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX0_MII_RX_DAT_SET" , 0x11800b0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX0_PRT_LOOP" , 0x11800b0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX0_RX_CLK_SET000" , 0x11800b0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_RX_CLK_SET001" , 0x11800b0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_RX_CLK_SET002" , 0x11800b0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_RX_PRT_EN" , 0x11800b0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX0_TX_CLK_SET000" , 0x11800b0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_TX_CLK_SET001" , 0x11800b0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_TX_CLK_SET002" , 0x11800b0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_TX_COMP_BYP" , 0x11800b0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX0_TX_HI_WATER000" , 0x11800b0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX0_TX_HI_WATER001" , 0x11800b0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX0_TX_HI_WATER002" , 0x11800b0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX0_TX_PRT_EN" , 0x11800b0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"DBG_DATA" , 0x11f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_RX_TX_STATUS" , 0x11800080007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_TX001_CLK" , 0x1180008000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_TX_CLK_MSK000" , 0x1180008000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_TX_CLK_MSK001" , 0x1180008000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"GPIO_BOOT_ENA" , 0x10700000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"GPIO_DBG_ENA" , 0x10700000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"GPIO_XBIT_CFG16" , 0x1070000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"GPIO_XBIT_CFG17" , 0x1070000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"GPIO_XBIT_CFG18" , 0x1070000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"GPIO_XBIT_CFG19" , 0x1070000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"GPIO_XBIT_CFG20" , 0x1070000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"GPIO_XBIT_CFG21" , 0x1070000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"GPIO_XBIT_CFG22" , 0x1070000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"GPIO_XBIT_CFG23" , 0x1070000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"LMC0_PLL_BWCTL" , 0x1180088000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"MIO_FUS_UNLOCK" , 0x1180000001578ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"MIO_PLL_CTL" , 0x1180000001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"MIO_PLL_SETTING" , 0x1180000001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"MPI_CFG" , 0x1070000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 267},
- {"MPI_DAT0" , 0x1070000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"MPI_DAT1" , 0x1070000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"MPI_DAT2" , 0x1070000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"MPI_DAT3" , 0x1070000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"MPI_DAT4" , 0x10700000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"MPI_DAT5" , 0x10700000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"MPI_DAT6" , 0x10700000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"MPI_DAT7" , 0x10700000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"MPI_DAT8" , 0x10700000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"MPI_STS" , 0x1070000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 269},
- {"MPI_TX" , 0x1070000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"NPI_BASE_ADDR_INPUT0" , 0x11f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"NPI_BASE_ADDR_OUTPUT0" , 0x11f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 272},
- {"NPI_BIST_STATUS" , 0x11f00000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 273},
- {"NPI_BUFF_SIZE_OUTPUT0" , 0x11f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 274},
- {"NPI_CTL_STATUS" , 0x11f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 275},
- {"NPI_DBG_SELECT" , 0x11f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"NPI_DMA_CONTROL" , 0x11f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"NPI_DMA_HIGHP_COUNTS" , 0x11f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 278},
- {"NPI_DMA_HIGHP_NADDR" , 0x11f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 279},
- {"NPI_DMA_LOWP_COUNTS" , 0x11f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 280},
- {"NPI_DMA_LOWP_NADDR" , 0x11f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 281},
- {"NPI_HIGHP_DBELL" , 0x11f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 282},
- {"NPI_HIGHP_IBUFF_SADDR" , 0x11f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 283},
- {"NPI_INPUT_CONTROL" , 0x11f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 284},
- {"NPI_INT_ENB" , 0x11f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 285},
- {"NPI_INT_SUM" , 0x11f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"NPI_LOWP_DBELL" , 0x11f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 287},
- {"NPI_LOWP_IBUFF_SADDR" , 0x11f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 288},
- {"NPI_MEM_ACCESS_SUBID3" , 0x11f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"NPI_MEM_ACCESS_SUBID4" , 0x11f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"NPI_MEM_ACCESS_SUBID5" , 0x11f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"NPI_MEM_ACCESS_SUBID6" , 0x11f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"NPI_MSI_RCV" , 0x11f0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 290},
- {"NPI_NUM_DESC_OUTPUT0" , 0x11f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
- {"NPI_OUTPUT_CONTROL" , 0x11f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"NPI_P0_DBPAIR_ADDR" , 0x11f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
- {"NPI_P0_INSTR_ADDR" , 0x11f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 294},
- {"NPI_P0_INSTR_CNTS" , 0x11f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"NPI_P0_PAIR_CNTS" , 0x11f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
- {"NPI_PCI_BURST_SIZE" , 0x11f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 297},
- {"NPI_PCI_INT_ARB_CFG" , 0x11f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 298},
- {"NPI_PCI_READ_CMD" , 0x11f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
- {"NPI_PORT32_INSTR_HDR" , 0x11f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
- {"NPI_PORT_BP_CONTROL" , 0x11f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
- {"NPI_RSL_INT_BLOCKS" , 0x11f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 302},
- {"NPI_SIZE_INPUT0" , 0x11f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 303},
- {"NPI_WIN_READ_TO" , 0x11f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 304},
- {"PCI_BAR1_INDEX0" , 0x11f0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX1" , 0x11f0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX2" , 0x11f0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX3" , 0x11f000000110cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX4" , 0x11f0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX5" , 0x11f0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX6" , 0x11f0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX7" , 0x11f000000111cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX8" , 0x11f0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX9" , 0x11f0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX10" , 0x11f0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX11" , 0x11f000000112cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX12" , 0x11f0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX13" , 0x11f0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX14" , 0x11f0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX15" , 0x11f000000113cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX16" , 0x11f0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX17" , 0x11f0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX18" , 0x11f0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX19" , 0x11f000000114cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX20" , 0x11f0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX21" , 0x11f0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX22" , 0x11f0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX23" , 0x11f000000115cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX24" , 0x11f0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX25" , 0x11f0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX26" , 0x11f0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX27" , 0x11f000000116cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX28" , 0x11f0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX29" , 0x11f0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX30" , 0x11f0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_BAR1_INDEX31" , 0x11f000000117cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
- {"PCI_CFG00" , 0x11f0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 306},
- {"PCI_CFG01" , 0x11f0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 307},
- {"PCI_CFG02" , 0x11f0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 308},
- {"PCI_CFG03" , 0x11f000000180cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 309},
- {"PCI_CFG04" , 0x11f0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 310},
- {"PCI_CFG05" , 0x11f0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 311},
- {"PCI_CFG06" , 0x11f0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 312},
- {"PCI_CFG07" , 0x11f000000181cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 313},
- {"PCI_CFG08" , 0x11f0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 314},
- {"PCI_CFG09" , 0x11f0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 315},
- {"PCI_CFG10" , 0x11f0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 316},
- {"PCI_CFG11" , 0x11f000000182cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 317},
- {"PCI_CFG12" , 0x11f0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 318},
- {"PCI_CFG13" , 0x11f0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 319},
- {"PCI_CFG15" , 0x11f000000183cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 320},
- {"PCI_CFG16" , 0x11f0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 321},
- {"PCI_CFG17" , 0x11f0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 322},
- {"PCI_CFG18" , 0x11f0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 323},
- {"PCI_CFG19" , 0x11f000000184cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 324},
- {"PCI_CFG20" , 0x11f0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 325},
- {"PCI_CFG21" , 0x11f0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 326},
- {"PCI_CFG22" , 0x11f0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 327},
- {"PCI_CFG56" , 0x11f00000018e0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 328},
- {"PCI_CFG57" , 0x11f00000018e4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 329},
- {"PCI_CFG58" , 0x11f00000018e8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 330},
- {"PCI_CFG59" , 0x11f00000018ecull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 331},
- {"PCI_CFG60" , 0x11f00000018f0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 332},
- {"PCI_CFG61" , 0x11f00000018f4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 333},
- {"PCI_CFG62" , 0x11f00000018f8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 334},
- {"PCI_CFG63" , 0x11f00000018fcull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 335},
- {"PCI_CTL_STATUS_2" , 0x11f000000118cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 336},
- {"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 337},
- {"PCI_DMA_CNT0" , 0xa0ull, CVMX_CSR_DB_TYPE_PCI, 32, 338},
- {"PCI_DMA_CNT1" , 0xa8ull, CVMX_CSR_DB_TYPE_PCI, 32, 338},
- {"PCI_DMA_INT_LEV0" , 0xa4ull, CVMX_CSR_DB_TYPE_PCI, 32, 339},
- {"PCI_DMA_INT_LEV1" , 0xacull, CVMX_CSR_DB_TYPE_PCI, 32, 339},
- {"PCI_DMA_TIME0" , 0xb0ull, CVMX_CSR_DB_TYPE_PCI, 32, 340},
- {"PCI_DMA_TIME1" , 0xb4ull, CVMX_CSR_DB_TYPE_PCI, 32, 340},
- {"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 341},
- {"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 342},
- {"PCI_INT_ENB2" , 0x11f00000011a0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 343},
- {"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 344},
- {"PCI_INT_SUM2" , 0x11f0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 345},
- {"PCI_MSI_RCV" , 0xf0ull, CVMX_CSR_DB_TYPE_PCI, 32, 346},
- {"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 347},
- {"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 348},
- {"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 349},
- {"PCI_PKTS_SENT_TIME0" , 0x4cull, CVMX_CSR_DB_TYPE_PCI, 32, 350},
- {"PCI_READ_CMD_6" , 0x11f0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 351},
- {"PCI_READ_CMD_C" , 0x11f0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 352},
- {"PCI_READ_CMD_E" , 0x11f0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
- {"PCI_READ_TIMEOUT" , 0x11f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"PCI_SCM_REG" , 0x11f00000011a8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 355},
- {"PCI_TSR_REG" , 0x11f00000011b0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 356},
- {"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 357},
- {"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 358},
- {"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 359},
- {"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 360},
- {"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 361},
- {"PCM0_DMA_CFG" , 0x1070000010018ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
- {"PCM1_DMA_CFG" , 0x1070000014018ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
- {"PCM2_DMA_CFG" , 0x1070000018018ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
- {"PCM3_DMA_CFG" , 0x107000001c018ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
- {"PCM0_INT_ENA" , 0x1070000010020ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
- {"PCM1_INT_ENA" , 0x1070000014020ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
- {"PCM2_INT_ENA" , 0x1070000018020ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
- {"PCM3_INT_ENA" , 0x107000001c020ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
- {"PCM0_INT_SUM" , 0x1070000010028ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
- {"PCM1_INT_SUM" , 0x1070000014028ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
- {"PCM2_INT_SUM" , 0x1070000018028ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
- {"PCM3_INT_SUM" , 0x107000001c028ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
- {"PCM0_RXADDR" , 0x1070000010068ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
- {"PCM1_RXADDR" , 0x1070000014068ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
- {"PCM2_RXADDR" , 0x1070000018068ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
- {"PCM3_RXADDR" , 0x107000001c068ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
- {"PCM0_RXCNT" , 0x1070000010060ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
- {"PCM1_RXCNT" , 0x1070000014060ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
- {"PCM2_RXCNT" , 0x1070000018060ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
- {"PCM3_RXCNT" , 0x107000001c060ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
- {"PCM0_RXMSK0" , 0x10700000100c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
- {"PCM1_RXMSK0" , 0x10700000140c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
- {"PCM2_RXMSK0" , 0x10700000180c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
- {"PCM3_RXMSK0" , 0x107000001c0c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
- {"PCM0_RXMSK1" , 0x10700000100c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
- {"PCM1_RXMSK1" , 0x10700000140c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
- {"PCM2_RXMSK1" , 0x10700000180c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
- {"PCM3_RXMSK1" , 0x107000001c0c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
- {"PCM0_RXMSK2" , 0x10700000100d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
- {"PCM1_RXMSK2" , 0x10700000140d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
- {"PCM2_RXMSK2" , 0x10700000180d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
- {"PCM3_RXMSK2" , 0x107000001c0d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
- {"PCM0_RXMSK3" , 0x10700000100d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
- {"PCM1_RXMSK3" , 0x10700000140d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
- {"PCM2_RXMSK3" , 0x10700000180d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
- {"PCM3_RXMSK3" , 0x107000001c0d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
- {"PCM0_RXMSK4" , 0x10700000100e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"PCM1_RXMSK4" , 0x10700000140e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"PCM2_RXMSK4" , 0x10700000180e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"PCM3_RXMSK4" , 0x107000001c0e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"PCM0_RXMSK5" , 0x10700000100e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
- {"PCM1_RXMSK5" , 0x10700000140e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
- {"PCM2_RXMSK5" , 0x10700000180e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
- {"PCM3_RXMSK5" , 0x107000001c0e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
- {"PCM0_RXMSK6" , 0x10700000100f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"PCM1_RXMSK6" , 0x10700000140f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"PCM2_RXMSK6" , 0x10700000180f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"PCM3_RXMSK6" , 0x107000001c0f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"PCM0_RXMSK7" , 0x10700000100f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
- {"PCM1_RXMSK7" , 0x10700000140f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
- {"PCM2_RXMSK7" , 0x10700000180f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
- {"PCM3_RXMSK7" , 0x107000001c0f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
- {"PCM0_RXSTART" , 0x1070000010058ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"PCM1_RXSTART" , 0x1070000014058ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"PCM2_RXSTART" , 0x1070000018058ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"PCM3_RXSTART" , 0x107000001c058ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"PCM0_TDM_CFG" , 0x1070000010010ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"PCM1_TDM_CFG" , 0x1070000014010ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"PCM2_TDM_CFG" , 0x1070000018010ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"PCM3_TDM_CFG" , 0x107000001c010ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"PCM0_TDM_DBG" , 0x1070000010030ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"PCM1_TDM_DBG" , 0x1070000014030ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"PCM2_TDM_DBG" , 0x1070000018030ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"PCM3_TDM_DBG" , 0x107000001c030ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"PCM0_TXADDR" , 0x1070000010050ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"PCM1_TXADDR" , 0x1070000014050ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"PCM2_TXADDR" , 0x1070000018050ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"PCM3_TXADDR" , 0x107000001c050ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"PCM0_TXCNT" , 0x1070000010048ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"PCM1_TXCNT" , 0x1070000014048ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"PCM2_TXCNT" , 0x1070000018048ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"PCM3_TXCNT" , 0x107000001c048ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"PCM0_TXMSK0" , 0x1070000010080ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"PCM1_TXMSK0" , 0x1070000014080ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"PCM2_TXMSK0" , 0x1070000018080ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"PCM3_TXMSK0" , 0x107000001c080ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"PCM0_TXMSK1" , 0x1070000010088ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM1_TXMSK1" , 0x1070000014088ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM2_TXMSK1" , 0x1070000018088ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM3_TXMSK1" , 0x107000001c088ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM0_TXMSK2" , 0x1070000010090ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM1_TXMSK2" , 0x1070000014090ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM2_TXMSK2" , 0x1070000018090ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM3_TXMSK2" , 0x107000001c090ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM0_TXMSK3" , 0x1070000010098ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM1_TXMSK3" , 0x1070000014098ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM2_TXMSK3" , 0x1070000018098ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM3_TXMSK3" , 0x107000001c098ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM0_TXMSK4" , 0x10700000100a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM1_TXMSK4" , 0x10700000140a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM2_TXMSK4" , 0x10700000180a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM3_TXMSK4" , 0x107000001c0a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM0_TXMSK5" , 0x10700000100a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM1_TXMSK5" , 0x10700000140a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM2_TXMSK5" , 0x10700000180a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM3_TXMSK5" , 0x107000001c0a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM0_TXMSK6" , 0x10700000100b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM1_TXMSK6" , 0x10700000140b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM2_TXMSK6" , 0x10700000180b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM3_TXMSK6" , 0x107000001c0b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM0_TXMSK7" , 0x10700000100b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM1_TXMSK7" , 0x10700000140b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM2_TXMSK7" , 0x10700000180b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM3_TXMSK7" , 0x107000001c0b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM0_TXSTART" , 0x1070000010040ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM1_TXSTART" , 0x1070000014040ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM2_TXSTART" , 0x1070000018040ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM3_TXSTART" , 0x107000001c040ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM_CLK0_CFG" , 0x1070000010000ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"PCM_CLK1_CFG" , 0x1070000014000ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"PCM_CLK0_DBG" , 0x1070000010038ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"PCM_CLK1_DBG" , 0x1070000014038ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"PCM_CLK0_GEN" , 0x1070000010008ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"PCM_CLK1_GEN" , 0x1070000014008ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 454},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 455},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 458},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 459},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 463},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 466},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 468},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"USBC0_DAINT" , 0x16f0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 488},
- {"USBC0_DAINTMSK" , 0x16f001000081cull, CVMX_CSR_DB_TYPE_NCB, 32, 489},
- {"USBC0_DCFG" , 0x16f0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 490},
- {"USBC0_DCTL" , 0x16f0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 491},
- {"USBC0_DIEPCTL000" , 0x16f0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 492},
- {"USBC0_DIEPCTL001" , 0x16f0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 492},
- {"USBC0_DIEPCTL002" , 0x16f0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 492},
- {"USBC0_DIEPCTL003" , 0x16f0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 492},
- {"USBC0_DIEPCTL004" , 0x16f0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 492},
- {"USBC0_DIEPINT000" , 0x16f0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 493},
- {"USBC0_DIEPINT001" , 0x16f0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 493},
- {"USBC0_DIEPINT002" , 0x16f0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 493},
- {"USBC0_DIEPINT003" , 0x16f0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 493},
- {"USBC0_DIEPINT004" , 0x16f0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 493},
- {"USBC0_DIEPMSK" , 0x16f0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 494},
- {"USBC0_DIEPTSIZ000" , 0x16f0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 495},
- {"USBC0_DIEPTSIZ001" , 0x16f0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 495},
- {"USBC0_DIEPTSIZ002" , 0x16f0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 495},
- {"USBC0_DIEPTSIZ003" , 0x16f0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 495},
- {"USBC0_DIEPTSIZ004" , 0x16f0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 495},
- {"USBC0_DOEPCTL000" , 0x16f0010000b00ull, CVMX_CSR_DB_TYPE_NCB, 32, 496},
- {"USBC0_DOEPCTL001" , 0x16f0010000b20ull, CVMX_CSR_DB_TYPE_NCB, 32, 496},
- {"USBC0_DOEPCTL002" , 0x16f0010000b40ull, CVMX_CSR_DB_TYPE_NCB, 32, 496},
- {"USBC0_DOEPCTL003" , 0x16f0010000b60ull, CVMX_CSR_DB_TYPE_NCB, 32, 496},
- {"USBC0_DOEPCTL004" , 0x16f0010000b80ull, CVMX_CSR_DB_TYPE_NCB, 32, 496},
- {"USBC0_DOEPINT000" , 0x16f0010000b08ull, CVMX_CSR_DB_TYPE_NCB, 32, 497},
- {"USBC0_DOEPINT001" , 0x16f0010000b28ull, CVMX_CSR_DB_TYPE_NCB, 32, 497},
- {"USBC0_DOEPINT002" , 0x16f0010000b48ull, CVMX_CSR_DB_TYPE_NCB, 32, 497},
- {"USBC0_DOEPINT003" , 0x16f0010000b68ull, CVMX_CSR_DB_TYPE_NCB, 32, 497},
- {"USBC0_DOEPINT004" , 0x16f0010000b88ull, CVMX_CSR_DB_TYPE_NCB, 32, 497},
- {"USBC0_DOEPMSK" , 0x16f0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 498},
- {"USBC0_DOEPTSIZ000" , 0x16f0010000b10ull, CVMX_CSR_DB_TYPE_NCB, 32, 499},
- {"USBC0_DOEPTSIZ001" , 0x16f0010000b30ull, CVMX_CSR_DB_TYPE_NCB, 32, 499},
- {"USBC0_DOEPTSIZ002" , 0x16f0010000b50ull, CVMX_CSR_DB_TYPE_NCB, 32, 499},
- {"USBC0_DOEPTSIZ003" , 0x16f0010000b70ull, CVMX_CSR_DB_TYPE_NCB, 32, 499},
- {"USBC0_DOEPTSIZ004" , 0x16f0010000b90ull, CVMX_CSR_DB_TYPE_NCB, 32, 499},
- {"USBC0_DPTXFSIZ001" , 0x16f0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 500},
- {"USBC0_DPTXFSIZ002" , 0x16f0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 500},
- {"USBC0_DPTXFSIZ003" , 0x16f001000010cull, CVMX_CSR_DB_TYPE_NCB, 32, 500},
- {"USBC0_DPTXFSIZ004" , 0x16f0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 500},
- {"USBC0_DSTS" , 0x16f0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 501},
- {"USBC0_DTKNQR1" , 0x16f0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 502},
- {"USBC0_DTKNQR2" , 0x16f0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 503},
- {"USBC0_DTKNQR3" , 0x16f0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 504},
- {"USBC0_DTKNQR4" , 0x16f0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 505},
- {"USBC0_GAHBCFG" , 0x16f0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 506},
- {"USBC0_GHWCFG1" , 0x16f0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 507},
- {"USBC0_GHWCFG2" , 0x16f0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 508},
- {"USBC0_GHWCFG3" , 0x16f001000004cull, CVMX_CSR_DB_TYPE_NCB, 32, 509},
- {"USBC0_GHWCFG4" , 0x16f0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
- {"USBC0_GINTMSK" , 0x16f0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
- {"USBC0_GINTSTS" , 0x16f0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 512},
- {"USBC0_GNPTXFSIZ" , 0x16f0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
- {"USBC0_GNPTXSTS" , 0x16f001000002cull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
- {"USBC0_GOTGCTL" , 0x16f0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
- {"USBC0_GOTGINT" , 0x16f0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 516},
- {"USBC0_GRSTCTL" , 0x16f0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
- {"USBC0_GRXFSIZ" , 0x16f0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 518},
- {"USBC0_GRXSTSPD" , 0x16f0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 519},
- {"USBC0_GRXSTSPH" , 0x16f0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 520},
- {"USBC0_GRXSTSRD" , 0x16f001004001cull, CVMX_CSR_DB_TYPE_NCB, 32, 521},
- {"USBC0_GRXSTSRH" , 0x16f001000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 522},
- {"USBC0_GSNPSID" , 0x16f0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 523},
- {"USBC0_GUSBCFG" , 0x16f001000000cull, CVMX_CSR_DB_TYPE_NCB, 32, 524},
- {"USBC0_HAINT" , 0x16f0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 525},
- {"USBC0_HAINTMSK" , 0x16f0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 526},
- {"USBC0_HCCHAR000" , 0x16f0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
- {"USBC0_HCCHAR001" , 0x16f0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
- {"USBC0_HCCHAR002" , 0x16f0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
- {"USBC0_HCCHAR003" , 0x16f0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
- {"USBC0_HCCHAR004" , 0x16f0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
- {"USBC0_HCCHAR005" , 0x16f00100005a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
- {"USBC0_HCCHAR006" , 0x16f00100005c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
- {"USBC0_HCCHAR007" , 0x16f00100005e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
- {"USBC0_HCFG" , 0x16f0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 528},
- {"USBC0_HCINT000" , 0x16f0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
- {"USBC0_HCINT001" , 0x16f0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
- {"USBC0_HCINT002" , 0x16f0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
- {"USBC0_HCINT003" , 0x16f0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
- {"USBC0_HCINT004" , 0x16f0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
- {"USBC0_HCINT005" , 0x16f00100005a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
- {"USBC0_HCINT006" , 0x16f00100005c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
- {"USBC0_HCINT007" , 0x16f00100005e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
- {"USBC0_HCINTMSK000" , 0x16f001000050cull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
- {"USBC0_HCINTMSK001" , 0x16f001000052cull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
- {"USBC0_HCINTMSK002" , 0x16f001000054cull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
- {"USBC0_HCINTMSK003" , 0x16f001000056cull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
- {"USBC0_HCINTMSK004" , 0x16f001000058cull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
- {"USBC0_HCINTMSK005" , 0x16f00100005acull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
- {"USBC0_HCINTMSK006" , 0x16f00100005ccull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
- {"USBC0_HCINTMSK007" , 0x16f00100005ecull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
- {"USBC0_HCSPLT000" , 0x16f0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_HCSPLT001" , 0x16f0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_HCSPLT002" , 0x16f0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_HCSPLT003" , 0x16f0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_HCSPLT004" , 0x16f0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_HCSPLT005" , 0x16f00100005a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_HCSPLT006" , 0x16f00100005c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_HCSPLT007" , 0x16f00100005e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_HCTSIZ000" , 0x16f0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_HCTSIZ001" , 0x16f0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_HCTSIZ002" , 0x16f0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_HCTSIZ003" , 0x16f0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_HCTSIZ004" , 0x16f0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_HCTSIZ005" , 0x16f00100005b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_HCTSIZ006" , 0x16f00100005d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_HCTSIZ007" , 0x16f00100005f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_HFIR" , 0x16f0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 533},
- {"USBC0_HFNUM" , 0x16f0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
- {"USBC0_HPRT" , 0x16f0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
- {"USBC0_HPTXFSIZ" , 0x16f0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
- {"USBC0_HPTXSTS" , 0x16f0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 537},
- {"USBC0_NPTXDFIFO000" , 0x16f0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_NPTXDFIFO001" , 0x16f0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_NPTXDFIFO002" , 0x16f0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_NPTXDFIFO003" , 0x16f0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_NPTXDFIFO004" , 0x16f0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_NPTXDFIFO005" , 0x16f0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_NPTXDFIFO006" , 0x16f0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_NPTXDFIFO007" , 0x16f0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_PCGCCTL" , 0x16f0010000e00ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
- {"USBN0_BIST_STATUS" , 0x11800680007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"USBN0_CTL_STATUS" , 0x16f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 542},
- {"USBN0_DMA0_INB_CHN0" , 0x16f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 543},
- {"USBN0_DMA0_INB_CHN1" , 0x16f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 544},
- {"USBN0_DMA0_INB_CHN2" , 0x16f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 545},
- {"USBN0_DMA0_INB_CHN3" , 0x16f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 546},
- {"USBN0_DMA0_INB_CHN4" , 0x16f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 547},
- {"USBN0_DMA0_INB_CHN5" , 0x16f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 548},
- {"USBN0_DMA0_INB_CHN6" , 0x16f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 549},
- {"USBN0_DMA0_INB_CHN7" , 0x16f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 550},
- {"USBN0_DMA0_OUTB_CHN0" , 0x16f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 551},
- {"USBN0_DMA0_OUTB_CHN1" , 0x16f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 552},
- {"USBN0_DMA0_OUTB_CHN2" , 0x16f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 553},
- {"USBN0_DMA0_OUTB_CHN3" , 0x16f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 554},
- {"USBN0_DMA0_OUTB_CHN4" , 0x16f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 555},
- {"USBN0_DMA0_OUTB_CHN5" , 0x16f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 556},
- {"USBN0_DMA0_OUTB_CHN6" , 0x16f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 557},
- {"USBN0_DMA0_OUTB_CHN7" , 0x16f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 558},
- {"USBN0_DMA_TEST" , 0x16f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 559},
- {"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"SETTING" , 0, 5, 0, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 0, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 1, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 0, 3, 2, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_3" , 3, 1, 2, "RAZ", 1, 1, 0, 0},
- {"TXPOP" , 4, 3, 2, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
- {"TXPSH" , 8, 3, 2, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_11_63" , 11, 53, 2, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 0, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 3, "RAZ", 1, 1, 0, 0},
- {"TXPOP" , 4, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 3, "RAZ", 1, 1, 0, 0},
- {"TXPSH" , 8, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 3, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 4, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
- {"INT_LOOP" , 0, 3, 5, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 5, "RAZ", 1, 1, 0, 0},
- {"EXT_LOOP" , 4, 3, 5, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 5, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 6, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 6, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 3, 7, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 7, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 8, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 9, "R/W", 0, 0, 8ull, 8ull},
- {"PCTL" , 4, 4, 9, "R/W", 0, 0, 8ull, 8ull},
- {"BYPASS" , 8, 1, 9, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 9, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 3, 10, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 10, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 3, 11, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 11, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 4, 12, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 12, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 1, 13, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 13, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 1, 14, "RO", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 14, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 15, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 16, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 16, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 16, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 16, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 16, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_47" , 47, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 16, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 16, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 17, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 18, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 18, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 18, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 18, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 18, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 18, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 18, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 18, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 18, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_47_47" , 47, 1, 18, "RAZ", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 18, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 18, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 52, 4, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 18, "RO", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 18, "RO", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 18, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 1, 19, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 19, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 20, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 21, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 21, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 1, 22, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 22, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 23, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 1, 24, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 24, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 25, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 26, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 26, "RAZ", 1, 1, 0, 0},
- {"SOFT_BIST" , 0, 1, 27, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 27, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 28, "R/W", 0, 0, 1ull, 0ull},
- {"NPI" , 1, 1, 28, "R/W", 0, 0, 0ull, 0ull},
- {"HOST64" , 2, 1, 28, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 28, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 29, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 29, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 30, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 30, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 30, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 31, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 31, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 31, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 31, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 31, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 31, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 31, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 32, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 32, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 32, "RO", 1, 1, 0, 0},
- {"RESERVED_23_27" , 23, 5, 32, "RAZ", 1, 1, 0, 0},
- {"PLL_MUL" , 28, 3, 32, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 32, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 33, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 34, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 34, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 34, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 34, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 34, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 34, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 34, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 35, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 35, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 36, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 37, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 38, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 38, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 39, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 39, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 39, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 40, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 40, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 40, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 41, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 41, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 42, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 42, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 43, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 3, 43, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_21" , 5, 17, 43, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 3, 43, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_25" , 25, 1, 43, "RAZ", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 43, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 43, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 43, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 10, 44, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 44, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 45, "R/W", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 45, "R/W", 0, 0, 0ull, 1ull},
- {"P0MII" , 2, 1, 45, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 45, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 46, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 46, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 47, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 47, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 47, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 47, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_63" , 4, 60, 47, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 48, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 49, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 50, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 51, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 52, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 53, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 54, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 54, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 55, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 55, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 55, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 55, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 56, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 56, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 57, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 58, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 58, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 58, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 58, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 58, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 58, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_FREE" , 6, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"VLAN_LEN" , 7, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 58, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 59, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 59, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 60, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 60, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 61, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 61, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 62, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 62, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 63, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 64, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 64, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 65, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 65, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 65, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 65, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 66, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 66, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 67, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 67, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 68, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 68, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 69, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 70, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 70, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 71, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 71, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 72, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 72, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 73, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 73, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 74, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 74, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 75, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 75, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 76, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 76, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 77, "R/W", 1, 1, 0, 0},
- {"RESERVED_6_63" , 6, 58, 77, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 78, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 78, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 79, "R/W", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 79, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 3, 80, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_15" , 3, 13, 80, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 3, 80, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 80, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 81, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_3_63" , 3, 61, 81, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 3, 82, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 82, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 3, 82, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 82, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 83, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 83, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 84, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 84, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 85, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 85, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 85, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 85, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 85, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 86, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 86, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 87, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 87, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 88, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 88, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 88, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 89, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 89, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 90, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 90, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 91, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 91, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 92, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 92, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 93, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 94, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 94, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 95, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 95, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 96, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 96, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 97, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 97, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 98, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 98, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 99, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 99, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 100, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 100, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 101, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 101, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 102, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 102, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 103, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 103, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 104, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 104, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 105, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 105, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 106, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 106, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 7, 107, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_7_63" , 7, 57, 107, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 3, 108, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 108, "RAZ", 1, 1, 0, 0},
- {"MSK" , 0, 1, 109, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 109, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 110, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 110, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 3, 111, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_3_63" , 3, 61, 111, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 112, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 112, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 112, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 113, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 3, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 113, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 3, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 113, "RAZ", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 3, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 113, "RAZ", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 3, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 113, "RAZ", 0, 0, 0ull, 0ull},
- {"PKO_NXA" , 0, 1, 114, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 114, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 3, 114, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 114, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 3, 114, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 114, "RAZ", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 3, 114, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 114, "RAZ", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 3, 114, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 114, "RAZ", 0, 0, 0ull, 0ull},
- {"JAM" , 0, 8, 115, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 115, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 116, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 116, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 3, 117, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 117, "RAZ", 0, 0, 0ull, 0ull},
- {"BP" , 4, 3, 117, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 117, "RAZ", 0, 0, 0ull, 0ull},
- {"EN" , 8, 3, 117, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 117, "RAZ", 0, 0, 0ull, 0ull},
- {"DMAC" , 0, 48, 118, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 118, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 119, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 119, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 120, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_5_63" , 5, 59, 120, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 121, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 121, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 122, "RAZ", 1, 1, 0, 0},
- {"BOOT_ENA" , 8, 4, 122, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 122, "RAZ", 1, 1, 0, 0},
- {"DBG_ENA" , 0, 21, 123, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 123, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 124, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 124, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 24, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 125, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 24, 126, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 126, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 24, 127, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 127, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 128, "RAZ", 1, 1, 0, 0},
- {"FIL_CNT" , 4, 4, 128, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 128, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 128, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 129, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 130, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 130, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 130, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 130, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 131, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 131, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 131, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 132, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 132, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 132, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 132, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 132, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 133, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 133, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 133, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 133, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 133, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 134, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 135, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 136, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 137, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 138, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 138, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 138, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 138, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 138, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 139, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 139, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 139, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 139, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 139, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 140, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 141, "R/W", 0, 1, 0ull, 0},
- {"PORT" , 0, 6, 142, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 142, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 143, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 143, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 144, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 144, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 145, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 146, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 147, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 147, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 148, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 149, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 149, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 149, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 150, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 151, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 151, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 151, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 151, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 151, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 151, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 152, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 152, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 153, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 153, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 154, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 154, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 155, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 155, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 155, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 156, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 156, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 3, 157, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 157, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 157, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 157, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 157, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 157, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 158, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 158, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 158, "RO", 0, 0, 4ull, 4ull},
- {"RESERVED_44_63" , 44, 20, 158, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 159, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 159, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 159, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 159, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 159, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 159, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 160, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 160, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 160, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 160, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 160, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 160, "RO", 0, 0, 8ull, 8ull},
- {"RESERVED_61_63" , 61, 3, 160, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 161, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 161, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 162, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 162, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 163, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 163, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 163, "R/W", 0, 0, 0ull, 0ull},
- {"PRB_CON" , 0, 32, 164, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 164, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 164, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 164, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 164, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 165, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 165, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 165, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 3, 166, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_3_63" , 3, 61, 166, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 167, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 167, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 168, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 168, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 169, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 169, "RAZ", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 169, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 9, 169, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_18" , 15, 4, 169, "RAZ", 0, 0, 0ull, 0ull},
- {"WLB_MSK" , 19, 4, 169, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 169, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 5, 170, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_8" , 5, 4, 170, "RAZ", 0, 0, 0ull, 0ull},
- {"VAB_VWCF" , 9, 1, 170, "RO", 0, 0, 0ull, 0ull},
- {"LRF" , 10, 2, 170, "RO", 0, 0, 0ull, 0ull},
- {"VWDF" , 12, 4, 170, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 170, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 171, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 171, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 171, "RAZ", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 171, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 171, "RAZ", 0, 0, 0ull, 0ull},
- {"RMDF" , 8, 4, 171, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 171, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 171, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 172, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 172, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 172, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 172, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 172, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 172, "RAZ", 1, 1, 0, 0},
- {"L2T" , 0, 1, 173, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 173, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 173, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 2, 173, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_5" , 5, 1, 173, "RAZ", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 1, 173, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_7_9" , 7, 3, 173, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 173, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 2, 173, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 173, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 174, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 174, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 174, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 174, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 175, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 175, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 176, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 177, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 177, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 177, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 2, 177, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_17" , 16, 2, 177, "RAZ", 0, 0, 0ull, 0ull},
- {"SET" , 18, 2, 177, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 177, "RAZ", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 177, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 177, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 2, 177, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_26" , 25, 2, 177, "RAZ", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 177, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 177, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 177, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 177, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 177, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 177, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 178, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 178, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 178, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 8, 179, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 8, 19, 179, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 179, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 2, 180, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_2_3" , 2, 2, 180, "RAZ", 0, 0, 0ull, 0ull},
- {"STPARTDIS" , 4, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 180, "RAZ", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 181, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 181, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 182, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 4, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 183, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 4, 184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 184, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 185, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 185, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 185, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 186, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 186, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 187, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 187, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 188, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 188, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 189, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 189, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 189, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 189, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 189, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 189, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 9, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_10" , 9, 2, 190, "RAZ", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 2, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_13" , 13, 1, 190, "RAZ", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 190, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 191, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 191, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 192, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 192, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 192, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 193, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 193, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 194, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 195, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 195, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 196, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_64K" , 34, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 196, "RO", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 197, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 197, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 197, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 197, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 8, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_20" , 19, 2, 197, "RAZ", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 2, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 197, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 197, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_28_63" , 28, 36, 197, "RAZ", 0, 0, 0ull, 0ull},
- {"PCTL_DAT" , 0, 4, 198, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CMD" , 4, 4, 198, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CLK" , 8, 4, 198, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 198, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 198, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CMD" , 20, 4, 198, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CLK" , 24, 4, 198, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 198, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 198, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 199, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 199, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 199, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 199, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 199, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 199, "R/W", 0, 0, 0ull, 1ull},
- {"MODE32B" , 10, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 11, 1, 199, "R/W", 0, 0, 1ull, 0ull},
- {"INORDER_MRF" , 12, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 199, "RAZ", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 199, "R/W", 0, 1, 0ull, 0},
- {"PLL_BYPASS" , 16, 1, 199, "R/W", 0, 0, 1ull, 1ull},
- {"PLL_DIV2" , 17, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 199, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 199, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 199, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 199, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 199, "RAZ", 1, 1, 0, 0},
- {"DATA_LAYOUT" , 0, 2, 200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 200, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 201, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 201, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 202, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 202, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 203, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 203, "RAZ", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 203, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 203, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 203, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 203, "R/W", 0, 0, 2ull, 2ull},
- {"SILO_HC" , 21, 1, 203, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 203, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 203, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 203, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 203, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 203, "RAZ", 0, 0, 0ull, 0ull},
- {"CLK" , 0, 5, 204, "R/W", 0, 0, 0ull, 0ull},
- {"CMD" , 5, 5, 204, "R/W", 0, 0, 0ull, 0ull},
- {"DQ" , 10, 5, 204, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 204, "RAZ", 1, 1, 0, 0},
- {"MRDSYN0" , 0, 8, 205, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 205, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 205, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 205, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 206, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 206, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 206, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 206, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 207, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 207, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 208, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 208, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 209, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 209, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 209, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 209, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 209, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 209, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 209, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 209, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 209, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 209, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 209, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 209, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 209, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 210, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 210, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 210, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 210, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 210, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 210, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 210, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 210, "R/W", 0, 0, 2ull, 2ull},
- {"COMP_BYPASS" , 31, 1, 210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 210, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 211, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 211, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 212, "RAZ", 1, 1, 0, 0},
- {"BWCTL" , 0, 4, 213, "R/W", 0, 0, 0ull, 0ull},
- {"BWUPD" , 4, 1, 213, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 213, "RAZ", 1, 1, 0, 0},
- {"RODT_LO0" , 0, 4, 214, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO1" , 4, 4, 214, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO2" , 8, 4, 214, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO3" , 12, 4, 214, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI0" , 16, 4, 214, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI1" , 20, 4, 214, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI2" , 24, 4, 214, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI3" , 28, 4, 214, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 214, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 215, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D0_R1" , 8, 8, 215, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R0" , 16, 8, 215, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R1" , 24, 8, 215, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 215, "RAZ", 0, 0, 0ull, 0ull},
- {"WODT_D2_R0" , 0, 8, 216, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R1" , 8, 8, 216, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R0" , 16, 8, 216, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R1" , 24, 8, 216, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 216, "RAZ", 0, 0, 0ull, 0ull},
- {"NCBI" , 0, 1, 217, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 217, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 2, 1, 217, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_1" , 3, 1, 217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 217, "RAZ", 1, 1, 0, 0},
- {"ADR_ERR" , 0, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 218, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 219, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 219, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 219, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 220, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 220, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 220, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 221, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 221, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 221, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 221, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 221, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 222, "R/W", 1, 1, 0, 0},
- {"BASE" , 0, 16, 223, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 223, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 223, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 223, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 223, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 223, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 223, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 223, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 223, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_63" , 37, 27, 223, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 224, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 224, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 224, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 224, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 224, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 224, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 224, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 224, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 224, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 224, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 224, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 224, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 224, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 225, "R/W", 0, 0, 26ull, 26ull},
- {"RESERVED_6_7" , 6, 2, 225, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 225, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 225, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 226, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 226, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 227, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 227, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 1, 228, "RO", 1, 1, 0, 0},
- {"RESERVED_1_11" , 1, 11, 228, "RAZ", 1, 1, 0, 0},
- {"PLL_OFF" , 12, 4, 228, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 228, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 228, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 228, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 228, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 228, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 228, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 228, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 229, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 229, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 229, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 229, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 229, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 229, "RO", 1, 1, 0, 0},
- {"RESERVED_29_30" , 29, 2, 229, "RAZ", 1, 1, 0, 0},
- {"PLL_DIV4" , 31, 1, 229, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 229, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 230, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 230, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 7, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 231, "RAZ", 1, 1, 0, 0},
- {"EFUSE" , 8, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 231, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 231, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 231, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 231, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 232, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 14, 14, 232, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 28, 14, 232, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 232, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 233, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 233, "RAZ", 1, 1, 0, 0},
- {"KEY" , 0, 24, 234, "R/W", 0, 0, 0ull, 5071723ull},
- {"RESERVED_24_63" , 24, 40, 234, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 10, 235, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 235, "RAZ", 1, 1, 0, 0},
- {"BW_CTL" , 0, 5, 236, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 236, "RAZ", 0, 0, 0ull, 0ull},
- {"SETTING" , 0, 17, 237, "RO", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 237, "RAZ", 0, 0, 0ull, 0ull},
- {"ST_INT" , 0, 1, 238, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 238, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 238, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 238, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 238, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 238, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 238, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 238, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 238, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 238, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 238, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 238, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 238, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 239, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 239, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 239, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 239, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 239, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 239, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 239, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 239, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 239, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 239, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 239, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 239, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 240, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 240, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 240, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 241, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 241, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 241, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 242, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 242, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 243, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 243, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 244, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 244, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 245, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 245, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 245, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 245, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 245, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 245, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 245, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 246, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 246, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 247, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 247, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 248, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 248, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 248, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 248, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 249, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 249, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 249, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 249, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 249, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 249, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 249, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 249, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 250, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 250, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 250, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 250, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 250, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 250, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 250, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 250, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 250, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 251, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 251, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 251, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 251, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 251, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 251, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 251, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 252, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 252, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 252, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 252, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 252, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 252, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 252, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 252, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 252, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 253, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 253, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 254, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 254, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 255, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 255, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 255, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 255, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 256, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 257, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 257, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 258, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 258, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 259, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 259, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 259, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 259, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 260, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 260, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 261, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 261, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 262, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 262, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 263, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 263, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 264, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 264, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 265, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 265, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 266, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 266, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 266, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 266, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 266, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 266, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"IDLELO" , 1, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_CONT" , 2, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"WIREOR" , 3, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 4, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"INT_ENA" , 5, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"CSENA" , 6, 1, 267, "R/W", 0, 0, 0ull, 1ull},
- {"CSHI" , 7, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"IDLECLKS" , 8, 2, 267, "R/W", 0, 0, 0ull, 0ull},
- {"TRITX" , 10, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"CSLATE" , 11, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 267, "RAZ", 1, 1, 0, 0},
- {"CLKDIV" , 16, 13, 267, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 267, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 8, 268, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 268, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 269, "RAZ", 1, 1, 0, 0},
- {"RXNUM" , 8, 5, 269, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 269, "RAZ", 1, 1, 0, 0},
- {"TOTNUM" , 0, 5, 270, "WO", 1, 0, 0, 2ull},
- {"RESERVED_5_7" , 5, 3, 270, "RAZ", 1, 1, 0, 0},
- {"TXNUM" , 8, 5, 270, "WO", 1, 0, 0, 1ull},
- {"RESERVED_13_15" , 13, 3, 270, "RAZ", 1, 1, 0, 0},
- {"LEAVECS" , 16, 1, 270, "WO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 270, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 271, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 271, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 272, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 272, "R/W", 0, 1, 0ull, 0},
- {"DPI_BS" , 0, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"PDF_BS" , 1, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"DOB_BS" , 2, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"NUS_BS" , 3, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"POS_BS" , 4, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 273, "RAZ", 1, 1, 0, 0},
- {"POF0_BS" , 8, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"PIG_BS" , 9, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"PGF_BS" , 10, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"RDNL_BS" , 11, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"PCAD_BS" , 12, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"PCAC_BS" , 13, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"RDN_BS" , 14, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"PCN_BS" , 15, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"PCNC_BS" , 16, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"RDP_BS" , 17, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"DIF_BS" , 18, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"CSR_BS" , 19, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 273, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 274, "R/W", 0, 1, 1024ull, 0},
- {"ISIZE" , 16, 7, 274, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 274, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 275, "R/W", 0, 0, 0ull, 50ull},
- {"RESERVED_10_31" , 10, 22, 275, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_WORD" , 32, 5, 275, "R/W", 0, 0, 2ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 275, "RAZ", 0, 0, 0ull, 0ull},
- {"WAIT_COM" , 40, 1, 275, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_WDIS" , 41, 1, 275, "R/W", 0, 0, 0ull, 0ull},
- {"INS0_64B" , 42, 1, 275, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_45" , 43, 3, 275, "RAZ", 0, 0, 0ull, 0ull},
- {"INS0_ENB" , 46, 1, 275, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_47_49" , 47, 3, 275, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT0_ENB" , 50, 1, 275, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_51_53" , 51, 3, 275, "RAZ", 0, 0, 0ull, 0ull},
- {"DIS_PNIW" , 54, 1, 275, "R/W", 0, 0, 0ull, 1ull},
- {"CHIP_REV" , 55, 8, 275, "RO", 1, 1, 0, 0},
- {"RESERVED_63_63" , 63, 1, 275, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 276, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 276, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 0, 14, 277, "R/W", 0, 1, 0ull, 0},
- {"LP_ENB" , 14, 1, 277, "R/W", 0, 0, 0ull, 1ull},
- {"HP_ENB" , 15, 1, 277, "R/W", 0, 0, 0ull, 1ull},
- {"O_MODE" , 16, 1, 277, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 17, 2, 277, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 19, 1, 277, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 20, 1, 277, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 21, 1, 277, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 22, 3, 277, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 25, 9, 277, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 34, 1, 277, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 35, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 277, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 278, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 278, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 278, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 279, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 279, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 279, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 280, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 280, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 280, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 281, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 281, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 281, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 282, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 283, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 1, 284, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 284, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 284, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 284, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 284, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 284, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 284, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 284, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 284, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_RSL" , 2, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PO0_2SML" , 3, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_6" , 4, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
- {"I0_RTOUT" , 7, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_10" , 8, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
- {"I0_OVERF" , 11, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_12_14" , 12, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_RTOUT" , 15, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_18" , 16, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_PERR" , 19, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_22" , 20, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
- {"G0_RTOUT" , 23, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_24_26" , 24, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_PPERR" , 27, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_28_30" , 28, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_PTOUT" , 31, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_34" , 32, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
- {"I0_PPERR" , 35, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_36_38" , 36, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
- {"WIN_RTO" , 39, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"P_DPERR" , 40, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 41, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_S_E" , 42, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_A_F" , 43, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_S_E" , 44, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_A_F" , 45, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_S_E" , 46, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_A_F" , 47, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_S_E" , 48, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_A_F" , 49, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"COM_S_E" , 50, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"COM_A_F" , 51, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_S_E" , 52, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_A_F" , 53, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RWX_S_E" , 54, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RDX_S_E" , 55, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_E" , 56, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_F" , 57, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_E" , 58, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_F" , 59, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_S_E" , 60, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_A_F" , 61, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_62_63" , 62, 2, 285, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_RSL" , 2, 1, 286, "RO", 0, 0, 0ull, 0ull},
- {"PO0_2SML" , 3, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_6" , 4, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"I0_RTOUT" , 7, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_10" , 8, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"I0_OVERF" , 11, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_RTOUT" , 15, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_PERR" , 19, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_22" , 20, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"G0_RTOUT" , 23, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_24_26" , 24, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_PPERR" , 27, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_30" , 28, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_PTOUT" , 31, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_34" , 32, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"I0_PPERR" , 35, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_36_38" , 36, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"WIN_RTO" , 39, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DPERR" , 40, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 41, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_S_E" , 42, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_A_F" , 43, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_S_E" , 44, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_A_F" , 45, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_S_E" , 46, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_A_F" , 47, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_S_E" , 48, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_A_F" , 49, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_S_E" , 50, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_A_F" , 51, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_S_E" , 52, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_A_F" , 53, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RWX_S_E" , 54, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDX_S_E" , 55, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_E" , 56, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_F" , 57, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_E" , 58, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_F" , 59, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_S_E" , 60, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_A_F" , 61, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 286, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 287, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 287, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 288, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 288, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 28, 289, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 28, 1, 289, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 29, 1, 289, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 30, 1, 289, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 31, 1, 289, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 32, 2, 289, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 34, 2, 289, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 36, 1, 289, "R/W", 0, 1, 0ull, 0},
- {"SHORTL" , 37, 1, 289, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 289, "RAZ", 1, 1, 0, 0},
- {"INT_VEC" , 0, 64, 290, "R/W1C", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 32, 291, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 291, "RAZ", 1, 1, 0, 0},
- {"ROR_SL0" , 0, 1, 292, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL0" , 1, 1, 292, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL0" , 2, 2, 292, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_15" , 4, 12, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"IPTR_O0" , 16, 1, 292, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_23" , 17, 7, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"O0_CSRM" , 24, 1, 292, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_25_27" , 25, 3, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"O0_RO" , 28, 1, 292, "R/W", 0, 1, 0ull, 0},
- {"O0_NS" , 29, 1, 292, "R/W", 0, 1, 0ull, 0},
- {"O0_ES" , 30, 2, 292, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_43" , 32, 12, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_BMODE" , 44, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_63" , 45, 19, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"NADDR" , 0, 61, 293, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 2, 293, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_63_63" , 63, 1, 293, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 294, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 3, 294, "RO", 0, 0, 0ull, 0ull},
- {"AVAIL" , 0, 32, 295, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 6, 295, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 295, "RAZ", 1, 1, 0, 0},
- {"AVAIL" , 0, 32, 296, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 5, 296, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 296, "RAZ", 1, 1, 0, 0},
- {"RD_BRST" , 0, 7, 297, "R/W", 0, 0, 17ull, 64ull},
- {"WR_BRST" , 7, 7, 297, "R/W", 0, 0, 16ull, 64ull},
- {"RESERVED_14_63" , 14, 50, 297, "RAZ", 1, 1, 0, 0},
- {"PARK_DEV" , 0, 3, 298, "R/W", 0, 1, 0ull, 0},
- {"PARK_MOD" , 3, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"EN" , 4, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 298, "RAZ", 1, 1, 0, 0},
- {"CMD_SIZE" , 0, 11, 299, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_11_63" , 11, 53, 299, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 300, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 300, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 300, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 300, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 300, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 300, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 300, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 300, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 300, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 4, 301, "R/W", 0, 0, 15ull, 15ull},
- {"BP_ON" , 4, 4, 301, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 301, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"NPI" , 3, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_8" , 8, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_14" , 14, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_15" , 15, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"LMC" , 17, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_21" , 21, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ASX0" , 22, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ASX1" , 23, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_24" , 24, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_25" , 25, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_26" , 26, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_27" , 27, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_28" , 28, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_29" , 29, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RINT_31" , 31, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 302, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 32, 303, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 303, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 304, "R/W", 0, 0, 0ull, 131072ull},
- {"RESERVED_32_63" , 32, 32, 304, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 305, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 305, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 305, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 305, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 305, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 306, "RO", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 306, "RO", 0, 0, 48ull, 48ull},
- {"ISAE" , 0, 1, 307, "RO", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 307, "R/W", 0, 0, 0ull, 1ull},
- {"ME" , 2, 1, 307, "R/W", 0, 0, 0ull, 1ull},
- {"SCSE" , 3, 1, 307, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 307, "R/W", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 307, "RO", 0, 0, 0ull, 0ull},
- {"PEE" , 6, 1, 307, "R/W", 0, 0, 0ull, 1ull},
- {"ADS" , 7, 1, 307, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 307, "R/W", 0, 0, 0ull, 1ull},
- {"FBBE" , 9, 1, 307, "R/W", 0, 0, 0ull, 1ull},
- {"I_DIS" , 10, 1, 307, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 307, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 307, "RO", 0, 0, 0ull, 0ull},
- {"CLE" , 20, 1, 307, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 307, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_22" , 22, 1, 307, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 307, "RO", 0, 1, 1ull, 0},
- {"MDPE" , 24, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 307, "RO", 0, 0, 1ull, 1ull},
- {"STA" , 27, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 308, "RO", 0, 0, 0ull, 0ull},
- {"CC" , 8, 24, 308, "RO", 0, 0, 733184ull, 733184ull},
- {"CLS" , 0, 8, 309, "R/W", 0, 1, 0ull, 0},
- {"LT" , 8, 8, 309, "R/W", 0, 0, 0ull, 64ull},
- {"HT" , 16, 8, 309, "RO", 0, 0, 0ull, 0ull},
- {"BCOD" , 24, 4, 309, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_29" , 28, 2, 309, "RAZ", 1, 1, 0, 0},
- {"BRB" , 30, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"BCAP" , 31, 1, 309, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 310, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 310, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 310, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 8, 310, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 12, 20, 310, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 311, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 312, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 312, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 312, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 23, 312, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 27, 5, 312, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 313, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 314, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 314, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 314, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 28, 314, "RO", 0, 0, 0ull, 0ull},
- {"HBASEZ" , 0, 7, 315, "RO", 0, 0, 0ull, 0ull},
- {"HBASE" , 7, 25, 315, "R/W", 0, 1, 0ull, 0},
- {"CISP" , 0, 32, 316, "RO", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 317, "RO", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 317, "RO", 0, 0, 1ull, 1ull},
- {"ERBAR_EN" , 0, 1, 318, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_10" , 1, 10, 318, "RAZ", 1, 1, 0, 0},
- {"ERBARZ" , 11, 5, 318, "RO", 0, 0, 0ull, 0ull},
- {"ERBAR" , 16, 16, 318, "R/W", 0, 1, 0ull, 0},
- {"CP" , 0, 8, 319, "RO", 0, 0, 224ull, 224ull},
- {"RESERVED_8_31" , 8, 24, 319, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 320, "R/W", 0, 1, 0ull, 0},
- {"INTA" , 8, 8, 320, "RO", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 320, "RO", 0, 0, 64ull, 64ull},
- {"ML" , 24, 8, 320, "RO", 0, 0, 64ull, 64ull},
- {"MLTD" , 0, 1, 321, "R/W", 0, 0, 0ull, 1ull},
- {"TSWC" , 1, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 321, "RAZ", 1, 1, 0, 0},
- {"DPPMR" , 3, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"PBE" , 4, 12, 321, "R/W", 0, 0, 0ull, 0ull},
- {"TILT" , 16, 4, 321, "R/W", 0, 0, 0ull, 0ull},
- {"TSLTE" , 20, 3, 321, "R/W", 0, 0, 0ull, 0ull},
- {"TMAE" , 23, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"TWTAE" , 24, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEN" , 25, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEI" , 26, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"TRTAE" , 27, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"TRDRS" , 28, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"RDSATI" , 29, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"TRDARD" , 30, 1, 321, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRDNPR" , 31, 1, 321, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSCME" , 0, 32, 322, "R/W1C", 0, 1, 0ull, 0},
- {"TDSRPS" , 0, 32, 323, "R/W1C", 0, 0, 0ull, 0ull},
- {"TDOMC" , 0, 5, 324, "R/W", 0, 0, 1ull, 1ull},
- {"TIDOMC" , 5, 1, 324, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 324, "RAZ", 1, 1, 0, 0},
- {"TIBDE" , 7, 1, 324, "R/W", 0, 0, 0ull, 0ull},
- {"TIBCD" , 8, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_10" , 9, 2, 324, "RAZ", 1, 1, 0, 0},
- {"TMAPES" , 11, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMDPES" , 12, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMSE" , 13, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMEI" , 14, 1, 324, "RO", 0, 0, 0ull, 0ull},
- {"TECI" , 15, 1, 324, "RO", 0, 0, 0ull, 0ull},
- {"TMES" , 16, 8, 324, "RO", 0, 0, 0ull, 0ull},
- {"MDRRMC" , 24, 3, 324, "R/W", 0, 0, 2ull, 2ull},
- {"MDRIMC" , 27, 1, 324, "R/W", 0, 0, 0ull, 0ull},
- {"MDRE" , 28, 1, 324, "R/W", 0, 0, 0ull, 0ull},
- {"MDWE" , 29, 1, 324, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCI" , 30, 1, 324, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCM" , 31, 1, 324, "R/W", 0, 0, 1ull, 1ull},
- {"MDSP" , 0, 32, 325, "R/W1C", 0, 1, 0ull, 0},
- {"SCMRE" , 0, 32, 326, "R/W1C", 0, 1, 0ull, 0},
- {"MTTV" , 0, 8, 327, "R/W", 0, 0, 0ull, 0ull},
- {"MRV" , 8, 8, 327, "R/W", 0, 0, 0ull, 255ull},
- {"MTTA" , 16, 1, 327, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRA" , 17, 1, 327, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLUSH" , 18, 1, 327, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_19_24" , 19, 6, 327, "RAZ", 1, 1, 0, 0},
- {"MAC" , 25, 7, 327, "R/W", 0, 0, 0ull, 0ull},
- {"PXCID" , 0, 8, 328, "RO", 0, 0, 7ull, 7ull},
- {"NCP" , 8, 8, 328, "RO", 0, 0, 232ull, 232ull},
- {"DPERE" , 16, 1, 328, "R/W", 0, 0, 0ull, 0ull},
- {"ROE" , 17, 1, 328, "R/W", 0, 0, 1ull, 1ull},
- {"MMBC" , 18, 2, 328, "R/W", 0, 0, 0ull, 0ull},
- {"MOST" , 20, 3, 328, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_23_31" , 23, 9, 328, "RAZ", 1, 1, 0, 0},
- {"FN" , 0, 3, 329, "RO", 0, 0, 0ull, 0ull},
- {"DN" , 3, 5, 329, "RO", 0, 0, 31ull, 31ull},
- {"BN" , 8, 8, 329, "RO", 0, 1, 17ull, 0},
- {"W64" , 16, 1, 329, "RO", 0, 0, 1ull, 1ull},
- {"M133" , 17, 1, 329, "RO", 0, 0, 1ull, 1ull},
- {"SCD" , 18, 1, 329, "R/W1C", 0, 1, 0ull, 0},
- {"USC" , 19, 1, 329, "R/W1C", 0, 1, 0ull, 0},
- {"DC" , 20, 1, 329, "RO", 0, 0, 0ull, 0ull},
- {"MMRBCD" , 21, 2, 329, "RO", 0, 0, 2ull, 2ull},
- {"MOSTD" , 23, 3, 329, "RO", 0, 0, 3ull, 3ull},
- {"MCRSD" , 26, 3, 329, "RO", 0, 0, 7ull, 7ull},
- {"SCEMR" , 29, 1, 329, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 329, "RAZ", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 330, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 330, "RO", 0, 0, 240ull, 240ull},
- {"PCIMIV" , 16, 3, 330, "RO", 0, 0, 2ull, 2ull},
- {"PMEC" , 19, 1, 330, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 330, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 330, "RO", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 330, "RO", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 330, "RO", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 330, "RO", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 330, "RO", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 331, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 331, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 331, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 331, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 331, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEN" , 23, 1, 331, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 331, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 332, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 332, "RO", 0, 0, 0ull, 0ull},
- {"MSIEN" , 16, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 332, "RO", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 332, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 332, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 332, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 333, "RAZ", 1, 1, 0, 0},
- {"MSI31T2" , 2, 30, 333, "R/W", 0, 1, 0ull, 0},
- {"MSI" , 0, 32, 334, "R/W", 0, 1, 0ull, 0},
- {"MSIMD" , 0, 16, 335, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 335, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 336, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 336, "R/W", 0, 0, 0ull, 1ull},
- {"TSR_HWM" , 4, 3, 336, "R/W", 0, 1, 1ull, 0},
- {"PMO_FPC" , 7, 3, 336, "R/W", 0, 0, 0ull, 0ull},
- {"PMO_AMOD" , 10, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"B12_BIST" , 11, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"AP_64AD" , 12, 1, 336, "RO", 0, 1, 0ull, 0},
- {"AP_PCIX" , 13, 1, 336, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_14" , 14, 1, 336, "RAZ", 0, 0, 0ull, 0ull},
- {"EN_WFILT" , 15, 1, 336, "R/W", 0, 0, 0ull, 1ull},
- {"SCM" , 16, 1, 336, "RO", 0, 1, 0ull, 0},
- {"SCMTYP" , 17, 1, 336, "RO", 0, 1, 0ull, 0},
- {"BAR2PRES" , 18, 1, 336, "R/W", 1, 1, 0, 0},
- {"ERST_N" , 19, 1, 336, "RO", 0, 0, 1ull, 1ull},
- {"BB0" , 20, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"BB1" , 21, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"BB_ES" , 22, 2, 336, "R/W", 0, 0, 0ull, 0ull},
- {"BB_CA" , 24, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"BB1_SIZ" , 25, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"BB1_HOLE" , 26, 3, 336, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 336, "RAZ", 1, 1, 0, 0},
- {"INC_VAL" , 0, 16, 337, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 337, "RAZ", 1, 1, 0, 0},
- {"DMA_CNT" , 0, 32, 338, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 339, "R/W", 0, 1, 0ull, 0},
- {"DMA_TIME" , 0, 32, 340, "R/W", 0, 1, 0ull, 0},
- {"ICNT" , 0, 32, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"ITR_WABT" , 0, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IMR_WABT" , 1, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IMR_WTTO" , 2, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"ITR_ABT" , 3, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IMR_ABT" , 4, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IMR_TTO" , 5, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IMSI_PER" , 6, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IMSI_TABT" , 7, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IMSI_MABT" , 8, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IMSC_MSG" , 9, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"ITSR_ABT" , 10, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"ISERR" , 11, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IAPERR" , 12, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IDPERR" , 13, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IRSL_INT" , 16, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IPCNT0" , 17, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_20" , 18, 3, 342, "RAZ", 0, 1, 0ull, 0},
- {"IPTIME0" , 21, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_24" , 22, 3, 342, "RAZ", 0, 1, 0ull, 0},
- {"IDCNT0" , 25, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IDCNT1" , 26, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IDTIME0" , 27, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"IDTIME1" , 28, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 342, "RAZ", 1, 1, 0, 0},
- {"RTR_WABT" , 0, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RMR_WABT" , 1, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RMR_WTTO" , 2, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RTR_ABT" , 3, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RMR_ABT" , 4, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RMR_TTO" , 5, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RMSI_PER" , 6, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RMSI_TABT" , 7, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RMSI_MABT" , 8, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RMSC_MSG" , 9, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RTSR_ABT" , 10, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RSERR" , 11, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RAPERR" , 12, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RDPERR" , 13, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RRSL_INT" , 16, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RPCNT0" , 17, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_20" , 18, 3, 343, "RAZ", 0, 1, 0ull, 0},
- {"RPTIME0" , 21, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_24" , 22, 3, 343, "RAZ", 0, 1, 0ull, 0},
- {"RDCNT0" , 25, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RDCNT1" , 26, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RDTIME0" , 27, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RDTIME1" , 28, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 343, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 344, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_20" , 18, 3, 344, "RAZ", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_24" , 22, 3, 344, "RAZ", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 344, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 345, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_20" , 18, 3, 345, "RAZ", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_24" , 22, 3, 345, "RAZ", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 345, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 6, 346, "WO", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 346, "R/W", 1, 1, 0, 0},
- {"PTR_CNT" , 0, 16, 347, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 16, 16, 347, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 0, 32, 348, "RO", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 349, "R/W", 0, 1, 0ull, 0},
- {"PKT_TIME" , 0, 32, 350, "R/W", 0, 1, 0ull, 0},
- {"PREFETCH" , 0, 3, 351, "R/W", 0, 0, 0ull, 2ull},
- {"MIN_DATA" , 3, 6, 351, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_9_31" , 9, 23, 351, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 352, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 352, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 352, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 353, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 353, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 353, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 31, 354, "R/W", 0, 0, 10000ull, 10000ull},
- {"ENB" , 31, 1, 354, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 354, "RAZ", 1, 1, 0, 0},
- {"SCM" , 0, 32, 355, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 355, "RAZ", 1, 1, 0, 0},
- {"TSR" , 0, 36, 356, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 356, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 357, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 2, 46, 357, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 357, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 357, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 358, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 359, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 359, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 359, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 359, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 360, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 361, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 361, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 362, "R/W", 0, 0, 0ull, 8ull},
- {"FETCHSIZ" , 4, 4, 362, "R/W", 0, 0, 0ull, 7ull},
- {"TXRD" , 8, 10, 362, "R/W", 0, 0, 0ull, 1ull},
- {"USELDT" , 18, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 362, "RAZ", 1, 1, 0, 0},
- {"RXST" , 20, 10, 362, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_30_31" , 30, 2, 362, "RAZ", 1, 1, 0, 0},
- {"TXSLOTS" , 32, 10, 362, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_42_43" , 42, 2, 362, "RAZ", 1, 1, 0, 0},
- {"RXSLOTS" , 44, 10, 362, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_62" , 54, 9, 362, "RAZ", 1, 1, 0, 0},
- {"RDPEND" , 63, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"FSYNCMISSED" , 0, 1, 363, "R/W", 0, 0, 0ull, 1ull},
- {"FSYNCEXTRA" , 1, 1, 363, "R/W", 0, 0, 0ull, 1ull},
- {"RXWRAP" , 2, 1, 363, "R/W", 0, 0, 0ull, 1ull},
- {"RXST" , 3, 1, 363, "R/W", 0, 0, 0ull, 1ull},
- {"TXWRAP" , 4, 1, 363, "R/W", 0, 0, 0ull, 1ull},
- {"TXRD" , 5, 1, 363, "R/W", 0, 0, 0ull, 1ull},
- {"TXEMPTY" , 6, 1, 363, "R/W", 0, 0, 0ull, 1ull},
- {"RXOVF" , 7, 1, 363, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 363, "RAZ", 1, 1, 0, 0},
- {"FSYNCMISSED" , 0, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYNCEXTRA" , 1, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXWRAP" , 2, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXST" , 3, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXWRAP" , 4, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXRD" , 5, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXEMPTY" , 6, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXOVF" , 7, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 364, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 365, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 365, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 366, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 366, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 367, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 368, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 369, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 370, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 371, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 372, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 373, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 374, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 375, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 375, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 375, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 376, "R/W", 0, 0, 0ull, 0ull},
- {"USECLK1" , 1, 1, 376, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 2, 1, 376, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 376, "RAZ", 1, 1, 0, 0},
- {"SAMPPT" , 32, 16, 376, "R/W", 0, 1, 0ull, 0},
- {"DRVTIM" , 48, 16, 376, "R/W", 0, 1, 0ull, 0},
- {"DEBUGINFO" , 0, 64, 377, "RO", 1, 1, 0, 0},
- {"FRAM" , 0, 3, 378, "R/W", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 378, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 378, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 379, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 379, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 380, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 381, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 382, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 383, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 384, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 385, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 386, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 387, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 388, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 388, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 388, "RAZ", 1, 1, 0, 0},
- {"ENA" , 0, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"FSYNCPOL" , 1, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"BCLKPOL" , 2, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"BITLEN" , 3, 2, 389, "R/W", 0, 0, 0ull, 0ull},
- {"EXTRABIT" , 5, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"NUMSLOTS" , 6, 10, 389, "R/W", 0, 1, 0ull, 0},
- {"FSYNCLOC" , 16, 5, 389, "R/W", 0, 0, 0ull, 0ull},
- {"FSYNCLEN" , 21, 5, 389, "R/W", 0, 0, 0ull, 2ull},
- {"RESERVED_26_31" , 26, 6, 389, "RAZ", 1, 1, 0, 0},
- {"FSYNCSAMP" , 32, 16, 389, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_62" , 48, 15, 389, "RAZ", 1, 1, 0, 0},
- {"FSYNCGOOD" , 63, 1, 389, "RO", 0, 0, 0ull, 1ull},
- {"DEBUGINFO" , 0, 64, 390, "RO", 1, 1, 0, 0},
- {"N" , 0, 32, 391, "R/W", 0, 1, 0ull, 0},
- {"NUMSAMP" , 32, 16, 391, "R/W", 0, 1, 0ull, 0},
- {"DELTASAMP" , 48, 16, 391, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 18, 392, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 392, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 393, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 393, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 393, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 393, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 394, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 394, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 394, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 394, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 394, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 394, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 395, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 395, "RAZ", 0, 1, 0ull, 0},
- {"L4_MAL" , 8, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 395, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 395, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 395, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 395, "RAZ", 0, 0, 0ull, 0ull},
- {"PKTDRP" , 0, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 396, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 397, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 398, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 398, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 399, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 399, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 399, "RAZ", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 399, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 399, "RAZ", 1, 1, 0, 0},
- {"GRP_WAT" , 28, 4, 399, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 399, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 400, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 400, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 400, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 400, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 400, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 400, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 400, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 400, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 400, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 401, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 401, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 402, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 402, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 403, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 2, 403, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 403, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 403, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 403, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 403, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 403, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 403, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 403, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 404, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 404, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 405, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 406, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 406, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 407, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 407, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 408, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 408, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 409, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 409, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 410, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 410, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 411, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 411, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 412, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 412, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 413, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 413, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 414, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 414, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 415, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 415, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 416, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 416, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 417, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 417, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 418, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 418, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 419, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 419, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 420, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 421, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 421, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 422, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 422, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 423, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 423, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 423, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 424, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 424, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 425, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 425, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 426, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 426, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 426, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 426, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 427, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 427, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 427, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 427, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 427, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 0, 16, 428, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 428, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 428, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 428, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 429, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 429, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 429, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 429, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 429, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 430, "RO", 1, 0, 0, 0ull},
- {"WIDX2" , 0, 17, 431, "RO", 1, 0, 0, 0ull},
- {"RIDX2" , 17, 17, 431, "RO", 1, 0, 0, 0ull},
- {"WIDX" , 34, 17, 431, "RO", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 431, "RO", 1, 0, 0, 0ull},
- {"RIDX" , 0, 17, 432, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 432, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 433, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 433, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 433, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 433, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 433, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 434, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 434, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 434, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 434, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 434, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 435, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 4, 436, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 4, 2, 436, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 6, 1, 436, "RO", 1, 0, 0, 0ull},
- {"QID_BASE" , 7, 7, 436, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 14, 3, 436, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 17, 5, 436, "RO", 1, 0, 0, 0ull},
- {"QOS" , 22, 3, 436, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 436, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 26, 1, 436, "RO", 1, 0, 0, 0ull},
- {"RESERVED_27_27" , 27, 1, 436, "RO", 1, 0, 0, 0ull},
- {"CBUF_FRE" , 28, 1, 436, "RO", 1, 0, 0, 0ull},
- {"XFER_DWR" , 29, 1, 436, "RO", 1, 0, 0, 0ull},
- {"XFER_WOR" , 30, 1, 436, "RO", 1, 0, 0, 0ull},
- {"UID" , 31, 1, 436, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 32, 16, 436, "RO", 1, 0, 0, 0ull},
- {"DWRI_CNT" , 48, 13, 436, "RO", 1, 0, 0, 0ull},
- {"DWRI_LEN" , 61, 1, 436, "RO", 1, 0, 0, 0ull},
- {"DWRI_SOP" , 62, 1, 436, "RO", 1, 0, 0, 0ull},
- {"DWRI_MOD" , 63, 1, 436, "RO", 1, 0, 0, 0ull},
- {"DWRI_MOD" , 0, 2, 437, "RO", 1, 0, 0, 0ull},
- {"DWRI_UID" , 2, 1, 437, "RO", 1, 0, 0, 0ull},
- {"DWRI_CHK" , 3, 1, 437, "RO", 1, 0, 0, 0ull},
- {"WORK_MIN" , 4, 3, 437, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 7, 1, 437, "RO", 1, 0, 0, 0ull},
- {"QID_OFFM" , 8, 3, 437, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 437, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 0, 16, 438, "RO", 1, 0, 0, 0ull},
- {"START" , 16, 33, 438, "RO", 1, 0, 0, 0ull},
- {"DWB" , 49, 9, 438, "RO", 1, 0, 0, 0ull},
- {"RESERVED_58_63" , 58, 6, 438, "RO", 1, 1, 0, 0},
- {"QCB_RIDX" , 0, 6, 439, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 439, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 439, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 439, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 439, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 439, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 440, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 440, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 440, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_7" , 5, 3, 440, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 440, "RO", 1, 0, 0, 0ull},
- {"RESERVED_28_63" , 28, 36, 440, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 441, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 441, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 441, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 441, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 441, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 441, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 441, "WR0", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 441, "WR0", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 441, "WR0", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 442, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 442, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 442, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 442, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 442, "RAZ", 1, 1, 0, 0},
- {"PSB" , 0, 7, 443, "RO", 1, 0, 0, 0ull},
- {"PDB" , 7, 4, 443, "RO", 1, 0, 0, 0ull},
- {"QCB" , 11, 2, 443, "RO", 1, 0, 0, 0ull},
- {"QSB" , 13, 2, 443, "RO", 1, 0, 0, 0ull},
- {"CHK" , 15, 1, 443, "RO", 1, 0, 0, 0ull},
- {"CRC" , 16, 1, 443, "RO", 1, 0, 0, 0ull},
- {"OUT" , 17, 1, 443, "RO", 1, 0, 0, 0ull},
- {"NCB" , 18, 1, 443, "RO", 1, 0, 0, 0ull},
- {"WIF" , 19, 1, 443, "RO", 1, 0, 0, 0ull},
- {"RIF" , 20, 1, 443, "RO", 1, 0, 0, 0ull},
- {"COUNT" , 21, 1, 443, "RO", 1, 0, 0, 0ull},
- {"PSB2" , 22, 5, 443, "RO", 1, 0, 0, 0ull},
- {"RESERVED_27_63" , 27, 37, 443, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 444, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 444, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 444, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 444, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 17, 445, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 445, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 446, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 447, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 447, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 448, "R/W", 0, 0, 0ull, 0ull},
- {"MODE1" , 3, 3, 448, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 448, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 449, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 449, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 449, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 450, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 450, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 451, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 451, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"PEND" , 1, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 2, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 3, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 4, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 5, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"NBT0" , 6, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"NBT1" , 7, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 8, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 452, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 452, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 453, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 453, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 454, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 454, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 454, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 454, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 454, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 454, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 454, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 454, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 454, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 454, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 454, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 454, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 454, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 455, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 455, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 456, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 456, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 457, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 457, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 7, 458, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 458, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 459, "R/W", 0, 0, 0ull, 1023ull},
- {"RESERVED_10_63" , 10, 54, 459, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 460, "R/W", 0, 0, 65535ull, 65535ull},
- {"RESERVED_16_63" , 16, 48, 460, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 461, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 461, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 461, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 461, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 461, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 6, 462, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_11" , 6, 6, 462, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 6, 462, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_18_23" , 18, 6, 462, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 7, 462, "RO", 0, 1, 58ull, 0},
- {"RESERVED_31_35" , 31, 5, 462, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 36, 7, 462, "RO", 0, 1, 0ull, 0},
- {"RESERVED_43_47" , 43, 5, 462, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 48, 7, 462, "RO", 0, 1, 0ull, 0},
- {"RESERVED_55_63" , 55, 9, 462, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 463, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 463, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 464, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 464, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 465, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 465, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 466, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 466, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 466, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 7, 467, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_11" , 7, 5, 467, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 12, 7, 467, "RO", 0, 1, 0ull, 0},
- {"RESERVED_19_23" , 19, 5, 467, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 24, 4, 467, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 467, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 468, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 468, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 468, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 468, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 468, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 6, 469, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_11" , 6, 6, 469, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 6, 469, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_23" , 18, 6, 469, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 469, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 469, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 469, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 470, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 470, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 471, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 472, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 473, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 473, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 473, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 473, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 473, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 473, "RAZ", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 473, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 473, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 474, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 474, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 474, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 474, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 1, 474, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 474, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 475, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 475, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 476, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 476, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 476, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 476, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 477, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 477, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 477, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 477, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 478, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 478, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 478, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 478, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 478, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 478, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 479, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 479, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 479, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 480, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 480, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 480, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 480, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 480, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 481, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 481, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 481, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 481, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 482, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 482, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 482, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 482, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 482, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 482, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 483, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 483, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 483, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 483, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 484, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 484, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 485, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 485, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 485, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 485, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 486, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 486, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 487, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 487, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 487, "RAZ", 1, 1, 0, 0},
- {"INEPINT" , 0, 16, 488, "RO", 0, 0, 0ull, 0ull},
- {"OUTEPINT" , 16, 16, 488, "RO", 0, 0, 0ull, 0ull},
- {"INEPMSK" , 0, 16, 489, "R/W", 0, 0, 0ull, 0ull},
- {"OUTEPMSK" , 16, 16, 489, "R/W", 0, 0, 0ull, 0ull},
- {"DEVSPD" , 0, 2, 490, "R/W", 0, 0, 0ull, 0ull},
- {"NZSTSOUTHSHK" , 2, 1, 490, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 490, "RAZ", 1, 1, 0, 0},
- {"DEVADDR" , 4, 7, 490, "R/W", 0, 0, 0ull, 0ull},
- {"PERFRINT" , 11, 2, 490, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_17" , 13, 5, 490, "RAZ", 1, 1, 0, 0},
- {"EPMISCNT" , 18, 5, 490, "R/W", 0, 0, 8ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 490, "RAZ", 1, 1, 0, 0},
- {"RMTWKUPSIG" , 0, 1, 491, "R/W", 0, 0, 0ull, 0ull},
- {"SFTDISCON" , 1, 1, 491, "R/W", 0, 0, 0ull, 0ull},
- {"GNPINNAKSTS" , 2, 1, 491, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKSTS" , 3, 1, 491, "RO", 0, 0, 0ull, 0ull},
- {"TSTCTL" , 4, 3, 491, "R/W", 0, 0, 0ull, 0ull},
- {"SGNPINNAK" , 7, 1, 491, "WO", 0, 0, 0ull, 0ull},
- {"CGNPINNAK" , 8, 1, 491, "WO", 0, 0, 0ull, 0ull},
- {"SGOUTNAK" , 9, 1, 491, "WO", 0, 0, 0ull, 0ull},
- {"CGOUTNAK" , 10, 1, 491, "WO", 0, 0, 0ull, 0ull},
- {"PWRONPRGDONE" , 11, 1, 491, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 491, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 492, "R/W", 0, 0, 0ull, 0ull},
- {"NEXTEP" , 11, 4, 492, "R/W", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 492, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 492, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 492, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 492, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 492, "RAZ", 1, 1, 0, 0},
- {"STALL" , 21, 1, 492, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 22, 4, 492, "R/W", 0, 0, 0ull, 0ull},
- {"CNAK" , 26, 1, 492, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 492, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 492, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 492, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 492, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 492, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMEOUT" , 3, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMP" , 4, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNEPMIS" , 5, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"INEPNAKEFF" , 6, 1, 493, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 493, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"TIMEOUTMSK" , 3, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMPMSK" , 4, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNEPMISMSK" , 5, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"INEPNAKEFFMSK" , 6, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 494, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 495, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 495, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 495, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 495, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 496, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_14" , 11, 4, 496, "RAZ", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 496, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 496, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 496, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 496, "R/W", 0, 0, 0ull, 0ull},
- {"SNP" , 20, 1, 496, "R/W", 0, 0, 0ull, 0ull},
- {"STALL" , 21, 1, 496, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_25" , 22, 4, 496, "RAZ", 1, 1, 0, 0},
- {"CNAK" , 26, 1, 496, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 496, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 496, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 496, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 496, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 496, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
- {"SETUP" , 3, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDIS" , 4, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 497, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 498, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 498, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 498, "R/W", 0, 0, 0ull, 0ull},
- {"SETUPMSK" , 3, 1, 498, "R/W", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDISMSK" , 4, 1, 498, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 498, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 499, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 499, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 499, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 499, "RAZ", 1, 1, 0, 0},
- {"DPTXFSTADDR" , 0, 16, 500, "RO", 0, 0, 0ull, 0ull},
- {"DPTXFSIZE" , 16, 16, 500, "RO", 0, 0, 1896ull, 1896ull},
- {"SUSPSTS" , 0, 1, 501, "RO", 0, 0, 0ull, 0ull},
- {"ENUMSPD" , 1, 2, 501, "RO", 0, 0, 0ull, 0ull},
- {"ERRTICERR" , 3, 1, 501, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 501, "RAZ", 1, 1, 0, 0},
- {"SOFFN" , 8, 14, 501, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 501, "RAZ", 1, 1, 0, 0},
- {"INTKNWPTR" , 0, 5, 502, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 502, "RAZ", 1, 1, 0, 0},
- {"WRAPBIT" , 7, 1, 502, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 8, 24, 502, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 503, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 504, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 505, "RO", 0, 0, 0ull, 0ull},
- {"GLBLINTRMSK" , 0, 1, 506, "R/W", 0, 0, 0ull, 1ull},
- {"HBSTLEN" , 1, 4, 506, "R/W", 0, 0, 0ull, 0ull},
- {"DMAEN" , 5, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 506, "RAZ", 1, 1, 0, 0},
- {"NPTXFEMPLVL" , 7, 1, 506, "R/W", 0, 0, 0ull, 1ull},
- {"PTXFEMPLVL" , 8, 1, 506, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_31" , 9, 23, 506, "RAZ", 1, 1, 0, 0},
- {"EPDIR" , 0, 32, 507, "RO", 0, 0, 0ull, 0ull},
- {"OTGMODE" , 0, 3, 508, "RO", 0, 0, 2ull, 2ull},
- {"OTGARCH" , 3, 2, 508, "RO", 0, 0, 1ull, 1ull},
- {"SINGPNT" , 5, 1, 508, "RO", 0, 0, 0ull, 0ull},
- {"HSPHYTYPE" , 6, 2, 508, "RO", 0, 0, 1ull, 1ull},
- {"FSPHYTYPE" , 8, 2, 508, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVEPS" , 10, 4, 508, "RO", 0, 0, 4ull, 4ull},
- {"NUMHSTCHNL" , 14, 4, 508, "RO", 0, 0, 7ull, 7ull},
- {"PERIOSUPPORT" , 18, 1, 508, "RO", 0, 0, 1ull, 1ull},
- {"DYNFIFOSIZING" , 19, 1, 508, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_20_21" , 20, 2, 508, "RAZ", 1, 1, 0, 0},
- {"NPTXQDEPTH" , 22, 2, 508, "RO", 0, 0, 2ull, 2ull},
- {"PTXQDEPTH" , 24, 2, 508, "RO", 0, 0, 2ull, 2ull},
- {"TKNQDEPTH" , 26, 5, 508, "RO", 0, 0, 30ull, 30ull},
- {"RESERVED_31_31" , 31, 1, 508, "RAZ", 1, 1, 0, 0},
- {"XFERSIZEWIDTH" , 0, 4, 509, "RO", 0, 0, 8ull, 8ull},
- {"PKTSIZEWIDTH" , 4, 3, 509, "RO", 0, 0, 6ull, 6ull},
- {"OTGEN" , 7, 1, 509, "RO", 0, 0, 1ull, 1ull},
- {"I2C_SELECTION" , 8, 1, 509, "RO", 0, 0, 0ull, 0ull},
- {"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 509, "RO", 0, 0, 0ull, 0ull},
- {"OPTFEATURE" , 10, 1, 509, "RO", 0, 0, 1ull, 1ull},
- {"RSTTYPE" , 11, 1, 509, "RO", 0, 0, 1ull, 1ull},
- {"AHBPHYSYNC" , 12, 1, 509, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 509, "RAZ", 1, 1, 0, 0},
- {"DFIFODEPTH" , 16, 16, 509, "RO", 0, 0, 1824ull, 1824ull},
- {"NUMDEVPERIOEPS" , 0, 4, 510, "RO", 0, 0, 4ull, 4ull},
- {"ENABLEPWROPT" , 4, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"AHBFREQ" , 5, 1, 510, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_13" , 6, 8, 510, "RAZ", 1, 1, 0, 0},
- {"PHYDATAWIDTH" , 14, 2, 510, "RO", 0, 0, 1ull, 1ull},
- {"NUMCTLEPS" , 16, 4, 510, "RO", 0, 0, 4ull, 4ull},
- {"IDDGFLTR" , 20, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"VBUSVALIDFLTR" , 21, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"AVALIDFLTR" , 22, 1, 510, "RO", 0, 0, 1ull, 1ull},
- {"BVALIDFLTR" , 23, 1, 510, "RO", 0, 0, 1ull, 1ull},
- {"SESSENDFLTR" , 24, 1, 510, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_25_31" , 25, 7, 510, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 511, "RAZ", 1, 1, 0, 0},
- {"MODEMISMSK" , 1, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"OTGINTMSK" , 2, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"SOFMSK" , 3, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"RXFLVLMSK" , 4, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"NPTXFEMPMSK" , 5, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"GINNAKEFFMSK" , 6, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFFMSK" , 7, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"ULPICKINTMSK" , 8, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"ERLYSUSPMSK" , 10, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"USBSUSPMSK" , 11, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"USBRSTMSK" , 12, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"ENUMDONEMSK" , 13, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"ISOOUTDROPMSK" , 14, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"EOPFMSK" , 15, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 511, "RAZ", 1, 1, 0, 0},
- {"EPMISMSK" , 17, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"INEPINTMSK" , 18, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"OEPINTMSK" , 19, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPISOINMSK" , 20, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPLPMSK" , 21, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"FETSUSPMSK" , 22, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 511, "RAZ", 1, 1, 0, 0},
- {"PRTINTMSK" , 24, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"HCHINTMSK" , 25, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"PTXFEMPMSK" , 26, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 511, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNGMSK" , 28, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"DISCONNINTMSK" , 29, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"SESSREQINTMSK" , 30, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"WKUPINTMSK" , 31, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"CURMOD" , 0, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"MODEMIS" , 1, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"OTGINT" , 2, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"SOF" , 3, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXFLVL" , 4, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"NPTXFEMP" , 5, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"GINNAKEFF" , 6, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFF" , 7, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"ULPICKINT" , 8, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"ERLYSUSP" , 10, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBSUSP" , 11, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBRST" , 12, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENUMDONE" , 13, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"ISOOUTDROP" , 14, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"EOPF" , 15, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 512, "RAZ", 1, 1, 0, 0},
- {"EPMIS" , 17, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"IEPINT" , 18, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"OEPINT" , 19, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"INCOMPISOIN" , 20, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"INCOMPLP" , 21, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"FETSUSP" , 22, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 512, "RAZ", 1, 1, 0, 0},
- {"PRTINT" , 24, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"HCHINT" , 25, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"PTXFEMP" , 26, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 512, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNG" , 28, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"DISCONNINT" , 29, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"SESSREQINT" , 30, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"WKUPINT" , 31, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"NPTXFSTADDR" , 0, 16, 513, "R/W", 0, 0, 1824ull, 456ull},
- {"NPTXFDEP" , 16, 16, 513, "R/W", 0, 0, 1824ull, 912ull},
- {"NPTXFSPCAVAIL" , 0, 16, 514, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQSPCAVAIL" , 16, 8, 514, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQTOP" , 24, 7, 514, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 514, "RAZ", 1, 1, 0, 0},
- {"SESREQSCS" , 0, 1, 515, "R/W", 0, 0, 0ull, 0ull},
- {"SESREQ" , 1, 1, 515, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 515, "RAZ", 1, 1, 0, 0},
- {"HSTNEGSCS" , 8, 1, 515, "R/W", 0, 0, 0ull, 0ull},
- {"HNPREQ" , 9, 1, 515, "R/W", 0, 0, 0ull, 0ull},
- {"HSTSETHNPEN" , 10, 1, 515, "R/W", 0, 0, 0ull, 0ull},
- {"DEVHNPEN" , 11, 1, 515, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 515, "RAZ", 1, 1, 0, 0},
- {"CONIDSTS" , 16, 1, 515, "RO", 1, 1, 0, 0},
- {"DBNCTIME" , 17, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"ASESVLD" , 18, 1, 515, "RO", 1, 1, 0, 0},
- {"BSESVLD" , 19, 1, 515, "RO", 1, 1, 0, 0},
- {"RESERVED_20_31" , 20, 12, 515, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 516, "RAZ", 1, 1, 0, 0},
- {"SESENDDET" , 2, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 516, "RAZ", 1, 1, 0, 0},
- {"SESREQSUCSTSCHNG" , 8, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSTNEGSUCSTSCHNG" , 9, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_16" , 10, 7, 516, "RAZ", 1, 1, 0, 0},
- {"HSTNEGDET" , 17, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
- {"ADEVTOUTCHG" , 18, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBNCEDONE" , 19, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 516, "RAZ", 1, 1, 0, 0},
- {"CSFTRST" , 0, 1, 517, "R/W", 0, 0, 0ull, 0ull},
- {"HSFTRST" , 1, 1, 517, "R/W", 0, 0, 0ull, 0ull},
- {"FRMCNTRRST" , 2, 1, 517, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNQFLSH" , 3, 1, 517, "R/W", 0, 0, 0ull, 0ull},
- {"RXFFLSH" , 4, 1, 517, "R/W", 0, 0, 0ull, 0ull},
- {"TXFFLSH" , 5, 1, 517, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 6, 5, 517, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_29" , 11, 19, 517, "RAZ", 1, 1, 0, 0},
- {"DMAREQ" , 30, 1, 517, "RO", 0, 0, 0ull, 0ull},
- {"AHBIDLE" , 31, 1, 517, "RO", 0, 0, 1ull, 1ull},
- {"RXFDEP" , 0, 16, 518, "R/W", 0, 0, 1824ull, 456ull},
- {"RESERVED_16_31" , 16, 16, 518, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 519, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 519, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 519, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 519, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 519, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 519, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 520, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 520, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 520, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 520, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 520, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 521, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 521, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 521, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 521, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 521, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 521, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 522, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 522, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 522, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 522, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 522, "RAZ", 1, 1, 0, 0},
- {"SYNOPSYSID" , 0, 32, 523, "RO", 1, 1, 0, 0},
- {"TOUTCAL" , 0, 3, 524, "R/W", 0, 0, 0ull, 0ull},
- {"PHYIF" , 3, 1, 524, "RO", 0, 0, 1ull, 1ull},
- {"ULPI_UTMI_SEL" , 4, 1, 524, "RO", 0, 0, 0ull, 0ull},
- {"FSINTF" , 5, 1, 524, "WO", 0, 0, 0ull, 0ull},
- {"PHYSEL" , 6, 1, 524, "WO", 0, 0, 0ull, 0ull},
- {"DDRSEL" , 7, 1, 524, "R/W", 0, 0, 0ull, 0ull},
- {"SRPCAP" , 8, 1, 524, "RO", 0, 0, 0ull, 0ull},
- {"HNPCAP" , 9, 1, 524, "RO", 0, 0, 0ull, 0ull},
- {"USBTRDTIM" , 10, 4, 524, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_14_14" , 14, 1, 524, "RAZ", 1, 1, 0, 0},
- {"PHYLPWRCLKSEL" , 15, 1, 524, "R/W", 0, 0, 0ull, 0ull},
- {"OTGI2CSEL" , 16, 1, 524, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 524, "RAZ", 1, 1, 0, 0},
- {"HAINT" , 0, 16, 525, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 525, "RAZ", 1, 1, 0, 0},
- {"HAINTMSK" , 0, 16, 526, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 526, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 527, "R/W", 0, 0, 0ull, 0ull},
- {"EPNUM" , 11, 4, 527, "R/W", 0, 0, 0ull, 0ull},
- {"EPDIR" , 15, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 527, "RAZ", 1, 1, 0, 0},
- {"LSPDDEV" , 17, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 527, "R/W", 0, 0, 0ull, 0ull},
- {"EC" , 20, 2, 527, "R/W", 0, 0, 0ull, 0ull},
- {"DEVADDR" , 22, 7, 527, "R/W", 0, 0, 0ull, 0ull},
- {"ODDFRM" , 29, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"CHDIS" , 30, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"CHENA" , 31, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSPCLKSEL" , 0, 2, 528, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSSUPP" , 2, 1, 528, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 528, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPL" , 0, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"CHHLTD" , 1, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"STALL" , 3, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAK" , 4, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACK" , 5, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"NYET" , 6, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"XACTERR" , 7, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"BBLERR" , 8, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMOVRUN" , 9, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATATGLERR" , 10, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 529, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"CHHLTDMSK" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"STALLMSK" , 3, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"NAKMSK" , 4, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"ACKMSK" , 5, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"NYETMSK" , 6, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"XACTERRMSK" , 7, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"BBLERRMSK" , 8, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"FRMOVRUNMSK" , 9, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"DATATGLERRMSK" , 10, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 530, "RAZ", 1, 1, 0, 0},
- {"PRTADDR" , 0, 7, 531, "R/W", 0, 0, 0ull, 0ull},
- {"HUBADDR" , 7, 7, 531, "R/W", 0, 0, 0ull, 0ull},
- {"XACTPOS" , 14, 2, 531, "R/W", 0, 0, 0ull, 0ull},
- {"COMPSPLT" , 16, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_30" , 17, 14, 531, "RAZ", 1, 1, 0, 0},
- {"SPLTENA" , 31, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"XFERSIZE" , 0, 19, 532, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 532, "R/W", 0, 0, 0ull, 0ull},
- {"PID" , 29, 2, 532, "R/W", 0, 0, 0ull, 0ull},
- {"DOPNG" , 31, 1, 532, "R/W", 0, 0, 0ull, 0ull},
- {"FRINT" , 0, 16, 533, "R/W", 0, 0, 2959ull, 3750ull},
- {"RESERVED_16_31" , 16, 16, 533, "RAZ", 1, 1, 0, 0},
- {"FRNUM" , 0, 16, 534, "RO", 0, 0, 16383ull, 0ull},
- {"FRREM" , 16, 16, 534, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNSTS" , 0, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNDET" , 1, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENA" , 2, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENCHNG" , 3, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRACT" , 4, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRCHNG" , 5, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTRES" , 6, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSUSP" , 7, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"PRTRST" , 8, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 535, "RAZ", 1, 1, 0, 0},
- {"PRTLNSTS" , 10, 2, 535, "RO", 0, 0, 0ull, 0ull},
- {"PRTPWR" , 12, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"PRTTSTCTL" , 13, 4, 535, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSPD" , 17, 2, 535, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 535, "RAZ", 1, 1, 0, 0},
- {"PTXFSTADDR" , 0, 16, 536, "R/W", 0, 0, 3648ull, 912ull},
- {"PTXFSIZE" , 16, 16, 536, "R/W", 0, 0, 1824ull, 456ull},
- {"PTXFSPCAVAIL" , 0, 16, 537, "RO", 0, 0, 0ull, 0ull},
- {"PTXQSPCAVAIL" , 16, 8, 537, "RO", 0, 0, 0ull, 0ull},
- {"PTXQTOP" , 24, 8, 537, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 32, 538, "R/W", 0, 0, 0ull, 0ull},
- {"STOPPCLK" , 0, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"GATEHCLK" , 1, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"PWRCLMP" , 2, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"RSTPDWNMODULE" , 3, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"PHYSUSPENDED" , 4, 1, 539, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 539, "RAZ", 1, 1, 0, 0},
- {"NOF_BIS" , 0, 1, 540, "RO", 0, 0, 0ull, 0ull},
- {"NIF_BIS" , 1, 1, 540, "RO", 0, 0, 0ull, 0ull},
- {"USBC_BIS" , 2, 1, 540, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 540, "RAZ", 1, 1, 0, 0},
- {"DIVIDE" , 0, 3, 541, "R/W", 0, 0, 4ull, 4ull},
- {"HRST" , 3, 1, 541, "R/W", 0, 0, 0ull, 1ull},
- {"PRST" , 4, 1, 541, "R/W", 0, 0, 0ull, 1ull},
- {"ENABLE" , 5, 1, 541, "R/W", 0, 0, 1ull, 1ull},
- {"POR" , 6, 1, 541, "R/W", 0, 0, 1ull, 0ull},
- {"S_BIST" , 7, 1, 541, "R/W", 0, 0, 0ull, 1ull},
- {"SD_MODE" , 8, 2, 541, "R/W", 0, 0, 0ull, 0ull},
- {"CDIV_BYP" , 10, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"P_C_SEL" , 11, 2, 541, "R/W", 0, 0, 2ull, 2ull},
- {"P_COM_ON" , 13, 1, 541, "R/W", 0, 0, 1ull, 1ull},
- {"P_XENBN" , 14, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"P_RCLK" , 15, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"P_X_ON" , 16, 1, 541, "R/W", 0, 0, 1ull, 1ull},
- {"HCLK_RST" , 17, 1, 541, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_18_63" , 18, 46, 541, "RAZ", 1, 1, 0, 0},
- {"L2C_EMOD" , 0, 2, 542, "R/W", 0, 0, 1ull, 1ull},
- {"INV_A2" , 2, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_TEST" , 3, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_STT" , 4, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_0PAG" , 5, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 542, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 543, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 543, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 544, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 544, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 545, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 545, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 546, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 546, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 547, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 547, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 548, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 548, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 549, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 549, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 550, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 550, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 551, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 551, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 552, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 552, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 553, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 553, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 554, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 554, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 555, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 555, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 556, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 556, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 557, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 557, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 558, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 558, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 4, 559, "R/W", 0, 0, 0ull, 0ull},
- {"CHANNEL" , 4, 5, 559, "R/W", 0, 0, 0ull, 0ull},
- {"COUNT" , 9, 11, 559, "R/W", 0, 0, 0ull, 0ull},
- {"F_ADDR" , 20, 18, 559, "R/W", 0, 0, 0ull, 0ull},
- {"REQ" , 38, 1, 559, "R/W1C", 0, 0, 0ull, 0ull},
- {"DONE" , 39, 1, 559, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 559, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_A_F" , 15, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_E" , 16, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_F" , 17, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PF" , 25, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"N2U_PF" , 26, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"N2U_PE" , 27, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"U2N_D_PE" , 28, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"U2N_D_PF" , 29, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"U2N_C_PF" , 30, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"U2N_C_PE" , 31, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"LTL_F_PE" , 32, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPF" , 35, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPE" , 36, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPF" , 37, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 560, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"L2C_A_F" , 15, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"LT_FI_E" , 16, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_FI_F" , 17, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"UOD_PF" , 25, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"N2U_PF" , 26, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"N2U_PE" , 27, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"U2N_D_PE" , 28, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"U2N_D_PF" , 29, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"U2N_C_PF" , 30, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"U2N_C_PE" , 31, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"LTL_F_PE" , 32, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_RPF" , 35, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPE" , 36, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPF" , 37, 1, 561, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_38_63" , 38, 26, 561, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_IN" , 1, 8, 562, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 9, 4, 562, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 13, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ENB" , 14, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_ENB" , 15, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_ENB" , 16, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_EN" , 17, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_ENH" , 18, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"TUNING" , 19, 4, 562, "R/W", 0, 0, 9ull, 0ull},
- {"HST_MODE" , 23, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"DM_PULLD" , 24, 1, 562, "R/W", 0, 0, 1ull, 1ull},
- {"DP_PULLD" , 25, 1, 562, "R/W", 0, 0, 1ull, 1ull},
- {"TCLK" , 26, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"USBP_BIST" , 27, 1, 562, "R/W", 0, 0, 1ull, 1ull},
- {"USBC_END" , 28, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_BMODE" , 29, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 562, "RAZ", 0, 0, 0ull, 0ull},
- {"TDATA_OUT" , 32, 4, 562, "RO", 1, 1, 0, 0},
- {"BIST_ERR" , 36, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 37, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 562, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 4, 0},
- {"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 4, 4},
- {"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 3, 8},
- {"cvmx_asx#_rld_bypass" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 11},
- {"cvmx_asx#_rld_bypass_setting", CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 13},
- {"cvmx_asx#_rld_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 3, 15},
- {"cvmx_asx#_rld_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 3, 18},
- {"cvmx_asx#_rld_fcram_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 21},
- {"cvmx_asx#_rld_nctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 23},
- {"cvmx_asx#_rld_nctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 25},
- {"cvmx_asx#_rld_pctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 27},
- {"cvmx_asx#_rld_pctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 29},
- {"cvmx_asx#_rld_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 31},
- {"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 33},
- {"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 35},
- {"cvmx_asx#_rx_wol" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 3, 37},
- {"cvmx_asx#_rx_wol_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 1, 40},
- {"cvmx_asx#_rx_wol_powok" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 2, 41},
- {"cvmx_asx#_rx_wol_sig" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 43},
- {"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 45},
- {"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 3, 47},
- {"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 50},
- {"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 52},
- {"cvmx_asx0_dbg_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 3, 54},
- {"cvmx_asx0_dbg_data_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 2, 57},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 66, 2, 59},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 67, 2, 61},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 68, 2, 63},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 69, 2, 65},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 70, 15, 67},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 103, 2, 82},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 136, 15, 84},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 169, 2, 99},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 170, 2, 101},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 2, 103},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 202, 2, 105},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 203, 2, 107},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 204, 2, 109},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 205, 1, 111},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 221, 3, 112},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 222, 2, 115},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 223, 4, 117},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 2, 121},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 3, 123},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 229, 7, 126},
- {"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 245, 7, 133},
- {"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 3, 140},
- {"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 247, 10, 143},
- {"cvmx_dfa_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 248, 5, 153},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 249, 2, 158},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 250, 4, 160},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 251, 3, 164},
- {"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 21, 167},
- {"cvmx_dfa_memcfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 253, 17, 188},
- {"cvmx_dfa_memcfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 11, 205},
- {"cvmx_dfa_memcfg2" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 8, 216},
- {"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 256, 6, 224},
- {"cvmx_dfa_memfcr" , CVMX_CSR_DB_TYPE_RSL, 64, 257, 6, 230},
- {"cvmx_dfa_memrld" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 236},
- {"cvmx_dfa_ncbctl" , CVMX_CSR_DB_TYPE_RSL, 64, 259, 8, 238},
- {"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 260, 1, 246},
- {"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 1, 247},
- {"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 262, 1, 248},
- {"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 263, 1, 249},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 6, 250},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 265, 7, 256},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 266, 3, 263},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 2, 266},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 280, 3, 268},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 281, 2, 271},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 29, 273},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 283, 29, 302},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 284, 2, 331},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 2, 333},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 3, 335},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 301, 3, 338},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 2, 341},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 2, 343},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 304, 8, 345},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 306, 2, 353},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 3, 355},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 310, 2, 358},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 312, 5, 360},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 320, 1, 365},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 328, 1, 366},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 336, 1, 367},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 344, 1, 368},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 352, 1, 369},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 360, 1, 370},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 368, 2, 371},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 4, 373},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 384, 2, 377},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 11, 379},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 10, 390},
- {"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 400},
- {"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 2, 402},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 2, 404},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 20, 406},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 20, 426},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 446},
- {"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 4, 448},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 2, 452},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 2, 454},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 480, 2, 456},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 488, 2, 458},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 496, 2, 460},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 504, 2, 462},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 512, 2, 464},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 520, 2, 466},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 528, 2, 468},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 536, 2, 470},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 544, 4, 472},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 552, 2, 476},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 560, 2, 478},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 568, 2, 480},
- {"cvmx_gmx#_rx_pass_en" , CVMX_CSR_DB_TYPE_RSL, 64, 576, 2, 482},
- {"cvmx_gmx#_rx_pass_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 578, 2, 484},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 610, 3, 486},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 612, 2, 489},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 614, 2, 491},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 622, 3, 493},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 624, 5, 496},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 632, 2, 501},
- {"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 640, 2, 503},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 648, 3, 505},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 656, 2, 508},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 664, 2, 510},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 672, 2, 512},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 680, 2, 514},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 688, 2, 516},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 696, 2, 518},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 704, 2, 520},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 712, 2, 522},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 720, 2, 524},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 728, 2, 526},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 736, 2, 528},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 744, 2, 530},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 752, 2, 532},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 760, 2, 534},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 768, 2, 536},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 776, 2, 538},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 784, 2, 540},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 792, 2, 542},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 800, 2, 544},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 2, 546},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 2, 548},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 2, 550},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 814, 3, 552},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 8, 555},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 818, 8, 563},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 2, 571},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 2, 573},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 4, 575},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 2, 579},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 2, 581},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 830, 2, 583},
- {"cvmx_gmx#_tx_spi_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 832, 3, 585},
- {"cvmx_gmx#_tx_spi_drain" , CVMX_CSR_DB_TYPE_RSL, 64, 834, 2, 588},
- {"cvmx_gmx#_tx_spi_max" , CVMX_CSR_DB_TYPE_RSL, 64, 836, 3, 590},
- {"cvmx_gmx#_tx_spi_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 838, 2, 593},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 840, 7, 595},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 856, 2, 602},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 857, 2, 604},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 858, 2, 606},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 859, 2, 608},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 860, 19, 610},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 861, 6, 629},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 862, 3, 635},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 3, 638},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 864, 3, 641},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 5, 644},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 866, 5, 649},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 1, 654},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 868, 1, 655},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 869, 5, 656},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 870, 5, 661},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 871, 3, 666},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 872, 3, 669},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 873, 3, 672},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 874, 5, 675},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 875, 5, 680},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 876, 1, 685},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 877, 1, 686},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 878, 3, 687},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 879, 3, 690},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 880, 3, 693},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 881, 2, 696},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 882, 2, 698},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 883, 2, 700},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 884, 2, 702},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 885, 17, 704},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 886, 2, 721},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 887, 1, 723},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 888, 10, 724},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 889, 11, 734},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 890, 11, 745},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 891, 2, 756},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 892, 2, 758},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 893, 2, 760},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 894, 3, 762},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 930, 2, 765},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 966, 6, 767},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 967, 5, 773},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 968, 6, 778},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 969, 7, 784},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 970, 2, 791},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 978, 2, 793},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 979, 3, 795},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 980, 5, 798},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 988, 3, 803},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 989, 2, 806},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 990, 2, 808},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 991, 2, 810},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 4, 812},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 993, 3, 816},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 994, 5, 819},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 5, 824},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 996, 5, 829},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 997, 5, 834},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 8, 839},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 999, 9, 847},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1000, 8, 856},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 1001, 5, 864},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 1002, 4, 869},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 2, 873},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 14, 875},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 1005, 19, 889},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 3, 908},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 1007, 3, 911},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1008, 2, 914},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1012, 17, 916},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1013, 5, 933},
- {"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1014, 5, 938},
- {"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1015, 5, 943},
- {"cvmx_l2c_spar3" , CVMX_CSR_DB_TYPE_RSL, 64, 1016, 5, 948},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1017, 2, 953},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1018, 3, 955},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 2, 958},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1020, 2, 960},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1021, 2, 962},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1022, 7, 964},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 4, 971},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 3, 975},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 3, 978},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 2, 981},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 983},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 2, 985},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 4, 987},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 13, 991},
- {"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1031, 2, 1004},
- {"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1032, 2, 1006},
- {"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1033, 2, 1008},
- {"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1034, 2, 1010},
- {"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 2, 1012},
- {"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1036, 2, 1014},
- {"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1037, 2, 1016},
- {"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 2, 1018},
- {"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1039, 2, 1020},
- {"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1047, 2, 1022},
- {"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1049, 2, 1024},
- {"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 2, 1026},
- {"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 2, 1028},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 9, 1030},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1056, 19, 1039},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 2, 1058},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1058, 2, 1060},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 18, 1062},
- {"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1060, 6, 1080},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 5, 1086},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1062, 6, 1091},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1063, 2, 1097},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1064, 2, 1099},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1065, 14, 1101},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1066, 9, 1115},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1067, 2, 1124},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1068, 2, 1126},
- {"cvmx_lmc#_pll_bwctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1069, 3, 1128},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1070, 9, 1131},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1071, 9, 1140},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1072, 4, 1149},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1073, 3, 1153},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1074, 3, 1156},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1075, 3, 1159},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1076, 5, 1162},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1078, 1, 1167},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1079, 6, 1168},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1087, 13, 1174},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1095, 4, 1187},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1096, 2, 1191},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1097, 2, 1193},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1098, 8, 1195},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1099, 8, 1203},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1100, 2, 1211},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1101, 8, 1213},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 1102, 4, 1221},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 2, 1225},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1104, 2, 1227},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 13, 1229},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1106, 12, 1242},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 3, 1254},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1108, 3, 1257},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 2, 1260},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1111, 2, 1262},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1113, 2, 1264},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1115, 7, 1266},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 2, 1273},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1119, 7, 1275},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1121, 4, 1282},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1123, 8, 1286},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1125, 9, 1294},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1127, 7, 1303},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1129, 9, 1310},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1131, 2, 1319},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1133, 2, 1321},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1135, 4, 1323},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1137, 2, 1327},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1139, 2, 1329},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1141, 2, 1331},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1143, 4, 1333},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 2, 1337},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1147, 2, 1339},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1149, 2, 1341},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1151, 2, 1343},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1153, 2, 1345},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1155, 2, 1347},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1157, 6, 1349},
- {"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1159, 2, 1355},
- {"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1163, 2, 1357},
- {"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1167, 21, 1359},
- {"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1168, 3, 1380},
- {"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1172, 21, 1383},
- {"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 1173, 2, 1404},
- {"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1174, 13, 1406},
- {"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1175, 3, 1419},
- {"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1176, 3, 1422},
- {"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1177, 3, 1425},
- {"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1178, 3, 1428},
- {"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1179, 2, 1431},
- {"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1180, 2, 1433},
- {"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1181, 10, 1435},
- {"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1182, 63, 1445},
- {"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1183, 63, 1508},
- {"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1184, 2, 1571},
- {"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1185, 2, 1573},
- {"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 1186, 10, 1575},
- {"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1190, 1, 1585},
- {"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1191, 2, 1586},
- {"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1195, 39, 1588},
- {"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1196, 3, 1627},
- {"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1200, 2, 1630},
- {"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1204, 3, 1632},
- {"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1208, 3, 1635},
- {"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1212, 3, 1638},
- {"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 1213, 4, 1641},
- {"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 1214, 2, 1645},
- {"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1215, 13, 1647},
- {"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1216, 13, 1660},
- {"cvmx_npi_port34_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1217, 13, 1673},
- {"cvmx_npi_port35_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1218, 13, 1686},
- {"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1219, 3, 1699},
- {"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 1220, 33, 1702},
- {"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1221, 2, 1735},
- {"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 1225, 2, 1737},
- {"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1226, 5, 1739},
- {"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1258, 2, 1744},
- {"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1259, 24, 1746},
- {"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1260, 2, 1770},
- {"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1261, 7, 1772},
- {"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1262, 5, 1779},
- {"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1263, 1, 1784},
- {"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1264, 5, 1785},
- {"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1265, 1, 1790},
- {"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1266, 4, 1791},
- {"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1267, 2, 1795},
- {"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1268, 1, 1797},
- {"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1269, 2, 1798},
- {"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1270, 4, 1800},
- {"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1271, 2, 1804},
- {"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1272, 4, 1806},
- {"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1273, 16, 1810},
- {"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1274, 1, 1826},
- {"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1275, 1, 1827},
- {"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1276, 18, 1828},
- {"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1277, 1, 1846},
- {"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1278, 1, 1847},
- {"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1279, 7, 1848},
- {"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1280, 7, 1855},
- {"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1281, 13, 1862},
- {"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1282, 10, 1875},
- {"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1283, 10, 1885},
- {"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1284, 7, 1895},
- {"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1285, 2, 1902},
- {"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1286, 1, 1904},
- {"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1287, 2, 1905},
- {"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1288, 22, 1907},
- {"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 1289, 2, 1929},
- {"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 1293, 1, 1931},
- {"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1295, 1, 1932},
- {"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1297, 1, 1933},
- {"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 1299, 1, 1934},
- {"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 1303, 35, 1935},
- {"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1304, 35, 1970},
- {"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 1305, 35, 2005},
- {"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1306, 35, 2040},
- {"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 1307, 2, 2075},
- {"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 1308, 2, 2077},
- {"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 1312, 1, 2079},
- {"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1316, 1, 2080},
- {"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1320, 1, 2081},
- {"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1324, 3, 2082},
- {"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1325, 3, 2085},
- {"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1326, 3, 2088},
- {"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 1327, 3, 2091},
- {"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1328, 2, 2094},
- {"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1329, 2, 2096},
- {"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1330, 4, 2098},
- {"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1331, 1, 2102},
- {"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1332, 4, 2103},
- {"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1333, 1, 2107},
- {"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 1334, 2, 2108},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1335, 5, 2110},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1336, 2, 2115},
- {"cvmx_pip_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 1337, 3, 2117},
- {"cvmx_pip_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 1339, 2, 2120},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1341, 4, 2122},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1345, 8, 2126},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1346, 16, 2134},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1347, 10, 2150},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1348, 10, 2160},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1349, 2, 2170},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1350, 18, 2172},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1386, 25, 2190},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1422, 2, 2215},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1486, 2, 2217},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1494, 9, 2219},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1498, 2, 2228},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1499, 2, 2230},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1500, 2, 2232},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1536, 2, 2234},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1572, 2, 2236},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1608, 2, 2238},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1644, 2, 2240},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1680, 2, 2242},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1716, 2, 2244},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1752, 2, 2246},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1788, 2, 2248},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1824, 2, 2250},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1860, 2, 2252},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1861, 2, 2254},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1897, 2, 2256},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 1933, 2, 2258},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1969, 2, 2260},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2033, 2, 2262},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2034, 3, 2264},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2035, 3, 2267},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2036, 2, 2270},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2037, 2, 2272},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2038, 4, 2274},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2039, 5, 2278},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2040, 4, 2283},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2041, 5, 2287},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2042, 1, 2292},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2043, 4, 2293},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2044, 2, 2297},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2045, 5, 2299},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2046, 5, 2304},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2047, 1, 2309},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2048, 19, 2310},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2049, 7, 2329},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2050, 4, 2336},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2051, 6, 2340},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2052, 7, 2346},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2053, 9, 2353},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2054, 5, 2362},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2055, 13, 2367},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2056, 4, 2380},
- {"cvmx_pko_reg_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 2057, 3, 2384},
- {"cvmx_pko_reg_crc_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 2059, 2, 2387},
- {"cvmx_pko_reg_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 2060, 2, 2389},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2062, 2, 2391},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2063, 3, 2393},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2064, 5, 2396},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2065, 3, 2401},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2066, 3, 2404},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2067, 2, 2407},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2068, 3, 2409},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2069, 13, 2412},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2070, 2, 2425},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2071, 13, 2427},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2072, 3, 2440},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2073, 2, 2443},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2081, 2, 2445},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2082, 2, 2447},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2083, 2, 2449},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2084, 2, 2451},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2100, 5, 2453},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2108, 8, 2458},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2116, 2, 2466},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2117, 2, 2468},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2118, 2, 2470},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2126, 3, 2472},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2127, 4, 2475},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2143, 5, 2479},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2144, 7, 2484},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2160, 2, 2491},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 3, 2493},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2177, 5, 2496},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2178, 8, 2501},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2179, 6, 2509},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 2, 2515},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2181, 4, 2517},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 4, 2521},
- {"cvmx_spx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2183, 2, 2525},
- {"cvmx_spx#_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2185, 4, 2527},
- {"cvmx_spx#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2187, 11, 2531},
- {"cvmx_spx#_clk_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2189, 9, 2542},
- {"cvmx_spx#_dbg_deskew_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2191, 16, 2551},
- {"cvmx_spx#_dbg_deskew_state" , CVMX_CSR_DB_TYPE_RSL, 64, 2193, 5, 2567},
- {"cvmx_spx#_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2195, 4, 2572},
- {"cvmx_spx#_err_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2197, 6, 2576},
- {"cvmx_spx#_int_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2199, 6, 2582},
- {"cvmx_spx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2201, 12, 2588},
- {"cvmx_spx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2203, 14, 2600},
- {"cvmx_spx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2205, 12, 2614},
- {"cvmx_spx#_tpa_acc" , CVMX_CSR_DB_TYPE_RSL, 64, 2207, 2, 2626},
- {"cvmx_spx#_tpa_max" , CVMX_CSR_DB_TYPE_RSL, 64, 2209, 2, 2628},
- {"cvmx_spx#_tpa_sel" , CVMX_CSR_DB_TYPE_RSL, 64, 2211, 2, 2630},
- {"cvmx_spx#_trn4_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2213, 8, 2632},
- {"cvmx_spx0_pll_bw_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2215, 2, 2640},
- {"cvmx_spx0_pll_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 2216, 2, 2642},
- {"cvmx_srx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2217, 5, 2644},
- {"cvmx_srx#_ign_rx_full" , CVMX_CSR_DB_TYPE_RSL, 64, 2219, 2, 2649},
- {"cvmx_srx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2221, 6, 2651},
- {"cvmx_srx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2285, 4, 2657},
- {"cvmx_srx#_sw_tick_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2287, 6, 2661},
- {"cvmx_srx#_sw_tick_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2289, 1, 2667},
- {"cvmx_stx#_arb_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2291, 5, 2668},
- {"cvmx_stx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2293, 2, 2673},
- {"cvmx_stx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2295, 4, 2675},
- {"cvmx_stx#_dip_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2297, 3, 2679},
- {"cvmx_stx#_ign_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 2299, 2, 2682},
- {"cvmx_stx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2301, 9, 2684},
- {"cvmx_stx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2303, 10, 2693},
- {"cvmx_stx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2305, 9, 2703},
- {"cvmx_stx#_min_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 2307, 2, 2712},
- {"cvmx_stx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2309, 6, 2714},
- {"cvmx_stx#_spi4_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2373, 3, 2720},
- {"cvmx_stx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2375, 4, 2723},
- {"cvmx_stx#_stat_bytes_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 2377, 2, 2727},
- {"cvmx_stx#_stat_bytes_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 2379, 2, 2729},
- {"cvmx_stx#_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2381, 3, 2731},
- {"cvmx_stx#_stat_pkt_xmt" , CVMX_CSR_DB_TYPE_RSL, 64, 2383, 2, 2734},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2385, 6, 2736},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2386, 3, 2742},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2387, 5, 2745},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2388, 4, 2750},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2389, 6, 2754},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2390, 4, 2760},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2391, 2, 2764},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2392, 4, 2766},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2393, 2, 2770},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2394, 3, 2772},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2395, 4, 2775},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2396, 12, 2779},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2397, 3, 2791},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2398, 2, 2794},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2399, 2, 2796},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2400, 17, 2798},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2401, 12, 2815},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2402, 6, 2827},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2403, 5, 2833},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2404, 1, 2838},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2405, 2, 2839},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2406, 2, 2841},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2407, 17, 2843},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2408, 12, 2860},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2409, 6, 2872},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2410, 2, 2878},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2411, 2, 2880},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2412, 17, 2882},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2413, 12, 2899},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2414, 6, 2911},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2415, 3, 2917},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2416, 5, 2920},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2417, 3, 2925},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2418, 6, 2928},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2419, 2, 2934},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2420, 2, 2936},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2421, 2, 2938},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"ASX0_INT_EN" , 0x11800b0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX1_INT_EN" , 0x11800b8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX0_INT_REG" , 0x11800b0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX1_INT_REG" , 0x11800b8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX0_PRT_LOOP" , 0x11800b0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX1_PRT_LOOP" , 0x11800b8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX0_RLD_BYPASS" , 0x11800b0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX1_RLD_BYPASS" , 0x11800b8000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX0_RLD_BYPASS_SETTING" , 0x11800b0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX1_RLD_BYPASS_SETTING" , 0x11800b8000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX0_RLD_COMP" , 0x11800b0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX1_RLD_COMP" , 0x11800b8000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX0_RLD_DATA_DRV" , 0x11800b0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX1_RLD_DATA_DRV" , 0x11800b8000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_RLD_FCRAM_MODE" , 0x11800b0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX1_RLD_FCRAM_MODE" , 0x11800b8000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX0_RLD_NCTL_STRONG" , 0x11800b0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX1_RLD_NCTL_STRONG" , 0x11800b8000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_RLD_NCTL_WEAK" , 0x11800b0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX1_RLD_NCTL_WEAK" , 0x11800b8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX0_RLD_PCTL_STRONG" , 0x11800b0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX1_RLD_PCTL_STRONG" , 0x11800b8000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX0_RLD_PCTL_WEAK" , 0x11800b0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"ASX1_RLD_PCTL_WEAK" , 0x11800b8000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"ASX0_RLD_SETTING" , 0x11800b0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX1_RLD_SETTING" , 0x11800b8000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX0_RX_CLK_SET000" , 0x11800b0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX0_RX_CLK_SET001" , 0x11800b0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX0_RX_CLK_SET002" , 0x11800b0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX0_RX_CLK_SET003" , 0x11800b0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX1_RX_CLK_SET000" , 0x11800b8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX1_RX_CLK_SET001" , 0x11800b8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX1_RX_CLK_SET002" , 0x11800b8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX1_RX_CLK_SET003" , 0x11800b8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX0_RX_PRT_EN" , 0x11800b0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX1_RX_PRT_EN" , 0x11800b8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX0_RX_WOL" , 0x11800b0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"ASX1_RX_WOL" , 0x11800b8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"ASX0_RX_WOL_MSK" , 0x11800b0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX1_RX_WOL_MSK" , 0x11800b8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX0_RX_WOL_POWOK" , 0x11800b0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"ASX1_RX_WOL_POWOK" , 0x11800b8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"ASX0_RX_WOL_SIG" , 0x11800b0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"ASX1_RX_WOL_SIG" , 0x11800b8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"ASX0_TX_CLK_SET000" , 0x11800b0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX0_TX_CLK_SET001" , 0x11800b0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX0_TX_CLK_SET002" , 0x11800b0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX0_TX_CLK_SET003" , 0x11800b0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX1_TX_CLK_SET000" , 0x11800b8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX1_TX_CLK_SET001" , 0x11800b8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX1_TX_CLK_SET002" , 0x11800b8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX1_TX_CLK_SET003" , 0x11800b8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"ASX0_TX_COMP_BYP" , 0x11800b0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"ASX1_TX_COMP_BYP" , 0x11800b8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"ASX0_TX_HI_WATER000" , 0x11800b0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX0_TX_HI_WATER001" , 0x11800b0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX0_TX_HI_WATER002" , 0x11800b0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX0_TX_HI_WATER003" , 0x11800b0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX1_TX_HI_WATER000" , 0x11800b8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX1_TX_HI_WATER001" , 0x11800b8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX1_TX_HI_WATER002" , 0x11800b8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX1_TX_HI_WATER003" , 0x11800b8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"ASX0_TX_PRT_EN" , 0x11800b0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"ASX1_TX_PRT_EN" , 0x11800b8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"ASX0_DBG_DATA_DRV" , 0x11800b0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"ASX0_DBG_DATA_ENABLE" , 0x11800b0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT10_EN0" , 0x10700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT11_EN0" , 0x10700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT12_EN0" , 0x10700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT13_EN0" , 0x10700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT14_EN0" , 0x10700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT15_EN0" , 0x10700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT24_EN0" , 0x1070000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT25_EN0" , 0x1070000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT26_EN0" , 0x10700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT27_EN0" , 0x10700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT28_EN0" , 0x10700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT29_EN0" , 0x10700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT30_EN0" , 0x10700000003e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT31_EN0" , 0x10700000003f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT10_EN1" , 0x10700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT11_EN1" , 0x10700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT12_EN1" , 0x10700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT13_EN1" , 0x10700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT14_EN1" , 0x10700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT15_EN1" , 0x10700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT24_EN1" , 0x1070000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT25_EN1" , 0x1070000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT26_EN1" , 0x10700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT27_EN1" , 0x10700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT28_EN1" , 0x10700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT29_EN1" , 0x10700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT30_EN1" , 0x10700000003e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT31_EN1" , 0x10700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT20_SUM0" , 0x10700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT21_SUM0" , 0x10700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT22_SUM0" , 0x10700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT23_SUM0" , 0x10700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT24_SUM0" , 0x10700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT25_SUM0" , 0x10700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT26_SUM0" , 0x10700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT27_SUM0" , 0x10700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT28_SUM0" , 0x10700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT29_SUM0" , 0x10700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT30_SUM0" , 0x10700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT31_SUM0" , 0x10700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR4" , 0x10700000006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR5" , 0x10700000006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR6" , 0x10700000006b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR7" , 0x10700000006b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR8" , 0x10700000006c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR9" , 0x10700000006c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR10" , 0x10700000006d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR11" , 0x10700000006d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR12" , 0x10700000006e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR13" , 0x10700000006e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR14" , 0x10700000006f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR15" , 0x10700000006f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET12" , 0x1070000000660ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET13" , 0x1070000000668ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET14" , 0x1070000000670ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET15" , 0x1070000000678ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE4" , 0x10700000005a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE5" , 0x10700000005a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE6" , 0x10700000005b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE7" , 0x10700000005b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE8" , 0x10700000005c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE9" , 0x10700000005c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE10" , 0x10700000005d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE11" , 0x10700000005d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE12" , 0x10700000005e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE13" , 0x10700000005e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE14" , 0x10700000005f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE15" , 0x10700000005f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG12" , 0x1070000000560ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG13" , 0x1070000000568ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG14" , 0x1070000000570ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_WDOG15" , 0x1070000000578ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"DBG_DATA" , 0x11f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
- {"DFA_BST0" , 0x11800300007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"DFA_BST1" , 0x11800300007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"DFA_CFG" , 0x1180030000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
- {"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"DFA_MEMCFG0" , 0x1180030000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"DFA_MEMCFG1" , 0x1180030000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"DFA_MEMCFG2" , 0x1180030000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"DFA_MEMFCR" , 0x1180030000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"DFA_MEMRLD" , 0x1180030000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"DFA_NCBCTL" , 0x1180030000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX1_INF_MODE" , 0x11800100007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX000_ADR_CAM4" , 0x11800100001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX001_ADR_CAM4" , 0x11800100009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX002_ADR_CAM4" , 0x11800100011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX003_ADR_CAM4" , 0x11800100019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX000_ADR_CAM5" , 0x11800100001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX001_ADR_CAM5" , 0x11800100009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX002_ADR_CAM5" , 0x11800100011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX003_ADR_CAM5" , 0x11800100019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX003_FRM_MAX" , 0x1180008001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX000_FRM_MAX" , 0x1180010000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX001_FRM_MAX" , 0x1180010000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX002_FRM_MAX" , 0x1180010001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX003_FRM_MAX" , 0x1180010001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX003_FRM_MIN" , 0x1180008001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX000_FRM_MIN" , 0x1180010000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX001_FRM_MIN" , 0x1180010000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX002_FRM_MIN" , 0x1180010001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX003_FRM_MIN" , 0x1180010001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX003_RX_INBND" , 0x1180008001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX000_RX_INBND" , 0x1180010000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX001_RX_INBND" , 0x1180010000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX002_RX_INBND" , 0x1180010001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX003_RX_INBND" , 0x1180010001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_PASS_EN" , 0x11800080005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX1_RX_PASS_EN" , 0x11800100005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX_PASS_MAP000" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP001" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP002" , 0x1180008000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP003" , 0x1180008000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP004" , 0x1180008000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP005" , 0x1180008000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP006" , 0x1180008000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP007" , 0x1180008000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP008" , 0x1180008000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP009" , 0x1180008000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP010" , 0x1180008000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP011" , 0x1180008000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP012" , 0x1180008000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP013" , 0x1180008000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP014" , 0x1180008000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP015" , 0x1180008000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP000" , 0x1180010000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP001" , 0x1180010000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP002" , 0x1180010000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP003" , 0x1180010000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP004" , 0x1180010000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP005" , 0x1180010000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP006" , 0x1180010000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP007" , 0x1180010000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP008" , 0x1180010000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP009" , 0x1180010000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP010" , 0x1180010000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP011" , 0x1180010000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP012" , 0x1180010000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP013" , 0x1180010000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP014" , 0x1180010000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP015" , 0x1180010000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_RX_PRT_INFO" , 0x11800100004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_SMAC001" , 0x1180010000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_SMAC003" , 0x1180010001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX001_APPEND" , 0x1180010000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX003_APPEND" , 0x1180010001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX001_BURST" , 0x1180010000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX003_BURST" , 0x1180010001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX001_CLK" , 0x1180008000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX003_CLK" , 0x1180008001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX000_CLK" , 0x1180010000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX001_CLK" , 0x1180010000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX002_CLK" , 0x1180010001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX003_CLK" , 0x1180010001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX001_CTL" , 0x1180010000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX003_CTL" , 0x1180010001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX001_MIN_PKT" , 0x1180010000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX003_MIN_PKT" , 0x1180010001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX001_PAUSE_TOGO" , 0x1180010000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX003_PAUSE_TOGO" , 0x1180010001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX001_PAUSE_ZERO" , 0x1180010000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX003_PAUSE_ZERO" , 0x1180010001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX001_SLOT" , 0x1180010000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX003_SLOT" , 0x1180010001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX001_SOFT_PAUSE" , 0x1180010000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX003_SOFT_PAUSE" , 0x1180010001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX001_STAT0" , 0x1180010000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX003_STAT0" , 0x1180010001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX001_STAT1" , 0x1180010000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX003_STAT1" , 0x1180010001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX001_STAT2" , 0x1180010000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX003_STAT2" , 0x1180010001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX001_STAT3" , 0x1180010000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX003_STAT3" , 0x1180010001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX000_STAT4" , 0x11800100002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX001_STAT4" , 0x1180010000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX002_STAT4" , 0x11800100012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX003_STAT4" , 0x1180010001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX000_STAT5" , 0x11800100002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX001_STAT5" , 0x1180010000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX002_STAT5" , 0x11800100012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX003_STAT5" , 0x1180010001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX000_STAT6" , 0x11800100002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX001_STAT6" , 0x1180010000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX002_STAT6" , 0x11800100012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX003_STAT6" , 0x1180010001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX000_STAT7" , 0x11800100002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX001_STAT7" , 0x1180010000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX002_STAT7" , 0x11800100012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX003_STAT7" , 0x1180010001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX000_STAT8" , 0x11800100002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX001_STAT8" , 0x1180010000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX002_STAT8" , 0x11800100012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX003_STAT8" , 0x1180010001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX000_STAT9" , 0x11800100002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX001_STAT9" , 0x1180010000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX002_STAT9" , 0x11800100012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX003_STAT9" , 0x1180010001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX001_STATS_CTL" , 0x1180010000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX003_STATS_CTL" , 0x1180010001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX001_THRESH" , 0x1180010000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX003_THRESH" , 0x1180010001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_TX_BP" , 0x11800100004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_TX_CORRUPT" , 0x11800100004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_TX_LFSR" , 0x11800100004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_TX_OVR_BP" , 0x11800100004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX_SPI_CTL" , 0x11800080004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_TX_SPI_CTL" , 0x11800100004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX_SPI_DRAIN" , 0x11800080004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_TX_SPI_DRAIN" , 0x11800100004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX_SPI_MAX" , 0x11800080004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX1_TX_SPI_MAX" , 0x11800100004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX_SPI_THRESH" , 0x11800080004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_THRESH" , 0x11800100004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT4_BP_PAGE_CNT" , 0x14f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT5_BP_PAGE_CNT" , 0x14f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT6_BP_PAGE_CNT" , 0x14f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT7_BP_PAGE_CNT" , 0x14f0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT8_BP_PAGE_CNT" , 0x14f0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT9_BP_PAGE_CNT" , 0x14f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT10_BP_PAGE_CNT" , 0x14f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT11_BP_PAGE_CNT" , 0x14f0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT12_BP_PAGE_CNT" , 0x14f0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT13_BP_PAGE_CNT" , 0x14f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT14_BP_PAGE_CNT" , 0x14f0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT15_BP_PAGE_CNT" , 0x14f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT16_BP_PAGE_CNT" , 0x14f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT17_BP_PAGE_CNT" , 0x14f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT18_BP_PAGE_CNT" , 0x14f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT19_BP_PAGE_CNT" , 0x14f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT20_BP_PAGE_CNT" , 0x14f00000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT21_BP_PAGE_CNT" , 0x14f00000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT22_BP_PAGE_CNT" , 0x14f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT23_BP_PAGE_CNT" , 0x14f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT24_BP_PAGE_CNT" , 0x14f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT25_BP_PAGE_CNT" , 0x14f00000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT26_BP_PAGE_CNT" , 0x14f00000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT27_BP_PAGE_CNT" , 0x14f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT28_BP_PAGE_CNT" , 0x14f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT29_BP_PAGE_CNT" , 0x14f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT30_BP_PAGE_CNT" , 0x14f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT31_BP_PAGE_CNT" , 0x14f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR4" , 0x14f00000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR5" , 0x14f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR6" , 0x14f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR7" , 0x14f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR8" , 0x14f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR9" , 0x14f0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR10" , 0x14f0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR11" , 0x14f0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR12" , 0x14f0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR13" , 0x14f0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR14" , 0x14f0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR15" , 0x14f0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14f0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14f0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14f0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14f0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR20" , 0x14f0000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR21" , 0x14f0000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR22" , 0x14f0000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR23" , 0x14f0000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR24" , 0x14f0000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR25" , 0x14f0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR26" , 0x14f0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR27" , 0x14f0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR28" , 0x14f0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR29" , 0x14f00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR30" , 0x14f00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR31" , 0x14f00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"L2C_SPAR3" , 0x1180080000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"LED_BLINK" , 0x1180000001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"LED_CLK_PHASE" , 0x1180000001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"LED_CYLON" , 0x1180000001af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"LED_DBG" , 0x1180000001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"LED_EN" , 0x1180000001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"LED_POLARITY" , 0x1180000001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"LED_PRT" , 0x1180000001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"LED_PRT_FMT" , 0x1180000001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"LED_PRT_STATUS0" , 0x1180000001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LED_PRT_STATUS1" , 0x1180000001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LED_PRT_STATUS2" , 0x1180000001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LED_PRT_STATUS3" , 0x1180000001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LED_PRT_STATUS4" , 0x1180000001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LED_PRT_STATUS5" , 0x1180000001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LED_PRT_STATUS6" , 0x1180000001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LED_PRT_STATUS7" , 0x1180000001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LED_UDD_CNT0" , 0x1180000001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_UDD_CNT1" , 0x1180000001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_UDD_DAT0" , 0x1180000001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"LED_UDD_DAT1" , 0x1180000001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"LED_UDD_DAT_CLR0" , 0x1180000001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"LED_UDD_DAT_CLR1" , 0x1180000001ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"LED_UDD_DAT_SET0" , 0x1180000001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"LED_UDD_DAT_SET1" , 0x1180000001ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"LMC0_PLL_BWCTL" , 0x1180088000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"NPI_BASE_ADDR_INPUT0" , 0x11f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"NPI_BASE_ADDR_INPUT1" , 0x11f0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"NPI_BASE_ADDR_INPUT2" , 0x11f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"NPI_BASE_ADDR_INPUT3" , 0x11f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"NPI_BASE_ADDR_OUTPUT0" , 0x11f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"NPI_BASE_ADDR_OUTPUT1" , 0x11f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"NPI_BASE_ADDR_OUTPUT2" , 0x11f00000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"NPI_BASE_ADDR_OUTPUT3" , 0x11f00000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"NPI_BIST_STATUS" , 0x11f00000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"NPI_BUFF_SIZE_OUTPUT0" , 0x11f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"NPI_BUFF_SIZE_OUTPUT1" , 0x11f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"NPI_BUFF_SIZE_OUTPUT2" , 0x11f00000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"NPI_BUFF_SIZE_OUTPUT3" , 0x11f00000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"NPI_CTL_STATUS" , 0x11f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
- {"NPI_DBG_SELECT" , 0x11f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
- {"NPI_DMA_CONTROL" , 0x11f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"NPI_DMA_HIGHP_COUNTS" , 0x11f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"NPI_DMA_HIGHP_NADDR" , 0x11f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"NPI_DMA_LOWP_COUNTS" , 0x11f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"NPI_DMA_LOWP_NADDR" , 0x11f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"NPI_HIGHP_DBELL" , 0x11f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"NPI_HIGHP_IBUFF_SADDR" , 0x11f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"NPI_INPUT_CONTROL" , 0x11f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"NPI_INT_ENB" , 0x11f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"NPI_INT_SUM" , 0x11f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"NPI_LOWP_DBELL" , 0x11f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"NPI_LOWP_IBUFF_SADDR" , 0x11f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"NPI_MEM_ACCESS_SUBID3" , 0x11f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"NPI_MEM_ACCESS_SUBID4" , 0x11f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"NPI_MEM_ACCESS_SUBID5" , 0x11f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"NPI_MEM_ACCESS_SUBID6" , 0x11f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"NPI_MSI_RCV" , 0x11f0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 345},
- {"NPI_NUM_DESC_OUTPUT0" , 0x11f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"NPI_NUM_DESC_OUTPUT1" , 0x11f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"NPI_NUM_DESC_OUTPUT2" , 0x11f0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"NPI_NUM_DESC_OUTPUT3" , 0x11f0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"NPI_OUTPUT_CONTROL" , 0x11f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
- {"NPI_P0_DBPAIR_ADDR" , 0x11f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"NPI_P1_DBPAIR_ADDR" , 0x11f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"NPI_P2_DBPAIR_ADDR" , 0x11f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"NPI_P3_DBPAIR_ADDR" , 0x11f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"NPI_P0_INSTR_ADDR" , 0x11f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"NPI_P1_INSTR_ADDR" , 0x11f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"NPI_P2_INSTR_ADDR" , 0x11f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"NPI_P3_INSTR_ADDR" , 0x11f00000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"NPI_P0_INSTR_CNTS" , 0x11f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"NPI_P1_INSTR_CNTS" , 0x11f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"NPI_P2_INSTR_CNTS" , 0x11f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"NPI_P3_INSTR_CNTS" , 0x11f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"NPI_P0_PAIR_CNTS" , 0x11f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"NPI_P1_PAIR_CNTS" , 0x11f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"NPI_P2_PAIR_CNTS" , 0x11f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"NPI_P3_PAIR_CNTS" , 0x11f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"NPI_PCI_BURST_SIZE" , 0x11f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
- {"NPI_PCI_INT_ARB_CFG" , 0x11f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 353},
- {"NPI_PCI_READ_CMD" , 0x11f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"NPI_PORT32_INSTR_HDR" , 0x11f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 355},
- {"NPI_PORT33_INSTR_HDR" , 0x11f0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
- {"NPI_PORT34_INSTR_HDR" , 0x11f0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 357},
- {"NPI_PORT35_INSTR_HDR" , 0x11f0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
- {"NPI_PORT_BP_CONTROL" , 0x11f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
- {"NPI_RSL_INT_BLOCKS" , 0x11f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
- {"NPI_SIZE_INPUT0" , 0x11f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
- {"NPI_SIZE_INPUT1" , 0x11f0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
- {"NPI_SIZE_INPUT2" , 0x11f0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
- {"NPI_SIZE_INPUT3" , 0x11f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
- {"NPI_WIN_READ_TO" , 0x11f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
- {"PCI_BAR1_INDEX0" , 0x11f0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX1" , 0x11f0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX2" , 0x11f0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX3" , 0x11f000000110cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX4" , 0x11f0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX5" , 0x11f0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX6" , 0x11f0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX7" , 0x11f000000111cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX8" , 0x11f0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX9" , 0x11f0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX10" , 0x11f0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX11" , 0x11f000000112cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX12" , 0x11f0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX13" , 0x11f0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX14" , 0x11f0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX15" , 0x11f000000113cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX16" , 0x11f0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX17" , 0x11f0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX18" , 0x11f0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX19" , 0x11f000000114cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX20" , 0x11f0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX21" , 0x11f0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX22" , 0x11f0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX23" , 0x11f000000115cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX24" , 0x11f0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX25" , 0x11f0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX26" , 0x11f0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX27" , 0x11f000000116cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX28" , 0x11f0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX29" , 0x11f0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX30" , 0x11f0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_BAR1_INDEX31" , 0x11f000000117cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
- {"PCI_CFG00" , 0x11f0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 364},
- {"PCI_CFG01" , 0x11f0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 365},
- {"PCI_CFG02" , 0x11f0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 366},
- {"PCI_CFG03" , 0x11f000000180cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 367},
- {"PCI_CFG04" , 0x11f0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 368},
- {"PCI_CFG05" , 0x11f0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 369},
- {"PCI_CFG06" , 0x11f0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 370},
- {"PCI_CFG07" , 0x11f000000181cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 371},
- {"PCI_CFG08" , 0x11f0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 372},
- {"PCI_CFG09" , 0x11f0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 373},
- {"PCI_CFG10" , 0x11f0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 374},
- {"PCI_CFG11" , 0x11f000000182cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 375},
- {"PCI_CFG12" , 0x11f0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 376},
- {"PCI_CFG13" , 0x11f0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 377},
- {"PCI_CFG15" , 0x11f000000183cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 378},
- {"PCI_CFG16" , 0x11f0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 379},
- {"PCI_CFG17" , 0x11f0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 380},
- {"PCI_CFG18" , 0x11f0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 381},
- {"PCI_CFG19" , 0x11f000000184cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 382},
- {"PCI_CFG20" , 0x11f0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 383},
- {"PCI_CFG21" , 0x11f0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 384},
- {"PCI_CFG22" , 0x11f0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 385},
- {"PCI_CFG56" , 0x11f00000018e0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 386},
- {"PCI_CFG57" , 0x11f00000018e4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 387},
- {"PCI_CFG58" , 0x11f00000018e8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 388},
- {"PCI_CFG59" , 0x11f00000018ecull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 389},
- {"PCI_CFG60" , 0x11f00000018f0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 390},
- {"PCI_CFG61" , 0x11f00000018f4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 391},
- {"PCI_CFG62" , 0x11f00000018f8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 392},
- {"PCI_CFG63" , 0x11f00000018fcull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 393},
- {"PCI_CTL_STATUS_2" , 0x11f000000118cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 394},
- {"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
- {"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
- {"PCI_DBELL2" , 0x90ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
- {"PCI_DBELL3" , 0x98ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
- {"PCI_DMA_CNT0" , 0xa0ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
- {"PCI_DMA_CNT1" , 0xa8ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
- {"PCI_DMA_INT_LEV0" , 0xa4ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
- {"PCI_DMA_INT_LEV1" , 0xacull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
- {"PCI_DMA_TIME0" , 0xb0ull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
- {"PCI_DMA_TIME1" , 0xb4ull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
- {"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 399},
- {"PCI_INSTR_COUNT1" , 0x8cull, CVMX_CSR_DB_TYPE_PCI, 32, 399},
- {"PCI_INSTR_COUNT2" , 0x94ull, CVMX_CSR_DB_TYPE_PCI, 32, 399},
- {"PCI_INSTR_COUNT3" , 0x9cull, CVMX_CSR_DB_TYPE_PCI, 32, 399},
- {"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 400},
- {"PCI_INT_ENB2" , 0x11f00000011a0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 401},
- {"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 402},
- {"PCI_INT_SUM2" , 0x11f0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 403},
- {"PCI_MSI_RCV" , 0xf0ull, CVMX_CSR_DB_TYPE_PCI, 32, 404},
- {"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 405},
- {"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 405},
- {"PCI_PKT_CREDITS2" , 0x64ull, CVMX_CSR_DB_TYPE_PCI, 32, 405},
- {"PCI_PKT_CREDITS3" , 0x74ull, CVMX_CSR_DB_TYPE_PCI, 32, 405},
- {"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
- {"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
- {"PCI_PKTS_SENT2" , 0x60ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
- {"PCI_PKTS_SENT3" , 0x70ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
- {"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
- {"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
- {"PCI_PKTS_SENT_INT_LEV2" , 0x68ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
- {"PCI_PKTS_SENT_INT_LEV3" , 0x78ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
- {"PCI_PKTS_SENT_TIME0" , 0x4cull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
- {"PCI_PKTS_SENT_TIME1" , 0x5cull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
- {"PCI_PKTS_SENT_TIME2" , 0x6cull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
- {"PCI_PKTS_SENT_TIME3" , 0x7cull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
- {"PCI_READ_CMD_6" , 0x11f0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 409},
- {"PCI_READ_CMD_C" , 0x11f0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 410},
- {"PCI_READ_CMD_E" , 0x11f0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 411},
- {"PCI_READ_TIMEOUT" , 0x11f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 412},
- {"PCI_SCM_REG" , 0x11f00000011a8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 413},
- {"PCI_TSR_REG" , 0x11f00000011b0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 414},
- {"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 415},
- {"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 416},
- {"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 417},
- {"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 418},
- {"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 419},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_CRC_CTL0" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_CRC_CTL1" , 0x11800a0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_CRC_IV0" , 0x11800a0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_CRC_IV1" , 0x11800a0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG4" , 0x11800a0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG5" , 0x11800a0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG6" , 0x11800a0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG7" , 0x11800a0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG8" , 0x11800a0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG9" , 0x11800a0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG10" , 0x11800a0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG11" , 0x11800a0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG12" , 0x11800a0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG13" , 0x11800a0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG14" , 0x11800a0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG15" , 0x11800a0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG16" , 0x11800a0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG17" , 0x11800a0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG18" , 0x11800a0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG19" , 0x11800a0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG20" , 0x11800a00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG21" , 0x11800a00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG22" , 0x11800a00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG23" , 0x11800a00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG24" , 0x11800a00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG25" , 0x11800a00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG26" , 0x11800a00002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG27" , 0x11800a00002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG28" , 0x11800a00002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG29" , 0x11800a00002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG30" , 0x11800a00002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG31" , 0x11800a00002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG4" , 0x11800a0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG5" , 0x11800a0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG6" , 0x11800a0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG7" , 0x11800a0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG8" , 0x11800a0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG9" , 0x11800a0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG10" , 0x11800a0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG11" , 0x11800a0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG12" , 0x11800a0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG13" , 0x11800a0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG14" , 0x11800a0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG15" , 0x11800a0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG16" , 0x11800a0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG17" , 0x11800a0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG18" , 0x11800a0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG19" , 0x11800a0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG20" , 0x11800a00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG21" , 0x11800a00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG22" , 0x11800a00004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG23" , 0x11800a00004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG24" , 0x11800a00004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG25" , 0x11800a00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG26" , 0x11800a00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG27" , 0x11800a00004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG28" , 0x11800a00004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG29" , 0x11800a00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG30" , 0x11800a00004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG31" , 0x11800a00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT4" , 0x11800a0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT5" , 0x11800a0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT6" , 0x11800a00009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT7" , 0x11800a0000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT8" , 0x11800a0000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT9" , 0x11800a0000ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT10" , 0x11800a0000b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT11" , 0x11800a0000b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT12" , 0x11800a0000bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT13" , 0x11800a0000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT14" , 0x11800a0000c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT15" , 0x11800a0000cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT16" , 0x11800a0000d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT17" , 0x11800a0000d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT18" , 0x11800a0000da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT19" , 0x11800a0000df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT20" , 0x11800a0000e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT21" , 0x11800a0000e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT22" , 0x11800a0000ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT23" , 0x11800a0000f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT24" , 0x11800a0000f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT25" , 0x11800a0000fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT26" , 0x11800a0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT27" , 0x11800a0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT28" , 0x11800a00010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT29" , 0x11800a0001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT30" , 0x11800a0001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT31" , 0x11800a00011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT4" , 0x11800a0000948ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT5" , 0x11800a0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT6" , 0x11800a00009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT7" , 0x11800a0000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT8" , 0x11800a0000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT9" , 0x11800a0000ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT10" , 0x11800a0000b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT11" , 0x11800a0000b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT12" , 0x11800a0000bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT13" , 0x11800a0000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT14" , 0x11800a0000c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT15" , 0x11800a0000cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT16" , 0x11800a0000d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT17" , 0x11800a0000d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT18" , 0x11800a0000da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT19" , 0x11800a0000df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT20" , 0x11800a0000e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT21" , 0x11800a0000e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT22" , 0x11800a0000ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT23" , 0x11800a0000f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT24" , 0x11800a0000f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT25" , 0x11800a0000fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT26" , 0x11800a0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT27" , 0x11800a0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT28" , 0x11800a00010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT29" , 0x11800a0001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT30" , 0x11800a0001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT31" , 0x11800a00011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT4" , 0x11800a0000950ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT5" , 0x11800a00009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT6" , 0x11800a00009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT7" , 0x11800a0000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT8" , 0x11800a0000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT9" , 0x11800a0000ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT10" , 0x11800a0000b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT11" , 0x11800a0000b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT12" , 0x11800a0000bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT13" , 0x11800a0000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT14" , 0x11800a0000c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT15" , 0x11800a0000cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT16" , 0x11800a0000d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT17" , 0x11800a0000d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT18" , 0x11800a0000db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT19" , 0x11800a0000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT20" , 0x11800a0000e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT21" , 0x11800a0000ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT22" , 0x11800a0000ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT23" , 0x11800a0000f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT24" , 0x11800a0000f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT25" , 0x11800a0000fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT26" , 0x11800a0001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT27" , 0x11800a0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT28" , 0x11800a00010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT29" , 0x11800a0001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT30" , 0x11800a0001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT31" , 0x11800a00011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT4" , 0x11800a0000958ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT5" , 0x11800a00009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT6" , 0x11800a00009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT7" , 0x11800a0000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT8" , 0x11800a0000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT9" , 0x11800a0000ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT10" , 0x11800a0000b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT11" , 0x11800a0000b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT12" , 0x11800a0000bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT13" , 0x11800a0000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT14" , 0x11800a0000c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT15" , 0x11800a0000cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT16" , 0x11800a0000d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT17" , 0x11800a0000d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT18" , 0x11800a0000db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT19" , 0x11800a0000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT20" , 0x11800a0000e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT21" , 0x11800a0000ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT22" , 0x11800a0000ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT23" , 0x11800a0000f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT24" , 0x11800a0000f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT25" , 0x11800a0000fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT26" , 0x11800a0001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT27" , 0x11800a0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT28" , 0x11800a00010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT29" , 0x11800a0001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT30" , 0x11800a0001178ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT31" , 0x11800a00011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT4" , 0x11800a0000960ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT5" , 0x11800a00009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT6" , 0x11800a0000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT7" , 0x11800a0000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT8" , 0x11800a0000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT9" , 0x11800a0000af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT10" , 0x11800a0000b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT11" , 0x11800a0000b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT12" , 0x11800a0000be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT13" , 0x11800a0000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT14" , 0x11800a0000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT15" , 0x11800a0000cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT16" , 0x11800a0000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT17" , 0x11800a0000d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT18" , 0x11800a0000dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT19" , 0x11800a0000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT20" , 0x11800a0000e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT21" , 0x11800a0000eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT22" , 0x11800a0000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT23" , 0x11800a0000f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT24" , 0x11800a0000fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT25" , 0x11800a0000ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT26" , 0x11800a0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT27" , 0x11800a0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT28" , 0x11800a00010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT29" , 0x11800a0001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT30" , 0x11800a0001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT31" , 0x11800a00011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT4" , 0x11800a0000968ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT5" , 0x11800a00009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT6" , 0x11800a0000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT7" , 0x11800a0000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT8" , 0x11800a0000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT9" , 0x11800a0000af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT10" , 0x11800a0000b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT11" , 0x11800a0000b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT12" , 0x11800a0000be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT13" , 0x11800a0000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT14" , 0x11800a0000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT15" , 0x11800a0000cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT16" , 0x11800a0000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT17" , 0x11800a0000d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT18" , 0x11800a0000dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT19" , 0x11800a0000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT20" , 0x11800a0000e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT21" , 0x11800a0000eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT22" , 0x11800a0000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT23" , 0x11800a0000f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT24" , 0x11800a0000fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT25" , 0x11800a0000ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT26" , 0x11800a0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT27" , 0x11800a0001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT28" , 0x11800a00010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT29" , 0x11800a0001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT30" , 0x11800a0001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT31" , 0x11800a00011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT4" , 0x11800a0000970ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT5" , 0x11800a00009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT6" , 0x11800a0000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT7" , 0x11800a0000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT8" , 0x11800a0000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT9" , 0x11800a0000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT10" , 0x11800a0000b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT11" , 0x11800a0000ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT12" , 0x11800a0000bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT13" , 0x11800a0000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT14" , 0x11800a0000c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT15" , 0x11800a0000ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT16" , 0x11800a0000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT17" , 0x11800a0000d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT18" , 0x11800a0000dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT19" , 0x11800a0000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT20" , 0x11800a0000e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT21" , 0x11800a0000ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT22" , 0x11800a0000f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT23" , 0x11800a0000f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT24" , 0x11800a0000fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT25" , 0x11800a0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT26" , 0x11800a0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT27" , 0x11800a00010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT28" , 0x11800a00010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT29" , 0x11800a0001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT30" , 0x11800a0001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT31" , 0x11800a00011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT4" , 0x11800a0000978ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT5" , 0x11800a00009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT6" , 0x11800a0000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT7" , 0x11800a0000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT8" , 0x11800a0000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT9" , 0x11800a0000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT10" , 0x11800a0000b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT11" , 0x11800a0000ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT12" , 0x11800a0000bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT13" , 0x11800a0000c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT14" , 0x11800a0000c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT15" , 0x11800a0000ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT16" , 0x11800a0000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT17" , 0x11800a0000d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT18" , 0x11800a0000dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT19" , 0x11800a0000e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT20" , 0x11800a0000e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT21" , 0x11800a0000ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT22" , 0x11800a0000f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT23" , 0x11800a0000f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT24" , 0x11800a0000fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT25" , 0x11800a0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT26" , 0x11800a0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT27" , 0x11800a00010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT28" , 0x11800a00010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT29" , 0x11800a0001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT30" , 0x11800a0001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT31" , 0x11800a00011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT4" , 0x11800a0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT5" , 0x11800a00009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT6" , 0x11800a0000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT7" , 0x11800a0000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT8" , 0x11800a0000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT9" , 0x11800a0000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT10" , 0x11800a0000b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT11" , 0x11800a0000bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT12" , 0x11800a0000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT13" , 0x11800a0000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT14" , 0x11800a0000ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT15" , 0x11800a0000cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT16" , 0x11800a0000d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT17" , 0x11800a0000d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT18" , 0x11800a0000de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT19" , 0x11800a0000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT20" , 0x11800a0000e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT21" , 0x11800a0000ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT22" , 0x11800a0000f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT23" , 0x11800a0000f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT24" , 0x11800a0000fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT25" , 0x11800a0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT26" , 0x11800a0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT27" , 0x11800a00010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT28" , 0x11800a0001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT29" , 0x11800a0001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT30" , 0x11800a00011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT31" , 0x11800a00011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT4" , 0x11800a0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT5" , 0x11800a00009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT6" , 0x11800a0000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT7" , 0x11800a0000a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT8" , 0x11800a0000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT9" , 0x11800a0000b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT10" , 0x11800a0000b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT11" , 0x11800a0000bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT12" , 0x11800a0000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT13" , 0x11800a0000c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT14" , 0x11800a0000ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT15" , 0x11800a0000cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT16" , 0x11800a0000d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT17" , 0x11800a0000d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT18" , 0x11800a0000de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT19" , 0x11800a0000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT20" , 0x11800a0000e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT21" , 0x11800a0000ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT22" , 0x11800a0000f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT23" , 0x11800a0000f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT24" , 0x11800a0000fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT25" , 0x11800a0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT26" , 0x11800a0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT27" , 0x11800a00010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT28" , 0x11800a0001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT29" , 0x11800a0001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT30" , 0x11800a00011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT31" , 0x11800a00011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS4" , 0x11800a0001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS5" , 0x11800a0001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS6" , 0x11800a0001ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS7" , 0x11800a0001af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS8" , 0x11800a0001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS9" , 0x11800a0001b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS10" , 0x11800a0001b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS11" , 0x11800a0001b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS12" , 0x11800a0001b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS13" , 0x11800a0001bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS14" , 0x11800a0001bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS15" , 0x11800a0001bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS16" , 0x11800a0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS17" , 0x11800a0001c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS18" , 0x11800a0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS19" , 0x11800a0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS20" , 0x11800a0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS21" , 0x11800a0001cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS22" , 0x11800a0001cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS23" , 0x11800a0001cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS24" , 0x11800a0001d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS25" , 0x11800a0001d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS26" , 0x11800a0001d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS27" , 0x11800a0001d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS28" , 0x11800a0001d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS29" , 0x11800a0001db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS30" , 0x11800a0001dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS31" , 0x11800a0001df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS4" , 0x11800a0001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS5" , 0x11800a0001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS6" , 0x11800a0001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS7" , 0x11800a0001ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS8" , 0x11800a0001b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS9" , 0x11800a0001b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS10" , 0x11800a0001b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS11" , 0x11800a0001b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS12" , 0x11800a0001b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS13" , 0x11800a0001ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS14" , 0x11800a0001bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS15" , 0x11800a0001be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS16" , 0x11800a0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS17" , 0x11800a0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS18" , 0x11800a0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS19" , 0x11800a0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS20" , 0x11800a0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS21" , 0x11800a0001ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS22" , 0x11800a0001cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS23" , 0x11800a0001ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS24" , 0x11800a0001d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS25" , 0x11800a0001d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS26" , 0x11800a0001d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS27" , 0x11800a0001d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS28" , 0x11800a0001d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS29" , 0x11800a0001da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS30" , 0x11800a0001dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS31" , 0x11800a0001de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS4" , 0x11800a0001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS5" , 0x11800a0001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS6" , 0x11800a0001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS7" , 0x11800a0001ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS8" , 0x11800a0001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS9" , 0x11800a0001b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS10" , 0x11800a0001b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS11" , 0x11800a0001b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS12" , 0x11800a0001b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS13" , 0x11800a0001ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS14" , 0x11800a0001bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS15" , 0x11800a0001be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS16" , 0x11800a0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS17" , 0x11800a0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS18" , 0x11800a0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS19" , 0x11800a0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS20" , 0x11800a0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS21" , 0x11800a0001ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS22" , 0x11800a0001cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS23" , 0x11800a0001ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS24" , 0x11800a0001d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS25" , 0x11800a0001d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS26" , 0x11800a0001d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS27" , 0x11800a0001d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS28" , 0x11800a0001d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS29" , 0x11800a0001da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS30" , 0x11800a0001dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS31" , 0x11800a0001de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"PKO_REG_CRC_CTL0" , 0x1180050000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"PKO_REG_CRC_CTL1" , 0x1180050000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"PKO_REG_CRC_ENABLE" , 0x1180050000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"PKO_REG_CRC_IV0" , 0x1180050000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"PKO_REG_CRC_IV1" , 0x1180050000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 491},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK12" , 0x1670000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK13" , 0x1670000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK14" , 0x1670000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_PP_GRP_MSK15" , 0x1670000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 497},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 498},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 500},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 502},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"SPX0_BCKPRS_CNT" , 0x1180090000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"SPX1_BCKPRS_CNT" , 0x1180098000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"SPX0_BIST_STAT" , 0x11800900007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"SPX1_BIST_STAT" , 0x11800980007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"SPX0_CLK_CTL" , 0x1180090000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"SPX1_CLK_CTL" , 0x1180098000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"SPX0_CLK_STAT" , 0x1180090000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"SPX1_CLK_STAT" , 0x1180098000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"SPX0_DBG_DESKEW_CTL" , 0x1180090000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"SPX1_DBG_DESKEW_CTL" , 0x1180098000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"SPX0_DBG_DESKEW_STATE" , 0x1180090000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"SPX1_DBG_DESKEW_STATE" , 0x1180098000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"SPX0_DRV_CTL" , 0x1180090000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"SPX1_DRV_CTL" , 0x1180098000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"SPX0_ERR_CTL" , 0x1180090000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"SPX1_ERR_CTL" , 0x1180098000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"SPX0_INT_DAT" , 0x1180090000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"SPX1_INT_DAT" , 0x1180098000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"SPX0_INT_MSK" , 0x1180090000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SPX1_INT_MSK" , 0x1180098000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SPX0_INT_REG" , 0x1180090000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"SPX1_INT_REG" , 0x1180098000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"SPX0_INT_SYNC" , 0x1180090000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"SPX1_INT_SYNC" , 0x1180098000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"SPX0_TPA_ACC" , 0x1180090000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"SPX1_TPA_ACC" , 0x1180098000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"SPX0_TPA_MAX" , 0x1180090000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"SPX1_TPA_MAX" , 0x1180098000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"SPX0_TPA_SEL" , 0x1180090000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"SPX1_TPA_SEL" , 0x1180098000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"SPX0_TRN4_CTL" , 0x1180090000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"SPX1_TRN4_CTL" , 0x1180098000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"SPX0_PLL_BW_CTL" , 0x1180090000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"SPX0_PLL_SETTING" , 0x1180090000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"SRX0_COM_CTL" , 0x1180090000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"SRX1_COM_CTL" , 0x1180098000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"SRX0_IGN_RX_FULL" , 0x1180090000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"SRX1_IGN_RX_FULL" , 0x1180098000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"SRX0_SPI4_CAL000" , 0x1180090000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL001" , 0x1180090000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL002" , 0x1180090000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL003" , 0x1180090000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL004" , 0x1180090000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL005" , 0x1180090000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL006" , 0x1180090000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL007" , 0x1180090000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL008" , 0x1180090000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL009" , 0x1180090000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL010" , 0x1180090000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL011" , 0x1180090000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL012" , 0x1180090000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL013" , 0x1180090000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL014" , 0x1180090000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL015" , 0x1180090000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL016" , 0x1180090000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL017" , 0x1180090000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL018" , 0x1180090000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL019" , 0x1180090000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL020" , 0x11800900000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL021" , 0x11800900000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL022" , 0x11800900000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL023" , 0x11800900000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL024" , 0x11800900000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL025" , 0x11800900000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL026" , 0x11800900000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL027" , 0x11800900000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL028" , 0x11800900000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL029" , 0x11800900000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL030" , 0x11800900000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_CAL031" , 0x11800900000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL000" , 0x1180098000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL001" , 0x1180098000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL002" , 0x1180098000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL003" , 0x1180098000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL004" , 0x1180098000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL005" , 0x1180098000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL006" , 0x1180098000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL007" , 0x1180098000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL008" , 0x1180098000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL009" , 0x1180098000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL010" , 0x1180098000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL011" , 0x1180098000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL012" , 0x1180098000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL013" , 0x1180098000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL014" , 0x1180098000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL015" , 0x1180098000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL016" , 0x1180098000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL017" , 0x1180098000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL018" , 0x1180098000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL019" , 0x1180098000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL020" , 0x11800980000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL021" , 0x11800980000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL022" , 0x11800980000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL023" , 0x11800980000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL024" , 0x11800980000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL025" , 0x11800980000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL026" , 0x11800980000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL027" , 0x11800980000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL028" , 0x11800980000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL029" , 0x11800980000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL030" , 0x11800980000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX1_SPI4_CAL031" , 0x11800980000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SRX0_SPI4_STAT" , 0x1180090000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"SRX1_SPI4_STAT" , 0x1180098000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"SRX0_SW_TICK_CTL" , 0x1180090000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"SRX1_SW_TICK_CTL" , 0x1180098000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"SRX0_SW_TICK_DAT" , 0x1180090000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"SRX1_SW_TICK_DAT" , 0x1180098000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"STX0_ARB_CTL" , 0x1180090000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"STX1_ARB_CTL" , 0x1180098000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"STX0_BCKPRS_CNT" , 0x1180090000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"STX1_BCKPRS_CNT" , 0x1180098000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"STX0_COM_CTL" , 0x1180090000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"STX1_COM_CTL" , 0x1180098000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"STX0_DIP_CNT" , 0x1180090000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"STX1_DIP_CNT" , 0x1180098000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"STX0_IGN_CAL" , 0x1180090000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"STX1_IGN_CAL" , 0x1180098000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"STX0_INT_MSK" , 0x11800900006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"STX1_INT_MSK" , 0x11800980006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"STX0_INT_REG" , 0x1180090000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"STX1_INT_REG" , 0x1180098000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"STX0_INT_SYNC" , 0x11800900006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"STX1_INT_SYNC" , 0x11800980006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"STX0_MIN_BST" , 0x1180090000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"STX1_MIN_BST" , 0x1180098000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"STX0_SPI4_CAL000" , 0x1180090000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL001" , 0x1180090000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL002" , 0x1180090000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL003" , 0x1180090000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL004" , 0x1180090000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL005" , 0x1180090000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL006" , 0x1180090000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL007" , 0x1180090000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL008" , 0x1180090000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL009" , 0x1180090000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL010" , 0x1180090000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL011" , 0x1180090000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL012" , 0x1180090000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL013" , 0x1180090000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL014" , 0x1180090000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL015" , 0x1180090000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL016" , 0x1180090000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL017" , 0x1180090000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL018" , 0x1180090000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL019" , 0x1180090000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL020" , 0x11800900004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL021" , 0x11800900004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL022" , 0x11800900004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL023" , 0x11800900004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL024" , 0x11800900004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL025" , 0x11800900004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL026" , 0x11800900004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL027" , 0x11800900004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL028" , 0x11800900004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL029" , 0x11800900004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL030" , 0x11800900004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_CAL031" , 0x11800900004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL000" , 0x1180098000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL001" , 0x1180098000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL002" , 0x1180098000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL003" , 0x1180098000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL004" , 0x1180098000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL005" , 0x1180098000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL006" , 0x1180098000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL007" , 0x1180098000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL008" , 0x1180098000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL009" , 0x1180098000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL010" , 0x1180098000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL011" , 0x1180098000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL012" , 0x1180098000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL013" , 0x1180098000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL014" , 0x1180098000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL015" , 0x1180098000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL016" , 0x1180098000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL017" , 0x1180098000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL018" , 0x1180098000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL019" , 0x1180098000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL020" , 0x11800980004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL021" , 0x11800980004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL022" , 0x11800980004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL023" , 0x11800980004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL024" , 0x11800980004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL025" , 0x11800980004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL026" , 0x11800980004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL027" , 0x11800980004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL028" , 0x11800980004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL029" , 0x11800980004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL030" , 0x11800980004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX1_SPI4_CAL031" , 0x11800980004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"STX0_SPI4_DAT" , 0x1180090000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"STX1_SPI4_DAT" , 0x1180098000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"STX0_SPI4_STAT" , 0x1180090000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"STX1_SPI4_STAT" , 0x1180098000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"STX0_STAT_BYTES_HI" , 0x1180090000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"STX1_STAT_BYTES_HI" , 0x1180098000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"STX0_STAT_BYTES_LO" , 0x1180090000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"STX1_STAT_BYTES_LO" , 0x1180098000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"STX0_STAT_CTL" , 0x1180090000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"STX1_STAT_CTL" , 0x1180098000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"STX0_STAT_PKT_XMT" , 0x1180090000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"STX1_STAT_PKT_XMT" , 0x1180098000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 577},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 578},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 581},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 582},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 583},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 584},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 585},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 586},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 587},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 588},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"OVRFLW" , 0, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"TXPOP" , 4, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"TXPSH" , 8, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_12_63" , 12, 52, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 0, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 4, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 8, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 1, "RAZ", 1, 1, 0, 0},
- {"INT_LOOP" , 0, 4, 2, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_LOOP" , 4, 4, 2, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 2, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 1, 3, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 3, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 4, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 5, "RO", 0, 1, 0ull, 0},
- {"PCTL" , 4, 4, 5, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 5, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 6, "R/W", 0, 1, 0ull, 0},
- {"PCTL" , 4, 4, 6, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 6, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 1, 7, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 7, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 8, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 9, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 10, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 10, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 11, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 12, "RO", 1, 1, 0, 0},
- {"RESERVED_5_63" , 5, 59, 12, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 4, 14, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 14, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 15, "RO", 1, 1, 0, 0},
- {"STATUS" , 1, 1, 15, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 15, "RAZ", 1, 1, 0, 0},
- {"MSK" , 0, 64, 16, "R/W", 0, 1, 0ull, 0},
- {"POWEROK" , 0, 1, 17, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_1_63" , 1, 63, 17, "RAZ", 1, 1, 0, 0},
- {"SIG" , 0, 32, 18, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 18, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 19, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 19, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 20, "R/W", 0, 0, 8ull, 8ull},
- {"PCTL" , 4, 4, 20, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_8_63" , 8, 56, 20, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 4, 21, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 4, 22, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 22, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 23, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 4, 4, 23, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_8_63" , 8, 56, 23, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 24, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_1_63" , 1, 63, 24, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 4, 25, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 25, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 16, 26, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 26, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 16, 27, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 27, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 28, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 28, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 29, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 29, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 29, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 29, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 29, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 29, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 29, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 29, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 29, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 29, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 29, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 30, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 30, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 31, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 31, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 31, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 31, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 31, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 31, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 31, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 32, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 32, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 33, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 33, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 34, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 34, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 16, 35, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 35, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 36, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 36, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 16, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 37, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 38, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 39, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 15, 39, "R/W", 0, 0, 32767ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 39, "RAZ", 1, 1, 0, 0},
- {"SOFT_BIST" , 0, 1, 40, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 40, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 41, "R/W", 0, 0, 1ull, 0ull},
- {"NPI" , 1, 1, 41, "R/W", 0, 0, 0ull, 0ull},
- {"HOST64" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 41, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 42, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 42, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 43, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 43, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 43, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 44, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 44, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 44, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 44, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 44, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 44, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 45, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 45, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 45, "RO", 1, 1, 0, 0},
- {"CCLK_DIV2" , 23, 1, 45, "RO", 1, 1, 0, 0},
- {"DCLK_MUL2" , 24, 1, 45, "RO", 1, 1, 0, 0},
- {"D_MUL" , 25, 4, 45, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 45, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 16, 46, "RO", 0, 0, 0ull, 0ull},
- {"RDF" , 16, 16, 46, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 46, "RAZ", 0, 0, 0ull, 0ull},
- {"P1_BRF" , 0, 8, 47, "RO", 0, 0, 0ull, 0ull},
- {"P0_BRF" , 8, 8, 47, "RO", 0, 0, 0ull, 0ull},
- {"P1_BWB" , 16, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"P0_BWB" , 17, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"CRF" , 18, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"DRF" , 19, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"GFU" , 20, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"IFU" , 21, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 22, 1, 47, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 47, "RAZ", 0, 0, 0ull, 0ull},
- {"SARB" , 0, 1, 48, "R/W", 0, 0, 1ull, 1ull},
- {"GXOR_ENA" , 1, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"NXOR_ENA" , 2, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"NRPL_ENA" , 3, 1, 48, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 48, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 20, 49, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 49, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 9, 50, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 50, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 50, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_20_63" , 20, 44, 50, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 51, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 31, 51, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 51, "RAZ", 1, 1, 0, 0},
- {"CP2ECCENA" , 0, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"CP2SBE" , 1, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2DBE" , 2, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2SBINA" , 3, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"CP2DBINA" , 4, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"CP2SYN" , 5, 8, 52, "RO", 0, 0, 0ull, 0ull},
- {"DTEECCENA" , 13, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"DTESBE" , 14, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTEDBE" , 15, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTESBINA" , 16, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"DTEDBINA" , 17, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"DTESYN" , 18, 7, 52, "RO", 0, 0, 0ull, 0ull},
- {"DTEPARENA" , 25, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"DTEPERR" , 26, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTEPINA" , 27, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"CP2PARENA" , 28, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"CP2PERR" , 29, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2PINA" , 30, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"DBLOVF" , 31, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBLINA" , 32, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 52, "RAZ", 1, 1, 0, 0},
- {"ENA_P1" , 0, 1, 53, "R/W", 0, 0, 1ull, 1ull},
- {"ENA_P0" , 1, 1, 53, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 53, "RAZ", 1, 1, 0, 0},
- {"MTYPE" , 3, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_LAT" , 4, 2, 53, "R/W", 0, 0, 0ull, 0ull},
- {"RW_DLY" , 6, 4, 53, "R/W", 0, 0, 1ull, 1ull},
- {"WR_DLY" , 10, 4, 53, "R/W", 0, 0, 2ull, 2ull},
- {"FPRCH" , 14, 2, 53, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 16, 2, 53, "R/W", 0, 0, 0ull, 0ull},
- {"BLEN" , 18, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"PBUNK" , 19, 3, 53, "R/W", 0, 0, 2ull, 2ull},
- {"R2R_PBUNK" , 22, 1, 53, "R/W", 0, 0, 1ull, 1ull},
- {"INIT_P1" , 23, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"INIT_P0" , 24, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"BUNK_INIT" , 25, 2, 53, "R/W", 0, 0, 3ull, 3ull},
- {"LPP_ENA" , 27, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 53, "RAZ", 1, 1, 0, 0},
- {"REF_INT" , 0, 4, 54, "R/W", 0, 0, 3ull, 3ull},
- {"TSKW" , 4, 2, 54, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 54, "RAZ", 0, 0, 0ull, 0ull},
- {"TRL" , 8, 4, 54, "R/W", 0, 0, 6ull, 6ull},
- {"TWL" , 12, 4, 54, "R/W", 0, 0, 7ull, 7ull},
- {"TRC" , 16, 4, 54, "R/W", 0, 0, 6ull, 6ull},
- {"TMRSC" , 20, 3, 54, "R/W", 0, 0, 6ull, 6ull},
- {"MRS_ENA" , 23, 1, 54, "R/W", 0, 0, 0ull, 0ull},
- {"AREF_ENA" , 24, 1, 54, "R/W", 0, 0, 0ull, 0ull},
- {"REF_INTLO" , 25, 9, 54, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 54, "RAZ", 1, 1, 0, 0},
- {"FCRAM2P" , 0, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"MAXBNK" , 1, 1, 55, "R/W", 0, 0, 1ull, 1ull},
- {"UA_START" , 2, 2, 55, "R/W", 0, 0, 1ull, 1ull},
- {"REFSHORT" , 4, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"TRFC" , 5, 5, 55, "R/W", 0, 0, 9ull, 9ull},
- {"SILRST" , 10, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"DTECLKDIS" , 11, 1, 55, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 55, "RAZ", 1, 1, 0, 0},
- {"MADDR" , 0, 24, 56, "RO", 0, 0, 0ull, 0ull},
- {"BNUM" , 24, 3, 56, "RO", 0, 0, 0ull, 0ull},
- {"PNUM" , 27, 1, 56, "RO", 0, 0, 0ull, 0ull},
- {"FSRC" , 28, 2, 56, "RO", 0, 0, 0ull, 0ull},
- {"FDST" , 30, 9, 56, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 56, "RAZ", 1, 1, 0, 0},
- {"MRS" , 0, 15, 57, "R/W", 0, 0, 66ull, 66ull},
- {"RESERVED_15_15" , 15, 1, 57, "RAZ", 1, 1, 0, 0},
- {"EMRS" , 16, 15, 57, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_31_31" , 31, 1, 57, "RAZ", 1, 1, 0, 0},
- {"EMRS2" , 32, 15, 57, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 57, "RAZ", 1, 1, 0, 0},
- {"MRSDAT" , 0, 23, 58, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_23_63" , 23, 41, 58, "RAZ", 1, 1, 0, 0},
- {"IMODE" , 0, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 1, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 2, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"DTMODE" , 3, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"DCMODE" , 4, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"SBDLCK" , 5, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"SBDNUM" , 6, 4, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 59, "RAZ", 1, 1, 0, 0},
- {"SBD0" , 0, 64, 60, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 61, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 62, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 63, "RO", 1, 1, 0, 0},
- {"FDR" , 0, 1, 64, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 64, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 64, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 64, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 64, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 64, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 65, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 65, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 65, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 65, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 65, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 65, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 65, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 66, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 66, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 66, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 67, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 67, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 68, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 68, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 68, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 69, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 69, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 70, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 70, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 71, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 72, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 72, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 73, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 73, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 74, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 74, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 74, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 75, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 75, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 75, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 76, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 76, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 77, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 77, "RAZ", 1, 1, 0, 0},
- {"OUT_COL" , 0, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB_OVR" , 1, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 16, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_21" , 18, 4, 78, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 78, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 10, 79, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 79, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 80, "RO", 1, 1, 0, 0},
- {"EN" , 1, 1, 80, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 80, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 81, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 81, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 82, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 82, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 82, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 82, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_63" , 4, 60, 82, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 83, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 84, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 85, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 86, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 87, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 88, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 89, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 89, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 90, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 90, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 90, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 90, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 91, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 91, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 92, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_FREE" , 6, 1, 93, "R/W", 0, 0, 0ull, 0ull},
- {"VLAN_LEN" , 7, 1, 93, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 93, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 93, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 94, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 94, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 95, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 95, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 96, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 96, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 97, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 98, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 99, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 99, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 100, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 100, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 100, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 100, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 101, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 102, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 102, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 103, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 103, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 104, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 104, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 105, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 105, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 106, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 106, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 107, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 108, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 108, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 109, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 109, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 110, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 110, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 111, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 111, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 112, "R/W", 1, 1, 0, 0},
- {"RESERVED_6_63" , 6, 58, 112, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 113, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 113, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 114, "R/W", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 114, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 16, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 115, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 4, 116, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 116, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 16, 117, "RO", 0, 0, 0ull, 0ull},
- {"DROP" , 16, 16, 117, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 117, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 118, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 118, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 119, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 119, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 120, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 120, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 120, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 121, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 121, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 121, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 121, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 121, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 122, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 122, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 123, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 123, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 124, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 124, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 124, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 125, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 125, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 126, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 126, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 127, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 127, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 128, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 128, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 129, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 129, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 130, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 130, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 131, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 131, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 132, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 132, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 133, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 133, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 134, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 134, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 135, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 135, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 136, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 136, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 137, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 137, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 138, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 138, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 139, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 140, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 141, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 141, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 142, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 143, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 143, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 144, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 144, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 145, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 145, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 146, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 146, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 147, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 147, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 147, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"NCB_NXA" , 1, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 148, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 148, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB_NXA" , 1, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 149, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 149, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 150, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 150, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 151, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 151, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 152, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 152, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 152, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 152, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 153, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 153, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 154, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 154, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 155, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_5_63" , 5, 59, 155, "RAZ", 1, 1, 0, 0},
- {"CONT_PKT" , 0, 1, 156, "R/W", 0, 1, 0ull, 0},
- {"TPA_CLR" , 1, 1, 156, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 156, "RAZ", 0, 0, 0ull, 0ull},
- {"DRAIN" , 0, 16, 157, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 157, "RAZ", 1, 1, 0, 0},
- {"MAX1" , 0, 8, 158, "R/W", 0, 1, 8ull, 0},
- {"MAX2" , 8, 8, 158, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_16_63" , 16, 48, 158, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 6, 159, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_6_63" , 6, 58, 159, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 160, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 160, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 160, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 160, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 160, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 161, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 161, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 162, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 163, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 163, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 164, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 164, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 165, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 166, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 166, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 166, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 166, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 166, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 166, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 167, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 168, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 168, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 168, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 169, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 169, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 170, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 170, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 170, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 170, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 170, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 171, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 171, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 171, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 171, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 171, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 172, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 173, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 174, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 174, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 174, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 174, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 174, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 175, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 176, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 176, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 177, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 177, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 177, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 178, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 178, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 178, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 179, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 179, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 179, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 179, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 179, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 180, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 180, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 180, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 180, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 180, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 181, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 182, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 183, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 183, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 184, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 185, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 185, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 186, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 186, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 187, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 187, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 188, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 189, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 190, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 191, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 191, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 192, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 193, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 193, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 193, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 194, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 195, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 196, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 196, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 197, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 197, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 198, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 198, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 199, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 199, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 200, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 200, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 3, 201, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 201, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 201, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 201, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 201, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 201, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 202, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 202, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 202, "RO", 0, 0, 36ull, 36ull},
- {"RESERVED_44_63" , 44, 20, 202, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 203, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 203, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 203, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 203, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 203, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 204, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 204, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 204, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 204, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 204, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 204, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_61_63" , 61, 3, 204, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 205, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 205, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 206, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 207, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 207, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 207, "R/W", 0, 0, 0ull, 0ull},
- {"PRB_CON" , 0, 32, 208, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 208, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 208, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 208, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 209, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 209, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 209, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 210, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 210, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 211, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 211, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 212, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 212, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 213, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 213, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 213, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 214, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 214, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 214, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 215, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 215, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 215, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 215, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 215, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 216, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 216, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 216, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 216, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 216, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 217, "RO", 0, 0, 0ull, 0ull},
- {"STIN_MSK" , 4, 1, 217, "RO", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 217, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 13, 217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 217, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 9, 218, "RO", 0, 0, 0ull, 0ull},
- {"VAB_VWCF" , 9, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"LRF" , 10, 2, 218, "RO", 0, 0, 0ull, 0ull},
- {"VWDF" , 12, 4, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 218, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"PICBST" , 2, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"RHDF" , 4, 4, 219, "RO", 0, 0, 0ull, 0ull},
- {"RMDF" , 8, 4, 219, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 219, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 219, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 220, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 220, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 220, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 220, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 220, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 220, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 220, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 220, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 220, "RAZ", 1, 1, 0, 0},
- {"L2T" , 0, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 3, 221, "R/W", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 4, 221, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 4, 221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 221, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 222, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 222, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 222, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 223, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 223, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 224, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 224, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 225, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 225, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 225, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 4, 225, "RO", 0, 0, 0ull, 0ull},
- {"SET" , 18, 3, 225, "RO", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 225, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 225, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 4, 225, "RO", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 225, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 225, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 225, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 225, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 225, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 226, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 226, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 10, 227, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 10, 17, 227, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 227, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 4, 228, "R/W", 0, 0, 15ull, 15ull},
- {"STPARTDIS" , 4, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 228, "RAZ", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 229, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 230, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 8, 231, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK1" , 8, 8, 231, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK2" , 16, 8, 231, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK3" , 24, 8, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 231, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK4" , 0, 8, 232, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK5" , 8, 8, 232, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK6" , 16, 8, 232, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK7" , 24, 8, 232, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 232, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK8" , 0, 8, 233, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK9" , 8, 8, 233, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK10" , 16, 8, 233, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK11" , 24, 8, 233, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 233, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK12" , 0, 8, 234, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK13" , 8, 8, 234, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK14" , 16, 8, 234, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK15" , 24, 8, 234, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 234, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 8, 235, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 235, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 236, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 236, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 236, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 237, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 237, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 238, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 239, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 240, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 240, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 240, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 240, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 240, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 240, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 11, 241, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 3, 241, "RO", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 241, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 241, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 242, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 242, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 242, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 243, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 243, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 243, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 244, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 245, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 245, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 246, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 246, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 247, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_512K" , 34, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_256K" , 35, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 247, "RO", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 248, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 248, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 248, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 248, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 248, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 248, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 10, 248, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 3, 248, "RO", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 248, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 248, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 248, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 248, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_28_63" , 28, 36, 248, "RAZ", 0, 0, 0ull, 0ull},
- {"RATE" , 0, 8, 249, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_63" , 8, 56, 249, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 7, 250, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_7_63" , 7, 57, 250, "RAZ", 1, 1, 0, 0},
- {"RATE" , 0, 16, 251, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 251, "RAZ", 1, 1, 0, 0},
- {"DBG_EN" , 0, 1, 252, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 252, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 253, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 253, "RAZ", 1, 1, 0, 0},
- {"POLARITY" , 0, 1, 254, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 254, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 8, 255, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 255, "RAZ", 1, 1, 0, 0},
- {"FORMAT" , 0, 4, 256, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 256, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 257, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 257, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 258, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 258, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 32, 259, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 259, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 32, 260, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 260, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 32, 261, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 261, "RAZ", 1, 1, 0, 0},
- {"PCTL_DAT" , 0, 4, 262, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CMD" , 4, 4, 262, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CLK" , 8, 4, 262, "R/W", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 262, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 262, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CMD" , 20, 4, 262, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CLK" , 24, 4, 262, "R/W", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 262, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 262, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 263, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 263, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 263, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 263, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 263, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 263, "R/W", 0, 0, 0ull, 1ull},
- {"MODE128B" , 10, 1, 263, "R/W", 0, 0, 1ull, 1ull},
- {"SET_ZERO" , 11, 1, 263, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MRF" , 12, 1, 263, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 263, "R/W", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 263, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 263, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_17" , 16, 2, 263, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 263, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 263, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 263, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 263, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 263, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 263, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 264, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 264, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 265, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 265, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 266, "R/W", 0, 0, 1ull, 1ull},
- {"RDQS" , 1, 1, 266, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 266, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 266, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 266, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 266, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 266, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 266, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 266, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 266, "R/W", 0, 0, 2ull, 2ull},
- {"SILO_HC" , 21, 1, 266, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 266, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 266, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 266, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 266, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 266, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 266, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 266, "RAZ", 0, 0, 0ull, 0ull},
- {"CLK" , 0, 4, 267, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 267, "RAZ", 0, 0, 0ull, 0ull},
- {"CMD" , 5, 4, 267, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 267, "RAZ", 0, 0, 0ull, 0ull},
- {"DQ" , 10, 4, 267, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 267, "RAZ", 0, 0, 0ull, 0ull},
- {"MRDSYN0" , 0, 8, 268, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 268, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 268, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 268, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 268, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 269, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 269, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 269, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 269, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 269, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 270, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 271, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 271, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 272, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 272, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 272, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 272, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 272, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 272, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 272, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 272, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 272, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 272, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 272, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 273, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 273, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 273, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 273, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 273, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 273, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 273, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 273, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_31_63" , 31, 33, 273, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 274, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 274, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 275, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
- {"BWCTL" , 0, 4, 276, "R/W", 0, 0, 0ull, 0ull},
- {"BWUPD" , 4, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 276, "RAZ", 1, 1, 0, 0},
- {"RODT_LO0" , 0, 4, 277, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO1" , 4, 4, 277, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO2" , 8, 4, 277, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO3" , 12, 4, 277, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI0" , 16, 4, 277, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI1" , 20, 4, 277, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI2" , 24, 4, 277, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI3" , 28, 4, 277, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 277, "RAZ", 1, 1, 0, 0},
- {"WODT_LO0" , 0, 4, 278, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO1" , 4, 4, 278, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO2" , 8, 4, 278, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO3" , 12, 4, 278, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI0" , 16, 4, 278, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI1" , 20, 4, 278, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI2" , 24, 4, 278, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI3" , 28, 4, 278, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 278, "RAZ", 1, 1, 0, 0},
- {"NCBI" , 0, 1, 279, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 279, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 2, 1, 279, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 279, "RAZ", 1, 1, 0, 0},
- {"ADR_ERR" , 0, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 280, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 281, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 281, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 282, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 282, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 283, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 283, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 283, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 284, "R/W", 1, 1, 0, 0},
- {"BASE" , 0, 16, 285, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 285, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_29" , 28, 2, 285, "RAZ", 1, 1, 0, 0},
- {"ORBIT" , 30, 1, 285, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 285, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 285, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 286, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 286, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 286, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 286, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 286, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 286, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 286, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 286, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 286, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_54_59" , 54, 6, 286, "RAZ", 1, 1, 0, 0},
- {"PAGES" , 60, 2, 286, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 286, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 286, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 287, "R/W", 0, 0, 26ull, 26ull},
- {"RESERVED_6_7" , 6, 2, 287, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 287, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 287, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 288, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 288, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 289, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 289, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 16, 290, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 290, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 290, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 290, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 290, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 290, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 290, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 290, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 291, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 291, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 291, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 291, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 291, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 291, "RO", 1, 1, 0, 0},
- {"ZIP_CRIP" , 29, 2, 291, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 291, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 292, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 292, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 7, 293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 293, "RAZ", 1, 1, 0, 0},
- {"EFUSE" , 8, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 293, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 293, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 293, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 293, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 294, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 14, 14, 294, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 28, 14, 294, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 294, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 295, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 295, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 10, 296, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 296, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 297, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 297, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 297, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 297, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 297, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 297, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 297, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 297, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 297, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 297, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 297, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 297, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 297, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 298, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 298, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 298, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 298, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 298, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 298, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 298, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 298, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 298, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 299, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 299, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 299, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 300, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 300, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 300, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 301, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 301, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 302, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 302, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 303, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 303, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 304, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 304, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 304, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 304, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 304, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 304, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 304, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 305, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 305, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 306, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 306, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 306, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 306, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 306, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 306, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 306, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 307, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 307, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 307, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 307, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 308, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 308, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 308, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 308, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 308, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 308, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 308, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 308, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 309, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 309, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 309, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 309, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 309, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 309, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 309, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 309, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 309, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 310, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 311, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 311, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 311, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 311, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 311, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 311, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 311, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 311, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 311, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 312, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 312, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 313, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 313, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 314, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 314, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 314, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 314, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 315, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 315, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 316, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 316, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 317, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 318, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 318, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 318, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 318, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 319, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 319, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 320, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 321, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 321, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 322, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 322, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 323, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 323, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 324, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 324, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 325, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 325, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 325, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 325, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 325, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 325, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 326, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 326, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 327, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 327, "R/W", 0, 1, 0ull, 0},
- {"DPI_BS" , 0, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PDF_BS" , 1, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"DOB_BS" , 2, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"NUS_BS" , 3, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"POS_BS" , 4, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"POF3_BS" , 5, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"POF2_BS" , 6, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"POF1_BS" , 7, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"POF0_BS" , 8, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PIG_BS" , 9, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PGF_BS" , 10, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"RDNL_BS" , 11, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PCAD_BS" , 12, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PCAC_BS" , 13, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"RDN_BS" , 14, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PCN_BS" , 15, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PCNC_BS" , 16, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"RDP_BS" , 17, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"DIF_BS" , 18, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"CSR_BS" , 19, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 328, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 329, "R/W", 0, 1, 1024ull, 0},
- {"ISIZE" , 16, 7, 329, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 329, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 330, "R/W", 0, 0, 0ull, 50ull},
- {"RESERVED_10_31" , 10, 22, 330, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_WORD" , 32, 5, 330, "R/W", 0, 0, 2ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 330, "RAZ", 0, 0, 0ull, 0ull},
- {"WAIT_COM" , 40, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_WDIS" , 41, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"INS0_64B" , 42, 1, 330, "R/W", 0, 1, 0ull, 0},
- {"INS1_64B" , 43, 1, 330, "R/W", 0, 1, 0ull, 0},
- {"INS2_64B" , 44, 1, 330, "R/W", 0, 1, 0ull, 0},
- {"INS3_64B" , 45, 1, 330, "R/W", 0, 1, 0ull, 0},
- {"INS0_ENB" , 46, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"INS1_ENB" , 47, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"INS2_ENB" , 48, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"INS3_ENB" , 49, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"OUT0_ENB" , 50, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"OUT1_ENB" , 51, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"OUT2_ENB" , 52, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"OUT3_ENB" , 53, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"DIS_PNIW" , 54, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"CHIP_REV" , 55, 8, 330, "RO", 1, 1, 0, 0},
- {"RESERVED_63_63" , 63, 1, 330, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 331, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 331, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 0, 14, 332, "R/W", 0, 1, 0ull, 0},
- {"LP_ENB" , 14, 1, 332, "R/W", 0, 0, 0ull, 1ull},
- {"HP_ENB" , 15, 1, 332, "R/W", 0, 0, 0ull, 1ull},
- {"O_MODE" , 16, 1, 332, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 17, 2, 332, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 19, 1, 332, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 20, 1, 332, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 21, 1, 332, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 22, 3, 332, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 25, 9, 332, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 34, 1, 332, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 35, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 332, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 333, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 333, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 333, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 334, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 334, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 334, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 335, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 335, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 335, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 336, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 336, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 336, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 337, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 337, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 338, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 338, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 1, 339, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 339, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 339, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 339, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 339, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 339, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 339, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 339, "R/W", 0, 1, 0ull, 0},
- {"PKT_RR" , 22, 1, 339, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 339, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_RSL" , 2, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PO0_2SML" , 3, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PO1_2SML" , 4, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PO2_2SML" , 5, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PO3_2SML" , 6, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I0_RTOUT" , 7, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I1_RTOUT" , 8, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I2_RTOUT" , 9, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I3_RTOUT" , 10, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I0_OVERF" , 11, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I1_OVERF" , 12, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I2_OVERF" , 13, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I3_OVERF" , 14, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P0_RTOUT" , 15, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P1_RTOUT" , 16, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P2_RTOUT" , 17, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P3_RTOUT" , 18, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PERR" , 19, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PERR" , 20, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PERR" , 21, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PERR" , 22, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"G0_RTOUT" , 23, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"G1_RTOUT" , 24, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"G2_RTOUT" , 25, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"G3_RTOUT" , 26, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PPERR" , 27, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PPERR" , 28, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PPERR" , 29, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PPERR" , 30, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PTOUT" , 31, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PTOUT" , 32, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PTOUT" , 33, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PTOUT" , 34, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I0_PPERR" , 35, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I1_PPERR" , 36, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I2_PPERR" , 37, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"I3_PPERR" , 38, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"WIN_RTO" , 39, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"P_DPERR" , 40, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 41, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_S_E" , 42, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_A_F" , 43, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_S_E" , 44, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_A_F" , 45, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_S_E" , 46, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_A_F" , 47, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_S_E" , 48, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_A_F" , 49, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"COM_S_E" , 50, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"COM_A_F" , 51, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_S_E" , 52, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_A_F" , 53, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"RWX_S_E" , 54, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"RDX_S_E" , 55, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_E" , 56, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_F" , 57, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_E" , 58, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_F" , 59, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_S_E" , 60, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_A_F" , 61, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_62_63" , 62, 2, 340, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_RSL" , 2, 1, 341, "RO", 0, 0, 0ull, 0ull},
- {"PO0_2SML" , 3, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO1_2SML" , 4, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO2_2SML" , 5, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO3_2SML" , 6, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_RTOUT" , 7, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_RTOUT" , 8, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_RTOUT" , 9, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_RTOUT" , 10, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_OVERF" , 11, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_OVERF" , 12, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_OVERF" , 13, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_OVERF" , 14, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_RTOUT" , 15, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_RTOUT" , 16, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_RTOUT" , 17, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_RTOUT" , 18, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PERR" , 19, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PERR" , 20, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PERR" , 21, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PERR" , 22, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"G0_RTOUT" , 23, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"G1_RTOUT" , 24, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"G2_RTOUT" , 25, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"G3_RTOUT" , 26, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PPERR" , 27, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PPERR" , 28, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PPERR" , 29, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PPERR" , 30, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PTOUT" , 31, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PTOUT" , 32, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PTOUT" , 33, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PTOUT" , 34, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_PPERR" , 35, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_PPERR" , 36, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_PPERR" , 37, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_PPERR" , 38, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_RTO" , 39, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DPERR" , 40, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 41, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_S_E" , 42, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_A_F" , 43, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_S_E" , 44, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_A_F" , 45, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_S_E" , 46, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_A_F" , 47, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_S_E" , 48, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_A_F" , 49, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_S_E" , 50, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_A_F" , 51, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_S_E" , 52, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_A_F" , 53, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"RWX_S_E" , 54, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDX_S_E" , 55, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_E" , 56, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_F" , 57, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_E" , 58, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_F" , 59, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_S_E" , 60, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_A_F" , 61, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 341, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 342, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 342, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 343, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 343, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 28, 344, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 28, 1, 344, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 29, 1, 344, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 30, 1, 344, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 31, 1, 344, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 32, 2, 344, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 34, 2, 344, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 36, 1, 344, "R/W", 0, 1, 0ull, 0},
- {"SHORTL" , 37, 1, 344, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 344, "RAZ", 1, 1, 0, 0},
- {"INT_VEC" , 0, 64, 345, "R/W1C", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 32, 346, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 346, "RAZ", 1, 1, 0, 0},
- {"ROR_SL0" , 0, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL0" , 1, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL0" , 2, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL1" , 4, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL1" , 5, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL1" , 6, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL2" , 8, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL2" , 9, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL2" , 10, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL3" , 12, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL3" , 13, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL3" , 14, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"IPTR_O0" , 16, 1, 347, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O1" , 17, 1, 347, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O2" , 18, 1, 347, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O3" , 19, 1, 347, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_23" , 20, 4, 347, "RAZ", 0, 0, 0ull, 0ull},
- {"O0_CSRM" , 24, 1, 347, "R/W", 0, 0, 0ull, 1ull},
- {"O1_CSRM" , 25, 1, 347, "R/W", 0, 0, 0ull, 1ull},
- {"O2_CSRM" , 26, 1, 347, "R/W", 0, 0, 0ull, 1ull},
- {"O3_CSRM" , 27, 1, 347, "R/W", 0, 0, 0ull, 1ull},
- {"O0_RO" , 28, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"O0_NS" , 29, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"O0_ES" , 30, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"O1_RO" , 32, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"O1_NS" , 33, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"O1_ES" , 34, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"O2_RO" , 36, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"O2_NS" , 37, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"O2_ES" , 38, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"O3_RO" , 40, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"O3_NS" , 41, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"O3_ES" , 42, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"P0_BMODE" , 44, 1, 347, "R/W", 0, 0, 0ull, 0ull},
- {"P1_BMODE" , 45, 1, 347, "R/W", 0, 0, 0ull, 0ull},
- {"P2_BMODE" , 46, 1, 347, "R/W", 0, 0, 0ull, 0ull},
- {"P3_BMODE" , 47, 1, 347, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 48, 1, 347, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 347, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 348, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 2, 348, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_63_63" , 63, 1, 348, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 349, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 3, 349, "RO", 0, 0, 0ull, 0ull},
- {"AVAIL" , 0, 32, 350, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 6, 350, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 350, "RAZ", 1, 1, 0, 0},
- {"AVAIL" , 0, 32, 351, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 5, 351, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 351, "RAZ", 1, 1, 0, 0},
- {"RD_BRST" , 0, 7, 352, "R/W", 0, 0, 17ull, 64ull},
- {"WR_BRST" , 7, 7, 352, "R/W", 0, 0, 16ull, 64ull},
- {"RESERVED_14_63" , 14, 50, 352, "RAZ", 1, 1, 0, 0},
- {"PARK_DEV" , 0, 3, 353, "R/W", 0, 1, 0ull, 0},
- {"PARK_MOD" , 3, 1, 353, "R/W", 0, 1, 0ull, 0},
- {"EN" , 4, 1, 353, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 353, "RAZ", 1, 1, 0, 0},
- {"CMD_SIZE" , 0, 11, 354, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_11_63" , 11, 53, 354, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 355, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 355, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 355, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 355, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 355, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 355, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 355, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 355, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 355, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 356, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 356, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 356, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 356, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 356, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 356, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 356, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 356, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 356, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 357, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 357, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 357, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 357, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 357, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 357, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 357, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 358, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 358, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 358, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 358, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 358, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 358, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 358, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 358, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 358, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 358, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 358, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 358, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 358, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 4, 359, "R/W", 0, 0, 15ull, 15ull},
- {"BP_ON" , 4, 4, 359, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 359, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"NPI" , 3, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_8" , 8, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_13" , 13, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_14" , 14, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_15" , 15, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"LMC" , 17, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_21" , 21, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"ASX0" , 22, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"ASX1" , 23, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_24" , 24, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_25" , 25, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_26" , 26, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_27" , 27, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_28" , 28, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_29" , 29, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RINT_31" , 31, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 360, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 32, 361, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 361, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 362, "R/W", 0, 0, 0ull, 131072ull},
- {"RESERVED_32_63" , 32, 32, 362, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 363, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 363, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 363, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 363, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 363, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 364, "RO", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 364, "RO", 0, 0, 5ull, 5ull},
- {"ISAE" , 0, 1, 365, "RO", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 365, "R/W", 0, 0, 0ull, 1ull},
- {"ME" , 2, 1, 365, "R/W", 0, 0, 0ull, 1ull},
- {"SCSE" , 3, 1, 365, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 365, "RO", 0, 0, 0ull, 0ull},
- {"PEE" , 6, 1, 365, "R/W", 0, 0, 0ull, 1ull},
- {"ADS" , 7, 1, 365, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 365, "R/W", 0, 0, 0ull, 1ull},
- {"FBBE" , 9, 1, 365, "R/W", 0, 0, 0ull, 1ull},
- {"I_DIS" , 10, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 365, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 365, "RO", 0, 0, 0ull, 0ull},
- {"CLE" , 20, 1, 365, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 365, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_22" , 22, 1, 365, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 365, "RO", 0, 1, 1ull, 0},
- {"MDPE" , 24, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 365, "RO", 0, 0, 1ull, 1ull},
- {"STA" , 27, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 366, "RO", 0, 0, 3ull, 3ull},
- {"CC" , 8, 24, 366, "RO", 0, 0, 733184ull, 733184ull},
- {"CLS" , 0, 8, 367, "R/W", 0, 1, 0ull, 0},
- {"LT" , 8, 8, 367, "R/W", 0, 0, 0ull, 64ull},
- {"HT" , 16, 8, 367, "RO", 0, 0, 0ull, 0ull},
- {"BCOD" , 24, 4, 367, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_29" , 28, 2, 367, "RAZ", 1, 1, 0, 0},
- {"BRB" , 30, 1, 367, "R/W", 0, 0, 0ull, 0ull},
- {"BCAP" , 31, 1, 367, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 368, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 368, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 368, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 8, 368, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 12, 20, 368, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 369, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 370, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 370, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 23, 370, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 27, 5, 370, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 371, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 372, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 372, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 372, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 28, 372, "RO", 0, 0, 0ull, 0ull},
- {"HBASEZ" , 0, 7, 373, "RO", 0, 0, 0ull, 0ull},
- {"HBASE" , 7, 25, 373, "R/W", 0, 1, 0ull, 0},
- {"CISP" , 0, 32, 374, "RO", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 375, "RO", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 375, "RO", 0, 0, 1ull, 1ull},
- {"ERBAR_EN" , 0, 1, 376, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_10" , 1, 10, 376, "RAZ", 1, 1, 0, 0},
- {"ERBARZ" , 11, 5, 376, "RO", 0, 0, 0ull, 0ull},
- {"ERBAR" , 16, 16, 376, "R/W", 0, 1, 0ull, 0},
- {"CP" , 0, 8, 377, "RO", 0, 0, 224ull, 224ull},
- {"RESERVED_8_31" , 8, 24, 377, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 378, "R/W", 0, 1, 0ull, 0},
- {"INTA" , 8, 8, 378, "RO", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 378, "RO", 0, 0, 64ull, 64ull},
- {"ML" , 24, 8, 378, "RO", 0, 0, 64ull, 64ull},
- {"MLTD" , 0, 1, 379, "R/W", 0, 0, 0ull, 1ull},
- {"TSWC" , 1, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 379, "RAZ", 1, 1, 0, 0},
- {"DPPMR" , 3, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"PBE" , 4, 12, 379, "R/W", 0, 0, 0ull, 0ull},
- {"TILT" , 16, 4, 379, "R/W", 0, 0, 0ull, 0ull},
- {"TSLTE" , 20, 3, 379, "R/W", 0, 0, 0ull, 0ull},
- {"TMAE" , 23, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"TWTAE" , 24, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEN" , 25, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEI" , 26, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"TRTAE" , 27, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"TRDRS" , 28, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"RDSATI" , 29, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"TRDARD" , 30, 1, 379, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRDNPR" , 31, 1, 379, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSCME" , 0, 32, 380, "R/W1C", 0, 1, 0ull, 0},
- {"TDSRPS" , 0, 32, 381, "R/W1C", 0, 0, 0ull, 0ull},
- {"TDOMC" , 0, 5, 382, "R/W", 0, 0, 1ull, 1ull},
- {"TIDOMC" , 5, 1, 382, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 382, "RAZ", 1, 1, 0, 0},
- {"TIBDE" , 7, 1, 382, "R/W", 0, 0, 0ull, 0ull},
- {"TIBCD" , 8, 1, 382, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_10" , 9, 2, 382, "RAZ", 1, 1, 0, 0},
- {"TMAPES" , 11, 1, 382, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMDPES" , 12, 1, 382, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMSE" , 13, 1, 382, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMEI" , 14, 1, 382, "RO", 0, 0, 0ull, 0ull},
- {"TECI" , 15, 1, 382, "RO", 0, 0, 0ull, 0ull},
- {"TMES" , 16, 8, 382, "RO", 0, 0, 0ull, 0ull},
- {"MDRRMC" , 24, 3, 382, "R/W", 0, 0, 2ull, 2ull},
- {"MDRIMC" , 27, 1, 382, "R/W", 0, 0, 0ull, 0ull},
- {"MDRE" , 28, 1, 382, "R/W", 0, 0, 0ull, 0ull},
- {"MDWE" , 29, 1, 382, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCI" , 30, 1, 382, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCM" , 31, 1, 382, "R/W", 0, 0, 1ull, 1ull},
- {"MDSP" , 0, 32, 383, "R/W1C", 0, 1, 0ull, 0},
- {"SCMRE" , 0, 32, 384, "R/W1C", 0, 1, 0ull, 0},
- {"MTTV" , 0, 8, 385, "R/W", 0, 0, 0ull, 0ull},
- {"MRV" , 8, 8, 385, "R/W", 0, 0, 0ull, 255ull},
- {"MTTA" , 16, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRA" , 17, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLUSH" , 18, 1, 385, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_19_24" , 19, 6, 385, "RAZ", 1, 1, 0, 0},
- {"MAC" , 25, 7, 385, "R/W", 0, 0, 0ull, 0ull},
- {"PXCID" , 0, 8, 386, "RO", 0, 0, 7ull, 7ull},
- {"NCP" , 8, 8, 386, "RO", 0, 0, 232ull, 232ull},
- {"DPERE" , 16, 1, 386, "R/W", 0, 0, 0ull, 0ull},
- {"ROE" , 17, 1, 386, "R/W", 0, 0, 1ull, 1ull},
- {"MMBC" , 18, 2, 386, "R/W", 0, 0, 0ull, 0ull},
- {"MOST" , 20, 3, 386, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_23_31" , 23, 9, 386, "RAZ", 1, 1, 0, 0},
- {"FN" , 0, 3, 387, "RO", 0, 0, 0ull, 0ull},
- {"DN" , 3, 5, 387, "RO", 0, 0, 31ull, 31ull},
- {"BN" , 8, 8, 387, "RO", 0, 1, 17ull, 0},
- {"W64" , 16, 1, 387, "RO", 0, 0, 1ull, 1ull},
- {"M133" , 17, 1, 387, "RO", 0, 0, 1ull, 1ull},
- {"SCD" , 18, 1, 387, "R/W1C", 0, 1, 0ull, 0},
- {"USC" , 19, 1, 387, "R/W1C", 0, 1, 0ull, 0},
- {"DC" , 20, 1, 387, "RO", 0, 0, 0ull, 0ull},
- {"MMRBCD" , 21, 2, 387, "RO", 0, 0, 2ull, 2ull},
- {"MOSTD" , 23, 3, 387, "RO", 0, 0, 3ull, 3ull},
- {"MCRSD" , 26, 3, 387, "RO", 0, 0, 7ull, 7ull},
- {"SCEMR" , 29, 1, 387, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 387, "RAZ", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 388, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 388, "RO", 0, 0, 240ull, 240ull},
- {"PCIMIV" , 16, 3, 388, "RO", 0, 0, 2ull, 2ull},
- {"PMEC" , 19, 1, 388, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 388, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 388, "RO", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 388, "RO", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 388, "RO", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 388, "RO", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 388, "RO", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 389, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 389, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 389, "R/W", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 389, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 389, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 389, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEN" , 23, 1, 389, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 389, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 390, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 390, "RO", 0, 0, 0ull, 0ull},
- {"MSIEN" , 16, 1, 390, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 390, "RO", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 390, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 390, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 390, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 391, "RAZ", 1, 1, 0, 0},
- {"MSI31T2" , 2, 30, 391, "R/W", 0, 1, 0ull, 0},
- {"MSI" , 0, 32, 392, "R/W", 0, 1, 0ull, 0},
- {"MSIMD" , 0, 16, 393, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 393, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 394, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 394, "R/W", 0, 0, 0ull, 1ull},
- {"TSR_HWM" , 4, 3, 394, "R/W", 0, 1, 1ull, 0},
- {"PMO_FPC" , 7, 3, 394, "R/W", 0, 0, 0ull, 0ull},
- {"PMO_AMOD" , 10, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"B12_BIST" , 11, 1, 394, "RO", 0, 0, 0ull, 0ull},
- {"AP_64AD" , 12, 1, 394, "RO", 1, 1, 0, 0},
- {"AP_PCIX" , 13, 1, 394, "RO", 1, 1, 0, 0},
- {"RESERVED_14_14" , 14, 1, 394, "RAZ", 0, 0, 0ull, 0ull},
- {"EN_WFILT" , 15, 1, 394, "R/W", 0, 0, 0ull, 1ull},
- {"SCM" , 16, 1, 394, "RO", 0, 1, 0ull, 0},
- {"SCMTYP" , 17, 1, 394, "RO", 0, 1, 0ull, 0},
- {"BAR2PRES" , 18, 1, 394, "R/W", 1, 1, 0, 0},
- {"ERST_N" , 19, 1, 394, "RO", 0, 0, 1ull, 1ull},
- {"BB0" , 20, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"BB1" , 21, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"BB_ES" , 22, 2, 394, "R/W", 0, 0, 0ull, 0ull},
- {"BB_CA" , 24, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"BB1_SIZ" , 25, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"BB1_HOLE" , 26, 3, 394, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 394, "RAZ", 1, 1, 0, 0},
- {"INC_VAL" , 0, 16, 395, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 395, "RAZ", 1, 1, 0, 0},
- {"DMA_CNT" , 0, 32, 396, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 397, "R/W", 0, 1, 0ull, 0},
- {"DMA_TIME" , 0, 32, 398, "R/W", 0, 1, 0ull, 0},
- {"ICNT" , 0, 32, 399, "R/W1C", 0, 0, 0ull, 0ull},
- {"ITR_WABT" , 0, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IMR_WABT" , 1, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IMR_WTTO" , 2, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"ITR_ABT" , 3, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IMR_ABT" , 4, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IMR_TTO" , 5, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IMSI_PER" , 6, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IMSI_TABT" , 7, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IMSI_MABT" , 8, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IMSC_MSG" , 9, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"ITSR_ABT" , 10, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"ISERR" , 11, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IAPERR" , 12, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IDPERR" , 13, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IRSL_INT" , 16, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IPCNT0" , 17, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IPCNT1" , 18, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IPCNT2" , 19, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IPCNT3" , 20, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IPTIME0" , 21, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IPTIME1" , 22, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IPTIME2" , 23, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IPTIME3" , 24, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IDCNT0" , 25, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IDCNT1" , 26, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IDTIME0" , 27, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"IDTIME1" , 28, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 400, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 400, "RAZ", 1, 1, 0, 0},
- {"RTR_WABT" , 0, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RMR_WABT" , 1, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RMR_WTTO" , 2, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RTR_ABT" , 3, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RMR_ABT" , 4, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RMR_TTO" , 5, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RMSI_PER" , 6, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RMSI_TABT" , 7, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RMSI_MABT" , 8, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RMSC_MSG" , 9, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RTSR_ABT" , 10, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RSERR" , 11, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RAPERR" , 12, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RDPERR" , 13, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RRSL_INT" , 16, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RPCNT0" , 17, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RPCNT1" , 18, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RPCNT2" , 19, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RPCNT3" , 20, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RPTIME0" , 21, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RPTIME1" , 22, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RPTIME2" , 23, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RPTIME3" , 24, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RDCNT0" , 25, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RDCNT1" , 26, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RDTIME0" , 27, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RDTIME1" , 28, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 401, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 402, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT2" , 19, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT3" , 20, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME2" , 23, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME3" , 24, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 402, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 403, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT2" , 19, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT3" , 20, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME2" , 23, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME3" , 24, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 403, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 6, 404, "WO", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 404, "R/W", 1, 1, 0, 0},
- {"PTR_CNT" , 0, 16, 405, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 16, 16, 405, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 0, 32, 406, "RO", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 407, "R/W", 0, 1, 0ull, 0},
- {"PKT_TIME" , 0, 32, 408, "R/W", 0, 1, 0ull, 0},
- {"PREFETCH" , 0, 3, 409, "R/W", 0, 0, 0ull, 2ull},
- {"MIN_DATA" , 3, 6, 409, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_9_31" , 9, 23, 409, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 410, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 410, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 410, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 411, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 411, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 411, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 31, 412, "R/W", 0, 0, 10000ull, 10000ull},
- {"ENB" , 31, 1, 412, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 412, "RAZ", 1, 1, 0, 0},
- {"SCM" , 0, 32, 413, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 413, "RAZ", 1, 1, 0, 0},
- {"TSR" , 0, 36, 414, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 414, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 415, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 3, 45, 415, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 415, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 415, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 416, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 417, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 417, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 417, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 417, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 418, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 419, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 420, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 420, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 420, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 420, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 420, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 18, 421, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 421, "RAZ", 1, 1, 0, 0},
- {"REFLECT" , 0, 1, 422, "R/W", 0, 0, 1ull, 1ull},
- {"INVRES" , 1, 1, 422, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 422, "RAZ", 1, 1, 0, 0},
- {"IV" , 0, 32, 423, "R/W", 0, 0, 1185899593ull, 1185899593ull},
- {"RESERVED_32_63" , 32, 32, 423, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 424, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 424, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 424, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 424, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 425, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 425, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 425, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 425, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 425, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 425, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 425, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 425, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 426, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 426, "RAZ", 0, 1, 0ull, 0},
- {"L4_MAL" , 8, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 426, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 426, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 426, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 426, "RAZ", 0, 0, 0ull, 0ull},
- {"PKTDRP" , 0, 1, 427, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 427, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 427, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 427, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 427, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 427, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 427, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 427, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 427, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 427, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 428, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 429, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 429, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 430, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 430, "RAZ", 1, 1, 0, 0},
- {"CRC_EN" , 12, 1, 430, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_15" , 13, 3, 430, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 430, "RAZ", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 430, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 430, "RAZ", 1, 1, 0, 0},
- {"GRP_WAT" , 28, 4, 430, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 430, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 431, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 431, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 431, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 431, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 431, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 431, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 431, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 431, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 431, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 432, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 432, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 433, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 433, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 434, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 2, 434, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 434, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 434, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 434, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 434, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 434, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 434, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 434, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 435, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 435, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 436, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 436, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 437, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 437, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 438, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 438, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 439, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 439, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 440, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 440, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 441, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 441, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 442, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 442, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 443, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 443, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 444, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 444, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 445, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 445, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 446, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 446, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 447, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 448, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 448, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 449, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 449, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 450, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 450, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 451, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 452, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 452, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 453, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 453, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 453, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 454, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 454, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 454, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 455, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 455, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 456, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 456, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 457, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 457, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 457, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 457, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 458, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 458, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 458, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 458, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 458, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 0, 16, 459, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 459, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 459, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 459, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 460, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 460, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 460, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 460, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 460, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 461, "RO", 1, 0, 0, 0ull},
- {"WIDX2" , 0, 17, 462, "RO", 1, 0, 0, 0ull},
- {"RIDX2" , 17, 17, 462, "RO", 1, 0, 0, 0ull},
- {"WIDX" , 34, 17, 462, "RO", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 462, "RAZ", 1, 1, 0, 0},
- {"RIDX" , 0, 17, 463, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 463, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 464, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 464, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 464, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 464, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 464, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 465, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 465, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 465, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 465, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 465, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 466, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 4, 467, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 4, 2, 467, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 6, 1, 467, "RO", 1, 0, 0, 0ull},
- {"QID_BASE" , 7, 7, 467, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 14, 3, 467, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 17, 5, 467, "RO", 1, 0, 0, 0ull},
- {"QOS" , 22, 3, 467, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 467, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 26, 1, 467, "RO", 1, 0, 0, 0ull},
- {"RESERVED_27_27" , 27, 1, 467, "RO", 1, 0, 0, 0ull},
- {"CBUF_FRE" , 28, 1, 467, "RO", 1, 0, 0, 0ull},
- {"XFER_DWR" , 29, 1, 467, "RO", 1, 0, 0, 0ull},
- {"XFER_WOR" , 30, 1, 467, "RO", 1, 0, 0, 0ull},
- {"UID" , 31, 1, 467, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 32, 16, 467, "RO", 1, 0, 0, 0ull},
- {"DWRI_CNT" , 48, 13, 467, "RO", 1, 0, 0, 0ull},
- {"DWRI_LEN" , 61, 1, 467, "RO", 1, 0, 0, 0ull},
- {"DWRI_SOP" , 62, 1, 467, "RO", 1, 0, 0, 0ull},
- {"DWRI_MOD" , 63, 1, 467, "RO", 1, 0, 0, 0ull},
- {"DWRI_MOD" , 0, 2, 468, "RO", 1, 0, 0, 0ull},
- {"DWRI_UID" , 2, 1, 468, "RO", 1, 0, 0, 0ull},
- {"DWRI_CHK" , 3, 1, 468, "RO", 1, 0, 0, 0ull},
- {"WORK_MIN" , 4, 3, 468, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 7, 1, 468, "RO", 1, 0, 0, 0ull},
- {"QID_OFFM" , 8, 3, 468, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 468, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 469, "RO", 1, 0, 0, 0ull},
- {"START" , 16, 33, 469, "RO", 1, 0, 0, 0ull},
- {"DWB" , 49, 9, 469, "RO", 1, 0, 0, 0ull},
- {"RESERVED_58_63" , 58, 6, 469, "RO", 1, 1, 0, 0},
- {"QCB_RIDX" , 0, 6, 470, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 470, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 470, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 470, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 470, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 470, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 471, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 471, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 471, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 471, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 471, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 471, "RO", 1, 0, 0, 0ull},
- {"RESERVED_28_63" , 28, 36, 471, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 472, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 472, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 472, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 472, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 472, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 472, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 472, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 472, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 472, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 473, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 473, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 473, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 473, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 473, "RAZ", 1, 1, 0, 0},
- {"PSB" , 0, 7, 474, "RO", 1, 0, 0, 0ull},
- {"PDB" , 7, 4, 474, "RO", 1, 0, 0, 0ull},
- {"QCB" , 11, 2, 474, "RO", 1, 0, 0, 0ull},
- {"QSB" , 13, 2, 474, "RO", 1, 0, 0, 0ull},
- {"CHK" , 15, 1, 474, "RO", 1, 0, 0, 0ull},
- {"CRC" , 16, 1, 474, "RO", 1, 0, 0, 0ull},
- {"OUT" , 17, 1, 474, "RO", 1, 0, 0, 0ull},
- {"NCB" , 18, 1, 474, "RO", 1, 0, 0, 0ull},
- {"WIF" , 19, 1, 474, "RO", 1, 0, 0, 0ull},
- {"RIF" , 20, 1, 474, "RO", 1, 0, 0, 0ull},
- {"COUNT" , 21, 1, 474, "RO", 1, 0, 0, 0ull},
- {"PSB2" , 22, 5, 474, "RO", 1, 0, 0, 0ull},
- {"RESERVED_27_63" , 27, 37, 474, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 475, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 475, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 475, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 475, "RAZ", 1, 1, 0, 0},
- {"REFIN" , 0, 1, 476, "R/W", 0, 0, 1ull, 1ull},
- {"INVRES" , 1, 1, 476, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 476, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 32, 477, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 477, "RAZ", 1, 1, 0, 0},
- {"IV" , 0, 32, 478, "R/W", 0, 0, 1185899593ull, 1185899593ull},
- {"RESERVED_32_63" , 32, 32, 478, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 17, 479, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 479, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 480, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 480, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 480, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 481, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 481, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 481, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 481, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 481, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 482, "R/W", 0, 0, 0ull, 0ull},
- {"MODE1" , 3, 3, 482, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 482, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 483, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 483, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 483, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 484, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 484, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 485, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 485, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 485, "RAZ", 1, 1, 0, 0},
- {"ADR0" , 0, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"ADR1" , 1, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"PEND0" , 2, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"PEND1" , 3, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 4, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 5, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 6, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 7, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 8, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 9, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 486, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 16, 486, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 486, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 487, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 487, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 488, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 488, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 488, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 488, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 488, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 488, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 488, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 488, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 488, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 488, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 488, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 488, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 488, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 489, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 489, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 489, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 490, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 490, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 491, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 491, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 12, 492, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 492, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 493, "R/W", 0, 0, 0ull, 1023ull},
- {"RESERVED_10_63" , 10, 54, 493, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 494, "R/W", 0, 0, 65535ull, 65535ull},
- {"RESERVED_16_63" , 16, 48, 494, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 495, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 495, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 495, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 495, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 495, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 11, 496, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 496, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 11, 496, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_23_23" , 23, 1, 496, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 12, 496, "RO", 0, 1, 2027ull, 0},
- {"BUF_CNT" , 36, 12, 496, "RO", 0, 1, 0ull, 0},
- {"DES_CNT" , 48, 12, 496, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 496, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 497, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 497, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 498, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 498, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 499, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 499, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 500, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 500, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 500, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 12, 501, "RO", 0, 1, 0ull, 0},
- {"DS_CNT" , 12, 12, 501, "RO", 0, 1, 0ull, 0},
- {"TC_CNT" , 24, 4, 501, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 501, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 502, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 502, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 502, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 502, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 502, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 11, 503, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 503, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 11, 503, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 503, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 503, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 503, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 503, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 504, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 504, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 505, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 505, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 505, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 506, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 507, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 507, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 507, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 507, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 507, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 507, "RAZ", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 507, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 507, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 508, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 508, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 508, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 508, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 1, 508, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 508, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 509, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 509, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 510, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 510, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 510, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 510, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 511, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 511, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 511, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 511, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 512, "RAZ", 0, 0, 0ull, 0ull},
- {"STAT0" , 0, 1, 513, "RO", 0, 0, 0ull, 0ull},
- {"STAT1" , 1, 1, 513, "RO", 0, 0, 0ull, 0ull},
- {"STAT2" , 2, 1, 513, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 513, "RAZ", 0, 0, 0ull, 0ull},
- {"SRXDLCK" , 0, 1, 514, "R/W", 0, 0, 0ull, 1ull},
- {"RCVTRN" , 1, 1, 514, "R/W", 0, 0, 0ull, 1ull},
- {"DRPTRN" , 2, 1, 514, "R/W", 0, 0, 0ull, 1ull},
- {"SNDTRN" , 3, 1, 514, "R/W", 0, 0, 0ull, 1ull},
- {"STATRCV" , 4, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"STATDRV" , 5, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"RUNBIST" , 6, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"CLKDLY" , 7, 5, 514, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_12_15" , 12, 4, 514, "RAZ", 0, 0, 0ull, 0ull},
- {"SEETRN" , 16, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 514, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 515, "RAZ", 0, 1, 0ull, 0},
- {"D4CLK0" , 4, 1, 515, "R/W1C", 0, 1, 0ull, 0},
- {"D4CLK1" , 5, 1, 515, "R/W1C", 0, 1, 0ull, 0},
- {"S4CLK0" , 6, 1, 515, "R/W1C", 0, 1, 0ull, 0},
- {"S4CLK1" , 7, 1, 515, "R/W1C", 0, 1, 0ull, 0},
- {"SRXTRN" , 8, 1, 515, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_9_9" , 9, 1, 515, "RAZ", 0, 1, 0ull, 0},
- {"STXCAL" , 10, 1, 515, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"DLLDIS" , 0, 1, 516, "R/W", 1, 0, 0, 0ull},
- {"DLLFRC" , 1, 1, 516, "WR0", 1, 0, 0, 0ull},
- {"OFFDLY" , 2, 6, 516, "R/W", 1, 0, 0, 0ull},
- {"BITSEL" , 8, 5, 516, "R/W", 1, 1, 0, 0},
- {"OFFSET" , 13, 5, 516, "R/W", 1, 1, 0, 0},
- {"MUX" , 18, 1, 516, "WR0", 1, 1, 0, 0},
- {"INC" , 19, 1, 516, "WR0", 1, 1, 0, 0},
- {"DEC" , 20, 1, 516, "WR0", 1, 1, 0, 0},
- {"CLRDLY" , 21, 1, 516, "WR0", 1, 1, 0, 0},
- {"RESERVED_22_23" , 22, 2, 516, "RAZ", 0, 0, 0ull, 0ull},
- {"SSTEP" , 24, 1, 516, "R/W", 1, 0, 0, 0ull},
- {"SSTEP_GO" , 25, 1, 516, "WR0", 1, 1, 0, 0},
- {"RESERVED_26_27" , 26, 2, 516, "RAZ", 0, 0, 0ull, 0ull},
- {"FALL8" , 28, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"FALLNOP" , 29, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 516, "RAZ", 0, 0, 0ull, 0ull},
- {"OFFSET" , 0, 5, 517, "RO", 0, 1, 0ull, 0},
- {"MUXSEL" , 5, 2, 517, "RO", 0, 1, 0ull, 0},
- {"UNXTERM" , 7, 1, 517, "R/W1C", 0, 0, 0ull, 0ull},
- {"TESTRES" , 8, 1, 517, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 517, "RAZ", 0, 0, 0ull, 0ull},
- {"SRX4CMP" , 0, 8, 518, "R/W", 0, 1, 0ull, 0},
- {"STX4PCMP" , 8, 4, 518, "R/W", 0, 1, 0ull, 0},
- {"STX4NCMP" , 12, 4, 518, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 518, "RAZ", 0, 0, 0ull, 0ull},
- {"ERRCNT" , 0, 4, 519, "R/W", 0, 0, 0ull, 3ull},
- {"RESERVED_4_5" , 4, 2, 519, "RAZ", 0, 0, 0ull, 0ull},
- {"DIPPAY" , 6, 1, 519, "R/W", 0, 0, 0ull, 0ull},
- {"DIPCLS" , 7, 1, 519, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 8, 1, 519, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 519, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT" , 0, 8, 520, "RO", 0, 0, 0ull, 0ull},
- {"RSVOP" , 8, 4, 520, "RO", 0, 0, 0ull, 0ull},
- {"CALBNK" , 12, 2, 520, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_30" , 14, 17, 520, "RAZ", 0, 0, 0ull, 0ull},
- {"MUL" , 31, 1, 520, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 520, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 521, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 521, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 522, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_30" , 12, 19, 522, "RAZ", 0, 0, 0ull, 0ull},
- {"SPF" , 31, 1, 522, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 522, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 523, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 523, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 524, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 524, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX" , 0, 32, 525, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 525, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTSEL" , 0, 4, 526, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 526, "RAZ", 0, 0, 0ull, 0ull},
- {"MUX_EN" , 0, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"MACRO_EN" , 1, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"MAXDIST" , 2, 5, 527, "R/W", 0, 0, 0ull, 8ull},
- {"SET_BOOT" , 7, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"CLR_BOOT" , 8, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"JITTER" , 9, 3, 527, "R/W", 0, 0, 0ull, 1ull},
- {"TRNTEST" , 12, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 527, "RAZ", 0, 0, 0ull, 0ull},
- {"BW_CTL" , 0, 5, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 528, "RAZ", 0, 0, 0ull, 0ull},
- {"SETTING" , 0, 17, 529, "RO", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 529, "RAZ", 0, 0, 0ull, 0ull},
- {"INF_EN" , 0, 1, 530, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_2" , 1, 2, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"ST_EN" , 3, 1, 530, "R/W", 0, 0, 0ull, 1ull},
- {"PRTS" , 4, 4, 530, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"IGNORE" , 0, 16, 531, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 531, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT0" , 0, 4, 532, "R/W", 1, 1, 0, 0},
- {"PRT1" , 4, 4, 532, "R/W", 1, 1, 0, 0},
- {"PRT2" , 8, 4, 532, "R/W", 1, 1, 0, 0},
- {"PRT3" , 12, 4, 532, "R/W", 1, 1, 0, 0},
- {"ODDPAR" , 16, 1, 532, "R/W", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 532, "RAZ", 0, 0, 0ull, 0ull},
- {"LEN" , 0, 7, 533, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 533, "RAZ", 0, 0, 0ull, 0ull},
- {"M" , 8, 8, 533, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 533, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 4, 534, "R/W", 0, 0, 0ull, 0ull},
- {"OPC" , 4, 4, 534, "R/W", 0, 0, 0ull, 0ull},
- {"MOD" , 8, 4, 534, "R/W", 0, 0, 0ull, 0ull},
- {"SOP" , 12, 1, 534, "R/W", 0, 0, 0ull, 0ull},
- {"EOP" , 13, 1, 534, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 534, "RAZ", 0, 0, 0ull, 0ull},
- {"DAT" , 0, 64, 535, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_2" , 0, 3, 536, "R/W", 0, 0, 0ull, 0ull},
- {"IGNTPA" , 3, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"MINTRN" , 5, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 536, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 537, "RAZ", 0, 0, 0ull, 0ull},
- {"INF_EN" , 0, 1, 538, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_2" , 1, 2, 538, "RAZ", 0, 0, 0ull, 0ull},
- {"ST_EN" , 3, 1, 538, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 538, "RAZ", 0, 0, 0ull, 0ull},
- {"DIPMAX" , 0, 4, 539, "R/W", 0, 0, 0ull, 0ull},
- {"FRMMAX" , 4, 4, 539, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 539, "RAZ", 0, 0, 0ull, 0ull},
- {"IGNTPA" , 0, 16, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 540, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 541, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 8, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 542, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 543, "R/W", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 543, "R/W", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 543, "R/W", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 543, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 543, "R/W", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 543, "R/W", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 543, "R/W", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 543, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 543, "RAZ", 0, 0, 0ull, 0ull},
- {"MINB" , 0, 9, 544, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 544, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT0" , 0, 4, 545, "R/W", 1, 1, 0, 0},
- {"PRT1" , 4, 4, 545, "R/W", 1, 1, 0, 0},
- {"PRT2" , 8, 4, 545, "R/W", 1, 1, 0, 0},
- {"PRT3" , 12, 4, 545, "R/W", 1, 1, 0, 0},
- {"ODDPAR" , 16, 1, 545, "R/W", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 545, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_T" , 0, 16, 546, "R/W", 0, 1, 0ull, 0},
- {"ALPHA" , 16, 16, 546, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 546, "RAZ", 0, 0, 0ull, 0ull},
- {"LEN" , 0, 7, 547, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 547, "RAZ", 0, 0, 0ull, 0ull},
- {"M" , 8, 8, 547, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 547, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 548, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 548, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 549, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 549, "RAZ", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 0, 4, 550, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 4, 1, 550, "WR0", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 550, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 551, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 551, "RAZ", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 0, 22, 552, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 552, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 552, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 552, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 552, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 552, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 553, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 553, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 553, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 554, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 554, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 554, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 554, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 554, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 555, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 555, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 555, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 555, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 556, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 556, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 556, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 556, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 556, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 557, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 557, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 557, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 557, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 558, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 558, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 559, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 559, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 559, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 559, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 560, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 561, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 561, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 561, "RAZ", 1, 1, 0, 0},
- {"TDF0" , 0, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"TDF1" , 1, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"TCF" , 2, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 562, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 563, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 563, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 563, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 563, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 564, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 564, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 564, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 565, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 565, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 566, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 566, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 567, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 567, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 568, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 568, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 568, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 568, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 568, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 568, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 568, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 568, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 568, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 568, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 568, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 568, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 569, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 569, "RAZ", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 570, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 570, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 570, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 570, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 570, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 571, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 572, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 572, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 573, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 573, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 574, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 575, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 575, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 575, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 575, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 575, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 575, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 575, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 575, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 575, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 575, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 575, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 575, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 576, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 576, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 577, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 577, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 578, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 579, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 579, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 580, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 580, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 580, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 580, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 580, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 581, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 581, "RAZ", 0, 0, 0ull, 0ull},
- {"ZIP_CTL" , 0, 4, 582, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 27, 582, "RO", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 582, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 583, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 583, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 583, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 583, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 583, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 584, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 584, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 585, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 585, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 585, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 585, "RO", 0, 0, 31744ull, 31744ull},
- {"RESERVED_48_63" , 48, 16, 585, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 14, 586, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 586, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 587, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 587, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 588, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 588, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xxp1[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 4, 0},
- {"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 4, 4},
- {"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 3, 8},
- {"cvmx_asx#_rld_bypass" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 11},
- {"cvmx_asx#_rld_bypass_setting", CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 13},
- {"cvmx_asx#_rld_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 3, 15},
- {"cvmx_asx#_rld_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 3, 18},
- {"cvmx_asx#_rld_nctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 21},
- {"cvmx_asx#_rld_nctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 23},
- {"cvmx_asx#_rld_pctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 25},
- {"cvmx_asx#_rld_pctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 27},
- {"cvmx_asx#_rld_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 6, 29},
- {"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 35},
- {"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 37},
- {"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 39},
- {"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 4, 41},
- {"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 45},
- {"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 47},
- {"cvmx_asx0_dbg_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 3, 49},
- {"cvmx_asx0_dbg_data_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 55, 2, 52},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 56, 2, 54},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 57, 2, 56},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 58, 2, 58},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 59, 2, 60},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 60, 15, 62},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 93, 2, 77},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 126, 15, 79},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 142, 2, 94},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 158, 15, 96},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 191, 15, 111},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 207, 2, 126},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 208, 2, 128},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 2, 130},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 240, 2, 132},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 241, 2, 134},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 242, 2, 136},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 243, 1, 138},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 259, 3, 139},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 260, 2, 142},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 261, 4, 144},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 262, 2, 148},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 263, 3, 150},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 267, 7, 153},
- {"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 283, 5, 160},
- {"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 284, 4, 165},
- {"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 285, 10, 169},
- {"cvmx_dfa_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 286, 5, 179},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 287, 2, 184},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 288, 4, 186},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 289, 3, 190},
- {"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 290, 21, 193},
- {"cvmx_dfa_memcfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 291, 20, 214},
- {"cvmx_dfa_memcfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 11, 234},
- {"cvmx_dfa_memcfg2" , CVMX_CSR_DB_TYPE_RSL, 64, 293, 8, 245},
- {"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 294, 6, 253},
- {"cvmx_dfa_memfcr" , CVMX_CSR_DB_TYPE_RSL, 64, 295, 6, 259},
- {"cvmx_dfa_memrld" , CVMX_CSR_DB_TYPE_RSL, 64, 296, 2, 265},
- {"cvmx_dfa_ncbctl" , CVMX_CSR_DB_TYPE_RSL, 64, 297, 8, 267},
- {"cvmx_dfa_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 298, 6, 275},
- {"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 299, 1, 281},
- {"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 1, 282},
- {"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 301, 1, 283},
- {"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 1, 284},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 6, 285},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 304, 7, 291},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 305, 3, 298},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 312, 2, 301},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 319, 3, 303},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 320, 2, 306},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 321, 29, 308},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 322, 29, 337},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 323, 2, 366},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 331, 2, 368},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 339, 3, 370},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 340, 3, 373},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 341, 2, 376},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 342, 2, 378},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 343, 8, 380},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 345, 2, 388},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 347, 3, 390},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 349, 2, 393},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 351, 5, 395},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 359, 1, 400},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 367, 1, 401},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 375, 1, 402},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 383, 1, 403},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 1, 404},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 399, 1, 405},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 2, 406},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 415, 4, 408},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 423, 2, 412},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 431, 11, 414},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 439, 10, 425},
- {"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 447, 2, 435},
- {"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 455, 2, 437},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 2, 439},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 21, 441},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 479, 21, 462},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 2, 483},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 495, 2, 485},
- {"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 4, 487},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 511, 2, 491},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 2, 493},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 527, 2, 495},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 535, 2, 497},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 543, 2, 499},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 551, 2, 501},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 559, 2, 503},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 567, 2, 505},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 575, 2, 507},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 583, 2, 509},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 591, 4, 511},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 599, 2, 515},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 607, 2, 517},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 615, 2, 519},
- {"cvmx_gmx#_rx_pass_en" , CVMX_CSR_DB_TYPE_RSL, 64, 623, 2, 521},
- {"cvmx_gmx#_rx_pass_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 625, 2, 523},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 657, 3, 525},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 659, 2, 528},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 661, 2, 530},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 669, 3, 532},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 671, 5, 535},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 679, 2, 540},
- {"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 687, 2, 542},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 695, 3, 544},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 703, 2, 547},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 711, 2, 549},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 719, 2, 551},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 727, 2, 553},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 735, 2, 555},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 743, 2, 557},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 751, 2, 559},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 759, 2, 561},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 767, 2, 563},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 775, 2, 565},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 783, 2, 567},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 791, 2, 569},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 799, 2, 571},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 807, 2, 573},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 815, 2, 575},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 823, 2, 577},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 831, 2, 579},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 839, 2, 581},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 847, 2, 583},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 855, 2, 585},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 857, 2, 587},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 859, 2, 589},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 861, 3, 591},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 8, 594},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 8, 602},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 2, 610},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 869, 2, 612},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 871, 4, 614},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 873, 2, 618},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 2, 620},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 877, 2, 622},
- {"cvmx_gmx#_tx_spi_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 879, 3, 624},
- {"cvmx_gmx#_tx_spi_drain" , CVMX_CSR_DB_TYPE_RSL, 64, 881, 2, 627},
- {"cvmx_gmx#_tx_spi_max" , CVMX_CSR_DB_TYPE_RSL, 64, 883, 4, 629},
- {"cvmx_gmx#_tx_spi_round#" , CVMX_CSR_DB_TYPE_RSL, 64, 885, 2, 633},
- {"cvmx_gmx#_tx_spi_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 949, 2, 635},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 951, 7, 637},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 967, 2, 644},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 968, 2, 646},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 969, 2, 648},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 970, 2, 650},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 971, 19, 652},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 972, 6, 671},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 973, 3, 677},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 974, 3, 680},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 975, 3, 683},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 976, 5, 686},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 977, 5, 691},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 978, 1, 696},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 979, 1, 697},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 980, 7, 698},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 981, 7, 705},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 982, 3, 712},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 983, 3, 715},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 984, 3, 718},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 985, 5, 721},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 986, 5, 726},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 987, 1, 731},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 988, 1, 732},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 989, 3, 733},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 3, 736},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 991, 3, 739},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 2, 742},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 993, 2, 744},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 994, 2, 746},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 995, 2, 748},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 996, 17, 750},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 997, 2, 767},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 998, 1, 769},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 999, 12, 770},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1000, 11, 782},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1001, 11, 793},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1002, 2, 804},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1003, 2, 806},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1004, 2, 808},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1005, 3, 810},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1041, 2, 813},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1077, 6, 815},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1078, 5, 821},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1079, 6, 826},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1080, 7, 832},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 1081, 2, 839},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1089, 2, 841},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 1090, 3, 843},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 1091, 5, 846},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 1099, 3, 851},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 1100, 2, 854},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 1101, 2, 856},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1102, 2, 858},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 4, 860},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1104, 3, 864},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 5, 867},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1106, 5, 872},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 7, 877},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1108, 5, 884},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 8, 889},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1110, 10, 897},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1111, 8, 907},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 1112, 5, 915},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 1113, 4, 920},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1114, 2, 924},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 1115, 14, 926},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 1116, 19, 940},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 3, 959},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 1118, 3, 962},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1119, 2, 965},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1123, 17, 967},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1124, 5, 984},
- {"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1125, 5, 989},
- {"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1126, 5, 994},
- {"cvmx_l2c_spar3" , CVMX_CSR_DB_TYPE_RSL, 64, 1127, 5, 999},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1128, 2, 1004},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1129, 3, 1006},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1130, 2, 1009},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1131, 2, 1011},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1132, 2, 1013},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1133, 7, 1015},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1134, 5, 1022},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1135, 3, 1027},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1136, 3, 1030},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1137, 2, 1033},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1138, 2, 1035},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1139, 2, 1037},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1140, 6, 1039},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1141, 14, 1045},
- {"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1142, 2, 1059},
- {"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1143, 2, 1061},
- {"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1144, 2, 1063},
- {"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 2, 1065},
- {"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1146, 2, 1067},
- {"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1147, 2, 1069},
- {"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1148, 2, 1071},
- {"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1149, 2, 1073},
- {"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1150, 2, 1075},
- {"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1158, 2, 1077},
- {"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1160, 2, 1079},
- {"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1162, 2, 1081},
- {"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1164, 2, 1083},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1166, 7, 1085},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 19, 1092},
- {"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 4, 1111},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 2, 1115},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 2, 1117},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 18, 1119},
- {"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 6, 1137},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1173, 5, 1143},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1174, 5, 1148},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1175, 6, 1153},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1176, 2, 1159},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1177, 2, 1161},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1178, 14, 1163},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1179, 9, 1177},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1180, 2, 1186},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1181, 2, 1188},
- {"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1182, 12, 1190},
- {"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1183, 3, 1202},
- {"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1184, 6, 1205},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1185, 9, 1211},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1186, 9, 1220},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1187, 4, 1229},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1188, 3, 1233},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1189, 3, 1236},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1190, 3, 1239},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1191, 5, 1242},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1193, 1, 1247},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1194, 10, 1248},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1202, 13, 1258},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1210, 4, 1271},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1211, 1, 1275},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1215, 2, 1276},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1216, 2, 1278},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1217, 9, 1280},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1218, 8, 1289},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 1219, 2, 1297},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 1220, 3, 1299},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1221, 2, 1302},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 1222, 6, 1304},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1223, 8, 1310},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 1224, 4, 1318},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1225, 2, 1322},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1226, 2, 1324},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1227, 13, 1326},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1228, 12, 1339},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1229, 3, 1351},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1230, 3, 1354},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1231, 2, 1357},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1233, 2, 1359},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1235, 2, 1361},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1237, 7, 1363},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1239, 2, 1370},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1241, 7, 1372},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1243, 4, 1379},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1245, 8, 1383},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1247, 9, 1391},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1249, 7, 1400},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1251, 9, 1407},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1253, 2, 1416},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1255, 2, 1418},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1257, 4, 1420},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1259, 2, 1424},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1261, 2, 1426},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1263, 2, 1428},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1265, 4, 1430},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1267, 2, 1434},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1269, 2, 1436},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1271, 2, 1438},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1273, 2, 1440},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1275, 2, 1442},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1277, 2, 1444},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1279, 6, 1446},
- {"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1281, 2, 1452},
- {"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1285, 2, 1454},
- {"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1289, 21, 1456},
- {"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1290, 3, 1477},
- {"cvmx_npi_comp_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1294, 3, 1480},
- {"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1295, 21, 1483},
- {"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 1296, 2, 1504},
- {"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1297, 13, 1506},
- {"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1298, 3, 1519},
- {"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1299, 3, 1522},
- {"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1300, 3, 1525},
- {"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1301, 3, 1528},
- {"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1302, 2, 1531},
- {"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1303, 2, 1533},
- {"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1304, 10, 1535},
- {"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1305, 63, 1545},
- {"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1306, 63, 1608},
- {"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1307, 2, 1671},
- {"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1308, 2, 1673},
- {"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 1309, 10, 1675},
- {"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1313, 1, 1685},
- {"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1314, 2, 1686},
- {"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1318, 39, 1688},
- {"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1319, 3, 1727},
- {"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1323, 2, 1730},
- {"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1327, 3, 1732},
- {"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1331, 3, 1735},
- {"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1335, 3, 1738},
- {"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 1336, 7, 1741},
- {"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 1337, 2, 1748},
- {"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1338, 13, 1750},
- {"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1339, 13, 1763},
- {"cvmx_npi_port34_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1340, 13, 1776},
- {"cvmx_npi_port35_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1341, 13, 1789},
- {"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1342, 3, 1802},
- {"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 1343, 33, 1805},
- {"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1344, 2, 1838},
- {"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 1348, 2, 1840},
- {"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1349, 5, 1842},
- {"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1381, 2, 1847},
- {"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1382, 24, 1849},
- {"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1383, 2, 1873},
- {"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1384, 7, 1875},
- {"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1385, 5, 1882},
- {"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1386, 1, 1887},
- {"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1387, 5, 1888},
- {"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1388, 1, 1893},
- {"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1389, 4, 1894},
- {"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1390, 2, 1898},
- {"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1391, 1, 1900},
- {"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1392, 2, 1901},
- {"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1393, 4, 1903},
- {"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1394, 2, 1907},
- {"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1395, 4, 1909},
- {"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1396, 16, 1913},
- {"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1397, 1, 1929},
- {"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1398, 1, 1930},
- {"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1399, 18, 1931},
- {"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1400, 1, 1949},
- {"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1401, 1, 1950},
- {"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1402, 7, 1951},
- {"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1403, 7, 1958},
- {"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1404, 13, 1965},
- {"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1405, 10, 1978},
- {"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1406, 10, 1988},
- {"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1407, 7, 1998},
- {"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1408, 2, 2005},
- {"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1409, 1, 2007},
- {"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1410, 2, 2008},
- {"cvmx_pci_cnt_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1411, 6, 2010},
- {"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1412, 22, 2016},
- {"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 1413, 2, 2038},
- {"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 1417, 1, 2040},
- {"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1419, 1, 2041},
- {"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1421, 1, 2042},
- {"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 1423, 1, 2043},
- {"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 1427, 35, 2044},
- {"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1428, 35, 2079},
- {"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 1429, 35, 2114},
- {"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1430, 35, 2149},
- {"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 1431, 2, 2184},
- {"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 1432, 2, 2186},
- {"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 1436, 1, 2188},
- {"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1440, 1, 2189},
- {"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1444, 1, 2190},
- {"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1448, 3, 2191},
- {"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1449, 3, 2194},
- {"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1450, 3, 2197},
- {"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 1451, 3, 2200},
- {"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1452, 2, 2203},
- {"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1453, 2, 2205},
- {"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1454, 4, 2207},
- {"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1455, 1, 2211},
- {"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1456, 4, 2212},
- {"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1457, 1, 2216},
- {"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 1458, 2, 2217},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1459, 5, 2219},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1460, 2, 2224},
- {"cvmx_pip_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 1461, 3, 2226},
- {"cvmx_pip_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 1463, 2, 2229},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1465, 4, 2231},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1469, 8, 2235},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1470, 16, 2243},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1471, 10, 2259},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1472, 10, 2269},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1473, 2, 2279},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1474, 19, 2281},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1510, 25, 2300},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1546, 2, 2325},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1610, 2, 2327},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1618, 9, 2329},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1622, 2, 2338},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1623, 2, 2340},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1624, 2, 2342},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1660, 2, 2344},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1696, 2, 2346},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1732, 2, 2348},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1768, 2, 2350},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1804, 2, 2352},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1840, 2, 2354},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1876, 2, 2356},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1912, 2, 2358},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1948, 2, 2360},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1984, 2, 2362},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1985, 2, 2364},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2021, 2, 2366},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 2057, 2, 2368},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 2093, 2, 2370},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2157, 2, 2372},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2158, 3, 2374},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2159, 3, 2377},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2160, 2, 2380},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2161, 2, 2382},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2162, 4, 2384},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2163, 5, 2388},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2164, 4, 2393},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2165, 8, 2397},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2166, 4, 2405},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2167, 5, 2409},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2168, 5, 2414},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2169, 1, 2419},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2170, 18, 2420},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2171, 4, 2438},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2172, 2, 2442},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2173, 6, 2444},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2174, 7, 2450},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2175, 4, 2457},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 9, 2461},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2177, 5, 2470},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2178, 15, 2475},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2179, 4, 2490},
- {"cvmx_pko_reg_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 3, 2494},
- {"cvmx_pko_reg_crc_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 2, 2497},
- {"cvmx_pko_reg_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 2183, 2, 2499},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2185, 1, 2501},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2186, 1, 2502},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2187, 1, 2503},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2188, 1, 2504},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2189, 4, 2505},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2190, 5, 2509},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2191, 3, 2514},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2192, 4, 2517},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2193, 2, 2521},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 2194, 3, 2523},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2195, 3, 2526},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2196, 13, 2529},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2197, 2, 2542},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2198, 13, 2544},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2199, 3, 2557},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2200, 2, 2560},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2208, 2, 2562},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2209, 2, 2564},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2210, 2, 2566},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 2211, 2, 2568},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2212, 10, 2570},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2228, 5, 2580},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2236, 8, 2585},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2244, 2, 2593},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2245, 2, 2595},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2246, 2, 2597},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2254, 3, 2599},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2255, 4, 2602},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2271, 5, 2606},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2272, 7, 2611},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2288, 2, 2618},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2304, 3, 2620},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2305, 7, 2623},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2306, 8, 2630},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2307, 6, 2638},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2308, 2, 2644},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2309, 4, 2646},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2310, 4, 2650},
- {"cvmx_spx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2311, 2, 2654},
- {"cvmx_spx#_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2313, 4, 2656},
- {"cvmx_spx#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2315, 11, 2660},
- {"cvmx_spx#_clk_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2317, 9, 2671},
- {"cvmx_spx#_dbg_deskew_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2319, 16, 2680},
- {"cvmx_spx#_dbg_deskew_state" , CVMX_CSR_DB_TYPE_RSL, 64, 2321, 5, 2696},
- {"cvmx_spx#_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2323, 5, 2701},
- {"cvmx_spx#_err_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2325, 6, 2706},
- {"cvmx_spx#_int_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2327, 6, 2712},
- {"cvmx_spx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2329, 12, 2718},
- {"cvmx_spx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2331, 14, 2730},
- {"cvmx_spx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2333, 12, 2744},
- {"cvmx_spx#_tpa_acc" , CVMX_CSR_DB_TYPE_RSL, 64, 2335, 2, 2756},
- {"cvmx_spx#_tpa_max" , CVMX_CSR_DB_TYPE_RSL, 64, 2337, 2, 2758},
- {"cvmx_spx#_tpa_sel" , CVMX_CSR_DB_TYPE_RSL, 64, 2339, 2, 2760},
- {"cvmx_spx#_trn4_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2341, 8, 2762},
- {"cvmx_srx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2343, 5, 2770},
- {"cvmx_srx#_ign_rx_full" , CVMX_CSR_DB_TYPE_RSL, 64, 2345, 2, 2775},
- {"cvmx_srx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2347, 6, 2777},
- {"cvmx_srx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2411, 4, 2783},
- {"cvmx_srx#_sw_tick_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2413, 6, 2787},
- {"cvmx_srx#_sw_tick_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2415, 1, 2793},
- {"cvmx_stx#_arb_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2417, 5, 2794},
- {"cvmx_stx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2419, 2, 2799},
- {"cvmx_stx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2421, 4, 2801},
- {"cvmx_stx#_dip_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2423, 3, 2805},
- {"cvmx_stx#_ign_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 2425, 2, 2808},
- {"cvmx_stx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2427, 9, 2810},
- {"cvmx_stx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2429, 10, 2819},
- {"cvmx_stx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2431, 9, 2829},
- {"cvmx_stx#_min_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 2433, 2, 2838},
- {"cvmx_stx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2435, 6, 2840},
- {"cvmx_stx#_spi4_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2499, 3, 2846},
- {"cvmx_stx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2501, 4, 2849},
- {"cvmx_stx#_stat_bytes_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 2503, 2, 2853},
- {"cvmx_stx#_stat_bytes_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 2505, 2, 2855},
- {"cvmx_stx#_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2507, 3, 2857},
- {"cvmx_stx#_stat_pkt_xmt" , CVMX_CSR_DB_TYPE_RSL, 64, 2509, 2, 2860},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2511, 6, 2862},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2512, 3, 2868},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2513, 5, 2871},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2514, 4, 2876},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2515, 6, 2880},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2516, 4, 2886},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2517, 2, 2890},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2518, 4, 2892},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2519, 2, 2896},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2520, 3, 2898},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2521, 4, 2901},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2522, 12, 2905},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2523, 3, 2917},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 2524, 5, 2920},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2525, 2, 2925},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2526, 2, 2927},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2527, 18, 2929},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2528, 12, 2947},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2529, 6, 2959},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2530, 5, 2965},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2531, 1, 2970},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2532, 2, 2971},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2533, 2, 2973},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2534, 18, 2975},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2535, 12, 2993},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2536, 6, 3005},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2537, 2, 3011},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2538, 2, 3013},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2539, 18, 3015},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2540, 12, 3033},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2541, 6, 3045},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2542, 3, 3051},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2543, 5, 3054},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2544, 3, 3059},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2545, 6, 3062},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2546, 2, 3068},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2547, 2, 3070},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2548, 2, 3072},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"ASX0_INT_EN" , 0x11800b0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX1_INT_EN" , 0x11800b8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX0_INT_REG" , 0x11800b0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX1_INT_REG" , 0x11800b8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX0_PRT_LOOP" , 0x11800b0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX1_PRT_LOOP" , 0x11800b8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX0_RLD_BYPASS" , 0x11800b0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX1_RLD_BYPASS" , 0x11800b8000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX0_RLD_BYPASS_SETTING" , 0x11800b0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX1_RLD_BYPASS_SETTING" , 0x11800b8000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX0_RLD_COMP" , 0x11800b0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX1_RLD_COMP" , 0x11800b8000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX0_RLD_DATA_DRV" , 0x11800b0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX1_RLD_DATA_DRV" , 0x11800b8000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_RLD_NCTL_STRONG" , 0x11800b0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX1_RLD_NCTL_STRONG" , 0x11800b8000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX0_RLD_NCTL_WEAK" , 0x11800b0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX1_RLD_NCTL_WEAK" , 0x11800b8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_RLD_PCTL_STRONG" , 0x11800b0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX1_RLD_PCTL_STRONG" , 0x11800b8000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX0_RLD_PCTL_WEAK" , 0x11800b0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX1_RLD_PCTL_WEAK" , 0x11800b8000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX0_RLD_SETTING" , 0x11800b0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"ASX1_RLD_SETTING" , 0x11800b8000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"ASX0_RX_CLK_SET000" , 0x11800b0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX0_RX_CLK_SET001" , 0x11800b0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX0_RX_CLK_SET002" , 0x11800b0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX0_RX_CLK_SET003" , 0x11800b0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX1_RX_CLK_SET000" , 0x11800b8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX1_RX_CLK_SET001" , 0x11800b8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX1_RX_CLK_SET002" , 0x11800b8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX1_RX_CLK_SET003" , 0x11800b8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX0_RX_PRT_EN" , 0x11800b0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX1_RX_PRT_EN" , 0x11800b8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX0_TX_CLK_SET000" , 0x11800b0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX0_TX_CLK_SET001" , 0x11800b0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX0_TX_CLK_SET002" , 0x11800b0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX0_TX_CLK_SET003" , 0x11800b0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX1_TX_CLK_SET000" , 0x11800b8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX1_TX_CLK_SET001" , 0x11800b8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX1_TX_CLK_SET002" , 0x11800b8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX1_TX_CLK_SET003" , 0x11800b8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX0_TX_COMP_BYP" , 0x11800b0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"ASX1_TX_COMP_BYP" , 0x11800b8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"ASX0_TX_HI_WATER000" , 0x11800b0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX0_TX_HI_WATER001" , 0x11800b0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX0_TX_HI_WATER002" , 0x11800b0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX0_TX_HI_WATER003" , 0x11800b0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX1_TX_HI_WATER000" , 0x11800b8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX1_TX_HI_WATER001" , 0x11800b8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX1_TX_HI_WATER002" , 0x11800b8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX1_TX_HI_WATER003" , 0x11800b8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX0_TX_PRT_EN" , 0x11800b0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"ASX1_TX_PRT_EN" , 0x11800b8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"ASX0_DBG_DATA_DRV" , 0x11800b0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"ASX0_DBG_DATA_ENABLE" , 0x11800b0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT10_EN0" , 0x10700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT11_EN0" , 0x10700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT12_EN0" , 0x10700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT13_EN0" , 0x10700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT14_EN0" , 0x10700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT15_EN0" , 0x10700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT24_EN0" , 0x1070000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT25_EN0" , 0x1070000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT26_EN0" , 0x10700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT27_EN0" , 0x10700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT28_EN0" , 0x10700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT29_EN0" , 0x10700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT30_EN0" , 0x10700000003e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT31_EN0" , 0x10700000003f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT10_EN1" , 0x10700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT11_EN1" , 0x10700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT12_EN1" , 0x10700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT13_EN1" , 0x10700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT14_EN1" , 0x10700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT15_EN1" , 0x10700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT24_EN1" , 0x1070000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT25_EN1" , 0x1070000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT26_EN1" , 0x10700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT27_EN1" , 0x10700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT28_EN1" , 0x10700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT29_EN1" , 0x10700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT30_EN1" , 0x10700000003e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT31_EN1" , 0x10700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT4_EN4_0" , 0x1070000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT5_EN4_0" , 0x1070000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT6_EN4_0" , 0x1070000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT7_EN4_0" , 0x1070000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT8_EN4_0" , 0x1070000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT9_EN4_0" , 0x1070000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT10_EN4_0" , 0x1070000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT11_EN4_0" , 0x1070000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT12_EN4_0" , 0x1070000000d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT13_EN4_0" , 0x1070000000d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT14_EN4_0" , 0x1070000000d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT15_EN4_0" , 0x1070000000d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT4_EN4_1" , 0x1070000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT5_EN4_1" , 0x1070000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT6_EN4_1" , 0x1070000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT7_EN4_1" , 0x1070000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT8_EN4_1" , 0x1070000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT9_EN4_1" , 0x1070000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT10_EN4_1" , 0x1070000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT11_EN4_1" , 0x1070000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT12_EN4_1" , 0x1070000000d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT13_EN4_1" , 0x1070000000d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT14_EN4_1" , 0x1070000000d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT15_EN4_1" , 0x1070000000d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT20_SUM0" , 0x10700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT21_SUM0" , 0x10700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT22_SUM0" , 0x10700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT23_SUM0" , 0x10700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT24_SUM0" , 0x10700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT25_SUM0" , 0x10700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT26_SUM0" , 0x10700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT27_SUM0" , 0x10700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT28_SUM0" , 0x10700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT29_SUM0" , 0x10700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT30_SUM0" , 0x10700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT31_SUM0" , 0x10700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT4_SUM4" , 0x1070000000c20ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT5_SUM4" , 0x1070000000c28ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT6_SUM4" , 0x1070000000c30ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT7_SUM4" , 0x1070000000c38ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT8_SUM4" , 0x1070000000c40ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT9_SUM4" , 0x1070000000c48ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT10_SUM4" , 0x1070000000c50ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT11_SUM4" , 0x1070000000c58ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT12_SUM4" , 0x1070000000c60ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT13_SUM4" , 0x1070000000c68ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT14_SUM4" , 0x1070000000c70ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT15_SUM4" , 0x1070000000c78ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR4" , 0x10700000006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR5" , 0x10700000006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR6" , 0x10700000006b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR7" , 0x10700000006b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR8" , 0x10700000006c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR9" , 0x10700000006c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR10" , 0x10700000006d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR11" , 0x10700000006d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR12" , 0x10700000006e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR13" , 0x10700000006e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR14" , 0x10700000006f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_CLR15" , 0x10700000006f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET12" , 0x1070000000660ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET13" , 0x1070000000668ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET14" , 0x1070000000670ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_MBOX_SET15" , 0x1070000000678ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE4" , 0x10700000005a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE5" , 0x10700000005a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE6" , 0x10700000005b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE7" , 0x10700000005b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE8" , 0x10700000005c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE9" , 0x10700000005c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE10" , 0x10700000005d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE11" , 0x10700000005d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE12" , 0x10700000005e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE13" , 0x10700000005e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE14" , 0x10700000005f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_POKE15" , 0x10700000005f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG12" , 0x1070000000560ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG13" , 0x1070000000568ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG14" , 0x1070000000570ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_WDOG15" , 0x1070000000578ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"DBG_DATA" , 0x11f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"DFA_BST0" , 0x11800300007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"DFA_BST1" , 0x11800300007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"DFA_CFG" , 0x1180030000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 47},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 48},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
- {"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"DFA_MEMCFG0" , 0x1180030000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"DFA_MEMCFG1" , 0x1180030000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"DFA_MEMCFG2" , 0x1180030000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"DFA_MEMFCR" , 0x1180030000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"DFA_MEMRLD" , 0x1180030000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"DFA_NCBCTL" , 0x1180030000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"DFA_RODT_COMP_CTL" , 0x1180030000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX1_INF_MODE" , 0x11800100007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX000_ADR_CAM4" , 0x11800100001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX001_ADR_CAM4" , 0x11800100009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX002_ADR_CAM4" , 0x11800100011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_RX003_ADR_CAM4" , 0x11800100019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX000_ADR_CAM5" , 0x11800100001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX001_ADR_CAM5" , 0x11800100009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX002_ADR_CAM5" , 0x11800100011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_RX003_ADR_CAM5" , 0x11800100019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX003_FRM_MAX" , 0x1180008001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX000_FRM_MAX" , 0x1180010000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX001_FRM_MAX" , 0x1180010000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX002_FRM_MAX" , 0x1180010001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX003_FRM_MAX" , 0x1180010001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX003_FRM_MIN" , 0x1180008001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX000_FRM_MIN" , 0x1180010000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX001_FRM_MIN" , 0x1180010000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX002_FRM_MIN" , 0x1180010001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX003_FRM_MIN" , 0x1180010001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180010000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180010000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180010001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180010001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX003_RX_INBND" , 0x1180008001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX000_RX_INBND" , 0x1180010000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX001_RX_INBND" , 0x1180010000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX002_RX_INBND" , 0x1180010001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX003_RX_INBND" , 0x1180010001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX_PASS_EN" , 0x11800080005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX1_RX_PASS_EN" , 0x11800100005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX_PASS_MAP000" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP001" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP002" , 0x1180008000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP003" , 0x1180008000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP004" , 0x1180008000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP005" , 0x1180008000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP006" , 0x1180008000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP007" , 0x1180008000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP008" , 0x1180008000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP009" , 0x1180008000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP010" , 0x1180008000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP011" , 0x1180008000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP012" , 0x1180008000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP013" , 0x1180008000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP014" , 0x1180008000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PASS_MAP015" , 0x1180008000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP000" , 0x1180010000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP001" , 0x1180010000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP002" , 0x1180010000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP003" , 0x1180010000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP004" , 0x1180010000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP005" , 0x1180010000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP006" , 0x1180010000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP007" , 0x1180010000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP008" , 0x1180010000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP009" , 0x1180010000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP010" , 0x1180010000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP011" , 0x1180010000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP012" , 0x1180010000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP013" , 0x1180010000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP014" , 0x1180010000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX_PASS_MAP015" , 0x1180010000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_RX_PRT_INFO" , 0x11800100004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_SMAC001" , 0x1180010000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_SMAC003" , 0x1180010001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX001_APPEND" , 0x1180010000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_TX003_APPEND" , 0x1180010001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX001_BURST" , 0x1180010000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_TX003_BURST" , 0x1180010001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX001_CLK" , 0x1180008000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX003_CLK" , 0x1180008001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX000_CLK" , 0x1180010000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX001_CLK" , 0x1180010000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX002_CLK" , 0x1180010001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_TX003_CLK" , 0x1180010001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX001_CTL" , 0x1180010000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_TX003_CTL" , 0x1180010001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX001_MIN_PKT" , 0x1180010000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_TX003_MIN_PKT" , 0x1180010001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX001_PAUSE_TOGO" , 0x1180010000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_TX003_PAUSE_TOGO" , 0x1180010001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX001_PAUSE_ZERO" , 0x1180010000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX003_PAUSE_ZERO" , 0x1180010001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX001_SLOT" , 0x1180010000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX003_SLOT" , 0x1180010001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX001_SOFT_PAUSE" , 0x1180010000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX003_SOFT_PAUSE" , 0x1180010001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX001_STAT0" , 0x1180010000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX003_STAT0" , 0x1180010001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX001_STAT1" , 0x1180010000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX003_STAT1" , 0x1180010001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX001_STAT2" , 0x1180010000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX003_STAT2" , 0x1180010001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX001_STAT3" , 0x1180010000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX003_STAT3" , 0x1180010001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX000_STAT4" , 0x11800100002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX001_STAT4" , 0x1180010000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX002_STAT4" , 0x11800100012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX003_STAT4" , 0x1180010001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX000_STAT5" , 0x11800100002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX001_STAT5" , 0x1180010000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX002_STAT5" , 0x11800100012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX003_STAT5" , 0x1180010001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX000_STAT6" , 0x11800100002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX001_STAT6" , 0x1180010000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX002_STAT6" , 0x11800100012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX003_STAT6" , 0x1180010001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX000_STAT7" , 0x11800100002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX001_STAT7" , 0x1180010000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX002_STAT7" , 0x11800100012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX003_STAT7" , 0x1180010001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX000_STAT8" , 0x11800100002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX001_STAT8" , 0x1180010000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX002_STAT8" , 0x11800100012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX003_STAT8" , 0x1180010001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX000_STAT9" , 0x11800100002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX001_STAT9" , 0x1180010000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX002_STAT9" , 0x11800100012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX003_STAT9" , 0x1180010001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX001_STATS_CTL" , 0x1180010000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX003_STATS_CTL" , 0x1180010001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX001_THRESH" , 0x1180010000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX003_THRESH" , 0x1180010001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_TX_BP" , 0x11800100004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_TX_CORRUPT" , 0x11800100004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_TX_LFSR" , 0x11800100004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_TX_OVR_BP" , 0x11800100004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX_SPI_CTL" , 0x11800080004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_TX_SPI_CTL" , 0x11800100004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX_SPI_DRAIN" , 0x11800080004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_TX_SPI_DRAIN" , 0x11800100004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX_SPI_MAX" , 0x11800080004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX1_TX_SPI_MAX" , 0x11800100004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX_SPI_ROUND000" , 0x1180008000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND001" , 0x1180008000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND002" , 0x1180008000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND003" , 0x1180008000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND004" , 0x11800080006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND005" , 0x11800080006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND006" , 0x11800080006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND007" , 0x11800080006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND008" , 0x11800080006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND009" , 0x11800080006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND010" , 0x11800080006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND011" , 0x11800080006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND012" , 0x11800080006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND013" , 0x11800080006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND014" , 0x11800080006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND015" , 0x11800080006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND016" , 0x1180008000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND017" , 0x1180008000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND018" , 0x1180008000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND019" , 0x1180008000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND020" , 0x1180008000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND021" , 0x1180008000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND022" , 0x1180008000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND023" , 0x1180008000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND024" , 0x1180008000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND025" , 0x1180008000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND026" , 0x1180008000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND027" , 0x1180008000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND028" , 0x1180008000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND029" , 0x1180008000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND030" , 0x1180008000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_ROUND031" , 0x1180008000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND000" , 0x1180010000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND001" , 0x1180010000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND002" , 0x1180010000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND003" , 0x1180010000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND004" , 0x11800100006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND005" , 0x11800100006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND006" , 0x11800100006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND007" , 0x11800100006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND008" , 0x11800100006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND009" , 0x11800100006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND010" , 0x11800100006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND011" , 0x11800100006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND012" , 0x11800100006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND013" , 0x11800100006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND014" , 0x11800100006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND015" , 0x11800100006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND016" , 0x1180010000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND017" , 0x1180010000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND018" , 0x1180010000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND019" , 0x1180010000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND020" , 0x1180010000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND021" , 0x1180010000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND022" , 0x1180010000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND023" , 0x1180010000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND024" , 0x1180010000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND025" , 0x1180010000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND026" , 0x1180010000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND027" , 0x1180010000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND028" , 0x1180010000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND029" , 0x1180010000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND030" , 0x1180010000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_SPI_ROUND031" , 0x1180010000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_SPI_THRESH" , 0x11800080004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX1_TX_SPI_THRESH" , 0x11800100004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT4_BP_PAGE_CNT" , 0x14f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT5_BP_PAGE_CNT" , 0x14f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT6_BP_PAGE_CNT" , 0x14f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT7_BP_PAGE_CNT" , 0x14f0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT8_BP_PAGE_CNT" , 0x14f0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT9_BP_PAGE_CNT" , 0x14f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT10_BP_PAGE_CNT" , 0x14f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT11_BP_PAGE_CNT" , 0x14f0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT12_BP_PAGE_CNT" , 0x14f0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT13_BP_PAGE_CNT" , 0x14f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT14_BP_PAGE_CNT" , 0x14f0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT15_BP_PAGE_CNT" , 0x14f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT16_BP_PAGE_CNT" , 0x14f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT17_BP_PAGE_CNT" , 0x14f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT18_BP_PAGE_CNT" , 0x14f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT19_BP_PAGE_CNT" , 0x14f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT20_BP_PAGE_CNT" , 0x14f00000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT21_BP_PAGE_CNT" , 0x14f00000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT22_BP_PAGE_CNT" , 0x14f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT23_BP_PAGE_CNT" , 0x14f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT24_BP_PAGE_CNT" , 0x14f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT25_BP_PAGE_CNT" , 0x14f00000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT26_BP_PAGE_CNT" , 0x14f00000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT27_BP_PAGE_CNT" , 0x14f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT28_BP_PAGE_CNT" , 0x14f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT29_BP_PAGE_CNT" , 0x14f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT30_BP_PAGE_CNT" , 0x14f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT31_BP_PAGE_CNT" , 0x14f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR4" , 0x14f00000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR5" , 0x14f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR6" , 0x14f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR7" , 0x14f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR8" , 0x14f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR9" , 0x14f0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR10" , 0x14f0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR11" , 0x14f0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR12" , 0x14f0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR13" , 0x14f0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR14" , 0x14f0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR15" , 0x14f0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14f0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14f0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14f0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14f0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR20" , 0x14f0000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR21" , 0x14f0000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR22" , 0x14f0000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR23" , 0x14f0000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR24" , 0x14f0000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR25" , 0x14f0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR26" , 0x14f0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR27" , 0x14f0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR28" , 0x14f0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR29" , 0x14f00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR30" , 0x14f00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR31" , 0x14f00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"L2C_SPAR3" , 0x1180080000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"LED_BLINK" , 0x1180000001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"LED_CLK_PHASE" , 0x1180000001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"LED_CYLON" , 0x1180000001af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"LED_DBG" , 0x1180000001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"LED_EN" , 0x1180000001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"LED_POLARITY" , 0x1180000001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"LED_PRT" , 0x1180000001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"LED_PRT_FMT" , 0x1180000001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LED_PRT_STATUS0" , 0x1180000001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_PRT_STATUS1" , 0x1180000001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_PRT_STATUS2" , 0x1180000001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_PRT_STATUS3" , 0x1180000001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_PRT_STATUS4" , 0x1180000001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_PRT_STATUS5" , 0x1180000001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_PRT_STATUS6" , 0x1180000001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_PRT_STATUS7" , 0x1180000001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_UDD_CNT0" , 0x1180000001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"LED_UDD_CNT1" , 0x1180000001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"LED_UDD_DAT0" , 0x1180000001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"LED_UDD_DAT1" , 0x1180000001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"LED_UDD_DAT_CLR0" , 0x1180000001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"LED_UDD_DAT_CLR1" , 0x1180000001ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"LED_UDD_DAT_SET0" , 0x1180000001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"LED_UDD_DAT_SET1" , 0x1180000001ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"LMC0_PLL_CTL" , 0x11800880000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"LMC0_PLL_STATUS" , 0x11800880000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"LMC0_RODT_COMP_CTL" , 0x11800880000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"NPI_BASE_ADDR_INPUT0" , 0x11f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"NPI_BASE_ADDR_INPUT1" , 0x11f0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"NPI_BASE_ADDR_INPUT2" , 0x11f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"NPI_BASE_ADDR_INPUT3" , 0x11f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"NPI_BASE_ADDR_OUTPUT0" , 0x11f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"NPI_BASE_ADDR_OUTPUT1" , 0x11f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"NPI_BASE_ADDR_OUTPUT2" , 0x11f00000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"NPI_BASE_ADDR_OUTPUT3" , 0x11f00000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"NPI_BIST_STATUS" , 0x11f00000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"NPI_BUFF_SIZE_OUTPUT0" , 0x11f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"NPI_BUFF_SIZE_OUTPUT1" , 0x11f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"NPI_BUFF_SIZE_OUTPUT2" , 0x11f00000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"NPI_BUFF_SIZE_OUTPUT3" , 0x11f00000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"NPI_COMP_CTL" , 0x11f0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"NPI_CTL_STATUS" , 0x11f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"NPI_DBG_SELECT" , 0x11f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"NPI_DMA_CONTROL" , 0x11f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"NPI_DMA_HIGHP_COUNTS" , 0x11f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"NPI_DMA_HIGHP_NADDR" , 0x11f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"NPI_DMA_LOWP_COUNTS" , 0x11f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"NPI_DMA_LOWP_NADDR" , 0x11f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"NPI_HIGHP_DBELL" , 0x11f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
- {"NPI_HIGHP_IBUFF_SADDR" , 0x11f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"NPI_INPUT_CONTROL" , 0x11f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"NPI_INT_ENB" , 0x11f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"NPI_INT_SUM" , 0x11f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"NPI_LOWP_DBELL" , 0x11f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
- {"NPI_LOWP_IBUFF_SADDR" , 0x11f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 353},
- {"NPI_MEM_ACCESS_SUBID3" , 0x11f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"NPI_MEM_ACCESS_SUBID4" , 0x11f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"NPI_MEM_ACCESS_SUBID5" , 0x11f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"NPI_MEM_ACCESS_SUBID6" , 0x11f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"NPI_MSI_RCV" , 0x11f0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 355},
- {"NPI_NUM_DESC_OUTPUT0" , 0x11f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
- {"NPI_NUM_DESC_OUTPUT1" , 0x11f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
- {"NPI_NUM_DESC_OUTPUT2" , 0x11f0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
- {"NPI_NUM_DESC_OUTPUT3" , 0x11f0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
- {"NPI_OUTPUT_CONTROL" , 0x11f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 357},
- {"NPI_P0_DBPAIR_ADDR" , 0x11f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
- {"NPI_P1_DBPAIR_ADDR" , 0x11f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
- {"NPI_P2_DBPAIR_ADDR" , 0x11f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
- {"NPI_P3_DBPAIR_ADDR" , 0x11f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
- {"NPI_P0_INSTR_ADDR" , 0x11f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
- {"NPI_P1_INSTR_ADDR" , 0x11f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
- {"NPI_P2_INSTR_ADDR" , 0x11f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
- {"NPI_P3_INSTR_ADDR" , 0x11f00000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
- {"NPI_P0_INSTR_CNTS" , 0x11f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
- {"NPI_P1_INSTR_CNTS" , 0x11f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
- {"NPI_P2_INSTR_CNTS" , 0x11f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
- {"NPI_P3_INSTR_CNTS" , 0x11f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
- {"NPI_P0_PAIR_CNTS" , 0x11f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
- {"NPI_P1_PAIR_CNTS" , 0x11f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
- {"NPI_P2_PAIR_CNTS" , 0x11f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
- {"NPI_P3_PAIR_CNTS" , 0x11f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
- {"NPI_PCI_BURST_SIZE" , 0x11f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
- {"NPI_PCI_INT_ARB_CFG" , 0x11f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
- {"NPI_PCI_READ_CMD" , 0x11f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
- {"NPI_PORT32_INSTR_HDR" , 0x11f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
- {"NPI_PORT33_INSTR_HDR" , 0x11f0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
- {"NPI_PORT34_INSTR_HDR" , 0x11f0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
- {"NPI_PORT35_INSTR_HDR" , 0x11f0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
- {"NPI_PORT_BP_CONTROL" , 0x11f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
- {"NPI_RSL_INT_BLOCKS" , 0x11f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
- {"NPI_SIZE_INPUT0" , 0x11f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"NPI_SIZE_INPUT1" , 0x11f0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"NPI_SIZE_INPUT2" , 0x11f0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"NPI_SIZE_INPUT3" , 0x11f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"NPI_WIN_READ_TO" , 0x11f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
- {"PCI_BAR1_INDEX0" , 0x11f0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX1" , 0x11f0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX2" , 0x11f0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX3" , 0x11f000000110cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX4" , 0x11f0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX5" , 0x11f0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX6" , 0x11f0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX7" , 0x11f000000111cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX8" , 0x11f0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX9" , 0x11f0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX10" , 0x11f0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX11" , 0x11f000000112cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX12" , 0x11f0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX13" , 0x11f0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX14" , 0x11f0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX15" , 0x11f000000113cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX16" , 0x11f0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX17" , 0x11f0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX18" , 0x11f0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX19" , 0x11f000000114cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX20" , 0x11f0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX21" , 0x11f0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX22" , 0x11f0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX23" , 0x11f000000115cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX24" , 0x11f0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX25" , 0x11f0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX26" , 0x11f0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX27" , 0x11f000000116cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX28" , 0x11f0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX29" , 0x11f0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX30" , 0x11f0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_BAR1_INDEX31" , 0x11f000000117cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
- {"PCI_CFG00" , 0x11f0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 374},
- {"PCI_CFG01" , 0x11f0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 375},
- {"PCI_CFG02" , 0x11f0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 376},
- {"PCI_CFG03" , 0x11f000000180cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 377},
- {"PCI_CFG04" , 0x11f0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 378},
- {"PCI_CFG05" , 0x11f0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 379},
- {"PCI_CFG06" , 0x11f0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 380},
- {"PCI_CFG07" , 0x11f000000181cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 381},
- {"PCI_CFG08" , 0x11f0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 382},
- {"PCI_CFG09" , 0x11f0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 383},
- {"PCI_CFG10" , 0x11f0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 384},
- {"PCI_CFG11" , 0x11f000000182cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 385},
- {"PCI_CFG12" , 0x11f0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 386},
- {"PCI_CFG13" , 0x11f0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 387},
- {"PCI_CFG15" , 0x11f000000183cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 388},
- {"PCI_CFG16" , 0x11f0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 389},
- {"PCI_CFG17" , 0x11f0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 390},
- {"PCI_CFG18" , 0x11f0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 391},
- {"PCI_CFG19" , 0x11f000000184cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 392},
- {"PCI_CFG20" , 0x11f0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 393},
- {"PCI_CFG21" , 0x11f0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 394},
- {"PCI_CFG22" , 0x11f0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 395},
- {"PCI_CFG56" , 0x11f00000018e0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 396},
- {"PCI_CFG57" , 0x11f00000018e4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 397},
- {"PCI_CFG58" , 0x11f00000018e8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 398},
- {"PCI_CFG59" , 0x11f00000018ecull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 399},
- {"PCI_CFG60" , 0x11f00000018f0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 400},
- {"PCI_CFG61" , 0x11f00000018f4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 401},
- {"PCI_CFG62" , 0x11f00000018f8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 402},
- {"PCI_CFG63" , 0x11f00000018fcull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 403},
- {"PCI_CNT_REG" , 0x11f00000011b8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 404},
- {"PCI_CTL_STATUS_2" , 0x11f000000118cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 405},
- {"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
- {"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
- {"PCI_DBELL2" , 0x90ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
- {"PCI_DBELL3" , 0x98ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
- {"PCI_DMA_CNT0" , 0xa0ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
- {"PCI_DMA_CNT1" , 0xa8ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
- {"PCI_DMA_INT_LEV0" , 0xa4ull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
- {"PCI_DMA_INT_LEV1" , 0xacull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
- {"PCI_DMA_TIME0" , 0xb0ull, CVMX_CSR_DB_TYPE_PCI, 32, 409},
- {"PCI_DMA_TIME1" , 0xb4ull, CVMX_CSR_DB_TYPE_PCI, 32, 409},
- {"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 410},
- {"PCI_INSTR_COUNT1" , 0x8cull, CVMX_CSR_DB_TYPE_PCI, 32, 410},
- {"PCI_INSTR_COUNT2" , 0x94ull, CVMX_CSR_DB_TYPE_PCI, 32, 410},
- {"PCI_INSTR_COUNT3" , 0x9cull, CVMX_CSR_DB_TYPE_PCI, 32, 410},
- {"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 411},
- {"PCI_INT_ENB2" , 0x11f00000011a0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 412},
- {"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 413},
- {"PCI_INT_SUM2" , 0x11f0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 414},
- {"PCI_MSI_RCV" , 0xf0ull, CVMX_CSR_DB_TYPE_PCI, 32, 415},
- {"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
- {"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
- {"PCI_PKT_CREDITS2" , 0x64ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
- {"PCI_PKT_CREDITS3" , 0x74ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
- {"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
- {"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
- {"PCI_PKTS_SENT2" , 0x60ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
- {"PCI_PKTS_SENT3" , 0x70ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
- {"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
- {"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
- {"PCI_PKTS_SENT_INT_LEV2" , 0x68ull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
- {"PCI_PKTS_SENT_INT_LEV3" , 0x78ull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
- {"PCI_PKTS_SENT_TIME0" , 0x4cull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
- {"PCI_PKTS_SENT_TIME1" , 0x5cull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
- {"PCI_PKTS_SENT_TIME2" , 0x6cull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
- {"PCI_PKTS_SENT_TIME3" , 0x7cull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
- {"PCI_READ_CMD_6" , 0x11f0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 420},
- {"PCI_READ_CMD_C" , 0x11f0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 421},
- {"PCI_READ_CMD_E" , 0x11f0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 422},
- {"PCI_READ_TIMEOUT" , 0x11f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 423},
- {"PCI_SCM_REG" , 0x11f00000011a8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 424},
- {"PCI_TSR_REG" , 0x11f00000011b0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 425},
- {"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 426},
- {"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 427},
- {"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 428},
- {"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 429},
- {"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 430},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_CRC_CTL0" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_CRC_CTL1" , 0x11800a0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_CRC_IV0" , 0x11800a0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_CRC_IV1" , 0x11800a0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG4" , 0x11800a0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG5" , 0x11800a0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG6" , 0x11800a0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG7" , 0x11800a0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG8" , 0x11800a0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG9" , 0x11800a0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG10" , 0x11800a0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG11" , 0x11800a0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG12" , 0x11800a0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG13" , 0x11800a0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG14" , 0x11800a0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG15" , 0x11800a0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG16" , 0x11800a0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG17" , 0x11800a0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG18" , 0x11800a0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG19" , 0x11800a0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG20" , 0x11800a00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG21" , 0x11800a00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG22" , 0x11800a00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG23" , 0x11800a00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG24" , 0x11800a00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG25" , 0x11800a00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG26" , 0x11800a00002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG27" , 0x11800a00002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG28" , 0x11800a00002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG29" , 0x11800a00002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG30" , 0x11800a00002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG31" , 0x11800a00002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG4" , 0x11800a0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG5" , 0x11800a0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG6" , 0x11800a0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG7" , 0x11800a0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG8" , 0x11800a0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG9" , 0x11800a0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG10" , 0x11800a0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG11" , 0x11800a0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG12" , 0x11800a0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG13" , 0x11800a0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG14" , 0x11800a0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG15" , 0x11800a0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG16" , 0x11800a0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG17" , 0x11800a0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG18" , 0x11800a0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG19" , 0x11800a0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG20" , 0x11800a00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG21" , 0x11800a00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG22" , 0x11800a00004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG23" , 0x11800a00004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG24" , 0x11800a00004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG25" , 0x11800a00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG26" , 0x11800a00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG27" , 0x11800a00004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG28" , 0x11800a00004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG29" , 0x11800a00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG30" , 0x11800a00004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG31" , 0x11800a00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT4" , 0x11800a0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT5" , 0x11800a0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT6" , 0x11800a00009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT7" , 0x11800a0000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT8" , 0x11800a0000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT9" , 0x11800a0000ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT10" , 0x11800a0000b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT11" , 0x11800a0000b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT12" , 0x11800a0000bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT13" , 0x11800a0000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT14" , 0x11800a0000c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT15" , 0x11800a0000cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT16" , 0x11800a0000d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT17" , 0x11800a0000d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT18" , 0x11800a0000da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT19" , 0x11800a0000df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT20" , 0x11800a0000e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT21" , 0x11800a0000e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT22" , 0x11800a0000ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT23" , 0x11800a0000f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT24" , 0x11800a0000f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT25" , 0x11800a0000fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT26" , 0x11800a0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT27" , 0x11800a0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT28" , 0x11800a00010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT29" , 0x11800a0001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT30" , 0x11800a0001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT31" , 0x11800a00011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT4" , 0x11800a0000948ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT5" , 0x11800a0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT6" , 0x11800a00009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT7" , 0x11800a0000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT8" , 0x11800a0000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT9" , 0x11800a0000ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT10" , 0x11800a0000b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT11" , 0x11800a0000b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT12" , 0x11800a0000bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT13" , 0x11800a0000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT14" , 0x11800a0000c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT15" , 0x11800a0000cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT16" , 0x11800a0000d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT17" , 0x11800a0000d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT18" , 0x11800a0000da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT19" , 0x11800a0000df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT20" , 0x11800a0000e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT21" , 0x11800a0000e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT22" , 0x11800a0000ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT23" , 0x11800a0000f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT24" , 0x11800a0000f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT25" , 0x11800a0000fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT26" , 0x11800a0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT27" , 0x11800a0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT28" , 0x11800a00010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT29" , 0x11800a0001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT30" , 0x11800a0001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT31" , 0x11800a00011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT4" , 0x11800a0000950ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT5" , 0x11800a00009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT6" , 0x11800a00009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT7" , 0x11800a0000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT8" , 0x11800a0000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT9" , 0x11800a0000ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT10" , 0x11800a0000b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT11" , 0x11800a0000b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT12" , 0x11800a0000bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT13" , 0x11800a0000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT14" , 0x11800a0000c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT15" , 0x11800a0000cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT16" , 0x11800a0000d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT17" , 0x11800a0000d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT18" , 0x11800a0000db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT19" , 0x11800a0000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT20" , 0x11800a0000e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT21" , 0x11800a0000ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT22" , 0x11800a0000ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT23" , 0x11800a0000f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT24" , 0x11800a0000f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT25" , 0x11800a0000fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT26" , 0x11800a0001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT27" , 0x11800a0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT28" , 0x11800a00010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT29" , 0x11800a0001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT30" , 0x11800a0001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT31" , 0x11800a00011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT4" , 0x11800a0000958ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT5" , 0x11800a00009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT6" , 0x11800a00009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT7" , 0x11800a0000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT8" , 0x11800a0000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT9" , 0x11800a0000ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT10" , 0x11800a0000b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT11" , 0x11800a0000b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT12" , 0x11800a0000bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT13" , 0x11800a0000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT14" , 0x11800a0000c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT15" , 0x11800a0000cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT16" , 0x11800a0000d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT17" , 0x11800a0000d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT18" , 0x11800a0000db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT19" , 0x11800a0000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT20" , 0x11800a0000e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT21" , 0x11800a0000ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT22" , 0x11800a0000ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT23" , 0x11800a0000f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT24" , 0x11800a0000f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT25" , 0x11800a0000fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT26" , 0x11800a0001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT27" , 0x11800a0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT28" , 0x11800a00010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT29" , 0x11800a0001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT30" , 0x11800a0001178ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT31" , 0x11800a00011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT4" , 0x11800a0000960ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT5" , 0x11800a00009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT6" , 0x11800a0000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT7" , 0x11800a0000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT8" , 0x11800a0000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT9" , 0x11800a0000af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT10" , 0x11800a0000b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT11" , 0x11800a0000b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT12" , 0x11800a0000be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT13" , 0x11800a0000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT14" , 0x11800a0000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT15" , 0x11800a0000cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT16" , 0x11800a0000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT17" , 0x11800a0000d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT18" , 0x11800a0000dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT19" , 0x11800a0000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT20" , 0x11800a0000e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT21" , 0x11800a0000eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT22" , 0x11800a0000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT23" , 0x11800a0000f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT24" , 0x11800a0000fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT25" , 0x11800a0000ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT26" , 0x11800a0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT27" , 0x11800a0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT28" , 0x11800a00010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT29" , 0x11800a0001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT30" , 0x11800a0001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT31" , 0x11800a00011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT4" , 0x11800a0000968ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT5" , 0x11800a00009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT6" , 0x11800a0000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT7" , 0x11800a0000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT8" , 0x11800a0000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT9" , 0x11800a0000af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT10" , 0x11800a0000b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT11" , 0x11800a0000b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT12" , 0x11800a0000be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT13" , 0x11800a0000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT14" , 0x11800a0000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT15" , 0x11800a0000cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT16" , 0x11800a0000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT17" , 0x11800a0000d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT18" , 0x11800a0000dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT19" , 0x11800a0000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT20" , 0x11800a0000e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT21" , 0x11800a0000eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT22" , 0x11800a0000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT23" , 0x11800a0000f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT24" , 0x11800a0000fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT25" , 0x11800a0000ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT26" , 0x11800a0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT27" , 0x11800a0001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT28" , 0x11800a00010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT29" , 0x11800a0001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT30" , 0x11800a0001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT31" , 0x11800a00011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT4" , 0x11800a0000970ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT5" , 0x11800a00009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT6" , 0x11800a0000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT7" , 0x11800a0000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT8" , 0x11800a0000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT9" , 0x11800a0000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT10" , 0x11800a0000b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT11" , 0x11800a0000ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT12" , 0x11800a0000bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT13" , 0x11800a0000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT14" , 0x11800a0000c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT15" , 0x11800a0000ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT16" , 0x11800a0000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT17" , 0x11800a0000d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT18" , 0x11800a0000dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT19" , 0x11800a0000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT20" , 0x11800a0000e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT21" , 0x11800a0000ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT22" , 0x11800a0000f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT23" , 0x11800a0000f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT24" , 0x11800a0000fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT25" , 0x11800a0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT26" , 0x11800a0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT27" , 0x11800a00010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT28" , 0x11800a00010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT29" , 0x11800a0001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT30" , 0x11800a0001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT31" , 0x11800a00011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT4" , 0x11800a0000978ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT5" , 0x11800a00009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT6" , 0x11800a0000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT7" , 0x11800a0000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT8" , 0x11800a0000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT9" , 0x11800a0000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT10" , 0x11800a0000b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT11" , 0x11800a0000ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT12" , 0x11800a0000bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT13" , 0x11800a0000c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT14" , 0x11800a0000c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT15" , 0x11800a0000ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT16" , 0x11800a0000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT17" , 0x11800a0000d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT18" , 0x11800a0000dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT19" , 0x11800a0000e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT20" , 0x11800a0000e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT21" , 0x11800a0000ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT22" , 0x11800a0000f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT23" , 0x11800a0000f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT24" , 0x11800a0000fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT25" , 0x11800a0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT26" , 0x11800a0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT27" , 0x11800a00010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT28" , 0x11800a00010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT29" , 0x11800a0001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT30" , 0x11800a0001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT31" , 0x11800a00011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT4" , 0x11800a0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT5" , 0x11800a00009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT6" , 0x11800a0000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT7" , 0x11800a0000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT8" , 0x11800a0000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT9" , 0x11800a0000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT10" , 0x11800a0000b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT11" , 0x11800a0000bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT12" , 0x11800a0000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT13" , 0x11800a0000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT14" , 0x11800a0000ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT15" , 0x11800a0000cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT16" , 0x11800a0000d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT17" , 0x11800a0000d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT18" , 0x11800a0000de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT19" , 0x11800a0000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT20" , 0x11800a0000e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT21" , 0x11800a0000ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT22" , 0x11800a0000f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT23" , 0x11800a0000f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT24" , 0x11800a0000fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT25" , 0x11800a0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT26" , 0x11800a0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT27" , 0x11800a00010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT28" , 0x11800a0001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT29" , 0x11800a0001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT30" , 0x11800a00011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT31" , 0x11800a00011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT4" , 0x11800a0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT5" , 0x11800a00009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT6" , 0x11800a0000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT7" , 0x11800a0000a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT8" , 0x11800a0000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT9" , 0x11800a0000b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT10" , 0x11800a0000b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT11" , 0x11800a0000bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT12" , 0x11800a0000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT13" , 0x11800a0000c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT14" , 0x11800a0000ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT15" , 0x11800a0000cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT16" , 0x11800a0000d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT17" , 0x11800a0000d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT18" , 0x11800a0000de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT19" , 0x11800a0000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT20" , 0x11800a0000e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT21" , 0x11800a0000ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT22" , 0x11800a0000f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT23" , 0x11800a0000f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT24" , 0x11800a0000fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT25" , 0x11800a0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT26" , 0x11800a0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT27" , 0x11800a00010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT28" , 0x11800a0001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT29" , 0x11800a0001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT30" , 0x11800a00011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT31" , 0x11800a00011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS4" , 0x11800a0001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS5" , 0x11800a0001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS6" , 0x11800a0001ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS7" , 0x11800a0001af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS8" , 0x11800a0001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS9" , 0x11800a0001b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS10" , 0x11800a0001b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS11" , 0x11800a0001b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS12" , 0x11800a0001b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS13" , 0x11800a0001bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS14" , 0x11800a0001bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS15" , 0x11800a0001bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS16" , 0x11800a0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS17" , 0x11800a0001c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS18" , 0x11800a0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS19" , 0x11800a0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS20" , 0x11800a0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS21" , 0x11800a0001cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS22" , 0x11800a0001cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS23" , 0x11800a0001cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS24" , 0x11800a0001d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS25" , 0x11800a0001d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS26" , 0x11800a0001d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS27" , 0x11800a0001d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS28" , 0x11800a0001d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS29" , 0x11800a0001db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS30" , 0x11800a0001dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS31" , 0x11800a0001df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS4" , 0x11800a0001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS5" , 0x11800a0001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS6" , 0x11800a0001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS7" , 0x11800a0001ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS8" , 0x11800a0001b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS9" , 0x11800a0001b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS10" , 0x11800a0001b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS11" , 0x11800a0001b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS12" , 0x11800a0001b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS13" , 0x11800a0001ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS14" , 0x11800a0001bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS15" , 0x11800a0001be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS16" , 0x11800a0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS17" , 0x11800a0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS18" , 0x11800a0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS19" , 0x11800a0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS20" , 0x11800a0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS21" , 0x11800a0001ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS22" , 0x11800a0001cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS23" , 0x11800a0001ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS24" , 0x11800a0001d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS25" , 0x11800a0001d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS26" , 0x11800a0001d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS27" , 0x11800a0001d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS28" , 0x11800a0001d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS29" , 0x11800a0001da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS30" , 0x11800a0001dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS31" , 0x11800a0001de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS4" , 0x11800a0001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS5" , 0x11800a0001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS6" , 0x11800a0001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS7" , 0x11800a0001ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS8" , 0x11800a0001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS9" , 0x11800a0001b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS10" , 0x11800a0001b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS11" , 0x11800a0001b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS12" , 0x11800a0001b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS13" , 0x11800a0001ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS14" , 0x11800a0001bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS15" , 0x11800a0001be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS16" , 0x11800a0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS17" , 0x11800a0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS18" , 0x11800a0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS19" , 0x11800a0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS20" , 0x11800a0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS21" , 0x11800a0001ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS22" , 0x11800a0001cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS23" , 0x11800a0001ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS24" , 0x11800a0001d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS25" , 0x11800a0001d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS26" , 0x11800a0001d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS27" , 0x11800a0001d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS28" , 0x11800a0001d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS29" , 0x11800a0001da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS30" , 0x11800a0001dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS31" , 0x11800a0001de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"PKO_REG_CRC_CTL0" , 0x1180050000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"PKO_REG_CRC_CTL1" , 0x1180050000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"PKO_REG_CRC_ENABLE" , 0x1180050000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"PKO_REG_CRC_IV0" , 0x1180050000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"PKO_REG_CRC_IV1" , 0x1180050000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 500},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 502},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 505},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 506},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 507},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 508},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK12" , 0x1670000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK13" , 0x1670000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK14" , 0x1670000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_PP_GRP_MSK15" , 0x1670000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 512},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 513},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 515},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 517},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"SPX0_BCKPRS_CNT" , 0x1180090000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"SPX1_BCKPRS_CNT" , 0x1180098000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"SPX0_BIST_STAT" , 0x11800900007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"SPX1_BIST_STAT" , 0x11800980007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"SPX0_CLK_CTL" , 0x1180090000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"SPX1_CLK_CTL" , 0x1180098000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"SPX0_CLK_STAT" , 0x1180090000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"SPX1_CLK_STAT" , 0x1180098000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"SPX0_DBG_DESKEW_CTL" , 0x1180090000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"SPX1_DBG_DESKEW_CTL" , 0x1180098000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"SPX0_DBG_DESKEW_STATE" , 0x1180090000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SPX1_DBG_DESKEW_STATE" , 0x1180098000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SPX0_DRV_CTL" , 0x1180090000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"SPX1_DRV_CTL" , 0x1180098000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"SPX0_ERR_CTL" , 0x1180090000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"SPX1_ERR_CTL" , 0x1180098000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"SPX0_INT_DAT" , 0x1180090000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"SPX1_INT_DAT" , 0x1180098000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"SPX0_INT_MSK" , 0x1180090000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"SPX1_INT_MSK" , 0x1180098000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"SPX0_INT_REG" , 0x1180090000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"SPX1_INT_REG" , 0x1180098000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"SPX0_INT_SYNC" , 0x1180090000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"SPX1_INT_SYNC" , 0x1180098000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"SPX0_TPA_ACC" , 0x1180090000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"SPX1_TPA_ACC" , 0x1180098000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"SPX0_TPA_MAX" , 0x1180090000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"SPX1_TPA_MAX" , 0x1180098000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"SPX0_TPA_SEL" , 0x1180090000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"SPX1_TPA_SEL" , 0x1180098000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"SPX0_TRN4_CTL" , 0x1180090000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"SPX1_TRN4_CTL" , 0x1180098000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"SRX0_COM_CTL" , 0x1180090000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"SRX1_COM_CTL" , 0x1180098000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"SRX0_IGN_RX_FULL" , 0x1180090000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"SRX1_IGN_RX_FULL" , 0x1180098000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"SRX0_SPI4_CAL000" , 0x1180090000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL001" , 0x1180090000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL002" , 0x1180090000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL003" , 0x1180090000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL004" , 0x1180090000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL005" , 0x1180090000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL006" , 0x1180090000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL007" , 0x1180090000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL008" , 0x1180090000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL009" , 0x1180090000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL010" , 0x1180090000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL011" , 0x1180090000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL012" , 0x1180090000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL013" , 0x1180090000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL014" , 0x1180090000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL015" , 0x1180090000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL016" , 0x1180090000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL017" , 0x1180090000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL018" , 0x1180090000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL019" , 0x1180090000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL020" , 0x11800900000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL021" , 0x11800900000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL022" , 0x11800900000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL023" , 0x11800900000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL024" , 0x11800900000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL025" , 0x11800900000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL026" , 0x11800900000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL027" , 0x11800900000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL028" , 0x11800900000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL029" , 0x11800900000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL030" , 0x11800900000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_CAL031" , 0x11800900000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL000" , 0x1180098000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL001" , 0x1180098000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL002" , 0x1180098000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL003" , 0x1180098000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL004" , 0x1180098000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL005" , 0x1180098000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL006" , 0x1180098000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL007" , 0x1180098000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL008" , 0x1180098000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL009" , 0x1180098000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL010" , 0x1180098000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL011" , 0x1180098000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL012" , 0x1180098000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL013" , 0x1180098000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL014" , 0x1180098000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL015" , 0x1180098000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL016" , 0x1180098000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL017" , 0x1180098000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL018" , 0x1180098000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL019" , 0x1180098000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL020" , 0x11800980000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL021" , 0x11800980000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL022" , 0x11800980000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL023" , 0x11800980000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL024" , 0x11800980000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL025" , 0x11800980000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL026" , 0x11800980000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL027" , 0x11800980000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL028" , 0x11800980000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL029" , 0x11800980000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL030" , 0x11800980000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX1_SPI4_CAL031" , 0x11800980000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SRX0_SPI4_STAT" , 0x1180090000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"SRX1_SPI4_STAT" , 0x1180098000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"SRX0_SW_TICK_CTL" , 0x1180090000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"SRX1_SW_TICK_CTL" , 0x1180098000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"SRX0_SW_TICK_DAT" , 0x1180090000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"SRX1_SW_TICK_DAT" , 0x1180098000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"STX0_ARB_CTL" , 0x1180090000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"STX1_ARB_CTL" , 0x1180098000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"STX0_BCKPRS_CNT" , 0x1180090000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"STX1_BCKPRS_CNT" , 0x1180098000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"STX0_COM_CTL" , 0x1180090000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"STX1_COM_CTL" , 0x1180098000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"STX0_DIP_CNT" , 0x1180090000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"STX1_DIP_CNT" , 0x1180098000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"STX0_IGN_CAL" , 0x1180090000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"STX1_IGN_CAL" , 0x1180098000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"STX0_INT_MSK" , 0x11800900006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"STX1_INT_MSK" , 0x11800980006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"STX0_INT_REG" , 0x1180090000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"STX1_INT_REG" , 0x1180098000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"STX0_INT_SYNC" , 0x11800900006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"STX1_INT_SYNC" , 0x11800980006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"STX0_MIN_BST" , 0x1180090000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"STX1_MIN_BST" , 0x1180098000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"STX0_SPI4_CAL000" , 0x1180090000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL001" , 0x1180090000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL002" , 0x1180090000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL003" , 0x1180090000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL004" , 0x1180090000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL005" , 0x1180090000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL006" , 0x1180090000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL007" , 0x1180090000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL008" , 0x1180090000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL009" , 0x1180090000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL010" , 0x1180090000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL011" , 0x1180090000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL012" , 0x1180090000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL013" , 0x1180090000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL014" , 0x1180090000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL015" , 0x1180090000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL016" , 0x1180090000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL017" , 0x1180090000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL018" , 0x1180090000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL019" , 0x1180090000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL020" , 0x11800900004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL021" , 0x11800900004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL022" , 0x11800900004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL023" , 0x11800900004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL024" , 0x11800900004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL025" , 0x11800900004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL026" , 0x11800900004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL027" , 0x11800900004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL028" , 0x11800900004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL029" , 0x11800900004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL030" , 0x11800900004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_CAL031" , 0x11800900004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL000" , 0x1180098000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL001" , 0x1180098000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL002" , 0x1180098000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL003" , 0x1180098000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL004" , 0x1180098000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL005" , 0x1180098000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL006" , 0x1180098000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL007" , 0x1180098000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL008" , 0x1180098000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL009" , 0x1180098000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL010" , 0x1180098000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL011" , 0x1180098000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL012" , 0x1180098000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL013" , 0x1180098000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL014" , 0x1180098000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL015" , 0x1180098000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL016" , 0x1180098000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL017" , 0x1180098000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL018" , 0x1180098000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL019" , 0x1180098000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL020" , 0x11800980004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL021" , 0x11800980004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL022" , 0x11800980004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL023" , 0x11800980004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL024" , 0x11800980004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL025" , 0x11800980004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL026" , 0x11800980004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL027" , 0x11800980004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL028" , 0x11800980004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL029" , 0x11800980004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL030" , 0x11800980004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX1_SPI4_CAL031" , 0x11800980004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_SPI4_DAT" , 0x1180090000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"STX1_SPI4_DAT" , 0x1180098000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"STX0_SPI4_STAT" , 0x1180090000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"STX1_SPI4_STAT" , 0x1180098000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"STX0_STAT_BYTES_HI" , 0x1180090000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"STX1_STAT_BYTES_HI" , 0x1180098000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"STX0_STAT_BYTES_LO" , 0x1180090000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {"STX1_STAT_BYTES_LO" , 0x1180098000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {"STX0_STAT_CTL" , 0x1180090000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
- {"STX1_STAT_CTL" , 0x1180098000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
- {"STX0_STAT_PKT_XMT" , 0x1180090000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
- {"STX1_STAT_PKT_XMT" , 0x1180098000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 577},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 578},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 581},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 582},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 583},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 584},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 585},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 586},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 587},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 588},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 589},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 590},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 591},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 592},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 593},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 594},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 595},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 596},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 597},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 598},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 599},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 600},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 601},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"OVRFLW" , 0, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"TXPOP" , 4, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"TXPSH" , 8, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_12_63" , 12, 52, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 0, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 4, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 8, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 1, "RAZ", 1, 1, 0, 0},
- {"INT_LOOP" , 0, 4, 2, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_LOOP" , 4, 4, 2, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 2, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 1, 3, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 3, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 4, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 5, "RO", 0, 1, 0ull, 0},
- {"PCTL" , 4, 5, 5, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 5, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 6, "R/W", 0, 1, 0ull, 0},
- {"PCTL" , 4, 4, 6, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 6, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 7, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 7, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 8, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 9, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 10, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 10, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 11, "RO", 1, 1, 0, 0},
- {"DFALOCK" , 5, 1, 11, "RO", 1, 1, 0, 0},
- {"DFALEAD" , 6, 1, 11, "RO", 1, 1, 0, 0},
- {"DFALAG" , 7, 1, 11, "RO", 1, 1, 0, 0},
- {"DFASET" , 8, 5, 11, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 11, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 12, "R/W", 0, 0, 24ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 12, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 4, 13, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 13, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 14, "R/W", 0, 0, 24ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 14, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 15, "R/W", 0, 0, 6ull, 6ull},
- {"RESERVED_5_7" , 5, 3, 15, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 5, 15, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_13_63" , 13, 51, 15, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 4, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 16, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 4, 17, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 17, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 18, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 4, 5, 18, "R/W", 0, 1, 31ull, 0},
- {"RESERVED_9_63" , 9, 55, 18, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 19, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_1_63" , 1, 63, 19, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 4, 20, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 20, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 16, 21, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 16, 22, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 24, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 24, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 24, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 24, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 24, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 24, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 24, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 24, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 24, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 24, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 24, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 24, "R/W", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 24, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 24, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 24, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 25, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 25, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 26, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 26, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 26, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 26, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 26, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 26, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 26, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 26, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 27, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 27, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 28, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 28, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 28, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 28, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 28, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 28, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 28, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 28, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 28, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 28, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 28, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 28, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 28, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 28, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 28, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 29, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 29, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 29, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 29, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 29, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 29, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 29, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 29, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 29, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 29, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 29, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 30, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 30, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 32, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 16, 33, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 33, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 34, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 34, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 16, 35, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 35, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 36, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 37, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 15, 37, "R/W", 0, 0, 32767ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 37, "RAZ", 1, 1, 0, 0},
- {"SOFT_BIST" , 0, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 38, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 39, "R/W", 0, 0, 1ull, 0ull},
- {"NPI" , 1, 1, 39, "R/W", 0, 0, 0ull, 0ull},
- {"HOST64" , 2, 1, 39, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 39, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 40, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 40, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 41, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 41, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 41, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 42, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 42, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 42, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 42, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 42, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 42, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 42, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 43, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 43, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 43, "RO", 1, 1, 0, 0},
- {"REM" , 23, 6, 43, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 43, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 4, 44, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 44, "RAZ", 0, 0, 0ull, 0ull},
- {"RDF" , 16, 4, 44, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 44, "RAZ", 0, 0, 0ull, 0ull},
- {"P1_BRF" , 0, 8, 45, "RO", 0, 0, 0ull, 0ull},
- {"P0_BRF" , 8, 8, 45, "RO", 0, 0, 0ull, 0ull},
- {"P1_BWB" , 16, 1, 45, "RO", 0, 0, 0ull, 0ull},
- {"P0_BWB" , 17, 1, 45, "RO", 0, 0, 0ull, 0ull},
- {"CRF" , 18, 1, 45, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 45, "RAZ", 0, 0, 0ull, 0ull},
- {"GFU" , 20, 1, 45, "RO", 0, 0, 0ull, 0ull},
- {"IFU" , 21, 1, 45, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 22, 1, 45, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 45, "RAZ", 0, 0, 0ull, 0ull},
- {"SARB" , 0, 1, 46, "R/W", 0, 0, 1ull, 1ull},
- {"GXOR_ENA" , 1, 1, 46, "R/W", 0, 0, 0ull, 0ull},
- {"NXOR_ENA" , 2, 1, 46, "R/W", 0, 0, 0ull, 0ull},
- {"NRPL_ENA" , 3, 1, 46, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 46, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 20, 47, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 47, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 9, 48, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 48, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 48, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_20_63" , 20, 44, 48, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 49, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 31, 49, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 49, "RAZ", 1, 1, 0, 0},
- {"CP2ECCENA" , 0, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"CP2SBE" , 1, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2DBE" , 2, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2SBINA" , 3, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"CP2DBINA" , 4, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"CP2SYN" , 5, 8, 50, "RO", 0, 0, 0ull, 0ull},
- {"DTEECCENA" , 13, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"DTESBE" , 14, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTEDBE" , 15, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTESBINA" , 16, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"DTEDBINA" , 17, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"DTESYN" , 18, 7, 50, "RO", 0, 0, 0ull, 0ull},
- {"DTEPARENA" , 25, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"DTEPERR" , 26, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTEPINA" , 27, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"CP2PARENA" , 28, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"CP2PERR" , 29, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2PINA" , 30, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"DBLOVF" , 31, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBLINA" , 32, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 50, "RAZ", 1, 1, 0, 0},
- {"ENA_P1" , 0, 1, 51, "R/W", 0, 0, 1ull, 1ull},
- {"ENA_P0" , 1, 1, 51, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 51, "RAZ", 1, 1, 0, 0},
- {"MTYPE" , 3, 1, 51, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_LAT" , 4, 2, 51, "R/W", 0, 0, 0ull, 0ull},
- {"RW_DLY" , 6, 4, 51, "R/W", 0, 0, 1ull, 1ull},
- {"WR_DLY" , 10, 4, 51, "R/W", 0, 0, 2ull, 2ull},
- {"FPRCH" , 14, 2, 51, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 16, 2, 51, "R/W", 0, 0, 0ull, 0ull},
- {"BLEN" , 18, 1, 51, "R/W", 0, 0, 0ull, 0ull},
- {"PBUNK" , 19, 3, 51, "R/W", 0, 0, 2ull, 2ull},
- {"R2R_PBUNK" , 22, 1, 51, "R/W", 0, 0, 1ull, 1ull},
- {"INIT_P1" , 23, 1, 51, "R/W", 0, 0, 0ull, 0ull},
- {"INIT_P0" , 24, 1, 51, "R/W", 0, 0, 0ull, 0ull},
- {"BUNK_INIT" , 25, 2, 51, "R/W", 0, 0, 3ull, 3ull},
- {"LPP_ENA" , 27, 1, 51, "R/W", 0, 0, 0ull, 0ull},
- {"CLKDIV" , 28, 2, 51, "R/W", 0, 0, 0ull, 0ull},
- {"RLDCK_RST" , 30, 1, 51, "R/W", 0, 0, 0ull, 0ull},
- {"RLDQCK90_RST" , 31, 1, 51, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 51, "RAZ", 1, 1, 0, 0},
- {"REF_INT" , 0, 4, 52, "R/W", 0, 0, 3ull, 3ull},
- {"TSKW" , 4, 2, 52, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 52, "RAZ", 0, 0, 0ull, 0ull},
- {"TRL" , 8, 4, 52, "R/W", 0, 0, 6ull, 6ull},
- {"TWL" , 12, 4, 52, "R/W", 0, 0, 7ull, 7ull},
- {"TRC" , 16, 4, 52, "R/W", 0, 0, 6ull, 6ull},
- {"TMRSC" , 20, 3, 52, "R/W", 0, 0, 6ull, 6ull},
- {"MRS_ENA" , 23, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"AREF_ENA" , 24, 1, 52, "R/W", 0, 0, 0ull, 0ull},
- {"REF_INTLO" , 25, 9, 52, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 52, "RAZ", 1, 1, 0, 0},
- {"FCRAM2P" , 0, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"MAXBNK" , 1, 1, 53, "R/W", 0, 0, 1ull, 1ull},
- {"UA_START" , 2, 2, 53, "R/W", 0, 0, 1ull, 1ull},
- {"REFSHORT" , 4, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"TRFC" , 5, 5, 53, "R/W", 0, 0, 9ull, 9ull},
- {"SILRST" , 10, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"DTECLKDIS" , 11, 1, 53, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 53, "RAZ", 1, 1, 0, 0},
- {"MADDR" , 0, 24, 54, "RO", 0, 0, 0ull, 0ull},
- {"BNUM" , 24, 3, 54, "RO", 0, 0, 0ull, 0ull},
- {"PNUM" , 27, 1, 54, "RO", 0, 0, 0ull, 0ull},
- {"FSRC" , 28, 2, 54, "RO", 0, 0, 0ull, 0ull},
- {"FDST" , 30, 9, 54, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 54, "RAZ", 1, 1, 0, 0},
- {"MRS" , 0, 15, 55, "R/W", 0, 0, 66ull, 66ull},
- {"RESERVED_15_15" , 15, 1, 55, "RAZ", 1, 1, 0, 0},
- {"EMRS" , 16, 15, 55, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_31_31" , 31, 1, 55, "RAZ", 1, 1, 0, 0},
- {"EMRS2" , 32, 15, 55, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 55, "RAZ", 1, 1, 0, 0},
- {"MRSDAT" , 0, 23, 56, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_23_63" , 23, 41, 56, "RAZ", 1, 1, 0, 0},
- {"IMODE" , 0, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 1, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 2, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"DTMODE" , 3, 1, 57, "R/W", 0, 0, 1ull, 1ull},
- {"DCMODE" , 4, 1, 57, "R/W", 0, 0, 0ull, 0ull},
- {"SBDLCK" , 5, 1, 57, "R/W", 0, 0, 0ull, 0ull},
- {"SBDNUM" , 6, 5, 57, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 57, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 58, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 58, "RAZ", 0, 1, 0ull, 0},
- {"NCTL" , 8, 4, 58, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 58, "RAZ", 0, 1, 0ull, 0},
- {"ENABLE" , 16, 1, 58, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 58, "RAZ", 0, 1, 0ull, 0},
- {"SBD0" , 0, 64, 59, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 60, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 61, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 62, "RO", 1, 1, 0, 0},
- {"FDR" , 0, 1, 63, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 63, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 63, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 63, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 63, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 63, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 64, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 64, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 64, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 65, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 65, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 65, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 66, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 66, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 67, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 67, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 67, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 68, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 68, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 69, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 69, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 70, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 71, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 71, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 72, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 72, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 73, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 73, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 73, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 74, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 74, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 74, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 75, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 75, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 76, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 76, "RAZ", 1, 1, 0, 0},
- {"OUT_COL" , 0, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB_OVR" , 1, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 16, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_21" , 18, 4, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 4, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 77, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 17, 78, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 78, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 79, "RO", 1, 1, 0, 0},
- {"EN" , 1, 1, 79, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 79, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 80, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 80, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 81, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 81, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 81, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 81, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_63" , 4, 60, 81, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 82, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 83, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 84, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 85, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 86, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 87, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 88, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 88, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 89, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 89, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 89, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 89, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 90, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 90, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 91, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 91, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 91, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 91, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 91, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 91, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 91, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 91, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 91, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 91, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 91, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 92, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_FREE" , 6, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"VLAN_LEN" , 7, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 92, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 93, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 93, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 94, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 94, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 95, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 95, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 96, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 97, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 98, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 98, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 99, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 99, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 100, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 100, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 100, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 100, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 101, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 102, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 102, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 103, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 103, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 104, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 104, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 105, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 105, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 106, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 106, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 107, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 108, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 108, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 109, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 109, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 110, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 110, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 111, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 111, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 112, "R/W", 1, 1, 0, 0},
- {"RESERVED_6_63" , 6, 58, 112, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 113, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 113, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 114, "R/W", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 114, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 16, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 115, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 4, 116, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 116, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 16, 117, "RO", 0, 0, 0ull, 0ull},
- {"DROP" , 16, 16, 117, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 117, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 118, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 118, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 119, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 119, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 120, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 120, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 120, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 121, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 121, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 121, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 121, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 121, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 122, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 122, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 123, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 123, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 124, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 124, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 124, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 125, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 125, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 126, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 126, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 127, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 127, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 128, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 128, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 129, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 129, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 130, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 130, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 131, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 131, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 132, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 132, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 133, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 133, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 134, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 134, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 135, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 135, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 136, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 136, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 137, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 137, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 138, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 138, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 139, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 140, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 141, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 141, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 142, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 143, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 143, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 144, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 144, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 145, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 145, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 146, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 146, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 147, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 147, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 147, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"NCB_NXA" , 1, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 148, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 148, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB_NXA" , 1, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 149, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 149, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 150, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 150, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 151, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 151, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 152, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 152, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 152, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 152, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 153, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 153, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 154, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 154, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 155, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_5_63" , 5, 59, 155, "RAZ", 1, 1, 0, 0},
- {"CONT_PKT" , 0, 1, 156, "R/W", 0, 1, 0ull, 0},
- {"TPA_CLR" , 1, 1, 156, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 156, "RAZ", 0, 0, 0ull, 0ull},
- {"DRAIN" , 0, 16, 157, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 157, "RAZ", 1, 1, 0, 0},
- {"MAX1" , 0, 8, 158, "R/W", 0, 1, 8ull, 0},
- {"MAX2" , 8, 8, 158, "R/W", 0, 1, 4ull, 0},
- {"SLICE" , 16, 7, 158, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 158, "RAZ", 1, 1, 0, 0},
- {"ROUND" , 0, 16, 159, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 159, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 6, 160, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_6_63" , 6, 58, 160, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 161, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 161, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 161, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 161, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 161, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 161, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 161, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 162, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 163, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 163, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 164, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 164, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 165, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 165, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 166, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 166, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 167, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 167, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 167, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 167, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 168, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 168, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 168, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 169, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 169, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 169, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 170, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 170, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 170, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 171, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 171, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 171, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 171, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 171, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 172, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 172, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 172, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 172, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 172, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 173, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 174, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 175, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 176, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 177, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 177, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 177, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 178, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 178, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 178, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 179, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 179, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 180, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 180, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 180, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 180, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 180, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 181, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 181, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 181, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 181, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 181, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 182, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 183, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 184, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 185, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 185, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 186, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 186, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 186, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 187, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 187, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 188, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 189, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 190, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 190, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 191, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 192, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 193, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 194, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 194, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 194, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 195, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 195, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 196, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 197, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 197, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 198, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 198, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 199, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 199, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 200, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 200, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 201, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 201, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 3, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 202, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 202, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 202, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 202, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 202, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 203, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 203, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 203, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 203, "RO", 0, 0, 36ull, 36ull},
- {"RESERVED_44_63" , 44, 20, 203, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 204, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 204, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 204, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 204, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 205, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 205, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 205, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 205, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 205, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 205, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_61_63" , 61, 3, 205, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 206, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 206, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 207, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 207, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 208, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 208, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 208, "R/W", 0, 0, 0ull, 0ull},
- {"PRB_CON" , 0, 32, 209, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 209, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 209, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 209, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 210, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 210, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 210, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 211, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 211, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 212, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 212, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 213, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 213, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 214, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 215, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 215, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 215, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 216, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 216, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 216, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 216, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 216, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 217, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 218, "RO", 0, 0, 0ull, 0ull},
- {"STIN_MSK" , 4, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 13, 218, "RO", 0, 0, 0ull, 0ull},
- {"WLB_MSK" , 19, 4, 218, "RO", 0, 0, 0ull, 0ull},
- {"DTBNK" , 23, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 218, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 9, 219, "RO", 0, 0, 0ull, 0ull},
- {"VAB_VWCF" , 9, 1, 219, "RO", 0, 0, 0ull, 0ull},
- {"LRF" , 10, 2, 219, "RO", 0, 0, 0ull, 0ull},
- {"VWDF" , 12, 4, 219, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 219, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"PICBST" , 2, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"RHDB" , 4, 4, 220, "RO", 0, 0, 0ull, 0ull},
- {"RMDB" , 8, 4, 220, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 220, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 221, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 221, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 221, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 221, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 221, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 221, "R/W", 0, 0, 0ull, 0ull},
- {"DFILL_DIS" , 14, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 221, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 3, 222, "R/W", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 4, 222, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 4, 222, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 222, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 223, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 223, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 223, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 223, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 224, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 224, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 224, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 224, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 225, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 226, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 226, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 4, 226, "RO", 0, 0, 0ull, 0ull},
- {"SET" , 18, 3, 226, "RO", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 4, 226, "RO", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 226, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 227, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 227, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 11, 228, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 11, 16, 228, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 228, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 4, 229, "R/W", 0, 0, 15ull, 15ull},
- {"STPARTDIS" , 4, 1, 229, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 229, "RAZ", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 230, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 231, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 8, 232, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK1" , 8, 8, 232, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK2" , 16, 8, 232, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK3" , 24, 8, 232, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 232, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK4" , 0, 8, 233, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK5" , 8, 8, 233, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK6" , 16, 8, 233, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK7" , 24, 8, 233, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 233, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK8" , 0, 8, 234, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK9" , 8, 8, 234, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK10" , 16, 8, 234, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK11" , 24, 8, 234, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 234, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK12" , 0, 8, 235, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK13" , 8, 8, 235, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK14" , 16, 8, 235, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK15" , 24, 8, 235, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 235, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 8, 236, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 236, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 237, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 237, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 238, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 239, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 240, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 241, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 241, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 241, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 241, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 11, 242, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 3, 242, "RO", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 242, "RO", 0, 0, 0ull, 0ull},
- {"FADRU" , 18, 1, 242, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 242, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 243, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 243, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 243, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 244, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 244, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 245, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 245, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 246, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 246, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 247, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 248, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_1024K" , 34, 1, 248, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_512K" , 35, 1, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_36" , 36, 1, 248, "RO", 0, 0, 0ull, 0ull},
- {"EMA_CTL" , 37, 2, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 248, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 249, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 249, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 249, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 249, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 10, 249, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 3, 249, "RO", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 249, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 249, "R/W", 0, 0, 0ull, 1ull},
- {"FADRU" , 28, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 249, "RAZ", 0, 0, 0ull, 0ull},
- {"RATE" , 0, 8, 250, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_63" , 8, 56, 250, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 7, 251, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_7_63" , 7, 57, 251, "RAZ", 1, 1, 0, 0},
- {"RATE" , 0, 16, 252, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 252, "RAZ", 1, 1, 0, 0},
- {"DBG_EN" , 0, 1, 253, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 253, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 254, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 254, "RAZ", 1, 1, 0, 0},
- {"POLARITY" , 0, 1, 255, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 255, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 8, 256, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 256, "RAZ", 1, 1, 0, 0},
- {"FORMAT" , 0, 4, 257, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 257, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 258, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 258, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 259, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 259, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 32, 260, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 260, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 32, 261, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 261, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 32, 262, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 262, "RAZ", 1, 1, 0, 0},
- {"PCTL_DAT" , 0, 4, 263, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_11" , 4, 8, 263, "RAZ", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 263, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 263, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_27" , 20, 8, 263, "RAZ", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 263, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 263, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 264, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 264, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 264, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 264, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 264, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"MODE128B" , 10, 1, 264, "R/W", 0, 0, 1ull, 1ull},
- {"DRESET" , 11, 1, 264, "R/W", 0, 0, 1ull, 0ull},
- {"INORDER_MRF" , 12, 1, 264, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 264, "RAZ", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 264, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 264, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_17" , 16, 2, 264, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 264, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 264, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 264, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 264, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 264, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 265, "RAZ", 0, 1, 0ull, 0},
- {"DCC_ENABLE" , 8, 1, 265, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_MODE" , 9, 1, 265, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 265, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 266, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 266, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 267, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 267, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 268, "R/W", 0, 0, 1ull, 1ull},
- {"RDQS" , 1, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 268, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 268, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 268, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 268, "R/W", 0, 0, 0ull, 0ull},
- {"SILO_HC" , 21, 1, 268, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 268, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 268, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 268, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 268, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 268, "RAZ", 0, 0, 0ull, 0ull},
- {"CLK" , 0, 4, 269, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 269, "RAZ", 0, 0, 0ull, 0ull},
- {"CMD" , 5, 4, 269, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 269, "RAZ", 0, 0, 0ull, 0ull},
- {"DQ" , 10, 4, 269, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 269, "RAZ", 0, 0, 0ull, 0ull},
- {"CS_MASK" , 0, 8, 270, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 270, "RAZ", 0, 1, 0ull, 0},
- {"ROW_LSB" , 16, 3, 270, "R/W", 0, 1, 3ull, 0},
- {"BANK8" , 19, 1, 270, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 270, "RAZ", 0, 1, 0ull, 0},
- {"MRDSYN0" , 0, 8, 271, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 271, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 271, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 271, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 271, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 272, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 272, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 272, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 272, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 272, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 273, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 273, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 274, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 274, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 275, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 275, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 275, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 275, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 275, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 275, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 275, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 275, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 275, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 275, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 275, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 275, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 275, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 276, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 276, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 276, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 276, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 276, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 276, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 276, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 276, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_31_63" , 31, 33, 276, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 277, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 277, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 278, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 278, "RAZ", 1, 1, 0, 0},
- {"EN2" , 0, 1, 279, "R/W", 0, 1, 0ull, 0},
- {"EN4" , 1, 1, 279, "R/W", 0, 1, 0ull, 0},
- {"EN6" , 2, 1, 279, "R/W", 0, 1, 0ull, 0},
- {"EN8" , 3, 1, 279, "R/W", 0, 1, 1ull, 0},
- {"EN12" , 4, 1, 279, "R/W", 0, 1, 0ull, 0},
- {"EN16" , 5, 1, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 279, "RAZ", 0, 1, 0ull, 0},
- {"CLKR" , 8, 6, 279, "R/W", 0, 1, 0ull, 0},
- {"CLKF" , 14, 12, 279, "R/W", 0, 1, 31ull, 0},
- {"RESET_N" , 26, 1, 279, "R/W", 0, 0, 0ull, 1ull},
- {"DIV_RESET" , 27, 1, 279, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 279, "RAZ", 0, 1, 0ull, 0},
- {"FBSLIP" , 0, 1, 280, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 280, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 280, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 281, "RAZ", 0, 1, 0ull, 0},
- {"NCTL" , 8, 4, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 281, "RAZ", 0, 1, 0ull, 0},
- {"ENABLE" , 16, 1, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 281, "RAZ", 0, 1, 0ull, 0},
- {"RODT_LO0" , 0, 4, 282, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_LO1" , 4, 4, 282, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_LO2" , 8, 4, 282, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_LO3" , 12, 4, 282, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI0" , 16, 4, 282, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI1" , 20, 4, 282, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI2" , 24, 4, 282, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI3" , 28, 4, 282, "R/W", 0, 0, 15ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 282, "RAZ", 1, 1, 0, 0},
- {"WODT_LO0" , 0, 4, 283, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO1" , 4, 4, 283, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO2" , 8, 4, 283, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO3" , 12, 4, 283, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI0" , 16, 4, 283, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI1" , 20, 4, 283, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI2" , 24, 4, 283, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI3" , 28, 4, 283, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 283, "RAZ", 1, 1, 0, 0},
- {"NCBI" , 0, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 2, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 284, "RAZ", 1, 1, 0, 0},
- {"ADR_ERR" , 0, 1, 285, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 285, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 285, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 286, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 286, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 286, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 287, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 287, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 287, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 288, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 288, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 288, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 288, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 288, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 289, "R/W", 1, 1, 0, 0},
- {"BASE" , 0, 16, 290, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 290, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 290, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 290, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 290, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 290, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 290, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 290, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 290, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_63" , 37, 27, 290, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 291, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 291, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 291, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 291, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 291, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 291, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 291, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 291, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 291, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 291, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 291, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 291, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 291, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 292, "R/W", 0, 0, 26ull, 26ull},
- {"RESERVED_6_7" , 6, 2, 292, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 292, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 292, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 293, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 294, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 294, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 295, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 295, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 16, 296, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 296, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 296, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 296, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 296, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 296, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 296, "RO", 1, 1, 0, 0},
- {"NOKASU" , 29, 1, 296, "RO", 1, 1, 0, 0},
- {"RESERVED_30_63" , 30, 34, 296, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 297, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 297, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 297, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 297, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 297, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 297, "RO", 1, 1, 0, 0},
- {"ZIP_CRIP" , 29, 2, 297, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 297, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 2, 298, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_2_63" , 2, 62, 298, "RAZ", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 299, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 299, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 299, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 300, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 300, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 8, 301, "R/W", 0, 1, 3ull, 0},
- {"SCLK_HI" , 8, 12, 301, "R/W", 0, 1, 100ull, 0},
- {"SCLK_LO" , 20, 4, 301, "R/W", 0, 1, 2ull, 0},
- {"OUT" , 24, 8, 301, "R/W", 0, 1, 3ull, 0},
- {"PROG_PIN" , 32, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 301, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 7, 302, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 302, "RAZ", 1, 1, 0, 0},
- {"EFUSE" , 8, 1, 302, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 302, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 302, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 302, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 302, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 302, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 303, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 14, 14, 303, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 28, 14, 303, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 303, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 304, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 304, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 2, 305, "R/W", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 305, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 306, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 306, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 306, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 306, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 306, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 306, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 306, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 306, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 306, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 306, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 306, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 306, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 306, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 307, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 307, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 307, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 307, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 307, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 307, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 307, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 307, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 307, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 307, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 307, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 307, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 308, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 308, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 308, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 309, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 309, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 309, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 310, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 310, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 311, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 311, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 312, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 312, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 313, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 313, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 313, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 313, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 313, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 313, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 313, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 314, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 314, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 315, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 315, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 315, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 315, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 315, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 315, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 315, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 316, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 316, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 316, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 316, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 317, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 317, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 317, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 318, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 318, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 318, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 318, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 318, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 318, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 318, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 318, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 318, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 319, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 319, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 319, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 319, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 319, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 319, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 319, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 320, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 320, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 320, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 320, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 320, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 320, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 320, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 320, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 320, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 321, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 321, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 322, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 322, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 323, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 323, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 323, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 323, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 324, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 324, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 325, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 325, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 326, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 326, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 327, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 327, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 327, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 327, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 328, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 328, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 329, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 330, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 330, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 331, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 331, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 332, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 332, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 333, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 333, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 334, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 334, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 334, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 334, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 334, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 334, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 335, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 335, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 336, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 336, "R/W", 0, 1, 0ull, 0},
- {"DPI_BS" , 0, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"PDF_BS" , 1, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"DOB_BS" , 2, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"NUS_BS" , 3, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"POS_BS" , 4, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"POF3_BS" , 5, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"POF2_BS" , 6, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"POF1_BS" , 7, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"POF0_BS" , 8, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"PIG_BS" , 9, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"PGF_BS" , 10, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"RDNL_BS" , 11, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"PCAD_BS" , 12, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"PCAC_BS" , 13, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"RDN_BS" , 14, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"PCN_BS" , 15, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"PCNC_BS" , 16, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"RDP_BS" , 17, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"DIF_BS" , 18, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"CSR_BS" , 19, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 337, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 338, "R/W", 0, 1, 1024ull, 0},
- {"ISIZE" , 16, 7, 338, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 338, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 339, "R/W", 0, 1, 16ull, 0},
- {"PCTL" , 5, 5, 339, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_10_63" , 10, 54, 339, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 340, "R/W", 0, 0, 0ull, 50ull},
- {"RESERVED_10_31" , 10, 22, 340, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_WORD" , 32, 5, 340, "R/W", 0, 0, 2ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 340, "RAZ", 0, 0, 0ull, 0ull},
- {"WAIT_COM" , 40, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_WDIS" , 41, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"INS0_64B" , 42, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"INS1_64B" , 43, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"INS2_64B" , 44, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"INS3_64B" , 45, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"INS0_ENB" , 46, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"INS1_ENB" , 47, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"INS2_ENB" , 48, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"INS3_ENB" , 49, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"OUT0_ENB" , 50, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"OUT1_ENB" , 51, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"OUT2_ENB" , 52, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"OUT3_ENB" , 53, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"DIS_PNIW" , 54, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"CHIP_REV" , 55, 8, 340, "RO", 1, 1, 0, 0},
- {"RESERVED_63_63" , 63, 1, 340, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 341, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 341, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 0, 14, 342, "R/W", 0, 1, 0ull, 0},
- {"LP_ENB" , 14, 1, 342, "R/W", 0, 0, 0ull, 1ull},
- {"HP_ENB" , 15, 1, 342, "R/W", 0, 0, 0ull, 1ull},
- {"O_MODE" , 16, 1, 342, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 17, 2, 342, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 19, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 20, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 21, 1, 342, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 22, 3, 342, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 25, 9, 342, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 34, 1, 342, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 35, 1, 342, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 342, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 343, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 343, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 343, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 344, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 344, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 344, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 345, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 345, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 345, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 346, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 346, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 346, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 347, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 347, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 348, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 348, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 1, 349, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 349, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 349, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 349, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 349, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 349, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 349, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 349, "R/W", 0, 1, 0ull, 0},
- {"PKT_RR" , 22, 1, 349, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 349, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_RSL" , 2, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PO0_2SML" , 3, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PO1_2SML" , 4, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PO2_2SML" , 5, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PO3_2SML" , 6, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I0_RTOUT" , 7, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I1_RTOUT" , 8, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I2_RTOUT" , 9, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I3_RTOUT" , 10, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I0_OVERF" , 11, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I1_OVERF" , 12, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I2_OVERF" , 13, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I3_OVERF" , 14, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P0_RTOUT" , 15, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P1_RTOUT" , 16, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P2_RTOUT" , 17, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P3_RTOUT" , 18, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PERR" , 19, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PERR" , 20, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PERR" , 21, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PERR" , 22, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"G0_RTOUT" , 23, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"G1_RTOUT" , 24, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"G2_RTOUT" , 25, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"G3_RTOUT" , 26, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PPERR" , 27, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PPERR" , 28, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PPERR" , 29, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PPERR" , 30, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PTOUT" , 31, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PTOUT" , 32, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PTOUT" , 33, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PTOUT" , 34, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I0_PPERR" , 35, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I1_PPERR" , 36, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I2_PPERR" , 37, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"I3_PPERR" , 38, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"WIN_RTO" , 39, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"P_DPERR" , 40, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 41, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_S_E" , 42, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_A_F" , 43, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_S_E" , 44, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_A_F" , 45, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_S_E" , 46, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_A_F" , 47, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_S_E" , 48, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_A_F" , 49, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"COM_S_E" , 50, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"COM_A_F" , 51, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_S_E" , 52, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_A_F" , 53, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"RWX_S_E" , 54, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"RDX_S_E" , 55, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_E" , 56, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_F" , 57, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_E" , 58, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_F" , 59, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_S_E" , 60, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_A_F" , 61, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_62_63" , 62, 2, 350, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_RSL" , 2, 1, 351, "RO", 0, 0, 0ull, 0ull},
- {"PO0_2SML" , 3, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO1_2SML" , 4, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO2_2SML" , 5, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO3_2SML" , 6, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_RTOUT" , 7, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_RTOUT" , 8, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_RTOUT" , 9, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_RTOUT" , 10, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_OVERF" , 11, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_OVERF" , 12, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_OVERF" , 13, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_OVERF" , 14, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_RTOUT" , 15, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_RTOUT" , 16, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_RTOUT" , 17, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_RTOUT" , 18, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PERR" , 19, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PERR" , 20, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PERR" , 21, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PERR" , 22, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"G0_RTOUT" , 23, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"G1_RTOUT" , 24, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"G2_RTOUT" , 25, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"G3_RTOUT" , 26, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PPERR" , 27, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PPERR" , 28, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PPERR" , 29, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PPERR" , 30, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PTOUT" , 31, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PTOUT" , 32, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PTOUT" , 33, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PTOUT" , 34, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_PPERR" , 35, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_PPERR" , 36, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_PPERR" , 37, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_PPERR" , 38, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_RTO" , 39, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DPERR" , 40, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 41, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_S_E" , 42, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_A_F" , 43, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_S_E" , 44, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_A_F" , 45, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_S_E" , 46, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_A_F" , 47, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_S_E" , 48, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_A_F" , 49, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_S_E" , 50, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_A_F" , 51, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_S_E" , 52, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_A_F" , 53, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"RWX_S_E" , 54, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDX_S_E" , 55, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_E" , 56, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_F" , 57, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_E" , 58, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_F" , 59, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_S_E" , 60, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_A_F" , 61, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 351, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 352, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 352, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 353, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 353, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 28, 354, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 28, 1, 354, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 29, 1, 354, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 30, 1, 354, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 31, 1, 354, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 32, 2, 354, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 34, 2, 354, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 36, 1, 354, "R/W", 0, 1, 0ull, 0},
- {"SHORTL" , 37, 1, 354, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 354, "RAZ", 1, 1, 0, 0},
- {"INT_VEC" , 0, 64, 355, "R/W1C", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 32, 356, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 356, "RAZ", 1, 1, 0, 0},
- {"ROR_SL0" , 0, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL0" , 1, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL0" , 2, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL1" , 4, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL1" , 5, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL1" , 6, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL2" , 8, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL2" , 9, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL2" , 10, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL3" , 12, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL3" , 13, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL3" , 14, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"IPTR_O0" , 16, 1, 357, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O1" , 17, 1, 357, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O2" , 18, 1, 357, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O3" , 19, 1, 357, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_23" , 20, 4, 357, "RAZ", 0, 0, 0ull, 0ull},
- {"O0_CSRM" , 24, 1, 357, "R/W", 0, 0, 0ull, 1ull},
- {"O1_CSRM" , 25, 1, 357, "R/W", 0, 0, 0ull, 1ull},
- {"O2_CSRM" , 26, 1, 357, "R/W", 0, 0, 0ull, 1ull},
- {"O3_CSRM" , 27, 1, 357, "R/W", 0, 0, 0ull, 1ull},
- {"O0_RO" , 28, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"O0_NS" , 29, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"O0_ES" , 30, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"O1_RO" , 32, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"O1_NS" , 33, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"O1_ES" , 34, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"O2_RO" , 36, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"O2_NS" , 37, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"O2_ES" , 38, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"O3_RO" , 40, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"O3_NS" , 41, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"O3_ES" , 42, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"P0_BMODE" , 44, 1, 357, "R/W", 0, 0, 0ull, 0ull},
- {"P1_BMODE" , 45, 1, 357, "R/W", 0, 0, 0ull, 0ull},
- {"P2_BMODE" , 46, 1, 357, "R/W", 0, 0, 0ull, 0ull},
- {"P3_BMODE" , 47, 1, 357, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 48, 1, 357, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 357, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 358, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 2, 358, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_63_63" , 63, 1, 358, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 359, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 3, 359, "RO", 0, 0, 0ull, 0ull},
- {"AVAIL" , 0, 32, 360, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 6, 360, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 360, "RAZ", 1, 1, 0, 0},
- {"AVAIL" , 0, 32, 361, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 5, 361, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 361, "RAZ", 1, 1, 0, 0},
- {"RD_BRST" , 0, 7, 362, "R/W", 0, 0, 17ull, 64ull},
- {"WR_BRST" , 7, 7, 362, "R/W", 0, 0, 16ull, 64ull},
- {"RESERVED_14_63" , 14, 50, 362, "RAZ", 1, 1, 0, 0},
- {"PARK_DEV" , 0, 3, 363, "R/W", 0, 1, 0ull, 0},
- {"PARK_MOD" , 3, 1, 363, "R/W", 0, 1, 0ull, 0},
- {"EN" , 4, 1, 363, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 363, "RAZ", 1, 1, 0, 0},
- {"PCI_OVR" , 8, 4, 363, "R/W", 0, 1, 0ull, 0},
- {"HOSTMODE" , 12, 1, 363, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 363, "RAZ", 1, 1, 0, 0},
- {"CMD_SIZE" , 0, 11, 364, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_11_63" , 11, 53, 364, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 365, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 365, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 365, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 365, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 365, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 365, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 365, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 365, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 365, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 365, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 365, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 365, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 365, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 366, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 366, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 366, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 366, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 366, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 366, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 366, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 366, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 366, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 367, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 367, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 367, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 367, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 367, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 367, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 367, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 368, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 368, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 368, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 368, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 368, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 368, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 368, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 368, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 368, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 368, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 368, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 368, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 368, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 4, 369, "R/W", 0, 0, 15ull, 15ull},
- {"BP_ON" , 4, 4, 369, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 369, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"NPI" , 3, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_8" , 8, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_13" , 13, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_14" , 14, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_15" , 15, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"LMC" , 17, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_21" , 21, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"ASX0" , 22, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"ASX1" , 23, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_24" , 24, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_25" , 25, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_26" , 26, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_27" , 27, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_28" , 28, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_29" , 29, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RINT_31" , 31, 1, 370, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 370, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 32, 371, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 371, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 372, "R/W", 0, 0, 0ull, 131072ull},
- {"RESERVED_32_63" , 32, 32, 372, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 373, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 373, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 373, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 373, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 373, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 374, "RO", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 374, "RO", 0, 0, 64ull, 64ull},
- {"ISAE" , 0, 1, 375, "RO", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 375, "R/W", 0, 0, 0ull, 1ull},
- {"ME" , 2, 1, 375, "R/W", 0, 0, 0ull, 1ull},
- {"SCSE" , 3, 1, 375, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 375, "R/W", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 375, "RO", 0, 0, 0ull, 0ull},
- {"PEE" , 6, 1, 375, "R/W", 0, 0, 0ull, 1ull},
- {"ADS" , 7, 1, 375, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 375, "R/W", 0, 0, 0ull, 1ull},
- {"FBBE" , 9, 1, 375, "R/W", 0, 0, 0ull, 1ull},
- {"I_DIS" , 10, 1, 375, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 375, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 375, "RO", 0, 0, 0ull, 0ull},
- {"CLE" , 20, 1, 375, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 375, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_22" , 22, 1, 375, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 375, "RO", 0, 1, 1ull, 0},
- {"MDPE" , 24, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 375, "RO", 0, 0, 1ull, 1ull},
- {"STA" , 27, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 376, "RO", 0, 0, 0ull, 0ull},
- {"CC" , 8, 24, 376, "RO", 0, 0, 733184ull, 733184ull},
- {"CLS" , 0, 8, 377, "R/W", 0, 1, 0ull, 0},
- {"LT" , 8, 8, 377, "R/W", 0, 0, 0ull, 64ull},
- {"HT" , 16, 8, 377, "RO", 0, 0, 0ull, 0ull},
- {"BCOD" , 24, 4, 377, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_29" , 28, 2, 377, "RAZ", 1, 1, 0, 0},
- {"BRB" , 30, 1, 377, "R/W", 0, 0, 0ull, 0ull},
- {"BCAP" , 31, 1, 377, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 378, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 378, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 378, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 8, 378, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 12, 20, 378, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 379, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 380, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 380, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 23, 380, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 27, 5, 380, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 381, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 382, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 382, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 382, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 28, 382, "RO", 0, 0, 0ull, 0ull},
- {"HBASEZ" , 0, 7, 383, "RO", 0, 0, 0ull, 0ull},
- {"HBASE" , 7, 25, 383, "R/W", 0, 1, 0ull, 0},
- {"CISP" , 0, 32, 384, "RO", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 385, "RO", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 385, "RO", 0, 0, 1ull, 1ull},
- {"ERBAR_EN" , 0, 1, 386, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_10" , 1, 10, 386, "RAZ", 1, 1, 0, 0},
- {"ERBARZ" , 11, 5, 386, "RO", 0, 0, 0ull, 0ull},
- {"ERBAR" , 16, 16, 386, "R/W", 0, 1, 0ull, 0},
- {"CP" , 0, 8, 387, "RO", 0, 0, 224ull, 224ull},
- {"RESERVED_8_31" , 8, 24, 387, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 388, "R/W", 0, 1, 0ull, 0},
- {"INTA" , 8, 8, 388, "RO", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 388, "RO", 0, 0, 64ull, 64ull},
- {"ML" , 24, 8, 388, "RO", 0, 0, 64ull, 64ull},
- {"MLTD" , 0, 1, 389, "R/W", 0, 0, 0ull, 1ull},
- {"TSWC" , 1, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 389, "RAZ", 1, 1, 0, 0},
- {"DPPMR" , 3, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"PBE" , 4, 12, 389, "R/W", 0, 0, 0ull, 0ull},
- {"TILT" , 16, 4, 389, "R/W", 0, 0, 0ull, 0ull},
- {"TSLTE" , 20, 3, 389, "R/W", 0, 0, 0ull, 0ull},
- {"TMAE" , 23, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"TWTAE" , 24, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEN" , 25, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEI" , 26, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"TRTAE" , 27, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"TRDRS" , 28, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"RDSATI" , 29, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"TRDARD" , 30, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRDNPR" , 31, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSCME" , 0, 32, 390, "R/W1C", 0, 1, 0ull, 0},
- {"TDSRPS" , 0, 32, 391, "R/W1C", 0, 0, 0ull, 0ull},
- {"TDOMC" , 0, 5, 392, "R/W", 0, 0, 1ull, 1ull},
- {"TIDOMC" , 5, 1, 392, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 392, "RAZ", 1, 1, 0, 0},
- {"TIBDE" , 7, 1, 392, "R/W", 0, 0, 0ull, 0ull},
- {"TIBCD" , 8, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_10" , 9, 2, 392, "RAZ", 1, 1, 0, 0},
- {"TMAPES" , 11, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMDPES" , 12, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMSE" , 13, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMEI" , 14, 1, 392, "RO", 0, 0, 0ull, 0ull},
- {"TECI" , 15, 1, 392, "RO", 0, 0, 0ull, 0ull},
- {"TMES" , 16, 8, 392, "RO", 0, 0, 0ull, 0ull},
- {"MDRRMC" , 24, 3, 392, "R/W", 0, 0, 2ull, 2ull},
- {"MDRIMC" , 27, 1, 392, "R/W", 0, 0, 0ull, 0ull},
- {"MDRE" , 28, 1, 392, "R/W", 0, 0, 0ull, 0ull},
- {"MDWE" , 29, 1, 392, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCI" , 30, 1, 392, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCM" , 31, 1, 392, "R/W", 0, 0, 1ull, 1ull},
- {"MDSP" , 0, 32, 393, "R/W1C", 0, 1, 0ull, 0},
- {"SCMRE" , 0, 32, 394, "R/W1C", 0, 1, 0ull, 0},
- {"MTTV" , 0, 8, 395, "R/W", 0, 0, 0ull, 0ull},
- {"MRV" , 8, 8, 395, "R/W", 0, 0, 0ull, 255ull},
- {"MTTA" , 16, 1, 395, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRA" , 17, 1, 395, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLUSH" , 18, 1, 395, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_19_24" , 19, 6, 395, "RAZ", 1, 1, 0, 0},
- {"MAC" , 25, 7, 395, "R/W", 0, 0, 0ull, 0ull},
- {"PXCID" , 0, 8, 396, "RO", 0, 0, 7ull, 7ull},
- {"NCP" , 8, 8, 396, "RO", 0, 0, 232ull, 232ull},
- {"DPERE" , 16, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"ROE" , 17, 1, 396, "R/W", 0, 0, 1ull, 1ull},
- {"MMBC" , 18, 2, 396, "R/W", 0, 0, 0ull, 0ull},
- {"MOST" , 20, 3, 396, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_23_31" , 23, 9, 396, "RAZ", 1, 1, 0, 0},
- {"FN" , 0, 3, 397, "RO", 0, 0, 0ull, 0ull},
- {"DN" , 3, 5, 397, "RO", 0, 0, 31ull, 31ull},
- {"BN" , 8, 8, 397, "RO", 0, 1, 17ull, 0},
- {"W64" , 16, 1, 397, "RO", 0, 0, 1ull, 1ull},
- {"M133" , 17, 1, 397, "RO", 0, 0, 1ull, 1ull},
- {"SCD" , 18, 1, 397, "R/W1C", 0, 1, 0ull, 0},
- {"USC" , 19, 1, 397, "R/W1C", 0, 1, 0ull, 0},
- {"DC" , 20, 1, 397, "RO", 0, 0, 0ull, 0ull},
- {"MMRBCD" , 21, 2, 397, "RO", 0, 0, 2ull, 2ull},
- {"MOSTD" , 23, 3, 397, "RO", 0, 0, 3ull, 3ull},
- {"MCRSD" , 26, 3, 397, "RO", 0, 0, 7ull, 7ull},
- {"SCEMR" , 29, 1, 397, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 397, "RAZ", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 398, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 398, "RO", 0, 0, 240ull, 240ull},
- {"PCIMIV" , 16, 3, 398, "RO", 0, 0, 2ull, 2ull},
- {"PMEC" , 19, 1, 398, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 398, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 398, "RO", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 398, "RO", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 398, "RO", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 398, "RO", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 398, "RO", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 399, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 399, "R/W", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 399, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 399, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 399, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 399, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEN" , 23, 1, 399, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 399, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 400, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 400, "RO", 0, 0, 0ull, 0ull},
- {"MSIEN" , 16, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 400, "RO", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 400, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 400, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 400, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 401, "RAZ", 1, 1, 0, 0},
- {"MSI31T2" , 2, 30, 401, "R/W", 0, 1, 0ull, 0},
- {"MSI" , 0, 32, 402, "R/W", 0, 1, 0ull, 0},
- {"MSIMD" , 0, 16, 403, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 403, "RAZ", 1, 1, 0, 0},
- {"PCICNT" , 0, 32, 404, "R/W", 0, 1, 0ull, 0},
- {"AP_SPEED" , 32, 2, 404, "RO", 1, 1, 0, 0},
- {"AP_PCIX" , 34, 1, 404, "RO", 1, 1, 0, 0},
- {"HM_SPEED" , 35, 2, 404, "RO", 0, 1, 0ull, 0},
- {"HM_PCIX" , 37, 1, 404, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 404, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 405, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 405, "R/W", 0, 0, 0ull, 1ull},
- {"TSR_HWM" , 4, 3, 405, "R/W", 0, 1, 1ull, 0},
- {"PMO_FPC" , 7, 3, 405, "R/W", 0, 0, 0ull, 0ull},
- {"PMO_AMOD" , 10, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"B12_BIST" , 11, 1, 405, "RO", 0, 0, 0ull, 0ull},
- {"AP_64AD" , 12, 1, 405, "RO", 0, 1, 0ull, 0},
- {"AP_PCIX" , 13, 1, 405, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_14" , 14, 1, 405, "RAZ", 0, 0, 0ull, 0ull},
- {"EN_WFILT" , 15, 1, 405, "R/W", 0, 0, 0ull, 1ull},
- {"SCM" , 16, 1, 405, "RO", 0, 1, 0ull, 0},
- {"SCMTYP" , 17, 1, 405, "RO", 0, 1, 0ull, 0},
- {"BAR2PRES" , 18, 1, 405, "R/W", 1, 1, 0, 0},
- {"ERST_N" , 19, 1, 405, "RO", 0, 0, 1ull, 1ull},
- {"BB0" , 20, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"BB1" , 21, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"BB_ES" , 22, 2, 405, "R/W", 0, 0, 0ull, 0ull},
- {"BB_CA" , 24, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"BB1_SIZ" , 25, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"BB1_HOLE" , 26, 3, 405, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 405, "RAZ", 1, 1, 0, 0},
- {"INC_VAL" , 0, 16, 406, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 406, "RAZ", 1, 1, 0, 0},
- {"DMA_CNT" , 0, 32, 407, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 408, "R/W", 0, 1, 0ull, 0},
- {"DMA_TIME" , 0, 32, 409, "R/W", 0, 1, 0ull, 0},
- {"ICNT" , 0, 32, 410, "R/W1C", 0, 0, 0ull, 0ull},
- {"ITR_WABT" , 0, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IMR_WABT" , 1, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IMR_WTTO" , 2, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"ITR_ABT" , 3, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IMR_ABT" , 4, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IMR_TTO" , 5, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IMSI_PER" , 6, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IMSI_TABT" , 7, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IMSI_MABT" , 8, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IMSC_MSG" , 9, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"ITSR_ABT" , 10, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"ISERR" , 11, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IAPERR" , 12, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IDPERR" , 13, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IRSL_INT" , 16, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IPCNT0" , 17, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IPCNT1" , 18, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IPCNT2" , 19, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IPCNT3" , 20, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IPTIME0" , 21, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IPTIME1" , 22, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IPTIME2" , 23, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IPTIME3" , 24, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IDCNT0" , 25, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IDCNT1" , 26, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IDTIME0" , 27, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"IDTIME1" , 28, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 411, "RAZ", 1, 1, 0, 0},
- {"RTR_WABT" , 0, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RMR_WABT" , 1, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RMR_WTTO" , 2, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RTR_ABT" , 3, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RMR_ABT" , 4, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RMR_TTO" , 5, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RMSI_PER" , 6, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RMSI_TABT" , 7, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RMSI_MABT" , 8, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RMSC_MSG" , 9, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RTSR_ABT" , 10, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RSERR" , 11, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RAPERR" , 12, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RDPERR" , 13, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RRSL_INT" , 16, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RPCNT0" , 17, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RPCNT1" , 18, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RPCNT2" , 19, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RPCNT3" , 20, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RPTIME0" , 21, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RPTIME1" , 22, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RPTIME2" , 23, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RPTIME3" , 24, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RDCNT0" , 25, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RDCNT1" , 26, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RDTIME0" , 27, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RDTIME1" , 28, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 412, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 412, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 413, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT2" , 19, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT3" , 20, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME2" , 23, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME3" , 24, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 413, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT2" , 19, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT3" , 20, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME2" , 23, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME3" , 24, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 414, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 6, 415, "WO", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 415, "R/W", 1, 1, 0, 0},
- {"PTR_CNT" , 0, 16, 416, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 16, 16, 416, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 0, 32, 417, "RO", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 418, "R/W", 0, 1, 0ull, 0},
- {"PKT_TIME" , 0, 32, 419, "R/W", 0, 1, 0ull, 0},
- {"PREFETCH" , 0, 3, 420, "R/W", 0, 0, 0ull, 2ull},
- {"MIN_DATA" , 3, 6, 420, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_9_31" , 9, 23, 420, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 421, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 421, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 421, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 422, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 422, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 422, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 31, 423, "R/W", 0, 0, 10000ull, 10000ull},
- {"ENB" , 31, 1, 423, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 423, "RAZ", 1, 1, 0, 0},
- {"SCM" , 0, 32, 424, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 424, "RAZ", 1, 1, 0, 0},
- {"TSR" , 0, 36, 425, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 425, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 426, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 3, 45, 426, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 426, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 426, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 427, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 428, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 428, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 428, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 428, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 429, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 430, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 431, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 431, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 431, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 431, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 431, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 18, 432, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 432, "RAZ", 1, 1, 0, 0},
- {"REFLECT" , 0, 1, 433, "R/W", 0, 0, 1ull, 1ull},
- {"INVRES" , 1, 1, 433, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 433, "RAZ", 1, 1, 0, 0},
- {"IV" , 0, 32, 434, "R/W", 0, 0, 1185899593ull, 1185899593ull},
- {"RESERVED_32_63" , 32, 32, 434, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 435, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 435, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 435, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 435, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 436, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 436, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 436, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 436, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 436, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 436, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 436, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 436, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 437, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 437, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 437, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 437, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 437, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 437, "RAZ", 0, 1, 0ull, 0},
- {"L4_MAL" , 8, 1, 437, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 437, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 437, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 437, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 437, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 437, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 437, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 437, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 437, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 437, "RAZ", 0, 0, 0ull, 0ull},
- {"PKTDRP" , 0, 1, 438, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 438, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 438, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 438, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 438, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 438, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 438, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 438, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 438, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 438, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 439, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 440, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 440, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 441, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 441, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 441, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 441, "RAZ", 1, 1, 0, 0},
- {"CRC_EN" , 12, 1, 441, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_15" , 13, 3, 441, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 441, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT" , 20, 4, 441, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 441, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 441, "RAZ", 1, 1, 0, 0},
- {"GRP_WAT" , 28, 4, 441, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 441, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 441, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 442, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 442, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 442, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 442, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 442, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 442, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 442, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 442, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 442, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 443, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 443, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 444, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 444, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 445, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 2, 445, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 445, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 445, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 445, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 445, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 445, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 445, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 445, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 446, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 446, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 447, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 448, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 448, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 449, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 449, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 450, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 450, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 451, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 451, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 452, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 452, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 453, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 453, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 454, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 454, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 455, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 455, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 456, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 456, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 457, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 457, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 458, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 458, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 459, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 459, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 460, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 460, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 461, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 461, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 462, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 462, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 463, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 463, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 464, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 464, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 464, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 465, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 465, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 465, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 466, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 466, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 467, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 467, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 468, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 468, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 468, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 468, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 469, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 469, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 469, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 469, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 469, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 470, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 470, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 470, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 470, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 471, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 471, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 471, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 471, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 471, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 471, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 471, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 471, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 0, 16, 472, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 472, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 472, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 472, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 473, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 473, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 473, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 473, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 473, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 474, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 474, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 474, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 474, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 474, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 475, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 476, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 476, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 476, "RO", 1, 0, 0, 0ull},
- {"QID_BASE" , 6, 8, 476, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 14, 4, 476, "RO", 1, 0, 0, 0ull},
- {"QID_OFF_MAX" , 18, 4, 476, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 22, 5, 476, "RO", 1, 0, 0, 0ull},
- {"QOS" , 27, 3, 476, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 30, 1, 476, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 31, 1, 476, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 32, 1, 476, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 33, 1, 476, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 34, 1, 476, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 35, 1, 476, "RO", 1, 0, 0, 0ull},
- {"UID" , 36, 3, 476, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 39, 6, 476, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 45, 16, 476, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 61, 3, 476, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 0, 3, 477, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 3, 16, 477, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 19, 16, 477, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 35, 29, 477, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 0, 11, 478, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 478, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 479, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 479, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 479, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 479, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 479, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 479, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 480, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 480, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 480, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 480, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 480, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 480, "RO", 1, 0, 0, 0ull},
- {"RESERVED_28_63" , 28, 36, 480, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 481, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 481, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 481, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 481, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 482, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 482, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 482, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 482, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 482, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 482, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 482, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 482, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 482, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 483, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 483, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 483, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 483, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 483, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 484, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 4, 484, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 484, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 484, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 484, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 6, 484, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 21, 1, 484, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 22, 3, 484, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 25, 1, 484, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 26, 1, 484, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 27, 3, 484, "RO", 1, 0, 0, 0ull},
- {"OUT_CRC" , 30, 1, 484, "RO", 1, 0, 0, 0ull},
- {"IOB" , 31, 1, 484, "RO", 1, 0, 0, 0ull},
- {"CSR" , 32, 1, 484, "RO", 1, 0, 0, 0ull},
- {"RESERVED_33_63" , 33, 31, 484, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 485, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 485, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 485, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 485, "RAZ", 1, 1, 0, 0},
- {"REFIN" , 0, 1, 486, "R/W", 0, 0, 1ull, 1ull},
- {"INVRES" , 1, 1, 486, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 486, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 32, 487, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 487, "RAZ", 1, 1, 0, 0},
- {"IV" , 0, 32, 488, "R/W", 0, 0, 1185899593ull, 1185899593ull},
- {"RESERVED_32_63" , 32, 32, 488, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 489, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 490, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 491, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 492, "RO", 0, 0, 0ull, 0ull},
- {"PARITY" , 0, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 493, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 494, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 494, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 495, "R/W", 0, 0, 0ull, 0ull},
- {"MODE1" , 3, 3, 495, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 495, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 496, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 496, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 496, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 496, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 497, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 497, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 498, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 498, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 498, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 499, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 499, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 499, "RAZ", 1, 1, 0, 0},
- {"ADR0" , 0, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"ADR1" , 1, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"PEND0" , 2, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"PEND1" , 3, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 4, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 5, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 6, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 7, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 8, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 9, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 500, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 16, 500, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 500, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 501, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 501, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 502, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 502, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 502, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 502, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 502, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 502, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 502, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 502, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 502, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 502, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 502, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 502, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 502, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 503, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 503, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 503, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 504, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 504, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 505, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 505, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 12, 506, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 506, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 507, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_10_63" , 10, 54, 507, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 508, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 508, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 509, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 509, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 509, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 509, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 509, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 509, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 509, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 509, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 509, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 509, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 510, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 510, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 510, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 510, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 510, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 11, 511, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 511, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 11, 511, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_23_23" , 23, 1, 511, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 12, 511, "RO", 0, 1, 2027ull, 0},
- {"BUF_CNT" , 36, 12, 511, "RO", 0, 1, 0ull, 0},
- {"DES_CNT" , 48, 12, 511, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 511, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 512, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 512, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 513, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 513, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 514, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 514, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 515, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 515, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 515, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 12, 516, "RO", 0, 1, 0ull, 0},
- {"DS_CNT" , 12, 12, 516, "RO", 0, 1, 0ull, 0},
- {"TC_CNT" , 24, 4, 516, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 516, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 517, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 517, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 517, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 517, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 517, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 11, 518, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 518, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 11, 518, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 518, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 518, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 518, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 518, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 519, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 519, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 520, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 520, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 520, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 521, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 522, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 522, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 522, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 522, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 522, "RAZ", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 522, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 522, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 523, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 523, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 1, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 523, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 524, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 525, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 525, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 525, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 525, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 526, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 526, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 526, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 526, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 527, "RAZ", 0, 0, 0ull, 0ull},
- {"STAT0" , 0, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"STAT1" , 1, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"STAT2" , 2, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 528, "RAZ", 0, 0, 0ull, 0ull},
- {"SRXDLCK" , 0, 1, 529, "R/W", 0, 0, 0ull, 1ull},
- {"RCVTRN" , 1, 1, 529, "R/W", 0, 0, 0ull, 1ull},
- {"DRPTRN" , 2, 1, 529, "R/W", 0, 0, 0ull, 1ull},
- {"SNDTRN" , 3, 1, 529, "R/W", 0, 0, 0ull, 1ull},
- {"STATRCV" , 4, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"STATDRV" , 5, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RUNBIST" , 6, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"CLKDLY" , 7, 5, 529, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_12_15" , 12, 4, 529, "RAZ", 0, 0, 0ull, 0ull},
- {"SEETRN" , 16, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 529, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 530, "RAZ", 0, 1, 0ull, 0},
- {"D4CLK0" , 4, 1, 530, "R/W1C", 0, 1, 0ull, 0},
- {"D4CLK1" , 5, 1, 530, "R/W1C", 0, 1, 0ull, 0},
- {"S4CLK0" , 6, 1, 530, "R/W1C", 0, 1, 0ull, 0},
- {"S4CLK1" , 7, 1, 530, "R/W1C", 0, 1, 0ull, 0},
- {"SRXTRN" , 8, 1, 530, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_9_9" , 9, 1, 530, "RAZ", 0, 1, 0ull, 0},
- {"STXCAL" , 10, 1, 530, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"DLLDIS" , 0, 1, 531, "R/W", 1, 0, 0, 0ull},
- {"DLLFRC" , 1, 1, 531, "WR0", 1, 0, 0, 0ull},
- {"OFFDLY" , 2, 6, 531, "R/W", 1, 0, 0, 0ull},
- {"BITSEL" , 8, 5, 531, "R/W", 1, 1, 0, 0},
- {"OFFSET" , 13, 5, 531, "R/W", 1, 1, 0, 0},
- {"MUX" , 18, 1, 531, "WR0", 1, 1, 0, 0},
- {"INC" , 19, 1, 531, "WR0", 1, 1, 0, 0},
- {"DEC" , 20, 1, 531, "WR0", 1, 1, 0, 0},
- {"CLRDLY" , 21, 1, 531, "WR0", 1, 1, 0, 0},
- {"RESERVED_22_23" , 22, 2, 531, "RAZ", 0, 0, 0ull, 0ull},
- {"SSTEP" , 24, 1, 531, "R/W", 1, 0, 0, 0ull},
- {"SSTEP_GO" , 25, 1, 531, "WR0", 1, 1, 0, 0},
- {"RESERVED_26_27" , 26, 2, 531, "RAZ", 0, 0, 0ull, 0ull},
- {"FALL8" , 28, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"FALLNOP" , 29, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 531, "RAZ", 0, 0, 0ull, 0ull},
- {"OFFSET" , 0, 5, 532, "RO", 0, 1, 0ull, 0},
- {"MUXSEL" , 5, 2, 532, "RO", 0, 1, 0ull, 0},
- {"UNXTERM" , 7, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
- {"TESTRES" , 8, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 532, "RAZ", 0, 0, 0ull, 0ull},
- {"SRX4CMP" , 0, 10, 533, "R/W", 0, 0, 239ull, 239ull},
- {"RESERVED_10_15" , 10, 6, 533, "RAZ", 0, 0, 0ull, 0ull},
- {"STX4PCMP" , 16, 4, 533, "R/W", 0, 1, 3ull, 0},
- {"STX4NCMP" , 20, 4, 533, "R/W", 0, 1, 12ull, 0},
- {"RESERVED_24_63" , 24, 40, 533, "RAZ", 0, 0, 0ull, 0ull},
- {"ERRCNT" , 0, 4, 534, "R/W", 0, 0, 0ull, 3ull},
- {"RESERVED_4_5" , 4, 2, 534, "RAZ", 0, 0, 0ull, 0ull},
- {"DIPPAY" , 6, 1, 534, "R/W", 0, 0, 0ull, 0ull},
- {"DIPCLS" , 7, 1, 534, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 8, 1, 534, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 534, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT" , 0, 8, 535, "RO", 0, 0, 0ull, 0ull},
- {"RSVOP" , 8, 4, 535, "RO", 0, 0, 0ull, 0ull},
- {"CALBNK" , 12, 2, 535, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_30" , 14, 17, 535, "RAZ", 0, 0, 0ull, 0ull},
- {"MUL" , 31, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 535, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 536, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 536, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 536, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 537, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_30" , 12, 19, 537, "RAZ", 0, 0, 0ull, 0ull},
- {"SPF" , 31, 1, 537, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 537, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 538, "R/W", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 538, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 538, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 538, "R/W", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 538, "R/W", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 538, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 538, "R/W", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 538, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 538, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 538, "R/W", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 538, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 538, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 539, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 539, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX" , 0, 32, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 540, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTSEL" , 0, 4, 541, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 541, "RAZ", 0, 0, 0ull, 0ull},
- {"MUX_EN" , 0, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"MACRO_EN" , 1, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"MAXDIST" , 2, 5, 542, "R/W", 0, 0, 0ull, 8ull},
- {"SET_BOOT" , 7, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"CLR_BOOT" , 8, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"JITTER" , 9, 3, 542, "R/W", 0, 0, 0ull, 1ull},
- {"TRNTEST" , 12, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 542, "RAZ", 0, 0, 0ull, 0ull},
- {"INF_EN" , 0, 1, 543, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_2" , 1, 2, 543, "RAZ", 0, 0, 0ull, 0ull},
- {"ST_EN" , 3, 1, 543, "R/W", 0, 0, 0ull, 1ull},
- {"PRTS" , 4, 4, 543, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 543, "RAZ", 0, 0, 0ull, 0ull},
- {"IGNORE" , 0, 16, 544, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 544, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT0" , 0, 4, 545, "R/W", 1, 1, 0, 0},
- {"PRT1" , 4, 4, 545, "R/W", 1, 1, 0, 0},
- {"PRT2" , 8, 4, 545, "R/W", 1, 1, 0, 0},
- {"PRT3" , 12, 4, 545, "R/W", 1, 1, 0, 0},
- {"ODDPAR" , 16, 1, 545, "R/W", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 545, "RAZ", 0, 0, 0ull, 0ull},
- {"LEN" , 0, 7, 546, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 546, "RAZ", 0, 0, 0ull, 0ull},
- {"M" , 8, 8, 546, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 546, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 4, 547, "R/W", 0, 0, 0ull, 0ull},
- {"OPC" , 4, 4, 547, "R/W", 0, 0, 0ull, 0ull},
- {"MOD" , 8, 4, 547, "R/W", 0, 0, 0ull, 0ull},
- {"SOP" , 12, 1, 547, "R/W", 0, 0, 0ull, 0ull},
- {"EOP" , 13, 1, 547, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 547, "RAZ", 0, 0, 0ull, 0ull},
- {"DAT" , 0, 64, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_2" , 0, 3, 549, "R/W", 0, 0, 0ull, 0ull},
- {"IGNTPA" , 3, 1, 549, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 549, "R/W", 0, 0, 0ull, 0ull},
- {"MINTRN" , 5, 1, 549, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 549, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 550, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 550, "RAZ", 0, 0, 0ull, 0ull},
- {"INF_EN" , 0, 1, 551, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_2" , 1, 2, 551, "RAZ", 0, 0, 0ull, 0ull},
- {"ST_EN" , 3, 1, 551, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 551, "RAZ", 0, 0, 0ull, 0ull},
- {"DIPMAX" , 0, 4, 552, "R/W", 0, 0, 0ull, 0ull},
- {"FRMMAX" , 4, 4, 552, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 552, "RAZ", 0, 0, 0ull, 0ull},
- {"IGNTPA" , 0, 16, 553, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 553, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 554, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 554, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 8, 1, 555, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 555, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 556, "RAZ", 0, 0, 0ull, 0ull},
- {"MINB" , 0, 9, 557, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 557, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT0" , 0, 4, 558, "R/W", 1, 1, 0, 0},
- {"PRT1" , 4, 4, 558, "R/W", 1, 1, 0, 0},
- {"PRT2" , 8, 4, 558, "R/W", 1, 1, 0, 0},
- {"PRT3" , 12, 4, 558, "R/W", 1, 1, 0, 0},
- {"ODDPAR" , 16, 1, 558, "R/W", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 558, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_T" , 0, 16, 559, "R/W", 0, 1, 0ull, 0},
- {"ALPHA" , 16, 16, 559, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 559, "RAZ", 0, 0, 0ull, 0ull},
- {"LEN" , 0, 7, 560, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 560, "RAZ", 0, 0, 0ull, 0ull},
- {"M" , 8, 8, 560, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 560, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 561, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 561, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 562, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 562, "RAZ", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 0, 4, 563, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 4, 1, 563, "WR0", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 563, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 564, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 564, "RAZ", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 0, 22, 565, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 565, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 565, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 565, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 565, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 565, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 566, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 566, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 566, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 567, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 567, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 567, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 567, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 567, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 568, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 568, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 568, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 568, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 569, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 569, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 569, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 569, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 569, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 570, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 570, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 570, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 570, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 571, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 572, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 572, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 572, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 572, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 573, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 573, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 574, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 574, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 574, "RAZ", 1, 1, 0, 0},
- {"TDF0" , 0, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"TDF1" , 1, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"TCF" , 2, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 575, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 576, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 576, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 576, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 576, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 577, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 577, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 577, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 578, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 578, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 578, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 578, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 578, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 579, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 579, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 580, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 580, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 581, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 581, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 582, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 582, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 582, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 582, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 582, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 582, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 582, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 582, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 582, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 582, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 582, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 582, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 583, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 583, "RAZ", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 584, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 584, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 584, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 584, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 584, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 585, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 586, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 586, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 587, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 587, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 588, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 588, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 589, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 589, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 589, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 589, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 589, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 589, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 589, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 589, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 589, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 589, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 589, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 589, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 590, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 590, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 590, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 590, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 590, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 590, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 591, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 591, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 592, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 592, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 593, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 593, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 594, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 594, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 594, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 594, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 594, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 594, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 594, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 594, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 594, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 594, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 594, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 594, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 595, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 595, "RAZ", 0, 0, 0ull, 0ull},
- {"ZIP_CTL" , 0, 4, 596, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 27, 596, "RO", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 596, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 597, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 597, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 597, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 597, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 598, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 598, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 599, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 599, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 599, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 599, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 599, "RO", 0, 0, 31744ull, 31744ull},
- {"RESERVED_48_63" , 48, 16, 599, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 14, 600, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 600, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 601, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 601, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 602, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 4, 0},
- {"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 4, 4},
- {"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 3, 8},
- {"cvmx_asx#_rld_bypass" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 11},
- {"cvmx_asx#_rld_bypass_setting", CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 13},
- {"cvmx_asx#_rld_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 3, 15},
- {"cvmx_asx#_rld_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 3, 18},
- {"cvmx_asx#_rld_nctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 21},
- {"cvmx_asx#_rld_nctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 23},
- {"cvmx_asx#_rld_pctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 25},
- {"cvmx_asx#_rld_pctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 27},
- {"cvmx_asx#_rld_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 6, 29},
- {"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 35},
- {"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 37},
- {"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 39},
- {"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 4, 41},
- {"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 45},
- {"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 47},
- {"cvmx_asx0_dbg_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 3, 49},
- {"cvmx_asx0_dbg_data_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 55, 2, 52},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 56, 2, 54},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 57, 2, 56},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 58, 2, 58},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 59, 2, 60},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 60, 15, 62},
- {"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 93, 15, 77},
- {"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 126, 15, 92},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 159, 2, 107},
- {"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 192, 2, 109},
- {"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 2, 111},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 258, 15, 113},
- {"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 274, 15, 128},
- {"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 290, 15, 143},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 306, 2, 158},
- {"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 322, 2, 160},
- {"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 338, 2, 162},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 354, 15, 164},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 387, 15, 179},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 403, 2, 194},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 404, 2, 196},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 420, 2, 198},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 436, 2, 200},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 437, 2, 202},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 438, 2, 204},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 439, 1, 206},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 455, 3, 207},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 456, 2, 210},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 457, 4, 212},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 458, 2, 216},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 459, 3, 218},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 463, 7, 221},
- {"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 479, 5, 228},
- {"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 480, 4, 233},
- {"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 481, 10, 237},
- {"cvmx_dfa_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 482, 5, 247},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 483, 2, 252},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 484, 4, 254},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 485, 3, 258},
- {"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 486, 21, 261},
- {"cvmx_dfa_memcfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 20, 282},
- {"cvmx_dfa_memcfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 488, 11, 302},
- {"cvmx_dfa_memcfg2" , CVMX_CSR_DB_TYPE_RSL, 64, 489, 8, 313},
- {"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 490, 6, 321},
- {"cvmx_dfa_memfcr" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 6, 327},
- {"cvmx_dfa_memrld" , CVMX_CSR_DB_TYPE_RSL, 64, 492, 2, 333},
- {"cvmx_dfa_ncbctl" , CVMX_CSR_DB_TYPE_RSL, 64, 493, 8, 335},
- {"cvmx_dfa_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 494, 6, 343},
- {"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 495, 1, 349},
- {"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 496, 1, 350},
- {"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 497, 1, 351},
- {"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 498, 1, 352},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 6, 353},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 500, 7, 359},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 501, 3, 366},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 508, 2, 369},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 3, 371},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 516, 2, 374},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 29, 376},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 518, 29, 405},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 2, 434},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 527, 2, 436},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 535, 3, 438},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 536, 3, 441},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 537, 2, 444},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 538, 2, 446},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 539, 8, 448},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 541, 2, 456},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 543, 3, 458},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 545, 2, 461},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 547, 5, 463},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 555, 1, 468},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 563, 1, 469},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 571, 1, 470},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 579, 1, 471},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 587, 1, 472},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 595, 1, 473},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 603, 2, 474},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 611, 4, 476},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 619, 2, 480},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 627, 11, 482},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 635, 12, 493},
- {"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 643, 2, 505},
- {"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 651, 2, 507},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 659, 2, 509},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 667, 21, 511},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 675, 21, 532},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 683, 2, 553},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 691, 2, 555},
- {"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 699, 4, 557},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 707, 2, 561},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 715, 2, 563},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 723, 2, 565},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 731, 2, 567},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 739, 2, 569},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 747, 2, 571},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 755, 2, 573},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 763, 2, 575},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 771, 2, 577},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 779, 2, 579},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 787, 4, 581},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 2, 585},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 2, 587},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 811, 2, 589},
- {"cvmx_gmx#_rx_pass_en" , CVMX_CSR_DB_TYPE_RSL, 64, 819, 2, 591},
- {"cvmx_gmx#_rx_pass_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 821, 2, 593},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 853, 3, 595},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 855, 2, 598},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 857, 2, 600},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 3, 602},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 5, 605},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 2, 610},
- {"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 883, 2, 612},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 891, 3, 614},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 899, 2, 617},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 907, 2, 619},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 915, 2, 621},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 2, 623},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 931, 2, 625},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 939, 2, 627},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 947, 2, 629},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 955, 2, 631},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 963, 2, 633},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 971, 2, 635},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 979, 2, 637},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 987, 2, 639},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 2, 641},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 2, 643},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 1011, 2, 645},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 2, 647},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 649},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 2, 651},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 1043, 2, 653},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 2, 655},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 2, 657},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 2, 659},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 3, 661},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 8, 664},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 8, 672},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 1063, 2, 680},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1065, 2, 682},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1067, 4, 684},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 1069, 2, 688},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 1071, 2, 690},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 1073, 2, 692},
- {"cvmx_gmx#_tx_spi_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1075, 3, 694},
- {"cvmx_gmx#_tx_spi_drain" , CVMX_CSR_DB_TYPE_RSL, 64, 1077, 2, 697},
- {"cvmx_gmx#_tx_spi_max" , CVMX_CSR_DB_TYPE_RSL, 64, 1079, 4, 699},
- {"cvmx_gmx#_tx_spi_round#" , CVMX_CSR_DB_TYPE_RSL, 64, 1081, 2, 703},
- {"cvmx_gmx#_tx_spi_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 2, 705},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 1147, 7, 707},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 1163, 2, 714},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 1164, 2, 716},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 1165, 2, 718},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 1166, 2, 720},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 19, 722},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 6, 741},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 3, 747},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 3, 750},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 3, 753},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 5, 756},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1173, 5, 761},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1174, 1, 766},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1175, 1, 767},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1176, 7, 768},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1177, 7, 775},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1178, 3, 782},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1179, 3, 785},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1180, 3, 788},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1181, 5, 791},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1182, 5, 796},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1183, 1, 801},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1184, 1, 802},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1185, 3, 803},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1186, 3, 806},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1187, 3, 809},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1188, 2, 812},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1189, 2, 814},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 1190, 2, 816},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 1191, 2, 818},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1192, 17, 820},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 1193, 2, 837},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1194, 1, 839},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1195, 12, 840},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1196, 11, 852},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1197, 11, 863},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1198, 2, 874},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1199, 2, 876},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1200, 2, 878},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1201, 3, 880},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1237, 2, 883},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1273, 6, 885},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1274, 5, 891},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1275, 6, 896},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1276, 7, 902},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 1277, 2, 909},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1285, 2, 911},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 1286, 3, 913},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 1287, 5, 916},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 1295, 3, 921},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 1296, 2, 924},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 1297, 2, 926},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1298, 2, 928},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1299, 4, 930},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1300, 3, 934},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1301, 5, 937},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1302, 5, 942},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1303, 7, 947},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1304, 5, 954},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1305, 8, 959},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1306, 13, 967},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1307, 8, 980},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 1308, 5, 988},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 1309, 4, 993},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1310, 2, 997},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 1311, 14, 999},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 1312, 19, 1013},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 1313, 3, 1032},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 1314, 3, 1035},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1315, 2, 1038},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1319, 17, 1040},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1320, 5, 1057},
- {"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1321, 5, 1062},
- {"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1322, 5, 1067},
- {"cvmx_l2c_spar3" , CVMX_CSR_DB_TYPE_RSL, 64, 1323, 5, 1072},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1324, 2, 1077},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 3, 1079},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1326, 2, 1082},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 2, 1084},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1328, 2, 1086},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 7, 1088},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1330, 5, 1095},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1331, 3, 1100},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1332, 3, 1103},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1333, 2, 1106},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 2, 1108},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1335, 2, 1110},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1336, 6, 1112},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1337, 14, 1118},
- {"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1338, 2, 1132},
- {"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1339, 2, 1134},
- {"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1340, 2, 1136},
- {"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1341, 2, 1138},
- {"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1342, 2, 1140},
- {"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1343, 2, 1142},
- {"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1344, 2, 1144},
- {"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1345, 2, 1146},
- {"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1346, 2, 1148},
- {"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1354, 2, 1150},
- {"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1356, 2, 1152},
- {"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1358, 2, 1154},
- {"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1360, 2, 1156},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1362, 7, 1158},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1363, 19, 1165},
- {"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1364, 4, 1184},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1365, 2, 1188},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1366, 2, 1190},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1367, 18, 1192},
- {"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1368, 6, 1210},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1369, 5, 1216},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1370, 5, 1221},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1371, 6, 1226},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1372, 2, 1232},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1373, 2, 1234},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1374, 14, 1236},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1375, 9, 1250},
- {"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 1376, 2, 1259},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1377, 2, 1261},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1378, 2, 1263},
- {"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1379, 12, 1265},
- {"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1380, 6, 1277},
- {"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1381, 6, 1283},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1382, 9, 1289},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1383, 9, 1298},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1384, 4, 1307},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1385, 3, 1311},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1386, 3, 1314},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1387, 3, 1317},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1388, 5, 1320},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1390, 1, 1325},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1391, 10, 1326},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1399, 13, 1336},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1407, 4, 1349},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1408, 1, 1353},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1412, 2, 1354},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1413, 2, 1356},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1414, 9, 1358},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1415, 8, 1367},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 1416, 2, 1375},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 1417, 1, 1377},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 1418, 3, 1378},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1419, 2, 1381},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 1420, 6, 1383},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1421, 8, 1389},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 1422, 4, 1397},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1423, 2, 1401},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1424, 2, 1403},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1425, 13, 1405},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1426, 12, 1418},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1427, 3, 1430},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1428, 3, 1433},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1429, 2, 1436},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1431, 2, 1438},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1433, 2, 1440},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1435, 7, 1442},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1437, 2, 1449},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1439, 7, 1451},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1441, 4, 1458},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1443, 8, 1462},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1445, 9, 1470},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1447, 7, 1479},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1449, 9, 1486},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1451, 2, 1495},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1453, 2, 1497},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1455, 4, 1499},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1457, 2, 1503},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1459, 2, 1505},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1461, 2, 1507},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1463, 4, 1509},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1465, 2, 1513},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1467, 2, 1515},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1469, 2, 1517},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1471, 2, 1519},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1473, 2, 1521},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1475, 2, 1523},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1477, 6, 1525},
- {"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1479, 2, 1531},
- {"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1483, 2, 1533},
- {"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1487, 21, 1535},
- {"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1488, 3, 1556},
- {"cvmx_npi_comp_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1492, 3, 1559},
- {"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1493, 21, 1562},
- {"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 1494, 2, 1583},
- {"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1495, 13, 1585},
- {"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1496, 3, 1598},
- {"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1497, 3, 1601},
- {"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1498, 3, 1604},
- {"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1499, 3, 1607},
- {"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1500, 2, 1610},
- {"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1501, 2, 1612},
- {"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1502, 10, 1614},
- {"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1503, 63, 1624},
- {"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1504, 63, 1687},
- {"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1505, 2, 1750},
- {"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1506, 2, 1752},
- {"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 1507, 10, 1754},
- {"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1511, 1, 1764},
- {"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1512, 2, 1765},
- {"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1516, 39, 1767},
- {"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1517, 3, 1806},
- {"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1521, 2, 1809},
- {"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1525, 3, 1811},
- {"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1529, 3, 1814},
- {"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1533, 3, 1817},
- {"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 1534, 7, 1820},
- {"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 1535, 2, 1827},
- {"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1536, 13, 1829},
- {"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1537, 13, 1842},
- {"cvmx_npi_port34_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1538, 13, 1855},
- {"cvmx_npi_port35_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1539, 13, 1868},
- {"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1540, 3, 1881},
- {"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 1541, 33, 1884},
- {"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1542, 2, 1917},
- {"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 1546, 2, 1919},
- {"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1547, 5, 1921},
- {"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1579, 2, 1926},
- {"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1580, 24, 1928},
- {"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1581, 2, 1952},
- {"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1582, 7, 1954},
- {"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1583, 5, 1961},
- {"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1584, 1, 1966},
- {"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1585, 5, 1967},
- {"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1586, 1, 1972},
- {"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1587, 4, 1973},
- {"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1588, 2, 1977},
- {"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1589, 1, 1979},
- {"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1590, 2, 1980},
- {"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1591, 4, 1982},
- {"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1592, 2, 1986},
- {"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1593, 4, 1988},
- {"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1594, 16, 1992},
- {"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1595, 1, 2008},
- {"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1596, 1, 2009},
- {"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1597, 18, 2010},
- {"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1598, 1, 2028},
- {"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1599, 1, 2029},
- {"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1600, 7, 2030},
- {"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1601, 7, 2037},
- {"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1602, 13, 2044},
- {"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1603, 10, 2057},
- {"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1604, 10, 2067},
- {"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1605, 7, 2077},
- {"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1606, 2, 2084},
- {"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1607, 1, 2086},
- {"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1608, 2, 2087},
- {"cvmx_pci_cnt_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1609, 6, 2089},
- {"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1610, 22, 2095},
- {"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 1611, 2, 2117},
- {"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 1615, 1, 2119},
- {"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1617, 1, 2120},
- {"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1619, 1, 2121},
- {"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 1621, 1, 2122},
- {"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 1625, 35, 2123},
- {"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1626, 35, 2158},
- {"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 1627, 35, 2193},
- {"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1628, 35, 2228},
- {"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 1629, 2, 2263},
- {"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 1630, 2, 2265},
- {"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 1634, 1, 2267},
- {"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1638, 1, 2268},
- {"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1642, 1, 2269},
- {"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1646, 3, 2270},
- {"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1647, 3, 2273},
- {"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1648, 3, 2276},
- {"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 1649, 3, 2279},
- {"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1650, 2, 2282},
- {"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1651, 2, 2284},
- {"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1652, 4, 2286},
- {"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1653, 1, 2290},
- {"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1654, 4, 2291},
- {"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1655, 1, 2295},
- {"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 1656, 2, 2296},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1657, 5, 2298},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1658, 2, 2303},
- {"cvmx_pip_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 1659, 3, 2305},
- {"cvmx_pip_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 1661, 2, 2308},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1663, 4, 2310},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1667, 8, 2314},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1668, 16, 2322},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1669, 12, 2338},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1670, 12, 2350},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1671, 2, 2362},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1672, 19, 2364},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1708, 25, 2383},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1744, 2, 2408},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1808, 2, 2410},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1816, 9, 2412},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1820, 2, 2421},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1821, 2, 2423},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1822, 2, 2425},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1858, 2, 2427},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1894, 2, 2429},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1930, 2, 2431},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1966, 2, 2433},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2002, 2, 2435},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2038, 2, 2437},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2074, 2, 2439},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2110, 2, 2441},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2146, 2, 2443},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 2, 2445},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2183, 2, 2447},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2219, 2, 2449},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 2255, 2, 2451},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 2291, 2, 2453},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2355, 2, 2455},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2356, 3, 2457},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2357, 3, 2460},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2358, 2, 2463},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2359, 2, 2465},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2360, 4, 2467},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2361, 5, 2471},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2362, 4, 2476},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2363, 8, 2480},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2364, 4, 2488},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2365, 5, 2492},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2366, 5, 2497},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2367, 1, 2502},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2368, 18, 2503},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2369, 4, 2521},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2370, 2, 2525},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2371, 6, 2527},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2372, 7, 2533},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2373, 4, 2540},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2374, 9, 2544},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2375, 5, 2553},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2376, 15, 2558},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2377, 4, 2573},
- {"cvmx_pko_reg_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 2378, 3, 2577},
- {"cvmx_pko_reg_crc_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 2380, 2, 2580},
- {"cvmx_pko_reg_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 2381, 2, 2582},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2383, 1, 2584},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2384, 1, 2585},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2385, 1, 2586},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2386, 1, 2587},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2387, 4, 2588},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2388, 5, 2592},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2389, 3, 2597},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2390, 4, 2600},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2391, 2, 2604},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 2392, 3, 2606},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2393, 3, 2609},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2394, 13, 2612},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2395, 2, 2625},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2396, 13, 2627},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2397, 3, 2640},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2398, 2, 2643},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2406, 2, 2645},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2407, 2, 2647},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2408, 2, 2649},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 2409, 2, 2651},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2410, 10, 2653},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2426, 5, 2663},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2434, 8, 2668},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2442, 2, 2676},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2443, 2, 2678},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2444, 2, 2680},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2452, 3, 2682},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2453, 4, 2685},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2469, 5, 2689},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2470, 7, 2694},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2486, 2, 2701},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2502, 3, 2703},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2503, 7, 2706},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2504, 8, 2713},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2505, 6, 2721},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2506, 2, 2727},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2507, 4, 2729},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2508, 4, 2733},
- {"cvmx_spx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2509, 2, 2737},
- {"cvmx_spx#_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2511, 4, 2739},
- {"cvmx_spx#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2513, 11, 2743},
- {"cvmx_spx#_clk_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2515, 9, 2754},
- {"cvmx_spx#_dbg_deskew_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2517, 16, 2763},
- {"cvmx_spx#_dbg_deskew_state" , CVMX_CSR_DB_TYPE_RSL, 64, 2519, 5, 2779},
- {"cvmx_spx#_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2521, 5, 2784},
- {"cvmx_spx#_err_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2523, 6, 2789},
- {"cvmx_spx#_int_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2525, 6, 2795},
- {"cvmx_spx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2527, 12, 2801},
- {"cvmx_spx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2529, 14, 2813},
- {"cvmx_spx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2531, 12, 2827},
- {"cvmx_spx#_tpa_acc" , CVMX_CSR_DB_TYPE_RSL, 64, 2533, 2, 2839},
- {"cvmx_spx#_tpa_max" , CVMX_CSR_DB_TYPE_RSL, 64, 2535, 2, 2841},
- {"cvmx_spx#_tpa_sel" , CVMX_CSR_DB_TYPE_RSL, 64, 2537, 2, 2843},
- {"cvmx_spx#_trn4_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2539, 8, 2845},
- {"cvmx_srx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2541, 5, 2853},
- {"cvmx_srx#_ign_rx_full" , CVMX_CSR_DB_TYPE_RSL, 64, 2543, 2, 2858},
- {"cvmx_srx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2545, 6, 2860},
- {"cvmx_srx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2609, 4, 2866},
- {"cvmx_srx#_sw_tick_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2611, 6, 2870},
- {"cvmx_srx#_sw_tick_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2613, 1, 2876},
- {"cvmx_stx#_arb_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2615, 5, 2877},
- {"cvmx_stx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2617, 2, 2882},
- {"cvmx_stx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2619, 4, 2884},
- {"cvmx_stx#_dip_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2621, 3, 2888},
- {"cvmx_stx#_ign_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 2623, 2, 2891},
- {"cvmx_stx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2625, 9, 2893},
- {"cvmx_stx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2627, 10, 2902},
- {"cvmx_stx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2629, 9, 2912},
- {"cvmx_stx#_min_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 2631, 2, 2921},
- {"cvmx_stx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2633, 6, 2923},
- {"cvmx_stx#_spi4_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2697, 3, 2929},
- {"cvmx_stx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2699, 4, 2932},
- {"cvmx_stx#_stat_bytes_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 2701, 2, 2936},
- {"cvmx_stx#_stat_bytes_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 2703, 2, 2938},
- {"cvmx_stx#_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2705, 3, 2940},
- {"cvmx_stx#_stat_pkt_xmt" , CVMX_CSR_DB_TYPE_RSL, 64, 2707, 2, 2943},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2709, 6, 2945},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2710, 3, 2951},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2711, 5, 2954},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2712, 4, 2959},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2713, 6, 2963},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2714, 4, 2969},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2715, 2, 2973},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2716, 4, 2975},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2717, 2, 2979},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2718, 3, 2981},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2719, 4, 2984},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2720, 12, 2988},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2721, 3, 3000},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 2722, 5, 3003},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2723, 2, 3008},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2724, 2, 3010},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2725, 18, 3012},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2726, 12, 3030},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2727, 6, 3042},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2728, 5, 3048},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2729, 1, 3053},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2730, 2, 3054},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2731, 2, 3056},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2732, 18, 3058},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2733, 12, 3076},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2734, 6, 3088},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2735, 2, 3094},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2736, 2, 3096},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2737, 18, 3098},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2738, 12, 3116},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2739, 6, 3128},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2740, 3, 3134},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2741, 5, 3137},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2742, 3, 3142},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2743, 6, 3145},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2744, 2, 3151},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2745, 2, 3153},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2746, 2, 3155},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"ASX0_INT_EN" , 0x11800b0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX1_INT_EN" , 0x11800b8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX0_INT_REG" , 0x11800b0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX1_INT_REG" , 0x11800b8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX0_PRT_LOOP" , 0x11800b0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX1_PRT_LOOP" , 0x11800b8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX0_RLD_BYPASS" , 0x11800b0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX1_RLD_BYPASS" , 0x11800b8000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX0_RLD_BYPASS_SETTING" , 0x11800b0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX1_RLD_BYPASS_SETTING" , 0x11800b8000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX0_RLD_COMP" , 0x11800b0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX1_RLD_COMP" , 0x11800b8000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX0_RLD_DATA_DRV" , 0x11800b0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX1_RLD_DATA_DRV" , 0x11800b8000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_RLD_NCTL_STRONG" , 0x11800b0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX1_RLD_NCTL_STRONG" , 0x11800b8000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX0_RLD_NCTL_WEAK" , 0x11800b0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX1_RLD_NCTL_WEAK" , 0x11800b8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_RLD_PCTL_STRONG" , 0x11800b0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX1_RLD_PCTL_STRONG" , 0x11800b8000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX0_RLD_PCTL_WEAK" , 0x11800b0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX1_RLD_PCTL_WEAK" , 0x11800b8000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX0_RLD_SETTING" , 0x11800b0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"ASX1_RLD_SETTING" , 0x11800b8000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"ASX0_RX_CLK_SET000" , 0x11800b0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX0_RX_CLK_SET001" , 0x11800b0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX0_RX_CLK_SET002" , 0x11800b0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX0_RX_CLK_SET003" , 0x11800b0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX1_RX_CLK_SET000" , 0x11800b8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX1_RX_CLK_SET001" , 0x11800b8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX1_RX_CLK_SET002" , 0x11800b8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX1_RX_CLK_SET003" , 0x11800b8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"ASX0_RX_PRT_EN" , 0x11800b0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX1_RX_PRT_EN" , 0x11800b8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"ASX0_TX_CLK_SET000" , 0x11800b0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX0_TX_CLK_SET001" , 0x11800b0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX0_TX_CLK_SET002" , 0x11800b0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX0_TX_CLK_SET003" , 0x11800b0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX1_TX_CLK_SET000" , 0x11800b8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX1_TX_CLK_SET001" , 0x11800b8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX1_TX_CLK_SET002" , 0x11800b8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX1_TX_CLK_SET003" , 0x11800b8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"ASX0_TX_COMP_BYP" , 0x11800b0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"ASX1_TX_COMP_BYP" , 0x11800b8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"ASX0_TX_HI_WATER000" , 0x11800b0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX0_TX_HI_WATER001" , 0x11800b0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX0_TX_HI_WATER002" , 0x11800b0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX0_TX_HI_WATER003" , 0x11800b0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX1_TX_HI_WATER000" , 0x11800b8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX1_TX_HI_WATER001" , 0x11800b8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX1_TX_HI_WATER002" , 0x11800b8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX1_TX_HI_WATER003" , 0x11800b8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"ASX0_TX_PRT_EN" , 0x11800b0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"ASX1_TX_PRT_EN" , 0x11800b8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"ASX0_DBG_DATA_DRV" , 0x11800b0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"ASX0_DBG_DATA_ENABLE" , 0x11800b0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT10_EN0" , 0x10700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT11_EN0" , 0x10700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT12_EN0" , 0x10700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT13_EN0" , 0x10700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT14_EN0" , 0x10700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT15_EN0" , 0x10700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT24_EN0" , 0x1070000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT25_EN0" , 0x1070000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT26_EN0" , 0x10700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT27_EN0" , 0x10700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT28_EN0" , 0x10700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT29_EN0" , 0x10700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT30_EN0" , 0x10700000003e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT31_EN0" , 0x10700000003f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT8_EN0_W1C" , 0x1070000002280ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT9_EN0_W1C" , 0x1070000002290ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT10_EN0_W1C" , 0x10700000022a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT11_EN0_W1C" , 0x10700000022b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT12_EN0_W1C" , 0x10700000022c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT13_EN0_W1C" , 0x10700000022d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT14_EN0_W1C" , 0x10700000022e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT15_EN0_W1C" , 0x10700000022f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT16_EN0_W1C" , 0x1070000002300ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT17_EN0_W1C" , 0x1070000002310ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT18_EN0_W1C" , 0x1070000002320ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT19_EN0_W1C" , 0x1070000002330ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT20_EN0_W1C" , 0x1070000002340ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT21_EN0_W1C" , 0x1070000002350ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT22_EN0_W1C" , 0x1070000002360ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT23_EN0_W1C" , 0x1070000002370ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT24_EN0_W1C" , 0x1070000002380ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT25_EN0_W1C" , 0x1070000002390ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT26_EN0_W1C" , 0x10700000023a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT27_EN0_W1C" , 0x10700000023b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT28_EN0_W1C" , 0x10700000023c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT29_EN0_W1C" , 0x10700000023d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT30_EN0_W1C" , 0x10700000023e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT31_EN0_W1C" , 0x10700000023f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT8_EN0_W1S" , 0x1070000006280ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT9_EN0_W1S" , 0x1070000006290ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT10_EN0_W1S" , 0x10700000062a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT11_EN0_W1S" , 0x10700000062b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT12_EN0_W1S" , 0x10700000062c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT13_EN0_W1S" , 0x10700000062d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT14_EN0_W1S" , 0x10700000062e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT15_EN0_W1S" , 0x10700000062f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT16_EN0_W1S" , 0x1070000006300ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT17_EN0_W1S" , 0x1070000006310ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT18_EN0_W1S" , 0x1070000006320ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT19_EN0_W1S" , 0x1070000006330ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT20_EN0_W1S" , 0x1070000006340ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT21_EN0_W1S" , 0x1070000006350ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT22_EN0_W1S" , 0x1070000006360ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT23_EN0_W1S" , 0x1070000006370ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT24_EN0_W1S" , 0x1070000006380ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT25_EN0_W1S" , 0x1070000006390ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT26_EN0_W1S" , 0x10700000063a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT27_EN0_W1S" , 0x10700000063b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT28_EN0_W1S" , 0x10700000063c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT29_EN0_W1S" , 0x10700000063d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT30_EN0_W1S" , 0x10700000063e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT31_EN0_W1S" , 0x10700000063f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT10_EN1" , 0x10700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT11_EN1" , 0x10700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT12_EN1" , 0x10700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT13_EN1" , 0x10700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT14_EN1" , 0x10700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT15_EN1" , 0x10700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT24_EN1" , 0x1070000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT25_EN1" , 0x1070000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT26_EN1" , 0x10700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT27_EN1" , 0x10700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT28_EN1" , 0x10700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT29_EN1" , 0x10700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT30_EN1" , 0x10700000003e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT31_EN1" , 0x10700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT8_EN1_W1C" , 0x1070000002288ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT9_EN1_W1C" , 0x1070000002298ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT10_EN1_W1C" , 0x10700000022a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT11_EN1_W1C" , 0x10700000022b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT12_EN1_W1C" , 0x10700000022c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT13_EN1_W1C" , 0x10700000022d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT14_EN1_W1C" , 0x10700000022e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT15_EN1_W1C" , 0x10700000022f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT16_EN1_W1C" , 0x1070000002308ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT17_EN1_W1C" , 0x1070000002318ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT18_EN1_W1C" , 0x1070000002328ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT19_EN1_W1C" , 0x1070000002338ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT20_EN1_W1C" , 0x1070000002348ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT21_EN1_W1C" , 0x1070000002358ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT22_EN1_W1C" , 0x1070000002368ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT23_EN1_W1C" , 0x1070000002378ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT24_EN1_W1C" , 0x1070000002388ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT25_EN1_W1C" , 0x1070000002398ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT26_EN1_W1C" , 0x10700000023a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT27_EN1_W1C" , 0x10700000023b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT28_EN1_W1C" , 0x10700000023c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT29_EN1_W1C" , 0x10700000023d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT30_EN1_W1C" , 0x10700000023e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT31_EN1_W1C" , 0x10700000023f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT8_EN1_W1S" , 0x1070000006288ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT9_EN1_W1S" , 0x1070000006298ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT10_EN1_W1S" , 0x10700000062a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT11_EN1_W1S" , 0x10700000062b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT12_EN1_W1S" , 0x10700000062c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT13_EN1_W1S" , 0x10700000062d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT14_EN1_W1S" , 0x10700000062e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT15_EN1_W1S" , 0x10700000062f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT16_EN1_W1S" , 0x1070000006308ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT17_EN1_W1S" , 0x1070000006318ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT18_EN1_W1S" , 0x1070000006328ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT19_EN1_W1S" , 0x1070000006338ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT20_EN1_W1S" , 0x1070000006348ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT21_EN1_W1S" , 0x1070000006358ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT22_EN1_W1S" , 0x1070000006368ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT23_EN1_W1S" , 0x1070000006378ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT24_EN1_W1S" , 0x1070000006388ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT25_EN1_W1S" , 0x1070000006398ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT26_EN1_W1S" , 0x10700000063a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT27_EN1_W1S" , 0x10700000063b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT28_EN1_W1S" , 0x10700000063c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT29_EN1_W1S" , 0x10700000063d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT30_EN1_W1S" , 0x10700000063e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT31_EN1_W1S" , 0x10700000063f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT4_EN4_0" , 0x1070000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT5_EN4_0" , 0x1070000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT6_EN4_0" , 0x1070000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT7_EN4_0" , 0x1070000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT8_EN4_0" , 0x1070000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT9_EN4_0" , 0x1070000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT10_EN4_0" , 0x1070000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT11_EN4_0" , 0x1070000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT12_EN4_0" , 0x1070000000d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT13_EN4_0" , 0x1070000000d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT14_EN4_0" , 0x1070000000d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT15_EN4_0" , 0x1070000000d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT0_EN4_0_W1C" , 0x1070000002c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT1_EN4_0_W1C" , 0x1070000002c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT2_EN4_0_W1C" , 0x1070000002ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT3_EN4_0_W1C" , 0x1070000002cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT4_EN4_0_W1C" , 0x1070000002cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT5_EN4_0_W1C" , 0x1070000002cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT6_EN4_0_W1C" , 0x1070000002ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT7_EN4_0_W1C" , 0x1070000002cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT8_EN4_0_W1C" , 0x1070000002d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT9_EN4_0_W1C" , 0x1070000002d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT10_EN4_0_W1C" , 0x1070000002d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT11_EN4_0_W1C" , 0x1070000002d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT12_EN4_0_W1C" , 0x1070000002d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT13_EN4_0_W1C" , 0x1070000002d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT14_EN4_0_W1C" , 0x1070000002d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT15_EN4_0_W1C" , 0x1070000002d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT0_EN4_0_W1S" , 0x1070000006c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT1_EN4_0_W1S" , 0x1070000006c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT2_EN4_0_W1S" , 0x1070000006ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT3_EN4_0_W1S" , 0x1070000006cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT4_EN4_0_W1S" , 0x1070000006cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT5_EN4_0_W1S" , 0x1070000006cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT6_EN4_0_W1S" , 0x1070000006ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT7_EN4_0_W1S" , 0x1070000006cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT8_EN4_0_W1S" , 0x1070000006d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT9_EN4_0_W1S" , 0x1070000006d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT10_EN4_0_W1S" , 0x1070000006d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT11_EN4_0_W1S" , 0x1070000006d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT12_EN4_0_W1S" , 0x1070000006d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT13_EN4_0_W1S" , 0x1070000006d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT14_EN4_0_W1S" , 0x1070000006d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT15_EN4_0_W1S" , 0x1070000006d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT4_EN4_1" , 0x1070000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT5_EN4_1" , 0x1070000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT6_EN4_1" , 0x1070000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT7_EN4_1" , 0x1070000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT8_EN4_1" , 0x1070000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT9_EN4_1" , 0x1070000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT10_EN4_1" , 0x1070000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT11_EN4_1" , 0x1070000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT12_EN4_1" , 0x1070000000d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT13_EN4_1" , 0x1070000000d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT14_EN4_1" , 0x1070000000d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT15_EN4_1" , 0x1070000000d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_INT0_EN4_1_W1C" , 0x1070000002c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT1_EN4_1_W1C" , 0x1070000002c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT2_EN4_1_W1C" , 0x1070000002ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT3_EN4_1_W1C" , 0x1070000002cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT4_EN4_1_W1C" , 0x1070000002cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT5_EN4_1_W1C" , 0x1070000002cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT6_EN4_1_W1C" , 0x1070000002ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT7_EN4_1_W1C" , 0x1070000002cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT8_EN4_1_W1C" , 0x1070000002d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT9_EN4_1_W1C" , 0x1070000002d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT10_EN4_1_W1C" , 0x1070000002d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT11_EN4_1_W1C" , 0x1070000002d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT12_EN4_1_W1C" , 0x1070000002d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT13_EN4_1_W1C" , 0x1070000002d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT14_EN4_1_W1C" , 0x1070000002d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT15_EN4_1_W1C" , 0x1070000002d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_INT0_EN4_1_W1S" , 0x1070000006c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT1_EN4_1_W1S" , 0x1070000006c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT2_EN4_1_W1S" , 0x1070000006ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT3_EN4_1_W1S" , 0x1070000006cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT4_EN4_1_W1S" , 0x1070000006cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT5_EN4_1_W1S" , 0x1070000006cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT6_EN4_1_W1S" , 0x1070000006ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT7_EN4_1_W1S" , 0x1070000006cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT8_EN4_1_W1S" , 0x1070000006d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT9_EN4_1_W1S" , 0x1070000006d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT10_EN4_1_W1S" , 0x1070000006d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT11_EN4_1_W1S" , 0x1070000006d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT12_EN4_1_W1S" , 0x1070000006d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT13_EN4_1_W1S" , 0x1070000006d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT14_EN4_1_W1S" , 0x1070000006d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT15_EN4_1_W1S" , 0x1070000006d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT20_SUM0" , 0x10700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT21_SUM0" , 0x10700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT22_SUM0" , 0x10700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT23_SUM0" , 0x10700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT24_SUM0" , 0x10700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT25_SUM0" , 0x10700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT26_SUM0" , 0x10700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT27_SUM0" , 0x10700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT28_SUM0" , 0x10700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT29_SUM0" , 0x10700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT30_SUM0" , 0x10700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT31_SUM0" , 0x10700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT4_SUM4" , 0x1070000000c20ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT5_SUM4" , 0x1070000000c28ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT6_SUM4" , 0x1070000000c30ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT7_SUM4" , 0x1070000000c38ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT8_SUM4" , 0x1070000000c40ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT9_SUM4" , 0x1070000000c48ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT10_SUM4" , 0x1070000000c50ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT11_SUM4" , 0x1070000000c58ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT12_SUM4" , 0x1070000000c60ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT13_SUM4" , 0x1070000000c68ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT14_SUM4" , 0x1070000000c70ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT15_SUM4" , 0x1070000000c78ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR4" , 0x10700000006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR5" , 0x10700000006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR6" , 0x10700000006b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR7" , 0x10700000006b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR8" , 0x10700000006c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR9" , 0x10700000006c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR10" , 0x10700000006d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR11" , 0x10700000006d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR12" , 0x10700000006e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR13" , 0x10700000006e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR14" , 0x10700000006f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_CLR15" , 0x10700000006f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET12" , 0x1070000000660ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET13" , 0x1070000000668ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET14" , 0x1070000000670ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_MBOX_SET15" , 0x1070000000678ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE4" , 0x10700000005a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE5" , 0x10700000005a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE6" , 0x10700000005b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE7" , 0x10700000005b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE8" , 0x10700000005c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE9" , 0x10700000005c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE10" , 0x10700000005d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE11" , 0x10700000005d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE12" , 0x10700000005e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE13" , 0x10700000005e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE14" , 0x10700000005f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_POKE15" , 0x10700000005f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 46},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 47},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 48},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG12" , 0x1070000000560ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG13" , 0x1070000000568ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG14" , 0x1070000000570ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_WDOG15" , 0x1070000000578ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"DBG_DATA" , 0x11f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
- {"DFA_BST0" , 0x11800300007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"DFA_BST1" , 0x11800300007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"DFA_CFG" , 0x1180030000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 55},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 56},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 57},
- {"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"DFA_MEMCFG0" , 0x1180030000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"DFA_MEMCFG1" , 0x1180030000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"DFA_MEMCFG2" , 0x1180030000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"DFA_MEMFCR" , 0x1180030000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"DFA_MEMRLD" , 0x1180030000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"DFA_NCBCTL" , 0x1180030000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"DFA_RODT_COMP_CTL" , 0x1180030000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX1_INF_MODE" , 0x11800100007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX000_ADR_CAM4" , 0x11800100001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX001_ADR_CAM4" , 0x11800100009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX002_ADR_CAM4" , 0x11800100011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX1_RX003_ADR_CAM4" , 0x11800100019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX000_ADR_CAM5" , 0x11800100001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX001_ADR_CAM5" , 0x11800100009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX002_ADR_CAM5" , 0x11800100011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX1_RX003_ADR_CAM5" , 0x11800100019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX003_FRM_MAX" , 0x1180008001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX000_FRM_MAX" , 0x1180010000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX001_FRM_MAX" , 0x1180010000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX002_FRM_MAX" , 0x1180010001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX1_RX003_FRM_MAX" , 0x1180010001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX003_FRM_MIN" , 0x1180008001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX000_FRM_MIN" , 0x1180010000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX001_FRM_MIN" , 0x1180010000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX002_FRM_MIN" , 0x1180010001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX1_RX003_FRM_MIN" , 0x1180010001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180010000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180010000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180010001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180010001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX003_RX_INBND" , 0x1180008001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX000_RX_INBND" , 0x1180010000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX001_RX_INBND" , 0x1180010000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX002_RX_INBND" , 0x1180010001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX1_RX003_RX_INBND" , 0x1180010001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX_PASS_EN" , 0x11800080005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_RX_PASS_EN" , 0x11800100005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_RX_PASS_MAP000" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP001" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP002" , 0x1180008000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP003" , 0x1180008000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP004" , 0x1180008000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP005" , 0x1180008000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP006" , 0x1180008000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP007" , 0x1180008000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP008" , 0x1180008000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP009" , 0x1180008000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP010" , 0x1180008000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP011" , 0x1180008000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP012" , 0x1180008000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP013" , 0x1180008000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP014" , 0x1180008000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PASS_MAP015" , 0x1180008000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP000" , 0x1180010000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP001" , 0x1180010000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP002" , 0x1180010000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP003" , 0x1180010000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP004" , 0x1180010000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP005" , 0x1180010000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP006" , 0x1180010000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP007" , 0x1180010000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP008" , 0x1180010000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP009" , 0x1180010000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP010" , 0x1180010000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP011" , 0x1180010000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP012" , 0x1180010000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP013" , 0x1180010000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP014" , 0x1180010000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX_PASS_MAP015" , 0x1180010000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_RX_PRT_INFO" , 0x11800100004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_SMAC001" , 0x1180010000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_SMAC003" , 0x1180010001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX001_APPEND" , 0x1180010000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_TX003_APPEND" , 0x1180010001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX001_BURST" , 0x1180010000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_TX003_BURST" , 0x1180010001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX001_CLK" , 0x1180008000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX003_CLK" , 0x1180008001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX000_CLK" , 0x1180010000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX001_CLK" , 0x1180010000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX002_CLK" , 0x1180010001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_TX003_CLK" , 0x1180010001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX001_CTL" , 0x1180010000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_TX003_CTL" , 0x1180010001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX001_MIN_PKT" , 0x1180010000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_TX003_MIN_PKT" , 0x1180010001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX001_PAUSE_TOGO" , 0x1180010000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_TX003_PAUSE_TOGO" , 0x1180010001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX001_PAUSE_ZERO" , 0x1180010000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_TX003_PAUSE_ZERO" , 0x1180010001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX001_SLOT" , 0x1180010000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_TX003_SLOT" , 0x1180010001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX001_SOFT_PAUSE" , 0x1180010000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_TX003_SOFT_PAUSE" , 0x1180010001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX001_STAT0" , 0x1180010000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_TX003_STAT0" , 0x1180010001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX001_STAT1" , 0x1180010000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_TX003_STAT1" , 0x1180010001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX001_STAT2" , 0x1180010000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_TX003_STAT2" , 0x1180010001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX001_STAT3" , 0x1180010000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_TX003_STAT3" , 0x1180010001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_TX000_STAT4" , 0x11800100002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_TX001_STAT4" , 0x1180010000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_TX002_STAT4" , 0x11800100012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_TX003_STAT4" , 0x1180010001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_TX000_STAT5" , 0x11800100002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_TX001_STAT5" , 0x1180010000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_TX002_STAT5" , 0x11800100012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_TX003_STAT5" , 0x1180010001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_TX000_STAT6" , 0x11800100002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_TX001_STAT6" , 0x1180010000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_TX002_STAT6" , 0x11800100012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_TX003_STAT6" , 0x1180010001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_TX000_STAT7" , 0x11800100002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_TX001_STAT7" , 0x1180010000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_TX002_STAT7" , 0x11800100012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_TX003_STAT7" , 0x1180010001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_TX000_STAT8" , 0x11800100002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_TX001_STAT8" , 0x1180010000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_TX002_STAT8" , 0x11800100012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_TX003_STAT8" , 0x1180010001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_TX000_STAT9" , 0x11800100002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_TX001_STAT9" , 0x1180010000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_TX002_STAT9" , 0x11800100012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_TX003_STAT9" , 0x1180010001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_TX001_STATS_CTL" , 0x1180010000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_TX003_STATS_CTL" , 0x1180010001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_TX001_THRESH" , 0x1180010000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_TX003_THRESH" , 0x1180010001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_TX_BP" , 0x11800100004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_TX_CORRUPT" , 0x11800100004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX_LFSR" , 0x11800100004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX1_TX_OVR_BP" , 0x11800100004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_TX_SPI_CTL" , 0x11800080004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX1_TX_SPI_CTL" , 0x11800100004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX_SPI_DRAIN" , 0x11800080004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX1_TX_SPI_DRAIN" , 0x11800100004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX_SPI_MAX" , 0x11800080004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX1_TX_SPI_MAX" , 0x11800100004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX_SPI_ROUND000" , 0x1180008000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND001" , 0x1180008000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND002" , 0x1180008000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND003" , 0x1180008000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND004" , 0x11800080006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND005" , 0x11800080006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND006" , 0x11800080006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND007" , 0x11800080006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND008" , 0x11800080006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND009" , 0x11800080006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND010" , 0x11800080006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND011" , 0x11800080006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND012" , 0x11800080006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND013" , 0x11800080006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND014" , 0x11800080006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND015" , 0x11800080006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND016" , 0x1180008000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND017" , 0x1180008000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND018" , 0x1180008000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND019" , 0x1180008000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND020" , 0x1180008000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND021" , 0x1180008000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND022" , 0x1180008000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND023" , 0x1180008000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND024" , 0x1180008000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND025" , 0x1180008000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND026" , 0x1180008000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND027" , 0x1180008000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND028" , 0x1180008000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND029" , 0x1180008000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND030" , 0x1180008000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_ROUND031" , 0x1180008000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND000" , 0x1180010000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND001" , 0x1180010000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND002" , 0x1180010000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND003" , 0x1180010000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND004" , 0x11800100006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND005" , 0x11800100006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND006" , 0x11800100006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND007" , 0x11800100006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND008" , 0x11800100006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND009" , 0x11800100006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND010" , 0x11800100006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND011" , 0x11800100006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND012" , 0x11800100006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND013" , 0x11800100006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND014" , 0x11800100006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND015" , 0x11800100006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND016" , 0x1180010000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND017" , 0x1180010000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND018" , 0x1180010000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND019" , 0x1180010000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND020" , 0x1180010000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND021" , 0x1180010000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND022" , 0x1180010000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND023" , 0x1180010000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND024" , 0x1180010000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND025" , 0x1180010000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND026" , 0x1180010000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND027" , 0x1180010000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND028" , 0x1180010000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND029" , 0x1180010000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND030" , 0x1180010000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX_SPI_ROUND031" , 0x1180010000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX_SPI_THRESH" , 0x11800080004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX1_TX_SPI_THRESH" , 0x11800100004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT4_BP_PAGE_CNT" , 0x14f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT5_BP_PAGE_CNT" , 0x14f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT6_BP_PAGE_CNT" , 0x14f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT7_BP_PAGE_CNT" , 0x14f0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT8_BP_PAGE_CNT" , 0x14f0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT9_BP_PAGE_CNT" , 0x14f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT10_BP_PAGE_CNT" , 0x14f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT11_BP_PAGE_CNT" , 0x14f0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT12_BP_PAGE_CNT" , 0x14f0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT13_BP_PAGE_CNT" , 0x14f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT14_BP_PAGE_CNT" , 0x14f0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT15_BP_PAGE_CNT" , 0x14f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT16_BP_PAGE_CNT" , 0x14f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT17_BP_PAGE_CNT" , 0x14f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT18_BP_PAGE_CNT" , 0x14f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT19_BP_PAGE_CNT" , 0x14f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT20_BP_PAGE_CNT" , 0x14f00000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT21_BP_PAGE_CNT" , 0x14f00000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT22_BP_PAGE_CNT" , 0x14f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT23_BP_PAGE_CNT" , 0x14f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT24_BP_PAGE_CNT" , 0x14f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT25_BP_PAGE_CNT" , 0x14f00000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT26_BP_PAGE_CNT" , 0x14f00000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT27_BP_PAGE_CNT" , 0x14f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT28_BP_PAGE_CNT" , 0x14f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT29_BP_PAGE_CNT" , 0x14f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT30_BP_PAGE_CNT" , 0x14f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT31_BP_PAGE_CNT" , 0x14f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR4" , 0x14f00000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR5" , 0x14f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR6" , 0x14f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR7" , 0x14f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR8" , 0x14f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR9" , 0x14f0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR10" , 0x14f0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR11" , 0x14f0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR12" , 0x14f0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR13" , 0x14f0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR14" , 0x14f0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR15" , 0x14f0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14f0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14f0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14f0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14f0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR20" , 0x14f0000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR21" , 0x14f0000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR22" , 0x14f0000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR23" , 0x14f0000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR24" , 0x14f0000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR25" , 0x14f0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR26" , 0x14f0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR27" , 0x14f0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR28" , 0x14f0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR29" , 0x14f00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR30" , 0x14f00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR31" , 0x14f00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"L2C_SPAR3" , 0x1180080000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"LED_BLINK" , 0x1180000001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"LED_CLK_PHASE" , 0x1180000001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"LED_CYLON" , 0x1180000001af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"LED_DBG" , 0x1180000001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"LED_EN" , 0x1180000001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"LED_POLARITY" , 0x1180000001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"LED_PRT" , 0x1180000001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"LED_PRT_FMT" , 0x1180000001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"LED_PRT_STATUS0" , 0x1180000001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LED_PRT_STATUS1" , 0x1180000001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LED_PRT_STATUS2" , 0x1180000001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LED_PRT_STATUS3" , 0x1180000001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LED_PRT_STATUS4" , 0x1180000001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LED_PRT_STATUS5" , 0x1180000001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LED_PRT_STATUS6" , 0x1180000001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LED_PRT_STATUS7" , 0x1180000001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"LED_UDD_CNT0" , 0x1180000001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"LED_UDD_CNT1" , 0x1180000001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"LED_UDD_DAT0" , 0x1180000001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"LED_UDD_DAT1" , 0x1180000001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"LED_UDD_DAT_CLR0" , 0x1180000001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"LED_UDD_DAT_CLR1" , 0x1180000001ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"LED_UDD_DAT_SET0" , 0x1180000001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"LED_UDD_DAT_SET1" , 0x1180000001ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"LMC0_NXM" , 0x11800880000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"LMC0_PLL_CTL" , 0x11800880000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"LMC0_PLL_STATUS" , 0x11800880000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"LMC0_RODT_COMP_CTL" , 0x11800880000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"NPI_BASE_ADDR_INPUT0" , 0x11f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"NPI_BASE_ADDR_INPUT1" , 0x11f0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"NPI_BASE_ADDR_INPUT2" , 0x11f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"NPI_BASE_ADDR_INPUT3" , 0x11f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"NPI_BASE_ADDR_OUTPUT0" , 0x11f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"NPI_BASE_ADDR_OUTPUT1" , 0x11f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"NPI_BASE_ADDR_OUTPUT2" , 0x11f00000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"NPI_BASE_ADDR_OUTPUT3" , 0x11f00000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"NPI_BIST_STATUS" , 0x11f00000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
- {"NPI_BUFF_SIZE_OUTPUT0" , 0x11f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"NPI_BUFF_SIZE_OUTPUT1" , 0x11f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"NPI_BUFF_SIZE_OUTPUT2" , 0x11f00000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"NPI_BUFF_SIZE_OUTPUT3" , 0x11f00000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"NPI_COMP_CTL" , 0x11f0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"NPI_CTL_STATUS" , 0x11f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"NPI_DBG_SELECT" , 0x11f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"NPI_DMA_CONTROL" , 0x11f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
- {"NPI_DMA_HIGHP_COUNTS" , 0x11f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 353},
- {"NPI_DMA_HIGHP_NADDR" , 0x11f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"NPI_DMA_LOWP_COUNTS" , 0x11f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 355},
- {"NPI_DMA_LOWP_NADDR" , 0x11f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
- {"NPI_HIGHP_DBELL" , 0x11f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 357},
- {"NPI_HIGHP_IBUFF_SADDR" , 0x11f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
- {"NPI_INPUT_CONTROL" , 0x11f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
- {"NPI_INT_ENB" , 0x11f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
- {"NPI_INT_SUM" , 0x11f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
- {"NPI_LOWP_DBELL" , 0x11f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
- {"NPI_LOWP_IBUFF_SADDR" , 0x11f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
- {"NPI_MEM_ACCESS_SUBID3" , 0x11f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
- {"NPI_MEM_ACCESS_SUBID4" , 0x11f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
- {"NPI_MEM_ACCESS_SUBID5" , 0x11f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
- {"NPI_MEM_ACCESS_SUBID6" , 0x11f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
- {"NPI_MSI_RCV" , 0x11f0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 365},
- {"NPI_NUM_DESC_OUTPUT0" , 0x11f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
- {"NPI_NUM_DESC_OUTPUT1" , 0x11f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
- {"NPI_NUM_DESC_OUTPUT2" , 0x11f0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
- {"NPI_NUM_DESC_OUTPUT3" , 0x11f0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
- {"NPI_OUTPUT_CONTROL" , 0x11f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
- {"NPI_P0_DBPAIR_ADDR" , 0x11f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
- {"NPI_P1_DBPAIR_ADDR" , 0x11f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
- {"NPI_P2_DBPAIR_ADDR" , 0x11f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
- {"NPI_P3_DBPAIR_ADDR" , 0x11f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
- {"NPI_P0_INSTR_ADDR" , 0x11f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
- {"NPI_P1_INSTR_ADDR" , 0x11f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
- {"NPI_P2_INSTR_ADDR" , 0x11f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
- {"NPI_P3_INSTR_ADDR" , 0x11f00000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
- {"NPI_P0_INSTR_CNTS" , 0x11f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
- {"NPI_P1_INSTR_CNTS" , 0x11f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
- {"NPI_P2_INSTR_CNTS" , 0x11f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
- {"NPI_P3_INSTR_CNTS" , 0x11f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
- {"NPI_P0_PAIR_CNTS" , 0x11f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"NPI_P1_PAIR_CNTS" , 0x11f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"NPI_P2_PAIR_CNTS" , 0x11f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"NPI_P3_PAIR_CNTS" , 0x11f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"NPI_PCI_BURST_SIZE" , 0x11f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
- {"NPI_PCI_INT_ARB_CFG" , 0x11f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"NPI_PCI_READ_CMD" , 0x11f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
- {"NPI_PORT32_INSTR_HDR" , 0x11f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"NPI_PORT33_INSTR_HDR" , 0x11f0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"NPI_PORT34_INSTR_HDR" , 0x11f0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"NPI_PORT35_INSTR_HDR" , 0x11f0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"NPI_PORT_BP_CONTROL" , 0x11f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"NPI_RSL_INT_BLOCKS" , 0x11f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"NPI_SIZE_INPUT0" , 0x11f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"NPI_SIZE_INPUT1" , 0x11f0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"NPI_SIZE_INPUT2" , 0x11f0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"NPI_SIZE_INPUT3" , 0x11f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"NPI_WIN_READ_TO" , 0x11f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCI_BAR1_INDEX0" , 0x11f0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX1" , 0x11f0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX2" , 0x11f0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX3" , 0x11f000000110cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX4" , 0x11f0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX5" , 0x11f0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX6" , 0x11f0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX7" , 0x11f000000111cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX8" , 0x11f0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX9" , 0x11f0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX10" , 0x11f0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX11" , 0x11f000000112cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX12" , 0x11f0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX13" , 0x11f0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX14" , 0x11f0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX15" , 0x11f000000113cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX16" , 0x11f0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX17" , 0x11f0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX18" , 0x11f0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX19" , 0x11f000000114cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX20" , 0x11f0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX21" , 0x11f0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX22" , 0x11f0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX23" , 0x11f000000115cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX24" , 0x11f0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX25" , 0x11f0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX26" , 0x11f0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX27" , 0x11f000000116cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX28" , 0x11f0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX29" , 0x11f0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX30" , 0x11f0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_BAR1_INDEX31" , 0x11f000000117cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
- {"PCI_CFG00" , 0x11f0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 384},
- {"PCI_CFG01" , 0x11f0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 385},
- {"PCI_CFG02" , 0x11f0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 386},
- {"PCI_CFG03" , 0x11f000000180cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 387},
- {"PCI_CFG04" , 0x11f0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 388},
- {"PCI_CFG05" , 0x11f0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 389},
- {"PCI_CFG06" , 0x11f0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 390},
- {"PCI_CFG07" , 0x11f000000181cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 391},
- {"PCI_CFG08" , 0x11f0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 392},
- {"PCI_CFG09" , 0x11f0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 393},
- {"PCI_CFG10" , 0x11f0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 394},
- {"PCI_CFG11" , 0x11f000000182cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 395},
- {"PCI_CFG12" , 0x11f0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 396},
- {"PCI_CFG13" , 0x11f0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 397},
- {"PCI_CFG15" , 0x11f000000183cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 398},
- {"PCI_CFG16" , 0x11f0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 399},
- {"PCI_CFG17" , 0x11f0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 400},
- {"PCI_CFG18" , 0x11f0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 401},
- {"PCI_CFG19" , 0x11f000000184cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 402},
- {"PCI_CFG20" , 0x11f0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 403},
- {"PCI_CFG21" , 0x11f0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 404},
- {"PCI_CFG22" , 0x11f0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 405},
- {"PCI_CFG56" , 0x11f00000018e0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 406},
- {"PCI_CFG57" , 0x11f00000018e4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 407},
- {"PCI_CFG58" , 0x11f00000018e8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 408},
- {"PCI_CFG59" , 0x11f00000018ecull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 409},
- {"PCI_CFG60" , 0x11f00000018f0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 410},
- {"PCI_CFG61" , 0x11f00000018f4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 411},
- {"PCI_CFG62" , 0x11f00000018f8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 412},
- {"PCI_CFG63" , 0x11f00000018fcull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 413},
- {"PCI_CNT_REG" , 0x11f00000011b8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 414},
- {"PCI_CTL_STATUS_2" , 0x11f000000118cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 415},
- {"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
- {"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
- {"PCI_DBELL2" , 0x90ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
- {"PCI_DBELL3" , 0x98ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
- {"PCI_DMA_CNT0" , 0xa0ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
- {"PCI_DMA_CNT1" , 0xa8ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
- {"PCI_DMA_INT_LEV0" , 0xa4ull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
- {"PCI_DMA_INT_LEV1" , 0xacull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
- {"PCI_DMA_TIME0" , 0xb0ull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
- {"PCI_DMA_TIME1" , 0xb4ull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
- {"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 420},
- {"PCI_INSTR_COUNT1" , 0x8cull, CVMX_CSR_DB_TYPE_PCI, 32, 420},
- {"PCI_INSTR_COUNT2" , 0x94ull, CVMX_CSR_DB_TYPE_PCI, 32, 420},
- {"PCI_INSTR_COUNT3" , 0x9cull, CVMX_CSR_DB_TYPE_PCI, 32, 420},
- {"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 421},
- {"PCI_INT_ENB2" , 0x11f00000011a0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 422},
- {"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 423},
- {"PCI_INT_SUM2" , 0x11f0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 424},
- {"PCI_MSI_RCV" , 0xf0ull, CVMX_CSR_DB_TYPE_PCI, 32, 425},
- {"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 426},
- {"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 426},
- {"PCI_PKT_CREDITS2" , 0x64ull, CVMX_CSR_DB_TYPE_PCI, 32, 426},
- {"PCI_PKT_CREDITS3" , 0x74ull, CVMX_CSR_DB_TYPE_PCI, 32, 426},
- {"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 427},
- {"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 427},
- {"PCI_PKTS_SENT2" , 0x60ull, CVMX_CSR_DB_TYPE_PCI, 32, 427},
- {"PCI_PKTS_SENT3" , 0x70ull, CVMX_CSR_DB_TYPE_PCI, 32, 427},
- {"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 428},
- {"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 428},
- {"PCI_PKTS_SENT_INT_LEV2" , 0x68ull, CVMX_CSR_DB_TYPE_PCI, 32, 428},
- {"PCI_PKTS_SENT_INT_LEV3" , 0x78ull, CVMX_CSR_DB_TYPE_PCI, 32, 428},
- {"PCI_PKTS_SENT_TIME0" , 0x4cull, CVMX_CSR_DB_TYPE_PCI, 32, 429},
- {"PCI_PKTS_SENT_TIME1" , 0x5cull, CVMX_CSR_DB_TYPE_PCI, 32, 429},
- {"PCI_PKTS_SENT_TIME2" , 0x6cull, CVMX_CSR_DB_TYPE_PCI, 32, 429},
- {"PCI_PKTS_SENT_TIME3" , 0x7cull, CVMX_CSR_DB_TYPE_PCI, 32, 429},
- {"PCI_READ_CMD_6" , 0x11f0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 430},
- {"PCI_READ_CMD_C" , 0x11f0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 431},
- {"PCI_READ_CMD_E" , 0x11f0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 432},
- {"PCI_READ_TIMEOUT" , 0x11f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 433},
- {"PCI_SCM_REG" , 0x11f00000011a8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 434},
- {"PCI_TSR_REG" , 0x11f00000011b0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 435},
- {"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 436},
- {"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 437},
- {"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 438},
- {"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 439},
- {"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 440},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PIP_CRC_CTL0" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_CRC_CTL1" , 0x11800a0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PIP_CRC_IV0" , 0x11800a0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_CRC_IV1" , 0x11800a0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG4" , 0x11800a0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG5" , 0x11800a0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG6" , 0x11800a0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG7" , 0x11800a0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG8" , 0x11800a0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG9" , 0x11800a0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG10" , 0x11800a0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG11" , 0x11800a0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG12" , 0x11800a0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG13" , 0x11800a0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG14" , 0x11800a0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG15" , 0x11800a0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG16" , 0x11800a0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG17" , 0x11800a0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG18" , 0x11800a0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG19" , 0x11800a0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG20" , 0x11800a00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG21" , 0x11800a00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG22" , 0x11800a00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG23" , 0x11800a00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG24" , 0x11800a00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG25" , 0x11800a00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG26" , 0x11800a00002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG27" , 0x11800a00002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG28" , 0x11800a00002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG29" , 0x11800a00002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG30" , 0x11800a00002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG31" , 0x11800a00002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG4" , 0x11800a0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG5" , 0x11800a0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG6" , 0x11800a0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG7" , 0x11800a0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG8" , 0x11800a0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG9" , 0x11800a0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG10" , 0x11800a0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG11" , 0x11800a0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG12" , 0x11800a0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG13" , 0x11800a0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG14" , 0x11800a0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG15" , 0x11800a0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG16" , 0x11800a0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG17" , 0x11800a0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG18" , 0x11800a0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG19" , 0x11800a0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG20" , 0x11800a00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG21" , 0x11800a00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG22" , 0x11800a00004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG23" , 0x11800a00004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG24" , 0x11800a00004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG25" , 0x11800a00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG26" , 0x11800a00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG27" , 0x11800a00004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG28" , 0x11800a00004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG29" , 0x11800a00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG30" , 0x11800a00004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG31" , 0x11800a00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT4" , 0x11800a0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT5" , 0x11800a0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT6" , 0x11800a00009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT7" , 0x11800a0000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT8" , 0x11800a0000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT9" , 0x11800a0000ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT10" , 0x11800a0000b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT11" , 0x11800a0000b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT12" , 0x11800a0000bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT13" , 0x11800a0000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT14" , 0x11800a0000c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT15" , 0x11800a0000cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT16" , 0x11800a0000d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT17" , 0x11800a0000d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT18" , 0x11800a0000da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT19" , 0x11800a0000df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT20" , 0x11800a0000e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT21" , 0x11800a0000e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT22" , 0x11800a0000ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT23" , 0x11800a0000f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT24" , 0x11800a0000f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT25" , 0x11800a0000fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT26" , 0x11800a0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT27" , 0x11800a0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT28" , 0x11800a00010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT29" , 0x11800a0001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT30" , 0x11800a0001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT31" , 0x11800a00011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT4" , 0x11800a0000948ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT5" , 0x11800a0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT6" , 0x11800a00009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT7" , 0x11800a0000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT8" , 0x11800a0000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT9" , 0x11800a0000ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT10" , 0x11800a0000b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT11" , 0x11800a0000b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT12" , 0x11800a0000bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT13" , 0x11800a0000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT14" , 0x11800a0000c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT15" , 0x11800a0000cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT16" , 0x11800a0000d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT17" , 0x11800a0000d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT18" , 0x11800a0000da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT19" , 0x11800a0000df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT20" , 0x11800a0000e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT21" , 0x11800a0000e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT22" , 0x11800a0000ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT23" , 0x11800a0000f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT24" , 0x11800a0000f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT25" , 0x11800a0000fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT26" , 0x11800a0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT27" , 0x11800a0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT28" , 0x11800a00010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT29" , 0x11800a0001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT30" , 0x11800a0001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT31" , 0x11800a00011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT4" , 0x11800a0000950ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT5" , 0x11800a00009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT6" , 0x11800a00009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT7" , 0x11800a0000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT8" , 0x11800a0000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT9" , 0x11800a0000ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT10" , 0x11800a0000b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT11" , 0x11800a0000b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT12" , 0x11800a0000bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT13" , 0x11800a0000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT14" , 0x11800a0000c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT15" , 0x11800a0000cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT16" , 0x11800a0000d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT17" , 0x11800a0000d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT18" , 0x11800a0000db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT19" , 0x11800a0000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT20" , 0x11800a0000e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT21" , 0x11800a0000ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT22" , 0x11800a0000ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT23" , 0x11800a0000f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT24" , 0x11800a0000f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT25" , 0x11800a0000fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT26" , 0x11800a0001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT27" , 0x11800a0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT28" , 0x11800a00010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT29" , 0x11800a0001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT30" , 0x11800a0001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT31" , 0x11800a00011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT4" , 0x11800a0000958ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT5" , 0x11800a00009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT6" , 0x11800a00009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT7" , 0x11800a0000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT8" , 0x11800a0000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT9" , 0x11800a0000ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT10" , 0x11800a0000b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT11" , 0x11800a0000b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT12" , 0x11800a0000bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT13" , 0x11800a0000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT14" , 0x11800a0000c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT15" , 0x11800a0000cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT16" , 0x11800a0000d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT17" , 0x11800a0000d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT18" , 0x11800a0000db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT19" , 0x11800a0000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT20" , 0x11800a0000e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT21" , 0x11800a0000ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT22" , 0x11800a0000ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT23" , 0x11800a0000f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT24" , 0x11800a0000f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT25" , 0x11800a0000fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT26" , 0x11800a0001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT27" , 0x11800a0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT28" , 0x11800a00010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT29" , 0x11800a0001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT30" , 0x11800a0001178ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT31" , 0x11800a00011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT4" , 0x11800a0000960ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT5" , 0x11800a00009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT6" , 0x11800a0000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT7" , 0x11800a0000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT8" , 0x11800a0000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT9" , 0x11800a0000af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT10" , 0x11800a0000b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT11" , 0x11800a0000b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT12" , 0x11800a0000be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT13" , 0x11800a0000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT14" , 0x11800a0000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT15" , 0x11800a0000cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT16" , 0x11800a0000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT17" , 0x11800a0000d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT18" , 0x11800a0000dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT19" , 0x11800a0000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT20" , 0x11800a0000e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT21" , 0x11800a0000eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT22" , 0x11800a0000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT23" , 0x11800a0000f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT24" , 0x11800a0000fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT25" , 0x11800a0000ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT26" , 0x11800a0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT27" , 0x11800a0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT28" , 0x11800a00010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT29" , 0x11800a0001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT30" , 0x11800a0001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT31" , 0x11800a00011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT4" , 0x11800a0000968ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT5" , 0x11800a00009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT6" , 0x11800a0000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT7" , 0x11800a0000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT8" , 0x11800a0000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT9" , 0x11800a0000af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT10" , 0x11800a0000b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT11" , 0x11800a0000b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT12" , 0x11800a0000be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT13" , 0x11800a0000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT14" , 0x11800a0000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT15" , 0x11800a0000cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT16" , 0x11800a0000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT17" , 0x11800a0000d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT18" , 0x11800a0000dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT19" , 0x11800a0000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT20" , 0x11800a0000e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT21" , 0x11800a0000eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT22" , 0x11800a0000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT23" , 0x11800a0000f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT24" , 0x11800a0000fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT25" , 0x11800a0000ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT26" , 0x11800a0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT27" , 0x11800a0001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT28" , 0x11800a00010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT29" , 0x11800a0001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT30" , 0x11800a0001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT31" , 0x11800a00011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT4" , 0x11800a0000970ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT5" , 0x11800a00009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT6" , 0x11800a0000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT7" , 0x11800a0000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT8" , 0x11800a0000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT9" , 0x11800a0000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT10" , 0x11800a0000b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT11" , 0x11800a0000ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT12" , 0x11800a0000bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT13" , 0x11800a0000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT14" , 0x11800a0000c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT15" , 0x11800a0000ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT16" , 0x11800a0000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT17" , 0x11800a0000d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT18" , 0x11800a0000dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT19" , 0x11800a0000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT20" , 0x11800a0000e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT21" , 0x11800a0000ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT22" , 0x11800a0000f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT23" , 0x11800a0000f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT24" , 0x11800a0000fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT25" , 0x11800a0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT26" , 0x11800a0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT27" , 0x11800a00010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT28" , 0x11800a00010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT29" , 0x11800a0001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT30" , 0x11800a0001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT31" , 0x11800a00011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT4" , 0x11800a0000978ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT5" , 0x11800a00009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT6" , 0x11800a0000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT7" , 0x11800a0000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT8" , 0x11800a0000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT9" , 0x11800a0000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT10" , 0x11800a0000b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT11" , 0x11800a0000ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT12" , 0x11800a0000bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT13" , 0x11800a0000c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT14" , 0x11800a0000c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT15" , 0x11800a0000ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT16" , 0x11800a0000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT17" , 0x11800a0000d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT18" , 0x11800a0000dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT19" , 0x11800a0000e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT20" , 0x11800a0000e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT21" , 0x11800a0000ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT22" , 0x11800a0000f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT23" , 0x11800a0000f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT24" , 0x11800a0000fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT25" , 0x11800a0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT26" , 0x11800a0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT27" , 0x11800a00010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT28" , 0x11800a00010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT29" , 0x11800a0001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT30" , 0x11800a0001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT31" , 0x11800a00011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT4" , 0x11800a0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT5" , 0x11800a00009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT6" , 0x11800a0000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT7" , 0x11800a0000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT8" , 0x11800a0000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT9" , 0x11800a0000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT10" , 0x11800a0000b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT11" , 0x11800a0000bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT12" , 0x11800a0000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT13" , 0x11800a0000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT14" , 0x11800a0000ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT15" , 0x11800a0000cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT16" , 0x11800a0000d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT17" , 0x11800a0000d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT18" , 0x11800a0000de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT19" , 0x11800a0000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT20" , 0x11800a0000e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT21" , 0x11800a0000ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT22" , 0x11800a0000f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT23" , 0x11800a0000f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT24" , 0x11800a0000fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT25" , 0x11800a0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT26" , 0x11800a0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT27" , 0x11800a00010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT28" , 0x11800a0001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT29" , 0x11800a0001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT30" , 0x11800a00011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT31" , 0x11800a00011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT4" , 0x11800a0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT5" , 0x11800a00009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT6" , 0x11800a0000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT7" , 0x11800a0000a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT8" , 0x11800a0000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT9" , 0x11800a0000b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT10" , 0x11800a0000b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT11" , 0x11800a0000bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT12" , 0x11800a0000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT13" , 0x11800a0000c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT14" , 0x11800a0000ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT15" , 0x11800a0000cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT16" , 0x11800a0000d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT17" , 0x11800a0000d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT18" , 0x11800a0000de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT19" , 0x11800a0000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT20" , 0x11800a0000e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT21" , 0x11800a0000ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT22" , 0x11800a0000f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT23" , 0x11800a0000f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT24" , 0x11800a0000fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT25" , 0x11800a0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT26" , 0x11800a0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT27" , 0x11800a00010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT28" , 0x11800a0001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT29" , 0x11800a0001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT30" , 0x11800a00011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT31" , 0x11800a00011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS4" , 0x11800a0001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS5" , 0x11800a0001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS6" , 0x11800a0001ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS7" , 0x11800a0001af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS8" , 0x11800a0001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS9" , 0x11800a0001b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS10" , 0x11800a0001b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS11" , 0x11800a0001b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS12" , 0x11800a0001b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS13" , 0x11800a0001bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS14" , 0x11800a0001bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS15" , 0x11800a0001bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS16" , 0x11800a0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS17" , 0x11800a0001c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS18" , 0x11800a0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS19" , 0x11800a0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS20" , 0x11800a0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS21" , 0x11800a0001cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS22" , 0x11800a0001cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS23" , 0x11800a0001cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS24" , 0x11800a0001d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS25" , 0x11800a0001d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS26" , 0x11800a0001d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS27" , 0x11800a0001d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS28" , 0x11800a0001d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS29" , 0x11800a0001db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS30" , 0x11800a0001dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS31" , 0x11800a0001df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS4" , 0x11800a0001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS5" , 0x11800a0001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS6" , 0x11800a0001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS7" , 0x11800a0001ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS8" , 0x11800a0001b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS9" , 0x11800a0001b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS10" , 0x11800a0001b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS11" , 0x11800a0001b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS12" , 0x11800a0001b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS13" , 0x11800a0001ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS14" , 0x11800a0001bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS15" , 0x11800a0001be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS16" , 0x11800a0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS17" , 0x11800a0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS18" , 0x11800a0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS19" , 0x11800a0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS20" , 0x11800a0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS21" , 0x11800a0001ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS22" , 0x11800a0001cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS23" , 0x11800a0001ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS24" , 0x11800a0001d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS25" , 0x11800a0001d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS26" , 0x11800a0001d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS27" , 0x11800a0001d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS28" , 0x11800a0001d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS29" , 0x11800a0001da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS30" , 0x11800a0001dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS31" , 0x11800a0001de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS4" , 0x11800a0001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS5" , 0x11800a0001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS6" , 0x11800a0001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS7" , 0x11800a0001ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS8" , 0x11800a0001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS9" , 0x11800a0001b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS10" , 0x11800a0001b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS11" , 0x11800a0001b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS12" , 0x11800a0001b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS13" , 0x11800a0001ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS14" , 0x11800a0001bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS15" , 0x11800a0001be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS16" , 0x11800a0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS17" , 0x11800a0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS18" , 0x11800a0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS19" , 0x11800a0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS20" , 0x11800a0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS21" , 0x11800a0001ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS22" , 0x11800a0001cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS23" , 0x11800a0001ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS24" , 0x11800a0001d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS25" , 0x11800a0001d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS26" , 0x11800a0001d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS27" , 0x11800a0001d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS28" , 0x11800a0001d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS29" , 0x11800a0001da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS30" , 0x11800a0001dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS31" , 0x11800a0001de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"PKO_REG_CRC_CTL0" , 0x1180050000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"PKO_REG_CRC_CTL1" , 0x1180050000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"PKO_REG_CRC_ENABLE" , 0x1180050000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"PKO_REG_CRC_IV0" , 0x1180050000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"PKO_REG_CRC_IV1" , 0x1180050000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 512},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 513},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 515},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 517},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK12" , 0x1670000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK13" , 0x1670000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK14" , 0x1670000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_PP_GRP_MSK15" , 0x1670000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 522},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 523},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 525},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 527},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"SPX0_BCKPRS_CNT" , 0x1180090000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"SPX1_BCKPRS_CNT" , 0x1180098000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"SPX0_BIST_STAT" , 0x11800900007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"SPX1_BIST_STAT" , 0x11800980007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"SPX0_CLK_CTL" , 0x1180090000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"SPX1_CLK_CTL" , 0x1180098000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"SPX0_CLK_STAT" , 0x1180090000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"SPX1_CLK_STAT" , 0x1180098000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"SPX0_DBG_DESKEW_CTL" , 0x1180090000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"SPX1_DBG_DESKEW_CTL" , 0x1180098000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"SPX0_DBG_DESKEW_STATE" , 0x1180090000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"SPX1_DBG_DESKEW_STATE" , 0x1180098000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"SPX0_DRV_CTL" , 0x1180090000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"SPX1_DRV_CTL" , 0x1180098000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"SPX0_ERR_CTL" , 0x1180090000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"SPX1_ERR_CTL" , 0x1180098000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"SPX0_INT_DAT" , 0x1180090000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SPX1_INT_DAT" , 0x1180098000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"SPX0_INT_MSK" , 0x1180090000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"SPX1_INT_MSK" , 0x1180098000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"SPX0_INT_REG" , 0x1180090000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"SPX1_INT_REG" , 0x1180098000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"SPX0_INT_SYNC" , 0x1180090000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"SPX1_INT_SYNC" , 0x1180098000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"SPX0_TPA_ACC" , 0x1180090000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"SPX1_TPA_ACC" , 0x1180098000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"SPX0_TPA_MAX" , 0x1180090000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"SPX1_TPA_MAX" , 0x1180098000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"SPX0_TPA_SEL" , 0x1180090000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"SPX1_TPA_SEL" , 0x1180098000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"SPX0_TRN4_CTL" , 0x1180090000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"SPX1_TRN4_CTL" , 0x1180098000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"SRX0_COM_CTL" , 0x1180090000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"SRX1_COM_CTL" , 0x1180098000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"SRX0_IGN_RX_FULL" , 0x1180090000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"SRX1_IGN_RX_FULL" , 0x1180098000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"SRX0_SPI4_CAL000" , 0x1180090000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL001" , 0x1180090000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL002" , 0x1180090000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL003" , 0x1180090000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL004" , 0x1180090000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL005" , 0x1180090000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL006" , 0x1180090000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL007" , 0x1180090000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL008" , 0x1180090000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL009" , 0x1180090000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL010" , 0x1180090000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL011" , 0x1180090000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL012" , 0x1180090000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL013" , 0x1180090000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL014" , 0x1180090000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL015" , 0x1180090000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL016" , 0x1180090000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL017" , 0x1180090000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL018" , 0x1180090000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL019" , 0x1180090000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL020" , 0x11800900000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL021" , 0x11800900000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL022" , 0x11800900000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL023" , 0x11800900000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL024" , 0x11800900000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL025" , 0x11800900000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL026" , 0x11800900000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL027" , 0x11800900000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL028" , 0x11800900000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL029" , 0x11800900000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL030" , 0x11800900000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_CAL031" , 0x11800900000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL000" , 0x1180098000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL001" , 0x1180098000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL002" , 0x1180098000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL003" , 0x1180098000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL004" , 0x1180098000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL005" , 0x1180098000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL006" , 0x1180098000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL007" , 0x1180098000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL008" , 0x1180098000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL009" , 0x1180098000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL010" , 0x1180098000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL011" , 0x1180098000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL012" , 0x1180098000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL013" , 0x1180098000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL014" , 0x1180098000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL015" , 0x1180098000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL016" , 0x1180098000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL017" , 0x1180098000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL018" , 0x1180098000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL019" , 0x1180098000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL020" , 0x11800980000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL021" , 0x11800980000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL022" , 0x11800980000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL023" , 0x11800980000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL024" , 0x11800980000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL025" , 0x11800980000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL026" , 0x11800980000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL027" , 0x11800980000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL028" , 0x11800980000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL029" , 0x11800980000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL030" , 0x11800980000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX1_SPI4_CAL031" , 0x11800980000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"SRX0_SPI4_STAT" , 0x1180090000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"SRX1_SPI4_STAT" , 0x1180098000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"SRX0_SW_TICK_CTL" , 0x1180090000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"SRX1_SW_TICK_CTL" , 0x1180098000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"SRX0_SW_TICK_DAT" , 0x1180090000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"SRX1_SW_TICK_DAT" , 0x1180098000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"STX0_ARB_CTL" , 0x1180090000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"STX1_ARB_CTL" , 0x1180098000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"STX0_BCKPRS_CNT" , 0x1180090000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"STX1_BCKPRS_CNT" , 0x1180098000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"STX0_COM_CTL" , 0x1180090000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"STX1_COM_CTL" , 0x1180098000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"STX0_DIP_CNT" , 0x1180090000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {"STX1_DIP_CNT" , 0x1180098000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {"STX0_IGN_CAL" , 0x1180090000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
- {"STX1_IGN_CAL" , 0x1180098000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
- {"STX0_INT_MSK" , 0x11800900006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
- {"STX1_INT_MSK" , 0x11800980006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
- {"STX0_INT_REG" , 0x1180090000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
- {"STX1_INT_REG" , 0x1180098000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
- {"STX0_INT_SYNC" , 0x11800900006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
- {"STX1_INT_SYNC" , 0x11800980006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
- {"STX0_MIN_BST" , 0x1180090000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
- {"STX1_MIN_BST" , 0x1180098000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
- {"STX0_SPI4_CAL000" , 0x1180090000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL001" , 0x1180090000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL002" , 0x1180090000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL003" , 0x1180090000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL004" , 0x1180090000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL005" , 0x1180090000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL006" , 0x1180090000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL007" , 0x1180090000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL008" , 0x1180090000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL009" , 0x1180090000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL010" , 0x1180090000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL011" , 0x1180090000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL012" , 0x1180090000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL013" , 0x1180090000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL014" , 0x1180090000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL015" , 0x1180090000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL016" , 0x1180090000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL017" , 0x1180090000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL018" , 0x1180090000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL019" , 0x1180090000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL020" , 0x11800900004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL021" , 0x11800900004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL022" , 0x11800900004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL023" , 0x11800900004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL024" , 0x11800900004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL025" , 0x11800900004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL026" , 0x11800900004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL027" , 0x11800900004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL028" , 0x11800900004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL029" , 0x11800900004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL030" , 0x11800900004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_CAL031" , 0x11800900004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL000" , 0x1180098000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL001" , 0x1180098000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL002" , 0x1180098000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL003" , 0x1180098000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL004" , 0x1180098000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL005" , 0x1180098000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL006" , 0x1180098000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL007" , 0x1180098000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL008" , 0x1180098000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL009" , 0x1180098000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL010" , 0x1180098000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL011" , 0x1180098000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL012" , 0x1180098000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL013" , 0x1180098000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL014" , 0x1180098000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL015" , 0x1180098000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL016" , 0x1180098000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL017" , 0x1180098000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL018" , 0x1180098000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL019" , 0x1180098000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL020" , 0x11800980004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL021" , 0x11800980004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL022" , 0x11800980004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL023" , 0x11800980004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL024" , 0x11800980004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL025" , 0x11800980004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL026" , 0x11800980004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL027" , 0x11800980004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL028" , 0x11800980004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL029" , 0x11800980004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL030" , 0x11800980004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX1_SPI4_CAL031" , 0x11800980004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"STX0_SPI4_DAT" , 0x1180090000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
- {"STX1_SPI4_DAT" , 0x1180098000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
- {"STX0_SPI4_STAT" , 0x1180090000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
- {"STX1_SPI4_STAT" , 0x1180098000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
- {"STX0_STAT_BYTES_HI" , 0x1180090000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
- {"STX1_STAT_BYTES_HI" , 0x1180098000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
- {"STX0_STAT_BYTES_LO" , 0x1180090000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
- {"STX1_STAT_BYTES_LO" , 0x1180098000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
- {"STX0_STAT_CTL" , 0x1180090000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
- {"STX1_STAT_CTL" , 0x1180098000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
- {"STX0_STAT_PKT_XMT" , 0x1180090000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
- {"STX1_STAT_PKT_XMT" , 0x1180098000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 577},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 578},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 581},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 582},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 583},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 584},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 585},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 586},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 587},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 588},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 589},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 590},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 591},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 592},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 593},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 594},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 595},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 596},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 597},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 598},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 599},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 600},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 601},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 606},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 612},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"OVRFLW" , 0, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"TXPOP" , 4, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"TXPSH" , 8, 4, 0, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_12_63" , 12, 52, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 0, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 4, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 8, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 1, "RAZ", 1, 1, 0, 0},
- {"INT_LOOP" , 0, 4, 2, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_LOOP" , 4, 4, 2, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 2, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 1, 3, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 3, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 4, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 5, "RO", 0, 1, 0ull, 0},
- {"PCTL" , 4, 5, 5, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 5, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 6, "R/W", 0, 1, 0ull, 0},
- {"PCTL" , 4, 4, 6, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 6, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 7, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 7, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 8, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 9, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 10, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 10, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 11, "RO", 1, 1, 0, 0},
- {"DFALOCK" , 5, 1, 11, "RO", 1, 1, 0, 0},
- {"DFALEAD" , 6, 1, 11, "RO", 1, 1, 0, 0},
- {"DFALAG" , 7, 1, 11, "RO", 1, 1, 0, 0},
- {"DFASET" , 8, 5, 11, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 11, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 12, "R/W", 0, 0, 24ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 12, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 4, 13, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 13, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 14, "R/W", 0, 0, 24ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 14, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 15, "R/W", 0, 0, 6ull, 6ull},
- {"RESERVED_5_7" , 5, 3, 15, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 5, 15, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_13_63" , 13, 51, 15, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 4, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 16, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 4, 17, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 17, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 4, 18, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 4, 5, 18, "R/W", 0, 1, 31ull, 0},
- {"RESERVED_9_63" , 9, 55, 18, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 19, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_1_63" , 1, 63, 19, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 4, 20, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 20, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 16, 21, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 16, 22, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 24, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 24, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 24, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 24, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 24, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 24, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 24, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 24, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 24, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 24, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 24, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 24, "R/W", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 24, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 24, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 24, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 25, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 25, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 25, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 26, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 26, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 26, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 27, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 27, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 28, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 28, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 29, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 29, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 30, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 30, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 30, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 30, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 30, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 30, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 30, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 30, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 30, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 30, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 30, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 30, "R/W", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 30, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 30, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 30, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 31, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 31, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 32, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 32, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 32, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 33, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 33, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 34, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 34, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 35, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 35, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 36, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 36, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 36, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 36, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 36, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 36, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 36, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 36, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 36, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 36, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 37, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 37, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 37, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 37, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 37, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 37, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 37, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 37, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 37, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 37, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 37, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 37, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 37, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 37, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 37, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 16, 38, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 38, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 39, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 40, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 40, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 16, 41, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 41, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 42, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 16, 43, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 43, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 44, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 45, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 15, 45, "R/W", 0, 0, 32767ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"SOFT_BIST" , 0, 1, 46, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 46, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 47, "R/W", 0, 0, 1ull, 0ull},
- {"NPI" , 1, 1, 47, "R/W", 0, 0, 0ull, 0ull},
- {"HOST64" , 2, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 47, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 48, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 48, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 49, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 49, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 49, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 50, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 50, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 50, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 50, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 50, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 50, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 51, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 51, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 51, "RO", 1, 1, 0, 0},
- {"REM" , 23, 6, 51, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 51, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 4, 52, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 52, "RAZ", 0, 0, 0ull, 0ull},
- {"RDF" , 16, 4, 52, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 52, "RAZ", 0, 0, 0ull, 0ull},
- {"P1_BRF" , 0, 8, 53, "RO", 0, 0, 0ull, 0ull},
- {"P0_BRF" , 8, 8, 53, "RO", 0, 0, 0ull, 0ull},
- {"P1_BWB" , 16, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"P0_BWB" , 17, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"CRF" , 18, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 53, "RAZ", 0, 0, 0ull, 0ull},
- {"GFU" , 20, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"IFU" , 21, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 22, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 53, "RAZ", 0, 0, 0ull, 0ull},
- {"SARB" , 0, 1, 54, "R/W", 0, 0, 1ull, 1ull},
- {"GXOR_ENA" , 1, 1, 54, "R/W", 0, 0, 0ull, 0ull},
- {"NXOR_ENA" , 2, 1, 54, "R/W", 0, 0, 0ull, 0ull},
- {"NRPL_ENA" , 3, 1, 54, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 54, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 20, 55, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 55, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 9, 56, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 56, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 56, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_20_63" , 20, 44, 56, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 57, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 31, 57, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 57, "RAZ", 1, 1, 0, 0},
- {"CP2ECCENA" , 0, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"CP2SBE" , 1, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2DBE" , 2, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2SBINA" , 3, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"CP2DBINA" , 4, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"CP2SYN" , 5, 8, 58, "RO", 0, 0, 0ull, 0ull},
- {"DTEECCENA" , 13, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"DTESBE" , 14, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTEDBE" , 15, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTESBINA" , 16, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"DTEDBINA" , 17, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"DTESYN" , 18, 7, 58, "RO", 0, 0, 0ull, 0ull},
- {"DTEPARENA" , 25, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"DTEPERR" , 26, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTEPINA" , 27, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"CP2PARENA" , 28, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"CP2PERR" , 29, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
- {"CP2PINA" , 30, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"DBLOVF" , 31, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBLINA" , 32, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 58, "RAZ", 1, 1, 0, 0},
- {"ENA_P1" , 0, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"ENA_P0" , 1, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 59, "RAZ", 1, 1, 0, 0},
- {"MTYPE" , 3, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_LAT" , 4, 2, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RW_DLY" , 6, 4, 59, "R/W", 0, 0, 1ull, 1ull},
- {"WR_DLY" , 10, 4, 59, "R/W", 0, 0, 2ull, 2ull},
- {"FPRCH" , 14, 2, 59, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 16, 2, 59, "R/W", 0, 0, 0ull, 0ull},
- {"BLEN" , 18, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"PBUNK" , 19, 3, 59, "R/W", 0, 0, 2ull, 2ull},
- {"R2R_PBUNK" , 22, 1, 59, "R/W", 0, 0, 1ull, 1ull},
- {"INIT_P1" , 23, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"INIT_P0" , 24, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"BUNK_INIT" , 25, 2, 59, "R/W", 0, 0, 3ull, 3ull},
- {"LPP_ENA" , 27, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"CLKDIV" , 28, 2, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RLDCK_RST" , 30, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RLDQCK90_RST" , 31, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 59, "RAZ", 1, 1, 0, 0},
- {"REF_INT" , 0, 4, 60, "R/W", 0, 0, 3ull, 3ull},
- {"TSKW" , 4, 2, 60, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 60, "RAZ", 0, 0, 0ull, 0ull},
- {"TRL" , 8, 4, 60, "R/W", 0, 0, 6ull, 6ull},
- {"TWL" , 12, 4, 60, "R/W", 0, 0, 7ull, 7ull},
- {"TRC" , 16, 4, 60, "R/W", 0, 0, 6ull, 6ull},
- {"TMRSC" , 20, 3, 60, "R/W", 0, 0, 6ull, 6ull},
- {"MRS_ENA" , 23, 1, 60, "R/W", 0, 0, 0ull, 0ull},
- {"AREF_ENA" , 24, 1, 60, "R/W", 0, 0, 0ull, 0ull},
- {"REF_INTLO" , 25, 9, 60, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 60, "RAZ", 1, 1, 0, 0},
- {"FCRAM2P" , 0, 1, 61, "R/W", 0, 0, 0ull, 0ull},
- {"MAXBNK" , 1, 1, 61, "R/W", 0, 0, 1ull, 1ull},
- {"UA_START" , 2, 2, 61, "R/W", 0, 0, 1ull, 1ull},
- {"REFSHORT" , 4, 1, 61, "R/W", 0, 0, 0ull, 0ull},
- {"TRFC" , 5, 5, 61, "R/W", 0, 0, 9ull, 9ull},
- {"SILRST" , 10, 1, 61, "R/W", 0, 0, 0ull, 0ull},
- {"DTECLKDIS" , 11, 1, 61, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 61, "RAZ", 1, 1, 0, 0},
- {"MADDR" , 0, 24, 62, "RO", 0, 0, 0ull, 0ull},
- {"BNUM" , 24, 3, 62, "RO", 0, 0, 0ull, 0ull},
- {"PNUM" , 27, 1, 62, "RO", 0, 0, 0ull, 0ull},
- {"FSRC" , 28, 2, 62, "RO", 0, 0, 0ull, 0ull},
- {"FDST" , 30, 9, 62, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 62, "RAZ", 1, 1, 0, 0},
- {"MRS" , 0, 15, 63, "R/W", 0, 0, 66ull, 66ull},
- {"RESERVED_15_15" , 15, 1, 63, "RAZ", 1, 1, 0, 0},
- {"EMRS" , 16, 15, 63, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_31_31" , 31, 1, 63, "RAZ", 1, 1, 0, 0},
- {"EMRS2" , 32, 15, 63, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 63, "RAZ", 1, 1, 0, 0},
- {"MRSDAT" , 0, 23, 64, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_23_63" , 23, 41, 64, "RAZ", 1, 1, 0, 0},
- {"IMODE" , 0, 1, 65, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 1, 1, 65, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 2, 1, 65, "R/W", 0, 0, 1ull, 1ull},
- {"DTMODE" , 3, 1, 65, "R/W", 0, 0, 1ull, 1ull},
- {"DCMODE" , 4, 1, 65, "R/W", 0, 0, 0ull, 0ull},
- {"SBDLCK" , 5, 1, 65, "R/W", 0, 0, 0ull, 0ull},
- {"SBDNUM" , 6, 5, 65, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 65, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 66, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 66, "RAZ", 0, 1, 0ull, 0},
- {"NCTL" , 8, 4, 66, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 66, "RAZ", 0, 1, 0ull, 0},
- {"ENABLE" , 16, 1, 66, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 66, "RAZ", 0, 1, 0ull, 0},
- {"SBD0" , 0, 64, 67, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 68, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 69, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 70, "RO", 1, 1, 0, 0},
- {"FDR" , 0, 1, 71, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 71, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 71, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 71, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 71, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 71, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 72, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 72, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 72, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 72, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 72, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 72, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 72, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 73, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 73, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 73, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 74, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 74, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 75, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 75, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 75, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 76, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 76, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 77, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 78, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 79, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 79, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 80, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 80, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 81, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 81, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 81, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 82, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 82, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 82, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 83, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 83, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 84, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 84, "RAZ", 1, 1, 0, 0},
- {"OUT_COL" , 0, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB_OVR" , 1, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 16, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_21" , 18, 4, 85, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 4, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 85, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 17, 86, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 86, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 87, "RO", 1, 1, 0, 0},
- {"EN" , 1, 1, 87, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 87, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 88, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 88, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 89, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 89, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 89, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 89, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_63" , 4, 60, 89, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 90, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 91, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 92, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 93, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 94, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 95, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 96, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 96, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 97, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 97, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 97, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 97, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 98, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 98, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 99, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 99, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 99, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 99, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 99, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 99, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 99, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 99, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 99, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 99, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 99, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 100, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 100, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 100, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 100, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 100, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 100, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_FREE" , 6, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"VLAN_LEN" , 7, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 100, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 101, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 101, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 102, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 102, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 103, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 103, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 104, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 105, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 106, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 106, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 107, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 107, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 108, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 108, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 108, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 108, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 109, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 109, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 110, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 110, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 111, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 111, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 112, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 112, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 113, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 113, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 114, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 114, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 115, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 115, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 116, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 116, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 117, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 117, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 118, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 118, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 119, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 119, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 119, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 120, "R/W", 1, 1, 0, 0},
- {"RESERVED_6_63" , 6, 58, 120, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 121, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 121, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 122, "R/W", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 122, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 16, 123, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 123, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 4, 124, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 124, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 16, 125, "RO", 0, 0, 0ull, 0ull},
- {"DROP" , 16, 16, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 125, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 126, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 126, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 127, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 127, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 128, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 128, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 129, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 129, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 129, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 129, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 129, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 130, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 130, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 131, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 131, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 132, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 132, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 132, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 133, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 133, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 134, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 134, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 135, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 135, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 136, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 136, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 137, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 137, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 138, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 138, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 139, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 139, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 140, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 141, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 141, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 142, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 142, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 143, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 143, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 144, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 144, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 145, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 145, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 146, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 146, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 147, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 147, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 148, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 148, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 149, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 149, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 150, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 151, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 151, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 152, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 152, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 153, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 153, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 154, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 154, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 155, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 155, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 155, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"NCB_NXA" , 1, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 156, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 156, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 156, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 156, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 156, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 156, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB_NXA" , 1, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 157, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 157, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 157, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 157, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 157, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 157, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 158, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 158, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 159, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 159, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 160, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 160, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 160, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 161, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 161, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 162, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 163, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_5_63" , 5, 59, 163, "RAZ", 1, 1, 0, 0},
- {"CONT_PKT" , 0, 1, 164, "R/W", 0, 1, 0ull, 0},
- {"TPA_CLR" , 1, 1, 164, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 164, "RAZ", 0, 0, 0ull, 0ull},
- {"DRAIN" , 0, 16, 165, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 165, "RAZ", 1, 1, 0, 0},
- {"MAX1" , 0, 8, 166, "R/W", 0, 1, 8ull, 0},
- {"MAX2" , 8, 8, 166, "R/W", 0, 1, 4ull, 0},
- {"SLICE" , 16, 7, 166, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 166, "RAZ", 1, 1, 0, 0},
- {"ROUND" , 0, 16, 167, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 6, 168, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_6_63" , 6, 58, 168, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 169, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 169, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 170, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 170, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 171, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 171, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 172, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 172, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 173, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 173, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 174, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 175, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 175, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 176, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 176, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 177, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 177, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 177, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 178, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 178, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 178, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 179, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 179, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 179, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 179, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 179, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 180, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 180, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 180, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 180, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 180, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 181, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 182, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 183, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 184, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 185, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 185, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 186, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 186, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 186, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 187, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 187, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 187, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 188, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 188, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 188, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 188, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 188, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 189, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 189, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 189, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 189, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 189, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 190, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 191, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 192, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 192, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 193, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 193, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 194, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 194, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 195, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 195, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 196, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 196, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 197, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 197, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 198, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 198, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 199, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 199, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 200, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 201, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 202, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 202, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 202, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 203, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 204, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 205, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 205, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 206, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 206, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 207, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 207, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 208, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 208, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 209, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 209, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 3, 210, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 210, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 210, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 210, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 210, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 210, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 211, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 211, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 211, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 211, "RO", 0, 0, 36ull, 36ull},
- {"RESERVED_44_63" , 44, 20, 211, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 212, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 212, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 212, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 212, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 213, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 213, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 213, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 213, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 213, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 213, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_61_63" , 61, 3, 213, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 214, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 214, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 215, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 215, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 216, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 216, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 216, "R/W", 0, 0, 0ull, 0ull},
- {"PRB_CON" , 0, 32, 217, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 217, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 217, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 217, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 218, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 218, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 218, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 219, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 219, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 220, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 220, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 221, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 221, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 222, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 223, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 223, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 224, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 224, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 224, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 224, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 224, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 225, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 226, "RO", 0, 0, 0ull, 0ull},
- {"STIN_MSK" , 4, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 13, 226, "RO", 0, 0, 0ull, 0ull},
- {"WLB_MSK" , 19, 4, 226, "RO", 0, 0, 0ull, 0ull},
- {"DTBNK" , 23, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 226, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 9, 227, "RO", 0, 0, 0ull, 0ull},
- {"VAB_VWCF" , 9, 1, 227, "RO", 0, 0, 0ull, 0ull},
- {"LRF" , 10, 2, 227, "RO", 0, 0, 0ull, 0ull},
- {"VWDF" , 12, 4, 227, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 227, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 228, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 228, "RO", 0, 0, 0ull, 0ull},
- {"PICBST" , 2, 1, 228, "RO", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 228, "RO", 0, 0, 0ull, 0ull},
- {"RHDB" , 4, 4, 228, "RO", 0, 0, 0ull, 0ull},
- {"RMDB" , 8, 4, 228, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 228, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 228, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 229, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 229, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 229, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 229, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 229, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 229, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 229, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 229, "R/W", 0, 0, 0ull, 0ull},
- {"DFILL_DIS" , 14, 1, 229, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_17" , 15, 3, 229, "RAZ", 0, 0, 0ull, 0ull},
- {"LBIST" , 18, 1, 229, "R/W", 0, 0, 0ull, 0ull},
- {"BSTRUN" , 19, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 229, "RAZ", 1, 1, 0, 0},
- {"L2T" , 0, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 3, 230, "R/W", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 4, 230, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 4, 230, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 230, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 231, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 231, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 231, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 232, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 232, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 232, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 232, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 233, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 233, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 234, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 234, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 4, 234, "RO", 0, 0, 0ull, 0ull},
- {"SET" , 18, 3, 234, "RO", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 4, 234, "RO", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 234, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 235, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 235, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 11, 236, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 11, 16, 236, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 236, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 4, 237, "R/W", 0, 0, 15ull, 15ull},
- {"STPARTDIS" , 4, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 237, "RAZ", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 238, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 239, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 8, 240, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK1" , 8, 8, 240, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK2" , 16, 8, 240, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK3" , 24, 8, 240, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 240, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK4" , 0, 8, 241, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK5" , 8, 8, 241, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK6" , 16, 8, 241, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK7" , 24, 8, 241, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 241, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK8" , 0, 8, 242, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK9" , 8, 8, 242, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK10" , 16, 8, 242, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK11" , 24, 8, 242, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 242, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK12" , 0, 8, 243, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK13" , 8, 8, 243, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK14" , 16, 8, 243, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK15" , 24, 8, 243, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 243, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 8, 244, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 244, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 245, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 245, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 245, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 246, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 246, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 247, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 248, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 249, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 249, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 249, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 249, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 249, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 11, 250, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 3, 250, "RO", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 250, "RO", 0, 0, 0ull, 0ull},
- {"FADRU" , 18, 1, 250, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 250, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 251, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 251, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 251, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 252, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 252, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 252, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 253, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 254, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 254, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 255, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 255, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 256, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_1024K" , 34, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_512K" , 35, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_36" , 36, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"EMA_CTL" , 37, 2, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 256, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 257, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 257, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 257, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 257, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 257, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 257, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 10, 257, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 3, 257, "RO", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 257, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 257, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 257, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 257, "R/W", 0, 0, 0ull, 1ull},
- {"FADRU" , 28, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 257, "RAZ", 0, 0, 0ull, 0ull},
- {"RATE" , 0, 8, 258, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_63" , 8, 56, 258, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 7, 259, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_7_63" , 7, 57, 259, "RAZ", 1, 1, 0, 0},
- {"RATE" , 0, 16, 260, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 260, "RAZ", 1, 1, 0, 0},
- {"DBG_EN" , 0, 1, 261, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 261, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 262, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 262, "RAZ", 1, 1, 0, 0},
- {"POLARITY" , 0, 1, 263, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 263, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 8, 264, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 264, "RAZ", 1, 1, 0, 0},
- {"FORMAT" , 0, 4, 265, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 265, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 266, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 266, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 267, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 267, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 32, 268, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 268, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 32, 269, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 269, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 32, 270, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
- {"PCTL_DAT" , 0, 5, 271, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_11" , 5, 7, 271, "RAZ", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 271, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 271, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_27" , 20, 8, 271, "RAZ", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 271, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 271, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 272, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 272, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 272, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 272, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 272, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"MODE128B" , 10, 1, 272, "R/W", 0, 0, 1ull, 1ull},
- {"DRESET" , 11, 1, 272, "R/W", 0, 0, 1ull, 0ull},
- {"INORDER_MRF" , 12, 1, 272, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 272, "RAZ", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 272, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 272, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_17" , 16, 2, 272, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 272, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 272, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 272, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 272, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 272, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 273, "RAZ", 0, 1, 0ull, 0},
- {"DCC_ENABLE" , 8, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_MODE" , 9, 1, 273, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 273, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 274, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 274, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 275, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 276, "R/W", 0, 0, 1ull, 1ull},
- {"RDQS" , 1, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 276, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 276, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 276, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 276, "R/W", 0, 0, 0ull, 0ull},
- {"SILO_HC" , 21, 1, 276, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 276, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 276, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 276, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 276, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 276, "RAZ", 0, 0, 0ull, 0ull},
- {"CLK" , 0, 4, 277, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 277, "RAZ", 0, 0, 0ull, 0ull},
- {"CMD" , 5, 4, 277, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 277, "RAZ", 0, 0, 0ull, 0ull},
- {"DQ" , 10, 4, 277, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 277, "RAZ", 0, 0, 0ull, 0ull},
- {"CS_MASK" , 0, 8, 278, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 278, "RAZ", 0, 1, 0ull, 0},
- {"ROW_LSB" , 16, 3, 278, "R/W", 0, 1, 3ull, 0},
- {"BANK8" , 19, 1, 278, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 278, "RAZ", 0, 1, 0ull, 0},
- {"MRDSYN0" , 0, 8, 279, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 279, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 279, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 279, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 279, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 280, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 280, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 280, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 280, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 280, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 280, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 281, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 281, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 282, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 282, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 283, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 283, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 283, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 283, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 283, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 283, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 283, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 283, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 283, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 283, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 283, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 283, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 283, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 283, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 284, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 284, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 284, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 284, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 284, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 284, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 284, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 284, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_31_63" , 31, 33, 284, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 285, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 285, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 286, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 286, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 287, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 287, "RAZ", 1, 1, 0, 0},
- {"EN2" , 0, 1, 288, "R/W", 0, 1, 0ull, 0},
- {"EN4" , 1, 1, 288, "R/W", 0, 1, 0ull, 0},
- {"EN6" , 2, 1, 288, "R/W", 0, 1, 0ull, 0},
- {"EN8" , 3, 1, 288, "R/W", 0, 1, 1ull, 0},
- {"EN12" , 4, 1, 288, "R/W", 0, 1, 0ull, 0},
- {"EN16" , 5, 1, 288, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 288, "RAZ", 0, 1, 0ull, 0},
- {"CLKR" , 8, 6, 288, "R/W", 0, 1, 0ull, 0},
- {"CLKF" , 14, 12, 288, "R/W", 0, 1, 31ull, 0},
- {"RESET_N" , 26, 1, 288, "R/W", 0, 0, 0ull, 1ull},
- {"DIV_RESET" , 27, 1, 288, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 288, "RAZ", 0, 1, 0ull, 0},
- {"FBSLIP" , 0, 1, 289, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 289, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_21" , 2, 20, 289, "RAZ", 1, 1, 0, 0},
- {"DDR__PCTL" , 22, 5, 289, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 27, 5, 289, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 289, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 290, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 290, "RAZ", 0, 1, 0ull, 0},
- {"NCTL" , 8, 4, 290, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 290, "RAZ", 0, 1, 0ull, 0},
- {"ENABLE" , 16, 1, 290, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 290, "RAZ", 0, 1, 0ull, 0},
- {"RODT_LO0" , 0, 4, 291, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO1" , 4, 4, 291, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO2" , 8, 4, 291, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO3" , 12, 4, 291, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI0" , 16, 4, 291, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI1" , 20, 4, 291, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI2" , 24, 4, 291, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI3" , 28, 4, 291, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 291, "RAZ", 1, 1, 0, 0},
- {"WODT_LO0" , 0, 4, 292, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO1" , 4, 4, 292, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO2" , 8, 4, 292, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO3" , 12, 4, 292, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI0" , 16, 4, 292, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI1" , 20, 4, 292, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI2" , 24, 4, 292, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI3" , 28, 4, 292, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 292, "RAZ", 1, 1, 0, 0},
- {"NCBI" , 0, 1, 293, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 293, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 2, 1, 293, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 293, "RAZ", 1, 1, 0, 0},
- {"ADR_ERR" , 0, 1, 294, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 294, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 294, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 295, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 295, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 295, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 296, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 296, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 296, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 297, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 297, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 297, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 297, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 297, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 298, "R/W", 1, 1, 0, 0},
- {"BASE" , 0, 16, 299, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 299, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 299, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 299, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_63" , 37, 27, 299, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 300, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 300, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 300, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 300, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 300, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 300, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 300, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 300, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 300, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 300, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 300, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 301, "R/W", 0, 0, 26ull, 26ull},
- {"RESERVED_6_7" , 6, 2, 301, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 301, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 301, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 302, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 303, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 303, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 304, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 304, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 16, 305, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 305, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 305, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 305, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 305, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 305, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 305, "RO", 1, 1, 0, 0},
- {"NOKASU" , 29, 1, 305, "RO", 1, 1, 0, 0},
- {"RESERVED_30_63" , 30, 34, 305, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 306, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 306, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 306, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 306, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 306, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 306, "RO", 1, 1, 0, 0},
- {"ZIP_CRIP" , 29, 2, 306, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 306, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 2, 307, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_2_63" , 2, 62, 307, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 308, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 309, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 309, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 309, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 310, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 310, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 8, 311, "R/W", 0, 1, 3ull, 0},
- {"SCLK_HI" , 8, 12, 311, "R/W", 0, 1, 100ull, 0},
- {"SCLK_LO" , 20, 4, 311, "R/W", 0, 1, 2ull, 0},
- {"OUT" , 24, 8, 311, "R/W", 0, 1, 3ull, 0},
- {"PROG_PIN" , 32, 1, 311, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 311, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 7, 312, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 312, "RAZ", 1, 1, 0, 0},
- {"EFUSE" , 8, 1, 312, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 312, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 312, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 312, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 312, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 312, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 313, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 14, 14, 313, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 28, 14, 313, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 313, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 314, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 314, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 2, 315, "R/W", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 315, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 316, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 316, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 316, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 316, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 316, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 316, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 316, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 316, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 317, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 317, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 317, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 317, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 317, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 317, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 317, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 317, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 318, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 318, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 318, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 319, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 319, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 319, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 320, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 320, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 321, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 321, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 322, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 322, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 323, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 323, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 323, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 323, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 323, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 323, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 323, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 324, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 324, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 325, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 325, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 326, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 326, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 326, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 326, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 327, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 327, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 327, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 327, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 327, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 327, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 327, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 327, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 328, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 328, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 328, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 328, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 328, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 328, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 328, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 328, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 328, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 329, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 330, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 330, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 330, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 330, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 330, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 330, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 330, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 330, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 330, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 331, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 331, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 332, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 332, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 333, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 333, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 333, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 333, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 334, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 334, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 335, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 335, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 336, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 336, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 337, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 337, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 337, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 337, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 338, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 338, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 339, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 339, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 340, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 340, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 341, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 341, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 342, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 342, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 343, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 343, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 344, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 344, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 344, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 344, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 344, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 344, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 345, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 345, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 346, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 346, "R/W", 0, 1, 0ull, 0},
- {"DPI_BS" , 0, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"PDF_BS" , 1, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"DOB_BS" , 2, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"NUS_BS" , 3, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"POS_BS" , 4, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"POF3_BS" , 5, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"POF2_BS" , 6, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"POF1_BS" , 7, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"POF0_BS" , 8, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"PIG_BS" , 9, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"PGF_BS" , 10, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"RDNL_BS" , 11, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"PCAD_BS" , 12, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"PCAC_BS" , 13, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"RDN_BS" , 14, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"PCN_BS" , 15, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"PCNC_BS" , 16, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"RDP_BS" , 17, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"DIF_BS" , 18, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"CSR_BS" , 19, 1, 347, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 347, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 348, "R/W", 0, 1, 1024ull, 0},
- {"ISIZE" , 16, 7, 348, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 348, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 349, "R/W", 0, 1, 16ull, 0},
- {"PCTL" , 5, 5, 349, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_10_63" , 10, 54, 349, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 350, "R/W", 0, 0, 0ull, 50ull},
- {"RESERVED_10_31" , 10, 22, 350, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_WORD" , 32, 5, 350, "R/W", 0, 0, 2ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 350, "RAZ", 0, 0, 0ull, 0ull},
- {"WAIT_COM" , 40, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_WDIS" , 41, 1, 350, "R/W", 0, 0, 0ull, 0ull},
- {"INS0_64B" , 42, 1, 350, "R/W", 0, 1, 0ull, 0},
- {"INS1_64B" , 43, 1, 350, "R/W", 0, 1, 0ull, 0},
- {"INS2_64B" , 44, 1, 350, "R/W", 0, 1, 0ull, 0},
- {"INS3_64B" , 45, 1, 350, "R/W", 0, 1, 0ull, 0},
- {"INS0_ENB" , 46, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"INS1_ENB" , 47, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"INS2_ENB" , 48, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"INS3_ENB" , 49, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"OUT0_ENB" , 50, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"OUT1_ENB" , 51, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"OUT2_ENB" , 52, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"OUT3_ENB" , 53, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"DIS_PNIW" , 54, 1, 350, "R/W", 0, 0, 0ull, 1ull},
- {"CHIP_REV" , 55, 8, 350, "RO", 1, 1, 0, 0},
- {"RESERVED_63_63" , 63, 1, 350, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 351, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 351, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 0, 14, 352, "R/W", 0, 1, 0ull, 0},
- {"LP_ENB" , 14, 1, 352, "R/W", 0, 0, 0ull, 1ull},
- {"HP_ENB" , 15, 1, 352, "R/W", 0, 0, 0ull, 1ull},
- {"O_MODE" , 16, 1, 352, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 17, 2, 352, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 19, 1, 352, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 20, 1, 352, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 21, 1, 352, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 22, 3, 352, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 25, 9, 352, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 34, 1, 352, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 35, 1, 352, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 352, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 353, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 353, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 353, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 354, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 354, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 354, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 355, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 355, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 355, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 356, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 356, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 356, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 357, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 357, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 358, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 358, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 359, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 359, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 359, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 359, "R/W", 0, 1, 0ull, 0},
- {"PKT_RR" , 22, 1, 359, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 359, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_RSL" , 2, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PO0_2SML" , 3, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PO1_2SML" , 4, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PO2_2SML" , 5, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PO3_2SML" , 6, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I0_RTOUT" , 7, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I1_RTOUT" , 8, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I2_RTOUT" , 9, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I3_RTOUT" , 10, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I0_OVERF" , 11, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I1_OVERF" , 12, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I2_OVERF" , 13, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I3_OVERF" , 14, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P0_RTOUT" , 15, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P1_RTOUT" , 16, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P2_RTOUT" , 17, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P3_RTOUT" , 18, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PERR" , 19, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PERR" , 20, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PERR" , 21, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PERR" , 22, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"G0_RTOUT" , 23, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"G1_RTOUT" , 24, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"G2_RTOUT" , 25, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"G3_RTOUT" , 26, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PPERR" , 27, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PPERR" , 28, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PPERR" , 29, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PPERR" , 30, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P0_PTOUT" , 31, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PTOUT" , 32, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P2_PTOUT" , 33, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P3_PTOUT" , 34, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I0_PPERR" , 35, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I1_PPERR" , 36, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I2_PPERR" , 37, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"I3_PPERR" , 38, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"WIN_RTO" , 39, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"P_DPERR" , 40, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 41, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_S_E" , 42, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_A_F" , 43, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_S_E" , 44, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_A_F" , 45, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_S_E" , 46, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_A_F" , 47, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_S_E" , 48, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_A_F" , 49, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"COM_S_E" , 50, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"COM_A_F" , 51, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_S_E" , 52, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_A_F" , 53, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"RWX_S_E" , 54, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"RDX_S_E" , 55, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_E" , 56, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_F" , 57, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_E" , 58, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_F" , 59, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_S_E" , 60, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_A_F" , 61, 1, 360, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_62_63" , 62, 2, 360, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_RSL" , 2, 1, 361, "RO", 0, 0, 0ull, 0ull},
- {"PO0_2SML" , 3, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO1_2SML" , 4, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO2_2SML" , 5, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO3_2SML" , 6, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_RTOUT" , 7, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_RTOUT" , 8, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_RTOUT" , 9, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_RTOUT" , 10, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_OVERF" , 11, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_OVERF" , 12, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_OVERF" , 13, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_OVERF" , 14, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_RTOUT" , 15, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_RTOUT" , 16, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_RTOUT" , 17, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_RTOUT" , 18, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PERR" , 19, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PERR" , 20, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PERR" , 21, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PERR" , 22, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"G0_RTOUT" , 23, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"G1_RTOUT" , 24, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"G2_RTOUT" , 25, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"G3_RTOUT" , 26, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PPERR" , 27, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PPERR" , 28, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PPERR" , 29, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PPERR" , 30, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_PTOUT" , 31, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PTOUT" , 32, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P2_PTOUT" , 33, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P3_PTOUT" , 34, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I0_PPERR" , 35, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_PPERR" , 36, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2_PPERR" , 37, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"I3_PPERR" , 38, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_RTO" , 39, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DPERR" , 40, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 41, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_S_E" , 42, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_A_F" , 43, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_S_E" , 44, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_A_F" , 45, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_S_E" , 46, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_A_F" , 47, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_S_E" , 48, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_A_F" , 49, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_S_E" , 50, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_A_F" , 51, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_S_E" , 52, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_A_F" , 53, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"RWX_S_E" , 54, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDX_S_E" , 55, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_E" , 56, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_F" , 57, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_E" , 58, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_F" , 59, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_S_E" , 60, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_A_F" , 61, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 361, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 362, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 362, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 363, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 363, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 28, 364, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 28, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 29, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 30, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 31, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 32, 2, 364, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 34, 2, 364, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 36, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"SHORTL" , 37, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 364, "RAZ", 1, 1, 0, 0},
- {"INT_VEC" , 0, 64, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 32, 366, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 366, "RAZ", 1, 1, 0, 0},
- {"ROR_SL0" , 0, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL0" , 1, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL0" , 2, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL1" , 4, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL1" , 5, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL1" , 6, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL2" , 8, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL2" , 9, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL2" , 10, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL3" , 12, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL3" , 13, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL3" , 14, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"IPTR_O0" , 16, 1, 367, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O1" , 17, 1, 367, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O2" , 18, 1, 367, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O3" , 19, 1, 367, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_23" , 20, 4, 367, "RAZ", 0, 0, 0ull, 0ull},
- {"O0_CSRM" , 24, 1, 367, "R/W", 0, 0, 0ull, 1ull},
- {"O1_CSRM" , 25, 1, 367, "R/W", 0, 0, 0ull, 1ull},
- {"O2_CSRM" , 26, 1, 367, "R/W", 0, 0, 0ull, 1ull},
- {"O3_CSRM" , 27, 1, 367, "R/W", 0, 0, 0ull, 1ull},
- {"O0_RO" , 28, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"O0_NS" , 29, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"O0_ES" , 30, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"O1_RO" , 32, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"O1_NS" , 33, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"O1_ES" , 34, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"O2_RO" , 36, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"O2_NS" , 37, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"O2_ES" , 38, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"O3_RO" , 40, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"O3_NS" , 41, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"O3_ES" , 42, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"P0_BMODE" , 44, 1, 367, "R/W", 0, 0, 0ull, 0ull},
- {"P1_BMODE" , 45, 1, 367, "R/W", 0, 0, 0ull, 0ull},
- {"P2_BMODE" , 46, 1, 367, "R/W", 0, 0, 0ull, 0ull},
- {"P3_BMODE" , 47, 1, 367, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 48, 1, 367, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 367, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 368, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 2, 368, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_63_63" , 63, 1, 368, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 369, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 3, 369, "RO", 0, 0, 0ull, 0ull},
- {"AVAIL" , 0, 32, 370, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 6, 370, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 370, "RAZ", 1, 1, 0, 0},
- {"AVAIL" , 0, 32, 371, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 5, 371, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 371, "RAZ", 1, 1, 0, 0},
- {"RD_BRST" , 0, 7, 372, "R/W", 0, 0, 17ull, 64ull},
- {"WR_BRST" , 7, 7, 372, "R/W", 0, 0, 16ull, 64ull},
- {"RESERVED_14_63" , 14, 50, 372, "RAZ", 1, 1, 0, 0},
- {"PARK_DEV" , 0, 3, 373, "R/W", 0, 1, 0ull, 0},
- {"PARK_MOD" , 3, 1, 373, "R/W", 0, 1, 0ull, 0},
- {"EN" , 4, 1, 373, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 373, "RAZ", 1, 1, 0, 0},
- {"PCI_OVR" , 8, 4, 373, "R/W", 0, 1, 0ull, 0},
- {"HOSTMODE" , 12, 1, 373, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 373, "RAZ", 1, 1, 0, 0},
- {"CMD_SIZE" , 0, 11, 374, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_11_63" , 11, 53, 374, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 375, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 375, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 375, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 375, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 375, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 375, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 375, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 375, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 375, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 376, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 376, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 376, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 376, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 376, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 376, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 376, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 376, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 376, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 376, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 376, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 376, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 376, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 377, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 377, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 377, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 377, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 377, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 377, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 377, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 377, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 377, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 378, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 378, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 378, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 378, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 378, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 378, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 378, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 378, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 378, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 378, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 378, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 378, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 378, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 4, 379, "R/W", 0, 0, 15ull, 15ull},
- {"BP_ON" , 4, 4, 379, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 379, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"NPI" , 3, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_8" , 8, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_13" , 13, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_14" , 14, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_15" , 15, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"LMC" , 17, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_21" , 21, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"ASX0" , 22, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"ASX1" , 23, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_24" , 24, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_25" , 25, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_26" , 26, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_27" , 27, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_28" , 28, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_29" , 29, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RINT_31" , 31, 1, 380, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 380, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 32, 381, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 381, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 382, "R/W", 0, 0, 0ull, 131072ull},
- {"RESERVED_32_63" , 32, 32, 382, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 383, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 383, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 383, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 383, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 383, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 384, "RO", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 384, "RO", 0, 0, 64ull, 64ull},
- {"ISAE" , 0, 1, 385, "RO", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 385, "R/W", 0, 0, 0ull, 1ull},
- {"ME" , 2, 1, 385, "R/W", 0, 0, 0ull, 1ull},
- {"SCSE" , 3, 1, 385, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 385, "R/W", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 385, "RO", 0, 0, 0ull, 0ull},
- {"PEE" , 6, 1, 385, "R/W", 0, 0, 0ull, 1ull},
- {"ADS" , 7, 1, 385, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 385, "R/W", 0, 0, 0ull, 1ull},
- {"FBBE" , 9, 1, 385, "R/W", 0, 0, 0ull, 1ull},
- {"I_DIS" , 10, 1, 385, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 385, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 385, "RO", 0, 0, 0ull, 0ull},
- {"CLE" , 20, 1, 385, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 385, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_22" , 22, 1, 385, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 385, "RO", 0, 1, 1ull, 0},
- {"MDPE" , 24, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 385, "RO", 0, 0, 1ull, 1ull},
- {"STA" , 27, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 386, "RO", 0, 0, 0ull, 0ull},
- {"CC" , 8, 24, 386, "RO", 0, 0, 733184ull, 733184ull},
- {"CLS" , 0, 8, 387, "R/W", 0, 1, 0ull, 0},
- {"LT" , 8, 8, 387, "R/W", 0, 0, 0ull, 64ull},
- {"HT" , 16, 8, 387, "RO", 0, 0, 0ull, 0ull},
- {"BCOD" , 24, 4, 387, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_29" , 28, 2, 387, "RAZ", 1, 1, 0, 0},
- {"BRB" , 30, 1, 387, "R/W", 0, 0, 0ull, 0ull},
- {"BCAP" , 31, 1, 387, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 388, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 388, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 388, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 8, 388, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 12, 20, 388, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 389, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 390, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 390, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 390, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 23, 390, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 27, 5, 390, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 391, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 392, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 392, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 392, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 28, 392, "RO", 0, 0, 0ull, 0ull},
- {"HBASEZ" , 0, 7, 393, "RO", 0, 0, 0ull, 0ull},
- {"HBASE" , 7, 25, 393, "R/W", 0, 1, 0ull, 0},
- {"CISP" , 0, 32, 394, "RO", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 395, "RO", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 395, "RO", 0, 0, 1ull, 1ull},
- {"ERBAR_EN" , 0, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_10" , 1, 10, 396, "RAZ", 1, 1, 0, 0},
- {"ERBARZ" , 11, 5, 396, "RO", 0, 0, 0ull, 0ull},
- {"ERBAR" , 16, 16, 396, "R/W", 0, 1, 0ull, 0},
- {"CP" , 0, 8, 397, "RO", 0, 0, 224ull, 224ull},
- {"RESERVED_8_31" , 8, 24, 397, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 398, "R/W", 0, 1, 0ull, 0},
- {"INTA" , 8, 8, 398, "RO", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 398, "RO", 0, 0, 64ull, 64ull},
- {"ML" , 24, 8, 398, "RO", 0, 0, 64ull, 64ull},
- {"MLTD" , 0, 1, 399, "R/W", 0, 0, 0ull, 1ull},
- {"TSWC" , 1, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 399, "RAZ", 1, 1, 0, 0},
- {"DPPMR" , 3, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"PBE" , 4, 12, 399, "R/W", 0, 0, 0ull, 0ull},
- {"TILT" , 16, 4, 399, "R/W", 0, 0, 0ull, 0ull},
- {"TSLTE" , 20, 3, 399, "R/W", 0, 0, 0ull, 0ull},
- {"TMAE" , 23, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"TWTAE" , 24, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEN" , 25, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEI" , 26, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"TRTAE" , 27, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"TRDRS" , 28, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RDSATI" , 29, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"TRDARD" , 30, 1, 399, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRDNPR" , 31, 1, 399, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSCME" , 0, 32, 400, "R/W1C", 0, 1, 0ull, 0},
- {"TDSRPS" , 0, 32, 401, "R/W1C", 0, 0, 0ull, 0ull},
- {"TDOMC" , 0, 5, 402, "R/W", 0, 0, 1ull, 1ull},
- {"TIDOMC" , 5, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 402, "RAZ", 1, 1, 0, 0},
- {"TIBDE" , 7, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"TIBCD" , 8, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_10" , 9, 2, 402, "RAZ", 1, 1, 0, 0},
- {"TMAPES" , 11, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMDPES" , 12, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMSE" , 13, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMEI" , 14, 1, 402, "RO", 0, 0, 0ull, 0ull},
- {"TECI" , 15, 1, 402, "RO", 0, 0, 0ull, 0ull},
- {"TMES" , 16, 8, 402, "RO", 0, 0, 0ull, 0ull},
- {"MDRRMC" , 24, 3, 402, "R/W", 0, 0, 2ull, 2ull},
- {"MDRIMC" , 27, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"MDRE" , 28, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"MDWE" , 29, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCI" , 30, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCM" , 31, 1, 402, "R/W", 0, 0, 1ull, 1ull},
- {"MDSP" , 0, 32, 403, "R/W1C", 0, 1, 0ull, 0},
- {"SCMRE" , 0, 32, 404, "R/W1C", 0, 1, 0ull, 0},
- {"MTTV" , 0, 8, 405, "R/W", 0, 0, 0ull, 0ull},
- {"MRV" , 8, 8, 405, "R/W", 0, 0, 0ull, 255ull},
- {"MTTA" , 16, 1, 405, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRA" , 17, 1, 405, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLUSH" , 18, 1, 405, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_19_24" , 19, 6, 405, "RAZ", 1, 1, 0, 0},
- {"MAC" , 25, 7, 405, "R/W", 0, 0, 0ull, 0ull},
- {"PXCID" , 0, 8, 406, "RO", 0, 0, 7ull, 7ull},
- {"NCP" , 8, 8, 406, "RO", 0, 0, 232ull, 232ull},
- {"DPERE" , 16, 1, 406, "R/W", 0, 0, 0ull, 0ull},
- {"ROE" , 17, 1, 406, "R/W", 0, 0, 1ull, 1ull},
- {"MMBC" , 18, 2, 406, "R/W", 0, 0, 0ull, 0ull},
- {"MOST" , 20, 3, 406, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_23_31" , 23, 9, 406, "RAZ", 1, 1, 0, 0},
- {"FN" , 0, 3, 407, "RO", 0, 0, 0ull, 0ull},
- {"DN" , 3, 5, 407, "RO", 0, 0, 31ull, 31ull},
- {"BN" , 8, 8, 407, "RO", 0, 1, 17ull, 0},
- {"W64" , 16, 1, 407, "RO", 0, 0, 1ull, 1ull},
- {"M133" , 17, 1, 407, "RO", 0, 0, 1ull, 1ull},
- {"SCD" , 18, 1, 407, "R/W1C", 0, 1, 0ull, 0},
- {"USC" , 19, 1, 407, "R/W1C", 0, 1, 0ull, 0},
- {"DC" , 20, 1, 407, "RO", 0, 0, 0ull, 0ull},
- {"MMRBCD" , 21, 2, 407, "RO", 0, 0, 2ull, 2ull},
- {"MOSTD" , 23, 3, 407, "RO", 0, 0, 3ull, 3ull},
- {"MCRSD" , 26, 3, 407, "RO", 0, 0, 7ull, 7ull},
- {"SCEMR" , 29, 1, 407, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 407, "RAZ", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 408, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 408, "RO", 0, 0, 240ull, 240ull},
- {"PCIMIV" , 16, 3, 408, "RO", 0, 0, 2ull, 2ull},
- {"PMEC" , 19, 1, 408, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 408, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 408, "RO", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 408, "RO", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 408, "RO", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 408, "RO", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 408, "RO", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 409, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 409, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 409, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 409, "R/W", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 409, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 409, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 409, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEN" , 23, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 409, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 410, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 410, "RO", 0, 0, 0ull, 0ull},
- {"MSIEN" , 16, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 410, "RO", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 410, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 410, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 410, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 411, "RAZ", 1, 1, 0, 0},
- {"MSI31T2" , 2, 30, 411, "R/W", 0, 1, 0ull, 0},
- {"MSI" , 0, 32, 412, "R/W", 0, 1, 0ull, 0},
- {"MSIMD" , 0, 16, 413, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 413, "RAZ", 1, 1, 0, 0},
- {"PCICNT" , 0, 32, 414, "R/W", 0, 1, 0ull, 0},
- {"AP_SPEED" , 32, 2, 414, "RO", 1, 1, 0, 0},
- {"AP_PCIX" , 34, 1, 414, "RO", 1, 1, 0, 0},
- {"HM_SPEED" , 35, 2, 414, "RO", 0, 1, 0ull, 0},
- {"HM_PCIX" , 37, 1, 414, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 414, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 415, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 415, "R/W", 0, 0, 0ull, 1ull},
- {"TSR_HWM" , 4, 3, 415, "R/W", 0, 1, 1ull, 0},
- {"PMO_FPC" , 7, 3, 415, "R/W", 0, 0, 0ull, 0ull},
- {"PMO_AMOD" , 10, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"B12_BIST" , 11, 1, 415, "RO", 0, 0, 0ull, 0ull},
- {"AP_64AD" , 12, 1, 415, "RO", 0, 1, 0ull, 0},
- {"AP_PCIX" , 13, 1, 415, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_14" , 14, 1, 415, "RAZ", 0, 0, 0ull, 0ull},
- {"EN_WFILT" , 15, 1, 415, "R/W", 0, 0, 0ull, 1ull},
- {"SCM" , 16, 1, 415, "RO", 0, 1, 0ull, 0},
- {"SCMTYP" , 17, 1, 415, "RO", 0, 1, 0ull, 0},
- {"BAR2PRES" , 18, 1, 415, "R/W", 1, 1, 0, 0},
- {"ERST_N" , 19, 1, 415, "RO", 0, 0, 1ull, 1ull},
- {"BB0" , 20, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BB1" , 21, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BB_ES" , 22, 2, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BB_CA" , 24, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BB1_SIZ" , 25, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BB1_HOLE" , 26, 3, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 415, "RAZ", 1, 1, 0, 0},
- {"INC_VAL" , 0, 16, 416, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 416, "RAZ", 1, 1, 0, 0},
- {"DMA_CNT" , 0, 32, 417, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 418, "R/W", 0, 1, 0ull, 0},
- {"DMA_TIME" , 0, 32, 419, "R/W", 0, 1, 0ull, 0},
- {"ICNT" , 0, 32, 420, "R/W1C", 0, 0, 0ull, 0ull},
- {"ITR_WABT" , 0, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IMR_WABT" , 1, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IMR_WTTO" , 2, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"ITR_ABT" , 3, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IMR_ABT" , 4, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IMR_TTO" , 5, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IMSI_PER" , 6, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IMSI_TABT" , 7, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IMSI_MABT" , 8, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IMSC_MSG" , 9, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"ITSR_ABT" , 10, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"ISERR" , 11, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IAPERR" , 12, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IDPERR" , 13, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IRSL_INT" , 16, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IPCNT0" , 17, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IPCNT1" , 18, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IPCNT2" , 19, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IPCNT3" , 20, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IPTIME0" , 21, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IPTIME1" , 22, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IPTIME2" , 23, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IPTIME3" , 24, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IDCNT0" , 25, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IDCNT1" , 26, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IDTIME0" , 27, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"IDTIME1" , 28, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 421, "RAZ", 1, 1, 0, 0},
- {"RTR_WABT" , 0, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RMR_WABT" , 1, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RMR_WTTO" , 2, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RTR_ABT" , 3, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RMR_ABT" , 4, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RMR_TTO" , 5, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RMSI_PER" , 6, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RMSI_TABT" , 7, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RMSI_MABT" , 8, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RMSC_MSG" , 9, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RTSR_ABT" , 10, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RSERR" , 11, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RAPERR" , 12, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RDPERR" , 13, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RRSL_INT" , 16, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RPCNT0" , 17, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RPCNT1" , 18, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RPCNT2" , 19, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RPCNT3" , 20, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RPTIME0" , 21, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RPTIME1" , 22, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RPTIME2" , 23, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RPTIME3" , 24, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RDCNT0" , 25, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RDCNT1" , 26, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RDTIME0" , 27, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RDTIME1" , 28, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 422, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 422, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 423, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT2" , 19, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT3" , 20, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME2" , 23, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME3" , 24, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 423, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 424, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT2" , 19, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT3" , 20, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME2" , 23, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME3" , 24, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 424, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 6, 425, "WO", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 425, "R/W", 1, 1, 0, 0},
- {"PTR_CNT" , 0, 16, 426, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 16, 16, 426, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 0, 32, 427, "RO", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
- {"PKT_TIME" , 0, 32, 429, "R/W", 0, 1, 0ull, 0},
- {"PREFETCH" , 0, 3, 430, "R/W", 0, 0, 0ull, 2ull},
- {"MIN_DATA" , 3, 6, 430, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_9_31" , 9, 23, 430, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 431, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 431, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 431, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 432, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 432, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 432, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 31, 433, "R/W", 0, 0, 10000ull, 10000ull},
- {"ENB" , 31, 1, 433, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 433, "RAZ", 1, 1, 0, 0},
- {"SCM" , 0, 32, 434, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 434, "RAZ", 1, 1, 0, 0},
- {"TSR" , 0, 36, 435, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 435, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 436, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 3, 45, 436, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 436, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 436, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 437, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 438, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 438, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 438, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 438, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 439, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 440, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 440, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 441, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 441, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 441, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 441, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 441, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 18, 442, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 442, "RAZ", 1, 1, 0, 0},
- {"REFLECT" , 0, 1, 443, "R/W", 0, 0, 1ull, 1ull},
- {"INVRES" , 1, 1, 443, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 443, "RAZ", 1, 1, 0, 0},
- {"IV" , 0, 32, 444, "R/W", 0, 0, 1185899593ull, 1185899593ull},
- {"RESERVED_32_63" , 32, 32, 444, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 445, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 445, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 445, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 445, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 446, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 446, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 446, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 446, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 446, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 446, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 446, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 446, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 447, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 447, "RAZ", 0, 1, 0ull, 0},
- {"L4_MAL" , 8, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 447, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 447, "RAZ", 0, 0, 0ull, 0ull},
- {"PKTDRP" , 0, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 448, "RAZ", 1, 1, 0, 0},
- {"PUNYERR" , 12, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 448, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 449, "RAZ", 1, 1, 0, 0},
- {"PUNYERR" , 12, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 449, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 450, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 450, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 451, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 451, "RAZ", 1, 1, 0, 0},
- {"CRC_EN" , 12, 1, 451, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_15" , 13, 3, 451, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 451, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT" , 20, 4, 451, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 451, "RAZ", 1, 1, 0, 0},
- {"GRP_WAT" , 28, 4, 451, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 451, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 452, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 452, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 452, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 452, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 452, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 452, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 452, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 452, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 452, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 453, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 453, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 454, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 455, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 2, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 455, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 455, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 455, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 455, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 456, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 456, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 457, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 457, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 458, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 458, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 459, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 459, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 460, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 460, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 461, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 461, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 462, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 462, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 463, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 463, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 464, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 464, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 465, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 465, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 466, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 466, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 467, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 467, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 468, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 468, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 469, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 469, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 470, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 470, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 471, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 471, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 472, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 472, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 473, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 473, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 474, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 474, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 474, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 475, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 475, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 475, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 476, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 476, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 477, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 477, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 478, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 478, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 478, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 478, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 479, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 479, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 479, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 479, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 479, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 480, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 480, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 480, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 480, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 481, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 481, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 481, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 481, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 481, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 481, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 481, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 481, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 0, 16, 482, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 482, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 482, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 482, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 483, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 483, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 483, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 483, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 483, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 484, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 484, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 484, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 484, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 484, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 485, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 486, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 486, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 486, "RO", 1, 0, 0, 0ull},
- {"QID_BASE" , 6, 8, 486, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 14, 4, 486, "RO", 1, 0, 0, 0ull},
- {"QID_OFF_MAX" , 18, 4, 486, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 22, 5, 486, "RO", 1, 0, 0, 0ull},
- {"QOS" , 27, 3, 486, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 30, 1, 486, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 31, 1, 486, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 32, 1, 486, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 33, 1, 486, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 34, 1, 486, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 35, 1, 486, "RO", 1, 0, 0, 0ull},
- {"UID" , 36, 3, 486, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 39, 6, 486, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 45, 16, 486, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 61, 3, 486, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 0, 3, 487, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 3, 16, 487, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 19, 16, 487, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 35, 29, 487, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 0, 11, 488, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 488, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 489, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 489, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 489, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 489, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 489, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 489, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 490, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 490, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 490, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 490, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 490, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 490, "RO", 1, 0, 0, 0ull},
- {"RESERVED_28_63" , 28, 36, 490, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 491, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 491, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 491, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 491, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 492, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 492, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 492, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 492, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 492, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 492, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 492, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 492, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 492, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 493, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 493, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 493, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 493, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 493, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 494, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 4, 494, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 494, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 494, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 494, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 6, 494, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 21, 1, 494, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 22, 3, 494, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 25, 1, 494, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 26, 1, 494, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 27, 3, 494, "RO", 1, 0, 0, 0ull},
- {"OUT_CRC" , 30, 1, 494, "RO", 1, 0, 0, 0ull},
- {"IOB" , 31, 1, 494, "RO", 1, 0, 0, 0ull},
- {"CSR" , 32, 1, 494, "RO", 1, 0, 0, 0ull},
- {"RESERVED_33_63" , 33, 31, 494, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 495, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 495, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 495, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 495, "RAZ", 1, 1, 0, 0},
- {"REFIN" , 0, 1, 496, "R/W", 0, 0, 1ull, 1ull},
- {"INVRES" , 1, 1, 496, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 496, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 32, 497, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 497, "RAZ", 1, 1, 0, 0},
- {"IV" , 0, 32, 498, "R/W", 0, 0, 1185899593ull, 1185899593ull},
- {"RESERVED_32_63" , 32, 32, 498, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 499, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 500, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 501, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 502, "RO", 0, 0, 0ull, 0ull},
- {"PARITY" , 0, 1, 503, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 503, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 503, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 503, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 504, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 504, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 505, "R/W", 0, 0, 0ull, 0ull},
- {"MODE1" , 3, 3, 505, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 505, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 506, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 507, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 507, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 508, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 509, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 509, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 509, "RAZ", 1, 1, 0, 0},
- {"ADR0" , 0, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"ADR1" , 1, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"PEND0" , 2, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"PEND1" , 3, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 4, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 5, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 6, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 7, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 8, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 9, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 510, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 16, 510, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 510, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 511, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 511, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 512, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 512, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 512, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 512, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 512, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 512, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 513, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 513, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 514, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 514, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 515, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 515, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 12, 516, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 516, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 517, "R/W", 0, 0, 0ull, 1023ull},
- {"RESERVED_10_63" , 10, 54, 517, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 518, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 518, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 519, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 519, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 519, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 519, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 519, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 519, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 519, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 519, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 519, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 519, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 520, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 520, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 520, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 520, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 520, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 11, 521, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 521, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 11, 521, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_23_23" , 23, 1, 521, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 12, 521, "RO", 0, 1, 2027ull, 0},
- {"BUF_CNT" , 36, 12, 521, "RO", 0, 1, 0ull, 0},
- {"DES_CNT" , 48, 12, 521, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 521, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 522, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 522, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 523, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 523, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 524, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 524, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 525, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 525, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 525, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 12, 526, "RO", 0, 1, 0ull, 0},
- {"DS_CNT" , 12, 12, 526, "RO", 0, 1, 0ull, 0},
- {"TC_CNT" , 24, 4, 526, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 526, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 527, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 527, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 527, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 527, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 527, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 11, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 528, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 11, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 528, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 528, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 528, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 529, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 529, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 530, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 531, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 531, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 532, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 532, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 532, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 532, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 532, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 532, "RAZ", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 532, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 532, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 533, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 533, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 533, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 533, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 1, 533, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 533, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 534, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 534, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 535, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 535, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 535, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 535, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 536, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 536, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 536, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 536, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 537, "RAZ", 0, 0, 0ull, 0ull},
- {"STAT0" , 0, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"STAT1" , 1, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"STAT2" , 2, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 538, "RAZ", 0, 0, 0ull, 0ull},
- {"SRXDLCK" , 0, 1, 539, "R/W", 0, 0, 0ull, 1ull},
- {"RCVTRN" , 1, 1, 539, "R/W", 0, 0, 0ull, 1ull},
- {"DRPTRN" , 2, 1, 539, "R/W", 0, 0, 0ull, 1ull},
- {"SNDTRN" , 3, 1, 539, "R/W", 0, 0, 0ull, 1ull},
- {"STATRCV" , 4, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"STATDRV" , 5, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"RUNBIST" , 6, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"CLKDLY" , 7, 5, 539, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_12_15" , 12, 4, 539, "RAZ", 0, 0, 0ull, 0ull},
- {"SEETRN" , 16, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 539, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 540, "RAZ", 0, 1, 0ull, 0},
- {"D4CLK0" , 4, 1, 540, "R/W1C", 0, 1, 0ull, 0},
- {"D4CLK1" , 5, 1, 540, "R/W1C", 0, 1, 0ull, 0},
- {"S4CLK0" , 6, 1, 540, "R/W1C", 0, 1, 0ull, 0},
- {"S4CLK1" , 7, 1, 540, "R/W1C", 0, 1, 0ull, 0},
- {"SRXTRN" , 8, 1, 540, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_9_9" , 9, 1, 540, "RAZ", 0, 1, 0ull, 0},
- {"STXCAL" , 10, 1, 540, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 540, "RAZ", 0, 0, 0ull, 0ull},
- {"DLLDIS" , 0, 1, 541, "R/W", 1, 0, 0, 0ull},
- {"DLLFRC" , 1, 1, 541, "WR0", 1, 0, 0, 0ull},
- {"OFFDLY" , 2, 6, 541, "R/W", 1, 0, 0, 0ull},
- {"BITSEL" , 8, 5, 541, "R/W", 1, 1, 0, 0},
- {"OFFSET" , 13, 5, 541, "R/W", 1, 1, 0, 0},
- {"MUX" , 18, 1, 541, "WR0", 1, 1, 0, 0},
- {"INC" , 19, 1, 541, "WR0", 1, 1, 0, 0},
- {"DEC" , 20, 1, 541, "WR0", 1, 1, 0, 0},
- {"CLRDLY" , 21, 1, 541, "WR0", 1, 1, 0, 0},
- {"RESERVED_22_23" , 22, 2, 541, "RAZ", 0, 0, 0ull, 0ull},
- {"SSTEP" , 24, 1, 541, "R/W", 1, 0, 0, 0ull},
- {"SSTEP_GO" , 25, 1, 541, "WR0", 1, 1, 0, 0},
- {"RESERVED_26_27" , 26, 2, 541, "RAZ", 0, 0, 0ull, 0ull},
- {"FALL8" , 28, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"FALLNOP" , 29, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 541, "RAZ", 0, 0, 0ull, 0ull},
- {"OFFSET" , 0, 5, 542, "RO", 0, 1, 0ull, 0},
- {"MUXSEL" , 5, 2, 542, "RO", 0, 1, 0ull, 0},
- {"UNXTERM" , 7, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"TESTRES" , 8, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 542, "RAZ", 0, 0, 0ull, 0ull},
- {"SRX4CMP" , 0, 10, 543, "R/W", 0, 0, 239ull, 239ull},
- {"RESERVED_10_15" , 10, 6, 543, "RAZ", 0, 0, 0ull, 0ull},
- {"STX4PCMP" , 16, 4, 543, "R/W", 0, 1, 3ull, 0},
- {"STX4NCMP" , 20, 4, 543, "R/W", 0, 1, 12ull, 0},
- {"RESERVED_24_63" , 24, 40, 543, "RAZ", 0, 0, 0ull, 0ull},
- {"ERRCNT" , 0, 4, 544, "R/W", 0, 0, 0ull, 3ull},
- {"RESERVED_4_5" , 4, 2, 544, "RAZ", 0, 0, 0ull, 0ull},
- {"DIPPAY" , 6, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"DIPCLS" , 7, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 8, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 544, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT" , 0, 8, 545, "RO", 0, 0, 0ull, 0ull},
- {"RSVOP" , 8, 4, 545, "RO", 0, 0, 0ull, 0ull},
- {"CALBNK" , 12, 2, 545, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_30" , 14, 17, 545, "RAZ", 0, 0, 0ull, 0ull},
- {"MUL" , 31, 1, 545, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 545, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 546, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 546, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 547, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_30" , 12, 19, 547, "RAZ", 0, 0, 0ull, 0ull},
- {"SPF" , 31, 1, 547, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 547, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 0, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"ABNORM" , 1, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 548, "RAZ", 0, 0, 0ull, 0ull},
- {"SPIOVR" , 4, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"CLSERR" , 5, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"DRWNNG" , 6, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 7, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"TPAOVR" , 8, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 9, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 10, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"CALERR" , 11, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 548, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 549, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 549, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX" , 0, 32, 550, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 550, "RAZ", 0, 0, 0ull, 0ull},
- {"PRTSEL" , 0, 4, 551, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 551, "RAZ", 0, 0, 0ull, 0ull},
- {"MUX_EN" , 0, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"MACRO_EN" , 1, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"MAXDIST" , 2, 5, 552, "R/W", 0, 0, 0ull, 8ull},
- {"SET_BOOT" , 7, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"CLR_BOOT" , 8, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"JITTER" , 9, 3, 552, "R/W", 0, 0, 0ull, 1ull},
- {"TRNTEST" , 12, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 552, "RAZ", 0, 0, 0ull, 0ull},
- {"INF_EN" , 0, 1, 553, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_2" , 1, 2, 553, "RAZ", 0, 0, 0ull, 0ull},
- {"ST_EN" , 3, 1, 553, "R/W", 0, 0, 0ull, 1ull},
- {"PRTS" , 4, 4, 553, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 553, "RAZ", 0, 0, 0ull, 0ull},
- {"IGNORE" , 0, 16, 554, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 554, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT0" , 0, 4, 555, "R/W", 1, 1, 0, 0},
- {"PRT1" , 4, 4, 555, "R/W", 1, 1, 0, 0},
- {"PRT2" , 8, 4, 555, "R/W", 1, 1, 0, 0},
- {"PRT3" , 12, 4, 555, "R/W", 1, 1, 0, 0},
- {"ODDPAR" , 16, 1, 555, "R/W", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 555, "RAZ", 0, 0, 0ull, 0ull},
- {"LEN" , 0, 7, 556, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 556, "RAZ", 0, 0, 0ull, 0ull},
- {"M" , 8, 8, 556, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 556, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 4, 557, "R/W", 0, 0, 0ull, 0ull},
- {"OPC" , 4, 4, 557, "R/W", 0, 0, 0ull, 0ull},
- {"MOD" , 8, 4, 557, "R/W", 0, 0, 0ull, 0ull},
- {"SOP" , 12, 1, 557, "R/W", 0, 0, 0ull, 0ull},
- {"EOP" , 13, 1, 557, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 557, "RAZ", 0, 0, 0ull, 0ull},
- {"DAT" , 0, 64, 558, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_2" , 0, 3, 559, "R/W", 0, 0, 0ull, 0ull},
- {"IGNTPA" , 3, 1, 559, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 559, "R/W", 0, 0, 0ull, 0ull},
- {"MINTRN" , 5, 1, 559, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 559, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 560, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 560, "RAZ", 0, 0, 0ull, 0ull},
- {"INF_EN" , 0, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_2" , 1, 2, 561, "RAZ", 0, 0, 0ull, 0ull},
- {"ST_EN" , 3, 1, 561, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 561, "RAZ", 0, 0, 0ull, 0ull},
- {"DIPMAX" , 0, 4, 562, "R/W", 0, 0, 0ull, 0ull},
- {"FRMMAX" , 4, 4, 562, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 562, "RAZ", 0, 0, 0ull, 0ull},
- {"IGNTPA" , 0, 16, 563, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 563, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 564, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNCERR" , 8, 1, 565, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 565, "RAZ", 0, 0, 0ull, 0ull},
- {"CALPAR0" , 0, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"CALPAR1" , 1, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"OVRBST" , 2, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"DATOVR" , 3, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"DIPERR" , 4, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"NOSYNC" , 5, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"UNXFRM" , 6, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"FRMERR" , 7, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 566, "RAZ", 0, 0, 0ull, 0ull},
- {"MINB" , 0, 9, 567, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 567, "RAZ", 0, 0, 0ull, 0ull},
- {"PRT0" , 0, 4, 568, "R/W", 1, 1, 0, 0},
- {"PRT1" , 4, 4, 568, "R/W", 1, 1, 0, 0},
- {"PRT2" , 8, 4, 568, "R/W", 1, 1, 0, 0},
- {"PRT3" , 12, 4, 568, "R/W", 1, 1, 0, 0},
- {"ODDPAR" , 16, 1, 568, "R/W", 1, 1, 0, 0},
- {"RESERVED_17_63" , 17, 47, 568, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_T" , 0, 16, 569, "R/W", 0, 1, 0ull, 0},
- {"ALPHA" , 16, 16, 569, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 569, "RAZ", 0, 0, 0ull, 0ull},
- {"LEN" , 0, 7, 570, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 570, "RAZ", 0, 0, 0ull, 0ull},
- {"M" , 8, 8, 570, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 570, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 571, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 571, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 572, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 572, "RAZ", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 0, 4, 573, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 4, 1, 573, "WR0", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 573, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 32, 574, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 574, "RAZ", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 0, 22, 575, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 575, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 575, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 575, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 575, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 575, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 576, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 576, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 576, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 577, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 577, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 577, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 577, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 577, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 578, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 578, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 578, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 579, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 579, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 579, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 579, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 579, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 580, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 580, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 580, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 580, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 581, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 582, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 582, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 583, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 583, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 584, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 584, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 584, "RAZ", 1, 1, 0, 0},
- {"TDF0" , 0, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"TDF1" , 1, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"TCF" , 2, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 585, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 586, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 586, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 586, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 586, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 587, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 587, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 587, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 588, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 588, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 588, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 588, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 588, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 589, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 589, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 590, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 590, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 591, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 591, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 592, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 592, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 592, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 592, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 592, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 592, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 592, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 592, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 592, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 592, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 592, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 592, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 593, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 593, "RAZ", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 594, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 594, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 594, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 594, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 594, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 595, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 596, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 596, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 597, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 598, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 598, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 599, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 599, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 599, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 599, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 599, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 599, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 599, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 599, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 599, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 599, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 599, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 599, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 600, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 600, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 601, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 601, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 602, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 602, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 603, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 604, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 604, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 604, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 604, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 604, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 604, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 604, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 604, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 604, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 604, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 604, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 604, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 605, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 605, "RAZ", 0, 0, 0ull, 0ull},
- {"ZIP_CTL" , 0, 4, 606, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 27, 606, "RO", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 606, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 607, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 607, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 607, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 607, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 607, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 608, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 608, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 609, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 609, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 609, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 609, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 609, "RO", 0, 0, 31744ull, 31744ull},
- {"RESERVED_48_63" , 48, 16, 609, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 14, 610, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 610, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 611, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 611, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 612, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xxp1[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 11, 0},
- {"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 11},
- {"cvmx_agl_gmx_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 13},
- {"cvmx_agl_gmx_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 3, 19},
- {"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 7, 22},
- {"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 1, 29},
- {"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 30},
- {"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 7, 1, 31},
- {"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 32},
- {"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 1, 33},
- {"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 34},
- {"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 11, 2, 35},
- {"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 4, 37},
- {"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 2, 41},
- {"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 10, 43},
- {"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 15, 11, 53},
- {"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 64},
- {"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 17, 2, 66},
- {"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 68},
- {"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 19, 19, 70},
- {"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 19, 89},
- {"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 21, 2, 108},
- {"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 110},
- {"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 23, 2, 112},
- {"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 114},
- {"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 25, 2, 116},
- {"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 118},
- {"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 27, 2, 120},
- {"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 122},
- {"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 29, 2, 124},
- {"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 126},
- {"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 31, 2, 128},
- {"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 130},
- {"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 33, 4, 132},
- {"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 136},
- {"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 35, 2, 138},
- {"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 2, 140},
- {"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 37, 4, 142},
- {"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 4, 146},
- {"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 39, 2, 150},
- {"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 3, 152},
- {"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 41, 5, 155},
- {"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 3, 160},
- {"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 43, 2, 163},
- {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 165},
- {"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 45, 2, 167},
- {"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 169},
- {"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 47, 2, 171},
- {"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 173},
- {"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 49, 2, 175},
- {"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 177},
- {"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 51, 2, 179},
- {"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 181},
- {"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 53, 2, 183},
- {"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 185},
- {"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 55, 2, 187},
- {"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 189},
- {"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 57, 2, 191},
- {"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 193},
- {"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 59, 2, 195},
- {"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 197},
- {"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 61, 2, 199},
- {"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 201},
- {"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 63, 3, 203},
- {"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 10, 206},
- {"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 10, 216},
- {"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 226},
- {"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 2, 228},
- {"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 6, 230},
- {"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 69, 2, 236},
- {"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 70, 2, 238},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 71, 2, 240},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 72, 2, 242},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 73, 2, 244},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 74, 2, 246},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 75, 21, 248},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 100, 2, 269},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 125, 21, 271},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 137, 2, 292},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 149, 21, 294},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 174, 21, 315},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 2, 336},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 187, 2, 338},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 199, 2, 340},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 211, 2, 342},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 212, 2, 344},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 213, 2, 346},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 214, 1, 348},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 226, 3, 349},
- {"cvmx_ciu_qlm_dcok" , CVMX_CSR_DB_TYPE_NCB, 64, 227, 2, 352},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 228, 5, 354},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 229, 6, 359},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 230, 2, 365},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 231, 2, 367},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 232, 2, 369},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 233, 2, 371},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 234, 3, 373},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 238, 7, 376},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 250, 6, 383},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 251, 7, 389},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 3, 396},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 259, 2, 399},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 266, 3, 401},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 267, 2, 404},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 268, 29, 406},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 269, 29, 435},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 270, 2, 464},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 278, 2, 466},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 286, 3, 468},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 287, 3, 471},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 288, 2, 474},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 289, 2, 476},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 290, 7, 478},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 2, 485},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 294, 2, 487},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 296, 7, 489},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 298, 2, 496},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 10, 498},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 1, 508},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 316, 1, 509},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 324, 1, 510},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 332, 1, 511},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 340, 1, 512},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 348, 1, 513},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 356, 2, 514},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 364, 4, 516},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 372, 2, 520},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 380, 9, 522},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 10, 531},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 2, 541},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 25, 543},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 25, 568},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 420, 2, 593},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 428, 2, 595},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 2, 597},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 444, 2, 599},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 452, 2, 601},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 460, 2, 603},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 468, 2, 605},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 476, 2, 607},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 484, 2, 609},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 492, 2, 611},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 500, 2, 613},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 508, 2, 615},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 516, 4, 617},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 524, 2, 621},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 532, 2, 623},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 540, 2, 625},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 548, 4, 627},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 550, 2, 631},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 552, 5, 633},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 554, 2, 638},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 556, 2, 640},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 564, 3, 642},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 566, 5, 645},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 574, 2, 650},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 582, 3, 652},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 590, 2, 655},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 598, 2, 657},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 606, 2, 659},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 614, 2, 661},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 622, 2, 663},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 630, 2, 665},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 638, 2, 667},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 646, 2, 669},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 654, 2, 671},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 662, 2, 673},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 670, 2, 675},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 678, 2, 677},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 686, 2, 679},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 694, 2, 681},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 702, 2, 683},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 710, 2, 685},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 718, 2, 687},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 726, 2, 689},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 734, 2, 691},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 742, 2, 693},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 2, 695},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 752, 2, 697},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 754, 2, 699},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 756, 3, 701},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 8, 704},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 760, 8, 712},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 762, 2, 720},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 764, 2, 722},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 766, 6, 724},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 768, 2, 730},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 770, 2, 732},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 772, 2, 734},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 774, 9, 736},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 776, 3, 745},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 778, 9, 748},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 794, 2, 757},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 798, 2, 759},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 799, 2, 761},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 800, 2, 763},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 801, 2, 765},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 19, 767},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 6, 786},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 3, 792},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 805, 3, 795},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 3, 798},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 807, 5, 801},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 808, 5, 806},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 809, 1, 811},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 1, 812},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 811, 7, 813},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 7, 820},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 813, 3, 827},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 814, 3, 830},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 815, 3, 833},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 5, 836},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 817, 5, 841},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 818, 1, 846},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 819, 1, 847},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 3, 848},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 821, 3, 851},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 3, 854},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 823, 2, 857},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 824, 2, 859},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 825, 2, 861},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 826, 2, 863},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 827, 19, 865},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 828, 2, 884},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 829, 1, 886},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 830, 15, 887},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 831, 13, 902},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 832, 13, 915},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 833, 2, 928},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 834, 2, 930},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 835, 2, 932},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 836, 3, 934},
- {"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 844, 3, 937},
- {"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 848, 2, 940},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 852, 2, 942},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 860, 2, 944},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 956, 1, 946},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 959, 1, 947},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 962, 6, 948},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 963, 5, 954},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 964, 6, 959},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 965, 7, 965},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 966, 2, 972},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 974, 2, 974},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 975, 3, 976},
- {"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 976, 2, 979},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 977, 5, 981},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 985, 3, 986},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 986, 4, 989},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 987, 3, 993},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 988, 2, 996},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 989, 2, 998},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 4, 1000},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 991, 3, 1004},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 5, 1007},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 993, 5, 1012},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 994, 7, 1017},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 11, 1024},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 996, 8, 1035},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 997, 15, 1043},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 8, 1058},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 999, 5, 1066},
- {"cvmx_l2c_grpwrr0" , CVMX_CSR_DB_TYPE_RSL, 64, 1000, 2, 1071},
- {"cvmx_l2c_grpwrr1" , CVMX_CSR_DB_TYPE_RSL, 64, 1001, 2, 1073},
- {"cvmx_l2c_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1002, 10, 1075},
- {"cvmx_l2c_int_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 10, 1085},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 4, 1095},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1005, 2, 1099},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 14, 1101},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 1007, 19, 1115},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 1008, 3, 1134},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 1009, 3, 1137},
- {"cvmx_l2c_oob" , CVMX_CSR_DB_TYPE_RSL, 64, 1010, 3, 1140},
- {"cvmx_l2c_oob1" , CVMX_CSR_DB_TYPE_RSL, 64, 1011, 6, 1143},
- {"cvmx_l2c_oob2" , CVMX_CSR_DB_TYPE_RSL, 64, 1012, 6, 1149},
- {"cvmx_l2c_oob3" , CVMX_CSR_DB_TYPE_RSL, 64, 1013, 6, 1155},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1014, 2, 1161},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1018, 17, 1163},
- {"cvmx_l2c_ppgrp" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 13, 1180},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1020, 5, 1193},
- {"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1021, 5, 1198},
- {"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1022, 5, 1203},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 2, 1208},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 3, 1210},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 2, 1213},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 2, 1215},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 1217},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 7, 1219},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 5, 1226},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 3, 1231},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1031, 3, 1234},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1032, 2, 1237},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1033, 2, 1239},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1034, 2, 1241},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 6, 1243},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1036, 14, 1249},
- {"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1037, 2, 1263},
- {"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 2, 1265},
- {"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1039, 2, 1267},
- {"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 2, 1269},
- {"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1041, 2, 1271},
- {"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 2, 1273},
- {"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1043, 2, 1275},
- {"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 2, 1277},
- {"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1045, 2, 1279},
- {"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 2, 1281},
- {"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 2, 1283},
- {"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 2, 1285},
- {"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 2, 1287},
- {"cvmx_lmc#_bist_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 2, 1289},
- {"cvmx_lmc#_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1063, 8, 1291},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1065, 7, 1299},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1067, 19, 1306},
- {"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1069, 8, 1325},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1071, 2, 1333},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1073, 2, 1335},
- {"cvmx_lmc#_dclk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1075, 5, 1337},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1077, 18, 1342},
- {"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1079, 6, 1360},
- {"cvmx_lmc#_dll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1081, 5, 1366},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1083, 5, 1371},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1085, 5, 1376},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1087, 6, 1381},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1089, 2, 1387},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1091, 2, 1389},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1093, 14, 1391},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1095, 9, 1405},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1097, 2, 1414},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1099, 2, 1416},
- {"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1101, 12, 1418},
- {"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 6, 1430},
- {"cvmx_lmc#_read_level_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 7, 1436},
- {"cvmx_lmc#_read_level_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 4, 1443},
- {"cvmx_lmc#_read_level_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 11, 1447},
- {"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 6, 1458},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1119, 9, 1464},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1121, 5, 1473},
- {"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1123, 5, 1478},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1125, 5, 1483},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 1126, 3, 1488},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1127, 10, 1491},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 1130, 3, 1501},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 1133, 3, 1504},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1136, 15, 1507},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1139, 3, 1522},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1140, 3, 1525},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1141, 3, 1528},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1142, 5, 1531},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1144, 1, 1536},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 13, 1537},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1153, 13, 1550},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1161, 6, 1563},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1162, 1, 1569},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1166, 2, 1570},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 2, 1572},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 13, 1574},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 8, 1587},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 4, 1595},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 1, 1599},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 3, 1600},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1173, 2, 1603},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 1174, 6, 1605},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1175, 7, 1611},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 1176, 4, 1618},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1177, 2, 1622},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1178, 2, 1624},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1179, 13, 1626},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1181, 12, 1639},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1183, 3, 1651},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1185, 3, 1654},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1187, 2, 1657},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1189, 2, 1659},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1191, 2, 1661},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1193, 7, 1663},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1195, 2, 1670},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1197, 7, 1672},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1199, 4, 1679},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1201, 8, 1683},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1203, 9, 1691},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1205, 7, 1700},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1207, 9, 1707},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1209, 2, 1716},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1211, 2, 1718},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1213, 4, 1720},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1215, 2, 1724},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1217, 2, 1726},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1219, 2, 1728},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1221, 4, 1730},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1223, 2, 1734},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1225, 2, 1736},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1227, 2, 1738},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1229, 2, 1740},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1231, 2, 1742},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1233, 2, 1744},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1235, 6, 1746},
- {"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 1237, 5, 1752},
- {"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1238, 8, 1757},
- {"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 1239, 8, 1765},
- {"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1240, 2, 1773},
- {"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 1241, 3, 1775},
- {"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 1242, 5, 1778},
- {"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 1243, 4, 1783},
- {"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 1244, 8, 1787},
- {"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1245, 2, 1795},
- {"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 1246, 2, 1797},
- {"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 1247, 5, 1799},
- {"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 1248, 4, 1804},
- {"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1249, 4, 1808},
- {"cvmx_npei_bar1_index#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 1250, 5, 1812},
- {"cvmx_npei_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1282, 59, 1817},
- {"cvmx_npei_ctl_port0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1283, 17, 1876},
- {"cvmx_npei_ctl_port1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1284, 17, 1893},
- {"cvmx_npei_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1285, 6, 1910},
- {"cvmx_npei_ctl_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1286, 11, 1916},
- {"cvmx_npei_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1287, 5, 1927},
- {"cvmx_npei_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1288, 8, 1932},
- {"cvmx_npei_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1289, 2, 1940},
- {"cvmx_npei_dma#_counts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1290, 3, 1942},
- {"cvmx_npei_dma#_dbell" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 1295, 2, 1945},
- {"cvmx_npei_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1300, 3, 1947},
- {"cvmx_npei_dma#_naddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1305, 2, 1950},
- {"cvmx_npei_dma0_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1310, 2, 1952},
- {"cvmx_npei_dma1_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1311, 2, 1954},
- {"cvmx_npei_dma_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1312, 2, 1956},
- {"cvmx_npei_dma_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1313, 16, 1958},
- {"cvmx_npei_dma_state1_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1314, 11, 1974},
- {"cvmx_npei_dma_state2_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1315, 6, 1985},
- {"cvmx_npei_dma_state3_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1316, 5, 1991},
- {"cvmx_npei_dma_state4_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1317, 5, 1996},
- {"cvmx_npei_dma_state5_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1318, 3, 2001},
- {"cvmx_npei_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1319, 63, 2004},
- {"cvmx_npei_int_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1320, 62, 2067},
- {"cvmx_npei_int_info" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1321, 3, 2129},
- {"cvmx_npei_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1322, 60, 2132},
- {"cvmx_npei_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1323, 1, 2192},
- {"cvmx_npei_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1324, 1, 2193},
- {"cvmx_npei_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1325, 3, 2194},
- {"cvmx_npei_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1326, 11, 2197},
- {"cvmx_npei_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1342, 1, 2208},
- {"cvmx_npei_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1343, 1, 2209},
- {"cvmx_npei_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1344, 1, 2210},
- {"cvmx_npei_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1345, 1, 2211},
- {"cvmx_npei_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1346, 1, 2212},
- {"cvmx_npei_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1347, 1, 2213},
- {"cvmx_npei_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1348, 1, 2214},
- {"cvmx_npei_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1349, 1, 2215},
- {"cvmx_npei_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1350, 3, 2216},
- {"cvmx_npei_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1351, 3, 2219},
- {"cvmx_npei_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1352, 2, 2222},
- {"cvmx_npei_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1353, 3, 2224},
- {"cvmx_npei_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1354, 3, 2227},
- {"cvmx_npei_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1355, 3, 2230},
- {"cvmx_npei_rsl_int_blocks" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1356, 29, 2233},
- {"cvmx_npei_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1357, 1, 2262},
- {"cvmx_npei_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1358, 4, 2263},
- {"cvmx_npei_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1359, 7, 2267},
- {"cvmx_npei_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1360, 5, 2274},
- {"cvmx_npei_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1361, 4, 2279},
- {"cvmx_npei_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1362, 1, 2283},
- {"cvmx_npei_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1363, 4, 2284},
- {"cvmx_npei_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1364, 1, 2288},
- {"cvmx_npei_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 1365, 2, 2289},
- {"cvmx_npei_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1366, 2, 2291},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1367, 2, 2293},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1368, 24, 2295},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1369, 4, 2319},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1370, 5, 2323},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1371, 5, 2328},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1372, 2, 2333},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1373, 1, 2335},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1374, 1, 2336},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1375, 5, 2337},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1376, 2, 2342},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1377, 1, 2344},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1378, 1, 2345},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1379, 4, 2346},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1380, 2, 2350},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1381, 2, 2352},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1382, 1, 2354},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1383, 1, 2355},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1384, 2, 2356},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1385, 3, 2358},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1386, 2, 2361},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1387, 2, 2363},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1388, 4, 2365},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1389, 10, 2369},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1390, 12, 2379},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1391, 7, 2391},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1392, 2, 2398},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1393, 1, 2400},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1394, 2, 2401},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1395, 7, 2403},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1396, 11, 2410},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1397, 19, 2421},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1398, 11, 2440},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1399, 17, 2451},
- {"cvmx_pcieep#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1400, 12, 2468},
- {"cvmx_pcieep#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1401, 22, 2480},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1402, 3, 2502},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1403, 3, 2505},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1404, 1, 2508},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1405, 1, 2509},
- {"cvmx_pcieep#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1406, 1, 2510},
- {"cvmx_pcieep#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1407, 1, 2511},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1408, 3, 2512},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1409, 14, 2515},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1410, 14, 2529},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1411, 14, 2543},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1412, 9, 2557},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1413, 9, 2566},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1414, 6, 2575},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1415, 1, 2581},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1416, 1, 2582},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1417, 1, 2583},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1418, 1, 2584},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1419, 2, 2585},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1420, 1, 2587},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1421, 6, 2588},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1422, 6, 2594},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1423, 13, 2600},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1424, 5, 2613},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1425, 8, 2618},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1426, 19, 2626},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1427, 3, 2645},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1428, 1, 2648},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1429, 1, 2649},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1430, 3, 2650},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1431, 3, 2653},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1432, 3, 2656},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1433, 4, 2659},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1434, 4, 2663},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1435, 4, 2667},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1436, 7, 2671},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1437, 5, 2678},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1438, 5, 2683},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1439, 4, 2688},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1440, 4, 2692},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1441, 4, 2696},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1442, 1, 2700},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1443, 1, 2701},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1444, 2, 2702},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1446, 24, 2704},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1448, 4, 2728},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1450, 5, 2732},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1452, 1, 2737},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1454, 1, 2738},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1456, 4, 2739},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1458, 17, 2743},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1460, 4, 2760},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1462, 6, 2764},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1464, 1, 2770},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1466, 1, 2771},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1468, 2, 2772},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1470, 2, 2774},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1472, 1, 2776},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1474, 15, 2777},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1476, 10, 2792},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1478, 12, 2802},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1480, 7, 2814},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1482, 2, 2821},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1484, 1, 2823},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1486, 2, 2824},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1488, 7, 2826},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1490, 11, 2833},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1492, 19, 2844},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1494, 11, 2863},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1496, 20, 2874},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1498, 12, 2894},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1500, 22, 2906},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1502, 8, 2928},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1504, 4, 2936},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1506, 3, 2940},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1508, 3, 2943},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1510, 1, 2946},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1512, 1, 2947},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1514, 1, 2948},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1516, 1, 2949},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1518, 3, 2950},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1520, 14, 2953},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1522, 14, 2967},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1524, 14, 2981},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1526, 9, 2995},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1528, 9, 3004},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1530, 6, 3013},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1532, 1, 3019},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1534, 1, 3020},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1536, 1, 3021},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1538, 1, 3022},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1540, 4, 3023},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1542, 9, 3027},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1544, 2, 3036},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1546, 2, 3038},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1548, 1, 3040},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1550, 6, 3041},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1552, 6, 3047},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1554, 13, 3053},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1556, 5, 3066},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1558, 8, 3071},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1560, 19, 3079},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1562, 3, 3098},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1564, 1, 3101},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1566, 1, 3102},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1568, 3, 3103},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1570, 3, 3106},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1572, 3, 3109},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1574, 4, 3112},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1576, 4, 3116},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1578, 4, 3120},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1580, 7, 3124},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1582, 5, 3131},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1584, 5, 3136},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1586, 4, 3141},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1588, 4, 3145},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1590, 4, 3149},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1592, 1, 3153},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1594, 1, 3154},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1596, 9, 3155},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1604, 6, 3164},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1612, 9, 3170},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1620, 6, 3179},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1628, 13, 3185},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1636, 13, 3198},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1644, 2, 3211},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1652, 4, 3213},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1660, 8, 3217},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1668, 13, 3225},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1676, 17, 3238},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1684, 7, 3255},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1692, 3, 3262},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1700, 8, 3265},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1708, 7, 3273},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1716, 4, 3280},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1724, 5, 3284},
- {"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1732, 8, 3289},
- {"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1734, 2, 3297},
- {"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1736, 5, 3299},
- {"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1738, 10, 3304},
- {"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1740, 2, 3314},
- {"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1742, 7, 3316},
- {"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1744, 7, 3323},
- {"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1746, 6, 3330},
- {"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1748, 5, 3336},
- {"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1750, 5, 3341},
- {"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1752, 3, 3346},
- {"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1754, 6, 3349},
- {"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1756, 9, 3355},
- {"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1758, 3, 3364},
- {"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1760, 9, 3367},
- {"cvmx_pesc#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1762, 13, 3376},
- {"cvmx_pesc#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1764, 15, 3389},
- {"cvmx_pesc#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 1766, 2, 3404},
- {"cvmx_pesc#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 1768, 2, 3406},
- {"cvmx_pesc#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 1770, 2, 3408},
- {"cvmx_pesc#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1772, 16, 3410},
- {"cvmx_pesc#_ctl_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1774, 2, 3426},
- {"cvmx_pesc#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 1776, 32, 3428},
- {"cvmx_pesc#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1778, 32, 3460},
- {"cvmx_pesc#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1780, 5, 3492},
- {"cvmx_pesc#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1782, 2, 3497},
- {"cvmx_pesc#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1784, 2, 3499},
- {"cvmx_pesc#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1786, 2, 3501},
- {"cvmx_pesc#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 1788, 2, 3503},
- {"cvmx_pesc#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1796, 2, 3505},
- {"cvmx_pesc#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 1804, 8, 3507},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1806, 5, 3515},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1807, 2, 3520},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1808, 4, 3522},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 1812, 3, 3526},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1814, 8, 3529},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1815, 18, 3537},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1816, 13, 3555},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1817, 13, 3568},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1818, 2, 3581},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1819, 27, 3583},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1831, 25, 3610},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1843, 2, 3635},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1907, 2, 3637},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1915, 9, 3639},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1923, 2, 3648},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1924, 2, 3650},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1925, 2, 3652},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1937, 2, 3654},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1949, 2, 3656},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1961, 2, 3658},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1973, 2, 3660},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1985, 2, 3662},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1997, 2, 3664},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2009, 2, 3666},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2021, 2, 3668},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2033, 2, 3670},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2045, 2, 3672},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2046, 2, 3674},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2058, 2, 3676},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 2070, 2, 3678},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 2082, 2, 3680},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2146, 2, 3682},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2147, 3, 3684},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2148, 3, 3687},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2149, 2, 3690},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2150, 2, 3692},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2151, 4, 3694},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2152, 5, 3698},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2153, 4, 3703},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2154, 8, 3707},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2155, 4, 3715},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2156, 5, 3719},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2157, 1, 3724},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2158, 5, 3725},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2159, 1, 3730},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2160, 13, 3731},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2161, 4, 3744},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2162, 13, 3748},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2163, 6, 3761},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2164, 9, 3767},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2165, 4, 3776},
- {"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2166, 7, 3780},
- {"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2167, 5, 3787},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 2168, 5, 3792},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 2169, 4, 3797},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2170, 9, 3801},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2171, 5, 3810},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2172, 16, 3815},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2173, 4, 3831},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2174, 1, 3835},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2175, 1, 3836},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 1, 3837},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2177, 1, 3838},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 2178, 11, 3839},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 2179, 2, 3850},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 4, 3852},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2181, 5, 3856},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 3, 3861},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2183, 4, 3864},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2184, 2, 3868},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 2185, 3, 3870},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2186, 3, 3873},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2187, 13, 3876},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2188, 2, 3889},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2189, 13, 3891},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2190, 3, 3904},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2191, 2, 3907},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2199, 2, 3909},
- {"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2200, 2, 3911},
- {"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 2201, 2, 3913},
- {"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2202, 2, 3915},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2210, 2, 3917},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2211, 2, 3919},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 2212, 2, 3921},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2213, 10, 3923},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2225, 5, 3933},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2233, 8, 3938},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2241, 2, 3946},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2242, 2, 3948},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2243, 2, 3950},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2251, 3, 3952},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2252, 4, 3955},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2268, 5, 3959},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2269, 7, 3964},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2285, 2, 3971},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2301, 1, 3973},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2302, 1, 3974},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2303, 1, 3975},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2304, 5, 3976},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2305, 5, 3981},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2306, 4, 3986},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2307, 10, 3990},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2308, 1, 4000},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2309, 3, 4001},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2310, 7, 4004},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2311, 2, 4011},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2312, 1, 4013},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2313, 1, 4014},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2314, 1, 4015},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2315, 18, 4016},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2316, 3, 4034},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2317, 2, 4037},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2318, 3, 4039},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2319, 7, 4042},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2320, 2, 4049},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2321, 2, 4051},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 2322, 2, 4053},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2323, 3, 4055},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2324, 3, 4058},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2325, 7, 4061},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2326, 10, 4068},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2328, 6, 4078},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2330, 2, 4084},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2332, 4, 4086},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2334, 4, 4090},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2336, 6, 4094},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2337, 3, 4100},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2338, 5, 4103},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2339, 4, 4108},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2340, 6, 4112},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2341, 4, 4118},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2342, 2, 4122},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2343, 4, 4124},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2344, 2, 4128},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2345, 3, 4130},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2346, 4, 4133},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2347, 12, 4137},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2348, 3, 4149},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 2349, 5, 4152},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2350, 2, 4157},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2351, 2, 4159},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2352, 18, 4161},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2353, 12, 4179},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2354, 6, 4191},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2355, 5, 4197},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2356, 1, 4202},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2357, 2, 4203},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2358, 2, 4205},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2359, 18, 4207},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2360, 12, 4225},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2361, 6, 4237},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2362, 2, 4243},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2363, 2, 4245},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2364, 18, 4247},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2365, 12, 4265},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2366, 6, 4277},
- {"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 2367, 2, 4283},
- {"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2368, 2, 4285},
- {"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2369, 8, 4287},
- {"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2370, 11, 4295},
- {"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 2371, 15, 4306},
- {"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2376, 8, 4321},
- {"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2381, 8, 4329},
- {"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2382, 4, 4337},
- {"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 2387, 15, 4341},
- {"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2392, 6, 4356},
- {"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2397, 6, 4362},
- {"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2398, 4, 4368},
- {"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2403, 2, 4372},
- {"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2407, 6, 4374},
- {"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 2408, 4, 4380},
- {"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 2409, 1, 4384},
- {"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 2410, 1, 4385},
- {"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 2411, 1, 4386},
- {"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2412, 7, 4387},
- {"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 2413, 1, 4394},
- {"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 2414, 14, 4395},
- {"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 2415, 10, 4409},
- {"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 2416, 14, 4419},
- {"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2417, 32, 4433},
- {"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2418, 32, 4465},
- {"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2419, 2, 4497},
- {"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2420, 4, 4499},
- {"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2421, 13, 4503},
- {"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 2422, 10, 4516},
- {"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2423, 10, 4526},
- {"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2424, 2, 4536},
- {"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 2425, 6, 4538},
- {"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 2426, 5, 4544},
- {"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 2427, 6, 4549},
- {"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 2428, 5, 4555},
- {"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 2429, 1, 4560},
- {"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2430, 13, 4561},
- {"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 2431, 2, 4574},
- {"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2432, 2, 4576},
- {"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 2433, 11, 4578},
- {"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2441, 3, 4589},
- {"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2442, 12, 4592},
- {"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 2450, 12, 4604},
- {"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 2458, 6, 4616},
- {"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2466, 4, 4622},
- {"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 2474, 2, 4626},
- {"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 2475, 2, 4628},
- {"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 2476, 15, 4630},
- {"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2477, 2, 4645},
- {"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2478, 3, 4647},
- {"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 2479, 1, 4650},
- {"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2487, 6, 4651},
- {"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2488, 8, 4657},
- {"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2489, 15, 4665},
- {"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 2490, 6, 4680},
- {"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2491, 2, 4686},
- {"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2492, 2, 4688},
- {"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2493, 2, 4690},
- {"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2494, 2, 4692},
- {"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2495, 2, 4694},
- {"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2496, 2, 4696},
- {"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2497, 2, 4698},
- {"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2498, 2, 4700},
- {"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2499, 2, 4702},
- {"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2500, 2, 4704},
- {"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2501, 2, 4706},
- {"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2502, 2, 4708},
- {"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2503, 2, 4710},
- {"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2504, 2, 4712},
- {"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2505, 2, 4714},
- {"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2506, 2, 4716},
- {"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 2507, 7, 4718},
- {"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 2508, 34, 4725},
- {"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 2509, 34, 4759},
- {"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2510, 35, 4793},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2511, 3, 4828},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2512, 5, 4831},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2513, 3, 4836},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2514, 6, 4839},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2515, 2, 4845},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2516, 2, 4847},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2517, 2, 4849},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"AGL_GMX_BAD_REG" , 0x11800e0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"AGL_GMX_BIST" , 0x11800e0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"AGL_GMX_DRV_CTL" , 0x11800e00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_INF_MODE" , 0x11800e00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_PRT0_CFG" , 0x11800e0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX0_ADR_CAM0" , 0x11800e0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX0_ADR_CAM1" , 0x11800e0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX0_ADR_CAM2" , 0x11800e0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX0_ADR_CAM3" , 0x11800e0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX0_ADR_CAM4" , 0x11800e00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX0_ADR_CAM5" , 0x11800e00001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800e0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX0_ADR_CTL" , 0x11800e0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX0_DECISION" , 0x11800e0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX0_FRM_CHK" , 0x11800e0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX0_FRM_CTL" , 0x11800e0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX0_FRM_MAX" , 0x11800e0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX0_FRM_MIN" , 0x11800e0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX0_IFG" , 0x11800e0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX0_INT_EN" , 0x11800e0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX0_INT_REG" , 0x11800e0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX0_JABBER" , 0x11800e0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800e0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX0_STATS_CTL" , 0x11800e0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX0_STATS_OCTS" , 0x11800e0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800e0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800e00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800e00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX0_STATS_PKTS" , 0x11800e0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800e00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800e0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800e00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800e00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX0_UDD_SKP" , 0x11800e0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_DROP0" , 0x11800e0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_OFF0" , 0x11800e0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_BP_ON0" , 0x11800e0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_PRT_INFO" , 0x11800e00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"AGL_GMX_RX_TX_STATUS" , 0x11800e00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_SMAC0" , 0x11800e0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_STAT_BP" , 0x11800e0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX0_APPEND" , 0x11800e0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX0_CTL" , 0x11800e0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX0_MIN_PKT" , 0x11800e0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800e0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800e0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800e0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800e0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800e0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX0_STAT0" , 0x11800e0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX0_STAT1" , 0x11800e0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX0_STAT2" , 0x11800e0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX0_STAT3" , 0x11800e0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX0_STAT4" , 0x11800e00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX0_STAT5" , 0x11800e00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX0_STAT6" , 0x11800e00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX0_STAT7" , 0x11800e00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX0_STAT8" , 0x11800e00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX0_STAT9" , 0x11800e00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX0_STATS_CTL" , 0x11800e0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX0_THRESH" , 0x11800e0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX_BP" , 0x11800e00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"AGL_GMX_TX_COL_ATTEMPT" , 0x11800e0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"AGL_GMX_TX_IFG" , 0x11800e0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"AGL_GMX_TX_INT_EN" , 0x11800e0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"AGL_GMX_TX_INT_REG" , 0x11800e0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"AGL_GMX_TX_JAM" , 0x11800e0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"AGL_GMX_TX_LFSR" , 0x11800e00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"AGL_GMX_TX_OVR_BP" , 0x11800e00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800e00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800e00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 71},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT10_EN0" , 0x10700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT11_EN0" , 0x10700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT12_EN0" , 0x10700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT13_EN0" , 0x10700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT14_EN0" , 0x10700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT15_EN0" , 0x10700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT10_EN1" , 0x10700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT11_EN1" , 0x10700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT12_EN1" , 0x10700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT13_EN1" , 0x10700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT14_EN1" , 0x10700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT15_EN1" , 0x10700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT4_EN4_0" , 0x1070000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT5_EN4_0" , 0x1070000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT6_EN4_0" , 0x1070000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT7_EN4_0" , 0x1070000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT8_EN4_0" , 0x1070000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT9_EN4_0" , 0x1070000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT10_EN4_0" , 0x1070000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT11_EN4_0" , 0x1070000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT4_EN4_1" , 0x1070000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT5_EN4_1" , 0x1070000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT6_EN4_1" , 0x1070000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT7_EN4_1" , 0x1070000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT8_EN4_1" , 0x1070000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT9_EN4_1" , 0x1070000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT10_EN4_1" , 0x1070000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT11_EN4_1" , 0x1070000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT20_SUM0" , 0x10700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT21_SUM0" , 0x10700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT22_SUM0" , 0x10700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT23_SUM0" , 0x10700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT4_SUM4" , 0x1070000000c20ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT5_SUM4" , 0x1070000000c28ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT6_SUM4" , 0x1070000000c30ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT7_SUM4" , 0x1070000000c38ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT8_SUM4" , 0x1070000000c40ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT9_SUM4" , 0x1070000000c48ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT10_SUM4" , 0x1070000000c50ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT11_SUM4" , 0x1070000000c58ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR4" , 0x10700000006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR5" , 0x10700000006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR6" , 0x10700000006b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR7" , 0x10700000006b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR8" , 0x10700000006c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR9" , 0x10700000006c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR10" , 0x10700000006d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR11" , 0x10700000006d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE4" , 0x10700000005a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE5" , 0x10700000005a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE6" , 0x10700000005b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE7" , 0x10700000005b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE8" , 0x10700000005c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE9" , 0x10700000005c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE10" , 0x10700000005d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE11" , 0x10700000005d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_QLM_DCOK" , 0x1070000000760ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX1_CLK_EN" , 0x11800100007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX1_INF_MODE" , 0x11800100007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_RX000_ADR_CAM4" , 0x11800100001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_RX001_ADR_CAM4" , 0x11800100009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_RX002_ADR_CAM4" , 0x11800100011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_RX003_ADR_CAM4" , 0x11800100019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_RX000_ADR_CAM5" , 0x11800100001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_RX001_ADR_CAM5" , 0x11800100009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_RX002_ADR_CAM5" , 0x11800100011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_RX003_ADR_CAM5" , 0x11800100019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180010000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180010000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180010001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180010001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_RX_PRT_INFO" , 0x11800100004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_RX_XAUI_BAD_COL" , 0x1180010000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_RX_XAUI_CTL" , 0x1180010000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_SMAC001" , 0x1180010000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_SMAC003" , 0x1180010001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_TX001_APPEND" , 0x1180010000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_TX003_APPEND" , 0x1180010001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_TX001_BURST" , 0x1180010000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_TX003_BURST" , 0x1180010001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_TX001_CTL" , 0x1180010000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_TX003_CTL" , 0x1180010001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_TX001_MIN_PKT" , 0x1180010000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_TX003_MIN_PKT" , 0x1180010001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX1_TX001_PAUSE_TOGO" , 0x1180010000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX1_TX003_PAUSE_TOGO" , 0x1180010001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX1_TX001_PAUSE_ZERO" , 0x1180010000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX1_TX003_PAUSE_ZERO" , 0x1180010001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX003_SGMII_CTL" , 0x1180008001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX1_TX000_SGMII_CTL" , 0x1180010000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX1_TX001_SGMII_CTL" , 0x1180010000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX1_TX002_SGMII_CTL" , 0x1180010001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX1_TX003_SGMII_CTL" , 0x1180010001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX1_TX001_SLOT" , 0x1180010000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX1_TX003_SLOT" , 0x1180010001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX1_TX001_SOFT_PAUSE" , 0x1180010000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX1_TX003_SOFT_PAUSE" , 0x1180010001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX1_TX001_STAT0" , 0x1180010000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX1_TX003_STAT0" , 0x1180010001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX1_TX001_STAT1" , 0x1180010000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX1_TX003_STAT1" , 0x1180010001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX001_STAT2" , 0x1180010000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX003_STAT2" , 0x1180010001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX1_TX001_STAT3" , 0x1180010000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX1_TX003_STAT3" , 0x1180010001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX1_TX000_STAT4" , 0x11800100002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX1_TX001_STAT4" , 0x1180010000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX1_TX002_STAT4" , 0x11800100012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX1_TX003_STAT4" , 0x1180010001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX1_TX000_STAT5" , 0x11800100002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX1_TX001_STAT5" , 0x1180010000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX1_TX002_STAT5" , 0x11800100012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX1_TX003_STAT5" , 0x1180010001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX1_TX000_STAT6" , 0x11800100002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX1_TX001_STAT6" , 0x1180010000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX1_TX002_STAT6" , 0x11800100012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX1_TX003_STAT6" , 0x1180010001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX1_TX000_STAT7" , 0x11800100002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX1_TX001_STAT7" , 0x1180010000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX1_TX002_STAT7" , 0x11800100012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX1_TX003_STAT7" , 0x1180010001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX1_TX000_STAT8" , 0x11800100002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX1_TX001_STAT8" , 0x1180010000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX1_TX002_STAT8" , 0x11800100012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX1_TX003_STAT8" , 0x1180010001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX1_TX000_STAT9" , 0x11800100002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX1_TX001_STAT9" , 0x1180010000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX1_TX002_STAT9" , 0x11800100012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX1_TX003_STAT9" , 0x1180010001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX1_TX001_STATS_CTL" , 0x1180010000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX1_TX003_STATS_CTL" , 0x1180010001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX1_TX001_THRESH" , 0x1180010000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX1_TX003_THRESH" , 0x1180010001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX1_TX_BP" , 0x11800100004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX1_TX_CORRUPT" , 0x11800100004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX1_TX_LFSR" , 0x11800100004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX1_TX_OVR_BP" , 0x11800100004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX1_TX_XAUI_CTL" , 0x1180010000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"GMX1_XAUI_EXT_LOOPBACK" , 0x1180010000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 225},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 226},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 227},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 228},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 229},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 230},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT16_BP_PAGE_CNT" , 0x14f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT17_BP_PAGE_CNT" , 0x14f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT18_BP_PAGE_CNT" , 0x14f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT19_BP_PAGE_CNT" , 0x14f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT36_BP_PAGE_CNT2" , 0x14f0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"IPD_PORT37_BP_PAGE_CNT2" , 0x14f0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"IPD_PORT38_BP_PAGE_CNT2" , 0x14f0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"IPD_PORT39_BP_PAGE_CNT2" , 0x14f0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14f0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14f0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14f0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14f00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14f0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14f0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14f0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14f0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_128_CNT" , 0x14f0000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_129_CNT" , 0x14f0000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_130_CNT" , 0x14f0000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_131_CNT" , 0x14f0000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_132_CNT" , 0x14f0000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_133_CNT" , 0x14f0000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_134_CNT" , 0x14f0000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_135_CNT" , 0x14f0000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_136_CNT" , 0x14f0000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_137_CNT" , 0x14f0000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_138_CNT" , 0x14f0000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_139_CNT" , 0x14f0000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_140_CNT" , 0x14f0000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_141_CNT" , 0x14f0000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_142_CNT" , 0x14f0000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_143_CNT" , 0x14f0000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_144_CNT" , 0x14f0000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_145_CNT" , 0x14f0000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_146_CNT" , 0x14f0000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_147_CNT" , 0x14f0000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_148_CNT" , 0x14f0000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_149_CNT" , 0x14f0000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_150_CNT" , 0x14f0000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_151_CNT" , 0x14f0000000d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_152_CNT" , 0x14f0000000d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_153_CNT" , 0x14f0000000d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_154_CNT" , 0x14f0000000d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_155_CNT" , 0x14f0000000d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_156_CNT" , 0x14f0000000d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_157_CNT" , 0x14f0000000d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_158_CNT" , 0x14f0000000d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_159_CNT" , 0x14f0000000d80ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"IPD_PORT_QOS_INT2" , 0x14f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"IPD_PORT_QOS_INT_ENB2" , 0x14f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"IPD_RED_PORT_ENABLE2" , 0x14f00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"L2C_GRPWRR0" , 0x11800800000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"L2C_GRPWRR1" , 0x11800800000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"L2C_INT_EN" , 0x1180080000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"L2C_INT_STAT" , 0x11800800000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"L2C_OOB" , 0x11800800000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"L2C_OOB1" , 0x11800800000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"L2C_OOB2" , 0x11800800000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"L2C_OOB3" , 0x11800800000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"L2C_PPGRP" , 0x11800800000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"LED_BLINK" , 0x1180000001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"LED_CLK_PHASE" , 0x1180000001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"LED_CYLON" , 0x1180000001af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"LED_DBG" , 0x1180000001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"LED_EN" , 0x1180000001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"LED_POLARITY" , 0x1180000001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"LED_PRT" , 0x1180000001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"LED_PRT_FMT" , 0x1180000001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"LED_PRT_STATUS0" , 0x1180000001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"LED_PRT_STATUS1" , 0x1180000001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"LED_PRT_STATUS2" , 0x1180000001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"LED_PRT_STATUS3" , 0x1180000001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"LED_PRT_STATUS4" , 0x1180000001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"LED_PRT_STATUS5" , 0x1180000001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"LED_PRT_STATUS6" , 0x1180000001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"LED_PRT_STATUS7" , 0x1180000001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"LED_UDD_CNT0" , 0x1180000001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"LED_UDD_CNT1" , 0x1180000001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"LED_UDD_DAT0" , 0x1180000001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"LED_UDD_DAT1" , 0x1180000001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"LED_UDD_DAT_CLR0" , 0x1180000001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"LED_UDD_DAT_CLR1" , 0x1180000001ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"LED_UDD_DAT_SET0" , 0x1180000001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"LED_UDD_DAT_SET1" , 0x1180000001ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"LMC0_BIST_CTL" , 0x11800880000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"LMC1_BIST_CTL" , 0x11800e80000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"LMC0_BIST_RESULT" , 0x11800880000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"LMC1_BIST_RESULT" , 0x11800e80000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"LMC1_COMP_CTL" , 0x11800e8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"LMC1_CTL" , 0x11800e8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"LMC1_CTL1" , 0x11800e8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"LMC1_DCLK_CNT_HI" , 0x11800e8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"LMC1_DCLK_CNT_LO" , 0x11800e8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"LMC0_DCLK_CTL" , 0x11800880000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"LMC1_DCLK_CTL" , 0x11800e80000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"LMC1_DDR2_CTL" , 0x11800e8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"LMC1_DELAY_CFG" , 0x11800e8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"LMC0_DLL_CTL" , 0x11800880000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LMC1_DLL_CTL" , 0x11800e80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"LMC1_DUAL_MEMCFG" , 0x11800e8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"LMC1_ECC_SYND" , 0x11800e8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"LMC1_FADR" , 0x11800e8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"LMC1_IFB_CNT_HI" , 0x11800e8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"LMC1_IFB_CNT_LO" , 0x11800e8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"LMC1_MEM_CFG0" , 0x11800e8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"LMC1_MEM_CFG1" , 0x11800e8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"LMC1_OPS_CNT_HI" , 0x11800e8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"LMC1_OPS_CNT_LO" , 0x11800e8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"LMC0_PLL_CTL" , 0x11800880000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"LMC1_PLL_CTL" , 0x11800e80000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"LMC0_PLL_STATUS" , 0x11800880000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"LMC1_PLL_STATUS" , 0x11800e80000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"LMC0_READ_LEVEL_CTL" , 0x1180088000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"LMC1_READ_LEVEL_CTL" , 0x11800e8000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"LMC0_READ_LEVEL_DBG" , 0x1180088000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"LMC1_READ_LEVEL_DBG" , 0x11800e8000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"LMC0_READ_LEVEL_RANK000" , 0x1180088000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"LMC0_READ_LEVEL_RANK001" , 0x1180088000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"LMC0_READ_LEVEL_RANK002" , 0x1180088000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"LMC0_READ_LEVEL_RANK003" , 0x1180088000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"LMC1_READ_LEVEL_RANK000" , 0x11800e8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"LMC1_READ_LEVEL_RANK001" , 0x11800e8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"LMC1_READ_LEVEL_RANK002" , 0x11800e8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"LMC1_READ_LEVEL_RANK003" , 0x11800e8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"LMC0_RODT_COMP_CTL" , 0x11800880000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"LMC1_RODT_COMP_CTL" , 0x11800e80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"LMC1_RODT_CTL" , 0x11800e8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"LMC1_WODT_CTL0" , 0x11800e8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"LMC1_WODT_CTL1" , 0x11800e8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"MIO_BOOT_DMA_CFG2" , 0x1180000000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"MIO_BOOT_DMA_INT2" , 0x1180000000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"MIO_BOOT_DMA_INT_EN2" , 0x1180000000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_DMA_TIM2" , 0x1180000000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
- {"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
- {"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
- {"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
- {"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
- {"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
- {"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
- {"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
- {"NPEI_BAR1_INDEX0" , 0x11f0000008000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX1" , 0x11f0000008010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX2" , 0x11f0000008020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX3" , 0x11f0000008030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX4" , 0x11f0000008040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX5" , 0x11f0000008050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX6" , 0x11f0000008060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX7" , 0x11f0000008070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX8" , 0x11f0000008080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX9" , 0x11f0000008090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX10" , 0x11f00000080a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX11" , 0x11f00000080b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX12" , 0x11f00000080c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX13" , 0x11f00000080d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX14" , 0x11f00000080e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX15" , 0x11f00000080f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX16" , 0x11f0000008100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX17" , 0x11f0000008110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX18" , 0x11f0000008120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX19" , 0x11f0000008130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX20" , 0x11f0000008140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX21" , 0x11f0000008150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX22" , 0x11f0000008160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX23" , 0x11f0000008170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX24" , 0x11f0000008180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX25" , 0x11f0000008190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX26" , 0x11f00000081a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX27" , 0x11f00000081b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX28" , 0x11f00000081c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX29" , 0x11f00000081d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX30" , 0x11f00000081e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BAR1_INDEX31" , 0x11f00000081f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
- {"NPEI_BIST_STATUS" , 0x11f0000008580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 409},
- {"NPEI_CTL_PORT0" , 0x11f0000008250ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 410},
- {"NPEI_CTL_PORT1" , 0x11f0000008260ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 411},
- {"NPEI_CTL_STATUS" , 0x11f0000008570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 412},
- {"NPEI_CTL_STATUS2" , 0x11f000000bc00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 413},
- {"NPEI_DATA_OUT_CNT" , 0x11f00000085f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 414},
- {"NPEI_DBG_DATA" , 0x11f0000008510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 415},
- {"NPEI_DBG_SELECT" , 0x11f0000008500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 416},
- {"NPEI_DMA0_COUNTS" , 0x11f0000008450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
- {"NPEI_DMA1_COUNTS" , 0x11f0000008460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
- {"NPEI_DMA2_COUNTS" , 0x11f0000008470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
- {"NPEI_DMA3_COUNTS" , 0x11f0000008480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
- {"NPEI_DMA4_COUNTS" , 0x11f0000008490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
- {"NPEI_DMA0_DBELL" , 0x11f00000083b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 418},
- {"NPEI_DMA1_DBELL" , 0x11f00000083c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 418},
- {"NPEI_DMA2_DBELL" , 0x11f00000083d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 418},
- {"NPEI_DMA3_DBELL" , 0x11f00000083e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 418},
- {"NPEI_DMA4_DBELL" , 0x11f00000083f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 418},
- {"NPEI_DMA0_IBUFF_SADDR" , 0x11f0000008400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
- {"NPEI_DMA1_IBUFF_SADDR" , 0x11f0000008410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
- {"NPEI_DMA2_IBUFF_SADDR" , 0x11f0000008420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
- {"NPEI_DMA3_IBUFF_SADDR" , 0x11f0000008430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
- {"NPEI_DMA4_IBUFF_SADDR" , 0x11f0000008440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
- {"NPEI_DMA0_NADDR" , 0x11f00000084a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
- {"NPEI_DMA1_NADDR" , 0x11f00000084b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
- {"NPEI_DMA2_NADDR" , 0x11f00000084c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
- {"NPEI_DMA3_NADDR" , 0x11f00000084d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
- {"NPEI_DMA4_NADDR" , 0x11f00000084e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
- {"NPEI_DMA0_INT_LEVEL" , 0x11f00000085c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 421},
- {"NPEI_DMA1_INT_LEVEL" , 0x11f00000085d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 422},
- {"NPEI_DMA_CNTS" , 0x11f00000085e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 423},
- {"NPEI_DMA_CONTROL" , 0x11f00000083a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 424},
- {"NPEI_DMA_STATE1_P1" , 0x11f0000008680ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 425},
- {"NPEI_DMA_STATE2_P1" , 0x11f0000008690ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 426},
- {"NPEI_DMA_STATE3_P1" , 0x11f00000086a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 427},
- {"NPEI_DMA_STATE4_P1" , 0x11f00000086b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 428},
- {"NPEI_DMA_STATE5_P1" , 0x11f00000086c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 429},
- {"NPEI_INT_ENB" , 0x11f0000008540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 430},
- {"NPEI_INT_ENB2" , 0x11f000000bcd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 431},
- {"NPEI_INT_INFO" , 0x11f0000008590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 432},
- {"NPEI_INT_SUM" , 0x11f0000008530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 433},
- {"NPEI_LAST_WIN_RDATA0" , 0x11f0000008600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 434},
- {"NPEI_LAST_WIN_RDATA1" , 0x11f0000008610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
- {"NPEI_MEM_ACCESS_CTL" , 0x11f00000084f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 436},
- {"NPEI_MEM_ACCESS_SUBID12" , 0x11f0000008280ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID13" , 0x11f0000008290ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID14" , 0x11f00000082a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID15" , 0x11f00000082b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID16" , 0x11f00000082c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID17" , 0x11f00000082d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID18" , 0x11f00000082e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID19" , 0x11f00000082f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID20" , 0x11f0000008300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID21" , 0x11f0000008310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID22" , 0x11f0000008320ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID23" , 0x11f0000008330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID24" , 0x11f0000008340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID25" , 0x11f0000008350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID26" , 0x11f0000008360ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MEM_ACCESS_SUBID27" , 0x11f0000008370ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_MSI_ENB0" , 0x11f000000bc50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
- {"NPEI_MSI_ENB1" , 0x11f000000bc60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 439},
- {"NPEI_MSI_ENB2" , 0x11f000000bc70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 440},
- {"NPEI_MSI_ENB3" , 0x11f000000bc80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 441},
- {"NPEI_MSI_RCV0" , 0x11f000000bc10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 442},
- {"NPEI_MSI_RCV1" , 0x11f000000bc20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 443},
- {"NPEI_MSI_RCV2" , 0x11f000000bc30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MSI_RCV3" , 0x11f000000bc40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 445},
- {"NPEI_MSI_RD_MAP" , 0x11f000000bca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 446},
- {"NPEI_MSI_WR_MAP" , 0x11f000000bc90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 447},
- {"NPEI_PCIE_MSI_RCV" , 0x11f000000bcb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
- {"NPEI_PCIE_MSI_RCV_B1" , 0x11f0000008650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 449},
- {"NPEI_PCIE_MSI_RCV_B2" , 0x11f0000008660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
- {"NPEI_PCIE_MSI_RCV_B3" , 0x11f0000008670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
- {"NPEI_RSL_INT_BLOCKS" , 0x11f0000008520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 452},
- {"NPEI_SCRATCH_1" , 0x11f0000008270ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 453},
- {"NPEI_STATE1" , 0x11f0000008620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 454},
- {"NPEI_STATE2" , 0x11f0000008630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_STATE3" , 0x11f0000008640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 456},
- {"NPEI_WIN_RD_ADDR" , 0x210ull, CVMX_CSR_DB_TYPE_PEXP, 64, 457},
- {"NPEI_WIN_RD_DATA" , 0x240ull, CVMX_CSR_DB_TYPE_PEXP, 64, 458},
- {"NPEI_WIN_WR_ADDR" , 0x200ull, CVMX_CSR_DB_TYPE_PEXP, 64, 459},
- {"NPEI_WIN_WR_DATA" , 0x220ull, CVMX_CSR_DB_TYPE_PEXP, 64, 460},
- {"NPEI_WIN_WR_MASK" , 0x230ull, CVMX_CSR_DB_TYPE_PEXP, 64, 461},
- {"NPEI_WINDOW_CTL" , 0x11f0000008380ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 462},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 463},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 464},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 465},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 466},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 467},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 468},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 469},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 470},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 471},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 472},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 473},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 474},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 475},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 476},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 477},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 478},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 479},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 480},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 481},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 482},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 483},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 484},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 485},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 486},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 487},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 488},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 489},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 490},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 491},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 492},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 493},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 494},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 495},
- {"PCIEEP0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 496},
- {"PCIEEP0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 497},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 498},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 499},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 500},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 501},
- {"PCIEEP0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 502},
- {"PCIEEP0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 503},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 504},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 505},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 506},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 507},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 508},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 509},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 510},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 511},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 512},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 513},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 514},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 515},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 516},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 517},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 518},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 519},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 520},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 521},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 522},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 523},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 524},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 525},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 526},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 527},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 528},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 529},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 530},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 531},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 532},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 533},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 534},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 535},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 536},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 537},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 538},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 539},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 540},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 540},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 541},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 541},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 542},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 542},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 543},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 543},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 544},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 544},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 545},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 545},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 546},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 546},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 547},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 547},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 548},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 548},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 549},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 549},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 550},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 550},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 551},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 551},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 552},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 552},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 553},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 553},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 554},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 554},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 555},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 555},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 556},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 556},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 557},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 557},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 558},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 558},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 559},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 559},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 560},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 560},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 561},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 561},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 562},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 562},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 563},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 563},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 564},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 564},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 565},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 565},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 566},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 566},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 567},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 567},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 568},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 568},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 569},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 569},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 570},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 570},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 571},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 571},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 572},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 572},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 573},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 573},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 574},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 574},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 575},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 575},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 576},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 576},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 577},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 577},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 578},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 578},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 579},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 579},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 580},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 580},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 581},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 581},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 582},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 582},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 583},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 583},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 584},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 584},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 585},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 585},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 586},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 586},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 587},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 587},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 588},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 588},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 589},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 589},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 590},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 590},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 591},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 591},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 592},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 592},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 593},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 593},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 594},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 594},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 595},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 595},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 596},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 596},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 597},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 597},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 598},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 598},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 599},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 599},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 600},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 600},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 601},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 601},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 602},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 602},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"PCS0_AN002_ADV_REG" , 0x11800b0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"PCS0_AN003_ADV_REG" , 0x11800b0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"PCS1_AN000_ADV_REG" , 0x11800b8001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"PCS1_AN001_ADV_REG" , 0x11800b8001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"PCS1_AN002_ADV_REG" , 0x11800b8001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"PCS1_AN003_ADV_REG" , 0x11800b8001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"PCS0_AN002_EXT_ST_REG" , 0x11800b0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"PCS0_AN003_EXT_ST_REG" , 0x11800b0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"PCS1_AN000_EXT_ST_REG" , 0x11800b8001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"PCS1_AN001_EXT_ST_REG" , 0x11800b8001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"PCS1_AN002_EXT_ST_REG" , 0x11800b8001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"PCS1_AN003_EXT_ST_REG" , 0x11800b8001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
- {"PCS0_AN002_LP_ABIL_REG" , 0x11800b0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
- {"PCS0_AN003_LP_ABIL_REG" , 0x11800b0001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
- {"PCS1_AN000_LP_ABIL_REG" , 0x11800b8001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
- {"PCS1_AN001_LP_ABIL_REG" , 0x11800b8001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
- {"PCS1_AN002_LP_ABIL_REG" , 0x11800b8001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
- {"PCS1_AN003_LP_ABIL_REG" , 0x11800b8001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"PCS0_AN002_RESULTS_REG" , 0x11800b0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"PCS0_AN003_RESULTS_REG" , 0x11800b0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"PCS1_AN000_RESULTS_REG" , 0x11800b8001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"PCS1_AN001_RESULTS_REG" , 0x11800b8001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"PCS1_AN002_RESULTS_REG" , 0x11800b8001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"PCS1_AN003_RESULTS_REG" , 0x11800b8001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"PCS0_INT002_EN_REG" , 0x11800b0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"PCS0_INT003_EN_REG" , 0x11800b0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"PCS1_INT000_EN_REG" , 0x11800b8001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"PCS1_INT001_EN_REG" , 0x11800b8001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"PCS1_INT002_EN_REG" , 0x11800b8001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"PCS1_INT003_EN_REG" , 0x11800b8001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"PCS0_INT002_REG" , 0x11800b0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"PCS0_INT003_REG" , 0x11800b0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"PCS1_INT000_REG" , 0x11800b8001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"PCS1_INT001_REG" , 0x11800b8001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"PCS1_INT002_REG" , 0x11800b8001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"PCS1_INT003_REG" , 0x11800b8001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"PCS0_LINK002_TIMER_COUNT_REG", 0x11800b0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"PCS0_LINK003_TIMER_COUNT_REG", 0x11800b0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"PCS1_LINK000_TIMER_COUNT_REG", 0x11800b8001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"PCS1_LINK001_TIMER_COUNT_REG", 0x11800b8001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"PCS1_LINK002_TIMER_COUNT_REG", 0x11800b8001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"PCS1_LINK003_TIMER_COUNT_REG", 0x11800b8001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS0_LOG_ANL002_REG" , 0x11800b0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS0_LOG_ANL003_REG" , 0x11800b0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS1_LOG_ANL000_REG" , 0x11800b8001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS1_LOG_ANL001_REG" , 0x11800b8001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS1_LOG_ANL002_REG" , 0x11800b8001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS1_LOG_ANL003_REG" , 0x11800b8001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS0_MISC002_CTL_REG" , 0x11800b0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS0_MISC003_CTL_REG" , 0x11800b0001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS1_MISC000_CTL_REG" , 0x11800b8001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS1_MISC001_CTL_REG" , 0x11800b8001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS1_MISC002_CTL_REG" , 0x11800b8001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS1_MISC003_CTL_REG" , 0x11800b8001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS0_MR002_CONTROL_REG" , 0x11800b0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS0_MR003_CONTROL_REG" , 0x11800b0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS1_MR000_CONTROL_REG" , 0x11800b8001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS1_MR001_CONTROL_REG" , 0x11800b8001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS1_MR002_CONTROL_REG" , 0x11800b8001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS1_MR003_CONTROL_REG" , 0x11800b8001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS0_MR002_STATUS_REG" , 0x11800b0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS0_MR003_STATUS_REG" , 0x11800b0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS1_MR000_STATUS_REG" , 0x11800b8001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS1_MR001_STATUS_REG" , 0x11800b8001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS1_MR002_STATUS_REG" , 0x11800b8001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS1_MR003_STATUS_REG" , 0x11800b8001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS0_RX002_STATES_REG" , 0x11800b0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS0_RX003_STATES_REG" , 0x11800b0001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS1_RX000_STATES_REG" , 0x11800b8001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS1_RX001_STATES_REG" , 0x11800b8001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS1_RX002_STATES_REG" , 0x11800b8001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS1_RX003_STATES_REG" , 0x11800b8001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS0_RX002_SYNC_REG" , 0x11800b0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS0_RX003_SYNC_REG" , 0x11800b0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS1_RX000_SYNC_REG" , 0x11800b8001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS1_RX001_SYNC_REG" , 0x11800b8001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS1_RX002_SYNC_REG" , 0x11800b8001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS1_RX003_SYNC_REG" , 0x11800b8001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS0_SGM002_AN_ADV_REG" , 0x11800b0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS0_SGM003_AN_ADV_REG" , 0x11800b0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS1_SGM000_AN_ADV_REG" , 0x11800b8001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS1_SGM001_AN_ADV_REG" , 0x11800b8001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS1_SGM002_AN_ADV_REG" , 0x11800b8001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS1_SGM003_AN_ADV_REG" , 0x11800b8001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS0_SGM002_LP_ADV_REG" , 0x11800b0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS0_SGM003_LP_ADV_REG" , 0x11800b0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS1_SGM000_LP_ADV_REG" , 0x11800b8001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS1_SGM001_LP_ADV_REG" , 0x11800b8001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS1_SGM002_LP_ADV_REG" , 0x11800b8001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS1_SGM003_LP_ADV_REG" , 0x11800b8001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS0_TX002_STATES_REG" , 0x11800b0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS0_TX003_STATES_REG" , 0x11800b0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS1_TX000_STATES_REG" , 0x11800b8001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS1_TX001_STATES_REG" , 0x11800b8001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS1_TX002_STATES_REG" , 0x11800b8001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS1_TX003_STATES_REG" , 0x11800b8001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS0_TX_RX002_POLARITY_REG" , 0x11800b0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS0_TX_RX003_POLARITY_REG" , 0x11800b0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS1_TX_RX000_POLARITY_REG" , 0x11800b8001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS1_TX_RX001_POLARITY_REG" , 0x11800b8001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS1_TX_RX002_POLARITY_REG" , 0x11800b8001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS1_TX_RX003_POLARITY_REG" , 0x11800b8001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCSX0_10GBX_STATUS_REG" , 0x11800b0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"PCSX1_10GBX_STATUS_REG" , 0x11800b8000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"PCSX0_BIST_STATUS_REG" , 0x11800b0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"PCSX1_BIST_STATUS_REG" , 0x11800b8000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800b0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"PCSX1_BIT_LOCK_STATUS_REG" , 0x11800b8000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"PCSX0_CONTROL1_REG" , 0x11800b0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"PCSX1_CONTROL1_REG" , 0x11800b8000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"PCSX0_CONTROL2_REG" , 0x11800b0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
- {"PCSX1_CONTROL2_REG" , 0x11800b8000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
- {"PCSX0_INT_EN_REG" , 0x11800b0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"PCSX1_INT_EN_REG" , 0x11800b8000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"PCSX0_INT_REG" , 0x11800b0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
- {"PCSX1_INT_REG" , 0x11800b8000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
- {"PCSX0_LOG_ANL_REG" , 0x11800b0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"PCSX1_LOG_ANL_REG" , 0x11800b8000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"PCSX0_MISC_CTL_REG" , 0x11800b0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"PCSX1_MISC_CTL_REG" , 0x11800b8000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"PCSX0_RX_SYNC_STATES_REG" , 0x11800b0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"PCSX1_RX_SYNC_STATES_REG" , 0x11800b8000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"PCSX0_SPD_ABIL_REG" , 0x11800b0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
- {"PCSX1_SPD_ABIL_REG" , 0x11800b8000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
- {"PCSX0_STATUS1_REG" , 0x11800b0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"PCSX1_STATUS1_REG" , 0x11800b8000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"PCSX0_STATUS2_REG" , 0x11800b0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"PCSX1_STATUS2_REG" , 0x11800b8000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"PCSX0_TX_RX_POLARITY_REG" , 0x11800b0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"PCSX1_TX_RX_POLARITY_REG" , 0x11800b8000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"PCSX0_TX_RX_STATES_REG" , 0x11800b0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"PCSX1_TX_RX_STATES_REG" , 0x11800b8000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"PESC0_BIST_STATUS" , 0x11800c8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
- {"PESC1_BIST_STATUS" , 0x11800d0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
- {"PESC0_BIST_STATUS2" , 0x11800c8000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"PESC1_BIST_STATUS2" , 0x11800d0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"PESC0_CFG_RD" , 0x11800c8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"PESC1_CFG_RD" , 0x11800d0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"PESC0_CFG_WR" , 0x11800c8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"PESC1_CFG_WR" , 0x11800d0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"PESC0_CPL_LUT_VALID" , 0x11800c8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"PESC1_CPL_LUT_VALID" , 0x11800d0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"PESC0_CTL_STATUS" , 0x11800c8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"PESC1_CTL_STATUS" , 0x11800d0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"PESC0_CTL_STATUS2" , 0x11800c8000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"PESC1_CTL_STATUS2" , 0x11800d0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"PESC0_DBG_INFO" , 0x11800c8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"PESC1_DBG_INFO" , 0x11800d0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"PESC0_DBG_INFO_EN" , 0x11800c80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"PESC1_DBG_INFO_EN" , 0x11800d00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"PESC0_DIAG_STATUS" , 0x11800c8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"PESC1_DIAG_STATUS" , 0x11800d0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"PESC0_P2N_BAR0_START" , 0x11800c8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"PESC1_P2N_BAR0_START" , 0x11800d0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"PESC0_P2N_BAR1_START" , 0x11800c8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"PESC1_P2N_BAR1_START" , 0x11800d0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"PESC0_P2N_BAR2_START" , 0x11800c8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"PESC1_P2N_BAR2_START" , 0x11800d0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"PESC0_P2P_BAR000_END" , 0x11800c8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"PESC0_P2P_BAR001_END" , 0x11800c8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"PESC0_P2P_BAR002_END" , 0x11800c8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"PESC0_P2P_BAR003_END" , 0x11800c8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"PESC1_P2P_BAR000_END" , 0x11800d0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"PESC1_P2P_BAR001_END" , 0x11800d0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"PESC1_P2P_BAR002_END" , 0x11800d0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"PESC1_P2P_BAR003_END" , 0x11800d0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"PESC0_P2P_BAR000_START" , 0x11800c8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"PESC0_P2P_BAR001_START" , 0x11800c8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"PESC0_P2P_BAR002_START" , 0x11800c8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"PESC0_P2P_BAR003_START" , 0x11800c8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"PESC1_P2P_BAR000_START" , 0x11800d0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"PESC1_P2P_BAR001_START" , 0x11800d0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"PESC1_P2P_BAR002_START" , 0x11800d0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"PESC1_P2P_BAR003_START" , 0x11800d0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"PESC0_TLP_CREDITS" , 0x11800c8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"PESC1_TLP_CREDITS" , 0x11800d0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"PIP_FRM_LEN_CHK1" , 0x11800a0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG16" , 0x11800a0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG17" , 0x11800a0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG18" , 0x11800a0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG19" , 0x11800a0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG16" , 0x11800a0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG17" , 0x11800a0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG18" , 0x11800a0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG19" , 0x11800a0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT16" , 0x11800a0000d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT17" , 0x11800a0000d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT18" , 0x11800a0000da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT19" , 0x11800a0000df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT36" , 0x11800a0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT37" , 0x11800a0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT38" , 0x11800a00013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT0_PRT39" , 0x11800a0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT16" , 0x11800a0000d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT17" , 0x11800a0000d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT18" , 0x11800a0000da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT19" , 0x11800a0000df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT36" , 0x11800a0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT37" , 0x11800a0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT38" , 0x11800a00013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT1_PRT39" , 0x11800a0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT16" , 0x11800a0000d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT17" , 0x11800a0000d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT18" , 0x11800a0000db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT19" , 0x11800a0000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT36" , 0x11800a0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT37" , 0x11800a00013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT38" , 0x11800a00013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT2_PRT39" , 0x11800a0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT16" , 0x11800a0000d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT17" , 0x11800a0000d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT18" , 0x11800a0000db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT19" , 0x11800a0000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT36" , 0x11800a0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT37" , 0x11800a00013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT38" , 0x11800a00013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT3_PRT39" , 0x11800a0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT16" , 0x11800a0000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT17" , 0x11800a0000d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT18" , 0x11800a0000dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT19" , 0x11800a0000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT36" , 0x11800a0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT37" , 0x11800a00013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT38" , 0x11800a0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT4_PRT39" , 0x11800a0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT16" , 0x11800a0000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT17" , 0x11800a0000d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT18" , 0x11800a0000dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT19" , 0x11800a0000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT36" , 0x11800a0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT37" , 0x11800a00013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT38" , 0x11800a0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT5_PRT39" , 0x11800a0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT16" , 0x11800a0000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT17" , 0x11800a0000d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT18" , 0x11800a0000dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT19" , 0x11800a0000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT36" , 0x11800a0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT37" , 0x11800a00013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT38" , 0x11800a0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT6_PRT39" , 0x11800a0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT16" , 0x11800a0000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT17" , 0x11800a0000d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT18" , 0x11800a0000dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT19" , 0x11800a0000e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT36" , 0x11800a0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT37" , 0x11800a00013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT38" , 0x11800a0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT7_PRT39" , 0x11800a0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT16" , 0x11800a0000d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT17" , 0x11800a0000d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT18" , 0x11800a0000de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT19" , 0x11800a0000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT36" , 0x11800a0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT37" , 0x11800a00013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT38" , 0x11800a0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT8_PRT39" , 0x11800a0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT16" , 0x11800a0000d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT17" , 0x11800a0000d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT18" , 0x11800a0000de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT19" , 0x11800a0000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT36" , 0x11800a0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT37" , 0x11800a00013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT38" , 0x11800a0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT9_PRT39" , 0x11800a0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS16" , 0x11800a0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS17" , 0x11800a0001c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS18" , 0x11800a0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS19" , 0x11800a0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS36" , 0x11800a0001e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS37" , 0x11800a0001eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS38" , 0x11800a0001ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_ERRS39" , 0x11800a0001ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS16" , 0x11800a0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS17" , 0x11800a0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS18" , 0x11800a0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS19" , 0x11800a0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS36" , 0x11800a0001e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS37" , 0x11800a0001ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS38" , 0x11800a0001ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_OCTS39" , 0x11800a0001ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS16" , 0x11800a0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS17" , 0x11800a0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS18" , 0x11800a0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS19" , 0x11800a0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS36" , 0x11800a0001e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS37" , 0x11800a0001ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS38" , 0x11800a0001ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT_INB_PKTS39" , 0x11800a0001ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 736},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 737},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 738},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 739},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 741},
- {"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 742},
- {"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 743},
- {"POW_IQ_THR0" , 0x16700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"POW_IQ_THR1" , 0x16700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"POW_IQ_THR2" , 0x16700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"POW_IQ_THR3" , 0x16700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"POW_IQ_THR4" , 0x16700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"POW_IQ_THR5" , 0x16700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"POW_IQ_THR6" , 0x16700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"POW_IQ_THR7" , 0x16700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 745},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 746},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 747},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 751},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 752},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 754},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 756},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 812},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 813},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 817},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 819},
- {"USBC0_DAINT" , 0x16f0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 820},
- {"USBC0_DAINTMSK" , 0x16f001000081cull, CVMX_CSR_DB_TYPE_NCB, 32, 821},
- {"USBC0_DCFG" , 0x16f0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 822},
- {"USBC0_DCTL" , 0x16f0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 823},
- {"USBC0_DIEPCTL000" , 0x16f0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 824},
- {"USBC0_DIEPCTL001" , 0x16f0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 824},
- {"USBC0_DIEPCTL002" , 0x16f0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 824},
- {"USBC0_DIEPCTL003" , 0x16f0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 824},
- {"USBC0_DIEPCTL004" , 0x16f0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 824},
- {"USBC0_DIEPINT000" , 0x16f0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 825},
- {"USBC0_DIEPINT001" , 0x16f0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 825},
- {"USBC0_DIEPINT002" , 0x16f0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 825},
- {"USBC0_DIEPINT003" , 0x16f0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 825},
- {"USBC0_DIEPINT004" , 0x16f0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 825},
- {"USBC0_DIEPMSK" , 0x16f0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 826},
- {"USBC0_DIEPTSIZ000" , 0x16f0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 827},
- {"USBC0_DIEPTSIZ001" , 0x16f0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 827},
- {"USBC0_DIEPTSIZ002" , 0x16f0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 827},
- {"USBC0_DIEPTSIZ003" , 0x16f0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 827},
- {"USBC0_DIEPTSIZ004" , 0x16f0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 827},
- {"USBC0_DOEPCTL000" , 0x16f0010000b00ull, CVMX_CSR_DB_TYPE_NCB, 32, 828},
- {"USBC0_DOEPCTL001" , 0x16f0010000b20ull, CVMX_CSR_DB_TYPE_NCB, 32, 828},
- {"USBC0_DOEPCTL002" , 0x16f0010000b40ull, CVMX_CSR_DB_TYPE_NCB, 32, 828},
- {"USBC0_DOEPCTL003" , 0x16f0010000b60ull, CVMX_CSR_DB_TYPE_NCB, 32, 828},
- {"USBC0_DOEPCTL004" , 0x16f0010000b80ull, CVMX_CSR_DB_TYPE_NCB, 32, 828},
- {"USBC0_DOEPINT000" , 0x16f0010000b08ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
- {"USBC0_DOEPINT001" , 0x16f0010000b28ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
- {"USBC0_DOEPINT002" , 0x16f0010000b48ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
- {"USBC0_DOEPINT003" , 0x16f0010000b68ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
- {"USBC0_DOEPINT004" , 0x16f0010000b88ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
- {"USBC0_DOEPMSK" , 0x16f0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 830},
- {"USBC0_DOEPTSIZ000" , 0x16f0010000b10ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
- {"USBC0_DOEPTSIZ001" , 0x16f0010000b30ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
- {"USBC0_DOEPTSIZ002" , 0x16f0010000b50ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
- {"USBC0_DOEPTSIZ003" , 0x16f0010000b70ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
- {"USBC0_DOEPTSIZ004" , 0x16f0010000b90ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
- {"USBC0_DPTXFSIZ001" , 0x16f0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
- {"USBC0_DPTXFSIZ002" , 0x16f0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
- {"USBC0_DPTXFSIZ003" , 0x16f001000010cull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
- {"USBC0_DPTXFSIZ004" , 0x16f0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
- {"USBC0_DSTS" , 0x16f0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC0_DTKNQR1" , 0x16f0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC0_DTKNQR2" , 0x16f0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 835},
- {"USBC0_DTKNQR3" , 0x16f0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC0_DTKNQR4" , 0x16f0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC0_GAHBCFG" , 0x16f0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC0_GHWCFG1" , 0x16f0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 839},
- {"USBC0_GHWCFG2" , 0x16f0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC0_GHWCFG3" , 0x16f001000004cull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
- {"USBC0_GHWCFG4" , 0x16f0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 842},
- {"USBC0_GINTMSK" , 0x16f0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 843},
- {"USBC0_GINTSTS" , 0x16f0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 844},
- {"USBC0_GNPTXFSIZ" , 0x16f0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 845},
- {"USBC0_GNPTXSTS" , 0x16f001000002cull, CVMX_CSR_DB_TYPE_NCB, 32, 846},
- {"USBC0_GOTGCTL" , 0x16f0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 847},
- {"USBC0_GOTGINT" , 0x16f0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 848},
- {"USBC0_GRSTCTL" , 0x16f0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 849},
- {"USBC0_GRXFSIZ" , 0x16f0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 850},
- {"USBC0_GRXSTSPD" , 0x16f0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 851},
- {"USBC0_GRXSTSPH" , 0x16f0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 852},
- {"USBC0_GRXSTSRD" , 0x16f001004001cull, CVMX_CSR_DB_TYPE_NCB, 32, 853},
- {"USBC0_GRXSTSRH" , 0x16f001000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 854},
- {"USBC0_GSNPSID" , 0x16f0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 855},
- {"USBC0_GUSBCFG" , 0x16f001000000cull, CVMX_CSR_DB_TYPE_NCB, 32, 856},
- {"USBC0_HAINT" , 0x16f0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 857},
- {"USBC0_HAINTMSK" , 0x16f0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 858},
- {"USBC0_HCCHAR000" , 0x16f0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
- {"USBC0_HCCHAR001" , 0x16f0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
- {"USBC0_HCCHAR002" , 0x16f0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
- {"USBC0_HCCHAR003" , 0x16f0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
- {"USBC0_HCCHAR004" , 0x16f0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
- {"USBC0_HCCHAR005" , 0x16f00100005a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
- {"USBC0_HCCHAR006" , 0x16f00100005c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
- {"USBC0_HCCHAR007" , 0x16f00100005e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
- {"USBC0_HCFG" , 0x16f0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 860},
- {"USBC0_HCINT000" , 0x16f0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
- {"USBC0_HCINT001" , 0x16f0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
- {"USBC0_HCINT002" , 0x16f0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
- {"USBC0_HCINT003" , 0x16f0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
- {"USBC0_HCINT004" , 0x16f0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
- {"USBC0_HCINT005" , 0x16f00100005a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
- {"USBC0_HCINT006" , 0x16f00100005c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
- {"USBC0_HCINT007" , 0x16f00100005e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
- {"USBC0_HCINTMSK000" , 0x16f001000050cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
- {"USBC0_HCINTMSK001" , 0x16f001000052cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
- {"USBC0_HCINTMSK002" , 0x16f001000054cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
- {"USBC0_HCINTMSK003" , 0x16f001000056cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
- {"USBC0_HCINTMSK004" , 0x16f001000058cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
- {"USBC0_HCINTMSK005" , 0x16f00100005acull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
- {"USBC0_HCINTMSK006" , 0x16f00100005ccull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
- {"USBC0_HCINTMSK007" , 0x16f00100005ecull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
- {"USBC0_HCSPLT000" , 0x16f0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
- {"USBC0_HCSPLT001" , 0x16f0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
- {"USBC0_HCSPLT002" , 0x16f0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
- {"USBC0_HCSPLT003" , 0x16f0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
- {"USBC0_HCSPLT004" , 0x16f0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
- {"USBC0_HCSPLT005" , 0x16f00100005a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
- {"USBC0_HCSPLT006" , 0x16f00100005c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
- {"USBC0_HCSPLT007" , 0x16f00100005e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
- {"USBC0_HCTSIZ000" , 0x16f0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
- {"USBC0_HCTSIZ001" , 0x16f0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
- {"USBC0_HCTSIZ002" , 0x16f0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
- {"USBC0_HCTSIZ003" , 0x16f0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
- {"USBC0_HCTSIZ004" , 0x16f0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
- {"USBC0_HCTSIZ005" , 0x16f00100005b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
- {"USBC0_HCTSIZ006" , 0x16f00100005d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
- {"USBC0_HCTSIZ007" , 0x16f00100005f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
- {"USBC0_HFIR" , 0x16f0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 865},
- {"USBC0_HFNUM" , 0x16f0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 866},
- {"USBC0_HPRT" , 0x16f0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 867},
- {"USBC0_HPTXFSIZ" , 0x16f0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC0_HPTXSTS" , 0x16f0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 869},
- {"USBC0_NPTXDFIFO000" , 0x16f0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_NPTXDFIFO001" , 0x16f0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_NPTXDFIFO002" , 0x16f0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_NPTXDFIFO003" , 0x16f0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_NPTXDFIFO004" , 0x16f0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_NPTXDFIFO005" , 0x16f0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_NPTXDFIFO006" , 0x16f0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_NPTXDFIFO007" , 0x16f0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_PCGCCTL" , 0x16f0010000e00ull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBN0_BIST_STATUS" , 0x11800680007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
- {"USBN0_CTL_STATUS" , 0x16f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 874},
- {"USBN0_DMA0_INB_CHN0" , 0x16f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 875},
- {"USBN0_DMA0_INB_CHN1" , 0x16f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 876},
- {"USBN0_DMA0_INB_CHN2" , 0x16f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 877},
- {"USBN0_DMA0_INB_CHN3" , 0x16f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 878},
- {"USBN0_DMA0_INB_CHN4" , 0x16f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 879},
- {"USBN0_DMA0_INB_CHN5" , 0x16f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 880},
- {"USBN0_DMA0_INB_CHN6" , 0x16f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 881},
- {"USBN0_DMA0_INB_CHN7" , 0x16f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 882},
- {"USBN0_DMA0_OUTB_CHN0" , 0x16f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 883},
- {"USBN0_DMA0_OUTB_CHN1" , 0x16f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 884},
- {"USBN0_DMA0_OUTB_CHN2" , 0x16f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 885},
- {"USBN0_DMA0_OUTB_CHN3" , 0x16f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 886},
- {"USBN0_DMA0_OUTB_CHN4" , 0x16f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 887},
- {"USBN0_DMA0_OUTB_CHN5" , 0x16f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 888},
- {"USBN0_DMA0_OUTB_CHN6" , 0x16f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 889},
- {"USBN0_DMA0_OUTB_CHN7" , 0x16f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 890},
- {"USBN0_DMA_TEST" , 0x16f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 891},
- {"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
- {"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 893},
- {"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 894},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 898},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 899},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 900},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 901},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_21" , 3, 19, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_25" , 23, 3, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 0, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 10, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_5_7" , 5, 3, 2, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 2, "RAZ", 1, 1, 0, 0},
- {"BYP_EN" , 16, 1, 2, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 2, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 3, "RAZ", 1, 1, 0, 0},
- {"EN" , 1, 1, 3, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 3, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 4, "RO", 0, 0, 0ull, 0ull},
- {"DUPLEX" , 2, 1, 4, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 4, "RO", 0, 0, 0ull, 0ull},
- {"RX_EN" , 4, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"TX_EN" , 5, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 4, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 9, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 10, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 11, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 11, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 12, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 12, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 12, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 12, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 14, "RAZ", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 14, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 7, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 15, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 16, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 16, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 17, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 17, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 18, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 18, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 19, "RAZ", 1, 1, 0, 0},
- {"MAXERR" , 2, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 19, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 19, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 19, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 20, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 21, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 22, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 27, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 27, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 32, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 32, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 33, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 33, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 33, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 33, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 34, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 35, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 35, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 36, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 36, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 1, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 37, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 1, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 37, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 1, 38, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 38, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 1, 38, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 38, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 39, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 39, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 40, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 40, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 40, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 41, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 60, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 1, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 61, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 65, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 65, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 65, "RAZ", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 65, "RAZ", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 65, "RAZ", 0, 0, 0ull, 0ull},
- {"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 1, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 68, "RAZ", 0, 0, 0ull, 0ull},
- {"BP" , 4, 1, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 68, "RAZ", 0, 0, 0ull, 0ull},
- {"EN" , 8, 1, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 68, "RAZ", 0, 0, 0ull, 0ull},
- {"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 4, 71, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 71, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 12, 72, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 72, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 12, 73, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 73, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 74, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 74, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 75, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 75, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 75, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 75, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 75, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 75, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 75, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 12, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 76, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 77, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 77, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 77, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 77, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 77, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 77, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 12, 78, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 78, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 79, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 79, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 79, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 79, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 79, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 79, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 79, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 80, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 80, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 80, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 80, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 80, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 80, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 80, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 12, 81, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 81, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 82, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 83, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 12, 84, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 84, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 85, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 85, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 12, 86, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 86, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 87, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 88, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 11, 88, "R/W", 0, 0, 32767ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 88, "RAZ", 1, 1, 0, 0},
- {"QLM_DCOK" , 0, 4, 89, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 89, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 4, 90, "R/W", 0, 1, 0ull, 0},
- {"MUX_SEL" , 4, 2, 90, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 90, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 90, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 90, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 91, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 91, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_60" , 37, 24, 91, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 91, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 91, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 91, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 92, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 93, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 93, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 94, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 94, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 95, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 95, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 96, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 96, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 97, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 97, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 97, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 97, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 97, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 98, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 98, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 98, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 98, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 98, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 98, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 99, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 99, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 99, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 99, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 99, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 99, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 99, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 100, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 100, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 100, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 101, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 101, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 102, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 102, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 102, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 103, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 103, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 104, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 105, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 106, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 106, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 107, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 107, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 108, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 108, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 108, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 109, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 109, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 109, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 110, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 110, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 111, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 111, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 112, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 112, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 112, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 112, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 112, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 112, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 112, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 113, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 113, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 114, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 115, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 115, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 115, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 2, 115, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 115, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 2, 115, "RO", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 115, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 116, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 116, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 117, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 117, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 117, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 117, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 117, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 117, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 117, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 117, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 117, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 117, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 118, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 119, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 120, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 121, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 122, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 123, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 124, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 124, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 125, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 125, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 125, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 125, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 126, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 126, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 127, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 127, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 127, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 127, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 127, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 127, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 127, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 127, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 127, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 128, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 128, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 128, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 128, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 128, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 128, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 128, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 128, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 129, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 129, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 130, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 130, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 130, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 130, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 130, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 130, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 131, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 131, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 131, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 131, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 131, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 131, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 132, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 132, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 133, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 133, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 134, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 135, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 135, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 136, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 136, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 137, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 137, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 138, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 138, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 139, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 140, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 141, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 141, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 142, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 142, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 143, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 143, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 144, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 144, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 144, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 145, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 145, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 146, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 146, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 147, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 147, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 4, 148, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 148, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 4, 148, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 148, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 149, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 149, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 150, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 150, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 150, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 150, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 150, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 151, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 151, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 152, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 152, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 153, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 153, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 154, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 154, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 154, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 154, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 154, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 155, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 155, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 156, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 156, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 156, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 157, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 157, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 158, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 158, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 159, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 159, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 160, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 160, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 161, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 161, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 162, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 162, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 163, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 163, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 164, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 164, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 165, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 165, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 166, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 166, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 167, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 167, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 168, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 168, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 169, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 169, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 170, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 170, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 171, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 171, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 172, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 172, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 173, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 173, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 174, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 174, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 175, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 176, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 176, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 177, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 177, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 178, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 178, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 179, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 179, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 180, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 180, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 180, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 181, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 181, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 181, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 181, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 181, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 182, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 182, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 182, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 183, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 183, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 184, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 184, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 185, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 185, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 185, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 185, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 186, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 186, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 187, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 187, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 188, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_5_63" , 5, 59, 188, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 189, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 189, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 189, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 189, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 189, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 189, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 189, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 190, "R/W", 0, 0, 8ull, 8ull},
- {"EN" , 4, 1, 190, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 190, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 191, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 191, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 191, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 191, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 192, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 192, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 193, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 193, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 194, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 195, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 195, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 196, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 196, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 197, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 198, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 198, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 198, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 198, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 199, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 199, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 200, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 200, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 200, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 201, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 201, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 201, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 202, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 202, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 202, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 202, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 202, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 203, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 203, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 203, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 203, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 203, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 204, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 205, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 206, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 207, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 208, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 208, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 209, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 209, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 210, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 210, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 211, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 211, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 211, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 211, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 211, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 212, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 212, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 212, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 212, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 212, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 213, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 214, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 215, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 215, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 215, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 216, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 216, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 216, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 217, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 217, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 218, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 218, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 219, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 219, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 220, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 220, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 221, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 222, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 40, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 223, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 224, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 225, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 225, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 225, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 226, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 227, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 228, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 229, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 229, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 230, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 230, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 231, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 231, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 232, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 232, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 232, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 233, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 233, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 234, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 234, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 235, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 235, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 236, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 237, "R/W", 0, 0, 0ull, 1ull},
- {"RADDR" , 0, 3, 238, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 238, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 238, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 238, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 238, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 238, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 239, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 239, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 239, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_44_63" , 44, 20, 239, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 240, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 240, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 240, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 240, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 241, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 241, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 241, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 241, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 241, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 241, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_61_63" , 61, 3, 241, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 242, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 242, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 243, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 243, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 244, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 244, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 244, "R/W", 0, 0, 0ull, 0ull},
- {"PRT_ENB" , 0, 4, 245, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 245, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 246, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 246, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 246, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 246, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 246, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 247, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 247, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 247, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 248, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_35" , 32, 4, 248, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT2" , 36, 4, 248, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_40_63" , 40, 24, 248, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 249, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 249, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 249, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 250, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 250, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 251, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 251, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 252, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 253, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 253, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 253, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 254, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 254, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 254, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 254, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 254, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 255, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 255, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 255, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 255, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 255, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 256, "RO", 0, 0, 0ull, 0ull},
- {"STIN_MSK" , 4, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 13, 256, "RO", 0, 0, 0ull, 0ull},
- {"WLB_MSK" , 19, 4, 256, "RO", 0, 0, 0ull, 0ull},
- {"DTBNK" , 23, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 256, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 9, 257, "RO", 0, 0, 0ull, 0ull},
- {"VAB_VWCF0" , 9, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 257, "RAZ", 0, 0, 0ull, 0ull},
- {"VAB_VWCF1" , 11, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"VWDF0" , 12, 4, 257, "RO", 0, 0, 0ull, 0ull},
- {"VWDF1" , 16, 4, 257, "RO", 0, 0, 0ull, 0ull},
- {"ILC" , 20, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"PLC0" , 21, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"PLC1" , 22, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"PLC2" , 23, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 257, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"PICBST" , 2, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RHDB" , 4, 4, 258, "RO", 0, 0, 0ull, 0ull},
- {"RMDB" , 8, 4, 258, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 258, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 259, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 259, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 259, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 259, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 259, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 259, "R/W", 0, 0, 0ull, 0ull},
- {"DFILL_DIS" , 14, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"DPRES0" , 15, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"DPRES1" , 16, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_BANK" , 17, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"LBIST" , 18, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"BSTRUN" , 19, 1, 259, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 259, "RAZ", 1, 1, 0, 0},
- {"L2T" , 0, 1, 260, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 260, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 260, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 3, 260, "R/W", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 4, 260, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 260, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 4, 260, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 260, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 261, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 261, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 261, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 261, "RAZ", 0, 0, 0ull, 0ull},
- {"PLC0RMSK" , 0, 32, 262, "R/W", 0, 0, 0ull, 0ull},
- {"PLC1RMSK" , 32, 32, 262, "R/W", 0, 0, 0ull, 0ull},
- {"PLC2RMSK" , 0, 32, 263, "R/W", 0, 0, 0ull, 0ull},
- {"ILCRMSK" , 32, 32, 263, "R/W", 0, 0, 0ull, 0ull},
- {"OOB1EN" , 0, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"OOB2EN" , 1, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"OOB3EN" , 2, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"L2TSECEN" , 3, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"L2TDEDEN" , 4, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"L2DSECEN" , 5, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDEDEN" , 6, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"LCKENA" , 7, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"LCK2ENA" , 8, 1, 264, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 264, "RAZ", 0, 0, 0ull, 0ull},
- {"OOB1" , 0, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
- {"OOB2" , 1, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
- {"OOB3" , 2, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2TSEC" , 3, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2TDED" , 4, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2DSEC" , 5, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2DDED" , 6, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK" , 7, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK2" , 8, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 265, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 266, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 266, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 266, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 266, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 267, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 267, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 268, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 268, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 268, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 4, 268, "RO", 0, 0, 0ull, 0ull},
- {"SET" , 18, 3, 268, "RO", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 268, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 268, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 4, 268, "RO", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 268, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 268, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 268, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 268, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 268, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 268, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 269, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 269, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 11, 270, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 11, 16, 270, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 270, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 4, 271, "R/W", 0, 0, 15ull, 15ull},
- {"STPARTDIS" , 4, 1, 271, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 271, "RAZ", 0, 0, 0ull, 0ull},
- {"STENA" , 0, 1, 272, "R/W", 0, 0, 0ull, 0ull},
- {"DWBENA" , 1, 1, 272, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 272, "RAZ", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 273, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 273, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 273, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 273, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 273, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 274, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 274, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 274, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 274, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 274, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 274, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 275, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 275, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 275, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 275, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 275, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 275, "RO", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 276, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 276, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 277, "RAZ", 0, 0, 0ull, 0ull},
- {"PP0GRP" , 0, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP1GRP" , 2, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP2GRP" , 4, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP3GRP" , 6, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP4GRP" , 8, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP5GRP" , 10, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP6GRP" , 12, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP7GRP" , 14, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP8GRP" , 16, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP9GRP" , 18, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP10GRP" , 20, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"PP11GRP" , 22, 2, 278, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 278, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 8, 279, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK1" , 8, 8, 279, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK2" , 16, 8, 279, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK3" , 24, 8, 279, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 279, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK4" , 0, 8, 280, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK5" , 8, 8, 280, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK6" , 16, 8, 280, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK7" , 24, 8, 280, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 280, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK8" , 0, 8, 281, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK9" , 8, 8, 281, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK10" , 16, 8, 281, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK11" , 24, 8, 281, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 281, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 8, 282, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 282, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 283, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 283, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 283, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 284, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 284, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 285, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 286, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 287, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 287, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 287, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 287, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 287, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 287, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 287, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 11, 288, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 3, 288, "RO", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 288, "RO", 0, 0, 0ull, 0ull},
- {"FADRU" , 18, 1, 288, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 288, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 289, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 289, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 289, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 290, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 290, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 290, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 292, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 293, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 293, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 294, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_1024K" , 34, 1, 294, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_512K" , 35, 1, 294, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_36" , 36, 1, 294, "RO", 0, 0, 0ull, 0ull},
- {"EMA_CTL" , 37, 3, 294, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 294, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 295, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 295, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 295, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 10, 295, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 3, 295, "RO", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 295, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 295, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"FADRU" , 28, 1, 295, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 295, "RAZ", 0, 0, 0ull, 0ull},
- {"RATE" , 0, 8, 296, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_63" , 8, 56, 296, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 7, 297, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_7_63" , 7, 57, 297, "RAZ", 1, 1, 0, 0},
- {"RATE" , 0, 16, 298, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 298, "RAZ", 1, 1, 0, 0},
- {"DBG_EN" , 0, 1, 299, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 299, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 300, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 300, "RAZ", 1, 1, 0, 0},
- {"POLARITY" , 0, 1, 301, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 301, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 8, 302, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 302, "RAZ", 1, 1, 0, 0},
- {"FORMAT" , 0, 4, 303, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 303, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 304, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 304, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 305, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 305, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 32, 306, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 306, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 32, 307, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 307, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 32, 308, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 308, "RAZ", 1, 1, 0, 0},
- {"START" , 0, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 309, "RAZ", 1, 0, 0, 0ull},
- {"MRD" , 0, 3, 310, "RO", 1, 0, 0, 0ull},
- {"MRF" , 3, 1, 310, "RO", 1, 0, 0, 0ull},
- {"MWC" , 4, 1, 310, "RO", 1, 0, 0, 0ull},
- {"MWD" , 5, 3, 310, "RO", 1, 0, 0, 0ull},
- {"MWF" , 8, 1, 310, "RO", 1, 0, 0, 0ull},
- {"CSRE2D" , 9, 1, 310, "RO", 1, 0, 0, 0ull},
- {"CSRD2E" , 10, 1, 310, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 310, "RAZ", 1, 0, 0, 0ull},
- {"PCTL_DAT" , 0, 5, 311, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_11" , 5, 7, 311, "RAZ", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 311, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 311, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_27" , 20, 8, 311, "RAZ", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 311, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 311, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 312, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 312, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 312, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 312, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 312, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 312, "R/W", 0, 0, 0ull, 1ull},
- {"MODE32B" , 10, 1, 312, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 11, 1, 312, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MRF" , 12, 1, 312, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 312, "RAZ", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 312, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 312, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_17" , 16, 2, 312, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 312, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 312, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 312, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 312, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 312, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 312, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 313, "RAZ", 0, 1, 0ull, 0},
- {"DCC_ENABLE" , 8, 1, 313, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_MODE" , 9, 1, 313, "R/W", 0, 0, 0ull, 1ull},
- {"SEQUENCE" , 10, 3, 313, "R/W", 0, 0, 0ull, 0ull},
- {"IDLEPOWER" , 13, 3, 313, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 16, 4, 313, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 20, 1, 313, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_63" , 21, 43, 313, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 314, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 314, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 315, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 315, "RAZ", 1, 1, 0, 0},
- {"DCLK90_VLU" , 0, 5, 316, "R/W", 0, 1, 0ull, 0},
- {"DCLK90_LD" , 5, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"DCLK90_BYP" , 6, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"OFF90_ENA" , 7, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 316, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 317, "R/W", 0, 0, 1ull, 1ull},
- {"RDQS" , 1, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 317, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 317, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 317, "R/W", 0, 0, 0ull, 0ull},
- {"SILO_HC" , 21, 1, 317, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 317, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 317, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 317, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 317, "RAZ", 0, 0, 0ull, 0ull},
- {"CLK" , 0, 4, 318, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 318, "RAZ", 0, 0, 0ull, 0ull},
- {"CMD" , 5, 4, 318, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 318, "RAZ", 0, 0, 0ull, 0ull},
- {"DQ" , 10, 4, 318, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 318, "RAZ", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 0, 5, 319, "R/W", 0, 1, 0ull, 0},
- {"DLL90_ENA" , 5, 1, 319, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 6, 1, 319, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 7, 1, 319, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 319, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 320, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 320, "RAZ", 0, 1, 0ull, 0},
- {"ROW_LSB" , 16, 3, 320, "R/W", 0, 1, 3ull, 0},
- {"BANK8" , 19, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 320, "RAZ", 0, 1, 0ull, 0},
- {"MRDSYN0" , 0, 8, 321, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 321, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 321, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 321, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 321, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 322, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 322, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 322, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 322, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 322, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 322, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 323, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 323, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 324, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 324, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 325, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 325, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 325, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 325, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 325, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 325, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 325, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 325, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 325, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 326, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 326, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 326, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 326, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 326, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 326, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 326, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 326, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_31_63" , 31, 33, 326, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 327, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 327, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 328, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 328, "RAZ", 1, 1, 0, 0},
- {"EN2" , 0, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"EN4" , 1, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"EN6" , 2, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"EN8" , 3, 1, 329, "R/W", 0, 1, 1ull, 0},
- {"EN12" , 4, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"EN16" , 5, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 329, "RAZ", 0, 1, 0ull, 0},
- {"CLKR" , 8, 6, 329, "R/W", 0, 1, 0ull, 0},
- {"CLKF" , 14, 12, 329, "R/W", 0, 1, 31ull, 0},
- {"RESET_N" , 26, 1, 329, "R/W", 0, 0, 0ull, 1ull},
- {"DIV_RESET" , 27, 1, 329, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 329, "RAZ", 0, 1, 0ull, 0},
- {"FBSLIP" , 0, 1, 330, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 330, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_21" , 2, 20, 330, "RAZ", 1, 1, 0, 0},
- {"DDR__PCTL" , 22, 5, 330, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 27, 5, 330, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 330, "RAZ", 1, 1, 0, 0},
- {"BNK" , 0, 3, 331, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 331, "RAZ", 0, 0, 0ull, 0ull},
- {"COL" , 4, 12, 331, "R/W", 0, 0, 0ull, 0ull},
- {"ROW" , 16, 16, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PATTERN" , 32, 8, 331, "R/W", 0, 0, 170ull, 170ull},
- {"RANKMASK" , 40, 4, 331, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_63" , 44, 20, 331, "RAZ", 0, 0, 0ull, 0ull},
- {"BYTE" , 0, 4, 332, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 332, "RAZ", 0, 0, 0ull, 0ull},
- {"BITMASK" , 16, 16, 332, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 332, "RAZ", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 4, 333, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 4, 4, 333, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 8, 4, 333, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 12, 4, 333, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 16, 4, 333, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 20, 4, 333, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 24, 4, 333, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 28, 4, 333, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 32, 4, 333, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 36, 2, 333, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 333, "RAZ", 1, 0, 0, 0ull},
- {"PCTL" , 0, 5, 334, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 334, "RAZ", 0, 1, 0ull, 0},
- {"NCTL" , 8, 4, 334, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 334, "RAZ", 0, 1, 0ull, 0},
- {"ENABLE" , 16, 1, 334, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 334, "RAZ", 0, 1, 0ull, 0},
- {"RODT_LO0" , 0, 4, 335, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_LO1" , 4, 4, 335, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_LO2" , 8, 4, 335, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_LO3" , 12, 4, 335, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI0" , 16, 4, 335, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI1" , 20, 4, 335, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI2" , 24, 4, 335, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI3" , 28, 4, 335, "R/W", 0, 0, 15ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 335, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 336, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D0_R1" , 8, 8, 336, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R0" , 16, 8, 336, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R1" , 24, 8, 336, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 336, "RAZ", 0, 0, 0ull, 0ull},
- {"WODT_D2_R0" , 0, 8, 337, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R1" , 8, 8, 337, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R0" , 16, 8, 337, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R1" , 24, 8, 337, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 337, "RAZ", 0, 0, 0ull, 0ull},
- {"NCBI" , 0, 1, 338, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 338, "RO", 0, 0, 0ull, 0ull},
- {"DMA" , 2, 1, 338, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 3, 1, 338, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 338, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 339, "R/W", 0, 1, 31ull, 0},
- {"PCTL" , 5, 5, 339, "R/W", 0, 1, 31ull, 0},
- {"RESERVED_10_63" , 10, 54, 339, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 340, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 340, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 340, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 341, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 341, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 341, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 342, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 342, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 343, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 343, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 343, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 343, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 343, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 343, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 343, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 343, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 343, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 343, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 343, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 344, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 345, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 346, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 346, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 346, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 347, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 347, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 347, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 347, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 348, "R/W", 1, 1, 0, 0},
- {"BASE" , 0, 16, 349, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 349, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 349, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 349, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 349, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 349, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 349, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 349, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 349, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 349, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 349, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 349, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 349, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 350, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 350, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 350, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 350, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 350, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 350, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 350, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 350, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 350, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 350, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 350, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 350, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 350, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 351, "R/W", 0, 0, 26ull, 26ull},
- {"RESERVED_6_7" , 6, 2, 351, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 351, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 351, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 351, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 351, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 352, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 353, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 353, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 354, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 354, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 12, 355, "RO", 1, 1, 0, 0},
- {"RESERVED_12_15" , 12, 4, 355, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 355, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 355, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 355, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 355, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 355, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 355, "RO", 1, 1, 0, 0},
- {"NOKASU" , 29, 1, 355, "RO", 1, 1, 0, 0},
- {"RESERVED_30_31" , 30, 2, 355, "RAZ", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 355, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 355, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 355, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 356, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 356, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 356, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 356, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 356, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 356, "RO", 1, 1, 0, 0},
- {"ZIP_CRIP" , 29, 2, 356, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 356, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 357, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_3_3" , 3, 1, 357, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 357, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_63" , 7, 57, 357, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 358, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 359, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 359, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 359, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 360, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 360, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 8, 361, "R/W", 0, 1, 3ull, 0},
- {"SCLK_HI" , 8, 12, 361, "R/W", 0, 1, 100ull, 0},
- {"SCLK_LO" , 20, 4, 361, "R/W", 0, 1, 2ull, 0},
- {"OUT" , 24, 8, 361, "R/W", 0, 1, 3ull, 0},
- {"PROG_PIN" , 32, 1, 361, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 361, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 362, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 362, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 362, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 362, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 362, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 363, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 14, 14, 363, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 28, 14, 363, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 363, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 364, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 364, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 3, 365, "R/W", 1, 1, 0, 0},
- {"RESERVED_3_63" , 3, 61, 365, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 366, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 366, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 366, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 366, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 366, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 366, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 366, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 366, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 367, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 367, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 367, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 367, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 367, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 367, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 367, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 368, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 368, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 368, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 369, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 369, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 369, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 370, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 370, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 371, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 371, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 372, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 372, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 373, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 373, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 373, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 373, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 373, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 373, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 373, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 374, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 374, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 375, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 375, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 376, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 376, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 376, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 376, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 377, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 377, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 377, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 378, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 378, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 378, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 378, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 378, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 378, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 378, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 378, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 378, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 379, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 379, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 379, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 379, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 379, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 379, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 379, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 380, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 380, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 380, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 380, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 380, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 380, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 380, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 380, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 380, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 381, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 381, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 382, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 382, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 383, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 383, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 383, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 383, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 384, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 385, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 385, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 386, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 386, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 387, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 387, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 387, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 387, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 388, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 388, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 389, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 389, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 390, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 390, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 391, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 391, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 392, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 392, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 393, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 393, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 394, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 394, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 394, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 394, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 394, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 394, "RAZ", 1, 1, 0, 0},
- {"ORFDAT" , 0, 1, 395, "RO", 0, 0, 0ull, 0ull},
- {"IRFDAT" , 1, 1, 395, "RO", 0, 0, 0ull, 0ull},
- {"IPFDAT" , 2, 1, 395, "RO", 0, 0, 0ull, 0ull},
- {"MRQDAT" , 3, 1, 395, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 395, "RAZ", 0, 0, 0ull, 0ull},
- {"MRQ_HWM" , 0, 2, 396, "R/W", 0, 0, 0ull, 1ull},
- {"NBTARB" , 2, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"LENDIAN" , 3, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 4, 1, 396, "RAZ", 0, 0, 0ull, 0ull},
- {"EN" , 5, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 6, 1, 396, "RO", 0, 0, 0ull, 0ull},
- {"CRC_STRIP" , 7, 1, 396, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 396, "RAZ", 1, 1, 0, 0},
- {"OVFENA" , 0, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"IVFENA" , 1, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"OTHENA" , 2, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"ITHENA" , 3, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_DRPENA" , 4, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"IRUNENA" , 5, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"ORUNENA" , 6, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 397, "RAZ", 1, 1, 0, 0},
- {"IRCNT" , 0, 20, 398, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 398, "RAZ", 1, 1, 0, 0},
- {"IRHWM" , 0, 20, 399, "R/W", 0, 0, 0ull, 0ull},
- {"IBPLWM" , 20, 20, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 399, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 400, "RAZ", 1, 1, 0, 0},
- {"IBASE" , 3, 33, 400, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 400, "RAZ", 1, 1, 0, 0},
- {"ISIZE" , 40, 20, 400, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 400, "RAZ", 1, 1, 0, 0},
- {"IDBELL" , 0, 20, 401, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 401, "RAZ", 1, 1, 0, 0},
- {"ITLPTR" , 32, 20, 401, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 401, "RAZ", 1, 1, 0, 0},
- {"ODBLOVF" , 0, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"IDBLOVF" , 1, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORTHRESH" , 2, 1, 402, "RO", 0, 0, 0ull, 0ull},
- {"IRTHRESH" , 3, 1, 402, "RO", 0, 0, 0ull, 0ull},
- {"DATA_DRP" , 4, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"IRUN" , 5, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORUN" , 6, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 402, "RAZ", 1, 1, 0, 0},
- {"ORCNT" , 0, 20, 403, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 403, "RAZ", 1, 1, 0, 0},
- {"ORHWM" , 0, 20, 404, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 404, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 405, "RAZ", 1, 1, 0, 0},
- {"OBASE" , 3, 33, 405, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 405, "RAZ", 1, 1, 0, 0},
- {"OSIZE" , 40, 20, 405, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 405, "RAZ", 1, 1, 0, 0},
- {"ODBELL" , 0, 20, 406, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 406, "RAZ", 1, 1, 0, 0},
- {"OTLPTR" , 32, 20, 406, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 406, "RAZ", 1, 1, 0, 0},
- {"OREMCNT" , 0, 20, 407, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 407, "RAZ", 1, 1, 0, 0},
- {"IREMCNT" , 32, 20, 407, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_52_63" , 52, 12, 407, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 408, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 408, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 408, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 408, "RAZ", 1, 1, 0, 0},
- {"NCB_CMD" , 0, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"DIF4" , 2, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"DIF3" , 3, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"DIF2" , 4, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"DIF1" , 5, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"DIF0" , 6, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"CSM1" , 7, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"CSM0" , 8, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P1" , 9, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_CO" , 19, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_NO" , 20, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_PO" , 21, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_CO" , 22, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_NO" , 23, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_PO" , 24, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P1" , 25, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_O" , 27, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_C" , 28, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_O" , 29, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"D4_PST" , 31, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"D3_PST" , 32, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"D2_PST" , 33, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"D1_PST" , 34, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"D0_PST" , 35, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"D4_MEM" , 36, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"D3_MEM" , 37, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"D2_MEM" , 38, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"D1_MEM" , 39, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"D0_MEM" , 40, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_S1" , 41, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_S0" , 42, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_I1" , 43, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_I0" , 44, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_OUT" , 45, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_OIF" , 46, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_ODF" , 47, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_SLM" , 48, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_IND" , 49, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_CNTM" , 50, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_IMEM" , 51, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PKT_POUT" , 52, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_SL" , 53, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_ID" , 54, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_CNT" , 55, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_IM" , 56, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_INT" , 57, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 409, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_CAX" , 1, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 2, 2, 410, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 4, 1, 410, "R/W", 0, 0, 0ull, 1ull},
- {"PTLP_RO" , 5, 1, 410, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 410, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 410, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 410, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 410, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 410, "R/W", 0, 0, 3ull, 3ull},
- {"INTA" , 16, 1, 410, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 17, 1, 410, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 18, 1, 410, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 19, 1, 410, "RO", 0, 0, 1ull, 1ull},
- {"WAITL_COM" , 20, 1, 410, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_63" , 21, 43, 410, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 411, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_CAX" , 1, 1, 411, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 2, 2, 411, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 4, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"PTLP_RO" , 5, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 411, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 411, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 411, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 411, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 411, "R/W", 0, 0, 3ull, 3ull},
- {"INTA" , 16, 1, 411, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 17, 1, 411, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 18, 1, 411, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 19, 1, 411, "RO", 0, 0, 1ull, 1ull},
- {"WAITL_COM" , 20, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_63" , 21, 43, 411, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 412, "RO", 1, 1, 0, 0},
- {"HOST_MODE" , 8, 1, 412, "RO", 1, 1, 0, 0},
- {"PKT_BP" , 9, 4, 412, "R/W", 0, 0, 15ull, 15ull},
- {"ARB" , 13, 1, 412, "R/W", 0, 0, 0ull, 1ull},
- {"LNK_RST" , 14, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 412, "RAZ", 1, 1, 0, 0},
- {"C0_B0_D" , 0, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"C0_WI_D" , 1, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"C1_B0_D" , 2, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"C1_WI_D" , 3, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"C0_B1_S" , 4, 3, 413, "R/W", 0, 0, 1ull, 1ull},
- {"C1_B1_S" , 7, 3, 413, "R/W", 0, 0, 1ull, 1ull},
- {"C0_W_FLT" , 10, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"C1_W_FLT" , 11, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"MRRS" , 12, 3, 413, "R/W", 0, 0, 2ull, 2ull},
- {"MPS" , 15, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 413, "RAZ", 1, 1, 0, 0},
- {"P0_FCNT" , 0, 6, 414, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 414, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 414, "RO", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 414, "RO", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 414, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 415, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 415, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 415, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 23, 2, 415, "RO", 1, 1, 0, 0},
- {"QLM3_SPD" , 25, 2, 415, "RO", 1, 1, 0, 0},
- {"QLM0_REV_LANES" , 27, 1, 415, "RO", 1, 1, 0, 0},
- {"QLM2_REV_LANES" , 28, 1, 415, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 415, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 416, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 416, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 417, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 417, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 417, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 418, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 418, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 419, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 29, 419, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 419, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 420, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 420, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 421, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 421, "R/W", 0, 1, 0ull, 0},
- {"CNT" , 0, 32, 422, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 422, "R/W", 0, 1, 0ull, 0},
- {"DMA0" , 0, 32, 423, "R/W", 0, 1, 0ull, 0},
- {"DMA1" , 32, 32, 423, "R/W", 0, 1, 0ull, 0},
- {"CSIZE" , 0, 14, 424, "R/W", 0, 1, 0ull, 0},
- {"O_MODE" , 14, 1, 424, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 424, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 424, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 424, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 424, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 424, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 424, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 424, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 424, "R/W", 0, 0, 0ull, 0ull},
- {"DMA0_ENB" , 34, 1, 424, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1_ENB" , 35, 1, 424, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2_ENB" , 36, 1, 424, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3_ENB" , 37, 1, 424, "R/W", 0, 0, 0ull, 1ull},
- {"DMA4_ENB" , 38, 1, 424, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_39_63" , 39, 25, 424, "RAZ", 1, 1, 0, 0},
- {"D4_REQST" , 0, 5, 425, "RO", 0, 1, 0ull, 0},
- {"D3_REQST" , 5, 5, 425, "RO", 0, 1, 0ull, 0},
- {"D2_REQST" , 10, 5, 425, "RO", 0, 1, 0ull, 0},
- {"D1_REQST" , 15, 5, 425, "RO", 0, 1, 0ull, 0},
- {"D0_REQST" , 20, 5, 425, "RO", 0, 1, 0ull, 0},
- {"D4_DIFST" , 25, 7, 425, "RO", 0, 1, 0ull, 0},
- {"D3_DIFST" , 32, 7, 425, "RO", 0, 1, 0ull, 0},
- {"D2_DIFST" , 39, 7, 425, "RO", 0, 1, 0ull, 0},
- {"D1_DIFST" , 46, 7, 425, "RO", 0, 1, 0ull, 0},
- {"D0_DIFST" , 53, 7, 425, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 425, "RAZ", 0, 0, 0ull, 0ull},
- {"D4_DFFST" , 0, 9, 426, "RO", 0, 1, 0ull, 0},
- {"D3_DFFST" , 9, 9, 426, "RO", 0, 1, 0ull, 0},
- {"D2_DFFST" , 18, 9, 426, "RO", 0, 1, 0ull, 0},
- {"D1_DFFST" , 27, 9, 426, "RO", 0, 1, 0ull, 0},
- {"D0_DFFST" , 36, 9, 426, "RO", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 426, "RAZ", 0, 0, 0ull, 0ull},
- {"D3_DREST" , 0, 15, 427, "RO", 0, 1, 0ull, 0},
- {"D2_DREST" , 15, 15, 427, "RO", 0, 1, 0ull, 0},
- {"D1_DREST" , 30, 15, 427, "RO", 0, 1, 0ull, 0},
- {"D0_DREST" , 45, 15, 427, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 427, "RAZ", 0, 0, 0ull, 0ull},
- {"D3_DWEST" , 0, 13, 428, "RO", 0, 1, 0ull, 0},
- {"D2_DWEST" , 13, 13, 428, "RO", 0, 1, 0ull, 0},
- {"D1_DWEST" , 26, 13, 428, "RO", 0, 1, 0ull, 0},
- {"D0_DWEST" , 39, 13, 428, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 428, "RAZ", 0, 0, 0ull, 0ull},
- {"D4_DWEST" , 0, 13, 429, "RO", 0, 1, 0ull, 0},
- {"D4_DREST" , 13, 15, 429, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 429, "RAZ", 0, 0, 0ull, 0ull},
- {"RML_RTO" , 0, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0DBO" , 4, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1DBO" , 5, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2DBO" , 6, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3DBO" , 7, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DMA4DBO" , 8, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0FI" , 9, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1FI" , 10, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT0" , 11, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT1" , 12, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME0" , 13, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME1" , 14, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"PSLDBOF" , 15, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"PIDBOF" , 16, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 17, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 18, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_AERI" , 19, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_20" , 20, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_SE" , 21, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_22" , 22, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_WAKE" , 23, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_PMEI" , 24, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_HPINT" , 25, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_AERI" , 26, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_SE" , 28, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_29_29" , 29, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_WAKE" , 30, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_PMEI" , 31, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_HPINT" , 32, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B0" , 33, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B1" , 34, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B2" , 35, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WI" , 36, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_BX" , 37, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B0" , 38, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B1" , 39, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B2" , 40, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WI" , 41, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_BX" , 42, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B0" , 43, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B1" , 44, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B2" , 45, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WI" , 46, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_BX" , 47, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B0" , 48, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B1" , 49, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B2" , 50, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WI" , 51, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_BX" , 52, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WF" , 53, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WF" , 54, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WF" , 55, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WF" , 56, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_EXC" , 57, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_EXC" , 58, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C0_LDWN" , 59, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"C1_LDWN" , 60, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_61_62" , 61, 2, 430, "RAZ", 0, 1, 0ull, 0},
- {"MIO_INTA" , 63, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"RML_RTO" , 0, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0DBO" , 4, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1DBO" , 5, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2DBO" , 6, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3DBO" , 7, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DMA4DBO" , 8, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0FI" , 9, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1FI" , 10, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT0" , 11, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT1" , 12, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME0" , 13, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME1" , 14, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"PSLDBOF" , 15, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"PIDBOF" , 16, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 17, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 18, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_AERI" , 19, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_20" , 20, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_SE" , 21, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_22" , 22, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_WAKE" , 23, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_PMEI" , 24, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_HPINT" , 25, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_AERI" , 26, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_SE" , 28, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_29_29" , 29, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_WAKE" , 30, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_PMEI" , 31, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_HPINT" , 32, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B0" , 33, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B1" , 34, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B2" , 35, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WI" , 36, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_BX" , 37, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B0" , 38, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B1" , 39, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B2" , 40, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WI" , 41, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_BX" , 42, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B0" , 43, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B1" , 44, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B2" , 45, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WI" , 46, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_BX" , 47, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B0" , 48, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B1" , 49, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B2" , 50, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WI" , 51, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_BX" , 52, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WF" , 53, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WF" , 54, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WF" , 55, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WF" , 56, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_EXC" , 57, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_EXC" , 58, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C0_LDWN" , 59, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"C1_LDWN" , 60, 1, 431, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_61_63" , 61, 3, 431, "RAZ", 0, 1, 0ull, 0},
- {"PSLDBOF" , 0, 6, 432, "RO", 0, 1, 0ull, 0},
- {"PIDBOF" , 6, 6, 432, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 432, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0DBO" , 4, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1DBO" , 5, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA2DBO" , 6, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA3DBO" , 7, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA4DBO" , 8, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0FI" , 9, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1FI" , 10, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 11, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 12, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 13, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 14, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_18" , 15, 4, 433, "RAZ", 0, 0, 0ull, 0ull},
- {"C0_AERI" , 19, 1, 433, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_SE" , 21, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_WAKE" , 23, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_PMEI" , 24, 1, 433, "RO", 0, 0, 0ull, 0ull},
- {"C0_HPINT" , 25, 1, 433, "RO", 0, 0, 0ull, 0ull},
- {"C1_AERI" , 26, 1, 433, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_SE" , 28, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_29" , 29, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_WAKE" , 30, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_PMEI" , 31, 1, 433, "RO", 0, 0, 0ull, 0ull},
- {"C1_HPINT" , 32, 1, 433, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B0" , 33, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_B1" , 34, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_B2" , 35, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_WI" , 36, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_BX" , 37, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B0" , 38, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B1" , 39, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B2" , 40, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_WI" , 41, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_BX" , 42, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B0" , 43, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B1" , 44, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B2" , 45, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_WI" , 46, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_BX" , 47, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B0" , 48, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B1" , 49, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B2" , 50, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_WI" , 51, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_BX" , 52, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_WF" , 53, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_WF" , 54, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_WF" , 55, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_WF" , 56, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_EXC" , 57, 1, 433, "RO", 0, 0, 0ull, 0ull},
- {"C1_EXC" , 58, 1, 433, "RO", 0, 0, 0ull, 0ull},
- {"C0_LDWN" , 59, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_LDWN" , 60, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_61_62" , 61, 2, 433, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO_INTA" , 63, 1, 433, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 434, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 435, "RO", 0, 1, 0ull, 0},
- {"TIMER" , 0, 10, 436, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 436, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 436, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 30, 437, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 30, 1, 437, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 31, 1, 437, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 32, 1, 437, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 33, 1, 437, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 437, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 437, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 437, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 2, 437, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 41, 1, 437, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 437, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 438, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 439, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 440, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 441, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 443, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 444, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 445, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 446, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 446, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 446, "RAZ", 1, 1, 0, 0},
- {"MSI_INT" , 0, 8, 447, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 447, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 447, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 448, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 448, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 449, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 449, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 449, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 450, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 450, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 450, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 451, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 451, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 451, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"NPEI" , 3, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 14, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"USB1" , 15, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 17, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
- {"ASXPCS0" , 22, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"ASXPCS1" , 23, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_27" , 24, 4, 452, "RAZ", 0, 0, 0ull, 0ull},
- {"AGL" , 28, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"LMC1" , 29, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 452, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 452, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 453, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 454, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 454, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 454, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 454, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 455, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 455, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 455, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 455, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 455, "RO", 0, 1, 1ull, 0},
- {"NPEI" , 47, 1, 455, "RO", 0, 1, 1ull, 0},
- {"RESERVED_48_63" , 48, 16, 455, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 456, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 456, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 456, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 456, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 456, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 457, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 457, "RAZ", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 457, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_51_63" , 51, 13, 457, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 458, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_1" , 0, 2, 459, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 2, 46, 459, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 459, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 460, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 461, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 461, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 462, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 462, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 463, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 463, "RO/WRSL", 0, 0, 80ull, 80ull},
- {"ISAE" , 0, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 464, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 464, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 464, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 464, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 464, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 464, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 464, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 464, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 464, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 464, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 464, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 464, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 465, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PI" , 8, 8, 465, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 465, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 465, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 466, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 466, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 466, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 466, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 466, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 467, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 467, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 467, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 467, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 467, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 468, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 468, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 469, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 470, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 471, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 471, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 471, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 471, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 471, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 472, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 472, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 473, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 474, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 475, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 475, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 475, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 475, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 476, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 476, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_6" , 0, 7, 477, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 7, 25, 477, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 478, "WORSL", 0, 0, 127ull, 127ull},
- {"CISP" , 0, 32, 479, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 480, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 480, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 481, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 481, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 481, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 482, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 482, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"CP" , 0, 8, 483, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 483, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 484, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 484, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 484, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 484, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 485, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 485, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 485, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 485, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 485, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 485, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 485, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 485, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 485, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 485, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 486, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 486, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 486, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 486, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 486, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 486, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 486, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 486, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 486, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 486, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 486, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 487, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 487, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 487, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 487, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 487, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 487, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 487, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 488, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 488, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 489, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 490, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 490, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 491, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 491, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 491, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 491, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 491, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 491, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 491, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 492, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 492, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 492, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 492, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 492, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 492, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 492, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 492, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 492, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 493, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 493, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 493, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 493, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 493, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 493, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 493, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 493, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 493, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 493, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 493, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 493, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 493, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 493, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 493, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 494, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MLW" , 4, 6, 494, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"ASLPMS" , 10, 2, 494, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 494, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 494, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 494, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 494, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 494, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 494, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 494, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 494, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 495, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 495, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 495, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 495, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 495, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 495, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 495, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 495, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 495, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 495, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 495, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 495, "RO", 0, 0, 0ull, 8ull},
- {"RESERVED_26_26" , 26, 1, 495, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 495, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 495, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 495, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 495, "RAZ", 1, 1, 0, 0},
- {"ABP" , 0, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 497, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 497, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 497, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 497, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 497, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 497, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 497, "R/W", 0, 0, 0ull, 0ull},
- {"PIC" , 8, 2, 497, "R/W", 0, 0, 0ull, 0ull},
- {"PCC" , 10, 1, 497, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 497, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 497, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 497, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 497, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 497, "RO", 0, 0, 0ull, 0ull},
- {"EMIS" , 23, 1, 497, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 497, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 497, "RAZ", 1, 1, 0, 0},
- {"CTRS" , 0, 4, 498, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 498, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 498, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 499, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 499, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 499, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 500, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 501, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 502, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 503, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 504, "RO", 0, 0, 1ull, 0ull},
- {"CV" , 16, 4, 504, "RO", 0, 0, 1ull, 0ull},
- {"NCO" , 20, 12, 504, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 505, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 505, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 505, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 505, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 506, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 506, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 506, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 506, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 507, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 507, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 507, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 507, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 507, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 507, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 507, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 507, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 507, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 507, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 507, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 507, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 507, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 507, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 508, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 508, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 508, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 509, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 509, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 509, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 509, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 509, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 509, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 509, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 509, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 509, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 510, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 510, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 510, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 510, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 511, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 512, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 513, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 514, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 515, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 515, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 516, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 517, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 517, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 517, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 517, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 517, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 517, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 518, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 518, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 518, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 518, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 518, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 518, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 519, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 519, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 519, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 519, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 519, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 519, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 519, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 519, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 519, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 519, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_22_24" , 22, 3, 519, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 519, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 519, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 520, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 520, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 520, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 520, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 520, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 521, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 521, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 521, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 521, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 521, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 521, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 521, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 522, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 522, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_BAR_MATCH" , 18, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 523, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 524, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 525, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 526, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 526, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 526, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 527, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 527, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 527, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 528, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 528, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 528, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 529, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 529, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 529, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 529, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 530, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 530, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 530, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 530, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 531, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 531, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 531, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 531, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 532, "RO/WRSL", 0, 0, 72ull, 72ull},
- {"HEADER_CREDITS" , 12, 8, 532, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 532, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 532, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 532, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 532, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 532, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 533, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"HEADER_CREDITS" , 12, 8, 533, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"RESERVED_20_20" , 20, 1, 533, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 533, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 533, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 534, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 534, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 534, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 534, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 534, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 535, "RO/WRSL", 0, 0, 216ull, 216ull},
- {"RESERVED_14_15" , 14, 2, 535, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 535, "RO/WRSL", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 535, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 536, "RO/WRSL", 0, 0, 56ull, 56ull},
- {"RESERVED_14_15" , 14, 2, 536, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 536, "RO/WRSL", 0, 0, 14ull, 14ull},
- {"RESERVED_26_31" , 26, 6, 536, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 537, "RO/WRSL", 0, 0, 360ull, 360ull},
- {"RESERVED_14_15" , 14, 2, 537, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 537, "RO/WRSL", 0, 0, 70ull, 70ull},
- {"RESERVED_26_31" , 26, 6, 537, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 538, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 539, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 540, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 540, "R/W", 0, 0, 80ull, 80ull},
- {"ISAE" , 0, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 541, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 541, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 541, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 541, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 541, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 541, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 541, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 541, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 541, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 541, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 541, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 541, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 542, "R/W", 0, 0, 0ull, 0ull},
- {"PI" , 8, 8, 542, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 542, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 542, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 543, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 543, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 543, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 543, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 543, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 544, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 545, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 546, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 546, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 546, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 546, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 547, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 547, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 547, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 547, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 547, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 547, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 547, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 547, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 547, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 547, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 547, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 548, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 548, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 548, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 549, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 549, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 549, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 549, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 549, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 549, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 550, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 551, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 552, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 552, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 553, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 553, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 554, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 555, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 555, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 555, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 555, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 555, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 555, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 555, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 555, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 555, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 555, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 555, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 555, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 555, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 555, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 555, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 556, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 556, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 556, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 556, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 556, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 556, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 556, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 557, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 557, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 557, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 557, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 557, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 557, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 557, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 557, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 557, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 557, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 557, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 558, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 558, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 558, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 558, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 558, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 558, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 558, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 559, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 559, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 560, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 561, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 561, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 562, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 562, "R/W", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 562, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 562, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 562, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 562, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 563, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 563, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 563, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 563, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 563, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 563, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 563, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 563, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 563, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 563, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 564, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 564, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 564, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 564, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 564, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 564, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 565, "R/W", 0, 0, 1ull, 1ull},
- {"MLW" , 4, 6, 565, "R/W", 0, 0, 8ull, 8ull},
- {"ASLPMS" , 10, 2, 565, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 565, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 565, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 565, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 565, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 565, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 565, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_23" , 22, 2, 565, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 565, "R/W", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 566, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 566, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 566, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 566, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 566, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 566, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 566, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 566, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 566, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 566, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 566, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 566, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 567, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 567, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 567, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 568, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 568, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 568, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 568, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 568, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 568, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 568, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 568, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 569, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 569, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 570, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 570, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 570, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 570, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 571, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 571, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 571, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 572, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 572, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 572, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 573, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 574, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 575, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 576, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 577, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 577, "RO", 0, 0, 1ull, 1ull},
- {"NCO" , 20, 12, 577, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 578, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 578, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 578, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 578, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 579, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 579, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 579, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 580, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 580, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 580, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 580, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 581, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 581, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 581, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 582, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 582, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 582, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 582, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 583, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 583, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 583, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 583, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 584, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 585, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 586, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 587, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 588, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 588, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 588, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 588, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 589, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 589, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 590, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 590, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 591, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 591, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 592, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 593, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 593, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 593, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 593, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 593, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 594, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 594, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 594, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 594, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 594, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 594, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 595, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 595, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 595, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 595, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 595, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_22_24" , 22, 3, 595, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 595, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 596, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 596, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 596, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 596, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 596, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 597, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 597, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 597, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 597, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 597, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 597, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 597, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 598, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 598, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_BAR_MATCH" , 18, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 599, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 600, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 601, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 602, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 602, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 602, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 603, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 603, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 603, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 604, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 604, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 604, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 605, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 605, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 605, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 605, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 606, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 606, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 606, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 606, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 607, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 607, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 607, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 607, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 608, "R/W", 0, 0, 72ull, 72ull},
- {"HEADER_CREDITS" , 12, 8, 608, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 608, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 608, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 608, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 608, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 609, "R/W", 0, 0, 4ull, 4ull},
- {"HEADER_CREDITS" , 12, 8, 609, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_20_20" , 20, 1, 609, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 609, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 609, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 610, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 610, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_20_20" , 20, 1, 610, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 610, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 610, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 611, "R/W", 0, 0, 216ull, 216ull},
- {"RESERVED_14_15" , 14, 2, 611, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 611, "R/W", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 611, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 612, "R/W", 0, 0, 56ull, 56ull},
- {"RESERVED_14_15" , 14, 2, 612, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 612, "R/W", 0, 0, 14ull, 14ull},
- {"RESERVED_26_31" , 26, 6, 612, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 613, "R/W", 0, 0, 360ull, 360ull},
- {"RESERVED_14_15" , 14, 2, 613, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 613, "R/W", 0, 0, 70ull, 70ull},
- {"RESERVED_26_31" , 26, 6, 613, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 614, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 615, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 616, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 616, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 616, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 616, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 616, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 616, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 616, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 616, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 616, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 617, "RAZ", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 617, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 617, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 617, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 617, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 617, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 618, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 618, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 618, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 618, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 618, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 618, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 618, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 618, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 618, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 619, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 619, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 619, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 619, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 620, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_12_63" , 12, 52, 620, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 621, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 622, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 622, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 623, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 623, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 623, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 623, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 624, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 624, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 624, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 624, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 624, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 624, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 624, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 624, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 625, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 625, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 625, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 625, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 625, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 625, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 625, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 625, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 625, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 625, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 625, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 625, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 625, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 626, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 626, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 626, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 626, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 626, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 626, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 626, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 627, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 627, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 627, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 627, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 627, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 627, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 627, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 628, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 628, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 628, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 629, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 629, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 629, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 629, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 629, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 629, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 629, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 629, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 630, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 630, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 630, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 630, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 630, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 630, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 630, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 631, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 631, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 631, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 631, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 632, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 632, "RAZ", 1, 1, 0, 0},
- {"L0SYNC" , 0, 1, 633, "RO", 0, 0, 0ull, 1ull},
- {"L1SYNC" , 1, 1, 633, "RO", 0, 0, 0ull, 1ull},
- {"L2SYNC" , 2, 1, 633, "RO", 0, 0, 0ull, 1ull},
- {"L3SYNC" , 3, 1, 633, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_4_10" , 4, 7, 633, "RAZ", 1, 1, 0, 0},
- {"PATTST" , 11, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"ALIGND" , 12, 1, 633, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_63" , 13, 51, 633, "RAZ", 1, 1, 0, 0},
- {"BIST_STATUS" , 0, 1, 634, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 634, "RAZ", 1, 1, 0, 0},
- {"BITLCK0" , 0, 1, 635, "RO", 0, 1, 0ull, 0},
- {"BITLCK1" , 1, 1, 635, "RO", 0, 1, 0ull, 0},
- {"BITLCK2" , 2, 1, 635, "RO", 0, 1, 0ull, 0},
- {"BITLCK3" , 3, 1, 635, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 635, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 636, "RAZ", 1, 1, 0, 0},
- {"SPD" , 2, 4, 636, "RO", 0, 0, 0ull, 0ull},
- {"SPDSEL0" , 6, 1, 636, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_10" , 7, 4, 636, "RAZ", 1, 1, 0, 0},
- {"LO_PWR" , 11, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 636, "RAZ", 1, 1, 0, 0},
- {"SPDSEL1" , 13, 1, 636, "RO", 0, 0, 1ull, 1ull},
- {"LOOPBCK1" , 14, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 636, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 636, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 637, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 637, "RAZ", 1, 1, 0, 0},
- {"TXFLT_EN" , 0, 1, 638, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 1, 1, 638, "R/W", 0, 0, 0ull, 1ull},
- {"RXSYNBAD_EN" , 2, 1, 638, "R/W", 0, 0, 0ull, 1ull},
- {"BITLCKLS_EN" , 3, 1, 638, "R/W", 0, 0, 0ull, 1ull},
- {"SYNLOS_EN" , 4, 1, 638, "R/W", 0, 0, 0ull, 1ull},
- {"ALGNLOS_EN" , 5, 1, 638, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 638, "RAZ", 1, 1, 0, 0},
- {"TXFLT" , 0, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 1, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXSYNBAD" , 2, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
- {"BITLCKLS" , 3, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNLOS" , 4, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALGNLOS" , 5, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 639, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 640, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 640, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 640, "R/W1C", 0, 0, 0ull, 0ull},
- {"DROP_LN" , 4, 2, 640, "R/W", 0, 0, 0ull, 0ull},
- {"ENC_MODE" , 6, 1, 640, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 640, "RAZ", 1, 1, 0, 0},
- {"GMXENO" , 0, 1, 641, "R/W", 0, 0, 0ull, 0ull},
- {"XAUI" , 1, 1, 641, "RO", 1, 1, 0, 0},
- {"RX_SWAP" , 2, 1, 641, "R/W", 0, 1, 0ull, 0},
- {"TX_SWAP" , 3, 1, 641, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 641, "RAZ", 1, 1, 0, 0},
- {"SYNC0ST" , 0, 4, 642, "RO", 0, 1, 0ull, 0},
- {"SYNC1ST" , 4, 4, 642, "RO", 0, 1, 0ull, 0},
- {"SYNC2ST" , 8, 4, 642, "RO", 0, 1, 0ull, 0},
- {"SYNC3ST" , 12, 4, 642, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 642, "RAZ", 1, 1, 0, 0},
- {"TENGB" , 0, 1, 643, "RO", 0, 0, 1ull, 1ull},
- {"TENPASST" , 1, 1, 643, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 643, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 644, "RAZ", 1, 1, 0, 0},
- {"LPABLE" , 1, 1, 644, "RO", 0, 0, 1ull, 1ull},
- {"RCV_LNK" , 2, 1, 644, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_3_6" , 3, 4, 644, "RAZ", 1, 1, 0, 0},
- {"FLT" , 7, 1, 644, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 644, "RAZ", 1, 1, 0, 0},
- {"TENGB_R" , 0, 1, 645, "RO", 0, 0, 0ull, 0ull},
- {"TENGB_X" , 1, 1, 645, "RO", 0, 0, 1ull, 1ull},
- {"TENGB_W" , 2, 1, 645, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_9" , 3, 7, 645, "RAZ", 1, 1, 0, 0},
- {"RCVFLT" , 10, 1, 645, "RC", 0, 0, 0ull, 0ull},
- {"XMTFLT" , 11, 1, 645, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 645, "RAZ", 1, 1, 0, 0},
- {"DEV" , 14, 2, 645, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_16_63" , 16, 48, 645, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 646, "RAZ", 1, 1, 0, 0},
- {"TX_ST" , 0, 3, 647, "RO", 0, 1, 0ull, 0},
- {"RX_ST" , 3, 2, 647, "RO", 0, 1, 0ull, 0},
- {"ALGN_ST" , 5, 3, 647, "RO", 0, 1, 0ull, 0},
- {"RXBAD" , 8, 1, 647, "RO", 0, 0, 0ull, 0ull},
- {"SYN0BAD" , 9, 1, 647, "RO", 0, 0, 0ull, 0ull},
- {"SYN1BAD" , 10, 1, 647, "RO", 0, 0, 0ull, 0ull},
- {"SYN2BAD" , 11, 1, 647, "RO", 0, 0, 0ull, 0ull},
- {"SYN3BAD" , 12, 1, 647, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 647, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA4" , 3, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 4, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 5, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 6, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 7, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 8, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"PTLP_OR" , 9, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"NTLP_OR" , 10, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"CTLP_OR" , 11, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 648, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"RSL_P2E" , 6, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 7, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"DBG_P2E" , 8, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"E2P_RSL" , 9, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 10, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 11, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 12, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"CTO_P2E" , 13, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 649, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 650, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 650, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 651, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 651, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 652, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 652, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 653, "RAZ", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 653, "RAZ", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 653, "RAZ", 0, 0, 0ull, 0ull},
- {"QLM_CFG" , 13, 2, 653, "RO", 1, 1, 0, 0},
- {"PBUS" , 15, 8, 653, "RO", 1, 1, 0, 0},
- {"DNUM" , 23, 5, 653, "RO", 1, 1, 0, 0},
- {"RESERVED_28_63" , 28, 36, 653, "RAZ", 1, 1, 0, 0},
- {"PCIERST" , 0, 1, 654, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 654, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 655, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 656, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 657, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 657, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 657, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 657, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 657, "RO", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 658, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 658, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 659, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 659, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_38" , 0, 39, 660, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 39, 25, 660, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 661, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 661, "R/W", 0, 1, 4503599627370495ull, 0},
- {"RESERVED_0_11" , 0, 12, 662, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 662, "R/W", 0, 1, 4503599627370495ull, 0},
- {"NPEI_P" , 0, 5, 663, "R/W", 0, 0, 2ull, 2ull},
- {"NPEI_NP" , 5, 5, 663, "R/W", 0, 0, 2ull, 2ull},
- {"NPEI_CPL" , 10, 5, 663, "R/W", 0, 0, 2ull, 2ull},
- {"PESC_P" , 15, 5, 663, "R/W", 0, 0, 2ull, 2ull},
- {"PESC_NP" , 20, 5, 663, "R/W", 0, 0, 2ull, 2ull},
- {"PESC_CPL" , 25, 5, 663, "R/W", 0, 0, 2ull, 2ull},
- {"PEAI_PPF" , 30, 8, 663, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_38_63" , 38, 26, 663, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 664, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 664, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 664, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 664, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 664, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 18, 665, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 665, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 666, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 666, "RAZ", 1, 1, 0, 0},
- {"MINLEN" , 0, 16, 667, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 667, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 667, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 668, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 668, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 668, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 668, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 668, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 668, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 669, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 669, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 669, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 20, 1, 669, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_63" , 21, 43, 669, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 670, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 671, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 672, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 673, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 673, "RAZ", 1, 1, 0, 0},
- {"CRC_EN" , 12, 1, 673, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 673, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 673, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT" , 20, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 673, "RAZ", 1, 1, 0, 0},
- {"GRP_WAT" , 28, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 673, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 673, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 673, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 673, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_63" , 53, 11, 673, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 674, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 674, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 674, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 674, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 674, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 675, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 675, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 676, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 677, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 677, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 677, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 677, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 677, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 677, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 677, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 677, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 677, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 678, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 678, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 679, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 680, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 680, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 681, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 681, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 682, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 682, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 683, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 683, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 684, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 684, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 685, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 685, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 686, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 686, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 687, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 687, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 688, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 688, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 689, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 689, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 690, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 690, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 691, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 691, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 692, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 692, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 693, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 693, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 694, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 694, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 695, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 695, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 696, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 696, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 696, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 697, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 697, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 697, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 698, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 698, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 699, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 699, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 700, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 700, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 700, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 700, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 701, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 701, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 701, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 701, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 701, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 702, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 702, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 702, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 702, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 703, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 703, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 703, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 703, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 703, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 703, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 703, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 703, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 704, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 704, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 704, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 704, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 705, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 705, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 705, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 705, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 705, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 706, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 707, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 707, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 707, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 707, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 707, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 708, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 709, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 709, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 709, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 709, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 709, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 709, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 709, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 709, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 709, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 709, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 709, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 709, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 709, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 710, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 710, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 710, "RO", 1, 0, 0, 0ull},
- {"RESERVED_54_63" , 54, 10, 710, "RAZ", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 711, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 711, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 711, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 711, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 711, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 711, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 711, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 711, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 711, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 711, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 711, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 711, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 711, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 712, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 712, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 712, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 712, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 712, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 712, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 713, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 713, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 713, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 713, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 6, 1, 713, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 713, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 713, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 713, "RO", 1, 0, 0, 0ull},
- {"RESERVED_29_63" , 29, 35, 713, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 714, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 714, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 714, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 714, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 715, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 715, "R/W", 1, 0, 0, 0ull},
- {"BP_PORT" , 10, 6, 715, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_52" , 16, 37, 715, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 715, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 61, 1, 715, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_62_63" , 62, 2, 715, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 716, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 716, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_10_52" , 10, 43, 716, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 716, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 716, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 717, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 717, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 717, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 717, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 717, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 718, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 718, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 718, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 718, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 719, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 719, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 719, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 719, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 719, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 719, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 719, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 719, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 719, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 720, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 720, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 720, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 720, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 720, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 721, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 721, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 721, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 721, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 721, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 721, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 8, 721, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 721, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 721, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 721, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 721, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 3, 721, "RO", 1, 0, 0, 0ull},
- {"OUT_DAT" , 32, 1, 721, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 721, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 721, "RO", 1, 0, 0, 0ull},
- {"RESERVED_35_63" , 35, 29, 721, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 722, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 722, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 722, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 722, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 723, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 724, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 725, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 726, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 727, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE1" , 4, 4, 727, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE2" , 8, 4, 727, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE3" , 12, 4, 727, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE4" , 16, 4, 727, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE5" , 20, 4, 727, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE6" , 24, 4, 727, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE7" , 28, 4, 727, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE8" , 32, 4, 727, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE9" , 36, 4, 727, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_40_63" , 40, 24, 727, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 10, 728, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 728, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 729, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 730, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 730, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 730, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 730, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 730, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 731, "R/W", 0, 0, 2ull, 2ull},
- {"MODE1" , 3, 3, 731, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 731, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 732, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 732, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 732, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 732, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 733, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 733, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 734, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 735, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 735, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 735, "RAZ", 1, 1, 0, 0},
- {"ADR0" , 0, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"ADR1" , 1, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"PEND0" , 2, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"PEND1" , 3, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 4, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 5, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 6, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 7, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 8, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 9, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 736, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 12, 736, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 736, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 737, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 737, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 738, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 738, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 738, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 738, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 738, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 738, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 738, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 738, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 738, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 739, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 739, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 740, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 740, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 741, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 741, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 742, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 742, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 743, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 743, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 744, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 744, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 12, 745, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 745, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 746, "R/W", 0, 0, 0ull, 1023ull},
- {"RESERVED_10_63" , 10, 54, 746, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 747, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 747, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 748, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 748, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 748, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 748, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 748, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 748, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 748, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 748, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 748, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 748, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 749, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 749, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 749, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 749, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 749, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 11, 750, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 750, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 11, 750, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_23_23" , 23, 1, 750, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 12, 750, "RO", 0, 1, 2027ull, 0},
- {"BUF_CNT" , 36, 12, 750, "RO", 0, 1, 0ull, 0},
- {"DES_CNT" , 48, 12, 750, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 750, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 751, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 751, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 752, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 752, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 753, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 753, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 754, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 754, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 754, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 12, 755, "RO", 0, 1, 0ull, 0},
- {"DS_CNT" , 12, 12, 755, "RO", 0, 1, 0ull, 0},
- {"TC_CNT" , 24, 4, 755, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 755, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 756, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 756, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 756, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 756, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 756, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 11, 757, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 757, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 11, 757, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 757, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 757, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 757, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 757, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 758, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 758, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 759, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 760, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 761, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 762, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 762, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 762, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 762, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 762, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 763, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 763, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 763, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 763, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 763, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 764, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 764, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 764, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 765, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 765, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 765, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 765, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 765, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 765, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 765, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 765, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 765, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 765, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 766, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 767, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 767, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 767, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 768, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 768, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 768, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 768, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 768, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 768, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 768, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 769, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 769, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 770, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 771, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 772, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 773, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 773, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 773, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 773, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 773, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 773, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 773, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 773, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 773, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 773, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 773, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 773, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 773, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 773, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 773, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 773, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 773, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 773, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 774, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 774, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 774, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 775, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 775, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 776, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 776, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 776, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 777, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 777, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 777, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 777, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 777, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 777, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 777, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 778, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 778, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 779, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 779, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 780, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 780, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 781, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 781, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 781, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 782, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 782, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 782, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 783, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 783, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 783, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 783, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 783, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 783, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 783, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 784, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 784, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 784, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 784, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 784, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 784, "RAZ", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 784, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 784, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 784, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 784, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 785, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 785, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 785, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 785, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 785, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 785, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 786, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 786, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 787, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 787, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 787, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 787, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 788, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 788, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 788, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 788, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 789, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 789, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 789, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 789, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 789, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 789, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 790, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 790, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 790, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 791, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 791, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 791, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 791, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 791, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 792, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 792, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 792, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 792, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 793, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 793, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 793, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 793, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 793, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 793, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 794, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 794, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 794, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 794, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 795, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 795, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 796, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 796, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 797, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 797, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 798, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 798, "RAZ", 1, 1, 0, 0},
- {"TDF0" , 0, 1, 799, "RO", 0, 0, 0ull, 0ull},
- {"TDF1" , 1, 1, 799, "RO", 0, 0, 0ull, 0ull},
- {"TCF" , 2, 1, 799, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 799, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 800, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 800, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 800, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 800, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 800, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 800, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 800, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 800, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 800, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 800, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 800, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 800, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 801, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 801, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 801, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 802, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 802, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 802, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 802, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 802, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 803, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 803, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 804, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 804, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 805, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 806, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 806, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 806, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 806, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 806, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 806, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 806, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 806, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 806, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 806, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 806, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 806, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 807, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 807, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 807, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 807, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 807, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 807, "RAZ", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 808, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 808, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 808, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 808, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 808, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 809, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 810, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 810, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 811, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 811, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 812, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 812, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 813, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 813, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 813, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 813, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 813, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 813, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 813, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 813, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 813, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 813, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 813, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 813, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 814, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 814, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 814, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 814, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 814, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 814, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 815, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 815, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 816, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 816, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 817, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 817, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 818, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 818, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 818, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 818, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 818, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 818, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 818, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 818, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 818, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 818, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 818, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 818, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 819, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 819, "RAZ", 0, 0, 0ull, 0ull},
- {"INEPINT" , 0, 16, 820, "RO", 0, 0, 0ull, 0ull},
- {"OUTEPINT" , 16, 16, 820, "RO", 0, 0, 0ull, 0ull},
- {"INEPMSK" , 0, 16, 821, "R/W", 0, 0, 0ull, 0ull},
- {"OUTEPMSK" , 16, 16, 821, "R/W", 0, 0, 0ull, 0ull},
- {"DEVSPD" , 0, 2, 822, "R/W", 0, 0, 0ull, 0ull},
- {"NZSTSOUTHSHK" , 2, 1, 822, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 822, "RAZ", 1, 1, 0, 0},
- {"DEVADDR" , 4, 7, 822, "R/W", 0, 0, 0ull, 0ull},
- {"PERFRINT" , 11, 2, 822, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_17" , 13, 5, 822, "RAZ", 1, 1, 0, 0},
- {"EPMISCNT" , 18, 5, 822, "R/W", 0, 0, 8ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 822, "RAZ", 1, 1, 0, 0},
- {"RMTWKUPSIG" , 0, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"SFTDISCON" , 1, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"GNPINNAKSTS" , 2, 1, 823, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKSTS" , 3, 1, 823, "RO", 0, 0, 0ull, 0ull},
- {"TSTCTL" , 4, 3, 823, "R/W", 0, 0, 0ull, 0ull},
- {"SGNPINNAK" , 7, 1, 823, "WO", 0, 0, 0ull, 0ull},
- {"CGNPINNAK" , 8, 1, 823, "WO", 0, 0, 0ull, 0ull},
- {"SGOUTNAK" , 9, 1, 823, "WO", 0, 0, 0ull, 0ull},
- {"CGOUTNAK" , 10, 1, 823, "WO", 0, 0, 0ull, 0ull},
- {"PWRONPRGDONE" , 11, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 823, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 824, "R/W", 0, 0, 0ull, 0ull},
- {"NEXTEP" , 11, 4, 824, "R/W", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 824, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 824, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 824, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 824, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 824, "RAZ", 1, 1, 0, 0},
- {"STALL" , 21, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 22, 4, 824, "R/W", 0, 0, 0ull, 0ull},
- {"CNAK" , 26, 1, 824, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 824, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 824, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 824, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMEOUT" , 3, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMP" , 4, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNEPMIS" , 5, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
- {"INEPNAKEFF" , 6, 1, 825, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 825, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"TIMEOUTMSK" , 3, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMPMSK" , 4, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNEPMISMSK" , 5, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"INEPNAKEFFMSK" , 6, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 826, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 827, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 827, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 827, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 827, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 828, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_14" , 11, 4, 828, "RAZ", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 828, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 828, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 828, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 828, "R/W", 0, 0, 0ull, 0ull},
- {"SNP" , 20, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"STALL" , 21, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_25" , 22, 4, 828, "RAZ", 1, 1, 0, 0},
- {"CNAK" , 26, 1, 828, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 828, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 828, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 828, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"SETUP" , 3, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDIS" , 4, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 829, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"SETUPMSK" , 3, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDISMSK" , 4, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 830, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 831, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 831, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 831, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 831, "RAZ", 1, 1, 0, 0},
- {"DPTXFSTADDR" , 0, 16, 832, "RO", 0, 0, 0ull, 0ull},
- {"DPTXFSIZE" , 16, 16, 832, "RO", 0, 0, 1896ull, 1896ull},
- {"SUSPSTS" , 0, 1, 833, "RO", 0, 0, 0ull, 0ull},
- {"ENUMSPD" , 1, 2, 833, "RO", 0, 0, 0ull, 0ull},
- {"ERRTICERR" , 3, 1, 833, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 833, "RAZ", 1, 1, 0, 0},
- {"SOFFN" , 8, 14, 833, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 833, "RAZ", 1, 1, 0, 0},
- {"INTKNWPTR" , 0, 5, 834, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 834, "RAZ", 1, 1, 0, 0},
- {"WRAPBIT" , 7, 1, 834, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 8, 24, 834, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 835, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 836, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 837, "RO", 0, 0, 0ull, 0ull},
- {"GLBLINTRMSK" , 0, 1, 838, "R/W", 0, 0, 0ull, 1ull},
- {"HBSTLEN" , 1, 4, 838, "R/W", 0, 0, 0ull, 0ull},
- {"DMAEN" , 5, 1, 838, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 838, "RAZ", 1, 1, 0, 0},
- {"NPTXFEMPLVL" , 7, 1, 838, "R/W", 0, 0, 0ull, 1ull},
- {"PTXFEMPLVL" , 8, 1, 838, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_31" , 9, 23, 838, "RAZ", 1, 1, 0, 0},
- {"EPDIR" , 0, 32, 839, "RO", 0, 0, 0ull, 0ull},
- {"OTGMODE" , 0, 3, 840, "RO", 0, 0, 2ull, 2ull},
- {"OTGARCH" , 3, 2, 840, "RO", 0, 0, 1ull, 1ull},
- {"SINGPNT" , 5, 1, 840, "RO", 0, 0, 0ull, 0ull},
- {"HSPHYTYPE" , 6, 2, 840, "RO", 0, 0, 1ull, 1ull},
- {"FSPHYTYPE" , 8, 2, 840, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVEPS" , 10, 4, 840, "RO", 0, 0, 4ull, 4ull},
- {"NUMHSTCHNL" , 14, 4, 840, "RO", 0, 0, 7ull, 7ull},
- {"PERIOSUPPORT" , 18, 1, 840, "RO", 0, 0, 1ull, 1ull},
- {"DYNFIFOSIZING" , 19, 1, 840, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_20_21" , 20, 2, 840, "RAZ", 1, 1, 0, 0},
- {"NPTXQDEPTH" , 22, 2, 840, "RO", 0, 0, 2ull, 2ull},
- {"PTXQDEPTH" , 24, 2, 840, "RO", 0, 0, 2ull, 2ull},
- {"TKNQDEPTH" , 26, 5, 840, "RO", 0, 0, 30ull, 30ull},
- {"RESERVED_31_31" , 31, 1, 840, "RAZ", 1, 1, 0, 0},
- {"XFERSIZEWIDTH" , 0, 4, 841, "RO", 0, 0, 8ull, 8ull},
- {"PKTSIZEWIDTH" , 4, 3, 841, "RO", 0, 0, 6ull, 6ull},
- {"OTGEN" , 7, 1, 841, "RO", 0, 0, 1ull, 1ull},
- {"I2C_SELECTION" , 8, 1, 841, "RO", 0, 0, 0ull, 0ull},
- {"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 841, "RO", 0, 0, 0ull, 0ull},
- {"OPTFEATURE" , 10, 1, 841, "RO", 0, 0, 1ull, 1ull},
- {"RSTTYPE" , 11, 1, 841, "RO", 0, 0, 1ull, 1ull},
- {"AHBPHYSYNC" , 12, 1, 841, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 841, "RAZ", 1, 1, 0, 0},
- {"DFIFODEPTH" , 16, 16, 841, "RO", 0, 0, 1824ull, 1824ull},
- {"NUMDEVPERIOEPS" , 0, 4, 842, "RO", 0, 0, 4ull, 4ull},
- {"ENABLEPWROPT" , 4, 1, 842, "RO", 0, 0, 0ull, 0ull},
- {"AHBFREQ" , 5, 1, 842, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_13" , 6, 8, 842, "RAZ", 1, 1, 0, 0},
- {"PHYDATAWIDTH" , 14, 2, 842, "RO", 0, 0, 1ull, 1ull},
- {"NUMCTLEPS" , 16, 4, 842, "RO", 0, 0, 4ull, 4ull},
- {"IDDGFLTR" , 20, 1, 842, "RO", 0, 0, 1ull, 1ull},
- {"VBUSVALIDFLTR" , 21, 1, 842, "RO", 0, 0, 1ull, 1ull},
- {"AVALIDFLTR" , 22, 1, 842, "RO", 0, 0, 0ull, 0ull},
- {"BVALIDFLTR" , 23, 1, 842, "RO", 0, 0, 0ull, 0ull},
- {"SESSENDFLTR" , 24, 1, 842, "RO", 0, 0, 0ull, 0ull},
- {"ENDEDTRFIFO" , 25, 1, 842, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVMODINEND" , 26, 4, 842, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_30_31" , 30, 2, 842, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 843, "RAZ", 1, 1, 0, 0},
- {"MODEMISMSK" , 1, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"OTGINTMSK" , 2, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"SOFMSK" , 3, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"RXFLVLMSK" , 4, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"NPTXFEMPMSK" , 5, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"GINNAKEFFMSK" , 6, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFFMSK" , 7, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"ULPICKINTMSK" , 8, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"ERLYSUSPMSK" , 10, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"USBSUSPMSK" , 11, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"USBRSTMSK" , 12, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"ENUMDONEMSK" , 13, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"ISOOUTDROPMSK" , 14, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"EOPFMSK" , 15, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 843, "RAZ", 1, 1, 0, 0},
- {"EPMISMSK" , 17, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"INEPINTMSK" , 18, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"OEPINTMSK" , 19, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPISOINMSK" , 20, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPLPMSK" , 21, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"FETSUSPMSK" , 22, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 843, "RAZ", 1, 1, 0, 0},
- {"PRTINTMSK" , 24, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"HCHINTMSK" , 25, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"PTXFEMPMSK" , 26, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 843, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNGMSK" , 28, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"DISCONNINTMSK" , 29, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"SESSREQINTMSK" , 30, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"WKUPINTMSK" , 31, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"CURMOD" , 0, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"MODEMIS" , 1, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"OTGINT" , 2, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"SOF" , 3, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXFLVL" , 4, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"NPTXFEMP" , 5, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"GINNAKEFF" , 6, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFF" , 7, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"ULPICKINT" , 8, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"ERLYSUSP" , 10, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBSUSP" , 11, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBRST" , 12, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENUMDONE" , 13, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"ISOOUTDROP" , 14, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"EOPF" , 15, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 844, "RAZ", 1, 1, 0, 0},
- {"EPMIS" , 17, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"IEPINT" , 18, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"OEPINT" , 19, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"INCOMPISOIN" , 20, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"INCOMPLP" , 21, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"FETSUSP" , 22, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 844, "RAZ", 1, 1, 0, 0},
- {"PRTINT" , 24, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"HCHINT" , 25, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"PTXFEMP" , 26, 1, 844, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 844, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNG" , 28, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"DISCONNINT" , 29, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"SESSREQINT" , 30, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"WKUPINT" , 31, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"NPTXFSTADDR" , 0, 16, 845, "R/W", 0, 0, 1824ull, 456ull},
- {"NPTXFDEP" , 16, 16, 845, "R/W", 0, 0, 1824ull, 912ull},
- {"NPTXFSPCAVAIL" , 0, 16, 846, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQSPCAVAIL" , 16, 8, 846, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQTOP" , 24, 7, 846, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 846, "RAZ", 1, 1, 0, 0},
- {"SESREQSCS" , 0, 1, 847, "R/W", 0, 0, 0ull, 0ull},
- {"SESREQ" , 1, 1, 847, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 847, "RAZ", 1, 1, 0, 0},
- {"HSTNEGSCS" , 8, 1, 847, "R/W", 0, 0, 0ull, 0ull},
- {"HNPREQ" , 9, 1, 847, "R/W", 0, 0, 0ull, 0ull},
- {"HSTSETHNPEN" , 10, 1, 847, "R/W", 0, 0, 0ull, 0ull},
- {"DEVHNPEN" , 11, 1, 847, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 847, "RAZ", 1, 1, 0, 0},
- {"CONIDSTS" , 16, 1, 847, "RO", 1, 1, 0, 0},
- {"DBNCTIME" , 17, 1, 847, "RO", 0, 0, 0ull, 0ull},
- {"ASESVLD" , 18, 1, 847, "RO", 1, 1, 0, 0},
- {"BSESVLD" , 19, 1, 847, "RO", 1, 1, 0, 0},
- {"RESERVED_20_31" , 20, 12, 847, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 848, "RAZ", 1, 1, 0, 0},
- {"SESENDDET" , 2, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 848, "RAZ", 1, 1, 0, 0},
- {"SESREQSUCSTSCHNG" , 8, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSTNEGSUCSTSCHNG" , 9, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_16" , 10, 7, 848, "RAZ", 1, 1, 0, 0},
- {"HSTNEGDET" , 17, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
- {"ADEVTOUTCHG" , 18, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBNCEDONE" , 19, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 848, "RAZ", 1, 1, 0, 0},
- {"CSFTRST" , 0, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"HSFTRST" , 1, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"FRMCNTRRST" , 2, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNQFLSH" , 3, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"RXFFLSH" , 4, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"TXFFLSH" , 5, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 6, 5, 849, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_29" , 11, 19, 849, "RAZ", 1, 1, 0, 0},
- {"DMAREQ" , 30, 1, 849, "RO", 0, 0, 0ull, 0ull},
- {"AHBIDLE" , 31, 1, 849, "RO", 0, 0, 1ull, 1ull},
- {"RXFDEP" , 0, 16, 850, "R/W", 0, 0, 1824ull, 456ull},
- {"RESERVED_16_31" , 16, 16, 850, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 851, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 851, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 851, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 851, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 851, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 851, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 852, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 852, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 852, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 852, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 852, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 853, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 853, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 853, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 853, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 853, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 853, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 854, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 854, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 854, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 854, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 854, "RAZ", 1, 1, 0, 0},
- {"SYNOPSYSID" , 0, 32, 855, "RO", 1, 1, 0, 0},
- {"TOUTCAL" , 0, 3, 856, "R/W", 0, 0, 0ull, 0ull},
- {"PHYIF" , 3, 1, 856, "RO", 0, 0, 1ull, 1ull},
- {"ULPI_UTMI_SEL" , 4, 1, 856, "RO", 0, 0, 0ull, 0ull},
- {"FSINTF" , 5, 1, 856, "WO", 0, 0, 0ull, 0ull},
- {"PHYSEL" , 6, 1, 856, "WO", 0, 0, 0ull, 0ull},
- {"DDRSEL" , 7, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"SRPCAP" , 8, 1, 856, "RO", 0, 0, 0ull, 0ull},
- {"HNPCAP" , 9, 1, 856, "RO", 0, 0, 0ull, 0ull},
- {"USBTRDTIM" , 10, 4, 856, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_14_14" , 14, 1, 856, "RAZ", 1, 1, 0, 0},
- {"PHYLPWRCLKSEL" , 15, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"OTGI2CSEL" , 16, 1, 856, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 856, "RAZ", 1, 1, 0, 0},
- {"HAINT" , 0, 16, 857, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 857, "RAZ", 1, 1, 0, 0},
- {"HAINTMSK" , 0, 16, 858, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 858, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 859, "R/W", 0, 0, 0ull, 0ull},
- {"EPNUM" , 11, 4, 859, "R/W", 0, 0, 0ull, 0ull},
- {"EPDIR" , 15, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 859, "RAZ", 1, 1, 0, 0},
- {"LSPDDEV" , 17, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 859, "R/W", 0, 0, 0ull, 0ull},
- {"EC" , 20, 2, 859, "R/W", 0, 0, 0ull, 0ull},
- {"DEVADDR" , 22, 7, 859, "R/W", 0, 0, 0ull, 0ull},
- {"ODDFRM" , 29, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"CHDIS" , 30, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"CHENA" , 31, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSPCLKSEL" , 0, 2, 860, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSSUPP" , 2, 1, 860, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 860, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPL" , 0, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"CHHLTD" , 1, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"STALL" , 3, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAK" , 4, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACK" , 5, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"NYET" , 6, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"XACTERR" , 7, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"BBLERR" , 8, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMOVRUN" , 9, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATATGLERR" , 10, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 861, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"CHHLTDMSK" , 1, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"STALLMSK" , 3, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"NAKMSK" , 4, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"ACKMSK" , 5, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"NYETMSK" , 6, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"XACTERRMSK" , 7, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"BBLERRMSK" , 8, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"FRMOVRUNMSK" , 9, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"DATATGLERRMSK" , 10, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 862, "RAZ", 1, 1, 0, 0},
- {"PRTADDR" , 0, 7, 863, "R/W", 0, 0, 0ull, 0ull},
- {"HUBADDR" , 7, 7, 863, "R/W", 0, 0, 0ull, 0ull},
- {"XACTPOS" , 14, 2, 863, "R/W", 0, 0, 0ull, 0ull},
- {"COMPSPLT" , 16, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_30" , 17, 14, 863, "RAZ", 1, 1, 0, 0},
- {"SPLTENA" , 31, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"XFERSIZE" , 0, 19, 864, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 864, "R/W", 0, 0, 0ull, 0ull},
- {"PID" , 29, 2, 864, "R/W", 0, 0, 0ull, 0ull},
- {"DOPNG" , 31, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"FRINT" , 0, 16, 865, "R/W", 0, 0, 2959ull, 3750ull},
- {"RESERVED_16_31" , 16, 16, 865, "RAZ", 1, 1, 0, 0},
- {"FRNUM" , 0, 16, 866, "RO", 0, 0, 16383ull, 0ull},
- {"FRREM" , 16, 16, 866, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNSTS" , 0, 1, 867, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNDET" , 1, 1, 867, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENA" , 2, 1, 867, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENCHNG" , 3, 1, 867, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRACT" , 4, 1, 867, "RO", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRCHNG" , 5, 1, 867, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTRES" , 6, 1, 867, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSUSP" , 7, 1, 867, "R/W", 0, 0, 0ull, 0ull},
- {"PRTRST" , 8, 1, 867, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 867, "RAZ", 1, 1, 0, 0},
- {"PRTLNSTS" , 10, 2, 867, "RO", 0, 0, 0ull, 0ull},
- {"PRTPWR" , 12, 1, 867, "R/W", 0, 0, 0ull, 0ull},
- {"PRTTSTCTL" , 13, 4, 867, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSPD" , 17, 2, 867, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 867, "RAZ", 1, 1, 0, 0},
- {"PTXFSTADDR" , 0, 16, 868, "R/W", 0, 0, 3648ull, 912ull},
- {"PTXFSIZE" , 16, 16, 868, "R/W", 0, 0, 256ull, 456ull},
- {"PTXFSPCAVAIL" , 0, 16, 869, "RO", 0, 0, 0ull, 0ull},
- {"PTXQSPCAVAIL" , 16, 8, 869, "RO", 0, 0, 0ull, 0ull},
- {"PTXQTOP" , 24, 8, 869, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 32, 870, "R/W", 0, 0, 0ull, 0ull},
- {"STOPPCLK" , 0, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"GATEHCLK" , 1, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"PWRCLMP" , 2, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"RSTPDWNMODULE" , 3, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"PHYSUSPENDED" , 4, 1, 871, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 871, "RAZ", 1, 1, 0, 0},
- {"NOF_BIS" , 0, 1, 872, "RO", 0, 0, 0ull, 0ull},
- {"NIF_BIS" , 1, 1, 872, "RO", 0, 0, 0ull, 0ull},
- {"USBC_BIS" , 2, 1, 872, "RO", 0, 0, 0ull, 0ull},
- {"N2UF_BIS" , 3, 1, 872, "RO", 0, 0, 0ull, 0ull},
- {"E2HC_BIS" , 4, 1, 872, "RO", 0, 0, 0ull, 0ull},
- {"U2NF_BIS" , 5, 1, 872, "RO", 0, 0, 0ull, 0ull},
- {"U2NC_BIS" , 6, 1, 872, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 872, "RAZ", 1, 1, 0, 0},
- {"DIVIDE" , 0, 3, 873, "R/W", 0, 0, 4ull, 0ull},
- {"HRST" , 3, 1, 873, "R/W", 0, 0, 0ull, 1ull},
- {"PRST" , 4, 1, 873, "R/W", 0, 0, 0ull, 1ull},
- {"ENABLE" , 5, 1, 873, "R/W", 0, 0, 1ull, 1ull},
- {"POR" , 6, 1, 873, "R/W", 0, 0, 1ull, 0ull},
- {"S_BIST" , 7, 1, 873, "R/W", 0, 0, 0ull, 1ull},
- {"SD_MODE" , 8, 2, 873, "R/W", 0, 0, 0ull, 0ull},
- {"CDIV_BYP" , 10, 1, 873, "R/W", 0, 0, 0ull, 0ull},
- {"P_C_SEL" , 11, 2, 873, "R/W", 0, 0, 2ull, 0ull},
- {"P_COM_ON" , 13, 1, 873, "R/W", 0, 0, 1ull, 1ull},
- {"P_RTYPE" , 14, 2, 873, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 873, "RAZ", 1, 1, 0, 0},
- {"HCLK_RST" , 17, 1, 873, "R/W", 0, 0, 1ull, 1ull},
- {"DIVIDE2" , 18, 2, 873, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_63" , 20, 44, 873, "RAZ", 1, 1, 0, 0},
- {"L2C_EMOD" , 0, 2, 874, "R/W", 0, 0, 1ull, 1ull},
- {"INV_A2" , 2, 1, 874, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_TEST" , 3, 1, 874, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_STT" , 4, 1, 874, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_0PAG" , 5, 1, 874, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 874, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 875, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 875, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 876, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 876, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 877, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 877, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 878, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 878, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 879, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 879, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 880, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 880, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 881, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 881, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 882, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 882, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 883, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 883, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 884, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 884, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 885, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 885, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 886, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 886, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 887, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 887, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 888, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 888, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 889, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 889, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 890, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 890, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 4, 891, "R/W", 0, 0, 0ull, 0ull},
- {"CHANNEL" , 4, 5, 891, "R/W", 0, 0, 0ull, 0ull},
- {"COUNT" , 9, 11, 891, "R/W", 0, 0, 0ull, 0ull},
- {"F_ADDR" , 20, 18, 891, "R/W", 0, 0, 0ull, 0ull},
- {"REQ" , 38, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
- {"DONE" , 39, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 891, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_A_F" , 15, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_E" , 16, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_F" , 17, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PF" , 25, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 892, "RAZ", 0, 0, 0ull, 0ull},
- {"LTL_F_PE" , 32, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPF" , 35, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPE" , 36, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPF" , 37, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 892, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 893, "R/W1C", 1, 0, 0, 0ull},
- {"L2C_A_F" , 15, 1, 893, "R/W1C", 1, 0, 0, 0ull},
- {"LT_FI_E" , 16, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_FI_F" , 17, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 893, "R/W1C", 1, 0, 0, 0ull},
- {"UOD_PF" , 25, 1, 893, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_26_31" , 26, 6, 893, "RAZ", 1, 0, 0, 0ull},
- {"LTL_F_PE" , 32, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 893, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_RPF" , 35, 1, 893, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPE" , 36, 1, 893, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPF" , 37, 1, 893, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_38_63" , 38, 26, 893, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_IN" , 1, 8, 894, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 9, 4, 894, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 13, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ENB" , 14, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_ENB" , 15, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_ENB" , 16, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_EN" , 17, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_ENH" , 18, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_22" , 19, 4, 894, "RAZ", 0, 0, 0ull, 0ull},
- {"HST_MODE" , 23, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"DM_PULLD" , 24, 1, 894, "R/W", 0, 0, 1ull, 1ull},
- {"DP_PULLD" , 25, 1, 894, "R/W", 0, 0, 1ull, 1ull},
- {"TCLK" , 26, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"USBP_BIST" , 27, 1, 894, "R/W", 0, 0, 1ull, 1ull},
- {"USBC_END" , 28, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_BMODE" , 29, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"TXPREEMPHASISTUNE" , 30, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 894, "RAZ", 0, 0, 0ull, 0ull},
- {"TDATA_OUT" , 32, 4, 894, "RO", 1, 1, 0, 0},
- {"BIST_ERR" , 36, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 37, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"HSBIST" , 38, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 39, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 40, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"DRVVBUS" , 41, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 42, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"OTGDISABLE" , 43, 1, 894, "R/W", 0, 0, 1ull, 1ull},
- {"OTGTUNE" , 44, 3, 894, "R/W", 0, 0, 2ull, 2ull},
- {"COMPDISTUNE" , 47, 3, 894, "R/W", 0, 0, 2ull, 2ull},
- {"SQRXTUNE" , 50, 3, 894, "R/W", 0, 0, 3ull, 3ull},
- {"TXHSXVTUNE" , 53, 2, 894, "R/W", 0, 0, 0ull, 0ull},
- {"TXFSLSTUNE" , 55, 4, 894, "R/W", 0, 0, 3ull, 3ull},
- {"TXVREFTUNE" , 59, 4, 894, "R/W", 0, 0, 7ull, 7ull},
- {"TXRISETUNE" , 63, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"ZIP_CTL" , 0, 4, 895, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 27, 895, "RO", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 895, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 896, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 896, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 896, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 896, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 896, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 897, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 897, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 897, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 898, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 898, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 898, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 898, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 898, "RO", 0, 0, 31744ull, 31744ull},
- {"RESERVED_48_63" , 48, 16, 898, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 14, 899, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 899, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 900, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 901, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 11, 0},
- {"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 11},
- {"cvmx_agl_gmx_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 13},
- {"cvmx_agl_gmx_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 3, 19},
- {"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 7, 22},
- {"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 1, 29},
- {"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 30},
- {"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 7, 1, 31},
- {"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 32},
- {"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 1, 33},
- {"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 34},
- {"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 11, 2, 35},
- {"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 4, 37},
- {"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 2, 41},
- {"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 10, 43},
- {"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 15, 11, 53},
- {"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 64},
- {"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 17, 2, 66},
- {"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 68},
- {"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 19, 19, 70},
- {"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 19, 89},
- {"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 21, 2, 108},
- {"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 110},
- {"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 23, 2, 112},
- {"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 114},
- {"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 25, 2, 116},
- {"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 118},
- {"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 27, 2, 120},
- {"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 122},
- {"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 29, 2, 124},
- {"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 126},
- {"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 31, 2, 128},
- {"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 130},
- {"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 33, 4, 132},
- {"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 136},
- {"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 35, 2, 138},
- {"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 2, 140},
- {"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 37, 4, 142},
- {"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 4, 146},
- {"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 39, 2, 150},
- {"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 3, 152},
- {"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 41, 5, 155},
- {"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 3, 160},
- {"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 43, 2, 163},
- {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 165},
- {"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 45, 2, 167},
- {"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 169},
- {"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 47, 2, 171},
- {"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 173},
- {"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 49, 2, 175},
- {"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 177},
- {"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 51, 2, 179},
- {"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 181},
- {"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 53, 2, 183},
- {"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 185},
- {"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 55, 2, 187},
- {"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 189},
- {"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 57, 2, 191},
- {"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 193},
- {"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 59, 2, 195},
- {"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 197},
- {"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 61, 2, 199},
- {"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 201},
- {"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 63, 3, 203},
- {"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 10, 206},
- {"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 10, 216},
- {"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 226},
- {"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 2, 228},
- {"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 6, 230},
- {"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 69, 2, 236},
- {"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 70, 2, 238},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 71, 2, 240},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 72, 2, 242},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 73, 2, 244},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 74, 2, 246},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 75, 21, 248},
- {"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 100, 21, 269},
- {"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 125, 21, 290},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 150, 2, 311},
- {"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 175, 2, 313},
- {"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 200, 2, 315},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 21, 317},
- {"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 237, 21, 338},
- {"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 249, 21, 359},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 261, 2, 380},
- {"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 273, 2, 382},
- {"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 285, 2, 384},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 297, 21, 386},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 322, 21, 407},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 334, 2, 428},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 335, 2, 430},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 347, 2, 432},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 359, 2, 434},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 360, 2, 436},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 361, 2, 438},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 362, 1, 440},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 374, 3, 441},
- {"cvmx_ciu_qlm_dcok" , CVMX_CSR_DB_TYPE_NCB, 64, 375, 2, 444},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 376, 5, 446},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 377, 8, 451},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 378, 2, 459},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 379, 2, 461},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 380, 2, 463},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 381, 2, 465},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 382, 3, 467},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 386, 7, 470},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 398, 6, 477},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 399, 7, 483},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 3, 490},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 2, 493},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 414, 3, 495},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 415, 2, 498},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 29, 500},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 417, 29, 529},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 418, 2, 558},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 426, 2, 560},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 434, 3, 562},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 435, 3, 565},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 2, 568},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 437, 2, 570},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 438, 7, 572},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 2, 579},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 442, 2, 581},
- {"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 444, 5, 583},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 446, 7, 588},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 595},
- {"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 450, 8, 597},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 452, 10, 605},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 1, 615},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 1, 616},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 476, 1, 617},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 484, 1, 618},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 492, 1, 619},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 500, 1, 620},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 508, 2, 621},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 516, 4, 623},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 524, 2, 627},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 532, 9, 629},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 540, 11, 638},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 548, 2, 649},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 556, 27, 651},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 564, 27, 678},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 572, 2, 705},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 580, 2, 707},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 588, 2, 709},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 596, 2, 711},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 604, 2, 713},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 612, 2, 715},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 620, 2, 717},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 628, 2, 719},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 636, 2, 721},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 644, 2, 723},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 652, 2, 725},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 660, 2, 727},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 668, 4, 729},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 676, 2, 733},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 684, 2, 735},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 692, 2, 737},
- {"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 700, 4, 739},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 702, 4, 743},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 704, 2, 747},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 706, 5, 749},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 708, 2, 754},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 710, 2, 756},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 718, 3, 758},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 720, 5, 761},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 728, 2, 766},
- {"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 736, 2, 768},
- {"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 738, 2, 770},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 740, 3, 772},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 748, 2, 775},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 756, 2, 777},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 764, 2, 779},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 772, 3, 781},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 780, 2, 784},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 788, 2, 786},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 2, 788},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 2, 790},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 2, 792},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 2, 794},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 2, 796},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 836, 2, 798},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 844, 2, 800},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 852, 2, 802},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 860, 2, 804},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 868, 2, 806},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 876, 2, 808},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 884, 2, 810},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 892, 2, 812},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 900, 2, 814},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 908, 2, 816},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 910, 2, 818},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 912, 2, 820},
- {"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 914, 2, 822},
- {"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 916, 2, 824},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 918, 3, 826},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 920, 8, 829},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 922, 8, 837},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 924, 2, 845},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 926, 2, 847},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 928, 6, 849},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 930, 2, 855},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 932, 2, 857},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 934, 2, 859},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 936, 9, 861},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 938, 3, 870},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 940, 9, 873},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 956, 2, 882},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 960, 2, 884},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 961, 2, 886},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 962, 2, 888},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 963, 2, 890},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 964, 19, 892},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 965, 6, 911},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 966, 3, 917},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 967, 3, 920},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 968, 3, 923},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 969, 5, 926},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 970, 5, 931},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 971, 1, 936},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 972, 1, 937},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 973, 7, 938},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 974, 7, 945},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 975, 3, 952},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 976, 3, 955},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 977, 3, 958},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 978, 5, 961},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 979, 5, 966},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 980, 1, 971},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 981, 1, 972},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 982, 3, 973},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 983, 3, 976},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 984, 3, 979},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 985, 2, 982},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 986, 2, 984},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 987, 2, 986},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 988, 2, 988},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 989, 19, 990},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 990, 2, 1009},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 991, 1, 1011},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 992, 15, 1012},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 993, 13, 1027},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 994, 13, 1040},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 995, 2, 1053},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 996, 2, 1055},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 997, 2, 1057},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 998, 3, 1059},
- {"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 1010, 3, 1062},
- {"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1014, 2, 1065},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1018, 2, 1067},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1030, 2, 1069},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 1158, 1, 1071},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 1161, 1, 1072},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1164, 6, 1073},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1165, 5, 1079},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1166, 6, 1084},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1167, 7, 1090},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 1168, 2, 1097},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1176, 2, 1099},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 1177, 3, 1101},
- {"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 1178, 2, 1104},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 1179, 5, 1106},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 1187, 3, 1111},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 1188, 4, 1114},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1189, 3, 1118},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 1190, 2, 1121},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1191, 2, 1123},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1192, 4, 1125},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1193, 3, 1129},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1194, 5, 1132},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1195, 5, 1137},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1196, 7, 1142},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1197, 11, 1149},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1198, 8, 1160},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1199, 15, 1168},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1200, 8, 1183},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 1201, 5, 1191},
- {"cvmx_l2c_grpwrr0" , CVMX_CSR_DB_TYPE_RSL, 64, 1202, 2, 1196},
- {"cvmx_l2c_grpwrr1" , CVMX_CSR_DB_TYPE_RSL, 64, 1203, 2, 1198},
- {"cvmx_l2c_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1204, 10, 1200},
- {"cvmx_l2c_int_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1205, 10, 1210},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 1206, 4, 1220},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1207, 2, 1224},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 1208, 14, 1226},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 1209, 19, 1240},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 1210, 3, 1259},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 1211, 3, 1262},
- {"cvmx_l2c_oob" , CVMX_CSR_DB_TYPE_RSL, 64, 1212, 3, 1265},
- {"cvmx_l2c_oob1" , CVMX_CSR_DB_TYPE_RSL, 64, 1213, 6, 1268},
- {"cvmx_l2c_oob2" , CVMX_CSR_DB_TYPE_RSL, 64, 1214, 6, 1274},
- {"cvmx_l2c_oob3" , CVMX_CSR_DB_TYPE_RSL, 64, 1215, 6, 1280},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1216, 2, 1286},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1220, 17, 1288},
- {"cvmx_l2c_ppgrp" , CVMX_CSR_DB_TYPE_RSL, 64, 1221, 13, 1305},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1222, 5, 1318},
- {"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1223, 5, 1323},
- {"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1224, 5, 1328},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1225, 2, 1333},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1226, 3, 1335},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1227, 2, 1338},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1228, 2, 1340},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1229, 2, 1342},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1230, 7, 1344},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1231, 5, 1351},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1232, 3, 1356},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1233, 3, 1359},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1234, 2, 1362},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1235, 2, 1364},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1236, 2, 1366},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1237, 6, 1368},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1238, 14, 1374},
- {"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1239, 2, 1388},
- {"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1240, 2, 1390},
- {"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1241, 2, 1392},
- {"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1242, 2, 1394},
- {"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1243, 2, 1396},
- {"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1244, 2, 1398},
- {"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1245, 2, 1400},
- {"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1246, 2, 1402},
- {"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1247, 2, 1404},
- {"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1255, 2, 1406},
- {"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1257, 2, 1408},
- {"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1259, 2, 1410},
- {"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1261, 2, 1412},
- {"cvmx_lmc#_bist_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1263, 2, 1414},
- {"cvmx_lmc#_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1265, 8, 1416},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1267, 7, 1424},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1269, 19, 1431},
- {"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1271, 8, 1450},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1273, 2, 1458},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1275, 2, 1460},
- {"cvmx_lmc#_dclk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1277, 5, 1462},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1279, 18, 1467},
- {"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1281, 6, 1485},
- {"cvmx_lmc#_dll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1283, 5, 1491},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1285, 5, 1496},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1287, 5, 1501},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1289, 6, 1506},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1291, 2, 1512},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1293, 2, 1514},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1295, 14, 1516},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1297, 9, 1530},
- {"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 1299, 2, 1539},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1301, 2, 1541},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1303, 2, 1543},
- {"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1305, 13, 1545},
- {"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1307, 6, 1558},
- {"cvmx_lmc#_read_level_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1309, 7, 1564},
- {"cvmx_lmc#_read_level_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1311, 4, 1571},
- {"cvmx_lmc#_read_level_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 1313, 11, 1575},
- {"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1321, 6, 1586},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1323, 9, 1592},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 5, 1601},
- {"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 5, 1606},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 5, 1611},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 1330, 3, 1616},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1331, 10, 1619},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 3, 1629},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 1337, 3, 1632},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1340, 15, 1635},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1343, 3, 1650},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1344, 3, 1653},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1345, 3, 1656},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1346, 5, 1659},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1348, 1, 1664},
- {"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 1349, 8, 1665},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1350, 13, 1673},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1358, 13, 1686},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1366, 6, 1699},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1367, 1, 1705},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1371, 2, 1706},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1372, 2, 1708},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1373, 13, 1710},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1374, 8, 1723},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 1375, 4, 1731},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 1376, 1, 1735},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 1377, 3, 1736},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1378, 2, 1739},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 1379, 6, 1741},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1380, 7, 1747},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 1381, 4, 1754},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1382, 2, 1758},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1383, 2, 1760},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1384, 13, 1762},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1386, 12, 1775},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1388, 3, 1787},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1390, 3, 1790},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1392, 2, 1793},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1394, 2, 1795},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1396, 2, 1797},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1398, 7, 1799},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1400, 2, 1806},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1402, 7, 1808},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1404, 4, 1815},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1406, 8, 1819},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1408, 9, 1827},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1410, 7, 1836},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1412, 9, 1843},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1414, 2, 1852},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1416, 2, 1854},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1418, 4, 1856},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1420, 2, 1860},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1422, 2, 1862},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1424, 2, 1864},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1426, 4, 1866},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1428, 2, 1870},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1430, 2, 1872},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1432, 2, 1874},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1434, 2, 1876},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1436, 2, 1878},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1438, 2, 1880},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1440, 6, 1882},
- {"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 1442, 5, 1888},
- {"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1443, 8, 1893},
- {"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 1444, 8, 1901},
- {"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1445, 2, 1909},
- {"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 1446, 3, 1911},
- {"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 1447, 5, 1914},
- {"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 1448, 4, 1919},
- {"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 1449, 8, 1923},
- {"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1450, 2, 1931},
- {"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 1451, 2, 1933},
- {"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 1452, 5, 1935},
- {"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 1453, 4, 1940},
- {"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1454, 4, 1944},
- {"cvmx_npei_bar1_index#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 1455, 5, 1948},
- {"cvmx_npei_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1487, 58, 1953},
- {"cvmx_npei_bist_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1488, 15, 2011},
- {"cvmx_npei_ctl_port0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1489, 17, 2026},
- {"cvmx_npei_ctl_port1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1490, 17, 2043},
- {"cvmx_npei_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1491, 10, 2060},
- {"cvmx_npei_ctl_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1492, 11, 2070},
- {"cvmx_npei_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1493, 5, 2081},
- {"cvmx_npei_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1494, 8, 2086},
- {"cvmx_npei_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1495, 2, 2094},
- {"cvmx_npei_dma#_counts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1496, 3, 2096},
- {"cvmx_npei_dma#_dbell" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 1501, 2, 2099},
- {"cvmx_npei_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1506, 4, 2101},
- {"cvmx_npei_dma#_naddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1511, 2, 2105},
- {"cvmx_npei_dma0_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1516, 2, 2107},
- {"cvmx_npei_dma1_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1517, 2, 2109},
- {"cvmx_npei_dma_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1518, 2, 2111},
- {"cvmx_npei_dma_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1519, 17, 2113},
- {"cvmx_npei_dma_pcie_req_num" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1520, 15, 2130},
- {"cvmx_npei_int_a_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1521, 11, 2145},
- {"cvmx_npei_int_a_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1522, 11, 2156},
- {"cvmx_npei_int_a_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1523, 11, 2167},
- {"cvmx_npei_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1524, 64, 2178},
- {"cvmx_npei_int_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1525, 63, 2242},
- {"cvmx_npei_int_info" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1526, 3, 2305},
- {"cvmx_npei_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1527, 64, 2308},
- {"cvmx_npei_int_sum2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1528, 61, 2372},
- {"cvmx_npei_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1529, 1, 2433},
- {"cvmx_npei_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1530, 1, 2434},
- {"cvmx_npei_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1531, 3, 2435},
- {"cvmx_npei_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1532, 11, 2438},
- {"cvmx_npei_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1548, 1, 2449},
- {"cvmx_npei_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1549, 1, 2450},
- {"cvmx_npei_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1550, 1, 2451},
- {"cvmx_npei_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1551, 1, 2452},
- {"cvmx_npei_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1552, 1, 2453},
- {"cvmx_npei_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1553, 1, 2454},
- {"cvmx_npei_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1554, 1, 2455},
- {"cvmx_npei_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1555, 1, 2456},
- {"cvmx_npei_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1556, 3, 2457},
- {"cvmx_npei_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1557, 1, 2460},
- {"cvmx_npei_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1558, 1, 2461},
- {"cvmx_npei_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1559, 1, 2462},
- {"cvmx_npei_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1560, 1, 2463},
- {"cvmx_npei_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1561, 1, 2464},
- {"cvmx_npei_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1562, 1, 2465},
- {"cvmx_npei_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1563, 1, 2466},
- {"cvmx_npei_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1564, 1, 2467},
- {"cvmx_npei_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1565, 3, 2468},
- {"cvmx_npei_pcie_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1566, 7, 2471},
- {"cvmx_npei_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1567, 2, 2478},
- {"cvmx_npei_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1568, 3, 2480},
- {"cvmx_npei_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1569, 3, 2483},
- {"cvmx_npei_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1570, 3, 2486},
- {"cvmx_npei_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1571, 3, 2489},
- {"cvmx_npei_pkt#_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1603, 2, 2492},
- {"cvmx_npei_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1635, 2, 2494},
- {"cvmx_npei_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1667, 2, 2496},
- {"cvmx_npei_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1699, 5, 2498},
- {"cvmx_npei_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1731, 13, 2503},
- {"cvmx_npei_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1763, 2, 2516},
- {"cvmx_npei_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1795, 2, 2518},
- {"cvmx_npei_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1827, 2, 2520},
- {"cvmx_npei_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1859, 2, 2522},
- {"cvmx_npei_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1860, 2, 2524},
- {"cvmx_npei_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1861, 1, 2526},
- {"cvmx_npei_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1862, 2, 2527},
- {"cvmx_npei_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1863, 2, 2529},
- {"cvmx_npei_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1864, 2, 2531},
- {"cvmx_npei_pkt_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1865, 2, 2533},
- {"cvmx_npei_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1866, 2, 2535},
- {"cvmx_npei_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1898, 2, 2537},
- {"cvmx_npei_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1899, 1, 2539},
- {"cvmx_npei_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1900, 10, 2540},
- {"cvmx_npei_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1901, 2, 2550},
- {"cvmx_npei_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1902, 1, 2552},
- {"cvmx_npei_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1903, 2, 2553},
- {"cvmx_npei_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1904, 3, 2555},
- {"cvmx_npei_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1905, 2, 2558},
- {"cvmx_npei_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1906, 2, 2560},
- {"cvmx_npei_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1907, 2, 2562},
- {"cvmx_npei_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1908, 2, 2564},
- {"cvmx_npei_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1909, 1, 2566},
- {"cvmx_npei_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1910, 2, 2567},
- {"cvmx_npei_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1911, 1, 2569},
- {"cvmx_npei_pkt_slist_id_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1912, 3, 2570},
- {"cvmx_npei_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1913, 2, 2573},
- {"cvmx_npei_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1914, 2, 2575},
- {"cvmx_npei_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1915, 2, 2577},
- {"cvmx_npei_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1916, 2, 2579},
- {"cvmx_npei_rsl_int_blocks" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1917, 29, 2581},
- {"cvmx_npei_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1918, 1, 2610},
- {"cvmx_npei_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1919, 4, 2611},
- {"cvmx_npei_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1920, 7, 2615},
- {"cvmx_npei_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1921, 5, 2622},
- {"cvmx_npei_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1922, 4, 2627},
- {"cvmx_npei_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1923, 1, 2631},
- {"cvmx_npei_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1924, 4, 2632},
- {"cvmx_npei_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1925, 1, 2636},
- {"cvmx_npei_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 1926, 2, 2637},
- {"cvmx_npei_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1927, 2, 2639},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1928, 2, 2641},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1929, 24, 2643},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1930, 4, 2667},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1931, 5, 2671},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1932, 5, 2676},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1933, 2, 2681},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1934, 1, 2683},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1935, 1, 2684},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1936, 5, 2685},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1937, 2, 2690},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1938, 1, 2692},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1939, 1, 2693},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1940, 4, 2694},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1941, 2, 2698},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1942, 2, 2700},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1943, 1, 2702},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1944, 1, 2703},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1945, 2, 2704},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1946, 3, 2706},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1947, 2, 2709},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1948, 2, 2711},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1949, 4, 2713},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1950, 10, 2717},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1951, 12, 2727},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1952, 7, 2739},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1953, 2, 2746},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1954, 1, 2748},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1955, 2, 2749},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1956, 7, 2751},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1957, 11, 2758},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1958, 19, 2769},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1959, 11, 2788},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1960, 17, 2799},
- {"cvmx_pcieep#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1961, 12, 2816},
- {"cvmx_pcieep#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1962, 22, 2828},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1963, 3, 2850},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1964, 3, 2853},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1965, 1, 2856},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1966, 1, 2857},
- {"cvmx_pcieep#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1967, 1, 2858},
- {"cvmx_pcieep#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1968, 1, 2859},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1969, 3, 2860},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1970, 14, 2863},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1971, 14, 2877},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1972, 14, 2891},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1973, 9, 2905},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1974, 9, 2914},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1975, 6, 2923},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1976, 1, 2929},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1977, 1, 2930},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1978, 1, 2931},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1979, 1, 2932},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1980, 2, 2933},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1981, 1, 2935},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1982, 6, 2936},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1983, 6, 2942},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1984, 13, 2948},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1985, 5, 2961},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1986, 8, 2966},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1987, 19, 2974},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1988, 3, 2993},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1989, 1, 2996},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1990, 1, 2997},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1991, 3, 2998},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1992, 3, 3001},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1993, 3, 3004},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1994, 4, 3007},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1995, 4, 3011},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1996, 4, 3015},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1997, 7, 3019},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1998, 5, 3026},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1999, 5, 3031},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 2000, 4, 3036},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 2001, 4, 3040},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 2002, 4, 3044},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 2003, 1, 3048},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 2004, 1, 3049},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2005, 2, 3050},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2007, 24, 3052},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2009, 4, 3076},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2011, 5, 3080},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2013, 1, 3085},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2015, 1, 3086},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2017, 4, 3087},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2019, 17, 3091},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2021, 4, 3108},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2023, 6, 3112},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2025, 1, 3118},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2027, 1, 3119},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2029, 2, 3120},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2031, 2, 3122},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2033, 1, 3124},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2035, 15, 3125},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2037, 10, 3140},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2039, 12, 3150},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2041, 7, 3162},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2043, 2, 3169},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2045, 1, 3171},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2047, 2, 3172},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2049, 7, 3174},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2051, 11, 3181},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2053, 19, 3192},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2055, 11, 3211},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2057, 20, 3222},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2059, 12, 3242},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2061, 22, 3254},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2063, 8, 3276},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2065, 4, 3284},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2067, 3, 3288},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2069, 3, 3291},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2071, 1, 3294},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2073, 1, 3295},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2075, 1, 3296},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2077, 1, 3297},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2079, 3, 3298},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2081, 14, 3301},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2083, 14, 3315},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2085, 14, 3329},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2087, 9, 3343},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2089, 9, 3352},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2091, 6, 3361},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2093, 1, 3367},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2095, 1, 3368},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2097, 1, 3369},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2099, 1, 3370},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2101, 4, 3371},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2103, 9, 3375},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2105, 2, 3384},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2107, 2, 3386},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2109, 1, 3388},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2111, 6, 3389},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2113, 6, 3395},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2115, 13, 3401},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2117, 5, 3414},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2119, 8, 3419},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2121, 19, 3427},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2123, 3, 3446},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2125, 1, 3449},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2127, 1, 3450},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2129, 3, 3451},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2131, 3, 3454},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2133, 3, 3457},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2135, 4, 3460},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2137, 4, 3464},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2139, 4, 3468},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2141, 7, 3472},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2143, 5, 3479},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2145, 5, 3484},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2147, 4, 3489},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2149, 4, 3493},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2151, 4, 3497},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2153, 1, 3501},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2155, 1, 3502},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2157, 9, 3503},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2165, 6, 3512},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2173, 9, 3518},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2181, 6, 3527},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2189, 13, 3533},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2197, 13, 3546},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 2205, 2, 3559},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2213, 4, 3561},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2221, 8, 3565},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2229, 13, 3573},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2237, 17, 3586},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2245, 7, 3603},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2253, 3, 3610},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2261, 8, 3613},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2269, 7, 3621},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2277, 4, 3628},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 2285, 5, 3632},
- {"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2293, 8, 3637},
- {"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2295, 2, 3645},
- {"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 2297, 5, 3647},
- {"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2299, 10, 3652},
- {"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2301, 2, 3662},
- {"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2303, 7, 3664},
- {"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2305, 7, 3671},
- {"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2307, 6, 3678},
- {"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2309, 5, 3684},
- {"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 2311, 5, 3689},
- {"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2313, 3, 3694},
- {"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2315, 6, 3697},
- {"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2317, 9, 3703},
- {"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 2319, 5, 3712},
- {"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2321, 10, 3717},
- {"cvmx_pesc#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2323, 14, 3727},
- {"cvmx_pesc#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 2325, 15, 3741},
- {"cvmx_pesc#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 2327, 2, 3756},
- {"cvmx_pesc#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 2329, 2, 3758},
- {"cvmx_pesc#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 2331, 2, 3760},
- {"cvmx_pesc#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2333, 16, 3762},
- {"cvmx_pesc#_ctl_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 2335, 3, 3778},
- {"cvmx_pesc#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 2337, 32, 3781},
- {"cvmx_pesc#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2339, 32, 3813},
- {"cvmx_pesc#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2341, 5, 3845},
- {"cvmx_pesc#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 2343, 2, 3850},
- {"cvmx_pesc#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 2345, 2, 3852},
- {"cvmx_pesc#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 2347, 2, 3854},
- {"cvmx_pesc#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 2349, 2, 3856},
- {"cvmx_pesc#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 2357, 2, 3858},
- {"cvmx_pesc#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 2365, 8, 3860},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 2367, 5, 3868},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2368, 2, 3873},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 2369, 4, 3875},
- {"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 2373, 16, 3879},
- {"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 2374, 16, 3895},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 2375, 3, 3911},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 2377, 8, 3914},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2378, 22, 3922},
- {"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2379, 6, 3944},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2380, 14, 3950},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2381, 14, 3964},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 2382, 2, 3978},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 2383, 28, 3980},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 2399, 25, 4008},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 2415, 2, 4033},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 2479, 4, 4035},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 2487, 9, 4039},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 2495, 2, 4048},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 2496, 2, 4050},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2497, 2, 4052},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2513, 2, 4054},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2529, 2, 4056},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2545, 2, 4058},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2561, 2, 4060},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2577, 2, 4062},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2593, 2, 4064},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2609, 2, 4066},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2625, 2, 4068},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2641, 2, 4070},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2657, 2, 4072},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2658, 2, 4074},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2674, 2, 4076},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 2690, 2, 4078},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 2706, 2, 4080},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2770, 2, 4082},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2771, 3, 4084},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2772, 3, 4087},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2773, 2, 4090},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2774, 2, 4092},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2775, 4, 4094},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2776, 5, 4098},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2777, 4, 4103},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2778, 8, 4107},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2779, 4, 4115},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2780, 5, 4119},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2781, 1, 4124},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2782, 5, 4125},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2783, 1, 4130},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2784, 13, 4131},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2785, 4, 4144},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2786, 13, 4148},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2787, 6, 4161},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2788, 9, 4167},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2789, 4, 4176},
- {"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2790, 7, 4180},
- {"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2791, 5, 4187},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 2792, 5, 4192},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 2793, 4, 4197},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2794, 9, 4201},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2795, 5, 4210},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2796, 16, 4215},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2797, 4, 4231},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2798, 1, 4235},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2799, 1, 4236},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2800, 1, 4237},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2801, 1, 4238},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 2802, 11, 4239},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 2803, 2, 4250},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2804, 4, 4252},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2805, 5, 4256},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2806, 3, 4261},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2807, 4, 4264},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2808, 2, 4268},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 2809, 3, 4270},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2810, 3, 4273},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2811, 13, 4276},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2812, 2, 4289},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2813, 13, 4291},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2814, 3, 4304},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2815, 2, 4307},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2823, 2, 4309},
- {"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2824, 2, 4311},
- {"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 2825, 2, 4313},
- {"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2826, 2, 4315},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2834, 2, 4317},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2835, 2, 4319},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 2836, 2, 4321},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2837, 10, 4323},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2849, 5, 4333},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2857, 8, 4338},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2865, 2, 4346},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2866, 2, 4348},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2867, 2, 4350},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2875, 3, 4352},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2876, 4, 4355},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2892, 5, 4359},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2893, 7, 4364},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2909, 2, 4371},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2925, 1, 4373},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2926, 1, 4374},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2927, 1, 4375},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2928, 5, 4376},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2929, 5, 4381},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2930, 4, 4386},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2931, 10, 4390},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2932, 1, 4400},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2933, 3, 4401},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2934, 7, 4404},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2935, 2, 4411},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2936, 1, 4413},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2937, 1, 4414},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2938, 1, 4415},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2939, 18, 4416},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2940, 3, 4434},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2941, 2, 4437},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2942, 3, 4439},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2943, 7, 4442},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2944, 2, 4449},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2945, 2, 4451},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 2946, 2, 4453},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2947, 3, 4455},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2948, 3, 4458},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2949, 7, 4461},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2950, 10, 4468},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2952, 6, 4478},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2954, 2, 4484},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2956, 4, 4486},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2958, 4, 4490},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2960, 6, 4494},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2961, 3, 4500},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2962, 5, 4503},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2963, 4, 4508},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2964, 6, 4512},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2965, 4, 4518},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2966, 2, 4522},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2967, 4, 4524},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2968, 2, 4528},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2969, 3, 4530},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2970, 4, 4533},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2971, 12, 4537},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2972, 3, 4549},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 2973, 5, 4552},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2974, 2, 4557},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2975, 2, 4559},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2976, 18, 4561},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2977, 12, 4579},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2978, 6, 4591},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2979, 5, 4597},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2980, 1, 4602},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2981, 2, 4603},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2982, 2, 4605},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2983, 18, 4607},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2984, 12, 4625},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2985, 6, 4637},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2986, 2, 4643},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2987, 2, 4645},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2988, 18, 4647},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2989, 12, 4665},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2990, 6, 4677},
- {"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 2991, 2, 4683},
- {"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2992, 2, 4685},
- {"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2993, 8, 4687},
- {"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2994, 11, 4695},
- {"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 2995, 15, 4706},
- {"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 3000, 8, 4721},
- {"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 3005, 8, 4729},
- {"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 3006, 4, 4737},
- {"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 3011, 15, 4741},
- {"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 3016, 6, 4756},
- {"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 3021, 6, 4762},
- {"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 3022, 4, 4768},
- {"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 3027, 2, 4772},
- {"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 3031, 6, 4774},
- {"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 3032, 4, 4780},
- {"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 3033, 1, 4784},
- {"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 3034, 1, 4785},
- {"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 3035, 1, 4786},
- {"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 3036, 7, 4787},
- {"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 3037, 1, 4794},
- {"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 3038, 14, 4795},
- {"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 3039, 10, 4809},
- {"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 3040, 14, 4819},
- {"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 3041, 32, 4833},
- {"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 3042, 32, 4865},
- {"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 3043, 2, 4897},
- {"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 3044, 4, 4899},
- {"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 3045, 13, 4903},
- {"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 3046, 10, 4916},
- {"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 3047, 10, 4926},
- {"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 3048, 2, 4936},
- {"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 3049, 6, 4938},
- {"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 3050, 5, 4944},
- {"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 3051, 6, 4949},
- {"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 3052, 5, 4955},
- {"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 3053, 1, 4960},
- {"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 3054, 13, 4961},
- {"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 3055, 2, 4974},
- {"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 3056, 2, 4976},
- {"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 3057, 11, 4978},
- {"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 3065, 3, 4989},
- {"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 3066, 12, 4992},
- {"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 3074, 12, 5004},
- {"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 3082, 6, 5016},
- {"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 3090, 4, 5022},
- {"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 3098, 2, 5026},
- {"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 3099, 2, 5028},
- {"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 3100, 15, 5030},
- {"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 3101, 2, 5045},
- {"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 3102, 3, 5047},
- {"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 3103, 1, 5050},
- {"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 3111, 6, 5051},
- {"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 3112, 8, 5057},
- {"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 3113, 15, 5065},
- {"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 3114, 6, 5080},
- {"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 3115, 2, 5086},
- {"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 3116, 2, 5088},
- {"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 3117, 2, 5090},
- {"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 3118, 2, 5092},
- {"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 3119, 2, 5094},
- {"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 3120, 2, 5096},
- {"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 3121, 2, 5098},
- {"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 3122, 2, 5100},
- {"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 3123, 2, 5102},
- {"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 3124, 2, 5104},
- {"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 3125, 2, 5106},
- {"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 3126, 2, 5108},
- {"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 3127, 2, 5110},
- {"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 3128, 2, 5112},
- {"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 3129, 2, 5114},
- {"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 3130, 2, 5116},
- {"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 3131, 7, 5118},
- {"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 3132, 34, 5125},
- {"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 3133, 34, 5159},
- {"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 3134, 35, 5193},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 3135, 3, 5228},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 3136, 5, 5231},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 3137, 3, 5236},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 3138, 6, 5239},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 3139, 2, 5245},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 3140, 2, 5247},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 3141, 2, 5249},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"AGL_GMX_BAD_REG" , 0x11800e0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"AGL_GMX_BIST" , 0x11800e0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"AGL_GMX_DRV_CTL" , 0x11800e00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_INF_MODE" , 0x11800e00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_PRT0_CFG" , 0x11800e0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX0_ADR_CAM0" , 0x11800e0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX0_ADR_CAM1" , 0x11800e0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX0_ADR_CAM2" , 0x11800e0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX0_ADR_CAM3" , 0x11800e0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX0_ADR_CAM4" , 0x11800e00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX0_ADR_CAM5" , 0x11800e00001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800e0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX0_ADR_CTL" , 0x11800e0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX0_DECISION" , 0x11800e0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX0_FRM_CHK" , 0x11800e0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX0_FRM_CTL" , 0x11800e0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX0_FRM_MAX" , 0x11800e0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX0_FRM_MIN" , 0x11800e0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX0_IFG" , 0x11800e0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX0_INT_EN" , 0x11800e0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX0_INT_REG" , 0x11800e0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX0_JABBER" , 0x11800e0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800e0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX0_STATS_CTL" , 0x11800e0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX0_STATS_OCTS" , 0x11800e0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800e0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800e00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800e00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX0_STATS_PKTS" , 0x11800e0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800e00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800e0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800e00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800e00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX0_UDD_SKP" , 0x11800e0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_DROP0" , 0x11800e0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_OFF0" , 0x11800e0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_BP_ON0" , 0x11800e0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_PRT_INFO" , 0x11800e00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"AGL_GMX_RX_TX_STATUS" , 0x11800e00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_SMAC0" , 0x11800e0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_STAT_BP" , 0x11800e0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX0_APPEND" , 0x11800e0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX0_CTL" , 0x11800e0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX0_MIN_PKT" , 0x11800e0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800e0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800e0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800e0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800e0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800e0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX0_STAT0" , 0x11800e0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX0_STAT1" , 0x11800e0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX0_STAT2" , 0x11800e0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX0_STAT3" , 0x11800e0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX0_STAT4" , 0x11800e00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX0_STAT5" , 0x11800e00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX0_STAT6" , 0x11800e00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX0_STAT7" , 0x11800e00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX0_STAT8" , 0x11800e00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX0_STAT9" , 0x11800e00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX0_STATS_CTL" , 0x11800e0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX0_THRESH" , 0x11800e0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX_BP" , 0x11800e00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"AGL_GMX_TX_COL_ATTEMPT" , 0x11800e0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"AGL_GMX_TX_IFG" , 0x11800e0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"AGL_GMX_TX_INT_EN" , 0x11800e0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"AGL_GMX_TX_INT_REG" , 0x11800e0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"AGL_GMX_TX_JAM" , 0x11800e0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"AGL_GMX_TX_LFSR" , 0x11800e00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"AGL_GMX_TX_OVR_BP" , 0x11800e00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800e00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800e00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 71},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT10_EN0" , 0x10700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT11_EN0" , 0x10700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT12_EN0" , 0x10700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT13_EN0" , 0x10700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT14_EN0" , 0x10700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT15_EN0" , 0x10700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT8_EN0_W1C" , 0x1070000002280ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT9_EN0_W1C" , 0x1070000002290ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT10_EN0_W1C" , 0x10700000022a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT11_EN0_W1C" , 0x10700000022b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT12_EN0_W1C" , 0x10700000022c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT13_EN0_W1C" , 0x10700000022d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT14_EN0_W1C" , 0x10700000022e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT15_EN0_W1C" , 0x10700000022f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT16_EN0_W1C" , 0x1070000002300ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT17_EN0_W1C" , 0x1070000002310ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT18_EN0_W1C" , 0x1070000002320ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT19_EN0_W1C" , 0x1070000002330ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT20_EN0_W1C" , 0x1070000002340ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT21_EN0_W1C" , 0x1070000002350ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT22_EN0_W1C" , 0x1070000002360ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT23_EN0_W1C" , 0x1070000002370ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT8_EN0_W1S" , 0x1070000006280ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT9_EN0_W1S" , 0x1070000006290ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT10_EN0_W1S" , 0x10700000062a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT11_EN0_W1S" , 0x10700000062b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT12_EN0_W1S" , 0x10700000062c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT13_EN0_W1S" , 0x10700000062d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT14_EN0_W1S" , 0x10700000062e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT15_EN0_W1S" , 0x10700000062f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT16_EN0_W1S" , 0x1070000006300ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT17_EN0_W1S" , 0x1070000006310ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT18_EN0_W1S" , 0x1070000006320ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT19_EN0_W1S" , 0x1070000006330ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT20_EN0_W1S" , 0x1070000006340ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT21_EN0_W1S" , 0x1070000006350ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT22_EN0_W1S" , 0x1070000006360ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT23_EN0_W1S" , 0x1070000006370ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT10_EN1" , 0x10700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT11_EN1" , 0x10700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT12_EN1" , 0x10700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT13_EN1" , 0x10700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT14_EN1" , 0x10700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT15_EN1" , 0x10700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT8_EN1_W1C" , 0x1070000002288ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT9_EN1_W1C" , 0x1070000002298ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT10_EN1_W1C" , 0x10700000022a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT11_EN1_W1C" , 0x10700000022b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT12_EN1_W1C" , 0x10700000022c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT13_EN1_W1C" , 0x10700000022d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT14_EN1_W1C" , 0x10700000022e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT15_EN1_W1C" , 0x10700000022f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT16_EN1_W1C" , 0x1070000002308ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT17_EN1_W1C" , 0x1070000002318ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT18_EN1_W1C" , 0x1070000002328ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT19_EN1_W1C" , 0x1070000002338ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT20_EN1_W1C" , 0x1070000002348ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT21_EN1_W1C" , 0x1070000002358ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT22_EN1_W1C" , 0x1070000002368ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT23_EN1_W1C" , 0x1070000002378ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT8_EN1_W1S" , 0x1070000006288ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT9_EN1_W1S" , 0x1070000006298ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT10_EN1_W1S" , 0x10700000062a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT11_EN1_W1S" , 0x10700000062b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT12_EN1_W1S" , 0x10700000062c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT13_EN1_W1S" , 0x10700000062d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT14_EN1_W1S" , 0x10700000062e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT15_EN1_W1S" , 0x10700000062f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT16_EN1_W1S" , 0x1070000006308ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT17_EN1_W1S" , 0x1070000006318ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT18_EN1_W1S" , 0x1070000006328ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT19_EN1_W1S" , 0x1070000006338ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT20_EN1_W1S" , 0x1070000006348ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT21_EN1_W1S" , 0x1070000006358ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT22_EN1_W1S" , 0x1070000006368ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT23_EN1_W1S" , 0x1070000006378ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT4_EN4_0" , 0x1070000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT5_EN4_0" , 0x1070000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT6_EN4_0" , 0x1070000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT7_EN4_0" , 0x1070000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT8_EN4_0" , 0x1070000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT9_EN4_0" , 0x1070000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT10_EN4_0" , 0x1070000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT11_EN4_0" , 0x1070000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT0_EN4_0_W1C" , 0x1070000002c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT1_EN4_0_W1C" , 0x1070000002c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT2_EN4_0_W1C" , 0x1070000002ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT3_EN4_0_W1C" , 0x1070000002cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT4_EN4_0_W1C" , 0x1070000002cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT5_EN4_0_W1C" , 0x1070000002cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT6_EN4_0_W1C" , 0x1070000002ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT7_EN4_0_W1C" , 0x1070000002cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT8_EN4_0_W1C" , 0x1070000002d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT9_EN4_0_W1C" , 0x1070000002d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT10_EN4_0_W1C" , 0x1070000002d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT11_EN4_0_W1C" , 0x1070000002d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT0_EN4_0_W1S" , 0x1070000006c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT1_EN4_0_W1S" , 0x1070000006c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT2_EN4_0_W1S" , 0x1070000006ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT3_EN4_0_W1S" , 0x1070000006cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT4_EN4_0_W1S" , 0x1070000006cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT5_EN4_0_W1S" , 0x1070000006cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT6_EN4_0_W1S" , 0x1070000006ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT7_EN4_0_W1S" , 0x1070000006cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT8_EN4_0_W1S" , 0x1070000006d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT9_EN4_0_W1S" , 0x1070000006d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT10_EN4_0_W1S" , 0x1070000006d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT11_EN4_0_W1S" , 0x1070000006d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT4_EN4_1" , 0x1070000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT5_EN4_1" , 0x1070000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT6_EN4_1" , 0x1070000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT7_EN4_1" , 0x1070000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT8_EN4_1" , 0x1070000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT9_EN4_1" , 0x1070000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT10_EN4_1" , 0x1070000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT11_EN4_1" , 0x1070000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT0_EN4_1_W1C" , 0x1070000002c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT1_EN4_1_W1C" , 0x1070000002c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT2_EN4_1_W1C" , 0x1070000002ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT3_EN4_1_W1C" , 0x1070000002cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT4_EN4_1_W1C" , 0x1070000002cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT5_EN4_1_W1C" , 0x1070000002cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT6_EN4_1_W1C" , 0x1070000002ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT7_EN4_1_W1C" , 0x1070000002cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT8_EN4_1_W1C" , 0x1070000002d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT9_EN4_1_W1C" , 0x1070000002d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT10_EN4_1_W1C" , 0x1070000002d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT11_EN4_1_W1C" , 0x1070000002d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT0_EN4_1_W1S" , 0x1070000006c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT1_EN4_1_W1S" , 0x1070000006c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT2_EN4_1_W1S" , 0x1070000006ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT3_EN4_1_W1S" , 0x1070000006cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT4_EN4_1_W1S" , 0x1070000006cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT5_EN4_1_W1S" , 0x1070000006cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT6_EN4_1_W1S" , 0x1070000006ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT7_EN4_1_W1S" , 0x1070000006cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT8_EN4_1_W1S" , 0x1070000006d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT9_EN4_1_W1S" , 0x1070000006d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT10_EN4_1_W1S" , 0x1070000006d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT11_EN4_1_W1S" , 0x1070000006d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT20_SUM0" , 0x10700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT21_SUM0" , 0x10700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT22_SUM0" , 0x10700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT23_SUM0" , 0x10700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT4_SUM4" , 0x1070000000c20ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT5_SUM4" , 0x1070000000c28ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT6_SUM4" , 0x1070000000c30ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT7_SUM4" , 0x1070000000c38ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT8_SUM4" , 0x1070000000c40ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT9_SUM4" , 0x1070000000c48ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT10_SUM4" , 0x1070000000c50ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT11_SUM4" , 0x1070000000c58ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR4" , 0x10700000006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR5" , 0x10700000006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR6" , 0x10700000006b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR7" , 0x10700000006b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR8" , 0x10700000006c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR9" , 0x10700000006c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR10" , 0x10700000006d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR11" , 0x10700000006d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE4" , 0x10700000005a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE5" , 0x10700000005a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE6" , 0x10700000005b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE7" , 0x10700000005b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE8" , 0x10700000005c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE9" , 0x10700000005c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE10" , 0x10700000005d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE11" , 0x10700000005d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_QLM_DCOK" , 0x1070000000760ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX1_CLK_EN" , 0x11800100007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX1_HG2_CONTROL" , 0x1180010000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX1_INF_MODE" , 0x11800100007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX1_PRT000_CBFC_CTL" , 0x1180010000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_RX000_ADR_CAM4" , 0x11800100001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_RX001_ADR_CAM4" , 0x11800100009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_RX002_ADR_CAM4" , 0x11800100011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX1_RX003_ADR_CAM4" , 0x11800100019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_RX000_ADR_CAM5" , 0x11800100001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_RX001_ADR_CAM5" , 0x11800100009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_RX002_ADR_CAM5" , 0x11800100011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX1_RX003_ADR_CAM5" , 0x11800100019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180010000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180010000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180010001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180010001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX1_RX_HG2_STATUS" , 0x1180010000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX1_RX_PRT_INFO" , 0x11800100004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX1_RX_XAUI_BAD_COL" , 0x1180010000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX1_RX_XAUI_CTL" , 0x1180010000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX1_SMAC001" , 0x1180010000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX1_SMAC003" , 0x1180010001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX1_TX001_APPEND" , 0x1180010000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX1_TX003_APPEND" , 0x1180010001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX1_TX001_BURST" , 0x1180010000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX1_TX003_BURST" , 0x1180010001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX000_CBFC_XOFF" , 0x11800080005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX1_TX000_CBFC_XOFF" , 0x11800100005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX000_CBFC_XON" , 0x11800080005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX1_TX000_CBFC_XON" , 0x11800100005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX1_TX001_CTL" , 0x1180010000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX1_TX003_CTL" , 0x1180010001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX1_TX001_MIN_PKT" , 0x1180010000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX1_TX003_MIN_PKT" , 0x1180010001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX1_TX001_PAUSE_TOGO" , 0x1180010000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX1_TX003_PAUSE_TOGO" , 0x1180010001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX1_TX001_PAUSE_ZERO" , 0x1180010000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX1_TX003_PAUSE_ZERO" , 0x1180010001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX003_SGMII_CTL" , 0x1180008001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX1_TX000_SGMII_CTL" , 0x1180010000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX1_TX001_SGMII_CTL" , 0x1180010000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX1_TX002_SGMII_CTL" , 0x1180010001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX1_TX003_SGMII_CTL" , 0x1180010001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX1_TX001_SLOT" , 0x1180010000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX1_TX003_SLOT" , 0x1180010001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX1_TX001_SOFT_PAUSE" , 0x1180010000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX1_TX003_SOFT_PAUSE" , 0x1180010001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX1_TX001_STAT0" , 0x1180010000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX1_TX003_STAT0" , 0x1180010001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX1_TX001_STAT1" , 0x1180010000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX1_TX003_STAT1" , 0x1180010001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX1_TX001_STAT2" , 0x1180010000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX1_TX003_STAT2" , 0x1180010001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX1_TX001_STAT3" , 0x1180010000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX1_TX003_STAT3" , 0x1180010001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX1_TX000_STAT4" , 0x11800100002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX1_TX001_STAT4" , 0x1180010000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX1_TX002_STAT4" , 0x11800100012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX1_TX003_STAT4" , 0x1180010001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX1_TX000_STAT5" , 0x11800100002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX1_TX001_STAT5" , 0x1180010000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX1_TX002_STAT5" , 0x11800100012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX1_TX003_STAT5" , 0x1180010001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX1_TX000_STAT6" , 0x11800100002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX1_TX001_STAT6" , 0x1180010000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX1_TX002_STAT6" , 0x11800100012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX1_TX003_STAT6" , 0x1180010001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX1_TX000_STAT7" , 0x11800100002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX1_TX001_STAT7" , 0x1180010000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX1_TX002_STAT7" , 0x11800100012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX1_TX003_STAT7" , 0x1180010001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX1_TX000_STAT8" , 0x11800100002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX1_TX001_STAT8" , 0x1180010000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX1_TX002_STAT8" , 0x11800100012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX1_TX003_STAT8" , 0x1180010001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX1_TX000_STAT9" , 0x11800100002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX1_TX001_STAT9" , 0x1180010000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX1_TX002_STAT9" , 0x11800100012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX1_TX003_STAT9" , 0x1180010001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX1_TX001_STATS_CTL" , 0x1180010000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX1_TX003_STATS_CTL" , 0x1180010001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX1_TX001_THRESH" , 0x1180010000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX1_TX003_THRESH" , 0x1180010001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"GMX1_TX_BP" , 0x11800100004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
- {"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
- {"GMX1_TX_CORRUPT" , 0x11800100004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
- {"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"GMX1_TX_HG2_REG1" , 0x1180010000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"GMX1_TX_HG2_REG2" , 0x1180010000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"GMX1_TX_LFSR" , 0x11800100004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"GMX1_TX_OVR_BP" , 0x11800100004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"GMX1_TX_XAUI_CTL" , 0x1180010000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"GMX1_XAUI_EXT_LOOPBACK" , 0x1180010000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT16_BP_PAGE_CNT" , 0x14f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT17_BP_PAGE_CNT" , 0x14f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT18_BP_PAGE_CNT" , 0x14f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT19_BP_PAGE_CNT" , 0x14f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT36_BP_PAGE_CNT2" , 0x14f0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT37_BP_PAGE_CNT2" , 0x14f0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT38_BP_PAGE_CNT2" , 0x14f0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT39_BP_PAGE_CNT2" , 0x14f0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14f0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14f0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14f0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14f00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14f0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14f0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14f0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14f0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_128_CNT" , 0x14f0000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_129_CNT" , 0x14f0000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_130_CNT" , 0x14f0000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_131_CNT" , 0x14f0000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_132_CNT" , 0x14f0000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_133_CNT" , 0x14f0000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_134_CNT" , 0x14f0000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_135_CNT" , 0x14f0000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_136_CNT" , 0x14f0000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_137_CNT" , 0x14f0000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_138_CNT" , 0x14f0000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_139_CNT" , 0x14f0000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_140_CNT" , 0x14f0000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_141_CNT" , 0x14f0000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_142_CNT" , 0x14f0000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_143_CNT" , 0x14f0000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_144_CNT" , 0x14f0000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_145_CNT" , 0x14f0000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_146_CNT" , 0x14f0000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_147_CNT" , 0x14f0000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_148_CNT" , 0x14f0000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_149_CNT" , 0x14f0000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_150_CNT" , 0x14f0000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_151_CNT" , 0x14f0000000d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_152_CNT" , 0x14f0000000d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_153_CNT" , 0x14f0000000d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_154_CNT" , 0x14f0000000d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_155_CNT" , 0x14f0000000d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_156_CNT" , 0x14f0000000d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_157_CNT" , 0x14f0000000d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_158_CNT" , 0x14f0000000d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_159_CNT" , 0x14f0000000d80ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_256_CNT" , 0x14f0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_257_CNT" , 0x14f0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_258_CNT" , 0x14f0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_259_CNT" , 0x14f00000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_260_CNT" , 0x14f00000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_261_CNT" , 0x14f00000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_262_CNT" , 0x14f00000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_263_CNT" , 0x14f00000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_264_CNT" , 0x14f00000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_265_CNT" , 0x14f00000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_266_CNT" , 0x14f00000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_267_CNT" , 0x14f00000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_268_CNT" , 0x14f00000010e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_269_CNT" , 0x14f00000010f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_270_CNT" , 0x14f00000010f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_271_CNT" , 0x14f0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_272_CNT" , 0x14f0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_273_CNT" , 0x14f0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_274_CNT" , 0x14f0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_275_CNT" , 0x14f0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_276_CNT" , 0x14f0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_277_CNT" , 0x14f0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_278_CNT" , 0x14f0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_279_CNT" , 0x14f0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_280_CNT" , 0x14f0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_281_CNT" , 0x14f0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_282_CNT" , 0x14f0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_283_CNT" , 0x14f0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_284_CNT" , 0x14f0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_285_CNT" , 0x14f0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_286_CNT" , 0x14f0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_287_CNT" , 0x14f0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"IPD_PORT_QOS_INT2" , 0x14f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"IPD_PORT_QOS_INT_ENB2" , 0x14f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"IPD_RED_PORT_ENABLE2" , 0x14f00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 265},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 266},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"L2C_GRPWRR0" , 0x11800800000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"L2C_GRPWRR1" , 0x11800800000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"L2C_INT_EN" , 0x1180080000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"L2C_INT_STAT" , 0x11800800000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"L2C_OOB" , 0x11800800000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"L2C_OOB1" , 0x11800800000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"L2C_OOB2" , 0x11800800000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"L2C_OOB3" , 0x11800800000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"L2C_PPGRP" , 0x11800800000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"LED_BLINK" , 0x1180000001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"LED_CLK_PHASE" , 0x1180000001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"LED_CYLON" , 0x1180000001af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"LED_DBG" , 0x1180000001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"LED_EN" , 0x1180000001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"LED_POLARITY" , 0x1180000001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"LED_PRT" , 0x1180000001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"LED_PRT_FMT" , 0x1180000001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"LED_PRT_STATUS0" , 0x1180000001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LED_PRT_STATUS1" , 0x1180000001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LED_PRT_STATUS2" , 0x1180000001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LED_PRT_STATUS3" , 0x1180000001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LED_PRT_STATUS4" , 0x1180000001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LED_PRT_STATUS5" , 0x1180000001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LED_PRT_STATUS6" , 0x1180000001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LED_PRT_STATUS7" , 0x1180000001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LED_UDD_CNT0" , 0x1180000001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"LED_UDD_CNT1" , 0x1180000001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"LED_UDD_DAT0" , 0x1180000001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"LED_UDD_DAT1" , 0x1180000001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"LED_UDD_DAT_CLR0" , 0x1180000001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"LED_UDD_DAT_CLR1" , 0x1180000001ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"LED_UDD_DAT_SET0" , 0x1180000001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"LED_UDD_DAT_SET1" , 0x1180000001ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"LMC0_BIST_CTL" , 0x11800880000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"LMC1_BIST_CTL" , 0x11800e80000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"LMC0_BIST_RESULT" , 0x11800880000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"LMC1_BIST_RESULT" , 0x11800e80000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"LMC1_COMP_CTL" , 0x11800e8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"LMC1_CTL" , 0x11800e8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"LMC1_CTL1" , 0x11800e8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"LMC1_DCLK_CNT_HI" , 0x11800e8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"LMC1_DCLK_CNT_LO" , 0x11800e8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"LMC0_DCLK_CTL" , 0x11800880000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"LMC1_DCLK_CTL" , 0x11800e80000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"LMC1_DDR2_CTL" , 0x11800e8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"LMC1_DELAY_CFG" , 0x11800e8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"LMC0_DLL_CTL" , 0x11800880000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"LMC1_DLL_CTL" , 0x11800e80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"LMC1_DUAL_MEMCFG" , 0x11800e8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"LMC1_ECC_SYND" , 0x11800e8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"LMC1_FADR" , 0x11800e8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
- {"LMC1_IFB_CNT_HI" , 0x11800e8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
- {"LMC1_IFB_CNT_LO" , 0x11800e8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"LMC1_MEM_CFG0" , 0x11800e8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"LMC1_MEM_CFG1" , 0x11800e8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"LMC0_NXM" , 0x11800880000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"LMC1_NXM" , 0x11800e80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"LMC1_OPS_CNT_HI" , 0x11800e8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"LMC1_OPS_CNT_LO" , 0x11800e8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"LMC0_PLL_CTL" , 0x11800880000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"LMC1_PLL_CTL" , 0x11800e80000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"LMC0_PLL_STATUS" , 0x11800880000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"LMC1_PLL_STATUS" , 0x11800e80000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"LMC0_READ_LEVEL_CTL" , 0x1180088000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"LMC1_READ_LEVEL_CTL" , 0x11800e8000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"LMC0_READ_LEVEL_DBG" , 0x1180088000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"LMC1_READ_LEVEL_DBG" , 0x11800e8000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"LMC0_READ_LEVEL_RANK000" , 0x1180088000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"LMC0_READ_LEVEL_RANK001" , 0x1180088000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"LMC0_READ_LEVEL_RANK002" , 0x1180088000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"LMC0_READ_LEVEL_RANK003" , 0x1180088000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"LMC1_READ_LEVEL_RANK000" , 0x11800e8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"LMC1_READ_LEVEL_RANK001" , 0x11800e8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"LMC1_READ_LEVEL_RANK002" , 0x11800e8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"LMC1_READ_LEVEL_RANK003" , 0x11800e8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"LMC0_RODT_COMP_CTL" , 0x11800880000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"LMC1_RODT_COMP_CTL" , 0x11800e80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"LMC1_RODT_CTL" , 0x11800e8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"LMC1_WODT_CTL0" , 0x11800e8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
- {"LMC1_WODT_CTL1" , 0x11800e8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"MIO_BOOT_DMA_CFG2" , 0x1180000000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"MIO_BOOT_DMA_INT2" , 0x1180000000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"MIO_BOOT_DMA_INT_EN2" , 0x1180000000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"MIO_BOOT_DMA_TIM2" , 0x1180000000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"MIO_BOOT_PIN_DEFS" , 0x11800000000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 412},
- {"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 413},
- {"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 414},
- {"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 415},
- {"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 416},
- {"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 417},
- {"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 418},
- {"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 419},
- {"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 420},
- {"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 421},
- {"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 422},
- {"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 423},
- {"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 424},
- {"NPEI_BAR1_INDEX0" , 0x11f0000008000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX1" , 0x11f0000008010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX2" , 0x11f0000008020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX3" , 0x11f0000008030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX4" , 0x11f0000008040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX5" , 0x11f0000008050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX6" , 0x11f0000008060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX7" , 0x11f0000008070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX8" , 0x11f0000008080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX9" , 0x11f0000008090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX10" , 0x11f00000080a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX11" , 0x11f00000080b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX12" , 0x11f00000080c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX13" , 0x11f00000080d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX14" , 0x11f00000080e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX15" , 0x11f00000080f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX16" , 0x11f0000008100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX17" , 0x11f0000008110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX18" , 0x11f0000008120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX19" , 0x11f0000008130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX20" , 0x11f0000008140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX21" , 0x11f0000008150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX22" , 0x11f0000008160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX23" , 0x11f0000008170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX24" , 0x11f0000008180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX25" , 0x11f0000008190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX26" , 0x11f00000081a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX27" , 0x11f00000081b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX28" , 0x11f00000081c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX29" , 0x11f00000081d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX30" , 0x11f00000081e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BAR1_INDEX31" , 0x11f00000081f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
- {"NPEI_BIST_STATUS" , 0x11f0000008580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 426},
- {"NPEI_BIST_STATUS2" , 0x11f0000008680ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 427},
- {"NPEI_CTL_PORT0" , 0x11f0000008250ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 428},
- {"NPEI_CTL_PORT1" , 0x11f0000008260ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 429},
- {"NPEI_CTL_STATUS" , 0x11f0000008570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 430},
- {"NPEI_CTL_STATUS2" , 0x11f000000bc00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 431},
- {"NPEI_DATA_OUT_CNT" , 0x11f00000085f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 432},
- {"NPEI_DBG_DATA" , 0x11f0000008510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 433},
- {"NPEI_DBG_SELECT" , 0x11f0000008500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 434},
- {"NPEI_DMA0_COUNTS" , 0x11f0000008450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
- {"NPEI_DMA1_COUNTS" , 0x11f0000008460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
- {"NPEI_DMA2_COUNTS" , 0x11f0000008470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
- {"NPEI_DMA3_COUNTS" , 0x11f0000008480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
- {"NPEI_DMA4_COUNTS" , 0x11f0000008490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
- {"NPEI_DMA0_DBELL" , 0x11f00000083b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 436},
- {"NPEI_DMA1_DBELL" , 0x11f00000083c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 436},
- {"NPEI_DMA2_DBELL" , 0x11f00000083d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 436},
- {"NPEI_DMA3_DBELL" , 0x11f00000083e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 436},
- {"NPEI_DMA4_DBELL" , 0x11f00000083f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 436},
- {"NPEI_DMA0_IBUFF_SADDR" , 0x11f0000008400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_DMA1_IBUFF_SADDR" , 0x11f0000008410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_DMA2_IBUFF_SADDR" , 0x11f0000008420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_DMA3_IBUFF_SADDR" , 0x11f0000008430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_DMA4_IBUFF_SADDR" , 0x11f0000008440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_DMA0_NADDR" , 0x11f00000084a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
- {"NPEI_DMA1_NADDR" , 0x11f00000084b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
- {"NPEI_DMA2_NADDR" , 0x11f00000084c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
- {"NPEI_DMA3_NADDR" , 0x11f00000084d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
- {"NPEI_DMA4_NADDR" , 0x11f00000084e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
- {"NPEI_DMA0_INT_LEVEL" , 0x11f00000085c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 439},
- {"NPEI_DMA1_INT_LEVEL" , 0x11f00000085d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 440},
- {"NPEI_DMA_CNTS" , 0x11f00000085e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 441},
- {"NPEI_DMA_CONTROL" , 0x11f00000083a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 442},
- {"NPEI_DMA_PCIE_REQ_NUM" , 0x11f00000085b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 443},
- {"NPEI_INT_A_ENB" , 0x11f0000008560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_INT_A_ENB2" , 0x11f000000bce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 445},
- {"NPEI_INT_A_SUM" , 0x11f0000008550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 446},
- {"NPEI_INT_ENB" , 0x11f0000008540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 447},
- {"NPEI_INT_ENB2" , 0x11f000000bcd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
- {"NPEI_INT_INFO" , 0x11f0000008590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 449},
- {"NPEI_INT_SUM" , 0x11f0000008530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
- {"NPEI_INT_SUM2" , 0x11f000000bcc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
- {"NPEI_LAST_WIN_RDATA0" , 0x11f0000008600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 452},
- {"NPEI_LAST_WIN_RDATA1" , 0x11f0000008610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 453},
- {"NPEI_MEM_ACCESS_CTL" , 0x11f00000084f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 454},
- {"NPEI_MEM_ACCESS_SUBID12" , 0x11f0000008280ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID13" , 0x11f0000008290ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID14" , 0x11f00000082a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID15" , 0x11f00000082b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID16" , 0x11f00000082c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID17" , 0x11f00000082d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID18" , 0x11f00000082e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID19" , 0x11f00000082f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID20" , 0x11f0000008300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID21" , 0x11f0000008310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID22" , 0x11f0000008320ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID23" , 0x11f0000008330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID24" , 0x11f0000008340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID25" , 0x11f0000008350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID26" , 0x11f0000008360ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MEM_ACCESS_SUBID27" , 0x11f0000008370ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_MSI_ENB0" , 0x11f000000bc50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 456},
- {"NPEI_MSI_ENB1" , 0x11f000000bc60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 457},
- {"NPEI_MSI_ENB2" , 0x11f000000bc70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 458},
- {"NPEI_MSI_ENB3" , 0x11f000000bc80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 459},
- {"NPEI_MSI_RCV0" , 0x11f000000bc10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 460},
- {"NPEI_MSI_RCV1" , 0x11f000000bc20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 461},
- {"NPEI_MSI_RCV2" , 0x11f000000bc30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 462},
- {"NPEI_MSI_RCV3" , 0x11f000000bc40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 463},
- {"NPEI_MSI_RD_MAP" , 0x11f000000bca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 464},
- {"NPEI_MSI_W1C_ENB0" , 0x11f000000bcf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 465},
- {"NPEI_MSI_W1C_ENB1" , 0x11f000000bd00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 466},
- {"NPEI_MSI_W1C_ENB2" , 0x11f000000bd10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 467},
- {"NPEI_MSI_W1C_ENB3" , 0x11f000000bd20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 468},
- {"NPEI_MSI_W1S_ENB0" , 0x11f000000bd30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 469},
- {"NPEI_MSI_W1S_ENB1" , 0x11f000000bd40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MSI_W1S_ENB2" , 0x11f000000bd50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 471},
- {"NPEI_MSI_W1S_ENB3" , 0x11f000000bd60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 472},
- {"NPEI_MSI_WR_MAP" , 0x11f000000bc90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 473},
- {"NPEI_PCIE_CREDIT_CNT" , 0x11f000000bd70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 474},
- {"NPEI_PCIE_MSI_RCV" , 0x11f000000bcb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 475},
- {"NPEI_PCIE_MSI_RCV_B1" , 0x11f0000008650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 476},
- {"NPEI_PCIE_MSI_RCV_B2" , 0x11f0000008660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 477},
- {"NPEI_PCIE_MSI_RCV_B3" , 0x11f0000008670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 478},
- {"NPEI_PKT0_CNTS" , 0x11f000000a400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT1_CNTS" , 0x11f000000a410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT2_CNTS" , 0x11f000000a420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT3_CNTS" , 0x11f000000a430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT4_CNTS" , 0x11f000000a440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT5_CNTS" , 0x11f000000a450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT6_CNTS" , 0x11f000000a460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT7_CNTS" , 0x11f000000a470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT8_CNTS" , 0x11f000000a480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT9_CNTS" , 0x11f000000a490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT10_CNTS" , 0x11f000000a4a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT11_CNTS" , 0x11f000000a4b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT12_CNTS" , 0x11f000000a4c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT13_CNTS" , 0x11f000000a4d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT14_CNTS" , 0x11f000000a4e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT15_CNTS" , 0x11f000000a4f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT16_CNTS" , 0x11f000000a500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT17_CNTS" , 0x11f000000a510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT18_CNTS" , 0x11f000000a520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT19_CNTS" , 0x11f000000a530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT20_CNTS" , 0x11f000000a540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT21_CNTS" , 0x11f000000a550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT22_CNTS" , 0x11f000000a560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT23_CNTS" , 0x11f000000a570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT24_CNTS" , 0x11f000000a580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT25_CNTS" , 0x11f000000a590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT26_CNTS" , 0x11f000000a5a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT27_CNTS" , 0x11f000000a5b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT28_CNTS" , 0x11f000000a5c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT29_CNTS" , 0x11f000000a5d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT30_CNTS" , 0x11f000000a5e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT31_CNTS" , 0x11f000000a5f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_PKT0_IN_BP" , 0x11f000000b800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT1_IN_BP" , 0x11f000000b810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT2_IN_BP" , 0x11f000000b820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT3_IN_BP" , 0x11f000000b830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT4_IN_BP" , 0x11f000000b840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT5_IN_BP" , 0x11f000000b850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT6_IN_BP" , 0x11f000000b860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT7_IN_BP" , 0x11f000000b870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT8_IN_BP" , 0x11f000000b880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT9_IN_BP" , 0x11f000000b890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT10_IN_BP" , 0x11f000000b8a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT11_IN_BP" , 0x11f000000b8b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT12_IN_BP" , 0x11f000000b8c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT13_IN_BP" , 0x11f000000b8d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT14_IN_BP" , 0x11f000000b8e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT15_IN_BP" , 0x11f000000b8f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT16_IN_BP" , 0x11f000000b900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT17_IN_BP" , 0x11f000000b910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT18_IN_BP" , 0x11f000000b920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT19_IN_BP" , 0x11f000000b930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT20_IN_BP" , 0x11f000000b940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT21_IN_BP" , 0x11f000000b950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT22_IN_BP" , 0x11f000000b960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT23_IN_BP" , 0x11f000000b970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT24_IN_BP" , 0x11f000000b980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT25_IN_BP" , 0x11f000000b990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT26_IN_BP" , 0x11f000000b9a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT27_IN_BP" , 0x11f000000b9b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT28_IN_BP" , 0x11f000000b9c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT29_IN_BP" , 0x11f000000b9d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT30_IN_BP" , 0x11f000000b9e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT31_IN_BP" , 0x11f000000b9f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_PKT0_INSTR_BADDR" , 0x11f000000a800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT1_INSTR_BADDR" , 0x11f000000a810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT2_INSTR_BADDR" , 0x11f000000a820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT3_INSTR_BADDR" , 0x11f000000a830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT4_INSTR_BADDR" , 0x11f000000a840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT5_INSTR_BADDR" , 0x11f000000a850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT6_INSTR_BADDR" , 0x11f000000a860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT7_INSTR_BADDR" , 0x11f000000a870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT8_INSTR_BADDR" , 0x11f000000a880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT9_INSTR_BADDR" , 0x11f000000a890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT10_INSTR_BADDR" , 0x11f000000a8a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT11_INSTR_BADDR" , 0x11f000000a8b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT12_INSTR_BADDR" , 0x11f000000a8c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT13_INSTR_BADDR" , 0x11f000000a8d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT14_INSTR_BADDR" , 0x11f000000a8e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT15_INSTR_BADDR" , 0x11f000000a8f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT16_INSTR_BADDR" , 0x11f000000a900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT17_INSTR_BADDR" , 0x11f000000a910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT18_INSTR_BADDR" , 0x11f000000a920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT19_INSTR_BADDR" , 0x11f000000a930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT20_INSTR_BADDR" , 0x11f000000a940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT21_INSTR_BADDR" , 0x11f000000a950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT22_INSTR_BADDR" , 0x11f000000a960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT23_INSTR_BADDR" , 0x11f000000a970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT24_INSTR_BADDR" , 0x11f000000a980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT25_INSTR_BADDR" , 0x11f000000a990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT26_INSTR_BADDR" , 0x11f000000a9a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT27_INSTR_BADDR" , 0x11f000000a9b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT28_INSTR_BADDR" , 0x11f000000a9c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT29_INSTR_BADDR" , 0x11f000000a9d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT30_INSTR_BADDR" , 0x11f000000a9e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT31_INSTR_BADDR" , 0x11f000000a9f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_PKT0_INSTR_BAOFF_DBELL" , 0x11f000000ac00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT1_INSTR_BAOFF_DBELL" , 0x11f000000ac10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT2_INSTR_BAOFF_DBELL" , 0x11f000000ac20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT3_INSTR_BAOFF_DBELL" , 0x11f000000ac30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT4_INSTR_BAOFF_DBELL" , 0x11f000000ac40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT5_INSTR_BAOFF_DBELL" , 0x11f000000ac50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT6_INSTR_BAOFF_DBELL" , 0x11f000000ac60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT7_INSTR_BAOFF_DBELL" , 0x11f000000ac70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT8_INSTR_BAOFF_DBELL" , 0x11f000000ac80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT9_INSTR_BAOFF_DBELL" , 0x11f000000ac90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT10_INSTR_BAOFF_DBELL", 0x11f000000aca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT11_INSTR_BAOFF_DBELL", 0x11f000000acb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT12_INSTR_BAOFF_DBELL", 0x11f000000acc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT13_INSTR_BAOFF_DBELL", 0x11f000000acd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT14_INSTR_BAOFF_DBELL", 0x11f000000ace0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT15_INSTR_BAOFF_DBELL", 0x11f000000acf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT16_INSTR_BAOFF_DBELL", 0x11f000000ad00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT17_INSTR_BAOFF_DBELL", 0x11f000000ad10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT18_INSTR_BAOFF_DBELL", 0x11f000000ad20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT19_INSTR_BAOFF_DBELL", 0x11f000000ad30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT20_INSTR_BAOFF_DBELL", 0x11f000000ad40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT21_INSTR_BAOFF_DBELL", 0x11f000000ad50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT22_INSTR_BAOFF_DBELL", 0x11f000000ad60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT23_INSTR_BAOFF_DBELL", 0x11f000000ad70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT24_INSTR_BAOFF_DBELL", 0x11f000000ad80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT25_INSTR_BAOFF_DBELL", 0x11f000000ad90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT26_INSTR_BAOFF_DBELL", 0x11f000000ada0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT27_INSTR_BAOFF_DBELL", 0x11f000000adb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT28_INSTR_BAOFF_DBELL", 0x11f000000adc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT29_INSTR_BAOFF_DBELL", 0x11f000000add0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT30_INSTR_BAOFF_DBELL", 0x11f000000ade0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT31_INSTR_BAOFF_DBELL", 0x11f000000adf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_PKT0_INSTR_FIFO_RSIZE" , 0x11f000000b000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT1_INSTR_FIFO_RSIZE" , 0x11f000000b010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT2_INSTR_FIFO_RSIZE" , 0x11f000000b020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT3_INSTR_FIFO_RSIZE" , 0x11f000000b030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT4_INSTR_FIFO_RSIZE" , 0x11f000000b040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT5_INSTR_FIFO_RSIZE" , 0x11f000000b050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT6_INSTR_FIFO_RSIZE" , 0x11f000000b060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT7_INSTR_FIFO_RSIZE" , 0x11f000000b070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT8_INSTR_FIFO_RSIZE" , 0x11f000000b080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT9_INSTR_FIFO_RSIZE" , 0x11f000000b090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT10_INSTR_FIFO_RSIZE" , 0x11f000000b0a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT11_INSTR_FIFO_RSIZE" , 0x11f000000b0b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT12_INSTR_FIFO_RSIZE" , 0x11f000000b0c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT13_INSTR_FIFO_RSIZE" , 0x11f000000b0d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT14_INSTR_FIFO_RSIZE" , 0x11f000000b0e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT15_INSTR_FIFO_RSIZE" , 0x11f000000b0f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT16_INSTR_FIFO_RSIZE" , 0x11f000000b100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT17_INSTR_FIFO_RSIZE" , 0x11f000000b110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT18_INSTR_FIFO_RSIZE" , 0x11f000000b120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT19_INSTR_FIFO_RSIZE" , 0x11f000000b130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT20_INSTR_FIFO_RSIZE" , 0x11f000000b140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT21_INSTR_FIFO_RSIZE" , 0x11f000000b150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT22_INSTR_FIFO_RSIZE" , 0x11f000000b160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT23_INSTR_FIFO_RSIZE" , 0x11f000000b170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT24_INSTR_FIFO_RSIZE" , 0x11f000000b180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT25_INSTR_FIFO_RSIZE" , 0x11f000000b190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT26_INSTR_FIFO_RSIZE" , 0x11f000000b1a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT27_INSTR_FIFO_RSIZE" , 0x11f000000b1b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT28_INSTR_FIFO_RSIZE" , 0x11f000000b1c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT29_INSTR_FIFO_RSIZE" , 0x11f000000b1d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT30_INSTR_FIFO_RSIZE" , 0x11f000000b1e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT31_INSTR_FIFO_RSIZE" , 0x11f000000b1f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_PKT0_INSTR_HEADER" , 0x11f000000b400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT1_INSTR_HEADER" , 0x11f000000b410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT2_INSTR_HEADER" , 0x11f000000b420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT3_INSTR_HEADER" , 0x11f000000b430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT4_INSTR_HEADER" , 0x11f000000b440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT5_INSTR_HEADER" , 0x11f000000b450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT6_INSTR_HEADER" , 0x11f000000b460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT7_INSTR_HEADER" , 0x11f000000b470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT8_INSTR_HEADER" , 0x11f000000b480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT9_INSTR_HEADER" , 0x11f000000b490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT10_INSTR_HEADER" , 0x11f000000b4a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT11_INSTR_HEADER" , 0x11f000000b4b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT12_INSTR_HEADER" , 0x11f000000b4c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT13_INSTR_HEADER" , 0x11f000000b4d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT14_INSTR_HEADER" , 0x11f000000b4e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT15_INSTR_HEADER" , 0x11f000000b4f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT16_INSTR_HEADER" , 0x11f000000b500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT17_INSTR_HEADER" , 0x11f000000b510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT18_INSTR_HEADER" , 0x11f000000b520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT19_INSTR_HEADER" , 0x11f000000b530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT20_INSTR_HEADER" , 0x11f000000b540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT21_INSTR_HEADER" , 0x11f000000b550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT22_INSTR_HEADER" , 0x11f000000b560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT23_INSTR_HEADER" , 0x11f000000b570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT24_INSTR_HEADER" , 0x11f000000b580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT25_INSTR_HEADER" , 0x11f000000b590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT26_INSTR_HEADER" , 0x11f000000b5a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT27_INSTR_HEADER" , 0x11f000000b5b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT28_INSTR_HEADER" , 0x11f000000b5c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT29_INSTR_HEADER" , 0x11f000000b5d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT30_INSTR_HEADER" , 0x11f000000b5e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT31_INSTR_HEADER" , 0x11f000000b5f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_PKT0_SLIST_BADDR" , 0x11f0000009400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT1_SLIST_BADDR" , 0x11f0000009410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT2_SLIST_BADDR" , 0x11f0000009420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT3_SLIST_BADDR" , 0x11f0000009430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT4_SLIST_BADDR" , 0x11f0000009440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT5_SLIST_BADDR" , 0x11f0000009450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT6_SLIST_BADDR" , 0x11f0000009460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT7_SLIST_BADDR" , 0x11f0000009470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT8_SLIST_BADDR" , 0x11f0000009480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT9_SLIST_BADDR" , 0x11f0000009490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT10_SLIST_BADDR" , 0x11f00000094a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT11_SLIST_BADDR" , 0x11f00000094b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT12_SLIST_BADDR" , 0x11f00000094c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT13_SLIST_BADDR" , 0x11f00000094d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT14_SLIST_BADDR" , 0x11f00000094e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT15_SLIST_BADDR" , 0x11f00000094f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT16_SLIST_BADDR" , 0x11f0000009500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT17_SLIST_BADDR" , 0x11f0000009510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT18_SLIST_BADDR" , 0x11f0000009520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT19_SLIST_BADDR" , 0x11f0000009530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT20_SLIST_BADDR" , 0x11f0000009540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT21_SLIST_BADDR" , 0x11f0000009550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT22_SLIST_BADDR" , 0x11f0000009560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT23_SLIST_BADDR" , 0x11f0000009570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT24_SLIST_BADDR" , 0x11f0000009580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT25_SLIST_BADDR" , 0x11f0000009590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT26_SLIST_BADDR" , 0x11f00000095a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT27_SLIST_BADDR" , 0x11f00000095b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT28_SLIST_BADDR" , 0x11f00000095c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT29_SLIST_BADDR" , 0x11f00000095d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT30_SLIST_BADDR" , 0x11f00000095e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT31_SLIST_BADDR" , 0x11f00000095f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_PKT0_SLIST_BAOFF_DBELL" , 0x11f0000009800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT1_SLIST_BAOFF_DBELL" , 0x11f0000009810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT2_SLIST_BAOFF_DBELL" , 0x11f0000009820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT3_SLIST_BAOFF_DBELL" , 0x11f0000009830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT4_SLIST_BAOFF_DBELL" , 0x11f0000009840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT5_SLIST_BAOFF_DBELL" , 0x11f0000009850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT6_SLIST_BAOFF_DBELL" , 0x11f0000009860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT7_SLIST_BAOFF_DBELL" , 0x11f0000009870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT8_SLIST_BAOFF_DBELL" , 0x11f0000009880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT9_SLIST_BAOFF_DBELL" , 0x11f0000009890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT10_SLIST_BAOFF_DBELL", 0x11f00000098a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT11_SLIST_BAOFF_DBELL", 0x11f00000098b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT12_SLIST_BAOFF_DBELL", 0x11f00000098c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT13_SLIST_BAOFF_DBELL", 0x11f00000098d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT14_SLIST_BAOFF_DBELL", 0x11f00000098e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT15_SLIST_BAOFF_DBELL", 0x11f00000098f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT16_SLIST_BAOFF_DBELL", 0x11f0000009900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT17_SLIST_BAOFF_DBELL", 0x11f0000009910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT18_SLIST_BAOFF_DBELL", 0x11f0000009920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT19_SLIST_BAOFF_DBELL", 0x11f0000009930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT20_SLIST_BAOFF_DBELL", 0x11f0000009940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT21_SLIST_BAOFF_DBELL", 0x11f0000009950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT22_SLIST_BAOFF_DBELL", 0x11f0000009960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT23_SLIST_BAOFF_DBELL", 0x11f0000009970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT24_SLIST_BAOFF_DBELL", 0x11f0000009980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT25_SLIST_BAOFF_DBELL", 0x11f0000009990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT26_SLIST_BAOFF_DBELL", 0x11f00000099a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT27_SLIST_BAOFF_DBELL", 0x11f00000099b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT28_SLIST_BAOFF_DBELL", 0x11f00000099c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT29_SLIST_BAOFF_DBELL", 0x11f00000099d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT30_SLIST_BAOFF_DBELL", 0x11f00000099e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT31_SLIST_BAOFF_DBELL", 0x11f00000099f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_PKT0_SLIST_FIFO_RSIZE" , 0x11f0000009c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT1_SLIST_FIFO_RSIZE" , 0x11f0000009c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT2_SLIST_FIFO_RSIZE" , 0x11f0000009c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT3_SLIST_FIFO_RSIZE" , 0x11f0000009c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT4_SLIST_FIFO_RSIZE" , 0x11f0000009c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT5_SLIST_FIFO_RSIZE" , 0x11f0000009c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT6_SLIST_FIFO_RSIZE" , 0x11f0000009c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT7_SLIST_FIFO_RSIZE" , 0x11f0000009c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT8_SLIST_FIFO_RSIZE" , 0x11f0000009c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT9_SLIST_FIFO_RSIZE" , 0x11f0000009c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT10_SLIST_FIFO_RSIZE" , 0x11f0000009ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT11_SLIST_FIFO_RSIZE" , 0x11f0000009cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT12_SLIST_FIFO_RSIZE" , 0x11f0000009cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT13_SLIST_FIFO_RSIZE" , 0x11f0000009cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT14_SLIST_FIFO_RSIZE" , 0x11f0000009ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT15_SLIST_FIFO_RSIZE" , 0x11f0000009cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT16_SLIST_FIFO_RSIZE" , 0x11f0000009d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT17_SLIST_FIFO_RSIZE" , 0x11f0000009d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT18_SLIST_FIFO_RSIZE" , 0x11f0000009d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT19_SLIST_FIFO_RSIZE" , 0x11f0000009d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT20_SLIST_FIFO_RSIZE" , 0x11f0000009d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT21_SLIST_FIFO_RSIZE" , 0x11f0000009d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT22_SLIST_FIFO_RSIZE" , 0x11f0000009d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT23_SLIST_FIFO_RSIZE" , 0x11f0000009d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT24_SLIST_FIFO_RSIZE" , 0x11f0000009d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT25_SLIST_FIFO_RSIZE" , 0x11f0000009d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT26_SLIST_FIFO_RSIZE" , 0x11f0000009da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT27_SLIST_FIFO_RSIZE" , 0x11f0000009db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT28_SLIST_FIFO_RSIZE" , 0x11f0000009dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT29_SLIST_FIFO_RSIZE" , 0x11f0000009dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT30_SLIST_FIFO_RSIZE" , 0x11f0000009de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT31_SLIST_FIFO_RSIZE" , 0x11f0000009df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_PKT_CNT_INT" , 0x11f0000009110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 488},
- {"NPEI_PKT_CNT_INT_ENB" , 0x11f0000009130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 489},
- {"NPEI_PKT_DATA_OUT_ES" , 0x11f00000090b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 490},
- {"NPEI_PKT_DATA_OUT_NS" , 0x11f00000090a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 491},
- {"NPEI_PKT_DATA_OUT_ROR" , 0x11f0000009090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 492},
- {"NPEI_PKT_DPADDR" , 0x11f0000009080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 493},
- {"NPEI_PKT_IN_BP" , 0x11f00000086b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT_IN_DONE0_CNTS" , 0x11f000000a000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE1_CNTS" , 0x11f000000a010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE2_CNTS" , 0x11f000000a020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE3_CNTS" , 0x11f000000a030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE4_CNTS" , 0x11f000000a040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE5_CNTS" , 0x11f000000a050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE6_CNTS" , 0x11f000000a060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE7_CNTS" , 0x11f000000a070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE8_CNTS" , 0x11f000000a080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE9_CNTS" , 0x11f000000a090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE10_CNTS" , 0x11f000000a0a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE11_CNTS" , 0x11f000000a0b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE12_CNTS" , 0x11f000000a0c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE13_CNTS" , 0x11f000000a0d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE14_CNTS" , 0x11f000000a0e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE15_CNTS" , 0x11f000000a0f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE16_CNTS" , 0x11f000000a100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE17_CNTS" , 0x11f000000a110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE18_CNTS" , 0x11f000000a120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE19_CNTS" , 0x11f000000a130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE20_CNTS" , 0x11f000000a140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE21_CNTS" , 0x11f000000a150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE22_CNTS" , 0x11f000000a160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE23_CNTS" , 0x11f000000a170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE24_CNTS" , 0x11f000000a180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE25_CNTS" , 0x11f000000a190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE26_CNTS" , 0x11f000000a1a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE27_CNTS" , 0x11f000000a1b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE28_CNTS" , 0x11f000000a1c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE29_CNTS" , 0x11f000000a1d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE30_CNTS" , 0x11f000000a1e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_DONE31_CNTS" , 0x11f000000a1f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT_IN_INSTR_COUNTS" , 0x11f00000086a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT_IN_PCIE_PORT" , 0x11f00000091a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT_INPUT_CONTROL" , 0x11f0000009150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT_INSTR_ENB" , 0x11f0000009000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT_INSTR_RD_SIZE" , 0x11f0000009190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT_INSTR_SIZE" , 0x11f0000009020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT_INT_LEVELS" , 0x11f0000009100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT_IPTR" , 0x11f0000009070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 503},
- {"NPEI_PKT_OUT_BMODE" , 0x11f00000090d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 504},
- {"NPEI_PKT_OUT_ENB" , 0x11f0000009010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 505},
- {"NPEI_PKT_OUTPUT_WMARK" , 0x11f0000009160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 506},
- {"NPEI_PKT_PCIE_PORT" , 0x11f00000090e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 507},
- {"NPEI_PKT_PORT_IN_RST" , 0x11f0000008690ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 508},
- {"NPEI_PKT_SLIST_ES" , 0x11f0000009050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 509},
- {"NPEI_PKT_SLIST_ID_SIZE" , 0x11f0000009180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_SLIST_NS" , 0x11f0000009040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 511},
- {"NPEI_PKT_SLIST_ROR" , 0x11f0000009030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 512},
- {"NPEI_PKT_TIME_INT" , 0x11f0000009120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 513},
- {"NPEI_PKT_TIME_INT_ENB" , 0x11f0000009140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 514},
- {"NPEI_RSL_INT_BLOCKS" , 0x11f0000008520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 515},
- {"NPEI_SCRATCH_1" , 0x11f0000008270ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 516},
- {"NPEI_STATE1" , 0x11f0000008620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 517},
- {"NPEI_STATE2" , 0x11f0000008630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 518},
- {"NPEI_STATE3" , 0x11f0000008640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 519},
- {"NPEI_WIN_RD_ADDR" , 0x210ull, CVMX_CSR_DB_TYPE_PEXP, 64, 520},
- {"NPEI_WIN_RD_DATA" , 0x240ull, CVMX_CSR_DB_TYPE_PEXP, 64, 521},
- {"NPEI_WIN_WR_ADDR" , 0x200ull, CVMX_CSR_DB_TYPE_PEXP, 64, 522},
- {"NPEI_WIN_WR_DATA" , 0x220ull, CVMX_CSR_DB_TYPE_PEXP, 64, 523},
- {"NPEI_WIN_WR_MASK" , 0x230ull, CVMX_CSR_DB_TYPE_PEXP, 64, 524},
- {"NPEI_WINDOW_CTL" , 0x11f0000008380ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 525},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 526},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 527},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 528},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 529},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 530},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 531},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 532},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 533},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 534},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 535},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 536},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 537},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 538},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 539},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 540},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 541},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 542},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 543},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 544},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 545},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 546},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 547},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 548},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 549},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 550},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 551},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 552},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 553},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 554},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 555},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 556},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 557},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 558},
- {"PCIEEP0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 559},
- {"PCIEEP0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 560},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 561},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 562},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 563},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 564},
- {"PCIEEP0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 565},
- {"PCIEEP0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 566},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 567},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 568},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 569},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 570},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 571},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 572},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 573},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 574},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 575},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 576},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 577},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 578},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 579},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 580},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 581},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 582},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 583},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 584},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 585},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 586},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 587},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 588},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 589},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 590},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 591},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 592},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 593},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 594},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 595},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 596},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 597},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 598},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 599},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 600},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 601},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 602},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 616},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 616},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 617},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 617},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 623},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 623},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 624},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 624},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 625},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 625},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 626},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 626},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 627},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 627},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 628},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 628},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"PCS0_AN002_ADV_REG" , 0x11800b0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"PCS0_AN003_ADV_REG" , 0x11800b0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"PCS1_AN000_ADV_REG" , 0x11800b8001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"PCS1_AN001_ADV_REG" , 0x11800b8001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"PCS1_AN002_ADV_REG" , 0x11800b8001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"PCS1_AN003_ADV_REG" , 0x11800b8001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PCS0_AN002_EXT_ST_REG" , 0x11800b0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PCS0_AN003_EXT_ST_REG" , 0x11800b0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PCS1_AN000_EXT_ST_REG" , 0x11800b8001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PCS1_AN001_EXT_ST_REG" , 0x11800b8001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PCS1_AN002_EXT_ST_REG" , 0x11800b8001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PCS1_AN003_EXT_ST_REG" , 0x11800b8001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PCS0_AN002_LP_ABIL_REG" , 0x11800b0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PCS0_AN003_LP_ABIL_REG" , 0x11800b0001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PCS1_AN000_LP_ABIL_REG" , 0x11800b8001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PCS1_AN001_LP_ABIL_REG" , 0x11800b8001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PCS1_AN002_LP_ABIL_REG" , 0x11800b8001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PCS1_AN003_LP_ABIL_REG" , 0x11800b8001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PCS0_AN002_RESULTS_REG" , 0x11800b0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PCS0_AN003_RESULTS_REG" , 0x11800b0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PCS1_AN000_RESULTS_REG" , 0x11800b8001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PCS1_AN001_RESULTS_REG" , 0x11800b8001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PCS1_AN002_RESULTS_REG" , 0x11800b8001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PCS1_AN003_RESULTS_REG" , 0x11800b8001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PCS0_INT002_EN_REG" , 0x11800b0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PCS0_INT003_EN_REG" , 0x11800b0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PCS1_INT000_EN_REG" , 0x11800b8001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PCS1_INT001_EN_REG" , 0x11800b8001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PCS1_INT002_EN_REG" , 0x11800b8001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PCS1_INT003_EN_REG" , 0x11800b8001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PCS0_INT002_REG" , 0x11800b0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PCS0_INT003_REG" , 0x11800b0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PCS1_INT000_REG" , 0x11800b8001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PCS1_INT001_REG" , 0x11800b8001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PCS1_INT002_REG" , 0x11800b8001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PCS1_INT003_REG" , 0x11800b8001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PCS0_LINK002_TIMER_COUNT_REG", 0x11800b0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PCS0_LINK003_TIMER_COUNT_REG", 0x11800b0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PCS1_LINK000_TIMER_COUNT_REG", 0x11800b8001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PCS1_LINK001_TIMER_COUNT_REG", 0x11800b8001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PCS1_LINK002_TIMER_COUNT_REG", 0x11800b8001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PCS1_LINK003_TIMER_COUNT_REG", 0x11800b8001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PCS0_LOG_ANL002_REG" , 0x11800b0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PCS0_LOG_ANL003_REG" , 0x11800b0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PCS1_LOG_ANL000_REG" , 0x11800b8001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PCS1_LOG_ANL001_REG" , 0x11800b8001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PCS1_LOG_ANL002_REG" , 0x11800b8001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PCS1_LOG_ANL003_REG" , 0x11800b8001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PCS0_MISC002_CTL_REG" , 0x11800b0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PCS0_MISC003_CTL_REG" , 0x11800b0001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PCS1_MISC000_CTL_REG" , 0x11800b8001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PCS1_MISC001_CTL_REG" , 0x11800b8001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PCS1_MISC002_CTL_REG" , 0x11800b8001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PCS1_MISC003_CTL_REG" , 0x11800b8001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PCS0_MR002_CONTROL_REG" , 0x11800b0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PCS0_MR003_CONTROL_REG" , 0x11800b0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PCS1_MR000_CONTROL_REG" , 0x11800b8001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PCS1_MR001_CONTROL_REG" , 0x11800b8001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PCS1_MR002_CONTROL_REG" , 0x11800b8001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PCS1_MR003_CONTROL_REG" , 0x11800b8001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PCS0_MR002_STATUS_REG" , 0x11800b0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PCS0_MR003_STATUS_REG" , 0x11800b0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PCS1_MR000_STATUS_REG" , 0x11800b8001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PCS1_MR001_STATUS_REG" , 0x11800b8001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PCS1_MR002_STATUS_REG" , 0x11800b8001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PCS1_MR003_STATUS_REG" , 0x11800b8001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PCS0_RX002_STATES_REG" , 0x11800b0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PCS0_RX003_STATES_REG" , 0x11800b0001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PCS1_RX000_STATES_REG" , 0x11800b8001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PCS1_RX001_STATES_REG" , 0x11800b8001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PCS1_RX002_STATES_REG" , 0x11800b8001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PCS1_RX003_STATES_REG" , 0x11800b8001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PCS0_RX002_SYNC_REG" , 0x11800b0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PCS0_RX003_SYNC_REG" , 0x11800b0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PCS1_RX000_SYNC_REG" , 0x11800b8001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PCS1_RX001_SYNC_REG" , 0x11800b8001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PCS1_RX002_SYNC_REG" , 0x11800b8001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PCS1_RX003_SYNC_REG" , 0x11800b8001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PCS0_SGM002_AN_ADV_REG" , 0x11800b0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PCS0_SGM003_AN_ADV_REG" , 0x11800b0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PCS1_SGM000_AN_ADV_REG" , 0x11800b8001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PCS1_SGM001_AN_ADV_REG" , 0x11800b8001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PCS1_SGM002_AN_ADV_REG" , 0x11800b8001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PCS1_SGM003_AN_ADV_REG" , 0x11800b8001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PCS0_SGM002_LP_ADV_REG" , 0x11800b0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PCS0_SGM003_LP_ADV_REG" , 0x11800b0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PCS1_SGM000_LP_ADV_REG" , 0x11800b8001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PCS1_SGM001_LP_ADV_REG" , 0x11800b8001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PCS1_SGM002_LP_ADV_REG" , 0x11800b8001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PCS1_SGM003_LP_ADV_REG" , 0x11800b8001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS0_TX002_STATES_REG" , 0x11800b0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS0_TX003_STATES_REG" , 0x11800b0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS1_TX000_STATES_REG" , 0x11800b8001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS1_TX001_STATES_REG" , 0x11800b8001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS1_TX002_STATES_REG" , 0x11800b8001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS1_TX003_STATES_REG" , 0x11800b8001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS0_TX_RX002_POLARITY_REG" , 0x11800b0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS0_TX_RX003_POLARITY_REG" , 0x11800b0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS1_TX_RX000_POLARITY_REG" , 0x11800b8001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS1_TX_RX001_POLARITY_REG" , 0x11800b8001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS1_TX_RX002_POLARITY_REG" , 0x11800b8001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS1_TX_RX003_POLARITY_REG" , 0x11800b8001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCSX0_10GBX_STATUS_REG" , 0x11800b0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PCSX1_10GBX_STATUS_REG" , 0x11800b8000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PCSX0_BIST_STATUS_REG" , 0x11800b0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PCSX1_BIST_STATUS_REG" , 0x11800b8000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800b0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PCSX1_BIT_LOCK_STATUS_REG" , 0x11800b8000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PCSX0_CONTROL1_REG" , 0x11800b0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PCSX1_CONTROL1_REG" , 0x11800b8000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PCSX0_CONTROL2_REG" , 0x11800b0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PCSX1_CONTROL2_REG" , 0x11800b8000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PCSX0_INT_EN_REG" , 0x11800b0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PCSX1_INT_EN_REG" , 0x11800b8000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PCSX0_INT_REG" , 0x11800b0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PCSX1_INT_REG" , 0x11800b8000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PCSX0_LOG_ANL_REG" , 0x11800b0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PCSX1_LOG_ANL_REG" , 0x11800b8000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PCSX0_MISC_CTL_REG" , 0x11800b0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PCSX1_MISC_CTL_REG" , 0x11800b8000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PCSX0_RX_SYNC_STATES_REG" , 0x11800b0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PCSX1_RX_SYNC_STATES_REG" , 0x11800b8000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PCSX0_SPD_ABIL_REG" , 0x11800b0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCSX1_SPD_ABIL_REG" , 0x11800b8000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCSX0_STATUS1_REG" , 0x11800b0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCSX1_STATUS1_REG" , 0x11800b8000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCSX0_STATUS2_REG" , 0x11800b0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCSX1_STATUS2_REG" , 0x11800b8000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCSX0_TX_RX_POLARITY_REG" , 0x11800b0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCSX1_TX_RX_POLARITY_REG" , 0x11800b8000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCSX0_TX_RX_STATES_REG" , 0x11800b0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCSX1_TX_RX_STATES_REG" , 0x11800b8000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PESC0_BIST_STATUS" , 0x11800c8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PESC1_BIST_STATUS" , 0x11800d0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PESC0_BIST_STATUS2" , 0x11800c8000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PESC1_BIST_STATUS2" , 0x11800d0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PESC0_CFG_RD" , 0x11800c8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PESC1_CFG_RD" , 0x11800d0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PESC0_CFG_WR" , 0x11800c8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PESC1_CFG_WR" , 0x11800d0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PESC0_CPL_LUT_VALID" , 0x11800c8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"PESC1_CPL_LUT_VALID" , 0x11800d0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"PESC0_CTL_STATUS" , 0x11800c8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"PESC1_CTL_STATUS" , 0x11800d0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"PESC0_CTL_STATUS2" , 0x11800c8000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"PESC1_CTL_STATUS2" , 0x11800d0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"PESC0_DBG_INFO" , 0x11800c8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"PESC1_DBG_INFO" , 0x11800d0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"PESC0_DBG_INFO_EN" , 0x11800c80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"PESC1_DBG_INFO_EN" , 0x11800d00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"PESC0_DIAG_STATUS" , 0x11800c8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"PESC1_DIAG_STATUS" , 0x11800d0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"PESC0_P2N_BAR0_START" , 0x11800c8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"PESC1_P2N_BAR0_START" , 0x11800d0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"PESC0_P2N_BAR1_START" , 0x11800c8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"PESC1_P2N_BAR1_START" , 0x11800d0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"PESC0_P2N_BAR2_START" , 0x11800c8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
- {"PESC1_P2N_BAR2_START" , 0x11800d0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
- {"PESC0_P2P_BAR000_END" , 0x11800c8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PESC0_P2P_BAR001_END" , 0x11800c8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PESC0_P2P_BAR002_END" , 0x11800c8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PESC0_P2P_BAR003_END" , 0x11800c8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PESC1_P2P_BAR000_END" , 0x11800d0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PESC1_P2P_BAR001_END" , 0x11800d0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PESC1_P2P_BAR002_END" , 0x11800d0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PESC1_P2P_BAR003_END" , 0x11800d0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PESC0_P2P_BAR000_START" , 0x11800c8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PESC0_P2P_BAR001_START" , 0x11800c8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PESC0_P2P_BAR002_START" , 0x11800c8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PESC0_P2P_BAR003_START" , 0x11800c8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PESC1_P2P_BAR000_START" , 0x11800d0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PESC1_P2P_BAR001_START" , 0x11800d0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PESC1_P2P_BAR002_START" , 0x11800d0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PESC1_P2P_BAR003_START" , 0x11800d0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PESC0_TLP_CREDITS" , 0x11800c8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
- {"PESC1_TLP_CREDITS" , 0x11800d0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"PIP_DSA_SRC_GRP" , 0x11800a0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PIP_DSA_VID_GRP" , 0x11800a0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"PIP_FRM_LEN_CHK1" , 0x11800a0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
- {"PIP_HG_PRI_QOS" , 0x11800a00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG16" , 0x11800a0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG17" , 0x11800a0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG18" , 0x11800a0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG19" , 0x11800a0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG16" , 0x11800a0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG17" , 0x11800a0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG18" , 0x11800a0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG19" , 0x11800a0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT16" , 0x11800a0000d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT17" , 0x11800a0000d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT18" , 0x11800a0000da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT19" , 0x11800a0000df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT36" , 0x11800a0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT37" , 0x11800a0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT38" , 0x11800a00013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT0_PRT39" , 0x11800a0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT16" , 0x11800a0000d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT17" , 0x11800a0000d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT18" , 0x11800a0000da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT19" , 0x11800a0000df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT36" , 0x11800a0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT37" , 0x11800a0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT38" , 0x11800a00013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT1_PRT39" , 0x11800a0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT16" , 0x11800a0000d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT17" , 0x11800a0000d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT18" , 0x11800a0000db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT19" , 0x11800a0000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT36" , 0x11800a0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT37" , 0x11800a00013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT38" , 0x11800a00013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT2_PRT39" , 0x11800a0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT16" , 0x11800a0000d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT17" , 0x11800a0000d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT18" , 0x11800a0000db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT19" , 0x11800a0000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT36" , 0x11800a0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT37" , 0x11800a00013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT38" , 0x11800a00013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT3_PRT39" , 0x11800a0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT16" , 0x11800a0000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT17" , 0x11800a0000d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT18" , 0x11800a0000dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT19" , 0x11800a0000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT36" , 0x11800a0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT37" , 0x11800a00013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT38" , 0x11800a0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT4_PRT39" , 0x11800a0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT16" , 0x11800a0000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT17" , 0x11800a0000d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT18" , 0x11800a0000dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT19" , 0x11800a0000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT36" , 0x11800a0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT37" , 0x11800a00013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT38" , 0x11800a0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT5_PRT39" , 0x11800a0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT16" , 0x11800a0000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT17" , 0x11800a0000d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT18" , 0x11800a0000dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT19" , 0x11800a0000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT36" , 0x11800a0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT37" , 0x11800a00013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT38" , 0x11800a0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT6_PRT39" , 0x11800a0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT16" , 0x11800a0000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT17" , 0x11800a0000d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT18" , 0x11800a0000dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT19" , 0x11800a0000e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT36" , 0x11800a0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT37" , 0x11800a00013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT38" , 0x11800a0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT7_PRT39" , 0x11800a0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT16" , 0x11800a0000d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT17" , 0x11800a0000d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT18" , 0x11800a0000de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT19" , 0x11800a0000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT36" , 0x11800a0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT37" , 0x11800a00013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT38" , 0x11800a0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT8_PRT39" , 0x11800a0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT16" , 0x11800a0000d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT17" , 0x11800a0000d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT18" , 0x11800a0000de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT19" , 0x11800a0000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT36" , 0x11800a0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT37" , 0x11800a00013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT38" , 0x11800a0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT9_PRT39" , 0x11800a0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS16" , 0x11800a0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS17" , 0x11800a0001c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS18" , 0x11800a0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS19" , 0x11800a0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS36" , 0x11800a0001e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS37" , 0x11800a0001eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS38" , 0x11800a0001ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_ERRS39" , 0x11800a0001ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS16" , 0x11800a0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS17" , 0x11800a0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS18" , 0x11800a0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS19" , 0x11800a0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS36" , 0x11800a0001e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS37" , 0x11800a0001ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS38" , 0x11800a0001ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_OCTS39" , 0x11800a0001ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS16" , 0x11800a0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS17" , 0x11800a0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS18" , 0x11800a0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS19" , 0x11800a0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS36" , 0x11800a0001e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS37" , 0x11800a0001ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS38" , 0x11800a0001ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT_INB_PKTS39" , 0x11800a0001ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 802},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 803},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 804},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 805},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 807},
- {"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 808},
- {"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 809},
- {"POW_IQ_THR0" , 0x16700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
- {"POW_IQ_THR1" , 0x16700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
- {"POW_IQ_THR2" , 0x16700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
- {"POW_IQ_THR3" , 0x16700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
- {"POW_IQ_THR4" , 0x16700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
- {"POW_IQ_THR5" , 0x16700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
- {"POW_IQ_THR6" , 0x16700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
- {"POW_IQ_THR7" , 0x16700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 811},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 812},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 813},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 817},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 818},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 822},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
- {"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
- {"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 865},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 869},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 870},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 871},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 874},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 875},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 876},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 877},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 878},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 879},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 880},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 883},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 884},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 885},
- {"USBC0_DAINT" , 0x16f0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 886},
- {"USBC0_DAINTMSK" , 0x16f001000081cull, CVMX_CSR_DB_TYPE_NCB, 32, 887},
- {"USBC0_DCFG" , 0x16f0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 888},
- {"USBC0_DCTL" , 0x16f0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 889},
- {"USBC0_DIEPCTL000" , 0x16f0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 890},
- {"USBC0_DIEPCTL001" , 0x16f0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 890},
- {"USBC0_DIEPCTL002" , 0x16f0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 890},
- {"USBC0_DIEPCTL003" , 0x16f0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 890},
- {"USBC0_DIEPCTL004" , 0x16f0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 890},
- {"USBC0_DIEPINT000" , 0x16f0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 891},
- {"USBC0_DIEPINT001" , 0x16f0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 891},
- {"USBC0_DIEPINT002" , 0x16f0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 891},
- {"USBC0_DIEPINT003" , 0x16f0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 891},
- {"USBC0_DIEPINT004" , 0x16f0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 891},
- {"USBC0_DIEPMSK" , 0x16f0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 892},
- {"USBC0_DIEPTSIZ000" , 0x16f0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 893},
- {"USBC0_DIEPTSIZ001" , 0x16f0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 893},
- {"USBC0_DIEPTSIZ002" , 0x16f0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 893},
- {"USBC0_DIEPTSIZ003" , 0x16f0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 893},
- {"USBC0_DIEPTSIZ004" , 0x16f0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 893},
- {"USBC0_DOEPCTL000" , 0x16f0010000b00ull, CVMX_CSR_DB_TYPE_NCB, 32, 894},
- {"USBC0_DOEPCTL001" , 0x16f0010000b20ull, CVMX_CSR_DB_TYPE_NCB, 32, 894},
- {"USBC0_DOEPCTL002" , 0x16f0010000b40ull, CVMX_CSR_DB_TYPE_NCB, 32, 894},
- {"USBC0_DOEPCTL003" , 0x16f0010000b60ull, CVMX_CSR_DB_TYPE_NCB, 32, 894},
- {"USBC0_DOEPCTL004" , 0x16f0010000b80ull, CVMX_CSR_DB_TYPE_NCB, 32, 894},
- {"USBC0_DOEPINT000" , 0x16f0010000b08ull, CVMX_CSR_DB_TYPE_NCB, 32, 895},
- {"USBC0_DOEPINT001" , 0x16f0010000b28ull, CVMX_CSR_DB_TYPE_NCB, 32, 895},
- {"USBC0_DOEPINT002" , 0x16f0010000b48ull, CVMX_CSR_DB_TYPE_NCB, 32, 895},
- {"USBC0_DOEPINT003" , 0x16f0010000b68ull, CVMX_CSR_DB_TYPE_NCB, 32, 895},
- {"USBC0_DOEPINT004" , 0x16f0010000b88ull, CVMX_CSR_DB_TYPE_NCB, 32, 895},
- {"USBC0_DOEPMSK" , 0x16f0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 896},
- {"USBC0_DOEPTSIZ000" , 0x16f0010000b10ull, CVMX_CSR_DB_TYPE_NCB, 32, 897},
- {"USBC0_DOEPTSIZ001" , 0x16f0010000b30ull, CVMX_CSR_DB_TYPE_NCB, 32, 897},
- {"USBC0_DOEPTSIZ002" , 0x16f0010000b50ull, CVMX_CSR_DB_TYPE_NCB, 32, 897},
- {"USBC0_DOEPTSIZ003" , 0x16f0010000b70ull, CVMX_CSR_DB_TYPE_NCB, 32, 897},
- {"USBC0_DOEPTSIZ004" , 0x16f0010000b90ull, CVMX_CSR_DB_TYPE_NCB, 32, 897},
- {"USBC0_DPTXFSIZ001" , 0x16f0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 898},
- {"USBC0_DPTXFSIZ002" , 0x16f0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 898},
- {"USBC0_DPTXFSIZ003" , 0x16f001000010cull, CVMX_CSR_DB_TYPE_NCB, 32, 898},
- {"USBC0_DPTXFSIZ004" , 0x16f0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 898},
- {"USBC0_DSTS" , 0x16f0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 899},
- {"USBC0_DTKNQR1" , 0x16f0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 900},
- {"USBC0_DTKNQR2" , 0x16f0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 901},
- {"USBC0_DTKNQR3" , 0x16f0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 902},
- {"USBC0_DTKNQR4" , 0x16f0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 903},
- {"USBC0_GAHBCFG" , 0x16f0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC0_GHWCFG1" , 0x16f0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC0_GHWCFG2" , 0x16f0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 906},
- {"USBC0_GHWCFG3" , 0x16f001000004cull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC0_GHWCFG4" , 0x16f0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC0_GINTMSK" , 0x16f0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC0_GINTSTS" , 0x16f0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 910},
- {"USBC0_GNPTXFSIZ" , 0x16f0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC0_GNPTXSTS" , 0x16f001000002cull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
- {"USBC0_GOTGCTL" , 0x16f0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 913},
- {"USBC0_GOTGINT" , 0x16f0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 914},
- {"USBC0_GRSTCTL" , 0x16f0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 915},
- {"USBC0_GRXFSIZ" , 0x16f0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 916},
- {"USBC0_GRXSTSPD" , 0x16f0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 917},
- {"USBC0_GRXSTSPH" , 0x16f0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 918},
- {"USBC0_GRXSTSRD" , 0x16f001004001cull, CVMX_CSR_DB_TYPE_NCB, 32, 919},
- {"USBC0_GRXSTSRH" , 0x16f001000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 920},
- {"USBC0_GSNPSID" , 0x16f0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 921},
- {"USBC0_GUSBCFG" , 0x16f001000000cull, CVMX_CSR_DB_TYPE_NCB, 32, 922},
- {"USBC0_HAINT" , 0x16f0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 923},
- {"USBC0_HAINTMSK" , 0x16f0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 924},
- {"USBC0_HCCHAR000" , 0x16f0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
- {"USBC0_HCCHAR001" , 0x16f0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
- {"USBC0_HCCHAR002" , 0x16f0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
- {"USBC0_HCCHAR003" , 0x16f0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
- {"USBC0_HCCHAR004" , 0x16f0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
- {"USBC0_HCCHAR005" , 0x16f00100005a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
- {"USBC0_HCCHAR006" , 0x16f00100005c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
- {"USBC0_HCCHAR007" , 0x16f00100005e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
- {"USBC0_HCFG" , 0x16f0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 926},
- {"USBC0_HCINT000" , 0x16f0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
- {"USBC0_HCINT001" , 0x16f0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
- {"USBC0_HCINT002" , 0x16f0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
- {"USBC0_HCINT003" , 0x16f0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
- {"USBC0_HCINT004" , 0x16f0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
- {"USBC0_HCINT005" , 0x16f00100005a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
- {"USBC0_HCINT006" , 0x16f00100005c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
- {"USBC0_HCINT007" , 0x16f00100005e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
- {"USBC0_HCINTMSK000" , 0x16f001000050cull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
- {"USBC0_HCINTMSK001" , 0x16f001000052cull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
- {"USBC0_HCINTMSK002" , 0x16f001000054cull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
- {"USBC0_HCINTMSK003" , 0x16f001000056cull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
- {"USBC0_HCINTMSK004" , 0x16f001000058cull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
- {"USBC0_HCINTMSK005" , 0x16f00100005acull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
- {"USBC0_HCINTMSK006" , 0x16f00100005ccull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
- {"USBC0_HCINTMSK007" , 0x16f00100005ecull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
- {"USBC0_HCSPLT000" , 0x16f0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
- {"USBC0_HCSPLT001" , 0x16f0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
- {"USBC0_HCSPLT002" , 0x16f0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
- {"USBC0_HCSPLT003" , 0x16f0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
- {"USBC0_HCSPLT004" , 0x16f0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
- {"USBC0_HCSPLT005" , 0x16f00100005a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
- {"USBC0_HCSPLT006" , 0x16f00100005c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
- {"USBC0_HCSPLT007" , 0x16f00100005e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
- {"USBC0_HCTSIZ000" , 0x16f0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
- {"USBC0_HCTSIZ001" , 0x16f0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
- {"USBC0_HCTSIZ002" , 0x16f0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
- {"USBC0_HCTSIZ003" , 0x16f0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
- {"USBC0_HCTSIZ004" , 0x16f0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
- {"USBC0_HCTSIZ005" , 0x16f00100005b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
- {"USBC0_HCTSIZ006" , 0x16f00100005d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
- {"USBC0_HCTSIZ007" , 0x16f00100005f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
- {"USBC0_HFIR" , 0x16f0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 931},
- {"USBC0_HFNUM" , 0x16f0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 932},
- {"USBC0_HPRT" , 0x16f0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 933},
- {"USBC0_HPTXFSIZ" , 0x16f0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 934},
- {"USBC0_HPTXSTS" , 0x16f0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 935},
- {"USBC0_NPTXDFIFO000" , 0x16f0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
- {"USBC0_NPTXDFIFO001" , 0x16f0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
- {"USBC0_NPTXDFIFO002" , 0x16f0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
- {"USBC0_NPTXDFIFO003" , 0x16f0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
- {"USBC0_NPTXDFIFO004" , 0x16f0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
- {"USBC0_NPTXDFIFO005" , 0x16f0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
- {"USBC0_NPTXDFIFO006" , 0x16f0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
- {"USBC0_NPTXDFIFO007" , 0x16f0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
- {"USBC0_PCGCCTL" , 0x16f0010000e00ull, CVMX_CSR_DB_TYPE_NCB, 32, 937},
- {"USBN0_BIST_STATUS" , 0x11800680007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 938},
- {"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"USBN0_CTL_STATUS" , 0x16f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 940},
- {"USBN0_DMA0_INB_CHN0" , 0x16f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 941},
- {"USBN0_DMA0_INB_CHN1" , 0x16f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 942},
- {"USBN0_DMA0_INB_CHN2" , 0x16f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 943},
- {"USBN0_DMA0_INB_CHN3" , 0x16f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 944},
- {"USBN0_DMA0_INB_CHN4" , 0x16f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 945},
- {"USBN0_DMA0_INB_CHN5" , 0x16f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 946},
- {"USBN0_DMA0_INB_CHN6" , 0x16f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 947},
- {"USBN0_DMA0_INB_CHN7" , 0x16f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 948},
- {"USBN0_DMA0_OUTB_CHN0" , 0x16f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 949},
- {"USBN0_DMA0_OUTB_CHN1" , 0x16f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 950},
- {"USBN0_DMA0_OUTB_CHN2" , 0x16f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 951},
- {"USBN0_DMA0_OUTB_CHN3" , 0x16f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 952},
- {"USBN0_DMA0_OUTB_CHN4" , 0x16f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 953},
- {"USBN0_DMA0_OUTB_CHN5" , 0x16f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 954},
- {"USBN0_DMA0_OUTB_CHN6" , 0x16f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 955},
- {"USBN0_DMA0_OUTB_CHN7" , 0x16f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 956},
- {"USBN0_DMA_TEST" , 0x16f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 957},
- {"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_21" , 3, 19, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_25" , 23, 3, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 0, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 10, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_5_7" , 5, 3, 2, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 2, "RAZ", 1, 1, 0, 0},
- {"BYP_EN" , 16, 1, 2, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 2, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 3, "RAZ", 1, 1, 0, 0},
- {"EN" , 1, 1, 3, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 3, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 4, "RO", 0, 0, 0ull, 0ull},
- {"DUPLEX" , 2, 1, 4, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 4, "RO", 0, 0, 0ull, 0ull},
- {"RX_EN" , 4, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"TX_EN" , 5, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 4, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 9, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 10, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 11, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 11, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 12, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 12, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 12, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 12, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 14, "RAZ", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 14, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 7, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 15, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 16, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 16, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 17, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 17, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 18, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 18, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 19, "RAZ", 1, 1, 0, 0},
- {"MAXERR" , 2, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 19, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 19, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 19, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 20, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 21, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 22, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 27, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 27, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 32, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 32, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 33, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 33, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 33, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 33, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 34, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 35, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 35, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 36, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 36, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 1, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 37, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 1, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 37, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 1, 38, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 38, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 1, 38, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 38, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 39, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 39, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 40, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 40, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 40, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 41, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 60, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 1, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 61, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 64, "RAZ", 0, 0, 0ull, 0ull},
- {"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 65, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 65, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 65, "RAZ", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 65, "RAZ", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 65, "RAZ", 0, 0, 0ull, 0ull},
- {"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 1, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 68, "RAZ", 0, 0, 0ull, 0ull},
- {"BP" , 4, 1, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 68, "RAZ", 0, 0, 0ull, 0ull},
- {"EN" , 8, 1, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 68, "RAZ", 0, 0, 0ull, 0ull},
- {"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 4, 71, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 71, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 12, 72, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 72, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 12, 73, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 73, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 74, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 74, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 75, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 75, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 75, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 75, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 75, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 75, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 75, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 76, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 76, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 77, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 12, 78, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 78, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 12, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 79, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 12, 80, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 80, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 81, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 81, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 81, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 81, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 81, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 81, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 81, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 81, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 81, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 81, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 82, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 82, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 83, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 83, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 12, 84, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 84, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 12, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 85, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 12, 86, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 86, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 87, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 87, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 87, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 87, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 87, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 87, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 87, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 88, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 88, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 88, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 88, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 88, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 88, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 88, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 88, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY_ZERO" , 51, 1, 88, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 88, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 88, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 12, 89, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 89, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 90, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 91, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 12, 92, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 92, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 93, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 93, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 12, 94, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 94, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 95, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 96, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 11, 96, "R/W", 0, 0, 32767ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 96, "RAZ", 1, 1, 0, 0},
- {"QLM_DCOK" , 0, 4, 97, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 97, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 4, 98, "R/W", 0, 1, 0ull, 0},
- {"MUX_SEL" , 4, 2, 98, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 98, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 98, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 98, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 99, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 99, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_39" , 37, 3, 99, "RAZ", 1, 1, 0, 0},
- {"SELECT" , 40, 4, 99, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_60" , 44, 17, 99, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 99, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 99, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 99, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 100, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 101, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 102, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 102, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 103, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 103, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 104, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 104, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 105, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 105, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 105, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 105, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 105, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 105, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 105, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 106, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 106, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 106, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 106, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 106, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 106, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 107, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 107, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 107, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 107, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 107, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 107, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 107, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 108, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 108, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 108, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 109, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 109, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 110, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 110, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 110, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 111, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 111, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 112, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 113, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 114, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 114, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 115, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 115, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 116, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 116, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 116, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 117, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 117, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 117, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 118, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 118, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 119, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 119, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 120, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 120, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 120, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 120, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 120, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 120, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 120, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 121, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 121, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 122, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 122, "RAZ", 1, 1, 0, 0},
- {"LOGL_EN" , 0, 16, 123, "R/W", 0, 1, 65535ull, 0},
- {"PHYS_EN" , 16, 1, 123, "R/W", 0, 1, 1ull, 0},
- {"HG2RX_EN" , 17, 1, 123, "R/W", 0, 0, 0ull, 0ull},
- {"HG2TX_EN" , 18, 1, 123, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 123, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 124, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 124, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 124, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 2, 124, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 124, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 2, 124, "RO", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 124, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 125, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 125, "RAZ", 1, 1, 0, 0},
- {"RX_EN" , 0, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EN" , 1, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"DRP_EN" , 2, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"BCK_EN" , 3, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 126, "RAZ", 1, 1, 0, 0},
- {"PHYS_BP" , 16, 16, 126, "R/W", 0, 1, 0ull, 0},
- {"LOGL_EN" , 32, 16, 126, "R/W", 0, 0, 255ull, 255ull},
- {"PHYS_EN" , 48, 16, 126, "R/W", 0, 0, 255ull, 255ull},
- {"EN" , 0, 1, 127, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 127, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 127, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 127, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 127, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 127, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 127, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 127, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 127, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 127, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 128, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 129, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 130, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 131, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 132, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 133, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 134, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 134, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 135, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 135, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 135, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 135, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 136, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 136, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 137, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 137, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 137, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 137, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 137, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 137, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 137, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 137, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 137, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 138, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 138, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 138, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 138, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 138, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 138, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 138, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 138, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 138, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 138, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 138, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 139, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 139, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 140, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 140, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 140, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 140, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 140, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 140, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 141, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 141, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 141, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 141, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 141, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 141, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 142, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 142, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 143, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 143, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 144, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 145, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 145, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 146, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 146, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 147, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 147, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 148, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 148, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 149, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 149, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 150, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 150, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 151, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 151, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 152, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 152, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 153, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 153, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 154, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 154, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 154, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 154, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 155, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 155, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 156, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 156, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 157, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 157, "RAZ", 1, 1, 0, 0},
- {"LGTIM2GO" , 0, 16, 158, "RO", 0, 1, 0ull, 0},
- {"XOF" , 16, 16, 158, "RO", 0, 0, 0ull, 0ull},
- {"PHTIM2GO" , 32, 16, 158, "RO", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 158, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 4, 159, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 159, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 4, 159, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 159, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 160, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 160, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 161, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 161, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 161, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 161, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 161, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 162, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 162, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 163, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 163, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 164, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 164, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 164, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 165, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 165, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 165, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 165, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 165, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 166, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 166, "RAZ", 1, 1, 0, 0},
- {"XOFF" , 0, 16, 167, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
- {"XON" , 0, 16, 168, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 168, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 169, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 169, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 169, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 170, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 170, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 171, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 171, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 172, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 172, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 173, "RO", 1, 1, 0, 0},
- {"MSG_TIME" , 16, 16, 173, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 173, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 174, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 174, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 175, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 175, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 176, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 176, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 177, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 177, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 178, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 178, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 179, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 179, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 180, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 180, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 181, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 181, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 182, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 182, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 183, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 183, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 184, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 184, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 185, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 185, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 186, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 186, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 187, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 187, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 188, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 189, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 189, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 190, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 191, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 191, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 192, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 192, "RAZ", 1, 1, 0, 0},
- {"TX_XOF" , 0, 16, 193, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 193, "RAZ", 1, 1, 0, 0},
- {"TX_XON" , 0, 16, 194, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 194, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 195, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 195, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 195, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 196, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 196, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 196, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 196, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 196, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 196, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 196, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 196, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 197, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 197, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 198, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 198, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 199, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 199, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 200, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 200, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 200, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 200, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 201, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 201, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 202, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 202, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 203, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_5_63" , 5, 59, 203, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 204, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 204, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 204, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 204, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 204, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 204, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 204, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 204, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 204, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 205, "R/W", 0, 0, 6ull, 6ull},
- {"EN" , 4, 1, 205, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 205, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 206, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 206, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 206, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 206, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 207, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 207, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 208, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 208, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 209, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 209, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 210, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 210, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 211, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 211, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 212, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 213, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 213, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 213, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 213, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 213, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 213, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 214, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 214, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 214, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 215, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 215, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 215, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 216, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 216, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 216, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 217, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 217, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 217, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 217, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 217, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 218, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 218, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 218, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 218, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 218, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 219, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 220, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 221, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 222, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 223, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 224, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 224, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 224, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 225, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 225, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 226, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 226, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 226, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 226, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 226, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 227, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 227, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 227, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 227, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 227, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 228, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 229, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 230, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 230, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 231, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 231, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 232, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 232, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 232, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 233, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 233, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 234, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 234, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 235, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 235, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 236, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 236, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 237, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 237, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 40, 238, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 238, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 239, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 240, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 240, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 240, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 241, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 242, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 243, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 243, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 244, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 244, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 245, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 245, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 246, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 246, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 246, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 247, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 247, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 247, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 248, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 248, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 249, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 249, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 250, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 250, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 251, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 252, "R/W", 0, 0, 0ull, 1ull},
- {"RADDR" , 0, 3, 253, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 253, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 253, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 253, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 253, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 253, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 254, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 254, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 254, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 254, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_44_63" , 44, 20, 254, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 255, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 255, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 255, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 255, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 255, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 255, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 256, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 256, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 256, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 256, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 256, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 256, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_61_63" , 61, 3, 256, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 257, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 257, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 258, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 259, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 259, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 259, "R/W", 0, 0, 0ull, 0ull},
- {"PRT_ENB" , 0, 4, 260, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 260, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 261, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 261, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 261, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 261, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 261, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 262, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 262, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 262, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 263, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_35" , 32, 4, 263, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT2" , 36, 4, 263, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_40_63" , 40, 24, 263, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 264, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 264, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 264, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 265, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 265, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 266, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 266, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 267, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 267, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 267, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 267, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 268, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 268, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 268, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 269, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 269, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 269, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 269, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 269, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 270, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 270, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 270, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 270, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 270, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 271, "RO", 0, 0, 0ull, 0ull},
- {"STIN_MSK" , 4, 1, 271, "RO", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 271, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 13, 271, "RO", 0, 0, 0ull, 0ull},
- {"WLB_MSK" , 19, 4, 271, "RO", 0, 0, 0ull, 0ull},
- {"DTBNK" , 23, 1, 271, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 271, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 9, 272, "RO", 0, 0, 0ull, 0ull},
- {"VAB_VWCF0" , 9, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 272, "RAZ", 0, 0, 0ull, 0ull},
- {"VAB_VWCF1" , 11, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"VWDF0" , 12, 4, 272, "RO", 0, 0, 0ull, 0ull},
- {"VWDF1" , 16, 4, 272, "RO", 0, 0, 0ull, 0ull},
- {"ILC" , 20, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"PLC0" , 21, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"PLC1" , 22, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"PLC2" , 23, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 272, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"PICBST" , 2, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 273, "RO", 0, 0, 0ull, 0ull},
- {"RHDB" , 4, 4, 273, "RO", 0, 0, 0ull, 0ull},
- {"RMDB" , 8, 4, 273, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 273, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 273, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 274, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 274, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 274, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 274, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 274, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 274, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 274, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 274, "R/W", 0, 0, 0ull, 0ull},
- {"DFILL_DIS" , 14, 1, 274, "R/W", 0, 0, 0ull, 0ull},
- {"DPRES0" , 15, 1, 274, "R/W", 0, 0, 0ull, 0ull},
- {"DPRES1" , 16, 1, 274, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_BANK" , 17, 1, 274, "R/W", 0, 0, 0ull, 0ull},
- {"LBIST" , 18, 1, 274, "R/W", 0, 0, 0ull, 0ull},
- {"BSTRUN" , 19, 1, 274, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 274, "RAZ", 1, 1, 0, 0},
- {"L2T" , 0, 1, 275, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 275, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 275, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 3, 275, "R/W", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 4, 275, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 275, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 4, 275, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 275, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 276, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 276, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 276, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 276, "RAZ", 0, 0, 0ull, 0ull},
- {"PLC0RMSK" , 0, 32, 277, "R/W", 0, 0, 0ull, 0ull},
- {"PLC1RMSK" , 32, 32, 277, "R/W", 0, 0, 0ull, 0ull},
- {"PLC2RMSK" , 0, 32, 278, "R/W", 0, 0, 0ull, 0ull},
- {"ILCRMSK" , 32, 32, 278, "R/W", 0, 0, 0ull, 0ull},
- {"OOB1EN" , 0, 1, 279, "R/W", 0, 0, 0ull, 1ull},
- {"OOB2EN" , 1, 1, 279, "R/W", 0, 0, 0ull, 1ull},
- {"OOB3EN" , 2, 1, 279, "R/W", 0, 0, 0ull, 1ull},
- {"L2TSECEN" , 3, 1, 279, "R/W", 0, 0, 0ull, 1ull},
- {"L2TDEDEN" , 4, 1, 279, "R/W", 0, 0, 0ull, 1ull},
- {"L2DSECEN" , 5, 1, 279, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDEDEN" , 6, 1, 279, "R/W", 0, 0, 0ull, 1ull},
- {"LCKENA" , 7, 1, 279, "R/W", 0, 0, 0ull, 1ull},
- {"LCK2ENA" , 8, 1, 279, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 279, "RAZ", 0, 0, 0ull, 0ull},
- {"OOB1" , 0, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"OOB2" , 1, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"OOB3" , 2, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2TSEC" , 3, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2TDED" , 4, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2DSEC" , 5, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2DDED" , 6, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK" , 7, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK2" , 8, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 280, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 281, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 281, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 281, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 281, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 282, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 282, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 283, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 283, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 283, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 4, 283, "RO", 0, 0, 0ull, 0ull},
- {"SET" , 18, 3, 283, "RO", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 283, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 283, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 4, 283, "RO", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 283, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 283, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 283, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 283, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 283, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 283, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 284, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 284, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 11, 285, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 11, 16, 285, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 4, 286, "R/W", 0, 0, 15ull, 15ull},
- {"STPARTDIS" , 4, 1, 286, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"STENA" , 0, 1, 287, "R/W", 0, 0, 0ull, 0ull},
- {"DWBENA" , 1, 1, 287, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 287, "RAZ", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 288, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 288, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 288, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 288, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 288, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 288, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 289, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 289, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 289, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 289, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 289, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 289, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 290, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 290, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 290, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 290, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 290, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 290, "RO", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"PP0GRP" , 0, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP1GRP" , 2, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP2GRP" , 4, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP3GRP" , 6, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP4GRP" , 8, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP5GRP" , 10, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP6GRP" , 12, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP7GRP" , 14, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP8GRP" , 16, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP9GRP" , 18, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP10GRP" , 20, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"PP11GRP" , 22, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 293, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 8, 294, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK1" , 8, 8, 294, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK2" , 16, 8, 294, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK3" , 24, 8, 294, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 294, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK4" , 0, 8, 295, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK5" , 8, 8, 295, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK6" , 16, 8, 295, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK7" , 24, 8, 295, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 295, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK8" , 0, 8, 296, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK9" , 8, 8, 296, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK10" , 16, 8, 296, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK11" , 24, 8, 296, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 8, 297, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 297, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 298, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 298, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 298, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 299, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 299, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 300, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 300, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 301, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 301, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 302, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 302, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 302, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 302, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 302, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 302, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 302, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 11, 303, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 3, 303, "RO", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 303, "RO", 0, 0, 0ull, 0ull},
- {"FADRU" , 18, 1, 303, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 303, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 304, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 304, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 305, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 305, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 305, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 306, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 306, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 307, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 307, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 308, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 308, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 309, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_1024K" , 34, 1, 309, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_512K" , 35, 1, 309, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_36" , 36, 1, 309, "RO", 0, 0, 0ull, 0ull},
- {"EMA_CTL" , 37, 3, 309, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 309, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 310, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 310, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 310, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 310, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 310, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 310, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 10, 310, "RO", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 3, 310, "RO", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 310, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 310, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 310, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 310, "R/W", 0, 0, 0ull, 1ull},
- {"FADRU" , 28, 1, 310, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 310, "RAZ", 0, 0, 0ull, 0ull},
- {"RATE" , 0, 8, 311, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_63" , 8, 56, 311, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 7, 312, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_7_63" , 7, 57, 312, "RAZ", 1, 1, 0, 0},
- {"RATE" , 0, 16, 313, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 313, "RAZ", 1, 1, 0, 0},
- {"DBG_EN" , 0, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 314, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 315, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 315, "RAZ", 1, 1, 0, 0},
- {"POLARITY" , 0, 1, 316, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 316, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 8, 317, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 317, "RAZ", 1, 1, 0, 0},
- {"FORMAT" , 0, 4, 318, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 318, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 319, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 319, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 320, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 320, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 32, 321, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 321, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 32, 322, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 322, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 32, 323, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 323, "RAZ", 1, 1, 0, 0},
- {"START" , 0, 1, 324, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 324, "RAZ", 1, 0, 0, 0ull},
- {"MRD" , 0, 3, 325, "RO", 1, 0, 0, 0ull},
- {"MRF" , 3, 1, 325, "RO", 1, 0, 0, 0ull},
- {"MWC" , 4, 1, 325, "RO", 1, 0, 0, 0ull},
- {"MWD" , 5, 3, 325, "RO", 1, 0, 0, 0ull},
- {"MWF" , 8, 1, 325, "RO", 1, 0, 0, 0ull},
- {"CSRE2D" , 9, 1, 325, "RO", 1, 0, 0, 0ull},
- {"CSRD2E" , 10, 1, 325, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 325, "RAZ", 1, 0, 0, 0ull},
- {"PCTL_DAT" , 0, 5, 326, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_11" , 5, 7, 326, "RAZ", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 326, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 326, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_27" , 20, 8, 326, "RAZ", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 326, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 326, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 327, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 327, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 327, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 327, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 327, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 327, "R/W", 0, 0, 0ull, 1ull},
- {"MODE32B" , 10, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 11, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MRF" , 12, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 327, "RAZ", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 327, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_17" , 16, 2, 327, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 327, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 327, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 327, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 327, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 327, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 328, "RAZ", 0, 1, 0ull, 0},
- {"DCC_ENABLE" , 8, 1, 328, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_MODE" , 9, 1, 328, "R/W", 0, 0, 0ull, 1ull},
- {"SEQUENCE" , 10, 3, 328, "R/W", 0, 0, 0ull, 0ull},
- {"IDLEPOWER" , 13, 3, 328, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 16, 4, 328, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 20, 1, 328, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_63" , 21, 43, 328, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 329, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 329, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 330, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 330, "RAZ", 1, 1, 0, 0},
- {"DCLK90_VLU" , 0, 5, 331, "R/W", 0, 1, 0ull, 0},
- {"DCLK90_LD" , 5, 1, 331, "R/W", 0, 1, 0ull, 0},
- {"DCLK90_BYP" , 6, 1, 331, "R/W", 0, 1, 0ull, 0},
- {"OFF90_ENA" , 7, 1, 331, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 331, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 332, "R/W", 0, 0, 1ull, 1ull},
- {"RDQS" , 1, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 332, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 332, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 332, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 332, "R/W", 0, 0, 0ull, 0ull},
- {"SILO_HC" , 21, 1, 332, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 332, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 332, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 332, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 332, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 332, "RAZ", 0, 0, 0ull, 0ull},
- {"CLK" , 0, 4, 333, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 333, "RAZ", 0, 0, 0ull, 0ull},
- {"CMD" , 5, 4, 333, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 333, "RAZ", 0, 0, 0ull, 0ull},
- {"DQ" , 10, 4, 333, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 333, "RAZ", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 0, 5, 334, "R/W", 0, 1, 0ull, 0},
- {"DLL90_ENA" , 5, 1, 334, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 6, 1, 334, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 7, 1, 334, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 334, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 335, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 335, "RAZ", 0, 1, 0ull, 0},
- {"ROW_LSB" , 16, 3, 335, "R/W", 0, 1, 3ull, 0},
- {"BANK8" , 19, 1, 335, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 335, "RAZ", 0, 1, 0ull, 0},
- {"MRDSYN0" , 0, 8, 336, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 336, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 336, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 336, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 336, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 337, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 337, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 337, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 337, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 337, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 337, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 338, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 338, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 339, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 339, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 340, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 340, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 340, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 340, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 340, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 340, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 340, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 340, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 340, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 340, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 341, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 341, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 341, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 341, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 341, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 341, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 341, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 341, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_31_63" , 31, 33, 341, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 342, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 342, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 343, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 343, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 344, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 344, "RAZ", 1, 1, 0, 0},
- {"EN2" , 0, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"EN4" , 1, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"EN6" , 2, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"EN8" , 3, 1, 345, "R/W", 0, 1, 1ull, 0},
- {"EN12" , 4, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"EN16" , 5, 1, 345, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 345, "RAZ", 0, 1, 0ull, 0},
- {"CLKR" , 8, 6, 345, "R/W", 0, 1, 0ull, 0},
- {"CLKF" , 14, 12, 345, "R/W", 0, 1, 31ull, 0},
- {"RESET_N" , 26, 1, 345, "R/W", 0, 0, 0ull, 1ull},
- {"DIV_RESET" , 27, 1, 345, "R/W", 0, 0, 1ull, 0ull},
- {"FASTEN_N" , 28, 1, 345, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_29_63" , 29, 35, 345, "RAZ", 0, 1, 0ull, 0},
- {"FBSLIP" , 0, 1, 346, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 346, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_21" , 2, 20, 346, "RAZ", 1, 1, 0, 0},
- {"DDR__PCTL" , 22, 5, 346, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 27, 5, 346, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 346, "RAZ", 1, 1, 0, 0},
- {"BNK" , 0, 3, 347, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 347, "RAZ", 0, 0, 0ull, 0ull},
- {"COL" , 4, 12, 347, "R/W", 0, 0, 0ull, 0ull},
- {"ROW" , 16, 16, 347, "R/W", 0, 0, 0ull, 0ull},
- {"PATTERN" , 32, 8, 347, "R/W", 0, 0, 170ull, 170ull},
- {"RANKMASK" , 40, 4, 347, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_63" , 44, 20, 347, "RAZ", 0, 0, 0ull, 0ull},
- {"BYTE" , 0, 4, 348, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 348, "RAZ", 0, 0, 0ull, 0ull},
- {"BITMASK" , 16, 16, 348, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 348, "RAZ", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 4, 349, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 4, 4, 349, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 8, 4, 349, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 12, 4, 349, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 16, 4, 349, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 20, 4, 349, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 24, 4, 349, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 28, 4, 349, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 32, 4, 349, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 36, 2, 349, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 349, "RAZ", 1, 0, 0, 0ull},
- {"PCTL" , 0, 5, 350, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 350, "RAZ", 0, 1, 0ull, 0},
- {"NCTL" , 8, 4, 350, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 350, "RAZ", 0, 1, 0ull, 0},
- {"ENABLE" , 16, 1, 350, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 350, "RAZ", 0, 1, 0ull, 0},
- {"RODT_LO0" , 0, 4, 351, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO1" , 4, 4, 351, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO2" , 8, 4, 351, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO3" , 12, 4, 351, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI0" , 16, 4, 351, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI1" , 20, 4, 351, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI2" , 24, 4, 351, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI3" , 28, 4, 351, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 351, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 352, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D0_R1" , 8, 8, 352, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R0" , 16, 8, 352, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R1" , 24, 8, 352, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 352, "RAZ", 0, 0, 0ull, 0ull},
- {"WODT_D2_R0" , 0, 8, 353, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R1" , 8, 8, 353, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R0" , 16, 8, 353, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R1" , 24, 8, 353, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 353, "RAZ", 0, 0, 0ull, 0ull},
- {"NCBI" , 0, 1, 354, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 354, "RO", 0, 0, 0ull, 0ull},
- {"DMA" , 2, 1, 354, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 3, 1, 354, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 354, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 355, "R/W", 1, 1, 0, 0},
- {"PCTL" , 5, 5, 355, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 355, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 356, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 356, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 356, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 357, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 357, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 357, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 358, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 358, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 358, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 359, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 359, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 359, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 359, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 359, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 359, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 359, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 359, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 359, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 359, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 359, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 360, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 360, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 360, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 361, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 361, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 362, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 362, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 362, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 363, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 363, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 363, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 363, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 363, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 364, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_8" , 0, 9, 365, "RAZ", 1, 1, 0, 0},
- {"TERM" , 9, 2, 365, "RO", 1, 1, 0, 0},
- {"DMACK_P0" , 11, 1, 365, "RO", 1, 1, 0, 0},
- {"DMACK_P1" , 12, 1, 365, "RO", 1, 1, 0, 0},
- {"DMACK_P2" , 13, 1, 365, "RO", 1, 1, 0, 0},
- {"WIDTH" , 14, 1, 365, "RO", 1, 1, 0, 0},
- {"ALE" , 15, 1, 365, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 365, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 16, 366, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 366, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 366, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 366, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 366, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 366, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 366, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 366, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 367, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 367, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 367, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 367, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 367, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 367, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 367, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 367, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 367, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 367, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 367, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 367, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 368, "R/W", 0, 0, 26ull, 26ull},
- {"RESERVED_6_7" , 6, 2, 368, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 368, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 368, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 368, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 368, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 369, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 370, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 370, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 371, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 371, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 12, 372, "RO", 1, 1, 0, 0},
- {"RESERVED_12_15" , 12, 4, 372, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 372, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 372, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 372, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 372, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 372, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 372, "RO", 1, 1, 0, 0},
- {"NOKASU" , 29, 1, 372, "RO", 1, 1, 0, 0},
- {"RESERVED_30_31" , 30, 2, 372, "RAZ", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 372, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 372, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 372, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 373, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 373, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 373, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 373, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 373, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 373, "RO", 1, 1, 0, 0},
- {"ZIP_CRIP" , 29, 2, 373, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 373, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 374, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_3_3" , 3, 1, 374, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 374, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_63" , 7, 57, 374, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 375, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 376, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 376, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 376, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 377, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 377, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 8, 378, "R/W", 0, 1, 3ull, 0},
- {"SCLK_HI" , 8, 12, 378, "R/W", 0, 1, 100ull, 0},
- {"SCLK_LO" , 20, 4, 378, "R/W", 0, 1, 2ull, 0},
- {"OUT" , 24, 8, 378, "R/W", 0, 1, 3ull, 0},
- {"PROG_PIN" , 32, 1, 378, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 378, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 379, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 379, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 379, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 379, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 379, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 379, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 380, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 14, 14, 380, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 28, 14, 380, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 380, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 381, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 381, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 3, 382, "R/W", 1, 1, 0, 0},
- {"RESERVED_3_63" , 3, 61, 382, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 383, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 383, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 383, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 383, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 383, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 383, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 383, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 383, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 383, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 383, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 383, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 383, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 383, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 384, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 384, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 384, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 384, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 384, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 384, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 384, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 384, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 385, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 385, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 385, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 386, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 386, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 386, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 387, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 387, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 388, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 388, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 389, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 389, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 390, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 390, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 390, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 390, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 390, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 390, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 390, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 391, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 392, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 392, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 392, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 392, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 392, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 392, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 392, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 393, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 393, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 393, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 393, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 394, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 394, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 394, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 394, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 394, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 394, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 394, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 394, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 395, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 395, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 395, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 395, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 395, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 395, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 395, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 395, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 395, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 396, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 396, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 396, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 396, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 396, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 396, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 396, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 397, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 397, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 397, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 397, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 397, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 397, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 397, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 397, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 397, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 398, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 398, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 399, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 399, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 400, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 400, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 400, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 400, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 401, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 402, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 402, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 403, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 403, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 404, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 404, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 404, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 404, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 405, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 405, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 406, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 406, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 407, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 407, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 408, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 408, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 409, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 409, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 410, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 410, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 411, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 411, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 411, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 411, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 411, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 411, "RAZ", 1, 1, 0, 0},
- {"ORFDAT" , 0, 1, 412, "RO", 0, 0, 0ull, 0ull},
- {"IRFDAT" , 1, 1, 412, "RO", 0, 0, 0ull, 0ull},
- {"IPFDAT" , 2, 1, 412, "RO", 0, 0, 0ull, 0ull},
- {"MRQDAT" , 3, 1, 412, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 412, "RAZ", 0, 0, 0ull, 0ull},
- {"MRQ_HWM" , 0, 2, 413, "R/W", 0, 0, 0ull, 1ull},
- {"NBTARB" , 2, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"LENDIAN" , 3, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 4, 1, 413, "RAZ", 0, 0, 0ull, 0ull},
- {"EN" , 5, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 6, 1, 413, "RO", 0, 0, 0ull, 0ull},
- {"CRC_STRIP" , 7, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 413, "RAZ", 1, 1, 0, 0},
- {"OVFENA" , 0, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IVFENA" , 1, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"OTHENA" , 2, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"ITHENA" , 3, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_DRPENA" , 4, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IRUNENA" , 5, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"ORUNENA" , 6, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 414, "RAZ", 1, 1, 0, 0},
- {"IRCNT" , 0, 20, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 415, "RAZ", 1, 1, 0, 0},
- {"IRHWM" , 0, 20, 416, "R/W", 0, 0, 0ull, 0ull},
- {"IBPLWM" , 20, 20, 416, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 416, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 417, "RAZ", 1, 1, 0, 0},
- {"IBASE" , 3, 33, 417, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 417, "RAZ", 1, 1, 0, 0},
- {"ISIZE" , 40, 20, 417, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 417, "RAZ", 1, 1, 0, 0},
- {"IDBELL" , 0, 20, 418, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 418, "RAZ", 1, 1, 0, 0},
- {"ITLPTR" , 32, 20, 418, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 418, "RAZ", 1, 1, 0, 0},
- {"ODBLOVF" , 0, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
- {"IDBLOVF" , 1, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORTHRESH" , 2, 1, 419, "RO", 0, 0, 0ull, 0ull},
- {"IRTHRESH" , 3, 1, 419, "RO", 0, 0, 0ull, 0ull},
- {"DATA_DRP" , 4, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
- {"IRUN" , 5, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORUN" , 6, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 419, "RAZ", 1, 1, 0, 0},
- {"ORCNT" , 0, 20, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 420, "RAZ", 1, 1, 0, 0},
- {"ORHWM" , 0, 20, 421, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 421, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 422, "RAZ", 1, 1, 0, 0},
- {"OBASE" , 3, 33, 422, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 422, "RAZ", 1, 1, 0, 0},
- {"OSIZE" , 40, 20, 422, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 422, "RAZ", 1, 1, 0, 0},
- {"ODBELL" , 0, 20, 423, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 423, "RAZ", 1, 1, 0, 0},
- {"OTLPTR" , 32, 20, 423, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 423, "RAZ", 1, 1, 0, 0},
- {"OREMCNT" , 0, 20, 424, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 424, "RAZ", 1, 1, 0, 0},
- {"IREMCNT" , 32, 20, 424, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_52_63" , 52, 12, 424, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 425, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 425, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 425, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 425, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 425, "RAZ", 1, 1, 0, 0},
- {"NCB_CMD" , 0, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"DIF4" , 2, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"DIF3" , 3, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"DIF2" , 4, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"DIF1" , 5, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"DIF0" , 6, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"CSM1" , 7, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"CSM0" , 8, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P1" , 9, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_CO" , 19, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_NO" , 20, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_PO" , 21, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_CO" , 22, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_NO" , 23, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_PO" , 24, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P1" , 25, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_O" , 27, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_C" , 28, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_O" , 29, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"D4_PST" , 31, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"D3_PST" , 32, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"D2_PST" , 33, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"D1_PST" , 34, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"D0_PST" , 35, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_39" , 36, 4, 426, "RAZ", 1, 1, 0, 0},
- {"DS_MEM" , 40, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"D4_MEM" , 41, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"D3_MEM" , 42, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"D2_MEM" , 43, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"D1_MEM" , 44, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"D0_MEM" , 45, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PKT_POP1" , 46, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PKT_POP0" , 47, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_48_49" , 48, 2, 426, "RAZ", 1, 1, 0, 0},
- {"PKT_POF" , 50, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PFM" , 51, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PKT_IMEM" , 52, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_SL" , 53, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_ID" , 54, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_CNT" , 55, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_IM" , 56, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_INT" , 57, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PIF" , 58, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PCR_GIM" , 59, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_60_62" , 60, 3, 426, "RAZ", 1, 1, 0, 0},
- {"PKT_RDF" , 63, 1, 426, "RO", 0, 0, 0ull, 0ull},
- {"PKT_BLK" , 0, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"PKT_GL" , 1, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"PKT_GD" , 2, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"PSC_P1" , 3, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"PSC_P0" , 4, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"PKT_RD" , 5, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"NWE_WR1" , 6, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"NWE_WR0" , 7, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"NWE_ST" , 8, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"NRD_ST" , 9, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"PRD_ERR" , 10, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"PRD_ST1" , 11, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"PRD_ST0" , 12, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"PRD_TAG" , 13, 1, 427, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 427, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 428, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_CAX" , 1, 1, 428, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 2, 2, 428, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 4, 1, 428, "R/W", 0, 0, 0ull, 1ull},
- {"PTLP_RO" , 5, 1, 428, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 428, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 428, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 428, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 428, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 428, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 428, "R/W", 0, 0, 3ull, 3ull},
- {"INTA" , 16, 1, 428, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 17, 1, 428, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 18, 1, 428, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 19, 1, 428, "RO", 0, 0, 1ull, 1ull},
- {"WAITL_COM" , 20, 1, 428, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_63" , 21, 43, 428, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_CAX" , 1, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 2, 2, 429, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 4, 1, 429, "R/W", 0, 0, 0ull, 1ull},
- {"PTLP_RO" , 5, 1, 429, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 429, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 429, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 429, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 429, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 429, "R/W", 0, 0, 3ull, 3ull},
- {"INTA" , 16, 1, 429, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 17, 1, 429, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 18, 1, 429, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 19, 1, 429, "RO", 0, 0, 1ull, 1ull},
- {"WAITL_COM" , 20, 1, 429, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_63" , 21, 43, 429, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 430, "RO", 1, 1, 0, 0},
- {"HOST_MODE" , 8, 1, 430, "RO", 1, 1, 0, 0},
- {"PKT_BP" , 9, 4, 430, "R/W", 0, 0, 15ull, 15ull},
- {"ARB" , 13, 1, 430, "R/W", 0, 0, 0ull, 1ull},
- {"LNK_RST" , 14, 1, 430, "R/W1C", 0, 0, 0ull, 0ull},
- {"RING_EN" , 15, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"CFG_RTRY" , 16, 16, 430, "R/W", 0, 0, 0ull, 32ull},
- {"P0_NTAGS" , 32, 6, 430, "R/W", 0, 0, 32ull, 32ull},
- {"P1_NTAGS" , 38, 6, 430, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_44_63" , 44, 20, 430, "RAZ", 1, 1, 0, 0},
- {"C0_B0_D" , 0, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"C0_WI_D" , 1, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"C1_B0_D" , 2, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"C1_WI_D" , 3, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"C0_B1_S" , 4, 3, 431, "R/W", 0, 0, 1ull, 1ull},
- {"C1_B1_S" , 7, 3, 431, "R/W", 0, 0, 1ull, 1ull},
- {"C0_W_FLT" , 10, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"C1_W_FLT" , 11, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"MRRS" , 12, 3, 431, "R/W", 0, 0, 2ull, 2ull},
- {"MPS" , 15, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 431, "RAZ", 1, 1, 0, 0},
- {"P0_FCNT" , 0, 6, 432, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 432, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 432, "RO", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 432, "RO", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 432, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 433, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 433, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 433, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 23, 2, 433, "RO", 1, 1, 0, 0},
- {"QLM3_SPD" , 25, 2, 433, "RO", 1, 1, 0, 0},
- {"QLM0_REV_LANES" , 27, 1, 433, "RO", 1, 1, 0, 0},
- {"QLM2_REV_LANES" , 28, 1, 433, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 433, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 434, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 434, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 435, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 435, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 435, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 436, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 436, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 437, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 29, 437, "R/W", 0, 1, 0ull, 0},
- {"IDLE" , 36, 1, 437, "RO", 0, 1, 1ull, 0},
- {"RESERVED_37_63" , 37, 27, 437, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 438, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 438, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 439, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 439, "R/W", 0, 1, 0ull, 0},
- {"CNT" , 0, 32, 440, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 440, "R/W", 0, 1, 0ull, 0},
- {"DMA0" , 0, 32, 441, "R/W", 0, 1, 0ull, 0},
- {"DMA1" , 32, 32, 441, "R/W", 0, 1, 0ull, 0},
- {"CSIZE" , 0, 14, 442, "R/W", 0, 1, 0ull, 0},
- {"O_MODE" , 14, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 442, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 442, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 442, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 442, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 442, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"DMA0_ENB" , 34, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1_ENB" , 35, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2_ENB" , 36, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3_ENB" , 37, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"DMA4_ENB" , 38, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"P_32B_M" , 39, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 442, "RAZ", 1, 1, 0, 0},
- {"DMA_CNT" , 0, 5, 443, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_5_7" , 5, 3, 443, "RAZ", 1, 1, 0, 0},
- {"DMA0_CNT" , 8, 5, 443, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 443, "RAZ", 1, 1, 0, 0},
- {"DMA1_CNT" , 16, 5, 443, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_21_23" , 21, 3, 443, "RAZ", 1, 1, 0, 0},
- {"DMA2_CNT" , 24, 5, 443, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_29_31" , 29, 3, 443, "RAZ", 1, 1, 0, 0},
- {"DMA3_CNT" , 32, 5, 443, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_37_39" , 37, 3, 443, "RAZ", 1, 1, 0, 0},
- {"DMA4_CNT" , 40, 5, 443, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_45_47" , 45, 3, 443, "RAZ", 1, 1, 0, 0},
- {"PKT_CNT" , 48, 5, 443, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_53_62" , 53, 10, 443, "RAZ", 1, 1, 0, 0},
- {"DMA_ARB" , 63, 1, 443, "R/W", 0, 1, 1ull, 0},
- {"DMA0_CPL" , 0, 1, 444, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1_CPL" , 1, 1, 444, "R/W", 0, 0, 0ull, 1ull},
- {"PINS_ERR" , 2, 1, 444, "R/W", 0, 0, 0ull, 1ull},
- {"POP_ERR" , 3, 1, 444, "R/W", 0, 0, 0ull, 1ull},
- {"PDI_ERR" , 4, 1, 444, "R/W", 0, 0, 0ull, 1ull},
- {"PGL_ERR" , 5, 1, 444, "R/W", 0, 0, 0ull, 1ull},
- {"P0_RDLK" , 6, 1, 444, "R/W", 0, 0, 0ull, 1ull},
- {"P1_RDLK" , 7, 1, 444, "R/W", 0, 0, 0ull, 1ull},
- {"PIN_BP" , 8, 1, 444, "R/W", 0, 0, 0ull, 1ull},
- {"POUT_ERR" , 9, 1, 444, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 444, "RAZ", 0, 1, 0ull, 0},
- {"DMA0_CPL" , 0, 1, 445, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1_CPL" , 1, 1, 445, "R/W", 0, 0, 0ull, 1ull},
- {"PINS_ERR" , 2, 1, 445, "R/W", 0, 0, 0ull, 1ull},
- {"POP_ERR" , 3, 1, 445, "R/W", 0, 0, 0ull, 1ull},
- {"PDI_ERR" , 4, 1, 445, "R/W", 0, 0, 0ull, 1ull},
- {"PGL_ERR" , 5, 1, 445, "R/W", 0, 0, 0ull, 1ull},
- {"P0_RDLK" , 6, 1, 445, "R/W", 0, 0, 0ull, 1ull},
- {"P1_RDLK" , 7, 1, 445, "R/W", 0, 0, 0ull, 1ull},
- {"PIN_BP" , 8, 1, 445, "R/W", 0, 0, 0ull, 1ull},
- {"POUT_ERR" , 9, 1, 445, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 445, "RAZ", 0, 1, 0ull, 0},
- {"DMA0_CPL" , 0, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_CPL" , 1, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 2, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 3, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 4, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 5, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_RDLK" , 6, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_RDLK" , 7, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 8, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 9, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 446, "RAZ", 0, 0, 0ull, 0ull},
- {"RML_RTO" , 0, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0DBO" , 4, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1DBO" , 5, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2DBO" , 6, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3DBO" , 7, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DMA4DBO" , 8, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0FI" , 9, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1FI" , 10, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT0" , 11, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT1" , 12, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME0" , 13, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME1" , 14, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"PSLDBOF" , 15, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"PIDBOF" , 16, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 17, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 18, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_AERI" , 19, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_ER" , 20, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_SE" , 21, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_DR" , 22, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_WAKE" , 23, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_PMEI" , 24, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_HPINT" , 25, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_AERI" , 26, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_ER" , 27, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_SE" , 28, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_DR" , 29, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_WAKE" , 30, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_PMEI" , 31, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_HPINT" , 32, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B0" , 33, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B1" , 34, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B2" , 35, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WI" , 36, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_BX" , 37, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B0" , 38, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B1" , 39, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B2" , 40, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WI" , 41, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_BX" , 42, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B0" , 43, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B1" , 44, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B2" , 45, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WI" , 46, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_BX" , 47, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B0" , 48, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B1" , 49, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B2" , 50, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WI" , 51, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_BX" , 52, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WF" , 53, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WF" , 54, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WF" , 55, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WF" , 56, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_EXC" , 57, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_EXC" , 58, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C0_LDWN" , 59, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"C1_LDWN" , 60, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"INT_A" , 61, 1, 447, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_62_62" , 62, 1, 447, "RAZ", 0, 1, 0ull, 0},
- {"MIO_INTA" , 63, 1, 447, "R/W", 0, 0, 0ull, 1ull},
- {"RML_RTO" , 0, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0DBO" , 4, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1DBO" , 5, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2DBO" , 6, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3DBO" , 7, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DMA4DBO" , 8, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0FI" , 9, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1FI" , 10, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT0" , 11, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT1" , 12, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME0" , 13, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME1" , 14, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"PSLDBOF" , 15, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"PIDBOF" , 16, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 17, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 18, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_AERI" , 19, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_ER" , 20, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_SE" , 21, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_DR" , 22, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_WAKE" , 23, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_PMEI" , 24, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_HPINT" , 25, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_AERI" , 26, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_ER" , 27, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_SE" , 28, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_DR" , 29, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_WAKE" , 30, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_PMEI" , 31, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_HPINT" , 32, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B0" , 33, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B1" , 34, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B2" , 35, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WI" , 36, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_BX" , 37, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B0" , 38, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B1" , 39, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B2" , 40, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WI" , 41, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_BX" , 42, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B0" , 43, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B1" , 44, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B2" , 45, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WI" , 46, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_BX" , 47, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B0" , 48, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B1" , 49, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B2" , 50, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WI" , 51, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_BX" , 52, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WF" , 53, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WF" , 54, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WF" , 55, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WF" , 56, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_EXC" , 57, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_EXC" , 58, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C0_LDWN" , 59, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"C1_LDWN" , 60, 1, 448, "R/W", 0, 0, 0ull, 1ull},
- {"INT_A" , 61, 1, 448, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_62_63" , 62, 2, 448, "RAZ", 0, 1, 0ull, 0},
- {"PSLDBOF" , 0, 6, 449, "RO", 0, 1, 0ull, 0},
- {"PIDBOF" , 6, 6, 449, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 449, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0DBO" , 4, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1DBO" , 5, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA2DBO" , 6, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA3DBO" , 7, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA4DBO" , 8, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0FI" , 9, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1FI" , 10, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 11, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 12, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 13, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 14, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 15, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 16, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT" , 17, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"PTIME" , 18, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"C0_AERI" , 19, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"CRS0_ER" , 20, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_SE" , 21, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS0_DR" , 22, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_WAKE" , 23, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_PMEI" , 24, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"C0_HPINT" , 25, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"C1_AERI" , 26, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"CRS1_ER" , 27, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_SE" , 28, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS1_DR" , 29, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_WAKE" , 30, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_PMEI" , 31, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"C1_HPINT" , 32, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B0" , 33, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_B1" , 34, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_B2" , 35, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_WI" , 36, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_BX" , 37, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B0" , 38, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B1" , 39, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B2" , 40, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_WI" , 41, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_BX" , 42, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B0" , 43, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B1" , 44, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B2" , 45, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_WI" , 46, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_BX" , 47, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B0" , 48, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B1" , 49, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B2" , 50, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_WI" , 51, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_BX" , 52, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_WF" , 53, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_WF" , 54, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_WF" , 55, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_WF" , 56, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_EXC" , 57, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"C1_EXC" , 58, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"C0_LDWN" , 59, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_LDWN" , 60, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"INT_A" , 61, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 450, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO_INTA" , 63, 1, 450, "RO", 0, 0, 0ull, 0ull},
- {"RML_RTO" , 0, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"DMA0DBO" , 4, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"DMA1DBO" , 5, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"DMA2DBO" , 6, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"DMA3DBO" , 7, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 451, "RO", 1, 1, 0, 0},
- {"DMA0FI" , 9, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"DMA1FI" , 10, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"DCNT0" , 11, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"DCNT1" , 12, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"DTIME0" , 13, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"DTIME1" , 14, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_18" , 15, 4, 451, "RAZ", 0, 0, 0ull, 0ull},
- {"C0_AERI" , 19, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"CRS0_ER" , 20, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_SE" , 21, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"CRS0_DR" , 22, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_WAKE" , 23, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_PMEI" , 24, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_HPINT" , 25, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_AERI" , 26, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"CRS1_ER" , 27, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_SE" , 28, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"CRS1_DR" , 29, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_WAKE" , 30, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_PMEI" , 31, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_HPINT" , 32, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B0" , 33, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B1" , 34, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B2" , 35, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_WI" , 36, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_BX" , 37, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_B0" , 38, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_B1" , 39, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_B2" , 40, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_WI" , 41, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_BX" , 42, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_B0" , 43, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_B1" , 44, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_B2" , 45, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_WI" , 46, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_BX" , 47, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_B0" , 48, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_B1" , 49, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_B2" , 50, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_WI" , 51, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_BX" , 52, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_WF" , 53, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_WF" , 54, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_WF" , 55, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_WF" , 56, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_EXC" , 57, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_EXC" , 58, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C0_LDWN" , 59, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"C1_LDWN" , 60, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"INT_A" , 61, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 451, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO_INTA" , 63, 1, 451, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 452, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 453, "RO", 0, 1, 0ull, 0},
- {"TIMER" , 0, 10, 454, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 454, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 30, 455, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 30, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 31, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 32, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 33, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 455, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 455, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 455, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 2, 455, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 41, 1, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 455, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 456, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 457, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 458, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 459, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 460, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 462, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 463, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 464, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 464, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 464, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 64, 465, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 466, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 467, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 468, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 469, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 470, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 471, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 472, "R/W", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 473, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 473, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 473, "RAZ", 1, 1, 0, 0},
- {"P0_PCNT" , 0, 8, 474, "R/W", 0, 0, 128ull, 128ull},
- {"P0_NCNT" , 8, 8, 474, "R/W", 0, 0, 16ull, 16ull},
- {"P0_CCNT" , 16, 8, 474, "R/W", 0, 0, 128ull, 128ull},
- {"P1_PCNT" , 24, 8, 474, "R/W", 0, 0, 128ull, 128ull},
- {"P1_NCNT" , 32, 8, 474, "R/W", 0, 0, 16ull, 16ull},
- {"P1_CCNT" , 40, 8, 474, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_48_63" , 48, 16, 474, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 475, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 475, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 476, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 476, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 476, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 477, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 477, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 477, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 478, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 478, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 478, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 479, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 32, 22, 479, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 479, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 480, "R/W", 0, 0, 0ull, 0ull},
- {"WMARK" , 32, 32, 480, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_0_2" , 0, 3, 481, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 481, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 482, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 482, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 483, "R/W", 0, 1, 0ull, 0},
- {"FCNT" , 32, 5, 483, "RO", 0, 1, 0ull, 0},
- {"WRP" , 37, 9, 483, "RO", 0, 1, 0ull, 0},
- {"RRP" , 46, 9, 483, "RO", 0, 1, 0ull, 0},
- {"MAX" , 55, 9, 483, "RO", 0, 1, 16ull, 0},
- {"RESERVED_0_5" , 0, 6, 484, "RAZ", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 484, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_13" , 13, 1, 484, "RAZ", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 484, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_20" , 16, 5, 484, "RAZ", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_27" , 22, 6, 484, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 484, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_35" , 35, 1, 484, "RAZ", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 484, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_42" , 38, 5, 484, "RAZ", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 484, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 485, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 4, 60, 485, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 486, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 486, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 487, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 487, "RAZ", 0, 1, 0ull, 0},
- {"PORT" , 0, 32, 488, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 488, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 489, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 489, "RAZ", 1, 1, 0, 0},
- {"ES" , 0, 64, 490, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 491, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 491, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 492, "RAZ", 1, 1, 0, 0},
- {"DPTR" , 0, 32, 493, "R/W", 0, 0, 0ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 493, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 32, 494, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 494, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 495, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 495, "RAZ", 0, 1, 0ull, 0},
- {"RD_CNT" , 0, 32, 496, "RO", 0, 1, 0ull, 0},
- {"WR_CNT" , 32, 32, 496, "RO", 0, 1, 0ull, 0},
- {"PP" , 0, 64, 497, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 0, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 498, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 498, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 498, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 498, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 22, 1, 498, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_23_63" , 23, 41, 498, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 499, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 499, "RAZ", 1, 1, 0, 0},
- {"RDSIZE" , 0, 64, 500, "R/W", 0, 1, 0ull, 0},
- {"IS_64B" , 0, 32, 501, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 501, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 502, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 22, 502, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_63" , 54, 10, 502, "RAZ", 1, 1, 0, 0},
- {"IPTR" , 0, 32, 503, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 503, "RAZ", 1, 1, 0, 0},
- {"BMODE" , 0, 32, 504, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 504, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 505, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 505, "RAZ", 1, 1, 0, 0},
- {"WMARK" , 0, 32, 506, "R/W", 0, 0, 0ull, 14ull},
- {"RESERVED_32_63" , 32, 32, 506, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 64, 507, "R/W", 0, 1, 0ull, 0},
- {"OUT_RST" , 0, 32, 508, "RO", 0, 1, 0ull, 0},
- {"IN_RST" , 32, 32, 508, "RO", 0, 1, 0ull, 0},
- {"ES" , 0, 64, 509, "R/W", 0, 1, 0ull, 0},
- {"BSIZE" , 0, 16, 510, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 16, 7, 510, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 510, "RAZ", 1, 1, 0, 0},
- {"NSR" , 0, 32, 511, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 511, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 512, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 512, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 513, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 513, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 514, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 514, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"NPEI" , 3, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 14, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"USB1" , 15, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 17, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"ASXPCS0" , 22, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"ASXPCS1" , 23, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_27" , 24, 4, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"AGL" , 28, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"LMC1" , 29, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 515, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 516, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 517, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 517, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 517, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 517, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 518, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 518, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 518, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 518, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 518, "RO", 0, 1, 1ull, 0},
- {"NPEI" , 47, 1, 518, "RO", 0, 1, 1ull, 0},
- {"RESERVED_48_63" , 48, 16, 518, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 519, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 519, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 519, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 519, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 519, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 520, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 520, "RAZ", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 520, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_51_63" , 51, 13, 520, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 521, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_1" , 0, 2, 522, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 2, 46, 522, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 522, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 522, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 523, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 524, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 524, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 525, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 525, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 526, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 526, "RO/WRSL", 0, 0, 80ull, 80ull},
- {"ISAE" , 0, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 527, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 527, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 527, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 527, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 528, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 528, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 528, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 528, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 529, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 529, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 529, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 529, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 529, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 530, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 530, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 530, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 530, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 530, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 531, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 531, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 532, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 533, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 534, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 534, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 534, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 534, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 534, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 535, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 535, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 536, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 537, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 538, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 538, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 538, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 538, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 539, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 539, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_6" , 0, 7, 540, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 7, 25, 540, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 541, "WORSL", 0, 0, 127ull, 127ull},
- {"CISP" , 0, 32, 542, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 543, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 543, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 544, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 544, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 545, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 545, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"CP" , 0, 8, 546, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 546, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 547, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 547, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 547, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 547, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 548, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 548, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 548, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 548, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 548, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 548, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 548, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 548, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 548, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 549, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 549, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 549, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 549, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 549, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 549, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 549, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 549, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 549, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 549, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 549, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 549, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 550, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 550, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 550, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 550, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 550, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 550, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 551, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 551, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 552, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 553, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 553, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 554, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 554, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 554, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 554, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 554, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 554, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 554, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 555, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 555, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 555, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 555, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 555, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 555, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 555, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 555, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 555, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 555, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 555, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 556, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 556, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 556, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 556, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 556, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 556, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 556, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 556, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 556, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 556, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 556, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 556, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 557, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MLW" , 4, 6, 557, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"ASLPMS" , 10, 2, 557, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 557, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 557, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 557, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 557, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 557, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 557, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 557, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 557, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 558, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 558, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 558, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 558, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 558, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 558, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 558, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 558, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 558, "RO", 0, 0, 0ull, 8ull},
- {"RESERVED_26_26" , 26, 1, 558, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 558, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 558, "RAZ", 1, 1, 0, 0},
- {"ABP" , 0, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 560, "R/W", 0, 0, 0ull, 0ull},
- {"PIC" , 8, 2, 560, "R/W", 0, 0, 0ull, 0ull},
- {"PCC" , 10, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 560, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 560, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 560, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 560, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 560, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 560, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 560, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 560, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 560, "RO", 0, 0, 0ull, 0ull},
- {"EMIS" , 23, 1, 560, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 560, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 560, "RAZ", 1, 1, 0, 0},
- {"CTRS" , 0, 4, 561, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 561, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 561, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 562, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 562, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 563, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 564, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 565, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 566, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 567, "RO", 0, 0, 1ull, 0ull},
- {"CV" , 16, 4, 567, "RO", 0, 0, 1ull, 0ull},
- {"NCO" , 20, 12, 567, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 568, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 568, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 568, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 568, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 569, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 569, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 569, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 570, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 570, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 570, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 570, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 570, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 570, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 570, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 570, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 570, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 570, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 570, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 570, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 570, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 570, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 571, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 571, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 571, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 572, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 572, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 572, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 572, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 572, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 572, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 572, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 572, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 572, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 573, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 573, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 573, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 573, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 574, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 575, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 576, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 577, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 578, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 578, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 579, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 580, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 580, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 580, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 580, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 580, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 581, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 581, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 581, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 581, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 581, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 581, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 582, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 582, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 582, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 582, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 582, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_22_24" , 22, 3, 582, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 582, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 582, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 583, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 583, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 584, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 584, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 584, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 584, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 584, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 584, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 584, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 584, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 585, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 585, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_BAR_MATCH" , 18, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 586, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 587, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 588, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 589, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 589, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 589, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 590, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 590, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 590, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 591, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 591, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 591, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 592, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 592, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 592, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 592, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 593, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 593, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 593, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 593, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 594, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 594, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 594, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 594, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 595, "RO/WRSL", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 595, "RO/WRSL", 0, 0, 35ull, 35ull},
- {"RESERVED_20_20" , 20, 1, 595, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 595, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 595, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 595, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 595, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 596, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"HEADER_CREDITS" , 12, 8, 596, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"RESERVED_20_20" , 20, 1, 596, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 596, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 596, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 597, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 597, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 597, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 597, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 597, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 598, "RO/WRSL", 0, 0, 331ull, 331ull},
- {"RESERVED_14_15" , 14, 2, 598, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 598, "RO/WRSL", 0, 0, 41ull, 41ull},
- {"RESERVED_26_31" , 26, 6, 598, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 599, "RO/WRSL", 0, 0, 56ull, 56ull},
- {"RESERVED_14_15" , 14, 2, 599, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 599, "RO/WRSL", 0, 0, 14ull, 14ull},
- {"RESERVED_26_31" , 26, 6, 599, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 600, "RO/WRSL", 0, 0, 360ull, 360ull},
- {"RESERVED_14_15" , 14, 2, 600, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 600, "RO/WRSL", 0, 0, 70ull, 70ull},
- {"RESERVED_26_31" , 26, 6, 600, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 601, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 602, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 603, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 603, "R/W", 0, 0, 80ull, 80ull},
- {"ISAE" , 0, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 604, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 604, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 604, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 604, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 604, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 604, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 604, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 604, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 604, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 604, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 604, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 604, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 605, "R/W", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 605, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 605, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 605, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 606, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 606, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 606, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 606, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 607, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 608, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 609, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 609, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 609, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 609, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 610, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 610, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 610, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 610, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 610, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 610, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 610, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 610, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 610, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 611, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 611, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 611, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 611, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 612, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 612, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 612, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 612, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 612, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 612, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 613, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 614, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 615, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 615, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 616, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 616, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 617, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 618, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 618, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 618, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 618, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 618, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 618, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 618, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 618, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 618, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 619, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 619, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 619, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 619, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 619, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 619, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 619, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 619, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 619, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 620, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 620, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 620, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 620, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 620, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 620, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 620, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 620, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 620, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 620, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 620, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 620, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 621, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 621, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 621, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 621, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 621, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 621, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 622, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 622, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 623, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 624, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 624, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 625, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 625, "R/W", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 625, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 625, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 625, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 625, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 625, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 626, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 626, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 626, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 626, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 626, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 626, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 626, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 626, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 626, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 626, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 626, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 627, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 627, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 627, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 627, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 627, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 627, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 627, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 627, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 627, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 627, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 627, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 627, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 627, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 627, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 627, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 627, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 627, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 627, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 627, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 628, "R/W", 0, 0, 1ull, 1ull},
- {"MLW" , 4, 6, 628, "R/W", 0, 0, 8ull, 8ull},
- {"ASLPMS" , 10, 2, 628, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 628, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 628, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 628, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 628, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 628, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 628, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_23" , 22, 2, 628, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 628, "R/W", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 629, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 629, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 629, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 629, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 629, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 629, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 629, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 629, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 629, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 629, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 629, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 629, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 630, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 630, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 630, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 631, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 631, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 631, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 631, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 631, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 631, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 631, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 632, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 632, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 632, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 632, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 633, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 633, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 633, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 634, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 634, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 634, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 635, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 635, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 635, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 636, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 637, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 638, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 639, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 640, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 640, "RO", 0, 0, 1ull, 1ull},
- {"NCO" , 20, 12, 640, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 641, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 641, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 641, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 641, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 642, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 642, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 642, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 642, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 643, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 643, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 643, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 643, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 643, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 643, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 643, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 643, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 644, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 644, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 644, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 645, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 645, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 645, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 645, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 646, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 646, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 646, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 646, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 647, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 648, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 649, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 650, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 651, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 651, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 651, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 651, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 652, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 652, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 653, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 653, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 654, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 654, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 655, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 656, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 656, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 656, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 656, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 657, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 657, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 657, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 657, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 657, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 657, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 658, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 658, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 658, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 658, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 658, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_22_24" , 22, 3, 658, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 658, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 659, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 659, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 659, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 659, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 659, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 660, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 660, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 660, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 660, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 660, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 660, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 660, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 660, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 661, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 661, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_BAR_MATCH" , 18, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 662, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 662, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 662, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 663, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 664, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 665, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 665, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 665, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 666, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 666, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 666, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 667, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 667, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 667, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 668, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 668, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 668, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 668, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 669, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 669, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 669, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 669, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 670, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 670, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 670, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 670, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 671, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 671, "R/W", 0, 0, 35ull, 35ull},
- {"RESERVED_20_20" , 20, 1, 671, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 671, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 671, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 671, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 672, "R/W", 0, 0, 4ull, 4ull},
- {"HEADER_CREDITS" , 12, 8, 672, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_20_20" , 20, 1, 672, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 672, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 672, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 673, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 673, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_20_20" , 20, 1, 673, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 673, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 673, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 674, "R/W", 0, 0, 331ull, 331ull},
- {"RESERVED_14_15" , 14, 2, 674, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 674, "R/W", 0, 0, 41ull, 41ull},
- {"RESERVED_26_31" , 26, 6, 674, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 675, "R/W", 0, 0, 56ull, 56ull},
- {"RESERVED_14_15" , 14, 2, 675, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 675, "R/W", 0, 0, 14ull, 14ull},
- {"RESERVED_26_31" , 26, 6, 675, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 676, "R/W", 0, 0, 360ull, 360ull},
- {"RESERVED_14_15" , 14, 2, 676, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 676, "R/W", 0, 0, 70ull, 70ull},
- {"RESERVED_26_31" , 26, 6, 676, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 677, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 678, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 679, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 679, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 679, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 679, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 679, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 679, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 679, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 679, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 679, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 680, "RAZ", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 680, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 680, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 680, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 681, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 681, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 681, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 681, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 681, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 681, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 681, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 681, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 681, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 682, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 682, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 682, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 682, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 682, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 682, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 683, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_12_63" , 12, 52, 683, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 684, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 685, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 685, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 686, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 686, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 686, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 686, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 687, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 687, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 687, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 688, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 688, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 688, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 688, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 688, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 688, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 688, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 688, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 688, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 688, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 688, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 688, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 688, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 689, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 689, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 689, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 689, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 689, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 689, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 689, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 689, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 689, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 689, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 689, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 689, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 689, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 689, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 689, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 689, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 689, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 690, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 690, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 690, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 690, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 690, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 690, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 690, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 691, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 691, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 691, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 692, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 692, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 692, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 692, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 692, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 692, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 692, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 692, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 693, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 693, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 693, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 693, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 693, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 693, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 693, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 694, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 694, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 694, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 695, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 695, "RAZ", 1, 1, 0, 0},
- {"L0SYNC" , 0, 1, 696, "RO", 0, 0, 0ull, 1ull},
- {"L1SYNC" , 1, 1, 696, "RO", 0, 0, 0ull, 1ull},
- {"L2SYNC" , 2, 1, 696, "RO", 0, 0, 0ull, 1ull},
- {"L3SYNC" , 3, 1, 696, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_4_10" , 4, 7, 696, "RAZ", 1, 1, 0, 0},
- {"PATTST" , 11, 1, 696, "RO", 0, 0, 0ull, 0ull},
- {"ALIGND" , 12, 1, 696, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_63" , 13, 51, 696, "RAZ", 1, 1, 0, 0},
- {"BIST_STATUS" , 0, 1, 697, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 697, "RAZ", 1, 1, 0, 0},
- {"BITLCK0" , 0, 1, 698, "RO", 0, 1, 0ull, 0},
- {"BITLCK1" , 1, 1, 698, "RO", 0, 1, 0ull, 0},
- {"BITLCK2" , 2, 1, 698, "RO", 0, 1, 0ull, 0},
- {"BITLCK3" , 3, 1, 698, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 698, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 699, "RAZ", 1, 1, 0, 0},
- {"SPD" , 2, 4, 699, "RO", 0, 0, 0ull, 0ull},
- {"SPDSEL0" , 6, 1, 699, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_10" , 7, 4, 699, "RAZ", 1, 1, 0, 0},
- {"LO_PWR" , 11, 1, 699, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 699, "RAZ", 1, 1, 0, 0},
- {"SPDSEL1" , 13, 1, 699, "RO", 0, 0, 1ull, 1ull},
- {"LOOPBCK1" , 14, 1, 699, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 699, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 699, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 700, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 700, "RAZ", 1, 1, 0, 0},
- {"TXFLT_EN" , 0, 1, 701, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 1, 1, 701, "R/W", 0, 0, 0ull, 1ull},
- {"RXSYNBAD_EN" , 2, 1, 701, "R/W", 0, 0, 0ull, 1ull},
- {"BITLCKLS_EN" , 3, 1, 701, "R/W", 0, 0, 0ull, 1ull},
- {"SYNLOS_EN" , 4, 1, 701, "R/W", 0, 0, 0ull, 1ull},
- {"ALGNLOS_EN" , 5, 1, 701, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 701, "RAZ", 1, 1, 0, 0},
- {"TXFLT" , 0, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 1, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXSYNBAD" , 2, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
- {"BITLCKLS" , 3, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNLOS" , 4, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALGNLOS" , 5, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 702, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 703, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"DROP_LN" , 4, 2, 703, "R/W", 0, 0, 0ull, 0ull},
- {"ENC_MODE" , 6, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 703, "RAZ", 1, 1, 0, 0},
- {"GMXENO" , 0, 1, 704, "R/W", 0, 0, 0ull, 0ull},
- {"XAUI" , 1, 1, 704, "RO", 1, 1, 0, 0},
- {"RX_SWAP" , 2, 1, 704, "R/W", 0, 1, 0ull, 0},
- {"TX_SWAP" , 3, 1, 704, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 704, "RAZ", 1, 1, 0, 0},
- {"SYNC0ST" , 0, 4, 705, "RO", 0, 1, 0ull, 0},
- {"SYNC1ST" , 4, 4, 705, "RO", 0, 1, 0ull, 0},
- {"SYNC2ST" , 8, 4, 705, "RO", 0, 1, 0ull, 0},
- {"SYNC3ST" , 12, 4, 705, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 705, "RAZ", 1, 1, 0, 0},
- {"TENGB" , 0, 1, 706, "RO", 0, 0, 1ull, 1ull},
- {"TENPASST" , 1, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 706, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 707, "RAZ", 1, 1, 0, 0},
- {"LPABLE" , 1, 1, 707, "RO", 0, 0, 1ull, 1ull},
- {"RCV_LNK" , 2, 1, 707, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_3_6" , 3, 4, 707, "RAZ", 1, 1, 0, 0},
- {"FLT" , 7, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 707, "RAZ", 1, 1, 0, 0},
- {"TENGB_R" , 0, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"TENGB_X" , 1, 1, 708, "RO", 0, 0, 1ull, 1ull},
- {"TENGB_W" , 2, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_9" , 3, 7, 708, "RAZ", 1, 1, 0, 0},
- {"RCVFLT" , 10, 1, 708, "RC", 0, 0, 0ull, 0ull},
- {"XMTFLT" , 11, 1, 708, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 708, "RAZ", 1, 1, 0, 0},
- {"DEV" , 14, 2, 708, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_16_63" , 16, 48, 708, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 709, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 709, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_TXPLRT" , 2, 4, 709, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_RXPLRT" , 6, 4, 709, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 709, "RAZ", 1, 1, 0, 0},
- {"TX_ST" , 0, 3, 710, "RO", 0, 1, 0ull, 0},
- {"RX_ST" , 3, 2, 710, "RO", 0, 1, 0ull, 0},
- {"ALGN_ST" , 5, 3, 710, "RO", 0, 1, 0ull, 0},
- {"RXBAD" , 8, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"SYN0BAD" , 9, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"SYN1BAD" , 10, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"SYN2BAD" , 11, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"SYN3BAD" , 12, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"TERM_ERR" , 13, 1, 710, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 710, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA4" , 3, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 4, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 5, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 6, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 7, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 8, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"PTLP_OR" , 9, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"NTLP_OR" , 10, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"CTLP_OR" , 11, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA5" , 12, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 711, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"RSL_P2E" , 6, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 7, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"DBG_P2E" , 8, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"E2P_RSL" , 9, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 10, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 11, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 12, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"CTO_P2E" , 13, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 712, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 713, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 713, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 714, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 714, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 715, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 715, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 716, "RAZ", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 716, "RAZ", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 716, "RAZ", 0, 0, 0ull, 0ull},
- {"QLM_CFG" , 13, 2, 716, "RO", 1, 1, 0, 0},
- {"PBUS" , 15, 8, 716, "RO", 1, 1, 0, 0},
- {"DNUM" , 23, 5, 716, "RO", 1, 1, 0, 0},
- {"RESERVED_28_63" , 28, 36, 716, "RAZ", 1, 1, 0, 0},
- {"PCIERST" , 0, 1, 717, "RO", 0, 0, 0ull, 0ull},
- {"PCLK_RUN" , 1, 1, 717, "R/W1C", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 717, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 718, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 719, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 720, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 720, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 720, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 720, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 720, "RO", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 721, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 721, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 722, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 722, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_38" , 0, 39, 723, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 39, 25, 723, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 724, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 724, "R/W", 0, 1, 4503599627370495ull, 0},
- {"RESERVED_0_11" , 0, 12, 725, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 725, "R/W", 0, 1, 4503599627370495ull, 0},
- {"NPEI_P" , 0, 8, 726, "R/W", 0, 0, 128ull, 128ull},
- {"NPEI_NP" , 8, 8, 726, "R/W", 0, 0, 16ull, 16ull},
- {"NPEI_CPL" , 16, 8, 726, "R/W", 0, 0, 128ull, 128ull},
- {"PESC_P" , 24, 8, 726, "R/W", 0, 0, 128ull, 128ull},
- {"PESC_NP" , 32, 8, 726, "R/W", 0, 0, 16ull, 16ull},
- {"PESC_CPL" , 40, 8, 726, "R/W", 0, 0, 128ull, 128ull},
- {"PEAI_PPF" , 48, 8, 726, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_56_63" , 56, 8, 726, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 727, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 727, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 727, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 727, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 18, 728, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 728, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 729, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 729, "RAZ", 1, 1, 0, 0},
- {"MAP0" , 0, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 730, "R/W", 0, 0, 0ull, 0ull},
- {"MAP0" , 0, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 731, "R/W", 0, 0, 0ull, 0ull},
- {"MINLEN" , 0, 16, 732, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 732, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 732, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 733, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 733, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 733, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 733, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 733, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 733, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 734, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 734, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 734, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 20, 1, 734, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_23" , 21, 3, 734, "RAZ", 1, 1, 0, 0},
- {"DSA_GRP_SID" , 24, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SCMD" , 25, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_TVID" , 26, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 734, "RAZ", 1, 1, 0, 0},
- {"PRI" , 0, 6, 735, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 735, "RAZ", 1, 1, 0, 0},
- {"QOS" , 8, 3, 735, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 735, "RAZ", 1, 1, 0, 0},
- {"UP_QOS" , 12, 1, 735, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_13_63" , 13, 51, 735, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 736, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 737, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 738, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 738, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 739, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 739, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_EN" , 10, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"HIGIG_EN" , 11, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"CRC_EN" , 12, 1, 739, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 739, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VSEL" , 19, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 739, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 739, "R/W", 0, 0, 0ull, 0ull},
- {"HG_QOS" , 27, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT" , 28, 4, 739, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 739, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 739, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 739, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 739, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 739, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 739, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_63" , 53, 11, 739, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 740, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 740, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 740, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 740, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 740, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 740, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 740, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 740, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 740, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 741, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 741, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 742, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 742, "RAZ", 1, 1, 0, 0},
- {"QOS1" , 4, 3, 742, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 742, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 743, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 743, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 743, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 743, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 743, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 743, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 743, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 743, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 743, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 744, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 744, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 745, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 746, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 746, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 747, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 747, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 748, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 748, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 749, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 749, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 750, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 750, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 751, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 751, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 752, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 752, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 753, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 753, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 754, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 754, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 755, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 755, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 756, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 756, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 757, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 757, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 758, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 758, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 759, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 759, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 760, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 760, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 761, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 761, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 762, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 762, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 762, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 763, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 763, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 763, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 764, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 764, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 765, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 765, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 766, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 766, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 766, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 766, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 767, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 767, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 767, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 767, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 767, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 768, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 768, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 768, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 768, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 769, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 769, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 769, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 769, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 769, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 769, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 769, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 769, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 770, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 770, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 770, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 770, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 771, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 771, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 771, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 771, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 771, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 772, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 773, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 773, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 773, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 773, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 773, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 774, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 775, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 775, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 775, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 775, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 775, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 775, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 775, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 775, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 775, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 775, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 775, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 775, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 775, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 776, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 776, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 776, "RO", 1, 0, 0, 0ull},
- {"RESERVED_54_63" , 54, 10, 776, "RAZ", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 777, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 777, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 777, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 777, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 777, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 777, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 777, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 777, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 777, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 777, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 777, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 777, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 777, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 778, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 778, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 778, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 778, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 778, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 778, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 779, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 779, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 779, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 779, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 6, 1, 779, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 779, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 779, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 779, "RO", 1, 0, 0, 0ull},
- {"RESERVED_29_63" , 29, 35, 779, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 780, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 780, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 780, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 780, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 781, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 781, "R/W", 1, 0, 0, 0ull},
- {"BP_PORT" , 10, 6, 781, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_52" , 16, 37, 781, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 781, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 61, 1, 781, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_62_63" , 62, 2, 781, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 782, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 782, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_10_52" , 10, 43, 782, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 782, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 782, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 783, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 783, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 783, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 783, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 783, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 784, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 784, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 784, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 784, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 785, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 785, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 785, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 785, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 785, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 785, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 785, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 785, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 785, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 786, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 786, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 786, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 786, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 786, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 787, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 787, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 787, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 787, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 787, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 787, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 8, 787, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 787, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 787, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 787, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 787, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 3, 787, "RO", 1, 0, 0, 0ull},
- {"OUT_DAT" , 32, 1, 787, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 787, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 787, "RO", 1, 0, 0, 0ull},
- {"RESERVED_35_63" , 35, 29, 787, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 788, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 788, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 788, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 788, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 789, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 790, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 791, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 792, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 793, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE1" , 4, 4, 793, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE2" , 8, 4, 793, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE3" , 12, 4, 793, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE4" , 16, 4, 793, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE5" , 20, 4, 793, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE6" , 24, 4, 793, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE7" , 28, 4, 793, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE8" , 32, 4, 793, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE9" , 36, 4, 793, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_40_63" , 40, 24, 793, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 10, 794, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 794, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 795, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 795, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 795, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 795, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 796, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 796, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 797, "R/W", 0, 0, 2ull, 2ull},
- {"MODE1" , 3, 3, 797, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 797, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 798, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 799, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 799, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 800, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 800, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 800, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 801, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 801, "RAZ", 1, 1, 0, 0},
- {"ADR0" , 0, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"ADR1" , 1, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"PEND0" , 2, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"PEND1" , 3, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 4, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 5, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 6, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 7, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 8, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 9, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 802, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 12, 802, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 802, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 803, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 803, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 804, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 804, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 804, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 804, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 804, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 804, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 804, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 804, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 804, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 805, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 805, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 805, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 806, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 806, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 807, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 807, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 808, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 808, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 809, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 809, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 810, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 810, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 12, 811, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 811, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 812, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_10_63" , 10, 54, 812, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 813, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 813, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 814, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 814, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 814, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 814, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 814, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 814, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 814, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 814, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 814, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 814, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 815, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 815, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 815, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 815, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 815, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 11, 816, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 816, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 11, 816, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_23_23" , 23, 1, 816, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 12, 816, "RO", 0, 1, 2027ull, 0},
- {"BUF_CNT" , 36, 12, 816, "RO", 0, 1, 0ull, 0},
- {"DES_CNT" , 48, 12, 816, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 816, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 817, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 817, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 818, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 818, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 819, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 819, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 820, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 820, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 820, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 12, 821, "RO", 0, 1, 0ull, 0},
- {"DS_CNT" , 12, 12, 821, "RO", 0, 1, 0ull, 0},
- {"TC_CNT" , 24, 4, 821, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 821, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 822, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 822, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 822, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 822, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 822, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 11, 823, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 823, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 11, 823, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 823, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 823, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 823, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 823, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 824, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 824, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 825, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 826, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 827, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 828, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 828, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 828, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 828, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 828, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 829, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 829, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 829, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 829, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 829, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 830, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 830, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 830, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 831, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 831, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 831, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 831, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 831, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 831, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 831, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 831, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 831, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 831, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 832, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 833, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 833, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 833, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 834, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 834, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 834, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 834, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 834, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 834, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 834, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 835, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 835, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 836, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 837, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 838, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 839, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 839, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 839, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 839, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 839, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 839, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 839, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 839, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 839, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 839, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 839, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 839, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 839, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 839, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 839, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 839, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 839, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 839, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 840, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 840, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 840, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 841, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 841, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 842, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 842, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 842, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 843, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 843, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 843, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 843, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 843, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 843, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 843, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 844, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 845, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 845, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 846, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 846, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 847, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 847, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 847, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 848, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 848, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 848, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 849, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 849, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 849, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 850, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 850, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 850, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 850, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 850, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 850, "R/W", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 850, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 850, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 850, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 850, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 851, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 851, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 851, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 851, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 851, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 851, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 852, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 852, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 853, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 853, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 853, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 853, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 854, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 854, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 854, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 854, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 855, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 855, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 855, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 855, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 855, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 855, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 856, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 856, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 856, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 857, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 857, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 857, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 857, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 857, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 858, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 858, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 858, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 858, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 859, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 859, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 859, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 859, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 859, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 860, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 860, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 860, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 860, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 861, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 861, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 862, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 862, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 863, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 863, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 864, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 864, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 864, "RAZ", 1, 1, 0, 0},
- {"TDF0" , 0, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"TDF1" , 1, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"TCF" , 2, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 865, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 866, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 866, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 866, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 866, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 866, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 866, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 866, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 866, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 866, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 866, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 866, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 866, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 867, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 867, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 867, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 868, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 868, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 868, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 868, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 868, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 869, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 869, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 870, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 870, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 871, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 871, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 872, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 872, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 872, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 872, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 872, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 872, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 872, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 872, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 872, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 872, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 872, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 872, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 873, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 873, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 873, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 873, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 873, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 873, "RAZ", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 874, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 874, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 874, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 874, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 874, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 875, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 876, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 876, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 877, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 877, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 878, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 878, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 879, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 879, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 879, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 879, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 879, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 879, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 879, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 879, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 879, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 879, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 879, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 879, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 880, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 880, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 881, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 881, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 882, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 883, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 883, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 884, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 884, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 884, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 884, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 884, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 884, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 884, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 884, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 884, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 884, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 884, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 884, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 885, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 885, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 885, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 885, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 885, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 885, "RAZ", 0, 0, 0ull, 0ull},
- {"INEPINT" , 0, 16, 886, "RO", 0, 0, 0ull, 0ull},
- {"OUTEPINT" , 16, 16, 886, "RO", 0, 0, 0ull, 0ull},
- {"INEPMSK" , 0, 16, 887, "R/W", 0, 0, 0ull, 0ull},
- {"OUTEPMSK" , 16, 16, 887, "R/W", 0, 0, 0ull, 0ull},
- {"DEVSPD" , 0, 2, 888, "R/W", 0, 0, 0ull, 0ull},
- {"NZSTSOUTHSHK" , 2, 1, 888, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 888, "RAZ", 1, 1, 0, 0},
- {"DEVADDR" , 4, 7, 888, "R/W", 0, 0, 0ull, 0ull},
- {"PERFRINT" , 11, 2, 888, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_17" , 13, 5, 888, "RAZ", 1, 1, 0, 0},
- {"EPMISCNT" , 18, 5, 888, "R/W", 0, 0, 8ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 888, "RAZ", 1, 1, 0, 0},
- {"RMTWKUPSIG" , 0, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"SFTDISCON" , 1, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"GNPINNAKSTS" , 2, 1, 889, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKSTS" , 3, 1, 889, "RO", 0, 0, 0ull, 0ull},
- {"TSTCTL" , 4, 3, 889, "R/W", 0, 0, 0ull, 0ull},
- {"SGNPINNAK" , 7, 1, 889, "WO", 0, 0, 0ull, 0ull},
- {"CGNPINNAK" , 8, 1, 889, "WO", 0, 0, 0ull, 0ull},
- {"SGOUTNAK" , 9, 1, 889, "WO", 0, 0, 0ull, 0ull},
- {"CGOUTNAK" , 10, 1, 889, "WO", 0, 0, 0ull, 0ull},
- {"PWRONPRGDONE" , 11, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 889, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 890, "R/W", 0, 0, 0ull, 0ull},
- {"NEXTEP" , 11, 4, 890, "R/W", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 890, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 890, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 890, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 890, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 890, "RAZ", 1, 1, 0, 0},
- {"STALL" , 21, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 22, 4, 890, "R/W", 0, 0, 0ull, 0ull},
- {"CNAK" , 26, 1, 890, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 890, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 890, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 890, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMEOUT" , 3, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMP" , 4, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNEPMIS" , 5, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
- {"INEPNAKEFF" , 6, 1, 891, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 891, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"TIMEOUTMSK" , 3, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMPMSK" , 4, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNEPMISMSK" , 5, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"INEPNAKEFFMSK" , 6, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 892, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 893, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 893, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 893, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 893, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 894, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_14" , 11, 4, 894, "RAZ", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 894, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 894, "R/W", 0, 0, 0ull, 0ull},
- {"SNP" , 20, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"STALL" , 21, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_25" , 22, 4, 894, "RAZ", 1, 1, 0, 0},
- {"CNAK" , 26, 1, 894, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 894, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 894, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 894, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 895, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 895, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 895, "R/W1C", 0, 0, 0ull, 0ull},
- {"SETUP" , 3, 1, 895, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDIS" , 4, 1, 895, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 895, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"SETUPMSK" , 3, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDISMSK" , 4, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 896, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 897, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 897, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 897, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 897, "RAZ", 1, 1, 0, 0},
- {"DPTXFSTADDR" , 0, 16, 898, "RO", 0, 0, 0ull, 0ull},
- {"DPTXFSIZE" , 16, 16, 898, "RO", 0, 0, 1896ull, 1896ull},
- {"SUSPSTS" , 0, 1, 899, "RO", 0, 0, 0ull, 0ull},
- {"ENUMSPD" , 1, 2, 899, "RO", 0, 0, 0ull, 0ull},
- {"ERRTICERR" , 3, 1, 899, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 899, "RAZ", 1, 1, 0, 0},
- {"SOFFN" , 8, 14, 899, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 899, "RAZ", 1, 1, 0, 0},
- {"INTKNWPTR" , 0, 5, 900, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 900, "RAZ", 1, 1, 0, 0},
- {"WRAPBIT" , 7, 1, 900, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 8, 24, 900, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 901, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 902, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 903, "RO", 0, 0, 0ull, 0ull},
- {"GLBLINTRMSK" , 0, 1, 904, "R/W", 0, 0, 0ull, 1ull},
- {"HBSTLEN" , 1, 4, 904, "R/W", 0, 0, 0ull, 0ull},
- {"DMAEN" , 5, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 904, "RAZ", 1, 1, 0, 0},
- {"NPTXFEMPLVL" , 7, 1, 904, "R/W", 0, 0, 0ull, 1ull},
- {"PTXFEMPLVL" , 8, 1, 904, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_31" , 9, 23, 904, "RAZ", 1, 1, 0, 0},
- {"EPDIR" , 0, 32, 905, "RO", 0, 0, 0ull, 0ull},
- {"OTGMODE" , 0, 3, 906, "RO", 0, 0, 2ull, 2ull},
- {"OTGARCH" , 3, 2, 906, "RO", 0, 0, 1ull, 1ull},
- {"SINGPNT" , 5, 1, 906, "RO", 0, 0, 0ull, 0ull},
- {"HSPHYTYPE" , 6, 2, 906, "RO", 0, 0, 1ull, 1ull},
- {"FSPHYTYPE" , 8, 2, 906, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVEPS" , 10, 4, 906, "RO", 0, 0, 4ull, 4ull},
- {"NUMHSTCHNL" , 14, 4, 906, "RO", 0, 0, 7ull, 7ull},
- {"PERIOSUPPORT" , 18, 1, 906, "RO", 0, 0, 1ull, 1ull},
- {"DYNFIFOSIZING" , 19, 1, 906, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_20_21" , 20, 2, 906, "RAZ", 1, 1, 0, 0},
- {"NPTXQDEPTH" , 22, 2, 906, "RO", 0, 0, 2ull, 2ull},
- {"PTXQDEPTH" , 24, 2, 906, "RO", 0, 0, 2ull, 2ull},
- {"TKNQDEPTH" , 26, 5, 906, "RO", 0, 0, 30ull, 30ull},
- {"RESERVED_31_31" , 31, 1, 906, "RAZ", 1, 1, 0, 0},
- {"XFERSIZEWIDTH" , 0, 4, 907, "RO", 0, 0, 8ull, 8ull},
- {"PKTSIZEWIDTH" , 4, 3, 907, "RO", 0, 0, 6ull, 6ull},
- {"OTGEN" , 7, 1, 907, "RO", 0, 0, 1ull, 1ull},
- {"I2C_SELECTION" , 8, 1, 907, "RO", 0, 0, 0ull, 0ull},
- {"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 907, "RO", 0, 0, 0ull, 0ull},
- {"OPTFEATURE" , 10, 1, 907, "RO", 0, 0, 1ull, 1ull},
- {"RSTTYPE" , 11, 1, 907, "RO", 0, 0, 0ull, 0ull},
- {"AHBPHYSYNC" , 12, 1, 907, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 907, "RAZ", 1, 1, 0, 0},
- {"DFIFODEPTH" , 16, 16, 907, "RO", 0, 0, 1824ull, 1824ull},
- {"NUMDEVPERIOEPS" , 0, 4, 908, "RO", 0, 0, 4ull, 4ull},
- {"ENABLEPWROPT" , 4, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"AHBFREQ" , 5, 1, 908, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_13" , 6, 8, 908, "RAZ", 1, 1, 0, 0},
- {"PHYDATAWIDTH" , 14, 2, 908, "RO", 0, 0, 1ull, 1ull},
- {"NUMCTLEPS" , 16, 4, 908, "RO", 0, 0, 4ull, 4ull},
- {"IDDGFLTR" , 20, 1, 908, "RO", 0, 0, 1ull, 1ull},
- {"VBUSVALIDFLTR" , 21, 1, 908, "RO", 0, 0, 1ull, 1ull},
- {"AVALIDFLTR" , 22, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"BVALIDFLTR" , 23, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"SESSENDFLTR" , 24, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"ENDEDTRFIFO" , 25, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVMODINEND" , 26, 4, 908, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_30_31" , 30, 2, 908, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 909, "RAZ", 1, 1, 0, 0},
- {"MODEMISMSK" , 1, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"OTGINTMSK" , 2, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"SOFMSK" , 3, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"RXFLVLMSK" , 4, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"NPTXFEMPMSK" , 5, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"GINNAKEFFMSK" , 6, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFFMSK" , 7, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"ULPICKINTMSK" , 8, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"ERLYSUSPMSK" , 10, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"USBSUSPMSK" , 11, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"USBRSTMSK" , 12, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"ENUMDONEMSK" , 13, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"ISOOUTDROPMSK" , 14, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"EOPFMSK" , 15, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 909, "RAZ", 1, 1, 0, 0},
- {"EPMISMSK" , 17, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"INEPINTMSK" , 18, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"OEPINTMSK" , 19, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPISOINMSK" , 20, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPLPMSK" , 21, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"FETSUSPMSK" , 22, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 909, "RAZ", 1, 1, 0, 0},
- {"PRTINTMSK" , 24, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"HCHINTMSK" , 25, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"PTXFEMPMSK" , 26, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 909, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNGMSK" , 28, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"DISCONNINTMSK" , 29, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"SESSREQINTMSK" , 30, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"WKUPINTMSK" , 31, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"CURMOD" , 0, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"MODEMIS" , 1, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"OTGINT" , 2, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"SOF" , 3, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXFLVL" , 4, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"NPTXFEMP" , 5, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"GINNAKEFF" , 6, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFF" , 7, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"ULPICKINT" , 8, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"ERLYSUSP" , 10, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBSUSP" , 11, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBRST" , 12, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENUMDONE" , 13, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"ISOOUTDROP" , 14, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"EOPF" , 15, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 910, "RAZ", 1, 1, 0, 0},
- {"EPMIS" , 17, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"IEPINT" , 18, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"OEPINT" , 19, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"INCOMPISOIN" , 20, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"INCOMPLP" , 21, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"FETSUSP" , 22, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 910, "RAZ", 1, 1, 0, 0},
- {"PRTINT" , 24, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"HCHINT" , 25, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"PTXFEMP" , 26, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 910, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNG" , 28, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"DISCONNINT" , 29, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"SESSREQINT" , 30, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"WKUPINT" , 31, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
- {"NPTXFSTADDR" , 0, 16, 911, "R/W", 0, 0, 1824ull, 456ull},
- {"NPTXFDEP" , 16, 16, 911, "R/W", 0, 0, 1824ull, 912ull},
- {"NPTXFSPCAVAIL" , 0, 16, 912, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQSPCAVAIL" , 16, 8, 912, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQTOP" , 24, 7, 912, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 912, "RAZ", 1, 1, 0, 0},
- {"SESREQSCS" , 0, 1, 913, "R/W", 0, 0, 0ull, 0ull},
- {"SESREQ" , 1, 1, 913, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 913, "RAZ", 1, 1, 0, 0},
- {"HSTNEGSCS" , 8, 1, 913, "R/W", 0, 0, 0ull, 0ull},
- {"HNPREQ" , 9, 1, 913, "R/W", 0, 0, 0ull, 0ull},
- {"HSTSETHNPEN" , 10, 1, 913, "R/W", 0, 0, 0ull, 0ull},
- {"DEVHNPEN" , 11, 1, 913, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 913, "RAZ", 1, 1, 0, 0},
- {"CONIDSTS" , 16, 1, 913, "RO", 1, 1, 0, 0},
- {"DBNCTIME" , 17, 1, 913, "RO", 0, 0, 0ull, 0ull},
- {"ASESVLD" , 18, 1, 913, "RO", 1, 1, 0, 0},
- {"BSESVLD" , 19, 1, 913, "RO", 1, 1, 0, 0},
- {"RESERVED_20_31" , 20, 12, 913, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 914, "RAZ", 1, 1, 0, 0},
- {"SESENDDET" , 2, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 914, "RAZ", 1, 1, 0, 0},
- {"SESREQSUCSTSCHNG" , 8, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSTNEGSUCSTSCHNG" , 9, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_16" , 10, 7, 914, "RAZ", 1, 1, 0, 0},
- {"HSTNEGDET" , 17, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
- {"ADEVTOUTCHG" , 18, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBNCEDONE" , 19, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 914, "RAZ", 1, 1, 0, 0},
- {"CSFTRST" , 0, 1, 915, "R/W", 0, 0, 0ull, 0ull},
- {"HSFTRST" , 1, 1, 915, "R/W", 0, 0, 0ull, 0ull},
- {"FRMCNTRRST" , 2, 1, 915, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNQFLSH" , 3, 1, 915, "R/W", 0, 0, 0ull, 0ull},
- {"RXFFLSH" , 4, 1, 915, "R/W", 0, 0, 0ull, 0ull},
- {"TXFFLSH" , 5, 1, 915, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 6, 5, 915, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_29" , 11, 19, 915, "RAZ", 1, 1, 0, 0},
- {"DMAREQ" , 30, 1, 915, "RO", 0, 0, 0ull, 0ull},
- {"AHBIDLE" , 31, 1, 915, "RO", 0, 0, 1ull, 1ull},
- {"RXFDEP" , 0, 16, 916, "R/W", 0, 0, 1824ull, 456ull},
- {"RESERVED_16_31" , 16, 16, 916, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 917, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 917, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 917, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 917, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 917, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 917, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 918, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 918, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 918, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 918, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 918, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 919, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 919, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 919, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 919, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 919, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 919, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 920, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 920, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 920, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 920, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 920, "RAZ", 1, 1, 0, 0},
- {"SYNOPSYSID" , 0, 32, 921, "RO", 1, 1, 0, 0},
- {"TOUTCAL" , 0, 3, 922, "R/W", 0, 0, 0ull, 0ull},
- {"PHYIF" , 3, 1, 922, "RO", 0, 0, 1ull, 1ull},
- {"ULPI_UTMI_SEL" , 4, 1, 922, "RO", 0, 0, 0ull, 0ull},
- {"FSINTF" , 5, 1, 922, "WO", 0, 0, 0ull, 0ull},
- {"PHYSEL" , 6, 1, 922, "WO", 0, 0, 0ull, 0ull},
- {"DDRSEL" , 7, 1, 922, "R/W", 0, 0, 0ull, 0ull},
- {"SRPCAP" , 8, 1, 922, "RO", 0, 0, 0ull, 0ull},
- {"HNPCAP" , 9, 1, 922, "RO", 0, 0, 0ull, 0ull},
- {"USBTRDTIM" , 10, 4, 922, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_14_14" , 14, 1, 922, "RAZ", 1, 1, 0, 0},
- {"PHYLPWRCLKSEL" , 15, 1, 922, "R/W", 0, 0, 0ull, 0ull},
- {"OTGI2CSEL" , 16, 1, 922, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 922, "RAZ", 1, 1, 0, 0},
- {"HAINT" , 0, 16, 923, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 923, "RAZ", 1, 1, 0, 0},
- {"HAINTMSK" , 0, 16, 924, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 924, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 925, "R/W", 0, 0, 0ull, 0ull},
- {"EPNUM" , 11, 4, 925, "R/W", 0, 0, 0ull, 0ull},
- {"EPDIR" , 15, 1, 925, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 925, "RAZ", 1, 1, 0, 0},
- {"LSPDDEV" , 17, 1, 925, "R/W", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 925, "R/W", 0, 0, 0ull, 0ull},
- {"EC" , 20, 2, 925, "R/W", 0, 0, 0ull, 0ull},
- {"DEVADDR" , 22, 7, 925, "R/W", 0, 0, 0ull, 0ull},
- {"ODDFRM" , 29, 1, 925, "R/W", 0, 0, 0ull, 0ull},
- {"CHDIS" , 30, 1, 925, "R/W", 0, 0, 0ull, 0ull},
- {"CHENA" , 31, 1, 925, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSPCLKSEL" , 0, 2, 926, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSSUPP" , 2, 1, 926, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 926, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPL" , 0, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"CHHLTD" , 1, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"STALL" , 3, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAK" , 4, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACK" , 5, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"NYET" , 6, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"XACTERR" , 7, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"BBLERR" , 8, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMOVRUN" , 9, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATATGLERR" , 10, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 927, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"CHHLTDMSK" , 1, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"STALLMSK" , 3, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"NAKMSK" , 4, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"ACKMSK" , 5, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"NYETMSK" , 6, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"XACTERRMSK" , 7, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"BBLERRMSK" , 8, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"FRMOVRUNMSK" , 9, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"DATATGLERRMSK" , 10, 1, 928, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 928, "RAZ", 1, 1, 0, 0},
- {"PRTADDR" , 0, 7, 929, "R/W", 0, 0, 0ull, 0ull},
- {"HUBADDR" , 7, 7, 929, "R/W", 0, 0, 0ull, 0ull},
- {"XACTPOS" , 14, 2, 929, "R/W", 0, 0, 0ull, 0ull},
- {"COMPSPLT" , 16, 1, 929, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_30" , 17, 14, 929, "RAZ", 1, 1, 0, 0},
- {"SPLTENA" , 31, 1, 929, "R/W", 0, 0, 0ull, 0ull},
- {"XFERSIZE" , 0, 19, 930, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 930, "R/W", 0, 0, 0ull, 0ull},
- {"PID" , 29, 2, 930, "R/W", 0, 0, 0ull, 0ull},
- {"DOPNG" , 31, 1, 930, "R/W", 0, 0, 0ull, 0ull},
- {"FRINT" , 0, 16, 931, "R/W", 0, 0, 2959ull, 3750ull},
- {"RESERVED_16_31" , 16, 16, 931, "RAZ", 1, 1, 0, 0},
- {"FRNUM" , 0, 16, 932, "RO", 0, 0, 16383ull, 0ull},
- {"FRREM" , 16, 16, 932, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNSTS" , 0, 1, 933, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNDET" , 1, 1, 933, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENA" , 2, 1, 933, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENCHNG" , 3, 1, 933, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRACT" , 4, 1, 933, "RO", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRCHNG" , 5, 1, 933, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTRES" , 6, 1, 933, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSUSP" , 7, 1, 933, "R/W", 0, 0, 0ull, 0ull},
- {"PRTRST" , 8, 1, 933, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 933, "RAZ", 1, 1, 0, 0},
- {"PRTLNSTS" , 10, 2, 933, "RO", 0, 0, 0ull, 0ull},
- {"PRTPWR" , 12, 1, 933, "R/W", 0, 0, 0ull, 0ull},
- {"PRTTSTCTL" , 13, 4, 933, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSPD" , 17, 2, 933, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 933, "RAZ", 1, 1, 0, 0},
- {"PTXFSTADDR" , 0, 16, 934, "R/W", 0, 0, 3648ull, 912ull},
- {"PTXFSIZE" , 16, 16, 934, "R/W", 0, 0, 256ull, 456ull},
- {"PTXFSPCAVAIL" , 0, 16, 935, "RO", 0, 0, 0ull, 0ull},
- {"PTXQSPCAVAIL" , 16, 8, 935, "RO", 0, 0, 0ull, 0ull},
- {"PTXQTOP" , 24, 8, 935, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 32, 936, "R/W", 0, 0, 0ull, 0ull},
- {"STOPPCLK" , 0, 1, 937, "R/W", 0, 0, 0ull, 0ull},
- {"GATEHCLK" , 1, 1, 937, "R/W", 0, 0, 0ull, 0ull},
- {"PWRCLMP" , 2, 1, 937, "R/W", 0, 0, 0ull, 0ull},
- {"RSTPDWNMODULE" , 3, 1, 937, "R/W", 0, 0, 0ull, 0ull},
- {"PHYSUSPENDED" , 4, 1, 937, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 937, "RAZ", 1, 1, 0, 0},
- {"NOF_BIS" , 0, 1, 938, "RO", 0, 0, 0ull, 0ull},
- {"NIF_BIS" , 1, 1, 938, "RO", 0, 0, 0ull, 0ull},
- {"USBC_BIS" , 2, 1, 938, "RO", 0, 0, 0ull, 0ull},
- {"N2UF_BIS" , 3, 1, 938, "RO", 0, 0, 0ull, 0ull},
- {"E2HC_BIS" , 4, 1, 938, "RO", 0, 0, 0ull, 0ull},
- {"U2NF_BIS" , 5, 1, 938, "RO", 0, 0, 0ull, 0ull},
- {"U2NC_BIS" , 6, 1, 938, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 938, "RAZ", 1, 1, 0, 0},
- {"DIVIDE" , 0, 3, 939, "R/W", 0, 0, 4ull, 0ull},
- {"HRST" , 3, 1, 939, "R/W", 0, 0, 0ull, 1ull},
- {"PRST" , 4, 1, 939, "R/W", 0, 0, 0ull, 1ull},
- {"ENABLE" , 5, 1, 939, "R/W", 0, 0, 1ull, 1ull},
- {"POR" , 6, 1, 939, "R/W", 0, 0, 1ull, 0ull},
- {"S_BIST" , 7, 1, 939, "R/W", 0, 0, 0ull, 1ull},
- {"SD_MODE" , 8, 2, 939, "R/W", 0, 0, 0ull, 0ull},
- {"CDIV_BYP" , 10, 1, 939, "R/W", 0, 0, 0ull, 0ull},
- {"P_C_SEL" , 11, 2, 939, "R/W", 0, 0, 2ull, 0ull},
- {"P_COM_ON" , 13, 1, 939, "R/W", 0, 0, 1ull, 1ull},
- {"P_RTYPE" , 14, 2, 939, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 939, "RAZ", 1, 1, 0, 0},
- {"HCLK_RST" , 17, 1, 939, "R/W", 0, 0, 1ull, 1ull},
- {"DIVIDE2" , 18, 2, 939, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_63" , 20, 44, 939, "RAZ", 1, 1, 0, 0},
- {"L2C_EMOD" , 0, 2, 940, "R/W", 0, 0, 1ull, 1ull},
- {"INV_A2" , 2, 1, 940, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_TEST" , 3, 1, 940, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_STT" , 4, 1, 940, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_0PAG" , 5, 1, 940, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 940, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 941, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 941, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 942, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 942, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 943, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 943, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 944, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 944, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 945, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 945, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 946, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 946, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 947, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 947, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 948, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 948, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 949, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 949, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 950, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 950, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 951, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 951, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 952, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 952, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 953, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 953, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 954, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 954, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 955, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 955, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 956, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 956, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 4, 957, "R/W", 0, 0, 0ull, 0ull},
- {"CHANNEL" , 4, 5, 957, "R/W", 0, 0, 0ull, 0ull},
- {"COUNT" , 9, 11, 957, "R/W", 0, 0, 0ull, 0ull},
- {"F_ADDR" , 20, 18, 957, "R/W", 0, 0, 0ull, 0ull},
- {"REQ" , 38, 1, 957, "R/W1C", 0, 0, 0ull, 0ull},
- {"DONE" , 39, 1, 957, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 957, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_A_F" , 15, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_E" , 16, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_F" , 17, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PF" , 25, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 958, "RAZ", 0, 0, 0ull, 0ull},
- {"LTL_F_PE" , 32, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPF" , 35, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPE" , 36, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPF" , 37, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 958, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 959, "R/W1C", 1, 0, 0, 0ull},
- {"L2C_A_F" , 15, 1, 959, "R/W1C", 1, 0, 0, 0ull},
- {"LT_FI_E" , 16, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_FI_F" , 17, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 959, "R/W1C", 1, 0, 0, 0ull},
- {"UOD_PF" , 25, 1, 959, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_26_31" , 26, 6, 959, "RAZ", 1, 0, 0, 0ull},
- {"LTL_F_PE" , 32, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 959, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_RPF" , 35, 1, 959, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPE" , 36, 1, 959, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPF" , 37, 1, 959, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_38_63" , 38, 26, 959, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_IN" , 1, 8, 960, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 9, 4, 960, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 13, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ENB" , 14, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_ENB" , 15, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_ENB" , 16, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_EN" , 17, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_ENH" , 18, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_22" , 19, 4, 960, "RAZ", 0, 0, 0ull, 0ull},
- {"HST_MODE" , 23, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"DM_PULLD" , 24, 1, 960, "R/W", 0, 0, 1ull, 1ull},
- {"DP_PULLD" , 25, 1, 960, "R/W", 0, 0, 1ull, 1ull},
- {"TCLK" , 26, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"USBP_BIST" , 27, 1, 960, "R/W", 0, 0, 1ull, 1ull},
- {"USBC_END" , 28, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_BMODE" , 29, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"TXPREEMPHASISTUNE" , 30, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"SIDDQ" , 31, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_OUT" , 32, 4, 960, "RO", 1, 1, 0, 0},
- {"BIST_ERR" , 36, 1, 960, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 37, 1, 960, "RO", 0, 0, 0ull, 0ull},
- {"HSBIST" , 38, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 39, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 40, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"DRVVBUS" , 41, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 42, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"OTGDISABLE" , 43, 1, 960, "R/W", 0, 0, 1ull, 1ull},
- {"OTGTUNE" , 44, 3, 960, "R/W", 0, 0, 2ull, 2ull},
- {"COMPDISTUNE" , 47, 3, 960, "R/W", 0, 0, 2ull, 2ull},
- {"SQRXTUNE" , 50, 3, 960, "R/W", 0, 0, 3ull, 3ull},
- {"TXHSXVTUNE" , 53, 2, 960, "R/W", 0, 0, 0ull, 0ull},
- {"TXFSLSTUNE" , 55, 4, 960, "R/W", 0, 0, 3ull, 3ull},
- {"TXVREFTUNE" , 59, 4, 960, "R/W", 0, 0, 7ull, 7ull},
- {"TXRISETUNE" , 63, 1, 960, "R/W", 0, 0, 0ull, 0ull},
- {"ZIP_CTL" , 0, 4, 961, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 27, 961, "RO", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 961, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 962, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 962, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 962, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 962, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 962, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 963, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 963, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 963, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 964, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 964, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 964, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 964, "RO", 0, 0, 31744ull, 31744ull},
- {"RESERVED_48_63" , 48, 16, 964, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 14, 965, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 965, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 966, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 966, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 967, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn50xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_asx#_gmii_rx_clk_set" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 2, 0},
- {"cvmx_asx#_gmii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 2},
- {"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 4},
- {"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 6, 10},
- {"cvmx_asx#_mii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 2, 16},
- {"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 4, 18},
- {"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 22},
- {"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 2, 24},
- {"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 2, 26},
- {"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 6, 28},
- {"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 34},
- {"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 17, 2, 36},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 18, 2, 38},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 19, 2, 40},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 20, 2, 42},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 21, 2, 44},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 22, 19, 46},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 27, 2, 65},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 32, 19, 67},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 34, 2, 86},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 36, 19, 88},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 41, 19, 107},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 43, 2, 126},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 44, 2, 128},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 46, 2, 130},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 48, 2, 132},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 49, 2, 134},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 50, 2, 136},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 51, 1, 138},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 53, 3, 139},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 54, 2, 142},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 55, 4, 144},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 56, 2, 148},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 57, 3, 150},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 61, 7, 153},
- {"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 63, 6, 160},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 6, 166},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 7, 172},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 29, 179},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 29, 208},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 2, 237},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 76, 2, 239},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 84, 3, 241},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 85, 3, 244},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 86, 2, 247},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 87, 2, 249},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 88, 8, 251},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 89, 2, 259},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 90, 4, 261},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 265},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 92, 5, 267},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 95, 1, 272},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 98, 1, 273},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 1, 274},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 104, 1, 275},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 1, 276},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 110, 1, 277},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 2, 278},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 116, 4, 280},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 2, 284},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 11, 286},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 125, 11, 297},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 128, 2, 308},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 131, 21, 310},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 134, 21, 331},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 137, 2, 352},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 140, 2, 354},
- {"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 143, 4, 356},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 146, 2, 360},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 149, 2, 362},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 152, 2, 364},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 155, 2, 366},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 158, 2, 368},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 161, 2, 370},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 164, 2, 372},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 167, 2, 374},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 170, 2, 376},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 173, 2, 378},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 176, 4, 380},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 179, 2, 384},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 182, 2, 386},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 185, 2, 388},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 188, 4, 390},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 189, 2, 394},
- {"cvmx_gmx#_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 190, 4, 396},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 191, 2, 400},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 194, 3, 402},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 195, 5, 405},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 198, 2, 410},
- {"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 201, 2, 412},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 204, 3, 414},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 207, 2, 417},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 210, 2, 419},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 213, 2, 421},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 216, 2, 423},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 219, 2, 425},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 222, 2, 427},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 225, 2, 429},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 228, 2, 431},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 231, 2, 433},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 234, 2, 435},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 237, 2, 437},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 240, 2, 439},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 243, 2, 441},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 2, 443},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 249, 2, 445},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 2, 447},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 2, 449},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 451},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 2, 453},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 2, 455},
- {"cvmx_gmx#_tx_clk_msk#" , CVMX_CSR_DB_TYPE_RSL, 64, 265, 2, 457},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 267, 2, 459},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 268, 2, 461},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 269, 3, 463},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 270, 10, 466},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 271, 10, 476},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 272, 2, 486},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 2, 488},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 274, 6, 490},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 275, 2, 496},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 276, 2, 498},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 277, 2, 500},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 278, 7, 502},
- {"cvmx_gpio_boot_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 294, 3, 509},
- {"cvmx_gpio_dbg_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 295, 2, 512},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 296, 2, 514},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 297, 2, 516},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 298, 2, 518},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 299, 2, 520},
- {"cvmx_gpio_xbit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 300, 6, 522},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 19, 528},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 309, 6, 547},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 310, 3, 553},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 311, 5, 556},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 312, 5, 561},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 313, 1, 566},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 314, 1, 567},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 315, 7, 568},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 316, 7, 575},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 317, 5, 582},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 318, 5, 587},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 319, 1, 592},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 320, 1, 593},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 321, 2, 594},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 322, 2, 596},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 323, 2, 598},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 324, 2, 600},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 325, 17, 602},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 326, 2, 619},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 327, 1, 621},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 328, 15, 622},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 329, 11, 637},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 330, 11, 648},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 331, 2, 659},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 332, 2, 661},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 333, 2, 663},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 334, 3, 665},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 339, 2, 668},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 344, 6, 670},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 345, 5, 676},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 346, 6, 681},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 347, 7, 687},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 348, 2, 694},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 356, 2, 696},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 357, 3, 698},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 358, 5, 701},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 366, 3, 706},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 367, 2, 709},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 368, 2, 711},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 369, 2, 713},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 370, 8, 715},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 371, 5, 723},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 372, 8, 728},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 373, 12, 736},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 374, 9, 748},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 375, 5, 757},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 4, 762},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 377, 2, 766},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 378, 16, 768},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 379, 19, 784},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 380, 3, 803},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 381, 4, 806},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 382, 2, 810},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 386, 17, 812},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 387, 3, 829},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 2, 832},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 389, 3, 834},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 390, 2, 837},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 2, 839},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 2, 841},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 393, 7, 843},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 394, 5, 850},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 395, 3, 855},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 3, 858},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 397, 2, 861},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 398, 2, 863},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 399, 2, 865},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 6, 867},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 401, 14, 873},
- {"cvmx_lmc#_bist_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 402, 2, 887},
- {"cvmx_lmc#_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 403, 6, 889},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 7, 895},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 405, 20, 902},
- {"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 406, 5, 922},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 2, 927},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 929},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 409, 18, 931},
- {"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 410, 6, 949},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 411, 5, 955},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 5, 960},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 413, 6, 965},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 414, 2, 971},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 415, 2, 973},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 14, 975},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 417, 10, 989},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 418, 2, 999},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 419, 2, 1001},
- {"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 420, 13, 1003},
- {"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 421, 6, 1016},
- {"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 422, 6, 1022},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 423, 9, 1028},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 9, 1037},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 425, 7, 1046},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 426, 3, 1053},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 427, 3, 1056},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 428, 3, 1059},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 429, 3, 1062},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 430, 5, 1065},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 1, 1070},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 433, 12, 1071},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 441, 13, 1083},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 449, 4, 1096},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 450, 1, 1100},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 454, 2, 1101},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 455, 2, 1103},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 13, 1105},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 457, 8, 1118},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 458, 4, 1126},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 459, 1, 1130},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 3, 1131},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 461, 2, 1134},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 462, 6, 1136},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 8, 1142},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 4, 1150},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 465, 2, 1154},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 466, 2, 1156},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 467, 13, 1158},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 12, 1171},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 469, 3, 1183},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 3, 1186},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 2, 1189},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 473, 2, 1191},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 475, 2, 1193},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 477, 7, 1195},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 479, 2, 1202},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 481, 7, 1204},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 483, 4, 1211},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 485, 8, 1215},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 9, 1223},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 489, 7, 1232},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 9, 1239},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 493, 2, 1248},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 495, 2, 1250},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 497, 4, 1252},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 2, 1256},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 501, 2, 1258},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 2, 1260},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 505, 4, 1262},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 2, 1266},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 509, 2, 1268},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 511, 2, 1270},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 513, 2, 1272},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 2, 1274},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 2, 1276},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 6, 1278},
- {"cvmx_mpi_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 521, 14, 1284},
- {"cvmx_mpi_dat#" , CVMX_CSR_DB_TYPE_NCB, 64, 522, 2, 1298},
- {"cvmx_mpi_sts" , CVMX_CSR_DB_TYPE_NCB, 64, 531, 4, 1300},
- {"cvmx_mpi_tx" , CVMX_CSR_DB_TYPE_NCB, 64, 532, 6, 1304},
- {"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 533, 2, 1310},
- {"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 535, 2, 1312},
- {"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 537, 20, 1314},
- {"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 538, 3, 1334},
- {"cvmx_npi_comp_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 540, 3, 1337},
- {"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 541, 18, 1340},
- {"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 542, 2, 1358},
- {"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 543, 13, 1360},
- {"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 544, 3, 1373},
- {"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 545, 3, 1376},
- {"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 546, 3, 1379},
- {"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 547, 3, 1382},
- {"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 548, 2, 1385},
- {"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 549, 2, 1387},
- {"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 550, 10, 1389},
- {"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 551, 54, 1399},
- {"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 552, 54, 1453},
- {"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 553, 2, 1507},
- {"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 554, 2, 1509},
- {"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 555, 10, 1511},
- {"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 559, 1, 1521},
- {"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 560, 2, 1522},
- {"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 562, 25, 1524},
- {"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 563, 3, 1549},
- {"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 565, 2, 1552},
- {"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 567, 3, 1554},
- {"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 569, 3, 1557},
- {"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 571, 3, 1560},
- {"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 572, 7, 1563},
- {"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 573, 2, 1570},
- {"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 574, 13, 1572},
- {"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 575, 13, 1585},
- {"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 576, 3, 1598},
- {"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 577, 29, 1601},
- {"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 578, 2, 1630},
- {"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 580, 2, 1632},
- {"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 581, 5, 1634},
- {"cvmx_pci_bist_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 613, 11, 1639},
- {"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 614, 2, 1650},
- {"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 615, 24, 1652},
- {"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 616, 2, 1676},
- {"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 617, 7, 1678},
- {"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 618, 5, 1685},
- {"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 619, 1, 1690},
- {"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 620, 5, 1691},
- {"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 621, 1, 1696},
- {"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 622, 4, 1697},
- {"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 623, 2, 1701},
- {"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 624, 1, 1703},
- {"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 625, 2, 1704},
- {"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 626, 4, 1706},
- {"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 627, 2, 1710},
- {"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 628, 4, 1712},
- {"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 629, 16, 1716},
- {"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 630, 1, 1732},
- {"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 631, 1, 1733},
- {"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 632, 18, 1734},
- {"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 633, 1, 1752},
- {"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 634, 1, 1753},
- {"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 635, 7, 1754},
- {"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 636, 7, 1761},
- {"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 637, 13, 1768},
- {"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 638, 10, 1781},
- {"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 639, 10, 1791},
- {"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 640, 7, 1801},
- {"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 641, 2, 1808},
- {"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 642, 1, 1810},
- {"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 643, 2, 1811},
- {"cvmx_pci_cnt_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 644, 6, 1813},
- {"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 645, 22, 1819},
- {"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 646, 2, 1841},
- {"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 648, 1, 1843},
- {"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 650, 1, 1844},
- {"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 652, 1, 1845},
- {"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 654, 1, 1846},
- {"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 656, 33, 1847},
- {"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 657, 33, 1880},
- {"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 658, 33, 1913},
- {"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 659, 33, 1946},
- {"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 660, 2, 1979},
- {"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 661, 2, 1981},
- {"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 663, 1, 1983},
- {"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 665, 1, 1984},
- {"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 667, 1, 1985},
- {"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 669, 3, 1986},
- {"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 670, 3, 1989},
- {"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 671, 3, 1992},
- {"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 672, 3, 1995},
- {"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 673, 2, 1998},
- {"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 674, 2, 2000},
- {"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 675, 4, 2002},
- {"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 676, 1, 2006},
- {"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 677, 4, 2007},
- {"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 678, 1, 2011},
- {"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 679, 2, 2012},
- {"cvmx_pcm#_dma_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 680, 12, 2014},
- {"cvmx_pcm#_int_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 684, 9, 2026},
- {"cvmx_pcm#_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 688, 9, 2035},
- {"cvmx_pcm#_rxaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 692, 2, 2044},
- {"cvmx_pcm#_rxcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 696, 2, 2046},
- {"cvmx_pcm#_rxmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 700, 1, 2048},
- {"cvmx_pcm#_rxmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 704, 1, 2049},
- {"cvmx_pcm#_rxmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 708, 1, 2050},
- {"cvmx_pcm#_rxmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 712, 1, 2051},
- {"cvmx_pcm#_rxmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 716, 1, 2052},
- {"cvmx_pcm#_rxmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 720, 1, 2053},
- {"cvmx_pcm#_rxmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 724, 1, 2054},
- {"cvmx_pcm#_rxmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 728, 1, 2055},
- {"cvmx_pcm#_rxstart" , CVMX_CSR_DB_TYPE_NCB, 64, 732, 3, 2056},
- {"cvmx_pcm#_tdm_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 736, 6, 2059},
- {"cvmx_pcm#_tdm_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 740, 1, 2065},
- {"cvmx_pcm#_txaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 744, 3, 2066},
- {"cvmx_pcm#_txcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 748, 2, 2069},
- {"cvmx_pcm#_txmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 752, 1, 2071},
- {"cvmx_pcm#_txmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 756, 1, 2072},
- {"cvmx_pcm#_txmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 760, 1, 2073},
- {"cvmx_pcm#_txmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 764, 1, 2074},
- {"cvmx_pcm#_txmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 768, 1, 2075},
- {"cvmx_pcm#_txmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 772, 1, 2076},
- {"cvmx_pcm#_txmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 776, 1, 2077},
- {"cvmx_pcm#_txmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 780, 1, 2078},
- {"cvmx_pcm#_txstart" , CVMX_CSR_DB_TYPE_NCB, 64, 784, 3, 2079},
- {"cvmx_pcm_clk#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 788, 12, 2082},
- {"cvmx_pcm_clk#_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 790, 1, 2094},
- {"cvmx_pcm_clk#_gen" , CVMX_CSR_DB_TYPE_NCB, 64, 792, 3, 2095},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 794, 2, 2098},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 4, 2100},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 799, 3, 2104},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 801, 8, 2107},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 16, 2115},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 13, 2131},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 13, 2144},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 805, 2, 2157},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 27, 2159},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 811, 25, 2186},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 2, 2211},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 880, 2, 2213},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 888, 9, 2215},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 896, 2, 2224},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 897, 2, 2226},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 898, 2, 2228},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 903, 2, 2230},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 908, 2, 2232},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 913, 2, 2234},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 918, 2, 2236},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 2, 2238},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 928, 2, 2240},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 933, 2, 2242},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 938, 2, 2244},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 943, 2, 2246},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 948, 2, 2248},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 949, 2, 2250},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 954, 2, 2252},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 959, 2, 2254},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 964, 2, 2256},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 2, 2258},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 3, 2260},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 3, 2263},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 1031, 2, 2266},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 1032, 2, 2268},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1033, 4, 2270},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1034, 5, 2274},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 4, 2279},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 1036, 8, 2283},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 1037, 4, 2291},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 5, 2295},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1039, 5, 2300},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 1, 2305},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 1041, 18, 2306},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 4, 2324},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 1043, 2, 2328},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 6, 2330},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 1045, 7, 2336},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 1046, 4, 2343},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 1047, 9, 2347},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1048, 5, 2356},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1049, 15, 2361},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1050, 4, 2376},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 1, 2380},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1052, 1, 2381},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 1, 2382},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1054, 1, 2383},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 4, 2384},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1056, 5, 2388},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 3, 2393},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1058, 4, 2396},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 2, 2400},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 1060, 3, 2402},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 3, 2405},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 1062, 12, 2408},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1063, 2, 2420},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 1064, 13, 2422},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1065, 3, 2435},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1066, 2, 2438},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1074, 2, 2440},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1075, 2, 2442},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 1076, 2, 2444},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 1077, 2, 2446},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 1078, 10, 2448},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 1080, 5, 2458},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1088, 10, 2463},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1096, 2, 2473},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1097, 2, 2475},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1098, 2, 2477},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1106, 3, 2479},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1107, 6, 2482},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1123, 5, 2488},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1124, 7, 2493},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1140, 2, 2500},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1156, 3, 2502},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1157, 7, 2505},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 1158, 10, 2512},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1159, 6, 2522},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1160, 2, 2528},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1161, 4, 2530},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1162, 4, 2534},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1163, 6, 2538},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1164, 3, 2544},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1165, 5, 2547},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 1166, 4, 2552},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 6, 2556},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 4, 2562},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 2, 2566},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 4, 2568},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 2, 2572},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 3, 2574},
- {"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 1173, 2, 2577},
- {"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1174, 2, 2579},
- {"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1175, 8, 2581},
- {"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1176, 11, 2589},
- {"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1177, 15, 2600},
- {"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1182, 8, 2615},
- {"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1187, 8, 2623},
- {"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1188, 4, 2631},
- {"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1193, 15, 2635},
- {"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1198, 6, 2650},
- {"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1203, 6, 2656},
- {"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1204, 4, 2662},
- {"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1209, 2, 2666},
- {"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1213, 6, 2668},
- {"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 1214, 4, 2674},
- {"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 1215, 1, 2678},
- {"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 1216, 1, 2679},
- {"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 1217, 1, 2680},
- {"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1218, 7, 2681},
- {"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 1219, 1, 2688},
- {"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 1220, 14, 2689},
- {"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 1221, 10, 2703},
- {"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 1222, 14, 2713},
- {"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1223, 32, 2727},
- {"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1224, 32, 2759},
- {"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1225, 2, 2791},
- {"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1226, 4, 2793},
- {"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1227, 13, 2797},
- {"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 1228, 10, 2810},
- {"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1229, 10, 2820},
- {"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1230, 2, 2830},
- {"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 1231, 6, 2832},
- {"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 1232, 5, 2838},
- {"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 1233, 6, 2843},
- {"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 1234, 5, 2849},
- {"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 1235, 1, 2854},
- {"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1236, 13, 2855},
- {"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 1237, 2, 2868},
- {"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1238, 2, 2870},
- {"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 1239, 11, 2872},
- {"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1247, 3, 2883},
- {"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1248, 12, 2886},
- {"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 1256, 12, 2898},
- {"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 1264, 6, 2910},
- {"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1272, 4, 2916},
- {"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 1280, 2, 2920},
- {"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 1281, 2, 2922},
- {"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 1282, 15, 2924},
- {"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1283, 2, 2939},
- {"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1284, 3, 2941},
- {"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 1285, 1, 2944},
- {"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1293, 6, 2945},
- {"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1294, 8, 2951},
- {"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1295, 15, 2959},
- {"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1296, 6, 2974},
- {"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1297, 2, 2980},
- {"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1298, 2, 2982},
- {"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1299, 2, 2984},
- {"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1300, 2, 2986},
- {"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1301, 2, 2988},
- {"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1302, 2, 2990},
- {"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1303, 2, 2992},
- {"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1304, 2, 2994},
- {"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1305, 2, 2996},
- {"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1306, 2, 2998},
- {"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1307, 2, 3000},
- {"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1308, 2, 3002},
- {"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1309, 2, 3004},
- {"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1310, 2, 3006},
- {"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1311, 2, 3008},
- {"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1312, 2, 3010},
- {"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 1313, 7, 3012},
- {"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1314, 34, 3019},
- {"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1315, 34, 3053},
- {"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1316, 35, 3087},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"ASX0_GMII_RX_CLK_SET" , 0x11800b0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"ASX0_GMII_RX_DAT_SET" , 0x11800b0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"ASX0_INT_EN" , 0x11800b0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"ASX0_INT_REG" , 0x11800b0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"ASX0_MII_RX_DAT_SET" , 0x11800b0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"ASX0_PRT_LOOP" , 0x11800b0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"ASX0_RX_CLK_SET000" , 0x11800b0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_RX_CLK_SET001" , 0x11800b0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_RX_CLK_SET002" , 0x11800b0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"ASX0_RX_PRT_EN" , 0x11800b0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"ASX0_TX_CLK_SET000" , 0x11800b0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_TX_CLK_SET001" , 0x11800b0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_TX_CLK_SET002" , 0x11800b0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"ASX0_TX_COMP_BYP" , 0x11800b0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"ASX0_TX_HI_WATER000" , 0x11800b0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX0_TX_HI_WATER001" , 0x11800b0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX0_TX_HI_WATER002" , 0x11800b0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"ASX0_TX_PRT_EN" , 0x11800b0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"DBG_DATA" , 0x11f00000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
- {"GMX0_RX_TX_STATUS" , 0x11800080007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
- {"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_TX001_CLK" , 0x1180008000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_TX_CLK_MSK000" , 0x1180008000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_TX_CLK_MSK001" , 0x1180008000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"GPIO_BOOT_ENA" , 0x10700000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"GPIO_DBG_ENA" , 0x10700000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"GPIO_XBIT_CFG16" , 0x1070000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"GPIO_XBIT_CFG17" , 0x1070000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"GPIO_XBIT_CFG18" , 0x1070000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"GPIO_XBIT_CFG19" , 0x1070000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"GPIO_XBIT_CFG20" , 0x1070000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"GPIO_XBIT_CFG21" , 0x1070000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"GPIO_XBIT_CFG22" , 0x1070000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"GPIO_XBIT_CFG23" , 0x1070000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"LMC0_BIST_CTL" , 0x11800880000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"LMC0_BIST_RESULT" , 0x11800880000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
- {"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"LMC0_PLL_CTL" , 0x11800880000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"LMC0_PLL_STATUS" , 0x11800880000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"LMC0_RODT_COMP_CTL" , 0x11800880000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"MPI_CFG" , 0x1070000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"MPI_DAT0" , 0x1070000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"MPI_DAT1" , 0x1070000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"MPI_DAT2" , 0x1070000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"MPI_DAT3" , 0x1070000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"MPI_DAT4" , 0x10700000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"MPI_DAT5" , 0x10700000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"MPI_DAT6" , 0x10700000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"MPI_DAT7" , 0x10700000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"MPI_DAT8" , 0x10700000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"MPI_STS" , 0x1070000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 278},
- {"MPI_TX" , 0x1070000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 279},
- {"NPI_BASE_ADDR_INPUT0" , 0x11f0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 280},
- {"NPI_BASE_ADDR_INPUT1" , 0x11f0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 280},
- {"NPI_BASE_ADDR_OUTPUT0" , 0x11f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 281},
- {"NPI_BASE_ADDR_OUTPUT1" , 0x11f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 281},
- {"NPI_BIST_STATUS" , 0x11f00000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 282},
- {"NPI_BUFF_SIZE_OUTPUT0" , 0x11f00000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 283},
- {"NPI_BUFF_SIZE_OUTPUT1" , 0x11f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 283},
- {"NPI_COMP_CTL" , 0x11f0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 284},
- {"NPI_CTL_STATUS" , 0x11f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 285},
- {"NPI_DBG_SELECT" , 0x11f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"NPI_DMA_CONTROL" , 0x11f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 287},
- {"NPI_DMA_HIGHP_COUNTS" , 0x11f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 288},
- {"NPI_DMA_HIGHP_NADDR" , 0x11f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"NPI_DMA_LOWP_COUNTS" , 0x11f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"NPI_DMA_LOWP_NADDR" , 0x11f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
- {"NPI_HIGHP_DBELL" , 0x11f0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"NPI_HIGHP_IBUFF_SADDR" , 0x11f0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
- {"NPI_INPUT_CONTROL" , 0x11f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 294},
- {"NPI_INT_ENB" , 0x11f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"NPI_INT_SUM" , 0x11f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
- {"NPI_LOWP_DBELL" , 0x11f0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 297},
- {"NPI_LOWP_IBUFF_SADDR" , 0x11f0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 298},
- {"NPI_MEM_ACCESS_SUBID3" , 0x11f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
- {"NPI_MEM_ACCESS_SUBID4" , 0x11f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
- {"NPI_MEM_ACCESS_SUBID5" , 0x11f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
- {"NPI_MEM_ACCESS_SUBID6" , 0x11f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
- {"NPI_MSI_RCV" , 0x11f0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 300},
- {"NPI_NUM_DESC_OUTPUT0" , 0x11f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
- {"NPI_NUM_DESC_OUTPUT1" , 0x11f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
- {"NPI_OUTPUT_CONTROL" , 0x11f0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 302},
- {"NPI_P0_DBPAIR_ADDR" , 0x11f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 303},
- {"NPI_P1_DBPAIR_ADDR" , 0x11f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 303},
- {"NPI_P0_INSTR_ADDR" , 0x11f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 304},
- {"NPI_P1_INSTR_ADDR" , 0x11f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 304},
- {"NPI_P0_INSTR_CNTS" , 0x11f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 305},
- {"NPI_P1_INSTR_CNTS" , 0x11f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 305},
- {"NPI_P0_PAIR_CNTS" , 0x11f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 306},
- {"NPI_P1_PAIR_CNTS" , 0x11f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 306},
- {"NPI_PCI_BURST_SIZE" , 0x11f00000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
- {"NPI_PCI_INT_ARB_CFG" , 0x11f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 308},
- {"NPI_PCI_READ_CMD" , 0x11f0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 309},
- {"NPI_PORT32_INSTR_HDR" , 0x11f00000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 310},
- {"NPI_PORT33_INSTR_HDR" , 0x11f0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 311},
- {"NPI_PORT_BP_CONTROL" , 0x11f00000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 312},
- {"NPI_RSL_INT_BLOCKS" , 0x11f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 313},
- {"NPI_SIZE_INPUT0" , 0x11f0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 314},
- {"NPI_SIZE_INPUT1" , 0x11f0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 314},
- {"NPI_WIN_READ_TO" , 0x11f00000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 315},
- {"PCI_BAR1_INDEX0" , 0x11f0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX1" , 0x11f0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX2" , 0x11f0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX3" , 0x11f000000110cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX4" , 0x11f0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX5" , 0x11f0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX6" , 0x11f0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX7" , 0x11f000000111cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX8" , 0x11f0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX9" , 0x11f0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX10" , 0x11f0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX11" , 0x11f000000112cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX12" , 0x11f0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX13" , 0x11f0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX14" , 0x11f0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX15" , 0x11f000000113cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX16" , 0x11f0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX17" , 0x11f0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX18" , 0x11f0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX19" , 0x11f000000114cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX20" , 0x11f0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX21" , 0x11f0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX22" , 0x11f0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX23" , 0x11f000000115cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX24" , 0x11f0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX25" , 0x11f0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX26" , 0x11f0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX27" , 0x11f000000116cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX28" , 0x11f0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX29" , 0x11f0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX30" , 0x11f0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BAR1_INDEX31" , 0x11f000000117cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
- {"PCI_BIST_REG" , 0x11f00000011c0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 317},
- {"PCI_CFG00" , 0x11f0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 318},
- {"PCI_CFG01" , 0x11f0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 319},
- {"PCI_CFG02" , 0x11f0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 320},
- {"PCI_CFG03" , 0x11f000000180cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 321},
- {"PCI_CFG04" , 0x11f0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 322},
- {"PCI_CFG05" , 0x11f0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 323},
- {"PCI_CFG06" , 0x11f0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 324},
- {"PCI_CFG07" , 0x11f000000181cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 325},
- {"PCI_CFG08" , 0x11f0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 326},
- {"PCI_CFG09" , 0x11f0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 327},
- {"PCI_CFG10" , 0x11f0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 328},
- {"PCI_CFG11" , 0x11f000000182cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 329},
- {"PCI_CFG12" , 0x11f0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 330},
- {"PCI_CFG13" , 0x11f0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 331},
- {"PCI_CFG15" , 0x11f000000183cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 332},
- {"PCI_CFG16" , 0x11f0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 333},
- {"PCI_CFG17" , 0x11f0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 334},
- {"PCI_CFG18" , 0x11f0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 335},
- {"PCI_CFG19" , 0x11f000000184cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 336},
- {"PCI_CFG20" , 0x11f0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 337},
- {"PCI_CFG21" , 0x11f0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 338},
- {"PCI_CFG22" , 0x11f0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 339},
- {"PCI_CFG56" , 0x11f00000018e0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 340},
- {"PCI_CFG57" , 0x11f00000018e4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 341},
- {"PCI_CFG58" , 0x11f00000018e8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 342},
- {"PCI_CFG59" , 0x11f00000018ecull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 343},
- {"PCI_CFG60" , 0x11f00000018f0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 344},
- {"PCI_CFG61" , 0x11f00000018f4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 345},
- {"PCI_CFG62" , 0x11f00000018f8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 346},
- {"PCI_CFG63" , 0x11f00000018fcull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 347},
- {"PCI_CNT_REG" , 0x11f00000011b8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 348},
- {"PCI_CTL_STATUS_2" , 0x11f000000118cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 349},
- {"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 350},
- {"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 350},
- {"PCI_DMA_CNT0" , 0xa0ull, CVMX_CSR_DB_TYPE_PCI, 32, 351},
- {"PCI_DMA_CNT1" , 0xa8ull, CVMX_CSR_DB_TYPE_PCI, 32, 351},
- {"PCI_DMA_INT_LEV0" , 0xa4ull, CVMX_CSR_DB_TYPE_PCI, 32, 352},
- {"PCI_DMA_INT_LEV1" , 0xacull, CVMX_CSR_DB_TYPE_PCI, 32, 352},
- {"PCI_DMA_TIME0" , 0xb0ull, CVMX_CSR_DB_TYPE_PCI, 32, 353},
- {"PCI_DMA_TIME1" , 0xb4ull, CVMX_CSR_DB_TYPE_PCI, 32, 353},
- {"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 354},
- {"PCI_INSTR_COUNT1" , 0x8cull, CVMX_CSR_DB_TYPE_PCI, 32, 354},
- {"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 355},
- {"PCI_INT_ENB2" , 0x11f00000011a0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 356},
- {"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 357},
- {"PCI_INT_SUM2" , 0x11f0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 358},
- {"PCI_MSI_RCV" , 0xf0ull, CVMX_CSR_DB_TYPE_PCI, 32, 359},
- {"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 360},
- {"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 360},
- {"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 361},
- {"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 361},
- {"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 362},
- {"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 362},
- {"PCI_PKTS_SENT_TIME0" , 0x4cull, CVMX_CSR_DB_TYPE_PCI, 32, 363},
- {"PCI_PKTS_SENT_TIME1" , 0x5cull, CVMX_CSR_DB_TYPE_PCI, 32, 363},
- {"PCI_READ_CMD_6" , 0x11f0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 364},
- {"PCI_READ_CMD_C" , 0x11f0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 365},
- {"PCI_READ_CMD_E" , 0x11f0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 366},
- {"PCI_READ_TIMEOUT" , 0x11f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
- {"PCI_SCM_REG" , 0x11f00000011a8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 368},
- {"PCI_TSR_REG" , 0x11f00000011b0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 369},
- {"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 370},
- {"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 371},
- {"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 372},
- {"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 373},
- {"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 374},
- {"PCM0_DMA_CFG" , 0x1070000010018ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"PCM1_DMA_CFG" , 0x1070000014018ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"PCM2_DMA_CFG" , 0x1070000018018ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"PCM3_DMA_CFG" , 0x107000001c018ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"PCM0_INT_ENA" , 0x1070000010020ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"PCM1_INT_ENA" , 0x1070000014020ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"PCM2_INT_ENA" , 0x1070000018020ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"PCM3_INT_ENA" , 0x107000001c020ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"PCM0_INT_SUM" , 0x1070000010028ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"PCM1_INT_SUM" , 0x1070000014028ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"PCM2_INT_SUM" , 0x1070000018028ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"PCM3_INT_SUM" , 0x107000001c028ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"PCM0_RXADDR" , 0x1070000010068ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"PCM1_RXADDR" , 0x1070000014068ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"PCM2_RXADDR" , 0x1070000018068ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"PCM3_RXADDR" , 0x107000001c068ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"PCM0_RXCNT" , 0x1070000010060ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"PCM1_RXCNT" , 0x1070000014060ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"PCM2_RXCNT" , 0x1070000018060ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"PCM3_RXCNT" , 0x107000001c060ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"PCM0_RXMSK0" , 0x10700000100c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"PCM1_RXMSK0" , 0x10700000140c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"PCM2_RXMSK0" , 0x10700000180c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"PCM3_RXMSK0" , 0x107000001c0c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"PCM0_RXMSK1" , 0x10700000100c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM1_RXMSK1" , 0x10700000140c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM2_RXMSK1" , 0x10700000180c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM3_RXMSK1" , 0x107000001c0c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"PCM0_RXMSK2" , 0x10700000100d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM1_RXMSK2" , 0x10700000140d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM2_RXMSK2" , 0x10700000180d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM3_RXMSK2" , 0x107000001c0d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"PCM0_RXMSK3" , 0x10700000100d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM1_RXMSK3" , 0x10700000140d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM2_RXMSK3" , 0x10700000180d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM3_RXMSK3" , 0x107000001c0d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"PCM0_RXMSK4" , 0x10700000100e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM1_RXMSK4" , 0x10700000140e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM2_RXMSK4" , 0x10700000180e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM3_RXMSK4" , 0x107000001c0e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"PCM0_RXMSK5" , 0x10700000100e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM1_RXMSK5" , 0x10700000140e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM2_RXMSK5" , 0x10700000180e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM3_RXMSK5" , 0x107000001c0e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"PCM0_RXMSK6" , 0x10700000100f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM1_RXMSK6" , 0x10700000140f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM2_RXMSK6" , 0x10700000180f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM3_RXMSK6" , 0x107000001c0f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"PCM0_RXMSK7" , 0x10700000100f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM1_RXMSK7" , 0x10700000140f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM2_RXMSK7" , 0x10700000180f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM3_RXMSK7" , 0x107000001c0f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"PCM0_RXSTART" , 0x1070000010058ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM1_RXSTART" , 0x1070000014058ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM2_RXSTART" , 0x1070000018058ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM3_RXSTART" , 0x107000001c058ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"PCM0_TDM_CFG" , 0x1070000010010ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"PCM1_TDM_CFG" , 0x1070000014010ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"PCM2_TDM_CFG" , 0x1070000018010ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"PCM3_TDM_CFG" , 0x107000001c010ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"PCM0_TDM_DBG" , 0x1070000010030ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"PCM1_TDM_DBG" , 0x1070000014030ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"PCM2_TDM_DBG" , 0x1070000018030ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"PCM3_TDM_DBG" , 0x107000001c030ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"PCM0_TXADDR" , 0x1070000010050ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"PCM1_TXADDR" , 0x1070000014050ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"PCM2_TXADDR" , 0x1070000018050ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"PCM3_TXADDR" , 0x107000001c050ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"PCM0_TXCNT" , 0x1070000010048ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
- {"PCM1_TXCNT" , 0x1070000014048ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
- {"PCM2_TXCNT" , 0x1070000018048ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
- {"PCM3_TXCNT" , 0x107000001c048ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
- {"PCM0_TXMSK0" , 0x1070000010080ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
- {"PCM1_TXMSK0" , 0x1070000014080ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
- {"PCM2_TXMSK0" , 0x1070000018080ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
- {"PCM3_TXMSK0" , 0x107000001c080ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
- {"PCM0_TXMSK1" , 0x1070000010088ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
- {"PCM1_TXMSK1" , 0x1070000014088ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
- {"PCM2_TXMSK1" , 0x1070000018088ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
- {"PCM3_TXMSK1" , 0x107000001c088ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
- {"PCM0_TXMSK2" , 0x1070000010090ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
- {"PCM1_TXMSK2" , 0x1070000014090ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
- {"PCM2_TXMSK2" , 0x1070000018090ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
- {"PCM3_TXMSK2" , 0x107000001c090ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
- {"PCM0_TXMSK3" , 0x1070000010098ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
- {"PCM1_TXMSK3" , 0x1070000014098ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
- {"PCM2_TXMSK3" , 0x1070000018098ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
- {"PCM3_TXMSK3" , 0x107000001c098ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
- {"PCM0_TXMSK4" , 0x10700000100a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
- {"PCM1_TXMSK4" , 0x10700000140a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
- {"PCM2_TXMSK4" , 0x10700000180a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
- {"PCM3_TXMSK4" , 0x107000001c0a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
- {"PCM0_TXMSK5" , 0x10700000100a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
- {"PCM1_TXMSK5" , 0x10700000140a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
- {"PCM2_TXMSK5" , 0x10700000180a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
- {"PCM3_TXMSK5" , 0x107000001c0a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
- {"PCM0_TXMSK6" , 0x10700000100b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
- {"PCM1_TXMSK6" , 0x10700000140b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
- {"PCM2_TXMSK6" , 0x10700000180b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
- {"PCM3_TXMSK6" , 0x107000001c0b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
- {"PCM0_TXMSK7" , 0x10700000100b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"PCM1_TXMSK7" , 0x10700000140b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"PCM2_TXMSK7" , 0x10700000180b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"PCM3_TXMSK7" , 0x107000001c0b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"PCM0_TXSTART" , 0x1070000010040ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"PCM1_TXSTART" , 0x1070000014040ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"PCM2_TXSTART" , 0x1070000018040ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"PCM3_TXSTART" , 0x107000001c040ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"PCM_CLK0_CFG" , 0x1070000010000ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"PCM_CLK1_CFG" , 0x1070000014000ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"PCM_CLK0_DBG" , 0x1070000010038ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"PCM_CLK1_DBG" , 0x1070000014038ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"PCM_CLK0_GEN" , 0x1070000010008ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"PCM_CLK1_GEN" , 0x1070000014008ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"PIP_FRM_LEN_CHK1" , 0x11800a0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 471},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 472},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 474},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 476},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 477},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 478},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 478},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 482},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"USBC0_DAINT" , 0x16f0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 506},
- {"USBC0_DAINTMSK" , 0x16f001000081cull, CVMX_CSR_DB_TYPE_NCB, 32, 507},
- {"USBC0_DCFG" , 0x16f0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 508},
- {"USBC0_DCTL" , 0x16f0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 509},
- {"USBC0_DIEPCTL000" , 0x16f0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
- {"USBC0_DIEPCTL001" , 0x16f0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
- {"USBC0_DIEPCTL002" , 0x16f0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
- {"USBC0_DIEPCTL003" , 0x16f0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
- {"USBC0_DIEPCTL004" , 0x16f0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
- {"USBC0_DIEPINT000" , 0x16f0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
- {"USBC0_DIEPINT001" , 0x16f0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
- {"USBC0_DIEPINT002" , 0x16f0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
- {"USBC0_DIEPINT003" , 0x16f0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
- {"USBC0_DIEPINT004" , 0x16f0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
- {"USBC0_DIEPMSK" , 0x16f0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 512},
- {"USBC0_DIEPTSIZ000" , 0x16f0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
- {"USBC0_DIEPTSIZ001" , 0x16f0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
- {"USBC0_DIEPTSIZ002" , 0x16f0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
- {"USBC0_DIEPTSIZ003" , 0x16f0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
- {"USBC0_DIEPTSIZ004" , 0x16f0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
- {"USBC0_DOEPCTL000" , 0x16f0010000b00ull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
- {"USBC0_DOEPCTL001" , 0x16f0010000b20ull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
- {"USBC0_DOEPCTL002" , 0x16f0010000b40ull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
- {"USBC0_DOEPCTL003" , 0x16f0010000b60ull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
- {"USBC0_DOEPCTL004" , 0x16f0010000b80ull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
- {"USBC0_DOEPINT000" , 0x16f0010000b08ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
- {"USBC0_DOEPINT001" , 0x16f0010000b28ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
- {"USBC0_DOEPINT002" , 0x16f0010000b48ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
- {"USBC0_DOEPINT003" , 0x16f0010000b68ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
- {"USBC0_DOEPINT004" , 0x16f0010000b88ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
- {"USBC0_DOEPMSK" , 0x16f0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 516},
- {"USBC0_DOEPTSIZ000" , 0x16f0010000b10ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
- {"USBC0_DOEPTSIZ001" , 0x16f0010000b30ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
- {"USBC0_DOEPTSIZ002" , 0x16f0010000b50ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
- {"USBC0_DOEPTSIZ003" , 0x16f0010000b70ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
- {"USBC0_DOEPTSIZ004" , 0x16f0010000b90ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
- {"USBC0_DPTXFSIZ001" , 0x16f0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 518},
- {"USBC0_DPTXFSIZ002" , 0x16f0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 518},
- {"USBC0_DPTXFSIZ003" , 0x16f001000010cull, CVMX_CSR_DB_TYPE_NCB, 32, 518},
- {"USBC0_DPTXFSIZ004" , 0x16f0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 518},
- {"USBC0_DSTS" , 0x16f0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 519},
- {"USBC0_DTKNQR1" , 0x16f0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 520},
- {"USBC0_DTKNQR2" , 0x16f0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 521},
- {"USBC0_DTKNQR3" , 0x16f0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 522},
- {"USBC0_DTKNQR4" , 0x16f0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 523},
- {"USBC0_GAHBCFG" , 0x16f0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 524},
- {"USBC0_GHWCFG1" , 0x16f0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 525},
- {"USBC0_GHWCFG2" , 0x16f0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 526},
- {"USBC0_GHWCFG3" , 0x16f001000004cull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
- {"USBC0_GHWCFG4" , 0x16f0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 528},
- {"USBC0_GINTMSK" , 0x16f0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
- {"USBC0_GINTSTS" , 0x16f0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
- {"USBC0_GNPTXFSIZ" , 0x16f0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
- {"USBC0_GNPTXSTS" , 0x16f001000002cull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
- {"USBC0_GOTGCTL" , 0x16f0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 533},
- {"USBC0_GOTGINT" , 0x16f0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
- {"USBC0_GRSTCTL" , 0x16f0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
- {"USBC0_GRXFSIZ" , 0x16f0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
- {"USBC0_GRXSTSPD" , 0x16f0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 537},
- {"USBC0_GRXSTSPH" , 0x16f0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
- {"USBC0_GRXSTSRD" , 0x16f001004001cull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
- {"USBC0_GRXSTSRH" , 0x16f001000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 540},
- {"USBC0_GSNPSID" , 0x16f0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 541},
- {"USBC0_GUSBCFG" , 0x16f001000000cull, CVMX_CSR_DB_TYPE_NCB, 32, 542},
- {"USBC0_HAINT" , 0x16f0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 543},
- {"USBC0_HAINTMSK" , 0x16f0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 544},
- {"USBC0_HCCHAR000" , 0x16f0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
- {"USBC0_HCCHAR001" , 0x16f0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
- {"USBC0_HCCHAR002" , 0x16f0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
- {"USBC0_HCCHAR003" , 0x16f0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
- {"USBC0_HCCHAR004" , 0x16f0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
- {"USBC0_HCCHAR005" , 0x16f00100005a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
- {"USBC0_HCCHAR006" , 0x16f00100005c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
- {"USBC0_HCCHAR007" , 0x16f00100005e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
- {"USBC0_HCFG" , 0x16f0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 546},
- {"USBC0_HCINT000" , 0x16f0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
- {"USBC0_HCINT001" , 0x16f0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
- {"USBC0_HCINT002" , 0x16f0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
- {"USBC0_HCINT003" , 0x16f0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
- {"USBC0_HCINT004" , 0x16f0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
- {"USBC0_HCINT005" , 0x16f00100005a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
- {"USBC0_HCINT006" , 0x16f00100005c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
- {"USBC0_HCINT007" , 0x16f00100005e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
- {"USBC0_HCINTMSK000" , 0x16f001000050cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
- {"USBC0_HCINTMSK001" , 0x16f001000052cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
- {"USBC0_HCINTMSK002" , 0x16f001000054cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
- {"USBC0_HCINTMSK003" , 0x16f001000056cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
- {"USBC0_HCINTMSK004" , 0x16f001000058cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
- {"USBC0_HCINTMSK005" , 0x16f00100005acull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
- {"USBC0_HCINTMSK006" , 0x16f00100005ccull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
- {"USBC0_HCINTMSK007" , 0x16f00100005ecull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
- {"USBC0_HCSPLT000" , 0x16f0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
- {"USBC0_HCSPLT001" , 0x16f0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
- {"USBC0_HCSPLT002" , 0x16f0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
- {"USBC0_HCSPLT003" , 0x16f0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
- {"USBC0_HCSPLT004" , 0x16f0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
- {"USBC0_HCSPLT005" , 0x16f00100005a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
- {"USBC0_HCSPLT006" , 0x16f00100005c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
- {"USBC0_HCSPLT007" , 0x16f00100005e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
- {"USBC0_HCTSIZ000" , 0x16f0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
- {"USBC0_HCTSIZ001" , 0x16f0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
- {"USBC0_HCTSIZ002" , 0x16f0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
- {"USBC0_HCTSIZ003" , 0x16f0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
- {"USBC0_HCTSIZ004" , 0x16f0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
- {"USBC0_HCTSIZ005" , 0x16f00100005b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
- {"USBC0_HCTSIZ006" , 0x16f00100005d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
- {"USBC0_HCTSIZ007" , 0x16f00100005f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
- {"USBC0_HFIR" , 0x16f0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 551},
- {"USBC0_HFNUM" , 0x16f0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 552},
- {"USBC0_HPRT" , 0x16f0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 553},
- {"USBC0_HPTXFSIZ" , 0x16f0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 554},
- {"USBC0_HPTXSTS" , 0x16f0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 555},
- {"USBC0_NPTXDFIFO000" , 0x16f0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
- {"USBC0_NPTXDFIFO001" , 0x16f0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
- {"USBC0_NPTXDFIFO002" , 0x16f0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
- {"USBC0_NPTXDFIFO003" , 0x16f0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
- {"USBC0_NPTXDFIFO004" , 0x16f0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
- {"USBC0_NPTXDFIFO005" , 0x16f0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
- {"USBC0_NPTXDFIFO006" , 0x16f0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
- {"USBC0_NPTXDFIFO007" , 0x16f0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
- {"USBC0_PCGCCTL" , 0x16f0010000e00ull, CVMX_CSR_DB_TYPE_NCB, 32, 557},
- {"USBN0_BIST_STATUS" , 0x11800680007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"USBN0_CTL_STATUS" , 0x16f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 560},
- {"USBN0_DMA0_INB_CHN0" , 0x16f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 561},
- {"USBN0_DMA0_INB_CHN1" , 0x16f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 562},
- {"USBN0_DMA0_INB_CHN2" , 0x16f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 563},
- {"USBN0_DMA0_INB_CHN3" , 0x16f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 564},
- {"USBN0_DMA0_INB_CHN4" , 0x16f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"USBN0_DMA0_INB_CHN5" , 0x16f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"USBN0_DMA0_INB_CHN6" , 0x16f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 567},
- {"USBN0_DMA0_INB_CHN7" , 0x16f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 568},
- {"USBN0_DMA0_OUTB_CHN0" , 0x16f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 569},
- {"USBN0_DMA0_OUTB_CHN1" , 0x16f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"USBN0_DMA0_OUTB_CHN2" , 0x16f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"USBN0_DMA0_OUTB_CHN3" , 0x16f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 572},
- {"USBN0_DMA0_OUTB_CHN4" , 0x16f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 573},
- {"USBN0_DMA0_OUTB_CHN5" , 0x16f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 574},
- {"USBN0_DMA0_OUTB_CHN6" , 0x16f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"USBN0_DMA0_OUTB_CHN7" , 0x16f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 576},
- {"USBN0_DMA_TEST" , 0x16f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 577},
- {"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 578},
- {"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
- {"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"SETTING" , 0, 5, 0, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 0, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 1, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 0, 3, 2, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_3" , 3, 1, 2, "RAZ", 1, 1, 0, 0},
- {"TXPOP" , 4, 3, 2, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
- {"TXPSH" , 8, 3, 2, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_11_63" , 11, 53, 2, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 0, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 3, "RAZ", 1, 1, 0, 0},
- {"TXPOP" , 4, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 3, "RAZ", 1, 1, 0, 0},
- {"TXPSH" , 8, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 3, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 4, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
- {"INT_LOOP" , 0, 3, 5, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 5, "RAZ", 1, 1, 0, 0},
- {"EXT_LOOP" , 4, 3, 5, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 5, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 6, "R/W", 0, 0, 24ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 6, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 3, 7, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 7, "RAZ", 1, 1, 0, 0},
- {"SETTING" , 0, 5, 8, "R/W", 0, 0, 24ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 9, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_5_7" , 5, 3, 9, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 5, 9, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 9, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 16, 1, 9, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 9, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 3, 10, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 10, "RAZ", 1, 1, 0, 0},
- {"PRT_EN" , 0, 3, 11, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 11, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 2, 12, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 12, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 2, 13, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 13, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 2, 14, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 14, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 15, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 16, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 16, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 16, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 16, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 16, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_47" , 47, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 16, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 16, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 2, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 17, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 18, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 18, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 18, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 18, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 18, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 18, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 18, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 18, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 18, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_47" , 47, 1, 18, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 18, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 18, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 18, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 18, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 18, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 18, "R/W", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 18, "R/W", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 18, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 18, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 2, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 19, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 20, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 20, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 20, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 20, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 20, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 20, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 20, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 20, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 20, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_47_47" , 47, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 20, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 20, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 52, 4, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 20, "RO", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 20, "RO", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 20, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 21, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 21, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 21, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 21, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 21, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 21, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 21, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 21, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 21, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_47_47" , 47, 1, 21, "RAZ", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 21, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 21, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 52, 4, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 21, "RO", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 21, "RO", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 21, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 2, 22, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 22, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 23, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 23, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 24, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 24, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 2, 25, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 25, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 26, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 2, 27, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 27, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 28, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 29, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 1, 29, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 29, "RAZ", 1, 1, 0, 0},
- {"SOFT_BIST" , 0, 1, 30, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 30, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 31, "R/W", 0, 0, 1ull, 0ull},
- {"NPI" , 1, 1, 31, "R/W", 0, 0, 0ull, 0ull},
- {"HOST64" , 2, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 31, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 32, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 32, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 33, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 33, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 33, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 34, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 34, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 34, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 34, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 34, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 34, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 34, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 35, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 35, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 35, "RO", 1, 1, 0, 0},
- {"RESERVED_23_27" , 23, 5, 35, "RAZ", 1, 1, 0, 0},
- {"PLL_MUL" , 28, 3, 35, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 35, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 36, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 36, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 36, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 36, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 36, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 37, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 37, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 37, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 37, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 37, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 37, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 37, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 38, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 38, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 39, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 40, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 40, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 41, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 41, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 42, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 42, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 42, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 43, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 43, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 43, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 44, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 45, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 45, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 46, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 3, 46, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_21" , 5, 17, 46, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 3, 46, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_25" , 25, 1, 46, "RAZ", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 46, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 46, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 46, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 12, 47, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 47, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 48, "R/W", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 48, "R/W", 0, 0, 0ull, 1ull},
- {"P0MII" , 2, 1, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 48, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 49, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 49, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 50, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 50, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 50, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 50, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_63" , 4, 60, 50, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 51, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 52, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 53, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 54, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 55, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 56, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 57, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 57, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 58, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 58, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 58, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 58, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 59, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 59, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 60, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 60, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 60, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 60, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 60, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 60, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 60, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 60, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 60, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 60, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 60, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 61, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 61, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 61, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 61, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 61, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 61, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 61, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 61, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 61, "R/W", 0, 0, 1ull, 1ull},
- {"NULL_DIS" , 10, 1, 61, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 61, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 62, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 62, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 63, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 63, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 63, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 63, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 63, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 64, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 64, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 64, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 64, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 65, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 65, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 66, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 66, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 67, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 67, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 67, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 67, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 68, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 69, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 70, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 70, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 71, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 71, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 72, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 72, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 73, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 73, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 74, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 74, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 75, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 75, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 76, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 76, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 77, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 77, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 78, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 78, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 78, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 78, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 79, "R/W", 1, 1, 0, 0},
- {"RESERVED_6_63" , 6, 58, 79, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 80, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 80, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 81, "R/W", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 81, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 3, 82, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_15" , 3, 13, 82, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 3, 82, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 82, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 83, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_3_63" , 3, 61, 83, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 3, 84, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 84, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 3, 84, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 84, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 85, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 85, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 86, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 86, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 86, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 87, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 87, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 87, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 87, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 87, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 88, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 88, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 89, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 89, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 90, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 90, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 90, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 91, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 91, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 92, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 92, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 93, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 93, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 94, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 94, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 95, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 95, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 96, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 96, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 97, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 97, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 98, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 98, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 99, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 99, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 100, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 100, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 101, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 101, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 102, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 102, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 103, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 103, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 104, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 104, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 105, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 105, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 106, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 106, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 107, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 107, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 108, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 7, 109, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_7_63" , 7, 57, 109, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 3, 110, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 110, "RAZ", 1, 1, 0, 0},
- {"MSK" , 0, 1, 111, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 111, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 112, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 112, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 3, 113, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_3_63" , 3, 61, 113, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 114, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 114, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 114, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 115, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 3, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 115, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 3, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 115, "RAZ", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 3, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 115, "RAZ", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 3, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 115, "RAZ", 0, 0, 0ull, 0ull},
- {"PKO_NXA" , 0, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 116, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 3, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 116, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 3, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 116, "RAZ", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 3, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 116, "RAZ", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 3, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 116, "RAZ", 0, 0, 0ull, 0ull},
- {"JAM" , 0, 8, 117, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 117, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 118, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 118, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 3, 119, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 119, "RAZ", 0, 0, 0ull, 0ull},
- {"BP" , 4, 3, 119, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 119, "RAZ", 0, 0, 0ull, 0ull},
- {"EN" , 8, 3, 119, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 119, "RAZ", 0, 0, 0ull, 0ull},
- {"DMAC" , 0, 48, 120, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 120, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 121, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 121, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 122, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_5_63" , 5, 59, 122, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 123, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 123, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 123, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 123, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 123, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 123, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 123, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 124, "RAZ", 1, 1, 0, 0},
- {"BOOT_ENA" , 8, 4, 124, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 124, "RAZ", 1, 1, 0, 0},
- {"DBG_ENA" , 0, 21, 125, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 125, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 126, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 126, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 24, 127, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 127, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 24, 128, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 128, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 24, 129, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 129, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 130, "RAZ", 1, 1, 0, 0},
- {"FIL_CNT" , 4, 4, 130, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 130, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 131, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 131, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 132, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 132, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 132, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 132, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 132, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 132, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 133, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 133, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 133, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 134, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 134, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 134, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 134, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 134, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 135, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 135, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 135, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 135, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 135, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 136, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 137, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 138, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 138, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 138, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 138, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 138, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 138, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 138, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 139, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 140, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 140, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 140, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 140, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 140, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 141, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 141, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 141, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 141, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 141, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 142, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 143, "R/W", 0, 1, 0ull, 0},
- {"PORT" , 0, 6, 144, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 144, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 145, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 146, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 146, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 147, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 147, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 148, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 148, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 149, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 149, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 150, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 151, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 151, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 152, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 153, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 154, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 154, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 155, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 155, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 156, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 156, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 157, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 157, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 157, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 158, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 158, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 3, 159, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 159, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 159, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 159, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 159, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 159, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 160, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 160, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 160, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 160, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_44_63" , 44, 20, 160, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 161, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 161, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 161, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 161, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 161, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 161, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 162, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 162, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 162, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 162, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 162, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 162, "RO", 0, 0, 8ull, 8ull},
- {"RESERVED_61_63" , 61, 3, 162, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 163, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 163, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 164, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 164, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 165, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 165, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 165, "R/W", 0, 0, 0ull, 0ull},
- {"PRB_CON" , 0, 32, 166, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 166, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 166, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 166, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 166, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 167, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 167, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 167, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 3, 168, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_3_63" , 3, 61, 168, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 169, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 169, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 170, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 170, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 171, "RO", 0, 0, 0ull, 0ull},
- {"STIN_MSK" , 4, 1, 171, "RO", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 171, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 10, 171, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 171, "RAZ", 0, 0, 0ull, 0ull},
- {"WLB_MSK" , 19, 4, 171, "RO", 0, 0, 0ull, 0ull},
- {"DTBNK" , 23, 1, 171, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 171, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 9, 172, "RO", 0, 0, 0ull, 0ull},
- {"VAB_VWCF" , 9, 1, 172, "RO", 0, 0, 0ull, 0ull},
- {"LRF" , 10, 2, 172, "RO", 0, 0, 0ull, 0ull},
- {"VWDF" , 12, 4, 172, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 172, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 173, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 173, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 173, "RAZ", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 173, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 173, "RAZ", 0, 0, 0ull, 0ull},
- {"RMDF" , 8, 4, 173, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 173, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 173, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 174, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 174, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 174, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 174, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 174, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 174, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 174, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 174, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_17" , 14, 4, 174, "RAZ", 1, 1, 0, 0},
- {"LBIST" , 18, 1, 174, "R/W", 0, 0, 0ull, 0ull},
- {"BSTRUN" , 19, 1, 174, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 174, "RAZ", 1, 1, 0, 0},
- {"L2T" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 3, 175, "R/W", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_9" , 7, 3, 175, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 3, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 175, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 176, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 176, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 176, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 176, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 177, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 177, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 177, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 177, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 178, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 178, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 179, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 179, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 179, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 3, 179, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_17" , 17, 1, 179, "RAZ", 0, 0, 0ull, 0ull},
- {"SET" , 18, 3, 179, "RO", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 179, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 179, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 3, 179, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 179, "RAZ", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 179, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 179, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 179, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 179, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 179, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 179, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 180, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 180, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 180, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 7, 181, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 7, 20, 181, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 181, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 3, 182, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_3_3" , 3, 1, 182, "RAZ", 0, 0, 0ull, 0ull},
- {"STPARTDIS" , 4, 1, 182, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 182, "RAZ", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 183, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 183, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 184, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 8, 185, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK1" , 8, 8, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 185, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 8, 186, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 186, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 187, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 187, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 187, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 188, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 188, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 189, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 189, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 190, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 191, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 191, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 191, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 191, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 191, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 191, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 8, 192, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_10" , 8, 3, 192, "RAZ", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 3, 192, "RO", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 192, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 192, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 193, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 193, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 193, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 194, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 194, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 195, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 195, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 196, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 197, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 198, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_64K" , 34, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_32K" , 35, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_36" , 36, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"EMA_CTL" , 37, 3, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 198, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 199, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 199, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 199, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 199, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 199, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 199, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 7, 199, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_20" , 18, 3, 199, "RAZ", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 3, 199, "RO", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 199, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 199, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 199, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 199, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_28_63" , 28, 36, 199, "RAZ", 0, 0, 0ull, 0ull},
- {"START" , 0, 1, 200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 200, "RAZ", 1, 0, 0, 0ull},
- {"MRD" , 0, 3, 201, "RO", 1, 0, 0, 0ull},
- {"MRF" , 3, 1, 201, "RO", 1, 0, 0, 0ull},
- {"MWC" , 4, 1, 201, "RO", 1, 0, 0, 0ull},
- {"MWD" , 5, 3, 201, "RO", 1, 0, 0, 0ull},
- {"MWF" , 8, 1, 201, "RO", 1, 0, 0, 0ull},
- {"RESERVED_9_63" , 9, 55, 201, "RAZ", 1, 0, 0, 0ull},
- {"PCTL_DAT" , 0, 5, 202, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_11" , 5, 7, 202, "RAZ", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 202, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 202, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_27" , 20, 8, 202, "RAZ", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 202, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 202, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 203, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 203, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 203, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 203, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 203, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 203, "R/W", 0, 0, 0ull, 1ull},
- {"MODE32B" , 10, 1, 203, "R/W", 0, 0, 1ull, 1ull},
- {"DRESET" , 11, 1, 203, "R/W", 0, 0, 1ull, 0ull},
- {"INORDER_MRF" , 12, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 203, "RAZ", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 203, "R/W", 0, 1, 0ull, 0},
- {"PLL_BYPASS" , 16, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_17" , 17, 1, 203, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 203, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 203, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 203, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 203, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 203, "RAZ", 1, 1, 0, 0},
- {"DATA_LAYOUT" , 0, 2, 204, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 204, "RAZ", 0, 1, 0ull, 0},
- {"DCC_ENABLE" , 8, 1, 204, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_MODE" , 9, 1, 204, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 204, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 205, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 206, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 207, "R/W", 0, 0, 1ull, 1ull},
- {"RDQS" , 1, 1, 207, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 207, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 207, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 207, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 207, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 207, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 207, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 207, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 207, "R/W", 0, 0, 0ull, 0ull},
- {"SILO_HC" , 21, 1, 207, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 207, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 207, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 207, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 207, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 207, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 207, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 207, "RAZ", 0, 0, 0ull, 0ull},
- {"CLK" , 0, 4, 208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 208, "RAZ", 0, 0, 0ull, 0ull},
- {"CMD" , 5, 4, 208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 208, "RAZ", 0, 0, 0ull, 0ull},
- {"DQ" , 10, 4, 208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 208, "RAZ", 0, 0, 0ull, 0ull},
- {"CS_MASK" , 0, 8, 209, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 209, "RAZ", 0, 1, 0ull, 0},
- {"ROW_LSB" , 16, 3, 209, "R/W", 0, 1, 3ull, 0},
- {"BANK8" , 19, 1, 209, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 209, "RAZ", 0, 1, 0ull, 0},
- {"MRDSYN0" , 0, 8, 210, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 210, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 210, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 210, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 211, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 211, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 211, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 211, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 211, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 211, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 212, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 213, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 214, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 214, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 214, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 214, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 214, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 214, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 214, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 214, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 214, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 214, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 214, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 214, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 214, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 214, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 215, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 215, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 215, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 215, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 215, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 215, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 215, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 215, "R/W", 0, 0, 2ull, 2ull},
- {"COMP_BYPASS" , 31, 1, 215, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 215, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 216, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 216, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 217, "RAZ", 1, 1, 0, 0},
- {"EN2" , 0, 1, 218, "R/W", 0, 1, 0ull, 0},
- {"EN4" , 1, 1, 218, "R/W", 0, 1, 0ull, 0},
- {"EN6" , 2, 1, 218, "R/W", 0, 1, 0ull, 0},
- {"EN8" , 3, 1, 218, "R/W", 0, 1, 1ull, 0},
- {"EN12" , 4, 1, 218, "R/W", 0, 1, 0ull, 0},
- {"EN16" , 5, 1, 218, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 218, "RAZ", 0, 1, 0ull, 0},
- {"CLKR" , 8, 6, 218, "R/W", 0, 1, 0ull, 0},
- {"CLKF" , 14, 12, 218, "R/W", 0, 1, 31ull, 0},
- {"RESET_N" , 26, 1, 218, "R/W", 0, 0, 0ull, 1ull},
- {"DIV_RESET" , 27, 1, 218, "R/W", 0, 0, 1ull, 0ull},
- {"FASTEN_N" , 28, 1, 218, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 218, "RAZ", 0, 1, 0ull, 0},
- {"FBSLIP" , 0, 1, 219, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 219, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_21" , 2, 20, 219, "RAZ", 1, 1, 0, 0},
- {"DDR__PCTL" , 22, 5, 219, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 27, 5, 219, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 219, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 0, 5, 220, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 220, "RAZ", 0, 1, 0ull, 0},
- {"NCTL" , 8, 4, 220, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 220, "RAZ", 0, 1, 0ull, 0},
- {"ENABLE" , 16, 1, 220, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 220, "RAZ", 0, 1, 0ull, 0},
- {"RODT_LO0" , 0, 4, 221, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO1" , 4, 4, 221, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO2" , 8, 4, 221, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO3" , 12, 4, 221, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI0" , 16, 4, 221, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI1" , 20, 4, 221, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI2" , 24, 4, 221, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI3" , 28, 4, 221, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 221, "RAZ", 1, 1, 0, 0},
- {"WODT_LO0" , 0, 4, 222, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO1" , 4, 4, 222, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO2" , 8, 4, 222, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_LO3" , 12, 4, 222, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI0" , 16, 4, 222, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI1" , 20, 4, 222, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI2" , 24, 4, 222, "R/W", 0, 0, 15ull, 15ull},
- {"WODT_HI3" , 28, 4, 222, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 222, "RAZ", 1, 1, 0, 0},
- {"NCBI" , 0, 1, 223, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 223, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 2, 1, 223, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_1" , 3, 1, 223, "RO", 0, 0, 0ull, 0ull},
- {"PCM_0" , 4, 1, 223, "RO", 0, 0, 0ull, 0ull},
- {"PCM_1" , 5, 1, 223, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 223, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 224, "R/W", 0, 1, 31ull, 0},
- {"PCTL" , 5, 5, 224, "R/W", 0, 1, 31ull, 0},
- {"RESERVED_10_63" , 10, 54, 224, "RAZ", 1, 1, 0, 0},
- {"ADR_ERR" , 0, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 225, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 226, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 226, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 226, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 227, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 227, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 227, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 228, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 228, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 228, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 228, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 228, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 229, "R/W", 1, 1, 0, 0},
- {"BASE" , 0, 16, 230, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 230, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 230, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 230, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 230, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 230, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 230, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 230, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 230, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 230, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 230, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_42_63" , 42, 22, 230, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 231, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 231, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 231, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 231, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 231, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 231, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 231, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 231, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 231, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 231, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 231, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 231, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 231, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 232, "R/W", 0, 0, 26ull, 26ull},
- {"RESERVED_6_7" , 6, 2, 232, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 232, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 232, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 233, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 234, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 234, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 235, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 235, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 2, 236, "RO", 1, 1, 0, 0},
- {"RESERVED_2_15" , 2, 14, 236, "RAZ", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 236, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 236, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 236, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 236, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 236, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 236, "RO", 0, 0, 1ull, 1ull},
- {"NOKASU" , 29, 1, 236, "RO", 1, 1, 0, 0},
- {"RESERVED_30_31" , 30, 2, 236, "RAZ", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 236, "RO", 0, 0, 0ull, 0ull},
- {"FUS318" , 33, 1, 236, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 236, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 237, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 237, "RO", 0, 0, 1ull, 1ull},
- {"NOZIP" , 25, 1, 237, "RO", 0, 0, 1ull, 1ull},
- {"EFUS_IGN" , 26, 1, 237, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 237, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 237, "RO", 1, 1, 0, 0},
- {"ZIP_CRIP" , 29, 2, 237, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 237, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 238, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_3_3" , 3, 1, 238, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 238, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_63" , 7, 57, 238, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 239, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 240, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 240, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 240, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 241, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 241, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 8, 242, "R/W", 0, 1, 3ull, 0},
- {"SCLK_HI" , 8, 12, 242, "R/W", 0, 1, 100ull, 0},
- {"SCLK_LO" , 20, 4, 242, "R/W", 0, 1, 2ull, 0},
- {"OUT" , 24, 8, 242, "R/W", 0, 1, 3ull, 0},
- {"PROG_PIN" , 32, 1, 242, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 242, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 7, 243, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 243, "RAZ", 1, 1, 0, 0},
- {"EFUSE" , 8, 1, 243, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 243, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 243, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 243, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 243, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 243, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 244, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 14, 14, 244, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 28, 14, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 244, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 245, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 245, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 2, 246, "R/W", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 246, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 247, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 247, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 247, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 247, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 247, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 247, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 247, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 247, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 248, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 248, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 248, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 248, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 248, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 248, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 248, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 248, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 248, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 248, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 248, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 248, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 249, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 249, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 249, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 250, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 250, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 250, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 251, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 251, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 252, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 252, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 253, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 253, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 254, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 254, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 254, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 254, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 254, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 254, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 254, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 255, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 255, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 256, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 256, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 256, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 257, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 257, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 257, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 257, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 258, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 258, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 258, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 258, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 258, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 258, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 258, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 258, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 259, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 259, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 259, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 259, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 259, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 259, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 259, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 259, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 259, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 260, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 260, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 260, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 260, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 260, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 260, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 260, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 261, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 261, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 261, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 261, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 261, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 261, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 261, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 261, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 261, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 262, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 262, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 263, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 263, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 264, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 264, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 264, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 264, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 265, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 265, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 266, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 266, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 267, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 267, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 268, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 268, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 268, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 268, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 269, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 269, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 270, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 270, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 271, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 271, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 272, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 272, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 273, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 273, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 274, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 274, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 275, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 275, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 275, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 275, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 275, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 275, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"IDLELO" , 1, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_CONT" , 2, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"WIREOR" , 3, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 4, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"INT_ENA" , 5, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"CSENA" , 6, 1, 276, "R/W", 0, 0, 0ull, 1ull},
- {"CSHI" , 7, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"IDLECLKS" , 8, 2, 276, "R/W", 0, 0, 0ull, 0ull},
- {"TRITX" , 10, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"CSLATE" , 11, 1, 276, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 276, "RAZ", 1, 1, 0, 0},
- {"CLKDIV" , 16, 13, 276, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 276, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 8, 277, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 277, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 278, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 278, "RAZ", 1, 1, 0, 0},
- {"RXNUM" , 8, 5, 278, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 278, "RAZ", 1, 1, 0, 0},
- {"TOTNUM" , 0, 5, 279, "WO", 1, 0, 0, 2ull},
- {"RESERVED_5_7" , 5, 3, 279, "RAZ", 1, 1, 0, 0},
- {"TXNUM" , 8, 5, 279, "WO", 1, 0, 0, 1ull},
- {"RESERVED_13_15" , 13, 3, 279, "RAZ", 1, 1, 0, 0},
- {"LEAVECS" , 16, 1, 279, "WO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 279, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 280, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 281, "RAZ", 1, 1, 0, 0},
- {"BADDR" , 3, 61, 281, "R/W", 0, 1, 0ull, 0},
- {"DPI_BS" , 0, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"PDF_BS" , 1, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"DOB_BS" , 2, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"NUS_BS" , 3, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"POS_BS" , 4, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 282, "RAZ", 0, 0, 0ull, 0ull},
- {"POF1_BS" , 7, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"POF0_BS" , 8, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"PIG_BS" , 9, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"PGF_BS" , 10, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"RDNL_BS" , 11, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"PCAD_BS" , 12, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"PCAC_BS" , 13, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"RDN_BS" , 14, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"PCN_BS" , 15, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"PCNC_BS" , 16, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"RDP_BS" , 17, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"DIF_BS" , 18, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"CSR_BS" , 19, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 282, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 283, "R/W", 0, 1, 1024ull, 0},
- {"ISIZE" , 16, 7, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 283, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 284, "R/W", 0, 1, 16ull, 0},
- {"PCTL" , 5, 5, 284, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_10_63" , 10, 54, 284, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 285, "R/W", 0, 0, 0ull, 50ull},
- {"RESERVED_10_31" , 10, 22, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"MAX_WORD" , 32, 5, 285, "R/W", 0, 0, 2ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"WAIT_COM" , 40, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_WDIS" , 41, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"INS0_64B" , 42, 1, 285, "R/W", 0, 1, 0ull, 0},
- {"INS1_64B" , 43, 1, 285, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_45" , 44, 2, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"INS0_ENB" , 46, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"INS1_ENB" , 47, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_48_49" , 48, 2, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT0_ENB" , 50, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"OUT1_ENB" , 51, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_52_53" , 52, 2, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"DIS_PNIW" , 54, 1, 285, "R/W", 0, 0, 0ull, 1ull},
- {"CHIP_REV" , 55, 8, 285, "RO", 1, 1, 0, 0},
- {"RESERVED_63_63" , 63, 1, 285, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 286, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 286, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 0, 14, 287, "R/W", 0, 1, 0ull, 0},
- {"LP_ENB" , 14, 1, 287, "R/W", 0, 0, 0ull, 1ull},
- {"HP_ENB" , 15, 1, 287, "R/W", 0, 0, 0ull, 1ull},
- {"O_MODE" , 16, 1, 287, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 17, 2, 287, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 19, 1, 287, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 20, 1, 287, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 21, 1, 287, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 22, 3, 287, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 25, 9, 287, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 34, 1, 287, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 35, 1, 287, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 287, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 288, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 288, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 288, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 289, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 289, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 289, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 290, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 290, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 290, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 291, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 4, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 291, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 292, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 292, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 293, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 293, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 1, 294, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 294, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 294, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 294, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 294, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 294, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 294, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 294, "R/W", 0, 1, 0ull, 0},
- {"PKT_RR" , 22, 1, 294, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 294, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PCI_RSL" , 2, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PO0_2SML" , 3, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PO1_2SML" , 4, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
- {"I0_RTOUT" , 7, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"I1_RTOUT" , 8, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_10" , 9, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
- {"I0_OVERF" , 11, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"I1_OVERF" , 12, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_RTOUT" , 15, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"P1_RTOUT" , 16, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_18" , 17, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_PERR" , 19, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PERR" , 20, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_22" , 21, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
- {"G0_RTOUT" , 23, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"G1_RTOUT" , 24, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_25_26" , 25, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_PPERR" , 27, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PPERR" , 28, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_29_30" , 29, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
- {"P0_PTOUT" , 31, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"P1_PTOUT" , 32, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_33_34" , 33, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
- {"I0_PPERR" , 35, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"I1_PPERR" , 36, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_37_38" , 37, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
- {"WIN_RTO" , 39, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"P_DPERR" , 40, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 41, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_S_E" , 42, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"FCR_A_F" , 43, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_S_E" , 44, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PCR_A_F" , 45, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_S_E" , 46, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"Q2_A_F" , 47, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_S_E" , 48, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"Q3_A_F" , 49, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"COM_S_E" , 50, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"COM_A_F" , 51, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_S_E" , 52, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PNC_A_F" , 53, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RWX_S_E" , 54, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RDX_S_E" , 55, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_E" , 56, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PCF_P_F" , 57, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_E" , 58, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"PDF_P_F" , 59, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_S_E" , 60, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"Q1_A_F" , 61, 1, 295, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_62_63" , 62, 2, 295, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_RSL" , 2, 1, 296, "RO", 0, 0, 0ull, 0ull},
- {"PO0_2SML" , 3, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"PO1_2SML" , 4, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"I0_RTOUT" , 7, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_RTOUT" , 8, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_10" , 9, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"I0_OVERF" , 11, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_OVERF" , 12, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_14" , 13, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_RTOUT" , 15, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_RTOUT" , 16, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_18" , 17, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_PERR" , 19, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PERR" , 20, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_22" , 21, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"G0_RTOUT" , 23, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"G1_RTOUT" , 24, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_26" , 25, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_PPERR" , 27, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PPERR" , 28, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_30" , 29, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_PTOUT" , 31, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_PTOUT" , 32, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_33_34" , 33, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"I0_PPERR" , 35, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"I1_PPERR" , 36, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_38" , 37, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"WIN_RTO" , 39, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DPERR" , 40, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 41, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_S_E" , 42, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCR_A_F" , 43, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_S_E" , 44, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCR_A_F" , 45, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_S_E" , 46, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_A_F" , 47, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_S_E" , 48, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_A_F" , 49, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_S_E" , 50, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"COM_A_F" , 51, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_S_E" , 52, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"PNC_A_F" , 53, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RWX_S_E" , 54, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDX_S_E" , 55, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_E" , 56, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCF_P_F" , 57, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_E" , 58, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDF_P_F" , 59, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_S_E" , 60, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_A_F" , 61, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 296, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 297, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 297, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 0, 36, 298, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 298, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 28, 299, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 28, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 29, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 30, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 31, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 32, 2, 299, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 34, 2, 299, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 36, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"SHORTL" , 37, 1, 299, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 299, "RAZ", 1, 1, 0, 0},
- {"INT_VEC" , 0, 64, 300, "R/W1C", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 32, 301, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 301, "RAZ", 1, 1, 0, 0},
- {"ROR_SL0" , 0, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL0" , 1, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL0" , 2, 2, 302, "R/W", 0, 1, 0ull, 0},
- {"ROR_SL1" , 4, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"NSR_SL1" , 5, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"ESR_SL1" , 6, 2, 302, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 302, "RAZ", 0, 0, 0ull, 0ull},
- {"IPTR_O0" , 16, 1, 302, "R/W", 0, 0, 0ull, 1ull},
- {"IPTR_O1" , 17, 1, 302, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_18_23" , 18, 6, 302, "RAZ", 0, 0, 0ull, 0ull},
- {"O0_CSRM" , 24, 1, 302, "R/W", 0, 0, 0ull, 1ull},
- {"O1_CSRM" , 25, 1, 302, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_26_27" , 26, 2, 302, "RAZ", 0, 0, 0ull, 0ull},
- {"O0_RO" , 28, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"O0_NS" , 29, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"O0_ES" , 30, 2, 302, "R/W", 0, 1, 0ull, 0},
- {"O1_RO" , 32, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"O1_NS" , 33, 1, 302, "R/W", 0, 1, 0ull, 0},
- {"O1_ES" , 34, 2, 302, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_43" , 36, 8, 302, "RAZ", 0, 0, 0ull, 0ull},
- {"P0_BMODE" , 44, 1, 302, "R/W", 0, 0, 0ull, 0ull},
- {"P1_BMODE" , 45, 1, 302, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_47" , 46, 2, 302, "RAZ", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 48, 1, 302, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 302, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 303, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 2, 303, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_63_63" , 63, 1, 303, "RAZ", 1, 1, 0, 0},
- {"NADDR" , 0, 61, 304, "RO", 0, 1, 0ull, 0},
- {"STATE" , 61, 3, 304, "RO", 0, 0, 0ull, 0ull},
- {"AVAIL" , 0, 32, 305, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 6, 305, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 305, "RAZ", 1, 1, 0, 0},
- {"AVAIL" , 0, 32, 306, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 5, 306, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 306, "RAZ", 1, 1, 0, 0},
- {"RD_BRST" , 0, 7, 307, "R/W", 0, 0, 17ull, 64ull},
- {"WR_BRST" , 7, 7, 307, "R/W", 0, 0, 16ull, 64ull},
- {"RESERVED_14_63" , 14, 50, 307, "RAZ", 1, 1, 0, 0},
- {"PARK_DEV" , 0, 3, 308, "R/W", 0, 1, 0ull, 0},
- {"PARK_MOD" , 3, 1, 308, "R/W", 0, 1, 0ull, 0},
- {"EN" , 4, 1, 308, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 308, "RAZ", 1, 1, 0, 0},
- {"PCI_OVR" , 8, 4, 308, "R/W", 0, 1, 0ull, 0},
- {"HOSTMODE" , 12, 1, 308, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 308, "RAZ", 1, 1, 0, 0},
- {"CMD_SIZE" , 0, 11, 309, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_11_63" , 11, 53, 309, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 310, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 310, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 310, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 310, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 310, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 310, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 310, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 310, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 310, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 310, "RAZ", 1, 1, 0, 0},
- {"RSV_A" , 0, 6, 311, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 311, "R/W", 0, 1, 0ull, 0},
- {"RSV_B" , 13, 1, 311, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 311, "R/W", 0, 1, 0ull, 0},
- {"RSV_C" , 16, 5, 311, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 311, "R/W", 0, 1, 0ull, 0},
- {"RSV_D" , 22, 6, 311, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 311, "R/W", 0, 1, 8ull, 0},
- {"RSV_E" , 35, 1, 311, "R/W", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 311, "R/W", 0, 1, 0ull, 0},
- {"RSV_F" , 38, 5, 311, "R/W", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 311, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 311, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 4, 312, "R/W", 0, 0, 15ull, 15ull},
- {"BP_ON" , 4, 4, 312, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 312, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"NPI" , 3, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 14, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"LMC" , 17, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"ASX0" , 22, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"ASX1" , 23, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_27" , 24, 4, 313, "RO", 0, 0, 0ull, 0ull},
- {"AGL" , 28, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"LMC1" , 29, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 313, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 313, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 32, 314, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 314, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 315, "R/W", 0, 0, 0ull, 131072ull},
- {"RESERVED_32_63" , 32, 32, 315, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 316, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 316, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 316, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 316, "RAZ", 1, 1, 0, 0},
- {"DBG2N_BS" , 0, 1, 317, "RO", 0, 0, 0ull, 0ull},
- {"DAT2N_BS" , 1, 1, 317, "RO", 0, 0, 0ull, 0ull},
- {"CSR2N_BS" , 2, 1, 317, "RO", 0, 0, 0ull, 0ull},
- {"RSP2P_BS" , 3, 1, 317, "RO", 0, 0, 0ull, 0ull},
- {"CSRR_BS" , 4, 1, 317, "RO", 0, 0, 0ull, 0ull},
- {"CSR2P_BS" , 5, 1, 317, "RO", 0, 0, 0ull, 0ull},
- {"CMD_BS" , 6, 1, 317, "RO", 0, 0, 0ull, 0ull},
- {"CMD0_BS" , 7, 1, 317, "RO", 0, 0, 0ull, 0ull},
- {"DMA0_BS" , 8, 1, 317, "RO", 0, 0, 0ull, 0ull},
- {"RSP_BS" , 9, 1, 317, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 317, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 318, "RO", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 318, "RO", 0, 0, 112ull, 32ull},
- {"ISAE" , 0, 1, 319, "RO", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 319, "R/W", 0, 0, 0ull, 1ull},
- {"ME" , 2, 1, 319, "R/W", 0, 0, 0ull, 1ull},
- {"SCSE" , 3, 1, 319, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 319, "R/W", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 319, "RO", 0, 0, 0ull, 0ull},
- {"PEE" , 6, 1, 319, "R/W", 0, 0, 0ull, 1ull},
- {"ADS" , 7, 1, 319, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 319, "R/W", 0, 0, 0ull, 1ull},
- {"FBBE" , 9, 1, 319, "R/W", 0, 0, 0ull, 1ull},
- {"I_DIS" , 10, 1, 319, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 319, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 319, "RO", 0, 0, 0ull, 0ull},
- {"CLE" , 20, 1, 319, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 319, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_22" , 22, 1, 319, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 319, "RO", 0, 1, 1ull, 0},
- {"MDPE" , 24, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 319, "RO", 0, 0, 1ull, 1ull},
- {"STA" , 27, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 320, "RO", 0, 0, 0ull, 0ull},
- {"CC" , 8, 24, 320, "RO", 0, 0, 733184ull, 733184ull},
- {"CLS" , 0, 8, 321, "R/W", 0, 1, 0ull, 0},
- {"LT" , 8, 8, 321, "R/W", 0, 0, 0ull, 64ull},
- {"HT" , 16, 8, 321, "RO", 0, 0, 0ull, 0ull},
- {"BCOD" , 24, 4, 321, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_29" , 28, 2, 321, "RAZ", 1, 1, 0, 0},
- {"BRB" , 30, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"BCAP" , 31, 1, 321, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 322, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 322, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 322, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 8, 322, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 12, 20, 322, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 323, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 324, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 324, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 324, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 23, 324, "RO", 0, 0, 0ull, 0ull},
- {"LBASE" , 27, 5, 324, "R/W", 0, 1, 0ull, 0},
- {"HBASE" , 0, 32, 325, "R/W", 0, 1, 0ull, 0},
- {"MSPC" , 0, 1, 326, "RO", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 326, "RO", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 326, "RO", 0, 0, 1ull, 1ull},
- {"LBASEZ" , 4, 28, 326, "RO", 0, 0, 0ull, 0ull},
- {"HBASEZ" , 0, 7, 327, "RO", 0, 0, 0ull, 0ull},
- {"HBASE" , 7, 25, 327, "R/W", 0, 1, 0ull, 0},
- {"CISP" , 0, 32, 328, "RO", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 329, "RO", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 329, "RO", 0, 0, 1ull, 1ull},
- {"ERBAR_EN" , 0, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_10" , 1, 10, 330, "RAZ", 1, 1, 0, 0},
- {"ERBARZ" , 11, 5, 330, "RO", 0, 0, 0ull, 0ull},
- {"ERBAR" , 16, 16, 330, "R/W", 0, 1, 0ull, 0},
- {"CP" , 0, 8, 331, "RO", 0, 0, 224ull, 224ull},
- {"RESERVED_8_31" , 8, 24, 331, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 332, "R/W", 0, 1, 0ull, 0},
- {"INTA" , 8, 8, 332, "RO", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 332, "RO", 0, 0, 64ull, 64ull},
- {"ML" , 24, 8, 332, "RO", 0, 0, 64ull, 64ull},
- {"MLTD" , 0, 1, 333, "R/W", 0, 0, 0ull, 1ull},
- {"TSWC" , 1, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 333, "RAZ", 1, 1, 0, 0},
- {"DPPMR" , 3, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"PBE" , 4, 12, 333, "R/W", 0, 0, 0ull, 0ull},
- {"TILT" , 16, 4, 333, "R/W", 0, 0, 0ull, 0ull},
- {"TSLTE" , 20, 3, 333, "R/W", 0, 0, 0ull, 0ull},
- {"TMAE" , 23, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"TWTAE" , 24, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEN" , 25, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"TWSEI" , 26, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"TRTAE" , 27, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"TRDRS" , 28, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"RDSATI" , 29, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"TRDARD" , 30, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRDNPR" , 31, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSCME" , 0, 32, 334, "R/W1C", 0, 1, 0ull, 0},
- {"TDSRPS" , 0, 32, 335, "R/W1C", 0, 0, 0ull, 0ull},
- {"TDOMC" , 0, 5, 336, "R/W", 0, 0, 1ull, 1ull},
- {"TIDOMC" , 5, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 336, "RAZ", 1, 1, 0, 0},
- {"TIBDE" , 7, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"TIBCD" , 8, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_10" , 9, 2, 336, "RAZ", 1, 1, 0, 0},
- {"TMAPES" , 11, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMDPES" , 12, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMSE" , 13, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"TMEI" , 14, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"TECI" , 15, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"TMES" , 16, 8, 336, "RO", 0, 0, 0ull, 0ull},
- {"MDRRMC" , 24, 3, 336, "R/W", 0, 0, 2ull, 2ull},
- {"MDRIMC" , 27, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"MDRE" , 28, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"MDWE" , 29, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCI" , 30, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"MRBCM" , 31, 1, 336, "R/W", 0, 0, 1ull, 1ull},
- {"MDSP" , 0, 32, 337, "R/W1C", 0, 1, 0ull, 0},
- {"SCMRE" , 0, 32, 338, "R/W1C", 0, 1, 0ull, 0},
- {"MTTV" , 0, 8, 339, "R/W", 0, 0, 0ull, 0ull},
- {"MRV" , 8, 8, 339, "R/W", 0, 0, 0ull, 255ull},
- {"MTTA" , 16, 1, 339, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRA" , 17, 1, 339, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLUSH" , 18, 1, 339, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_19_24" , 19, 6, 339, "RAZ", 1, 1, 0, 0},
- {"MAC" , 25, 7, 339, "R/W", 0, 0, 0ull, 0ull},
- {"PXCID" , 0, 8, 340, "RO", 0, 0, 7ull, 7ull},
- {"NCP" , 8, 8, 340, "RO", 0, 0, 232ull, 232ull},
- {"DPERE" , 16, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"ROE" , 17, 1, 340, "R/W", 0, 0, 1ull, 1ull},
- {"MMBC" , 18, 2, 340, "R/W", 0, 0, 0ull, 0ull},
- {"MOST" , 20, 3, 340, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_23_31" , 23, 9, 340, "RAZ", 1, 1, 0, 0},
- {"FN" , 0, 3, 341, "RO", 0, 0, 0ull, 0ull},
- {"DN" , 3, 5, 341, "RO", 0, 0, 31ull, 31ull},
- {"BN" , 8, 8, 341, "RO", 0, 1, 17ull, 0},
- {"W64" , 16, 1, 341, "RO", 0, 0, 1ull, 1ull},
- {"M133" , 17, 1, 341, "RO", 0, 0, 1ull, 1ull},
- {"SCD" , 18, 1, 341, "R/W1C", 0, 1, 0ull, 0},
- {"USC" , 19, 1, 341, "R/W1C", 0, 1, 0ull, 0},
- {"DC" , 20, 1, 341, "RO", 0, 0, 0ull, 0ull},
- {"MMRBCD" , 21, 2, 341, "RO", 0, 0, 2ull, 2ull},
- {"MOSTD" , 23, 3, 341, "RO", 0, 0, 3ull, 3ull},
- {"MCRSD" , 26, 3, 341, "RO", 0, 0, 7ull, 7ull},
- {"SCEMR" , 29, 1, 341, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 341, "RAZ", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 342, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 342, "RO", 0, 0, 240ull, 240ull},
- {"PCIMIV" , 16, 3, 342, "RO", 0, 0, 2ull, 2ull},
- {"PMEC" , 19, 1, 342, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 342, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 342, "RO", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 342, "RO", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 342, "RO", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 342, "RO", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 342, "RO", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 343, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 343, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 343, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 343, "R/W", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 343, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 343, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEN" , 23, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 343, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 344, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 344, "RO", 0, 0, 0ull, 0ull},
- {"MSIEN" , 16, 1, 344, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 344, "RO", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 344, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 344, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 344, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 345, "RAZ", 1, 1, 0, 0},
- {"MSI31T2" , 2, 30, 345, "R/W", 0, 1, 0ull, 0},
- {"MSI" , 0, 32, 346, "R/W", 0, 1, 0ull, 0},
- {"MSIMD" , 0, 16, 347, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 347, "RAZ", 1, 1, 0, 0},
- {"PCICNT" , 0, 32, 348, "R/W", 0, 1, 0ull, 0},
- {"AP_SPEED" , 32, 2, 348, "RO", 1, 1, 0, 0},
- {"AP_PCIX" , 34, 1, 348, "RO", 1, 1, 0, 0},
- {"HM_SPEED" , 35, 2, 348, "RO", 0, 1, 0ull, 0},
- {"HM_PCIX" , 37, 1, 348, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 348, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 349, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 349, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 349, "R/W", 0, 0, 0ull, 1ull},
- {"TSR_HWM" , 4, 3, 349, "R/W", 0, 1, 1ull, 0},
- {"PMO_FPC" , 7, 3, 349, "R/W", 0, 0, 0ull, 0ull},
- {"PMO_AMOD" , 10, 1, 349, "R/W", 0, 0, 0ull, 0ull},
- {"B12_BIST" , 11, 1, 349, "RO", 0, 0, 0ull, 0ull},
- {"AP_64AD" , 12, 1, 349, "RO", 0, 1, 0ull, 0},
- {"AP_PCIX" , 13, 1, 349, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_14" , 14, 1, 349, "RAZ", 0, 0, 0ull, 0ull},
- {"EN_WFILT" , 15, 1, 349, "R/W", 0, 0, 0ull, 1ull},
- {"SCM" , 16, 1, 349, "RO", 0, 1, 0ull, 0},
- {"SCMTYP" , 17, 1, 349, "RO", 0, 1, 0ull, 0},
- {"BAR2PRES" , 18, 1, 349, "R/W", 1, 1, 0, 0},
- {"ERST_N" , 19, 1, 349, "RO", 0, 0, 1ull, 1ull},
- {"BB0" , 20, 1, 349, "R/W", 0, 0, 0ull, 0ull},
- {"BB1" , 21, 1, 349, "R/W", 0, 0, 0ull, 0ull},
- {"BB_ES" , 22, 2, 349, "R/W", 0, 0, 0ull, 0ull},
- {"BB_CA" , 24, 1, 349, "R/W", 0, 0, 0ull, 0ull},
- {"BB1_SIZ" , 25, 1, 349, "R/W", 0, 0, 0ull, 0ull},
- {"BB1_HOLE" , 26, 3, 349, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 349, "RAZ", 1, 1, 0, 0},
- {"INC_VAL" , 0, 16, 350, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 350, "RAZ", 1, 1, 0, 0},
- {"DMA_CNT" , 0, 32, 351, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 352, "R/W", 0, 1, 0ull, 0},
- {"DMA_TIME" , 0, 32, 353, "R/W", 0, 1, 0ull, 0},
- {"ICNT" , 0, 32, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"ITR_WABT" , 0, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IMR_WABT" , 1, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IMR_WTTO" , 2, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"ITR_ABT" , 3, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IMR_ABT" , 4, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IMR_TTO" , 5, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IMSI_PER" , 6, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IMSI_TABT" , 7, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IMSI_MABT" , 8, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IMSC_MSG" , 9, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"ITSR_ABT" , 10, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"ISERR" , 11, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IAPERR" , 12, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IDPERR" , 13, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IRSL_INT" , 16, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IPCNT0" , 17, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IPCNT1" , 18, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_19_20" , 19, 2, 355, "RAZ", 0, 1, 0ull, 0},
- {"IPTIME0" , 21, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IPTIME1" , 22, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_24" , 23, 2, 355, "RAZ", 0, 1, 0ull, 0},
- {"IDCNT0" , 25, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IDCNT1" , 26, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IDTIME0" , 27, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"IDTIME1" , 28, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 355, "RAZ", 1, 1, 0, 0},
- {"RTR_WABT" , 0, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RMR_WABT" , 1, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RMR_WTTO" , 2, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RTR_ABT" , 3, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RMR_ABT" , 4, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RMR_TTO" , 5, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RMSI_PER" , 6, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RMSI_TABT" , 7, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RMSI_MABT" , 8, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RMSC_MSG" , 9, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RTSR_ABT" , 10, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RSERR" , 11, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RAPERR" , 12, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RDPERR" , 13, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"ILL_RWR" , 14, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"ILL_RRD" , 15, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RRSL_INT" , 16, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RPCNT0" , 17, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RPCNT1" , 18, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_19_20" , 19, 2, 356, "RAZ", 0, 1, 0ull, 0},
- {"RPTIME0" , 21, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RPTIME1" , 22, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_24" , 23, 2, 356, "RAZ", 0, 1, 0ull, 0},
- {"RDCNT0" , 25, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RDCNT1" , 26, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RDTIME0" , 27, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RDTIME1" , 28, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"DMA0_FI" , 29, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"DMA1_FI" , 30, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"WIN_WR" , 31, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"ILL_WR" , 32, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"ILL_RD" , 33, 1, 356, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_34_63" , 34, 30, 356, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 357, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_20" , 19, 2, 357, "RAZ", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_24" , 23, 2, 357, "RAZ", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 357, "RAZ", 1, 1, 0, 0},
- {"TR_WABT" , 0, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WABT" , 1, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_WTTO" , 2, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"TR_ABT" , 3, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_ABT" , 4, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"MR_TTO" , 5, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_PER" , 6, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_TABT" , 7, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_MABT" , 8, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSC_MSG" , 9, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"TSR_ABT" , 10, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"SERR" , 11, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"APERR" , 12, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPERR" , 13, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RWR" , 14, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RRD" , 15, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSL_INT" , 16, 1, 358, "RO", 0, 0, 0ull, 0ull},
- {"PCNT0" , 17, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT1" , 18, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_20" , 19, 2, 358, "RAZ", 0, 0, 0ull, 0ull},
- {"PTIME0" , 21, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTIME1" , 22, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_24" , 23, 2, 358, "RAZ", 0, 0, 0ull, 0ull},
- {"DCNT0" , 25, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 26, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 27, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 28, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0_FI" , 29, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_FI" , 30, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"WIN_WR" , 31, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_WR" , 32, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_RD" , 33, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 358, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 6, 359, "WO", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 359, "R/W", 1, 1, 0, 0},
- {"PTR_CNT" , 0, 16, 360, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 16, 16, 360, "R/W", 0, 1, 0ull, 0},
- {"PKT_CNT" , 0, 32, 361, "RO", 0, 0, 0ull, 0ull},
- {"PKT_CNT" , 0, 32, 362, "R/W", 0, 1, 0ull, 0},
- {"PKT_TIME" , 0, 32, 363, "R/W", 0, 1, 0ull, 0},
- {"PREFETCH" , 0, 3, 364, "R/W", 0, 0, 0ull, 2ull},
- {"MIN_DATA" , 3, 6, 364, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_9_31" , 9, 23, 364, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 365, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 365, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 365, "RAZ", 1, 1, 0, 0},
- {"PREFETCH" , 0, 3, 366, "R/W", 0, 0, 0ull, 3ull},
- {"MIN_DATA" , 3, 6, 366, "R/W", 0, 0, 0ull, 6ull},
- {"RESERVED_9_31" , 9, 23, 366, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 31, 367, "R/W", 0, 0, 10000ull, 10000ull},
- {"ENB" , 31, 1, 367, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 367, "RAZ", 1, 1, 0, 0},
- {"SCM" , 0, 32, 368, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 368, "RAZ", 1, 1, 0, 0},
- {"TSR" , 0, 36, 369, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 369, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 370, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 2, 46, 370, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 370, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 370, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 371, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 372, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 372, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 372, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 372, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 373, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 374, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 374, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 375, "R/W", 0, 0, 0ull, 8ull},
- {"FETCHSIZ" , 4, 4, 375, "R/W", 0, 0, 0ull, 7ull},
- {"TXRD" , 8, 10, 375, "R/W", 0, 0, 0ull, 1ull},
- {"USELDT" , 18, 1, 375, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 375, "RAZ", 1, 1, 0, 0},
- {"RXST" , 20, 10, 375, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_30_31" , 30, 2, 375, "RAZ", 1, 1, 0, 0},
- {"TXSLOTS" , 32, 10, 375, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_42_43" , 42, 2, 375, "RAZ", 1, 1, 0, 0},
- {"RXSLOTS" , 44, 10, 375, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_62" , 54, 9, 375, "RAZ", 1, 1, 0, 0},
- {"RDPEND" , 63, 1, 375, "RO", 0, 0, 0ull, 0ull},
- {"FSYNCMISSED" , 0, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"FSYNCEXTRA" , 1, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"RXWRAP" , 2, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"RXST" , 3, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"TXWRAP" , 4, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"TXRD" , 5, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"TXEMPTY" , 6, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"RXOVF" , 7, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 376, "RAZ", 1, 1, 0, 0},
- {"FSYNCMISSED" , 0, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYNCEXTRA" , 1, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXWRAP" , 2, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXST" , 3, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXWRAP" , 4, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXRD" , 5, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXEMPTY" , 6, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXOVF" , 7, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 377, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 378, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 378, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 379, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 379, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 380, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 381, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 382, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 383, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 384, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 385, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 386, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 387, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 388, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 388, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 388, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"USECLK1" , 1, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 2, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 389, "RAZ", 1, 1, 0, 0},
- {"SAMPPT" , 32, 16, 389, "R/W", 0, 1, 0ull, 0},
- {"DRVTIM" , 48, 16, 389, "R/W", 0, 1, 0ull, 0},
- {"DEBUGINFO" , 0, 64, 390, "RO", 1, 1, 0, 0},
- {"FRAM" , 0, 3, 391, "R/W", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 391, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 391, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 392, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 392, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 393, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 394, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 395, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 396, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 397, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 398, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 399, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 400, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 401, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 401, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 401, "RAZ", 1, 1, 0, 0},
- {"ENA" , 0, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"FSYNCPOL" , 1, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"BCLKPOL" , 2, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"BITLEN" , 3, 2, 402, "R/W", 0, 0, 0ull, 0ull},
- {"EXTRABIT" , 5, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"NUMSLOTS" , 6, 10, 402, "R/W", 0, 1, 0ull, 0},
- {"FSYNCLOC" , 16, 5, 402, "R/W", 0, 0, 0ull, 0ull},
- {"FSYNCLEN" , 21, 5, 402, "R/W", 0, 0, 0ull, 2ull},
- {"RESERVED_26_31" , 26, 6, 402, "RAZ", 1, 1, 0, 0},
- {"FSYNCSAMP" , 32, 16, 402, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_62" , 48, 15, 402, "RAZ", 1, 1, 0, 0},
- {"FSYNCGOOD" , 63, 1, 402, "RO", 0, 0, 0ull, 1ull},
- {"DEBUGINFO" , 0, 64, 403, "RO", 1, 1, 0, 0},
- {"N" , 0, 32, 404, "R/W", 0, 1, 0ull, 0},
- {"NUMSAMP" , 32, 16, 404, "R/W", 0, 1, 0ull, 0},
- {"DELTASAMP" , 48, 16, 404, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 17, 405, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 405, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 406, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 406, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 406, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 406, "RAZ", 1, 1, 0, 0},
- {"MINLEN" , 0, 16, 407, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 407, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 407, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 408, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 408, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 408, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 408, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 408, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 408, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 409, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 409, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 409, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 409, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 409, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 409, "RAZ", 0, 1, 0ull, 0},
- {"L4_MAL" , 8, 1, 409, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 409, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 409, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 409, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 409, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 409, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 409, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 409, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 409, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 409, "RAZ", 0, 0, 0ull, 0ull},
- {"PKTDRP" , 0, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 410, "RAZ", 1, 1, 0, 0},
- {"BCKPRS" , 2, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 410, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 411, "RAZ", 1, 1, 0, 0},
- {"BCKPRS" , 2, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 411, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 412, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 412, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 413, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 413, "RAZ", 1, 1, 0, 0},
- {"CRC_EN" , 12, 1, 413, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 413, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 413, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT" , 20, 4, 413, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 413, "RAZ", 1, 1, 0, 0},
- {"GRP_WAT" , 28, 4, 413, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 413, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 413, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 413, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 413, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 413, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 413, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_63" , 53, 11, 413, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 414, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 414, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 414, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 414, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 414, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 414, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 414, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 414, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 415, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 416, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 416, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 417, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 417, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 417, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 417, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 417, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 417, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 417, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 417, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 417, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 418, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 419, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 420, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 420, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 421, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 421, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 422, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 422, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 423, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 423, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 424, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 424, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 425, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 425, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 426, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 426, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 427, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 427, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 428, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 429, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 429, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 430, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 430, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 431, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 431, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 432, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 432, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 433, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 433, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 434, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 434, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 435, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 435, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 436, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 436, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 436, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 437, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 437, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 437, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 438, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 438, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 439, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 439, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 440, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 440, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 440, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 440, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 441, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 441, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 441, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 441, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 441, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 442, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 442, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 442, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 442, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 443, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 443, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 443, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 443, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 443, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 443, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 443, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 443, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 0, 16, 444, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 444, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 444, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 444, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 445, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 445, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 445, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 445, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 445, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 446, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 446, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 446, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 446, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 446, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 447, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 448, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 448, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 448, "RO", 1, 0, 0, 0ull},
- {"QID_BASE" , 6, 8, 448, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 14, 4, 448, "RO", 1, 0, 0, 0ull},
- {"QID_OFF_MAX" , 18, 4, 448, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 22, 5, 448, "RO", 1, 0, 0, 0ull},
- {"QOS" , 27, 3, 448, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 30, 1, 448, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 31, 1, 448, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 32, 1, 448, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 33, 1, 448, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 34, 1, 448, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 35, 1, 448, "RO", 1, 0, 0, 0ull},
- {"UID" , 36, 3, 448, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 39, 6, 448, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 45, 16, 448, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 61, 3, 448, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 0, 3, 449, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 3, 16, 449, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 19, 16, 449, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 35, 29, 449, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 0, 11, 450, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 450, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 451, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 451, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 451, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 451, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 451, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 451, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 452, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 452, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 452, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 452, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 452, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 452, "RO", 1, 0, 0, 0ull},
- {"RESERVED_28_63" , 28, 36, 452, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 453, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 453, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 453, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 453, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 454, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 454, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 454, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 454, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 454, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 454, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 454, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 454, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 454, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 455, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 455, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 455, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 455, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 455, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 456, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 4, 456, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 456, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 456, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 456, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 6, 456, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 21, 1, 456, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 22, 3, 456, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 25, 1, 456, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 26, 1, 456, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 27, 3, 456, "RO", 1, 0, 0, 0ull},
- {"OUT_CRC" , 30, 1, 456, "RO", 1, 0, 0, 0ull},
- {"IOB" , 31, 1, 456, "RO", 1, 0, 0, 0ull},
- {"CSR" , 32, 1, 456, "RO", 1, 0, 0, 0ull},
- {"RESERVED_33_63" , 33, 31, 456, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 457, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 457, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 457, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 457, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 458, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 459, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 460, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 461, "RO", 0, 0, 0ull, 0ull},
- {"PARITY" , 0, 1, 462, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 462, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 462, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 462, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 463, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 463, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 463, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 463, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 463, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 464, "R/W", 0, 0, 0ull, 0ull},
- {"MODE1" , 3, 3, 464, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 464, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 465, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 466, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 466, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 467, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 467, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 467, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 468, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 468, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 468, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 1, 469, "RO", 0, 0, 0ull, 0ull},
- {"PEND" , 1, 1, 469, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 2, 1, 469, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 3, 1, 469, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 4, 1, 469, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 5, 1, 469, "RO", 0, 0, 0ull, 0ull},
- {"NBT0" , 6, 1, 469, "RO", 0, 0, 0ull, 0ull},
- {"NBT1" , 7, 1, 469, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 8, 1, 469, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 469, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 2, 469, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 469, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 470, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 470, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 471, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 471, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 471, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 471, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 471, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 471, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 471, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 471, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 471, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 471, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 472, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 472, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 473, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 473, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 474, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 474, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 9, 475, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 475, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 476, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_10_63" , 10, 54, 476, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 477, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 477, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 478, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 478, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 478, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 478, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 478, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 478, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 478, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 478, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 478, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 478, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 479, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 479, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 479, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 479, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 479, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 8, 480, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_11" , 8, 4, 480, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 8, 480, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_20_23" , 20, 4, 480, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 9, 480, "RO", 0, 1, 249ull, 0},
- {"RESERVED_33_35" , 33, 3, 480, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 36, 9, 480, "RO", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 480, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 48, 9, 480, "RO", 0, 1, 0ull, 0},
- {"RESERVED_57_63" , 57, 7, 480, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 481, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 481, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 482, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 482, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 483, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 483, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 484, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 484, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 484, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 9, 485, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 485, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 12, 9, 485, "RO", 0, 1, 0ull, 0},
- {"RESERVED_21_23" , 21, 3, 485, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 24, 4, 485, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 485, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 486, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 486, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 486, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 486, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 486, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 8, 487, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_11" , 8, 4, 487, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 8, 487, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_23" , 20, 4, 487, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 487, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 487, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 487, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 488, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 488, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 489, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 489, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 489, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 490, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 490, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 490, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 490, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 490, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 490, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 490, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 491, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 491, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 491, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 491, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 491, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 491, "RAZ", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 491, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 491, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 491, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 491, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 492, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 492, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 492, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 493, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 493, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 494, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 494, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 494, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 494, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 495, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 495, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 495, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 495, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 496, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 496, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 496, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 496, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 496, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 496, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 497, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 497, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 497, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 498, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 498, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 498, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 498, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 498, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 499, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 499, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 499, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 499, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 500, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 500, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 500, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 500, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 500, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 500, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 501, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 501, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 501, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 501, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 502, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 502, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 503, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 503, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 503, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 503, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 504, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 504, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 505, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 505, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 505, "RAZ", 1, 1, 0, 0},
- {"INEPINT" , 0, 16, 506, "RO", 0, 0, 0ull, 0ull},
- {"OUTEPINT" , 16, 16, 506, "RO", 0, 0, 0ull, 0ull},
- {"INEPMSK" , 0, 16, 507, "R/W", 0, 0, 0ull, 0ull},
- {"OUTEPMSK" , 16, 16, 507, "R/W", 0, 0, 0ull, 0ull},
- {"DEVSPD" , 0, 2, 508, "R/W", 0, 0, 0ull, 0ull},
- {"NZSTSOUTHSHK" , 2, 1, 508, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 508, "RAZ", 1, 1, 0, 0},
- {"DEVADDR" , 4, 7, 508, "R/W", 0, 0, 0ull, 0ull},
- {"PERFRINT" , 11, 2, 508, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_17" , 13, 5, 508, "RAZ", 1, 1, 0, 0},
- {"EPMISCNT" , 18, 5, 508, "R/W", 0, 0, 8ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 508, "RAZ", 1, 1, 0, 0},
- {"RMTWKUPSIG" , 0, 1, 509, "R/W", 0, 0, 0ull, 0ull},
- {"SFTDISCON" , 1, 1, 509, "R/W", 0, 0, 0ull, 0ull},
- {"GNPINNAKSTS" , 2, 1, 509, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKSTS" , 3, 1, 509, "RO", 0, 0, 0ull, 0ull},
- {"TSTCTL" , 4, 3, 509, "R/W", 0, 0, 0ull, 0ull},
- {"SGNPINNAK" , 7, 1, 509, "WO", 0, 0, 0ull, 0ull},
- {"CGNPINNAK" , 8, 1, 509, "WO", 0, 0, 0ull, 0ull},
- {"SGOUTNAK" , 9, 1, 509, "WO", 0, 0, 0ull, 0ull},
- {"CGOUTNAK" , 10, 1, 509, "WO", 0, 0, 0ull, 0ull},
- {"PWRONPRGDONE" , 11, 1, 509, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 509, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 510, "R/W", 0, 0, 0ull, 0ull},
- {"NEXTEP" , 11, 4, 510, "R/W", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 510, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 510, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 510, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 510, "RAZ", 1, 1, 0, 0},
- {"STALL" , 21, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 22, 4, 510, "R/W", 0, 0, 0ull, 0ull},
- {"CNAK" , 26, 1, 510, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 510, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 510, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 510, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 510, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMEOUT" , 3, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMP" , 4, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNEPMIS" , 5, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
- {"INEPNAKEFF" , 6, 1, 511, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 511, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"TIMEOUTMSK" , 3, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMPMSK" , 4, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNEPMISMSK" , 5, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"INEPNAKEFFMSK" , 6, 1, 512, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 512, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 513, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 513, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 513, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 513, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 514, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_14" , 11, 4, 514, "RAZ", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 514, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 514, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 514, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 514, "R/W", 0, 0, 0ull, 0ull},
- {"SNP" , 20, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"STALL" , 21, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_25" , 22, 4, 514, "RAZ", 1, 1, 0, 0},
- {"CNAK" , 26, 1, 514, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 514, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 514, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 514, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"SETUP" , 3, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDIS" , 4, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 515, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"SETUPMSK" , 3, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDISMSK" , 4, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 516, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 517, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 517, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 517, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 517, "RAZ", 1, 1, 0, 0},
- {"DPTXFSTADDR" , 0, 16, 518, "RO", 0, 0, 0ull, 0ull},
- {"DPTXFSIZE" , 16, 16, 518, "RO", 0, 0, 1896ull, 1896ull},
- {"SUSPSTS" , 0, 1, 519, "RO", 0, 0, 0ull, 0ull},
- {"ENUMSPD" , 1, 2, 519, "RO", 0, 0, 0ull, 0ull},
- {"ERRTICERR" , 3, 1, 519, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 519, "RAZ", 1, 1, 0, 0},
- {"SOFFN" , 8, 14, 519, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 519, "RAZ", 1, 1, 0, 0},
- {"INTKNWPTR" , 0, 5, 520, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 520, "RAZ", 1, 1, 0, 0},
- {"WRAPBIT" , 7, 1, 520, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 8, 24, 520, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 521, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 522, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 523, "RO", 0, 0, 0ull, 0ull},
- {"GLBLINTRMSK" , 0, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"HBSTLEN" , 1, 4, 524, "R/W", 0, 0, 0ull, 0ull},
- {"DMAEN" , 5, 1, 524, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 524, "RAZ", 1, 1, 0, 0},
- {"NPTXFEMPLVL" , 7, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"PTXFEMPLVL" , 8, 1, 524, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_31" , 9, 23, 524, "RAZ", 1, 1, 0, 0},
- {"EPDIR" , 0, 32, 525, "RO", 0, 0, 0ull, 0ull},
- {"OTGMODE" , 0, 3, 526, "RO", 0, 0, 2ull, 2ull},
- {"OTGARCH" , 3, 2, 526, "RO", 0, 0, 1ull, 1ull},
- {"SINGPNT" , 5, 1, 526, "RO", 0, 0, 0ull, 0ull},
- {"HSPHYTYPE" , 6, 2, 526, "RO", 0, 0, 1ull, 1ull},
- {"FSPHYTYPE" , 8, 2, 526, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVEPS" , 10, 4, 526, "RO", 0, 0, 4ull, 4ull},
- {"NUMHSTCHNL" , 14, 4, 526, "RO", 0, 0, 7ull, 7ull},
- {"PERIOSUPPORT" , 18, 1, 526, "RO", 0, 0, 1ull, 1ull},
- {"DYNFIFOSIZING" , 19, 1, 526, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_20_21" , 20, 2, 526, "RAZ", 1, 1, 0, 0},
- {"NPTXQDEPTH" , 22, 2, 526, "RO", 0, 0, 2ull, 2ull},
- {"PTXQDEPTH" , 24, 2, 526, "RO", 0, 0, 2ull, 2ull},
- {"TKNQDEPTH" , 26, 5, 526, "RO", 0, 0, 30ull, 30ull},
- {"RESERVED_31_31" , 31, 1, 526, "RAZ", 1, 1, 0, 0},
- {"XFERSIZEWIDTH" , 0, 4, 527, "RO", 0, 0, 8ull, 8ull},
- {"PKTSIZEWIDTH" , 4, 3, 527, "RO", 0, 0, 6ull, 6ull},
- {"OTGEN" , 7, 1, 527, "RO", 0, 0, 1ull, 1ull},
- {"I2C_SELECTION" , 8, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"OPTFEATURE" , 10, 1, 527, "RO", 0, 0, 1ull, 1ull},
- {"RSTTYPE" , 11, 1, 527, "RO", 0, 0, 1ull, 1ull},
- {"AHBPHYSYNC" , 12, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 527, "RAZ", 1, 1, 0, 0},
- {"DFIFODEPTH" , 16, 16, 527, "RO", 0, 0, 1824ull, 1824ull},
- {"NUMDEVPERIOEPS" , 0, 4, 528, "RO", 0, 0, 4ull, 4ull},
- {"ENABLEPWROPT" , 4, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"AHBFREQ" , 5, 1, 528, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_13" , 6, 8, 528, "RAZ", 1, 1, 0, 0},
- {"PHYDATAWIDTH" , 14, 2, 528, "RO", 0, 0, 1ull, 1ull},
- {"NUMCTLEPS" , 16, 4, 528, "RO", 0, 0, 4ull, 4ull},
- {"IDDGFLTR" , 20, 1, 528, "RO", 0, 0, 1ull, 1ull},
- {"VBUSVALIDFLTR" , 21, 1, 528, "RO", 0, 0, 1ull, 1ull},
- {"AVALIDFLTR" , 22, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"BVALIDFLTR" , 23, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"SESSENDFLTR" , 24, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"ENDEDTRFIFO" , 25, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVMODINEND" , 26, 4, 528, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_30_31" , 30, 2, 528, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 529, "RAZ", 1, 1, 0, 0},
- {"MODEMISMSK" , 1, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"OTGINTMSK" , 2, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"SOFMSK" , 3, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RXFLVLMSK" , 4, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"NPTXFEMPMSK" , 5, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"GINNAKEFFMSK" , 6, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFFMSK" , 7, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"ULPICKINTMSK" , 8, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"ERLYSUSPMSK" , 10, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"USBSUSPMSK" , 11, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"USBRSTMSK" , 12, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"ENUMDONEMSK" , 13, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"ISOOUTDROPMSK" , 14, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"EOPFMSK" , 15, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 529, "RAZ", 1, 1, 0, 0},
- {"EPMISMSK" , 17, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"INEPINTMSK" , 18, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"OEPINTMSK" , 19, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPISOINMSK" , 20, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPLPMSK" , 21, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"FETSUSPMSK" , 22, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 529, "RAZ", 1, 1, 0, 0},
- {"PRTINTMSK" , 24, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"HCHINTMSK" , 25, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"PTXFEMPMSK" , 26, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 529, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNGMSK" , 28, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"DISCONNINTMSK" , 29, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"SESSREQINTMSK" , 30, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"WKUPINTMSK" , 31, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"CURMOD" , 0, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"MODEMIS" , 1, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"OTGINT" , 2, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"SOF" , 3, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXFLVL" , 4, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"NPTXFEMP" , 5, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"GINNAKEFF" , 6, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFF" , 7, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"ULPICKINT" , 8, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"ERLYSUSP" , 10, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBSUSP" , 11, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBRST" , 12, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENUMDONE" , 13, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"ISOOUTDROP" , 14, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"EOPF" , 15, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 530, "RAZ", 1, 1, 0, 0},
- {"EPMIS" , 17, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"IEPINT" , 18, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"OEPINT" , 19, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"INCOMPISOIN" , 20, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"INCOMPLP" , 21, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"FETSUSP" , 22, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 530, "RAZ", 1, 1, 0, 0},
- {"PRTINT" , 24, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"HCHINT" , 25, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"PTXFEMP" , 26, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 530, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNG" , 28, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"DISCONNINT" , 29, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"SESSREQINT" , 30, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"WKUPINT" , 31, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
- {"NPTXFSTADDR" , 0, 16, 531, "R/W", 0, 0, 1824ull, 456ull},
- {"NPTXFDEP" , 16, 16, 531, "R/W", 0, 0, 1824ull, 912ull},
- {"NPTXFSPCAVAIL" , 0, 16, 532, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQSPCAVAIL" , 16, 8, 532, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQTOP" , 24, 7, 532, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 532, "RAZ", 1, 1, 0, 0},
- {"SESREQSCS" , 0, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"SESREQ" , 1, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 533, "RAZ", 1, 1, 0, 0},
- {"HSTNEGSCS" , 8, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"HNPREQ" , 9, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"HSTSETHNPEN" , 10, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"DEVHNPEN" , 11, 1, 533, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 533, "RAZ", 1, 1, 0, 0},
- {"CONIDSTS" , 16, 1, 533, "RO", 1, 1, 0, 0},
- {"DBNCTIME" , 17, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"ASESVLD" , 18, 1, 533, "RO", 1, 1, 0, 0},
- {"BSESVLD" , 19, 1, 533, "RO", 1, 1, 0, 0},
- {"RESERVED_20_31" , 20, 12, 533, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 534, "RAZ", 1, 1, 0, 0},
- {"SESENDDET" , 2, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 534, "RAZ", 1, 1, 0, 0},
- {"SESREQSUCSTSCHNG" , 8, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSTNEGSUCSTSCHNG" , 9, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_16" , 10, 7, 534, "RAZ", 1, 1, 0, 0},
- {"HSTNEGDET" , 17, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
- {"ADEVTOUTCHG" , 18, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBNCEDONE" , 19, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 534, "RAZ", 1, 1, 0, 0},
- {"CSFTRST" , 0, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"HSFTRST" , 1, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"FRMCNTRRST" , 2, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNQFLSH" , 3, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"RXFFLSH" , 4, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"TXFFLSH" , 5, 1, 535, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 6, 5, 535, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_29" , 11, 19, 535, "RAZ", 1, 1, 0, 0},
- {"DMAREQ" , 30, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"AHBIDLE" , 31, 1, 535, "RO", 0, 0, 1ull, 1ull},
- {"RXFDEP" , 0, 16, 536, "R/W", 0, 0, 1824ull, 456ull},
- {"RESERVED_16_31" , 16, 16, 536, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 537, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 537, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 537, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 537, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 537, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 537, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 538, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 538, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 538, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 538, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 538, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 539, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 539, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 539, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 539, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 539, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 539, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 540, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 540, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 540, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 540, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 540, "RAZ", 1, 1, 0, 0},
- {"SYNOPSYSID" , 0, 32, 541, "RO", 1, 1, 0, 0},
- {"TOUTCAL" , 0, 3, 542, "R/W", 0, 0, 0ull, 0ull},
- {"PHYIF" , 3, 1, 542, "RO", 0, 0, 1ull, 1ull},
- {"ULPI_UTMI_SEL" , 4, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"FSINTF" , 5, 1, 542, "WO", 0, 0, 0ull, 0ull},
- {"PHYSEL" , 6, 1, 542, "WO", 0, 0, 0ull, 0ull},
- {"DDRSEL" , 7, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"SRPCAP" , 8, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"HNPCAP" , 9, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"USBTRDTIM" , 10, 4, 542, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_14_14" , 14, 1, 542, "RAZ", 1, 1, 0, 0},
- {"PHYLPWRCLKSEL" , 15, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"OTGI2CSEL" , 16, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 542, "RAZ", 1, 1, 0, 0},
- {"HAINT" , 0, 16, 543, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 543, "RAZ", 1, 1, 0, 0},
- {"HAINTMSK" , 0, 16, 544, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 544, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 545, "R/W", 0, 0, 0ull, 0ull},
- {"EPNUM" , 11, 4, 545, "R/W", 0, 0, 0ull, 0ull},
- {"EPDIR" , 15, 1, 545, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 545, "RAZ", 1, 1, 0, 0},
- {"LSPDDEV" , 17, 1, 545, "R/W", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 545, "R/W", 0, 0, 0ull, 0ull},
- {"EC" , 20, 2, 545, "R/W", 0, 0, 0ull, 0ull},
- {"DEVADDR" , 22, 7, 545, "R/W", 0, 0, 0ull, 0ull},
- {"ODDFRM" , 29, 1, 545, "R/W", 0, 0, 0ull, 0ull},
- {"CHDIS" , 30, 1, 545, "R/W", 0, 0, 0ull, 0ull},
- {"CHENA" , 31, 1, 545, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSPCLKSEL" , 0, 2, 546, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSSUPP" , 2, 1, 546, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 546, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPL" , 0, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"CHHLTD" , 1, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"STALL" , 3, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAK" , 4, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACK" , 5, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"NYET" , 6, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"XACTERR" , 7, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"BBLERR" , 8, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMOVRUN" , 9, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATATGLERR" , 10, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 547, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"CHHLTDMSK" , 1, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"STALLMSK" , 3, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"NAKMSK" , 4, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"ACKMSK" , 5, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"NYETMSK" , 6, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"XACTERRMSK" , 7, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"BBLERRMSK" , 8, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"FRMOVRUNMSK" , 9, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"DATATGLERRMSK" , 10, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 548, "RAZ", 1, 1, 0, 0},
- {"PRTADDR" , 0, 7, 549, "R/W", 0, 0, 0ull, 0ull},
- {"HUBADDR" , 7, 7, 549, "R/W", 0, 0, 0ull, 0ull},
- {"XACTPOS" , 14, 2, 549, "R/W", 0, 0, 0ull, 0ull},
- {"COMPSPLT" , 16, 1, 549, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_30" , 17, 14, 549, "RAZ", 1, 1, 0, 0},
- {"SPLTENA" , 31, 1, 549, "R/W", 0, 0, 0ull, 0ull},
- {"XFERSIZE" , 0, 19, 550, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 550, "R/W", 0, 0, 0ull, 0ull},
- {"PID" , 29, 2, 550, "R/W", 0, 0, 0ull, 0ull},
- {"DOPNG" , 31, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"FRINT" , 0, 16, 551, "R/W", 0, 0, 2959ull, 3750ull},
- {"RESERVED_16_31" , 16, 16, 551, "RAZ", 1, 1, 0, 0},
- {"FRNUM" , 0, 16, 552, "RO", 0, 0, 16383ull, 0ull},
- {"FRREM" , 16, 16, 552, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNSTS" , 0, 1, 553, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNDET" , 1, 1, 553, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENA" , 2, 1, 553, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENCHNG" , 3, 1, 553, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRACT" , 4, 1, 553, "RO", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRCHNG" , 5, 1, 553, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTRES" , 6, 1, 553, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSUSP" , 7, 1, 553, "R/W", 0, 0, 0ull, 0ull},
- {"PRTRST" , 8, 1, 553, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 553, "RAZ", 1, 1, 0, 0},
- {"PRTLNSTS" , 10, 2, 553, "RO", 0, 0, 0ull, 0ull},
- {"PRTPWR" , 12, 1, 553, "R/W", 0, 0, 0ull, 0ull},
- {"PRTTSTCTL" , 13, 4, 553, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSPD" , 17, 2, 553, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 553, "RAZ", 1, 1, 0, 0},
- {"PTXFSTADDR" , 0, 16, 554, "R/W", 0, 0, 3648ull, 912ull},
- {"PTXFSIZE" , 16, 16, 554, "R/W", 0, 0, 256ull, 456ull},
- {"PTXFSPCAVAIL" , 0, 16, 555, "RO", 0, 0, 0ull, 0ull},
- {"PTXQSPCAVAIL" , 16, 8, 555, "RO", 0, 0, 0ull, 0ull},
- {"PTXQTOP" , 24, 8, 555, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 32, 556, "R/W", 0, 0, 0ull, 0ull},
- {"STOPPCLK" , 0, 1, 557, "R/W", 0, 0, 0ull, 0ull},
- {"GATEHCLK" , 1, 1, 557, "R/W", 0, 0, 0ull, 0ull},
- {"PWRCLMP" , 2, 1, 557, "R/W", 0, 0, 0ull, 0ull},
- {"RSTPDWNMODULE" , 3, 1, 557, "R/W", 0, 0, 0ull, 0ull},
- {"PHYSUSPENDED" , 4, 1, 557, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 557, "RAZ", 1, 1, 0, 0},
- {"NOF_BIS" , 0, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"NIF_BIS" , 1, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"USBC_BIS" , 2, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"N2UF_BIS" , 3, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"E2HC_BIS" , 4, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"U2NF_BIS" , 5, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"U2NC_BIS" , 6, 1, 558, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 558, "RAZ", 1, 1, 0, 0},
- {"DIVIDE" , 0, 3, 559, "R/W", 0, 0, 4ull, 0ull},
- {"HRST" , 3, 1, 559, "R/W", 0, 0, 0ull, 1ull},
- {"PRST" , 4, 1, 559, "R/W", 0, 0, 0ull, 1ull},
- {"ENABLE" , 5, 1, 559, "R/W", 0, 0, 1ull, 1ull},
- {"POR" , 6, 1, 559, "R/W", 0, 0, 1ull, 0ull},
- {"S_BIST" , 7, 1, 559, "R/W", 0, 0, 0ull, 1ull},
- {"SD_MODE" , 8, 2, 559, "R/W", 0, 0, 0ull, 0ull},
- {"CDIV_BYP" , 10, 1, 559, "R/W", 0, 0, 0ull, 0ull},
- {"P_C_SEL" , 11, 2, 559, "R/W", 0, 0, 2ull, 0ull},
- {"P_COM_ON" , 13, 1, 559, "R/W", 0, 0, 1ull, 1ull},
- {"P_RTYPE" , 14, 2, 559, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 559, "RAZ", 1, 1, 0, 0},
- {"HCLK_RST" , 17, 1, 559, "R/W", 0, 0, 1ull, 1ull},
- {"DIVIDE2" , 18, 2, 559, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_63" , 20, 44, 559, "RAZ", 1, 1, 0, 0},
- {"L2C_EMOD" , 0, 2, 560, "R/W", 0, 0, 1ull, 1ull},
- {"INV_A2" , 2, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_TEST" , 3, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_STT" , 4, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_0PAG" , 5, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 560, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 561, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 561, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 562, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 562, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 563, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 563, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 564, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 564, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 565, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 565, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 566, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 566, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 567, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 567, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 568, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 568, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 569, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 569, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 570, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 570, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 571, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 571, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 572, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 572, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 573, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 573, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 574, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 574, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 575, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 575, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 576, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 576, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 4, 577, "R/W", 0, 0, 0ull, 0ull},
- {"CHANNEL" , 4, 5, 577, "R/W", 0, 0, 0ull, 0ull},
- {"COUNT" , 9, 11, 577, "R/W", 0, 0, 0ull, 0ull},
- {"F_ADDR" , 20, 18, 577, "R/W", 0, 0, 0ull, 0ull},
- {"REQ" , 38, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
- {"DONE" , 39, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 577, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_A_F" , 15, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_E" , 16, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_F" , 17, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PF" , 25, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 578, "RAZ", 0, 0, 0ull, 0ull},
- {"LTL_F_PE" , 32, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPF" , 35, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPE" , 36, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPF" , 37, 1, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 578, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 579, "R/W1C", 1, 0, 0, 0ull},
- {"L2C_A_F" , 15, 1, 579, "R/W1C", 1, 0, 0, 0ull},
- {"LT_FI_E" , 16, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_FI_F" , 17, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 579, "R/W1C", 1, 0, 0, 0ull},
- {"UOD_PF" , 25, 1, 579, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_26_31" , 26, 6, 579, "RAZ", 1, 0, 0, 0ull},
- {"LTL_F_PE" , 32, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 579, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_RPF" , 35, 1, 579, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPE" , 36, 1, 579, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPF" , 37, 1, 579, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_38_63" , 38, 26, 579, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_IN" , 1, 8, 580, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 9, 4, 580, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 13, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ENB" , 14, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_ENB" , 15, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_ENB" , 16, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_EN" , 17, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_ENH" , 18, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_22" , 19, 4, 580, "RAZ", 0, 0, 0ull, 0ull},
- {"HST_MODE" , 23, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"DM_PULLD" , 24, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"DP_PULLD" , 25, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"TCLK" , 26, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"USBP_BIST" , 27, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"USBC_END" , 28, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_BMODE" , 29, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"TXPREEMPHASISTUNE" , 30, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 580, "RAZ", 0, 0, 0ull, 0ull},
- {"TDATA_OUT" , 32, 4, 580, "RO", 1, 1, 0, 0},
- {"BIST_ERR" , 36, 1, 580, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 37, 1, 580, "RO", 0, 0, 0ull, 0ull},
- {"HSBIST" , 38, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 39, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 40, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"DRVVBUS" , 41, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 42, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"OTGDISABLE" , 43, 1, 580, "R/W", 0, 0, 1ull, 1ull},
- {"OTGTUNE" , 44, 3, 580, "R/W", 0, 0, 2ull, 2ull},
- {"COMPDISTUNE" , 47, 3, 580, "R/W", 0, 0, 2ull, 2ull},
- {"SQRXTUNE" , 50, 3, 580, "R/W", 0, 0, 3ull, 3ull},
- {"TXHSXVTUNE" , 53, 2, 580, "R/W", 0, 0, 0ull, 0ull},
- {"TXFSLSTUNE" , 55, 4, 580, "R/W", 0, 0, 3ull, 3ull},
- {"TXVREFTUNE" , 59, 4, 580, "R/W", 0, 0, 7ull, 7ull},
- {"TXRISETUNE" , 63, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xxp1[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 14, 0},
- {"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 14},
- {"cvmx_agl_gmx_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 12, 16},
- {"cvmx_agl_gmx_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 3, 28},
- {"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 7, 31},
- {"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 38},
- {"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 39},
- {"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 40},
- {"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 1, 41},
- {"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 1, 42},
- {"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 1, 43},
- {"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 44},
- {"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 4, 46},
- {"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 50},
- {"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 10, 52},
- {"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 11, 62},
- {"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 73},
- {"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 75},
- {"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 77},
- {"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 19, 79},
- {"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 19, 98},
- {"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 2, 117},
- {"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 40, 2, 119},
- {"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 121},
- {"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 123},
- {"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 125},
- {"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 127},
- {"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 129},
- {"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 131},
- {"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 133},
- {"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 135},
- {"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 137},
- {"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 139},
- {"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 4, 141},
- {"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 2, 145},
- {"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 147},
- {"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 2, 149},
- {"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 70, 4, 151},
- {"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 4, 155},
- {"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 2, 159},
- {"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 3, 161},
- {"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 5, 164},
- {"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 3, 169},
- {"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 2, 172},
- {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 81, 2, 174},
- {"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 176},
- {"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 85, 2, 178},
- {"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 87, 2, 180},
- {"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 89, 2, 182},
- {"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 184},
- {"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 93, 2, 186},
- {"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 95, 2, 188},
- {"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 97, 2, 190},
- {"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 2, 192},
- {"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 194},
- {"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 2, 196},
- {"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 2, 198},
- {"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 2, 200},
- {"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 109, 2, 202},
- {"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 111, 2, 204},
- {"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 2, 206},
- {"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 115, 2, 208},
- {"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 116, 2, 210},
- {"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 117, 3, 212},
- {"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 118, 10, 215},
- {"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 10, 225},
- {"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 120, 2, 235},
- {"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 121, 2, 237},
- {"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 6, 239},
- {"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 123, 2, 245},
- {"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 124, 2, 247},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 125, 2, 249},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 126, 2, 251},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 127, 2, 253},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 128, 2, 255},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 129, 22, 257},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 138, 6, 279},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 147, 22, 285},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 151, 6, 307},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 155, 22, 313},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 164, 22, 335},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 168, 6, 357},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 169, 2, 363},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 173, 2, 365},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 177, 2, 367},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 178, 2, 369},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 179, 2, 371},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 180, 1, 373},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 184, 3, 374},
- {"cvmx_ciu_qlm_dcok" , CVMX_CSR_DB_TYPE_NCB, 64, 185, 2, 377},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 6, 379},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 187, 8, 385},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 188, 2, 393},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 189, 2, 395},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 190, 2, 397},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 191, 2, 399},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 192, 3, 401},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 196, 7, 404},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 200, 6, 411},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 201, 7, 417},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 202, 29, 424},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 203, 29, 453},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 204, 2, 482},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 212, 2, 484},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 220, 3, 486},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 221, 3, 489},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 222, 2, 492},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 223, 2, 494},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 224, 7, 496},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 225, 2, 503},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 226, 2, 505},
- {"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 227, 5, 507},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 228, 7, 512},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 229, 2, 519},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 230, 10, 521},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 234, 1, 531},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 238, 1, 532},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 242, 1, 533},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 1, 534},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 250, 1, 535},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 1, 536},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 537},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 262, 4, 539},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 266, 2, 543},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 270, 9, 545},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 274, 11, 554},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 278, 2, 565},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 27, 567},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 286, 27, 594},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 290, 2, 621},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 294, 2, 623},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 298, 2, 625},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 2, 627},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 306, 2, 629},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 310, 2, 631},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 314, 2, 633},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 318, 2, 635},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 322, 2, 637},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 326, 2, 639},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 330, 2, 641},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 334, 2, 643},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 338, 4, 645},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 342, 2, 649},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 346, 2, 651},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 350, 2, 653},
- {"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 354, 4, 655},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 355, 4, 659},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 356, 2, 663},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 357, 5, 665},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 358, 2, 670},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 359, 2, 672},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 363, 3, 674},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 364, 5, 677},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 368, 2, 682},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 372, 3, 684},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 2, 687},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 380, 2, 689},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 384, 2, 691},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 3, 693},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 2, 696},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 2, 698},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 2, 700},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 2, 702},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 704},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 2, 706},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 2, 708},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 420, 2, 710},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 2, 712},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 428, 2, 714},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 2, 716},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 2, 718},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 2, 720},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 444, 2, 722},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 724},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 452, 2, 726},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 2, 728},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 457, 2, 730},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 458, 2, 732},
- {"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 459, 2, 734},
- {"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 2, 736},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 461, 3, 738},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 462, 8, 741},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 8, 749},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 2, 757},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 465, 2, 759},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 466, 6, 761},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 467, 2, 767},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 2, 769},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 469, 2, 771},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 9, 773},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 3, 782},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 472, 9, 785},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 488, 2, 794},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 492, 2, 796},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 493, 2, 798},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 494, 2, 800},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 495, 2, 802},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 496, 19, 804},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 497, 6, 823},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 498, 3, 829},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 3, 832},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 500, 3, 835},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 501, 5, 838},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 502, 5, 843},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 1, 848},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 504, 1, 849},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 505, 7, 850},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 506, 7, 857},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 3, 864},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 508, 3, 867},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 509, 3, 870},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 510, 5, 873},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 511, 5, 878},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 512, 1, 883},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 513, 1, 884},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 514, 3, 885},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 3, 888},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 516, 3, 891},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 2, 894},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 518, 2, 896},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 519, 2, 898},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 520, 2, 900},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 521, 19, 902},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 522, 2, 921},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 523, 1, 923},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 524, 15, 924},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 525, 13, 939},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 526, 13, 952},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 527, 2, 965},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 528, 2, 967},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 529, 2, 969},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 530, 3, 971},
- {"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 534, 3, 974},
- {"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 538, 2, 977},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 542, 2, 979},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 546, 2, 981},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 610, 1, 983},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 612, 1, 984},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 614, 6, 985},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 615, 5, 991},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 616, 6, 996},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 617, 7, 1002},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 618, 2, 1009},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 626, 2, 1011},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 627, 3, 1013},
- {"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 628, 2, 1016},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 629, 5, 1018},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 637, 3, 1023},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 638, 4, 1026},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 639, 3, 1030},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 640, 2, 1033},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 641, 2, 1035},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 642, 8, 1037},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 643, 9, 1045},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 644, 8, 1054},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 645, 12, 1062},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 646, 9, 1074},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 647, 5, 1083},
- {"cvmx_l2c_grpwrr0" , CVMX_CSR_DB_TYPE_RSL, 64, 648, 2, 1088},
- {"cvmx_l2c_grpwrr1" , CVMX_CSR_DB_TYPE_RSL, 64, 649, 2, 1090},
- {"cvmx_l2c_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 650, 10, 1092},
- {"cvmx_l2c_int_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 651, 10, 1102},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 652, 4, 1112},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 653, 2, 1116},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 654, 16, 1118},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 655, 19, 1134},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 656, 3, 1153},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 657, 4, 1156},
- {"cvmx_l2c_oob" , CVMX_CSR_DB_TYPE_RSL, 64, 658, 3, 1160},
- {"cvmx_l2c_oob1" , CVMX_CSR_DB_TYPE_RSL, 64, 659, 6, 1163},
- {"cvmx_l2c_oob2" , CVMX_CSR_DB_TYPE_RSL, 64, 660, 6, 1169},
- {"cvmx_l2c_oob3" , CVMX_CSR_DB_TYPE_RSL, 64, 661, 6, 1175},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 662, 2, 1181},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 666, 17, 1183},
- {"cvmx_l2c_ppgrp" , CVMX_CSR_DB_TYPE_RSL, 64, 667, 5, 1200},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 668, 5, 1205},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 669, 2, 1210},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 670, 3, 1212},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 671, 2, 1215},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 672, 2, 1217},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 673, 2, 1219},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 674, 7, 1221},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 675, 5, 1228},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 676, 3, 1233},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 677, 3, 1236},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 678, 2, 1239},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 679, 2, 1241},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 680, 2, 1243},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 681, 6, 1245},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 682, 14, 1251},
- {"cvmx_lmc#_bist_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 683, 2, 1265},
- {"cvmx_lmc#_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 684, 8, 1267},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 685, 7, 1275},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 686, 19, 1282},
- {"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 687, 8, 1301},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 688, 2, 1309},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 689, 2, 1311},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 690, 18, 1313},
- {"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 691, 6, 1331},
- {"cvmx_lmc#_dll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 692, 5, 1337},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 693, 5, 1342},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 694, 5, 1347},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 695, 6, 1352},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 696, 2, 1358},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 697, 2, 1360},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 698, 14, 1362},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 699, 9, 1376},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 700, 2, 1385},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 701, 2, 1387},
- {"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 702, 14, 1389},
- {"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 703, 6, 1403},
- {"cvmx_lmc#_read_level_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 704, 7, 1409},
- {"cvmx_lmc#_read_level_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 705, 4, 1416},
- {"cvmx_lmc#_read_level_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 706, 11, 1420},
- {"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 710, 6, 1431},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 711, 9, 1437},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 712, 5, 1446},
- {"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 713, 5, 1451},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 714, 5, 1456},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 715, 3, 1461},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 716, 10, 1464},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 718, 3, 1474},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 720, 3, 1477},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 722, 15, 1480},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 724, 3, 1495},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 725, 3, 1498},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 726, 3, 1501},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 727, 5, 1504},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 729, 1, 1509},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 730, 13, 1510},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 738, 13, 1523},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 746, 6, 1536},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 747, 1, 1542},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 751, 2, 1543},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 752, 2, 1545},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 753, 13, 1547},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 754, 8, 1560},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 755, 4, 1568},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 756, 1, 1572},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 757, 3, 1573},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 2, 1576},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 759, 6, 1578},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 760, 7, 1584},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 761, 4, 1591},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 762, 2, 1595},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 763, 2, 1597},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 764, 13, 1599},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 766, 12, 1612},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 768, 3, 1624},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 770, 3, 1627},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 772, 2, 1630},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 774, 2, 1632},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 776, 2, 1634},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 778, 7, 1636},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 780, 2, 1643},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 782, 7, 1645},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 784, 4, 1652},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 786, 8, 1656},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 788, 9, 1664},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 790, 7, 1673},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 792, 9, 1680},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 794, 2, 1689},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 2, 1691},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 798, 4, 1693},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 800, 2, 1697},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 2, 1699},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 2, 1701},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 4, 1703},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 2, 1707},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 2, 1709},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 2, 1711},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 814, 2, 1713},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 2, 1715},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 818, 2, 1717},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 6, 1719},
- {"cvmx_mio_uart2_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 2, 1725},
- {"cvmx_mio_uart2_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 823, 2, 1727},
- {"cvmx_mio_uart2_far" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 2, 1729},
- {"cvmx_mio_uart2_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 825, 7, 1731},
- {"cvmx_mio_uart2_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 2, 1738},
- {"cvmx_mio_uart2_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 827, 7, 1740},
- {"cvmx_mio_uart2_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 4, 1747},
- {"cvmx_mio_uart2_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 829, 8, 1751},
- {"cvmx_mio_uart2_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 830, 9, 1759},
- {"cvmx_mio_uart2_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 831, 7, 1768},
- {"cvmx_mio_uart2_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 832, 9, 1775},
- {"cvmx_mio_uart2_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 833, 2, 1784},
- {"cvmx_mio_uart2_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 834, 2, 1786},
- {"cvmx_mio_uart2_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 835, 4, 1788},
- {"cvmx_mio_uart2_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 836, 2, 1792},
- {"cvmx_mio_uart2_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 837, 2, 1794},
- {"cvmx_mio_uart2_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 838, 2, 1796},
- {"cvmx_mio_uart2_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 839, 4, 1798},
- {"cvmx_mio_uart2_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 840, 2, 1802},
- {"cvmx_mio_uart2_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 841, 2, 1804},
- {"cvmx_mio_uart2_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 842, 2, 1806},
- {"cvmx_mio_uart2_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 843, 2, 1808},
- {"cvmx_mio_uart2_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 844, 2, 1810},
- {"cvmx_mio_uart2_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 845, 2, 1812},
- {"cvmx_mio_uart2_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 846, 6, 1814},
- {"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 847, 5, 1820},
- {"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 849, 8, 1825},
- {"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 851, 8, 1833},
- {"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 853, 2, 1841},
- {"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 855, 3, 1843},
- {"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 857, 5, 1846},
- {"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 859, 4, 1851},
- {"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 861, 8, 1855},
- {"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 863, 2, 1863},
- {"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 865, 2, 1865},
- {"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 867, 5, 1867},
- {"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 869, 4, 1872},
- {"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 871, 4, 1876},
- {"cvmx_npei_bar1_index#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 873, 5, 1880},
- {"cvmx_npei_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 905, 47, 1885},
- {"cvmx_npei_ctl_port0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 906, 17, 1932},
- {"cvmx_npei_ctl_port1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 907, 17, 1949},
- {"cvmx_npei_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 908, 10, 1966},
- {"cvmx_npei_ctl_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909, 11, 1976},
- {"cvmx_npei_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 910, 5, 1987},
- {"cvmx_npei_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 911, 8, 1992},
- {"cvmx_npei_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 912, 2, 2000},
- {"cvmx_npei_dma#_counts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 913, 3, 2002},
- {"cvmx_npei_dma#_dbell" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 917, 2, 2005},
- {"cvmx_npei_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 921, 3, 2007},
- {"cvmx_npei_dma#_naddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 925, 2, 2010},
- {"cvmx_npei_dma0_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 929, 2, 2012},
- {"cvmx_npei_dma1_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 930, 2, 2014},
- {"cvmx_npei_dma_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 931, 2, 2016},
- {"cvmx_npei_dma_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932, 15, 2018},
- {"cvmx_npei_dma_state1_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933, 11, 2033},
- {"cvmx_npei_dma_state2_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934, 6, 2044},
- {"cvmx_npei_dma_state3_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935, 5, 2050},
- {"cvmx_npei_dma_state4_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936, 5, 2055},
- {"cvmx_npei_int_a_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937, 3, 2060},
- {"cvmx_npei_int_a_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938, 3, 2063},
- {"cvmx_npei_int_a_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939, 3, 2066},
- {"cvmx_npei_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940, 64, 2069},
- {"cvmx_npei_int_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941, 63, 2133},
- {"cvmx_npei_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942, 61, 2196},
- {"cvmx_npei_int_sum2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943, 61, 2257},
- {"cvmx_npei_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944, 1, 2318},
- {"cvmx_npei_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945, 1, 2319},
- {"cvmx_npei_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946, 3, 2320},
- {"cvmx_npei_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947, 11, 2323},
- {"cvmx_npei_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 963, 1, 2334},
- {"cvmx_npei_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 964, 1, 2335},
- {"cvmx_npei_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 965, 1, 2336},
- {"cvmx_npei_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 966, 1, 2337},
- {"cvmx_npei_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 967, 1, 2338},
- {"cvmx_npei_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 968, 1, 2339},
- {"cvmx_npei_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969, 1, 2340},
- {"cvmx_npei_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 970, 1, 2341},
- {"cvmx_npei_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 971, 3, 2342},
- {"cvmx_npei_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 972, 3, 2345},
- {"cvmx_npei_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 973, 2, 2348},
- {"cvmx_npei_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 974, 3, 2350},
- {"cvmx_npei_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 975, 3, 2353},
- {"cvmx_npei_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 976, 3, 2356},
- {"cvmx_npei_rsl_int_blocks" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977, 29, 2359},
- {"cvmx_npei_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 978, 1, 2388},
- {"cvmx_npei_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 979, 4, 2389},
- {"cvmx_npei_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 980, 7, 2393},
- {"cvmx_npei_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 981, 5, 2400},
- {"cvmx_npei_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 982, 4, 2405},
- {"cvmx_npei_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 983, 1, 2409},
- {"cvmx_npei_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 984, 4, 2410},
- {"cvmx_npei_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 985, 1, 2414},
- {"cvmx_npei_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 986, 2, 2415},
- {"cvmx_npei_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 987, 2, 2417},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 988, 2, 2419},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 989, 24, 2421},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 990, 4, 2445},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 991, 5, 2449},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 992, 5, 2454},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 993, 2, 2459},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 994, 1, 2461},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 995, 1, 2462},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 996, 5, 2463},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 997, 2, 2468},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 998, 1, 2470},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 999, 1, 2471},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1000, 4, 2472},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1001, 2, 2476},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1002, 2, 2478},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1003, 1, 2480},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1004, 1, 2481},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1005, 2, 2482},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1006, 3, 2484},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1007, 2, 2487},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1008, 2, 2489},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1009, 4, 2491},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1010, 10, 2495},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1011, 12, 2505},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1012, 7, 2517},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1013, 2, 2524},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1014, 1, 2526},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1015, 2, 2527},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1016, 7, 2529},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1017, 11, 2536},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1018, 19, 2547},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1019, 11, 2566},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1020, 17, 2577},
- {"cvmx_pcieep#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1021, 12, 2594},
- {"cvmx_pcieep#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1022, 22, 2606},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1023, 3, 2628},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1024, 3, 2631},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1025, 1, 2634},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1026, 1, 2635},
- {"cvmx_pcieep#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1027, 1, 2636},
- {"cvmx_pcieep#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1028, 1, 2637},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1029, 3, 2638},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1030, 14, 2641},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1031, 14, 2655},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1032, 14, 2669},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1033, 9, 2683},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1034, 9, 2692},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1035, 6, 2701},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1036, 1, 2707},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1037, 1, 2708},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1038, 1, 2709},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1039, 1, 2710},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1040, 2, 2711},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1041, 1, 2713},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1042, 6, 2714},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1043, 6, 2720},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1044, 13, 2726},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1045, 5, 2739},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1046, 8, 2744},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1047, 19, 2752},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1048, 3, 2771},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1049, 1, 2774},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1050, 1, 2775},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1051, 3, 2776},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1052, 3, 2779},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1053, 3, 2782},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1054, 4, 2785},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1055, 4, 2789},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1056, 4, 2793},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1057, 7, 2797},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1058, 5, 2804},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1059, 5, 2809},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1060, 4, 2814},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1061, 4, 2818},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1062, 4, 2822},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1063, 1, 2826},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1064, 1, 2827},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1065, 2, 2828},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1067, 24, 2830},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1069, 4, 2854},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1071, 5, 2858},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1073, 1, 2863},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1075, 1, 2864},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1077, 4, 2865},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1079, 17, 2869},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1081, 4, 2886},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1083, 6, 2890},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1085, 1, 2896},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1087, 1, 2897},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1089, 2, 2898},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1091, 2, 2900},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1093, 1, 2902},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1095, 15, 2903},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1097, 10, 2918},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1099, 12, 2928},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1101, 7, 2940},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1103, 2, 2947},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1105, 1, 2949},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1107, 2, 2950},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1109, 7, 2952},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1111, 11, 2959},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1113, 19, 2970},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1115, 11, 2989},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1117, 20, 3000},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1119, 12, 3020},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1121, 22, 3032},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1123, 8, 3054},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1125, 4, 3062},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1127, 3, 3066},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1129, 3, 3069},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1131, 1, 3072},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1133, 1, 3073},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1135, 1, 3074},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1137, 1, 3075},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1139, 3, 3076},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1141, 14, 3079},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1143, 14, 3093},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1145, 14, 3107},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1147, 9, 3121},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1149, 9, 3130},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1151, 6, 3139},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1153, 1, 3145},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1155, 1, 3146},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1157, 1, 3147},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1159, 1, 3148},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1161, 4, 3149},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1163, 9, 3153},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1165, 2, 3162},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1167, 2, 3164},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1169, 1, 3166},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1171, 6, 3167},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1173, 6, 3173},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1175, 13, 3179},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1177, 5, 3192},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1179, 8, 3197},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1181, 19, 3205},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1183, 3, 3224},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1185, 1, 3227},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1187, 1, 3228},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1189, 3, 3229},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1191, 3, 3232},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1193, 3, 3235},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1195, 4, 3238},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1197, 4, 3242},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1199, 4, 3246},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1201, 7, 3250},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1203, 5, 3257},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1205, 5, 3262},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1207, 4, 3267},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1209, 4, 3271},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1211, 4, 3275},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1213, 1, 3279},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1215, 1, 3280},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1217, 9, 3281},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1221, 6, 3290},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1225, 9, 3296},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1229, 6, 3305},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1233, 13, 3311},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1237, 13, 3324},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1241, 2, 3337},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1245, 4, 3339},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1249, 8, 3343},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1253, 13, 3351},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1257, 17, 3364},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1261, 7, 3381},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1265, 3, 3388},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1269, 8, 3391},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1273, 7, 3399},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1277, 4, 3406},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1281, 5, 3410},
- {"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1285, 8, 3415},
- {"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1286, 2, 3423},
- {"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1287, 5, 3425},
- {"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1288, 10, 3430},
- {"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1289, 2, 3440},
- {"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1290, 7, 3442},
- {"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1291, 7, 3449},
- {"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1292, 6, 3456},
- {"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1293, 5, 3462},
- {"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1294, 5, 3467},
- {"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1295, 3, 3472},
- {"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1296, 6, 3475},
- {"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1297, 9, 3481},
- {"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1298, 3, 3490},
- {"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1299, 9, 3493},
- {"cvmx_pesc#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1300, 13, 3502},
- {"cvmx_pesc#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1302, 15, 3515},
- {"cvmx_pesc#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 1304, 2, 3530},
- {"cvmx_pesc#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 1306, 2, 3532},
- {"cvmx_pesc#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 1308, 2, 3534},
- {"cvmx_pesc#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1310, 16, 3536},
- {"cvmx_pesc#_ctl_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1312, 2, 3552},
- {"cvmx_pesc#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 1314, 32, 3554},
- {"cvmx_pesc#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1316, 32, 3586},
- {"cvmx_pesc#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1318, 5, 3618},
- {"cvmx_pesc#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1320, 2, 3623},
- {"cvmx_pesc#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1322, 2, 3625},
- {"cvmx_pesc#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1324, 2, 3627},
- {"cvmx_pesc#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 1326, 2, 3629},
- {"cvmx_pesc#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 2, 3631},
- {"cvmx_pesc#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 1342, 8, 3633},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1344, 2, 3641},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1345, 4, 3643},
- {"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 1349, 16, 3647},
- {"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 1350, 16, 3663},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 1351, 3, 3679},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1353, 8, 3682},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1354, 22, 3690},
- {"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1355, 6, 3712},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1356, 14, 3718},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1357, 14, 3732},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1358, 2, 3746},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1359, 28, 3748},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1367, 25, 3776},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1375, 2, 3801},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1439, 4, 3803},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1447, 9, 3807},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1455, 2, 3816},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1456, 2, 3818},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1457, 2, 3820},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1465, 2, 3822},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1473, 2, 3824},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1481, 2, 3826},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1489, 2, 3828},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1497, 2, 3830},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1505, 2, 3832},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1513, 2, 3834},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1521, 2, 3836},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1529, 2, 3838},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1537, 2, 3840},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1538, 2, 3842},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1546, 2, 3844},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 1554, 2, 3846},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1562, 2, 3848},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1626, 2, 3850},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 1627, 3, 3852},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 1628, 3, 3855},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 1629, 2, 3858},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 1630, 2, 3860},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1631, 4, 3862},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1632, 5, 3866},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 1633, 4, 3871},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 1634, 8, 3875},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 1635, 4, 3883},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 1636, 5, 3887},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 1637, 1, 3892},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1638, 5, 3893},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1639, 1, 3898},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 1640, 13, 3899},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 1641, 4, 3912},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 1642, 13, 3916},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 1643, 6, 3929},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 1644, 9, 3935},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 1645, 4, 3944},
- {"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 1646, 7, 3948},
- {"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1647, 5, 3955},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 1648, 5, 3960},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 1649, 4, 3965},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 1650, 9, 3969},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1651, 5, 3978},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1652, 16, 3983},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1653, 4, 3999},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1654, 1, 4003},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1655, 1, 4004},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1656, 1, 4005},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1657, 1, 4006},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 1658, 11, 4007},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 1659, 2, 4018},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1660, 4, 4020},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1661, 5, 4024},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1662, 3, 4029},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1663, 4, 4032},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1664, 2, 4036},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 1665, 3, 4038},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1666, 3, 4041},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 1667, 12, 4044},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1668, 2, 4056},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 1669, 13, 4058},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1670, 3, 4071},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1671, 2, 4074},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1679, 2, 4076},
- {"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1680, 2, 4078},
- {"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 1681, 2, 4080},
- {"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1682, 2, 4082},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1690, 2, 4084},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 1691, 2, 4086},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 1692, 2, 4088},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 1693, 10, 4090},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 1697, 5, 4100},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1705, 10, 4105},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1713, 2, 4115},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1714, 2, 4117},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1715, 2, 4119},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1723, 3, 4121},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1724, 6, 4124},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1740, 5, 4130},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1741, 7, 4135},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1757, 2, 4142},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1773, 1, 4144},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1774, 1, 4145},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1775, 1, 4146},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1776, 5, 4147},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1777, 5, 4152},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1778, 4, 4157},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1779, 10, 4161},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1780, 1, 4171},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 1781, 3, 4172},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 1782, 7, 4175},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 1783, 2, 4182},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1784, 1, 4184},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1785, 1, 4185},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 1786, 1, 4186},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 1787, 18, 4187},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 1788, 3, 4205},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 1789, 2, 4208},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 1790, 3, 4210},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 1791, 7, 4213},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1792, 2, 4220},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1793, 2, 4222},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 1794, 2, 4224},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1795, 3, 4226},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1796, 3, 4229},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1797, 7, 4232},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 1798, 10, 4239},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1800, 6, 4249},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1802, 2, 4255},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1804, 4, 4257},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1806, 4, 4261},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1808, 6, 4265},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1809, 3, 4271},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1810, 5, 4274},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 1811, 4, 4279},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 1812, 6, 4283},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1813, 4, 4289},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1814, 2, 4293},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1815, 4, 4295},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1816, 2, 4299},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1817, 3, 4301},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1818, 4, 4304},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1819, 12, 4308},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 1820, 3, 4320},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 1821, 5, 4323},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1822, 2, 4328},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1823, 2, 4330},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1824, 18, 4332},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1825, 12, 4350},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1826, 6, 4362},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1827, 5, 4368},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1828, 1, 4373},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1829, 2, 4374},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1830, 2, 4376},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1831, 18, 4378},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1832, 12, 4396},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1833, 6, 4408},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1834, 2, 4414},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1835, 2, 4416},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1836, 18, 4418},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1837, 12, 4436},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1838, 6, 4448},
- {"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 1839, 2, 4454},
- {"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1841, 2, 4456},
- {"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1843, 8, 4458},
- {"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1845, 11, 4466},
- {"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1847, 15, 4477},
- {"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1857, 8, 4492},
- {"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1867, 8, 4500},
- {"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1869, 4, 4508},
- {"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1879, 15, 4512},
- {"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1889, 6, 4527},
- {"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1899, 6, 4533},
- {"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1901, 4, 4539},
- {"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1911, 2, 4543},
- {"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1919, 6, 4545},
- {"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 1921, 4, 4551},
- {"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 1923, 1, 4555},
- {"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 1925, 1, 4556},
- {"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 1927, 1, 4557},
- {"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1929, 7, 4558},
- {"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 1931, 1, 4565},
- {"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 1933, 14, 4566},
- {"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 1935, 10, 4580},
- {"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 1937, 14, 4590},
- {"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1939, 32, 4604},
- {"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1941, 32, 4636},
- {"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1943, 2, 4668},
- {"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1945, 4, 4670},
- {"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1947, 13, 4674},
- {"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 1949, 10, 4687},
- {"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1951, 10, 4697},
- {"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1953, 2, 4707},
- {"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 1955, 6, 4709},
- {"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 1957, 5, 4715},
- {"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 1959, 6, 4720},
- {"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 1961, 5, 4726},
- {"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 1963, 1, 4731},
- {"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1965, 13, 4732},
- {"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 1967, 2, 4745},
- {"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1969, 2, 4747},
- {"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 1971, 11, 4749},
- {"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1987, 3, 4760},
- {"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1989, 12, 4763},
- {"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 2005, 12, 4775},
- {"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 2021, 6, 4787},
- {"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2037, 4, 4793},
- {"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 2053, 2, 4797},
- {"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 2055, 2, 4799},
- {"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 2057, 15, 4801},
- {"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2059, 2, 4816},
- {"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2061, 3, 4818},
- {"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 2063, 1, 4821},
- {"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2079, 6, 4822},
- {"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2081, 8, 4828},
- {"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2083, 15, 4836},
- {"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 2085, 6, 4851},
- {"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2087, 2, 4857},
- {"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2089, 2, 4859},
- {"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2091, 2, 4861},
- {"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2093, 2, 4863},
- {"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2095, 2, 4865},
- {"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2097, 2, 4867},
- {"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2099, 2, 4869},
- {"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2101, 2, 4871},
- {"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2103, 2, 4873},
- {"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2105, 2, 4875},
- {"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2107, 2, 4877},
- {"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2109, 2, 4879},
- {"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2111, 2, 4881},
- {"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2113, 2, 4883},
- {"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2115, 2, 4885},
- {"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2117, 2, 4887},
- {"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 2119, 7, 4889},
- {"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 2121, 34, 4896},
- {"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 2123, 34, 4930},
- {"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2125, 35, 4964},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"AGL_GMX_BAD_REG" , 0x11800e0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"AGL_GMX_BIST" , 0x11800e0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"AGL_GMX_DRV_CTL" , 0x11800e00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_INF_MODE" , 0x11800e00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_PRT0_CFG" , 0x11800e0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_PRT1_CFG" , 0x11800e0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX0_ADR_CAM0" , 0x11800e0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX1_ADR_CAM0" , 0x11800e0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX0_ADR_CAM1" , 0x11800e0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX1_ADR_CAM1" , 0x11800e0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX0_ADR_CAM2" , 0x11800e0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX1_ADR_CAM2" , 0x11800e0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX0_ADR_CAM3" , 0x11800e0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX1_ADR_CAM3" , 0x11800e0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX0_ADR_CAM4" , 0x11800e00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX1_ADR_CAM4" , 0x11800e00009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX0_ADR_CAM5" , 0x11800e00001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX1_ADR_CAM5" , 0x11800e00009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800e0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX1_ADR_CAM_EN" , 0x11800e0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX0_ADR_CTL" , 0x11800e0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX1_ADR_CTL" , 0x11800e0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX0_DECISION" , 0x11800e0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX1_DECISION" , 0x11800e0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX0_FRM_CHK" , 0x11800e0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX1_FRM_CHK" , 0x11800e0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX0_FRM_CTL" , 0x11800e0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX1_FRM_CTL" , 0x11800e0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX0_FRM_MAX" , 0x11800e0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX1_FRM_MAX" , 0x11800e0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX0_FRM_MIN" , 0x11800e0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX1_FRM_MIN" , 0x11800e0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX0_IFG" , 0x11800e0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX1_IFG" , 0x11800e0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX0_INT_EN" , 0x11800e0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX1_INT_EN" , 0x11800e0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX0_INT_REG" , 0x11800e0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX1_INT_REG" , 0x11800e0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX0_JABBER" , 0x11800e0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX1_JABBER" , 0x11800e0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800e0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX1_PAUSE_DROP_TIME" , 0x11800e0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX0_STATS_CTL" , 0x11800e0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX1_STATS_CTL" , 0x11800e0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX0_STATS_OCTS" , 0x11800e0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX1_STATS_OCTS" , 0x11800e0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800e0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX1_STATS_OCTS_CTL" , 0x11800e0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800e00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX1_STATS_OCTS_DMAC" , 0x11800e00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800e00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX1_STATS_OCTS_DRP" , 0x11800e00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX0_STATS_PKTS" , 0x11800e0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX1_STATS_PKTS" , 0x11800e0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800e00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX1_STATS_PKTS_BAD" , 0x11800e00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800e0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX1_STATS_PKTS_CTL" , 0x11800e0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800e00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX1_STATS_PKTS_DMAC" , 0x11800e00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800e00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX1_STATS_PKTS_DRP" , 0x11800e00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX0_UDD_SKP" , 0x11800e0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX1_UDD_SKP" , 0x11800e0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_DROP0" , 0x11800e0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_DROP1" , 0x11800e0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_OFF0" , 0x11800e0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_BP_OFF1" , 0x11800e0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_BP_ON0" , 0x11800e0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_BP_ON1" , 0x11800e0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_PRT_INFO" , 0x11800e00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"AGL_GMX_RX_TX_STATUS" , 0x11800e00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_SMAC0" , 0x11800e0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_SMAC1" , 0x11800e0000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_STAT_BP" , 0x11800e0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX0_APPEND" , 0x11800e0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX1_APPEND" , 0x11800e0000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX0_CTL" , 0x11800e0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX1_CTL" , 0x11800e0000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX0_MIN_PKT" , 0x11800e0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX1_MIN_PKT" , 0x11800e0000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800e0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX1_PAUSE_PKT_INTERVAL", 0x11800e0000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800e0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX1_PAUSE_PKT_TIME" , 0x11800e0000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800e0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX1_PAUSE_TOGO" , 0x11800e0000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800e0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX1_PAUSE_ZERO" , 0x11800e0000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800e0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX1_SOFT_PAUSE" , 0x11800e0000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX0_STAT0" , 0x11800e0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX1_STAT0" , 0x11800e0000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX0_STAT1" , 0x11800e0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX1_STAT1" , 0x11800e0000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX0_STAT2" , 0x11800e0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX1_STAT2" , 0x11800e0000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX0_STAT3" , 0x11800e0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX1_STAT3" , 0x11800e0000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX0_STAT4" , 0x11800e00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX1_STAT4" , 0x11800e0000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX0_STAT5" , 0x11800e00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX1_STAT5" , 0x11800e0000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX0_STAT6" , 0x11800e00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX1_STAT6" , 0x11800e0000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX0_STAT7" , 0x11800e00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX1_STAT7" , 0x11800e0000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX0_STAT8" , 0x11800e00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX1_STAT8" , 0x11800e0000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX0_STAT9" , 0x11800e00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX1_STAT9" , 0x11800e0000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX0_STATS_CTL" , 0x11800e0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX1_STATS_CTL" , 0x11800e0000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX0_THRESH" , 0x11800e0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX1_THRESH" , 0x11800e0000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX_BP" , 0x11800e00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"AGL_GMX_TX_COL_ATTEMPT" , 0x11800e0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"AGL_GMX_TX_IFG" , 0x11800e0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"AGL_GMX_TX_INT_EN" , 0x11800e0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"AGL_GMX_TX_INT_REG" , 0x11800e0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"AGL_GMX_TX_JAM" , 0x11800e0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"AGL_GMX_TX_LFSR" , 0x11800e00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"AGL_GMX_TX_OVR_BP" , 0x11800e00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800e00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800e00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 71},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_QLM_DCOK" , 0x1070000000760ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_TX003_SGMII_CTL" , 0x1180008001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 225},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 226},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 227},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 228},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 229},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 230},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_PORT36_BP_PAGE_CNT2" , 0x14f0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"IPD_PORT37_BP_PAGE_CNT2" , 0x14f0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"IPD_PORT38_BP_PAGE_CNT2" , 0x14f0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"IPD_PORT39_BP_PAGE_CNT2" , 0x14f0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14f0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14f0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14f0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14f00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"IPD_RED_PORT_ENABLE2" , 0x14f00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"L2C_GRPWRR0" , 0x11800800000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"L2C_GRPWRR1" , 0x11800800000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"L2C_INT_EN" , 0x1180080000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"L2C_INT_STAT" , 0x11800800000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"L2C_OOB" , 0x11800800000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"L2C_OOB1" , 0x11800800000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"L2C_OOB2" , 0x11800800000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"L2C_OOB3" , 0x11800800000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"L2C_PPGRP" , 0x11800800000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"LMC0_BIST_CTL" , 0x11800880000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"LMC0_BIST_RESULT" , 0x11800880000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"LMC0_DLL_CTL" , 0x11800880000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"LMC0_PLL_CTL" , 0x11800880000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"LMC0_PLL_STATUS" , 0x11800880000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"LMC0_READ_LEVEL_CTL" , 0x1180088000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"LMC0_READ_LEVEL_DBG" , 0x1180088000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"LMC0_READ_LEVEL_RANK000" , 0x1180088000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"LMC0_READ_LEVEL_RANK001" , 0x1180088000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"LMC0_READ_LEVEL_RANK002" , 0x1180088000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"LMC0_READ_LEVEL_RANK003" , 0x1180088000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"LMC0_RODT_COMP_CTL" , 0x11800880000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"MIO_UART2_DLH" , 0x1180000000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"MIO_UART2_DLL" , 0x1180000000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"MIO_UART2_FAR" , 0x1180000000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"MIO_UART2_FCR" , 0x1180000000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"MIO_UART2_HTX" , 0x1180000000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"MIO_UART2_IER" , 0x1180000000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"MIO_UART2_IIR" , 0x1180000000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"MIO_UART2_LCR" , 0x1180000000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"MIO_UART2_LSR" , 0x1180000000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"MIO_UART2_MCR" , 0x1180000000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"MIO_UART2_MSR" , 0x1180000000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"MIO_UART2_RBR" , 0x1180000000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"MIO_UART2_RFL" , 0x1180000000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"MIO_UART2_RFW" , 0x1180000000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"MIO_UART2_SBCR" , 0x1180000000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"MIO_UART2_SCR" , 0x1180000000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"MIO_UART2_SFE" , 0x1180000000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"MIO_UART2_SRR" , 0x1180000000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"MIO_UART2_SRT" , 0x1180000000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"MIO_UART2_SRTS" , 0x1180000000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"MIO_UART2_STT" , 0x1180000000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"MIO_UART2_TFL" , 0x1180000000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"MIO_UART2_TFR" , 0x1180000000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"MIO_UART2_THR" , 0x1180000000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"MIO_UART2_USR" , 0x1180000000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"MIX1_BIST" , 0x1070000100878ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
- {"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"MIX1_CTL" , 0x1070000100820ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
- {"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"MIX1_INTENA" , 0x1070000100850ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"MIX1_IRCNT" , 0x1070000100830ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"MIX1_IRHWM" , 0x1070000100828ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
- {"MIX1_IRING1" , 0x1070000100810ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
- {"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
- {"MIX1_IRING2" , 0x1070000100818ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
- {"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
- {"MIX1_ISR" , 0x1070000100848ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
- {"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
- {"MIX1_ORCNT" , 0x1070000100840ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
- {"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
- {"MIX1_ORHWM" , 0x1070000100838ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
- {"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
- {"MIX1_ORING1" , 0x1070000100800ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
- {"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 411},
- {"MIX1_ORING2" , 0x1070000100808ull, CVMX_CSR_DB_TYPE_NCB, 64, 411},
- {"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 412},
- {"MIX1_REMCNT" , 0x1070000100858ull, CVMX_CSR_DB_TYPE_NCB, 64, 412},
- {"NPEI_BAR1_INDEX0" , 0x11f0000008000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX1" , 0x11f0000008010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX2" , 0x11f0000008020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX3" , 0x11f0000008030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX4" , 0x11f0000008040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX5" , 0x11f0000008050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX6" , 0x11f0000008060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX7" , 0x11f0000008070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX8" , 0x11f0000008080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX9" , 0x11f0000008090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX10" , 0x11f00000080a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX11" , 0x11f00000080b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX12" , 0x11f00000080c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX13" , 0x11f00000080d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX14" , 0x11f00000080e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX15" , 0x11f00000080f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX16" , 0x11f0000008100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX17" , 0x11f0000008110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX18" , 0x11f0000008120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX19" , 0x11f0000008130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX20" , 0x11f0000008140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX21" , 0x11f0000008150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX22" , 0x11f0000008160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX23" , 0x11f0000008170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX24" , 0x11f0000008180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX25" , 0x11f0000008190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX26" , 0x11f00000081a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX27" , 0x11f00000081b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX28" , 0x11f00000081c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX29" , 0x11f00000081d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX30" , 0x11f00000081e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BAR1_INDEX31" , 0x11f00000081f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
- {"NPEI_BIST_STATUS" , 0x11f0000008580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 414},
- {"NPEI_CTL_PORT0" , 0x11f0000008250ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 415},
- {"NPEI_CTL_PORT1" , 0x11f0000008260ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 416},
- {"NPEI_CTL_STATUS" , 0x11f0000008570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
- {"NPEI_CTL_STATUS2" , 0x11f000000bc00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 418},
- {"NPEI_DATA_OUT_CNT" , 0x11f00000085f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
- {"NPEI_DBG_DATA" , 0x11f0000008510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
- {"NPEI_DBG_SELECT" , 0x11f0000008500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 421},
- {"NPEI_DMA0_COUNTS" , 0x11f0000008450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 422},
- {"NPEI_DMA1_COUNTS" , 0x11f0000008460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 422},
- {"NPEI_DMA2_COUNTS" , 0x11f0000008470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 422},
- {"NPEI_DMA3_COUNTS" , 0x11f0000008480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 422},
- {"NPEI_DMA0_DBELL" , 0x11f00000083b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 423},
- {"NPEI_DMA1_DBELL" , 0x11f00000083c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 423},
- {"NPEI_DMA2_DBELL" , 0x11f00000083d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 423},
- {"NPEI_DMA3_DBELL" , 0x11f00000083e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 423},
- {"NPEI_DMA0_IBUFF_SADDR" , 0x11f0000008400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 424},
- {"NPEI_DMA1_IBUFF_SADDR" , 0x11f0000008410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 424},
- {"NPEI_DMA2_IBUFF_SADDR" , 0x11f0000008420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 424},
- {"NPEI_DMA3_IBUFF_SADDR" , 0x11f0000008430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 424},
- {"NPEI_DMA0_NADDR" , 0x11f00000084a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 425},
- {"NPEI_DMA1_NADDR" , 0x11f00000084b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 425},
- {"NPEI_DMA2_NADDR" , 0x11f00000084c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 425},
- {"NPEI_DMA3_NADDR" , 0x11f00000084d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 425},
- {"NPEI_DMA0_INT_LEVEL" , 0x11f00000085c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 426},
- {"NPEI_DMA1_INT_LEVEL" , 0x11f00000085d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 427},
- {"NPEI_DMA_CNTS" , 0x11f00000085e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 428},
- {"NPEI_DMA_CONTROL" , 0x11f00000083a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 429},
- {"NPEI_DMA_STATE1_P1" , 0x11f0000008680ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 430},
- {"NPEI_DMA_STATE2_P1" , 0x11f0000008690ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 431},
- {"NPEI_DMA_STATE3_P1" , 0x11f00000086a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 432},
- {"NPEI_DMA_STATE4_P1" , 0x11f00000086b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 433},
- {"NPEI_INT_A_ENB" , 0x11f0000008560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 434},
- {"NPEI_INT_A_ENB2" , 0x11f000000bce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
- {"NPEI_INT_A_SUM" , 0x11f0000008550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 436},
- {"NPEI_INT_ENB" , 0x11f0000008540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
- {"NPEI_INT_ENB2" , 0x11f000000bcd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
- {"NPEI_INT_SUM" , 0x11f0000008530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 439},
- {"NPEI_INT_SUM2" , 0x11f000000bcc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 440},
- {"NPEI_LAST_WIN_RDATA0" , 0x11f0000008600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 441},
- {"NPEI_LAST_WIN_RDATA1" , 0x11f0000008610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 442},
- {"NPEI_MEM_ACCESS_CTL" , 0x11f00000084f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 443},
- {"NPEI_MEM_ACCESS_SUBID12" , 0x11f0000008280ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID13" , 0x11f0000008290ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID14" , 0x11f00000082a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID15" , 0x11f00000082b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID16" , 0x11f00000082c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID17" , 0x11f00000082d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID18" , 0x11f00000082e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID19" , 0x11f00000082f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID20" , 0x11f0000008300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID21" , 0x11f0000008310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID22" , 0x11f0000008320ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID23" , 0x11f0000008330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID24" , 0x11f0000008340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID25" , 0x11f0000008350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID26" , 0x11f0000008360ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MEM_ACCESS_SUBID27" , 0x11f0000008370ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_MSI_ENB0" , 0x11f000000bc50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 445},
- {"NPEI_MSI_ENB1" , 0x11f000000bc60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 446},
- {"NPEI_MSI_ENB2" , 0x11f000000bc70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 447},
- {"NPEI_MSI_ENB3" , 0x11f000000bc80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
- {"NPEI_MSI_RCV0" , 0x11f000000bc10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 449},
- {"NPEI_MSI_RCV1" , 0x11f000000bc20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
- {"NPEI_MSI_RCV2" , 0x11f000000bc30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
- {"NPEI_MSI_RCV3" , 0x11f000000bc40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 452},
- {"NPEI_MSI_RD_MAP" , 0x11f000000bca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 453},
- {"NPEI_MSI_WR_MAP" , 0x11f000000bc90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 454},
- {"NPEI_PCIE_MSI_RCV" , 0x11f000000bcb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_PCIE_MSI_RCV_B1" , 0x11f0000008650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 456},
- {"NPEI_PCIE_MSI_RCV_B2" , 0x11f0000008660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 457},
- {"NPEI_PCIE_MSI_RCV_B3" , 0x11f0000008670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 458},
- {"NPEI_RSL_INT_BLOCKS" , 0x11f0000008520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 459},
- {"NPEI_SCRATCH_1" , 0x11f0000008270ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 460},
- {"NPEI_STATE1" , 0x11f0000008620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 461},
- {"NPEI_STATE2" , 0x11f0000008630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 462},
- {"NPEI_STATE3" , 0x11f0000008640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 463},
- {"NPEI_WIN_RD_ADDR" , 0x210ull, CVMX_CSR_DB_TYPE_PEXP, 64, 464},
- {"NPEI_WIN_RD_DATA" , 0x240ull, CVMX_CSR_DB_TYPE_PEXP, 64, 465},
- {"NPEI_WIN_WR_ADDR" , 0x200ull, CVMX_CSR_DB_TYPE_PEXP, 64, 466},
- {"NPEI_WIN_WR_DATA" , 0x220ull, CVMX_CSR_DB_TYPE_PEXP, 64, 467},
- {"NPEI_WIN_WR_MASK" , 0x230ull, CVMX_CSR_DB_TYPE_PEXP, 64, 468},
- {"NPEI_WINDOW_CTL" , 0x11f0000008380ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 469},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 470},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 471},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 472},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 473},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 474},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 475},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 476},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 477},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 478},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 479},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 480},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 481},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 482},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 483},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 484},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 485},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 486},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 487},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 488},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 489},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 490},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 491},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 492},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 493},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 494},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 495},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 496},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 497},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 498},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 499},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 500},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 501},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 502},
- {"PCIEEP0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 503},
- {"PCIEEP0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 504},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 505},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 506},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 507},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 508},
- {"PCIEEP0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 509},
- {"PCIEEP0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 510},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 511},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 512},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 513},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 514},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 515},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 516},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 517},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 518},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 519},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 520},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 521},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 522},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 523},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 524},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 525},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 526},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 527},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 528},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 529},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 530},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 531},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 532},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 533},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 534},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 535},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 536},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 537},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 538},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 539},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 540},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 541},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 542},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 543},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 544},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 545},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 546},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 547},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 547},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 548},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 548},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 549},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 549},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 550},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 550},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 551},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 551},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 552},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 552},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 553},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 553},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 554},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 554},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 555},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 555},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 556},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 556},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 557},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 557},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 558},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 558},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 559},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 559},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 560},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 560},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 561},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 561},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 562},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 562},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 563},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 563},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 564},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 564},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 565},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 565},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 566},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 566},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 567},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 567},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 568},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 568},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 569},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 569},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 570},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 570},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 571},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 571},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 572},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 572},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 573},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 573},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 574},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 574},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 575},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 575},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 576},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 576},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 577},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 577},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 578},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 578},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 579},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 579},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 580},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 580},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 581},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 581},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 582},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 582},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 583},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 583},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 584},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 584},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 585},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 585},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 586},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 586},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 587},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 587},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 588},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 588},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 589},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 589},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 590},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 590},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 591},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 591},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 592},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 592},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 593},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 593},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 594},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 594},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 595},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 595},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 596},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 596},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 597},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 597},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 598},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 598},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 599},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 599},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 600},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 600},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 601},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 601},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 602},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 602},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 616},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 616},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 617},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 617},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS0_AN002_ADV_REG" , 0x11800b0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS0_AN003_ADV_REG" , 0x11800b0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS0_AN002_EXT_ST_REG" , 0x11800b0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS0_AN003_EXT_ST_REG" , 0x11800b0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS0_AN002_LP_ABIL_REG" , 0x11800b0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS0_AN003_LP_ABIL_REG" , 0x11800b0001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS0_AN002_RESULTS_REG" , 0x11800b0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS0_AN003_RESULTS_REG" , 0x11800b0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS0_INT002_EN_REG" , 0x11800b0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS0_INT003_EN_REG" , 0x11800b0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS0_INT002_REG" , 0x11800b0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS0_INT003_REG" , 0x11800b0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS0_LINK002_TIMER_COUNT_REG", 0x11800b0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS0_LINK003_TIMER_COUNT_REG", 0x11800b0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS0_LOG_ANL002_REG" , 0x11800b0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS0_LOG_ANL003_REG" , 0x11800b0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS0_MISC002_CTL_REG" , 0x11800b0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS0_MISC003_CTL_REG" , 0x11800b0001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS0_MR002_CONTROL_REG" , 0x11800b0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS0_MR003_CONTROL_REG" , 0x11800b0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"PCS0_MR002_STATUS_REG" , 0x11800b0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"PCS0_MR003_STATUS_REG" , 0x11800b0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"PCS0_RX002_STATES_REG" , 0x11800b0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"PCS0_RX003_STATES_REG" , 0x11800b0001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"PCS0_RX002_SYNC_REG" , 0x11800b0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"PCS0_RX003_SYNC_REG" , 0x11800b0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"PCS0_SGM002_AN_ADV_REG" , 0x11800b0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"PCS0_SGM003_AN_ADV_REG" , 0x11800b0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
- {"PCS0_SGM002_LP_ADV_REG" , 0x11800b0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
- {"PCS0_SGM003_LP_ADV_REG" , 0x11800b0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"PCS0_TX002_STATES_REG" , 0x11800b0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"PCS0_TX003_STATES_REG" , 0x11800b0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
- {"PCS0_TX_RX002_POLARITY_REG" , 0x11800b0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
- {"PCS0_TX_RX003_POLARITY_REG" , 0x11800b0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
- {"PCSX0_10GBX_STATUS_REG" , 0x11800b0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"PCSX0_BIST_STATUS_REG" , 0x11800b0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800b0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"PCSX0_CONTROL1_REG" , 0x11800b0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
- {"PCSX0_CONTROL2_REG" , 0x11800b0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"PCSX0_INT_EN_REG" , 0x11800b0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"PCSX0_INT_REG" , 0x11800b0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"PCSX0_LOG_ANL_REG" , 0x11800b0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"PCSX0_MISC_CTL_REG" , 0x11800b0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
- {"PCSX0_RX_SYNC_STATES_REG" , 0x11800b0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"PCSX0_SPD_ABIL_REG" , 0x11800b0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"PCSX0_STATUS1_REG" , 0x11800b0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"PCSX0_STATUS2_REG" , 0x11800b0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"PCSX0_TX_RX_POLARITY_REG" , 0x11800b0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"PCSX0_TX_RX_STATES_REG" , 0x11800b0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"PESC0_BIST_STATUS" , 0x11800c8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"PESC1_BIST_STATUS" , 0x11800d0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"PESC0_BIST_STATUS2" , 0x11800c8000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"PESC1_BIST_STATUS2" , 0x11800d0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"PESC0_CFG_RD" , 0x11800c8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"PESC1_CFG_RD" , 0x11800d0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"PESC0_CFG_WR" , 0x11800c8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"PESC1_CFG_WR" , 0x11800d0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"PESC0_CPL_LUT_VALID" , 0x11800c8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"PESC1_CPL_LUT_VALID" , 0x11800d0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"PESC0_CTL_STATUS" , 0x11800c8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"PESC1_CTL_STATUS" , 0x11800d0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"PESC0_CTL_STATUS2" , 0x11800c8000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"PESC1_CTL_STATUS2" , 0x11800d0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"PESC0_DBG_INFO" , 0x11800c8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"PESC1_DBG_INFO" , 0x11800d0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"PESC0_DBG_INFO_EN" , 0x11800c80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"PESC1_DBG_INFO_EN" , 0x11800d00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"PESC0_DIAG_STATUS" , 0x11800c8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"PESC1_DIAG_STATUS" , 0x11800d0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"PESC0_P2N_BAR0_START" , 0x11800c8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"PESC1_P2N_BAR0_START" , 0x11800d0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"PESC0_P2N_BAR1_START" , 0x11800c8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"PESC1_P2N_BAR1_START" , 0x11800d0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"PESC0_P2N_BAR2_START" , 0x11800c8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"PESC1_P2N_BAR2_START" , 0x11800d0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"PESC0_P2P_BAR000_END" , 0x11800c8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"PESC0_P2P_BAR001_END" , 0x11800c8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"PESC0_P2P_BAR002_END" , 0x11800c8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"PESC0_P2P_BAR003_END" , 0x11800c8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"PESC1_P2P_BAR000_END" , 0x11800d0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"PESC1_P2P_BAR001_END" , 0x11800d0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"PESC1_P2P_BAR002_END" , 0x11800d0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"PESC1_P2P_BAR003_END" , 0x11800d0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"PESC0_P2P_BAR000_START" , 0x11800c8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"PESC0_P2P_BAR001_START" , 0x11800c8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"PESC0_P2P_BAR002_START" , 0x11800c8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"PESC0_P2P_BAR003_START" , 0x11800c8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"PESC1_P2P_BAR000_START" , 0x11800d0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"PESC1_P2P_BAR001_START" , 0x11800d0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"PESC1_P2P_BAR002_START" , 0x11800d0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"PESC1_P2P_BAR003_START" , 0x11800d0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"PESC0_TLP_CREDITS" , 0x11800c8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"PESC1_TLP_CREDITS" , 0x11800d0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"PIP_DSA_SRC_GRP" , 0x11800a0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"PIP_DSA_VID_GRP" , 0x11800a0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_FRM_LEN_CHK1" , 0x11800a0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"PIP_HG_PRI_QOS" , 0x11800a00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT0_PRT36" , 0x11800a0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT0_PRT37" , 0x11800a0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT0_PRT38" , 0x11800a00013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT0_PRT39" , 0x11800a0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PIP_STAT1_PRT36" , 0x11800a0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PIP_STAT1_PRT37" , 0x11800a0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PIP_STAT1_PRT38" , 0x11800a00013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PIP_STAT1_PRT39" , 0x11800a0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT2_PRT36" , 0x11800a0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT2_PRT37" , 0x11800a00013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT2_PRT38" , 0x11800a00013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT2_PRT39" , 0x11800a0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT3_PRT36" , 0x11800a0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT3_PRT37" , 0x11800a00013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT3_PRT38" , 0x11800a00013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT3_PRT39" , 0x11800a0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT4_PRT36" , 0x11800a0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT4_PRT37" , 0x11800a00013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT4_PRT38" , 0x11800a0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT4_PRT39" , 0x11800a0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_STAT5_PRT36" , 0x11800a0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_STAT5_PRT37" , 0x11800a00013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_STAT5_PRT38" , 0x11800a0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_STAT5_PRT39" , 0x11800a0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PIP_STAT6_PRT36" , 0x11800a0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PIP_STAT6_PRT37" , 0x11800a00013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PIP_STAT6_PRT38" , 0x11800a0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PIP_STAT6_PRT39" , 0x11800a0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PIP_STAT7_PRT36" , 0x11800a0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PIP_STAT7_PRT37" , 0x11800a00013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PIP_STAT7_PRT38" , 0x11800a0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PIP_STAT7_PRT39" , 0x11800a0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PIP_STAT8_PRT36" , 0x11800a0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PIP_STAT8_PRT37" , 0x11800a00013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PIP_STAT8_PRT38" , 0x11800a0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PIP_STAT8_PRT39" , 0x11800a0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PIP_STAT9_PRT36" , 0x11800a0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PIP_STAT9_PRT37" , 0x11800a00013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PIP_STAT9_PRT38" , 0x11800a0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PIP_STAT9_PRT39" , 0x11800a0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PIP_STAT_INB_ERRS36" , 0x11800a0001e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PIP_STAT_INB_ERRS37" , 0x11800a0001eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PIP_STAT_INB_ERRS38" , 0x11800a0001ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PIP_STAT_INB_ERRS39" , 0x11800a0001ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PIP_STAT_INB_OCTS36" , 0x11800a0001e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PIP_STAT_INB_OCTS37" , 0x11800a0001ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PIP_STAT_INB_OCTS38" , 0x11800a0001ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PIP_STAT_INB_OCTS39" , 0x11800a0001ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PIP_STAT_INB_PKTS36" , 0x11800a0001e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PIP_STAT_INB_PKTS37" , 0x11800a0001ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PIP_STAT_INB_PKTS38" , 0x11800a0001ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PIP_STAT_INB_PKTS39" , 0x11800a0001ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
- {"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 745},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 746},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 747},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 751},
- {"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 752},
- {"POW_IQ_THR0" , 0x16700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_IQ_THR1" , 0x16700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_IQ_THR2" , 0x16700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_IQ_THR3" , 0x16700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_IQ_THR4" , 0x16700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_IQ_THR5" , 0x16700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_IQ_THR6" , 0x16700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_IQ_THR7" , 0x16700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 754},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 756},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 760},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 761},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 763},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 765},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 812},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 813},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 817},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 819},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 820},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 821},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 822},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 823},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"USBC0_DAINT" , 0x16f0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
- {"USBC1_DAINT" , 0x17f0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
- {"USBC0_DAINTMSK" , 0x16f001000081cull, CVMX_CSR_DB_TYPE_NCB, 32, 830},
- {"USBC1_DAINTMSK" , 0x17f001000081cull, CVMX_CSR_DB_TYPE_NCB, 32, 830},
- {"USBC0_DCFG" , 0x16f0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
- {"USBC1_DCFG" , 0x17f0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
- {"USBC0_DCTL" , 0x16f0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
- {"USBC1_DCTL" , 0x17f0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
- {"USBC0_DIEPCTL000" , 0x16f0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC0_DIEPCTL001" , 0x16f0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC0_DIEPCTL002" , 0x16f0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC0_DIEPCTL003" , 0x16f0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC0_DIEPCTL004" , 0x16f0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC1_DIEPCTL000" , 0x17f0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC1_DIEPCTL001" , 0x17f0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC1_DIEPCTL002" , 0x17f0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC1_DIEPCTL003" , 0x17f0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC1_DIEPCTL004" , 0x17f0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
- {"USBC0_DIEPINT000" , 0x16f0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC0_DIEPINT001" , 0x16f0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC0_DIEPINT002" , 0x16f0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC0_DIEPINT003" , 0x16f0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC0_DIEPINT004" , 0x16f0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC1_DIEPINT000" , 0x17f0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC1_DIEPINT001" , 0x17f0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC1_DIEPINT002" , 0x17f0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC1_DIEPINT003" , 0x17f0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC1_DIEPINT004" , 0x17f0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
- {"USBC0_DIEPMSK" , 0x16f0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 835},
- {"USBC1_DIEPMSK" , 0x17f0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 835},
- {"USBC0_DIEPTSIZ000" , 0x16f0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC0_DIEPTSIZ001" , 0x16f0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC0_DIEPTSIZ002" , 0x16f0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC0_DIEPTSIZ003" , 0x16f0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC0_DIEPTSIZ004" , 0x16f0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC1_DIEPTSIZ000" , 0x17f0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC1_DIEPTSIZ001" , 0x17f0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC1_DIEPTSIZ002" , 0x17f0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC1_DIEPTSIZ003" , 0x17f0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC1_DIEPTSIZ004" , 0x17f0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
- {"USBC0_DOEPCTL000" , 0x16f0010000b00ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC0_DOEPCTL001" , 0x16f0010000b20ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC0_DOEPCTL002" , 0x16f0010000b40ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC0_DOEPCTL003" , 0x16f0010000b60ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC0_DOEPCTL004" , 0x16f0010000b80ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC1_DOEPCTL000" , 0x17f0010000b00ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC1_DOEPCTL001" , 0x17f0010000b20ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC1_DOEPCTL002" , 0x17f0010000b40ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC1_DOEPCTL003" , 0x17f0010000b60ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC1_DOEPCTL004" , 0x17f0010000b80ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
- {"USBC0_DOEPINT000" , 0x16f0010000b08ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC0_DOEPINT001" , 0x16f0010000b28ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC0_DOEPINT002" , 0x16f0010000b48ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC0_DOEPINT003" , 0x16f0010000b68ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC0_DOEPINT004" , 0x16f0010000b88ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC1_DOEPINT000" , 0x17f0010000b08ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC1_DOEPINT001" , 0x17f0010000b28ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC1_DOEPINT002" , 0x17f0010000b48ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC1_DOEPINT003" , 0x17f0010000b68ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC1_DOEPINT004" , 0x17f0010000b88ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
- {"USBC0_DOEPMSK" , 0x16f0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 839},
- {"USBC1_DOEPMSK" , 0x17f0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 839},
- {"USBC0_DOEPTSIZ000" , 0x16f0010000b10ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC0_DOEPTSIZ001" , 0x16f0010000b30ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC0_DOEPTSIZ002" , 0x16f0010000b50ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC0_DOEPTSIZ003" , 0x16f0010000b70ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC0_DOEPTSIZ004" , 0x16f0010000b90ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC1_DOEPTSIZ000" , 0x17f0010000b10ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC1_DOEPTSIZ001" , 0x17f0010000b30ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC1_DOEPTSIZ002" , 0x17f0010000b50ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC1_DOEPTSIZ003" , 0x17f0010000b70ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC1_DOEPTSIZ004" , 0x17f0010000b90ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
- {"USBC0_DPTXFSIZ001" , 0x16f0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
- {"USBC0_DPTXFSIZ002" , 0x16f0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
- {"USBC0_DPTXFSIZ003" , 0x16f001000010cull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
- {"USBC0_DPTXFSIZ004" , 0x16f0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
- {"USBC1_DPTXFSIZ001" , 0x17f0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
- {"USBC1_DPTXFSIZ002" , 0x17f0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
- {"USBC1_DPTXFSIZ003" , 0x17f001000010cull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
- {"USBC1_DPTXFSIZ004" , 0x17f0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
- {"USBC0_DSTS" , 0x16f0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 842},
- {"USBC1_DSTS" , 0x17f0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 842},
- {"USBC0_DTKNQR1" , 0x16f0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 843},
- {"USBC1_DTKNQR1" , 0x17f0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 843},
- {"USBC0_DTKNQR2" , 0x16f0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 844},
- {"USBC1_DTKNQR2" , 0x17f0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 844},
- {"USBC0_DTKNQR3" , 0x16f0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 845},
- {"USBC1_DTKNQR3" , 0x17f0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 845},
- {"USBC0_DTKNQR4" , 0x16f0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 846},
- {"USBC1_DTKNQR4" , 0x17f0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 846},
- {"USBC0_GAHBCFG" , 0x16f0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 847},
- {"USBC1_GAHBCFG" , 0x17f0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 847},
- {"USBC0_GHWCFG1" , 0x16f0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 848},
- {"USBC1_GHWCFG1" , 0x17f0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 848},
- {"USBC0_GHWCFG2" , 0x16f0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 849},
- {"USBC1_GHWCFG2" , 0x17f0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 849},
- {"USBC0_GHWCFG3" , 0x16f001000004cull, CVMX_CSR_DB_TYPE_NCB, 32, 850},
- {"USBC1_GHWCFG3" , 0x17f001000004cull, CVMX_CSR_DB_TYPE_NCB, 32, 850},
- {"USBC0_GHWCFG4" , 0x16f0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 851},
- {"USBC1_GHWCFG4" , 0x17f0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 851},
- {"USBC0_GINTMSK" , 0x16f0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 852},
- {"USBC1_GINTMSK" , 0x17f0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 852},
- {"USBC0_GINTSTS" , 0x16f0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 853},
- {"USBC1_GINTSTS" , 0x17f0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 853},
- {"USBC0_GNPTXFSIZ" , 0x16f0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 854},
- {"USBC1_GNPTXFSIZ" , 0x17f0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 854},
- {"USBC0_GNPTXSTS" , 0x16f001000002cull, CVMX_CSR_DB_TYPE_NCB, 32, 855},
- {"USBC1_GNPTXSTS" , 0x17f001000002cull, CVMX_CSR_DB_TYPE_NCB, 32, 855},
- {"USBC0_GOTGCTL" , 0x16f0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 856},
- {"USBC1_GOTGCTL" , 0x17f0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 856},
- {"USBC0_GOTGINT" , 0x16f0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 857},
- {"USBC1_GOTGINT" , 0x17f0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 857},
- {"USBC0_GRSTCTL" , 0x16f0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 858},
- {"USBC1_GRSTCTL" , 0x17f0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 858},
- {"USBC0_GRXFSIZ" , 0x16f0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
- {"USBC1_GRXFSIZ" , 0x17f0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
- {"USBC0_GRXSTSPD" , 0x16f0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 860},
- {"USBC1_GRXSTSPD" , 0x17f0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 860},
- {"USBC0_GRXSTSPH" , 0x16f0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
- {"USBC1_GRXSTSPH" , 0x17f0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
- {"USBC0_GRXSTSRD" , 0x16f001004001cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
- {"USBC1_GRXSTSRD" , 0x17f001004001cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
- {"USBC0_GRXSTSRH" , 0x16f001000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
- {"USBC1_GRXSTSRH" , 0x17f001000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
- {"USBC0_GSNPSID" , 0x16f0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
- {"USBC1_GSNPSID" , 0x17f0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
- {"USBC0_GUSBCFG" , 0x16f001000000cull, CVMX_CSR_DB_TYPE_NCB, 32, 865},
- {"USBC1_GUSBCFG" , 0x17f001000000cull, CVMX_CSR_DB_TYPE_NCB, 32, 865},
- {"USBC0_HAINT" , 0x16f0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 866},
- {"USBC1_HAINT" , 0x17f0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 866},
- {"USBC0_HAINTMSK" , 0x16f0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 867},
- {"USBC1_HAINTMSK" , 0x17f0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 867},
- {"USBC0_HCCHAR000" , 0x16f0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC0_HCCHAR001" , 0x16f0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC0_HCCHAR002" , 0x16f0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC0_HCCHAR003" , 0x16f0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC0_HCCHAR004" , 0x16f0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC0_HCCHAR005" , 0x16f00100005a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC0_HCCHAR006" , 0x16f00100005c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC0_HCCHAR007" , 0x16f00100005e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC1_HCCHAR000" , 0x17f0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC1_HCCHAR001" , 0x17f0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC1_HCCHAR002" , 0x17f0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC1_HCCHAR003" , 0x17f0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC1_HCCHAR004" , 0x17f0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC1_HCCHAR005" , 0x17f00100005a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC1_HCCHAR006" , 0x17f00100005c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC1_HCCHAR007" , 0x17f00100005e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
- {"USBC0_HCFG" , 0x16f0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 869},
- {"USBC1_HCFG" , 0x17f0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 869},
- {"USBC0_HCINT000" , 0x16f0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_HCINT001" , 0x16f0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_HCINT002" , 0x16f0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_HCINT003" , 0x16f0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_HCINT004" , 0x16f0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_HCINT005" , 0x16f00100005a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_HCINT006" , 0x16f00100005c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_HCINT007" , 0x16f00100005e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC1_HCINT000" , 0x17f0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC1_HCINT001" , 0x17f0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC1_HCINT002" , 0x17f0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC1_HCINT003" , 0x17f0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC1_HCINT004" , 0x17f0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC1_HCINT005" , 0x17f00100005a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC1_HCINT006" , 0x17f00100005c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC1_HCINT007" , 0x17f00100005e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
- {"USBC0_HCINTMSK000" , 0x16f001000050cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC0_HCINTMSK001" , 0x16f001000052cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC0_HCINTMSK002" , 0x16f001000054cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC0_HCINTMSK003" , 0x16f001000056cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC0_HCINTMSK004" , 0x16f001000058cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC0_HCINTMSK005" , 0x16f00100005acull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC0_HCINTMSK006" , 0x16f00100005ccull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC0_HCINTMSK007" , 0x16f00100005ecull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC1_HCINTMSK000" , 0x17f001000050cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC1_HCINTMSK001" , 0x17f001000052cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC1_HCINTMSK002" , 0x17f001000054cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC1_HCINTMSK003" , 0x17f001000056cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC1_HCINTMSK004" , 0x17f001000058cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC1_HCINTMSK005" , 0x17f00100005acull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC1_HCINTMSK006" , 0x17f00100005ccull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC1_HCINTMSK007" , 0x17f00100005ecull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
- {"USBC0_HCSPLT000" , 0x16f0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC0_HCSPLT001" , 0x16f0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC0_HCSPLT002" , 0x16f0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC0_HCSPLT003" , 0x16f0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC0_HCSPLT004" , 0x16f0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC0_HCSPLT005" , 0x16f00100005a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC0_HCSPLT006" , 0x16f00100005c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC0_HCSPLT007" , 0x16f00100005e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC1_HCSPLT000" , 0x17f0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC1_HCSPLT001" , 0x17f0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC1_HCSPLT002" , 0x17f0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC1_HCSPLT003" , 0x17f0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC1_HCSPLT004" , 0x17f0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC1_HCSPLT005" , 0x17f00100005a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC1_HCSPLT006" , 0x17f00100005c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC1_HCSPLT007" , 0x17f00100005e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
- {"USBC0_HCTSIZ000" , 0x16f0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC0_HCTSIZ001" , 0x16f0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC0_HCTSIZ002" , 0x16f0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC0_HCTSIZ003" , 0x16f0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC0_HCTSIZ004" , 0x16f0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC0_HCTSIZ005" , 0x16f00100005b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC0_HCTSIZ006" , 0x16f00100005d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC0_HCTSIZ007" , 0x16f00100005f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC1_HCTSIZ000" , 0x17f0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC1_HCTSIZ001" , 0x17f0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC1_HCTSIZ002" , 0x17f0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC1_HCTSIZ003" , 0x17f0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC1_HCTSIZ004" , 0x17f0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC1_HCTSIZ005" , 0x17f00100005b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC1_HCTSIZ006" , 0x17f00100005d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC1_HCTSIZ007" , 0x17f00100005f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
- {"USBC0_HFIR" , 0x16f0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 874},
- {"USBC1_HFIR" , 0x17f0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 874},
- {"USBC0_HFNUM" , 0x16f0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 875},
- {"USBC1_HFNUM" , 0x17f0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 875},
- {"USBC0_HPRT" , 0x16f0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 876},
- {"USBC1_HPRT" , 0x17f0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 876},
- {"USBC0_HPTXFSIZ" , 0x16f0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 877},
- {"USBC1_HPTXFSIZ" , 0x17f0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 877},
- {"USBC0_HPTXSTS" , 0x16f0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 878},
- {"USBC1_HPTXSTS" , 0x17f0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 878},
- {"USBC0_NPTXDFIFO000" , 0x16f0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC0_NPTXDFIFO001" , 0x16f0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC0_NPTXDFIFO002" , 0x16f0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC0_NPTXDFIFO003" , 0x16f0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC0_NPTXDFIFO004" , 0x16f0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC0_NPTXDFIFO005" , 0x16f0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC0_NPTXDFIFO006" , 0x16f0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC0_NPTXDFIFO007" , 0x16f0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC1_NPTXDFIFO000" , 0x17f0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC1_NPTXDFIFO001" , 0x17f0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC1_NPTXDFIFO002" , 0x17f0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC1_NPTXDFIFO003" , 0x17f0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC1_NPTXDFIFO004" , 0x17f0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC1_NPTXDFIFO005" , 0x17f0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC1_NPTXDFIFO006" , 0x17f0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC1_NPTXDFIFO007" , 0x17f0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
- {"USBC0_PCGCCTL" , 0x16f0010000e00ull, CVMX_CSR_DB_TYPE_NCB, 32, 880},
- {"USBC1_PCGCCTL" , 0x17f0010000e00ull, CVMX_CSR_DB_TYPE_NCB, 32, 880},
- {"USBN0_BIST_STATUS" , 0x11800680007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
- {"USBN1_BIST_STATUS" , 0x11800780007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
- {"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
- {"USBN1_CLK_CTL" , 0x1180078000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
- {"USBN0_CTL_STATUS" , 0x16f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 883},
- {"USBN1_CTL_STATUS" , 0x17f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 883},
- {"USBN0_DMA0_INB_CHN0" , 0x16f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 884},
- {"USBN1_DMA0_INB_CHN0" , 0x17f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 884},
- {"USBN0_DMA0_INB_CHN1" , 0x16f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 885},
- {"USBN1_DMA0_INB_CHN1" , 0x17f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 885},
- {"USBN0_DMA0_INB_CHN2" , 0x16f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 886},
- {"USBN1_DMA0_INB_CHN2" , 0x17f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 886},
- {"USBN0_DMA0_INB_CHN3" , 0x16f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 887},
- {"USBN1_DMA0_INB_CHN3" , 0x17f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 887},
- {"USBN0_DMA0_INB_CHN4" , 0x16f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 888},
- {"USBN1_DMA0_INB_CHN4" , 0x17f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 888},
- {"USBN0_DMA0_INB_CHN5" , 0x16f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 889},
- {"USBN1_DMA0_INB_CHN5" , 0x17f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 889},
- {"USBN0_DMA0_INB_CHN6" , 0x16f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 890},
- {"USBN1_DMA0_INB_CHN6" , 0x17f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 890},
- {"USBN0_DMA0_INB_CHN7" , 0x16f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 891},
- {"USBN1_DMA0_INB_CHN7" , 0x17f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 891},
- {"USBN0_DMA0_OUTB_CHN0" , 0x16f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 892},
- {"USBN1_DMA0_OUTB_CHN0" , 0x17f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 892},
- {"USBN0_DMA0_OUTB_CHN1" , 0x16f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 893},
- {"USBN1_DMA0_OUTB_CHN1" , 0x17f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 893},
- {"USBN0_DMA0_OUTB_CHN2" , 0x16f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 894},
- {"USBN1_DMA0_OUTB_CHN2" , 0x17f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 894},
- {"USBN0_DMA0_OUTB_CHN3" , 0x16f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 895},
- {"USBN1_DMA0_OUTB_CHN3" , 0x17f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 895},
- {"USBN0_DMA0_OUTB_CHN4" , 0x16f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 896},
- {"USBN1_DMA0_OUTB_CHN4" , 0x17f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 896},
- {"USBN0_DMA0_OUTB_CHN5" , 0x16f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 897},
- {"USBN1_DMA0_OUTB_CHN5" , 0x17f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 897},
- {"USBN0_DMA0_OUTB_CHN6" , 0x16f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 898},
- {"USBN1_DMA0_OUTB_CHN6" , 0x17f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 898},
- {"USBN0_DMA0_OUTB_CHN7" , 0x16f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 899},
- {"USBN1_DMA0_OUTB_CHN7" , 0x17f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 899},
- {"USBN0_DMA_TEST" , 0x16f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 900},
- {"USBN1_DMA_TEST" , 0x17f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 900},
- {"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 901},
- {"USBN1_INT_ENB" , 0x1180078000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 901},
- {"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 902},
- {"USBN1_INT_SUM" , 0x1180078000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 902},
- {"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 903},
- {"USBN1_USBP_CTL_STATUS" , 0x1180078000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 903},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_21" , 4, 18, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_25" , 23, 3, 0, "RAZ", 1, 1, 0, 0},
- {"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRFLW1" , 35, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP1" , 36, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH1" , 37, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 0, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 10, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_5_7" , 5, 3, 2, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 2, "RAZ", 1, 1, 0, 0},
- {"BYP_EN" , 16, 1, 2, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 2, "RAZ", 1, 1, 0, 0},
- {"NCTL1" , 32, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_37_39" , 37, 3, 2, "RAZ", 1, 1, 0, 0},
- {"PCTL1" , 40, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_45_47" , 45, 3, 2, "RAZ", 1, 1, 0, 0},
- {"BYP_EN1" , 48, 1, 2, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 2, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 3, "RAZ", 1, 1, 0, 0},
- {"EN" , 1, 1, 3, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 3, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 4, "RO", 0, 0, 0ull, 0ull},
- {"DUPLEX" , 2, 1, 4, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 4, "RO", 0, 0, 0ull, 0ull},
- {"RX_EN" , 4, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"TX_EN" , 5, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 4, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 9, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 10, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 11, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 11, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 12, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 12, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 12, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 12, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 14, "RAZ", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 14, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 7, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 15, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 16, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 16, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 17, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 17, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 18, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 18, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 19, "RAZ", 1, 1, 0, 0},
- {"MAXERR" , 2, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 19, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 19, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 19, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 20, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 21, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 22, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 27, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 27, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 32, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 32, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 33, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 33, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 33, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 33, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 34, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 35, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 35, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 36, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 36, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 2, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 37, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 2, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 37, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 2, 38, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 38, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 2, 38, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 38, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 39, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 39, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 40, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 40, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 40, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 41, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 60, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 2, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 61, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 64, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 64, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 64, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 64, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 64, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 65, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 65, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 65, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 65, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 65, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 68, "RAZ", 1, 1, 0, 0},
- {"BP" , 4, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 68, "RAZ", 1, 1, 0, 0},
- {"EN" , 8, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 68, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 3, 71, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 71, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 4, 72, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 72, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 4, 73, "RO", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 73, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 74, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 74, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 75, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 75, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 75, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 75, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 75, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 75, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 75, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 75, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 76, "RAZ", 1, 1, 0, 0},
- {"UART2" , 16, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"USB1" , 17, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"MII1" , 18, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 76, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 77, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 77, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 77, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 77, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 77, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 77, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 78, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 78, "RAZ", 1, 1, 0, 0},
- {"UART2" , 16, 1, 78, "R/W", 0, 0, 0ull, 0ull},
- {"USB1" , 17, 1, 78, "R/W", 0, 0, 0ull, 0ull},
- {"MII1" , 18, 1, 78, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 78, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 79, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 79, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 79, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 79, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 79, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 79, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 79, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 79, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 79, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 79, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 80, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 80, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 80, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 80, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 80, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 80, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 80, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 80, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 80, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 80, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 81, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 81, "RAZ", 1, 1, 0, 0},
- {"UART2" , 16, 1, 81, "RO", 0, 0, 0ull, 0ull},
- {"USB1" , 17, 1, 81, "RO", 0, 0, 0ull, 0ull},
- {"MII1" , 18, 1, 81, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 81, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 82, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 83, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 4, 84, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 84, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 85, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 85, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 4, 86, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 86, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 87, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 88, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 3, 88, "R/W", 0, 0, 32767ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 88, "RAZ", 1, 1, 0, 0},
- {"QLM_DCOK" , 0, 2, 89, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 89, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 2, 90, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 90, "RAZ", 1, 1, 0, 0},
- {"MUX_SEL" , 4, 1, 90, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 90, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 90, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 90, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 91, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 91, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_39" , 37, 3, 91, "RAZ", 1, 1, 0, 0},
- {"SELECT" , 40, 2, 91, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_42_60" , 42, 19, 91, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 91, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 91, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 91, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 92, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 93, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 93, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 94, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 94, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 95, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 95, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 96, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 96, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 97, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 97, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 97, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 97, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 97, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 98, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 98, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 98, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 98, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 98, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 98, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 99, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 99, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 99, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 99, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 99, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 99, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 99, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 100, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 101, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 102, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 102, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 103, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 103, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 104, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 104, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 104, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 105, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 105, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 105, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 106, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 106, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 107, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 108, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 108, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 108, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 108, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 108, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 108, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 108, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 109, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 109, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 110, "RAZ", 1, 1, 0, 0},
- {"LOGL_EN" , 0, 16, 111, "R/W", 0, 1, 65535ull, 0},
- {"PHYS_EN" , 16, 1, 111, "R/W", 0, 1, 1ull, 0},
- {"HG2RX_EN" , 17, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"HG2TX_EN" , 18, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 111, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 112, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 112, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 112, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 2, 112, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 112, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 2, 112, "RO", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 112, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 113, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 113, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 114, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 114, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 114, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 114, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 114, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 114, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 114, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 114, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 114, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 115, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 116, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 117, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 118, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 119, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 120, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 121, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 121, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 122, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 122, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 122, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 122, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 123, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 123, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 124, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 124, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 124, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 124, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 124, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 124, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 124, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 124, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 124, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 125, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 125, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 125, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 125, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 125, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 125, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 125, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 125, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 126, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 126, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 127, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 127, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 127, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 127, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 127, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 127, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 128, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 128, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 128, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 128, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 128, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 128, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 129, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 129, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 130, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 130, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 131, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 131, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 132, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 132, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 133, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 133, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 134, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 134, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 135, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 135, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 136, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 136, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 137, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 137, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 138, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 138, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 139, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 140, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 141, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 141, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 141, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 142, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 142, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 143, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 143, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 144, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 144, "RAZ", 1, 1, 0, 0},
- {"LGTIM2GO" , 0, 16, 145, "RO", 0, 1, 0ull, 0},
- {"XOF" , 16, 16, 145, "RO", 0, 0, 0ull, 0ull},
- {"PHTIM2GO" , 32, 16, 145, "RO", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 145, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 4, 146, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 146, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 4, 146, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 146, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 147, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 147, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 148, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 148, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 148, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 148, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 148, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 149, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 149, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 150, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 150, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 151, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 151, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 151, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 152, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 152, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 152, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 152, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 152, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 153, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 153, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 154, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 154, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 154, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 155, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 155, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 156, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 156, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 157, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 157, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 158, "RO", 1, 1, 0, 0},
- {"MSG_TIME" , 16, 16, 158, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 158, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 159, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 159, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 160, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 160, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 161, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 161, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 162, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 163, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 163, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 164, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 164, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 165, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 165, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 166, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 166, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 167, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 167, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 168, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 168, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 169, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 169, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 170, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 170, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 171, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 171, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 172, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 172, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 173, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 173, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 174, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 174, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 175, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 175, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 176, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 176, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 177, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 177, "RAZ", 1, 1, 0, 0},
- {"TX_XOF" , 0, 16, 178, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 178, "RAZ", 1, 1, 0, 0},
- {"TX_XON" , 0, 16, 179, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 179, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 180, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 180, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 180, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 181, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 181, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 181, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 181, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 181, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 182, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 182, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 182, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 183, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 183, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 184, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 184, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 185, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 185, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 185, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 185, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 186, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 186, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 187, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 187, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 188, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_5_63" , 5, 59, 188, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 189, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 189, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 189, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 189, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 189, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 189, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 189, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 190, "R/W", 0, 0, 8ull, 8ull},
- {"EN" , 4, 1, 190, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 190, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 191, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 191, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 191, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 191, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 191, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 192, "WO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 192, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 193, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 193, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 194, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 195, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 195, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 196, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 196, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 197, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 198, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 198, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 198, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 198, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 199, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 199, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 200, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 200, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 200, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 201, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 201, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 201, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 202, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 202, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 202, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 202, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 202, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 203, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 203, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 203, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 203, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 203, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 204, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 205, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 206, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 207, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 208, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 208, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 209, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 209, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 210, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 210, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 211, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 211, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 211, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 211, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 211, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 212, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 212, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 212, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 212, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 212, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 213, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 214, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 215, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 215, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 215, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 216, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 216, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 216, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 217, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 217, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 218, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 218, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 219, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 219, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 220, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 220, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 221, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 222, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 40, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 223, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 224, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 225, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 225, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 225, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 226, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 227, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 228, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 229, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 229, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 230, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 230, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 231, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 231, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 232, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 232, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 232, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 233, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 233, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 234, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 234, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 235, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 235, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 236, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 237, "R/W", 0, 0, 0ull, 1ull},
- {"RADDR" , 0, 3, 238, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 238, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 238, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 238, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 238, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 238, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 239, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 239, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 239, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 239, "RO", 0, 0, 8ull, 8ull},
- {"RESERVED_44_63" , 44, 20, 239, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 240, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 240, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 240, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 240, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 241, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 241, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 241, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 241, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 241, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 241, "RO", 0, 0, 8ull, 8ull},
- {"RESERVED_61_63" , 61, 3, 241, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 242, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 242, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 243, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 243, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 244, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 244, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 244, "R/W", 0, 0, 0ull, 0ull},
- {"PRT_ENB" , 0, 4, 245, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 245, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 246, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 246, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 246, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 246, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 246, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 247, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 247, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 247, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 248, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_35" , 32, 4, 248, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT2" , 36, 4, 248, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_40_63" , 40, 24, 248, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 249, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 249, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 249, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 250, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 250, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 251, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 251, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 252, "RO", 0, 0, 0ull, 0ull},
- {"STIN_MSK" , 4, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 10, 252, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 252, "RAZ", 0, 0, 0ull, 0ull},
- {"WLB_MSK" , 19, 4, 252, "RO", 0, 0, 0ull, 0ull},
- {"DTBNK" , 23, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 252, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 9, 253, "RO", 0, 0, 0ull, 0ull},
- {"VAB_VWCF" , 9, 1, 253, "RO", 0, 0, 0ull, 0ull},
- {"ILC" , 10, 1, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 253, "RAZ", 0, 0, 0ull, 0ull},
- {"VWDF" , 12, 4, 253, "RO", 0, 0, 0ull, 0ull},
- {"PLC0" , 16, 1, 253, "RO", 0, 0, 0ull, 0ull},
- {"PLC1" , 17, 1, 253, "RO", 0, 0, 0ull, 0ull},
- {"PLC2" , 18, 1, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 253, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 254, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 254, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 254, "RAZ", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 254, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 254, "RAZ", 0, 0, 0ull, 0ull},
- {"RMDF" , 8, 4, 254, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 254, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 254, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 255, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 255, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 255, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 255, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 255, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 255, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 255, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 255, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_17" , 14, 4, 255, "RAZ", 1, 1, 0, 0},
- {"LBIST" , 18, 1, 255, "R/W", 0, 0, 0ull, 0ull},
- {"BSTRUN" , 19, 1, 255, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 255, "RAZ", 1, 1, 0, 0},
- {"L2T" , 0, 1, 256, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 256, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 256, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 3, 256, "R/W", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 2, 256, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_9" , 8, 2, 256, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 256, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 3, 256, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 256, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 257, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 257, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 257, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 257, "RAZ", 0, 0, 0ull, 0ull},
- {"PLC0RMSK" , 0, 32, 258, "R/W", 0, 0, 0ull, 0ull},
- {"PLC1RMSK" , 32, 32, 258, "R/W", 0, 0, 0ull, 0ull},
- {"PLC2RMSK" , 0, 32, 259, "R/W", 0, 0, 0ull, 0ull},
- {"ILCRMSK" , 32, 32, 259, "R/W", 0, 0, 0ull, 0ull},
- {"OOB1EN" , 0, 1, 260, "R/W", 0, 0, 0ull, 1ull},
- {"OOB2EN" , 1, 1, 260, "R/W", 0, 0, 0ull, 1ull},
- {"OOB3EN" , 2, 1, 260, "R/W", 0, 0, 0ull, 1ull},
- {"L2TSECEN" , 3, 1, 260, "R/W", 0, 0, 0ull, 1ull},
- {"L2TDEDEN" , 4, 1, 260, "R/W", 0, 0, 0ull, 1ull},
- {"L2DSECEN" , 5, 1, 260, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDEDEN" , 6, 1, 260, "R/W", 0, 0, 0ull, 1ull},
- {"LCKENA" , 7, 1, 260, "R/W", 0, 0, 0ull, 1ull},
- {"LCK2ENA" , 8, 1, 260, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 260, "RAZ", 0, 0, 0ull, 0ull},
- {"OOB1" , 0, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
- {"OOB2" , 1, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
- {"OOB3" , 2, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2TSEC" , 3, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2TDED" , 4, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2DSEC" , 5, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2DDED" , 6, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK" , 7, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK2" , 8, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 261, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 262, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 262, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 262, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 262, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 263, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 263, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 264, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 264, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 3, 264, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_17" , 17, 1, 264, "RAZ", 0, 0, 0ull, 0ull},
- {"SET" , 18, 3, 264, "RO", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 3, 264, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 264, "RAZ", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 264, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 265, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 265, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 9, 266, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 9, 18, 266, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 266, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 3, 267, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_3_3" , 3, 1, 267, "RAZ", 0, 0, 0ull, 0ull},
- {"STPARTDIS" , 4, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 267, "RAZ", 0, 0, 0ull, 0ull},
- {"STENA" , 0, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"DWBENA" , 1, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 268, "RAZ", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 269, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 269, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 269, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 269, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 269, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 270, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 270, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 270, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 270, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 270, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 270, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 271, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 271, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 271, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 271, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 271, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 271, "RO", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 272, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 272, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 273, "RAZ", 0, 0, 0ull, 0ull},
- {"PP0GRP" , 0, 2, 274, "R/W", 0, 0, 0ull, 0ull},
- {"PP1GRP" , 2, 2, 274, "R/W", 0, 0, 0ull, 0ull},
- {"PP2GRP" , 4, 2, 274, "R/W", 0, 0, 0ull, 0ull},
- {"PP3GRP" , 6, 2, 274, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 274, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 8, 275, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK1" , 8, 8, 275, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK2" , 16, 8, 275, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK3" , 24, 8, 275, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 275, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 8, 276, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 276, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 277, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 277, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 278, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 278, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 279, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 279, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 280, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 280, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 281, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 281, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 281, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 281, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 281, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 281, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 281, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 10, 282, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 282, "RAZ", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 3, 282, "RO", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 282, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 282, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 283, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 283, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 283, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 284, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 284, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 284, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 285, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 286, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 287, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 287, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 288, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_256K" , 34, 1, 288, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_128K" , 35, 1, 288, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_36" , 36, 1, 288, "RO", 0, 0, 0ull, 0ull},
- {"EMA_CTL" , 37, 3, 288, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 288, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 289, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 289, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 289, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 289, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 289, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 289, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 9, 289, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 289, "RAZ", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 3, 289, "RO", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 289, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 289, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 289, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 289, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_28_63" , 28, 36, 289, "RAZ", 0, 0, 0ull, 0ull},
- {"START" , 0, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 290, "RAZ", 1, 0, 0, 0ull},
- {"MRD" , 0, 3, 291, "RO", 1, 0, 0, 0ull},
- {"MRF" , 3, 1, 291, "RO", 1, 0, 0, 0ull},
- {"MWC" , 4, 1, 291, "RO", 1, 0, 0, 0ull},
- {"MWD" , 5, 3, 291, "RO", 1, 0, 0, 0ull},
- {"MWF" , 8, 1, 291, "RO", 1, 0, 0, 0ull},
- {"CSRE2D" , 9, 1, 291, "RO", 1, 0, 0, 0ull},
- {"CSRD2E" , 10, 1, 291, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 291, "RAZ", 1, 0, 0, 0ull},
- {"PCTL_DAT" , 0, 5, 292, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_11" , 5, 7, 292, "RAZ", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 292, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 292, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_27" , 20, 8, 292, "RAZ", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 292, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 293, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 293, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 293, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 293, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"MODE32B" , 10, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 11, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MRF" , 12, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 293, "RAZ", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 293, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_17" , 16, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 293, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 293, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 293, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 293, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 294, "RAZ", 0, 1, 0ull, 0},
- {"DCC_ENABLE" , 8, 1, 294, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_MODE" , 9, 1, 294, "R/W", 0, 0, 0ull, 1ull},
- {"SEQUENCE" , 10, 3, 294, "R/W", 0, 0, 0ull, 0ull},
- {"IDLEPOWER" , 13, 3, 294, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 16, 4, 294, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 20, 1, 294, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_63" , 21, 43, 294, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 295, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 295, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 296, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 296, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 297, "R/W", 0, 0, 1ull, 1ull},
- {"RDQS" , 1, 1, 297, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 297, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 297, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 297, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 297, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 297, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 297, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 297, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 297, "R/W", 0, 0, 0ull, 0ull},
- {"SILO_HC" , 21, 1, 297, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 297, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 297, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 297, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 297, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 297, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 297, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 297, "RAZ", 0, 0, 0ull, 0ull},
- {"CLK" , 0, 4, 298, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 298, "RAZ", 0, 0, 0ull, 0ull},
- {"CMD" , 5, 4, 298, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 298, "RAZ", 0, 0, 0ull, 0ull},
- {"DQ" , 10, 4, 298, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 298, "RAZ", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 0, 5, 299, "R/W", 0, 1, 0ull, 0},
- {"DLL90_ENA" , 5, 1, 299, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 6, 1, 299, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 7, 1, 299, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 299, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 300, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 300, "RAZ", 0, 1, 0ull, 0},
- {"ROW_LSB" , 16, 3, 300, "R/W", 0, 1, 3ull, 0},
- {"BANK8" , 19, 1, 300, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 300, "RAZ", 0, 1, 0ull, 0},
- {"MRDSYN0" , 0, 8, 301, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 301, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 301, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 301, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 301, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 302, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 302, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 302, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 302, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 302, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 303, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 303, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 304, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 304, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 305, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 305, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 305, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 305, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 305, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 305, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 305, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 305, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 305, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 305, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 305, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 305, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 305, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 305, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 306, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 306, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 306, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 306, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 306, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 306, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 306, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 306, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_31_63" , 31, 33, 306, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 307, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 307, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 308, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 308, "RAZ", 1, 1, 0, 0},
- {"EN2" , 0, 1, 309, "R/W", 0, 1, 0ull, 0},
- {"EN4" , 1, 1, 309, "R/W", 0, 1, 0ull, 0},
- {"EN6" , 2, 1, 309, "R/W", 0, 1, 0ull, 0},
- {"EN8" , 3, 1, 309, "R/W", 0, 1, 1ull, 0},
- {"EN12" , 4, 1, 309, "R/W", 0, 1, 0ull, 0},
- {"EN16" , 5, 1, 309, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 309, "RAZ", 0, 1, 0ull, 0},
- {"CLKR" , 8, 6, 309, "R/W", 0, 1, 0ull, 0},
- {"CLKF" , 14, 12, 309, "R/W", 0, 1, 31ull, 0},
- {"RESET_N" , 26, 1, 309, "R/W", 0, 0, 0ull, 1ull},
- {"DIV_RESET" , 27, 1, 309, "R/W", 0, 0, 1ull, 0ull},
- {"FASTEN_N" , 28, 1, 309, "R/W", 0, 0, 0ull, 1ull},
- {"BYPASS" , 29, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 309, "RAZ", 0, 1, 0ull, 0},
- {"FBSLIP" , 0, 1, 310, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 310, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_21" , 2, 20, 310, "RAZ", 1, 1, 0, 0},
- {"DDR__PCTL" , 22, 5, 310, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 27, 5, 310, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 310, "RAZ", 1, 1, 0, 0},
- {"BNK" , 0, 3, 311, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 311, "RAZ", 0, 0, 0ull, 0ull},
- {"COL" , 4, 12, 311, "R/W", 0, 0, 0ull, 0ull},
- {"ROW" , 16, 16, 311, "R/W", 0, 0, 0ull, 0ull},
- {"PATTERN" , 32, 8, 311, "R/W", 0, 0, 170ull, 170ull},
- {"RANKMASK" , 40, 4, 311, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_63" , 44, 20, 311, "RAZ", 0, 0, 0ull, 0ull},
- {"BYTE" , 0, 4, 312, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 312, "RAZ", 0, 0, 0ull, 0ull},
- {"BITMASK" , 16, 16, 312, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 312, "RAZ", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 4, 313, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 4, 4, 313, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 8, 4, 313, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 12, 4, 313, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 16, 4, 313, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 20, 4, 313, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 24, 4, 313, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 28, 4, 313, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 32, 4, 313, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 36, 2, 313, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 313, "RAZ", 1, 0, 0, 0ull},
- {"PCTL" , 0, 5, 314, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 314, "RAZ", 0, 1, 0ull, 0},
- {"NCTL" , 8, 4, 314, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 314, "RAZ", 0, 1, 0ull, 0},
- {"ENABLE" , 16, 1, 314, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 314, "RAZ", 0, 1, 0ull, 0},
- {"RODT_LO0" , 0, 4, 315, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_LO1" , 4, 4, 315, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_LO2" , 8, 4, 315, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_LO3" , 12, 4, 315, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI0" , 16, 4, 315, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI1" , 20, 4, 315, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI2" , 24, 4, 315, "R/W", 0, 0, 15ull, 0ull},
- {"RODT_HI3" , 28, 4, 315, "R/W", 0, 0, 15ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 315, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 316, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D0_R1" , 8, 8, 316, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R0" , 16, 8, 316, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R1" , 24, 8, 316, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 316, "RAZ", 0, 0, 0ull, 0ull},
- {"WODT_D2_R0" , 0, 8, 317, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R1" , 8, 8, 317, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R0" , 16, 8, 317, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R1" , 24, 8, 317, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 317, "RAZ", 0, 0, 0ull, 0ull},
- {"NCBI" , 0, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"DMA" , 2, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 3, 1, 318, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 318, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 319, "R/W", 0, 1, 31ull, 0},
- {"PCTL" , 5, 5, 319, "R/W", 0, 1, 31ull, 0},
- {"RESERVED_10_63" , 10, 54, 319, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 320, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 320, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 320, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 320, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 321, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 321, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 321, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 322, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 322, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 322, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 323, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 323, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 323, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 323, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 323, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 323, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 323, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 323, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 323, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 323, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 323, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 323, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 323, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 323, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 323, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 324, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 325, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 326, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 326, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 326, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 327, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 327, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 327, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 327, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 327, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 328, "R/W", 1, 1, 0, 0},
- {"BASE" , 0, 16, 329, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 329, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 329, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 329, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 329, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 329, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 329, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 329, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 329, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 330, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 330, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 330, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 330, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 330, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 330, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 330, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 330, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 330, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 330, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 330, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 330, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 330, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 331, "R/W", 0, 0, 26ull, 26ull},
- {"RESERVED_6_7" , 6, 2, 331, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 331, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 331, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 331, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 331, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 332, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 333, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 333, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 334, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 334, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 4, 335, "RO", 1, 1, 0, 0},
- {"RESERVED_4_15" , 4, 12, 335, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 335, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 335, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 335, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 335, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 335, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 335, "RO", 1, 1, 0, 0},
- {"NOKASU" , 29, 1, 335, "RO", 1, 1, 0, 0},
- {"RESERVED_30_31" , 30, 2, 335, "RAZ", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 335, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 335, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 335, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 336, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 336, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 336, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 336, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 336, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 336, "RO", 1, 1, 0, 0},
- {"ZIP_CRIP" , 29, 2, 336, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 336, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 337, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_3_3" , 3, 1, 337, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 337, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_63" , 7, 57, 337, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 338, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 339, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 339, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 339, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 340, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 340, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 8, 341, "R/W", 0, 1, 3ull, 0},
- {"SCLK_HI" , 8, 12, 341, "R/W", 0, 1, 100ull, 0},
- {"SCLK_LO" , 20, 4, 341, "R/W", 0, 1, 2ull, 0},
- {"OUT" , 24, 8, 341, "R/W", 0, 1, 3ull, 0},
- {"PROG_PIN" , 32, 1, 341, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 341, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 342, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 342, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 342, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 342, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 342, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 342, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 342, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 343, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 14, 14, 343, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 28, 14, 343, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 343, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 344, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 344, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 3, 345, "R/W", 1, 1, 0, 0},
- {"RESERVED_3_63" , 3, 61, 345, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 346, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 346, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 346, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 346, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 346, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 346, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 346, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 346, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 346, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 346, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 346, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 346, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 346, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 347, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 347, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 347, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 347, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 347, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 347, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 347, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 347, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 347, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 348, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 348, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 348, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 349, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 349, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 349, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 350, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 350, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 351, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 351, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 352, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 352, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 353, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 353, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 353, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 353, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 353, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 353, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 353, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 354, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 354, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 355, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 355, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 355, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 356, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 356, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 356, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 356, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 357, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 357, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 357, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 357, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 358, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 358, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 358, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 358, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 358, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 358, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 358, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 358, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 358, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 359, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 359, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 360, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 360, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 360, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 360, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 360, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 360, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 360, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 360, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 360, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 361, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 361, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 362, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 362, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 363, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 363, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 363, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 363, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 364, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 365, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 365, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 366, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 366, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 367, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 367, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 367, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 367, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 368, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 368, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 369, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 369, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 370, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 370, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 371, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 371, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 372, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 372, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 373, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 373, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 374, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 374, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 374, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 374, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 374, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 374, "RAZ", 1, 1, 0, 0},
- {"DLH" , 0, 8, 375, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 375, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 376, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 376, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 377, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 378, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 378, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 378, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 378, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 378, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 378, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 378, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 379, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 379, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 380, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 380, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 380, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 380, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 380, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 380, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 380, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 381, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 381, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 381, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 381, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 382, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 382, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 382, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 382, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 382, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 382, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 382, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 382, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 383, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 383, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 383, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 383, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 383, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 383, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 383, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 383, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 383, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 384, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 384, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 385, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 385, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 385, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 385, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 385, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 385, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 385, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 385, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 385, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 386, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 386, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 387, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 387, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 388, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 388, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 388, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 388, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 389, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 389, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 390, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 390, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 391, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 391, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 392, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 392, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 392, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 392, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 393, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 393, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 394, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 394, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 395, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 395, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 396, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 396, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 397, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 397, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 398, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 398, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 399, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 399, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 399, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 399, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 399, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 399, "RAZ", 1, 1, 0, 0},
- {"ORFDAT" , 0, 1, 400, "RO", 0, 0, 0ull, 0ull},
- {"IRFDAT" , 1, 1, 400, "RO", 0, 0, 0ull, 0ull},
- {"IPFDAT" , 2, 1, 400, "RO", 0, 0, 0ull, 0ull},
- {"MRQDAT" , 3, 1, 400, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 400, "RAZ", 0, 0, 0ull, 0ull},
- {"MRQ_HWM" , 0, 2, 401, "R/W", 0, 0, 0ull, 1ull},
- {"NBTARB" , 2, 1, 401, "R/W", 0, 0, 0ull, 0ull},
- {"LENDIAN" , 3, 1, 401, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 4, 1, 401, "R/W", 0, 0, 1ull, 0ull},
- {"EN" , 5, 1, 401, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 6, 1, 401, "RO", 0, 0, 0ull, 0ull},
- {"CRC_STRIP" , 7, 1, 401, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 401, "RAZ", 1, 1, 0, 0},
- {"OVFENA" , 0, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"IVFENA" , 1, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"OTHENA" , 2, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"ITHENA" , 3, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_DRPENA" , 4, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"IRUNENA" , 5, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"ORUNENA" , 6, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 402, "RAZ", 1, 1, 0, 0},
- {"IRCNT" , 0, 20, 403, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 403, "RAZ", 1, 1, 0, 0},
- {"IRHWM" , 0, 20, 404, "R/W", 0, 0, 0ull, 0ull},
- {"IBPLWM" , 20, 20, 404, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 404, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 405, "RAZ", 1, 1, 0, 0},
- {"IBASE" , 3, 33, 405, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 405, "RAZ", 1, 1, 0, 0},
- {"ISIZE" , 40, 20, 405, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 405, "RAZ", 1, 1, 0, 0},
- {"IDBELL" , 0, 20, 406, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 406, "RAZ", 1, 1, 0, 0},
- {"ITLPTR" , 32, 20, 406, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 406, "RAZ", 1, 1, 0, 0},
- {"ODBLOVF" , 0, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
- {"IDBLOVF" , 1, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORTHRESH" , 2, 1, 407, "RO", 0, 0, 0ull, 0ull},
- {"IRTHRESH" , 3, 1, 407, "RO", 0, 0, 0ull, 0ull},
- {"DATA_DRP" , 4, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
- {"IRUN" , 5, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORUN" , 6, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 407, "RAZ", 1, 1, 0, 0},
- {"ORCNT" , 0, 20, 408, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 408, "RAZ", 1, 1, 0, 0},
- {"ORHWM" , 0, 20, 409, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 409, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 410, "RAZ", 1, 1, 0, 0},
- {"OBASE" , 3, 33, 410, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 410, "RAZ", 1, 1, 0, 0},
- {"OSIZE" , 40, 20, 410, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 410, "RAZ", 1, 1, 0, 0},
- {"ODBELL" , 0, 20, 411, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 411, "RAZ", 1, 1, 0, 0},
- {"OTLPTR" , 32, 20, 411, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 411, "RAZ", 1, 1, 0, 0},
- {"OREMCNT" , 0, 20, 412, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 412, "RAZ", 1, 1, 0, 0},
- {"IREMCNT" , 32, 20, 412, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_52_63" , 52, 12, 412, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 413, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 413, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 413, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 413, "RAZ", 1, 1, 0, 0},
- {"NCB_CMD" , 0, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"DR3_MEM" , 2, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"DIF3" , 3, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"DIF2" , 4, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"DIF1" , 5, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"DIF0" , 6, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"CSM1" , 7, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"CSM0" , 8, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P1" , 9, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_CO" , 19, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_NO" , 20, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_PO" , 21, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_CO" , 22, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_NO" , 23, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_PO" , 24, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P1" , 25, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_O" , 27, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_C" , 28, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_O" , 29, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"DR2_MEM" , 31, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D3_PST" , 32, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D2_PST" , 33, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D1_PST" , 34, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D0_PST" , 35, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"DR1_MEM" , 36, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D3_MEM" , 37, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D2_MEM" , 38, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D1_MEM" , 39, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D0_MEM" , 40, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"DR0_MEM" , 41, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D3_MEM3" , 42, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D2_MEM2" , 43, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D1_MEM1" , 44, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"D0_MEM0" , 45, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 414, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_CAX" , 1, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 2, 2, 415, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 4, 1, 415, "R/W", 0, 0, 0ull, 1ull},
- {"PTLP_RO" , 5, 1, 415, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 415, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 415, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 415, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 415, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 415, "R/W", 0, 0, 3ull, 3ull},
- {"INTA" , 16, 1, 415, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 17, 1, 415, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 18, 1, 415, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 19, 1, 415, "RO", 0, 0, 1ull, 1ull},
- {"WAITL_COM" , 20, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_63" , 21, 43, 415, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_CAX" , 1, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 2, 2, 416, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 4, 1, 416, "R/W", 0, 0, 0ull, 1ull},
- {"PTLP_RO" , 5, 1, 416, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 416, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 416, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 416, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 416, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 416, "R/W", 0, 0, 3ull, 3ull},
- {"INTA" , 16, 1, 416, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 17, 1, 416, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 18, 1, 416, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 19, 1, 416, "RO", 0, 0, 1ull, 1ull},
- {"WAITL_COM" , 20, 1, 416, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_63" , 21, 43, 416, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 417, "RO", 1, 1, 0, 0},
- {"HOST_MODE" , 8, 1, 417, "RO", 1, 1, 0, 0},
- {"RESERVED_9_12" , 9, 4, 417, "RAZ", 0, 0, 0ull, 0ull},
- {"ARB" , 13, 1, 417, "R/W", 0, 0, 0ull, 1ull},
- {"LNK_RST" , 14, 1, 417, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 417, "RAZ", 0, 0, 0ull, 0ull},
- {"CFG_RTRY" , 16, 16, 417, "R/W", 0, 0, 0ull, 0ull},
- {"P0_NTAGS" , 32, 6, 417, "R/W", 0, 0, 32ull, 32ull},
- {"P1_NTAGS" , 38, 6, 417, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_44_63" , 44, 20, 417, "RAZ", 1, 1, 0, 0},
- {"C0_B0_D" , 0, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"C0_WI_D" , 1, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"C1_B0_D" , 2, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"C1_WI_D" , 3, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"C0_B1_S" , 4, 3, 418, "R/W", 0, 0, 1ull, 1ull},
- {"C1_B1_S" , 7, 3, 418, "R/W", 0, 0, 1ull, 1ull},
- {"C0_W_FLT" , 10, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"C1_W_FLT" , 11, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"MRRS" , 12, 3, 418, "R/W", 0, 0, 2ull, 2ull},
- {"MPS" , 15, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 418, "RAZ", 1, 1, 0, 0},
- {"P0_FCNT" , 0, 6, 419, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 419, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 419, "RO", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 419, "RO", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 419, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 420, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 420, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 420, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 23, 2, 420, "RO", 1, 1, 0, 0},
- {"QLM1_MODE" , 25, 2, 420, "RO", 1, 1, 0, 0},
- {"QLM0_REV_LANES" , 27, 1, 420, "RO", 1, 1, 0, 0},
- {"QLM0_LINK_WIDTH" , 28, 1, 420, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 420, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 421, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 421, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 422, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 422, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 422, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 423, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 423, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 424, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 29, 424, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 424, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 425, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 425, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 426, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 426, "R/W", 0, 1, 0ull, 0},
- {"CNT" , 0, 32, 427, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 427, "R/W", 0, 1, 0ull, 0},
- {"DMA0" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
- {"DMA1" , 32, 32, 428, "R/W", 0, 1, 0ull, 0},
- {"CSIZE" , 0, 14, 429, "R/W", 0, 1, 0ull, 0},
- {"O_MODE" , 14, 1, 429, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 429, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 429, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 429, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 429, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 429, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 429, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 429, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"DMA0_ENB" , 34, 1, 429, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1_ENB" , 35, 1, 429, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2_ENB" , 36, 1, 429, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3_ENB" , 37, 1, 429, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_38_63" , 38, 26, 429, "RO", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 430, "RAZ", 0, 0, 0ull, 0ull},
- {"D3_REQST" , 5, 5, 430, "RO", 0, 1, 0ull, 0},
- {"D2_REQST" , 10, 5, 430, "RO", 0, 1, 0ull, 0},
- {"D1_REQST" , 15, 5, 430, "RO", 0, 1, 0ull, 0},
- {"D0_REQST" , 20, 5, 430, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_31" , 25, 7, 430, "RAZ", 0, 0, 0ull, 0ull},
- {"D3_DIFST" , 32, 7, 430, "RO", 0, 1, 0ull, 0},
- {"D2_DIFST" , 39, 7, 430, "RO", 0, 1, 0ull, 0},
- {"D1_DIFST" , 46, 7, 430, "RO", 0, 1, 0ull, 0},
- {"D0_DIFST" , 53, 7, 430, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 430, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_0_8" , 0, 9, 431, "RAZ", 0, 0, 0ull, 0ull},
- {"D3_DFFST" , 9, 9, 431, "RO", 0, 1, 0ull, 0},
- {"D2_DFFST" , 18, 9, 431, "RO", 0, 1, 0ull, 0},
- {"D1_DFFST" , 27, 9, 431, "RO", 0, 1, 0ull, 0},
- {"D0_DFFST" , 36, 9, 431, "RO", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 431, "RAZ", 0, 0, 0ull, 0ull},
- {"D3_DREST" , 0, 15, 432, "RO", 0, 1, 0ull, 0},
- {"D2_DREST" , 15, 15, 432, "RO", 0, 1, 0ull, 0},
- {"D1_DREST" , 30, 15, 432, "RO", 0, 1, 0ull, 0},
- {"D0_DREST" , 45, 15, 432, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 432, "RAZ", 0, 0, 0ull, 0ull},
- {"D3_DWEST" , 0, 13, 433, "RO", 0, 1, 0ull, 0},
- {"D2_DWEST" , 13, 13, 433, "RO", 0, 1, 0ull, 0},
- {"D1_DWEST" , 26, 13, 433, "RO", 0, 1, 0ull, 0},
- {"D0_DWEST" , 39, 13, 433, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 433, "RAZ", 0, 0, 0ull, 0ull},
- {"DMA0_CPL" , 0, 1, 434, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1_CPL" , 1, 1, 434, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 434, "RAZ", 0, 1, 0ull, 0},
- {"DMA0_CPL" , 0, 1, 435, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1_CPL" , 1, 1, 435, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 435, "RAZ", 0, 1, 0ull, 0},
- {"DMA0_CPL" , 0, 1, 436, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_CPL" , 1, 1, 436, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 436, "RAZ", 0, 0, 0ull, 0ull},
- {"RML_RTO" , 0, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0DBO" , 4, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1DBO" , 5, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2DBO" , 6, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3DBO" , 7, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_8" , 8, 1, 437, "R/W", 1, 1, 0, 0},
- {"DMA0FI" , 9, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1FI" , 10, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT0" , 11, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT1" , 12, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME0" , 13, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME1" , 14, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"PSLDBOF" , 15, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"PIDBOF" , 16, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 17, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 18, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_AERI" , 19, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_ER" , 20, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_SE" , 21, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_DR" , 22, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_WAKE" , 23, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_PMEI" , 24, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_HPINT" , 25, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_AERI" , 26, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_ER" , 27, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_SE" , 28, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_DR" , 29, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_WAKE" , 30, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_PMEI" , 31, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_HPINT" , 32, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B0" , 33, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B1" , 34, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B2" , 35, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WI" , 36, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_BX" , 37, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B0" , 38, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B1" , 39, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B2" , 40, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WI" , 41, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_BX" , 42, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B0" , 43, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B1" , 44, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B2" , 45, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WI" , 46, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_BX" , 47, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B0" , 48, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B1" , 49, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B2" , 50, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WI" , 51, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_BX" , 52, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WF" , 53, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WF" , 54, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WF" , 55, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WF" , 56, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_EXC" , 57, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_EXC" , 58, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C0_LDWN" , 59, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"C1_LDWN" , 60, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"INT_A" , 61, 1, 437, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_62_62" , 62, 1, 437, "RAZ", 0, 1, 0ull, 0},
- {"MIO_INTA" , 63, 1, 437, "R/W", 0, 0, 0ull, 1ull},
- {"RML_RTO" , 0, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0DBO" , 4, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1DBO" , 5, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2DBO" , 6, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3DBO" , 7, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_8" , 8, 1, 438, "R/W", 1, 1, 0, 0},
- {"DMA0FI" , 9, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1FI" , 10, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT0" , 11, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT1" , 12, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME0" , 13, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME1" , 14, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"PSLDBOF" , 15, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"PIDBOF" , 16, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 17, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 18, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_AERI" , 19, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_ER" , 20, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_SE" , 21, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_DR" , 22, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_WAKE" , 23, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_PMEI" , 24, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_HPINT" , 25, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_AERI" , 26, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_ER" , 27, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_SE" , 28, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_DR" , 29, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_WAKE" , 30, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_PMEI" , 31, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_HPINT" , 32, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B0" , 33, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B1" , 34, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B2" , 35, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WI" , 36, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_BX" , 37, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B0" , 38, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B1" , 39, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B2" , 40, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WI" , 41, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_BX" , 42, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B0" , 43, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B1" , 44, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B2" , 45, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WI" , 46, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_BX" , 47, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B0" , 48, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B1" , 49, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B2" , 50, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WI" , 51, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_BX" , 52, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WF" , 53, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WF" , 54, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WF" , 55, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WF" , 56, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_EXC" , 57, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_EXC" , 58, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C0_LDWN" , 59, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"C1_LDWN" , 60, 1, 438, "R/W", 0, 0, 0ull, 1ull},
- {"INT_A" , 61, 1, 438, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_62_63" , 62, 2, 438, "RAZ", 0, 1, 0ull, 0},
- {"RML_RTO" , 0, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0DBO" , 4, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1DBO" , 5, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA2DBO" , 6, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA3DBO" , 7, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 439, "R/W", 1, 1, 0, 0},
- {"DMA0FI" , 9, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1FI" , 10, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 11, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 12, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 13, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 14, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_18" , 15, 4, 439, "RAZ", 0, 0, 0ull, 0ull},
- {"C0_AERI" , 19, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"CRS0_ER" , 20, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_SE" , 21, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS0_DR" , 22, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_WAKE" , 23, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_PMEI" , 24, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"C0_HPINT" , 25, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"C1_AERI" , 26, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"CRS1_ER" , 27, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_SE" , 28, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS1_DR" , 29, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_WAKE" , 30, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_PMEI" , 31, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"C1_HPINT" , 32, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B0" , 33, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_B1" , 34, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_B2" , 35, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_WI" , 36, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_BX" , 37, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B0" , 38, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B1" , 39, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B2" , 40, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_WI" , 41, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_BX" , 42, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B0" , 43, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B1" , 44, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B2" , 45, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_WI" , 46, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_BX" , 47, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B0" , 48, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B1" , 49, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B2" , 50, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_WI" , 51, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_BX" , 52, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_WF" , 53, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_WF" , 54, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_WF" , 55, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_WF" , 56, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_EXC" , 57, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"C1_EXC" , 58, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"C0_LDWN" , 59, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_LDWN" , 60, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
- {"INT_A" , 61, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 439, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO_INTA" , 63, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"RML_RTO" , 0, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"DMA0DBO" , 4, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"DMA1DBO" , 5, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"DMA2DBO" , 6, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"DMA3DBO" , 7, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 440, "RO", 1, 1, 0, 0},
- {"DMA0FI" , 9, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"DMA1FI" , 10, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"DCNT0" , 11, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"DCNT1" , 12, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"DTIME0" , 13, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"DTIME1" , 14, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_18" , 15, 4, 440, "RAZ", 0, 0, 0ull, 0ull},
- {"C0_AERI" , 19, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"CRS0_ER" , 20, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_SE" , 21, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"CRS0_DR" , 22, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_WAKE" , 23, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_PMEI" , 24, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_HPINT" , 25, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_AERI" , 26, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"CRS1_ER" , 27, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_SE" , 28, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"CRS1_DR" , 29, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_WAKE" , 30, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_PMEI" , 31, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_HPINT" , 32, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B0" , 33, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B1" , 34, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B2" , 35, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_WI" , 36, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_BX" , 37, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_B0" , 38, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_B1" , 39, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_B2" , 40, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_WI" , 41, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_BX" , 42, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_B0" , 43, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_B1" , 44, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_B2" , 45, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_WI" , 46, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_BX" , 47, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_B0" , 48, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_B1" , 49, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_B2" , 50, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_WI" , 51, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_BX" , 52, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_WF" , 53, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_WF" , 54, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_WF" , 55, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_WF" , 56, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_EXC" , 57, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_EXC" , 58, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C0_LDWN" , 59, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"C1_LDWN" , 60, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"INT_A" , 61, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 440, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO_INTA" , 63, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 441, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 442, "RO", 0, 1, 0ull, 0},
- {"TIMER" , 0, 10, 443, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 443, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 443, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 30, 444, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 30, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 31, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 32, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 33, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 444, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 444, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 444, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 2, 444, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 41, 1, 444, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 444, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 445, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 446, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 447, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 448, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 449, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 450, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 451, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 452, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 453, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 453, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 453, "RAZ", 1, 1, 0, 0},
- {"MSI_INT" , 0, 8, 454, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 454, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 454, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 455, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 455, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 456, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 456, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 456, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 457, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 457, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 457, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 458, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 458, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 458, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"NPEI" , 3, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 14, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"USB1" , 15, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 17, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
- {"ASXPCS0" , 22, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"ASXPCS1" , 23, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_27" , 24, 4, 459, "RAZ", 0, 0, 0ull, 0ull},
- {"AGL" , 28, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"LMC1" , 29, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 459, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 459, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 460, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 461, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 461, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 461, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 461, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 462, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 462, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 462, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 462, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 462, "RO", 0, 1, 1ull, 0},
- {"NPEI" , 47, 1, 462, "RO", 0, 1, 1ull, 0},
- {"RESERVED_48_63" , 48, 16, 462, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 463, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 463, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 463, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 463, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 463, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 464, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 464, "RAZ", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 464, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_51_63" , 51, 13, 464, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 465, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_1" , 0, 2, 466, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 2, 46, 466, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 466, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 466, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 467, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 468, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 468, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 469, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 469, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 470, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 470, "RO/WRSL", 0, 0, 128ull, 128ull},
- {"ISAE" , 0, 1, 471, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 471, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 471, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 471, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 471, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 471, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 471, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 471, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 471, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 471, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 471, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 472, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PI" , 8, 8, 472, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 472, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 472, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 473, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 473, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 473, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 473, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 473, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 474, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 474, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 474, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 474, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 474, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 475, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 475, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 476, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 477, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 478, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 478, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 478, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 478, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 478, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 479, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 479, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 480, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 481, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 482, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 482, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 482, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 482, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 483, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 483, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_6" , 0, 7, 484, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 7, 25, 484, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 485, "WORSL", 0, 0, 127ull, 127ull},
- {"CISP" , 0, 32, 486, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 487, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 487, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 488, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 488, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 488, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 489, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 489, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"CP" , 0, 8, 490, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 490, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 491, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 491, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 491, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 491, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 492, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 492, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 492, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 492, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 492, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 493, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 493, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 493, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 493, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 493, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 493, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 493, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 493, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 493, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 493, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 493, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 494, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 494, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 494, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 494, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 494, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 494, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 495, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 495, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 496, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 497, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 497, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 498, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 498, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 498, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 498, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 498, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 498, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 498, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 499, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 499, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 499, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 499, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 499, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 499, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 499, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 499, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 499, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 499, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 499, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 500, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 500, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 500, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 500, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 500, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 500, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 500, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 500, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 500, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 500, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 500, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 500, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 500, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 500, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 500, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 500, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 500, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 500, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 501, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MLW" , 4, 6, 501, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"ASLPMS" , 10, 2, 501, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 501, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 501, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 501, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 501, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 501, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 501, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 501, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 501, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 502, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 502, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 502, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 502, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 502, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 502, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 502, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 502, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 502, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 502, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 502, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 502, "RO", 0, 0, 0ull, 8ull},
- {"RESERVED_26_26" , 26, 1, 502, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 502, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 502, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 502, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 502, "RAZ", 1, 1, 0, 0},
- {"ABP" , 0, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 504, "R/W", 0, 0, 0ull, 0ull},
- {"PIC" , 8, 2, 504, "R/W", 0, 0, 0ull, 0ull},
- {"PCC" , 10, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 504, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 504, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 504, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 504, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 504, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 504, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 504, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 504, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 504, "RO", 0, 0, 0ull, 0ull},
- {"EMIS" , 23, 1, 504, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 504, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 504, "RAZ", 1, 1, 0, 0},
- {"CTRS" , 0, 4, 505, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 505, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 505, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 506, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 506, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 506, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 507, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 508, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 509, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 510, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 511, "RO", 0, 0, 1ull, 0ull},
- {"CV" , 16, 4, 511, "RO", 0, 0, 1ull, 0ull},
- {"NCO" , 20, 12, 511, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 512, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 512, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 512, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 513, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 513, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 513, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 513, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 514, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 514, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 514, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 514, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 514, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 514, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 514, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 514, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 514, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 515, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 515, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 515, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 516, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 516, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 516, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 516, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 516, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 517, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 517, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 517, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 517, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 517, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 517, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 518, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 519, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 520, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 521, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 522, "R/W", 0, 0, 4143ull, 4143ull},
- {"RTL" , 16, 16, 522, "R/W", 0, 0, 12429ull, 12429ull},
- {"OMR" , 0, 32, 523, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 524, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 524, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 524, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 524, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 524, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 524, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 525, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 525, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 525, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 525, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 525, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 525, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 526, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 526, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 526, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 526, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 526, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_22_24" , 22, 3, 526, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 526, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 527, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 527, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 527, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 528, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 528, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 528, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 528, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 528, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 528, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 528, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 528, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 529, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 529, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_BAR_MATCH" , 18, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 530, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 531, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 532, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 533, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 533, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 533, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 534, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 534, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 534, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 535, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 535, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 535, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 536, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 536, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 536, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 536, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 537, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 537, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 537, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 537, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 538, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 538, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 538, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 538, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 539, "RO/WRSL", 0, 0, 72ull, 72ull},
- {"HEADER_CREDITS" , 12, 8, 539, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 539, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 539, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 539, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 539, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 539, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 540, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"HEADER_CREDITS" , 12, 8, 540, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"RESERVED_20_20" , 20, 1, 540, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 540, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 540, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 541, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 541, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 541, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 541, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 541, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 542, "RO/WRSL", 0, 0, 216ull, 216ull},
- {"RESERVED_14_15" , 14, 2, 542, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 542, "RO/WRSL", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 542, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 543, "RO/WRSL", 0, 0, 56ull, 56ull},
- {"RESERVED_14_15" , 14, 2, 543, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 543, "RO/WRSL", 0, 0, 14ull, 14ull},
- {"RESERVED_26_31" , 26, 6, 543, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 544, "RO/WRSL", 0, 0, 360ull, 360ull},
- {"RESERVED_14_15" , 14, 2, 544, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 544, "RO/WRSL", 0, 0, 70ull, 70ull},
- {"RESERVED_26_31" , 26, 6, 544, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 545, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 546, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 547, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 547, "R/W", 0, 0, 128ull, 128ull},
- {"ISAE" , 0, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 548, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 548, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 548, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 548, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 548, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 549, "R/W", 0, 0, 0ull, 0ull},
- {"PI" , 8, 8, 549, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 549, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 549, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 550, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 550, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 550, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 550, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 550, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 551, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 552, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 553, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 553, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 553, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 553, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 554, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 554, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 554, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 554, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 554, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 554, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 554, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 554, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 554, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 554, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 554, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 555, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 555, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 555, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 555, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 556, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 556, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 556, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 556, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 556, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 556, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 557, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 558, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 559, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 559, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 560, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 560, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 561, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 562, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 562, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 562, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 562, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 562, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 563, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 563, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 563, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 563, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 563, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 563, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 563, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 563, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 564, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 564, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 564, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 564, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 564, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 564, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 564, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 565, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 565, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 565, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 565, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 565, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 565, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 565, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 566, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 566, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 567, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 568, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 568, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 569, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 569, "R/W", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 569, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 569, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 569, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 569, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 570, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 570, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 570, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 570, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 570, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 570, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 570, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 570, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 570, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 570, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 570, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 571, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 571, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 571, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 571, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 571, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 571, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 571, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 571, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 572, "R/W", 0, 0, 1ull, 1ull},
- {"MLW" , 4, 6, 572, "R/W", 0, 0, 8ull, 8ull},
- {"ASLPMS" , 10, 2, 572, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 572, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 572, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 572, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 572, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 572, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 572, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_23" , 22, 2, 572, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 572, "R/W", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 573, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 573, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 573, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 573, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 573, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 573, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 573, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 573, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 573, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 573, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 573, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 573, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 574, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 574, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 574, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 575, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 575, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 575, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 575, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 575, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 576, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 576, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 576, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 576, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 576, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 577, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 577, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 577, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 578, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 578, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 578, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 579, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 579, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 580, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 581, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 582, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 583, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 584, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 584, "RO", 0, 0, 1ull, 1ull},
- {"NCO" , 20, 12, 584, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 585, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 585, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 585, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 586, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 586, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 586, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 586, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 587, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 587, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 587, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 587, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 587, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 587, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 587, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 587, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 588, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 588, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 588, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 589, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 589, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 589, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 589, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 590, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 590, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 590, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 590, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 590, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 590, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 591, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 592, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 593, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 594, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 595, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 596, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 596, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 597, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 597, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 598, "R/W", 0, 0, 4143ull, 4143ull},
- {"RTL" , 16, 16, 598, "R/W", 0, 0, 12429ull, 12429ull},
- {"OMR" , 0, 32, 599, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 600, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 600, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 600, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 600, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 600, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 601, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 601, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 601, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 601, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 601, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 601, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 602, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 602, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 602, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 602, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 602, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_22_24" , 22, 3, 602, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 602, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 603, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 603, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 603, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 603, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 603, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 604, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 604, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 604, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 604, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 604, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 604, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 604, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 604, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 605, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 605, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_BAR_MATCH" , 18, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 606, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 607, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 608, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 609, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 609, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 609, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 610, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 610, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 610, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 611, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 611, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 611, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 612, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 612, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 612, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 612, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 613, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 613, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 613, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 613, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 614, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 614, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 614, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 614, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 615, "R/W", 0, 0, 72ull, 72ull},
- {"HEADER_CREDITS" , 12, 8, 615, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 615, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 615, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 615, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 615, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 615, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 616, "R/W", 0, 0, 4ull, 4ull},
- {"HEADER_CREDITS" , 12, 8, 616, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_20_20" , 20, 1, 616, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 616, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 616, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 617, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 617, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_20_20" , 20, 1, 617, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 617, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 617, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 618, "R/W", 0, 0, 216ull, 216ull},
- {"RESERVED_14_15" , 14, 2, 618, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 618, "R/W", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 618, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 619, "R/W", 0, 0, 56ull, 56ull},
- {"RESERVED_14_15" , 14, 2, 619, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 619, "R/W", 0, 0, 14ull, 14ull},
- {"RESERVED_26_31" , 26, 6, 619, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 620, "R/W", 0, 0, 360ull, 360ull},
- {"RESERVED_14_15" , 14, 2, 620, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 620, "R/W", 0, 0, 70ull, 70ull},
- {"RESERVED_26_31" , 26, 6, 620, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 621, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 622, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 623, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 623, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 623, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 623, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 623, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 623, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 623, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 623, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 623, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 624, "RAZ", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 624, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 624, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 624, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 624, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 624, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 625, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 625, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 625, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 625, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 625, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 625, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 625, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 625, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 625, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 626, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 626, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 626, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 626, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 626, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 627, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_12_63" , 12, 52, 627, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 628, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 629, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 629, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 630, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 630, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 631, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 631, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 631, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 632, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 632, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 632, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 632, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 632, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 632, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 633, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 633, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 633, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 633, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 633, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 633, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 633, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 634, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 634, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 634, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 634, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 634, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 634, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 634, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 635, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 635, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 635, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 636, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 636, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 636, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 636, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 636, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 636, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 636, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 637, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 637, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 637, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 637, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 637, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 637, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 637, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 638, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 638, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 638, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 638, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 639, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 639, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 639, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 639, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 639, "RAZ", 1, 1, 0, 0},
- {"L0SYNC" , 0, 1, 640, "RO", 0, 0, 0ull, 1ull},
- {"L1SYNC" , 1, 1, 640, "RO", 0, 0, 0ull, 1ull},
- {"L2SYNC" , 2, 1, 640, "RO", 0, 0, 0ull, 1ull},
- {"L3SYNC" , 3, 1, 640, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_4_10" , 4, 7, 640, "RAZ", 1, 1, 0, 0},
- {"PATTST" , 11, 1, 640, "RO", 0, 0, 0ull, 0ull},
- {"ALIGND" , 12, 1, 640, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_63" , 13, 51, 640, "RAZ", 1, 1, 0, 0},
- {"BIST_STATUS" , 0, 1, 641, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 641, "RAZ", 1, 1, 0, 0},
- {"BITLCK0" , 0, 1, 642, "RO", 0, 1, 0ull, 0},
- {"BITLCK1" , 1, 1, 642, "RO", 0, 1, 0ull, 0},
- {"BITLCK2" , 2, 1, 642, "RO", 0, 1, 0ull, 0},
- {"BITLCK3" , 3, 1, 642, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 642, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 643, "RAZ", 1, 1, 0, 0},
- {"SPD" , 2, 4, 643, "RO", 0, 0, 0ull, 0ull},
- {"SPDSEL0" , 6, 1, 643, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_10" , 7, 4, 643, "RAZ", 1, 1, 0, 0},
- {"LO_PWR" , 11, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 643, "RAZ", 1, 1, 0, 0},
- {"SPDSEL1" , 13, 1, 643, "RO", 0, 0, 1ull, 1ull},
- {"LOOPBCK1" , 14, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 643, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 643, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 644, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 644, "RAZ", 1, 1, 0, 0},
- {"TXFLT_EN" , 0, 1, 645, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 1, 1, 645, "R/W", 0, 0, 0ull, 1ull},
- {"RXSYNBAD_EN" , 2, 1, 645, "R/W", 0, 0, 0ull, 1ull},
- {"BITLCKLS_EN" , 3, 1, 645, "R/W", 0, 0, 0ull, 1ull},
- {"SYNLOS_EN" , 4, 1, 645, "R/W", 0, 0, 0ull, 1ull},
- {"ALGNLOS_EN" , 5, 1, 645, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 645, "RAZ", 1, 1, 0, 0},
- {"TXFLT" , 0, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 1, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXSYNBAD" , 2, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"BITLCKLS" , 3, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNLOS" , 4, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALGNLOS" , 5, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 646, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 647, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 647, "R/W1C", 0, 0, 0ull, 0ull},
- {"DROP_LN" , 4, 2, 647, "R/W", 0, 0, 0ull, 0ull},
- {"ENC_MODE" , 6, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 647, "RAZ", 1, 1, 0, 0},
- {"GMXENO" , 0, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"XAUI" , 1, 1, 648, "RO", 1, 1, 0, 0},
- {"RX_SWAP" , 2, 1, 648, "R/W", 0, 1, 0ull, 0},
- {"TX_SWAP" , 3, 1, 648, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 648, "RAZ", 1, 1, 0, 0},
- {"SYNC0ST" , 0, 4, 649, "RO", 0, 1, 0ull, 0},
- {"SYNC1ST" , 4, 4, 649, "RO", 0, 1, 0ull, 0},
- {"SYNC2ST" , 8, 4, 649, "RO", 0, 1, 0ull, 0},
- {"SYNC3ST" , 12, 4, 649, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 649, "RAZ", 1, 1, 0, 0},
- {"TENGB" , 0, 1, 650, "RO", 0, 0, 1ull, 1ull},
- {"TENPASST" , 1, 1, 650, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 650, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 651, "RAZ", 1, 1, 0, 0},
- {"LPABLE" , 1, 1, 651, "RO", 0, 0, 1ull, 1ull},
- {"RCV_LNK" , 2, 1, 651, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_3_6" , 3, 4, 651, "RAZ", 1, 1, 0, 0},
- {"FLT" , 7, 1, 651, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 651, "RAZ", 1, 1, 0, 0},
- {"TENGB_R" , 0, 1, 652, "RO", 0, 0, 0ull, 0ull},
- {"TENGB_X" , 1, 1, 652, "RO", 0, 0, 1ull, 1ull},
- {"TENGB_W" , 2, 1, 652, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_9" , 3, 7, 652, "RAZ", 1, 1, 0, 0},
- {"RCVFLT" , 10, 1, 652, "RC", 0, 0, 0ull, 0ull},
- {"XMTFLT" , 11, 1, 652, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 652, "RAZ", 1, 1, 0, 0},
- {"DEV" , 14, 2, 652, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_16_63" , 16, 48, 652, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 653, "RAZ", 1, 1, 0, 0},
- {"TX_ST" , 0, 3, 654, "RO", 0, 1, 0ull, 0},
- {"RX_ST" , 3, 2, 654, "RO", 0, 1, 0ull, 0},
- {"ALGN_ST" , 5, 3, 654, "RO", 0, 1, 0ull, 0},
- {"RXBAD" , 8, 1, 654, "RO", 0, 0, 0ull, 0ull},
- {"SYN0BAD" , 9, 1, 654, "RO", 0, 0, 0ull, 0ull},
- {"SYN1BAD" , 10, 1, 654, "RO", 0, 0, 0ull, 0ull},
- {"SYN2BAD" , 11, 1, 654, "RO", 0, 0, 0ull, 0ull},
- {"SYN3BAD" , 12, 1, 654, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 654, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA4" , 3, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 4, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 5, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 6, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 7, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 8, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"PTLP_OR" , 9, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"NTLP_OR" , 10, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"CTLP_OR" , 11, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 655, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"RSL_P2E" , 6, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 7, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"DBG_P2E" , 8, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"E2P_RSL" , 9, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 10, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 11, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 12, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"CTO_P2E" , 13, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 656, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 657, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 657, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 658, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 658, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 659, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 659, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 660, "RAZ", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 660, "RAZ", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"LANE_SWP" , 12, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"QLM_CFG" , 13, 2, 660, "RO", 1, 1, 0, 0},
- {"PBUS" , 15, 8, 660, "RO", 1, 1, 0, 0},
- {"DNUM" , 23, 5, 660, "RO", 1, 1, 0, 0},
- {"RESERVED_28_63" , 28, 36, 660, "RAZ", 1, 1, 0, 0},
- {"PCIERST" , 0, 1, 661, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 661, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 662, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 663, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 664, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 664, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 664, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 664, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 664, "RO", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 665, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 665, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 666, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_38" , 0, 39, 667, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 39, 25, 667, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 668, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 668, "R/W", 0, 1, 4503599627370495ull, 0},
- {"RESERVED_0_11" , 0, 12, 669, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 669, "R/W", 0, 1, 4503599627370495ull, 0},
- {"NPEI_P" , 0, 5, 670, "R/W", 0, 0, 2ull, 2ull},
- {"NPEI_NP" , 5, 5, 670, "R/W", 0, 0, 2ull, 2ull},
- {"NPEI_CPL" , 10, 5, 670, "R/W", 0, 0, 2ull, 2ull},
- {"PESC_P" , 15, 5, 670, "R/W", 0, 0, 2ull, 2ull},
- {"PESC_NP" , 20, 5, 670, "R/W", 0, 0, 2ull, 2ull},
- {"PESC_CPL" , 25, 5, 670, "R/W", 0, 0, 2ull, 2ull},
- {"PEAI_PPF" , 30, 8, 670, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_38_63" , 38, 26, 670, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 18, 671, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 671, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 672, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 672, "RAZ", 1, 1, 0, 0},
- {"MAP0" , 0, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 673, "R/W", 0, 0, 0ull, 0ull},
- {"MAP0" , 0, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 674, "R/W", 0, 0, 0ull, 0ull},
- {"MINLEN" , 0, 16, 675, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 675, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 675, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 676, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 676, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 676, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 676, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 677, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 677, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 677, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 20, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 677, "RAZ", 1, 1, 0, 0},
- {"DSA_GRP_SID" , 24, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SCMD" , 25, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_TVID" , 26, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 677, "RAZ", 1, 1, 0, 0},
- {"PRI" , 0, 6, 678, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 678, "RAZ", 1, 1, 0, 0},
- {"QOS" , 8, 3, 678, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 678, "RAZ", 1, 1, 0, 0},
- {"UP_QOS" , 12, 1, 678, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_13_63" , 13, 51, 678, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 679, "RAZ", 1, 1, 0, 0},
- {"BCKPRS" , 2, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 679, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 680, "RAZ", 1, 1, 0, 0},
- {"BCKPRS" , 2, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 680, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 681, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 681, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 682, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 682, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 682, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_EN" , 10, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"HIGIG_EN" , 11, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"CRC_EN" , 12, 1, 682, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 682, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VSEL" , 19, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 682, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 682, "R/W", 0, 0, 0ull, 0ull},
- {"HG_QOS" , 27, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT" , 28, 4, 682, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 682, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 682, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 682, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 682, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 682, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 682, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 682, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_63" , 53, 11, 682, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 683, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 683, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 683, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 683, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 683, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 683, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 683, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 683, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 683, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 684, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 684, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 685, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 685, "RAZ", 1, 1, 0, 0},
- {"QOS1" , 4, 3, 685, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 685, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 686, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 686, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 686, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 686, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 686, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 686, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 686, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 686, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 686, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 687, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 687, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 688, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 688, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 689, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 689, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 690, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 690, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 691, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 691, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 692, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 692, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 693, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 693, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 694, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 694, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 695, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 695, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 696, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 696, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 697, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 697, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 698, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 698, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 699, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 699, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 700, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 700, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 701, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 701, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 702, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 702, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 703, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 703, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 704, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 704, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 705, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 705, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 705, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 706, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 706, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 706, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 707, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 707, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 708, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 708, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 709, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 709, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 709, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 709, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 710, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 710, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 710, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 710, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 710, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 711, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 711, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 711, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 711, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 712, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 712, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 712, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 712, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 712, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 712, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 712, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 712, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 713, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 713, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 713, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 713, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 714, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 714, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 714, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 714, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 714, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 715, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 716, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 716, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 716, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 716, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 716, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 717, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 718, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 718, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 718, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 718, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 718, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 718, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 718, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 718, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 718, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 718, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 718, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 718, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 718, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 719, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 719, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 719, "RO", 1, 0, 0, 0ull},
- {"RESERVED_54_63" , 54, 10, 719, "RAZ", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 720, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 720, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 720, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 720, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 720, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 720, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 720, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 720, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 720, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 720, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 720, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 720, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 720, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 721, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 721, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 721, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 721, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 721, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 721, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 722, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 722, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 722, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 722, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 6, 1, 722, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 722, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 722, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 722, "RO", 1, 0, 0, 0ull},
- {"RESERVED_29_63" , 29, 35, 722, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 723, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 723, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 723, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 723, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 724, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 724, "R/W", 1, 0, 0, 0ull},
- {"BP_PORT" , 10, 6, 724, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_52" , 16, 37, 724, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 724, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 61, 1, 724, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_62_63" , 62, 2, 724, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 725, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 725, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_10_52" , 10, 43, 725, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 725, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 725, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 726, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 726, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 726, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 726, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 726, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 727, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 727, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 727, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 727, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 728, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 728, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 728, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 728, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 728, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 728, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 728, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 728, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 728, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 729, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 729, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 729, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 729, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 729, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 730, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 730, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 730, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 730, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 730, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 730, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 8, 730, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 730, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 730, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 730, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 730, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 3, 730, "RO", 1, 0, 0, 0ull},
- {"OUT_DAT" , 32, 1, 730, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 730, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 730, "RO", 1, 0, 0, 0ull},
- {"RESERVED_35_63" , 35, 29, 730, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 731, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 731, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 731, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 731, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 732, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 733, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 734, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 735, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 736, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE1" , 4, 4, 736, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE2" , 8, 4, 736, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE3" , 12, 4, 736, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE4" , 16, 4, 736, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE5" , 20, 4, 736, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE6" , 24, 4, 736, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE7" , 28, 4, 736, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE8" , 32, 4, 736, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE9" , 36, 4, 736, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_40_63" , 40, 24, 736, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 10, 737, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 737, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 738, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 739, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 739, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 740, "R/W", 0, 0, 2ull, 2ull},
- {"MODE1" , 3, 3, 740, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 740, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 741, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 741, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 741, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 741, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 742, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 742, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 743, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 743, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 743, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 744, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 744, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 744, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 1, 745, "RO", 0, 0, 0ull, 0ull},
- {"PEND" , 1, 1, 745, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 2, 1, 745, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 3, 1, 745, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 4, 1, 745, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 5, 1, 745, "RO", 0, 0, 0ull, 0ull},
- {"NBT0" , 6, 1, 745, "RO", 0, 0, 0ull, 0ull},
- {"NBT1" , 7, 1, 745, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 8, 1, 745, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 745, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 4, 745, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 745, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 746, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 746, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 747, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 747, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 747, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 747, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 747, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 747, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 747, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 747, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 747, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 747, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 747, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 747, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 747, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 748, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 748, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 748, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 749, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 749, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 750, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 750, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 751, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 751, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 752, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 752, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 753, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 753, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 10, 754, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 754, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 755, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_10_63" , 10, 54, 755, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 756, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 756, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 757, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 757, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 757, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 757, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 757, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 757, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 757, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 757, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 757, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 757, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 758, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 758, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 758, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 758, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 758, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 9, 759, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 759, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 9, 759, "R/W", 0, 1, 511ull, 0},
- {"RESERVED_21_23" , 21, 3, 759, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 10, 759, "RO", 0, 1, 503ull, 0},
- {"RESERVED_34_35" , 34, 2, 759, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 36, 10, 759, "RO", 0, 1, 0ull, 0},
- {"RESERVED_46_47" , 46, 2, 759, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 48, 10, 759, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 759, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 760, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 760, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 761, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 761, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 762, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 762, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 763, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 763, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 763, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 10, 764, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_11" , 10, 2, 764, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 12, 10, 764, "RO", 0, 1, 0ull, 0},
- {"RESERVED_22_23" , 22, 2, 764, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 24, 4, 764, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 764, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 765, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 765, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 765, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 765, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 765, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 9, 766, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 766, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 9, 766, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_23" , 21, 3, 766, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 766, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 766, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 766, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 767, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 767, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 768, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 769, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 770, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 771, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 771, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 771, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 771, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 771, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 772, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 772, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 772, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 772, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 772, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 773, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 773, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 773, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 773, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 774, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 774, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 774, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 774, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 774, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 774, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 774, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 774, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 774, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 774, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 775, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 776, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 776, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 776, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 777, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 777, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 777, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 777, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 777, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 777, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 777, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 778, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 778, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 779, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 780, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 781, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 782, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 782, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 782, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 782, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 782, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 782, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 782, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 782, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 782, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 782, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 782, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 782, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 782, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 782, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 782, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 782, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 782, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 782, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 783, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 783, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 783, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 784, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 784, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 785, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 785, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 785, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 786, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 786, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 786, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 786, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 786, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 786, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 786, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 787, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 787, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 788, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 788, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 789, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 789, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 790, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 790, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 790, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 791, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 791, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 791, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 792, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 792, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 792, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 792, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 792, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 792, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 792, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 793, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 793, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 793, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 793, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 793, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 793, "RAZ", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 793, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 793, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 793, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 793, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 794, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 794, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 794, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 794, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 794, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 794, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 795, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 795, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 796, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 796, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 796, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 796, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 797, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 797, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 797, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 797, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 798, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 798, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 798, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 798, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 798, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 798, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 799, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 799, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 799, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 800, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 800, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 800, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 800, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 800, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 801, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 801, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 801, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 802, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 802, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 802, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 802, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 802, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 802, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 803, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 803, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 803, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 803, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 804, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 805, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 805, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 805, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 805, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 806, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 806, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 807, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 807, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 807, "RAZ", 1, 1, 0, 0},
- {"TDF0" , 0, 1, 808, "RO", 0, 0, 0ull, 0ull},
- {"TDF1" , 1, 1, 808, "RO", 0, 0, 0ull, 0ull},
- {"TCF" , 2, 1, 808, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 808, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 809, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 809, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 809, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 809, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 809, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 809, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 809, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 809, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 809, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 809, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 809, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 809, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 810, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 810, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 810, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 811, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 811, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 811, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 811, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 811, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 812, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 812, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 813, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 813, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 814, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 814, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 815, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 815, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 815, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 815, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 815, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 815, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 815, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 815, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 815, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 815, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 815, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 815, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 816, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 816, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 816, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 816, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 816, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 816, "RAZ", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 817, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 817, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 817, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 817, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 817, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 818, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 819, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 819, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 820, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 820, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 821, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 821, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 822, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 822, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 822, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 822, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 822, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 822, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 822, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 822, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 822, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 822, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 822, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 822, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 823, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 823, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 824, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 824, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 825, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 825, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 826, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 827, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 827, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 827, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 827, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 827, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 827, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 827, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 827, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 827, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 827, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 827, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 827, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 828, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 828, "RAZ", 0, 0, 0ull, 0ull},
- {"INEPINT" , 0, 16, 829, "RO", 0, 0, 0ull, 0ull},
- {"OUTEPINT" , 16, 16, 829, "RO", 0, 0, 0ull, 0ull},
- {"INEPMSK" , 0, 16, 830, "R/W", 0, 0, 0ull, 0ull},
- {"OUTEPMSK" , 16, 16, 830, "R/W", 0, 0, 0ull, 0ull},
- {"DEVSPD" , 0, 2, 831, "R/W", 0, 0, 0ull, 0ull},
- {"NZSTSOUTHSHK" , 2, 1, 831, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 831, "RAZ", 1, 1, 0, 0},
- {"DEVADDR" , 4, 7, 831, "R/W", 0, 0, 0ull, 0ull},
- {"PERFRINT" , 11, 2, 831, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_17" , 13, 5, 831, "RAZ", 1, 1, 0, 0},
- {"EPMISCNT" , 18, 5, 831, "R/W", 0, 0, 8ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 831, "RAZ", 1, 1, 0, 0},
- {"RMTWKUPSIG" , 0, 1, 832, "R/W", 0, 0, 0ull, 0ull},
- {"SFTDISCON" , 1, 1, 832, "R/W", 0, 0, 0ull, 0ull},
- {"GNPINNAKSTS" , 2, 1, 832, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKSTS" , 3, 1, 832, "RO", 0, 0, 0ull, 0ull},
- {"TSTCTL" , 4, 3, 832, "R/W", 0, 0, 0ull, 0ull},
- {"SGNPINNAK" , 7, 1, 832, "WO", 0, 0, 0ull, 0ull},
- {"CGNPINNAK" , 8, 1, 832, "WO", 0, 0, 0ull, 0ull},
- {"SGOUTNAK" , 9, 1, 832, "WO", 0, 0, 0ull, 0ull},
- {"CGOUTNAK" , 10, 1, 832, "WO", 0, 0, 0ull, 0ull},
- {"PWRONPRGDONE" , 11, 1, 832, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 832, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 833, "R/W", 0, 0, 0ull, 0ull},
- {"NEXTEP" , 11, 4, 833, "R/W", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 833, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 833, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 833, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 833, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 833, "RAZ", 1, 1, 0, 0},
- {"STALL" , 21, 1, 833, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 22, 4, 833, "R/W", 0, 0, 0ull, 0ull},
- {"CNAK" , 26, 1, 833, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 833, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 833, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 833, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 833, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 833, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMEOUT" , 3, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMP" , 4, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNEPMIS" , 5, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
- {"INEPNAKEFF" , 6, 1, 834, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 834, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"TIMEOUTMSK" , 3, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMPMSK" , 4, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNEPMISMSK" , 5, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"INEPNAKEFFMSK" , 6, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 835, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 836, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 836, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 836, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 836, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 837, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_14" , 11, 4, 837, "RAZ", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 837, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 837, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 837, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 837, "R/W", 0, 0, 0ull, 0ull},
- {"SNP" , 20, 1, 837, "R/W", 0, 0, 0ull, 0ull},
- {"STALL" , 21, 1, 837, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_25" , 22, 4, 837, "RAZ", 1, 1, 0, 0},
- {"CNAK" , 26, 1, 837, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 837, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 837, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 837, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 837, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 837, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 838, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 838, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 838, "R/W1C", 0, 0, 0ull, 0ull},
- {"SETUP" , 3, 1, 838, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDIS" , 4, 1, 838, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 838, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"SETUPMSK" , 3, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDISMSK" , 4, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 839, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 840, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 840, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 840, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 840, "RAZ", 1, 1, 0, 0},
- {"DPTXFSTADDR" , 0, 16, 841, "RO", 0, 0, 0ull, 0ull},
- {"DPTXFSIZE" , 16, 16, 841, "RO", 0, 0, 1896ull, 1896ull},
- {"SUSPSTS" , 0, 1, 842, "RO", 0, 0, 0ull, 0ull},
- {"ENUMSPD" , 1, 2, 842, "RO", 0, 0, 0ull, 0ull},
- {"ERRTICERR" , 3, 1, 842, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 842, "RAZ", 1, 1, 0, 0},
- {"SOFFN" , 8, 14, 842, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 842, "RAZ", 1, 1, 0, 0},
- {"INTKNWPTR" , 0, 5, 843, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 843, "RAZ", 1, 1, 0, 0},
- {"WRAPBIT" , 7, 1, 843, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 8, 24, 843, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 844, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 845, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 846, "RO", 0, 0, 0ull, 0ull},
- {"GLBLINTRMSK" , 0, 1, 847, "R/W", 0, 0, 0ull, 1ull},
- {"HBSTLEN" , 1, 4, 847, "R/W", 0, 0, 0ull, 0ull},
- {"DMAEN" , 5, 1, 847, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 847, "RAZ", 1, 1, 0, 0},
- {"NPTXFEMPLVL" , 7, 1, 847, "R/W", 0, 0, 0ull, 1ull},
- {"PTXFEMPLVL" , 8, 1, 847, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_31" , 9, 23, 847, "RAZ", 1, 1, 0, 0},
- {"EPDIR" , 0, 32, 848, "RO", 0, 0, 0ull, 0ull},
- {"OTGMODE" , 0, 3, 849, "RO", 0, 0, 2ull, 2ull},
- {"OTGARCH" , 3, 2, 849, "RO", 0, 0, 1ull, 1ull},
- {"SINGPNT" , 5, 1, 849, "RO", 0, 0, 0ull, 0ull},
- {"HSPHYTYPE" , 6, 2, 849, "RO", 0, 0, 1ull, 1ull},
- {"FSPHYTYPE" , 8, 2, 849, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVEPS" , 10, 4, 849, "RO", 0, 0, 4ull, 4ull},
- {"NUMHSTCHNL" , 14, 4, 849, "RO", 0, 0, 7ull, 7ull},
- {"PERIOSUPPORT" , 18, 1, 849, "RO", 0, 0, 1ull, 1ull},
- {"DYNFIFOSIZING" , 19, 1, 849, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_20_21" , 20, 2, 849, "RAZ", 1, 1, 0, 0},
- {"NPTXQDEPTH" , 22, 2, 849, "RO", 0, 0, 2ull, 2ull},
- {"PTXQDEPTH" , 24, 2, 849, "RO", 0, 0, 2ull, 2ull},
- {"TKNQDEPTH" , 26, 5, 849, "RO", 0, 0, 30ull, 30ull},
- {"RESERVED_31_31" , 31, 1, 849, "RAZ", 1, 1, 0, 0},
- {"XFERSIZEWIDTH" , 0, 4, 850, "RO", 0, 0, 8ull, 8ull},
- {"PKTSIZEWIDTH" , 4, 3, 850, "RO", 0, 0, 6ull, 6ull},
- {"OTGEN" , 7, 1, 850, "RO", 0, 0, 1ull, 1ull},
- {"I2C_SELECTION" , 8, 1, 850, "RO", 0, 0, 0ull, 0ull},
- {"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 850, "RO", 0, 0, 0ull, 0ull},
- {"OPTFEATURE" , 10, 1, 850, "RO", 0, 0, 1ull, 1ull},
- {"RSTTYPE" , 11, 1, 850, "RO", 0, 0, 0ull, 0ull},
- {"AHBPHYSYNC" , 12, 1, 850, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 850, "RAZ", 1, 1, 0, 0},
- {"DFIFODEPTH" , 16, 16, 850, "RO", 0, 0, 1824ull, 1824ull},
- {"NUMDEVPERIOEPS" , 0, 4, 851, "RO", 0, 0, 4ull, 4ull},
- {"ENABLEPWROPT" , 4, 1, 851, "RO", 0, 0, 0ull, 0ull},
- {"AHBFREQ" , 5, 1, 851, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_13" , 6, 8, 851, "RAZ", 1, 1, 0, 0},
- {"PHYDATAWIDTH" , 14, 2, 851, "RO", 0, 0, 1ull, 1ull},
- {"NUMCTLEPS" , 16, 4, 851, "RO", 0, 0, 4ull, 4ull},
- {"IDDGFLTR" , 20, 1, 851, "RO", 0, 0, 1ull, 1ull},
- {"VBUSVALIDFLTR" , 21, 1, 851, "RO", 0, 0, 1ull, 1ull},
- {"AVALIDFLTR" , 22, 1, 851, "RO", 0, 0, 0ull, 0ull},
- {"BVALIDFLTR" , 23, 1, 851, "RO", 0, 0, 0ull, 0ull},
- {"SESSENDFLTR" , 24, 1, 851, "RO", 0, 0, 0ull, 0ull},
- {"ENDEDTRFIFO" , 25, 1, 851, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVMODINEND" , 26, 4, 851, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_30_31" , 30, 2, 851, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 852, "RAZ", 1, 1, 0, 0},
- {"MODEMISMSK" , 1, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"OTGINTMSK" , 2, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"SOFMSK" , 3, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"RXFLVLMSK" , 4, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"NPTXFEMPMSK" , 5, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"GINNAKEFFMSK" , 6, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFFMSK" , 7, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"ULPICKINTMSK" , 8, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"ERLYSUSPMSK" , 10, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"USBSUSPMSK" , 11, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"USBRSTMSK" , 12, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"ENUMDONEMSK" , 13, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"ISOOUTDROPMSK" , 14, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"EOPFMSK" , 15, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 852, "RAZ", 1, 1, 0, 0},
- {"EPMISMSK" , 17, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"INEPINTMSK" , 18, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"OEPINTMSK" , 19, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPISOINMSK" , 20, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPLPMSK" , 21, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"FETSUSPMSK" , 22, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 852, "RAZ", 1, 1, 0, 0},
- {"PRTINTMSK" , 24, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"HCHINTMSK" , 25, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"PTXFEMPMSK" , 26, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 852, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNGMSK" , 28, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"DISCONNINTMSK" , 29, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"SESSREQINTMSK" , 30, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"WKUPINTMSK" , 31, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"CURMOD" , 0, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"MODEMIS" , 1, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"OTGINT" , 2, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"SOF" , 3, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXFLVL" , 4, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"NPTXFEMP" , 5, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"GINNAKEFF" , 6, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFF" , 7, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"ULPICKINT" , 8, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"ERLYSUSP" , 10, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBSUSP" , 11, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBRST" , 12, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENUMDONE" , 13, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"ISOOUTDROP" , 14, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"EOPF" , 15, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 853, "RAZ", 1, 1, 0, 0},
- {"EPMIS" , 17, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"IEPINT" , 18, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"OEPINT" , 19, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"INCOMPISOIN" , 20, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"INCOMPLP" , 21, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"FETSUSP" , 22, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 853, "RAZ", 1, 1, 0, 0},
- {"PRTINT" , 24, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"HCHINT" , 25, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"PTXFEMP" , 26, 1, 853, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 853, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNG" , 28, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"DISCONNINT" , 29, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"SESSREQINT" , 30, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"WKUPINT" , 31, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"NPTXFSTADDR" , 0, 16, 854, "R/W", 0, 0, 1824ull, 456ull},
- {"NPTXFDEP" , 16, 16, 854, "R/W", 0, 0, 1824ull, 912ull},
- {"NPTXFSPCAVAIL" , 0, 16, 855, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQSPCAVAIL" , 16, 8, 855, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQTOP" , 24, 7, 855, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 855, "RAZ", 1, 1, 0, 0},
- {"SESREQSCS" , 0, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"SESREQ" , 1, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 856, "RAZ", 1, 1, 0, 0},
- {"HSTNEGSCS" , 8, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"HNPREQ" , 9, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"HSTSETHNPEN" , 10, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"DEVHNPEN" , 11, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 856, "RAZ", 1, 1, 0, 0},
- {"CONIDSTS" , 16, 1, 856, "RO", 1, 1, 0, 0},
- {"DBNCTIME" , 17, 1, 856, "RO", 0, 0, 0ull, 0ull},
- {"ASESVLD" , 18, 1, 856, "RO", 1, 1, 0, 0},
- {"BSESVLD" , 19, 1, 856, "RO", 1, 1, 0, 0},
- {"RESERVED_20_31" , 20, 12, 856, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 857, "RAZ", 1, 1, 0, 0},
- {"SESENDDET" , 2, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 857, "RAZ", 1, 1, 0, 0},
- {"SESREQSUCSTSCHNG" , 8, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSTNEGSUCSTSCHNG" , 9, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_16" , 10, 7, 857, "RAZ", 1, 1, 0, 0},
- {"HSTNEGDET" , 17, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
- {"ADEVTOUTCHG" , 18, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBNCEDONE" , 19, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 857, "RAZ", 1, 1, 0, 0},
- {"CSFTRST" , 0, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"HSFTRST" , 1, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"FRMCNTRRST" , 2, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNQFLSH" , 3, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"RXFFLSH" , 4, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"TXFFLSH" , 5, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 6, 5, 858, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_29" , 11, 19, 858, "RAZ", 1, 1, 0, 0},
- {"DMAREQ" , 30, 1, 858, "RO", 0, 0, 0ull, 0ull},
- {"AHBIDLE" , 31, 1, 858, "RO", 0, 0, 1ull, 1ull},
- {"RXFDEP" , 0, 16, 859, "R/W", 0, 0, 1824ull, 456ull},
- {"RESERVED_16_31" , 16, 16, 859, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 860, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 860, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 860, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 860, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 860, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 860, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 861, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 861, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 861, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 861, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 861, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 862, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 862, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 862, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 862, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 862, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 862, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 863, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 863, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 863, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 863, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 863, "RAZ", 1, 1, 0, 0},
- {"SYNOPSYSID" , 0, 32, 864, "RO", 1, 1, 0, 0},
- {"TOUTCAL" , 0, 3, 865, "R/W", 0, 0, 0ull, 0ull},
- {"PHYIF" , 3, 1, 865, "RO", 0, 0, 1ull, 1ull},
- {"ULPI_UTMI_SEL" , 4, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"FSINTF" , 5, 1, 865, "WO", 0, 0, 0ull, 0ull},
- {"PHYSEL" , 6, 1, 865, "WO", 0, 0, 0ull, 0ull},
- {"DDRSEL" , 7, 1, 865, "R/W", 0, 0, 0ull, 0ull},
- {"SRPCAP" , 8, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"HNPCAP" , 9, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"USBTRDTIM" , 10, 4, 865, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_14_14" , 14, 1, 865, "RAZ", 1, 1, 0, 0},
- {"PHYLPWRCLKSEL" , 15, 1, 865, "R/W", 0, 0, 0ull, 0ull},
- {"OTGI2CSEL" , 16, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 865, "RAZ", 1, 1, 0, 0},
- {"HAINT" , 0, 16, 866, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 866, "RAZ", 1, 1, 0, 0},
- {"HAINTMSK" , 0, 16, 867, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 867, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 868, "R/W", 0, 0, 0ull, 0ull},
- {"EPNUM" , 11, 4, 868, "R/W", 0, 0, 0ull, 0ull},
- {"EPDIR" , 15, 1, 868, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 868, "RAZ", 1, 1, 0, 0},
- {"LSPDDEV" , 17, 1, 868, "R/W", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 868, "R/W", 0, 0, 0ull, 0ull},
- {"EC" , 20, 2, 868, "R/W", 0, 0, 0ull, 0ull},
- {"DEVADDR" , 22, 7, 868, "R/W", 0, 0, 0ull, 0ull},
- {"ODDFRM" , 29, 1, 868, "R/W", 0, 0, 0ull, 0ull},
- {"CHDIS" , 30, 1, 868, "R/W", 0, 0, 0ull, 0ull},
- {"CHENA" , 31, 1, 868, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSPCLKSEL" , 0, 2, 869, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSSUPP" , 2, 1, 869, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 869, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPL" , 0, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"CHHLTD" , 1, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"STALL" , 3, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAK" , 4, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACK" , 5, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"NYET" , 6, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"XACTERR" , 7, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"BBLERR" , 8, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMOVRUN" , 9, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATATGLERR" , 10, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 870, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"CHHLTDMSK" , 1, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"STALLMSK" , 3, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"NAKMSK" , 4, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"ACKMSK" , 5, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"NYETMSK" , 6, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"XACTERRMSK" , 7, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"BBLERRMSK" , 8, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"FRMOVRUNMSK" , 9, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"DATATGLERRMSK" , 10, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 871, "RAZ", 1, 1, 0, 0},
- {"PRTADDR" , 0, 7, 872, "R/W", 0, 0, 0ull, 0ull},
- {"HUBADDR" , 7, 7, 872, "R/W", 0, 0, 0ull, 0ull},
- {"XACTPOS" , 14, 2, 872, "R/W", 0, 0, 0ull, 0ull},
- {"COMPSPLT" , 16, 1, 872, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_30" , 17, 14, 872, "RAZ", 1, 1, 0, 0},
- {"SPLTENA" , 31, 1, 872, "R/W", 0, 0, 0ull, 0ull},
- {"XFERSIZE" , 0, 19, 873, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 873, "R/W", 0, 0, 0ull, 0ull},
- {"PID" , 29, 2, 873, "R/W", 0, 0, 0ull, 0ull},
- {"DOPNG" , 31, 1, 873, "R/W", 0, 0, 0ull, 0ull},
- {"FRINT" , 0, 16, 874, "R/W", 0, 0, 2959ull, 3750ull},
- {"RESERVED_16_31" , 16, 16, 874, "RAZ", 1, 1, 0, 0},
- {"FRNUM" , 0, 16, 875, "RO", 0, 0, 16383ull, 0ull},
- {"FRREM" , 16, 16, 875, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNSTS" , 0, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNDET" , 1, 1, 876, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENA" , 2, 1, 876, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENCHNG" , 3, 1, 876, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRACT" , 4, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRCHNG" , 5, 1, 876, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTRES" , 6, 1, 876, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSUSP" , 7, 1, 876, "R/W", 0, 0, 0ull, 0ull},
- {"PRTRST" , 8, 1, 876, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 876, "RAZ", 1, 1, 0, 0},
- {"PRTLNSTS" , 10, 2, 876, "RO", 0, 0, 0ull, 0ull},
- {"PRTPWR" , 12, 1, 876, "R/W", 0, 0, 0ull, 0ull},
- {"PRTTSTCTL" , 13, 4, 876, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSPD" , 17, 2, 876, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 876, "RAZ", 1, 1, 0, 0},
- {"PTXFSTADDR" , 0, 16, 877, "R/W", 0, 0, 3648ull, 912ull},
- {"PTXFSIZE" , 16, 16, 877, "R/W", 0, 0, 256ull, 456ull},
- {"PTXFSPCAVAIL" , 0, 16, 878, "RO", 0, 0, 0ull, 0ull},
- {"PTXQSPCAVAIL" , 16, 8, 878, "RO", 0, 0, 0ull, 0ull},
- {"PTXQTOP" , 24, 8, 878, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 32, 879, "R/W", 0, 0, 0ull, 0ull},
- {"STOPPCLK" , 0, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"GATEHCLK" , 1, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"PWRCLMP" , 2, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"RSTPDWNMODULE" , 3, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"PHYSUSPENDED" , 4, 1, 880, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 880, "RAZ", 1, 1, 0, 0},
- {"NOF_BIS" , 0, 1, 881, "RO", 0, 0, 0ull, 0ull},
- {"NIF_BIS" , 1, 1, 881, "RO", 0, 0, 0ull, 0ull},
- {"USBC_BIS" , 2, 1, 881, "RO", 0, 0, 0ull, 0ull},
- {"N2UF_BIS" , 3, 1, 881, "RO", 0, 0, 0ull, 0ull},
- {"E2HC_BIS" , 4, 1, 881, "RO", 0, 0, 0ull, 0ull},
- {"U2NF_BIS" , 5, 1, 881, "RO", 0, 0, 0ull, 0ull},
- {"U2NC_BIS" , 6, 1, 881, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 881, "RAZ", 1, 1, 0, 0},
- {"DIVIDE" , 0, 3, 882, "R/W", 0, 0, 4ull, 0ull},
- {"HRST" , 3, 1, 882, "R/W", 0, 0, 0ull, 1ull},
- {"PRST" , 4, 1, 882, "R/W", 0, 0, 0ull, 1ull},
- {"ENABLE" , 5, 1, 882, "R/W", 0, 0, 1ull, 1ull},
- {"POR" , 6, 1, 882, "R/W", 0, 0, 1ull, 0ull},
- {"S_BIST" , 7, 1, 882, "R/W", 0, 0, 0ull, 1ull},
- {"SD_MODE" , 8, 2, 882, "R/W", 0, 0, 0ull, 0ull},
- {"CDIV_BYP" , 10, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"P_C_SEL" , 11, 2, 882, "R/W", 0, 0, 2ull, 0ull},
- {"P_COM_ON" , 13, 1, 882, "R/W", 0, 0, 1ull, 1ull},
- {"P_RTYPE" , 14, 2, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 882, "RAZ", 1, 1, 0, 0},
- {"HCLK_RST" , 17, 1, 882, "R/W", 0, 0, 1ull, 1ull},
- {"DIVIDE2" , 18, 2, 882, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_63" , 20, 44, 882, "RAZ", 1, 1, 0, 0},
- {"L2C_EMOD" , 0, 2, 883, "R/W", 0, 0, 1ull, 1ull},
- {"INV_A2" , 2, 1, 883, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_TEST" , 3, 1, 883, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_STT" , 4, 1, 883, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_0PAG" , 5, 1, 883, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 883, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 884, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 884, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 885, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 885, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 886, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 886, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 887, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 887, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 888, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 888, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 889, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 889, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 890, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 890, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 891, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 891, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 892, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 892, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 893, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 893, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 894, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 894, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 895, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 895, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 896, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 896, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 897, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 897, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 898, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 898, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 899, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 899, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"CHANNEL" , 4, 5, 900, "R/W", 0, 0, 0ull, 0ull},
- {"COUNT" , 9, 11, 900, "R/W", 0, 0, 0ull, 0ull},
- {"F_ADDR" , 20, 18, 900, "R/W", 0, 0, 0ull, 0ull},
- {"REQ" , 38, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"DONE" , 39, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 900, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_A_F" , 15, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_E" , 16, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_F" , 17, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PF" , 25, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 901, "RAZ", 0, 0, 0ull, 0ull},
- {"LTL_F_PE" , 32, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPF" , 35, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPE" , 36, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPF" , 37, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 901, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 902, "R/W1C", 1, 0, 0, 0ull},
- {"L2C_A_F" , 15, 1, 902, "R/W1C", 1, 0, 0, 0ull},
- {"LT_FI_E" , 16, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_FI_F" , 17, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 902, "R/W1C", 1, 0, 0, 0ull},
- {"UOD_PF" , 25, 1, 902, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_26_31" , 26, 6, 902, "RAZ", 1, 0, 0, 0ull},
- {"LTL_F_PE" , 32, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 902, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_RPF" , 35, 1, 902, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPE" , 36, 1, 902, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPF" , 37, 1, 902, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_38_63" , 38, 26, 902, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_IN" , 1, 8, 903, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 9, 4, 903, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 13, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ENB" , 14, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_ENB" , 15, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_ENB" , 16, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_EN" , 17, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_ENH" , 18, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_22" , 19, 4, 903, "RAZ", 0, 0, 0ull, 0ull},
- {"HST_MODE" , 23, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"DM_PULLD" , 24, 1, 903, "R/W", 0, 0, 1ull, 1ull},
- {"DP_PULLD" , 25, 1, 903, "R/W", 0, 0, 1ull, 1ull},
- {"TCLK" , 26, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"USBP_BIST" , 27, 1, 903, "R/W", 0, 0, 1ull, 1ull},
- {"USBC_END" , 28, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_BMODE" , 29, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"TXPREEMPHASISTUNE" , 30, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 903, "RAZ", 0, 0, 0ull, 0ull},
- {"TDATA_OUT" , 32, 4, 903, "RO", 1, 1, 0, 0},
- {"BIST_ERR" , 36, 1, 903, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 37, 1, 903, "RO", 0, 0, 0ull, 0ull},
- {"HSBIST" , 38, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 39, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 40, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"DRVVBUS" , 41, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 42, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"OTGDISABLE" , 43, 1, 903, "R/W", 0, 0, 1ull, 1ull},
- {"OTGTUNE" , 44, 3, 903, "R/W", 0, 0, 2ull, 2ull},
- {"COMPDISTUNE" , 47, 3, 903, "R/W", 0, 0, 2ull, 2ull},
- {"SQRXTUNE" , 50, 3, 903, "R/W", 0, 0, 3ull, 3ull},
- {"TXHSXVTUNE" , 53, 2, 903, "R/W", 0, 0, 0ull, 0ull},
- {"TXFSLSTUNE" , 55, 4, 903, "R/W", 0, 0, 3ull, 3ull},
- {"TXVREFTUNE" , 59, 4, 903, "R/W", 0, 0, 7ull, 7ull},
- {"TXRISETUNE" , 63, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 14, 0},
- {"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 14},
- {"cvmx_agl_gmx_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 12, 16},
- {"cvmx_agl_gmx_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 3, 28},
- {"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 7, 31},
- {"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 38},
- {"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 39},
- {"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 40},
- {"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 1, 41},
- {"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 1, 42},
- {"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 1, 43},
- {"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 44},
- {"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 4, 46},
- {"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 50},
- {"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 10, 52},
- {"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 11, 62},
- {"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 73},
- {"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 75},
- {"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 77},
- {"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 19, 79},
- {"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 19, 98},
- {"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 2, 117},
- {"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 40, 2, 119},
- {"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 121},
- {"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 123},
- {"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 125},
- {"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 127},
- {"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 129},
- {"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 131},
- {"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 133},
- {"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 135},
- {"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 137},
- {"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 139},
- {"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 4, 141},
- {"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 2, 145},
- {"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 147},
- {"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 2, 149},
- {"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 70, 4, 151},
- {"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 4, 155},
- {"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 2, 159},
- {"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 3, 161},
- {"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 5, 164},
- {"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 3, 169},
- {"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 2, 172},
- {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 81, 2, 174},
- {"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 176},
- {"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 85, 2, 178},
- {"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 87, 2, 180},
- {"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 89, 2, 182},
- {"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 184},
- {"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 93, 2, 186},
- {"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 95, 2, 188},
- {"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 97, 2, 190},
- {"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 2, 192},
- {"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 194},
- {"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 2, 196},
- {"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 2, 198},
- {"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 2, 200},
- {"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 109, 2, 202},
- {"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 111, 2, 204},
- {"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 2, 206},
- {"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 115, 2, 208},
- {"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 116, 2, 210},
- {"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 117, 3, 212},
- {"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 118, 10, 215},
- {"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 10, 225},
- {"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 120, 2, 235},
- {"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 121, 2, 237},
- {"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 6, 239},
- {"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 123, 2, 245},
- {"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 124, 2, 247},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 125, 2, 249},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 126, 2, 251},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 127, 2, 253},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 128, 2, 255},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 129, 22, 257},
- {"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 138, 22, 279},
- {"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 147, 22, 301},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 156, 7, 323},
- {"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 165, 7, 330},
- {"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 174, 7, 337},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 183, 22, 344},
- {"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 187, 22, 366},
- {"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 191, 22, 388},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 195, 7, 410},
- {"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 199, 7, 417},
- {"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 203, 7, 424},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 207, 22, 431},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 216, 22, 453},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 220, 7, 475},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 221, 2, 482},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 2, 484},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 229, 2, 486},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 230, 2, 488},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 231, 2, 490},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 232, 1, 492},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 236, 3, 493},
- {"cvmx_ciu_qlm_dcok" , CVMX_CSR_DB_TYPE_NCB, 64, 237, 2, 496},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 238, 6, 498},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 239, 8, 504},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 240, 2, 512},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 241, 2, 514},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 242, 2, 516},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 243, 2, 518},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 244, 3, 520},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 248, 7, 523},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 6, 530},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 253, 7, 536},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 29, 543},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 29, 572},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 256, 2, 601},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 2, 603},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 272, 3, 605},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 3, 608},
- {"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 274, 2, 611},
- {"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 275, 2, 613},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 276, 7, 615},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 277, 2, 622},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 278, 2, 624},
- {"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 279, 5, 626},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 280, 7, 631},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 281, 2, 638},
- {"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 8, 640},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 283, 10, 648},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 287, 1, 658},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 291, 1, 659},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 295, 1, 660},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 299, 1, 661},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 1, 662},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 307, 1, 663},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 311, 2, 664},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 315, 4, 666},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 319, 2, 670},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 323, 9, 672},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 327, 11, 681},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 331, 2, 692},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 335, 27, 694},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 339, 27, 721},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 343, 2, 748},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 347, 2, 750},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 351, 2, 752},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 355, 2, 754},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 359, 2, 756},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 363, 2, 758},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 367, 2, 760},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 371, 2, 762},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 375, 2, 764},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 379, 2, 766},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 383, 2, 768},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 387, 2, 770},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 4, 772},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 395, 2, 776},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 399, 2, 778},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 403, 2, 780},
- {"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 4, 782},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 4, 786},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 409, 2, 790},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 410, 5, 792},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 411, 2, 797},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 2, 799},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 3, 801},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 417, 5, 804},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 421, 2, 809},
- {"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 425, 2, 811},
- {"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 426, 2, 813},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 427, 3, 815},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 431, 2, 818},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 435, 2, 820},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 439, 2, 822},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 443, 3, 824},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 447, 2, 827},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 451, 2, 829},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 455, 2, 831},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 459, 2, 833},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 2, 835},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 467, 2, 837},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 2, 839},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 475, 2, 841},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 479, 2, 843},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 483, 2, 845},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 2, 847},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 2, 849},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 495, 2, 851},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 2, 853},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 2, 855},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 2, 857},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 511, 2, 859},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 512, 2, 861},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 513, 2, 863},
- {"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 514, 2, 865},
- {"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 2, 867},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 516, 3, 869},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 8, 872},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 518, 8, 880},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 2, 888},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 520, 2, 890},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 521, 6, 892},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 522, 2, 898},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 523, 2, 900},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 524, 2, 902},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 525, 9, 904},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 526, 3, 913},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 527, 9, 916},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 543, 2, 925},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 547, 2, 927},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 548, 2, 929},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 549, 2, 931},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 550, 2, 933},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 551, 19, 935},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 552, 7, 954},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 553, 3, 961},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 554, 3, 964},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 555, 3, 967},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 556, 5, 970},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 557, 5, 975},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 558, 1, 980},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 559, 1, 981},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 560, 7, 982},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 561, 7, 989},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 562, 3, 996},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 563, 3, 999},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 564, 3, 1002},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 565, 5, 1005},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 566, 5, 1010},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 567, 1, 1015},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 568, 1, 1016},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 569, 3, 1017},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 570, 3, 1020},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 571, 3, 1023},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 572, 2, 1026},
- {"cvmx_iob_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 573, 4, 1028},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 574, 2, 1032},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 575, 2, 1034},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 576, 2, 1036},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 577, 19, 1038},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 578, 2, 1057},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 579, 1, 1059},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 580, 15, 1060},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 581, 13, 1075},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 582, 13, 1088},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 583, 2, 1101},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 584, 2, 1103},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 585, 2, 1105},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 586, 3, 1107},
- {"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 594, 3, 1110},
- {"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 598, 2, 1113},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 602, 2, 1115},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 610, 2, 1117},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 706, 1, 1119},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 708, 1, 1120},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 710, 6, 1121},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 711, 5, 1127},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 712, 6, 1132},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 713, 7, 1138},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 714, 2, 1145},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 722, 2, 1147},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 723, 3, 1149},
- {"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 724, 2, 1152},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 725, 5, 1154},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 733, 3, 1159},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 734, 4, 1162},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 735, 3, 1166},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 736, 2, 1169},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 737, 2, 1171},
- {"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 738, 8, 1173},
- {"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 739, 9, 1181},
- {"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 740, 8, 1190},
- {"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 741, 12, 1198},
- {"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 742, 9, 1210},
- {"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 743, 5, 1219},
- {"cvmx_l2c_grpwrr0" , CVMX_CSR_DB_TYPE_RSL, 64, 744, 2, 1224},
- {"cvmx_l2c_grpwrr1" , CVMX_CSR_DB_TYPE_RSL, 64, 745, 2, 1226},
- {"cvmx_l2c_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 746, 10, 1228},
- {"cvmx_l2c_int_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 747, 10, 1238},
- {"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 748, 4, 1248},
- {"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 749, 2, 1252},
- {"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 16, 1254},
- {"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 751, 19, 1270},
- {"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 752, 3, 1289},
- {"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 753, 4, 1292},
- {"cvmx_l2c_oob" , CVMX_CSR_DB_TYPE_RSL, 64, 754, 3, 1296},
- {"cvmx_l2c_oob1" , CVMX_CSR_DB_TYPE_RSL, 64, 755, 6, 1299},
- {"cvmx_l2c_oob2" , CVMX_CSR_DB_TYPE_RSL, 64, 756, 6, 1305},
- {"cvmx_l2c_oob3" , CVMX_CSR_DB_TYPE_RSL, 64, 757, 6, 1311},
- {"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 2, 1317},
- {"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 762, 17, 1319},
- {"cvmx_l2c_ppgrp" , CVMX_CSR_DB_TYPE_RSL, 64, 763, 5, 1336},
- {"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 764, 5, 1341},
- {"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 765, 2, 1346},
- {"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 766, 3, 1348},
- {"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 767, 2, 1351},
- {"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 768, 2, 1353},
- {"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 769, 2, 1355},
- {"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 770, 7, 1357},
- {"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 771, 5, 1364},
- {"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 772, 3, 1369},
- {"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 773, 3, 1372},
- {"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 774, 2, 1375},
- {"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 775, 2, 1377},
- {"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 776, 2, 1379},
- {"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 777, 6, 1381},
- {"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 778, 14, 1387},
- {"cvmx_lmc#_bist_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 779, 2, 1401},
- {"cvmx_lmc#_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 780, 8, 1403},
- {"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 781, 7, 1411},
- {"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 782, 19, 1418},
- {"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 783, 8, 1437},
- {"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 784, 2, 1445},
- {"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 785, 2, 1447},
- {"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 786, 18, 1449},
- {"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 787, 6, 1467},
- {"cvmx_lmc#_dll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 788, 5, 1473},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 789, 5, 1478},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 790, 5, 1483},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 791, 6, 1488},
- {"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 792, 2, 1494},
- {"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 793, 2, 1496},
- {"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 794, 14, 1498},
- {"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 9, 1512},
- {"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 2, 1521},
- {"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 797, 2, 1523},
- {"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 798, 2, 1525},
- {"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 799, 14, 1527},
- {"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 800, 6, 1541},
- {"cvmx_lmc#_read_level_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 801, 7, 1547},
- {"cvmx_lmc#_read_level_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 4, 1554},
- {"cvmx_lmc#_read_level_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 11, 1558},
- {"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 807, 6, 1569},
- {"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 9, 1575},
- {"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 809, 5, 1584},
- {"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 5, 1589},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 811, 6, 1594},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 3, 1600},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 813, 10, 1603},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 815, 3, 1613},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 817, 3, 1616},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 819, 15, 1619},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 821, 3, 1634},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 3, 1637},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 823, 3, 1640},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 5, 1643},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 1, 1648},
- {"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 827, 9, 1649},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 13, 1658},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 836, 13, 1671},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 844, 6, 1684},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 845, 1, 1690},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 849, 2, 1691},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 850, 2, 1693},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 851, 13, 1695},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 852, 8, 1708},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 853, 4, 1716},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 854, 1, 1720},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 855, 3, 1721},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 856, 2, 1724},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 857, 6, 1726},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 858, 7, 1732},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 859, 4, 1739},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 860, 2, 1743},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 861, 2, 1745},
- {"cvmx_mio_ndf_dma_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 862, 10, 1747},
- {"cvmx_mio_ndf_dma_int" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 2, 1757},
- {"cvmx_mio_ndf_dma_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 864, 2, 1759},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 13, 1761},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 12, 1774},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 869, 3, 1786},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 871, 3, 1789},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 873, 2, 1792},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 2, 1794},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 877, 2, 1796},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 879, 7, 1798},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 881, 2, 1805},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 883, 7, 1807},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 885, 4, 1814},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 887, 8, 1818},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 889, 9, 1826},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 891, 7, 1835},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 893, 9, 1842},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 895, 2, 1851},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 897, 2, 1853},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 899, 4, 1855},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 901, 2, 1859},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 903, 2, 1861},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 905, 2, 1863},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 907, 4, 1865},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 909, 2, 1869},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 911, 2, 1871},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 913, 2, 1873},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 915, 2, 1875},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 917, 2, 1877},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 919, 2, 1879},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 921, 6, 1881},
- {"cvmx_mio_uart2_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 2, 1887},
- {"cvmx_mio_uart2_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 924, 2, 1889},
- {"cvmx_mio_uart2_far" , CVMX_CSR_DB_TYPE_RSL, 64, 925, 2, 1891},
- {"cvmx_mio_uart2_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 926, 7, 1893},
- {"cvmx_mio_uart2_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 927, 2, 1900},
- {"cvmx_mio_uart2_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 928, 7, 1902},
- {"cvmx_mio_uart2_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 929, 4, 1909},
- {"cvmx_mio_uart2_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 930, 8, 1913},
- {"cvmx_mio_uart2_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 931, 9, 1921},
- {"cvmx_mio_uart2_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 932, 7, 1930},
- {"cvmx_mio_uart2_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 933, 9, 1937},
- {"cvmx_mio_uart2_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 934, 2, 1946},
- {"cvmx_mio_uart2_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 935, 2, 1948},
- {"cvmx_mio_uart2_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 936, 4, 1950},
- {"cvmx_mio_uart2_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 937, 2, 1954},
- {"cvmx_mio_uart2_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 938, 2, 1956},
- {"cvmx_mio_uart2_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 939, 2, 1958},
- {"cvmx_mio_uart2_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 940, 4, 1960},
- {"cvmx_mio_uart2_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 941, 2, 1964},
- {"cvmx_mio_uart2_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 942, 2, 1966},
- {"cvmx_mio_uart2_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 943, 2, 1968},
- {"cvmx_mio_uart2_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 944, 2, 1970},
- {"cvmx_mio_uart2_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 945, 2, 1972},
- {"cvmx_mio_uart2_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 946, 2, 1974},
- {"cvmx_mio_uart2_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 947, 6, 1976},
- {"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 948, 5, 1982},
- {"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 950, 8, 1987},
- {"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 952, 8, 1995},
- {"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 954, 2, 2003},
- {"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 956, 3, 2005},
- {"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 958, 5, 2008},
- {"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 960, 4, 2013},
- {"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 962, 8, 2017},
- {"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 964, 2, 2025},
- {"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 966, 2, 2027},
- {"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 968, 5, 2029},
- {"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 970, 4, 2034},
- {"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 972, 4, 2038},
- {"cvmx_ndf_bt_pg_info" , CVMX_CSR_DB_TYPE_NCB, 64, 974, 4, 2042},
- {"cvmx_ndf_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 975, 1, 2046},
- {"cvmx_ndf_drbell" , CVMX_CSR_DB_TYPE_NCB, 64, 976, 2, 2047},
- {"cvmx_ndf_ecc_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 977, 3, 2049},
- {"cvmx_ndf_int" , CVMX_CSR_DB_TYPE_NCB, 64, 978, 8, 2052},
- {"cvmx_ndf_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 979, 8, 2060},
- {"cvmx_ndf_misc" , CVMX_CSR_DB_TYPE_NCB, 64, 980, 11, 2068},
- {"cvmx_ndf_st_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 981, 8, 2079},
- {"cvmx_npei_bar1_index#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 982, 5, 2087},
- {"cvmx_npei_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1014, 58, 2092},
- {"cvmx_npei_bist_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1015, 15, 2150},
- {"cvmx_npei_ctl_port0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1016, 17, 2165},
- {"cvmx_npei_ctl_port1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1017, 17, 2182},
- {"cvmx_npei_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018, 10, 2199},
- {"cvmx_npei_ctl_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1019, 11, 2209},
- {"cvmx_npei_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1020, 5, 2220},
- {"cvmx_npei_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1021, 8, 2225},
- {"cvmx_npei_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1022, 2, 2233},
- {"cvmx_npei_dma#_counts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1023, 3, 2235},
- {"cvmx_npei_dma#_dbell" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 1028, 2, 2238},
- {"cvmx_npei_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1033, 4, 2240},
- {"cvmx_npei_dma#_naddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1038, 2, 2244},
- {"cvmx_npei_dma0_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1043, 2, 2246},
- {"cvmx_npei_dma1_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1044, 2, 2248},
- {"cvmx_npei_dma_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1045, 2, 2250},
- {"cvmx_npei_dma_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1046, 17, 2252},
- {"cvmx_npei_dma_pcie_req_num" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1047, 15, 2269},
- {"cvmx_npei_dma_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1048, 6, 2284},
- {"cvmx_npei_dma_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1049, 6, 2290},
- {"cvmx_npei_int_a_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050, 11, 2296},
- {"cvmx_npei_int_a_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1051, 11, 2307},
- {"cvmx_npei_int_a_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1052, 11, 2318},
- {"cvmx_npei_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1053, 64, 2329},
- {"cvmx_npei_int_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1054, 63, 2393},
- {"cvmx_npei_int_info" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1055, 3, 2456},
- {"cvmx_npei_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1056, 64, 2459},
- {"cvmx_npei_int_sum2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1057, 61, 2523},
- {"cvmx_npei_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1058, 1, 2584},
- {"cvmx_npei_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1059, 1, 2585},
- {"cvmx_npei_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1060, 3, 2586},
- {"cvmx_npei_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1061, 11, 2589},
- {"cvmx_npei_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077, 1, 2600},
- {"cvmx_npei_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078, 1, 2601},
- {"cvmx_npei_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079, 1, 2602},
- {"cvmx_npei_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080, 1, 2603},
- {"cvmx_npei_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081, 1, 2604},
- {"cvmx_npei_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082, 1, 2605},
- {"cvmx_npei_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1083, 1, 2606},
- {"cvmx_npei_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1084, 1, 2607},
- {"cvmx_npei_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1085, 3, 2608},
- {"cvmx_npei_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1086, 1, 2611},
- {"cvmx_npei_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1087, 1, 2612},
- {"cvmx_npei_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1088, 1, 2613},
- {"cvmx_npei_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1089, 1, 2614},
- {"cvmx_npei_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1090, 1, 2615},
- {"cvmx_npei_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091, 1, 2616},
- {"cvmx_npei_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1092, 1, 2617},
- {"cvmx_npei_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1093, 1, 2618},
- {"cvmx_npei_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1094, 3, 2619},
- {"cvmx_npei_pcie_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1095, 7, 2622},
- {"cvmx_npei_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1096, 2, 2629},
- {"cvmx_npei_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1097, 3, 2631},
- {"cvmx_npei_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1098, 3, 2634},
- {"cvmx_npei_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1099, 3, 2637},
- {"cvmx_npei_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1100, 3, 2640},
- {"cvmx_npei_pkt#_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1132, 2, 2643},
- {"cvmx_npei_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1164, 2, 2645},
- {"cvmx_npei_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1196, 2, 2647},
- {"cvmx_npei_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1228, 5, 2649},
- {"cvmx_npei_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1260, 13, 2654},
- {"cvmx_npei_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1292, 2, 2667},
- {"cvmx_npei_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1324, 2, 2669},
- {"cvmx_npei_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1356, 2, 2671},
- {"cvmx_npei_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1388, 2, 2673},
- {"cvmx_npei_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1389, 2, 2675},
- {"cvmx_npei_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1390, 1, 2677},
- {"cvmx_npei_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1391, 2, 2678},
- {"cvmx_npei_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1392, 2, 2680},
- {"cvmx_npei_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1393, 2, 2682},
- {"cvmx_npei_pkt_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1394, 2, 2684},
- {"cvmx_npei_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1395, 2, 2686},
- {"cvmx_npei_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1427, 2, 2688},
- {"cvmx_npei_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1428, 1, 2690},
- {"cvmx_npei_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1429, 10, 2691},
- {"cvmx_npei_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1430, 2, 2701},
- {"cvmx_npei_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1431, 1, 2703},
- {"cvmx_npei_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1432, 2, 2704},
- {"cvmx_npei_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1433, 3, 2706},
- {"cvmx_npei_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1434, 2, 2709},
- {"cvmx_npei_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1435, 2, 2711},
- {"cvmx_npei_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1436, 2, 2713},
- {"cvmx_npei_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1437, 2, 2715},
- {"cvmx_npei_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1438, 1, 2717},
- {"cvmx_npei_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1439, 2, 2718},
- {"cvmx_npei_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1440, 1, 2720},
- {"cvmx_npei_pkt_slist_id_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1441, 3, 2721},
- {"cvmx_npei_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1442, 2, 2724},
- {"cvmx_npei_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1443, 2, 2726},
- {"cvmx_npei_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1444, 2, 2728},
- {"cvmx_npei_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1445, 2, 2730},
- {"cvmx_npei_rsl_int_blocks" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1446, 29, 2732},
- {"cvmx_npei_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1447, 1, 2761},
- {"cvmx_npei_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1448, 4, 2762},
- {"cvmx_npei_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1449, 7, 2766},
- {"cvmx_npei_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1450, 5, 2773},
- {"cvmx_npei_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1451, 4, 2778},
- {"cvmx_npei_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1452, 1, 2782},
- {"cvmx_npei_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1453, 4, 2783},
- {"cvmx_npei_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1454, 1, 2787},
- {"cvmx_npei_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 1455, 2, 2788},
- {"cvmx_npei_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1456, 2, 2790},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1457, 2, 2792},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1458, 24, 2794},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1459, 4, 2818},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1460, 5, 2822},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1461, 5, 2827},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1462, 2, 2832},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1463, 1, 2834},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1464, 1, 2835},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1465, 5, 2836},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1466, 2, 2841},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1467, 1, 2843},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1468, 1, 2844},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1469, 4, 2845},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1470, 2, 2849},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1471, 2, 2851},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1472, 1, 2853},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1473, 1, 2854},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1474, 2, 2855},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1475, 3, 2857},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1476, 2, 2860},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1477, 2, 2862},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1478, 4, 2864},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1479, 10, 2868},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1480, 12, 2878},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1481, 7, 2890},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1482, 2, 2897},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1483, 1, 2899},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1484, 2, 2900},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1485, 7, 2902},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1486, 11, 2909},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1487, 19, 2920},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1488, 11, 2939},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1489, 17, 2950},
- {"cvmx_pcieep#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1490, 12, 2967},
- {"cvmx_pcieep#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1491, 22, 2979},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1492, 3, 3001},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1493, 3, 3004},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1494, 1, 3007},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1495, 1, 3008},
- {"cvmx_pcieep#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1496, 1, 3009},
- {"cvmx_pcieep#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1497, 1, 3010},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1498, 3, 3011},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1499, 14, 3014},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1500, 14, 3028},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1501, 14, 3042},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1502, 9, 3056},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1503, 9, 3065},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1504, 6, 3074},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1505, 1, 3080},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1506, 1, 3081},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1507, 1, 3082},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1508, 1, 3083},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1509, 2, 3084},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1510, 1, 3086},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1511, 6, 3087},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1512, 6, 3093},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1513, 13, 3099},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1514, 5, 3112},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1515, 8, 3117},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1516, 19, 3125},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1517, 3, 3144},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1518, 1, 3147},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1519, 1, 3148},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1520, 3, 3149},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1521, 3, 3152},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1522, 3, 3155},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1523, 4, 3158},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1524, 4, 3162},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1525, 4, 3166},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1526, 7, 3170},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1527, 5, 3177},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1528, 5, 3182},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1529, 4, 3187},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1530, 4, 3191},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1531, 4, 3195},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1532, 1, 3199},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1533, 1, 3200},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1534, 2, 3201},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1536, 24, 3203},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1538, 4, 3227},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1540, 5, 3231},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1542, 1, 3236},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1544, 1, 3237},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1546, 4, 3238},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1548, 17, 3242},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1550, 4, 3259},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1552, 6, 3263},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1554, 1, 3269},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1556, 1, 3270},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1558, 2, 3271},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1560, 2, 3273},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1562, 1, 3275},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1564, 15, 3276},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1566, 10, 3291},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1568, 12, 3301},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1570, 7, 3313},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1572, 2, 3320},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1574, 1, 3322},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1576, 2, 3323},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1578, 7, 3325},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1580, 11, 3332},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1582, 19, 3343},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1584, 11, 3362},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1586, 20, 3373},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1588, 12, 3393},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1590, 22, 3405},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1592, 8, 3427},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1594, 4, 3435},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1596, 3, 3439},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1598, 3, 3442},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1600, 1, 3445},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1602, 1, 3446},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1604, 1, 3447},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1606, 1, 3448},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1608, 3, 3449},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1610, 14, 3452},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1612, 14, 3466},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1614, 14, 3480},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1616, 9, 3494},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1618, 9, 3503},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1620, 6, 3512},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1622, 1, 3518},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1624, 1, 3519},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1626, 1, 3520},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1628, 1, 3521},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1630, 4, 3522},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1632, 9, 3526},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1634, 2, 3535},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1636, 2, 3537},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1638, 1, 3539},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1640, 6, 3540},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1642, 6, 3546},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1644, 13, 3552},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1646, 5, 3565},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1648, 8, 3570},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1650, 19, 3578},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1652, 3, 3597},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1654, 1, 3600},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1656, 1, 3601},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1658, 3, 3602},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1660, 3, 3605},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1662, 3, 3608},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1664, 4, 3611},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1666, 4, 3615},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1668, 4, 3619},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1670, 7, 3623},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1672, 5, 3630},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1674, 5, 3635},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1676, 4, 3640},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1678, 4, 3644},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1680, 4, 3648},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1682, 1, 3652},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1684, 1, 3653},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1686, 9, 3654},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1690, 6, 3663},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1694, 9, 3669},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1698, 6, 3678},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1702, 13, 3684},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1706, 13, 3697},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1710, 2, 3710},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1714, 4, 3712},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1718, 8, 3716},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1722, 13, 3724},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1726, 17, 3737},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1730, 7, 3754},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1734, 3, 3761},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1738, 8, 3764},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1742, 7, 3772},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1746, 4, 3779},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1750, 5, 3783},
- {"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1754, 8, 3788},
- {"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1755, 2, 3796},
- {"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1756, 5, 3798},
- {"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1757, 10, 3803},
- {"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1758, 2, 3813},
- {"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1759, 7, 3815},
- {"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1760, 7, 3822},
- {"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1761, 6, 3829},
- {"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1762, 5, 3835},
- {"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1763, 5, 3840},
- {"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1764, 3, 3845},
- {"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1765, 6, 3848},
- {"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1766, 9, 3854},
- {"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1767, 5, 3863},
- {"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1768, 10, 3868},
- {"cvmx_pesc#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1769, 14, 3878},
- {"cvmx_pesc#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1771, 15, 3892},
- {"cvmx_pesc#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 1773, 2, 3907},
- {"cvmx_pesc#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 1775, 2, 3909},
- {"cvmx_pesc#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 1777, 2, 3911},
- {"cvmx_pesc#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1779, 16, 3913},
- {"cvmx_pesc#_ctl_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1781, 3, 3929},
- {"cvmx_pesc#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 1783, 32, 3932},
- {"cvmx_pesc#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1785, 32, 3964},
- {"cvmx_pesc#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1787, 5, 3996},
- {"cvmx_pesc#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1789, 2, 4001},
- {"cvmx_pesc#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1791, 2, 4003},
- {"cvmx_pesc#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1793, 2, 4005},
- {"cvmx_pesc#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 1795, 2, 4007},
- {"cvmx_pesc#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1803, 2, 4009},
- {"cvmx_pesc#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 1811, 8, 4011},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1813, 2, 4019},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1814, 4, 4021},
- {"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 1818, 16, 4025},
- {"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 1819, 16, 4041},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 1820, 3, 4057},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1822, 8, 4060},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1823, 22, 4068},
- {"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1824, 6, 4090},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1825, 14, 4096},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1826, 14, 4110},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1827, 2, 4124},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1828, 28, 4126},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1840, 25, 4154},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1852, 2, 4179},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1916, 4, 4181},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1924, 9, 4185},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1932, 2, 4194},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1933, 2, 4196},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1934, 2, 4198},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1946, 2, 4200},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1958, 2, 4202},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1970, 2, 4204},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1982, 2, 4206},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1994, 2, 4208},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2006, 2, 4210},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2018, 2, 4212},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2030, 2, 4214},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2042, 2, 4216},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2054, 2, 4218},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2055, 2, 4220},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2067, 2, 4222},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 2079, 2, 4224},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 2091, 2, 4226},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2155, 2, 4228},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2156, 3, 4230},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2157, 3, 4233},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2158, 2, 4236},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2159, 2, 4238},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2160, 4, 4240},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2161, 5, 4244},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2162, 4, 4249},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2163, 8, 4253},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2164, 4, 4261},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2165, 5, 4265},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2166, 1, 4270},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2167, 5, 4271},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2168, 1, 4276},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2169, 13, 4277},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2170, 4, 4290},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2171, 13, 4294},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2172, 6, 4307},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2173, 9, 4313},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2174, 4, 4322},
- {"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2175, 7, 4326},
- {"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 5, 4333},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 2177, 5, 4338},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 2178, 4, 4343},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2179, 9, 4347},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 5, 4356},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2181, 16, 4361},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 4, 4377},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2183, 1, 4381},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2184, 1, 4382},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2185, 1, 4383},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2186, 1, 4384},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 2187, 11, 4385},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 2188, 2, 4396},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2189, 4, 4398},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2190, 5, 4402},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2191, 3, 4407},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2192, 4, 4410},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2193, 2, 4414},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 2194, 3, 4416},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2195, 3, 4419},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2196, 12, 4422},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2197, 2, 4434},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2198, 13, 4436},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2199, 3, 4449},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2200, 2, 4452},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2208, 2, 4454},
- {"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2209, 2, 4456},
- {"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 2210, 2, 4458},
- {"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2211, 2, 4460},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2219, 2, 4462},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2220, 2, 4464},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 2221, 2, 4466},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2222, 10, 4468},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2226, 5, 4478},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2234, 10, 4483},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2242, 2, 4493},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2243, 2, 4495},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2244, 2, 4497},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2252, 3, 4499},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2253, 6, 4502},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2269, 5, 4508},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2270, 7, 4513},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2286, 2, 4520},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2302, 1, 4522},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2303, 1, 4523},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2304, 1, 4524},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2305, 5, 4525},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2306, 5, 4530},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2307, 4, 4535},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2308, 10, 4539},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2309, 1, 4549},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2310, 3, 4550},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2311, 7, 4553},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2312, 2, 4560},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2313, 1, 4562},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2314, 1, 4563},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2315, 1, 4564},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2316, 18, 4565},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2317, 3, 4583},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2318, 2, 4586},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2319, 3, 4588},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2320, 7, 4591},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2321, 2, 4598},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2322, 2, 4600},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 2323, 2, 4602},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2324, 3, 4604},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2325, 3, 4607},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2326, 7, 4610},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2327, 10, 4617},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2329, 6, 4627},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2331, 2, 4633},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2333, 4, 4635},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2335, 4, 4639},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2337, 6, 4643},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2338, 3, 4649},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2339, 5, 4652},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2340, 4, 4657},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2341, 6, 4661},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2342, 4, 4667},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2343, 2, 4671},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2344, 4, 4673},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2345, 2, 4677},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2346, 3, 4679},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2347, 4, 4682},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2348, 12, 4686},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2349, 3, 4698},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 2350, 5, 4701},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2351, 2, 4706},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2352, 2, 4708},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2353, 18, 4710},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2354, 12, 4728},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2355, 6, 4740},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2356, 5, 4746},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2357, 1, 4751},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2358, 2, 4752},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2359, 2, 4754},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2360, 18, 4756},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2361, 12, 4774},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2362, 6, 4786},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2363, 2, 4792},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2364, 2, 4794},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2365, 18, 4796},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2366, 12, 4814},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2367, 6, 4826},
- {"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 2368, 2, 4832},
- {"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2370, 2, 4834},
- {"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2372, 8, 4836},
- {"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2374, 11, 4844},
- {"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 2376, 15, 4855},
- {"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2386, 8, 4870},
- {"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2396, 8, 4878},
- {"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2398, 4, 4886},
- {"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 2408, 15, 4890},
- {"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2418, 6, 4905},
- {"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2428, 6, 4911},
- {"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2430, 4, 4917},
- {"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2440, 2, 4921},
- {"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2448, 6, 4923},
- {"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 2450, 4, 4929},
- {"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 2452, 1, 4933},
- {"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 2454, 1, 4934},
- {"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 2456, 1, 4935},
- {"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2458, 7, 4936},
- {"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 2460, 1, 4943},
- {"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 2462, 14, 4944},
- {"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 2464, 10, 4958},
- {"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 2466, 14, 4968},
- {"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2468, 32, 4982},
- {"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2470, 32, 5014},
- {"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2472, 2, 5046},
- {"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2474, 4, 5048},
- {"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2476, 13, 5052},
- {"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 2478, 10, 5065},
- {"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2480, 10, 5075},
- {"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2482, 2, 5085},
- {"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 2484, 6, 5087},
- {"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 2486, 5, 5093},
- {"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 2488, 6, 5098},
- {"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 2490, 5, 5104},
- {"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 2492, 1, 5109},
- {"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2494, 13, 5110},
- {"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 2496, 2, 5123},
- {"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2498, 2, 5125},
- {"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 2500, 11, 5127},
- {"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2516, 3, 5138},
- {"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2518, 12, 5141},
- {"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 2534, 12, 5153},
- {"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 2550, 6, 5165},
- {"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2566, 4, 5171},
- {"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 2582, 2, 5175},
- {"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 2584, 2, 5177},
- {"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 2586, 15, 5179},
- {"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2588, 2, 5194},
- {"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2590, 3, 5196},
- {"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 2592, 1, 5199},
- {"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2608, 6, 5200},
- {"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2610, 8, 5206},
- {"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2612, 15, 5214},
- {"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 2614, 6, 5229},
- {"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2616, 2, 5235},
- {"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2618, 2, 5237},
- {"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2620, 2, 5239},
- {"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2622, 2, 5241},
- {"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2624, 2, 5243},
- {"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2626, 2, 5245},
- {"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2628, 2, 5247},
- {"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2630, 2, 5249},
- {"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2632, 2, 5251},
- {"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2634, 2, 5253},
- {"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2636, 2, 5255},
- {"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2638, 2, 5257},
- {"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2640, 2, 5259},
- {"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2642, 2, 5261},
- {"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2644, 2, 5263},
- {"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2646, 2, 5265},
- {"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 2648, 7, 5267},
- {"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 2650, 34, 5274},
- {"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 2652, 34, 5308},
- {"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2654, 35, 5342},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"AGL_GMX_BAD_REG" , 0x11800e0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"AGL_GMX_BIST" , 0x11800e0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"AGL_GMX_DRV_CTL" , 0x11800e00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_INF_MODE" , 0x11800e00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_PRT0_CFG" , 0x11800e0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_PRT1_CFG" , 0x11800e0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX0_ADR_CAM0" , 0x11800e0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX1_ADR_CAM0" , 0x11800e0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX0_ADR_CAM1" , 0x11800e0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX1_ADR_CAM1" , 0x11800e0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX0_ADR_CAM2" , 0x11800e0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX1_ADR_CAM2" , 0x11800e0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX0_ADR_CAM3" , 0x11800e0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX1_ADR_CAM3" , 0x11800e0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX0_ADR_CAM4" , 0x11800e00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX1_ADR_CAM4" , 0x11800e00009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX0_ADR_CAM5" , 0x11800e00001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX1_ADR_CAM5" , 0x11800e00009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800e0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX1_ADR_CAM_EN" , 0x11800e0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX0_ADR_CTL" , 0x11800e0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX1_ADR_CTL" , 0x11800e0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX0_DECISION" , 0x11800e0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX1_DECISION" , 0x11800e0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX0_FRM_CHK" , 0x11800e0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX1_FRM_CHK" , 0x11800e0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX0_FRM_CTL" , 0x11800e0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX1_FRM_CTL" , 0x11800e0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX0_FRM_MAX" , 0x11800e0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX1_FRM_MAX" , 0x11800e0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX0_FRM_MIN" , 0x11800e0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX1_FRM_MIN" , 0x11800e0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX0_IFG" , 0x11800e0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX1_IFG" , 0x11800e0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX0_INT_EN" , 0x11800e0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX1_INT_EN" , 0x11800e0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX0_INT_REG" , 0x11800e0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX1_INT_REG" , 0x11800e0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX0_JABBER" , 0x11800e0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX1_JABBER" , 0x11800e0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800e0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX1_PAUSE_DROP_TIME" , 0x11800e0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX0_STATS_CTL" , 0x11800e0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX1_STATS_CTL" , 0x11800e0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX0_STATS_OCTS" , 0x11800e0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX1_STATS_OCTS" , 0x11800e0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800e0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX1_STATS_OCTS_CTL" , 0x11800e0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800e00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX1_STATS_OCTS_DMAC" , 0x11800e00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800e00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX1_STATS_OCTS_DRP" , 0x11800e00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX0_STATS_PKTS" , 0x11800e0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX1_STATS_PKTS" , 0x11800e0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800e00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX1_STATS_PKTS_BAD" , 0x11800e00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800e0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX1_STATS_PKTS_CTL" , 0x11800e0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800e00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX1_STATS_PKTS_DMAC" , 0x11800e00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800e00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX1_STATS_PKTS_DRP" , 0x11800e00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX0_UDD_SKP" , 0x11800e0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX1_UDD_SKP" , 0x11800e0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_DROP0" , 0x11800e0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_DROP1" , 0x11800e0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_OFF0" , 0x11800e0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_BP_OFF1" , 0x11800e0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_BP_ON0" , 0x11800e0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_BP_ON1" , 0x11800e0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_PRT_INFO" , 0x11800e00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"AGL_GMX_RX_TX_STATUS" , 0x11800e00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_SMAC0" , 0x11800e0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_SMAC1" , 0x11800e0000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_STAT_BP" , 0x11800e0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX0_APPEND" , 0x11800e0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX1_APPEND" , 0x11800e0000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX0_CTL" , 0x11800e0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX1_CTL" , 0x11800e0000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX0_MIN_PKT" , 0x11800e0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX1_MIN_PKT" , 0x11800e0000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800e0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX1_PAUSE_PKT_INTERVAL", 0x11800e0000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800e0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX1_PAUSE_PKT_TIME" , 0x11800e0000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800e0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX1_PAUSE_TOGO" , 0x11800e0000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800e0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX1_PAUSE_ZERO" , 0x11800e0000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800e0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX1_SOFT_PAUSE" , 0x11800e0000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX0_STAT0" , 0x11800e0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX1_STAT0" , 0x11800e0000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX0_STAT1" , 0x11800e0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX1_STAT1" , 0x11800e0000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX0_STAT2" , 0x11800e0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX1_STAT2" , 0x11800e0000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX0_STAT3" , 0x11800e0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX1_STAT3" , 0x11800e0000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX0_STAT4" , 0x11800e00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX1_STAT4" , 0x11800e0000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX0_STAT5" , 0x11800e00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX1_STAT5" , 0x11800e0000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX0_STAT6" , 0x11800e00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX1_STAT6" , 0x11800e0000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX0_STAT7" , 0x11800e00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX1_STAT7" , 0x11800e0000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX0_STAT8" , 0x11800e00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX1_STAT8" , 0x11800e0000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX0_STAT9" , 0x11800e00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX1_STAT9" , 0x11800e0000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX0_STATS_CTL" , 0x11800e0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX1_STATS_CTL" , 0x11800e0000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX0_THRESH" , 0x11800e0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX1_THRESH" , 0x11800e0000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX_BP" , 0x11800e00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"AGL_GMX_TX_COL_ATTEMPT" , 0x11800e0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"AGL_GMX_TX_IFG" , 0x11800e0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"AGL_GMX_TX_INT_EN" , 0x11800e0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"AGL_GMX_TX_INT_REG" , 0x11800e0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"AGL_GMX_TX_JAM" , 0x11800e0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"AGL_GMX_TX_LFSR" , 0x11800e00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"AGL_GMX_TX_OVR_BP" , 0x11800e00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800e00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800e00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 71},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT0_EN4_0_W1C" , 0x1070000002c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT1_EN4_0_W1C" , 0x1070000002c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT2_EN4_0_W1C" , 0x1070000002ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT3_EN4_0_W1C" , 0x1070000002cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT0_EN4_0_W1S" , 0x1070000006c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT1_EN4_0_W1S" , 0x1070000006c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT2_EN4_0_W1S" , 0x1070000006ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT3_EN4_0_W1S" , 0x1070000006cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT0_EN4_1_W1C" , 0x1070000002c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT1_EN4_1_W1C" , 0x1070000002c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT2_EN4_1_W1C" , 0x1070000002ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT3_EN4_1_W1C" , 0x1070000002cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT0_EN4_1_W1S" , 0x1070000006c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT1_EN4_1_W1S" , 0x1070000006c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT2_EN4_1_W1S" , 0x1070000006ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT3_EN4_1_W1S" , 0x1070000006cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_QLM_DCOK" , 0x1070000000760ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"FPA_WART_CTL" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"FPA_WART_STATUS" , 0x11800280000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
- {"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"GMX0_TX000_CBFC_XOFF" , 0x11800080005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"GMX0_TX000_CBFC_XON" , 0x11800080005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX003_SGMII_CTL" , 0x1180008001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"IOB_TO_CMB_CREDITS" , 0x11800f00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"IPD_PORT36_BP_PAGE_CNT2" , 0x14f0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"IPD_PORT37_BP_PAGE_CNT2" , 0x14f0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"IPD_PORT38_BP_PAGE_CNT2" , 0x14f0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"IPD_PORT39_BP_PAGE_CNT2" , 0x14f0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14f0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14f0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14f0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14f00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_256_CNT" , 0x14f0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_257_CNT" , 0x14f0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_258_CNT" , 0x14f0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_259_CNT" , 0x14f00000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_260_CNT" , 0x14f00000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_261_CNT" , 0x14f00000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_262_CNT" , 0x14f00000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_263_CNT" , 0x14f00000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_264_CNT" , 0x14f00000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_265_CNT" , 0x14f00000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_266_CNT" , 0x14f00000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_267_CNT" , 0x14f00000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_268_CNT" , 0x14f00000010e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_269_CNT" , 0x14f00000010f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_270_CNT" , 0x14f00000010f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_271_CNT" , 0x14f0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_272_CNT" , 0x14f0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_273_CNT" , 0x14f0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_274_CNT" , 0x14f0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_275_CNT" , 0x14f0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_276_CNT" , 0x14f0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_277_CNT" , 0x14f0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_278_CNT" , 0x14f0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_279_CNT" , 0x14f0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_280_CNT" , 0x14f0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_281_CNT" , 0x14f0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_282_CNT" , 0x14f0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_283_CNT" , 0x14f0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_284_CNT" , 0x14f0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_285_CNT" , 0x14f0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_286_CNT" , 0x14f0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_287_CNT" , 0x14f0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"IPD_RED_PORT_ENABLE2" , 0x14f00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"L2C_BST0" , 0x11800800007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"L2C_BST1" , 0x11800800007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"L2C_BST2" , 0x11800800007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"L2C_GRPWRR0" , 0x11800800000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"L2C_GRPWRR1" , 0x11800800000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"L2C_INT_EN" , 0x1180080000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"L2C_INT_STAT" , 0x11800800000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"L2C_LFB3" , 0x11800800000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"L2C_OOB" , 0x11800800000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"L2C_OOB1" , 0x11800800000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"L2C_OOB2" , 0x11800800000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"L2C_OOB3" , 0x11800800000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"L2C_PFC1" , 0x11800800000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"L2C_PFC2" , 0x11800800000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"L2C_PFC3" , 0x11800800000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"L2C_PPGRP" , 0x11800800000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"L2D_FUS0" , 0x11800800007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"L2D_FUS1" , 0x11800800007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"L2D_FUS2" , 0x11800800007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"L2D_FUS3" , 0x11800800007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"LMC0_BIST_CTL" , 0x11800880000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"LMC0_BIST_RESULT" , 0x11800880000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"LMC0_DLL_CTL" , 0x11800880000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"LMC0_NXM" , 0x11800880000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"LMC0_PLL_CTL" , 0x11800880000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"LMC0_PLL_STATUS" , 0x11800880000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"LMC0_READ_LEVEL_CTL" , 0x1180088000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"LMC0_READ_LEVEL_DBG" , 0x1180088000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"LMC0_READ_LEVEL_RANK000" , 0x1180088000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"LMC0_READ_LEVEL_RANK001" , 0x1180088000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"LMC0_READ_LEVEL_RANK002" , 0x1180088000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"LMC0_READ_LEVEL_RANK003" , 0x1180088000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"LMC0_RODT_COMP_CTL" , 0x11800880000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"MIO_BOOT_PIN_DEFS" , 0x11800000000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"MIO_NDF_DMA_CFG" , 0x1180000000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"MIO_NDF_DMA_INT" , 0x1180000000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"MIO_NDF_DMA_INT_EN" , 0x1180000000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"MIO_UART2_DLH" , 0x1180000000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"MIO_UART2_DLL" , 0x1180000000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"MIO_UART2_FAR" , 0x1180000000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"MIO_UART2_FCR" , 0x1180000000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"MIO_UART2_HTX" , 0x1180000000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"MIO_UART2_IER" , 0x1180000000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"MIO_UART2_IIR" , 0x1180000000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"MIO_UART2_LCR" , 0x1180000000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"MIO_UART2_LSR" , 0x1180000000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"MIO_UART2_MCR" , 0x1180000000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"MIO_UART2_MSR" , 0x1180000000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"MIO_UART2_RBR" , 0x1180000000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"MIO_UART2_RFL" , 0x1180000000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"MIO_UART2_RFW" , 0x1180000000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"MIO_UART2_SBCR" , 0x1180000000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"MIO_UART2_SCR" , 0x1180000000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"MIO_UART2_SFE" , 0x1180000000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"MIO_UART2_SRR" , 0x1180000000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"MIO_UART2_SRT" , 0x1180000000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"MIO_UART2_SRTS" , 0x1180000000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"MIO_UART2_STT" , 0x1180000000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"MIO_UART2_TFL" , 0x1180000000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"MIO_UART2_TFR" , 0x1180000000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"MIO_UART2_THR" , 0x1180000000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"MIO_UART2_USR" , 0x1180000000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 417},
- {"MIX1_BIST" , 0x1070000100878ull, CVMX_CSR_DB_TYPE_NCB, 64, 417},
- {"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 418},
- {"MIX1_CTL" , 0x1070000100820ull, CVMX_CSR_DB_TYPE_NCB, 64, 418},
- {"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 419},
- {"MIX1_INTENA" , 0x1070000100850ull, CVMX_CSR_DB_TYPE_NCB, 64, 419},
- {"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 420},
- {"MIX1_IRCNT" , 0x1070000100830ull, CVMX_CSR_DB_TYPE_NCB, 64, 420},
- {"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 421},
- {"MIX1_IRHWM" , 0x1070000100828ull, CVMX_CSR_DB_TYPE_NCB, 64, 421},
- {"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 422},
- {"MIX1_IRING1" , 0x1070000100810ull, CVMX_CSR_DB_TYPE_NCB, 64, 422},
- {"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 423},
- {"MIX1_IRING2" , 0x1070000100818ull, CVMX_CSR_DB_TYPE_NCB, 64, 423},
- {"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 424},
- {"MIX1_ISR" , 0x1070000100848ull, CVMX_CSR_DB_TYPE_NCB, 64, 424},
- {"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 425},
- {"MIX1_ORCNT" , 0x1070000100840ull, CVMX_CSR_DB_TYPE_NCB, 64, 425},
- {"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 426},
- {"MIX1_ORHWM" , 0x1070000100838ull, CVMX_CSR_DB_TYPE_NCB, 64, 426},
- {"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 427},
- {"MIX1_ORING1" , 0x1070000100800ull, CVMX_CSR_DB_TYPE_NCB, 64, 427},
- {"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 428},
- {"MIX1_ORING2" , 0x1070000100808ull, CVMX_CSR_DB_TYPE_NCB, 64, 428},
- {"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 429},
- {"MIX1_REMCNT" , 0x1070000100858ull, CVMX_CSR_DB_TYPE_NCB, 64, 429},
- {"NDF_BT_PG_INFO" , 0x1070001000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 430},
- {"NDF_CMD" , 0x1070001000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 431},
- {"NDF_DRBELL" , 0x1070001000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 432},
- {"NDF_ECC_CNT" , 0x1070001000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 433},
- {"NDF_INT" , 0x1070001000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 434},
- {"NDF_INT_EN" , 0x1070001000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 435},
- {"NDF_MISC" , 0x1070001000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 436},
- {"NDF_ST_REG" , 0x1070001000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 437},
- {"NPEI_BAR1_INDEX0" , 0x11f0000008000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX1" , 0x11f0000008010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX2" , 0x11f0000008020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX3" , 0x11f0000008030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX4" , 0x11f0000008040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX5" , 0x11f0000008050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX6" , 0x11f0000008060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX7" , 0x11f0000008070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX8" , 0x11f0000008080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX9" , 0x11f0000008090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX10" , 0x11f00000080a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX11" , 0x11f00000080b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX12" , 0x11f00000080c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX13" , 0x11f00000080d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX14" , 0x11f00000080e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX15" , 0x11f00000080f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX16" , 0x11f0000008100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX17" , 0x11f0000008110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX18" , 0x11f0000008120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX19" , 0x11f0000008130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX20" , 0x11f0000008140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX21" , 0x11f0000008150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX22" , 0x11f0000008160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX23" , 0x11f0000008170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX24" , 0x11f0000008180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX25" , 0x11f0000008190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX26" , 0x11f00000081a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX27" , 0x11f00000081b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX28" , 0x11f00000081c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX29" , 0x11f00000081d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX30" , 0x11f00000081e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BAR1_INDEX31" , 0x11f00000081f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
- {"NPEI_BIST_STATUS" , 0x11f0000008580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 439},
- {"NPEI_BIST_STATUS2" , 0x11f0000008680ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 440},
- {"NPEI_CTL_PORT0" , 0x11f0000008250ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 441},
- {"NPEI_CTL_PORT1" , 0x11f0000008260ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 442},
- {"NPEI_CTL_STATUS" , 0x11f0000008570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 443},
- {"NPEI_CTL_STATUS2" , 0x11f000000bc00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
- {"NPEI_DATA_OUT_CNT" , 0x11f00000085f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 445},
- {"NPEI_DBG_DATA" , 0x11f0000008510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 446},
- {"NPEI_DBG_SELECT" , 0x11f0000008500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 447},
- {"NPEI_DMA0_COUNTS" , 0x11f0000008450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
- {"NPEI_DMA1_COUNTS" , 0x11f0000008460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
- {"NPEI_DMA2_COUNTS" , 0x11f0000008470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
- {"NPEI_DMA3_COUNTS" , 0x11f0000008480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
- {"NPEI_DMA4_COUNTS" , 0x11f0000008490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
- {"NPEI_DMA0_DBELL" , 0x11f00000083b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 449},
- {"NPEI_DMA1_DBELL" , 0x11f00000083c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 449},
- {"NPEI_DMA2_DBELL" , 0x11f00000083d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 449},
- {"NPEI_DMA3_DBELL" , 0x11f00000083e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 449},
- {"NPEI_DMA4_DBELL" , 0x11f00000083f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 449},
- {"NPEI_DMA0_IBUFF_SADDR" , 0x11f0000008400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
- {"NPEI_DMA1_IBUFF_SADDR" , 0x11f0000008410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
- {"NPEI_DMA2_IBUFF_SADDR" , 0x11f0000008420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
- {"NPEI_DMA3_IBUFF_SADDR" , 0x11f0000008430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
- {"NPEI_DMA4_IBUFF_SADDR" , 0x11f0000008440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
- {"NPEI_DMA0_NADDR" , 0x11f00000084a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
- {"NPEI_DMA1_NADDR" , 0x11f00000084b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
- {"NPEI_DMA2_NADDR" , 0x11f00000084c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
- {"NPEI_DMA3_NADDR" , 0x11f00000084d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
- {"NPEI_DMA4_NADDR" , 0x11f00000084e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
- {"NPEI_DMA0_INT_LEVEL" , 0x11f00000085c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 452},
- {"NPEI_DMA1_INT_LEVEL" , 0x11f00000085d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 453},
- {"NPEI_DMA_CNTS" , 0x11f00000085e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 454},
- {"NPEI_DMA_CONTROL" , 0x11f00000083a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
- {"NPEI_DMA_PCIE_REQ_NUM" , 0x11f00000085b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 456},
- {"NPEI_DMA_STATE1" , 0x11f00000086c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 457},
- {"NPEI_DMA_STATE2" , 0x11f00000086d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 458},
- {"NPEI_INT_A_ENB" , 0x11f0000008560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 459},
- {"NPEI_INT_A_ENB2" , 0x11f000000bce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 460},
- {"NPEI_INT_A_SUM" , 0x11f0000008550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 461},
- {"NPEI_INT_ENB" , 0x11f0000008540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 462},
- {"NPEI_INT_ENB2" , 0x11f000000bcd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 463},
- {"NPEI_INT_INFO" , 0x11f0000008590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 464},
- {"NPEI_INT_SUM" , 0x11f0000008530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 465},
- {"NPEI_INT_SUM2" , 0x11f000000bcc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 466},
- {"NPEI_LAST_WIN_RDATA0" , 0x11f0000008600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 467},
- {"NPEI_LAST_WIN_RDATA1" , 0x11f0000008610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 468},
- {"NPEI_MEM_ACCESS_CTL" , 0x11f00000084f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 469},
- {"NPEI_MEM_ACCESS_SUBID12" , 0x11f0000008280ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID13" , 0x11f0000008290ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID14" , 0x11f00000082a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID15" , 0x11f00000082b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID16" , 0x11f00000082c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID17" , 0x11f00000082d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID18" , 0x11f00000082e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID19" , 0x11f00000082f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID20" , 0x11f0000008300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID21" , 0x11f0000008310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID22" , 0x11f0000008320ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID23" , 0x11f0000008330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID24" , 0x11f0000008340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID25" , 0x11f0000008350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID26" , 0x11f0000008360ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MEM_ACCESS_SUBID27" , 0x11f0000008370ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
- {"NPEI_MSI_ENB0" , 0x11f000000bc50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 471},
- {"NPEI_MSI_ENB1" , 0x11f000000bc60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 472},
- {"NPEI_MSI_ENB2" , 0x11f000000bc70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 473},
- {"NPEI_MSI_ENB3" , 0x11f000000bc80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 474},
- {"NPEI_MSI_RCV0" , 0x11f000000bc10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 475},
- {"NPEI_MSI_RCV1" , 0x11f000000bc20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 476},
- {"NPEI_MSI_RCV2" , 0x11f000000bc30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 477},
- {"NPEI_MSI_RCV3" , 0x11f000000bc40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 478},
- {"NPEI_MSI_RD_MAP" , 0x11f000000bca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
- {"NPEI_MSI_W1C_ENB0" , 0x11f000000bcf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
- {"NPEI_MSI_W1C_ENB1" , 0x11f000000bd00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
- {"NPEI_MSI_W1C_ENB2" , 0x11f000000bd10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
- {"NPEI_MSI_W1C_ENB3" , 0x11f000000bd20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
- {"NPEI_MSI_W1S_ENB0" , 0x11f000000bd30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
- {"NPEI_MSI_W1S_ENB1" , 0x11f000000bd40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
- {"NPEI_MSI_W1S_ENB2" , 0x11f000000bd50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
- {"NPEI_MSI_W1S_ENB3" , 0x11f000000bd60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
- {"NPEI_MSI_WR_MAP" , 0x11f000000bc90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 488},
- {"NPEI_PCIE_CREDIT_CNT" , 0x11f000000bd70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 489},
- {"NPEI_PCIE_MSI_RCV" , 0x11f000000bcb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 490},
- {"NPEI_PCIE_MSI_RCV_B1" , 0x11f0000008650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 491},
- {"NPEI_PCIE_MSI_RCV_B2" , 0x11f0000008660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 492},
- {"NPEI_PCIE_MSI_RCV_B3" , 0x11f0000008670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 493},
- {"NPEI_PKT0_CNTS" , 0x11f000000a400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT1_CNTS" , 0x11f000000a410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT2_CNTS" , 0x11f000000a420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT3_CNTS" , 0x11f000000a430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT4_CNTS" , 0x11f000000a440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT5_CNTS" , 0x11f000000a450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT6_CNTS" , 0x11f000000a460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT7_CNTS" , 0x11f000000a470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT8_CNTS" , 0x11f000000a480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT9_CNTS" , 0x11f000000a490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT10_CNTS" , 0x11f000000a4a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT11_CNTS" , 0x11f000000a4b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT12_CNTS" , 0x11f000000a4c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT13_CNTS" , 0x11f000000a4d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT14_CNTS" , 0x11f000000a4e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT15_CNTS" , 0x11f000000a4f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT16_CNTS" , 0x11f000000a500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT17_CNTS" , 0x11f000000a510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT18_CNTS" , 0x11f000000a520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT19_CNTS" , 0x11f000000a530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT20_CNTS" , 0x11f000000a540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT21_CNTS" , 0x11f000000a550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT22_CNTS" , 0x11f000000a560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT23_CNTS" , 0x11f000000a570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT24_CNTS" , 0x11f000000a580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT25_CNTS" , 0x11f000000a590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT26_CNTS" , 0x11f000000a5a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT27_CNTS" , 0x11f000000a5b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT28_CNTS" , 0x11f000000a5c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT29_CNTS" , 0x11f000000a5d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT30_CNTS" , 0x11f000000a5e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT31_CNTS" , 0x11f000000a5f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
- {"NPEI_PKT0_IN_BP" , 0x11f000000b800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT1_IN_BP" , 0x11f000000b810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT2_IN_BP" , 0x11f000000b820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT3_IN_BP" , 0x11f000000b830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT4_IN_BP" , 0x11f000000b840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT5_IN_BP" , 0x11f000000b850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT6_IN_BP" , 0x11f000000b860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT7_IN_BP" , 0x11f000000b870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT8_IN_BP" , 0x11f000000b880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT9_IN_BP" , 0x11f000000b890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT10_IN_BP" , 0x11f000000b8a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT11_IN_BP" , 0x11f000000b8b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT12_IN_BP" , 0x11f000000b8c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT13_IN_BP" , 0x11f000000b8d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT14_IN_BP" , 0x11f000000b8e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT15_IN_BP" , 0x11f000000b8f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT16_IN_BP" , 0x11f000000b900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT17_IN_BP" , 0x11f000000b910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT18_IN_BP" , 0x11f000000b920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT19_IN_BP" , 0x11f000000b930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT20_IN_BP" , 0x11f000000b940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT21_IN_BP" , 0x11f000000b950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT22_IN_BP" , 0x11f000000b960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT23_IN_BP" , 0x11f000000b970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT24_IN_BP" , 0x11f000000b980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT25_IN_BP" , 0x11f000000b990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT26_IN_BP" , 0x11f000000b9a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT27_IN_BP" , 0x11f000000b9b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT28_IN_BP" , 0x11f000000b9c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT29_IN_BP" , 0x11f000000b9d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT30_IN_BP" , 0x11f000000b9e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT31_IN_BP" , 0x11f000000b9f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
- {"NPEI_PKT0_INSTR_BADDR" , 0x11f000000a800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT1_INSTR_BADDR" , 0x11f000000a810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT2_INSTR_BADDR" , 0x11f000000a820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT3_INSTR_BADDR" , 0x11f000000a830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT4_INSTR_BADDR" , 0x11f000000a840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT5_INSTR_BADDR" , 0x11f000000a850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT6_INSTR_BADDR" , 0x11f000000a860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT7_INSTR_BADDR" , 0x11f000000a870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT8_INSTR_BADDR" , 0x11f000000a880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT9_INSTR_BADDR" , 0x11f000000a890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT10_INSTR_BADDR" , 0x11f000000a8a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT11_INSTR_BADDR" , 0x11f000000a8b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT12_INSTR_BADDR" , 0x11f000000a8c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT13_INSTR_BADDR" , 0x11f000000a8d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT14_INSTR_BADDR" , 0x11f000000a8e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT15_INSTR_BADDR" , 0x11f000000a8f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT16_INSTR_BADDR" , 0x11f000000a900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT17_INSTR_BADDR" , 0x11f000000a910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT18_INSTR_BADDR" , 0x11f000000a920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT19_INSTR_BADDR" , 0x11f000000a930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT20_INSTR_BADDR" , 0x11f000000a940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT21_INSTR_BADDR" , 0x11f000000a950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT22_INSTR_BADDR" , 0x11f000000a960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT23_INSTR_BADDR" , 0x11f000000a970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT24_INSTR_BADDR" , 0x11f000000a980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT25_INSTR_BADDR" , 0x11f000000a990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT26_INSTR_BADDR" , 0x11f000000a9a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT27_INSTR_BADDR" , 0x11f000000a9b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT28_INSTR_BADDR" , 0x11f000000a9c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT29_INSTR_BADDR" , 0x11f000000a9d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT30_INSTR_BADDR" , 0x11f000000a9e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT31_INSTR_BADDR" , 0x11f000000a9f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
- {"NPEI_PKT0_INSTR_BAOFF_DBELL" , 0x11f000000ac00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT1_INSTR_BAOFF_DBELL" , 0x11f000000ac10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT2_INSTR_BAOFF_DBELL" , 0x11f000000ac20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT3_INSTR_BAOFF_DBELL" , 0x11f000000ac30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT4_INSTR_BAOFF_DBELL" , 0x11f000000ac40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT5_INSTR_BAOFF_DBELL" , 0x11f000000ac50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT6_INSTR_BAOFF_DBELL" , 0x11f000000ac60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT7_INSTR_BAOFF_DBELL" , 0x11f000000ac70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT8_INSTR_BAOFF_DBELL" , 0x11f000000ac80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT9_INSTR_BAOFF_DBELL" , 0x11f000000ac90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT10_INSTR_BAOFF_DBELL", 0x11f000000aca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT11_INSTR_BAOFF_DBELL", 0x11f000000acb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT12_INSTR_BAOFF_DBELL", 0x11f000000acc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT13_INSTR_BAOFF_DBELL", 0x11f000000acd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT14_INSTR_BAOFF_DBELL", 0x11f000000ace0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT15_INSTR_BAOFF_DBELL", 0x11f000000acf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT16_INSTR_BAOFF_DBELL", 0x11f000000ad00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT17_INSTR_BAOFF_DBELL", 0x11f000000ad10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT18_INSTR_BAOFF_DBELL", 0x11f000000ad20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT19_INSTR_BAOFF_DBELL", 0x11f000000ad30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT20_INSTR_BAOFF_DBELL", 0x11f000000ad40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT21_INSTR_BAOFF_DBELL", 0x11f000000ad50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT22_INSTR_BAOFF_DBELL", 0x11f000000ad60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT23_INSTR_BAOFF_DBELL", 0x11f000000ad70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT24_INSTR_BAOFF_DBELL", 0x11f000000ad80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT25_INSTR_BAOFF_DBELL", 0x11f000000ad90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT26_INSTR_BAOFF_DBELL", 0x11f000000ada0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT27_INSTR_BAOFF_DBELL", 0x11f000000adb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT28_INSTR_BAOFF_DBELL", 0x11f000000adc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT29_INSTR_BAOFF_DBELL", 0x11f000000add0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT30_INSTR_BAOFF_DBELL", 0x11f000000ade0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT31_INSTR_BAOFF_DBELL", 0x11f000000adf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
- {"NPEI_PKT0_INSTR_FIFO_RSIZE" , 0x11f000000b000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT1_INSTR_FIFO_RSIZE" , 0x11f000000b010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT2_INSTR_FIFO_RSIZE" , 0x11f000000b020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT3_INSTR_FIFO_RSIZE" , 0x11f000000b030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT4_INSTR_FIFO_RSIZE" , 0x11f000000b040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT5_INSTR_FIFO_RSIZE" , 0x11f000000b050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT6_INSTR_FIFO_RSIZE" , 0x11f000000b060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT7_INSTR_FIFO_RSIZE" , 0x11f000000b070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT8_INSTR_FIFO_RSIZE" , 0x11f000000b080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT9_INSTR_FIFO_RSIZE" , 0x11f000000b090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT10_INSTR_FIFO_RSIZE" , 0x11f000000b0a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT11_INSTR_FIFO_RSIZE" , 0x11f000000b0b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT12_INSTR_FIFO_RSIZE" , 0x11f000000b0c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT13_INSTR_FIFO_RSIZE" , 0x11f000000b0d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT14_INSTR_FIFO_RSIZE" , 0x11f000000b0e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT15_INSTR_FIFO_RSIZE" , 0x11f000000b0f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT16_INSTR_FIFO_RSIZE" , 0x11f000000b100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT17_INSTR_FIFO_RSIZE" , 0x11f000000b110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT18_INSTR_FIFO_RSIZE" , 0x11f000000b120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT19_INSTR_FIFO_RSIZE" , 0x11f000000b130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT20_INSTR_FIFO_RSIZE" , 0x11f000000b140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT21_INSTR_FIFO_RSIZE" , 0x11f000000b150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT22_INSTR_FIFO_RSIZE" , 0x11f000000b160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT23_INSTR_FIFO_RSIZE" , 0x11f000000b170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT24_INSTR_FIFO_RSIZE" , 0x11f000000b180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT25_INSTR_FIFO_RSIZE" , 0x11f000000b190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT26_INSTR_FIFO_RSIZE" , 0x11f000000b1a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT27_INSTR_FIFO_RSIZE" , 0x11f000000b1b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT28_INSTR_FIFO_RSIZE" , 0x11f000000b1c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT29_INSTR_FIFO_RSIZE" , 0x11f000000b1d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT30_INSTR_FIFO_RSIZE" , 0x11f000000b1e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT31_INSTR_FIFO_RSIZE" , 0x11f000000b1f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
- {"NPEI_PKT0_INSTR_HEADER" , 0x11f000000b400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT1_INSTR_HEADER" , 0x11f000000b410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT2_INSTR_HEADER" , 0x11f000000b420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT3_INSTR_HEADER" , 0x11f000000b430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT4_INSTR_HEADER" , 0x11f000000b440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT5_INSTR_HEADER" , 0x11f000000b450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT6_INSTR_HEADER" , 0x11f000000b460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT7_INSTR_HEADER" , 0x11f000000b470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT8_INSTR_HEADER" , 0x11f000000b480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT9_INSTR_HEADER" , 0x11f000000b490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT10_INSTR_HEADER" , 0x11f000000b4a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT11_INSTR_HEADER" , 0x11f000000b4b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT12_INSTR_HEADER" , 0x11f000000b4c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT13_INSTR_HEADER" , 0x11f000000b4d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT14_INSTR_HEADER" , 0x11f000000b4e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT15_INSTR_HEADER" , 0x11f000000b4f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT16_INSTR_HEADER" , 0x11f000000b500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT17_INSTR_HEADER" , 0x11f000000b510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT18_INSTR_HEADER" , 0x11f000000b520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT19_INSTR_HEADER" , 0x11f000000b530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT20_INSTR_HEADER" , 0x11f000000b540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT21_INSTR_HEADER" , 0x11f000000b550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT22_INSTR_HEADER" , 0x11f000000b560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT23_INSTR_HEADER" , 0x11f000000b570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT24_INSTR_HEADER" , 0x11f000000b580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT25_INSTR_HEADER" , 0x11f000000b590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT26_INSTR_HEADER" , 0x11f000000b5a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT27_INSTR_HEADER" , 0x11f000000b5b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT28_INSTR_HEADER" , 0x11f000000b5c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT29_INSTR_HEADER" , 0x11f000000b5d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT30_INSTR_HEADER" , 0x11f000000b5e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT31_INSTR_HEADER" , 0x11f000000b5f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
- {"NPEI_PKT0_SLIST_BADDR" , 0x11f0000009400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT1_SLIST_BADDR" , 0x11f0000009410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT2_SLIST_BADDR" , 0x11f0000009420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT3_SLIST_BADDR" , 0x11f0000009430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT4_SLIST_BADDR" , 0x11f0000009440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT5_SLIST_BADDR" , 0x11f0000009450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT6_SLIST_BADDR" , 0x11f0000009460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT7_SLIST_BADDR" , 0x11f0000009470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT8_SLIST_BADDR" , 0x11f0000009480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT9_SLIST_BADDR" , 0x11f0000009490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT10_SLIST_BADDR" , 0x11f00000094a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT11_SLIST_BADDR" , 0x11f00000094b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT12_SLIST_BADDR" , 0x11f00000094c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT13_SLIST_BADDR" , 0x11f00000094d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT14_SLIST_BADDR" , 0x11f00000094e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT15_SLIST_BADDR" , 0x11f00000094f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT16_SLIST_BADDR" , 0x11f0000009500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT17_SLIST_BADDR" , 0x11f0000009510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT18_SLIST_BADDR" , 0x11f0000009520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT19_SLIST_BADDR" , 0x11f0000009530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT20_SLIST_BADDR" , 0x11f0000009540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT21_SLIST_BADDR" , 0x11f0000009550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT22_SLIST_BADDR" , 0x11f0000009560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT23_SLIST_BADDR" , 0x11f0000009570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT24_SLIST_BADDR" , 0x11f0000009580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT25_SLIST_BADDR" , 0x11f0000009590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT26_SLIST_BADDR" , 0x11f00000095a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT27_SLIST_BADDR" , 0x11f00000095b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT28_SLIST_BADDR" , 0x11f00000095c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT29_SLIST_BADDR" , 0x11f00000095d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT30_SLIST_BADDR" , 0x11f00000095e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT31_SLIST_BADDR" , 0x11f00000095f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
- {"NPEI_PKT0_SLIST_BAOFF_DBELL" , 0x11f0000009800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT1_SLIST_BAOFF_DBELL" , 0x11f0000009810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT2_SLIST_BAOFF_DBELL" , 0x11f0000009820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT3_SLIST_BAOFF_DBELL" , 0x11f0000009830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT4_SLIST_BAOFF_DBELL" , 0x11f0000009840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT5_SLIST_BAOFF_DBELL" , 0x11f0000009850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT6_SLIST_BAOFF_DBELL" , 0x11f0000009860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT7_SLIST_BAOFF_DBELL" , 0x11f0000009870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT8_SLIST_BAOFF_DBELL" , 0x11f0000009880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT9_SLIST_BAOFF_DBELL" , 0x11f0000009890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT10_SLIST_BAOFF_DBELL", 0x11f00000098a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT11_SLIST_BAOFF_DBELL", 0x11f00000098b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT12_SLIST_BAOFF_DBELL", 0x11f00000098c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT13_SLIST_BAOFF_DBELL", 0x11f00000098d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT14_SLIST_BAOFF_DBELL", 0x11f00000098e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT15_SLIST_BAOFF_DBELL", 0x11f00000098f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT16_SLIST_BAOFF_DBELL", 0x11f0000009900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT17_SLIST_BAOFF_DBELL", 0x11f0000009910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT18_SLIST_BAOFF_DBELL", 0x11f0000009920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT19_SLIST_BAOFF_DBELL", 0x11f0000009930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT20_SLIST_BAOFF_DBELL", 0x11f0000009940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT21_SLIST_BAOFF_DBELL", 0x11f0000009950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT22_SLIST_BAOFF_DBELL", 0x11f0000009960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT23_SLIST_BAOFF_DBELL", 0x11f0000009970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT24_SLIST_BAOFF_DBELL", 0x11f0000009980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT25_SLIST_BAOFF_DBELL", 0x11f0000009990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT26_SLIST_BAOFF_DBELL", 0x11f00000099a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT27_SLIST_BAOFF_DBELL", 0x11f00000099b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT28_SLIST_BAOFF_DBELL", 0x11f00000099c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT29_SLIST_BAOFF_DBELL", 0x11f00000099d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT30_SLIST_BAOFF_DBELL", 0x11f00000099e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT31_SLIST_BAOFF_DBELL", 0x11f00000099f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
- {"NPEI_PKT0_SLIST_FIFO_RSIZE" , 0x11f0000009c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT1_SLIST_FIFO_RSIZE" , 0x11f0000009c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT2_SLIST_FIFO_RSIZE" , 0x11f0000009c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT3_SLIST_FIFO_RSIZE" , 0x11f0000009c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT4_SLIST_FIFO_RSIZE" , 0x11f0000009c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT5_SLIST_FIFO_RSIZE" , 0x11f0000009c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT6_SLIST_FIFO_RSIZE" , 0x11f0000009c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT7_SLIST_FIFO_RSIZE" , 0x11f0000009c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT8_SLIST_FIFO_RSIZE" , 0x11f0000009c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT9_SLIST_FIFO_RSIZE" , 0x11f0000009c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT10_SLIST_FIFO_RSIZE" , 0x11f0000009ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT11_SLIST_FIFO_RSIZE" , 0x11f0000009cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT12_SLIST_FIFO_RSIZE" , 0x11f0000009cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT13_SLIST_FIFO_RSIZE" , 0x11f0000009cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT14_SLIST_FIFO_RSIZE" , 0x11f0000009ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT15_SLIST_FIFO_RSIZE" , 0x11f0000009cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT16_SLIST_FIFO_RSIZE" , 0x11f0000009d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT17_SLIST_FIFO_RSIZE" , 0x11f0000009d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT18_SLIST_FIFO_RSIZE" , 0x11f0000009d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT19_SLIST_FIFO_RSIZE" , 0x11f0000009d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT20_SLIST_FIFO_RSIZE" , 0x11f0000009d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT21_SLIST_FIFO_RSIZE" , 0x11f0000009d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT22_SLIST_FIFO_RSIZE" , 0x11f0000009d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT23_SLIST_FIFO_RSIZE" , 0x11f0000009d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT24_SLIST_FIFO_RSIZE" , 0x11f0000009d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT25_SLIST_FIFO_RSIZE" , 0x11f0000009d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT26_SLIST_FIFO_RSIZE" , 0x11f0000009da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT27_SLIST_FIFO_RSIZE" , 0x11f0000009db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT28_SLIST_FIFO_RSIZE" , 0x11f0000009dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT29_SLIST_FIFO_RSIZE" , 0x11f0000009dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT30_SLIST_FIFO_RSIZE" , 0x11f0000009de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT31_SLIST_FIFO_RSIZE" , 0x11f0000009df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
- {"NPEI_PKT_CNT_INT" , 0x11f0000009110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 503},
- {"NPEI_PKT_CNT_INT_ENB" , 0x11f0000009130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 504},
- {"NPEI_PKT_DATA_OUT_ES" , 0x11f00000090b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 505},
- {"NPEI_PKT_DATA_OUT_NS" , 0x11f00000090a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 506},
- {"NPEI_PKT_DATA_OUT_ROR" , 0x11f0000009090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 507},
- {"NPEI_PKT_DPADDR" , 0x11f0000009080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 508},
- {"NPEI_PKT_IN_BP" , 0x11f00000086b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 509},
- {"NPEI_PKT_IN_DONE0_CNTS" , 0x11f000000a000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE1_CNTS" , 0x11f000000a010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE2_CNTS" , 0x11f000000a020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE3_CNTS" , 0x11f000000a030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE4_CNTS" , 0x11f000000a040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE5_CNTS" , 0x11f000000a050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE6_CNTS" , 0x11f000000a060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE7_CNTS" , 0x11f000000a070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE8_CNTS" , 0x11f000000a080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE9_CNTS" , 0x11f000000a090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE10_CNTS" , 0x11f000000a0a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE11_CNTS" , 0x11f000000a0b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE12_CNTS" , 0x11f000000a0c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE13_CNTS" , 0x11f000000a0d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE14_CNTS" , 0x11f000000a0e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE15_CNTS" , 0x11f000000a0f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE16_CNTS" , 0x11f000000a100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE17_CNTS" , 0x11f000000a110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE18_CNTS" , 0x11f000000a120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE19_CNTS" , 0x11f000000a130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE20_CNTS" , 0x11f000000a140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE21_CNTS" , 0x11f000000a150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE22_CNTS" , 0x11f000000a160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE23_CNTS" , 0x11f000000a170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE24_CNTS" , 0x11f000000a180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE25_CNTS" , 0x11f000000a190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE26_CNTS" , 0x11f000000a1a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE27_CNTS" , 0x11f000000a1b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE28_CNTS" , 0x11f000000a1c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE29_CNTS" , 0x11f000000a1d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE30_CNTS" , 0x11f000000a1e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_DONE31_CNTS" , 0x11f000000a1f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
- {"NPEI_PKT_IN_INSTR_COUNTS" , 0x11f00000086a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 511},
- {"NPEI_PKT_IN_PCIE_PORT" , 0x11f00000091a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 512},
- {"NPEI_PKT_INPUT_CONTROL" , 0x11f0000009150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 513},
- {"NPEI_PKT_INSTR_ENB" , 0x11f0000009000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 514},
- {"NPEI_PKT_INSTR_RD_SIZE" , 0x11f0000009190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 515},
- {"NPEI_PKT_INSTR_SIZE" , 0x11f0000009020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 516},
- {"NPEI_PKT_INT_LEVELS" , 0x11f0000009100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 517},
- {"NPEI_PKT_IPTR" , 0x11f0000009070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 518},
- {"NPEI_PKT_OUT_BMODE" , 0x11f00000090d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 519},
- {"NPEI_PKT_OUT_ENB" , 0x11f0000009010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 520},
- {"NPEI_PKT_OUTPUT_WMARK" , 0x11f0000009160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 521},
- {"NPEI_PKT_PCIE_PORT" , 0x11f00000090e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 522},
- {"NPEI_PKT_PORT_IN_RST" , 0x11f0000008690ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 523},
- {"NPEI_PKT_SLIST_ES" , 0x11f0000009050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 524},
- {"NPEI_PKT_SLIST_ID_SIZE" , 0x11f0000009180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 525},
- {"NPEI_PKT_SLIST_NS" , 0x11f0000009040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 526},
- {"NPEI_PKT_SLIST_ROR" , 0x11f0000009030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 527},
- {"NPEI_PKT_TIME_INT" , 0x11f0000009120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 528},
- {"NPEI_PKT_TIME_INT_ENB" , 0x11f0000009140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 529},
- {"NPEI_RSL_INT_BLOCKS" , 0x11f0000008520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 530},
- {"NPEI_SCRATCH_1" , 0x11f0000008270ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 531},
- {"NPEI_STATE1" , 0x11f0000008620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 532},
- {"NPEI_STATE2" , 0x11f0000008630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 533},
- {"NPEI_STATE3" , 0x11f0000008640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 534},
- {"NPEI_WIN_RD_ADDR" , 0x210ull, CVMX_CSR_DB_TYPE_PEXP, 64, 535},
- {"NPEI_WIN_RD_DATA" , 0x240ull, CVMX_CSR_DB_TYPE_PEXP, 64, 536},
- {"NPEI_WIN_WR_ADDR" , 0x200ull, CVMX_CSR_DB_TYPE_PEXP, 64, 537},
- {"NPEI_WIN_WR_DATA" , 0x220ull, CVMX_CSR_DB_TYPE_PEXP, 64, 538},
- {"NPEI_WIN_WR_MASK" , 0x230ull, CVMX_CSR_DB_TYPE_PEXP, 64, 539},
- {"NPEI_WINDOW_CTL" , 0x11f0000008380ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 540},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 541},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 542},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 543},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 544},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 545},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 546},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 547},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 548},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 549},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 550},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 551},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 552},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 553},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 554},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 555},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 556},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 557},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 558},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 559},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 560},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 561},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 562},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 563},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 564},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 565},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 566},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 567},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 568},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 569},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 570},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 571},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 572},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 573},
- {"PCIEEP0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 574},
- {"PCIEEP0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 575},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 576},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 577},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 578},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 579},
- {"PCIEEP0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 580},
- {"PCIEEP0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 581},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 582},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 583},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 584},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 585},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 586},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 587},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 588},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 589},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 590},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 591},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 592},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 593},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 594},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 595},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 596},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 597},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 598},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 599},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 600},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 601},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 602},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 603},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 604},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 605},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 606},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 607},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 608},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 609},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 610},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 611},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 612},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 613},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 614},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 615},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 616},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 617},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 623},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 623},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 624},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 624},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 625},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 625},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 626},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 626},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 627},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 627},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 628},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 628},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS0_AN002_ADV_REG" , 0x11800b0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS0_AN003_ADV_REG" , 0x11800b0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS0_AN002_EXT_ST_REG" , 0x11800b0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS0_AN003_EXT_ST_REG" , 0x11800b0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PCS0_AN002_LP_ABIL_REG" , 0x11800b0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PCS0_AN003_LP_ABIL_REG" , 0x11800b0001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PCS0_AN002_RESULTS_REG" , 0x11800b0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PCS0_AN003_RESULTS_REG" , 0x11800b0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PCS0_INT002_EN_REG" , 0x11800b0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PCS0_INT003_EN_REG" , 0x11800b0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PCS0_INT002_REG" , 0x11800b0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PCS0_INT003_REG" , 0x11800b0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PCS0_LINK002_TIMER_COUNT_REG", 0x11800b0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PCS0_LINK003_TIMER_COUNT_REG", 0x11800b0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PCS0_LOG_ANL002_REG" , 0x11800b0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PCS0_LOG_ANL003_REG" , 0x11800b0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PCS0_MISC002_CTL_REG" , 0x11800b0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PCS0_MISC003_CTL_REG" , 0x11800b0001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PCS0_MR002_CONTROL_REG" , 0x11800b0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PCS0_MR003_CONTROL_REG" , 0x11800b0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PCS0_MR002_STATUS_REG" , 0x11800b0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PCS0_MR003_STATUS_REG" , 0x11800b0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PCS0_RX002_STATES_REG" , 0x11800b0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PCS0_RX003_STATES_REG" , 0x11800b0001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_RX002_SYNC_REG" , 0x11800b0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_RX003_SYNC_REG" , 0x11800b0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_SGM002_AN_ADV_REG" , 0x11800b0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_SGM003_AN_ADV_REG" , 0x11800b0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_SGM002_LP_ADV_REG" , 0x11800b0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_SGM003_LP_ADV_REG" , 0x11800b0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_TX002_STATES_REG" , 0x11800b0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_TX003_STATES_REG" , 0x11800b0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_TX_RX002_POLARITY_REG" , 0x11800b0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_TX_RX003_POLARITY_REG" , 0x11800b0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCSX0_10GBX_STATUS_REG" , 0x11800b0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PCSX0_BIST_STATUS_REG" , 0x11800b0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800b0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PCSX0_CONTROL1_REG" , 0x11800b0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PCSX0_CONTROL2_REG" , 0x11800b0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"PCSX0_INT_EN_REG" , 0x11800b0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"PCSX0_INT_REG" , 0x11800b0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"PCSX0_LOG_ANL_REG" , 0x11800b0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"PCSX0_MISC_CTL_REG" , 0x11800b0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"PCSX0_RX_SYNC_STATES_REG" , 0x11800b0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"PCSX0_SPD_ABIL_REG" , 0x11800b0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"PCSX0_STATUS1_REG" , 0x11800b0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"PCSX0_STATUS2_REG" , 0x11800b0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
- {"PCSX0_TX_RX_POLARITY_REG" , 0x11800b0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PCSX0_TX_RX_STATES_REG" , 0x11800b0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PESC0_BIST_STATUS" , 0x11800c8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
- {"PESC1_BIST_STATUS" , 0x11800d0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
- {"PESC0_BIST_STATUS2" , 0x11800c8000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
- {"PESC1_BIST_STATUS2" , 0x11800d0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
- {"PESC0_CFG_RD" , 0x11800c8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
- {"PESC1_CFG_RD" , 0x11800d0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
- {"PESC0_CFG_WR" , 0x11800c8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"PESC1_CFG_WR" , 0x11800d0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"PESC0_CPL_LUT_VALID" , 0x11800c8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PESC1_CPL_LUT_VALID" , 0x11800d0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PESC0_CTL_STATUS" , 0x11800c8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
- {"PESC1_CTL_STATUS" , 0x11800d0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
- {"PESC0_CTL_STATUS2" , 0x11800c8000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"PESC1_CTL_STATUS2" , 0x11800d0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"PESC0_DBG_INFO" , 0x11800c8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
- {"PESC1_DBG_INFO" , 0x11800d0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
- {"PESC0_DBG_INFO_EN" , 0x11800c80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
- {"PESC1_DBG_INFO_EN" , 0x11800d00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
- {"PESC0_DIAG_STATUS" , 0x11800c8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
- {"PESC1_DIAG_STATUS" , 0x11800d0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
- {"PESC0_P2N_BAR0_START" , 0x11800c8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
- {"PESC1_P2N_BAR0_START" , 0x11800d0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
- {"PESC0_P2N_BAR1_START" , 0x11800c8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
- {"PESC1_P2N_BAR1_START" , 0x11800d0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
- {"PESC0_P2N_BAR2_START" , 0x11800c8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PESC1_P2N_BAR2_START" , 0x11800d0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PESC0_P2P_BAR000_END" , 0x11800c8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PESC0_P2P_BAR001_END" , 0x11800c8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PESC0_P2P_BAR002_END" , 0x11800c8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PESC0_P2P_BAR003_END" , 0x11800c8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PESC1_P2P_BAR000_END" , 0x11800d0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PESC1_P2P_BAR001_END" , 0x11800d0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PESC1_P2P_BAR002_END" , 0x11800d0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PESC1_P2P_BAR003_END" , 0x11800d0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PESC0_P2P_BAR000_START" , 0x11800c8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PESC0_P2P_BAR001_START" , 0x11800c8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PESC0_P2P_BAR002_START" , 0x11800c8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PESC0_P2P_BAR003_START" , 0x11800c8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PESC1_P2P_BAR000_START" , 0x11800d0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PESC1_P2P_BAR001_START" , 0x11800d0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PESC1_P2P_BAR002_START" , 0x11800d0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PESC1_P2P_BAR003_START" , 0x11800d0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PESC0_TLP_CREDITS" , 0x11800c8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PESC1_TLP_CREDITS" , 0x11800d0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PIP_DSA_SRC_GRP" , 0x11800a0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
- {"PIP_DSA_VID_GRP" , 0x11800a0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_FRM_LEN_CHK1" , 0x11800a0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PIP_HG_PRI_QOS" , 0x11800a00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT36" , 0x11800a0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT37" , 0x11800a0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT38" , 0x11800a00013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT0_PRT39" , 0x11800a0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT36" , 0x11800a0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT37" , 0x11800a0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT38" , 0x11800a00013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT1_PRT39" , 0x11800a0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT36" , 0x11800a0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT37" , 0x11800a00013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT38" , 0x11800a00013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT2_PRT39" , 0x11800a0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT36" , 0x11800a0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT37" , 0x11800a00013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT38" , 0x11800a00013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT3_PRT39" , 0x11800a0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT36" , 0x11800a0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT37" , 0x11800a00013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT38" , 0x11800a0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT4_PRT39" , 0x11800a0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT36" , 0x11800a0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT37" , 0x11800a00013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT38" , 0x11800a0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT5_PRT39" , 0x11800a0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT36" , 0x11800a0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT37" , 0x11800a00013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT38" , 0x11800a0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT6_PRT39" , 0x11800a0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT36" , 0x11800a0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT37" , 0x11800a00013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT38" , 0x11800a0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT7_PRT39" , 0x11800a0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT36" , 0x11800a0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT37" , 0x11800a00013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT38" , 0x11800a0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT8_PRT39" , 0x11800a0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT36" , 0x11800a0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT37" , 0x11800a00013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT38" , 0x11800a0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT9_PRT39" , 0x11800a0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS36" , 0x11800a0001e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS37" , 0x11800a0001eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS38" , 0x11800a0001ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_ERRS39" , 0x11800a0001ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS36" , 0x11800a0001e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS37" , 0x11800a0001ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS38" , 0x11800a0001ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_OCTS39" , 0x11800a0001ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS36" , 0x11800a0001e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS37" , 0x11800a0001ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS38" , 0x11800a0001ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT_INB_PKTS39" , 0x11800a0001ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 812},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 813},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 817},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 818},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
- {"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 822},
- {"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
- {"POW_IQ_THR0" , 0x16700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_IQ_THR1" , 0x16700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_IQ_THR2" , 0x16700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_IQ_THR3" , 0x16700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_IQ_THR4" , 0x16700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_IQ_THR5" , 0x16700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_IQ_THR6" , 0x16700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_IQ_THR7" , 0x16700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 825},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 826},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 827},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 831},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 832},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 834},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 836},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 865},
- {"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 865},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
- {"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
- {"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
- {"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 869},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 870},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 871},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 874},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 875},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 876},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 877},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 878},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 879},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 880},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 883},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 884},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 885},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 886},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 887},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 888},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 889},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 890},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 891},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 893},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 894},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 898},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 899},
- {"USBC0_DAINT" , 0x16f0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 900},
- {"USBC1_DAINT" , 0x17f0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 900},
- {"USBC0_DAINTMSK" , 0x16f001000081cull, CVMX_CSR_DB_TYPE_NCB, 32, 901},
- {"USBC1_DAINTMSK" , 0x17f001000081cull, CVMX_CSR_DB_TYPE_NCB, 32, 901},
- {"USBC0_DCFG" , 0x16f0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 902},
- {"USBC1_DCFG" , 0x17f0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 902},
- {"USBC0_DCTL" , 0x16f0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 903},
- {"USBC1_DCTL" , 0x17f0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 903},
- {"USBC0_DIEPCTL000" , 0x16f0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC0_DIEPCTL001" , 0x16f0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC0_DIEPCTL002" , 0x16f0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC0_DIEPCTL003" , 0x16f0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC0_DIEPCTL004" , 0x16f0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC1_DIEPCTL000" , 0x17f0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC1_DIEPCTL001" , 0x17f0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC1_DIEPCTL002" , 0x17f0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC1_DIEPCTL003" , 0x17f0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC1_DIEPCTL004" , 0x17f0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
- {"USBC0_DIEPINT000" , 0x16f0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC0_DIEPINT001" , 0x16f0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC0_DIEPINT002" , 0x16f0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC0_DIEPINT003" , 0x16f0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC0_DIEPINT004" , 0x16f0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC1_DIEPINT000" , 0x17f0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC1_DIEPINT001" , 0x17f0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC1_DIEPINT002" , 0x17f0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC1_DIEPINT003" , 0x17f0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC1_DIEPINT004" , 0x17f0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
- {"USBC0_DIEPMSK" , 0x16f0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 906},
- {"USBC1_DIEPMSK" , 0x17f0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 906},
- {"USBC0_DIEPTSIZ000" , 0x16f0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC0_DIEPTSIZ001" , 0x16f0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC0_DIEPTSIZ002" , 0x16f0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC0_DIEPTSIZ003" , 0x16f0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC0_DIEPTSIZ004" , 0x16f0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC1_DIEPTSIZ000" , 0x17f0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC1_DIEPTSIZ001" , 0x17f0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC1_DIEPTSIZ002" , 0x17f0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC1_DIEPTSIZ003" , 0x17f0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC1_DIEPTSIZ004" , 0x17f0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
- {"USBC0_DOEPCTL000" , 0x16f0010000b00ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC0_DOEPCTL001" , 0x16f0010000b20ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC0_DOEPCTL002" , 0x16f0010000b40ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC0_DOEPCTL003" , 0x16f0010000b60ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC0_DOEPCTL004" , 0x16f0010000b80ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC1_DOEPCTL000" , 0x17f0010000b00ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC1_DOEPCTL001" , 0x17f0010000b20ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC1_DOEPCTL002" , 0x17f0010000b40ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC1_DOEPCTL003" , 0x17f0010000b60ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC1_DOEPCTL004" , 0x17f0010000b80ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
- {"USBC0_DOEPINT000" , 0x16f0010000b08ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC0_DOEPINT001" , 0x16f0010000b28ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC0_DOEPINT002" , 0x16f0010000b48ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC0_DOEPINT003" , 0x16f0010000b68ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC0_DOEPINT004" , 0x16f0010000b88ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC1_DOEPINT000" , 0x17f0010000b08ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC1_DOEPINT001" , 0x17f0010000b28ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC1_DOEPINT002" , 0x17f0010000b48ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC1_DOEPINT003" , 0x17f0010000b68ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC1_DOEPINT004" , 0x17f0010000b88ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
- {"USBC0_DOEPMSK" , 0x16f0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 910},
- {"USBC1_DOEPMSK" , 0x17f0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 910},
- {"USBC0_DOEPTSIZ000" , 0x16f0010000b10ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC0_DOEPTSIZ001" , 0x16f0010000b30ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC0_DOEPTSIZ002" , 0x16f0010000b50ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC0_DOEPTSIZ003" , 0x16f0010000b70ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC0_DOEPTSIZ004" , 0x16f0010000b90ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC1_DOEPTSIZ000" , 0x17f0010000b10ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC1_DOEPTSIZ001" , 0x17f0010000b30ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC1_DOEPTSIZ002" , 0x17f0010000b50ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC1_DOEPTSIZ003" , 0x17f0010000b70ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC1_DOEPTSIZ004" , 0x17f0010000b90ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
- {"USBC0_DPTXFSIZ001" , 0x16f0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
- {"USBC0_DPTXFSIZ002" , 0x16f0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
- {"USBC0_DPTXFSIZ003" , 0x16f001000010cull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
- {"USBC0_DPTXFSIZ004" , 0x16f0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
- {"USBC1_DPTXFSIZ001" , 0x17f0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
- {"USBC1_DPTXFSIZ002" , 0x17f0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
- {"USBC1_DPTXFSIZ003" , 0x17f001000010cull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
- {"USBC1_DPTXFSIZ004" , 0x17f0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
- {"USBC0_DSTS" , 0x16f0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 913},
- {"USBC1_DSTS" , 0x17f0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 913},
- {"USBC0_DTKNQR1" , 0x16f0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 914},
- {"USBC1_DTKNQR1" , 0x17f0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 914},
- {"USBC0_DTKNQR2" , 0x16f0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 915},
- {"USBC1_DTKNQR2" , 0x17f0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 915},
- {"USBC0_DTKNQR3" , 0x16f0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 916},
- {"USBC1_DTKNQR3" , 0x17f0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 916},
- {"USBC0_DTKNQR4" , 0x16f0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 917},
- {"USBC1_DTKNQR4" , 0x17f0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 917},
- {"USBC0_GAHBCFG" , 0x16f0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 918},
- {"USBC1_GAHBCFG" , 0x17f0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 918},
- {"USBC0_GHWCFG1" , 0x16f0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 919},
- {"USBC1_GHWCFG1" , 0x17f0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 919},
- {"USBC0_GHWCFG2" , 0x16f0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 920},
- {"USBC1_GHWCFG2" , 0x17f0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 920},
- {"USBC0_GHWCFG3" , 0x16f001000004cull, CVMX_CSR_DB_TYPE_NCB, 32, 921},
- {"USBC1_GHWCFG3" , 0x17f001000004cull, CVMX_CSR_DB_TYPE_NCB, 32, 921},
- {"USBC0_GHWCFG4" , 0x16f0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 922},
- {"USBC1_GHWCFG4" , 0x17f0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 922},
- {"USBC0_GINTMSK" , 0x16f0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 923},
- {"USBC1_GINTMSK" , 0x17f0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 923},
- {"USBC0_GINTSTS" , 0x16f0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 924},
- {"USBC1_GINTSTS" , 0x17f0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 924},
- {"USBC0_GNPTXFSIZ" , 0x16f0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
- {"USBC1_GNPTXFSIZ" , 0x17f0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
- {"USBC0_GNPTXSTS" , 0x16f001000002cull, CVMX_CSR_DB_TYPE_NCB, 32, 926},
- {"USBC1_GNPTXSTS" , 0x17f001000002cull, CVMX_CSR_DB_TYPE_NCB, 32, 926},
- {"USBC0_GOTGCTL" , 0x16f0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
- {"USBC1_GOTGCTL" , 0x17f0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
- {"USBC0_GOTGINT" , 0x16f0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
- {"USBC1_GOTGINT" , 0x17f0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
- {"USBC0_GRSTCTL" , 0x16f0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
- {"USBC1_GRSTCTL" , 0x17f0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
- {"USBC0_GRXFSIZ" , 0x16f0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
- {"USBC1_GRXFSIZ" , 0x17f0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
- {"USBC0_GRXSTSPD" , 0x16f0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 931},
- {"USBC1_GRXSTSPD" , 0x17f0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 931},
- {"USBC0_GRXSTSPH" , 0x16f0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 932},
- {"USBC1_GRXSTSPH" , 0x17f0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 932},
- {"USBC0_GRXSTSRD" , 0x16f001004001cull, CVMX_CSR_DB_TYPE_NCB, 32, 933},
- {"USBC1_GRXSTSRD" , 0x17f001004001cull, CVMX_CSR_DB_TYPE_NCB, 32, 933},
- {"USBC0_GRXSTSRH" , 0x16f001000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 934},
- {"USBC1_GRXSTSRH" , 0x17f001000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 934},
- {"USBC0_GSNPSID" , 0x16f0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 935},
- {"USBC1_GSNPSID" , 0x17f0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 935},
- {"USBC0_GUSBCFG" , 0x16f001000000cull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
- {"USBC1_GUSBCFG" , 0x17f001000000cull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
- {"USBC0_HAINT" , 0x16f0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 937},
- {"USBC1_HAINT" , 0x17f0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 937},
- {"USBC0_HAINTMSK" , 0x16f0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 938},
- {"USBC1_HAINTMSK" , 0x17f0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 938},
- {"USBC0_HCCHAR000" , 0x16f0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC0_HCCHAR001" , 0x16f0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC0_HCCHAR002" , 0x16f0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC0_HCCHAR003" , 0x16f0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC0_HCCHAR004" , 0x16f0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC0_HCCHAR005" , 0x16f00100005a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC0_HCCHAR006" , 0x16f00100005c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC0_HCCHAR007" , 0x16f00100005e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC1_HCCHAR000" , 0x17f0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC1_HCCHAR001" , 0x17f0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC1_HCCHAR002" , 0x17f0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC1_HCCHAR003" , 0x17f0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC1_HCCHAR004" , 0x17f0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC1_HCCHAR005" , 0x17f00100005a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC1_HCCHAR006" , 0x17f00100005c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC1_HCCHAR007" , 0x17f00100005e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
- {"USBC0_HCFG" , 0x16f0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 940},
- {"USBC1_HCFG" , 0x17f0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 940},
- {"USBC0_HCINT000" , 0x16f0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC0_HCINT001" , 0x16f0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC0_HCINT002" , 0x16f0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC0_HCINT003" , 0x16f0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC0_HCINT004" , 0x16f0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC0_HCINT005" , 0x16f00100005a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC0_HCINT006" , 0x16f00100005c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC0_HCINT007" , 0x16f00100005e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC1_HCINT000" , 0x17f0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC1_HCINT001" , 0x17f0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC1_HCINT002" , 0x17f0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC1_HCINT003" , 0x17f0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC1_HCINT004" , 0x17f0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC1_HCINT005" , 0x17f00100005a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC1_HCINT006" , 0x17f00100005c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC1_HCINT007" , 0x17f00100005e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
- {"USBC0_HCINTMSK000" , 0x16f001000050cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC0_HCINTMSK001" , 0x16f001000052cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC0_HCINTMSK002" , 0x16f001000054cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC0_HCINTMSK003" , 0x16f001000056cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC0_HCINTMSK004" , 0x16f001000058cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC0_HCINTMSK005" , 0x16f00100005acull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC0_HCINTMSK006" , 0x16f00100005ccull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC0_HCINTMSK007" , 0x16f00100005ecull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC1_HCINTMSK000" , 0x17f001000050cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC1_HCINTMSK001" , 0x17f001000052cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC1_HCINTMSK002" , 0x17f001000054cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC1_HCINTMSK003" , 0x17f001000056cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC1_HCINTMSK004" , 0x17f001000058cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC1_HCINTMSK005" , 0x17f00100005acull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC1_HCINTMSK006" , 0x17f00100005ccull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC1_HCINTMSK007" , 0x17f00100005ecull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
- {"USBC0_HCSPLT000" , 0x16f0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC0_HCSPLT001" , 0x16f0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC0_HCSPLT002" , 0x16f0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC0_HCSPLT003" , 0x16f0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC0_HCSPLT004" , 0x16f0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC0_HCSPLT005" , 0x16f00100005a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC0_HCSPLT006" , 0x16f00100005c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC0_HCSPLT007" , 0x16f00100005e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC1_HCSPLT000" , 0x17f0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC1_HCSPLT001" , 0x17f0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC1_HCSPLT002" , 0x17f0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC1_HCSPLT003" , 0x17f0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC1_HCSPLT004" , 0x17f0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC1_HCSPLT005" , 0x17f00100005a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC1_HCSPLT006" , 0x17f00100005c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC1_HCSPLT007" , 0x17f00100005e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
- {"USBC0_HCTSIZ000" , 0x16f0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC0_HCTSIZ001" , 0x16f0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC0_HCTSIZ002" , 0x16f0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC0_HCTSIZ003" , 0x16f0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC0_HCTSIZ004" , 0x16f0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC0_HCTSIZ005" , 0x16f00100005b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC0_HCTSIZ006" , 0x16f00100005d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC0_HCTSIZ007" , 0x16f00100005f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC1_HCTSIZ000" , 0x17f0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC1_HCTSIZ001" , 0x17f0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC1_HCTSIZ002" , 0x17f0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC1_HCTSIZ003" , 0x17f0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC1_HCTSIZ004" , 0x17f0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC1_HCTSIZ005" , 0x17f00100005b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC1_HCTSIZ006" , 0x17f00100005d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC1_HCTSIZ007" , 0x17f00100005f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
- {"USBC0_HFIR" , 0x16f0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 945},
- {"USBC1_HFIR" , 0x17f0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 945},
- {"USBC0_HFNUM" , 0x16f0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 946},
- {"USBC1_HFNUM" , 0x17f0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 946},
- {"USBC0_HPRT" , 0x16f0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 947},
- {"USBC1_HPRT" , 0x17f0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 947},
- {"USBC0_HPTXFSIZ" , 0x16f0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 948},
- {"USBC1_HPTXFSIZ" , 0x17f0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 948},
- {"USBC0_HPTXSTS" , 0x16f0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 949},
- {"USBC1_HPTXSTS" , 0x17f0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 949},
- {"USBC0_NPTXDFIFO000" , 0x16f0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC0_NPTXDFIFO001" , 0x16f0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC0_NPTXDFIFO002" , 0x16f0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC0_NPTXDFIFO003" , 0x16f0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC0_NPTXDFIFO004" , 0x16f0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC0_NPTXDFIFO005" , 0x16f0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC0_NPTXDFIFO006" , 0x16f0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC0_NPTXDFIFO007" , 0x16f0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC1_NPTXDFIFO000" , 0x17f0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC1_NPTXDFIFO001" , 0x17f0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC1_NPTXDFIFO002" , 0x17f0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC1_NPTXDFIFO003" , 0x17f0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC1_NPTXDFIFO004" , 0x17f0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC1_NPTXDFIFO005" , 0x17f0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC1_NPTXDFIFO006" , 0x17f0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC1_NPTXDFIFO007" , 0x17f0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
- {"USBC0_PCGCCTL" , 0x16f0010000e00ull, CVMX_CSR_DB_TYPE_NCB, 32, 951},
- {"USBC1_PCGCCTL" , 0x17f0010000e00ull, CVMX_CSR_DB_TYPE_NCB, 32, 951},
- {"USBN0_BIST_STATUS" , 0x11800680007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"USBN1_BIST_STATUS" , 0x11800780007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"USBN1_CLK_CTL" , 0x1180078000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"USBN0_CTL_STATUS" , 0x16f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 954},
- {"USBN1_CTL_STATUS" , 0x17f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 954},
- {"USBN0_DMA0_INB_CHN0" , 0x16f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 955},
- {"USBN1_DMA0_INB_CHN0" , 0x17f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 955},
- {"USBN0_DMA0_INB_CHN1" , 0x16f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 956},
- {"USBN1_DMA0_INB_CHN1" , 0x17f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 956},
- {"USBN0_DMA0_INB_CHN2" , 0x16f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 957},
- {"USBN1_DMA0_INB_CHN2" , 0x17f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 957},
- {"USBN0_DMA0_INB_CHN3" , 0x16f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 958},
- {"USBN1_DMA0_INB_CHN3" , 0x17f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 958},
- {"USBN0_DMA0_INB_CHN4" , 0x16f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 959},
- {"USBN1_DMA0_INB_CHN4" , 0x17f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 959},
- {"USBN0_DMA0_INB_CHN5" , 0x16f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 960},
- {"USBN1_DMA0_INB_CHN5" , 0x17f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 960},
- {"USBN0_DMA0_INB_CHN6" , 0x16f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 961},
- {"USBN1_DMA0_INB_CHN6" , 0x17f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 961},
- {"USBN0_DMA0_INB_CHN7" , 0x16f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 962},
- {"USBN1_DMA0_INB_CHN7" , 0x17f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 962},
- {"USBN0_DMA0_OUTB_CHN0" , 0x16f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 963},
- {"USBN1_DMA0_OUTB_CHN0" , 0x17f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 963},
- {"USBN0_DMA0_OUTB_CHN1" , 0x16f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 964},
- {"USBN1_DMA0_OUTB_CHN1" , 0x17f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 964},
- {"USBN0_DMA0_OUTB_CHN2" , 0x16f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 965},
- {"USBN1_DMA0_OUTB_CHN2" , 0x17f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 965},
- {"USBN0_DMA0_OUTB_CHN3" , 0x16f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 966},
- {"USBN1_DMA0_OUTB_CHN3" , 0x17f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 966},
- {"USBN0_DMA0_OUTB_CHN4" , 0x16f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 967},
- {"USBN1_DMA0_OUTB_CHN4" , 0x17f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 967},
- {"USBN0_DMA0_OUTB_CHN5" , 0x16f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 968},
- {"USBN1_DMA0_OUTB_CHN5" , 0x17f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 968},
- {"USBN0_DMA0_OUTB_CHN6" , 0x16f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 969},
- {"USBN1_DMA0_OUTB_CHN6" , 0x17f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 969},
- {"USBN0_DMA0_OUTB_CHN7" , 0x16f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 970},
- {"USBN1_DMA0_OUTB_CHN7" , 0x17f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 970},
- {"USBN0_DMA_TEST" , 0x16f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 971},
- {"USBN1_DMA_TEST" , 0x17f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 971},
- {"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
- {"USBN1_INT_ENB" , 0x1180078000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
- {"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
- {"USBN1_INT_SUM" , 0x1180078000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
- {"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
- {"USBN1_USBP_CTL_STATUS" , 0x1180078000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_21" , 4, 18, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_25" , 23, 3, 0, "RAZ", 1, 1, 0, 0},
- {"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRFLW1" , 35, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP1" , 36, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH1" , 37, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 0, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 10, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_5_7" , 5, 3, 2, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 2, "RAZ", 1, 1, 0, 0},
- {"BYP_EN" , 16, 1, 2, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 2, "RAZ", 1, 1, 0, 0},
- {"NCTL1" , 32, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_37_39" , 37, 3, 2, "RAZ", 1, 1, 0, 0},
- {"PCTL1" , 40, 5, 2, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_45_47" , 45, 3, 2, "RAZ", 1, 1, 0, 0},
- {"BYP_EN1" , 48, 1, 2, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 2, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 3, "RAZ", 1, 1, 0, 0},
- {"EN" , 1, 1, 3, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 3, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 4, "RO", 0, 0, 0ull, 0ull},
- {"DUPLEX" , 2, 1, 4, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 4, "RO", 0, 0, 0ull, 0ull},
- {"RX_EN" , 4, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"TX_EN" , 5, 1, 4, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 4, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 9, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 10, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 11, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 11, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 12, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 12, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 12, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 12, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 14, "RAZ", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 14, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 14, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 7, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 15, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 15, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 15, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 16, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 16, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 17, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 17, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 18, "R/W", 0, 0, 12ull, 12ull},
- {"RESERVED_4_63" , 4, 60, 18, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 19, "RAZ", 1, 1, 0, 0},
- {"MAXERR" , 2, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 19, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 19, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 19, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 19, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 20, "RAZ", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 20, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 21, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 22, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 27, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 27, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 32, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 32, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 33, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 33, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 33, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 33, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 34, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 35, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 35, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 36, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 36, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 2, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 37, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 2, 37, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 37, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 2, 38, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 38, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 2, 38, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 38, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 39, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 39, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 40, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 40, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 40, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 41, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 60, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 2, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 61, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 64, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 64, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 64, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 64, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 64, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 65, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 65, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 65, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 65, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 65, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 68, "RAZ", 1, 1, 0, 0},
- {"BP" , 4, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 68, "RAZ", 1, 1, 0, 0},
- {"EN" , 8, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 68, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 3, 71, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 71, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 4, 72, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 72, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 4, 73, "RO", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 73, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 74, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 74, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 75, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 75, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 75, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 75, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 75, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 75, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 75, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 75, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 75, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 75, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 76, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 76, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 76, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 76, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 77, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 78, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 78, "RAZ", 1, 1, 0, 0},
- {"UART2" , 16, 1, 78, "R/W", 0, 0, 0ull, 0ull},
- {"USB1" , 17, 1, 78, "R/W", 0, 0, 0ull, 0ull},
- {"MII1" , 18, 1, 78, "R/W", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 78, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 78, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 4, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 79, "RAZ", 1, 1, 0, 0},
- {"UART2" , 16, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB1" , 17, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII1" , 18, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 79, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 4, 80, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 80, "RAZ", 1, 1, 0, 0},
- {"UART2" , 16, 1, 80, "R/W1", 0, 0, 0ull, 0ull},
- {"USB1" , 17, 1, 80, "R/W1", 0, 0, 0ull, 0ull},
- {"MII1" , 18, 1, 80, "R/W1", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 80, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 80, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 81, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 81, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 81, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 81, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 81, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 81, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 81, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 81, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 81, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 81, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 81, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 82, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 82, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 83, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 83, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 84, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 84, "RAZ", 1, 1, 0, 0},
- {"UART2" , 16, 1, 84, "R/W", 0, 0, 0ull, 0ull},
- {"USB1" , 17, 1, 84, "R/W", 0, 0, 0ull, 0ull},
- {"MII1" , 18, 1, 84, "R/W", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 84, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 84, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 4, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 85, "RAZ", 1, 1, 0, 0},
- {"UART2" , 16, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB1" , 17, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII1" , 18, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 85, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 4, 86, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 86, "RAZ", 1, 1, 0, 0},
- {"UART2" , 16, 1, 86, "R/W1", 0, 0, 0ull, 0ull},
- {"USB1" , 17, 1, 86, "R/W1", 0, 0, 0ull, 0ull},
- {"MII1" , 18, 1, 86, "R/W1", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 86, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 86, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 87, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 87, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 87, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 87, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 87, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 87, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 87, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 87, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 87, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 88, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 88, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 88, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 88, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 88, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 88, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 88, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 88, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 88, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 88, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 88, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 88, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 88, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 89, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 89, "RAZ", 1, 1, 0, 0},
- {"UART2" , 16, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"USB1" , 17, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"MII1" , 18, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 89, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 90, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 91, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 4, 92, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 92, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 93, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 93, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 4, 94, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 94, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 95, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 96, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 3, 96, "R/W", 0, 0, 32767ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 96, "RAZ", 1, 1, 0, 0},
- {"QLM_DCOK" , 0, 2, 97, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 97, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 2, 98, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 98, "RAZ", 1, 1, 0, 0},
- {"MUX_SEL" , 4, 1, 98, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 98, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 98, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 98, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 99, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 99, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_39" , 37, 3, 99, "RAZ", 1, 1, 0, 0},
- {"SELECT" , 40, 2, 99, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_42_60" , 42, 19, 99, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 99, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 99, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 99, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 100, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 100, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 101, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 102, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 102, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 103, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 103, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 104, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 104, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 105, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 105, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 105, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 105, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 105, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 105, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 105, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 106, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 106, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 106, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 106, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 106, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 106, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 107, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 107, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 107, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 107, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 107, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 107, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 107, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 108, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 108, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 109, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 110, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 110, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 111, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 111, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 112, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 112, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 112, "RAZ", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 113, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 113, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 113, "RAZ", 0, 0, 0ull, 7ull},
- {"CTL" , 0, 16, 114, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_63" , 16, 48, 114, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 32, 115, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 115, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 116, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 116, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 116, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 117, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 117, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 118, "RAZ", 1, 1, 0, 0},
- {"LOGL_EN" , 0, 16, 119, "R/W", 0, 1, 65535ull, 0},
- {"PHYS_EN" , 16, 1, 119, "R/W", 0, 1, 1ull, 0},
- {"HG2RX_EN" , 17, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"HG2TX_EN" , 18, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 119, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 120, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 120, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 120, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 2, 120, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 120, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 2, 120, "RO", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 120, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 121, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 121, "RAZ", 1, 1, 0, 0},
- {"RX_EN" , 0, 1, 122, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EN" , 1, 1, 122, "R/W", 0, 0, 0ull, 0ull},
- {"DRP_EN" , 2, 1, 122, "R/W", 0, 0, 0ull, 0ull},
- {"BCK_EN" , 3, 1, 122, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 122, "RAZ", 1, 1, 0, 0},
- {"PHYS_BP" , 16, 16, 122, "R/W", 0, 1, 65535ull, 0},
- {"LOGL_EN" , 32, 16, 122, "R/W", 0, 0, 255ull, 255ull},
- {"PHYS_EN" , 48, 16, 122, "R/W", 0, 0, 255ull, 255ull},
- {"EN" , 0, 1, 123, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 123, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 123, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 123, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 123, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 123, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 123, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 123, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 123, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 123, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 124, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 125, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 126, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 127, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 128, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 129, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 130, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 130, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 131, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 131, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 131, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 131, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 132, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 132, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 133, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 133, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 133, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 133, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 133, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 133, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 133, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 133, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 133, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 134, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 134, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 134, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 134, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 134, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 134, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 134, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 134, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 135, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 135, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 136, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 136, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 136, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 136, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 136, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 136, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 137, "RAZ", 1, 1, 0, 0},
- {"CAREXT" , 1, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 137, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 137, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 137, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 137, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 137, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 138, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 138, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 139, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 139, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 140, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 141, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 141, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 142, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 142, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 143, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 143, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 144, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 144, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 145, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 145, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 146, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 146, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 147, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 147, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 148, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 148, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 149, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 149, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 150, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 150, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 150, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 151, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 151, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 152, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 152, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 153, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 153, "RAZ", 1, 1, 0, 0},
- {"LGTIM2GO" , 0, 16, 154, "RO", 0, 1, 0ull, 0},
- {"XOF" , 16, 16, 154, "RO", 0, 0, 0ull, 0ull},
- {"PHTIM2GO" , 32, 16, 154, "RO", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 154, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 4, 155, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 155, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 4, 155, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 155, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 156, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 156, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 157, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 157, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 157, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 157, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 157, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 158, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 158, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 159, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 159, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 160, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 160, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 160, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 161, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 161, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 161, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 161, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 161, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 162, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
- {"XOFF" , 0, 16, 163, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 163, "RAZ", 1, 1, 0, 0},
- {"XON" , 0, 16, 164, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 164, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 165, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 165, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 165, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 166, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 166, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 167, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 168, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 168, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 169, "RO", 1, 1, 0, 0},
- {"MSG_TIME" , 16, 16, 169, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 169, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 170, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 170, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 171, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 171, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 172, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 172, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 173, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 173, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 174, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 174, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 175, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 175, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 176, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 176, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 177, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 177, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 178, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 178, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 179, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 179, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 180, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 180, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 181, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 181, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 182, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 182, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 183, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 183, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 184, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 185, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 185, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 186, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 186, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 187, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 187, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 188, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 188, "RAZ", 1, 1, 0, 0},
- {"TX_XOF" , 0, 16, 189, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 189, "RAZ", 1, 1, 0, 0},
- {"TX_XON" , 0, 16, 190, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 190, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 191, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 191, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 191, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 192, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 192, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 192, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 192, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 192, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 193, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 193, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 193, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 193, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 193, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 193, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 193, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 194, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 194, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 195, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 195, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 196, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 196, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 196, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 196, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 196, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 196, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 197, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 197, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 198, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 198, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 199, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_5_63" , 5, 59, 199, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 200, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 200, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 200, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 200, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 200, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 200, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 200, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 201, "R/W", 0, 0, 6ull, 6ull},
- {"EN" , 4, 1, 201, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 201, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 202, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 202, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 202, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 203, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 203, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 204, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 205, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 206, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 206, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 207, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 207, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 208, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 209, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
- {"RR_MODE" , 5, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 209, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 210, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 210, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 211, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 211, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 211, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 212, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 212, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 212, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 213, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 213, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 213, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 213, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 213, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 214, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 214, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 214, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 214, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 214, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 215, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 216, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 217, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 218, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 219, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 219, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 219, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 220, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 220, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 220, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 221, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 221, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 222, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 222, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 222, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 222, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 222, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 223, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 223, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 223, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 223, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 223, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 224, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 225, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 226, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 226, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 227, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 227, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 228, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 228, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 229, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 229, "RAZ", 1, 1, 0, 0},
- {"NCB_WR" , 0, 3, 230, "R/W", 0, 1, 0ull, 0},
- {"NCB_RD" , 3, 3, 230, "R/W", 0, 1, 0ull, 0},
- {"PKO_RD" , 6, 3, 230, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 230, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 231, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 232, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 232, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 233, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 233, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 234, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 234, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 40, 235, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 235, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 236, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 237, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 237, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 237, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 238, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 238, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 239, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 240, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 240, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 241, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 241, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 242, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 242, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 243, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 243, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 243, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 244, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 244, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 244, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 245, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 245, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 246, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 246, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 247, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 247, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 248, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 249, "R/W", 0, 0, 0ull, 1ull},
- {"RADDR" , 0, 3, 250, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 250, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 250, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 250, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 250, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 250, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 251, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 251, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 251, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 251, "RO", 0, 0, 12ull, 12ull},
- {"RESERVED_44_63" , 44, 20, 251, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 252, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 252, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 252, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 252, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 253, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 253, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 253, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 253, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 253, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 253, "RO", 0, 0, 8ull, 8ull},
- {"RESERVED_61_63" , 61, 3, 253, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 254, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 254, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 255, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 255, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 256, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 256, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 256, "R/W", 0, 0, 0ull, 0ull},
- {"PRT_ENB" , 0, 4, 257, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 257, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 258, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 258, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 258, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 258, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 258, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 259, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 259, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 259, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 260, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_35" , 32, 4, 260, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT2" , 36, 4, 260, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_40_63" , 40, 24, 260, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 261, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 261, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 261, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 262, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 262, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 263, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 263, "RAZ", 1, 1, 0, 0},
- {"WLB_DAT" , 0, 4, 264, "RO", 0, 0, 0ull, 0ull},
- {"STIN_MSK" , 4, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"DT" , 5, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"DTCNT" , 6, 10, 264, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 264, "RAZ", 0, 0, 0ull, 0ull},
- {"WLB_MSK" , 19, 4, 264, "RO", 0, 0, 0ull, 0ull},
- {"DTBNK" , 23, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 264, "RAZ", 0, 0, 0ull, 0ull},
- {"L2T" , 0, 9, 265, "RO", 0, 0, 0ull, 0ull},
- {"VAB_VWCF" , 9, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"ILC" , 10, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 265, "RAZ", 0, 0, 0ull, 0ull},
- {"VWDF" , 12, 4, 265, "RO", 0, 0, 0ull, 0ull},
- {"PLC0" , 16, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"PLC1" , 17, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"PLC2" , 18, 1, 265, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 265, "RAZ", 0, 0, 0ull, 0ull},
- {"XRDDAT" , 0, 1, 266, "RO", 0, 0, 0ull, 0ull},
- {"XRDMSK" , 1, 1, 266, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 266, "RAZ", 0, 0, 0ull, 0ull},
- {"IPCBST" , 3, 1, 266, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 266, "RAZ", 0, 0, 0ull, 0ull},
- {"RMDF" , 8, 4, 266, "RO", 0, 0, 0ull, 0ull},
- {"MRB" , 12, 4, 266, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 266, "RAZ", 0, 0, 0ull, 0ull},
- {"LRF_ARB_MODE" , 0, 1, 267, "R/W", 0, 0, 1ull, 1ull},
- {"RFB_ARB_MODE" , 1, 1, 267, "R/W", 0, 0, 1ull, 1ull},
- {"RSP_ARB_MODE" , 2, 1, 267, "R/W", 0, 0, 1ull, 1ull},
- {"MWF_CRD" , 3, 4, 267, "R/W", 0, 0, 2ull, 2ull},
- {"IDXALIAS" , 7, 1, 267, "R/W", 0, 0, 0ull, 1ull},
- {"FPEN" , 8, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"FPEMPTY" , 9, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"FPEXP" , 10, 4, 267, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_17" , 14, 4, 267, "RAZ", 1, 1, 0, 0},
- {"LBIST" , 18, 1, 267, "R/W", 0, 0, 0ull, 0ull},
- {"BSTRUN" , 19, 1, 267, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 267, "RAZ", 1, 1, 0, 0},
- {"L2T" , 0, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"L2D" , 1, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"FINV" , 2, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 3, 3, 268, "R/W", 0, 0, 0ull, 0ull},
- {"PPNUM" , 6, 2, 268, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_9" , 8, 2, 268, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_DMP" , 10, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"LFB_ENUM" , 11, 3, 268, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 268, "RAZ", 0, 0, 0ull, 0ull},
- {"DT_TAG" , 0, 29, 269, "RO", 0, 0, 0ull, 0ull},
- {"DT_VLD" , 29, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 269, "RAZ", 0, 0, 0ull, 0ull},
- {"DTENA" , 31, 1, 269, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 269, "RAZ", 0, 0, 0ull, 0ull},
- {"PLC0RMSK" , 0, 32, 270, "R/W", 0, 0, 0ull, 0ull},
- {"PLC1RMSK" , 32, 32, 270, "R/W", 0, 0, 0ull, 0ull},
- {"PLC2RMSK" , 0, 32, 271, "R/W", 0, 0, 0ull, 0ull},
- {"ILCRMSK" , 32, 32, 271, "R/W", 0, 0, 0ull, 0ull},
- {"OOB1EN" , 0, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"OOB2EN" , 1, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"OOB3EN" , 2, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"L2TSECEN" , 3, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"L2TDEDEN" , 4, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"L2DSECEN" , 5, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDEDEN" , 6, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"LCKENA" , 7, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"LCK2ENA" , 8, 1, 272, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 272, "RAZ", 0, 0, 0ull, 0ull},
- {"OOB1" , 0, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
- {"OOB2" , 1, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
- {"OOB3" , 2, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2TSEC" , 3, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2TDED" , 4, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2DSEC" , 5, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2DDED" , 6, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK" , 7, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK2" , 8, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 273, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_ENA" , 0, 1, 274, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 274, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_BASE" , 4, 27, 274, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 274, "RAZ", 0, 0, 0ull, 0ull},
- {"LCK_OFFSET" , 0, 10, 275, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 275, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 276, "RO", 0, 0, 0ull, 0ull},
- {"CMD" , 1, 4, 276, "RO", 0, 0, 0ull, 0ull},
- {"SID" , 5, 9, 276, "RO", 0, 0, 0ull, 0ull},
- {"VABNUM" , 14, 3, 276, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_17" , 17, 1, 276, "RAZ", 0, 0, 0ull, 0ull},
- {"SET" , 18, 3, 276, "RO", 0, 0, 0ull, 0ull},
- {"IHD" , 21, 1, 276, "RO", 0, 0, 0ull, 0ull},
- {"ITL" , 22, 1, 276, "RO", 0, 0, 0ull, 0ull},
- {"INXT" , 23, 3, 276, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 276, "RAZ", 0, 0, 0ull, 0ull},
- {"VAM" , 27, 1, 276, "RO", 0, 0, 0ull, 0ull},
- {"STCFL" , 28, 1, 276, "RO", 0, 0, 0ull, 0ull},
- {"STINV" , 29, 1, 276, "RO", 0, 0, 0ull, 0ull},
- {"STPND" , 30, 1, 276, "RO", 0, 0, 0ull, 0ull},
- {"STCPND" , 31, 1, 276, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 276, "RAZ", 0, 0, 0ull, 0ull},
- {"VLD" , 0, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTPRB" , 1, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"PRBRTY" , 2, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTMFL" , 3, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTVTM" , 4, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSC" , 5, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTSTRSP" , 6, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTSTDT" , 7, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTRDA" , 8, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTSTM" , 9, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTWRM" , 10, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTWHF" , 11, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTWHP" , 12, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTDQ" , 13, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTDW" , 14, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"WTRSP" , 15, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"BID" , 16, 2, 277, "RO", 0, 0, 0ull, 0ull},
- {"DSGOING" , 18, 1, 277, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 277, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_IDX" , 0, 9, 278, "RO", 0, 0, 0ull, 0ull},
- {"LFB_TAG" , 9, 18, 278, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 278, "RAZ", 0, 0, 0ull, 0ull},
- {"LFB_HWM" , 0, 3, 279, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_3_3" , 3, 1, 279, "RAZ", 0, 0, 0ull, 0ull},
- {"STPARTDIS" , 4, 1, 279, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 279, "RAZ", 0, 0, 0ull, 0ull},
- {"STENA" , 0, 1, 280, "R/W", 0, 0, 0ull, 0ull},
- {"DWBENA" , 1, 1, 280, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 280, "RAZ", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 281, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 281, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 281, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 281, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 281, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 281, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 282, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 282, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 282, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 282, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 282, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 282, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 14, 283, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_19" , 14, 6, 283, "RAZ", 0, 0, 0ull, 0ull},
- {"SADR" , 20, 14, 283, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 283, "RAZ", 0, 0, 0ull, 0ull},
- {"FSRC" , 36, 1, 283, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 37, 27, 283, "RO", 0, 0, 0ull, 0ull},
- {"PFCNT0" , 0, 36, 284, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 284, "RAZ", 0, 0, 0ull, 0ull},
- {"CNT0SEL" , 0, 6, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0CLR" , 6, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0ENA" , 7, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1SEL" , 8, 6, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1CLR" , 14, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 15, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2SEL" , 16, 6, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2CLR" , 22, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 23, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3SEL" , 24, 6, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3CLR" , 30, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 31, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RDCLR" , 32, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RDCLR" , 33, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RDCLR" , 34, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RDCLR" , 35, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"PP0GRP" , 0, 2, 286, "R/W", 0, 0, 0ull, 0ull},
- {"PP1GRP" , 2, 2, 286, "R/W", 0, 0, 0ull, 0ull},
- {"PP2GRP" , 4, 2, 286, "R/W", 0, 0, 0ull, 0ull},
- {"PP3GRP" , 6, 2, 286, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSK0" , 0, 8, 287, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK1" , 8, 8, 287, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK2" , 16, 8, 287, "R/W", 0, 0, 0ull, 0ull},
- {"UMSK3" , 24, 8, 287, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 287, "RAZ", 0, 0, 0ull, 0ull},
- {"UMSKIOB" , 0, 8, 288, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 288, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0STAT" , 0, 34, 289, "RO", 0, 0, 0ull, 0ull},
- {"FTL" , 34, 1, 289, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 289, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1STAT" , 0, 34, 290, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 290, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2STAT" , 0, 34, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3STAT" , 0, 34, 292, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 293, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 293, "R/W1C", 0, 0, 0ull, 0ull},
- {"BMHCLSEL" , 5, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 293, "RAZ", 0, 0, 0ull, 0ull},
- {"FADR" , 0, 10, 294, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 294, "RAZ", 0, 0, 0ull, 0ull},
- {"FSET" , 11, 3, 294, "RO", 0, 0, 0ull, 0ull},
- {"FOWMSK" , 14, 4, 294, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 294, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW0" , 0, 10, 295, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW1" , 10, 10, 295, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 295, "RAZ", 0, 0, 0ull, 0ull},
- {"FSYN_OW2" , 0, 10, 296, "RO", 0, 0, 0ull, 0ull},
- {"FSYN_OW3" , 10, 10, 296, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 296, "RAZ", 0, 0, 0ull, 0ull},
- {"Q0FUS" , 0, 34, 297, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 297, "RAZ", 0, 0, 0ull, 0ull},
- {"Q1FUS" , 0, 34, 298, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 298, "RAZ", 0, 0, 0ull, 0ull},
- {"Q2FUS" , 0, 34, 299, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 299, "RAZ", 0, 0, 0ull, 0ull},
- {"Q3FUS" , 0, 34, 300, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_256K" , 34, 1, 300, "RO", 0, 0, 0ull, 0ull},
- {"CRIP_128K" , 35, 1, 300, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_36" , 36, 1, 300, "RO", 0, 0, 0ull, 0ull},
- {"EMA_CTL" , 37, 3, 300, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 300, "RAZ", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 0, 1, 301, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_INTENA" , 1, 1, 301, "R/W", 0, 0, 0ull, 1ull},
- {"DED_INTENA" , 2, 1, 301, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 3, 1, 301, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 4, 1, 301, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYN" , 5, 6, 301, "RO", 0, 0, 0ull, 0ull},
- {"FADR" , 11, 9, 301, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 301, "RAZ", 0, 0, 0ull, 0ull},
- {"FSET" , 21, 3, 301, "RO", 0, 0, 0ull, 0ull},
- {"LCKERR" , 24, 1, 301, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA" , 25, 1, 301, "R/W", 0, 0, 0ull, 1ull},
- {"LCKERR2" , 26, 1, 301, "R/W1C", 0, 0, 0ull, 0ull},
- {"LCK_INTENA2" , 27, 1, 301, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_28_63" , 28, 36, 301, "RAZ", 0, 0, 0ull, 0ull},
- {"START" , 0, 1, 302, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 302, "RAZ", 1, 0, 0, 0ull},
- {"MRD" , 0, 3, 303, "RO", 1, 0, 0, 0ull},
- {"MRF" , 3, 1, 303, "RO", 1, 0, 0, 0ull},
- {"MWC" , 4, 1, 303, "RO", 1, 0, 0, 0ull},
- {"MWD" , 5, 3, 303, "RO", 1, 0, 0, 0ull},
- {"MWF" , 8, 1, 303, "RO", 1, 0, 0, 0ull},
- {"CSRE2D" , 9, 1, 303, "RO", 1, 0, 0, 0ull},
- {"CSRD2E" , 10, 1, 303, "RO", 1, 0, 0, 0ull},
- {"RESERVED_11_63" , 11, 53, 303, "RAZ", 1, 0, 0, 0ull},
- {"PCTL_DAT" , 0, 5, 304, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_11" , 5, 7, 304, "RAZ", 0, 1, 0ull, 0},
- {"PCTL_CSR" , 12, 4, 304, "R/W", 0, 1, 15ull, 0},
- {"NCTL_DAT" , 16, 4, 304, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_27" , 20, 8, 304, "RAZ", 0, 1, 0ull, 0},
- {"NCTL_CSR" , 28, 4, 304, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_32_63" , 32, 32, 304, "RAZ", 0, 0, 0ull, 0ull},
- {"DIC" , 0, 2, 305, "R/W", 0, 0, 0ull, 0ull},
- {"QS_DIC" , 2, 2, 305, "R/W", 0, 0, 2ull, 2ull},
- {"TSKW" , 4, 2, 305, "R/W", 0, 0, 0ull, 1ull},
- {"SIL_LAT" , 6, 2, 305, "R/W", 0, 0, 1ull, 1ull},
- {"BPRCH" , 8, 1, 305, "R/W", 0, 1, 0ull, 0},
- {"FPRCH2" , 9, 1, 305, "R/W", 0, 0, 0ull, 1ull},
- {"MODE32B" , 10, 1, 305, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 11, 1, 305, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MRF" , 12, 1, 305, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_MWF" , 13, 1, 305, "RAZ", 0, 0, 0ull, 0ull},
- {"R2R_SLOT" , 14, 1, 305, "R/W", 0, 0, 0ull, 0ull},
- {"RDIMM_ENA" , 15, 1, 305, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_17" , 16, 2, 305, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 18, 4, 305, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 22, 1, 305, "R/W", 0, 0, 0ull, 1ull},
- {"SLOW_SCF" , 23, 1, 305, "R/W", 0, 0, 0ull, 0ull},
- {"DDR__PCTL" , 24, 4, 305, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 28, 4, 305, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 305, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 306, "RAZ", 0, 1, 0ull, 0},
- {"DCC_ENABLE" , 8, 1, 306, "R/W", 0, 0, 0ull, 0ull},
- {"SIL_MODE" , 9, 1, 306, "R/W", 0, 0, 0ull, 1ull},
- {"SEQUENCE" , 10, 3, 306, "R/W", 0, 0, 0ull, 0ull},
- {"IDLEPOWER" , 13, 3, 306, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 16, 4, 306, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 20, 1, 306, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_63" , 21, 43, 306, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_HI" , 0, 32, 307, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 307, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT_LO" , 0, 32, 308, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 308, "RAZ", 1, 1, 0, 0},
- {"DDR2" , 0, 1, 309, "R/W", 0, 0, 1ull, 1ull},
- {"RDQS" , 1, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 2, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 3, 5, 309, "R/W", 0, 1, 0ull, 0},
- {"QDLL_ENA" , 8, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"ODT_ENA" , 9, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 10, 1, 309, "R/W", 0, 1, 0ull, 0},
- {"CRIP_MODE" , 11, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"TFAW" , 12, 5, 309, "R/W", 0, 0, 0ull, 9ull},
- {"DDR_EOF" , 17, 4, 309, "R/W", 0, 0, 0ull, 0ull},
- {"SILO_HC" , 21, 1, 309, "R/W", 0, 1, 1ull, 0},
- {"TWR" , 22, 3, 309, "R/W", 0, 0, 3ull, 1ull},
- {"BWCNT" , 25, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 26, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"ADDLAT" , 27, 3, 309, "R/W", 0, 0, 0ull, 0ull},
- {"BURST8" , 30, 1, 309, "R/W", 0, 0, 0ull, 1ull},
- {"BANK8" , 31, 1, 309, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 309, "RAZ", 0, 0, 0ull, 0ull},
- {"CLK" , 0, 4, 310, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 310, "RAZ", 0, 0, 0ull, 0ull},
- {"CMD" , 5, 4, 310, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 310, "RAZ", 0, 0, 0ull, 0ull},
- {"DQ" , 10, 4, 310, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 310, "RAZ", 0, 0, 0ull, 0ull},
- {"DLL90_VLU" , 0, 5, 311, "R/W", 0, 1, 0ull, 0},
- {"DLL90_ENA" , 5, 1, 311, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYP" , 6, 1, 311, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 7, 1, 311, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 311, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 312, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 312, "RAZ", 0, 1, 0ull, 0},
- {"ROW_LSB" , 16, 3, 312, "R/W", 0, 1, 3ull, 0},
- {"BANK8" , 19, 1, 312, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 312, "RAZ", 0, 1, 0ull, 0},
- {"MRDSYN0" , 0, 8, 313, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 313, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 313, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 313, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 313, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 12, 314, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 12, 14, 314, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 26, 3, 314, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 29, 1, 314, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 30, 2, 314, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 314, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_HI" , 0, 32, 315, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 315, "RAZ", 1, 1, 0, 0},
- {"IFBCNT_LO" , 0, 32, 316, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 316, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 317, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 317, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 317, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 317, "R/W", 0, 1, 5ull, 0},
- {"REF_INT" , 9, 6, 317, "R/W", 0, 0, 1ull, 2ull},
- {"TCL" , 15, 4, 317, "R/W", 0, 1, 3ull, 0},
- {"INTR_SEC_ENA" , 19, 1, 317, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 20, 1, 317, "R/W", 0, 0, 0ull, 1ull},
- {"SEC_ERR" , 21, 4, 317, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 25, 4, 317, "R/W1C", 0, 0, 0ull, 0ull},
- {"BUNK_ENA" , 29, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"SILO_QC" , 30, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 31, 1, 317, "RAZ", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 317, "RAZ", 1, 1, 0, 0},
- {"TRAS" , 0, 5, 318, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 5, 4, 318, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 9, 4, 318, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 13, 4, 318, "R/W", 0, 0, 5ull, 4ull},
- {"TRFC" , 17, 5, 318, "R/W", 0, 0, 6ull, 7ull},
- {"TMRD" , 22, 3, 318, "R/W", 0, 0, 2ull, 2ull},
- {"CASLAT" , 25, 3, 318, "R/W", 0, 0, 4ull, 4ull},
- {"TRRD" , 28, 3, 318, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_31_63" , 31, 33, 318, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 319, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 319, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_HI" , 0, 32, 320, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 320, "RAZ", 1, 1, 0, 0},
- {"OPSCNT_LO" , 0, 32, 321, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 321, "RAZ", 1, 1, 0, 0},
- {"EN2" , 0, 1, 322, "R/W", 0, 1, 0ull, 0},
- {"EN4" , 1, 1, 322, "R/W", 0, 1, 0ull, 0},
- {"EN6" , 2, 1, 322, "R/W", 0, 1, 0ull, 0},
- {"EN8" , 3, 1, 322, "R/W", 0, 1, 1ull, 0},
- {"EN12" , 4, 1, 322, "R/W", 0, 1, 0ull, 0},
- {"EN16" , 5, 1, 322, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 322, "RAZ", 0, 1, 0ull, 0},
- {"CLKR" , 8, 6, 322, "R/W", 0, 1, 0ull, 0},
- {"CLKF" , 14, 12, 322, "R/W", 0, 1, 31ull, 0},
- {"RESET_N" , 26, 1, 322, "R/W", 0, 0, 0ull, 1ull},
- {"DIV_RESET" , 27, 1, 322, "R/W", 0, 0, 1ull, 0ull},
- {"FASTEN_N" , 28, 1, 322, "R/W", 0, 0, 0ull, 1ull},
- {"BYPASS" , 29, 1, 322, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 322, "RAZ", 0, 1, 0ull, 0},
- {"FBSLIP" , 0, 1, 323, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 323, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_21" , 2, 20, 323, "RAZ", 1, 1, 0, 0},
- {"DDR__PCTL" , 22, 5, 323, "RO", 1, 1, 0, 0},
- {"DDR__NCTL" , 27, 5, 323, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 323, "RAZ", 1, 1, 0, 0},
- {"BNK" , 0, 3, 324, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 324, "RAZ", 0, 0, 0ull, 0ull},
- {"COL" , 4, 12, 324, "R/W", 0, 0, 0ull, 0ull},
- {"ROW" , 16, 16, 324, "R/W", 0, 0, 0ull, 0ull},
- {"PATTERN" , 32, 8, 324, "R/W", 0, 0, 170ull, 170ull},
- {"RANKMASK" , 40, 4, 324, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_63" , 44, 20, 324, "RAZ", 0, 0, 0ull, 0ull},
- {"BYTE" , 0, 4, 325, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 325, "RAZ", 0, 0, 0ull, 0ull},
- {"BITMASK" , 16, 16, 325, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 325, "RAZ", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 4, 326, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 4, 4, 326, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 8, 4, 326, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 12, 4, 326, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 16, 4, 326, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 20, 4, 326, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 24, 4, 326, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 28, 4, 326, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 32, 4, 326, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 36, 2, 326, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 326, "RAZ", 1, 0, 0, 0ull},
- {"PCTL" , 0, 5, 327, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 327, "RAZ", 0, 1, 0ull, 0},
- {"NCTL" , 8, 4, 327, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 327, "RAZ", 0, 1, 0ull, 0},
- {"ENABLE" , 16, 1, 327, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 327, "RAZ", 0, 1, 0ull, 0},
- {"RODT_LO0" , 0, 4, 328, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO1" , 4, 4, 328, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO2" , 8, 4, 328, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_LO3" , 12, 4, 328, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI0" , 16, 4, 328, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI1" , 20, 4, 328, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI2" , 24, 4, 328, "R/W", 0, 0, 15ull, 15ull},
- {"RODT_HI3" , 28, 4, 328, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_32_63" , 32, 32, 328, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 329, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D0_R1" , 8, 8, 329, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R0" , 16, 8, 329, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R1" , 24, 8, 329, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 329, "RAZ", 0, 0, 0ull, 0ull},
- {"WODT_D2_R0" , 0, 8, 330, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R1" , 8, 8, 330, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R0" , 16, 8, 330, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R1" , 24, 8, 330, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 330, "RAZ", 0, 0, 0ull, 0ull},
- {"NCBI" , 0, 1, 331, "RO", 0, 0, 0ull, 0ull},
- {"LOC" , 1, 1, 331, "RO", 0, 0, 0ull, 0ull},
- {"DMA" , 2, 1, 331, "RO", 0, 0, 0ull, 0ull},
- {"NCBO_0" , 3, 1, 331, "RO", 0, 0, 0ull, 0ull},
- {"NDF" , 4, 2, 331, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 331, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 5, 332, "R/W", 1, 1, 0, 0},
- {"PCTL" , 5, 5, 332, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 332, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 333, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 333, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 333, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 333, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 333, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 333, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 333, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 333, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 333, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 333, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 334, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 334, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 334, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 335, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 335, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 335, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 336, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 336, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 336, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 336, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 336, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 336, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 336, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 336, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 336, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 336, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 336, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 336, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 336, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 336, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 336, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 337, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 337, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 337, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 338, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 338, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 338, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 339, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 339, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 339, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 340, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 340, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 340, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 340, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 340, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 341, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 342, "RAZ", 1, 1, 0, 0},
- {"NAND" , 8, 1, 342, "RO", 1, 1, 0, 0},
- {"TERM" , 9, 2, 342, "RO", 1, 1, 0, 0},
- {"DMACK_P0" , 11, 1, 342, "RO", 1, 1, 0, 0},
- {"DMACK_P1" , 12, 1, 342, "RO", 1, 1, 0, 0},
- {"RESERVED_13_13" , 13, 1, 342, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 14, 1, 342, "RO", 1, 1, 0, 0},
- {"ALE" , 15, 1, 342, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 342, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 16, 343, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 343, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 343, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 343, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 343, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 343, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 343, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 343, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 343, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 344, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 344, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 344, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 344, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 344, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 344, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 344, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 344, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 344, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 344, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 344, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 344, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 344, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 345, "R/W", 0, 0, 25ull, 25ull},
- {"RESERVED_6_7" , 6, 2, 345, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 345, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 345, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 345, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 345, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 346, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 347, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 347, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 348, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 348, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 4, 349, "RO", 1, 1, 0, 0},
- {"RESERVED_4_15" , 4, 12, 349, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 349, "RO", 1, 1, 0, 0},
- {"BIST_DIS" , 24, 1, 349, "RO", 1, 1, 0, 0},
- {"RST_SHT" , 25, 1, 349, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 349, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 349, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 349, "RO", 1, 1, 0, 0},
- {"NOKASU" , 29, 1, 349, "RO", 1, 1, 0, 0},
- {"RESERVED_30_31" , 30, 2, 349, "RAZ", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 349, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 349, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 349, "RAZ", 1, 1, 0, 0},
- {"ICACHE" , 0, 24, 350, "RO", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 350, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 350, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 350, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 350, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 350, "RO", 1, 1, 0, 0},
- {"ZIP_CRIP" , 29, 2, 350, "RO", 1, 1, 0, 0},
- {"RESERVED_31_63" , 31, 33, 350, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 351, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_3_3" , 3, 1, 351, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 351, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_63" , 7, 57, 351, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 352, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 353, "R/W1C", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 353, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 353, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 354, "R/W", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 354, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 8, 355, "R/W", 0, 1, 3ull, 0},
- {"SCLK_HI" , 8, 12, 355, "R/W", 0, 1, 100ull, 0},
- {"SCLK_LO" , 20, 4, 355, "R/W", 0, 1, 2ull, 0},
- {"OUT" , 24, 8, 355, "R/W", 0, 1, 3ull, 0},
- {"PROG_PIN" , 32, 1, 355, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_63" , 33, 31, 355, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 356, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 356, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 356, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 356, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 356, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 356, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 356, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 357, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 14, 14, 357, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 28, 14, 357, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 357, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 358, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 358, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 3, 359, "R/W", 1, 1, 0, 0},
- {"RESERVED_3_63" , 3, 61, 359, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 360, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 360, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 360, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 360, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 360, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 360, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 360, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 360, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 360, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 360, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 361, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 361, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 362, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 362, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 363, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 363, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 363, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 363, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 363, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 363, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 363, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 363, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 363, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 363, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 363, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 363, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 363, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 364, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 364, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 364, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 364, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 364, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 364, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 364, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 364, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 364, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 365, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 365, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 365, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 366, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 366, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 366, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 367, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 367, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 368, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 368, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 369, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 369, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 370, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 370, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 370, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 370, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 370, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 370, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 370, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 371, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 371, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 372, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 372, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 372, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 372, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 372, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 372, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 372, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 373, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 373, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 373, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 373, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 374, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 374, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 374, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 374, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 374, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 374, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 374, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 374, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 375, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 375, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 375, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 375, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 375, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 375, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 375, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 375, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 375, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 376, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 376, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 376, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 376, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 376, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 376, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 376, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 377, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 377, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 377, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 377, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 377, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 377, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 377, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 377, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 377, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 378, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 378, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 379, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 379, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 380, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 380, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 380, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 380, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 381, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 381, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 382, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 382, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 383, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 383, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 384, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 384, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 384, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 384, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 385, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 385, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 386, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 386, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 387, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 387, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 388, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 388, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 389, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 389, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 390, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 390, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 391, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 391, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 391, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 391, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 391, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 391, "RAZ", 1, 1, 0, 0},
- {"DLH" , 0, 8, 392, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 392, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 393, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 393, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 394, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 394, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 395, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 395, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 395, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 395, "RAZ", 0, 1, 0ull, 0},
- {"TXTRIG" , 4, 2, 395, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 395, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 395, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 396, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 396, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 397, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 397, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 397, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 397, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 397, "RAZ", 0, 1, 0ull, 0},
- {"PTIME" , 7, 1, 397, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 397, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 398, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 398, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 398, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 398, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 399, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 399, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 399, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 399, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 399, "RAZ", 0, 1, 0ull, 0},
- {"BRK" , 6, 1, 399, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 399, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 399, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 400, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 400, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 400, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 400, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 400, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 400, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 400, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 400, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 400, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 401, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 401, "RAZ", 0, 1, 0ull, 0},
- {"DCTS" , 0, 1, 402, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 402, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 402, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 402, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 402, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 402, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 402, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 402, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 402, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 403, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 403, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 404, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 404, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 405, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 405, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 405, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 405, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 406, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 406, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 407, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 407, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 408, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 408, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 409, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 409, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 409, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 409, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 410, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 410, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 411, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 412, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 412, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 413, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 413, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 414, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 414, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 415, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 415, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 416, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 416, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 416, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 416, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 416, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 416, "RAZ", 1, 1, 0, 0},
- {"ORFDAT" , 0, 1, 417, "RO", 0, 0, 0ull, 0ull},
- {"IRFDAT" , 1, 1, 417, "RO", 0, 0, 0ull, 0ull},
- {"IPFDAT" , 2, 1, 417, "RO", 0, 0, 0ull, 0ull},
- {"MRQDAT" , 3, 1, 417, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 417, "RAZ", 0, 0, 0ull, 0ull},
- {"MRQ_HWM" , 0, 2, 418, "R/W", 0, 0, 0ull, 1ull},
- {"NBTARB" , 2, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"LENDIAN" , 3, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 4, 1, 418, "R/W", 0, 0, 1ull, 0ull},
- {"EN" , 5, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 6, 1, 418, "RO", 0, 0, 0ull, 0ull},
- {"CRC_STRIP" , 7, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 418, "RAZ", 1, 1, 0, 0},
- {"OVFENA" , 0, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IVFENA" , 1, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"OTHENA" , 2, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"ITHENA" , 3, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_DRPENA" , 4, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"IRUNENA" , 5, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"ORUNENA" , 6, 1, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 419, "RAZ", 1, 1, 0, 0},
- {"IRCNT" , 0, 20, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 420, "RAZ", 1, 1, 0, 0},
- {"IRHWM" , 0, 20, 421, "R/W", 0, 0, 0ull, 0ull},
- {"IBPLWM" , 20, 20, 421, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 421, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 422, "RAZ", 1, 1, 0, 0},
- {"IBASE" , 3, 33, 422, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 422, "RAZ", 1, 1, 0, 0},
- {"ISIZE" , 40, 20, 422, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 422, "RAZ", 1, 1, 0, 0},
- {"IDBELL" , 0, 20, 423, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 423, "RAZ", 1, 1, 0, 0},
- {"ITLPTR" , 32, 20, 423, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 423, "RAZ", 1, 1, 0, 0},
- {"ODBLOVF" , 0, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"IDBLOVF" , 1, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORTHRESH" , 2, 1, 424, "RO", 0, 0, 0ull, 0ull},
- {"IRTHRESH" , 3, 1, 424, "RO", 0, 0, 0ull, 0ull},
- {"DATA_DRP" , 4, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"IRUN" , 5, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORUN" , 6, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 424, "RAZ", 1, 1, 0, 0},
- {"ORCNT" , 0, 20, 425, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 425, "RAZ", 1, 1, 0, 0},
- {"ORHWM" , 0, 20, 426, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 426, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 427, "RAZ", 1, 1, 0, 0},
- {"OBASE" , 3, 33, 427, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 427, "RAZ", 1, 1, 0, 0},
- {"OSIZE" , 40, 20, 427, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 427, "RAZ", 1, 1, 0, 0},
- {"ODBELL" , 0, 20, 428, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 428, "RAZ", 1, 1, 0, 0},
- {"OTLPTR" , 32, 20, 428, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 428, "RAZ", 1, 1, 0, 0},
- {"OREMCNT" , 0, 20, 429, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 429, "RAZ", 1, 1, 0, 0},
- {"IREMCNT" , 32, 20, 429, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_52_63" , 52, 12, 429, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 3, 430, "R/W", 0, 1, 0ull, 0},
- {"ADR_CYC" , 3, 4, 430, "R/W", 0, 1, 8ull, 0},
- {"T_MULT" , 7, 4, 430, "R/W", 0, 1, 9ull, 0},
- {"RESERVED_11_63" , 11, 53, 430, "RAZ", 1, 1, 0, 0},
- {"NF_CMD" , 0, 64, 431, "R/W", 0, 1, 0ull, 0},
- {"CNT" , 0, 8, 432, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 432, "RAZ", 1, 1, 0, 0},
- {"ECC_ERR" , 0, 8, 433, "RO", 0, 1, 0ull, 0},
- {"XOR_ECC" , 8, 24, 433, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 433, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 434, "R/W1C", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 434, "R/W1C", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 434, "R/W1C", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 434, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 434, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 434, "R/W1C", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 434, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 434, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 435, "R/W", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 435, "R/W", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 435, "R/W", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 435, "R/W", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 435, "R/W", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 435, "R/W", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 435, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 435, "RAZ", 1, 1, 0, 0},
- {"RST_FF" , 0, 1, 436, "R/W", 0, 0, 0ull, 0ull},
- {"EX_DIS" , 1, 1, 436, "R/W", 0, 0, 0ull, 0ull},
- {"BT_DIS" , 2, 1, 436, "R/W", 0, 0, 0ull, 1ull},
- {"BT_DMA" , 3, 1, 436, "R/W", 0, 1, 0ull, 0},
- {"RD_CMD" , 4, 1, 436, "R/W", 0, 0, 0ull, 0ull},
- {"RD_VAL" , 5, 1, 436, "RO", 0, 1, 0ull, 0},
- {"RD_DONE" , 6, 1, 436, "R/W1C", 0, 0, 0ull, 0ull},
- {"FR_BYT" , 7, 11, 436, "RO", 0, 1, 0ull, 0},
- {"WAIT_CNT" , 18, 6, 436, "R/W", 0, 1, 20ull, 0},
- {"NBR_HWM" , 24, 3, 436, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_27_63" , 27, 37, 436, "RAZ", 1, 1, 0, 0},
- {"MAIN_SM" , 0, 3, 437, "RO", 0, 1, 0ull, 0},
- {"MAIN_BAD" , 3, 1, 437, "RO", 0, 1, 0ull, 0},
- {"RD_FF" , 4, 2, 437, "RO", 0, 1, 0ull, 0},
- {"RD_FF_BAD" , 6, 1, 437, "RO", 0, 1, 0ull, 0},
- {"BT_SM" , 7, 4, 437, "RO", 0, 1, 0ull, 0},
- {"EXE_SM" , 11, 4, 437, "RO", 0, 1, 0ull, 0},
- {"EXE_IDLE" , 15, 1, 437, "RO", 0, 1, 1ull, 0},
- {"RESERVED_16_63" , 16, 48, 437, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 438, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 438, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 438, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 14, 438, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 438, "RAZ", 1, 1, 0, 0},
- {"NCB_CMD" , 0, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"DIF4" , 2, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"DIF3" , 3, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"DIF2" , 4, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"DIF1" , 5, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"DIF0" , 6, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"CSM1" , 7, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"CSM0" , 8, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P1" , 9, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_CO" , 19, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_NO" , 20, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_PO" , 21, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_CO" , 22, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_NO" , 23, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_PO" , 24, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P1" , 25, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_O" , 27, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_C" , 28, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_O" , 29, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"D4_PST" , 31, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"D3_PST" , 32, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"D2_PST" , 33, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"D1_PST" , 34, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"D0_PST" , 35, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_39" , 36, 4, 439, "RAZ", 1, 1, 0, 0},
- {"DS_MEM" , 40, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"D4_MEM" , 41, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"D3_MEM" , 42, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"D2_MEM" , 43, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"D1_MEM" , 44, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"D0_MEM" , 45, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PKT_POP1" , 46, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PKT_POP0" , 47, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_48_49" , 48, 2, 439, "RAZ", 1, 1, 0, 0},
- {"PKT_POF" , 50, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PFM" , 51, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PKT_IMEM" , 52, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_SL" , 53, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_ID" , 54, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_CNT" , 55, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_IM" , 56, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PCSR_INT" , 57, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PIF" , 58, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PCR_GIM" , 59, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_60_62" , 60, 3, 439, "RAZ", 1, 1, 0, 0},
- {"PKT_RDF" , 63, 1, 439, "RO", 0, 0, 0ull, 0ull},
- {"PKT_BLK" , 0, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"PKT_GL" , 1, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"PKT_GD" , 2, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"PSC_P1" , 3, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"PSC_P0" , 4, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"PKT_RD" , 5, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"NWE_WR1" , 6, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"NWE_WR0" , 7, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"NWE_ST" , 8, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"NRD_ST" , 9, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"PRD_ERR" , 10, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"PRD_ST1" , 11, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"PRD_ST0" , 12, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"PRD_TAG" , 13, 1, 440, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 440, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_CAX" , 1, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 2, 2, 441, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 4, 1, 441, "R/W", 0, 0, 0ull, 1ull},
- {"PTLP_RO" , 5, 1, 441, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 441, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 441, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 441, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 441, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 441, "R/W", 0, 0, 3ull, 3ull},
- {"INTA" , 16, 1, 441, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 17, 1, 441, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 18, 1, 441, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 19, 1, 441, "RO", 0, 0, 1ull, 1ull},
- {"WAITL_COM" , 20, 1, 441, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_63" , 21, 43, 441, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_CAX" , 1, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 2, 2, 442, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 4, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"PTLP_RO" , 5, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 442, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 442, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 442, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 442, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 442, "R/W", 0, 0, 3ull, 3ull},
- {"INTA" , 16, 1, 442, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 17, 1, 442, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 18, 1, 442, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 19, 1, 442, "RO", 0, 0, 1ull, 1ull},
- {"WAITL_COM" , 20, 1, 442, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_63" , 21, 43, 442, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 443, "RO", 1, 1, 0, 0},
- {"HOST_MODE" , 8, 1, 443, "RO", 1, 1, 0, 0},
- {"PKT_BP" , 9, 4, 443, "R/W", 0, 0, 15ull, 15ull},
- {"ARB" , 13, 1, 443, "R/W", 0, 0, 0ull, 1ull},
- {"LNK_RST" , 14, 1, 443, "R/W1C", 0, 0, 0ull, 0ull},
- {"RING_EN" , 15, 1, 443, "R/W", 0, 0, 0ull, 0ull},
- {"CFG_RTRY" , 16, 16, 443, "R/W", 0, 0, 0ull, 32ull},
- {"P0_NTAGS" , 32, 6, 443, "R/W", 0, 0, 32ull, 32ull},
- {"P1_NTAGS" , 38, 6, 443, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_44_63" , 44, 20, 443, "RAZ", 1, 1, 0, 0},
- {"C0_B0_D" , 0, 1, 444, "R/W", 0, 0, 0ull, 0ull},
- {"C0_WI_D" , 1, 1, 444, "R/W", 0, 0, 0ull, 0ull},
- {"C1_B0_D" , 2, 1, 444, "R/W", 0, 0, 0ull, 0ull},
- {"C1_WI_D" , 3, 1, 444, "R/W", 0, 0, 0ull, 0ull},
- {"C0_B1_S" , 4, 3, 444, "R/W", 0, 0, 1ull, 1ull},
- {"C1_B1_S" , 7, 3, 444, "R/W", 0, 0, 1ull, 1ull},
- {"C0_W_FLT" , 10, 1, 444, "R/W", 0, 0, 0ull, 0ull},
- {"C1_W_FLT" , 11, 1, 444, "R/W", 0, 0, 0ull, 0ull},
- {"MRRS" , 12, 3, 444, "R/W", 0, 0, 2ull, 2ull},
- {"MPS" , 15, 1, 444, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 444, "RAZ", 1, 1, 0, 0},
- {"P0_FCNT" , 0, 6, 445, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 445, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 445, "RO", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 445, "RO", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 445, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 446, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 446, "R/W", 0, 0, 1ull, 0ull},
- {"C_MUL" , 18, 5, 446, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 23, 2, 446, "RO", 1, 1, 0, 0},
- {"QLM1_MODE" , 25, 2, 446, "RO", 1, 1, 0, 0},
- {"QLM0_REV_LANES" , 27, 1, 446, "RO", 1, 1, 0, 0},
- {"QLM0_LINK_WIDTH" , 28, 1, 446, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 446, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 16, 447, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 447, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 448, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 448, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 448, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 449, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 449, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 450, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 29, 450, "R/W", 0, 1, 0ull, 0},
- {"IDLE" , 36, 1, 450, "RO", 0, 1, 1ull, 0},
- {"RESERVED_37_63" , 37, 27, 450, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 451, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 451, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 452, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 452, "R/W", 0, 1, 0ull, 0},
- {"CNT" , 0, 32, 453, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 453, "R/W", 0, 1, 0ull, 0},
- {"DMA0" , 0, 32, 454, "R/W", 0, 1, 0ull, 0},
- {"DMA1" , 32, 32, 454, "R/W", 0, 1, 0ull, 0},
- {"CSIZE" , 0, 14, 455, "R/W", 0, 1, 0ull, 0},
- {"O_MODE" , 14, 1, 455, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 455, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 455, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 455, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 455, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 455, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 455, "R/W", 0, 0, 0ull, 0ull},
- {"DMA0_ENB" , 34, 1, 455, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1_ENB" , 35, 1, 455, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2_ENB" , 36, 1, 455, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3_ENB" , 37, 1, 455, "R/W", 0, 0, 0ull, 1ull},
- {"DMA4_ENB" , 38, 1, 455, "R/W", 0, 0, 0ull, 1ull},
- {"P_32B_M" , 39, 1, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 455, "RAZ", 1, 1, 0, 0},
- {"DMA_CNT" , 0, 5, 456, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_5_7" , 5, 3, 456, "RAZ", 1, 1, 0, 0},
- {"DMA0_CNT" , 8, 5, 456, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 456, "RAZ", 1, 1, 0, 0},
- {"DMA1_CNT" , 16, 5, 456, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_21_23" , 21, 3, 456, "RAZ", 1, 1, 0, 0},
- {"DMA2_CNT" , 24, 5, 456, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_29_31" , 29, 3, 456, "RAZ", 1, 1, 0, 0},
- {"DMA3_CNT" , 32, 5, 456, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_37_39" , 37, 3, 456, "RAZ", 1, 1, 0, 0},
- {"DMA4_CNT" , 40, 5, 456, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_45_47" , 45, 3, 456, "RAZ", 1, 1, 0, 0},
- {"PKT_CNT" , 48, 5, 456, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_53_62" , 53, 10, 456, "RAZ", 1, 1, 0, 0},
- {"DMA_ARB" , 63, 1, 456, "R/W", 0, 1, 1ull, 0},
- {"D0_DWE" , 0, 8, 457, "RO", 0, 1, 1ull, 0},
- {"D1_DWE" , 8, 8, 457, "RO", 0, 1, 1ull, 0},
- {"D2_DWE" , 16, 8, 457, "RO", 0, 1, 1ull, 0},
- {"D3_DWE" , 24, 8, 457, "RO", 0, 1, 1ull, 0},
- {"D4_DWE" , 32, 8, 457, "RO", 0, 1, 1ull, 0},
- {"RESERVED_40_63" , 40, 24, 457, "RAZ", 1, 1, 0, 0},
- {"PRD" , 0, 10, 458, "RO", 0, 1, 1ull, 0},
- {"RESERVED_10_15" , 10, 6, 458, "RAZ", 1, 1, 0, 0},
- {"NDRE" , 16, 5, 458, "RO", 0, 1, 1ull, 0},
- {"RESERVED_21_23" , 21, 3, 458, "RAZ", 1, 1, 0, 0},
- {"NDWE" , 24, 4, 458, "RO", 0, 1, 1ull, 0},
- {"RESERVED_28_63" , 28, 36, 458, "RAZ", 1, 1, 0, 0},
- {"DMA0_CPL" , 0, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1_CPL" , 1, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"PINS_ERR" , 2, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"POP_ERR" , 3, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"PDI_ERR" , 4, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"PGL_ERR" , 5, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"P0_RDLK" , 6, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"P1_RDLK" , 7, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"PIN_BP" , 8, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"POUT_ERR" , 9, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 459, "RAZ", 0, 1, 0ull, 0},
- {"DMA0_CPL" , 0, 1, 460, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1_CPL" , 1, 1, 460, "R/W", 0, 0, 0ull, 1ull},
- {"PINS_ERR" , 2, 1, 460, "R/W", 0, 0, 0ull, 1ull},
- {"POP_ERR" , 3, 1, 460, "R/W", 0, 0, 0ull, 1ull},
- {"PDI_ERR" , 4, 1, 460, "R/W", 0, 0, 0ull, 1ull},
- {"PGL_ERR" , 5, 1, 460, "R/W", 0, 0, 0ull, 1ull},
- {"P0_RDLK" , 6, 1, 460, "R/W", 0, 0, 0ull, 1ull},
- {"P1_RDLK" , 7, 1, 460, "R/W", 0, 0, 0ull, 1ull},
- {"PIN_BP" , 8, 1, 460, "R/W", 0, 0, 0ull, 1ull},
- {"POUT_ERR" , 9, 1, 460, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 460, "RAZ", 0, 1, 0ull, 0},
- {"DMA0_CPL" , 0, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1_CPL" , 1, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 2, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 3, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 4, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 5, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"P0_RDLK" , 6, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"P1_RDLK" , 7, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 8, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 9, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 461, "RAZ", 0, 0, 0ull, 0ull},
- {"RML_RTO" , 0, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0DBO" , 4, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1DBO" , 5, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2DBO" , 6, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3DBO" , 7, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DMA4DBO" , 8, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0FI" , 9, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1FI" , 10, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT0" , 11, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT1" , 12, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME0" , 13, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME1" , 14, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"PSLDBOF" , 15, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"PIDBOF" , 16, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 17, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 18, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_AERI" , 19, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_ER" , 20, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_SE" , 21, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_DR" , 22, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_WAKE" , 23, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_PMEI" , 24, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_HPINT" , 25, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_AERI" , 26, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_ER" , 27, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_SE" , 28, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_DR" , 29, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_WAKE" , 30, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_PMEI" , 31, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_HPINT" , 32, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B0" , 33, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B1" , 34, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B2" , 35, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WI" , 36, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_BX" , 37, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B0" , 38, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B1" , 39, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B2" , 40, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WI" , 41, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_BX" , 42, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B0" , 43, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B1" , 44, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B2" , 45, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WI" , 46, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_BX" , 47, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B0" , 48, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B1" , 49, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B2" , 50, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WI" , 51, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_BX" , 52, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WF" , 53, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WF" , 54, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WF" , 55, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WF" , 56, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_EXC" , 57, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_EXC" , 58, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C0_LDWN" , 59, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"C1_LDWN" , 60, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"INT_A" , 61, 1, 462, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_62_62" , 62, 1, 462, "RAZ", 0, 1, 0ull, 0},
- {"MIO_INTA" , 63, 1, 462, "R/W", 0, 0, 0ull, 1ull},
- {"RML_RTO" , 0, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"RML_WTO" , 1, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0DBO" , 4, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1DBO" , 5, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DMA2DBO" , 6, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DMA3DBO" , 7, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DMA4DBO" , 8, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DMA0FI" , 9, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DMA1FI" , 10, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT0" , 11, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DCNT1" , 12, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME0" , 13, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"DTIME1" , 14, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"PSLDBOF" , 15, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"PIDBOF" , 16, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 17, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 18, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_AERI" , 19, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_ER" , 20, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_SE" , 21, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"CRS0_DR" , 22, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_WAKE" , 23, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_PMEI" , 24, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_HPINT" , 25, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_AERI" , 26, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_ER" , 27, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_SE" , 28, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"CRS1_DR" , 29, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_WAKE" , 30, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_PMEI" , 31, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_HPINT" , 32, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B0" , 33, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B1" , 34, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_B2" , 35, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WI" , 36, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_BX" , 37, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B0" , 38, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B1" , 39, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_B2" , 40, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WI" , 41, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_BX" , 42, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B0" , 43, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B1" , 44, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_B2" , 45, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WI" , 46, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_BX" , 47, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B0" , 48, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B1" , 49, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_B2" , 50, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WI" , 51, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_BX" , 52, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UN_WF" , 53, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UN_WF" , 54, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_UP_WF" , 55, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_UP_WF" , 56, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_EXC" , 57, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_EXC" , 58, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C0_LDWN" , 59, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"C1_LDWN" , 60, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"INT_A" , 61, 1, 463, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_62_63" , 62, 2, 463, "RAZ", 0, 1, 0ull, 0},
- {"PSLDBOF" , 0, 6, 464, "RO", 0, 1, 0ull, 0},
- {"PIDBOF" , 6, 6, 464, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 464, "RAZ", 1, 1, 0, 0},
- {"RML_RTO" , 0, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0DBO" , 4, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1DBO" , 5, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA2DBO" , 6, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA3DBO" , 7, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA4DBO" , 8, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA0FI" , 9, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DMA1FI" , 10, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT0" , 11, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT1" , 12, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME0" , 13, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"DTIME1" , 14, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 15, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 16, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT" , 17, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"PTIME" , 18, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"C0_AERI" , 19, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"CRS0_ER" , 20, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_SE" , 21, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS0_DR" , 22, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_WAKE" , 23, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_PMEI" , 24, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"C0_HPINT" , 25, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"C1_AERI" , 26, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"CRS1_ER" , 27, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_SE" , 28, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS1_DR" , 29, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_WAKE" , 30, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_PMEI" , 31, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"C1_HPINT" , 32, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B0" , 33, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_B1" , 34, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_B2" , 35, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_WI" , 36, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_BX" , 37, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B0" , 38, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B1" , 39, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_B2" , 40, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_WI" , 41, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_BX" , 42, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B0" , 43, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B1" , 44, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_B2" , 45, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_WI" , 46, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_BX" , 47, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B0" , 48, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B1" , 49, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_B2" , 50, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_WI" , 51, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_BX" , 52, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UN_WF" , 53, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UN_WF" , 54, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_UP_WF" , 55, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_UP_WF" , 56, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C0_EXC" , 57, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"C1_EXC" , 58, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"C0_LDWN" , 59, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"C1_LDWN" , 60, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
- {"INT_A" , 61, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 465, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO_INTA" , 63, 1, 465, "RO", 0, 0, 0ull, 0ull},
- {"RML_RTO" , 0, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"RML_WTO" , 1, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"DMA0DBO" , 4, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"DMA1DBO" , 5, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"DMA2DBO" , 6, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"DMA3DBO" , 7, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 466, "RO", 1, 1, 0, 0},
- {"DMA0FI" , 9, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"DMA1FI" , 10, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"DCNT0" , 11, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"DCNT1" , 12, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"DTIME0" , 13, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"DTIME1" , 14, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_18" , 15, 4, 466, "RAZ", 0, 0, 0ull, 0ull},
- {"C0_AERI" , 19, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"CRS0_ER" , 20, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_SE" , 21, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"CRS0_DR" , 22, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_WAKE" , 23, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_PMEI" , 24, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_HPINT" , 25, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_AERI" , 26, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"CRS1_ER" , 27, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_SE" , 28, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"CRS1_DR" , 29, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_WAKE" , 30, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_PMEI" , 31, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_HPINT" , 32, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B0" , 33, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B1" , 34, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_B2" , 35, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_WI" , 36, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_BX" , 37, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_B0" , 38, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_B1" , 39, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_B2" , 40, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_WI" , 41, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_BX" , 42, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_B0" , 43, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_B1" , 44, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_B2" , 45, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_WI" , 46, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_BX" , 47, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_B0" , 48, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_B1" , 49, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_B2" , 50, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_WI" , 51, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_BX" , 52, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UN_WF" , 53, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UN_WF" , 54, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_UP_WF" , 55, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_UP_WF" , 56, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_EXC" , 57, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_EXC" , 58, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C0_LDWN" , 59, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"C1_LDWN" , 60, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"INT_A" , 61, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 466, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO_INTA" , 63, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 467, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 468, "RO", 0, 1, 0ull, 0},
- {"TIMER" , 0, 10, 469, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 469, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 469, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 30, 470, "R/W", 0, 1, 0ull, 0},
- {"ROW" , 30, 1, 470, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 31, 1, 470, "R/W", 0, 1, 0ull, 0},
- {"NSW" , 32, 1, 470, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 33, 1, 470, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 470, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 470, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 470, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 2, 470, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 41, 1, 470, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 470, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 471, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 472, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 473, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 474, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 475, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 476, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 477, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 478, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 479, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 479, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 479, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 64, 480, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 481, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 482, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 483, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 484, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 485, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 486, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 487, "R/W", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 488, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 488, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 488, "RAZ", 1, 1, 0, 0},
- {"P0_PCNT" , 0, 8, 489, "R/W", 0, 0, 128ull, 128ull},
- {"P0_NCNT" , 8, 8, 489, "R/W", 0, 0, 16ull, 16ull},
- {"P0_CCNT" , 16, 8, 489, "R/W", 0, 0, 128ull, 128ull},
- {"P1_PCNT" , 24, 8, 489, "R/W", 0, 0, 128ull, 128ull},
- {"P1_NCNT" , 32, 8, 489, "R/W", 0, 0, 16ull, 16ull},
- {"P1_CCNT" , 40, 8, 489, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_48_63" , 48, 16, 489, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 490, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 490, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 491, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 491, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 491, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 492, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 492, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 493, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 493, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 493, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 494, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 32, 22, 494, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 494, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 495, "R/W", 0, 0, 0ull, 0ull},
- {"WMARK" , 32, 32, 495, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_0_2" , 0, 3, 496, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 496, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 497, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 497, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 498, "R/W", 0, 1, 0ull, 0},
- {"FCNT" , 32, 5, 498, "RO", 0, 1, 0ull, 0},
- {"WRP" , 37, 9, 498, "RO", 0, 1, 0ull, 0},
- {"RRP" , 46, 9, 498, "RO", 0, 1, 0ull, 0},
- {"MAX" , 55, 9, 498, "RO", 0, 1, 16ull, 0},
- {"RESERVED_0_5" , 0, 6, 499, "RAZ", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 499, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_13" , 13, 1, 499, "RAZ", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 499, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_20" , 16, 5, 499, "RAZ", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 499, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_27" , 22, 6, 499, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 499, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_35" , 35, 1, 499, "RAZ", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 499, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_42" , 38, 5, 499, "RAZ", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 499, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 499, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 500, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 4, 60, 500, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 501, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 501, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 502, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 502, "RAZ", 0, 1, 0ull, 0},
- {"PORT" , 0, 32, 503, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 503, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 504, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 504, "RAZ", 1, 1, 0, 0},
- {"ES" , 0, 64, 505, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 506, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 506, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 507, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 507, "RAZ", 1, 1, 0, 0},
- {"DPTR" , 0, 32, 508, "R/W", 0, 0, 0ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 508, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 32, 509, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 509, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 510, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 510, "RAZ", 0, 1, 0ull, 0},
- {"RD_CNT" , 0, 32, 511, "RO", 0, 1, 0ull, 0},
- {"WR_CNT" , 32, 32, 511, "RO", 0, 1, 0ull, 0},
- {"PP" , 0, 64, 512, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 0, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 513, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 513, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 513, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 513, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 22, 1, 513, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_23_63" , 23, 41, 513, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 514, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 514, "RAZ", 1, 1, 0, 0},
- {"RDSIZE" , 0, 64, 515, "R/W", 0, 1, 0ull, 0},
- {"IS_64B" , 0, 32, 516, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 516, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 517, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 22, 517, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_63" , 54, 10, 517, "RAZ", 1, 1, 0, 0},
- {"IPTR" , 0, 32, 518, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 518, "RAZ", 1, 1, 0, 0},
- {"BMODE" , 0, 32, 519, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 519, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 520, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 520, "RAZ", 1, 1, 0, 0},
- {"WMARK" , 0, 32, 521, "R/W", 0, 0, 0ull, 14ull},
- {"RESERVED_32_63" , 32, 32, 521, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 64, 522, "R/W", 0, 1, 0ull, 0},
- {"OUT_RST" , 0, 32, 523, "RO", 0, 1, 0ull, 0},
- {"IN_RST" , 32, 32, 523, "RO", 0, 1, 0ull, 0},
- {"ES" , 0, 64, 524, "R/W", 0, 1, 0ull, 0},
- {"BSIZE" , 0, 16, 525, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 16, 7, 525, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 525, "RAZ", 1, 1, 0, 0},
- {"NSR" , 0, 32, 526, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 526, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 527, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 527, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 528, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 528, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 529, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 529, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"NPEI" , 3, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD" , 9, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 14, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"USB1" , 15, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 16, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 17, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"SPX0" , 18, 1, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"SPX1" , 19, 1, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"PIP" , 20, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"ASXPCS0" , 22, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"ASXPCS1" , 23, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_27" , 24, 4, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"AGL" , 28, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"LMC1" , 29, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 30, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 530, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 531, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 532, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 532, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 532, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 532, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 533, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 533, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 533, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 533, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 533, "RO", 0, 1, 1ull, 0},
- {"NPEI" , 47, 1, 533, "RO", 0, 1, 1ull, 0},
- {"RESERVED_48_63" , 48, 16, 533, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 534, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 534, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 534, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 534, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 534, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 535, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 535, "RAZ", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 535, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_51_63" , 51, 13, 535, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 536, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_1" , 0, 2, 537, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 2, 46, 537, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 537, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 537, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 538, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 539, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 539, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 540, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 540, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 541, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 541, "RO/WRSL", 0, 0, 128ull, 128ull},
- {"ISAE" , 0, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 542, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 542, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 542, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 542, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 542, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 543, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 543, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 543, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 543, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 544, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 544, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 544, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 544, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 544, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 545, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 545, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 545, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 545, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 545, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 546, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 546, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 547, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 548, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 549, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 549, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 549, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 549, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 549, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 550, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 550, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 551, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 552, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 553, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 553, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 553, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 553, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 554, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 554, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_6" , 0, 7, 555, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 7, 25, 555, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 556, "WORSL", 0, 0, 127ull, 127ull},
- {"CISP" , 0, 32, 557, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 558, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 558, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 559, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 559, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 559, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 560, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 560, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"CP" , 0, 8, 561, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 561, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 562, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 562, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 562, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 562, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 563, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 563, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 563, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 563, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 563, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 564, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 564, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 564, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 564, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 564, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 564, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 564, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 564, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 564, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 565, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 565, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 565, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 565, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 565, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 565, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 565, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 566, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 566, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 567, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 568, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 568, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 569, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 569, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 569, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 569, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 569, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 569, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 569, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 570, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 570, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 570, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 570, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 570, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 570, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 570, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 570, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 570, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 570, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 570, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 571, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 571, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 571, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 571, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 571, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 571, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 571, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 571, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 571, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 572, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MLW" , 4, 6, 572, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"ASLPMS" , 10, 2, 572, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 572, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 572, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 572, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 572, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 572, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 572, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 572, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 572, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 573, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 573, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 573, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 573, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 573, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 573, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 573, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 573, "RO", 0, 0, 0ull, 8ull},
- {"RESERVED_26_26" , 26, 1, 573, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 573, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 573, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 573, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 573, "RAZ", 1, 1, 0, 0},
- {"ABP" , 0, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 575, "R/W", 0, 0, 0ull, 0ull},
- {"PIC" , 8, 2, 575, "R/W", 0, 0, 0ull, 0ull},
- {"PCC" , 10, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 575, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"EMIS" , 23, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 575, "RAZ", 1, 1, 0, 0},
- {"CTRS" , 0, 4, 576, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 576, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 576, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 577, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 577, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 577, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 578, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 579, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 580, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 581, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 582, "RO", 0, 0, 1ull, 0ull},
- {"CV" , 16, 4, 582, "RO", 0, 0, 1ull, 0ull},
- {"NCO" , 20, 12, 582, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 583, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 583, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 583, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 583, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 584, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 584, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 584, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 584, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 584, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 585, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 585, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 585, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 585, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 585, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 585, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 585, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 585, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 586, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 586, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 586, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 587, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 587, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 587, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 587, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 588, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 588, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 588, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 588, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 588, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 588, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 589, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 590, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 591, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 592, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 593, "R/W", 0, 0, 4143ull, 4143ull},
- {"RTL" , 16, 16, 593, "R/W", 0, 0, 12429ull, 12429ull},
- {"OMR" , 0, 32, 594, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 595, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 595, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 595, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 595, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 595, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 596, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 596, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 596, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 596, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 596, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 596, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 597, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 597, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 597, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 597, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 597, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_22_24" , 22, 3, 597, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 597, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 598, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 598, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 599, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 599, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 599, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 599, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 599, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 599, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 599, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 600, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 600, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_BAR_MATCH" , 18, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 601, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 602, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 603, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 604, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 604, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 604, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 605, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 605, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 605, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 606, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 606, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 606, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 607, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 607, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 607, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 607, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 608, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 608, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 608, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 608, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 609, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 609, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 609, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 609, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 610, "RO/WRSL", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 610, "RO/WRSL", 0, 0, 35ull, 35ull},
- {"RESERVED_20_20" , 20, 1, 610, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 610, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 610, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 610, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 610, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 611, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"HEADER_CREDITS" , 12, 8, 611, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"RESERVED_20_20" , 20, 1, 611, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 611, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 611, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 612, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 612, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 612, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 612, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 612, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 613, "RO/WRSL", 0, 0, 331ull, 331ull},
- {"RESERVED_14_15" , 14, 2, 613, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 613, "RO/WRSL", 0, 0, 41ull, 41ull},
- {"RESERVED_26_31" , 26, 6, 613, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 614, "RO/WRSL", 0, 0, 56ull, 56ull},
- {"RESERVED_14_15" , 14, 2, 614, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 614, "RO/WRSL", 0, 0, 14ull, 14ull},
- {"RESERVED_26_31" , 26, 6, 614, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 615, "RO/WRSL", 0, 0, 360ull, 360ull},
- {"RESERVED_14_15" , 14, 2, 615, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 615, "RO/WRSL", 0, 0, 70ull, 70ull},
- {"RESERVED_26_31" , 26, 6, 615, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 616, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 617, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 618, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 618, "R/W", 0, 0, 128ull, 128ull},
- {"ISAE" , 0, 1, 619, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 619, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 619, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 619, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 619, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 619, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 619, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 619, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 619, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 619, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 620, "R/W", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 620, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 620, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 620, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 621, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 621, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 621, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 621, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 622, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 623, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 624, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 624, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 624, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 624, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 625, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 625, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 625, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 625, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 625, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 625, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 625, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 625, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 625, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 625, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 625, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 626, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 626, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 626, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 626, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 627, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 627, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 627, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 627, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 627, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 627, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 628, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 629, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 630, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 630, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 631, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 631, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 632, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 633, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 633, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 633, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 633, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 634, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 634, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 634, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 634, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 634, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 634, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 634, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 634, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 634, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 634, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 635, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 635, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 635, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 635, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 635, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 635, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 635, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 635, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 635, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 635, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 635, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 635, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 636, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 636, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 636, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 636, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 636, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 636, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 637, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 637, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 638, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 639, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 639, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 640, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 640, "R/W", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 640, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 640, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 640, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 640, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 640, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 641, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 641, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 641, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 641, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 641, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 641, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 641, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 641, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 641, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 641, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 641, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 642, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 642, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 642, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 642, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 642, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 642, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 642, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 642, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 642, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 642, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 642, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 642, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 642, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 643, "R/W", 0, 0, 1ull, 1ull},
- {"MLW" , 4, 6, 643, "R/W", 0, 0, 8ull, 8ull},
- {"ASLPMS" , 10, 2, 643, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 643, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 643, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 643, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 643, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 643, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_23" , 22, 2, 643, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 643, "R/W", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 644, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 644, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 644, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 644, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 644, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 644, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 644, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 644, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 644, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 644, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 645, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 645, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 645, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 646, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 646, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 646, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 646, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 646, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 646, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 646, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 647, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 647, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 647, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 647, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 648, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 648, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 648, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 649, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 649, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 649, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 650, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 650, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 650, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 651, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 652, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 653, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 654, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 655, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 655, "RO", 0, 0, 1ull, 1ull},
- {"NCO" , 20, 12, 655, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 656, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 656, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 656, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 656, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 657, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 657, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 657, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 657, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 658, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 658, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 658, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 658, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 658, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 658, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 658, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 658, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 659, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 659, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 659, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 660, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 660, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 660, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 660, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 661, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 661, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 661, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 661, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 662, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 663, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 664, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 665, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 666, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 667, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 667, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 668, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 668, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 669, "R/W", 0, 0, 4143ull, 4143ull},
- {"RTL" , 16, 16, 669, "R/W", 0, 0, 12429ull, 12429ull},
- {"OMR" , 0, 32, 670, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 671, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 671, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 671, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 671, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 671, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 672, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 672, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 672, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 672, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 672, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 672, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 673, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 673, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 673, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 673, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 673, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_22_24" , 22, 3, 673, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 673, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 674, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 674, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 675, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 675, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 675, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 675, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 675, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 675, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 675, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 675, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 676, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 676, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_BAR_MATCH" , 18, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 677, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 678, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 679, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 680, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 680, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 680, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 681, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 681, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 681, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 682, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 682, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 682, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 683, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 683, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 683, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 683, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 684, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 684, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 684, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 684, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 685, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 685, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 685, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 685, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 686, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 686, "R/W", 0, 0, 35ull, 35ull},
- {"RESERVED_20_20" , 20, 1, 686, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 686, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 686, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 686, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 686, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 687, "R/W", 0, 0, 4ull, 4ull},
- {"HEADER_CREDITS" , 12, 8, 687, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_20_20" , 20, 1, 687, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 687, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 687, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 688, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 688, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_20_20" , 20, 1, 688, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 688, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 688, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 689, "R/W", 0, 0, 331ull, 331ull},
- {"RESERVED_14_15" , 14, 2, 689, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 689, "R/W", 0, 0, 41ull, 41ull},
- {"RESERVED_26_31" , 26, 6, 689, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 690, "R/W", 0, 0, 56ull, 56ull},
- {"RESERVED_14_15" , 14, 2, 690, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 690, "R/W", 0, 0, 14ull, 14ull},
- {"RESERVED_26_31" , 26, 6, 690, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 691, "R/W", 0, 0, 360ull, 360ull},
- {"RESERVED_14_15" , 14, 2, 691, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 691, "R/W", 0, 0, 70ull, 70ull},
- {"RESERVED_26_31" , 26, 6, 691, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 692, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 693, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 694, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 694, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 694, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 694, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 694, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 694, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 694, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 694, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 695, "RAZ", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 695, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 695, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 695, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 695, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 695, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 696, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 696, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 696, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 696, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 696, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 696, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 696, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 696, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 696, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 697, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 697, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 697, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 697, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 697, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 697, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 698, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_12_63" , 12, 52, 698, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 699, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 700, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 700, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 701, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 701, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 701, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 701, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 702, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 702, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 702, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 702, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 702, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 702, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 702, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 702, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 703, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 703, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 703, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 703, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 703, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 703, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 704, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 704, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 704, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 704, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 704, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 704, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 704, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 705, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 705, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 705, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 705, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 705, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 705, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 705, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 706, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 707, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 707, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 707, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 707, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 707, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 707, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 707, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 708, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 708, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 708, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 708, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 708, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 708, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 708, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 709, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 709, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 709, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 709, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 710, "RAZ", 1, 1, 0, 0},
- {"L0SYNC" , 0, 1, 711, "RO", 0, 0, 0ull, 1ull},
- {"L1SYNC" , 1, 1, 711, "RO", 0, 0, 0ull, 1ull},
- {"L2SYNC" , 2, 1, 711, "RO", 0, 0, 0ull, 1ull},
- {"L3SYNC" , 3, 1, 711, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_4_10" , 4, 7, 711, "RAZ", 1, 1, 0, 0},
- {"PATTST" , 11, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"ALIGND" , 12, 1, 711, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_63" , 13, 51, 711, "RAZ", 1, 1, 0, 0},
- {"BIST_STATUS" , 0, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 712, "RAZ", 1, 1, 0, 0},
- {"BITLCK0" , 0, 1, 713, "RO", 0, 1, 0ull, 0},
- {"BITLCK1" , 1, 1, 713, "RO", 0, 1, 0ull, 0},
- {"BITLCK2" , 2, 1, 713, "RO", 0, 1, 0ull, 0},
- {"BITLCK3" , 3, 1, 713, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 713, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 714, "RAZ", 1, 1, 0, 0},
- {"SPD" , 2, 4, 714, "RO", 0, 0, 0ull, 0ull},
- {"SPDSEL0" , 6, 1, 714, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_10" , 7, 4, 714, "RAZ", 1, 1, 0, 0},
- {"LO_PWR" , 11, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 714, "RAZ", 1, 1, 0, 0},
- {"SPDSEL1" , 13, 1, 714, "RO", 0, 0, 1ull, 1ull},
- {"LOOPBCK1" , 14, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 714, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 714, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 715, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 715, "RAZ", 1, 1, 0, 0},
- {"TXFLT_EN" , 0, 1, 716, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 1, 1, 716, "R/W", 0, 0, 0ull, 1ull},
- {"RXSYNBAD_EN" , 2, 1, 716, "R/W", 0, 0, 0ull, 1ull},
- {"BITLCKLS_EN" , 3, 1, 716, "R/W", 0, 0, 0ull, 1ull},
- {"SYNLOS_EN" , 4, 1, 716, "R/W", 0, 0, 0ull, 1ull},
- {"ALGNLOS_EN" , 5, 1, 716, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 716, "RAZ", 1, 1, 0, 0},
- {"TXFLT" , 0, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 1, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXSYNBAD" , 2, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"BITLCKLS" , 3, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNLOS" , 4, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALGNLOS" , 5, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 717, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 718, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
- {"DROP_LN" , 4, 2, 718, "R/W", 0, 0, 0ull, 0ull},
- {"ENC_MODE" , 6, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 718, "RAZ", 1, 1, 0, 0},
- {"GMXENO" , 0, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"XAUI" , 1, 1, 719, "RO", 1, 1, 0, 0},
- {"RX_SWAP" , 2, 1, 719, "R/W", 0, 1, 0ull, 0},
- {"TX_SWAP" , 3, 1, 719, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 719, "RAZ", 1, 1, 0, 0},
- {"SYNC0ST" , 0, 4, 720, "RO", 0, 1, 0ull, 0},
- {"SYNC1ST" , 4, 4, 720, "RO", 0, 1, 0ull, 0},
- {"SYNC2ST" , 8, 4, 720, "RO", 0, 1, 0ull, 0},
- {"SYNC3ST" , 12, 4, 720, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 720, "RAZ", 1, 1, 0, 0},
- {"TENGB" , 0, 1, 721, "RO", 0, 0, 1ull, 1ull},
- {"TENPASST" , 1, 1, 721, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 721, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 722, "RAZ", 1, 1, 0, 0},
- {"LPABLE" , 1, 1, 722, "RO", 0, 0, 1ull, 1ull},
- {"RCV_LNK" , 2, 1, 722, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_3_6" , 3, 4, 722, "RAZ", 1, 1, 0, 0},
- {"FLT" , 7, 1, 722, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 722, "RAZ", 1, 1, 0, 0},
- {"TENGB_R" , 0, 1, 723, "RO", 0, 0, 0ull, 0ull},
- {"TENGB_X" , 1, 1, 723, "RO", 0, 0, 1ull, 1ull},
- {"TENGB_W" , 2, 1, 723, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_9" , 3, 7, 723, "RAZ", 1, 1, 0, 0},
- {"RCVFLT" , 10, 1, 723, "RC", 0, 0, 0ull, 0ull},
- {"XMTFLT" , 11, 1, 723, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 723, "RAZ", 1, 1, 0, 0},
- {"DEV" , 14, 2, 723, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_16_63" , 16, 48, 723, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 724, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 724, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_TXPLRT" , 2, 4, 724, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_RXPLRT" , 6, 4, 724, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 724, "RAZ", 1, 1, 0, 0},
- {"TX_ST" , 0, 3, 725, "RO", 0, 1, 0ull, 0},
- {"RX_ST" , 3, 2, 725, "RO", 0, 1, 0ull, 0},
- {"ALGN_ST" , 5, 3, 725, "RO", 0, 1, 0ull, 0},
- {"RXBAD" , 8, 1, 725, "RO", 0, 0, 0ull, 0ull},
- {"SYN0BAD" , 9, 1, 725, "RO", 0, 0, 0ull, 0ull},
- {"SYN1BAD" , 10, 1, 725, "RO", 0, 0, 0ull, 0ull},
- {"SYN2BAD" , 11, 1, 725, "RO", 0, 0, 0ull, 0ull},
- {"SYN3BAD" , 12, 1, 725, "RO", 0, 0, 0ull, 0ull},
- {"TERM_ERR" , 13, 1, 725, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 725, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA4" , 3, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 4, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 5, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 6, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 7, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 8, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"PTLP_OR" , 9, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"NTLP_OR" , 10, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"CTLP_OR" , 11, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA5" , 12, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 726, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"RSL_P2E" , 6, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 7, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"DBG_P2E" , 8, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"E2P_RSL" , 9, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 10, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 11, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 12, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"CTO_P2E" , 13, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 727, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 728, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 728, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 729, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 729, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 730, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 730, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 731, "RAZ", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 731, "RAZ", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"LANE_SWP" , 12, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"QLM_CFG" , 13, 2, 731, "RO", 1, 1, 0, 0},
- {"PBUS" , 15, 8, 731, "RO", 1, 1, 0, 0},
- {"DNUM" , 23, 5, 731, "RO", 1, 1, 0, 0},
- {"RESERVED_28_63" , 28, 36, 731, "RAZ", 1, 1, 0, 0},
- {"PCIERST" , 0, 1, 732, "RO", 0, 0, 0ull, 0ull},
- {"PCLK_RUN" , 1, 1, 732, "R/W1C", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 732, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 733, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 734, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 735, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 735, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 735, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 735, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 735, "RO", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 736, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 736, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 737, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 737, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_38" , 0, 39, 738, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 39, 25, 738, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 739, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 739, "R/W", 0, 1, 4503599627370495ull, 0},
- {"RESERVED_0_11" , 0, 12, 740, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 740, "R/W", 0, 1, 4503599627370495ull, 0},
- {"NPEI_P" , 0, 8, 741, "R/W", 0, 0, 128ull, 128ull},
- {"NPEI_NP" , 8, 8, 741, "R/W", 0, 0, 16ull, 16ull},
- {"NPEI_CPL" , 16, 8, 741, "R/W", 0, 0, 128ull, 128ull},
- {"PESC_P" , 24, 8, 741, "R/W", 0, 0, 128ull, 128ull},
- {"PESC_NP" , 32, 8, 741, "R/W", 0, 0, 16ull, 16ull},
- {"PESC_CPL" , 40, 8, 741, "R/W", 0, 0, 128ull, 128ull},
- {"PEAI_PPF" , 48, 8, 741, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_56_63" , 56, 8, 741, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 18, 742, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 742, "RAZ", 1, 1, 0, 0},
- {"DPRT" , 0, 16, 743, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 743, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 743, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 743, "RAZ", 1, 1, 0, 0},
- {"MAP0" , 0, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 744, "R/W", 0, 0, 0ull, 0ull},
- {"MAP0" , 0, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 745, "R/W", 0, 0, 0ull, 0ull},
- {"MINLEN" , 0, 16, 746, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 746, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 746, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 747, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 747, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 747, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 747, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 748, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 748, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 748, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 748, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 748, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 748, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 748, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 748, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 748, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 748, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 748, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 748, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 748, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 748, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 748, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 748, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 20, 1, 748, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 748, "RAZ", 1, 1, 0, 0},
- {"DSA_GRP_SID" , 24, 1, 748, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SCMD" , 25, 1, 748, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_TVID" , 26, 1, 748, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 748, "RAZ", 1, 1, 0, 0},
- {"PRI" , 0, 6, 749, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 749, "RAZ", 1, 1, 0, 0},
- {"QOS" , 8, 3, 749, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 749, "RAZ", 1, 1, 0, 0},
- {"UP_QOS" , 12, 1, 749, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_13_63" , 13, 51, 749, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 750, "RAZ", 1, 1, 0, 0},
- {"BCKPRS" , 2, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 750, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 750, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 751, "RAZ", 1, 1, 0, 0},
- {"BCKPRS" , 2, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 751, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 752, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 752, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 753, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 753, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 753, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_EN" , 10, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"HIGIG_EN" , 11, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"CRC_EN" , 12, 1, 753, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 753, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VSEL" , 19, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 753, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 753, "R/W", 0, 0, 0ull, 0ull},
- {"HG_QOS" , 27, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT" , 28, 4, 753, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 753, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 753, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 753, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 753, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 753, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 753, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 753, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_63" , 53, 11, 753, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 754, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 754, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 754, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 754, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 754, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 754, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 755, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 755, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 756, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 756, "RAZ", 1, 1, 0, 0},
- {"QOS1" , 4, 3, 756, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 756, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 757, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 757, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 757, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 757, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 757, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 757, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 757, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 757, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 757, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 758, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 758, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 759, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 759, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 760, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 760, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 761, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 761, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 762, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 762, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 763, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 763, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 764, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 764, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 765, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 765, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 766, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 766, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 767, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 767, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 768, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 768, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 769, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 769, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 770, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 770, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 771, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 771, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 772, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 772, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 773, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 773, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 774, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 774, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 775, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 775, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 776, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 776, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 776, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 777, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 777, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 777, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 778, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 778, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 779, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 779, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 780, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 780, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 780, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 780, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 781, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 781, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 781, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 781, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 781, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 782, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 782, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 782, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 782, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 783, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 783, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 783, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 783, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 783, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 783, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 783, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 783, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 784, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 784, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 784, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 784, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 785, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 785, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 785, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 785, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 785, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 786, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 787, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 787, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 787, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 787, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 787, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 788, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 789, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 789, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 789, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 789, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 789, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 789, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 789, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 789, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 789, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 789, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 789, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 789, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 789, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 790, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 790, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 790, "RO", 1, 0, 0, 0ull},
- {"RESERVED_54_63" , 54, 10, 790, "RAZ", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 791, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 791, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 791, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 791, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 791, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 791, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 791, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 791, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 791, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 791, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 791, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 791, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 791, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 792, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 792, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 792, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 792, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 792, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 792, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 793, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 793, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 793, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 793, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 6, 1, 793, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 793, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 793, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 793, "RO", 1, 0, 0, 0ull},
- {"RESERVED_29_63" , 29, 35, 793, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 794, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 794, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 794, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 794, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 795, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 795, "R/W", 1, 0, 0, 0ull},
- {"BP_PORT" , 10, 6, 795, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_52" , 16, 37, 795, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 795, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 61, 1, 795, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_62_63" , 62, 2, 795, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 796, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 796, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_10_52" , 10, 43, 796, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 796, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 796, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 797, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 797, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 797, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 797, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 797, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 798, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 798, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 798, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 798, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 799, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 799, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 799, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 799, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 799, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 799, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 799, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 799, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 799, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 800, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 800, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 800, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 800, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 800, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 801, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 801, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 801, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 801, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 801, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 801, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 8, 801, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 801, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 801, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 801, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 801, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 3, 801, "RO", 1, 0, 0, 0ull},
- {"OUT_DAT" , 32, 1, 801, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 801, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 801, "RO", 1, 0, 0, 0ull},
- {"RESERVED_35_63" , 35, 29, 801, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 802, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 802, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 802, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 802, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 803, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 804, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 805, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 806, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 807, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE1" , 4, 4, 807, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE2" , 8, 4, 807, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE3" , 12, 4, 807, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE4" , 16, 4, 807, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE5" , 20, 4, 807, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE6" , 24, 4, 807, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE7" , 28, 4, 807, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE8" , 32, 4, 807, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE9" , 36, 4, 807, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_40_63" , 40, 24, 807, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 10, 808, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 808, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 809, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 809, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 809, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 809, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 810, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 810, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 810, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 810, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 810, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 811, "R/W", 0, 0, 2ull, 2ull},
- {"MODE1" , 3, 3, 811, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 811, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 812, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 812, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 812, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 812, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 813, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 813, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 814, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 814, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 814, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 815, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 815, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 815, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 1, 816, "RO", 0, 0, 0ull, 0ull},
- {"PEND" , 1, 1, 816, "RO", 0, 0, 0ull, 0ull},
- {"NBR0" , 2, 1, 816, "RO", 0, 0, 0ull, 0ull},
- {"NBR1" , 3, 1, 816, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 4, 1, 816, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 5, 1, 816, "RO", 0, 0, 0ull, 0ull},
- {"NBT0" , 6, 1, 816, "RO", 0, 0, 0ull, 0ull},
- {"NBT1" , 7, 1, 816, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 8, 1, 816, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 816, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 4, 816, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 816, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 817, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 817, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 818, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 818, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 818, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 818, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 818, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 818, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 818, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 818, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 818, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 818, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 818, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 818, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 818, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 819, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 819, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 820, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 820, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 821, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 821, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 822, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 822, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 823, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 823, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 824, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 824, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 10, 825, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 825, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 826, "R/W", 0, 0, 0ull, 1023ull},
- {"RESERVED_10_63" , 10, 54, 826, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 827, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 827, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 828, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 828, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 828, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 828, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 828, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 828, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 828, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 828, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 828, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 828, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 829, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 829, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 829, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 829, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 829, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 9, 830, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 830, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 9, 830, "R/W", 0, 1, 511ull, 0},
- {"RESERVED_21_23" , 21, 3, 830, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 10, 830, "RO", 0, 1, 503ull, 0},
- {"RESERVED_34_35" , 34, 2, 830, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 36, 10, 830, "RO", 0, 1, 0ull, 0},
- {"RESERVED_46_47" , 46, 2, 830, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 48, 10, 830, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 830, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 831, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 831, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 832, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 832, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 833, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 833, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 834, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 834, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 834, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 10, 835, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_11" , 10, 2, 835, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 12, 10, 835, "RO", 0, 1, 0ull, 0},
- {"RESERVED_22_23" , 22, 2, 835, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 24, 4, 835, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 835, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 836, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 836, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 836, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 836, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 836, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 9, 837, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 837, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 9, 837, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_23" , 21, 3, 837, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 837, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 837, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 837, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 838, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 838, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 839, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 840, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 841, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 842, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 842, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 842, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 842, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 842, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 843, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 843, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 843, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 843, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 843, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 844, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 844, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 844, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 844, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 845, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 845, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 845, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 845, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 845, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 845, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 845, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 845, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 845, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 845, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 846, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 847, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 847, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 847, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 848, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 848, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 848, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 848, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 848, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 848, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 848, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 849, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 849, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 850, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 851, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 852, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 853, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 853, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 853, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 853, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 853, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 853, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 853, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 853, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 853, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 853, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 853, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 853, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 853, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 853, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 853, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 853, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 853, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 853, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 854, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 854, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 854, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 855, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 855, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 856, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 856, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 856, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 857, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 857, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 857, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 857, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 857, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 857, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 857, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 858, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 858, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 859, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 860, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 860, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 861, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 861, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 861, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 862, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 862, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 862, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 863, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 863, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 864, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 864, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 864, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 864, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 864, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 864, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 864, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 865, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 865, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 865, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 865, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 865, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 865, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 866, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 866, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 867, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 867, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 867, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 867, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 868, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 868, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 868, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 868, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 869, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 869, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 869, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 869, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 869, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 869, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 870, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 870, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 870, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 871, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 871, "RAZ", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 871, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 871, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 871, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 872, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 872, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 872, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 872, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 873, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 873, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 873, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 873, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 873, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 873, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 874, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 874, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 874, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 874, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 875, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 875, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 876, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 876, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 876, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 876, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 877, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 877, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 878, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 878, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 878, "RAZ", 1, 1, 0, 0},
- {"TDF0" , 0, 1, 879, "RO", 0, 0, 0ull, 0ull},
- {"TDF1" , 1, 1, 879, "RO", 0, 0, 0ull, 0ull},
- {"TCF" , 2, 1, 879, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 879, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 880, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 880, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 880, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 880, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 881, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 881, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 881, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 882, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 882, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 882, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 882, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 882, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 883, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 883, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 884, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 884, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 885, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 886, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 886, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 886, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 886, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 887, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 887, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 887, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 887, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 887, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 887, "RAZ", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 888, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 889, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 890, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 890, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 891, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 891, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 892, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 892, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 893, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 893, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 893, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 893, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 893, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 893, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 893, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 893, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 893, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 893, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 893, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 893, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 894, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 894, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 895, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 895, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 36, 896, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 896, "RAZ", 0, 0, 0ull, 0ull},
- {"DWB" , 0, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 1, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 2, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"LDD" , 3, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 4, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 5, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 6, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 7, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 8, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 9, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 10, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 11, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 12, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 13, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST" , 14, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"IOBDMA" , 15, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"SAA" , 16, 1, 897, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_17_63" , 17, 47, 897, "RAZ", 0, 0, 0ull, 0ull},
- {"MIO" , 0, 1, 898, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 898, "R/W", 0, 0, 0ull, 3ull},
- {"PCI" , 3, 1, 898, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 898, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 898, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 898, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 898, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 898, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 9, 3, 898, "R/W", 0, 0, 0ull, 7ull},
- {"POW" , 12, 1, 898, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 13, 19, 898, "R/W", 0, 0, 0ull, 524287ull},
- {"RESERVED_32_63" , 32, 32, 898, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 16, 899, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 899, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 899, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 899, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 899, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 899, "RAZ", 0, 0, 0ull, 0ull},
- {"INEPINT" , 0, 16, 900, "RO", 0, 0, 0ull, 0ull},
- {"OUTEPINT" , 16, 16, 900, "RO", 0, 0, 0ull, 0ull},
- {"INEPMSK" , 0, 16, 901, "R/W", 0, 0, 0ull, 0ull},
- {"OUTEPMSK" , 16, 16, 901, "R/W", 0, 0, 0ull, 0ull},
- {"DEVSPD" , 0, 2, 902, "R/W", 0, 0, 0ull, 0ull},
- {"NZSTSOUTHSHK" , 2, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 902, "RAZ", 1, 1, 0, 0},
- {"DEVADDR" , 4, 7, 902, "R/W", 0, 0, 0ull, 0ull},
- {"PERFRINT" , 11, 2, 902, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_17" , 13, 5, 902, "RAZ", 1, 1, 0, 0},
- {"EPMISCNT" , 18, 5, 902, "R/W", 0, 0, 8ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 902, "RAZ", 1, 1, 0, 0},
- {"RMTWKUPSIG" , 0, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"SFTDISCON" , 1, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"GNPINNAKSTS" , 2, 1, 903, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKSTS" , 3, 1, 903, "RO", 0, 0, 0ull, 0ull},
- {"TSTCTL" , 4, 3, 903, "R/W", 0, 0, 0ull, 0ull},
- {"SGNPINNAK" , 7, 1, 903, "WO", 0, 0, 0ull, 0ull},
- {"CGNPINNAK" , 8, 1, 903, "WO", 0, 0, 0ull, 0ull},
- {"SGOUTNAK" , 9, 1, 903, "WO", 0, 0, 0ull, 0ull},
- {"CGOUTNAK" , 10, 1, 903, "WO", 0, 0, 0ull, 0ull},
- {"PWRONPRGDONE" , 11, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 903, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 904, "R/W", 0, 0, 0ull, 0ull},
- {"NEXTEP" , 11, 4, 904, "R/W", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 904, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 904, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 904, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 904, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 904, "RAZ", 1, 1, 0, 0},
- {"STALL" , 21, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 22, 4, 904, "R/W", 0, 0, 0ull, 0ull},
- {"CNAK" , 26, 1, 904, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 904, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 904, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 904, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIMEOUT" , 3, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMP" , 4, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTKNEPMIS" , 5, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"INEPNAKEFF" , 6, 1, 905, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 905, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"TIMEOUTMSK" , 3, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNTXFEMPMSK" , 4, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNEPMISMSK" , 5, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"INEPNAKEFFMSK" , 6, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 906, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 907, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 907, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 907, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 907, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 908, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_14" , 11, 4, 908, "RAZ", 0, 0, 0ull, 0ull},
- {"USBACTEP" , 15, 1, 908, "R/W", 0, 0, 1ull, 0ull},
- {"DPID" , 16, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"NAKSTS" , 17, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 908, "R/W", 0, 0, 0ull, 0ull},
- {"SNP" , 20, 1, 908, "R/W", 0, 0, 0ull, 0ull},
- {"STALL" , 21, 1, 908, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_25" , 22, 4, 908, "RAZ", 1, 1, 0, 0},
- {"CNAK" , 26, 1, 908, "WO", 0, 0, 0ull, 0ull},
- {"SNAK" , 27, 1, 908, "WO", 0, 0, 0ull, 0ull},
- {"SETD0PID" , 28, 1, 908, "WO", 0, 0, 0ull, 0ull},
- {"SETD1PID" , 29, 1, 908, "WO", 0, 0, 0ull, 0ull},
- {"EPDIS" , 30, 1, 908, "R/W", 0, 0, 0ull, 0ull},
- {"EPENA" , 31, 1, 908, "R/W", 0, 0, 0ull, 0ull},
- {"XFERCOMPL" , 0, 1, 909, "R/W1C", 0, 0, 0ull, 0ull},
- {"EPDISBLD" , 1, 1, 909, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 909, "R/W1C", 0, 0, 0ull, 0ull},
- {"SETUP" , 3, 1, 909, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDIS" , 4, 1, 909, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 909, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 910, "R/W", 0, 0, 0ull, 0ull},
- {"EPDISBLDMSK" , 1, 1, 910, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 910, "R/W", 0, 0, 0ull, 0ull},
- {"SETUPMSK" , 3, 1, 910, "R/W", 0, 0, 0ull, 0ull},
- {"OUTTKNEPDISMSK" , 4, 1, 910, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 910, "RAZ", 1, 1, 0, 0},
- {"XFERSIZE" , 0, 19, 911, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 911, "R/W", 0, 0, 0ull, 0ull},
- {"MC" , 29, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 911, "RAZ", 1, 1, 0, 0},
- {"DPTXFSTADDR" , 0, 16, 912, "RO", 0, 0, 0ull, 0ull},
- {"DPTXFSIZE" , 16, 16, 912, "RO", 0, 0, 1896ull, 1896ull},
- {"SUSPSTS" , 0, 1, 913, "RO", 0, 0, 0ull, 0ull},
- {"ENUMSPD" , 1, 2, 913, "RO", 0, 0, 0ull, 0ull},
- {"ERRTICERR" , 3, 1, 913, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 913, "RAZ", 1, 1, 0, 0},
- {"SOFFN" , 8, 14, 913, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 913, "RAZ", 1, 1, 0, 0},
- {"INTKNWPTR" , 0, 5, 914, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 914, "RAZ", 1, 1, 0, 0},
- {"WRAPBIT" , 7, 1, 914, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 8, 24, 914, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 915, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 916, "RO", 0, 0, 0ull, 0ull},
- {"EPTKN" , 0, 32, 917, "RO", 0, 0, 0ull, 0ull},
- {"GLBLINTRMSK" , 0, 1, 918, "R/W", 0, 0, 0ull, 1ull},
- {"HBSTLEN" , 1, 4, 918, "R/W", 0, 0, 0ull, 0ull},
- {"DMAEN" , 5, 1, 918, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 918, "RAZ", 1, 1, 0, 0},
- {"NPTXFEMPLVL" , 7, 1, 918, "R/W", 0, 0, 0ull, 1ull},
- {"PTXFEMPLVL" , 8, 1, 918, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_31" , 9, 23, 918, "RAZ", 1, 1, 0, 0},
- {"EPDIR" , 0, 32, 919, "RO", 0, 0, 0ull, 0ull},
- {"OTGMODE" , 0, 3, 920, "RO", 0, 0, 2ull, 2ull},
- {"OTGARCH" , 3, 2, 920, "RO", 0, 0, 1ull, 1ull},
- {"SINGPNT" , 5, 1, 920, "RO", 0, 0, 0ull, 0ull},
- {"HSPHYTYPE" , 6, 2, 920, "RO", 0, 0, 1ull, 1ull},
- {"FSPHYTYPE" , 8, 2, 920, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVEPS" , 10, 4, 920, "RO", 0, 0, 4ull, 4ull},
- {"NUMHSTCHNL" , 14, 4, 920, "RO", 0, 0, 7ull, 7ull},
- {"PERIOSUPPORT" , 18, 1, 920, "RO", 0, 0, 1ull, 1ull},
- {"DYNFIFOSIZING" , 19, 1, 920, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_20_21" , 20, 2, 920, "RAZ", 1, 1, 0, 0},
- {"NPTXQDEPTH" , 22, 2, 920, "RO", 0, 0, 2ull, 2ull},
- {"PTXQDEPTH" , 24, 2, 920, "RO", 0, 0, 2ull, 2ull},
- {"TKNQDEPTH" , 26, 5, 920, "RO", 0, 0, 30ull, 30ull},
- {"RESERVED_31_31" , 31, 1, 920, "RAZ", 1, 1, 0, 0},
- {"XFERSIZEWIDTH" , 0, 4, 921, "RO", 0, 0, 8ull, 8ull},
- {"PKTSIZEWIDTH" , 4, 3, 921, "RO", 0, 0, 6ull, 6ull},
- {"OTGEN" , 7, 1, 921, "RO", 0, 0, 1ull, 1ull},
- {"I2C_SELECTION" , 8, 1, 921, "RO", 0, 0, 0ull, 0ull},
- {"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 921, "RO", 0, 0, 0ull, 0ull},
- {"OPTFEATURE" , 10, 1, 921, "RO", 0, 0, 1ull, 1ull},
- {"RSTTYPE" , 11, 1, 921, "RO", 0, 0, 0ull, 0ull},
- {"AHBPHYSYNC" , 12, 1, 921, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 921, "RAZ", 1, 1, 0, 0},
- {"DFIFODEPTH" , 16, 16, 921, "RO", 0, 0, 1824ull, 1824ull},
- {"NUMDEVPERIOEPS" , 0, 4, 922, "RO", 0, 0, 4ull, 4ull},
- {"ENABLEPWROPT" , 4, 1, 922, "RO", 0, 0, 0ull, 0ull},
- {"AHBFREQ" , 5, 1, 922, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_13" , 6, 8, 922, "RAZ", 1, 1, 0, 0},
- {"PHYDATAWIDTH" , 14, 2, 922, "RO", 0, 0, 1ull, 1ull},
- {"NUMCTLEPS" , 16, 4, 922, "RO", 0, 0, 4ull, 4ull},
- {"IDDGFLTR" , 20, 1, 922, "RO", 0, 0, 1ull, 1ull},
- {"VBUSVALIDFLTR" , 21, 1, 922, "RO", 0, 0, 1ull, 1ull},
- {"AVALIDFLTR" , 22, 1, 922, "RO", 0, 0, 0ull, 0ull},
- {"BVALIDFLTR" , 23, 1, 922, "RO", 0, 0, 0ull, 0ull},
- {"SESSENDFLTR" , 24, 1, 922, "RO", 0, 0, 0ull, 0ull},
- {"ENDEDTRFIFO" , 25, 1, 922, "RO", 0, 0, 0ull, 0ull},
- {"NUMDEVMODINEND" , 26, 4, 922, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_30_31" , 30, 2, 922, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 923, "RAZ", 1, 1, 0, 0},
- {"MODEMISMSK" , 1, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"OTGINTMSK" , 2, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"SOFMSK" , 3, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"RXFLVLMSK" , 4, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"NPTXFEMPMSK" , 5, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"GINNAKEFFMSK" , 6, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFFMSK" , 7, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"ULPICKINTMSK" , 8, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"ERLYSUSPMSK" , 10, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"USBSUSPMSK" , 11, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"USBRSTMSK" , 12, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"ENUMDONEMSK" , 13, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"ISOOUTDROPMSK" , 14, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"EOPFMSK" , 15, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 923, "RAZ", 1, 1, 0, 0},
- {"EPMISMSK" , 17, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"INEPINTMSK" , 18, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"OEPINTMSK" , 19, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPISOINMSK" , 20, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"INCOMPLPMSK" , 21, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"FETSUSPMSK" , 22, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 923, "RAZ", 1, 1, 0, 0},
- {"PRTINTMSK" , 24, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"HCHINTMSK" , 25, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"PTXFEMPMSK" , 26, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 923, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNGMSK" , 28, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"DISCONNINTMSK" , 29, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"SESSREQINTMSK" , 30, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"WKUPINTMSK" , 31, 1, 923, "R/W", 0, 0, 0ull, 0ull},
- {"CURMOD" , 0, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"MODEMIS" , 1, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"OTGINT" , 2, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"SOF" , 3, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXFLVL" , 4, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"NPTXFEMP" , 5, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"GINNAKEFF" , 6, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"GOUTNAKEFF" , 7, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"ULPICKINT" , 8, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"I2CINT" , 9, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"ERLYSUSP" , 10, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBSUSP" , 11, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBRST" , 12, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENUMDONE" , 13, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"ISOOUTDROP" , 14, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"EOPF" , 15, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 924, "RAZ", 1, 1, 0, 0},
- {"EPMIS" , 17, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"IEPINT" , 18, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"OEPINT" , 19, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"INCOMPISOIN" , 20, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"INCOMPLP" , 21, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"FETSUSP" , 22, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 924, "RAZ", 1, 1, 0, 0},
- {"PRTINT" , 24, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"HCHINT" , 25, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"PTXFEMP" , 26, 1, 924, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 924, "RAZ", 1, 1, 0, 0},
- {"CONIDSTSCHNG" , 28, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"DISCONNINT" , 29, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"SESSREQINT" , 30, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"WKUPINT" , 31, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"NPTXFSTADDR" , 0, 16, 925, "R/W", 0, 0, 1824ull, 456ull},
- {"NPTXFDEP" , 16, 16, 925, "R/W", 0, 0, 1824ull, 912ull},
- {"NPTXFSPCAVAIL" , 0, 16, 926, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQSPCAVAIL" , 16, 8, 926, "RO", 0, 0, 0ull, 0ull},
- {"NPTXQTOP" , 24, 7, 926, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 926, "RAZ", 1, 1, 0, 0},
- {"SESREQSCS" , 0, 1, 927, "R/W", 0, 0, 0ull, 0ull},
- {"SESREQ" , 1, 1, 927, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 927, "RAZ", 1, 1, 0, 0},
- {"HSTNEGSCS" , 8, 1, 927, "R/W", 0, 0, 0ull, 0ull},
- {"HNPREQ" , 9, 1, 927, "R/W", 0, 0, 0ull, 0ull},
- {"HSTSETHNPEN" , 10, 1, 927, "R/W", 0, 0, 0ull, 0ull},
- {"DEVHNPEN" , 11, 1, 927, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 927, "RAZ", 1, 1, 0, 0},
- {"CONIDSTS" , 16, 1, 927, "RO", 1, 1, 0, 0},
- {"DBNCTIME" , 17, 1, 927, "RO", 0, 0, 0ull, 0ull},
- {"ASESVLD" , 18, 1, 927, "RO", 1, 1, 0, 0},
- {"BSESVLD" , 19, 1, 927, "RO", 1, 1, 0, 0},
- {"RESERVED_20_31" , 20, 12, 927, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 928, "RAZ", 1, 1, 0, 0},
- {"SESENDDET" , 2, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 928, "RAZ", 1, 1, 0, 0},
- {"SESREQSUCSTSCHNG" , 8, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSTNEGSUCSTSCHNG" , 9, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_16" , 10, 7, 928, "RAZ", 1, 1, 0, 0},
- {"HSTNEGDET" , 17, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
- {"ADEVTOUTCHG" , 18, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBNCEDONE" , 19, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 928, "RAZ", 1, 1, 0, 0},
- {"CSFTRST" , 0, 1, 929, "R/W", 0, 0, 0ull, 0ull},
- {"HSFTRST" , 1, 1, 929, "R/W", 0, 0, 0ull, 0ull},
- {"FRMCNTRRST" , 2, 1, 929, "R/W", 0, 0, 0ull, 0ull},
- {"INTKNQFLSH" , 3, 1, 929, "R/W", 0, 0, 0ull, 0ull},
- {"RXFFLSH" , 4, 1, 929, "R/W", 0, 0, 0ull, 0ull},
- {"TXFFLSH" , 5, 1, 929, "R/W", 0, 0, 0ull, 0ull},
- {"TXFNUM" , 6, 5, 929, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_29" , 11, 19, 929, "RAZ", 1, 1, 0, 0},
- {"DMAREQ" , 30, 1, 929, "RO", 0, 0, 0ull, 0ull},
- {"AHBIDLE" , 31, 1, 929, "RO", 0, 0, 1ull, 1ull},
- {"RXFDEP" , 0, 16, 930, "R/W", 0, 0, 1824ull, 456ull},
- {"RESERVED_16_31" , 16, 16, 930, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 931, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 931, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 931, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 931, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 931, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 931, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 932, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 932, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 932, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 932, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 932, "RAZ", 1, 1, 0, 0},
- {"EPNUM" , 0, 4, 933, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 933, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 933, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 933, "RO", 0, 0, 0ull, 0ull},
- {"FN" , 21, 4, 933, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 933, "RAZ", 1, 1, 0, 0},
- {"CHNUM" , 0, 4, 934, "RO", 0, 0, 0ull, 0ull},
- {"BCNT" , 4, 11, 934, "RO", 0, 0, 0ull, 0ull},
- {"DPID" , 15, 2, 934, "RO", 0, 0, 0ull, 0ull},
- {"PKTSTS" , 17, 4, 934, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 934, "RAZ", 1, 1, 0, 0},
- {"SYNOPSYSID" , 0, 32, 935, "RO", 1, 1, 0, 0},
- {"TOUTCAL" , 0, 3, 936, "R/W", 0, 0, 0ull, 0ull},
- {"PHYIF" , 3, 1, 936, "RO", 0, 0, 1ull, 1ull},
- {"ULPI_UTMI_SEL" , 4, 1, 936, "RO", 0, 0, 0ull, 0ull},
- {"FSINTF" , 5, 1, 936, "WO", 0, 0, 0ull, 0ull},
- {"PHYSEL" , 6, 1, 936, "WO", 0, 0, 0ull, 0ull},
- {"DDRSEL" , 7, 1, 936, "R/W", 0, 0, 0ull, 0ull},
- {"SRPCAP" , 8, 1, 936, "RO", 0, 0, 0ull, 0ull},
- {"HNPCAP" , 9, 1, 936, "RO", 0, 0, 0ull, 0ull},
- {"USBTRDTIM" , 10, 4, 936, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_14_14" , 14, 1, 936, "RAZ", 1, 1, 0, 0},
- {"PHYLPWRCLKSEL" , 15, 1, 936, "R/W", 0, 0, 0ull, 0ull},
- {"OTGI2CSEL" , 16, 1, 936, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 936, "RAZ", 1, 1, 0, 0},
- {"HAINT" , 0, 16, 937, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 937, "RAZ", 1, 1, 0, 0},
- {"HAINTMSK" , 0, 16, 938, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 938, "RAZ", 1, 1, 0, 0},
- {"MPS" , 0, 11, 939, "R/W", 0, 0, 0ull, 0ull},
- {"EPNUM" , 11, 4, 939, "R/W", 0, 0, 0ull, 0ull},
- {"EPDIR" , 15, 1, 939, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 939, "RAZ", 1, 1, 0, 0},
- {"LSPDDEV" , 17, 1, 939, "R/W", 0, 0, 0ull, 0ull},
- {"EPTYPE" , 18, 2, 939, "R/W", 0, 0, 0ull, 0ull},
- {"EC" , 20, 2, 939, "R/W", 0, 0, 0ull, 0ull},
- {"DEVADDR" , 22, 7, 939, "R/W", 0, 0, 0ull, 0ull},
- {"ODDFRM" , 29, 1, 939, "R/W", 0, 0, 0ull, 0ull},
- {"CHDIS" , 30, 1, 939, "R/W", 0, 0, 0ull, 0ull},
- {"CHENA" , 31, 1, 939, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSPCLKSEL" , 0, 2, 940, "R/W", 0, 0, 0ull, 0ull},
- {"FSLSSUPP" , 2, 1, 940, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 940, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPL" , 0, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"CHHLTD" , 1, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"AHBERR" , 2, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"STALL" , 3, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAK" , 4, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACK" , 5, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"NYET" , 6, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"XACTERR" , 7, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"BBLERR" , 8, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"FRMOVRUN" , 9, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"DATATGLERR" , 10, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 941, "RAZ", 1, 1, 0, 0},
- {"XFERCOMPLMSK" , 0, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"CHHLTDMSK" , 1, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"AHBERRMSK" , 2, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"STALLMSK" , 3, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"NAKMSK" , 4, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"ACKMSK" , 5, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"NYETMSK" , 6, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"XACTERRMSK" , 7, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"BBLERRMSK" , 8, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"FRMOVRUNMSK" , 9, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"DATATGLERRMSK" , 10, 1, 942, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 942, "RAZ", 1, 1, 0, 0},
- {"PRTADDR" , 0, 7, 943, "R/W", 0, 0, 0ull, 0ull},
- {"HUBADDR" , 7, 7, 943, "R/W", 0, 0, 0ull, 0ull},
- {"XACTPOS" , 14, 2, 943, "R/W", 0, 0, 0ull, 0ull},
- {"COMPSPLT" , 16, 1, 943, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_30" , 17, 14, 943, "RAZ", 1, 1, 0, 0},
- {"SPLTENA" , 31, 1, 943, "R/W", 0, 0, 0ull, 0ull},
- {"XFERSIZE" , 0, 19, 944, "R/W", 0, 0, 0ull, 0ull},
- {"PKTCNT" , 19, 10, 944, "R/W", 0, 0, 0ull, 0ull},
- {"PID" , 29, 2, 944, "R/W", 0, 0, 0ull, 0ull},
- {"DOPNG" , 31, 1, 944, "R/W", 0, 0, 0ull, 0ull},
- {"FRINT" , 0, 16, 945, "R/W", 0, 0, 2959ull, 3750ull},
- {"RESERVED_16_31" , 16, 16, 945, "RAZ", 1, 1, 0, 0},
- {"FRNUM" , 0, 16, 946, "RO", 0, 0, 16383ull, 0ull},
- {"FRREM" , 16, 16, 946, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNSTS" , 0, 1, 947, "RO", 0, 0, 0ull, 0ull},
- {"PRTCONNDET" , 1, 1, 947, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENA" , 2, 1, 947, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTENCHNG" , 3, 1, 947, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRACT" , 4, 1, 947, "RO", 0, 0, 0ull, 0ull},
- {"PRTOVRCURRCHNG" , 5, 1, 947, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTRES" , 6, 1, 947, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSUSP" , 7, 1, 947, "R/W", 0, 0, 0ull, 0ull},
- {"PRTRST" , 8, 1, 947, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 947, "RAZ", 1, 1, 0, 0},
- {"PRTLNSTS" , 10, 2, 947, "RO", 0, 0, 0ull, 0ull},
- {"PRTPWR" , 12, 1, 947, "R/W", 0, 0, 0ull, 0ull},
- {"PRTTSTCTL" , 13, 4, 947, "R/W", 0, 0, 0ull, 0ull},
- {"PRTSPD" , 17, 2, 947, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 947, "RAZ", 1, 1, 0, 0},
- {"PTXFSTADDR" , 0, 16, 948, "R/W", 0, 0, 3648ull, 912ull},
- {"PTXFSIZE" , 16, 16, 948, "R/W", 0, 0, 256ull, 456ull},
- {"PTXFSPCAVAIL" , 0, 16, 949, "RO", 0, 0, 0ull, 0ull},
- {"PTXQSPCAVAIL" , 16, 8, 949, "RO", 0, 0, 0ull, 0ull},
- {"PTXQTOP" , 24, 8, 949, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 32, 950, "R/W", 0, 0, 0ull, 0ull},
- {"STOPPCLK" , 0, 1, 951, "R/W", 0, 0, 0ull, 0ull},
- {"GATEHCLK" , 1, 1, 951, "R/W", 0, 0, 0ull, 0ull},
- {"PWRCLMP" , 2, 1, 951, "R/W", 0, 0, 0ull, 0ull},
- {"RSTPDWNMODULE" , 3, 1, 951, "R/W", 0, 0, 0ull, 0ull},
- {"PHYSUSPENDED" , 4, 1, 951, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 951, "RAZ", 1, 1, 0, 0},
- {"NOF_BIS" , 0, 1, 952, "RO", 0, 0, 0ull, 0ull},
- {"NIF_BIS" , 1, 1, 952, "RO", 0, 0, 0ull, 0ull},
- {"USBC_BIS" , 2, 1, 952, "RO", 0, 0, 0ull, 0ull},
- {"N2UF_BIS" , 3, 1, 952, "RO", 0, 0, 0ull, 0ull},
- {"E2HC_BIS" , 4, 1, 952, "RO", 0, 0, 0ull, 0ull},
- {"U2NF_BIS" , 5, 1, 952, "RO", 0, 0, 0ull, 0ull},
- {"U2NC_BIS" , 6, 1, 952, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 952, "RAZ", 1, 1, 0, 0},
- {"DIVIDE" , 0, 3, 953, "R/W", 0, 0, 4ull, 0ull},
- {"HRST" , 3, 1, 953, "R/W", 0, 0, 0ull, 1ull},
- {"PRST" , 4, 1, 953, "R/W", 0, 0, 0ull, 1ull},
- {"ENABLE" , 5, 1, 953, "R/W", 0, 0, 1ull, 1ull},
- {"POR" , 6, 1, 953, "R/W", 0, 0, 1ull, 0ull},
- {"S_BIST" , 7, 1, 953, "R/W", 0, 0, 0ull, 1ull},
- {"SD_MODE" , 8, 2, 953, "R/W", 0, 0, 0ull, 0ull},
- {"CDIV_BYP" , 10, 1, 953, "R/W", 0, 0, 0ull, 0ull},
- {"P_C_SEL" , 11, 2, 953, "R/W", 0, 0, 2ull, 0ull},
- {"P_COM_ON" , 13, 1, 953, "R/W", 0, 0, 1ull, 1ull},
- {"P_RTYPE" , 14, 2, 953, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 953, "RAZ", 1, 1, 0, 0},
- {"HCLK_RST" , 17, 1, 953, "R/W", 0, 0, 1ull, 1ull},
- {"DIVIDE2" , 18, 2, 953, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_63" , 20, 44, 953, "RAZ", 1, 1, 0, 0},
- {"L2C_EMOD" , 0, 2, 954, "R/W", 0, 0, 1ull, 1ull},
- {"INV_A2" , 2, 1, 954, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_TEST" , 3, 1, 954, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_STT" , 4, 1, 954, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_0PAG" , 5, 1, 954, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 954, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 955, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 955, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 956, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 956, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 957, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 957, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 958, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 958, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 959, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 959, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 960, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 960, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 961, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 961, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 962, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 962, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 963, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 963, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 964, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 964, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 965, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 965, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 966, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 966, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 967, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 967, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 968, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 968, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 969, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 969, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 970, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 970, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 4, 971, "R/W", 0, 0, 0ull, 0ull},
- {"CHANNEL" , 4, 5, 971, "R/W", 0, 0, 0ull, 0ull},
- {"COUNT" , 9, 11, 971, "R/W", 0, 0, 0ull, 0ull},
- {"F_ADDR" , 20, 18, 971, "R/W", 0, 0, 0ull, 0ull},
- {"REQ" , 38, 1, 971, "R/W1C", 0, 0, 0ull, 0ull},
- {"DONE" , 39, 1, 971, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 971, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_A_F" , 15, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_E" , 16, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"L2_FI_F" , 17, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"UOD_PF" , 25, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 972, "RAZ", 0, 0, 0ull, 0ull},
- {"LTL_F_PE" , 32, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_RPF" , 35, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPE" , 36, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"ND4O_DPF" , 37, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 972, "RAZ", 1, 1, 0, 0},
- {"PR_PO_E" , 0, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"PR_PU_F" , 1, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PO_E" , 2, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"NR_PU_F" , 3, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PO_E" , 4, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"LR_PU_F" , 5, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PO_E" , 6, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"PT_PU_F" , 7, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PO_E" , 8, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"NT_PU_F" , 9, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PO_E" , 10, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_PU_F" , 11, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_E" , 12, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCRED_F" , 13, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C_S_E" , 14, 1, 973, "R/W1C", 1, 0, 0, 0ull},
- {"L2C_A_F" , 15, 1, 973, "R/W1C", 1, 0, 0, 0ull},
- {"LT_FI_E" , 16, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"LT_FI_F" , 17, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_E" , 18, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"RG_FI_F" , 19, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_F" , 20, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q2_E" , 21, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_F" , 22, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQ_Q3_E" , 23, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"UOD_PE" , 24, 1, 973, "R/W1C", 1, 0, 0, 0ull},
- {"UOD_PF" , 25, 1, 973, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_26_31" , 26, 6, 973, "RAZ", 1, 0, 0, 0ull},
- {"LTL_F_PE" , 32, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"LTL_F_PF" , 33, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
- {"ND4O_RPE" , 34, 1, 973, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_RPF" , 35, 1, 973, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPE" , 36, 1, 973, "R/W1C", 1, 0, 0, 0ull},
- {"ND4O_DPF" , 37, 1, 973, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_38_63" , 38, 26, 973, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_IN" , 1, 8, 974, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 9, 4, 974, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 13, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ENB" , 14, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_ENB" , 15, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_ENB" , 16, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_EN" , 17, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"TX_BS_ENH" , 18, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_22" , 19, 4, 974, "RAZ", 0, 0, 0ull, 0ull},
- {"HST_MODE" , 23, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"DM_PULLD" , 24, 1, 974, "R/W", 0, 0, 1ull, 1ull},
- {"DP_PULLD" , 25, 1, 974, "R/W", 0, 0, 1ull, 1ull},
- {"TCLK" , 26, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"USBP_BIST" , 27, 1, 974, "R/W", 0, 0, 1ull, 1ull},
- {"USBC_END" , 28, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"DMA_BMODE" , 29, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"TXPREEMPHASISTUNE" , 30, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"SIDDQ" , 31, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_OUT" , 32, 4, 974, "RO", 1, 1, 0, 0},
- {"BIST_ERR" , 36, 1, 974, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 37, 1, 974, "RO", 0, 0, 0ull, 0ull},
- {"HSBIST" , 38, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 39, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 40, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"DRVVBUS" , 41, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 42, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"OTGDISABLE" , 43, 1, 974, "R/W", 0, 0, 1ull, 1ull},
- {"OTGTUNE" , 44, 3, 974, "R/W", 0, 0, 2ull, 2ull},
- {"COMPDISTUNE" , 47, 3, 974, "R/W", 0, 0, 2ull, 2ull},
- {"SQRXTUNE" , 50, 3, 974, "R/W", 0, 0, 3ull, 3ull},
- {"TXHSXVTUNE" , 53, 2, 974, "R/W", 0, 0, 0ull, 0ull},
- {"TXFSLSTUNE" , 55, 4, 974, "R/W", 0, 0, 3ull, 3ull},
- {"TXVREFTUNE" , 59, 4, 974, "R/W", 0, 0, 7ull, 7ull},
- {"TXRISETUNE" , 63, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn61xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 14, 0},
- {"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 14},
- {"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 13, 16},
- {"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 1, 29},
- {"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 30},
- {"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 31},
- {"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 32},
- {"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 1, 33},
- {"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 1, 34},
- {"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 35},
- {"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 4, 37},
- {"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 41},
- {"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 11, 43},
- {"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 14, 54},
- {"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 68},
- {"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 70},
- {"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 72},
- {"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 21, 74},
- {"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 21, 95},
- {"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 2, 116},
- {"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 38, 2, 118},
- {"cvmx_agl_gmx_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 4, 120},
- {"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 124},
- {"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 126},
- {"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 128},
- {"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 130},
- {"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 132},
- {"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 134},
- {"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 136},
- {"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 138},
- {"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 140},
- {"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 142},
- {"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 4, 144},
- {"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 2, 148},
- {"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 150},
- {"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 2, 152},
- {"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 70, 4, 154},
- {"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 4, 158},
- {"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 2, 162},
- {"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 3, 164},
- {"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 5, 167},
- {"cvmx_agl_gmx_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 2, 172},
- {"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 3, 174},
- {"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 81, 2, 177},
- {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 179},
- {"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 85, 2, 181},
- {"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 87, 2, 183},
- {"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 89, 2, 185},
- {"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 187},
- {"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 93, 2, 189},
- {"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 95, 2, 191},
- {"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 97, 2, 193},
- {"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 2, 195},
- {"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 197},
- {"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 2, 199},
- {"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 2, 201},
- {"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 2, 203},
- {"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 109, 2, 205},
- {"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 111, 2, 207},
- {"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 2, 209},
- {"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 115, 2, 211},
- {"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 117, 2, 213},
- {"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 118, 2, 215},
- {"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 3, 217},
- {"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 120, 12, 220},
- {"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 121, 12, 232},
- {"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 2, 244},
- {"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 123, 2, 246},
- {"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 124, 6, 248},
- {"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 125, 2, 254},
- {"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 126, 2, 256},
- {"cvmx_agl_prt#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 127, 23, 258},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 129, 2, 281},
- {"cvmx_ciu_block_int" , CVMX_CSR_DB_TYPE_NCB, 64, 130, 34, 283},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 131, 2, 317},
- {"cvmx_ciu_en2_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 132, 3, 319},
- {"cvmx_ciu_en2_io#_int_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 134, 3, 322},
- {"cvmx_ciu_en2_io#_int_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 136, 3, 325},
- {"cvmx_ciu_en2_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 138, 3, 328},
- {"cvmx_ciu_en2_pp#_ip2_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 142, 3, 331},
- {"cvmx_ciu_en2_pp#_ip2_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 146, 3, 334},
- {"cvmx_ciu_en2_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 150, 3, 337},
- {"cvmx_ciu_en2_pp#_ip3_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 154, 3, 340},
- {"cvmx_ciu_en2_pp#_ip3_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 158, 3, 343},
- {"cvmx_ciu_en2_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 162, 3, 346},
- {"cvmx_ciu_en2_pp#_ip4_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 166, 3, 349},
- {"cvmx_ciu_en2_pp#_ip4_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 170, 3, 352},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 174, 2, 355},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 175, 2, 357},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 176, 22, 359},
- {"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 22, 381},
- {"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 196, 22, 403},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 206, 33, 425},
- {"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 216, 33, 458},
- {"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 226, 33, 491},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 236, 22, 524},
- {"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 240, 22, 546},
- {"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 244, 22, 568},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 248, 33, 590},
- {"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 252, 33, 623},
- {"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 256, 33, 656},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 260, 22, 689},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 269, 22, 711},
- {"cvmx_ciu_int33_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 273, 22, 733},
- {"cvmx_ciu_int_dbg_sel" , CVMX_CSR_DB_TYPE_NCB, 64, 274, 6, 755},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 275, 31, 761},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 276, 2, 792},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 280, 2, 794},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 284, 2, 796},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 285, 2, 798},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 286, 2, 800},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 287, 1, 802},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 291, 3, 803},
- {"cvmx_ciu_qlm0" , CVMX_CSR_DB_TYPE_NCB, 64, 292, 13, 806},
- {"cvmx_ciu_qlm1" , CVMX_CSR_DB_TYPE_NCB, 64, 293, 13, 819},
- {"cvmx_ciu_qlm2" , CVMX_CSR_DB_TYPE_NCB, 64, 294, 8, 832},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 295, 6, 840},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 296, 8, 846},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 297, 2, 854},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 298, 2, 856},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 299, 2, 858},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 300, 2, 860},
- {"cvmx_ciu_sum1_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 301, 33, 862},
- {"cvmx_ciu_sum1_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 303, 33, 895},
- {"cvmx_ciu_sum1_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 307, 33, 928},
- {"cvmx_ciu_sum1_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 311, 33, 961},
- {"cvmx_ciu_sum2_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 315, 3, 994},
- {"cvmx_ciu_sum2_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 317, 3, 997},
- {"cvmx_ciu_sum2_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 321, 3, 1000},
- {"cvmx_ciu_sum2_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 325, 3, 1003},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 329, 3, 1006},
- {"cvmx_ciu_tim_multi_cast" , CVMX_CSR_DB_TYPE_NCB, 64, 339, 2, 1009},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 340, 7, 1011},
- {"cvmx_dfa_bist0" , CVMX_CSR_DB_TYPE_RSL, 64, 344, 10, 1018},
- {"cvmx_dfa_bist1" , CVMX_CSR_DB_TYPE_RSL, 64, 345, 14, 1028},
- {"cvmx_dfa_config" , CVMX_CSR_DB_TYPE_RSL, 64, 346, 7, 1042},
- {"cvmx_dfa_control" , CVMX_CSR_DB_TYPE_RSL, 64, 347, 7, 1049},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 348, 2, 1056},
- {"cvmx_dfa_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 349, 1, 1058},
- {"cvmx_dfa_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 350, 1, 1059},
- {"cvmx_dfa_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 351, 1, 1060},
- {"cvmx_dfa_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 352, 1, 1061},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 353, 5, 1062},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 354, 3, 1067},
- {"cvmx_dfa_dtcfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 355, 6, 1070},
- {"cvmx_dfa_error" , CVMX_CSR_DB_TYPE_RSL, 64, 356, 9, 1076},
- {"cvmx_dfa_intmsk" , CVMX_CSR_DB_TYPE_RSL, 64, 357, 8, 1085},
- {"cvmx_dfa_memhidat" , CVMX_CSR_DB_TYPE_NCB, 64, 358, 1, 1093},
- {"cvmx_dfa_pfc0_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 359, 1, 1094},
- {"cvmx_dfa_pfc0_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 360, 5, 1095},
- {"cvmx_dfa_pfc1_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 361, 1, 1100},
- {"cvmx_dfa_pfc1_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 362, 5, 1101},
- {"cvmx_dfa_pfc2_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 363, 1, 1106},
- {"cvmx_dfa_pfc2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 364, 5, 1107},
- {"cvmx_dfa_pfc3_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 365, 1, 1112},
- {"cvmx_dfa_pfc3_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 366, 5, 1113},
- {"cvmx_dfa_pfc_gctl" , CVMX_CSR_DB_TYPE_RSL, 64, 367, 18, 1118},
- {"cvmx_dpi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 368, 2, 1136},
- {"cvmx_dpi_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 369, 2, 1138},
- {"cvmx_dpi_dma#_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 370, 3, 1140},
- {"cvmx_dpi_dma#_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 378, 2, 1143},
- {"cvmx_dpi_dma#_err_rsp_status", CVMX_CSR_DB_TYPE_NCB, 64, 386, 2, 1145},
- {"cvmx_dpi_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 394, 7, 1147},
- {"cvmx_dpi_dma#_iflight" , CVMX_CSR_DB_TYPE_NCB, 64, 402, 2, 1154},
- {"cvmx_dpi_dma#_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 410, 2, 1156},
- {"cvmx_dpi_dma#_reqbnk0" , CVMX_CSR_DB_TYPE_NCB, 64, 418, 1, 1158},
- {"cvmx_dpi_dma#_reqbnk1" , CVMX_CSR_DB_TYPE_NCB, 64, 426, 1, 1159},
- {"cvmx_dpi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 434, 20, 1160},
- {"cvmx_dpi_dma_eng#_en" , CVMX_CSR_DB_TYPE_NCB, 64, 435, 2, 1180},
- {"cvmx_dpi_dma_pp#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 441, 2, 1182},
- {"cvmx_dpi_eng#_buf" , CVMX_CSR_DB_TYPE_NCB, 64, 445, 5, 1184},
- {"cvmx_dpi_info_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 451, 5, 1189},
- {"cvmx_dpi_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 452, 17, 1194},
- {"cvmx_dpi_int_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 453, 17, 1211},
- {"cvmx_dpi_ncb#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 454, 2, 1228},
- {"cvmx_dpi_pint_info" , CVMX_CSR_DB_TYPE_NCB, 64, 455, 4, 1230},
- {"cvmx_dpi_pkt_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 456, 2, 1234},
- {"cvmx_dpi_req_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 457, 2, 1236},
- {"cvmx_dpi_req_err_rsp_en" , CVMX_CSR_DB_TYPE_NCB, 64, 458, 2, 1238},
- {"cvmx_dpi_req_err_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 459, 2, 1240},
- {"cvmx_dpi_req_err_rst_en" , CVMX_CSR_DB_TYPE_NCB, 64, 460, 2, 1242},
- {"cvmx_dpi_req_err_skip_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 461, 4, 1244},
- {"cvmx_dpi_req_gbl_en" , CVMX_CSR_DB_TYPE_NCB, 64, 462, 2, 1248},
- {"cvmx_dpi_sli_prt#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 463, 13, 1250},
- {"cvmx_dpi_sli_prt#_err" , CVMX_CSR_DB_TYPE_NCB, 64, 465, 2, 1263},
- {"cvmx_dpi_sli_prt#_err_info" , CVMX_CSR_DB_TYPE_NCB, 64, 467, 6, 1265},
- {"cvmx_fpa_addr_range_error" , CVMX_CSR_DB_TYPE_RSL, 64, 469, 3, 1271},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 6, 1274},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 10, 1280},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 3, 1290},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 479, 2, 1293},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 486, 3, 1295},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 2, 1298},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 488, 47, 1300},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 489, 47, 1347},
- {"cvmx_fpa_packet_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 490, 2, 1394},
- {"cvmx_fpa_pool#_end_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 2, 1396},
- {"cvmx_fpa_pool#_start_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 2, 1398},
- {"cvmx_fpa_pool#_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 2, 1400},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 2, 1402},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 523, 2, 1404},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 531, 3, 1406},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 532, 3, 1409},
- {"cvmx_fpa_wqe_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 533, 2, 1412},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 534, 7, 1414},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 536, 2, 1421},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 538, 2, 1423},
- {"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 540, 5, 1425},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 542, 7, 1430},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 544, 2, 1437},
- {"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 546, 8, 1439},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 548, 10, 1447},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 556, 1, 1457},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 564, 1, 1458},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 572, 1, 1459},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 580, 1, 1460},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 588, 1, 1461},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 596, 1, 1462},
- {"cvmx_gmx#_rx#_adr_cam_all_en", CVMX_CSR_DB_TYPE_RSL, 64, 604, 2, 1463},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 612, 2, 1465},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 620, 4, 1467},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 628, 2, 1471},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 636, 9, 1473},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 644, 13, 1482},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 652, 2, 1495},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 660, 27, 1497},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 668, 27, 1524},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 676, 2, 1551},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 684, 2, 1553},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 692, 2, 1555},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 700, 2, 1557},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 708, 2, 1559},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 716, 2, 1561},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 724, 2, 1563},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 732, 2, 1565},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 740, 2, 1567},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 748, 2, 1569},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 756, 2, 1571},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 764, 2, 1573},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 772, 4, 1575},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 780, 2, 1579},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 788, 2, 1581},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 2, 1583},
- {"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 4, 1585},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 4, 1589},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 2, 1593},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 5, 1595},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 2, 1600},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 814, 2, 1602},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 3, 1604},
- {"cvmx_gmx#_tb_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 2, 1607},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 5, 1609},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 834, 2, 1614},
- {"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 842, 2, 1616},
- {"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 844, 2, 1618},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 846, 3, 1620},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 854, 2, 1623},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 862, 2, 1625},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 870, 2, 1627},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 878, 3, 1629},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 886, 2, 1632},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 894, 2, 1634},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 902, 2, 1636},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 910, 2, 1638},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 918, 2, 1640},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 926, 2, 1642},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 934, 2, 1644},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 942, 2, 1646},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 950, 2, 1648},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 958, 2, 1650},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 966, 2, 1652},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 974, 2, 1654},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 982, 2, 1656},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 2, 1658},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 2, 1660},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 2, 1662},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1014, 2, 1664},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 1016, 2, 1666},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 1018, 2, 1668},
- {"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1020, 2, 1670},
- {"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 1022, 2, 1672},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 3, 1674},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 10, 1677},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 10, 1687},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 2, 1697},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1032, 2, 1699},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1034, 6, 1701},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 1036, 2, 1707},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 2, 1709},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 2, 1711},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 9, 1713},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 3, 1722},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 1046, 10, 1725},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 1062, 2, 1735},
- {"cvmx_gpio_clk_qlm#" , CVMX_CSR_DB_TYPE_NCB, 64, 1066, 5, 1737},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 1068, 2, 1742},
- {"cvmx_gpio_multi_cast" , CVMX_CSR_DB_TYPE_NCB, 64, 1069, 2, 1744},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 1070, 2, 1746},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 1071, 2, 1748},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 1072, 2, 1750},
- {"cvmx_gpio_xbit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 1073, 10, 1752},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1077, 24, 1762},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1078, 9, 1786},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1079, 3, 1795},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 1080, 3, 1798},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1081, 3, 1801},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1082, 5, 1804},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1083, 5, 1809},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1084, 1, 1814},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1085, 1, 1815},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1086, 7, 1816},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1087, 7, 1823},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1088, 3, 1830},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1089, 3, 1833},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1090, 3, 1836},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1091, 5, 1839},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1092, 5, 1844},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1093, 1, 1849},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1094, 1, 1850},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1095, 3, 1851},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1096, 3, 1854},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1097, 3, 1857},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1098, 3, 1860},
- {"cvmx_iob_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 1099, 4, 1863},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1100, 2, 1867},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 1101, 2, 1869},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 1102, 2, 1871},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1103, 19, 1873},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 1104, 2, 1892},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1105, 1, 1894},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1106, 18, 1895},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1107, 13, 1913},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1108, 13, 1926},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1109, 2, 1939},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1110, 2, 1941},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1111, 2, 1943},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1112, 3, 1945},
- {"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 1124, 3, 1948},
- {"cvmx_ipd_port#_bp_page_cnt3" , CVMX_CSR_DB_TYPE_NCB, 64, 1128, 3, 1951},
- {"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1136, 2, 1954},
- {"cvmx_ipd_port_bp_counters3_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1140, 2, 1956},
- {"cvmx_ipd_port_bp_counters4_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1144, 2, 1958},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1148, 2, 1960},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1160, 2, 1962},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 1352, 1, 1964},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 1356, 1, 1965},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1360, 6, 1966},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1361, 5, 1972},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1362, 6, 1977},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1363, 7, 1983},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 1364, 2, 1990},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1372, 2, 1992},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 1373, 3, 1994},
- {"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 1374, 2, 1997},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 1375, 5, 1999},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 1383, 3, 2004},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 1384, 4, 2007},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1385, 3, 2011},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 1386, 2, 2014},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1387, 2, 2016},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1388, 4, 2018},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1389, 3, 2022},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1390, 5, 2025},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1391, 5, 2030},
- {"cvmx_l2c_big_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1392, 4, 2035},
- {"cvmx_l2c_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 1393, 12, 2039},
- {"cvmx_l2c_bst_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 1394, 5, 2051},
- {"cvmx_l2c_bst_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1395, 5, 2056},
- {"cvmx_l2c_bst_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1396, 3, 2061},
- {"cvmx_l2c_cop0_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 1397, 1, 2064},
- {"cvmx_l2c_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2677, 15, 2065},
- {"cvmx_l2c_dut_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 2678, 4, 2080},
- {"cvmx_l2c_err_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 3702, 9, 2084},
- {"cvmx_l2c_err_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 3703, 9, 2093},
- {"cvmx_l2c_err_vbf#" , CVMX_CSR_DB_TYPE_RSL, 64, 3704, 6, 2102},
- {"cvmx_l2c_err_xmc" , CVMX_CSR_DB_TYPE_RSL, 64, 3705, 5, 2108},
- {"cvmx_l2c_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 3706, 9, 2113},
- {"cvmx_l2c_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 3707, 11, 2122},
- {"cvmx_l2c_ioc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 3708, 1, 2133},
- {"cvmx_l2c_ior#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 3709, 1, 2134},
- {"cvmx_l2c_qos_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 3710, 4, 2135},
- {"cvmx_l2c_qos_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 3711, 2, 2139},
- {"cvmx_l2c_qos_wgt" , CVMX_CSR_DB_TYPE_RSL, 64, 3715, 5, 2141},
- {"cvmx_l2c_rsc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 3716, 1, 2146},
- {"cvmx_l2c_rsd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 3717, 1, 2147},
- {"cvmx_l2c_tad#_ecc0" , CVMX_CSR_DB_TYPE_RSL, 64, 3718, 8, 2148},
- {"cvmx_l2c_tad#_ecc1" , CVMX_CSR_DB_TYPE_RSL, 64, 3719, 8, 2156},
- {"cvmx_l2c_tad#_ien" , CVMX_CSR_DB_TYPE_RSL, 64, 3720, 10, 2164},
- {"cvmx_l2c_tad#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 3721, 10, 2174},
- {"cvmx_l2c_tad#_pfc0" , CVMX_CSR_DB_TYPE_RSL, 64, 3722, 1, 2184},
- {"cvmx_l2c_tad#_pfc1" , CVMX_CSR_DB_TYPE_RSL, 64, 3723, 1, 2185},
- {"cvmx_l2c_tad#_pfc2" , CVMX_CSR_DB_TYPE_RSL, 64, 3724, 1, 2186},
- {"cvmx_l2c_tad#_pfc3" , CVMX_CSR_DB_TYPE_RSL, 64, 3725, 1, 2187},
- {"cvmx_l2c_tad#_prf" , CVMX_CSR_DB_TYPE_RSL, 64, 3726, 5, 2188},
- {"cvmx_l2c_tad#_tag" , CVMX_CSR_DB_TYPE_RSL, 64, 3727, 9, 2193},
- {"cvmx_l2c_ver_id" , CVMX_CSR_DB_TYPE_RSL, 64, 3728, 1, 2202},
- {"cvmx_l2c_ver_iob" , CVMX_CSR_DB_TYPE_RSL, 64, 3729, 2, 2203},
- {"cvmx_l2c_ver_msc" , CVMX_CSR_DB_TYPE_RSL, 64, 3730, 3, 2205},
- {"cvmx_l2c_ver_pp" , CVMX_CSR_DB_TYPE_RSL, 64, 3731, 2, 2208},
- {"cvmx_l2c_virtid_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 3732, 4, 2210},
- {"cvmx_l2c_virtid_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 3733, 2, 2214},
- {"cvmx_l2c_vrt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 3737, 6, 2216},
- {"cvmx_l2c_vrt_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 3738, 3, 2222},
- {"cvmx_l2c_wpar_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 4762, 2, 2225},
- {"cvmx_l2c_wpar_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 4763, 2, 2227},
- {"cvmx_l2c_xmc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4767, 1, 2229},
- {"cvmx_l2c_xmc_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 4768, 4, 2230},
- {"cvmx_l2c_xmd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4769, 1, 2234},
- {"cvmx_lmc#_char_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4770, 7, 2235},
- {"cvmx_lmc#_char_mask0" , CVMX_CSR_DB_TYPE_RSL, 64, 4771, 1, 2242},
- {"cvmx_lmc#_char_mask1" , CVMX_CSR_DB_TYPE_RSL, 64, 4772, 2, 2243},
- {"cvmx_lmc#_char_mask2" , CVMX_CSR_DB_TYPE_RSL, 64, 4773, 1, 2245},
- {"cvmx_lmc#_char_mask3" , CVMX_CSR_DB_TYPE_RSL, 64, 4774, 2, 2246},
- {"cvmx_lmc#_char_mask4" , CVMX_CSR_DB_TYPE_RSL, 64, 4775, 12, 2248},
- {"cvmx_lmc#_comp_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 4776, 11, 2260},
- {"cvmx_lmc#_config" , CVMX_CSR_DB_TYPE_RSL, 64, 4777, 23, 2271},
- {"cvmx_lmc#_control" , CVMX_CSR_DB_TYPE_RSL, 64, 4778, 26, 2294},
- {"cvmx_lmc#_dclk_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 4779, 1, 2320},
- {"cvmx_lmc#_ddr_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4780, 11, 2321},
- {"cvmx_lmc#_dimm#_params" , CVMX_CSR_DB_TYPE_RSL, 64, 4781, 16, 2332},
- {"cvmx_lmc#_dimm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4783, 5, 2348},
- {"cvmx_lmc#_dll_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 4784, 7, 2353},
- {"cvmx_lmc#_dll_ctl3" , CVMX_CSR_DB_TYPE_RSL, 64, 4785, 16, 2360},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4786, 4, 2376},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 4787, 5, 2380},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 4788, 6, 2385},
- {"cvmx_lmc#_ifb_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 4789, 1, 2391},
- {"cvmx_lmc#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4790, 4, 2392},
- {"cvmx_lmc#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 4791, 4, 2396},
- {"cvmx_lmc#_modereg_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 4792, 16, 2400},
- {"cvmx_lmc#_modereg_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 4793, 25, 2416},
- {"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 4794, 10, 2441},
- {"cvmx_lmc#_ops_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 4795, 1, 2451},
- {"cvmx_lmc#_phy_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4796, 10, 2452},
- {"cvmx_lmc#_reset_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4797, 5, 2462},
- {"cvmx_lmc#_rlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4798, 10, 2467},
- {"cvmx_lmc#_rlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 4799, 1, 2477},
- {"cvmx_lmc#_rlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 4800, 11, 2478},
- {"cvmx_lmc#_rodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 4804, 8, 2489},
- {"cvmx_lmc#_scramble_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 4805, 1, 2497},
- {"cvmx_lmc#_scramble_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 4806, 1, 2498},
- {"cvmx_lmc#_scrambled_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 4807, 6, 2499},
- {"cvmx_lmc#_slot_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 4808, 5, 2505},
- {"cvmx_lmc#_slot_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 4809, 5, 2510},
- {"cvmx_lmc#_slot_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 4810, 5, 2515},
- {"cvmx_lmc#_timing_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 4811, 12, 2520},
- {"cvmx_lmc#_timing_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 4812, 13, 2532},
- {"cvmx_lmc#_tro_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4813, 3, 2545},
- {"cvmx_lmc#_tro_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 4814, 2, 2548},
- {"cvmx_lmc#_wlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4815, 6, 2550},
- {"cvmx_lmc#_wlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 4816, 3, 2556},
- {"cvmx_lmc#_wlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 4817, 11, 2559},
- {"cvmx_lmc#_wodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 4821, 8, 2570},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 4822, 2, 2578},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 4823, 3, 2580},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 4824, 10, 2583},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 4826, 3, 2593},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 4828, 3, 2596},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 4830, 15, 2599},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 4832, 3, 2614},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4833, 3, 2617},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 4834, 3, 2620},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 4835, 5, 2623},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 4837, 1, 2628},
- {"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 4838, 10, 2629},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 4839, 13, 2639},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 4847, 13, 2652},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 4855, 6, 2665},
- {"cvmx_mio_emm_buf_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 4856, 1, 2671},
- {"cvmx_mio_emm_buf_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 4857, 5, 2672},
- {"cvmx_mio_emm_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4858, 4, 2677},
- {"cvmx_mio_emm_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 4859, 11, 2681},
- {"cvmx_mio_emm_dma" , CVMX_CSR_DB_TYPE_RSL, 64, 4860, 11, 2692},
- {"cvmx_mio_emm_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4861, 8, 2703},
- {"cvmx_mio_emm_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 4862, 8, 2711},
- {"cvmx_mio_emm_mode#" , CVMX_CSR_DB_TYPE_RSL, 64, 4863, 8, 2719},
- {"cvmx_mio_emm_rca" , CVMX_CSR_DB_TYPE_RSL, 64, 4867, 2, 2727},
- {"cvmx_mio_emm_rsp_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 4868, 1, 2729},
- {"cvmx_mio_emm_rsp_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 4869, 1, 2730},
- {"cvmx_mio_emm_rsp_sts" , CVMX_CSR_DB_TYPE_RSL, 64, 4870, 25, 2731},
- {"cvmx_mio_emm_sample" , CVMX_CSR_DB_TYPE_RSL, 64, 4871, 4, 2756},
- {"cvmx_mio_emm_sts_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 4872, 2, 2760},
- {"cvmx_mio_emm_switch" , CVMX_CSR_DB_TYPE_RSL, 64, 4873, 14, 2762},
- {"cvmx_mio_emm_wdog" , CVMX_CSR_DB_TYPE_RSL, 64, 4874, 2, 2776},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 4875, 1, 2778},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 4877, 2, 2779},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 4878, 2, 2781},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 4879, 15, 2783},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 4880, 18, 2798},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 4881, 4, 2816},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 4882, 1, 2820},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 4883, 7, 2821},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 4884, 3, 2828},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 4885, 8, 2831},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 4886, 7, 2839},
- {"cvmx_mio_fus_read_times" , CVMX_CSR_DB_TYPE_RSL, 64, 4887, 6, 2846},
- {"cvmx_mio_fus_repair_res0" , CVMX_CSR_DB_TYPE_RSL, 64, 4888, 5, 2852},
- {"cvmx_mio_fus_repair_res1" , CVMX_CSR_DB_TYPE_RSL, 64, 4889, 4, 2857},
- {"cvmx_mio_fus_repair_res2" , CVMX_CSR_DB_TYPE_RSL, 64, 4890, 2, 2861},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 4891, 4, 2863},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 4892, 2, 2867},
- {"cvmx_mio_fus_tgg" , CVMX_CSR_DB_TYPE_RSL, 64, 4893, 2, 2869},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 4894, 2, 2871},
- {"cvmx_mio_gpio_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 4895, 3, 2873},
- {"cvmx_mio_ndf_dma_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4896, 10, 2876},
- {"cvmx_mio_ndf_dma_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4897, 2, 2886},
- {"cvmx_mio_ndf_dma_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 4898, 2, 2888},
- {"cvmx_mio_ptp_ckout_hi_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 4899, 2, 2890},
- {"cvmx_mio_ptp_ckout_lo_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 4900, 2, 2892},
- {"cvmx_mio_ptp_ckout_thresh_hi", CVMX_CSR_DB_TYPE_NCB, 64, 4901, 1, 2894},
- {"cvmx_mio_ptp_ckout_thresh_lo", CVMX_CSR_DB_TYPE_NCB, 64, 4902, 2, 2895},
- {"cvmx_mio_ptp_clock_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 4903, 20, 2897},
- {"cvmx_mio_ptp_clock_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 4904, 2, 2917},
- {"cvmx_mio_ptp_clock_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 4905, 1, 2919},
- {"cvmx_mio_ptp_clock_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 4906, 2, 2920},
- {"cvmx_mio_ptp_evt_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 4907, 1, 2922},
- {"cvmx_mio_ptp_pps_hi_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 4908, 2, 2923},
- {"cvmx_mio_ptp_pps_lo_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 4909, 2, 2925},
- {"cvmx_mio_ptp_pps_thresh_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 4910, 1, 2927},
- {"cvmx_mio_ptp_pps_thresh_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 4911, 2, 2928},
- {"cvmx_mio_ptp_timestamp" , CVMX_CSR_DB_TYPE_NCB, 64, 4912, 1, 2930},
- {"cvmx_mio_qlm#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4913, 6, 2931},
- {"cvmx_mio_rst_boot" , CVMX_CSR_DB_TYPE_RSL, 64, 4916, 17, 2937},
- {"cvmx_mio_rst_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4917, 5, 2954},
- {"cvmx_mio_rst_ckill" , CVMX_CSR_DB_TYPE_RSL, 64, 4918, 2, 2959},
- {"cvmx_mio_rst_cntl#" , CVMX_CSR_DB_TYPE_RSL, 64, 4919, 13, 2961},
- {"cvmx_mio_rst_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 4921, 13, 2974},
- {"cvmx_mio_rst_delay" , CVMX_CSR_DB_TYPE_RSL, 64, 4923, 3, 2987},
- {"cvmx_mio_rst_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4924, 6, 2990},
- {"cvmx_mio_rst_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 4925, 6, 2996},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4926, 13, 3002},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 4928, 12, 3015},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 4930, 3, 3027},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 4932, 3, 3030},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 4934, 2, 3033},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 4936, 2, 3035},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 4938, 2, 3037},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 4940, 7, 3039},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 4942, 2, 3046},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 4944, 7, 3048},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 4946, 4, 3055},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 4948, 8, 3059},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 4950, 9, 3067},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 4952, 7, 3076},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 4954, 9, 3083},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 4956, 2, 3092},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 4958, 2, 3094},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 4960, 4, 3096},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 4962, 2, 3100},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 4964, 2, 3102},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 4966, 2, 3104},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 4968, 4, 3106},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 4970, 2, 3110},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 4972, 2, 3112},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 4974, 2, 3114},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 4976, 2, 3116},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 4978, 2, 3118},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 4980, 2, 3120},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 4982, 6, 3122},
- {"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 4984, 7, 3128},
- {"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 4986, 9, 3135},
- {"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 4988, 9, 3144},
- {"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 4990, 2, 3153},
- {"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 4992, 3, 3155},
- {"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 4994, 4, 3158},
- {"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 4996, 4, 3162},
- {"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 4998, 9, 3166},
- {"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5000, 2, 3175},
- {"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 5002, 2, 3177},
- {"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 5004, 4, 3179},
- {"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 5006, 4, 3183},
- {"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5008, 4, 3187},
- {"cvmx_mix#_tsctl" , CVMX_CSR_DB_TYPE_NCB, 64, 5010, 6, 3191},
- {"cvmx_mix#_tstamp" , CVMX_CSR_DB_TYPE_NCB, 64, 5012, 1, 3197},
- {"cvmx_mpi_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5014, 16, 3198},
- {"cvmx_mpi_dat#" , CVMX_CSR_DB_TYPE_NCB, 64, 5015, 2, 3214},
- {"cvmx_mpi_sts" , CVMX_CSR_DB_TYPE_NCB, 64, 5024, 4, 3216},
- {"cvmx_mpi_tx" , CVMX_CSR_DB_TYPE_NCB, 64, 5025, 8, 3220},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5026, 2, 3228},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5028, 24, 3230},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5030, 4, 3254},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5032, 5, 3258},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5034, 5, 3263},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5036, 2, 3268},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5038, 1, 3270},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5040, 1, 3271},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5042, 5, 3272},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5044, 2, 3277},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5046, 1, 3279},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5048, 1, 3280},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5050, 4, 3281},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5052, 2, 3285},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5054, 2, 3287},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5056, 1, 3289},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5058, 1, 3290},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5060, 2, 3291},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5062, 3, 3293},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5064, 2, 3296},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5066, 2, 3298},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5068, 4, 3300},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5070, 10, 3304},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5072, 12, 3314},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5074, 8, 3326},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5076, 2, 3334},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5078, 1, 3336},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5080, 2, 3337},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5082, 7, 3339},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5084, 12, 3346},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5086, 19, 3358},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5088, 12, 3377},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5090, 20, 3389},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5092, 11, 3409},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5094, 8, 3420},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5096, 4, 3428},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5098, 11, 3432},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5100, 3, 3443},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5102, 16, 3446},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5104, 16, 3462},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5106, 16, 3478},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5108, 9, 3494},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5110, 9, 3503},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5112, 6, 3512},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5114, 1, 3518},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5116, 1, 3519},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5118, 1, 3520},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5120, 1, 3521},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5122, 2, 3522},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5124, 1, 3524},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5126, 6, 3525},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5128, 7, 3531},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5130, 11, 3538},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5132, 5, 3549},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5134, 6, 3554},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5136, 19, 3560},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5138, 5, 3579},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5140, 1, 3584},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5142, 1, 3585},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5144, 3, 3586},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5146, 3, 3589},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5148, 3, 3592},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5150, 4, 3595},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5152, 4, 3599},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5154, 4, 3603},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5156, 7, 3607},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5158, 5, 3614},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5160, 5, 3619},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5162, 4, 3624},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5164, 4, 3628},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5166, 4, 3632},
- {"cvmx_pcieep#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5168, 7, 3636},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5170, 1, 3643},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5172, 1, 3644},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5174, 2, 3645},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5176, 24, 3647},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5178, 4, 3671},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5180, 5, 3675},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5182, 1, 3680},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5184, 1, 3681},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5186, 4, 3682},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5188, 17, 3686},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5190, 4, 3703},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5192, 6, 3707},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5194, 1, 3713},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5196, 1, 3714},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5198, 2, 3715},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5200, 2, 3717},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5202, 1, 3719},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5204, 15, 3720},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5206, 10, 3735},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5208, 12, 3745},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5210, 8, 3757},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5212, 2, 3765},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5214, 1, 3767},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5216, 2, 3768},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5218, 7, 3770},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5220, 11, 3777},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5222, 19, 3788},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5224, 12, 3807},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5226, 20, 3819},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5228, 12, 3839},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5230, 22, 3851},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5232, 8, 3873},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5234, 4, 3881},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5236, 11, 3885},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5238, 8, 3896},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5240, 4, 3904},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5242, 11, 3908},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5244, 1, 3919},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5246, 1, 3920},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5248, 3, 3921},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5250, 16, 3924},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5252, 16, 3940},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5254, 16, 3956},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5256, 9, 3972},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5258, 9, 3981},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5260, 6, 3990},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5262, 1, 3996},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5264, 1, 3997},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5266, 1, 3998},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5268, 1, 3999},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5270, 4, 4000},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5272, 9, 4004},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5274, 2, 4013},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5276, 2, 4015},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5278, 1, 4017},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5280, 6, 4018},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5282, 7, 4024},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5284, 11, 4031},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5286, 5, 4042},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5288, 6, 4047},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5290, 19, 4053},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5292, 5, 4072},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5294, 1, 4077},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5296, 1, 4078},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5298, 3, 4079},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5300, 3, 4082},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5302, 3, 4085},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5304, 4, 4088},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5306, 4, 4092},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5308, 4, 4096},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5310, 7, 4100},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5312, 5, 4107},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5314, 5, 4112},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5316, 4, 4117},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5318, 4, 4121},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5320, 4, 4125},
- {"cvmx_pcierc#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5322, 7, 4129},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5324, 1, 4136},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5326, 1, 4137},
- {"cvmx_pcm#_dma_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5328, 12, 4138},
- {"cvmx_pcm#_int_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 5332, 9, 4150},
- {"cvmx_pcm#_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 5336, 9, 4159},
- {"cvmx_pcm#_rxaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 5340, 2, 4168},
- {"cvmx_pcm#_rxcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5344, 2, 4170},
- {"cvmx_pcm#_rxmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 5348, 1, 4172},
- {"cvmx_pcm#_rxmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 5352, 1, 4173},
- {"cvmx_pcm#_rxmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 5356, 1, 4174},
- {"cvmx_pcm#_rxmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 5360, 1, 4175},
- {"cvmx_pcm#_rxmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 5364, 1, 4176},
- {"cvmx_pcm#_rxmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 5368, 1, 4177},
- {"cvmx_pcm#_rxmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 5372, 1, 4178},
- {"cvmx_pcm#_rxmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 5376, 1, 4179},
- {"cvmx_pcm#_rxstart" , CVMX_CSR_DB_TYPE_NCB, 64, 5380, 3, 4180},
- {"cvmx_pcm#_tdm_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5384, 6, 4183},
- {"cvmx_pcm#_tdm_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 5388, 1, 4189},
- {"cvmx_pcm#_txaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 5392, 3, 4190},
- {"cvmx_pcm#_txcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5396, 2, 4193},
- {"cvmx_pcm#_txmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 5400, 1, 4195},
- {"cvmx_pcm#_txmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 5404, 1, 4196},
- {"cvmx_pcm#_txmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 5408, 1, 4197},
- {"cvmx_pcm#_txmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 5412, 1, 4198},
- {"cvmx_pcm#_txmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 5416, 1, 4199},
- {"cvmx_pcm#_txmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 5420, 1, 4200},
- {"cvmx_pcm#_txmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 5424, 1, 4201},
- {"cvmx_pcm#_txmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 5428, 1, 4202},
- {"cvmx_pcm#_txstart" , CVMX_CSR_DB_TYPE_NCB, 64, 5432, 3, 4203},
- {"cvmx_pcm_clk#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5436, 12, 4206},
- {"cvmx_pcm_clk#_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 5438, 1, 4218},
- {"cvmx_pcm_clk#_gen" , CVMX_CSR_DB_TYPE_NCB, 64, 5440, 3, 4219},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5442, 9, 4222},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5450, 6, 4231},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5458, 9, 4237},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5466, 6, 4246},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5474, 14, 4252},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5482, 14, 4266},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 5490, 2, 4280},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5498, 4, 4282},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5506, 8, 4286},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5514, 13, 4294},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5522, 17, 4307},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5530, 7, 4324},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5538, 3, 4331},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5546, 8, 4334},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5554, 7, 4342},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5562, 4, 4349},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 5570, 5, 4353},
- {"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5578, 8, 4358},
- {"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5580, 2, 4366},
- {"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 5582, 5, 4368},
- {"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5584, 10, 4373},
- {"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5586, 2, 4383},
- {"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5588, 8, 4385},
- {"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5590, 8, 4393},
- {"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5592, 6, 4401},
- {"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5594, 5, 4407},
- {"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 5596, 5, 4412},
- {"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5598, 3, 4417},
- {"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5600, 6, 4420},
- {"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5602, 9, 4426},
- {"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 5604, 5, 4435},
- {"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5606, 10, 4440},
- {"cvmx_pem#_bar1_index#" , CVMX_CSR_DB_TYPE_RSL, 64, 5608, 5, 4450},
- {"cvmx_pem#_bar2_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 5640, 3, 4455},
- {"cvmx_pem#_bar_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5642, 5, 4458},
- {"cvmx_pem#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5644, 9, 4463},
- {"cvmx_pem#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 5646, 11, 4472},
- {"cvmx_pem#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 5648, 2, 4483},
- {"cvmx_pem#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 5650, 2, 4485},
- {"cvmx_pem#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 5652, 2, 4487},
- {"cvmx_pem#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5654, 18, 4489},
- {"cvmx_pem#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 5656, 32, 4507},
- {"cvmx_pem#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5658, 32, 4539},
- {"cvmx_pem#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5660, 5, 4571},
- {"cvmx_pem#_inb_read_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 5662, 2, 4576},
- {"cvmx_pem#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 5664, 15, 4578},
- {"cvmx_pem#_int_enb_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5666, 15, 4593},
- {"cvmx_pem#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 5668, 15, 4608},
- {"cvmx_pem#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 5670, 2, 4623},
- {"cvmx_pem#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 5672, 2, 4625},
- {"cvmx_pem#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 5674, 2, 4627},
- {"cvmx_pem#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 5676, 6, 4629},
- {"cvmx_pip_alt_skip_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 5678, 12, 4635},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 5682, 5, 4647},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5683, 2, 4652},
- {"cvmx_pip_bsel_ext_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 5684, 7, 4654},
- {"cvmx_pip_bsel_ext_pos#" , CVMX_CSR_DB_TYPE_RSL, 64, 5688, 16, 4661},
- {"cvmx_pip_bsel_tbl_ent#" , CVMX_CSR_DB_TYPE_RSL, 64, 5692, 12, 4677},
- {"cvmx_pip_clken" , CVMX_CSR_DB_TYPE_RSL, 64, 6204, 2, 4689},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 6205, 4, 4691},
- {"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 6209, 16, 4695},
- {"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 6210, 16, 4711},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 6211, 3, 4727},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 6212, 8, 4730},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6213, 23, 4738},
- {"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6214, 6, 4761},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 6215, 14, 4767},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6216, 14, 4781},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 6217, 2, 4795},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 6218, 28, 4797},
- {"cvmx_pip_prt_cfgb#" , CVMX_CSR_DB_TYPE_RSL, 64, 6234, 7, 4825},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 6250, 25, 4832},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 6266, 2, 4857},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 6330, 4, 4859},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 6338, 9, 4863},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 6346, 2, 4872},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 6347, 2, 4874},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6348, 2, 4876},
- {"cvmx_pip_stat10_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6364, 2, 4878},
- {"cvmx_pip_stat11_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6380, 2, 4880},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6396, 2, 4882},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6412, 2, 4884},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6428, 2, 4886},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6444, 2, 4888},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6460, 2, 4890},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6476, 2, 4892},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6492, 2, 4894},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6508, 2, 4896},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6524, 2, 4898},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6540, 2, 4900},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 6541, 2, 4902},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 6557, 2, 4904},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 6573, 2, 4906},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 6589, 2, 4908},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6653, 2, 4910},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 6654, 3, 4912},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 6655, 3, 4915},
- {"cvmx_pip_vlan_etypes#" , CVMX_CSR_DB_TYPE_RSL, 64, 6656, 4, 4918},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 6658, 2, 4922},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 6659, 2, 4924},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6660, 4, 4926},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6661, 5, 4930},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 6662, 4, 4935},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 6663, 8, 4939},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 6664, 4, 4947},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 6665, 5, 4951},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 6666, 1, 4956},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6667, 5, 4957},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6668, 1, 4962},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 6669, 13, 4963},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 6670, 6, 4976},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 6671, 13, 4982},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 6672, 6, 4995},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 6673, 12, 5001},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 6674, 4, 5013},
- {"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 6675, 7, 5017},
- {"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6676, 5, 5024},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 6677, 5, 5029},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 6678, 4, 5034},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 6679, 9, 5038},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6680, 5, 5047},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 6681, 16, 5052},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 6682, 4, 5068},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6683, 1, 5072},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6684, 1, 5073},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6685, 1, 5074},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6686, 1, 5075},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 6687, 15, 5076},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 6688, 2, 5091},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 6689, 4, 5093},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 6690, 8, 5097},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 6691, 3, 5105},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6692, 4, 5108},
- {"cvmx_pko_reg_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 6693, 2, 5112},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 6694, 2, 5114},
- {"cvmx_pko_reg_queue_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 6695, 3, 5116},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 6696, 3, 5119},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 6697, 3, 5122},
- {"cvmx_pko_reg_timestamp" , CVMX_CSR_DB_TYPE_RSL, 64, 6698, 2, 5125},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 6699, 10, 5127},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6700, 2, 5137},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 6701, 13, 5139},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 6702, 3, 5152},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 6703, 2, 5155},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 6711, 2, 5157},
- {"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 6712, 2, 5159},
- {"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 6713, 2, 5161},
- {"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6714, 2, 5163},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 6722, 2, 5165},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 6723, 2, 5167},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 6724, 2, 5169},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 6725, 10, 5171},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 6729, 5, 5181},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6737, 10, 5186},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6745, 2, 5196},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6746, 2, 5198},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 6747, 2, 5200},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 6755, 3, 5202},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 6756, 6, 5205},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6772, 5, 5211},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6773, 7, 5216},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 6789, 2, 5223},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6805, 1, 5225},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6806, 1, 5226},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6807, 1, 5227},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 6808, 5, 5228},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 6809, 5, 5233},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6810, 4, 5238},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6811, 10, 5242},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6812, 1, 5252},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 6813, 3, 5253},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 6814, 7, 5256},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 6815, 2, 5263},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6816, 1, 5265},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6817, 1, 5266},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 6818, 1, 5267},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 6819, 18, 5268},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 6820, 3, 5286},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 6821, 2, 5289},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 6822, 3, 5291},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 6823, 7, 5294},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 6824, 2, 5301},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6825, 2, 5303},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 6826, 2, 5305},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 6827, 3, 5307},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6828, 3, 5310},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6829, 10, 5313},
- {"cvmx_rnm_eer_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 6830, 1, 5323},
- {"cvmx_rnm_eer_key" , CVMX_CSR_DB_TYPE_RSL, 64, 6831, 1, 5324},
- {"cvmx_rnm_serial_num" , CVMX_CSR_DB_TYPE_RSL, 64, 6832, 1, 5325},
- {"cvmx_sli_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6833, 24, 5326},
- {"cvmx_sli_ctl_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6834, 16, 5350},
- {"cvmx_sli_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6836, 3, 5366},
- {"cvmx_sli_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6837, 5, 5369},
- {"cvmx_sli_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6838, 3, 5374},
- {"cvmx_sli_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6839, 3, 5377},
- {"cvmx_sli_dma#_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6840, 2, 5380},
- {"cvmx_sli_dma#_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6842, 2, 5382},
- {"cvmx_sli_dma#_tim" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6844, 2, 5384},
- {"cvmx_sli_int_enb_ciu" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6846, 45, 5386},
- {"cvmx_sli_int_enb_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6847, 46, 5431},
- {"cvmx_sli_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6849, 46, 5477},
- {"cvmx_sli_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6850, 1, 5523},
- {"cvmx_sli_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6851, 1, 5524},
- {"cvmx_sli_last_win_rdata2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6852, 1, 5525},
- {"cvmx_sli_last_win_rdata3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6853, 1, 5526},
- {"cvmx_sli_mac_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6854, 13, 5527},
- {"cvmx_sli_mac_credit_cnt2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6855, 13, 5540},
- {"cvmx_sli_mac_number" , CVMX_CSR_DB_TYPE_PEXP, 64, 6856, 3, 5553},
- {"cvmx_sli_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6857, 3, 5556},
- {"cvmx_sli_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6858, 9, 5559},
- {"cvmx_sli_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6874, 1, 5568},
- {"cvmx_sli_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6875, 1, 5569},
- {"cvmx_sli_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6876, 1, 5570},
- {"cvmx_sli_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6877, 1, 5571},
- {"cvmx_sli_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6878, 1, 5572},
- {"cvmx_sli_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6879, 1, 5573},
- {"cvmx_sli_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6880, 1, 5574},
- {"cvmx_sli_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6881, 1, 5575},
- {"cvmx_sli_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6882, 3, 5576},
- {"cvmx_sli_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6883, 1, 5579},
- {"cvmx_sli_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6884, 1, 5580},
- {"cvmx_sli_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6885, 1, 5581},
- {"cvmx_sli_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6886, 1, 5582},
- {"cvmx_sli_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6887, 1, 5583},
- {"cvmx_sli_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6888, 1, 5584},
- {"cvmx_sli_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6889, 1, 5585},
- {"cvmx_sli_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6890, 1, 5586},
- {"cvmx_sli_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6891, 3, 5587},
- {"cvmx_sli_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6892, 2, 5590},
- {"cvmx_sli_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6893, 3, 5592},
- {"cvmx_sli_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6894, 3, 5595},
- {"cvmx_sli_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6895, 3, 5598},
- {"cvmx_sli_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6896, 3, 5601},
- {"cvmx_sli_pkt#_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6928, 2, 5604},
- {"cvmx_sli_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6960, 2, 5606},
- {"cvmx_sli_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6992, 2, 5608},
- {"cvmx_sli_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7024, 5, 5610},
- {"cvmx_sli_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7056, 21, 5615},
- {"cvmx_sli_pkt#_out_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7088, 3, 5636},
- {"cvmx_sli_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7120, 2, 5639},
- {"cvmx_sli_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7152, 2, 5641},
- {"cvmx_sli_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7184, 2, 5643},
- {"cvmx_sli_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7216, 2, 5645},
- {"cvmx_sli_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7217, 2, 5647},
- {"cvmx_sli_pkt_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7218, 3, 5649},
- {"cvmx_sli_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7219, 1, 5652},
- {"cvmx_sli_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7220, 2, 5653},
- {"cvmx_sli_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7221, 2, 5655},
- {"cvmx_sli_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7222, 2, 5657},
- {"cvmx_sli_pkt_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7223, 2, 5659},
- {"cvmx_sli_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7224, 2, 5661},
- {"cvmx_sli_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7256, 2, 5663},
- {"cvmx_sli_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7257, 1, 5665},
- {"cvmx_sli_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7258, 17, 5666},
- {"cvmx_sli_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7259, 2, 5683},
- {"cvmx_sli_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7260, 1, 5685},
- {"cvmx_sli_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7261, 2, 5686},
- {"cvmx_sli_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7262, 3, 5688},
- {"cvmx_sli_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7263, 2, 5691},
- {"cvmx_sli_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7264, 2, 5693},
- {"cvmx_sli_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7265, 2, 5695},
- {"cvmx_sli_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7266, 2, 5697},
- {"cvmx_sli_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7267, 1, 5699},
- {"cvmx_sli_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7268, 2, 5700},
- {"cvmx_sli_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7269, 1, 5702},
- {"cvmx_sli_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7270, 2, 5703},
- {"cvmx_sli_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7271, 2, 5705},
- {"cvmx_sli_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7272, 2, 5707},
- {"cvmx_sli_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7273, 2, 5709},
- {"cvmx_sli_s2m_port#_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7274, 4, 5711},
- {"cvmx_sli_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7276, 1, 5715},
- {"cvmx_sli_scratch_2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7277, 1, 5716},
- {"cvmx_sli_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7278, 4, 5717},
- {"cvmx_sli_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7279, 8, 5721},
- {"cvmx_sli_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7280, 5, 5729},
- {"cvmx_sli_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 7281, 4, 5734},
- {"cvmx_sli_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 7282, 1, 5738},
- {"cvmx_sli_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 7283, 4, 5739},
- {"cvmx_sli_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 7284, 1, 5743},
- {"cvmx_sli_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 7285, 2, 5744},
- {"cvmx_sli_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7286, 2, 5746},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 7287, 10, 5748},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7289, 6, 5758},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 7291, 2, 5764},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7293, 4, 5766},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7295, 4, 5770},
- {"cvmx_smi_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7297, 4, 5774},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 7298, 6, 5778},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 7299, 3, 5784},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 7300, 5, 5787},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 7301, 4, 5792},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 7302, 6, 5796},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 7303, 4, 5802},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 7304, 2, 5806},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 7305, 4, 5808},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 7306, 2, 5812},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 7307, 3, 5814},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7308, 2, 5817},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7309, 14, 5819},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 7310, 3, 5833},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 7311, 5, 5836},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7312, 2, 5841},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7313, 2, 5843},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7314, 57, 5845},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7315, 20, 5902},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7316, 7, 5922},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7317, 5, 5929},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7318, 1, 5934},
- {"cvmx_tra#_read_dat_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 7319, 2, 5935},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7320, 2, 5937},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7321, 2, 5939},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7322, 57, 5941},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7323, 20, 5998},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7324, 7, 6018},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7325, 2, 6025},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7326, 2, 6027},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7327, 57, 6029},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7328, 20, 6086},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7329, 7, 6106},
- {"cvmx_uahc#_ehci_asynclistaddr", CVMX_CSR_DB_TYPE_NCB, 32, 7330, 2, 6113},
- {"cvmx_uahc#_ehci_configflag" , CVMX_CSR_DB_TYPE_NCB, 32, 7331, 2, 6115},
- {"cvmx_uahc#_ehci_ctrldssegment", CVMX_CSR_DB_TYPE_NCB, 32, 7332, 1, 6117},
- {"cvmx_uahc#_ehci_frindex" , CVMX_CSR_DB_TYPE_NCB, 32, 7333, 2, 6118},
- {"cvmx_uahc#_ehci_hccapbase" , CVMX_CSR_DB_TYPE_NCB, 32, 7334, 3, 6120},
- {"cvmx_uahc#_ehci_hccparams" , CVMX_CSR_DB_TYPE_NCB, 32, 7335, 7, 6123},
- {"cvmx_uahc#_ehci_hcsparams" , CVMX_CSR_DB_TYPE_NCB, 32, 7336, 10, 6130},
- {"cvmx_uahc#_ehci_insnreg00" , CVMX_CSR_DB_TYPE_NCB, 32, 7337, 3, 6140},
- {"cvmx_uahc#_ehci_insnreg03" , CVMX_CSR_DB_TYPE_NCB, 32, 7338, 5, 6143},
- {"cvmx_uahc#_ehci_insnreg04" , CVMX_CSR_DB_TYPE_NCB, 32, 7339, 7, 6148},
- {"cvmx_uahc#_ehci_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 7340, 2, 6155},
- {"cvmx_uahc#_ehci_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 7341, 1, 6157},
- {"cvmx_uahc#_ehci_periodiclistbase", CVMX_CSR_DB_TYPE_NCB, 32, 7342, 2, 6158},
- {"cvmx_uahc#_ehci_portsc#" , CVMX_CSR_DB_TYPE_NCB, 32, 7343, 19, 6160},
- {"cvmx_uahc#_ehci_usbcmd" , CVMX_CSR_DB_TYPE_NCB, 32, 7345, 13, 6179},
- {"cvmx_uahc#_ehci_usbintr" , CVMX_CSR_DB_TYPE_NCB, 32, 7346, 7, 6192},
- {"cvmx_uahc#_ehci_usbsts" , CVMX_CSR_DB_TYPE_NCB, 32, 7347, 12, 6199},
- {"cvmx_uahc#_ohci0_hcbulkcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7348, 2, 6211},
- {"cvmx_uahc#_ohci0_hcbulkheaded", CVMX_CSR_DB_TYPE_NCB, 32, 7349, 2, 6213},
- {"cvmx_uahc#_ohci0_hccommandstatus", CVMX_CSR_DB_TYPE_NCB, 32, 7350, 7, 6215},
- {"cvmx_uahc#_ohci0_hccontrol" , CVMX_CSR_DB_TYPE_NCB, 32, 7351, 10, 6222},
- {"cvmx_uahc#_ohci0_hccontrolcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7352, 2, 6232},
- {"cvmx_uahc#_ohci0_hccontrolheaded", CVMX_CSR_DB_TYPE_NCB, 32, 7353, 2, 6234},
- {"cvmx_uahc#_ohci0_hcdonehead" , CVMX_CSR_DB_TYPE_NCB, 32, 7354, 2, 6236},
- {"cvmx_uahc#_ohci0_hcfminterval", CVMX_CSR_DB_TYPE_NCB, 32, 7355, 4, 6238},
- {"cvmx_uahc#_ohci0_hcfmnumber" , CVMX_CSR_DB_TYPE_NCB, 32, 7356, 2, 6242},
- {"cvmx_uahc#_ohci0_hcfmremaining", CVMX_CSR_DB_TYPE_NCB, 32, 7357, 3, 6244},
- {"cvmx_uahc#_ohci0_hchcca" , CVMX_CSR_DB_TYPE_NCB, 32, 7358, 2, 6247},
- {"cvmx_uahc#_ohci0_hcinterruptdisable", CVMX_CSR_DB_TYPE_NCB, 32, 7359, 10, 6249},
- {"cvmx_uahc#_ohci0_hcinterruptenable", CVMX_CSR_DB_TYPE_NCB, 32, 7360, 10, 6259},
- {"cvmx_uahc#_ohci0_hcinterruptstatus", CVMX_CSR_DB_TYPE_NCB, 32, 7361, 10, 6269},
- {"cvmx_uahc#_ohci0_hclsthreshold", CVMX_CSR_DB_TYPE_NCB, 32, 7362, 2, 6279},
- {"cvmx_uahc#_ohci0_hcperiodcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7363, 2, 6281},
- {"cvmx_uahc#_ohci0_hcperiodicstart", CVMX_CSR_DB_TYPE_NCB, 32, 7364, 2, 6283},
- {"cvmx_uahc#_ohci0_hcrevision" , CVMX_CSR_DB_TYPE_NCB, 32, 7365, 2, 6285},
- {"cvmx_uahc#_ohci0_hcrhdescriptora", CVMX_CSR_DB_TYPE_NCB, 32, 7366, 8, 6287},
- {"cvmx_uahc#_ohci0_hcrhdescriptorb", CVMX_CSR_DB_TYPE_NCB, 32, 7367, 2, 6295},
- {"cvmx_uahc#_ohci0_hcrhportstatus#", CVMX_CSR_DB_TYPE_NCB, 32, 7368, 15, 6297},
- {"cvmx_uahc#_ohci0_hcrhstatus" , CVMX_CSR_DB_TYPE_NCB, 32, 7370, 8, 6312},
- {"cvmx_uahc#_ohci0_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 7371, 2, 6320},
- {"cvmx_uahc#_ohci0_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 7372, 1, 6322},
- {"cvmx_uctl#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7373, 7, 6323},
- {"cvmx_uctl#_clk_rst_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7374, 21, 6330},
- {"cvmx_uctl#_ehci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7375, 12, 6351},
- {"cvmx_uctl#_ehci_fla" , CVMX_CSR_DB_TYPE_RSL, 64, 7376, 2, 6363},
- {"cvmx_uctl#_erto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7377, 3, 6365},
- {"cvmx_uctl#_if_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 7378, 2, 6368},
- {"cvmx_uctl#_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 7379, 9, 6370},
- {"cvmx_uctl#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7380, 9, 6379},
- {"cvmx_uctl#_ohci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7381, 11, 6388},
- {"cvmx_uctl#_orto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7382, 3, 6399},
- {"cvmx_uctl#_ppaf_wm" , CVMX_CSR_DB_TYPE_RSL, 64, 7383, 2, 6402},
- {"cvmx_uctl#_uphy_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7384, 11, 6404},
- {"cvmx_uctl#_uphy_port#_ctl_status", CVMX_CSR_DB_TYPE_RSL, 64, 7385, 20, 6415},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 7387, 3, 6435},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 7388, 5, 6438},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7389, 3, 6443},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 7390, 8, 6446},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 7391, 2, 6454},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 7392, 2, 6456},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 7393, 2, 6458},
- {"cvmx_zip_throttle" , CVMX_CSR_DB_TYPE_RSL, 64, 7394, 2, 6460},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn61xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"AGL_GMX_BAD_REG" , 0x11800e0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"AGL_GMX_BIST" , 0x11800e0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"AGL_GMX_PRT0_CFG" , 0x11800e0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_PRT1_CFG" , 0x11800e0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_RX0_ADR_CAM0" , 0x11800e0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_RX1_ADR_CAM0" , 0x11800e0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_RX0_ADR_CAM1" , 0x11800e0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX1_ADR_CAM1" , 0x11800e0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX0_ADR_CAM2" , 0x11800e0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX1_ADR_CAM2" , 0x11800e0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX0_ADR_CAM3" , 0x11800e0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX1_ADR_CAM3" , 0x11800e0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX0_ADR_CAM4" , 0x11800e00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX1_ADR_CAM4" , 0x11800e00009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX0_ADR_CAM5" , 0x11800e00001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX1_ADR_CAM5" , 0x11800e00009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800e0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX1_ADR_CAM_EN" , 0x11800e0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX0_ADR_CTL" , 0x11800e0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX1_ADR_CTL" , 0x11800e0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX0_DECISION" , 0x11800e0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX1_DECISION" , 0x11800e0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX0_FRM_CHK" , 0x11800e0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX1_FRM_CHK" , 0x11800e0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX0_FRM_CTL" , 0x11800e0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX1_FRM_CTL" , 0x11800e0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX0_FRM_MAX" , 0x11800e0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX1_FRM_MAX" , 0x11800e0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX0_FRM_MIN" , 0x11800e0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX1_FRM_MIN" , 0x11800e0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX0_IFG" , 0x11800e0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX1_IFG" , 0x11800e0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX0_INT_EN" , 0x11800e0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX1_INT_EN" , 0x11800e0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX0_INT_REG" , 0x11800e0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX1_INT_REG" , 0x11800e0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX0_JABBER" , 0x11800e0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX1_JABBER" , 0x11800e0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800e0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX1_PAUSE_DROP_TIME" , 0x11800e0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX0_RX_INBND" , 0x11800e0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX1_RX_INBND" , 0x11800e0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX0_STATS_CTL" , 0x11800e0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX1_STATS_CTL" , 0x11800e0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX0_STATS_OCTS" , 0x11800e0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX1_STATS_OCTS" , 0x11800e0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800e0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX1_STATS_OCTS_CTL" , 0x11800e0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800e00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX1_STATS_OCTS_DMAC" , 0x11800e00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800e00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX1_STATS_OCTS_DRP" , 0x11800e00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX0_STATS_PKTS" , 0x11800e0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX1_STATS_PKTS" , 0x11800e0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800e00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX1_STATS_PKTS_BAD" , 0x11800e00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800e0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX1_STATS_PKTS_CTL" , 0x11800e0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800e00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX1_STATS_PKTS_DMAC" , 0x11800e00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800e00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX1_STATS_PKTS_DRP" , 0x11800e00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX0_UDD_SKP" , 0x11800e0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX1_UDD_SKP" , 0x11800e0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX_BP_DROP0" , 0x11800e0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_DROP1" , 0x11800e0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_OFF0" , 0x11800e0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_OFF1" , 0x11800e0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_ON0" , 0x11800e0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_BP_ON1" , 0x11800e0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_PRT_INFO" , 0x11800e00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_TX_STATUS" , 0x11800e00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"AGL_GMX_SMAC0" , 0x11800e0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_SMAC1" , 0x11800e0000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_STAT_BP" , 0x11800e0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_TX0_APPEND" , 0x11800e0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX1_APPEND" , 0x11800e0000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX0_CLK" , 0x11800e0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX1_CLK" , 0x11800e0000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX0_CTL" , 0x11800e0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX1_CTL" , 0x11800e0000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX0_MIN_PKT" , 0x11800e0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX1_MIN_PKT" , 0x11800e0000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800e0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX1_PAUSE_PKT_INTERVAL", 0x11800e0000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800e0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX1_PAUSE_PKT_TIME" , 0x11800e0000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800e0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX1_PAUSE_TOGO" , 0x11800e0000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800e0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX1_PAUSE_ZERO" , 0x11800e0000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800e0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX1_SOFT_PAUSE" , 0x11800e0000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX0_STAT0" , 0x11800e0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX1_STAT0" , 0x11800e0000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX0_STAT1" , 0x11800e0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX1_STAT1" , 0x11800e0000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX0_STAT2" , 0x11800e0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX1_STAT2" , 0x11800e0000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX0_STAT3" , 0x11800e0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX1_STAT3" , 0x11800e0000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX0_STAT4" , 0x11800e00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX1_STAT4" , 0x11800e0000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX0_STAT5" , 0x11800e00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX1_STAT5" , 0x11800e0000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX0_STAT6" , 0x11800e00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX1_STAT6" , 0x11800e0000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX0_STAT7" , 0x11800e00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX1_STAT7" , 0x11800e0000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX0_STAT8" , 0x11800e00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX1_STAT8" , 0x11800e0000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX0_STAT9" , 0x11800e00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX1_STAT9" , 0x11800e0000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX0_STATS_CTL" , 0x11800e0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX1_STATS_CTL" , 0x11800e0000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX0_THRESH" , 0x11800e0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX1_THRESH" , 0x11800e0000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX_BP" , 0x11800e00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"AGL_GMX_TX_COL_ATTEMPT" , 0x11800e0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"AGL_GMX_TX_IFG" , 0x11800e0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"AGL_GMX_TX_INT_EN" , 0x11800e0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"AGL_GMX_TX_INT_REG" , 0x11800e0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"AGL_GMX_TX_JAM" , 0x11800e0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"AGL_GMX_TX_LFSR" , 0x11800e00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"AGL_GMX_TX_OVR_BP" , 0x11800e00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800e00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800e00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"AGL_PRT0_CTL" , 0x11800e0002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"AGL_PRT1_CTL" , 0x11800e0002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU_BLOCK_INT" , 0x10700000007c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU_EN2_IO0_INT" , 0x107000000a600ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_EN2_IO1_INT" , 0x107000000a608ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_EN2_IO0_INT_W1C" , 0x107000000ce00ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_EN2_IO1_INT_W1C" , 0x107000000ce08ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_EN2_IO0_INT_W1S" , 0x107000000ae00ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_EN2_IO1_INT_W1S" , 0x107000000ae08ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_EN2_PP0_IP2" , 0x107000000a000ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP1_IP2" , 0x107000000a008ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP2_IP2" , 0x107000000a010ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP3_IP2" , 0x107000000a018ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP0_IP2_W1C" , 0x107000000c800ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP1_IP2_W1C" , 0x107000000c808ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP2_IP2_W1C" , 0x107000000c810ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP3_IP2_W1C" , 0x107000000c818ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP0_IP2_W1S" , 0x107000000a800ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP1_IP2_W1S" , 0x107000000a808ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP2_IP2_W1S" , 0x107000000a810ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP3_IP2_W1S" , 0x107000000a818ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP0_IP3" , 0x107000000a200ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP1_IP3" , 0x107000000a208ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP2_IP3" , 0x107000000a210ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP3_IP3" , 0x107000000a218ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP0_IP3_W1C" , 0x107000000ca00ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP1_IP3_W1C" , 0x107000000ca08ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP2_IP3_W1C" , 0x107000000ca10ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP3_IP3_W1C" , 0x107000000ca18ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP0_IP3_W1S" , 0x107000000aa00ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP1_IP3_W1S" , 0x107000000aa08ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP2_IP3_W1S" , 0x107000000aa10ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP3_IP3_W1S" , 0x107000000aa18ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP0_IP4" , 0x107000000a400ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP1_IP4" , 0x107000000a408ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP2_IP4" , 0x107000000a410ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP3_IP4" , 0x107000000a418ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP0_IP4_W1C" , 0x107000000cc00ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP1_IP4_W1C" , 0x107000000cc08ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP2_IP4_W1C" , 0x107000000cc10ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP3_IP4_W1C" , 0x107000000cc18ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP0_IP4_W1S" , 0x107000000ac00ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP1_IP4_W1S" , 0x107000000ac08ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP2_IP4_W1S" , 0x107000000ac10ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP3_IP4_W1S" , 0x107000000ac18ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT33_EN0" , 0x1070000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT33_EN0_W1C" , 0x1070000002410ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT33_EN0_W1S" , 0x1070000006410ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT33_EN1" , 0x1070000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT33_EN1_W1C" , 0x1070000002418ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT33_EN1_W1S" , 0x1070000006418ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT0_EN4_0_W1C" , 0x1070000002c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT1_EN4_0_W1C" , 0x1070000002c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT2_EN4_0_W1C" , 0x1070000002ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT3_EN4_0_W1C" , 0x1070000002cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT0_EN4_0_W1S" , 0x1070000006c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT1_EN4_0_W1S" , 0x1070000006c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT2_EN4_0_W1S" , 0x1070000006ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT3_EN4_0_W1S" , 0x1070000006cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT0_EN4_1_W1C" , 0x1070000002c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT1_EN4_1_W1C" , 0x1070000002c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT2_EN4_1_W1C" , 0x1070000002ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT3_EN4_1_W1C" , 0x1070000002cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT0_EN4_1_W1S" , 0x1070000006c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT1_EN4_1_W1S" , 0x1070000006c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT2_EN4_1_W1S" , 0x1070000006ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT3_EN4_1_W1S" , 0x1070000006cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT33_SUM0" , 0x1070000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU_INT_DBG_SEL" , 0x10700000007d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU_QLM0" , 0x1070000000780ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU_QLM1" , 0x1070000000788ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU_QLM2" , 0x1070000000790ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU_SUM1_IO0_INT" , 0x1070000008600ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU_SUM1_IO1_INT" , 0x1070000008608ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU_SUM1_PP0_IP2" , 0x1070000008000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU_SUM1_PP1_IP2" , 0x1070000008008ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU_SUM1_PP2_IP2" , 0x1070000008010ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU_SUM1_PP3_IP2" , 0x1070000008018ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU_SUM1_PP0_IP3" , 0x1070000008200ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU_SUM1_PP1_IP3" , 0x1070000008208ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU_SUM1_PP2_IP3" , 0x1070000008210ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU_SUM1_PP3_IP3" , 0x1070000008218ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU_SUM1_PP0_IP4" , 0x1070000008400ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP1_IP4" , 0x1070000008408ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP2_IP4" , 0x1070000008410ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP3_IP4" , 0x1070000008418ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM2_IO0_INT" , 0x1070000008e00ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM2_IO1_INT" , 0x1070000008e08ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM2_PP0_IP2" , 0x1070000008800ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM2_PP1_IP2" , 0x1070000008808ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM2_PP2_IP2" , 0x1070000008810ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM2_PP3_IP2" , 0x1070000008818ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM2_PP0_IP3" , 0x1070000008a00ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU_SUM2_PP1_IP3" , 0x1070000008a08ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU_SUM2_PP2_IP3" , 0x1070000008a10ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU_SUM2_PP3_IP3" , 0x1070000008a18ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU_SUM2_PP0_IP4" , 0x1070000008c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP1_IP4" , 0x1070000008c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP2_IP4" , 0x1070000008c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP3_IP4" , 0x1070000008c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_TIM4" , 0x10700000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_TIM5" , 0x10700000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_TIM6" , 0x10700000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_TIM7" , 0x10700000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_TIM8" , 0x10700000004c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_TIM9" , 0x10700000004c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_TIM_MULTI_CAST" , 0x107000000c200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"DFA_BIST0" , 0x11800370007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"DFA_BIST1" , 0x11800370007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"DFA_CONFIG" , 0x1180037000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"DFA_CONTROL" , 0x1180037000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"DFA_DEBUG0" , 0x1180037000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"DFA_DEBUG1" , 0x1180037000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"DFA_DEBUG2" , 0x1180037000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"DFA_DEBUG3" , 0x1180037000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"DFA_DTCFADR" , 0x1180037000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"DFA_ERROR" , 0x1180037000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"DFA_INTMSK" , 0x1180037000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"DFA_MEMHIDAT" , 0x1370700000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"DFA_PFC0_CNT" , 0x1180037000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"DFA_PFC0_CTL" , 0x1180037000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"DFA_PFC1_CNT" , 0x11800370000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"DFA_PFC1_CTL" , 0x1180037000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"DFA_PFC2_CNT" , 0x11800370000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"DFA_PFC2_CTL" , 0x11800370000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"DFA_PFC3_CNT" , 0x11800370000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"DFA_PFC3_CTL" , 0x11800370000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"DFA_PFC_GCTL" , 0x1180037000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"DPI_BIST_STATUS" , 0x1df0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"DPI_CTL" , 0x1df0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"DPI_DMA0_COUNTS" , 0x1df0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"DPI_DMA1_COUNTS" , 0x1df0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"DPI_DMA2_COUNTS" , 0x1df0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"DPI_DMA3_COUNTS" , 0x1df0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"DPI_DMA4_COUNTS" , 0x1df0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"DPI_DMA5_COUNTS" , 0x1df0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"DPI_DMA6_COUNTS" , 0x1df0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"DPI_DMA7_COUNTS" , 0x1df0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"DPI_DMA0_DBELL" , 0x1df0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"DPI_DMA1_DBELL" , 0x1df0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"DPI_DMA2_DBELL" , 0x1df0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"DPI_DMA3_DBELL" , 0x1df0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"DPI_DMA4_DBELL" , 0x1df0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"DPI_DMA5_DBELL" , 0x1df0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"DPI_DMA6_DBELL" , 0x1df0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"DPI_DMA7_DBELL" , 0x1df0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"DPI_DMA0_ERR_RSP_STATUS" , 0x1df0000000a80ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"DPI_DMA1_ERR_RSP_STATUS" , 0x1df0000000a88ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"DPI_DMA2_ERR_RSP_STATUS" , 0x1df0000000a90ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"DPI_DMA3_ERR_RSP_STATUS" , 0x1df0000000a98ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"DPI_DMA4_ERR_RSP_STATUS" , 0x1df0000000aa0ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"DPI_DMA5_ERR_RSP_STATUS" , 0x1df0000000aa8ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"DPI_DMA6_ERR_RSP_STATUS" , 0x1df0000000ab0ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"DPI_DMA7_ERR_RSP_STATUS" , 0x1df0000000ab8ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"DPI_DMA0_IBUFF_SADDR" , 0x1df0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"DPI_DMA1_IBUFF_SADDR" , 0x1df0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"DPI_DMA2_IBUFF_SADDR" , 0x1df0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"DPI_DMA3_IBUFF_SADDR" , 0x1df0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"DPI_DMA4_IBUFF_SADDR" , 0x1df00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"DPI_DMA5_IBUFF_SADDR" , 0x1df00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"DPI_DMA6_IBUFF_SADDR" , 0x1df00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"DPI_DMA7_IBUFF_SADDR" , 0x1df00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"DPI_DMA0_IFLIGHT" , 0x1df0000000a00ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"DPI_DMA1_IFLIGHT" , 0x1df0000000a08ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"DPI_DMA2_IFLIGHT" , 0x1df0000000a10ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"DPI_DMA3_IFLIGHT" , 0x1df0000000a18ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"DPI_DMA4_IFLIGHT" , 0x1df0000000a20ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"DPI_DMA5_IFLIGHT" , 0x1df0000000a28ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"DPI_DMA6_IFLIGHT" , 0x1df0000000a30ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"DPI_DMA7_IFLIGHT" , 0x1df0000000a38ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"DPI_DMA0_NADDR" , 0x1df0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"DPI_DMA1_NADDR" , 0x1df0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"DPI_DMA2_NADDR" , 0x1df0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"DPI_DMA3_NADDR" , 0x1df0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"DPI_DMA4_NADDR" , 0x1df00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"DPI_DMA5_NADDR" , 0x1df00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"DPI_DMA6_NADDR" , 0x1df00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"DPI_DMA7_NADDR" , 0x1df00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"DPI_DMA0_REQBNK0" , 0x1df0000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"DPI_DMA1_REQBNK0" , 0x1df0000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"DPI_DMA2_REQBNK0" , 0x1df0000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"DPI_DMA3_REQBNK0" , 0x1df0000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"DPI_DMA4_REQBNK0" , 0x1df0000000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"DPI_DMA5_REQBNK0" , 0x1df0000000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"DPI_DMA6_REQBNK0" , 0x1df0000000430ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"DPI_DMA7_REQBNK0" , 0x1df0000000438ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"DPI_DMA0_REQBNK1" , 0x1df0000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"DPI_DMA1_REQBNK1" , 0x1df0000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"DPI_DMA2_REQBNK1" , 0x1df0000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"DPI_DMA3_REQBNK1" , 0x1df0000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"DPI_DMA4_REQBNK1" , 0x1df00000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"DPI_DMA5_REQBNK1" , 0x1df00000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"DPI_DMA6_REQBNK1" , 0x1df00000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"DPI_DMA7_REQBNK1" , 0x1df00000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"DPI_DMA_CONTROL" , 0x1df0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"DPI_DMA_ENG0_EN" , 0x1df0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"DPI_DMA_ENG1_EN" , 0x1df0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"DPI_DMA_ENG2_EN" , 0x1df0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"DPI_DMA_ENG3_EN" , 0x1df0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"DPI_DMA_ENG4_EN" , 0x1df00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"DPI_DMA_ENG5_EN" , 0x1df00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"DPI_DMA_PP0_CNT" , 0x1df0000000b00ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA_PP1_CNT" , 0x1df0000000b08ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA_PP2_CNT" , 0x1df0000000b10ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA_PP3_CNT" , 0x1df0000000b18ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_ENG0_BUF" , 0x1df0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_ENG1_BUF" , 0x1df0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_ENG2_BUF" , 0x1df0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_ENG3_BUF" , 0x1df0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_ENG4_BUF" , 0x1df00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_ENG5_BUF" , 0x1df00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_INFO_REG" , 0x1df0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_INT_EN" , 0x1df0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_INT_REG" , 0x1df0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_NCB0_CFG" , 0x1df0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_PINT_INFO" , 0x1df0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"DPI_PKT_ERR_RSP" , 0x1df0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_REQ_ERR_RSP" , 0x1df0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"DPI_REQ_ERR_RSP_EN" , 0x1df0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"DPI_REQ_ERR_RST" , 0x1df0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"DPI_REQ_ERR_RST_EN" , 0x1df0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"DPI_REQ_ERR_SKIP_COMP" , 0x1df0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"DPI_REQ_GBL_EN" , 0x1df0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"DPI_SLI_PRT0_CFG" , 0x1df0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"DPI_SLI_PRT1_CFG" , 0x1df0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"DPI_SLI_PRT0_ERR" , 0x1df0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"DPI_SLI_PRT1_ERR" , 0x1df0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"DPI_SLI_PRT0_ERR_INFO" , 0x1df0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
- {"DPI_SLI_PRT1_ERR_INFO" , 0x1df0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
- {"FPA_ADDR_RANGE_ERROR" , 0x1180028000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"FPA_PACKET_THRESHOLD" , 0x1180028000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"FPA_POOL0_END_ADDR" , 0x1180028000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_POOL1_END_ADDR" , 0x1180028000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_POOL2_END_ADDR" , 0x1180028000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_POOL3_END_ADDR" , 0x1180028000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_POOL4_END_ADDR" , 0x1180028000378ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_POOL5_END_ADDR" , 0x1180028000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_POOL6_END_ADDR" , 0x1180028000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_POOL7_END_ADDR" , 0x1180028000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_POOL0_START_ADDR" , 0x1180028000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"FPA_POOL1_START_ADDR" , 0x1180028000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"FPA_POOL2_START_ADDR" , 0x1180028000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"FPA_POOL3_START_ADDR" , 0x1180028000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"FPA_POOL4_START_ADDR" , 0x1180028000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"FPA_POOL5_START_ADDR" , 0x1180028000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"FPA_POOL6_START_ADDR" , 0x1180028000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"FPA_POOL7_START_ADDR" , 0x1180028000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"FPA_POOL0_THRESHOLD" , 0x1180028000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"FPA_POOL1_THRESHOLD" , 0x1180028000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"FPA_POOL2_THRESHOLD" , 0x1180028000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"FPA_POOL3_THRESHOLD" , 0x1180028000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"FPA_POOL4_THRESHOLD" , 0x1180028000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"FPA_POOL5_THRESHOLD" , 0x1180028000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"FPA_POOL6_THRESHOLD" , 0x1180028000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"FPA_POOL7_THRESHOLD" , 0x1180028000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"FPA_WQE_THRESHOLD" , 0x1180028000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
- {"GMX1_CLK_EN" , 0x11800100007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
- {"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
- {"GMX1_HG2_CONTROL" , 0x1180010000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"GMX1_INF_MODE" , 0x11800100007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"GMX1_PRT000_CBFC_CTL" , 0x1180010000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX1_RX000_ADR_CAM4" , 0x11800100001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX1_RX001_ADR_CAM4" , 0x11800100009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX1_RX002_ADR_CAM4" , 0x11800100011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX1_RX003_ADR_CAM4" , 0x11800100019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX1_RX000_ADR_CAM5" , 0x11800100001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX1_RX001_ADR_CAM5" , 0x11800100009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX1_RX002_ADR_CAM5" , 0x11800100011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX1_RX003_ADR_CAM5" , 0x11800100019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX000_ADR_CAM_ALL_EN" , 0x1180008000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX001_ADR_CAM_ALL_EN" , 0x1180008000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX002_ADR_CAM_ALL_EN" , 0x1180008001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX003_ADR_CAM_ALL_EN" , 0x1180008001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX1_RX000_ADR_CAM_ALL_EN" , 0x1180010000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX1_RX001_ADR_CAM_ALL_EN" , 0x1180010000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX1_RX002_ADR_CAM_ALL_EN" , 0x1180010001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX1_RX003_ADR_CAM_ALL_EN" , 0x1180010001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180010000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180010000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180010001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180010001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"GMX1_RX_HG2_STATUS" , 0x1180010000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"GMX1_RX_PRT_INFO" , 0x11800100004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX1_RX_XAUI_BAD_COL" , 0x1180010000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX1_RX_XAUI_CTL" , 0x1180010000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX1_SMAC001" , 0x1180010000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX1_SMAC003" , 0x1180010001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX0_TB_REG" , 0x11800080007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX1_TB_REG" , 0x11800100007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX1_TX001_APPEND" , 0x1180010000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX1_TX003_APPEND" , 0x1180010001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX1_TX001_BURST" , 0x1180010000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX1_TX003_BURST" , 0x1180010001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX0_TX000_CBFC_XOFF" , 0x11800080005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX1_TX000_CBFC_XOFF" , 0x11800100005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX0_TX000_CBFC_XON" , 0x11800080005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX1_TX000_CBFC_XON" , 0x11800100005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX1_TX001_CTL" , 0x1180010000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX1_TX003_CTL" , 0x1180010001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX1_TX001_MIN_PKT" , 0x1180010000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX1_TX003_MIN_PKT" , 0x1180010001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX1_TX001_PAUSE_TOGO" , 0x1180010000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX1_TX003_PAUSE_TOGO" , 0x1180010001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX1_TX001_PAUSE_ZERO" , 0x1180010000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX1_TX003_PAUSE_ZERO" , 0x1180010001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX003_SGMII_CTL" , 0x1180008001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX1_TX000_SGMII_CTL" , 0x1180010000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX1_TX001_SGMII_CTL" , 0x1180010000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX1_TX002_SGMII_CTL" , 0x1180010001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX1_TX003_SGMII_CTL" , 0x1180010001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX1_TX001_SLOT" , 0x1180010000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX1_TX003_SLOT" , 0x1180010001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX1_TX001_SOFT_PAUSE" , 0x1180010000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX1_TX003_SOFT_PAUSE" , 0x1180010001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX1_TX001_STAT0" , 0x1180010000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX1_TX003_STAT0" , 0x1180010001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX1_TX001_STAT1" , 0x1180010000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX1_TX003_STAT1" , 0x1180010001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX1_TX001_STAT2" , 0x1180010000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX1_TX003_STAT2" , 0x1180010001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX1_TX001_STAT3" , 0x1180010000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX1_TX003_STAT3" , 0x1180010001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX1_TX000_STAT4" , 0x11800100002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX1_TX001_STAT4" , 0x1180010000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX1_TX002_STAT4" , 0x11800100012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX1_TX003_STAT4" , 0x1180010001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX1_TX000_STAT5" , 0x11800100002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX1_TX001_STAT5" , 0x1180010000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX1_TX002_STAT5" , 0x11800100012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX1_TX003_STAT5" , 0x1180010001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX1_TX000_STAT6" , 0x11800100002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX1_TX001_STAT6" , 0x1180010000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX1_TX002_STAT6" , 0x11800100012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX1_TX003_STAT6" , 0x1180010001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX1_TX000_STAT7" , 0x11800100002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX1_TX001_STAT7" , 0x1180010000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX1_TX002_STAT7" , 0x11800100012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX1_TX003_STAT7" , 0x1180010001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX1_TX000_STAT8" , 0x11800100002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX1_TX001_STAT8" , 0x1180010000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX1_TX002_STAT8" , 0x11800100012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX1_TX003_STAT8" , 0x1180010001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX1_TX000_STAT9" , 0x11800100002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX1_TX001_STAT9" , 0x1180010000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX1_TX002_STAT9" , 0x11800100012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX1_TX003_STAT9" , 0x1180010001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX1_TX001_STATS_CTL" , 0x1180010000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX1_TX003_STATS_CTL" , 0x1180010001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX1_TX001_THRESH" , 0x1180010000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX1_TX003_THRESH" , 0x1180010001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX1_TX_BP" , 0x11800100004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"GMX1_TX_CORRUPT" , 0x11800100004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"GMX1_TX_HG2_REG1" , 0x1180010000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"GMX1_TX_HG2_REG2" , 0x1180010000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"GMX1_TX_LFSR" , 0x11800100004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX1_TX_OVR_BP" , 0x11800100004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX1_TX_XAUI_CTL" , 0x1180010000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GMX1_XAUI_EXT_LOOPBACK" , 0x1180010000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
- {"GPIO_CLK_QLM0" , 0x10700000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 294},
- {"GPIO_CLK_QLM1" , 0x10700000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 294},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_MULTI_CAST" , 0x10700000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 297},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 298},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
- {"GPIO_XBIT_CFG16" , 0x1070000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
- {"GPIO_XBIT_CFG17" , 0x1070000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
- {"GPIO_XBIT_CFG18" , 0x1070000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
- {"GPIO_XBIT_CFG19" , 0x1070000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"IOB_TO_CMB_CREDITS" , 0x11800f00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 325},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT16_BP_PAGE_CNT" , 0x14f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT17_BP_PAGE_CNT" , 0x14f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT18_BP_PAGE_CNT" , 0x14f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT19_BP_PAGE_CNT" , 0x14f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT36_BP_PAGE_CNT2" , 0x14f0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT37_BP_PAGE_CNT2" , 0x14f0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT38_BP_PAGE_CNT2" , 0x14f0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT39_BP_PAGE_CNT2" , 0x14f0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT40_BP_PAGE_CNT3" , 0x14f00000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT41_BP_PAGE_CNT3" , 0x14f00000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT42_BP_PAGE_CNT3" , 0x14f00000003e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT43_BP_PAGE_CNT3" , 0x14f00000003e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT44_BP_PAGE_CNT3" , 0x14f00000003f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT45_BP_PAGE_CNT3" , 0x14f00000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT46_BP_PAGE_CNT3" , 0x14f0000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT47_BP_PAGE_CNT3" , 0x14f0000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14f0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14f0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14f0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14f00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT_BP_COUNTERS3_PAIR40", 0x14f00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PORT_BP_COUNTERS3_PAIR41", 0x14f00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PORT_BP_COUNTERS3_PAIR42", 0x14f00000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PORT_BP_COUNTERS3_PAIR43", 0x14f00000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PORT_BP_COUNTERS4_PAIR44", 0x14f0000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"IPD_PORT_BP_COUNTERS4_PAIR45", 0x14f0000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"IPD_PORT_BP_COUNTERS4_PAIR46", 0x14f0000000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"IPD_PORT_BP_COUNTERS4_PAIR47", 0x14f0000000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14f0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14f0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14f0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14f0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_128_CNT" , 0x14f0000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_129_CNT" , 0x14f0000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_130_CNT" , 0x14f0000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_131_CNT" , 0x14f0000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_132_CNT" , 0x14f0000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_133_CNT" , 0x14f0000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_134_CNT" , 0x14f0000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_135_CNT" , 0x14f0000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_136_CNT" , 0x14f0000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_137_CNT" , 0x14f0000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_138_CNT" , 0x14f0000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_139_CNT" , 0x14f0000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_140_CNT" , 0x14f0000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_141_CNT" , 0x14f0000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_142_CNT" , 0x14f0000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_143_CNT" , 0x14f0000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_144_CNT" , 0x14f0000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_145_CNT" , 0x14f0000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_146_CNT" , 0x14f0000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_147_CNT" , 0x14f0000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_148_CNT" , 0x14f0000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_149_CNT" , 0x14f0000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_150_CNT" , 0x14f0000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_151_CNT" , 0x14f0000000d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_152_CNT" , 0x14f0000000d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_153_CNT" , 0x14f0000000d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_154_CNT" , 0x14f0000000d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_155_CNT" , 0x14f0000000d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_156_CNT" , 0x14f0000000d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_157_CNT" , 0x14f0000000d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_158_CNT" , 0x14f0000000d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_159_CNT" , 0x14f0000000d80ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_256_CNT" , 0x14f0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_257_CNT" , 0x14f0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_258_CNT" , 0x14f0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_259_CNT" , 0x14f00000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_260_CNT" , 0x14f00000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_261_CNT" , 0x14f00000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_262_CNT" , 0x14f00000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_263_CNT" , 0x14f00000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_264_CNT" , 0x14f00000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_265_CNT" , 0x14f00000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_266_CNT" , 0x14f00000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_267_CNT" , 0x14f00000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_268_CNT" , 0x14f00000010e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_269_CNT" , 0x14f00000010f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_270_CNT" , 0x14f00000010f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_271_CNT" , 0x14f0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_272_CNT" , 0x14f0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_273_CNT" , 0x14f0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_274_CNT" , 0x14f0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_275_CNT" , 0x14f0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_276_CNT" , 0x14f0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_277_CNT" , 0x14f0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_278_CNT" , 0x14f0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_279_CNT" , 0x14f0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_280_CNT" , 0x14f0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_281_CNT" , 0x14f0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_282_CNT" , 0x14f0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_283_CNT" , 0x14f0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_284_CNT" , 0x14f0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_285_CNT" , 0x14f0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_286_CNT" , 0x14f0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_287_CNT" , 0x14f0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_320_CNT" , 0x14f0000001288ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_321_CNT" , 0x14f0000001290ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_322_CNT" , 0x14f0000001298ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_323_CNT" , 0x14f00000012a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_324_CNT" , 0x14f00000012a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_325_CNT" , 0x14f00000012b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_326_CNT" , 0x14f00000012b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_327_CNT" , 0x14f00000012c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_328_CNT" , 0x14f00000012c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_329_CNT" , 0x14f00000012d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_330_CNT" , 0x14f00000012d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_331_CNT" , 0x14f00000012e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_332_CNT" , 0x14f00000012e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_333_CNT" , 0x14f00000012f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_334_CNT" , 0x14f00000012f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_335_CNT" , 0x14f0000001300ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_336_CNT" , 0x14f0000001308ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_337_CNT" , 0x14f0000001310ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_338_CNT" , 0x14f0000001318ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_339_CNT" , 0x14f0000001320ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_340_CNT" , 0x14f0000001328ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_341_CNT" , 0x14f0000001330ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_342_CNT" , 0x14f0000001338ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_343_CNT" , 0x14f0000001340ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_344_CNT" , 0x14f0000001348ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_345_CNT" , 0x14f0000001350ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_346_CNT" , 0x14f0000001358ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_347_CNT" , 0x14f0000001360ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_348_CNT" , 0x14f0000001368ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_349_CNT" , 0x14f0000001370ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_350_CNT" , 0x14f0000001378ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_351_CNT" , 0x14f0000001380ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_352_CNT" , 0x14f0000001388ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_353_CNT" , 0x14f0000001390ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_354_CNT" , 0x14f0000001398ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_355_CNT" , 0x14f00000013a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_356_CNT" , 0x14f00000013a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_357_CNT" , 0x14f00000013b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_358_CNT" , 0x14f00000013b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_359_CNT" , 0x14f00000013c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_360_CNT" , 0x14f00000013c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_361_CNT" , 0x14f00000013d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_362_CNT" , 0x14f00000013d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_363_CNT" , 0x14f00000013e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_364_CNT" , 0x14f00000013e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_365_CNT" , 0x14f00000013f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_366_CNT" , 0x14f00000013f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_367_CNT" , 0x14f0000001400ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_368_CNT" , 0x14f0000001408ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_369_CNT" , 0x14f0000001410ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_370_CNT" , 0x14f0000001418ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_371_CNT" , 0x14f0000001420ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_372_CNT" , 0x14f0000001428ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_373_CNT" , 0x14f0000001430ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_374_CNT" , 0x14f0000001438ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_375_CNT" , 0x14f0000001440ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_376_CNT" , 0x14f0000001448ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_377_CNT" , 0x14f0000001450ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_378_CNT" , 0x14f0000001458ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_379_CNT" , 0x14f0000001460ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_380_CNT" , 0x14f0000001468ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_381_CNT" , 0x14f0000001470ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_382_CNT" , 0x14f0000001478ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_383_CNT" , 0x14f0000001480ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"IPD_PORT_QOS_INT2" , 0x14f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"IPD_PORT_QOS_INT5" , 0x14f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_PORT_QOS_INT_ENB2" , 0x14f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_PORT_QOS_INT_ENB5" , 0x14f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
- {"IPD_RED_PORT_ENABLE2" , 0x14f00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 353},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 355},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 357},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_BIG_CTL" , 0x1180080800030ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"L2C_BST" , 0x11800808007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_BST_MEM0" , 0x1180080c007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"L2C_BST_TDT0" , 0x1180080a007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"L2C_BST_TTG0" , 0x1180080a007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"L2C_COP0_MAP0" , 0x1180080940000ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1" , 0x1180080940008ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP2" , 0x1180080940010ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP3" , 0x1180080940018ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP4" , 0x1180080940020ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP5" , 0x1180080940028ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP6" , 0x1180080940030ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP7" , 0x1180080940038ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP8" , 0x1180080940040ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP9" , 0x1180080940048ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP10" , 0x1180080940050ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP11" , 0x1180080940058ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP12" , 0x1180080940060ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP13" , 0x1180080940068ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP14" , 0x1180080940070ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP15" , 0x1180080940078ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16" , 0x1180080940080ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP17" , 0x1180080940088ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP18" , 0x1180080940090ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP19" , 0x1180080940098ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP20" , 0x11800809400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP21" , 0x11800809400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP22" , 0x11800809400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP23" , 0x11800809400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP24" , 0x11800809400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP25" , 0x11800809400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP26" , 0x11800809400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP27" , 0x11800809400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP28" , 0x11800809400e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP29" , 0x11800809400e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP30" , 0x11800809400f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP31" , 0x11800809400f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP32" , 0x1180080940100ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP33" , 0x1180080940108ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP34" , 0x1180080940110ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP35" , 0x1180080940118ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP36" , 0x1180080940120ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP37" , 0x1180080940128ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP38" , 0x1180080940130ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP39" , 0x1180080940138ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP40" , 0x1180080940140ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP41" , 0x1180080940148ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP42" , 0x1180080940150ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP43" , 0x1180080940158ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP44" , 0x1180080940160ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP45" , 0x1180080940168ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP46" , 0x1180080940170ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP47" , 0x1180080940178ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP48" , 0x1180080940180ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP49" , 0x1180080940188ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP50" , 0x1180080940190ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP51" , 0x1180080940198ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP52" , 0x11800809401a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP53" , 0x11800809401a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP54" , 0x11800809401b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP55" , 0x11800809401b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP56" , 0x11800809401c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP57" , 0x11800809401c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP58" , 0x11800809401d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP59" , 0x11800809401d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP60" , 0x11800809401e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP61" , 0x11800809401e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP62" , 0x11800809401f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP63" , 0x11800809401f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP64" , 0x1180080940200ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP65" , 0x1180080940208ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP66" , 0x1180080940210ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP67" , 0x1180080940218ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP68" , 0x1180080940220ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP69" , 0x1180080940228ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP70" , 0x1180080940230ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP71" , 0x1180080940238ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP72" , 0x1180080940240ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP73" , 0x1180080940248ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP74" , 0x1180080940250ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP75" , 0x1180080940258ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP76" , 0x1180080940260ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP77" , 0x1180080940268ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP78" , 0x1180080940270ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP79" , 0x1180080940278ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP80" , 0x1180080940280ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP81" , 0x1180080940288ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP82" , 0x1180080940290ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP83" , 0x1180080940298ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP84" , 0x11800809402a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP85" , 0x11800809402a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP86" , 0x11800809402b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP87" , 0x11800809402b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP88" , 0x11800809402c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP89" , 0x11800809402c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP90" , 0x11800809402d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP91" , 0x11800809402d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP92" , 0x11800809402e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP93" , 0x11800809402e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP94" , 0x11800809402f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP95" , 0x11800809402f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP96" , 0x1180080940300ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP97" , 0x1180080940308ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP98" , 0x1180080940310ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP99" , 0x1180080940318ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP100" , 0x1180080940320ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP101" , 0x1180080940328ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP102" , 0x1180080940330ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP103" , 0x1180080940338ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP104" , 0x1180080940340ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP105" , 0x1180080940348ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP106" , 0x1180080940350ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP107" , 0x1180080940358ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP108" , 0x1180080940360ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP109" , 0x1180080940368ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP110" , 0x1180080940370ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP111" , 0x1180080940378ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP112" , 0x1180080940380ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP113" , 0x1180080940388ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP114" , 0x1180080940390ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP115" , 0x1180080940398ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP116" , 0x11800809403a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP117" , 0x11800809403a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP118" , 0x11800809403b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP119" , 0x11800809403b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP120" , 0x11800809403c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP121" , 0x11800809403c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP122" , 0x11800809403d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP123" , 0x11800809403d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP124" , 0x11800809403e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP125" , 0x11800809403e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP126" , 0x11800809403f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP127" , 0x11800809403f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP128" , 0x1180080940400ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP129" , 0x1180080940408ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP130" , 0x1180080940410ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP131" , 0x1180080940418ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP132" , 0x1180080940420ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP133" , 0x1180080940428ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP134" , 0x1180080940430ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP135" , 0x1180080940438ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP136" , 0x1180080940440ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP137" , 0x1180080940448ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP138" , 0x1180080940450ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP139" , 0x1180080940458ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP140" , 0x1180080940460ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP141" , 0x1180080940468ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP142" , 0x1180080940470ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP143" , 0x1180080940478ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP144" , 0x1180080940480ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP145" , 0x1180080940488ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP146" , 0x1180080940490ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP147" , 0x1180080940498ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP148" , 0x11800809404a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP149" , 0x11800809404a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP150" , 0x11800809404b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP151" , 0x11800809404b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP152" , 0x11800809404c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP153" , 0x11800809404c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP154" , 0x11800809404d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP155" , 0x11800809404d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP156" , 0x11800809404e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP157" , 0x11800809404e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP158" , 0x11800809404f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP159" , 0x11800809404f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP160" , 0x1180080940500ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP161" , 0x1180080940508ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP162" , 0x1180080940510ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP163" , 0x1180080940518ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP164" , 0x1180080940520ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP165" , 0x1180080940528ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP166" , 0x1180080940530ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP167" , 0x1180080940538ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP168" , 0x1180080940540ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP169" , 0x1180080940548ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP170" , 0x1180080940550ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP171" , 0x1180080940558ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP172" , 0x1180080940560ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP173" , 0x1180080940568ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP174" , 0x1180080940570ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP175" , 0x1180080940578ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP176" , 0x1180080940580ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP177" , 0x1180080940588ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP178" , 0x1180080940590ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP179" , 0x1180080940598ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP180" , 0x11800809405a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP181" , 0x11800809405a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP182" , 0x11800809405b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP183" , 0x11800809405b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP184" , 0x11800809405c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP185" , 0x11800809405c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP186" , 0x11800809405d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP187" , 0x11800809405d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP188" , 0x11800809405e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP189" , 0x11800809405e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP190" , 0x11800809405f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP191" , 0x11800809405f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP192" , 0x1180080940600ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP193" , 0x1180080940608ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP194" , 0x1180080940610ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP195" , 0x1180080940618ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP196" , 0x1180080940620ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP197" , 0x1180080940628ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP198" , 0x1180080940630ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP199" , 0x1180080940638ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP200" , 0x1180080940640ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP201" , 0x1180080940648ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP202" , 0x1180080940650ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP203" , 0x1180080940658ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP204" , 0x1180080940660ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP205" , 0x1180080940668ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP206" , 0x1180080940670ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP207" , 0x1180080940678ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP208" , 0x1180080940680ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP209" , 0x1180080940688ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP210" , 0x1180080940690ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP211" , 0x1180080940698ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP212" , 0x11800809406a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP213" , 0x11800809406a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP214" , 0x11800809406b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP215" , 0x11800809406b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP216" , 0x11800809406c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP217" , 0x11800809406c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP218" , 0x11800809406d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP219" , 0x11800809406d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP220" , 0x11800809406e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP221" , 0x11800809406e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP222" , 0x11800809406f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP223" , 0x11800809406f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP224" , 0x1180080940700ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP225" , 0x1180080940708ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP226" , 0x1180080940710ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP227" , 0x1180080940718ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP228" , 0x1180080940720ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP229" , 0x1180080940728ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP230" , 0x1180080940730ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP231" , 0x1180080940738ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP232" , 0x1180080940740ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP233" , 0x1180080940748ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP234" , 0x1180080940750ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP235" , 0x1180080940758ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP236" , 0x1180080940760ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP237" , 0x1180080940768ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP238" , 0x1180080940770ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP239" , 0x1180080940778ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP240" , 0x1180080940780ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP241" , 0x1180080940788ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP242" , 0x1180080940790ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP243" , 0x1180080940798ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP244" , 0x11800809407a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP245" , 0x11800809407a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP246" , 0x11800809407b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP247" , 0x11800809407b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP248" , 0x11800809407c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP249" , 0x11800809407c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP250" , 0x11800809407d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP251" , 0x11800809407d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP252" , 0x11800809407e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP253" , 0x11800809407e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP254" , 0x11800809407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP255" , 0x11800809407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP256" , 0x1180080940800ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP257" , 0x1180080940808ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP258" , 0x1180080940810ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP259" , 0x1180080940818ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP260" , 0x1180080940820ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP261" , 0x1180080940828ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP262" , 0x1180080940830ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP263" , 0x1180080940838ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP264" , 0x1180080940840ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP265" , 0x1180080940848ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP266" , 0x1180080940850ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP267" , 0x1180080940858ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP268" , 0x1180080940860ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP269" , 0x1180080940868ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP270" , 0x1180080940870ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP271" , 0x1180080940878ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP272" , 0x1180080940880ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP273" , 0x1180080940888ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP274" , 0x1180080940890ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP275" , 0x1180080940898ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP276" , 0x11800809408a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP277" , 0x11800809408a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP278" , 0x11800809408b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP279" , 0x11800809408b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP280" , 0x11800809408c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP281" , 0x11800809408c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP282" , 0x11800809408d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP283" , 0x11800809408d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP284" , 0x11800809408e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP285" , 0x11800809408e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP286" , 0x11800809408f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP287" , 0x11800809408f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP288" , 0x1180080940900ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP289" , 0x1180080940908ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP290" , 0x1180080940910ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP291" , 0x1180080940918ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP292" , 0x1180080940920ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP293" , 0x1180080940928ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP294" , 0x1180080940930ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP295" , 0x1180080940938ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP296" , 0x1180080940940ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP297" , 0x1180080940948ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP298" , 0x1180080940950ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP299" , 0x1180080940958ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP300" , 0x1180080940960ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP301" , 0x1180080940968ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP302" , 0x1180080940970ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP303" , 0x1180080940978ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP304" , 0x1180080940980ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP305" , 0x1180080940988ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP306" , 0x1180080940990ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP307" , 0x1180080940998ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP308" , 0x11800809409a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP309" , 0x11800809409a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP310" , 0x11800809409b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP311" , 0x11800809409b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP312" , 0x11800809409c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP313" , 0x11800809409c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP314" , 0x11800809409d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP315" , 0x11800809409d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP316" , 0x11800809409e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP317" , 0x11800809409e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP318" , 0x11800809409f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP319" , 0x11800809409f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP320" , 0x1180080940a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP321" , 0x1180080940a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP322" , 0x1180080940a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP323" , 0x1180080940a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP324" , 0x1180080940a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP325" , 0x1180080940a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP326" , 0x1180080940a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP327" , 0x1180080940a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP328" , 0x1180080940a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP329" , 0x1180080940a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP330" , 0x1180080940a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP331" , 0x1180080940a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP332" , 0x1180080940a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP333" , 0x1180080940a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP334" , 0x1180080940a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP335" , 0x1180080940a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP336" , 0x1180080940a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP337" , 0x1180080940a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP338" , 0x1180080940a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP339" , 0x1180080940a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP340" , 0x1180080940aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP341" , 0x1180080940aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP342" , 0x1180080940ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP343" , 0x1180080940ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP344" , 0x1180080940ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP345" , 0x1180080940ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP346" , 0x1180080940ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP347" , 0x1180080940ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP348" , 0x1180080940ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP349" , 0x1180080940ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP350" , 0x1180080940af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP351" , 0x1180080940af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP352" , 0x1180080940b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP353" , 0x1180080940b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP354" , 0x1180080940b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP355" , 0x1180080940b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP356" , 0x1180080940b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP357" , 0x1180080940b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP358" , 0x1180080940b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP359" , 0x1180080940b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP360" , 0x1180080940b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP361" , 0x1180080940b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP362" , 0x1180080940b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP363" , 0x1180080940b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP364" , 0x1180080940b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP365" , 0x1180080940b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP366" , 0x1180080940b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP367" , 0x1180080940b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP368" , 0x1180080940b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP369" , 0x1180080940b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP370" , 0x1180080940b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP371" , 0x1180080940b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP372" , 0x1180080940ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP373" , 0x1180080940ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP374" , 0x1180080940bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP375" , 0x1180080940bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP376" , 0x1180080940bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP377" , 0x1180080940bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP378" , 0x1180080940bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP379" , 0x1180080940bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP380" , 0x1180080940be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP381" , 0x1180080940be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP382" , 0x1180080940bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP383" , 0x1180080940bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP384" , 0x1180080940c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP385" , 0x1180080940c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP386" , 0x1180080940c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP387" , 0x1180080940c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP388" , 0x1180080940c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP389" , 0x1180080940c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP390" , 0x1180080940c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP391" , 0x1180080940c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP392" , 0x1180080940c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP393" , 0x1180080940c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP394" , 0x1180080940c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP395" , 0x1180080940c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP396" , 0x1180080940c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP397" , 0x1180080940c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP398" , 0x1180080940c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP399" , 0x1180080940c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP400" , 0x1180080940c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP401" , 0x1180080940c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP402" , 0x1180080940c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP403" , 0x1180080940c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP404" , 0x1180080940ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP405" , 0x1180080940ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP406" , 0x1180080940cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP407" , 0x1180080940cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP408" , 0x1180080940cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP409" , 0x1180080940cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP410" , 0x1180080940cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP411" , 0x1180080940cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP412" , 0x1180080940ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP413" , 0x1180080940ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP414" , 0x1180080940cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP415" , 0x1180080940cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP416" , 0x1180080940d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP417" , 0x1180080940d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP418" , 0x1180080940d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP419" , 0x1180080940d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP420" , 0x1180080940d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP421" , 0x1180080940d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP422" , 0x1180080940d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP423" , 0x1180080940d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP424" , 0x1180080940d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP425" , 0x1180080940d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP426" , 0x1180080940d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP427" , 0x1180080940d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP428" , 0x1180080940d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP429" , 0x1180080940d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP430" , 0x1180080940d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP431" , 0x1180080940d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP432" , 0x1180080940d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP433" , 0x1180080940d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP434" , 0x1180080940d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP435" , 0x1180080940d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP436" , 0x1180080940da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP437" , 0x1180080940da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP438" , 0x1180080940db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP439" , 0x1180080940db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP440" , 0x1180080940dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP441" , 0x1180080940dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP442" , 0x1180080940dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP443" , 0x1180080940dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP444" , 0x1180080940de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP445" , 0x1180080940de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP446" , 0x1180080940df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP447" , 0x1180080940df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP448" , 0x1180080940e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP449" , 0x1180080940e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP450" , 0x1180080940e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP451" , 0x1180080940e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP452" , 0x1180080940e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP453" , 0x1180080940e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP454" , 0x1180080940e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP455" , 0x1180080940e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP456" , 0x1180080940e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP457" , 0x1180080940e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP458" , 0x1180080940e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP459" , 0x1180080940e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP460" , 0x1180080940e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP461" , 0x1180080940e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP462" , 0x1180080940e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP463" , 0x1180080940e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP464" , 0x1180080940e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP465" , 0x1180080940e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP466" , 0x1180080940e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP467" , 0x1180080940e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP468" , 0x1180080940ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP469" , 0x1180080940ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP470" , 0x1180080940eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP471" , 0x1180080940eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP472" , 0x1180080940ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP473" , 0x1180080940ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP474" , 0x1180080940ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP475" , 0x1180080940ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP476" , 0x1180080940ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP477" , 0x1180080940ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP478" , 0x1180080940ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP479" , 0x1180080940ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP480" , 0x1180080940f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP481" , 0x1180080940f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP482" , 0x1180080940f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP483" , 0x1180080940f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP484" , 0x1180080940f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP485" , 0x1180080940f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP486" , 0x1180080940f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP487" , 0x1180080940f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP488" , 0x1180080940f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP489" , 0x1180080940f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP490" , 0x1180080940f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP491" , 0x1180080940f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP492" , 0x1180080940f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP493" , 0x1180080940f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP494" , 0x1180080940f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP495" , 0x1180080940f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP496" , 0x1180080940f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP497" , 0x1180080940f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP498" , 0x1180080940f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP499" , 0x1180080940f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP500" , 0x1180080940fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP501" , 0x1180080940fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP502" , 0x1180080940fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP503" , 0x1180080940fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP504" , 0x1180080940fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP505" , 0x1180080940fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP506" , 0x1180080940fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP507" , 0x1180080940fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP508" , 0x1180080940fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP509" , 0x1180080940fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP510" , 0x1180080940ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP511" , 0x1180080940ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP512" , 0x1180080941000ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP513" , 0x1180080941008ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP514" , 0x1180080941010ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP515" , 0x1180080941018ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP516" , 0x1180080941020ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP517" , 0x1180080941028ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP518" , 0x1180080941030ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP519" , 0x1180080941038ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP520" , 0x1180080941040ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP521" , 0x1180080941048ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP522" , 0x1180080941050ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP523" , 0x1180080941058ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP524" , 0x1180080941060ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP525" , 0x1180080941068ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP526" , 0x1180080941070ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP527" , 0x1180080941078ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP528" , 0x1180080941080ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP529" , 0x1180080941088ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP530" , 0x1180080941090ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP531" , 0x1180080941098ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP532" , 0x11800809410a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP533" , 0x11800809410a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP534" , 0x11800809410b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP535" , 0x11800809410b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP536" , 0x11800809410c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP537" , 0x11800809410c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP538" , 0x11800809410d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP539" , 0x11800809410d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP540" , 0x11800809410e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP541" , 0x11800809410e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP542" , 0x11800809410f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP543" , 0x11800809410f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP544" , 0x1180080941100ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP545" , 0x1180080941108ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP546" , 0x1180080941110ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP547" , 0x1180080941118ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP548" , 0x1180080941120ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP549" , 0x1180080941128ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP550" , 0x1180080941130ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP551" , 0x1180080941138ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP552" , 0x1180080941140ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP553" , 0x1180080941148ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP554" , 0x1180080941150ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP555" , 0x1180080941158ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP556" , 0x1180080941160ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP557" , 0x1180080941168ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP558" , 0x1180080941170ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP559" , 0x1180080941178ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP560" , 0x1180080941180ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP561" , 0x1180080941188ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP562" , 0x1180080941190ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP563" , 0x1180080941198ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP564" , 0x11800809411a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP565" , 0x11800809411a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP566" , 0x11800809411b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP567" , 0x11800809411b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP568" , 0x11800809411c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP569" , 0x11800809411c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP570" , 0x11800809411d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP571" , 0x11800809411d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP572" , 0x11800809411e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP573" , 0x11800809411e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP574" , 0x11800809411f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP575" , 0x11800809411f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP576" , 0x1180080941200ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP577" , 0x1180080941208ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP578" , 0x1180080941210ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP579" , 0x1180080941218ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP580" , 0x1180080941220ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP581" , 0x1180080941228ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP582" , 0x1180080941230ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP583" , 0x1180080941238ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP584" , 0x1180080941240ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP585" , 0x1180080941248ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP586" , 0x1180080941250ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP587" , 0x1180080941258ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP588" , 0x1180080941260ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP589" , 0x1180080941268ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP590" , 0x1180080941270ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP591" , 0x1180080941278ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP592" , 0x1180080941280ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP593" , 0x1180080941288ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP594" , 0x1180080941290ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP595" , 0x1180080941298ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP596" , 0x11800809412a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP597" , 0x11800809412a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP598" , 0x11800809412b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP599" , 0x11800809412b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP600" , 0x11800809412c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP601" , 0x11800809412c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP602" , 0x11800809412d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP603" , 0x11800809412d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP604" , 0x11800809412e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP605" , 0x11800809412e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP606" , 0x11800809412f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP607" , 0x11800809412f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP608" , 0x1180080941300ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP609" , 0x1180080941308ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP610" , 0x1180080941310ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP611" , 0x1180080941318ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP612" , 0x1180080941320ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP613" , 0x1180080941328ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP614" , 0x1180080941330ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP615" , 0x1180080941338ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP616" , 0x1180080941340ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP617" , 0x1180080941348ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP618" , 0x1180080941350ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP619" , 0x1180080941358ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP620" , 0x1180080941360ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP621" , 0x1180080941368ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP622" , 0x1180080941370ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP623" , 0x1180080941378ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP624" , 0x1180080941380ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP625" , 0x1180080941388ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP626" , 0x1180080941390ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP627" , 0x1180080941398ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP628" , 0x11800809413a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP629" , 0x11800809413a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP630" , 0x11800809413b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP631" , 0x11800809413b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP632" , 0x11800809413c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP633" , 0x11800809413c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP634" , 0x11800809413d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP635" , 0x11800809413d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP636" , 0x11800809413e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP637" , 0x11800809413e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP638" , 0x11800809413f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP639" , 0x11800809413f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP640" , 0x1180080941400ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP641" , 0x1180080941408ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP642" , 0x1180080941410ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP643" , 0x1180080941418ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP644" , 0x1180080941420ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP645" , 0x1180080941428ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP646" , 0x1180080941430ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP647" , 0x1180080941438ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP648" , 0x1180080941440ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP649" , 0x1180080941448ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP650" , 0x1180080941450ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP651" , 0x1180080941458ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP652" , 0x1180080941460ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP653" , 0x1180080941468ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP654" , 0x1180080941470ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP655" , 0x1180080941478ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP656" , 0x1180080941480ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP657" , 0x1180080941488ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP658" , 0x1180080941490ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP659" , 0x1180080941498ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP660" , 0x11800809414a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP661" , 0x11800809414a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP662" , 0x11800809414b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP663" , 0x11800809414b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP664" , 0x11800809414c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP665" , 0x11800809414c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP666" , 0x11800809414d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP667" , 0x11800809414d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP668" , 0x11800809414e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP669" , 0x11800809414e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP670" , 0x11800809414f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP671" , 0x11800809414f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP672" , 0x1180080941500ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP673" , 0x1180080941508ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP674" , 0x1180080941510ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP675" , 0x1180080941518ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP676" , 0x1180080941520ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP677" , 0x1180080941528ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP678" , 0x1180080941530ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP679" , 0x1180080941538ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP680" , 0x1180080941540ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP681" , 0x1180080941548ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP682" , 0x1180080941550ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP683" , 0x1180080941558ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP684" , 0x1180080941560ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP685" , 0x1180080941568ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP686" , 0x1180080941570ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP687" , 0x1180080941578ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP688" , 0x1180080941580ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP689" , 0x1180080941588ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP690" , 0x1180080941590ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP691" , 0x1180080941598ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP692" , 0x11800809415a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP693" , 0x11800809415a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP694" , 0x11800809415b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP695" , 0x11800809415b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP696" , 0x11800809415c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP697" , 0x11800809415c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP698" , 0x11800809415d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP699" , 0x11800809415d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP700" , 0x11800809415e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP701" , 0x11800809415e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP702" , 0x11800809415f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP703" , 0x11800809415f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP704" , 0x1180080941600ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP705" , 0x1180080941608ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP706" , 0x1180080941610ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP707" , 0x1180080941618ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP708" , 0x1180080941620ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP709" , 0x1180080941628ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP710" , 0x1180080941630ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP711" , 0x1180080941638ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP712" , 0x1180080941640ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP713" , 0x1180080941648ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP714" , 0x1180080941650ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP715" , 0x1180080941658ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP716" , 0x1180080941660ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP717" , 0x1180080941668ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP718" , 0x1180080941670ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP719" , 0x1180080941678ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP720" , 0x1180080941680ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP721" , 0x1180080941688ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP722" , 0x1180080941690ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP723" , 0x1180080941698ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP724" , 0x11800809416a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP725" , 0x11800809416a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP726" , 0x11800809416b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP727" , 0x11800809416b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP728" , 0x11800809416c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP729" , 0x11800809416c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP730" , 0x11800809416d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP731" , 0x11800809416d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP732" , 0x11800809416e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP733" , 0x11800809416e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP734" , 0x11800809416f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP735" , 0x11800809416f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP736" , 0x1180080941700ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP737" , 0x1180080941708ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP738" , 0x1180080941710ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP739" , 0x1180080941718ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP740" , 0x1180080941720ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP741" , 0x1180080941728ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP742" , 0x1180080941730ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP743" , 0x1180080941738ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP744" , 0x1180080941740ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP745" , 0x1180080941748ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP746" , 0x1180080941750ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP747" , 0x1180080941758ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP748" , 0x1180080941760ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP749" , 0x1180080941768ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP750" , 0x1180080941770ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP751" , 0x1180080941778ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP752" , 0x1180080941780ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP753" , 0x1180080941788ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP754" , 0x1180080941790ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP755" , 0x1180080941798ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP756" , 0x11800809417a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP757" , 0x11800809417a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP758" , 0x11800809417b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP759" , 0x11800809417b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP760" , 0x11800809417c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP761" , 0x11800809417c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP762" , 0x11800809417d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP763" , 0x11800809417d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP764" , 0x11800809417e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP765" , 0x11800809417e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP766" , 0x11800809417f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP767" , 0x11800809417f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP768" , 0x1180080941800ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP769" , 0x1180080941808ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP770" , 0x1180080941810ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP771" , 0x1180080941818ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP772" , 0x1180080941820ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP773" , 0x1180080941828ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP774" , 0x1180080941830ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP775" , 0x1180080941838ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP776" , 0x1180080941840ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP777" , 0x1180080941848ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP778" , 0x1180080941850ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP779" , 0x1180080941858ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP780" , 0x1180080941860ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP781" , 0x1180080941868ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP782" , 0x1180080941870ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP783" , 0x1180080941878ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP784" , 0x1180080941880ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP785" , 0x1180080941888ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP786" , 0x1180080941890ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP787" , 0x1180080941898ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP788" , 0x11800809418a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP789" , 0x11800809418a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP790" , 0x11800809418b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP791" , 0x11800809418b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP792" , 0x11800809418c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP793" , 0x11800809418c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP794" , 0x11800809418d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP795" , 0x11800809418d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP796" , 0x11800809418e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP797" , 0x11800809418e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP798" , 0x11800809418f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP799" , 0x11800809418f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP800" , 0x1180080941900ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP801" , 0x1180080941908ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP802" , 0x1180080941910ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP803" , 0x1180080941918ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP804" , 0x1180080941920ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP805" , 0x1180080941928ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP806" , 0x1180080941930ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP807" , 0x1180080941938ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP808" , 0x1180080941940ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP809" , 0x1180080941948ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP810" , 0x1180080941950ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP811" , 0x1180080941958ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP812" , 0x1180080941960ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP813" , 0x1180080941968ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP814" , 0x1180080941970ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP815" , 0x1180080941978ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP816" , 0x1180080941980ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP817" , 0x1180080941988ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP818" , 0x1180080941990ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP819" , 0x1180080941998ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP820" , 0x11800809419a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP821" , 0x11800809419a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP822" , 0x11800809419b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP823" , 0x11800809419b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP824" , 0x11800809419c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP825" , 0x11800809419c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP826" , 0x11800809419d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP827" , 0x11800809419d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP828" , 0x11800809419e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP829" , 0x11800809419e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP830" , 0x11800809419f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP831" , 0x11800809419f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP832" , 0x1180080941a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP833" , 0x1180080941a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP834" , 0x1180080941a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP835" , 0x1180080941a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP836" , 0x1180080941a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP837" , 0x1180080941a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP838" , 0x1180080941a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP839" , 0x1180080941a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP840" , 0x1180080941a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP841" , 0x1180080941a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP842" , 0x1180080941a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP843" , 0x1180080941a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP844" , 0x1180080941a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP845" , 0x1180080941a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP846" , 0x1180080941a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP847" , 0x1180080941a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP848" , 0x1180080941a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP849" , 0x1180080941a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP850" , 0x1180080941a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP851" , 0x1180080941a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP852" , 0x1180080941aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP853" , 0x1180080941aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP854" , 0x1180080941ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP855" , 0x1180080941ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP856" , 0x1180080941ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP857" , 0x1180080941ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP858" , 0x1180080941ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP859" , 0x1180080941ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP860" , 0x1180080941ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP861" , 0x1180080941ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP862" , 0x1180080941af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP863" , 0x1180080941af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP864" , 0x1180080941b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP865" , 0x1180080941b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP866" , 0x1180080941b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP867" , 0x1180080941b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP868" , 0x1180080941b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP869" , 0x1180080941b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP870" , 0x1180080941b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP871" , 0x1180080941b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP872" , 0x1180080941b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP873" , 0x1180080941b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP874" , 0x1180080941b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP875" , 0x1180080941b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP876" , 0x1180080941b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP877" , 0x1180080941b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP878" , 0x1180080941b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP879" , 0x1180080941b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP880" , 0x1180080941b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP881" , 0x1180080941b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP882" , 0x1180080941b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP883" , 0x1180080941b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP884" , 0x1180080941ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP885" , 0x1180080941ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP886" , 0x1180080941bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP887" , 0x1180080941bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP888" , 0x1180080941bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP889" , 0x1180080941bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP890" , 0x1180080941bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP891" , 0x1180080941bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP892" , 0x1180080941be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP893" , 0x1180080941be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP894" , 0x1180080941bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP895" , 0x1180080941bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP896" , 0x1180080941c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP897" , 0x1180080941c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP898" , 0x1180080941c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP899" , 0x1180080941c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP900" , 0x1180080941c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP901" , 0x1180080941c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP902" , 0x1180080941c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP903" , 0x1180080941c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP904" , 0x1180080941c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP905" , 0x1180080941c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP906" , 0x1180080941c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP907" , 0x1180080941c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP908" , 0x1180080941c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP909" , 0x1180080941c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP910" , 0x1180080941c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP911" , 0x1180080941c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP912" , 0x1180080941c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP913" , 0x1180080941c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP914" , 0x1180080941c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP915" , 0x1180080941c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP916" , 0x1180080941ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP917" , 0x1180080941ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP918" , 0x1180080941cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP919" , 0x1180080941cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP920" , 0x1180080941cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP921" , 0x1180080941cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP922" , 0x1180080941cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP923" , 0x1180080941cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP924" , 0x1180080941ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP925" , 0x1180080941ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP926" , 0x1180080941cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP927" , 0x1180080941cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP928" , 0x1180080941d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP929" , 0x1180080941d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP930" , 0x1180080941d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP931" , 0x1180080941d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP932" , 0x1180080941d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP933" , 0x1180080941d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP934" , 0x1180080941d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP935" , 0x1180080941d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP936" , 0x1180080941d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP937" , 0x1180080941d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP938" , 0x1180080941d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP939" , 0x1180080941d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP940" , 0x1180080941d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP941" , 0x1180080941d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP942" , 0x1180080941d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP943" , 0x1180080941d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP944" , 0x1180080941d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP945" , 0x1180080941d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP946" , 0x1180080941d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP947" , 0x1180080941d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP948" , 0x1180080941da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP949" , 0x1180080941da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP950" , 0x1180080941db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP951" , 0x1180080941db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP952" , 0x1180080941dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP953" , 0x1180080941dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP954" , 0x1180080941dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP955" , 0x1180080941dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP956" , 0x1180080941de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP957" , 0x1180080941de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP958" , 0x1180080941df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP959" , 0x1180080941df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP960" , 0x1180080941e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP961" , 0x1180080941e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP962" , 0x1180080941e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP963" , 0x1180080941e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP964" , 0x1180080941e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP965" , 0x1180080941e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP966" , 0x1180080941e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP967" , 0x1180080941e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP968" , 0x1180080941e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP969" , 0x1180080941e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP970" , 0x1180080941e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP971" , 0x1180080941e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP972" , 0x1180080941e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP973" , 0x1180080941e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP974" , 0x1180080941e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP975" , 0x1180080941e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP976" , 0x1180080941e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP977" , 0x1180080941e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP978" , 0x1180080941e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP979" , 0x1180080941e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP980" , 0x1180080941ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP981" , 0x1180080941ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP982" , 0x1180080941eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP983" , 0x1180080941eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP984" , 0x1180080941ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP985" , 0x1180080941ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP986" , 0x1180080941ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP987" , 0x1180080941ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP988" , 0x1180080941ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP989" , 0x1180080941ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP990" , 0x1180080941ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP991" , 0x1180080941ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP992" , 0x1180080941f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP993" , 0x1180080941f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP994" , 0x1180080941f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP995" , 0x1180080941f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP996" , 0x1180080941f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP997" , 0x1180080941f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP998" , 0x1180080941f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP999" , 0x1180080941f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1000" , 0x1180080941f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1001" , 0x1180080941f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1002" , 0x1180080941f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1003" , 0x1180080941f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1004" , 0x1180080941f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1005" , 0x1180080941f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1006" , 0x1180080941f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1007" , 0x1180080941f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1008" , 0x1180080941f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1009" , 0x1180080941f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1010" , 0x1180080941f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1011" , 0x1180080941f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1012" , 0x1180080941fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1013" , 0x1180080941fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1014" , 0x1180080941fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1015" , 0x1180080941fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1016" , 0x1180080941fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1017" , 0x1180080941fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1018" , 0x1180080941fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1019" , 0x1180080941fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1020" , 0x1180080941fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1021" , 0x1180080941fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1022" , 0x1180080941ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1023" , 0x1180080941ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16128" , 0x118008095f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16129" , 0x118008095f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16130" , 0x118008095f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16131" , 0x118008095f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16132" , 0x118008095f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16133" , 0x118008095f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16134" , 0x118008095f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16135" , 0x118008095f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16136" , 0x118008095f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16137" , 0x118008095f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16138" , 0x118008095f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16139" , 0x118008095f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16140" , 0x118008095f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16141" , 0x118008095f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16142" , 0x118008095f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16143" , 0x118008095f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16144" , 0x118008095f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16145" , 0x118008095f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16146" , 0x118008095f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16147" , 0x118008095f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16148" , 0x118008095f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16149" , 0x118008095f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16150" , 0x118008095f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16151" , 0x118008095f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16152" , 0x118008095f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16153" , 0x118008095f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16154" , 0x118008095f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16155" , 0x118008095f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16156" , 0x118008095f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16157" , 0x118008095f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16158" , 0x118008095f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16159" , 0x118008095f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16160" , 0x118008095f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16161" , 0x118008095f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16162" , 0x118008095f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16163" , 0x118008095f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16164" , 0x118008095f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16165" , 0x118008095f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16166" , 0x118008095f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16167" , 0x118008095f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16168" , 0x118008095f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16169" , 0x118008095f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16170" , 0x118008095f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16171" , 0x118008095f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16172" , 0x118008095f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16173" , 0x118008095f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16174" , 0x118008095f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16175" , 0x118008095f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16176" , 0x118008095f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16177" , 0x118008095f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16178" , 0x118008095f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16179" , 0x118008095f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16180" , 0x118008095f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16181" , 0x118008095f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16182" , 0x118008095f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16183" , 0x118008095f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16184" , 0x118008095f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16185" , 0x118008095f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16186" , 0x118008095f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16187" , 0x118008095f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16188" , 0x118008095f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16189" , 0x118008095f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16190" , 0x118008095f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16191" , 0x118008095f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16192" , 0x118008095fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16193" , 0x118008095fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16194" , 0x118008095fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16195" , 0x118008095fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16196" , 0x118008095fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16197" , 0x118008095fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16198" , 0x118008095fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16199" , 0x118008095fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16200" , 0x118008095fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16201" , 0x118008095fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16202" , 0x118008095fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16203" , 0x118008095fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16204" , 0x118008095fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16205" , 0x118008095fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16206" , 0x118008095fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16207" , 0x118008095fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16208" , 0x118008095fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16209" , 0x118008095fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16210" , 0x118008095fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16211" , 0x118008095fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16212" , 0x118008095faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16213" , 0x118008095faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16214" , 0x118008095fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16215" , 0x118008095fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16216" , 0x118008095fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16217" , 0x118008095fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16218" , 0x118008095fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16219" , 0x118008095fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16220" , 0x118008095fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16221" , 0x118008095fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16222" , 0x118008095faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16223" , 0x118008095faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16224" , 0x118008095fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16225" , 0x118008095fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16226" , 0x118008095fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16227" , 0x118008095fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16228" , 0x118008095fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16229" , 0x118008095fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16230" , 0x118008095fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16231" , 0x118008095fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16232" , 0x118008095fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16233" , 0x118008095fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16234" , 0x118008095fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16235" , 0x118008095fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16236" , 0x118008095fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16237" , 0x118008095fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16238" , 0x118008095fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16239" , 0x118008095fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16240" , 0x118008095fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16241" , 0x118008095fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16242" , 0x118008095fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16243" , 0x118008095fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16244" , 0x118008095fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16245" , 0x118008095fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16246" , 0x118008095fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16247" , 0x118008095fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16248" , 0x118008095fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16249" , 0x118008095fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16250" , 0x118008095fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16251" , 0x118008095fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16252" , 0x118008095fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16253" , 0x118008095fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16254" , 0x118008095fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16255" , 0x118008095fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16256" , 0x118008095fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16257" , 0x118008095fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16258" , 0x118008095fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16259" , 0x118008095fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16260" , 0x118008095fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16261" , 0x118008095fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16262" , 0x118008095fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16263" , 0x118008095fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16264" , 0x118008095fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16265" , 0x118008095fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16266" , 0x118008095fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16267" , 0x118008095fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16268" , 0x118008095fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16269" , 0x118008095fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16270" , 0x118008095fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16271" , 0x118008095fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16272" , 0x118008095fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16273" , 0x118008095fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16274" , 0x118008095fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16275" , 0x118008095fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16276" , 0x118008095fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16277" , 0x118008095fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16278" , 0x118008095fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16279" , 0x118008095fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16280" , 0x118008095fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16281" , 0x118008095fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16282" , 0x118008095fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16283" , 0x118008095fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16284" , 0x118008095fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16285" , 0x118008095fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16286" , 0x118008095fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16287" , 0x118008095fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16288" , 0x118008095fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16289" , 0x118008095fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16290" , 0x118008095fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16291" , 0x118008095fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16292" , 0x118008095fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16293" , 0x118008095fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16294" , 0x118008095fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16295" , 0x118008095fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16296" , 0x118008095fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16297" , 0x118008095fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16298" , 0x118008095fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16299" , 0x118008095fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16300" , 0x118008095fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16301" , 0x118008095fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16302" , 0x118008095fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16303" , 0x118008095fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16304" , 0x118008095fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16305" , 0x118008095fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16306" , 0x118008095fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16307" , 0x118008095fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16308" , 0x118008095fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16309" , 0x118008095fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16310" , 0x118008095fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16311" , 0x118008095fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16312" , 0x118008095fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16313" , 0x118008095fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16314" , 0x118008095fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16315" , 0x118008095fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16316" , 0x118008095fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16317" , 0x118008095fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16318" , 0x118008095fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16319" , 0x118008095fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16320" , 0x118008095fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16321" , 0x118008095fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16322" , 0x118008095fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16323" , 0x118008095fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16324" , 0x118008095fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16325" , 0x118008095fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16326" , 0x118008095fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16327" , 0x118008095fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16328" , 0x118008095fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16329" , 0x118008095fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16330" , 0x118008095fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16331" , 0x118008095fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16332" , 0x118008095fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16333" , 0x118008095fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16334" , 0x118008095fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16335" , 0x118008095fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16336" , 0x118008095fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16337" , 0x118008095fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16338" , 0x118008095fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16339" , 0x118008095fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16340" , 0x118008095fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16341" , 0x118008095fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16342" , 0x118008095feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16343" , 0x118008095feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16344" , 0x118008095fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16345" , 0x118008095fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16346" , 0x118008095fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16347" , 0x118008095fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16348" , 0x118008095fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16349" , 0x118008095fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16350" , 0x118008095fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16351" , 0x118008095fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16352" , 0x118008095ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16353" , 0x118008095ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16354" , 0x118008095ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16355" , 0x118008095ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16356" , 0x118008095ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16357" , 0x118008095ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16358" , 0x118008095ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16359" , 0x118008095ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16360" , 0x118008095ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16361" , 0x118008095ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16362" , 0x118008095ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16363" , 0x118008095ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16364" , 0x118008095ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16365" , 0x118008095ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16366" , 0x118008095ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16367" , 0x118008095ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16368" , 0x118008095ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16369" , 0x118008095ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16370" , 0x118008095ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16371" , 0x118008095ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16372" , 0x118008095ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16373" , 0x118008095ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16374" , 0x118008095ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16375" , 0x118008095ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16376" , 0x118008095ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16377" , 0x118008095ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16378" , 0x118008095ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16379" , 0x118008095ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16380" , 0x118008095ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16381" , 0x118008095ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16382" , 0x118008095fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16383" , 0x118008095fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_CTL" , 0x1180080800000ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"L2C_DUT_MAP0" , 0x1180080e00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1" , 0x1180080e00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP2" , 0x1180080e00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP3" , 0x1180080e00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP4" , 0x1180080e00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP5" , 0x1180080e00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP6" , 0x1180080e00030ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP7" , 0x1180080e00038ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP8" , 0x1180080e00040ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP9" , 0x1180080e00048ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP10" , 0x1180080e00050ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP11" , 0x1180080e00058ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP12" , 0x1180080e00060ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP13" , 0x1180080e00068ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP14" , 0x1180080e00070ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP15" , 0x1180080e00078ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP16" , 0x1180080e00080ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP17" , 0x1180080e00088ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP18" , 0x1180080e00090ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP19" , 0x1180080e00098ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP20" , 0x1180080e000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP21" , 0x1180080e000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP22" , 0x1180080e000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP23" , 0x1180080e000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP24" , 0x1180080e000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP25" , 0x1180080e000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP26" , 0x1180080e000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP27" , 0x1180080e000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP28" , 0x1180080e000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP29" , 0x1180080e000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP30" , 0x1180080e000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP31" , 0x1180080e000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP32" , 0x1180080e00100ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP33" , 0x1180080e00108ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP34" , 0x1180080e00110ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP35" , 0x1180080e00118ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP36" , 0x1180080e00120ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP37" , 0x1180080e00128ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP38" , 0x1180080e00130ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP39" , 0x1180080e00138ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP40" , 0x1180080e00140ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP41" , 0x1180080e00148ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP42" , 0x1180080e00150ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP43" , 0x1180080e00158ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP44" , 0x1180080e00160ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP45" , 0x1180080e00168ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP46" , 0x1180080e00170ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP47" , 0x1180080e00178ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP48" , 0x1180080e00180ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP49" , 0x1180080e00188ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP50" , 0x1180080e00190ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP51" , 0x1180080e00198ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP52" , 0x1180080e001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP53" , 0x1180080e001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP54" , 0x1180080e001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP55" , 0x1180080e001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP56" , 0x1180080e001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP57" , 0x1180080e001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP58" , 0x1180080e001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP59" , 0x1180080e001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP60" , 0x1180080e001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP61" , 0x1180080e001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP62" , 0x1180080e001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP63" , 0x1180080e001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP64" , 0x1180080e00200ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP65" , 0x1180080e00208ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP66" , 0x1180080e00210ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP67" , 0x1180080e00218ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP68" , 0x1180080e00220ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP69" , 0x1180080e00228ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP70" , 0x1180080e00230ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP71" , 0x1180080e00238ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP72" , 0x1180080e00240ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP73" , 0x1180080e00248ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP74" , 0x1180080e00250ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP75" , 0x1180080e00258ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP76" , 0x1180080e00260ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP77" , 0x1180080e00268ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP78" , 0x1180080e00270ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP79" , 0x1180080e00278ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP80" , 0x1180080e00280ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP81" , 0x1180080e00288ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP82" , 0x1180080e00290ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP83" , 0x1180080e00298ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP84" , 0x1180080e002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP85" , 0x1180080e002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP86" , 0x1180080e002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP87" , 0x1180080e002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP88" , 0x1180080e002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP89" , 0x1180080e002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP90" , 0x1180080e002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP91" , 0x1180080e002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP92" , 0x1180080e002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP93" , 0x1180080e002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP94" , 0x1180080e002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP95" , 0x1180080e002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP96" , 0x1180080e00300ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP97" , 0x1180080e00308ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP98" , 0x1180080e00310ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP99" , 0x1180080e00318ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP100" , 0x1180080e00320ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP101" , 0x1180080e00328ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP102" , 0x1180080e00330ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP103" , 0x1180080e00338ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP104" , 0x1180080e00340ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP105" , 0x1180080e00348ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP106" , 0x1180080e00350ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP107" , 0x1180080e00358ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP108" , 0x1180080e00360ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP109" , 0x1180080e00368ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP110" , 0x1180080e00370ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP111" , 0x1180080e00378ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP112" , 0x1180080e00380ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP113" , 0x1180080e00388ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP114" , 0x1180080e00390ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP115" , 0x1180080e00398ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP116" , 0x1180080e003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP117" , 0x1180080e003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP118" , 0x1180080e003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP119" , 0x1180080e003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP120" , 0x1180080e003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP121" , 0x1180080e003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP122" , 0x1180080e003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP123" , 0x1180080e003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP124" , 0x1180080e003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP125" , 0x1180080e003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP126" , 0x1180080e003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP127" , 0x1180080e003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP128" , 0x1180080e00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP129" , 0x1180080e00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP130" , 0x1180080e00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP131" , 0x1180080e00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP132" , 0x1180080e00420ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP133" , 0x1180080e00428ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP134" , 0x1180080e00430ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP135" , 0x1180080e00438ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP136" , 0x1180080e00440ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP137" , 0x1180080e00448ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP138" , 0x1180080e00450ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP139" , 0x1180080e00458ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP140" , 0x1180080e00460ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP141" , 0x1180080e00468ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP142" , 0x1180080e00470ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP143" , 0x1180080e00478ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP144" , 0x1180080e00480ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP145" , 0x1180080e00488ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP146" , 0x1180080e00490ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP147" , 0x1180080e00498ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP148" , 0x1180080e004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP149" , 0x1180080e004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP150" , 0x1180080e004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP151" , 0x1180080e004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP152" , 0x1180080e004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP153" , 0x1180080e004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP154" , 0x1180080e004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP155" , 0x1180080e004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP156" , 0x1180080e004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP157" , 0x1180080e004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP158" , 0x1180080e004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP159" , 0x1180080e004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP160" , 0x1180080e00500ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP161" , 0x1180080e00508ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP162" , 0x1180080e00510ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP163" , 0x1180080e00518ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP164" , 0x1180080e00520ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP165" , 0x1180080e00528ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP166" , 0x1180080e00530ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP167" , 0x1180080e00538ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP168" , 0x1180080e00540ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP169" , 0x1180080e00548ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP170" , 0x1180080e00550ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP171" , 0x1180080e00558ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP172" , 0x1180080e00560ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP173" , 0x1180080e00568ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP174" , 0x1180080e00570ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP175" , 0x1180080e00578ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP176" , 0x1180080e00580ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP177" , 0x1180080e00588ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP178" , 0x1180080e00590ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP179" , 0x1180080e00598ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP180" , 0x1180080e005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP181" , 0x1180080e005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP182" , 0x1180080e005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP183" , 0x1180080e005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP184" , 0x1180080e005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP185" , 0x1180080e005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP186" , 0x1180080e005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP187" , 0x1180080e005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP188" , 0x1180080e005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP189" , 0x1180080e005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP190" , 0x1180080e005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP191" , 0x1180080e005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP192" , 0x1180080e00600ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP193" , 0x1180080e00608ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP194" , 0x1180080e00610ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP195" , 0x1180080e00618ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP196" , 0x1180080e00620ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP197" , 0x1180080e00628ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP198" , 0x1180080e00630ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP199" , 0x1180080e00638ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP200" , 0x1180080e00640ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP201" , 0x1180080e00648ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP202" , 0x1180080e00650ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP203" , 0x1180080e00658ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP204" , 0x1180080e00660ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP205" , 0x1180080e00668ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP206" , 0x1180080e00670ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP207" , 0x1180080e00678ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP208" , 0x1180080e00680ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP209" , 0x1180080e00688ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP210" , 0x1180080e00690ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP211" , 0x1180080e00698ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP212" , 0x1180080e006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP213" , 0x1180080e006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP214" , 0x1180080e006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP215" , 0x1180080e006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP216" , 0x1180080e006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP217" , 0x1180080e006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP218" , 0x1180080e006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP219" , 0x1180080e006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP220" , 0x1180080e006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP221" , 0x1180080e006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP222" , 0x1180080e006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP223" , 0x1180080e006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP224" , 0x1180080e00700ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP225" , 0x1180080e00708ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP226" , 0x1180080e00710ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP227" , 0x1180080e00718ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP228" , 0x1180080e00720ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP229" , 0x1180080e00728ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP230" , 0x1180080e00730ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP231" , 0x1180080e00738ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP232" , 0x1180080e00740ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP233" , 0x1180080e00748ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP234" , 0x1180080e00750ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP235" , 0x1180080e00758ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP236" , 0x1180080e00760ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP237" , 0x1180080e00768ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP238" , 0x1180080e00770ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP239" , 0x1180080e00778ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP240" , 0x1180080e00780ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP241" , 0x1180080e00788ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP242" , 0x1180080e00790ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP243" , 0x1180080e00798ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP244" , 0x1180080e007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP245" , 0x1180080e007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP246" , 0x1180080e007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP247" , 0x1180080e007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP248" , 0x1180080e007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP249" , 0x1180080e007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP250" , 0x1180080e007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP251" , 0x1180080e007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP252" , 0x1180080e007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP253" , 0x1180080e007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP254" , 0x1180080e007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP255" , 0x1180080e007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP256" , 0x1180080e00800ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP257" , 0x1180080e00808ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP258" , 0x1180080e00810ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP259" , 0x1180080e00818ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP260" , 0x1180080e00820ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP261" , 0x1180080e00828ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP262" , 0x1180080e00830ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP263" , 0x1180080e00838ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP264" , 0x1180080e00840ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP265" , 0x1180080e00848ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP266" , 0x1180080e00850ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP267" , 0x1180080e00858ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP268" , 0x1180080e00860ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP269" , 0x1180080e00868ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP270" , 0x1180080e00870ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP271" , 0x1180080e00878ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP272" , 0x1180080e00880ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP273" , 0x1180080e00888ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP274" , 0x1180080e00890ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP275" , 0x1180080e00898ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP276" , 0x1180080e008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP277" , 0x1180080e008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP278" , 0x1180080e008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP279" , 0x1180080e008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP280" , 0x1180080e008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP281" , 0x1180080e008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP282" , 0x1180080e008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP283" , 0x1180080e008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP284" , 0x1180080e008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP285" , 0x1180080e008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP286" , 0x1180080e008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP287" , 0x1180080e008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP288" , 0x1180080e00900ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP289" , 0x1180080e00908ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP290" , 0x1180080e00910ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP291" , 0x1180080e00918ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP292" , 0x1180080e00920ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP293" , 0x1180080e00928ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP294" , 0x1180080e00930ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP295" , 0x1180080e00938ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP296" , 0x1180080e00940ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP297" , 0x1180080e00948ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP298" , 0x1180080e00950ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP299" , 0x1180080e00958ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP300" , 0x1180080e00960ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP301" , 0x1180080e00968ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP302" , 0x1180080e00970ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP303" , 0x1180080e00978ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP304" , 0x1180080e00980ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP305" , 0x1180080e00988ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP306" , 0x1180080e00990ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP307" , 0x1180080e00998ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP308" , 0x1180080e009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP309" , 0x1180080e009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP310" , 0x1180080e009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP311" , 0x1180080e009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP312" , 0x1180080e009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP313" , 0x1180080e009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP314" , 0x1180080e009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP315" , 0x1180080e009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP316" , 0x1180080e009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP317" , 0x1180080e009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP318" , 0x1180080e009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP319" , 0x1180080e009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP320" , 0x1180080e00a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP321" , 0x1180080e00a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP322" , 0x1180080e00a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP323" , 0x1180080e00a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP324" , 0x1180080e00a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP325" , 0x1180080e00a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP326" , 0x1180080e00a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP327" , 0x1180080e00a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP328" , 0x1180080e00a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP329" , 0x1180080e00a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP330" , 0x1180080e00a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP331" , 0x1180080e00a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP332" , 0x1180080e00a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP333" , 0x1180080e00a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP334" , 0x1180080e00a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP335" , 0x1180080e00a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP336" , 0x1180080e00a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP337" , 0x1180080e00a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP338" , 0x1180080e00a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP339" , 0x1180080e00a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP340" , 0x1180080e00aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP341" , 0x1180080e00aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP342" , 0x1180080e00ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP343" , 0x1180080e00ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP344" , 0x1180080e00ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP345" , 0x1180080e00ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP346" , 0x1180080e00ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP347" , 0x1180080e00ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP348" , 0x1180080e00ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP349" , 0x1180080e00ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP350" , 0x1180080e00af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP351" , 0x1180080e00af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP352" , 0x1180080e00b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP353" , 0x1180080e00b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP354" , 0x1180080e00b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP355" , 0x1180080e00b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP356" , 0x1180080e00b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP357" , 0x1180080e00b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP358" , 0x1180080e00b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP359" , 0x1180080e00b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP360" , 0x1180080e00b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP361" , 0x1180080e00b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP362" , 0x1180080e00b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP363" , 0x1180080e00b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP364" , 0x1180080e00b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP365" , 0x1180080e00b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP366" , 0x1180080e00b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP367" , 0x1180080e00b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP368" , 0x1180080e00b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP369" , 0x1180080e00b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP370" , 0x1180080e00b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP371" , 0x1180080e00b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP372" , 0x1180080e00ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP373" , 0x1180080e00ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP374" , 0x1180080e00bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP375" , 0x1180080e00bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP376" , 0x1180080e00bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP377" , 0x1180080e00bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP378" , 0x1180080e00bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP379" , 0x1180080e00bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP380" , 0x1180080e00be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP381" , 0x1180080e00be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP382" , 0x1180080e00bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP383" , 0x1180080e00bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP384" , 0x1180080e00c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP385" , 0x1180080e00c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP386" , 0x1180080e00c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP387" , 0x1180080e00c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP388" , 0x1180080e00c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP389" , 0x1180080e00c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP390" , 0x1180080e00c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP391" , 0x1180080e00c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP392" , 0x1180080e00c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP393" , 0x1180080e00c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP394" , 0x1180080e00c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP395" , 0x1180080e00c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP396" , 0x1180080e00c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP397" , 0x1180080e00c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP398" , 0x1180080e00c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP399" , 0x1180080e00c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP400" , 0x1180080e00c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP401" , 0x1180080e00c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP402" , 0x1180080e00c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP403" , 0x1180080e00c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP404" , 0x1180080e00ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP405" , 0x1180080e00ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP406" , 0x1180080e00cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP407" , 0x1180080e00cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP408" , 0x1180080e00cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP409" , 0x1180080e00cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP410" , 0x1180080e00cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP411" , 0x1180080e00cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP412" , 0x1180080e00ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP413" , 0x1180080e00ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP414" , 0x1180080e00cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP415" , 0x1180080e00cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP416" , 0x1180080e00d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP417" , 0x1180080e00d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP418" , 0x1180080e00d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP419" , 0x1180080e00d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP420" , 0x1180080e00d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP421" , 0x1180080e00d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP422" , 0x1180080e00d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP423" , 0x1180080e00d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP424" , 0x1180080e00d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP425" , 0x1180080e00d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP426" , 0x1180080e00d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP427" , 0x1180080e00d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP428" , 0x1180080e00d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP429" , 0x1180080e00d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP430" , 0x1180080e00d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP431" , 0x1180080e00d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP432" , 0x1180080e00d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP433" , 0x1180080e00d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP434" , 0x1180080e00d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP435" , 0x1180080e00d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP436" , 0x1180080e00da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP437" , 0x1180080e00da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP438" , 0x1180080e00db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP439" , 0x1180080e00db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP440" , 0x1180080e00dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP441" , 0x1180080e00dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP442" , 0x1180080e00dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP443" , 0x1180080e00dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP444" , 0x1180080e00de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP445" , 0x1180080e00de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP446" , 0x1180080e00df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP447" , 0x1180080e00df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP448" , 0x1180080e00e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP449" , 0x1180080e00e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP450" , 0x1180080e00e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP451" , 0x1180080e00e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP452" , 0x1180080e00e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP453" , 0x1180080e00e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP454" , 0x1180080e00e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP455" , 0x1180080e00e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP456" , 0x1180080e00e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP457" , 0x1180080e00e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP458" , 0x1180080e00e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP459" , 0x1180080e00e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP460" , 0x1180080e00e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP461" , 0x1180080e00e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP462" , 0x1180080e00e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP463" , 0x1180080e00e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP464" , 0x1180080e00e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP465" , 0x1180080e00e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP466" , 0x1180080e00e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP467" , 0x1180080e00e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP468" , 0x1180080e00ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP469" , 0x1180080e00ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP470" , 0x1180080e00eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP471" , 0x1180080e00eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP472" , 0x1180080e00ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP473" , 0x1180080e00ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP474" , 0x1180080e00ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP475" , 0x1180080e00ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP476" , 0x1180080e00ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP477" , 0x1180080e00ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP478" , 0x1180080e00ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP479" , 0x1180080e00ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP480" , 0x1180080e00f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP481" , 0x1180080e00f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP482" , 0x1180080e00f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP483" , 0x1180080e00f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP484" , 0x1180080e00f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP485" , 0x1180080e00f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP486" , 0x1180080e00f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP487" , 0x1180080e00f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP488" , 0x1180080e00f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP489" , 0x1180080e00f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP490" , 0x1180080e00f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP491" , 0x1180080e00f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP492" , 0x1180080e00f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP493" , 0x1180080e00f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP494" , 0x1180080e00f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP495" , 0x1180080e00f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP496" , 0x1180080e00f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP497" , 0x1180080e00f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP498" , 0x1180080e00f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP499" , 0x1180080e00f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP500" , 0x1180080e00fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP501" , 0x1180080e00fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP502" , 0x1180080e00fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP503" , 0x1180080e00fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP504" , 0x1180080e00fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP505" , 0x1180080e00fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP506" , 0x1180080e00fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP507" , 0x1180080e00fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP508" , 0x1180080e00fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP509" , 0x1180080e00fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP510" , 0x1180080e00ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP511" , 0x1180080e00ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP512" , 0x1180080e01000ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP513" , 0x1180080e01008ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP514" , 0x1180080e01010ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP515" , 0x1180080e01018ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP516" , 0x1180080e01020ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP517" , 0x1180080e01028ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP518" , 0x1180080e01030ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP519" , 0x1180080e01038ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP520" , 0x1180080e01040ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP521" , 0x1180080e01048ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP522" , 0x1180080e01050ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP523" , 0x1180080e01058ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP524" , 0x1180080e01060ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP525" , 0x1180080e01068ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP526" , 0x1180080e01070ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP527" , 0x1180080e01078ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP528" , 0x1180080e01080ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP529" , 0x1180080e01088ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP530" , 0x1180080e01090ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP531" , 0x1180080e01098ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP532" , 0x1180080e010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP533" , 0x1180080e010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP534" , 0x1180080e010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP535" , 0x1180080e010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP536" , 0x1180080e010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP537" , 0x1180080e010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP538" , 0x1180080e010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP539" , 0x1180080e010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP540" , 0x1180080e010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP541" , 0x1180080e010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP542" , 0x1180080e010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP543" , 0x1180080e010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP544" , 0x1180080e01100ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP545" , 0x1180080e01108ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP546" , 0x1180080e01110ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP547" , 0x1180080e01118ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP548" , 0x1180080e01120ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP549" , 0x1180080e01128ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP550" , 0x1180080e01130ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP551" , 0x1180080e01138ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP552" , 0x1180080e01140ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP553" , 0x1180080e01148ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP554" , 0x1180080e01150ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP555" , 0x1180080e01158ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP556" , 0x1180080e01160ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP557" , 0x1180080e01168ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP558" , 0x1180080e01170ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP559" , 0x1180080e01178ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP560" , 0x1180080e01180ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP561" , 0x1180080e01188ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP562" , 0x1180080e01190ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP563" , 0x1180080e01198ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP564" , 0x1180080e011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP565" , 0x1180080e011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP566" , 0x1180080e011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP567" , 0x1180080e011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP568" , 0x1180080e011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP569" , 0x1180080e011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP570" , 0x1180080e011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP571" , 0x1180080e011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP572" , 0x1180080e011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP573" , 0x1180080e011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP574" , 0x1180080e011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP575" , 0x1180080e011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP576" , 0x1180080e01200ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP577" , 0x1180080e01208ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP578" , 0x1180080e01210ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP579" , 0x1180080e01218ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP580" , 0x1180080e01220ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP581" , 0x1180080e01228ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP582" , 0x1180080e01230ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP583" , 0x1180080e01238ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP584" , 0x1180080e01240ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP585" , 0x1180080e01248ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP586" , 0x1180080e01250ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP587" , 0x1180080e01258ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP588" , 0x1180080e01260ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP589" , 0x1180080e01268ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP590" , 0x1180080e01270ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP591" , 0x1180080e01278ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP592" , 0x1180080e01280ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP593" , 0x1180080e01288ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP594" , 0x1180080e01290ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP595" , 0x1180080e01298ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP596" , 0x1180080e012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP597" , 0x1180080e012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP598" , 0x1180080e012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP599" , 0x1180080e012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP600" , 0x1180080e012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP601" , 0x1180080e012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP602" , 0x1180080e012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP603" , 0x1180080e012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP604" , 0x1180080e012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP605" , 0x1180080e012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP606" , 0x1180080e012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP607" , 0x1180080e012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP608" , 0x1180080e01300ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP609" , 0x1180080e01308ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP610" , 0x1180080e01310ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP611" , 0x1180080e01318ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP612" , 0x1180080e01320ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP613" , 0x1180080e01328ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP614" , 0x1180080e01330ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP615" , 0x1180080e01338ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP616" , 0x1180080e01340ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP617" , 0x1180080e01348ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP618" , 0x1180080e01350ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP619" , 0x1180080e01358ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP620" , 0x1180080e01360ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP621" , 0x1180080e01368ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP622" , 0x1180080e01370ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP623" , 0x1180080e01378ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP624" , 0x1180080e01380ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP625" , 0x1180080e01388ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP626" , 0x1180080e01390ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP627" , 0x1180080e01398ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP628" , 0x1180080e013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP629" , 0x1180080e013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP630" , 0x1180080e013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP631" , 0x1180080e013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP632" , 0x1180080e013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP633" , 0x1180080e013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP634" , 0x1180080e013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP635" , 0x1180080e013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP636" , 0x1180080e013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP637" , 0x1180080e013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP638" , 0x1180080e013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP639" , 0x1180080e013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP640" , 0x1180080e01400ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP641" , 0x1180080e01408ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP642" , 0x1180080e01410ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP643" , 0x1180080e01418ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP644" , 0x1180080e01420ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP645" , 0x1180080e01428ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP646" , 0x1180080e01430ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP647" , 0x1180080e01438ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP648" , 0x1180080e01440ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP649" , 0x1180080e01448ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP650" , 0x1180080e01450ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP651" , 0x1180080e01458ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP652" , 0x1180080e01460ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP653" , 0x1180080e01468ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP654" , 0x1180080e01470ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP655" , 0x1180080e01478ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP656" , 0x1180080e01480ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP657" , 0x1180080e01488ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP658" , 0x1180080e01490ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP659" , 0x1180080e01498ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP660" , 0x1180080e014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP661" , 0x1180080e014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP662" , 0x1180080e014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP663" , 0x1180080e014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP664" , 0x1180080e014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP665" , 0x1180080e014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP666" , 0x1180080e014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP667" , 0x1180080e014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP668" , 0x1180080e014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP669" , 0x1180080e014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP670" , 0x1180080e014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP671" , 0x1180080e014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP672" , 0x1180080e01500ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP673" , 0x1180080e01508ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP674" , 0x1180080e01510ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP675" , 0x1180080e01518ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP676" , 0x1180080e01520ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP677" , 0x1180080e01528ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP678" , 0x1180080e01530ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP679" , 0x1180080e01538ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP680" , 0x1180080e01540ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP681" , 0x1180080e01548ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP682" , 0x1180080e01550ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP683" , 0x1180080e01558ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP684" , 0x1180080e01560ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP685" , 0x1180080e01568ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP686" , 0x1180080e01570ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP687" , 0x1180080e01578ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP688" , 0x1180080e01580ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP689" , 0x1180080e01588ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP690" , 0x1180080e01590ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP691" , 0x1180080e01598ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP692" , 0x1180080e015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP693" , 0x1180080e015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP694" , 0x1180080e015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP695" , 0x1180080e015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP696" , 0x1180080e015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP697" , 0x1180080e015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP698" , 0x1180080e015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP699" , 0x1180080e015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP700" , 0x1180080e015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP701" , 0x1180080e015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP702" , 0x1180080e015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP703" , 0x1180080e015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP704" , 0x1180080e01600ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP705" , 0x1180080e01608ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP706" , 0x1180080e01610ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP707" , 0x1180080e01618ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP708" , 0x1180080e01620ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP709" , 0x1180080e01628ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP710" , 0x1180080e01630ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP711" , 0x1180080e01638ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP712" , 0x1180080e01640ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP713" , 0x1180080e01648ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP714" , 0x1180080e01650ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP715" , 0x1180080e01658ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP716" , 0x1180080e01660ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP717" , 0x1180080e01668ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP718" , 0x1180080e01670ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP719" , 0x1180080e01678ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP720" , 0x1180080e01680ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP721" , 0x1180080e01688ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP722" , 0x1180080e01690ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP723" , 0x1180080e01698ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP724" , 0x1180080e016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP725" , 0x1180080e016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP726" , 0x1180080e016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP727" , 0x1180080e016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP728" , 0x1180080e016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP729" , 0x1180080e016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP730" , 0x1180080e016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP731" , 0x1180080e016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP732" , 0x1180080e016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP733" , 0x1180080e016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP734" , 0x1180080e016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP735" , 0x1180080e016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP736" , 0x1180080e01700ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP737" , 0x1180080e01708ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP738" , 0x1180080e01710ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP739" , 0x1180080e01718ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP740" , 0x1180080e01720ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP741" , 0x1180080e01728ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP742" , 0x1180080e01730ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP743" , 0x1180080e01738ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP744" , 0x1180080e01740ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP745" , 0x1180080e01748ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP746" , 0x1180080e01750ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP747" , 0x1180080e01758ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP748" , 0x1180080e01760ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP749" , 0x1180080e01768ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP750" , 0x1180080e01770ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP751" , 0x1180080e01778ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP752" , 0x1180080e01780ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP753" , 0x1180080e01788ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP754" , 0x1180080e01790ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP755" , 0x1180080e01798ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP756" , 0x1180080e017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP757" , 0x1180080e017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP758" , 0x1180080e017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP759" , 0x1180080e017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP760" , 0x1180080e017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP761" , 0x1180080e017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP762" , 0x1180080e017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP763" , 0x1180080e017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP764" , 0x1180080e017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP765" , 0x1180080e017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP766" , 0x1180080e017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP767" , 0x1180080e017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP768" , 0x1180080e01800ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP769" , 0x1180080e01808ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP770" , 0x1180080e01810ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP771" , 0x1180080e01818ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP772" , 0x1180080e01820ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP773" , 0x1180080e01828ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP774" , 0x1180080e01830ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP775" , 0x1180080e01838ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP776" , 0x1180080e01840ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP777" , 0x1180080e01848ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP778" , 0x1180080e01850ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP779" , 0x1180080e01858ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP780" , 0x1180080e01860ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP781" , 0x1180080e01868ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP782" , 0x1180080e01870ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP783" , 0x1180080e01878ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP784" , 0x1180080e01880ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP785" , 0x1180080e01888ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP786" , 0x1180080e01890ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP787" , 0x1180080e01898ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP788" , 0x1180080e018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP789" , 0x1180080e018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP790" , 0x1180080e018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP791" , 0x1180080e018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP792" , 0x1180080e018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP793" , 0x1180080e018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP794" , 0x1180080e018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP795" , 0x1180080e018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP796" , 0x1180080e018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP797" , 0x1180080e018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP798" , 0x1180080e018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP799" , 0x1180080e018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP800" , 0x1180080e01900ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP801" , 0x1180080e01908ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP802" , 0x1180080e01910ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP803" , 0x1180080e01918ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP804" , 0x1180080e01920ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP805" , 0x1180080e01928ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP806" , 0x1180080e01930ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP807" , 0x1180080e01938ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP808" , 0x1180080e01940ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP809" , 0x1180080e01948ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP810" , 0x1180080e01950ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP811" , 0x1180080e01958ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP812" , 0x1180080e01960ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP813" , 0x1180080e01968ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP814" , 0x1180080e01970ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP815" , 0x1180080e01978ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP816" , 0x1180080e01980ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP817" , 0x1180080e01988ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP818" , 0x1180080e01990ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP819" , 0x1180080e01998ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP820" , 0x1180080e019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP821" , 0x1180080e019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP822" , 0x1180080e019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP823" , 0x1180080e019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP824" , 0x1180080e019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP825" , 0x1180080e019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP826" , 0x1180080e019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP827" , 0x1180080e019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP828" , 0x1180080e019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP829" , 0x1180080e019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP830" , 0x1180080e019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP831" , 0x1180080e019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP832" , 0x1180080e01a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP833" , 0x1180080e01a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP834" , 0x1180080e01a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP835" , 0x1180080e01a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP836" , 0x1180080e01a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP837" , 0x1180080e01a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP838" , 0x1180080e01a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP839" , 0x1180080e01a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP840" , 0x1180080e01a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP841" , 0x1180080e01a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP842" , 0x1180080e01a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP843" , 0x1180080e01a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP844" , 0x1180080e01a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP845" , 0x1180080e01a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP846" , 0x1180080e01a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP847" , 0x1180080e01a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP848" , 0x1180080e01a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP849" , 0x1180080e01a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP850" , 0x1180080e01a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP851" , 0x1180080e01a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP852" , 0x1180080e01aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP853" , 0x1180080e01aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP854" , 0x1180080e01ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP855" , 0x1180080e01ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP856" , 0x1180080e01ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP857" , 0x1180080e01ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP858" , 0x1180080e01ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP859" , 0x1180080e01ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP860" , 0x1180080e01ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP861" , 0x1180080e01ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP862" , 0x1180080e01af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP863" , 0x1180080e01af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP864" , 0x1180080e01b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP865" , 0x1180080e01b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP866" , 0x1180080e01b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP867" , 0x1180080e01b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP868" , 0x1180080e01b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP869" , 0x1180080e01b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP870" , 0x1180080e01b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP871" , 0x1180080e01b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP872" , 0x1180080e01b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP873" , 0x1180080e01b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP874" , 0x1180080e01b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP875" , 0x1180080e01b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP876" , 0x1180080e01b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP877" , 0x1180080e01b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP878" , 0x1180080e01b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP879" , 0x1180080e01b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP880" , 0x1180080e01b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP881" , 0x1180080e01b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP882" , 0x1180080e01b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP883" , 0x1180080e01b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP884" , 0x1180080e01ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP885" , 0x1180080e01ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP886" , 0x1180080e01bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP887" , 0x1180080e01bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP888" , 0x1180080e01bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP889" , 0x1180080e01bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP890" , 0x1180080e01bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP891" , 0x1180080e01bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP892" , 0x1180080e01be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP893" , 0x1180080e01be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP894" , 0x1180080e01bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP895" , 0x1180080e01bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP896" , 0x1180080e01c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP897" , 0x1180080e01c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP898" , 0x1180080e01c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP899" , 0x1180080e01c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP900" , 0x1180080e01c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP901" , 0x1180080e01c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP902" , 0x1180080e01c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP903" , 0x1180080e01c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP904" , 0x1180080e01c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP905" , 0x1180080e01c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP906" , 0x1180080e01c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP907" , 0x1180080e01c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP908" , 0x1180080e01c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP909" , 0x1180080e01c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP910" , 0x1180080e01c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP911" , 0x1180080e01c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP912" , 0x1180080e01c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP913" , 0x1180080e01c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP914" , 0x1180080e01c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP915" , 0x1180080e01c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP916" , 0x1180080e01ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP917" , 0x1180080e01ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP918" , 0x1180080e01cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP919" , 0x1180080e01cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP920" , 0x1180080e01cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP921" , 0x1180080e01cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP922" , 0x1180080e01cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP923" , 0x1180080e01cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP924" , 0x1180080e01ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP925" , 0x1180080e01ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP926" , 0x1180080e01cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP927" , 0x1180080e01cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP928" , 0x1180080e01d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP929" , 0x1180080e01d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP930" , 0x1180080e01d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP931" , 0x1180080e01d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP932" , 0x1180080e01d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP933" , 0x1180080e01d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP934" , 0x1180080e01d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP935" , 0x1180080e01d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP936" , 0x1180080e01d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP937" , 0x1180080e01d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP938" , 0x1180080e01d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP939" , 0x1180080e01d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP940" , 0x1180080e01d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP941" , 0x1180080e01d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP942" , 0x1180080e01d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP943" , 0x1180080e01d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP944" , 0x1180080e01d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP945" , 0x1180080e01d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP946" , 0x1180080e01d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP947" , 0x1180080e01d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP948" , 0x1180080e01da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP949" , 0x1180080e01da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP950" , 0x1180080e01db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP951" , 0x1180080e01db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP952" , 0x1180080e01dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP953" , 0x1180080e01dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP954" , 0x1180080e01dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP955" , 0x1180080e01dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP956" , 0x1180080e01de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP957" , 0x1180080e01de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP958" , 0x1180080e01df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP959" , 0x1180080e01df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP960" , 0x1180080e01e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP961" , 0x1180080e01e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP962" , 0x1180080e01e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP963" , 0x1180080e01e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP964" , 0x1180080e01e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP965" , 0x1180080e01e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP966" , 0x1180080e01e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP967" , 0x1180080e01e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP968" , 0x1180080e01e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP969" , 0x1180080e01e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP970" , 0x1180080e01e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP971" , 0x1180080e01e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP972" , 0x1180080e01e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP973" , 0x1180080e01e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP974" , 0x1180080e01e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP975" , 0x1180080e01e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP976" , 0x1180080e01e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP977" , 0x1180080e01e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP978" , 0x1180080e01e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP979" , 0x1180080e01e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP980" , 0x1180080e01ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP981" , 0x1180080e01ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP982" , 0x1180080e01eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP983" , 0x1180080e01eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP984" , 0x1180080e01ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP985" , 0x1180080e01ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP986" , 0x1180080e01ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP987" , 0x1180080e01ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP988" , 0x1180080e01ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP989" , 0x1180080e01ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP990" , 0x1180080e01ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP991" , 0x1180080e01ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP992" , 0x1180080e01f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP993" , 0x1180080e01f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP994" , 0x1180080e01f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP995" , 0x1180080e01f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP996" , 0x1180080e01f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP997" , 0x1180080e01f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP998" , 0x1180080e01f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP999" , 0x1180080e01f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1000" , 0x1180080e01f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1001" , 0x1180080e01f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1002" , 0x1180080e01f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1003" , 0x1180080e01f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1004" , 0x1180080e01f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1005" , 0x1180080e01f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1006" , 0x1180080e01f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1007" , 0x1180080e01f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1008" , 0x1180080e01f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1009" , 0x1180080e01f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1010" , 0x1180080e01f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1011" , 0x1180080e01f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1012" , 0x1180080e01fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1013" , 0x1180080e01fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1014" , 0x1180080e01fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1015" , 0x1180080e01fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1016" , 0x1180080e01fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1017" , 0x1180080e01fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1018" , 0x1180080e01fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1019" , 0x1180080e01fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1020" , 0x1180080e01fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1021" , 0x1180080e01fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1022" , 0x1180080e01ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1023" , 0x1180080e01ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_ERR_TDT0" , 0x1180080a007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"L2C_ERR_TTG0" , 0x1180080a007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"L2C_ERR_VBF0" , 0x1180080c007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"L2C_ERR_XMC" , 0x11800808007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"L2C_INT_ENA" , 0x1180080800020ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"L2C_INT_REG" , 0x1180080800018ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"L2C_IOC0_PFC" , 0x1180080800420ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"L2C_IOR0_PFC" , 0x1180080800428ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"L2C_QOS_IOB0" , 0x1180080880200ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"L2C_QOS_PP0" , 0x1180080880000ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_QOS_PP1" , 0x1180080880008ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_QOS_PP2" , 0x1180080880010ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_QOS_PP3" , 0x1180080880018ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_QOS_WGT" , 0x1180080800008ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"L2C_RSC0_PFC" , 0x1180080800410ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"L2C_RSD0_PFC" , 0x1180080800418ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"L2C_TAD0_ECC0" , 0x1180080a00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"L2C_TAD0_ECC1" , 0x1180080a00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"L2C_TAD0_IEN" , 0x1180080a00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"L2C_TAD0_INT" , 0x1180080a00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"L2C_TAD0_PFC0" , 0x1180080a00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"L2C_TAD0_PFC1" , 0x1180080a00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"L2C_TAD0_PFC2" , 0x1180080a00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"L2C_TAD0_PFC3" , 0x1180080a00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"L2C_TAD0_PRF" , 0x1180080a00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"L2C_TAD0_TAG" , 0x1180080a00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VER_ID" , 0x11800808007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"L2C_VER_IOB" , 0x11800808007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"L2C_VER_MSC" , 0x11800808007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"L2C_VER_PP" , 0x11800808007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"L2C_VIRTID_IOB0" , 0x11800808c0200ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"L2C_VIRTID_PP0" , 0x11800808c0000ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_VIRTID_PP1" , 0x11800808c0008ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_VIRTID_PP2" , 0x11800808c0010ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_VIRTID_PP3" , 0x11800808c0018ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_VRT_CTL" , 0x1180080800010ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"L2C_VRT_MEM0" , 0x1180080900000ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1" , 0x1180080900008ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM2" , 0x1180080900010ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM3" , 0x1180080900018ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM4" , 0x1180080900020ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM5" , 0x1180080900028ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM6" , 0x1180080900030ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM7" , 0x1180080900038ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM8" , 0x1180080900040ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM9" , 0x1180080900048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM10" , 0x1180080900050ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM11" , 0x1180080900058ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM12" , 0x1180080900060ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM13" , 0x1180080900068ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM14" , 0x1180080900070ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM15" , 0x1180080900078ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM16" , 0x1180080900080ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM17" , 0x1180080900088ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM18" , 0x1180080900090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM19" , 0x1180080900098ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM20" , 0x11800809000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM21" , 0x11800809000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM22" , 0x11800809000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM23" , 0x11800809000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM24" , 0x11800809000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM25" , 0x11800809000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM26" , 0x11800809000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM27" , 0x11800809000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM28" , 0x11800809000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM29" , 0x11800809000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM30" , 0x11800809000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM31" , 0x11800809000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM32" , 0x1180080900100ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM33" , 0x1180080900108ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM34" , 0x1180080900110ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM35" , 0x1180080900118ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM36" , 0x1180080900120ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM37" , 0x1180080900128ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM38" , 0x1180080900130ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM39" , 0x1180080900138ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM40" , 0x1180080900140ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM41" , 0x1180080900148ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM42" , 0x1180080900150ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM43" , 0x1180080900158ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM44" , 0x1180080900160ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM45" , 0x1180080900168ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM46" , 0x1180080900170ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM47" , 0x1180080900178ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM48" , 0x1180080900180ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM49" , 0x1180080900188ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM50" , 0x1180080900190ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM51" , 0x1180080900198ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM52" , 0x11800809001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM53" , 0x11800809001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM54" , 0x11800809001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM55" , 0x11800809001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM56" , 0x11800809001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM57" , 0x11800809001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM58" , 0x11800809001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM59" , 0x11800809001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM60" , 0x11800809001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM61" , 0x11800809001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM62" , 0x11800809001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM63" , 0x11800809001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM64" , 0x1180080900200ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM65" , 0x1180080900208ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM66" , 0x1180080900210ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM67" , 0x1180080900218ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM68" , 0x1180080900220ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM69" , 0x1180080900228ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM70" , 0x1180080900230ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM71" , 0x1180080900238ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM72" , 0x1180080900240ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM73" , 0x1180080900248ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM74" , 0x1180080900250ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM75" , 0x1180080900258ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM76" , 0x1180080900260ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM77" , 0x1180080900268ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM78" , 0x1180080900270ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM79" , 0x1180080900278ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM80" , 0x1180080900280ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM81" , 0x1180080900288ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM82" , 0x1180080900290ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM83" , 0x1180080900298ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM84" , 0x11800809002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM85" , 0x11800809002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM86" , 0x11800809002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM87" , 0x11800809002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM88" , 0x11800809002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM89" , 0x11800809002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM90" , 0x11800809002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM91" , 0x11800809002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM92" , 0x11800809002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM93" , 0x11800809002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM94" , 0x11800809002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM95" , 0x11800809002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM96" , 0x1180080900300ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM97" , 0x1180080900308ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM98" , 0x1180080900310ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM99" , 0x1180080900318ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM100" , 0x1180080900320ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM101" , 0x1180080900328ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM102" , 0x1180080900330ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM103" , 0x1180080900338ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM104" , 0x1180080900340ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM105" , 0x1180080900348ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM106" , 0x1180080900350ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM107" , 0x1180080900358ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM108" , 0x1180080900360ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM109" , 0x1180080900368ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM110" , 0x1180080900370ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM111" , 0x1180080900378ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM112" , 0x1180080900380ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM113" , 0x1180080900388ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM114" , 0x1180080900390ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM115" , 0x1180080900398ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM116" , 0x11800809003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM117" , 0x11800809003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM118" , 0x11800809003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM119" , 0x11800809003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM120" , 0x11800809003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM121" , 0x11800809003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM122" , 0x11800809003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM123" , 0x11800809003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM124" , 0x11800809003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM125" , 0x11800809003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM126" , 0x11800809003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM127" , 0x11800809003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM128" , 0x1180080900400ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM129" , 0x1180080900408ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM130" , 0x1180080900410ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM131" , 0x1180080900418ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM132" , 0x1180080900420ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM133" , 0x1180080900428ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM134" , 0x1180080900430ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM135" , 0x1180080900438ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM136" , 0x1180080900440ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM137" , 0x1180080900448ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM138" , 0x1180080900450ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM139" , 0x1180080900458ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM140" , 0x1180080900460ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM141" , 0x1180080900468ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM142" , 0x1180080900470ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM143" , 0x1180080900478ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM144" , 0x1180080900480ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM145" , 0x1180080900488ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM146" , 0x1180080900490ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM147" , 0x1180080900498ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM148" , 0x11800809004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM149" , 0x11800809004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM150" , 0x11800809004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM151" , 0x11800809004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM152" , 0x11800809004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM153" , 0x11800809004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM154" , 0x11800809004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM155" , 0x11800809004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM156" , 0x11800809004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM157" , 0x11800809004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM158" , 0x11800809004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM159" , 0x11800809004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM160" , 0x1180080900500ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM161" , 0x1180080900508ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM162" , 0x1180080900510ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM163" , 0x1180080900518ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM164" , 0x1180080900520ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM165" , 0x1180080900528ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM166" , 0x1180080900530ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM167" , 0x1180080900538ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM168" , 0x1180080900540ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM169" , 0x1180080900548ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM170" , 0x1180080900550ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM171" , 0x1180080900558ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM172" , 0x1180080900560ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM173" , 0x1180080900568ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM174" , 0x1180080900570ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM175" , 0x1180080900578ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM176" , 0x1180080900580ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM177" , 0x1180080900588ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM178" , 0x1180080900590ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM179" , 0x1180080900598ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM180" , 0x11800809005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM181" , 0x11800809005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM182" , 0x11800809005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM183" , 0x11800809005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM184" , 0x11800809005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM185" , 0x11800809005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM186" , 0x11800809005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM187" , 0x11800809005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM188" , 0x11800809005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM189" , 0x11800809005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM190" , 0x11800809005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM191" , 0x11800809005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM192" , 0x1180080900600ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM193" , 0x1180080900608ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM194" , 0x1180080900610ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM195" , 0x1180080900618ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM196" , 0x1180080900620ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM197" , 0x1180080900628ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM198" , 0x1180080900630ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM199" , 0x1180080900638ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM200" , 0x1180080900640ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM201" , 0x1180080900648ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM202" , 0x1180080900650ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM203" , 0x1180080900658ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM204" , 0x1180080900660ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM205" , 0x1180080900668ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM206" , 0x1180080900670ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM207" , 0x1180080900678ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM208" , 0x1180080900680ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM209" , 0x1180080900688ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM210" , 0x1180080900690ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM211" , 0x1180080900698ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM212" , 0x11800809006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM213" , 0x11800809006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM214" , 0x11800809006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM215" , 0x11800809006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM216" , 0x11800809006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM217" , 0x11800809006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM218" , 0x11800809006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM219" , 0x11800809006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM220" , 0x11800809006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM221" , 0x11800809006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM222" , 0x11800809006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM223" , 0x11800809006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM224" , 0x1180080900700ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM225" , 0x1180080900708ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM226" , 0x1180080900710ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM227" , 0x1180080900718ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM228" , 0x1180080900720ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM229" , 0x1180080900728ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM230" , 0x1180080900730ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM231" , 0x1180080900738ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM232" , 0x1180080900740ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM233" , 0x1180080900748ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM234" , 0x1180080900750ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM235" , 0x1180080900758ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM236" , 0x1180080900760ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM237" , 0x1180080900768ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM238" , 0x1180080900770ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM239" , 0x1180080900778ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM240" , 0x1180080900780ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM241" , 0x1180080900788ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM242" , 0x1180080900790ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM243" , 0x1180080900798ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM244" , 0x11800809007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM245" , 0x11800809007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM246" , 0x11800809007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM247" , 0x11800809007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM248" , 0x11800809007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM249" , 0x11800809007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM250" , 0x11800809007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM251" , 0x11800809007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM252" , 0x11800809007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM253" , 0x11800809007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM254" , 0x11800809007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM255" , 0x11800809007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM256" , 0x1180080900800ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM257" , 0x1180080900808ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM258" , 0x1180080900810ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM259" , 0x1180080900818ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM260" , 0x1180080900820ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM261" , 0x1180080900828ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM262" , 0x1180080900830ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM263" , 0x1180080900838ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM264" , 0x1180080900840ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM265" , 0x1180080900848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM266" , 0x1180080900850ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM267" , 0x1180080900858ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM268" , 0x1180080900860ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM269" , 0x1180080900868ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM270" , 0x1180080900870ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM271" , 0x1180080900878ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM272" , 0x1180080900880ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM273" , 0x1180080900888ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM274" , 0x1180080900890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM275" , 0x1180080900898ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM276" , 0x11800809008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM277" , 0x11800809008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM278" , 0x11800809008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM279" , 0x11800809008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM280" , 0x11800809008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM281" , 0x11800809008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM282" , 0x11800809008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM283" , 0x11800809008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM284" , 0x11800809008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM285" , 0x11800809008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM286" , 0x11800809008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM287" , 0x11800809008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM288" , 0x1180080900900ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM289" , 0x1180080900908ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM290" , 0x1180080900910ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM291" , 0x1180080900918ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM292" , 0x1180080900920ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM293" , 0x1180080900928ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM294" , 0x1180080900930ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM295" , 0x1180080900938ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM296" , 0x1180080900940ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM297" , 0x1180080900948ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM298" , 0x1180080900950ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM299" , 0x1180080900958ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM300" , 0x1180080900960ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM301" , 0x1180080900968ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM302" , 0x1180080900970ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM303" , 0x1180080900978ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM304" , 0x1180080900980ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM305" , 0x1180080900988ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM306" , 0x1180080900990ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM307" , 0x1180080900998ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM308" , 0x11800809009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM309" , 0x11800809009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM310" , 0x11800809009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM311" , 0x11800809009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM312" , 0x11800809009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM313" , 0x11800809009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM314" , 0x11800809009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM315" , 0x11800809009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM316" , 0x11800809009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM317" , 0x11800809009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM318" , 0x11800809009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM319" , 0x11800809009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM320" , 0x1180080900a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM321" , 0x1180080900a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM322" , 0x1180080900a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM323" , 0x1180080900a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM324" , 0x1180080900a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM325" , 0x1180080900a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM326" , 0x1180080900a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM327" , 0x1180080900a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM328" , 0x1180080900a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM329" , 0x1180080900a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM330" , 0x1180080900a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM331" , 0x1180080900a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM332" , 0x1180080900a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM333" , 0x1180080900a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM334" , 0x1180080900a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM335" , 0x1180080900a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM336" , 0x1180080900a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM337" , 0x1180080900a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM338" , 0x1180080900a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM339" , 0x1180080900a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM340" , 0x1180080900aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM341" , 0x1180080900aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM342" , 0x1180080900ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM343" , 0x1180080900ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM344" , 0x1180080900ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM345" , 0x1180080900ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM346" , 0x1180080900ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM347" , 0x1180080900ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM348" , 0x1180080900ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM349" , 0x1180080900ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM350" , 0x1180080900af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM351" , 0x1180080900af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM352" , 0x1180080900b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM353" , 0x1180080900b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM354" , 0x1180080900b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM355" , 0x1180080900b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM356" , 0x1180080900b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM357" , 0x1180080900b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM358" , 0x1180080900b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM359" , 0x1180080900b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM360" , 0x1180080900b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM361" , 0x1180080900b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM362" , 0x1180080900b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM363" , 0x1180080900b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM364" , 0x1180080900b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM365" , 0x1180080900b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM366" , 0x1180080900b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM367" , 0x1180080900b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM368" , 0x1180080900b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM369" , 0x1180080900b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM370" , 0x1180080900b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM371" , 0x1180080900b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM372" , 0x1180080900ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM373" , 0x1180080900ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM374" , 0x1180080900bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM375" , 0x1180080900bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM376" , 0x1180080900bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM377" , 0x1180080900bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM378" , 0x1180080900bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM379" , 0x1180080900bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM380" , 0x1180080900be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM381" , 0x1180080900be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM382" , 0x1180080900bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM383" , 0x1180080900bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM384" , 0x1180080900c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM385" , 0x1180080900c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM386" , 0x1180080900c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM387" , 0x1180080900c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM388" , 0x1180080900c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM389" , 0x1180080900c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM390" , 0x1180080900c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM391" , 0x1180080900c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM392" , 0x1180080900c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM393" , 0x1180080900c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM394" , 0x1180080900c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM395" , 0x1180080900c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM396" , 0x1180080900c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM397" , 0x1180080900c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM398" , 0x1180080900c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM399" , 0x1180080900c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM400" , 0x1180080900c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM401" , 0x1180080900c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM402" , 0x1180080900c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM403" , 0x1180080900c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM404" , 0x1180080900ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM405" , 0x1180080900ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM406" , 0x1180080900cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM407" , 0x1180080900cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM408" , 0x1180080900cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM409" , 0x1180080900cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM410" , 0x1180080900cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM411" , 0x1180080900cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM412" , 0x1180080900ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM413" , 0x1180080900ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM414" , 0x1180080900cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM415" , 0x1180080900cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM416" , 0x1180080900d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM417" , 0x1180080900d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM418" , 0x1180080900d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM419" , 0x1180080900d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM420" , 0x1180080900d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM421" , 0x1180080900d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM422" , 0x1180080900d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM423" , 0x1180080900d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM424" , 0x1180080900d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM425" , 0x1180080900d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM426" , 0x1180080900d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM427" , 0x1180080900d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM428" , 0x1180080900d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM429" , 0x1180080900d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM430" , 0x1180080900d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM431" , 0x1180080900d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM432" , 0x1180080900d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM433" , 0x1180080900d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM434" , 0x1180080900d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM435" , 0x1180080900d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM436" , 0x1180080900da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM437" , 0x1180080900da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM438" , 0x1180080900db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM439" , 0x1180080900db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM440" , 0x1180080900dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM441" , 0x1180080900dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM442" , 0x1180080900dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM443" , 0x1180080900dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM444" , 0x1180080900de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM445" , 0x1180080900de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM446" , 0x1180080900df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM447" , 0x1180080900df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM448" , 0x1180080900e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM449" , 0x1180080900e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM450" , 0x1180080900e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM451" , 0x1180080900e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM452" , 0x1180080900e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM453" , 0x1180080900e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM454" , 0x1180080900e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM455" , 0x1180080900e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM456" , 0x1180080900e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM457" , 0x1180080900e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM458" , 0x1180080900e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM459" , 0x1180080900e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM460" , 0x1180080900e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM461" , 0x1180080900e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM462" , 0x1180080900e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM463" , 0x1180080900e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM464" , 0x1180080900e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM465" , 0x1180080900e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM466" , 0x1180080900e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM467" , 0x1180080900e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM468" , 0x1180080900ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM469" , 0x1180080900ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM470" , 0x1180080900eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM471" , 0x1180080900eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM472" , 0x1180080900ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM473" , 0x1180080900ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM474" , 0x1180080900ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM475" , 0x1180080900ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM476" , 0x1180080900ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM477" , 0x1180080900ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM478" , 0x1180080900ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM479" , 0x1180080900ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM480" , 0x1180080900f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM481" , 0x1180080900f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM482" , 0x1180080900f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM483" , 0x1180080900f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM484" , 0x1180080900f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM485" , 0x1180080900f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM486" , 0x1180080900f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM487" , 0x1180080900f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM488" , 0x1180080900f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM489" , 0x1180080900f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM490" , 0x1180080900f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM491" , 0x1180080900f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM492" , 0x1180080900f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM493" , 0x1180080900f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM494" , 0x1180080900f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM495" , 0x1180080900f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM496" , 0x1180080900f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM497" , 0x1180080900f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM498" , 0x1180080900f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM499" , 0x1180080900f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM500" , 0x1180080900fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM501" , 0x1180080900fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM502" , 0x1180080900fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM503" , 0x1180080900fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM504" , 0x1180080900fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM505" , 0x1180080900fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM506" , 0x1180080900fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM507" , 0x1180080900fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM508" , 0x1180080900fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM509" , 0x1180080900fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM510" , 0x1180080900ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM511" , 0x1180080900ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM512" , 0x1180080901000ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM513" , 0x1180080901008ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM514" , 0x1180080901010ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM515" , 0x1180080901018ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM516" , 0x1180080901020ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM517" , 0x1180080901028ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM518" , 0x1180080901030ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM519" , 0x1180080901038ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM520" , 0x1180080901040ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM521" , 0x1180080901048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM522" , 0x1180080901050ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM523" , 0x1180080901058ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM524" , 0x1180080901060ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM525" , 0x1180080901068ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM526" , 0x1180080901070ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM527" , 0x1180080901078ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM528" , 0x1180080901080ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM529" , 0x1180080901088ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM530" , 0x1180080901090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM531" , 0x1180080901098ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM532" , 0x11800809010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM533" , 0x11800809010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM534" , 0x11800809010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM535" , 0x11800809010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM536" , 0x11800809010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM537" , 0x11800809010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM538" , 0x11800809010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM539" , 0x11800809010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM540" , 0x11800809010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM541" , 0x11800809010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM542" , 0x11800809010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM543" , 0x11800809010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM544" , 0x1180080901100ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM545" , 0x1180080901108ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM546" , 0x1180080901110ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM547" , 0x1180080901118ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM548" , 0x1180080901120ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM549" , 0x1180080901128ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM550" , 0x1180080901130ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM551" , 0x1180080901138ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM552" , 0x1180080901140ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM553" , 0x1180080901148ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM554" , 0x1180080901150ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM555" , 0x1180080901158ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM556" , 0x1180080901160ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM557" , 0x1180080901168ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM558" , 0x1180080901170ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM559" , 0x1180080901178ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM560" , 0x1180080901180ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM561" , 0x1180080901188ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM562" , 0x1180080901190ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM563" , 0x1180080901198ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM564" , 0x11800809011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM565" , 0x11800809011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM566" , 0x11800809011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM567" , 0x11800809011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM568" , 0x11800809011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM569" , 0x11800809011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM570" , 0x11800809011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM571" , 0x11800809011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM572" , 0x11800809011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM573" , 0x11800809011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM574" , 0x11800809011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM575" , 0x11800809011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM576" , 0x1180080901200ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM577" , 0x1180080901208ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM578" , 0x1180080901210ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM579" , 0x1180080901218ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM580" , 0x1180080901220ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM581" , 0x1180080901228ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM582" , 0x1180080901230ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM583" , 0x1180080901238ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM584" , 0x1180080901240ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM585" , 0x1180080901248ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM586" , 0x1180080901250ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM587" , 0x1180080901258ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM588" , 0x1180080901260ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM589" , 0x1180080901268ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM590" , 0x1180080901270ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM591" , 0x1180080901278ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM592" , 0x1180080901280ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM593" , 0x1180080901288ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM594" , 0x1180080901290ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM595" , 0x1180080901298ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM596" , 0x11800809012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM597" , 0x11800809012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM598" , 0x11800809012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM599" , 0x11800809012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM600" , 0x11800809012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM601" , 0x11800809012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM602" , 0x11800809012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM603" , 0x11800809012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM604" , 0x11800809012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM605" , 0x11800809012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM606" , 0x11800809012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM607" , 0x11800809012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM608" , 0x1180080901300ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM609" , 0x1180080901308ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM610" , 0x1180080901310ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM611" , 0x1180080901318ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM612" , 0x1180080901320ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM613" , 0x1180080901328ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM614" , 0x1180080901330ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM615" , 0x1180080901338ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM616" , 0x1180080901340ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM617" , 0x1180080901348ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM618" , 0x1180080901350ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM619" , 0x1180080901358ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM620" , 0x1180080901360ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM621" , 0x1180080901368ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM622" , 0x1180080901370ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM623" , 0x1180080901378ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM624" , 0x1180080901380ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM625" , 0x1180080901388ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM626" , 0x1180080901390ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM627" , 0x1180080901398ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM628" , 0x11800809013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM629" , 0x11800809013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM630" , 0x11800809013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM631" , 0x11800809013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM632" , 0x11800809013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM633" , 0x11800809013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM634" , 0x11800809013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM635" , 0x11800809013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM636" , 0x11800809013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM637" , 0x11800809013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM638" , 0x11800809013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM639" , 0x11800809013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM640" , 0x1180080901400ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM641" , 0x1180080901408ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM642" , 0x1180080901410ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM643" , 0x1180080901418ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM644" , 0x1180080901420ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM645" , 0x1180080901428ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM646" , 0x1180080901430ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM647" , 0x1180080901438ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM648" , 0x1180080901440ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM649" , 0x1180080901448ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM650" , 0x1180080901450ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM651" , 0x1180080901458ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM652" , 0x1180080901460ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM653" , 0x1180080901468ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM654" , 0x1180080901470ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM655" , 0x1180080901478ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM656" , 0x1180080901480ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM657" , 0x1180080901488ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM658" , 0x1180080901490ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM659" , 0x1180080901498ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM660" , 0x11800809014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM661" , 0x11800809014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM662" , 0x11800809014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM663" , 0x11800809014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM664" , 0x11800809014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM665" , 0x11800809014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM666" , 0x11800809014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM667" , 0x11800809014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM668" , 0x11800809014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM669" , 0x11800809014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM670" , 0x11800809014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM671" , 0x11800809014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM672" , 0x1180080901500ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM673" , 0x1180080901508ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM674" , 0x1180080901510ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM675" , 0x1180080901518ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM676" , 0x1180080901520ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM677" , 0x1180080901528ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM678" , 0x1180080901530ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM679" , 0x1180080901538ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM680" , 0x1180080901540ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM681" , 0x1180080901548ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM682" , 0x1180080901550ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM683" , 0x1180080901558ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM684" , 0x1180080901560ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM685" , 0x1180080901568ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM686" , 0x1180080901570ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM687" , 0x1180080901578ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM688" , 0x1180080901580ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM689" , 0x1180080901588ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM690" , 0x1180080901590ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM691" , 0x1180080901598ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM692" , 0x11800809015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM693" , 0x11800809015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM694" , 0x11800809015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM695" , 0x11800809015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM696" , 0x11800809015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM697" , 0x11800809015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM698" , 0x11800809015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM699" , 0x11800809015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM700" , 0x11800809015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM701" , 0x11800809015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM702" , 0x11800809015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM703" , 0x11800809015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM704" , 0x1180080901600ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM705" , 0x1180080901608ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM706" , 0x1180080901610ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM707" , 0x1180080901618ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM708" , 0x1180080901620ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM709" , 0x1180080901628ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM710" , 0x1180080901630ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM711" , 0x1180080901638ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM712" , 0x1180080901640ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM713" , 0x1180080901648ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM714" , 0x1180080901650ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM715" , 0x1180080901658ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM716" , 0x1180080901660ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM717" , 0x1180080901668ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM718" , 0x1180080901670ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM719" , 0x1180080901678ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM720" , 0x1180080901680ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM721" , 0x1180080901688ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM722" , 0x1180080901690ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM723" , 0x1180080901698ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM724" , 0x11800809016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM725" , 0x11800809016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM726" , 0x11800809016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM727" , 0x11800809016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM728" , 0x11800809016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM729" , 0x11800809016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM730" , 0x11800809016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM731" , 0x11800809016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM732" , 0x11800809016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM733" , 0x11800809016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM734" , 0x11800809016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM735" , 0x11800809016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM736" , 0x1180080901700ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM737" , 0x1180080901708ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM738" , 0x1180080901710ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM739" , 0x1180080901718ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM740" , 0x1180080901720ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM741" , 0x1180080901728ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM742" , 0x1180080901730ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM743" , 0x1180080901738ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM744" , 0x1180080901740ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM745" , 0x1180080901748ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM746" , 0x1180080901750ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM747" , 0x1180080901758ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM748" , 0x1180080901760ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM749" , 0x1180080901768ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM750" , 0x1180080901770ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM751" , 0x1180080901778ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM752" , 0x1180080901780ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM753" , 0x1180080901788ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM754" , 0x1180080901790ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM755" , 0x1180080901798ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM756" , 0x11800809017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM757" , 0x11800809017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM758" , 0x11800809017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM759" , 0x11800809017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM760" , 0x11800809017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM761" , 0x11800809017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM762" , 0x11800809017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM763" , 0x11800809017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM764" , 0x11800809017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM765" , 0x11800809017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM766" , 0x11800809017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM767" , 0x11800809017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM768" , 0x1180080901800ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM769" , 0x1180080901808ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM770" , 0x1180080901810ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM771" , 0x1180080901818ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM772" , 0x1180080901820ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM773" , 0x1180080901828ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM774" , 0x1180080901830ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM775" , 0x1180080901838ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM776" , 0x1180080901840ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM777" , 0x1180080901848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM778" , 0x1180080901850ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM779" , 0x1180080901858ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM780" , 0x1180080901860ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM781" , 0x1180080901868ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM782" , 0x1180080901870ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM783" , 0x1180080901878ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM784" , 0x1180080901880ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM785" , 0x1180080901888ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM786" , 0x1180080901890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM787" , 0x1180080901898ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM788" , 0x11800809018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM789" , 0x11800809018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM790" , 0x11800809018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM791" , 0x11800809018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM792" , 0x11800809018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM793" , 0x11800809018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM794" , 0x11800809018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM795" , 0x11800809018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM796" , 0x11800809018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM797" , 0x11800809018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM798" , 0x11800809018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM799" , 0x11800809018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM800" , 0x1180080901900ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM801" , 0x1180080901908ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM802" , 0x1180080901910ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM803" , 0x1180080901918ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM804" , 0x1180080901920ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM805" , 0x1180080901928ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM806" , 0x1180080901930ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM807" , 0x1180080901938ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM808" , 0x1180080901940ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM809" , 0x1180080901948ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM810" , 0x1180080901950ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM811" , 0x1180080901958ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM812" , 0x1180080901960ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM813" , 0x1180080901968ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM814" , 0x1180080901970ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM815" , 0x1180080901978ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM816" , 0x1180080901980ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM817" , 0x1180080901988ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM818" , 0x1180080901990ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM819" , 0x1180080901998ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM820" , 0x11800809019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM821" , 0x11800809019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM822" , 0x11800809019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM823" , 0x11800809019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM824" , 0x11800809019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM825" , 0x11800809019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM826" , 0x11800809019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM827" , 0x11800809019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM828" , 0x11800809019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM829" , 0x11800809019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM830" , 0x11800809019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM831" , 0x11800809019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM832" , 0x1180080901a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM833" , 0x1180080901a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM834" , 0x1180080901a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM835" , 0x1180080901a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM836" , 0x1180080901a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM837" , 0x1180080901a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM838" , 0x1180080901a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM839" , 0x1180080901a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM840" , 0x1180080901a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM841" , 0x1180080901a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM842" , 0x1180080901a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM843" , 0x1180080901a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM844" , 0x1180080901a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM845" , 0x1180080901a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM846" , 0x1180080901a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM847" , 0x1180080901a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM848" , 0x1180080901a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM849" , 0x1180080901a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM850" , 0x1180080901a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM851" , 0x1180080901a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM852" , 0x1180080901aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM853" , 0x1180080901aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM854" , 0x1180080901ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM855" , 0x1180080901ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM856" , 0x1180080901ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM857" , 0x1180080901ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM858" , 0x1180080901ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM859" , 0x1180080901ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM860" , 0x1180080901ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM861" , 0x1180080901ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM862" , 0x1180080901af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM863" , 0x1180080901af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM864" , 0x1180080901b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM865" , 0x1180080901b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM866" , 0x1180080901b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM867" , 0x1180080901b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM868" , 0x1180080901b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM869" , 0x1180080901b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM870" , 0x1180080901b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM871" , 0x1180080901b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM872" , 0x1180080901b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM873" , 0x1180080901b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM874" , 0x1180080901b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM875" , 0x1180080901b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM876" , 0x1180080901b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM877" , 0x1180080901b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM878" , 0x1180080901b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM879" , 0x1180080901b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM880" , 0x1180080901b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM881" , 0x1180080901b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM882" , 0x1180080901b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM883" , 0x1180080901b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM884" , 0x1180080901ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM885" , 0x1180080901ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM886" , 0x1180080901bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM887" , 0x1180080901bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM888" , 0x1180080901bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM889" , 0x1180080901bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM890" , 0x1180080901bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM891" , 0x1180080901bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM892" , 0x1180080901be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM893" , 0x1180080901be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM894" , 0x1180080901bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM895" , 0x1180080901bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM896" , 0x1180080901c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM897" , 0x1180080901c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM898" , 0x1180080901c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM899" , 0x1180080901c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM900" , 0x1180080901c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM901" , 0x1180080901c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM902" , 0x1180080901c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM903" , 0x1180080901c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM904" , 0x1180080901c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM905" , 0x1180080901c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM906" , 0x1180080901c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM907" , 0x1180080901c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM908" , 0x1180080901c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM909" , 0x1180080901c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM910" , 0x1180080901c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM911" , 0x1180080901c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM912" , 0x1180080901c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM913" , 0x1180080901c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM914" , 0x1180080901c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM915" , 0x1180080901c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM916" , 0x1180080901ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM917" , 0x1180080901ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM918" , 0x1180080901cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM919" , 0x1180080901cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM920" , 0x1180080901cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM921" , 0x1180080901cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM922" , 0x1180080901cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM923" , 0x1180080901cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM924" , 0x1180080901ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM925" , 0x1180080901ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM926" , 0x1180080901cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM927" , 0x1180080901cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM928" , 0x1180080901d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM929" , 0x1180080901d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM930" , 0x1180080901d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM931" , 0x1180080901d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM932" , 0x1180080901d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM933" , 0x1180080901d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM934" , 0x1180080901d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM935" , 0x1180080901d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM936" , 0x1180080901d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM937" , 0x1180080901d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM938" , 0x1180080901d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM939" , 0x1180080901d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM940" , 0x1180080901d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM941" , 0x1180080901d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM942" , 0x1180080901d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM943" , 0x1180080901d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM944" , 0x1180080901d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM945" , 0x1180080901d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM946" , 0x1180080901d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM947" , 0x1180080901d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM948" , 0x1180080901da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM949" , 0x1180080901da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM950" , 0x1180080901db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM951" , 0x1180080901db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM952" , 0x1180080901dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM953" , 0x1180080901dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM954" , 0x1180080901dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM955" , 0x1180080901dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM956" , 0x1180080901de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM957" , 0x1180080901de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM958" , 0x1180080901df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM959" , 0x1180080901df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM960" , 0x1180080901e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM961" , 0x1180080901e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM962" , 0x1180080901e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM963" , 0x1180080901e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM964" , 0x1180080901e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM965" , 0x1180080901e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM966" , 0x1180080901e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM967" , 0x1180080901e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM968" , 0x1180080901e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM969" , 0x1180080901e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM970" , 0x1180080901e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM971" , 0x1180080901e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM972" , 0x1180080901e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM973" , 0x1180080901e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM974" , 0x1180080901e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM975" , 0x1180080901e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM976" , 0x1180080901e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM977" , 0x1180080901e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM978" , 0x1180080901e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM979" , 0x1180080901e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM980" , 0x1180080901ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM981" , 0x1180080901ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM982" , 0x1180080901eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM983" , 0x1180080901eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM984" , 0x1180080901ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM985" , 0x1180080901ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM986" , 0x1180080901ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM987" , 0x1180080901ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM988" , 0x1180080901ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM989" , 0x1180080901ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM990" , 0x1180080901ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM991" , 0x1180080901ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM992" , 0x1180080901f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM993" , 0x1180080901f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM994" , 0x1180080901f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM995" , 0x1180080901f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM996" , 0x1180080901f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM997" , 0x1180080901f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM998" , 0x1180080901f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM999" , 0x1180080901f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1000" , 0x1180080901f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1001" , 0x1180080901f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1002" , 0x1180080901f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1003" , 0x1180080901f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1004" , 0x1180080901f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1005" , 0x1180080901f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1006" , 0x1180080901f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1007" , 0x1180080901f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1008" , 0x1180080901f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1009" , 0x1180080901f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1010" , 0x1180080901f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1011" , 0x1180080901f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1012" , 0x1180080901fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1013" , 0x1180080901fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1014" , 0x1180080901fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1015" , 0x1180080901fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1016" , 0x1180080901fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1017" , 0x1180080901fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1018" , 0x1180080901fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1019" , 0x1180080901fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1020" , 0x1180080901fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1021" , 0x1180080901fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1022" , 0x1180080901ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1023" , 0x1180080901ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_WPAR_IOB0" , 0x1180080840200ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"L2C_WPAR_PP0" , 0x1180080840000ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_WPAR_PP1" , 0x1180080840008ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_WPAR_PP2" , 0x1180080840010ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_WPAR_PP3" , 0x1180080840018ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_XMC0_PFC" , 0x1180080800400ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"L2C_XMC_CMD" , 0x1180080800028ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_XMD0_PFC" , 0x1180080800408ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"LMC0_CHAR_CTL" , 0x1180088000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"LMC0_CHAR_MASK0" , 0x1180088000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"LMC0_CHAR_MASK1" , 0x1180088000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"LMC0_CHAR_MASK2" , 0x1180088000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"LMC0_CHAR_MASK3" , 0x1180088000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"LMC0_CHAR_MASK4" , 0x1180088000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"LMC0_COMP_CTL2" , 0x11800880001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"LMC0_CONFIG" , 0x1180088000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"LMC0_CONTROL" , 0x1180088000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"LMC0_DCLK_CNT" , 0x11800880001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"LMC0_DDR_PLL_CTL" , 0x1180088000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"LMC0_DIMM000_PARAMS" , 0x1180088000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"LMC0_DIMM001_PARAMS" , 0x1180088000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"LMC0_DIMM_CTL" , 0x1180088000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"LMC0_DLL_CTL2" , 0x11800880001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"LMC0_DLL_CTL3" , 0x1180088000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"LMC0_IFB_CNT" , 0x11800880001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"LMC0_INT" , 0x11800880001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"LMC0_INT_EN" , 0x11800880001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"LMC0_MODEREG_PARAMS0" , 0x11800880001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"LMC0_MODEREG_PARAMS1" , 0x1180088000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"LMC0_NXM" , 0x11800880000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"LMC0_OPS_CNT" , 0x11800880001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"LMC0_PHY_CTL" , 0x1180088000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"LMC0_RESET_CTL" , 0x1180088000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"LMC0_RLEVEL_CTL" , 0x11800880002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"LMC0_RLEVEL_DBG" , 0x11800880002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"LMC0_RLEVEL_RANK000" , 0x1180088000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"LMC0_RLEVEL_RANK001" , 0x1180088000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"LMC0_RLEVEL_RANK002" , 0x1180088000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"LMC0_RLEVEL_RANK003" , 0x1180088000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"LMC0_RODT_MASK" , 0x1180088000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"LMC0_SCRAMBLE_CFG0" , 0x1180088000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"LMC0_SCRAMBLE_CFG1" , 0x1180088000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"LMC0_SCRAMBLED_FADR" , 0x1180088000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"LMC0_SLOT_CTL0" , 0x11800880001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"LMC0_SLOT_CTL1" , 0x1180088000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"LMC0_SLOT_CTL2" , 0x1180088000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"LMC0_TIMING_PARAMS0" , 0x1180088000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"LMC0_TIMING_PARAMS1" , 0x11800880001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"LMC0_TRO_CTL" , 0x1180088000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"LMC0_TRO_STAT" , 0x1180088000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"LMC0_WLEVEL_CTL" , 0x1180088000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"LMC0_WLEVEL_DBG" , 0x1180088000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"LMC0_WLEVEL_RANK000" , 0x11800880002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"LMC0_WLEVEL_RANK001" , 0x11800880002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"LMC0_WLEVEL_RANK002" , 0x11800880002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"LMC0_WLEVEL_RANK003" , 0x11800880002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"LMC0_WODT_MASK" , 0x11800880001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"MIO_BOOT_PIN_DEFS" , 0x11800000000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"MIO_EMM_BUF_DAT" , 0x11800000020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"MIO_EMM_BUF_IDX" , 0x11800000020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"MIO_EMM_CFG" , 0x1180000002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"MIO_EMM_CMD" , 0x1180000002058ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"MIO_EMM_DMA" , 0x1180000002050ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"MIO_EMM_INT" , 0x1180000002078ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"MIO_EMM_INT_EN" , 0x1180000002080ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"MIO_EMM_MODE0" , 0x1180000002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"MIO_EMM_MODE1" , 0x1180000002010ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"MIO_EMM_MODE2" , 0x1180000002018ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"MIO_EMM_MODE3" , 0x1180000002020ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"MIO_EMM_RCA" , 0x11800000020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"MIO_EMM_RSP_HI" , 0x1180000002070ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"MIO_EMM_RSP_LO" , 0x1180000002068ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"MIO_EMM_RSP_STS" , 0x1180000002060ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"MIO_EMM_SAMPLE" , 0x1180000002090ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"MIO_EMM_STS_MASK" , 0x1180000002098ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"MIO_EMM_SWITCH" , 0x1180000002048ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"MIO_EMM_WDOG" , 0x1180000002088ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"MIO_FUS_READ_TIMES" , 0x1180000001570ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"MIO_FUS_REPAIR_RES0" , 0x1180000001558ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"MIO_FUS_REPAIR_RES1" , 0x1180000001560ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"MIO_FUS_REPAIR_RES2" , 0x1180000001568ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_FUS_TGG" , 0x1180000001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"MIO_GPIO_COMP" , 0x11800000000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"MIO_NDF_DMA_CFG" , 0x1180000000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"MIO_NDF_DMA_INT" , 0x1180000000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"MIO_NDF_DMA_INT_EN" , 0x1180000000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"MIO_PTP_CKOUT_HI_INCR" , 0x1070000000f40ull, CVMX_CSR_DB_TYPE_NCB, 64, 507},
- {"MIO_PTP_CKOUT_LO_INCR" , 0x1070000000f48ull, CVMX_CSR_DB_TYPE_NCB, 64, 508},
- {"MIO_PTP_CKOUT_THRESH_HI" , 0x1070000000f38ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
- {"MIO_PTP_CKOUT_THRESH_LO" , 0x1070000000f30ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
- {"MIO_PTP_CLOCK_CFG" , 0x1070000000f00ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
- {"MIO_PTP_CLOCK_COMP" , 0x1070000000f18ull, CVMX_CSR_DB_TYPE_NCB, 64, 512},
- {"MIO_PTP_CLOCK_HI" , 0x1070000000f10ull, CVMX_CSR_DB_TYPE_NCB, 64, 513},
- {"MIO_PTP_CLOCK_LO" , 0x1070000000f08ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
- {"MIO_PTP_EVT_CNT" , 0x1070000000f28ull, CVMX_CSR_DB_TYPE_NCB, 64, 515},
- {"MIO_PTP_PPS_HI_INCR" , 0x1070000000f60ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
- {"MIO_PTP_PPS_LO_INCR" , 0x1070000000f68ull, CVMX_CSR_DB_TYPE_NCB, 64, 517},
- {"MIO_PTP_PPS_THRESH_HI" , 0x1070000000f58ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
- {"MIO_PTP_PPS_THRESH_LO" , 0x1070000000f50ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
- {"MIO_PTP_TIMESTAMP" , 0x1070000000f20ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"MIO_QLM0_CFG" , 0x1180000001590ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"MIO_QLM1_CFG" , 0x1180000001598ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"MIO_QLM2_CFG" , 0x11800000015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"MIO_RST_BOOT" , 0x1180000001600ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"MIO_RST_CFG" , 0x1180000001610ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"MIO_RST_CKILL" , 0x1180000001638ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"MIO_RST_CNTL0" , 0x1180000001648ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"MIO_RST_CNTL1" , 0x1180000001650ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"MIO_RST_CTL0" , 0x1180000001618ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"MIO_RST_CTL1" , 0x1180000001620ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"MIO_RST_DELAY" , 0x1180000001608ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"MIO_RST_INT" , 0x1180000001628ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"MIO_RST_INT_EN" , 0x1180000001630ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 559},
- {"MIX1_BIST" , 0x1070000100878ull, CVMX_CSR_DB_TYPE_NCB, 64, 559},
- {"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 560},
- {"MIX1_CTL" , 0x1070000100820ull, CVMX_CSR_DB_TYPE_NCB, 64, 560},
- {"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 561},
- {"MIX1_INTENA" , 0x1070000100850ull, CVMX_CSR_DB_TYPE_NCB, 64, 561},
- {"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 562},
- {"MIX1_IRCNT" , 0x1070000100830ull, CVMX_CSR_DB_TYPE_NCB, 64, 562},
- {"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 563},
- {"MIX1_IRHWM" , 0x1070000100828ull, CVMX_CSR_DB_TYPE_NCB, 64, 563},
- {"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 564},
- {"MIX1_IRING1" , 0x1070000100810ull, CVMX_CSR_DB_TYPE_NCB, 64, 564},
- {"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"MIX1_IRING2" , 0x1070000100818ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"MIX1_ISR" , 0x1070000100848ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 567},
- {"MIX1_ORCNT" , 0x1070000100840ull, CVMX_CSR_DB_TYPE_NCB, 64, 567},
- {"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 568},
- {"MIX1_ORHWM" , 0x1070000100838ull, CVMX_CSR_DB_TYPE_NCB, 64, 568},
- {"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 569},
- {"MIX1_ORING1" , 0x1070000100800ull, CVMX_CSR_DB_TYPE_NCB, 64, 569},
- {"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"MIX1_ORING2" , 0x1070000100808ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"MIX1_REMCNT" , 0x1070000100858ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"MIX0_TSCTL" , 0x1070000100068ull, CVMX_CSR_DB_TYPE_NCB, 64, 572},
- {"MIX1_TSCTL" , 0x1070000100868ull, CVMX_CSR_DB_TYPE_NCB, 64, 572},
- {"MIX0_TSTAMP" , 0x1070000100060ull, CVMX_CSR_DB_TYPE_NCB, 64, 573},
- {"MIX1_TSTAMP" , 0x1070000100860ull, CVMX_CSR_DB_TYPE_NCB, 64, 573},
- {"MPI_CFG" , 0x1070000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 574},
- {"MPI_DAT0" , 0x1070000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"MPI_DAT1" , 0x1070000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"MPI_DAT2" , 0x1070000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"MPI_DAT3" , 0x1070000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"MPI_DAT4" , 0x10700000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"MPI_DAT5" , 0x10700000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"MPI_DAT6" , 0x10700000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"MPI_DAT7" , 0x10700000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"MPI_DAT8" , 0x10700000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"MPI_STS" , 0x1070000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 576},
- {"MPI_TX" , 0x1070000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 577},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 578},
- {"PCIEEP1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 578},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 579},
- {"PCIEEP1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 579},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 580},
- {"PCIEEP1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 580},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 581},
- {"PCIEEP1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 581},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 582},
- {"PCIEEP1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 582},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 583},
- {"PCIEEP1_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 583},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 584},
- {"PCIEEP1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 584},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 585},
- {"PCIEEP1_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 585},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 586},
- {"PCIEEP1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 586},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 587},
- {"PCIEEP1_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 587},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 588},
- {"PCIEEP1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 588},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 589},
- {"PCIEEP1_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 589},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 590},
- {"PCIEEP1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 590},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 591},
- {"PCIEEP1_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 591},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 592},
- {"PCIEEP1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 592},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 593},
- {"PCIEEP1_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 593},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 594},
- {"PCIEEP1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 594},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 595},
- {"PCIEEP1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 595},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 596},
- {"PCIEEP1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 596},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 597},
- {"PCIEEP1_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 597},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 598},
- {"PCIEEP1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 598},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 599},
- {"PCIEEP1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 599},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 600},
- {"PCIEEP1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 600},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 601},
- {"PCIEEP1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 601},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 602},
- {"PCIEEP1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 602},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 603},
- {"PCIEEP1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 603},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 604},
- {"PCIEEP1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 604},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 605},
- {"PCIEEP1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 605},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 606},
- {"PCIEEP1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 606},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 607},
- {"PCIEEP1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 607},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 608},
- {"PCIEEP1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 608},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 609},
- {"PCIEEP1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 609},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 610},
- {"PCIEEP1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 610},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 611},
- {"PCIEEP1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 611},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 612},
- {"PCIEEP1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 612},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 613},
- {"PCIEEP1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 613},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 614},
- {"PCIEEP1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 614},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 615},
- {"PCIEEP1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 615},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 616},
- {"PCIEEP1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 616},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 617},
- {"PCIEEP1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 617},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 618},
- {"PCIEEP1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 618},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 619},
- {"PCIEEP1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 619},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 620},
- {"PCIEEP1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 620},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 621},
- {"PCIEEP1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 621},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 622},
- {"PCIEEP1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 622},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 623},
- {"PCIEEP1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 623},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 624},
- {"PCIEEP1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 624},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 625},
- {"PCIEEP1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 625},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 626},
- {"PCIEEP1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 626},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 627},
- {"PCIEEP1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 627},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 628},
- {"PCIEEP1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 628},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 629},
- {"PCIEEP1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 629},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 630},
- {"PCIEEP1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 630},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 631},
- {"PCIEEP1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 631},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 632},
- {"PCIEEP1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 632},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 633},
- {"PCIEEP1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 633},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 634},
- {"PCIEEP1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 634},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 635},
- {"PCIEEP1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 635},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 636},
- {"PCIEEP1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 636},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 637},
- {"PCIEEP1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 637},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 638},
- {"PCIEEP1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 638},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 639},
- {"PCIEEP1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 639},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 640},
- {"PCIEEP1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 640},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 641},
- {"PCIEEP1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 641},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 642},
- {"PCIEEP1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 642},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 643},
- {"PCIEEP1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 643},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 644},
- {"PCIEEP1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 644},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 645},
- {"PCIEEP1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 645},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 646},
- {"PCIEEP1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 646},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 647},
- {"PCIEEP1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 647},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 648},
- {"PCIEEP1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 648},
- {"PCIEEP0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 649},
- {"PCIEEP1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 649},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 650},
- {"PCIEEP1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 650},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 651},
- {"PCIEEP1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 651},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 694},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 694},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 695},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 695},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 696},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 696},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 697},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 697},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 698},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 698},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 699},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 699},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 700},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 700},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 701},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 701},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 702},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 702},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 703},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 703},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 704},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 704},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 705},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 705},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 706},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 706},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 707},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 707},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 708},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 708},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 709},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 709},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 710},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 710},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 711},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 711},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 712},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 712},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 713},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 713},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 714},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 714},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 715},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 715},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 716},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 716},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 717},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 717},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 718},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 718},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 719},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 719},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 720},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 720},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 721},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 721},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 722},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 722},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 723},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 723},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 724},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 724},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 725},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 725},
- {"PCIERC0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 726},
- {"PCIERC1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 726},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 727},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 727},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 728},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 728},
- {"PCM0_DMA_CFG" , 0x1070000010018ull, CVMX_CSR_DB_TYPE_NCB, 64, 729},
- {"PCM1_DMA_CFG" , 0x1070000014018ull, CVMX_CSR_DB_TYPE_NCB, 64, 729},
- {"PCM2_DMA_CFG" , 0x1070000018018ull, CVMX_CSR_DB_TYPE_NCB, 64, 729},
- {"PCM3_DMA_CFG" , 0x107000001c018ull, CVMX_CSR_DB_TYPE_NCB, 64, 729},
- {"PCM0_INT_ENA" , 0x1070000010020ull, CVMX_CSR_DB_TYPE_NCB, 64, 730},
- {"PCM1_INT_ENA" , 0x1070000014020ull, CVMX_CSR_DB_TYPE_NCB, 64, 730},
- {"PCM2_INT_ENA" , 0x1070000018020ull, CVMX_CSR_DB_TYPE_NCB, 64, 730},
- {"PCM3_INT_ENA" , 0x107000001c020ull, CVMX_CSR_DB_TYPE_NCB, 64, 730},
- {"PCM0_INT_SUM" , 0x1070000010028ull, CVMX_CSR_DB_TYPE_NCB, 64, 731},
- {"PCM1_INT_SUM" , 0x1070000014028ull, CVMX_CSR_DB_TYPE_NCB, 64, 731},
- {"PCM2_INT_SUM" , 0x1070000018028ull, CVMX_CSR_DB_TYPE_NCB, 64, 731},
- {"PCM3_INT_SUM" , 0x107000001c028ull, CVMX_CSR_DB_TYPE_NCB, 64, 731},
- {"PCM0_RXADDR" , 0x1070000010068ull, CVMX_CSR_DB_TYPE_NCB, 64, 732},
- {"PCM1_RXADDR" , 0x1070000014068ull, CVMX_CSR_DB_TYPE_NCB, 64, 732},
- {"PCM2_RXADDR" , 0x1070000018068ull, CVMX_CSR_DB_TYPE_NCB, 64, 732},
- {"PCM3_RXADDR" , 0x107000001c068ull, CVMX_CSR_DB_TYPE_NCB, 64, 732},
- {"PCM0_RXCNT" , 0x1070000010060ull, CVMX_CSR_DB_TYPE_NCB, 64, 733},
- {"PCM1_RXCNT" , 0x1070000014060ull, CVMX_CSR_DB_TYPE_NCB, 64, 733},
- {"PCM2_RXCNT" , 0x1070000018060ull, CVMX_CSR_DB_TYPE_NCB, 64, 733},
- {"PCM3_RXCNT" , 0x107000001c060ull, CVMX_CSR_DB_TYPE_NCB, 64, 733},
- {"PCM0_RXMSK0" , 0x10700000100c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 734},
- {"PCM1_RXMSK0" , 0x10700000140c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 734},
- {"PCM2_RXMSK0" , 0x10700000180c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 734},
- {"PCM3_RXMSK0" , 0x107000001c0c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 734},
- {"PCM0_RXMSK1" , 0x10700000100c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 735},
- {"PCM1_RXMSK1" , 0x10700000140c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 735},
- {"PCM2_RXMSK1" , 0x10700000180c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 735},
- {"PCM3_RXMSK1" , 0x107000001c0c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 735},
- {"PCM0_RXMSK2" , 0x10700000100d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 736},
- {"PCM1_RXMSK2" , 0x10700000140d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 736},
- {"PCM2_RXMSK2" , 0x10700000180d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 736},
- {"PCM3_RXMSK2" , 0x107000001c0d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 736},
- {"PCM0_RXMSK3" , 0x10700000100d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 737},
- {"PCM1_RXMSK3" , 0x10700000140d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 737},
- {"PCM2_RXMSK3" , 0x10700000180d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 737},
- {"PCM3_RXMSK3" , 0x107000001c0d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 737},
- {"PCM0_RXMSK4" , 0x10700000100e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 738},
- {"PCM1_RXMSK4" , 0x10700000140e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 738},
- {"PCM2_RXMSK4" , 0x10700000180e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 738},
- {"PCM3_RXMSK4" , 0x107000001c0e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 738},
- {"PCM0_RXMSK5" , 0x10700000100e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 739},
- {"PCM1_RXMSK5" , 0x10700000140e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 739},
- {"PCM2_RXMSK5" , 0x10700000180e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 739},
- {"PCM3_RXMSK5" , 0x107000001c0e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 739},
- {"PCM0_RXMSK6" , 0x10700000100f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"PCM1_RXMSK6" , 0x10700000140f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"PCM2_RXMSK6" , 0x10700000180f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"PCM3_RXMSK6" , 0x107000001c0f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"PCM0_RXMSK7" , 0x10700000100f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 741},
- {"PCM1_RXMSK7" , 0x10700000140f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 741},
- {"PCM2_RXMSK7" , 0x10700000180f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 741},
- {"PCM3_RXMSK7" , 0x107000001c0f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 741},
- {"PCM0_RXSTART" , 0x1070000010058ull, CVMX_CSR_DB_TYPE_NCB, 64, 742},
- {"PCM1_RXSTART" , 0x1070000014058ull, CVMX_CSR_DB_TYPE_NCB, 64, 742},
- {"PCM2_RXSTART" , 0x1070000018058ull, CVMX_CSR_DB_TYPE_NCB, 64, 742},
- {"PCM3_RXSTART" , 0x107000001c058ull, CVMX_CSR_DB_TYPE_NCB, 64, 742},
- {"PCM0_TDM_CFG" , 0x1070000010010ull, CVMX_CSR_DB_TYPE_NCB, 64, 743},
- {"PCM1_TDM_CFG" , 0x1070000014010ull, CVMX_CSR_DB_TYPE_NCB, 64, 743},
- {"PCM2_TDM_CFG" , 0x1070000018010ull, CVMX_CSR_DB_TYPE_NCB, 64, 743},
- {"PCM3_TDM_CFG" , 0x107000001c010ull, CVMX_CSR_DB_TYPE_NCB, 64, 743},
- {"PCM0_TDM_DBG" , 0x1070000010030ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"PCM1_TDM_DBG" , 0x1070000014030ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"PCM2_TDM_DBG" , 0x1070000018030ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"PCM3_TDM_DBG" , 0x107000001c030ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
- {"PCM0_TXADDR" , 0x1070000010050ull, CVMX_CSR_DB_TYPE_NCB, 64, 745},
- {"PCM1_TXADDR" , 0x1070000014050ull, CVMX_CSR_DB_TYPE_NCB, 64, 745},
- {"PCM2_TXADDR" , 0x1070000018050ull, CVMX_CSR_DB_TYPE_NCB, 64, 745},
- {"PCM3_TXADDR" , 0x107000001c050ull, CVMX_CSR_DB_TYPE_NCB, 64, 745},
- {"PCM0_TXCNT" , 0x1070000010048ull, CVMX_CSR_DB_TYPE_NCB, 64, 746},
- {"PCM1_TXCNT" , 0x1070000014048ull, CVMX_CSR_DB_TYPE_NCB, 64, 746},
- {"PCM2_TXCNT" , 0x1070000018048ull, CVMX_CSR_DB_TYPE_NCB, 64, 746},
- {"PCM3_TXCNT" , 0x107000001c048ull, CVMX_CSR_DB_TYPE_NCB, 64, 746},
- {"PCM0_TXMSK0" , 0x1070000010080ull, CVMX_CSR_DB_TYPE_NCB, 64, 747},
- {"PCM1_TXMSK0" , 0x1070000014080ull, CVMX_CSR_DB_TYPE_NCB, 64, 747},
- {"PCM2_TXMSK0" , 0x1070000018080ull, CVMX_CSR_DB_TYPE_NCB, 64, 747},
- {"PCM3_TXMSK0" , 0x107000001c080ull, CVMX_CSR_DB_TYPE_NCB, 64, 747},
- {"PCM0_TXMSK1" , 0x1070000010088ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"PCM1_TXMSK1" , 0x1070000014088ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"PCM2_TXMSK1" , 0x1070000018088ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"PCM3_TXMSK1" , 0x107000001c088ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
- {"PCM0_TXMSK2" , 0x1070000010090ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"PCM1_TXMSK2" , 0x1070000014090ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"PCM2_TXMSK2" , 0x1070000018090ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"PCM3_TXMSK2" , 0x107000001c090ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
- {"PCM0_TXMSK3" , 0x1070000010098ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"PCM1_TXMSK3" , 0x1070000014098ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"PCM2_TXMSK3" , 0x1070000018098ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"PCM3_TXMSK3" , 0x107000001c098ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
- {"PCM0_TXMSK4" , 0x10700000100a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 751},
- {"PCM1_TXMSK4" , 0x10700000140a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 751},
- {"PCM2_TXMSK4" , 0x10700000180a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 751},
- {"PCM3_TXMSK4" , 0x107000001c0a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 751},
- {"PCM0_TXMSK5" , 0x10700000100a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 752},
- {"PCM1_TXMSK5" , 0x10700000140a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 752},
- {"PCM2_TXMSK5" , 0x10700000180a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 752},
- {"PCM3_TXMSK5" , 0x107000001c0a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 752},
- {"PCM0_TXMSK6" , 0x10700000100b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"PCM1_TXMSK6" , 0x10700000140b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"PCM2_TXMSK6" , 0x10700000180b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"PCM3_TXMSK6" , 0x107000001c0b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
- {"PCM0_TXMSK7" , 0x10700000100b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 754},
- {"PCM1_TXMSK7" , 0x10700000140b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 754},
- {"PCM2_TXMSK7" , 0x10700000180b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 754},
- {"PCM3_TXMSK7" , 0x107000001c0b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 754},
- {"PCM0_TXSTART" , 0x1070000010040ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"PCM1_TXSTART" , 0x1070000014040ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"PCM2_TXSTART" , 0x1070000018040ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"PCM3_TXSTART" , 0x107000001c040ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
- {"PCM_CLK0_CFG" , 0x1070000010000ull, CVMX_CSR_DB_TYPE_NCB, 64, 756},
- {"PCM_CLK1_CFG" , 0x1070000014000ull, CVMX_CSR_DB_TYPE_NCB, 64, 756},
- {"PCM_CLK0_DBG" , 0x1070000010038ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"PCM_CLK1_DBG" , 0x1070000014038ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
- {"PCM_CLK0_GEN" , 0x1070000010008ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"PCM_CLK1_GEN" , 0x1070000014008ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS0_AN002_ADV_REG" , 0x11800b0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS0_AN003_ADV_REG" , 0x11800b0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS1_AN000_ADV_REG" , 0x11800b8001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS1_AN001_ADV_REG" , 0x11800b8001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS1_AN002_ADV_REG" , 0x11800b8001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS1_AN003_ADV_REG" , 0x11800b8001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS0_AN002_EXT_ST_REG" , 0x11800b0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS0_AN003_EXT_ST_REG" , 0x11800b0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS1_AN000_EXT_ST_REG" , 0x11800b8001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS1_AN001_EXT_ST_REG" , 0x11800b8001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS1_AN002_EXT_ST_REG" , 0x11800b8001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS1_AN003_EXT_ST_REG" , 0x11800b8001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS0_AN002_LP_ABIL_REG" , 0x11800b0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS0_AN003_LP_ABIL_REG" , 0x11800b0001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS1_AN000_LP_ABIL_REG" , 0x11800b8001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS1_AN001_LP_ABIL_REG" , 0x11800b8001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS1_AN002_LP_ABIL_REG" , 0x11800b8001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS1_AN003_LP_ABIL_REG" , 0x11800b8001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS0_AN002_RESULTS_REG" , 0x11800b0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS0_AN003_RESULTS_REG" , 0x11800b0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS1_AN000_RESULTS_REG" , 0x11800b8001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS1_AN001_RESULTS_REG" , 0x11800b8001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS1_AN002_RESULTS_REG" , 0x11800b8001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS1_AN003_RESULTS_REG" , 0x11800b8001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS0_INT002_EN_REG" , 0x11800b0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS0_INT003_EN_REG" , 0x11800b0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS1_INT000_EN_REG" , 0x11800b8001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS1_INT001_EN_REG" , 0x11800b8001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS1_INT002_EN_REG" , 0x11800b8001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS1_INT003_EN_REG" , 0x11800b8001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS0_INT002_REG" , 0x11800b0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS0_INT003_REG" , 0x11800b0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS1_INT000_REG" , 0x11800b8001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS1_INT001_REG" , 0x11800b8001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS1_INT002_REG" , 0x11800b8001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS1_INT003_REG" , 0x11800b8001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS0_LINK002_TIMER_COUNT_REG", 0x11800b0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS0_LINK003_TIMER_COUNT_REG", 0x11800b0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS1_LINK000_TIMER_COUNT_REG", 0x11800b8001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS1_LINK001_TIMER_COUNT_REG", 0x11800b8001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS1_LINK002_TIMER_COUNT_REG", 0x11800b8001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS1_LINK003_TIMER_COUNT_REG", 0x11800b8001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS0_LOG_ANL002_REG" , 0x11800b0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS0_LOG_ANL003_REG" , 0x11800b0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS1_LOG_ANL000_REG" , 0x11800b8001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS1_LOG_ANL001_REG" , 0x11800b8001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS1_LOG_ANL002_REG" , 0x11800b8001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS1_LOG_ANL003_REG" , 0x11800b8001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS0_MISC002_CTL_REG" , 0x11800b0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS0_MISC003_CTL_REG" , 0x11800b0001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS1_MISC000_CTL_REG" , 0x11800b8001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS1_MISC001_CTL_REG" , 0x11800b8001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS1_MISC002_CTL_REG" , 0x11800b8001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS1_MISC003_CTL_REG" , 0x11800b8001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS0_MR002_CONTROL_REG" , 0x11800b0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS0_MR003_CONTROL_REG" , 0x11800b0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS1_MR000_CONTROL_REG" , 0x11800b8001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS1_MR001_CONTROL_REG" , 0x11800b8001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS1_MR002_CONTROL_REG" , 0x11800b8001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS1_MR003_CONTROL_REG" , 0x11800b8001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS0_MR002_STATUS_REG" , 0x11800b0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS0_MR003_STATUS_REG" , 0x11800b0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS1_MR000_STATUS_REG" , 0x11800b8001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS1_MR001_STATUS_REG" , 0x11800b8001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS1_MR002_STATUS_REG" , 0x11800b8001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS1_MR003_STATUS_REG" , 0x11800b8001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS0_RX002_STATES_REG" , 0x11800b0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS0_RX003_STATES_REG" , 0x11800b0001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS1_RX000_STATES_REG" , 0x11800b8001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS1_RX001_STATES_REG" , 0x11800b8001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS1_RX002_STATES_REG" , 0x11800b8001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS1_RX003_STATES_REG" , 0x11800b8001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS0_RX002_SYNC_REG" , 0x11800b0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS0_RX003_SYNC_REG" , 0x11800b0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS1_RX000_SYNC_REG" , 0x11800b8001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS1_RX001_SYNC_REG" , 0x11800b8001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS1_RX002_SYNC_REG" , 0x11800b8001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS1_RX003_SYNC_REG" , 0x11800b8001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS0_SGM002_AN_ADV_REG" , 0x11800b0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS0_SGM003_AN_ADV_REG" , 0x11800b0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS1_SGM000_AN_ADV_REG" , 0x11800b8001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS1_SGM001_AN_ADV_REG" , 0x11800b8001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS1_SGM002_AN_ADV_REG" , 0x11800b8001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS1_SGM003_AN_ADV_REG" , 0x11800b8001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PCS0_SGM002_LP_ADV_REG" , 0x11800b0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PCS0_SGM003_LP_ADV_REG" , 0x11800b0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PCS1_SGM000_LP_ADV_REG" , 0x11800b8001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PCS1_SGM001_LP_ADV_REG" , 0x11800b8001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PCS1_SGM002_LP_ADV_REG" , 0x11800b8001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PCS1_SGM003_LP_ADV_REG" , 0x11800b8001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PCS0_TX002_STATES_REG" , 0x11800b0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PCS0_TX003_STATES_REG" , 0x11800b0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PCS1_TX000_STATES_REG" , 0x11800b8001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PCS1_TX001_STATES_REG" , 0x11800b8001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PCS1_TX002_STATES_REG" , 0x11800b8001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PCS1_TX003_STATES_REG" , 0x11800b8001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PCS0_TX_RX002_POLARITY_REG" , 0x11800b0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PCS0_TX_RX003_POLARITY_REG" , 0x11800b0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PCS1_TX_RX000_POLARITY_REG" , 0x11800b8001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PCS1_TX_RX001_POLARITY_REG" , 0x11800b8001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PCS1_TX_RX002_POLARITY_REG" , 0x11800b8001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PCS1_TX_RX003_POLARITY_REG" , 0x11800b8001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PCSX0_10GBX_STATUS_REG" , 0x11800b0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PCSX1_10GBX_STATUS_REG" , 0x11800b8000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PCSX0_BIST_STATUS_REG" , 0x11800b0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PCSX1_BIST_STATUS_REG" , 0x11800b8000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800b0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PCSX1_BIT_LOCK_STATUS_REG" , 0x11800b8000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PCSX0_CONTROL1_REG" , 0x11800b0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PCSX1_CONTROL1_REG" , 0x11800b8000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PCSX0_CONTROL2_REG" , 0x11800b0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PCSX1_CONTROL2_REG" , 0x11800b8000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PCSX0_INT_EN_REG" , 0x11800b0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PCSX1_INT_EN_REG" , 0x11800b8000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PCSX0_INT_REG" , 0x11800b0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PCSX1_INT_REG" , 0x11800b8000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PCSX0_LOG_ANL_REG" , 0x11800b0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PCSX1_LOG_ANL_REG" , 0x11800b8000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PCSX0_MISC_CTL_REG" , 0x11800b0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PCSX1_MISC_CTL_REG" , 0x11800b8000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PCSX0_RX_SYNC_STATES_REG" , 0x11800b0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PCSX1_RX_SYNC_STATES_REG" , 0x11800b8000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PCSX0_SPD_ABIL_REG" , 0x11800b0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PCSX1_SPD_ABIL_REG" , 0x11800b8000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PCSX0_STATUS1_REG" , 0x11800b0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PCSX1_STATUS1_REG" , 0x11800b8000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PCSX0_STATUS2_REG" , 0x11800b0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PCSX1_STATUS2_REG" , 0x11800b8000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PCSX0_TX_RX_POLARITY_REG" , 0x11800b0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PCSX1_TX_RX_POLARITY_REG" , 0x11800b8000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PCSX0_TX_RX_STATES_REG" , 0x11800b0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PCSX1_TX_RX_STATES_REG" , 0x11800b8000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PEM0_BAR1_INDEX000" , 0x11800c00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX001" , 0x11800c00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX002" , 0x11800c00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX003" , 0x11800c00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX004" , 0x11800c00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX005" , 0x11800c00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX006" , 0x11800c00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX007" , 0x11800c00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX008" , 0x11800c00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX009" , 0x11800c00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX010" , 0x11800c00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX011" , 0x11800c0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX012" , 0x11800c0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX013" , 0x11800c0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX014" , 0x11800c0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR1_INDEX015" , 0x11800c0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX000" , 0x11800c10000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX001" , 0x11800c10000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX002" , 0x11800c10000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX003" , 0x11800c10000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX004" , 0x11800c10000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX005" , 0x11800c10000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX006" , 0x11800c10000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX007" , 0x11800c10000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX008" , 0x11800c10000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX009" , 0x11800c10000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX010" , 0x11800c10000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX011" , 0x11800c1000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX012" , 0x11800c1000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX013" , 0x11800c1000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX014" , 0x11800c1000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BAR1_INDEX015" , 0x11800c1000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BAR2_MASK" , 0x11800c0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PEM1_BAR2_MASK" , 0x11800c1000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PEM0_BAR_CTL" , 0x11800c0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PEM1_BAR_CTL" , 0x11800c1000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PEM0_BIST_STATUS" , 0x11800c0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PEM1_BIST_STATUS" , 0x11800c1000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PEM0_BIST_STATUS2" , 0x11800c0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PEM1_BIST_STATUS2" , 0x11800c1000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PEM0_CFG_RD" , 0x11800c0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PEM1_CFG_RD" , 0x11800c1000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PEM0_CFG_WR" , 0x11800c0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PEM1_CFG_WR" , 0x11800c1000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PEM0_CPL_LUT_VALID" , 0x11800c0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PEM1_CPL_LUT_VALID" , 0x11800c1000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PEM0_CTL_STATUS" , 0x11800c0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PEM1_CTL_STATUS" , 0x11800c1000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PEM0_DBG_INFO" , 0x11800c0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PEM1_DBG_INFO" , 0x11800c1000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PEM0_DBG_INFO_EN" , 0x11800c00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PEM1_DBG_INFO_EN" , 0x11800c10000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PEM0_DIAG_STATUS" , 0x11800c0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"PEM1_DIAG_STATUS" , 0x11800c1000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"PEM0_INB_READ_CREDITS" , 0x11800c0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"PEM1_INB_READ_CREDITS" , 0x11800c1000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"PEM0_INT_ENB" , 0x11800c0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"PEM1_INT_ENB" , 0x11800c1000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"PEM0_INT_ENB_INT" , 0x11800c0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"PEM1_INT_ENB_INT" , 0x11800c1000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"PEM0_INT_SUM" , 0x11800c0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"PEM1_INT_SUM" , 0x11800c1000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"PEM0_P2N_BAR0_START" , 0x11800c0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PEM1_P2N_BAR0_START" , 0x11800c1000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PEM0_P2N_BAR1_START" , 0x11800c0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PEM1_P2N_BAR1_START" , 0x11800c1000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PEM0_P2N_BAR2_START" , 0x11800c0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"PEM1_P2N_BAR2_START" , 0x11800c1000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"PEM0_TLP_CREDITS" , 0x11800c0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"PEM1_TLP_CREDITS" , 0x11800c1000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"PIP_ALT_SKIP_CFG0" , 0x11800a0002a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
- {"PIP_ALT_SKIP_CFG1" , 0x11800a0002a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
- {"PIP_ALT_SKIP_CFG2" , 0x11800a0002a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
- {"PIP_ALT_SKIP_CFG3" , 0x11800a0002a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 812},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 813},
- {"PIP_BSEL_EXT_CFG0" , 0x11800a0002800ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PIP_BSEL_EXT_CFG1" , 0x11800a0002810ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PIP_BSEL_EXT_CFG2" , 0x11800a0002820ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PIP_BSEL_EXT_CFG3" , 0x11800a0002830ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PIP_BSEL_EXT_POS0" , 0x11800a0002808ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
- {"PIP_BSEL_EXT_POS1" , 0x11800a0002818ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
- {"PIP_BSEL_EXT_POS2" , 0x11800a0002828ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
- {"PIP_BSEL_EXT_POS3" , 0x11800a0002838ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
- {"PIP_BSEL_TBL_ENT0" , 0x11800a0003000ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT1" , 0x11800a0003008ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT2" , 0x11800a0003010ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT3" , 0x11800a0003018ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT4" , 0x11800a0003020ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT5" , 0x11800a0003028ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT6" , 0x11800a0003030ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT7" , 0x11800a0003038ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT8" , 0x11800a0003040ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT9" , 0x11800a0003048ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT10" , 0x11800a0003050ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT11" , 0x11800a0003058ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT12" , 0x11800a0003060ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT13" , 0x11800a0003068ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT14" , 0x11800a0003070ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT15" , 0x11800a0003078ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT16" , 0x11800a0003080ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT17" , 0x11800a0003088ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT18" , 0x11800a0003090ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT19" , 0x11800a0003098ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT20" , 0x11800a00030a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT21" , 0x11800a00030a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT22" , 0x11800a00030b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT23" , 0x11800a00030b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT24" , 0x11800a00030c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT25" , 0x11800a00030c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT26" , 0x11800a00030d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT27" , 0x11800a00030d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT28" , 0x11800a00030e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT29" , 0x11800a00030e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT30" , 0x11800a00030f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT31" , 0x11800a00030f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT32" , 0x11800a0003100ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT33" , 0x11800a0003108ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT34" , 0x11800a0003110ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT35" , 0x11800a0003118ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT36" , 0x11800a0003120ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT37" , 0x11800a0003128ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT38" , 0x11800a0003130ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT39" , 0x11800a0003138ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT40" , 0x11800a0003140ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT41" , 0x11800a0003148ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT42" , 0x11800a0003150ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT43" , 0x11800a0003158ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT44" , 0x11800a0003160ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT45" , 0x11800a0003168ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT46" , 0x11800a0003170ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT47" , 0x11800a0003178ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT48" , 0x11800a0003180ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT49" , 0x11800a0003188ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT50" , 0x11800a0003190ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT51" , 0x11800a0003198ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT52" , 0x11800a00031a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT53" , 0x11800a00031a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT54" , 0x11800a00031b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT55" , 0x11800a00031b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT56" , 0x11800a00031c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT57" , 0x11800a00031c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT58" , 0x11800a00031d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT59" , 0x11800a00031d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT60" , 0x11800a00031e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT61" , 0x11800a00031e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT62" , 0x11800a00031f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT63" , 0x11800a00031f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT64" , 0x11800a0003200ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT65" , 0x11800a0003208ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT66" , 0x11800a0003210ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT67" , 0x11800a0003218ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT68" , 0x11800a0003220ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT69" , 0x11800a0003228ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT70" , 0x11800a0003230ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT71" , 0x11800a0003238ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT72" , 0x11800a0003240ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT73" , 0x11800a0003248ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT74" , 0x11800a0003250ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT75" , 0x11800a0003258ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT76" , 0x11800a0003260ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT77" , 0x11800a0003268ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT78" , 0x11800a0003270ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT79" , 0x11800a0003278ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT80" , 0x11800a0003280ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT81" , 0x11800a0003288ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT82" , 0x11800a0003290ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT83" , 0x11800a0003298ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT84" , 0x11800a00032a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT85" , 0x11800a00032a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT86" , 0x11800a00032b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT87" , 0x11800a00032b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT88" , 0x11800a00032c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT89" , 0x11800a00032c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT90" , 0x11800a00032d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT91" , 0x11800a00032d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT92" , 0x11800a00032e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT93" , 0x11800a00032e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT94" , 0x11800a00032f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT95" , 0x11800a00032f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT96" , 0x11800a0003300ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT97" , 0x11800a0003308ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT98" , 0x11800a0003310ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT99" , 0x11800a0003318ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT100" , 0x11800a0003320ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT101" , 0x11800a0003328ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT102" , 0x11800a0003330ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT103" , 0x11800a0003338ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT104" , 0x11800a0003340ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT105" , 0x11800a0003348ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT106" , 0x11800a0003350ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT107" , 0x11800a0003358ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT108" , 0x11800a0003360ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT109" , 0x11800a0003368ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT110" , 0x11800a0003370ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT111" , 0x11800a0003378ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT112" , 0x11800a0003380ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT113" , 0x11800a0003388ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT114" , 0x11800a0003390ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT115" , 0x11800a0003398ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT116" , 0x11800a00033a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT117" , 0x11800a00033a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT118" , 0x11800a00033b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT119" , 0x11800a00033b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT120" , 0x11800a00033c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT121" , 0x11800a00033c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT122" , 0x11800a00033d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT123" , 0x11800a00033d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT124" , 0x11800a00033e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT125" , 0x11800a00033e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT126" , 0x11800a00033f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT127" , 0x11800a00033f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT128" , 0x11800a0003400ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT129" , 0x11800a0003408ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT130" , 0x11800a0003410ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT131" , 0x11800a0003418ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT132" , 0x11800a0003420ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT133" , 0x11800a0003428ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT134" , 0x11800a0003430ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT135" , 0x11800a0003438ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT136" , 0x11800a0003440ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT137" , 0x11800a0003448ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT138" , 0x11800a0003450ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT139" , 0x11800a0003458ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT140" , 0x11800a0003460ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT141" , 0x11800a0003468ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT142" , 0x11800a0003470ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT143" , 0x11800a0003478ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT144" , 0x11800a0003480ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT145" , 0x11800a0003488ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT146" , 0x11800a0003490ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT147" , 0x11800a0003498ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT148" , 0x11800a00034a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT149" , 0x11800a00034a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT150" , 0x11800a00034b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT151" , 0x11800a00034b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT152" , 0x11800a00034c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT153" , 0x11800a00034c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT154" , 0x11800a00034d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT155" , 0x11800a00034d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT156" , 0x11800a00034e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT157" , 0x11800a00034e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT158" , 0x11800a00034f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT159" , 0x11800a00034f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT160" , 0x11800a0003500ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT161" , 0x11800a0003508ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT162" , 0x11800a0003510ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT163" , 0x11800a0003518ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT164" , 0x11800a0003520ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT165" , 0x11800a0003528ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT166" , 0x11800a0003530ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT167" , 0x11800a0003538ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT168" , 0x11800a0003540ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT169" , 0x11800a0003548ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT170" , 0x11800a0003550ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT171" , 0x11800a0003558ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT172" , 0x11800a0003560ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT173" , 0x11800a0003568ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT174" , 0x11800a0003570ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT175" , 0x11800a0003578ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT176" , 0x11800a0003580ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT177" , 0x11800a0003588ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT178" , 0x11800a0003590ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT179" , 0x11800a0003598ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT180" , 0x11800a00035a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT181" , 0x11800a00035a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT182" , 0x11800a00035b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT183" , 0x11800a00035b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT184" , 0x11800a00035c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT185" , 0x11800a00035c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT186" , 0x11800a00035d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT187" , 0x11800a00035d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT188" , 0x11800a00035e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT189" , 0x11800a00035e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT190" , 0x11800a00035f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT191" , 0x11800a00035f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT192" , 0x11800a0003600ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT193" , 0x11800a0003608ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT194" , 0x11800a0003610ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT195" , 0x11800a0003618ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT196" , 0x11800a0003620ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT197" , 0x11800a0003628ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT198" , 0x11800a0003630ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT199" , 0x11800a0003638ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT200" , 0x11800a0003640ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT201" , 0x11800a0003648ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT202" , 0x11800a0003650ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT203" , 0x11800a0003658ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT204" , 0x11800a0003660ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT205" , 0x11800a0003668ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT206" , 0x11800a0003670ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT207" , 0x11800a0003678ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT208" , 0x11800a0003680ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT209" , 0x11800a0003688ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT210" , 0x11800a0003690ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT211" , 0x11800a0003698ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT212" , 0x11800a00036a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT213" , 0x11800a00036a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT214" , 0x11800a00036b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT215" , 0x11800a00036b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT216" , 0x11800a00036c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT217" , 0x11800a00036c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT218" , 0x11800a00036d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT219" , 0x11800a00036d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT220" , 0x11800a00036e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT221" , 0x11800a00036e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT222" , 0x11800a00036f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT223" , 0x11800a00036f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT224" , 0x11800a0003700ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT225" , 0x11800a0003708ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT226" , 0x11800a0003710ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT227" , 0x11800a0003718ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT228" , 0x11800a0003720ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT229" , 0x11800a0003728ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT230" , 0x11800a0003730ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT231" , 0x11800a0003738ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT232" , 0x11800a0003740ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT233" , 0x11800a0003748ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT234" , 0x11800a0003750ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT235" , 0x11800a0003758ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT236" , 0x11800a0003760ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT237" , 0x11800a0003768ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT238" , 0x11800a0003770ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT239" , 0x11800a0003778ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT240" , 0x11800a0003780ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT241" , 0x11800a0003788ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT242" , 0x11800a0003790ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT243" , 0x11800a0003798ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT244" , 0x11800a00037a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT245" , 0x11800a00037a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT246" , 0x11800a00037b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT247" , 0x11800a00037b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT248" , 0x11800a00037c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT249" , 0x11800a00037c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT250" , 0x11800a00037d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT251" , 0x11800a00037d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT252" , 0x11800a00037e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT253" , 0x11800a00037e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT254" , 0x11800a00037f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT255" , 0x11800a00037f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT256" , 0x11800a0003800ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT257" , 0x11800a0003808ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT258" , 0x11800a0003810ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT259" , 0x11800a0003818ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT260" , 0x11800a0003820ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT261" , 0x11800a0003828ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT262" , 0x11800a0003830ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT263" , 0x11800a0003838ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT264" , 0x11800a0003840ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT265" , 0x11800a0003848ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT266" , 0x11800a0003850ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT267" , 0x11800a0003858ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT268" , 0x11800a0003860ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT269" , 0x11800a0003868ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT270" , 0x11800a0003870ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT271" , 0x11800a0003878ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT272" , 0x11800a0003880ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT273" , 0x11800a0003888ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT274" , 0x11800a0003890ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT275" , 0x11800a0003898ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT276" , 0x11800a00038a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT277" , 0x11800a00038a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT278" , 0x11800a00038b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT279" , 0x11800a00038b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT280" , 0x11800a00038c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT281" , 0x11800a00038c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT282" , 0x11800a00038d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT283" , 0x11800a00038d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT284" , 0x11800a00038e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT285" , 0x11800a00038e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT286" , 0x11800a00038f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT287" , 0x11800a00038f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT288" , 0x11800a0003900ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT289" , 0x11800a0003908ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT290" , 0x11800a0003910ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT291" , 0x11800a0003918ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT292" , 0x11800a0003920ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT293" , 0x11800a0003928ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT294" , 0x11800a0003930ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT295" , 0x11800a0003938ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT296" , 0x11800a0003940ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT297" , 0x11800a0003948ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT298" , 0x11800a0003950ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT299" , 0x11800a0003958ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT300" , 0x11800a0003960ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT301" , 0x11800a0003968ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT302" , 0x11800a0003970ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT303" , 0x11800a0003978ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT304" , 0x11800a0003980ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT305" , 0x11800a0003988ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT306" , 0x11800a0003990ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT307" , 0x11800a0003998ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT308" , 0x11800a00039a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT309" , 0x11800a00039a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT310" , 0x11800a00039b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT311" , 0x11800a00039b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT312" , 0x11800a00039c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT313" , 0x11800a00039c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT314" , 0x11800a00039d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT315" , 0x11800a00039d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT316" , 0x11800a00039e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT317" , 0x11800a00039e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT318" , 0x11800a00039f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT319" , 0x11800a00039f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT320" , 0x11800a0003a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT321" , 0x11800a0003a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT322" , 0x11800a0003a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT323" , 0x11800a0003a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT324" , 0x11800a0003a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT325" , 0x11800a0003a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT326" , 0x11800a0003a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT327" , 0x11800a0003a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT328" , 0x11800a0003a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT329" , 0x11800a0003a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT330" , 0x11800a0003a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT331" , 0x11800a0003a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT332" , 0x11800a0003a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT333" , 0x11800a0003a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT334" , 0x11800a0003a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT335" , 0x11800a0003a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT336" , 0x11800a0003a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT337" , 0x11800a0003a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT338" , 0x11800a0003a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT339" , 0x11800a0003a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT340" , 0x11800a0003aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT341" , 0x11800a0003aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT342" , 0x11800a0003ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT343" , 0x11800a0003ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT344" , 0x11800a0003ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT345" , 0x11800a0003ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT346" , 0x11800a0003ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT347" , 0x11800a0003ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT348" , 0x11800a0003ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT349" , 0x11800a0003ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT350" , 0x11800a0003af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT351" , 0x11800a0003af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT352" , 0x11800a0003b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT353" , 0x11800a0003b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT354" , 0x11800a0003b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT355" , 0x11800a0003b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT356" , 0x11800a0003b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT357" , 0x11800a0003b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT358" , 0x11800a0003b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT359" , 0x11800a0003b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT360" , 0x11800a0003b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT361" , 0x11800a0003b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT362" , 0x11800a0003b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT363" , 0x11800a0003b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT364" , 0x11800a0003b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT365" , 0x11800a0003b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT366" , 0x11800a0003b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT367" , 0x11800a0003b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT368" , 0x11800a0003b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT369" , 0x11800a0003b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT370" , 0x11800a0003b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT371" , 0x11800a0003b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT372" , 0x11800a0003ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT373" , 0x11800a0003ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT374" , 0x11800a0003bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT375" , 0x11800a0003bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT376" , 0x11800a0003bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT377" , 0x11800a0003bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT378" , 0x11800a0003bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT379" , 0x11800a0003bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT380" , 0x11800a0003be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT381" , 0x11800a0003be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT382" , 0x11800a0003bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT383" , 0x11800a0003bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT384" , 0x11800a0003c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT385" , 0x11800a0003c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT386" , 0x11800a0003c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT387" , 0x11800a0003c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT388" , 0x11800a0003c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT389" , 0x11800a0003c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT390" , 0x11800a0003c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT391" , 0x11800a0003c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT392" , 0x11800a0003c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT393" , 0x11800a0003c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT394" , 0x11800a0003c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT395" , 0x11800a0003c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT396" , 0x11800a0003c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT397" , 0x11800a0003c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT398" , 0x11800a0003c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT399" , 0x11800a0003c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT400" , 0x11800a0003c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT401" , 0x11800a0003c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT402" , 0x11800a0003c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT403" , 0x11800a0003c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT404" , 0x11800a0003ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT405" , 0x11800a0003ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT406" , 0x11800a0003cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT407" , 0x11800a0003cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT408" , 0x11800a0003cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT409" , 0x11800a0003cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT410" , 0x11800a0003cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT411" , 0x11800a0003cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT412" , 0x11800a0003ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT413" , 0x11800a0003ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT414" , 0x11800a0003cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT415" , 0x11800a0003cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT416" , 0x11800a0003d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT417" , 0x11800a0003d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT418" , 0x11800a0003d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT419" , 0x11800a0003d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT420" , 0x11800a0003d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT421" , 0x11800a0003d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT422" , 0x11800a0003d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT423" , 0x11800a0003d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT424" , 0x11800a0003d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT425" , 0x11800a0003d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT426" , 0x11800a0003d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT427" , 0x11800a0003d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT428" , 0x11800a0003d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT429" , 0x11800a0003d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT430" , 0x11800a0003d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT431" , 0x11800a0003d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT432" , 0x11800a0003d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT433" , 0x11800a0003d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT434" , 0x11800a0003d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT435" , 0x11800a0003d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT436" , 0x11800a0003da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT437" , 0x11800a0003da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT438" , 0x11800a0003db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT439" , 0x11800a0003db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT440" , 0x11800a0003dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT441" , 0x11800a0003dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT442" , 0x11800a0003dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT443" , 0x11800a0003dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT444" , 0x11800a0003de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT445" , 0x11800a0003de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT446" , 0x11800a0003df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT447" , 0x11800a0003df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT448" , 0x11800a0003e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT449" , 0x11800a0003e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT450" , 0x11800a0003e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT451" , 0x11800a0003e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT452" , 0x11800a0003e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT453" , 0x11800a0003e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT454" , 0x11800a0003e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT455" , 0x11800a0003e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT456" , 0x11800a0003e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT457" , 0x11800a0003e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT458" , 0x11800a0003e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT459" , 0x11800a0003e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT460" , 0x11800a0003e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT461" , 0x11800a0003e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT462" , 0x11800a0003e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT463" , 0x11800a0003e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT464" , 0x11800a0003e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT465" , 0x11800a0003e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT466" , 0x11800a0003e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT467" , 0x11800a0003e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT468" , 0x11800a0003ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT469" , 0x11800a0003ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT470" , 0x11800a0003eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT471" , 0x11800a0003eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT472" , 0x11800a0003ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT473" , 0x11800a0003ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT474" , 0x11800a0003ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT475" , 0x11800a0003ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT476" , 0x11800a0003ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT477" , 0x11800a0003ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT478" , 0x11800a0003ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT479" , 0x11800a0003ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT480" , 0x11800a0003f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT481" , 0x11800a0003f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT482" , 0x11800a0003f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT483" , 0x11800a0003f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT484" , 0x11800a0003f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT485" , 0x11800a0003f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT486" , 0x11800a0003f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT487" , 0x11800a0003f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT488" , 0x11800a0003f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT489" , 0x11800a0003f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT490" , 0x11800a0003f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT491" , 0x11800a0003f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT492" , 0x11800a0003f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT493" , 0x11800a0003f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT494" , 0x11800a0003f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT495" , 0x11800a0003f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT496" , 0x11800a0003f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT497" , 0x11800a0003f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT498" , 0x11800a0003f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT499" , 0x11800a0003f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT500" , 0x11800a0003fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT501" , 0x11800a0003fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT502" , 0x11800a0003fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT503" , 0x11800a0003fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT504" , 0x11800a0003fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT505" , 0x11800a0003fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT506" , 0x11800a0003fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT507" , 0x11800a0003fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT508" , 0x11800a0003fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT509" , 0x11800a0003fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT510" , 0x11800a0003ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_BSEL_TBL_ENT511" , 0x11800a0003ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_CLKEN" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 817},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
- {"PIP_DSA_SRC_GRP" , 0x11800a0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 819},
- {"PIP_DSA_VID_GRP" , 0x11800a0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 820},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 821},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 822},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 823},
- {"PIP_HG_PRI_QOS" , 0x11800a00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG16" , 0x11800a0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG17" , 0x11800a0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG18" , 0x11800a0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG19" , 0x11800a0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_PRT_CFGB0" , 0x11800a0008000ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB1" , 0x11800a0008008ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB2" , 0x11800a0008010ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB3" , 0x11800a0008018ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB16" , 0x11800a0008080ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB17" , 0x11800a0008088ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB18" , 0x11800a0008090ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB19" , 0x11800a0008098ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB32" , 0x11800a0008100ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB33" , 0x11800a0008108ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB34" , 0x11800a0008110ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB35" , 0x11800a0008118ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB36" , 0x11800a0008120ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB37" , 0x11800a0008128ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB38" , 0x11800a0008130ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_CFGB39" , 0x11800a0008138ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG16" , 0x11800a0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG17" , 0x11800a0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG18" , 0x11800a0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG19" , 0x11800a0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT16" , 0x11800a0000d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT17" , 0x11800a0000d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT18" , 0x11800a0000da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT19" , 0x11800a0000df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT36" , 0x11800a0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT37" , 0x11800a0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT38" , 0x11800a00013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT0_PRT39" , 0x11800a0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT10_PRT0" , 0x11800a0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT1" , 0x11800a0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT2" , 0x11800a00014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT3" , 0x11800a00014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT16" , 0x11800a0001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT17" , 0x11800a0001590ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT18" , 0x11800a00015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT19" , 0x11800a00015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT32" , 0x11800a0001680ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT33" , 0x11800a0001690ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT34" , 0x11800a00016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT35" , 0x11800a00016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT36" , 0x11800a00016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT37" , 0x11800a00016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT38" , 0x11800a00016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT10_PRT39" , 0x11800a00016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT11_PRT0" , 0x11800a0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT1" , 0x11800a0001498ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT2" , 0x11800a00014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT3" , 0x11800a00014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT16" , 0x11800a0001588ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT17" , 0x11800a0001598ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT18" , 0x11800a00015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT19" , 0x11800a00015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT32" , 0x11800a0001688ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT33" , 0x11800a0001698ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT34" , 0x11800a00016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT35" , 0x11800a00016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT36" , 0x11800a00016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT37" , 0x11800a00016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT38" , 0x11800a00016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT11_PRT39" , 0x11800a00016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT16" , 0x11800a0000d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT17" , 0x11800a0000d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT18" , 0x11800a0000da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT19" , 0x11800a0000df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT36" , 0x11800a0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT37" , 0x11800a0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT38" , 0x11800a00013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT1_PRT39" , 0x11800a0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT16" , 0x11800a0000d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT17" , 0x11800a0000d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT18" , 0x11800a0000db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT19" , 0x11800a0000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT36" , 0x11800a0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT37" , 0x11800a00013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT38" , 0x11800a00013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT2_PRT39" , 0x11800a0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT16" , 0x11800a0000d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT17" , 0x11800a0000d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT18" , 0x11800a0000db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT19" , 0x11800a0000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT36" , 0x11800a0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT37" , 0x11800a00013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT38" , 0x11800a00013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT3_PRT39" , 0x11800a0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT16" , 0x11800a0000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT17" , 0x11800a0000d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT18" , 0x11800a0000dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT19" , 0x11800a0000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT36" , 0x11800a0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT37" , 0x11800a00013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT38" , 0x11800a0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT4_PRT39" , 0x11800a0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT16" , 0x11800a0000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT17" , 0x11800a0000d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT18" , 0x11800a0000dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT19" , 0x11800a0000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT36" , 0x11800a0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT37" , 0x11800a00013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT38" , 0x11800a0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT5_PRT39" , 0x11800a0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT16" , 0x11800a0000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT17" , 0x11800a0000d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT18" , 0x11800a0000dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT19" , 0x11800a0000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT36" , 0x11800a0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT37" , 0x11800a00013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT38" , 0x11800a0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT6_PRT39" , 0x11800a0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT16" , 0x11800a0000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT17" , 0x11800a0000d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT18" , 0x11800a0000dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT19" , 0x11800a0000e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT36" , 0x11800a0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT37" , 0x11800a00013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT38" , 0x11800a0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT7_PRT39" , 0x11800a0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT16" , 0x11800a0000d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT17" , 0x11800a0000d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT18" , 0x11800a0000de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT19" , 0x11800a0000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT36" , 0x11800a0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT37" , 0x11800a00013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT38" , 0x11800a0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT8_PRT39" , 0x11800a0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT16" , 0x11800a0000d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT17" , 0x11800a0000d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT18" , 0x11800a0000de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT19" , 0x11800a0000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT36" , 0x11800a0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT37" , 0x11800a00013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT38" , 0x11800a0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT9_PRT39" , 0x11800a0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS16" , 0x11800a0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS17" , 0x11800a0001c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS18" , 0x11800a0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS19" , 0x11800a0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS36" , 0x11800a0001e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS37" , 0x11800a0001eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS38" , 0x11800a0001ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_ERRS39" , 0x11800a0001ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS16" , 0x11800a0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS17" , 0x11800a0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS18" , 0x11800a0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS19" , 0x11800a0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS36" , 0x11800a0001e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS37" , 0x11800a0001ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS38" , 0x11800a0001ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_OCTS39" , 0x11800a0001ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS16" , 0x11800a0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS17" , 0x11800a0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS18" , 0x11800a0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS19" , 0x11800a0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS36" , 0x11800a0001e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS37" , 0x11800a0001ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS38" , 0x11800a0001ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_STAT_INB_PKTS39" , 0x11800a0001ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"PIP_VLAN_ETYPES0" , 0x11800a00001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"PIP_VLAN_ETYPES1" , 0x11800a00001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 865},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 869},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 870},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 871},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
- {"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 874},
- {"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 875},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 876},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 877},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 878},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 879},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 880},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 883},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 884},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 885},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 886},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 887},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 888},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 889},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 890},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 891},
- {"PKO_REG_PREEMPT" , 0x1180050000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 893},
- {"PKO_REG_QUEUE_PREEMPT" , 0x1180050000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 894},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
- {"PKO_REG_TIMESTAMP" , 0x1180050000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 898},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 899},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 900},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 901},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 902},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 902},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 902},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 902},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 902},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 902},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 902},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 902},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 903},
- {"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 904},
- {"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 905},
- {"POW_IQ_THR0" , 0x16700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 906},
- {"POW_IQ_THR1" , 0x16700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 906},
- {"POW_IQ_THR2" , 0x16700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 906},
- {"POW_IQ_THR3" , 0x16700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 906},
- {"POW_IQ_THR4" , 0x16700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 906},
- {"POW_IQ_THR5" , 0x16700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 906},
- {"POW_IQ_THR6" , 0x16700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 906},
- {"POW_IQ_THR7" , 0x16700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 906},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 907},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 908},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 909},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 911},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 911},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 911},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 911},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 911},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 911},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 911},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 911},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 912},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 912},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 912},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 912},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 912},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 912},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 912},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 912},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 913},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 914},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 915},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 915},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 915},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 915},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 915},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 915},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 915},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 915},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 916},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 929},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 934},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 935},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 936},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 937},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 938},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"RNM_EER_DBG" , 0x1180040000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"RNM_EER_KEY" , 0x1180040000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"RNM_SERIAL_NUM" , 0x1180040000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"SLI_BIST_STATUS" , 0x11f0000010580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_CTL_PORT0" , 0x11f0000010050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_CTL_PORT1" , 0x11f0000010060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_CTL_STATUS" , 0x11f0000010570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_DATA_OUT_CNT" , 0x11f00000105f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 952},
- {"SLI_DBG_DATA" , 0x11f0000010310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 953},
- {"SLI_DBG_SELECT" , 0x11f0000010300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 954},
- {"SLI_DMA0_CNT" , 0x11f0000010400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 955},
- {"SLI_DMA1_CNT" , 0x11f0000010410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 955},
- {"SLI_DMA0_INT_LEVEL" , 0x11f00000103e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 956},
- {"SLI_DMA1_INT_LEVEL" , 0x11f00000103f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 956},
- {"SLI_DMA0_TIM" , 0x11f0000010420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 957},
- {"SLI_DMA1_TIM" , 0x11f0000010430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 957},
- {"SLI_INT_ENB_CIU" , 0x11f0000013cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 958},
- {"SLI_INT_ENB_PORT0" , 0x11f0000010340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 959},
- {"SLI_INT_ENB_PORT1" , 0x11f0000010350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 959},
- {"SLI_INT_SUM" , 0x11f0000010330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_LAST_WIN_RDATA0" , 0x11f0000010600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 961},
- {"SLI_LAST_WIN_RDATA1" , 0x11f0000010610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 962},
- {"SLI_LAST_WIN_RDATA2" , 0x11f00000106c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 963},
- {"SLI_LAST_WIN_RDATA3" , 0x11f00000106d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 964},
- {"SLI_MAC_CREDIT_CNT" , 0x11f0000013d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 965},
- {"SLI_MAC_CREDIT_CNT2" , 0x11f0000013e10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 966},
- {"SLI_MAC_NUMBER" , 0x3e00ull, CVMX_CSR_DB_TYPE_PEXP, 64, 967},
- {"SLI_MEM_ACCESS_CTL" , 0x11f00000102f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 968},
- {"SLI_MEM_ACCESS_SUBID12" , 0x11f00000100e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID13" , 0x11f00000100f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID14" , 0x11f0000010100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID15" , 0x11f0000010110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID16" , 0x11f0000010120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID17" , 0x11f0000010130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID18" , 0x11f0000010140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID19" , 0x11f0000010150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID20" , 0x11f0000010160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID21" , 0x11f0000010170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID22" , 0x11f0000010180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID23" , 0x11f0000010190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID24" , 0x11f00000101a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID25" , 0x11f00000101b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID26" , 0x11f00000101c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MEM_ACCESS_SUBID27" , 0x11f00000101d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_MSI_ENB0" , 0x11f0000013c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 970},
- {"SLI_MSI_ENB1" , 0x11f0000013c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 971},
- {"SLI_MSI_ENB2" , 0x11f0000013c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 972},
- {"SLI_MSI_ENB3" , 0x11f0000013c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 973},
- {"SLI_MSI_RCV0" , 0x11f0000013c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 974},
- {"SLI_MSI_RCV1" , 0x11f0000013c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 975},
- {"SLI_MSI_RCV2" , 0x11f0000013c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 976},
- {"SLI_MSI_RCV3" , 0x11f0000013c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MSI_RD_MAP" , 0x11f0000013ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 978},
- {"SLI_MSI_W1C_ENB0" , 0x11f0000013cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 979},
- {"SLI_MSI_W1C_ENB1" , 0x11f0000013d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 980},
- {"SLI_MSI_W1C_ENB2" , 0x11f0000013d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 981},
- {"SLI_MSI_W1C_ENB3" , 0x11f0000013d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 982},
- {"SLI_MSI_W1S_ENB0" , 0x11f0000013d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 983},
- {"SLI_MSI_W1S_ENB1" , 0x11f0000013d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 984},
- {"SLI_MSI_W1S_ENB2" , 0x11f0000013d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 985},
- {"SLI_MSI_W1S_ENB3" , 0x11f0000013d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 986},
- {"SLI_MSI_WR_MAP" , 0x11f0000013c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 987},
- {"SLI_PCIE_MSI_RCV" , 0x11f0000013cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 988},
- {"SLI_PCIE_MSI_RCV_B1" , 0x11f0000010650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 989},
- {"SLI_PCIE_MSI_RCV_B2" , 0x11f0000010660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 990},
- {"SLI_PCIE_MSI_RCV_B3" , 0x11f0000010670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 991},
- {"SLI_PKT0_CNTS" , 0x11f0000012400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT1_CNTS" , 0x11f0000012410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT2_CNTS" , 0x11f0000012420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT3_CNTS" , 0x11f0000012430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT4_CNTS" , 0x11f0000012440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT5_CNTS" , 0x11f0000012450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT6_CNTS" , 0x11f0000012460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT7_CNTS" , 0x11f0000012470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT8_CNTS" , 0x11f0000012480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT9_CNTS" , 0x11f0000012490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT10_CNTS" , 0x11f00000124a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT11_CNTS" , 0x11f00000124b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT12_CNTS" , 0x11f00000124c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT13_CNTS" , 0x11f00000124d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT14_CNTS" , 0x11f00000124e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT15_CNTS" , 0x11f00000124f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT16_CNTS" , 0x11f0000012500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT17_CNTS" , 0x11f0000012510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT18_CNTS" , 0x11f0000012520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT19_CNTS" , 0x11f0000012530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT20_CNTS" , 0x11f0000012540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT21_CNTS" , 0x11f0000012550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT22_CNTS" , 0x11f0000012560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT23_CNTS" , 0x11f0000012570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT24_CNTS" , 0x11f0000012580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT25_CNTS" , 0x11f0000012590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT26_CNTS" , 0x11f00000125a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT27_CNTS" , 0x11f00000125b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT28_CNTS" , 0x11f00000125c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT29_CNTS" , 0x11f00000125d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT30_CNTS" , 0x11f00000125e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT31_CNTS" , 0x11f00000125f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_PKT0_IN_BP" , 0x11f0000013800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT1_IN_BP" , 0x11f0000013810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT2_IN_BP" , 0x11f0000013820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT3_IN_BP" , 0x11f0000013830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT4_IN_BP" , 0x11f0000013840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT5_IN_BP" , 0x11f0000013850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT6_IN_BP" , 0x11f0000013860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT7_IN_BP" , 0x11f0000013870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT8_IN_BP" , 0x11f0000013880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT9_IN_BP" , 0x11f0000013890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT10_IN_BP" , 0x11f00000138a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT11_IN_BP" , 0x11f00000138b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT12_IN_BP" , 0x11f00000138c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT13_IN_BP" , 0x11f00000138d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT14_IN_BP" , 0x11f00000138e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT15_IN_BP" , 0x11f00000138f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT16_IN_BP" , 0x11f0000013900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT17_IN_BP" , 0x11f0000013910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT18_IN_BP" , 0x11f0000013920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT19_IN_BP" , 0x11f0000013930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT20_IN_BP" , 0x11f0000013940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT21_IN_BP" , 0x11f0000013950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT22_IN_BP" , 0x11f0000013960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT23_IN_BP" , 0x11f0000013970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT24_IN_BP" , 0x11f0000013980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT25_IN_BP" , 0x11f0000013990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT26_IN_BP" , 0x11f00000139a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT27_IN_BP" , 0x11f00000139b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT28_IN_BP" , 0x11f00000139c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT29_IN_BP" , 0x11f00000139d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT30_IN_BP" , 0x11f00000139e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT31_IN_BP" , 0x11f00000139f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_PKT0_INSTR_BADDR" , 0x11f0000012800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT1_INSTR_BADDR" , 0x11f0000012810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT2_INSTR_BADDR" , 0x11f0000012820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT3_INSTR_BADDR" , 0x11f0000012830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT4_INSTR_BADDR" , 0x11f0000012840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT5_INSTR_BADDR" , 0x11f0000012850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT6_INSTR_BADDR" , 0x11f0000012860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT7_INSTR_BADDR" , 0x11f0000012870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT8_INSTR_BADDR" , 0x11f0000012880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT9_INSTR_BADDR" , 0x11f0000012890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT10_INSTR_BADDR" , 0x11f00000128a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT11_INSTR_BADDR" , 0x11f00000128b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT12_INSTR_BADDR" , 0x11f00000128c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT13_INSTR_BADDR" , 0x11f00000128d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT14_INSTR_BADDR" , 0x11f00000128e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT15_INSTR_BADDR" , 0x11f00000128f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT16_INSTR_BADDR" , 0x11f0000012900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT17_INSTR_BADDR" , 0x11f0000012910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT18_INSTR_BADDR" , 0x11f0000012920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT19_INSTR_BADDR" , 0x11f0000012930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT20_INSTR_BADDR" , 0x11f0000012940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT21_INSTR_BADDR" , 0x11f0000012950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT22_INSTR_BADDR" , 0x11f0000012960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT23_INSTR_BADDR" , 0x11f0000012970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT24_INSTR_BADDR" , 0x11f0000012980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT25_INSTR_BADDR" , 0x11f0000012990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT26_INSTR_BADDR" , 0x11f00000129a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT27_INSTR_BADDR" , 0x11f00000129b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT28_INSTR_BADDR" , 0x11f00000129c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT29_INSTR_BADDR" , 0x11f00000129d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT30_INSTR_BADDR" , 0x11f00000129e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT31_INSTR_BADDR" , 0x11f00000129f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_PKT0_INSTR_BAOFF_DBELL" , 0x11f0000012c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT1_INSTR_BAOFF_DBELL" , 0x11f0000012c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT2_INSTR_BAOFF_DBELL" , 0x11f0000012c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT3_INSTR_BAOFF_DBELL" , 0x11f0000012c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT4_INSTR_BAOFF_DBELL" , 0x11f0000012c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT5_INSTR_BAOFF_DBELL" , 0x11f0000012c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT6_INSTR_BAOFF_DBELL" , 0x11f0000012c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT7_INSTR_BAOFF_DBELL" , 0x11f0000012c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT8_INSTR_BAOFF_DBELL" , 0x11f0000012c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT9_INSTR_BAOFF_DBELL" , 0x11f0000012c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT10_INSTR_BAOFF_DBELL" , 0x11f0000012ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT11_INSTR_BAOFF_DBELL" , 0x11f0000012cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT12_INSTR_BAOFF_DBELL" , 0x11f0000012cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT13_INSTR_BAOFF_DBELL" , 0x11f0000012cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT14_INSTR_BAOFF_DBELL" , 0x11f0000012ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT15_INSTR_BAOFF_DBELL" , 0x11f0000012cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT16_INSTR_BAOFF_DBELL" , 0x11f0000012d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT17_INSTR_BAOFF_DBELL" , 0x11f0000012d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT18_INSTR_BAOFF_DBELL" , 0x11f0000012d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT19_INSTR_BAOFF_DBELL" , 0x11f0000012d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT20_INSTR_BAOFF_DBELL" , 0x11f0000012d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT21_INSTR_BAOFF_DBELL" , 0x11f0000012d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT22_INSTR_BAOFF_DBELL" , 0x11f0000012d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT23_INSTR_BAOFF_DBELL" , 0x11f0000012d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT24_INSTR_BAOFF_DBELL" , 0x11f0000012d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT25_INSTR_BAOFF_DBELL" , 0x11f0000012d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT26_INSTR_BAOFF_DBELL" , 0x11f0000012da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT27_INSTR_BAOFF_DBELL" , 0x11f0000012db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT28_INSTR_BAOFF_DBELL" , 0x11f0000012dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT29_INSTR_BAOFF_DBELL" , 0x11f0000012dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT30_INSTR_BAOFF_DBELL" , 0x11f0000012de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT31_INSTR_BAOFF_DBELL" , 0x11f0000012df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PKT0_INSTR_FIFO_RSIZE" , 0x11f0000013000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT1_INSTR_FIFO_RSIZE" , 0x11f0000013010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT2_INSTR_FIFO_RSIZE" , 0x11f0000013020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT3_INSTR_FIFO_RSIZE" , 0x11f0000013030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT4_INSTR_FIFO_RSIZE" , 0x11f0000013040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT5_INSTR_FIFO_RSIZE" , 0x11f0000013050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT6_INSTR_FIFO_RSIZE" , 0x11f0000013060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT7_INSTR_FIFO_RSIZE" , 0x11f0000013070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT8_INSTR_FIFO_RSIZE" , 0x11f0000013080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT9_INSTR_FIFO_RSIZE" , 0x11f0000013090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT10_INSTR_FIFO_RSIZE" , 0x11f00000130a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT11_INSTR_FIFO_RSIZE" , 0x11f00000130b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT12_INSTR_FIFO_RSIZE" , 0x11f00000130c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT13_INSTR_FIFO_RSIZE" , 0x11f00000130d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT14_INSTR_FIFO_RSIZE" , 0x11f00000130e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT15_INSTR_FIFO_RSIZE" , 0x11f00000130f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT16_INSTR_FIFO_RSIZE" , 0x11f0000013100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT17_INSTR_FIFO_RSIZE" , 0x11f0000013110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT18_INSTR_FIFO_RSIZE" , 0x11f0000013120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT19_INSTR_FIFO_RSIZE" , 0x11f0000013130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT20_INSTR_FIFO_RSIZE" , 0x11f0000013140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT21_INSTR_FIFO_RSIZE" , 0x11f0000013150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT22_INSTR_FIFO_RSIZE" , 0x11f0000013160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT23_INSTR_FIFO_RSIZE" , 0x11f0000013170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT24_INSTR_FIFO_RSIZE" , 0x11f0000013180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT25_INSTR_FIFO_RSIZE" , 0x11f0000013190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT26_INSTR_FIFO_RSIZE" , 0x11f00000131a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT27_INSTR_FIFO_RSIZE" , 0x11f00000131b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT28_INSTR_FIFO_RSIZE" , 0x11f00000131c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT29_INSTR_FIFO_RSIZE" , 0x11f00000131d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT30_INSTR_FIFO_RSIZE" , 0x11f00000131e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT31_INSTR_FIFO_RSIZE" , 0x11f00000131f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PKT0_INSTR_HEADER" , 0x11f0000013400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT1_INSTR_HEADER" , 0x11f0000013410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT2_INSTR_HEADER" , 0x11f0000013420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT3_INSTR_HEADER" , 0x11f0000013430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT4_INSTR_HEADER" , 0x11f0000013440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT5_INSTR_HEADER" , 0x11f0000013450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT6_INSTR_HEADER" , 0x11f0000013460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT7_INSTR_HEADER" , 0x11f0000013470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT8_INSTR_HEADER" , 0x11f0000013480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT9_INSTR_HEADER" , 0x11f0000013490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT10_INSTR_HEADER" , 0x11f00000134a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT11_INSTR_HEADER" , 0x11f00000134b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT12_INSTR_HEADER" , 0x11f00000134c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT13_INSTR_HEADER" , 0x11f00000134d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT14_INSTR_HEADER" , 0x11f00000134e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT15_INSTR_HEADER" , 0x11f00000134f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT16_INSTR_HEADER" , 0x11f0000013500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT17_INSTR_HEADER" , 0x11f0000013510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT18_INSTR_HEADER" , 0x11f0000013520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT19_INSTR_HEADER" , 0x11f0000013530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT20_INSTR_HEADER" , 0x11f0000013540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT21_INSTR_HEADER" , 0x11f0000013550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT22_INSTR_HEADER" , 0x11f0000013560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT23_INSTR_HEADER" , 0x11f0000013570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT24_INSTR_HEADER" , 0x11f0000013580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT25_INSTR_HEADER" , 0x11f0000013590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT26_INSTR_HEADER" , 0x11f00000135a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT27_INSTR_HEADER" , 0x11f00000135b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT28_INSTR_HEADER" , 0x11f00000135c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT29_INSTR_HEADER" , 0x11f00000135d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT30_INSTR_HEADER" , 0x11f00000135e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT31_INSTR_HEADER" , 0x11f00000135f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PKT0_OUT_SIZE" , 0x11f0000010c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT1_OUT_SIZE" , 0x11f0000010c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT2_OUT_SIZE" , 0x11f0000010c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT3_OUT_SIZE" , 0x11f0000010c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT4_OUT_SIZE" , 0x11f0000010c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT5_OUT_SIZE" , 0x11f0000010c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT6_OUT_SIZE" , 0x11f0000010c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT7_OUT_SIZE" , 0x11f0000010c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT8_OUT_SIZE" , 0x11f0000010c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT9_OUT_SIZE" , 0x11f0000010c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT10_OUT_SIZE" , 0x11f0000010ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT11_OUT_SIZE" , 0x11f0000010cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT12_OUT_SIZE" , 0x11f0000010cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT13_OUT_SIZE" , 0x11f0000010cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT14_OUT_SIZE" , 0x11f0000010ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT15_OUT_SIZE" , 0x11f0000010cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT16_OUT_SIZE" , 0x11f0000010d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT17_OUT_SIZE" , 0x11f0000010d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT18_OUT_SIZE" , 0x11f0000010d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT19_OUT_SIZE" , 0x11f0000010d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT20_OUT_SIZE" , 0x11f0000010d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT21_OUT_SIZE" , 0x11f0000010d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT22_OUT_SIZE" , 0x11f0000010d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT23_OUT_SIZE" , 0x11f0000010d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT24_OUT_SIZE" , 0x11f0000010d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT25_OUT_SIZE" , 0x11f0000010d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT26_OUT_SIZE" , 0x11f0000010da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT27_OUT_SIZE" , 0x11f0000010db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT28_OUT_SIZE" , 0x11f0000010dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT29_OUT_SIZE" , 0x11f0000010dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT30_OUT_SIZE" , 0x11f0000010de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT31_OUT_SIZE" , 0x11f0000010df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PKT0_SLIST_BADDR" , 0x11f0000011400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT1_SLIST_BADDR" , 0x11f0000011410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT2_SLIST_BADDR" , 0x11f0000011420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT3_SLIST_BADDR" , 0x11f0000011430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT4_SLIST_BADDR" , 0x11f0000011440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT5_SLIST_BADDR" , 0x11f0000011450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT6_SLIST_BADDR" , 0x11f0000011460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT7_SLIST_BADDR" , 0x11f0000011470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT8_SLIST_BADDR" , 0x11f0000011480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT9_SLIST_BADDR" , 0x11f0000011490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT10_SLIST_BADDR" , 0x11f00000114a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT11_SLIST_BADDR" , 0x11f00000114b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT12_SLIST_BADDR" , 0x11f00000114c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT13_SLIST_BADDR" , 0x11f00000114d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT14_SLIST_BADDR" , 0x11f00000114e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT15_SLIST_BADDR" , 0x11f00000114f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT16_SLIST_BADDR" , 0x11f0000011500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT17_SLIST_BADDR" , 0x11f0000011510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT18_SLIST_BADDR" , 0x11f0000011520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT19_SLIST_BADDR" , 0x11f0000011530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT20_SLIST_BADDR" , 0x11f0000011540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT21_SLIST_BADDR" , 0x11f0000011550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT22_SLIST_BADDR" , 0x11f0000011560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT23_SLIST_BADDR" , 0x11f0000011570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT24_SLIST_BADDR" , 0x11f0000011580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT25_SLIST_BADDR" , 0x11f0000011590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT26_SLIST_BADDR" , 0x11f00000115a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT27_SLIST_BADDR" , 0x11f00000115b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT28_SLIST_BADDR" , 0x11f00000115c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT29_SLIST_BADDR" , 0x11f00000115d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT30_SLIST_BADDR" , 0x11f00000115e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT31_SLIST_BADDR" , 0x11f00000115f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT0_SLIST_BAOFF_DBELL" , 0x11f0000011800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT1_SLIST_BAOFF_DBELL" , 0x11f0000011810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT2_SLIST_BAOFF_DBELL" , 0x11f0000011820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT3_SLIST_BAOFF_DBELL" , 0x11f0000011830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT4_SLIST_BAOFF_DBELL" , 0x11f0000011840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT5_SLIST_BAOFF_DBELL" , 0x11f0000011850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT6_SLIST_BAOFF_DBELL" , 0x11f0000011860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT7_SLIST_BAOFF_DBELL" , 0x11f0000011870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT8_SLIST_BAOFF_DBELL" , 0x11f0000011880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT9_SLIST_BAOFF_DBELL" , 0x11f0000011890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT10_SLIST_BAOFF_DBELL" , 0x11f00000118a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT11_SLIST_BAOFF_DBELL" , 0x11f00000118b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT12_SLIST_BAOFF_DBELL" , 0x11f00000118c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT13_SLIST_BAOFF_DBELL" , 0x11f00000118d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT14_SLIST_BAOFF_DBELL" , 0x11f00000118e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT15_SLIST_BAOFF_DBELL" , 0x11f00000118f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT16_SLIST_BAOFF_DBELL" , 0x11f0000011900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT17_SLIST_BAOFF_DBELL" , 0x11f0000011910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT18_SLIST_BAOFF_DBELL" , 0x11f0000011920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT19_SLIST_BAOFF_DBELL" , 0x11f0000011930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT20_SLIST_BAOFF_DBELL" , 0x11f0000011940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT21_SLIST_BAOFF_DBELL" , 0x11f0000011950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT22_SLIST_BAOFF_DBELL" , 0x11f0000011960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT23_SLIST_BAOFF_DBELL" , 0x11f0000011970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT24_SLIST_BAOFF_DBELL" , 0x11f0000011980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT25_SLIST_BAOFF_DBELL" , 0x11f0000011990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT26_SLIST_BAOFF_DBELL" , 0x11f00000119a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT27_SLIST_BAOFF_DBELL" , 0x11f00000119b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT28_SLIST_BAOFF_DBELL" , 0x11f00000119c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT29_SLIST_BAOFF_DBELL" , 0x11f00000119d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT30_SLIST_BAOFF_DBELL" , 0x11f00000119e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT31_SLIST_BAOFF_DBELL" , 0x11f00000119f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT0_SLIST_FIFO_RSIZE" , 0x11f0000011c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT1_SLIST_FIFO_RSIZE" , 0x11f0000011c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT2_SLIST_FIFO_RSIZE" , 0x11f0000011c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT3_SLIST_FIFO_RSIZE" , 0x11f0000011c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT4_SLIST_FIFO_RSIZE" , 0x11f0000011c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT5_SLIST_FIFO_RSIZE" , 0x11f0000011c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT6_SLIST_FIFO_RSIZE" , 0x11f0000011c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT7_SLIST_FIFO_RSIZE" , 0x11f0000011c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT8_SLIST_FIFO_RSIZE" , 0x11f0000011c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT9_SLIST_FIFO_RSIZE" , 0x11f0000011c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT10_SLIST_FIFO_RSIZE" , 0x11f0000011ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT11_SLIST_FIFO_RSIZE" , 0x11f0000011cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT12_SLIST_FIFO_RSIZE" , 0x11f0000011cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT13_SLIST_FIFO_RSIZE" , 0x11f0000011cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT14_SLIST_FIFO_RSIZE" , 0x11f0000011ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT15_SLIST_FIFO_RSIZE" , 0x11f0000011cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT16_SLIST_FIFO_RSIZE" , 0x11f0000011d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT17_SLIST_FIFO_RSIZE" , 0x11f0000011d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT18_SLIST_FIFO_RSIZE" , 0x11f0000011d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT19_SLIST_FIFO_RSIZE" , 0x11f0000011d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT20_SLIST_FIFO_RSIZE" , 0x11f0000011d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT21_SLIST_FIFO_RSIZE" , 0x11f0000011d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT22_SLIST_FIFO_RSIZE" , 0x11f0000011d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT23_SLIST_FIFO_RSIZE" , 0x11f0000011d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT24_SLIST_FIFO_RSIZE" , 0x11f0000011d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT25_SLIST_FIFO_RSIZE" , 0x11f0000011d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT26_SLIST_FIFO_RSIZE" , 0x11f0000011da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT27_SLIST_FIFO_RSIZE" , 0x11f0000011db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT28_SLIST_FIFO_RSIZE" , 0x11f0000011dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT29_SLIST_FIFO_RSIZE" , 0x11f0000011dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT30_SLIST_FIFO_RSIZE" , 0x11f0000011de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT31_SLIST_FIFO_RSIZE" , 0x11f0000011df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT_CNT_INT" , 0x11f0000011130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT_CNT_INT_ENB" , 0x11f0000011150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT_CTL" , 0x11f0000011220ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT_DATA_OUT_ES" , 0x11f00000110b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT_DATA_OUT_NS" , 0x11f00000110a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT_DATA_OUT_ROR" , 0x11f0000011090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT_DPADDR" , 0x11f0000011080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT_IN_BP" , 0x11f0000011210ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT_IN_DONE0_CNTS" , 0x11f0000012000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE1_CNTS" , 0x11f0000012010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE2_CNTS" , 0x11f0000012020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE3_CNTS" , 0x11f0000012030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE4_CNTS" , 0x11f0000012040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE5_CNTS" , 0x11f0000012050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE6_CNTS" , 0x11f0000012060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE7_CNTS" , 0x11f0000012070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE8_CNTS" , 0x11f0000012080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE9_CNTS" , 0x11f0000012090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE10_CNTS" , 0x11f00000120a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE11_CNTS" , 0x11f00000120b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE12_CNTS" , 0x11f00000120c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE13_CNTS" , 0x11f00000120d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE14_CNTS" , 0x11f00000120e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE15_CNTS" , 0x11f00000120f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE16_CNTS" , 0x11f0000012100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE17_CNTS" , 0x11f0000012110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE18_CNTS" , 0x11f0000012120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE19_CNTS" , 0x11f0000012130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE20_CNTS" , 0x11f0000012140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE21_CNTS" , 0x11f0000012150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE22_CNTS" , 0x11f0000012160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE23_CNTS" , 0x11f0000012170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE24_CNTS" , 0x11f0000012180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE25_CNTS" , 0x11f0000012190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE26_CNTS" , 0x11f00000121a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE27_CNTS" , 0x11f00000121b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE28_CNTS" , 0x11f00000121c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE29_CNTS" , 0x11f00000121d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE30_CNTS" , 0x11f00000121e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_DONE31_CNTS" , 0x11f00000121f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_IN_INSTR_COUNTS" , 0x11f0000011200ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1011},
- {"SLI_PKT_IN_PCIE_PORT" , 0x11f00000111b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1012},
- {"SLI_PKT_INPUT_CONTROL" , 0x11f0000011170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1013},
- {"SLI_PKT_INSTR_ENB" , 0x11f0000011000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1014},
- {"SLI_PKT_INSTR_RD_SIZE" , 0x11f00000111a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1015},
- {"SLI_PKT_INSTR_SIZE" , 0x11f0000011020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1016},
- {"SLI_PKT_INT_LEVELS" , 0x11f0000011120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1017},
- {"SLI_PKT_IPTR" , 0x11f0000011070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_OUT_BMODE" , 0x11f00000110d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1019},
- {"SLI_PKT_OUT_ENB" , 0x11f0000011010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1020},
- {"SLI_PKT_OUTPUT_WMARK" , 0x11f0000011180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1021},
- {"SLI_PKT_PCIE_PORT" , 0x11f00000110e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1022},
- {"SLI_PKT_PORT_IN_RST" , 0x11f00000111f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1023},
- {"SLI_PKT_SLIST_ES" , 0x11f0000011050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1024},
- {"SLI_PKT_SLIST_NS" , 0x11f0000011040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1025},
- {"SLI_PKT_SLIST_ROR" , 0x11f0000011030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1026},
- {"SLI_PKT_TIME_INT" , 0x11f0000011140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1027},
- {"SLI_PKT_TIME_INT_ENB" , 0x11f0000011160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1028},
- {"SLI_S2M_PORT0_CTL" , 0x11f0000013d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1029},
- {"SLI_S2M_PORT1_CTL" , 0x11f0000013d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1029},
- {"SLI_SCRATCH_1" , 0x11f00000103c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1030},
- {"SLI_SCRATCH_2" , 0x11f00000103d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1031},
- {"SLI_STATE1" , 0x11f0000010620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1032},
- {"SLI_STATE2" , 0x11f0000010630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1033},
- {"SLI_STATE3" , 0x11f0000010640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1034},
- {"SLI_WIN_RD_ADDR" , 0x10ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1035},
- {"SLI_WIN_RD_DATA" , 0x40ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1036},
- {"SLI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1037},
- {"SLI_WIN_WR_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1038},
- {"SLI_WIN_WR_MASK" , 0x30ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1039},
- {"SLI_WINDOW_CTL" , 0x11f00000102e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1040},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1043},
- {"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1043},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"SMI_DRV_CTL" , 0x1180000001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1047},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1049},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1050},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1051},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1052},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1053},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1054},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1055},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1056},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1057},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1058},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1059},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1060},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1061},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1064},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1065},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1066},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1067},
- {"TRA0_READ_DAT_HI" , 0x11800a8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1068},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1069},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1070},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1071},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1072},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1073},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1074},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1075},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1076},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1077},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1078},
- {"UAHC0_EHCI_ASYNCLISTADDR" , 0x16f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 1079},
- {"UAHC0_EHCI_CONFIGFLAG" , 0x16f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 1080},
- {"UAHC0_EHCI_CTRLDSSEGMENT" , 0x16f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 1081},
- {"UAHC0_EHCI_FRINDEX" , 0x16f000000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 1082},
- {"UAHC0_EHCI_HCCAPBASE" , 0x16f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 1083},
- {"UAHC0_EHCI_HCCPARAMS" , 0x16f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 1084},
- {"UAHC0_EHCI_HCSPARAMS" , 0x16f0000000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 1085},
- {"UAHC0_EHCI_INSNREG00" , 0x16f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 32, 1086},
- {"UAHC0_EHCI_INSNREG03" , 0x16f000000009cull, CVMX_CSR_DB_TYPE_NCB, 32, 1087},
- {"UAHC0_EHCI_INSNREG04" , 0x16f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 1088},
- {"UAHC0_EHCI_INSNREG06" , 0x16f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 1089},
- {"UAHC0_EHCI_INSNREG07" , 0x16f00000000ecull, CVMX_CSR_DB_TYPE_NCB, 32, 1090},
- {"UAHC0_EHCI_PERIODICLISTBASE" , 0x16f0000000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 1091},
- {"UAHC0_EHCI_PORTSC001" , 0x16f0000000054ull, CVMX_CSR_DB_TYPE_NCB, 32, 1092},
- {"UAHC0_EHCI_PORTSC002" , 0x16f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 32, 1092},
- {"UAHC0_EHCI_USBCMD" , 0x16f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 1093},
- {"UAHC0_EHCI_USBINTR" , 0x16f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 1094},
- {"UAHC0_EHCI_USBSTS" , 0x16f0000000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 1095},
- {"UAHC0_OHCI0_HCBULKCURRENTED" , 0x16f000000042cull, CVMX_CSR_DB_TYPE_NCB, 32, 1096},
- {"UAHC0_OHCI0_HCBULKHEADED" , 0x16f0000000428ull, CVMX_CSR_DB_TYPE_NCB, 32, 1097},
- {"UAHC0_OHCI0_HCCOMMANDSTATUS" , 0x16f0000000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 1098},
- {"UAHC0_OHCI0_HCCONTROL" , 0x16f0000000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 1099},
- {"UAHC0_OHCI0_HCCONTROLCURRENTED", 0x16f0000000424ull, CVMX_CSR_DB_TYPE_NCB, 32, 1100},
- {"UAHC0_OHCI0_HCCONTROLHEADED" , 0x16f0000000420ull, CVMX_CSR_DB_TYPE_NCB, 32, 1101},
- {"UAHC0_OHCI0_HCDONEHEAD" , 0x16f0000000430ull, CVMX_CSR_DB_TYPE_NCB, 32, 1102},
- {"UAHC0_OHCI0_HCFMINTERVAL" , 0x16f0000000434ull, CVMX_CSR_DB_TYPE_NCB, 32, 1103},
- {"UAHC0_OHCI0_HCFMNUMBER" , 0x16f000000043cull, CVMX_CSR_DB_TYPE_NCB, 32, 1104},
- {"UAHC0_OHCI0_HCFMREMAINING" , 0x16f0000000438ull, CVMX_CSR_DB_TYPE_NCB, 32, 1105},
- {"UAHC0_OHCI0_HCHCCA" , 0x16f0000000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 1106},
- {"UAHC0_OHCI0_HCINTERRUPTDISABLE", 0x16f0000000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 1107},
- {"UAHC0_OHCI0_HCINTERRUPTENABLE", 0x16f0000000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 1108},
- {"UAHC0_OHCI0_HCINTERRUPTSTATUS", 0x16f000000040cull, CVMX_CSR_DB_TYPE_NCB, 32, 1109},
- {"UAHC0_OHCI0_HCLSTHRESHOLD" , 0x16f0000000444ull, CVMX_CSR_DB_TYPE_NCB, 32, 1110},
- {"UAHC0_OHCI0_HCPERIODCURRENTED", 0x16f000000041cull, CVMX_CSR_DB_TYPE_NCB, 32, 1111},
- {"UAHC0_OHCI0_HCPERIODICSTART" , 0x16f0000000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 1112},
- {"UAHC0_OHCI0_HCREVISION" , 0x16f0000000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 1113},
- {"UAHC0_OHCI0_HCRHDESCRIPTORA" , 0x16f0000000448ull, CVMX_CSR_DB_TYPE_NCB, 32, 1114},
- {"UAHC0_OHCI0_HCRHDESCRIPTORB" , 0x16f000000044cull, CVMX_CSR_DB_TYPE_NCB, 32, 1115},
- {"UAHC0_OHCI0_HCRHPORTSTATUS001", 0x16f0000000454ull, CVMX_CSR_DB_TYPE_NCB, 32, 1116},
- {"UAHC0_OHCI0_HCRHPORTSTATUS002", 0x16f0000000458ull, CVMX_CSR_DB_TYPE_NCB, 32, 1116},
- {"UAHC0_OHCI0_HCRHSTATUS" , 0x16f0000000450ull, CVMX_CSR_DB_TYPE_NCB, 32, 1117},
- {"UAHC0_OHCI0_INSNREG06" , 0x16f0000000498ull, CVMX_CSR_DB_TYPE_NCB, 32, 1118},
- {"UAHC0_OHCI0_INSNREG07" , 0x16f000000049cull, CVMX_CSR_DB_TYPE_NCB, 32, 1119},
- {"UCTL0_BIST_STATUS" , 0x118006f0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1120},
- {"UCTL0_CLK_RST_CTL" , 0x118006f000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1121},
- {"UCTL0_EHCI_CTL" , 0x118006f000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1122},
- {"UCTL0_EHCI_FLA" , 0x118006f0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1123},
- {"UCTL0_ERTO_CTL" , 0x118006f000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1124},
- {"UCTL0_IF_ENA" , 0x118006f000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1125},
- {"UCTL0_INT_ENA" , 0x118006f000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1126},
- {"UCTL0_INT_REG" , 0x118006f000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1127},
- {"UCTL0_OHCI_CTL" , 0x118006f000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1128},
- {"UCTL0_ORTO_CTL" , 0x118006f000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1129},
- {"UCTL0_PPAF_WM" , 0x118006f000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1130},
- {"UCTL0_UPHY_CTL_STATUS" , 0x118006f000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1131},
- {"UCTL0_UPHY_PORT000_CTL_STATUS", 0x118006f000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1132},
- {"UCTL0_UPHY_PORT001_CTL_STATUS", 0x118006f000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1132},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1133},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1134},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1135},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1136},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1137},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1138},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1139},
- {"ZIP_THROTTLE" , 0x1180038000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1140},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn61xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_21" , 4, 18, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_24_25" , 24, 2, 0, "RAZ", 1, 1, 0, 0},
- {"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRFLW1" , 35, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP1" , 36, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH1" , 37, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 0, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"RX_EN" , 4, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"TX_EN" , 5, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"BURST" , 6, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 2, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 2, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 2, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 2, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 3, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 4, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 9, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 10, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 10, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 10, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 10, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 11, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 12, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 13, "RO", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 7, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"NULL_DIS" , 10, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 13, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 13, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 14, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 14, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 15, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 15, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 16, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 16, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 17, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 18, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 19, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 19, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 20, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 20, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 21, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 21, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 21, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 22, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 22, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 23, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 23, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 27, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 27, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 32, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 32, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 33, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 33, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 34, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 35, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 35, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 36, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 36, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 37, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 37, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 38, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 38, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 39, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 39, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 40, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 41, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 60, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 2, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 61, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 64, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 64, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 64, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 64, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 64, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 64, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 65, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 65, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 65, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 65, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 65, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 65, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 68, "RAZ", 1, 1, 0, 0},
- {"BP" , 4, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 68, "RAZ", 1, 1, 0, 0},
- {"EN" , 8, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 68, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 1, 71, "RO", 0, 0, 0ull, 0ull},
- {"CLKRST" , 1, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"ENABLE" , 2, 1, 71, "R/W", 0, 0, 1ull, 1ull},
- {"COMP" , 3, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"DLLRST" , 4, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_SET" , 8, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_14" , 13, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_BYP" , 15, 1, 71, "R/W", 0, 1, 1ull, 0},
- {"CLKRX_SET" , 16, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_22" , 21, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKRX_BYP" , 23, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"CLK_SET" , 24, 5, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_NCTL" , 32, 6, 71, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_38_39" , 38, 2, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_PCTL" , 40, 6, 71, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_46_47" , 46, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_NCTL" , 48, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_54_55" , 54, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_PCTL" , 56, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_BYP" , 63, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"BIST" , 0, 6, 72, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 72, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 3, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 73, "RAZ", 1, 1, 0, 0},
- {"IPD" , 9, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 14, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 73, "RAZ", 1, 1, 0, 0},
- {"L2C" , 16, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 17, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 73, "RAZ", 1, 1, 0, 0},
- {"PIP" , 20, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 73, "RAZ", 1, 1, 0, 0},
- {"ASXPCS0" , 22, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"ASXPCS1" , 23, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_24" , 24, 1, 73, "RAZ", 1, 1, 0, 0},
- {"PEM0" , 25, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 26, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 73, "RAZ", 1, 1, 0, 0},
- {"AGL" , 28, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_29" , 29, 1, 73, "RAZ", 1, 1, 0, 0},
- {"IOB" , 30, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_40" , 31, 10, 73, "RAZ", 1, 1, 0, 0},
- {"DPI" , 41, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 42, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 73, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 4, 74, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 74, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 75, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 75, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 76, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 76, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 77, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 77, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 78, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 78, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 78, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 79, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 79, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 80, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 80, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 80, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 81, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 81, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 81, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 82, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 82, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 83, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 83, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 84, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 84, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 84, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 85, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 85, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 86, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 86, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 86, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 4, 87, "RO", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 87, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 88, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 89, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 89, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 89, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 89, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 89, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 89, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 89, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 89, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 89, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 89, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 90, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 90, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 91, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 91, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 92, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 92, "R/W", 0, 0, 0ull, 0ull},
- {"DPI_DMA" , 40, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_45" , 41, 5, 92, "R/W", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 92, "R/W", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 93, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI_DMA" , 40, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_45" , 41, 5, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 94, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI_DMA" , 40, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_45" , 41, 5, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 95, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 95, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 95, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 95, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 95, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 95, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 95, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 95, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 95, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 95, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 96, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 96, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 97, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 97, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 98, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 98, "R/W", 0, 0, 0ull, 0ull},
- {"DPI_DMA" , 40, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_45" , 41, 5, 98, "R/W", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 98, "R/W", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 99, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI_DMA" , 40, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_45" , 41, 5, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 100, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI_DMA" , 40, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_45" , 41, 5, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 101, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 101, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 101, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 101, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 101, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"SUM2" , 51, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 102, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 102, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 102, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 102, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 102, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 102, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 102, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 102, "R/W1C", 0, 0, 0ull, 0ull},
- {"SUM2" , 51, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 102, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 102, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 103, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 103, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 103, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 103, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 103, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 103, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 103, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 103, "R/W1C", 0, 0, 0ull, 0ull},
- {"SUM2" , 51, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 103, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 103, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"PP" , 0, 4, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_7" , 4, 4, 104, "RAZ", 1, 1, 0, 0},
- {"IRQ" , 8, 2, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 104, "RAZ", 1, 1, 0, 0},
- {"SEL" , 16, 3, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_19_63" , 19, 45, 104, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 4, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 105, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 105, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 105, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 105, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"BITS" , 0, 32, 106, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 106, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 107, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 4, 108, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 108, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 109, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 109, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 4, 110, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 110, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 111, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 112, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 3, 112, "R/W", 0, 0, 7ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 112, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 113, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 113, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 113, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 113, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 113, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 113, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 113, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 113, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 114, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 114, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 114, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 114, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 114, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 114, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 114, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 114, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 115, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 115, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 115, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 115, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 115, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 115, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 115, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 115, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 3, 116, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 116, "RAZ", 1, 1, 0, 0},
- {"MUX_SEL" , 4, 2, 116, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 116, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 116, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 116, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 117, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 117, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_39" , 37, 3, 117, "RAZ", 1, 1, 0, 0},
- {"SELECT" , 40, 3, 117, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_60" , 43, 18, 117, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 117, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 117, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 117, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 118, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 118, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 119, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 119, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 120, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 120, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 121, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 121, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 4, 122, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 122, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 122, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_45" , 41, 5, 122, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 122, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 122, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 122, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 123, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 123, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 123, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_45" , 41, 5, 123, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 123, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 123, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 123, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 124, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 124, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_45" , 41, 5, 124, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 124, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 124, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 124, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_17" , 4, 14, 125, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 125, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_45" , 41, 5, 125, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 125, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 125, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 125, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 126, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 126, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 126, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 127, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 127, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 127, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 128, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 128, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 129, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 129, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 129, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 130, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 130, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 131, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 131, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 132, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 132, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 132, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 132, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 132, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 132, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 132, "RAZ", 1, 1, 0, 0},
- {"PDB" , 0, 1, 133, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 133, "RAZ", 0, 0, 0ull, 0ull},
- {"RDF" , 4, 1, 133, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 133, "RAZ", 0, 0, 0ull, 0ull},
- {"DTX" , 8, 2, 133, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 133, "RAZ", 0, 0, 0ull, 0ull},
- {"STX" , 16, 2, 133, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_23" , 18, 6, 133, "RAZ", 0, 0, 0ull, 0ull},
- {"GFB" , 24, 1, 133, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 133, "RAZ", 0, 0, 0ull, 0ull},
- {"GFU" , 0, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"GIB" , 1, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"GIF" , 2, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"NCD" , 3, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"GUTP" , 4, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 134, "RAZ", 0, 0, 0ull, 0ull},
- {"GUTV" , 8, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 9, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"RAM1" , 10, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"RAM2" , 11, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"RAM3" , 12, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_18" , 13, 6, 134, "RAZ", 0, 0, 0ull, 0ull},
- {"DLC0RAM" , 19, 1, 134, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 134, "RAZ", 0, 0, 0ull, 0ull},
- {"DTECLKDIS" , 0, 1, 135, "R/W", 0, 0, 1ull, 0ull},
- {"CLDTECRIP" , 1, 3, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CLMSKCRIP" , 4, 4, 135, "R/W", 0, 0, 0ull, 0ull},
- {"REPL_ENA" , 8, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"DLCSTART_BIST" , 9, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"DLCCLEAR_BIST" , 10, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 135, "RAZ", 1, 1, 0, 0},
- {"IMODE" , 0, 1, 136, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 1, 1, 136, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 2, 1, 136, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_4" , 3, 2, 136, "RAZ", 1, 1, 0, 0},
- {"SBDLCK" , 5, 1, 136, "R/W", 0, 0, 0ull, 0ull},
- {"SBDNUM" , 6, 4, 136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 136, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 20, 137, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 137, "RAZ", 1, 1, 0, 0},
- {"SBD0" , 0, 64, 138, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 139, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 140, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 141, "RO", 1, 1, 0, 0},
- {"SIZE" , 0, 9, 142, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 142, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 142, "R/W", 0, 1, 1ull, 0},
- {"MSEGBASE" , 20, 6, 142, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 142, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 143, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 35, 143, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 143, "RAZ", 1, 1, 0, 0},
- {"RAM1FADR" , 0, 14, 144, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 144, "RAZ", 1, 1, 0, 0},
- {"RAM2FADR" , 16, 9, 144, "RO", 1, 1, 0, 0},
- {"RESERVED_25_31" , 25, 7, 144, "RAZ", 1, 1, 0, 0},
- {"RAM3FADR" , 32, 12, 144, "RO", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 144, "RAZ", 1, 1, 0, 0},
- {"DBLOVF" , 0, 1, 145, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC0PERR" , 1, 3, 145, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_12" , 4, 9, 145, "RAZ", 1, 1, 0, 0},
- {"DLC0_OVFERR" , 13, 1, 145, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 145, "RAZ", 1, 1, 0, 0},
- {"CNDRD" , 16, 1, 145, "RO", 0, 0, 0ull, 0ull},
- {"DFANXM" , 17, 1, 145, "R/W1C", 0, 0, 0ull, 0ull},
- {"REPLERR" , 18, 1, 145, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 145, "RAZ", 1, 1, 0, 0},
- {"DBLINA" , 0, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"DC0PENA" , 1, 3, 146, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_12" , 4, 9, 146, "RAZ", 1, 1, 0, 0},
- {"DLC0_OVFENA" , 13, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_16" , 14, 3, 146, "RAZ", 1, 1, 0, 0},
- {"DFANXMENA" , 17, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"REPLERRENA" , 18, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 146, "RAZ", 1, 1, 0, 0},
- {"HIDAT" , 0, 64, 147, "R/W", 1, 1, 0, 0},
- {"PFCNT0" , 0, 64, 148, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 149, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 149, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 149, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 149, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 149, "RAZ", 1, 1, 0, 0},
- {"PFCNT1" , 0, 64, 150, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 151, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 151, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 151, "RAZ", 1, 1, 0, 0},
- {"PFCNT2" , 0, 64, 152, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 153, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 153, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 153, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 153, "RAZ", 1, 1, 0, 0},
- {"PFCNT3" , 0, 64, 154, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 155, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 155, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 155, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 155, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 155, "RAZ", 1, 1, 0, 0},
- {"CNT0ENA" , 0, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 1, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 2, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 3, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0WCLR" , 4, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1WCLR" , 5, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2WCLR" , 6, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3WCLR" , 7, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RCLR" , 8, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RCLR" , 9, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RCLR" , 10, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RCLR" , 11, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"SNODE" , 12, 3, 156, "R/W", 0, 0, 0ull, 0ull},
- {"ENODE" , 15, 3, 156, "R/W", 0, 0, 0ull, 0ull},
- {"EDNODE" , 18, 2, 156, "R/W", 0, 0, 0ull, 0ull},
- {"PMODE" , 20, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"VGID" , 21, 8, 156, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 156, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 47, 157, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 157, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 158, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 158, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 159, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 159, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 159, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 160, "WO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 160, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 161, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 162, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 29, 162, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 162, "RAZ", 1, 1, 0, 0},
- {"IDLE" , 40, 1, 162, "RO", 0, 1, 1ull, 0},
- {"RESERVED_41_47" , 41, 7, 162, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 48, 14, 162, "R/W", 0, 1, 64ull, 0},
- {"RESERVED_62_63" , 62, 2, 162, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 3, 163, "R/W", 0, 0, 6ull, 6ull},
- {"RESERVED_3_63" , 3, 61, 163, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 164, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 164, "RAZ", 1, 1, 0, 0},
- {"STATE" , 0, 64, 165, "RO", 0, 1, 0ull, 0},
- {"STATE" , 0, 64, 166, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_13" , 0, 14, 167, "RAZ", 1, 1, 0, 0},
- {"O_MODE" , 14, 1, 167, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 167, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 167, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 167, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 167, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 167, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 167, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 167, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_47" , 34, 14, 167, "RAZ", 1, 1, 0, 0},
- {"DMA_ENB" , 48, 6, 167, "R/W", 0, 0, 0ull, 63ull},
- {"RESERVED_54_55" , 54, 2, 167, "RAZ", 1, 1, 0, 0},
- {"PKT_EN" , 56, 1, 167, "R/W", 0, 1, 0ull, 0},
- {"PKT_HP" , 57, 1, 167, "RO", 0, 0, 0ull, 0ull},
- {"COMMIT_MODE" , 58, 1, 167, "R/W", 0, 0, 0ull, 1ull},
- {"FFP_DIS" , 59, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_EN1" , 60, 1, 167, "R/W", 0, 1, 0ull, 0},
- {"DICI_MODE" , 61, 1, 167, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 167, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 168, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 168, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 169, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 169, "RAZ", 1, 1, 0, 0},
- {"BLKS" , 0, 4, 170, "R/W", 0, 1, 2ull, 0},
- {"BASE" , 4, 5, 170, "RO", 1, 1, 0, 0},
- {"RESERVED_9_31" , 9, 23, 170, "RAZ", 1, 1, 0, 0},
- {"COMPBLKS" , 32, 5, 170, "RO", 1, 1, 0, 0},
- {"RESERVED_37_63" , 37, 27, 170, "RAZ", 1, 1, 0, 0},
- {"RSL" , 0, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB" , 1, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 171, "RAZ", 1, 1, 0, 0},
- {"FFP" , 4, 4, 171, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 171, "RAZ", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 172, "R/W", 0, 0, 0ull, 0ull},
- {"DMADBO" , 8, 8, 172, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 172, "R/W", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT2_RST" , 26, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT3_RST" , 27, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 172, "RAZ", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 173, "RAZ", 1, 1, 0, 0},
- {"DMADBO" , 8, 8, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 173, "RAZ", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT2_RST" , 26, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT3_RST" , 27, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 173, "RAZ", 1, 1, 0, 0},
- {"MOLR" , 0, 6, 174, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 174, "RAZ", 1, 1, 0, 0},
- {"SINFO" , 0, 6, 175, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 175, "RAZ", 1, 1, 0, 0},
- {"IINFO" , 8, 6, 175, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 175, "RAZ", 1, 1, 0, 0},
- {"PKTERR" , 0, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 176, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 177, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 177, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 178, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 178, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 179, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 179, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 180, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 180, "RAZ", 1, 1, 0, 0},
- {"EN_RSP" , 0, 8, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 181, "RAZ", 1, 1, 0, 0},
- {"EN_RST" , 16, 8, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 181, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 182, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 182, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 2, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 183, "RAZ", 1, 1, 0, 0},
- {"MRRS_LIM" , 3, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"MPS" , 4, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 183, "RAZ", 1, 1, 0, 0},
- {"MPS_LIM" , 7, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"MOLR" , 8, 6, 183, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 183, "RAZ", 1, 1, 0, 0},
- {"RD_MODE" , 16, 1, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 183, "RAZ", 1, 1, 0, 0},
- {"QLM_CFG" , 20, 4, 183, "RO", 1, 1, 0, 0},
- {"HALT" , 24, 1, 183, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 183, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 184, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 184, "RO", 0, 1, 0ull, 0},
- {"REQQ" , 0, 3, 185, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 185, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 4, 1, 185, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 185, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 8, 1, 185, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 185, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 186, "RO", 0, 1, 0ull, 0},
- {"POOL" , 33, 5, 186, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 186, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 187, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 187, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 187, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 187, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 187, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 187, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 188, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 188, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OFF" , 18, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RET_OFF" , 19, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"FREE_EN" , 20, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 188, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 189, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 189, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 189, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 190, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 190, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 191, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 191, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 191, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 192, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 192, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"RES_44" , 44, 5, 193, "R/W", 0, 0, 0ull, 0ull},
- {"PADDR_E" , 49, 1, 193, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_63" , 50, 14, 193, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_48" , 44, 5, 194, "RAZ", 1, 1, 0, 0},
- {"PADDR_E" , 49, 1, 194, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_50_63" , 50, 14, 194, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 32, 195, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 195, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 196, "R/W", 0, 1, 8589934591ull, 0},
- {"RESERVED_33_63" , 33, 31, 196, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 197, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 197, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 29, 198, "R/W", 0, 0, 536870911ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 198, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 199, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 199, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 200, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 200, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 201, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 201, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 201, "RO", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 202, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 202, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 202, "RO", 0, 0, 0ull, 7ull},
- {"THRESH" , 0, 32, 203, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 203, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 204, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 204, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 204, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 205, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 206, "RAZ", 1, 1, 0, 0},
- {"LOGL_EN" , 0, 16, 207, "R/W", 0, 1, 65535ull, 0},
- {"PHYS_EN" , 16, 1, 207, "R/W", 0, 1, 1ull, 0},
- {"HG2RX_EN" , 17, 1, 207, "R/W", 0, 0, 0ull, 0ull},
- {"HG2TX_EN" , 18, 1, 207, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 207, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 208, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 208, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 208, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 1, 208, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 208, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 4, 208, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 208, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 209, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 209, "RAZ", 1, 1, 0, 0},
- {"RX_EN" , 0, 1, 210, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EN" , 1, 1, 210, "R/W", 0, 0, 0ull, 0ull},
- {"DRP_EN" , 2, 1, 210, "R/W", 0, 0, 0ull, 0ull},
- {"BCK_EN" , 3, 1, 210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 210, "RAZ", 1, 1, 0, 0},
- {"PHYS_BP" , 16, 16, 210, "R/W", 0, 1, 65535ull, 0},
- {"LOGL_EN" , 32, 16, 210, "R/W", 0, 0, 255ull, 255ull},
- {"PHYS_EN" , 48, 16, 210, "R/W", 0, 0, 255ull, 255ull},
- {"EN" , 0, 1, 211, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 211, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 211, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 211, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 211, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 211, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 211, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 211, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 211, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 211, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 212, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 213, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 214, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 215, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 216, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 217, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 32, 218, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 218, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 219, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 219, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 220, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 220, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 220, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 220, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 221, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 221, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 222, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 222, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 222, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 222, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 222, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 222, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 222, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 222, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 222, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 223, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 223, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 223, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 223, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 223, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 223, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 223, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 223, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 223, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 224, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 224, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 225, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 225, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 225, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 225, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 225, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 225, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 226, "R/W1C", 0, 1, 0ull, 0},
- {"CAREXT" , 1, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 226, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 226, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 226, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 226, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 226, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 226, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 227, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 227, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 228, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 228, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 229, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 229, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 230, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 230, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 231, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 231, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 232, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 232, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 233, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 233, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 234, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 234, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 235, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 235, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 236, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 236, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 237, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 237, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 238, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 238, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 239, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 239, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 239, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 239, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 240, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 240, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 241, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 241, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 242, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 242, "RAZ", 1, 1, 0, 0},
- {"LGTIM2GO" , 0, 16, 243, "RO", 0, 1, 0ull, 0},
- {"XOF" , 16, 16, 243, "RO", 0, 0, 0ull, 0ull},
- {"PHTIM2GO" , 32, 16, 243, "RO", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 243, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 4, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 244, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 4, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 244, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 245, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 245, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 246, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 246, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 246, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 246, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 246, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 247, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 248, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 248, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 249, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 249, "RAZ", 1, 1, 0, 0},
- {"WR_MAGIC" , 0, 1, 250, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 250, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 251, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 251, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 251, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 251, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 251, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 252, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 252, "RAZ", 1, 1, 0, 0},
- {"XOFF" , 0, 16, 253, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 253, "RAZ", 1, 1, 0, 0},
- {"XON" , 0, 16, 254, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 254, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 255, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 255, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 255, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 256, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 256, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 257, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 257, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 258, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 258, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 259, "RO", 1, 1, 0, 0},
- {"MSG_TIME" , 16, 16, 259, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 259, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 260, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 260, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 261, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 261, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 262, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 262, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 263, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 263, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 264, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 264, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 265, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 265, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 266, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 266, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 267, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 267, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 268, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 268, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 269, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 269, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 270, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 270, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 271, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 271, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 272, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 272, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 273, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 273, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 274, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 274, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 275, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 275, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 276, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 276, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 277, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 277, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 278, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 278, "RAZ", 1, 1, 0, 0},
- {"TX_XOF" , 0, 16, 279, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 279, "RAZ", 1, 1, 0, 0},
- {"TX_XON" , 0, 16, 280, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 280, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 281, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 281, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 281, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 282, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 282, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 282, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 282, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 282, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 282, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 282, "R/W", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 282, "R/W", 0, 0, 0ull, 0ull},
- {"XCHANGE" , 24, 1, 282, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 282, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 283, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 283, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 283, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 283, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 283, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 283, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 283, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 283, "R/W1C", 0, 0, 0ull, 0ull},
- {"XCHANGE" , 24, 1, 283, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 283, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 284, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 284, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 285, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 285, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 286, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 286, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 286, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 286, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 286, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 286, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 287, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 287, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 288, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 288, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 289, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_5_63" , 5, 59, 289, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 290, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 290, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 290, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 290, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 290, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 290, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 291, "R/W", 0, 0, 6ull, 6ull},
- {"EN" , 4, 1, 291, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 291, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 292, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 292, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCE_SEL" , 15, 2, 292, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 292, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 293, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 293, "RAZ", 1, 1, 0, 0},
- {"LANE_SEL" , 0, 2, 294, "R/W", 0, 0, 0ull, 0ull},
- {"DIV" , 2, 1, 294, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 294, "RAZ", 1, 1, 0, 0},
- {"QLM_SEL" , 8, 2, 294, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 294, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 295, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 295, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 296, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 296, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 20, 297, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 297, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 20, 298, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 298, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 20, 299, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 299, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 300, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 300, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 300, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 300, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 300, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 300, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 300, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 300, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCE_SEL" , 15, 2, 300, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 300, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"IOCFIF" , 18, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"RSDFIF" , 19, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"IORFIF" , 20, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"XMCFIF" , 21, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"XMDFIF" , 22, 1, 301, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 301, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 302, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 302, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 302, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 302, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 302, "R/W1C", 0, 0, 0ull, 0ull},
- {"RR_MODE" , 5, 1, 302, "R/W", 0, 0, 0ull, 0ull},
- {"XMC_PER" , 6, 4, 302, "R/W", 0, 0, 0ull, 0ull},
- {"FIF_DLY" , 10, 1, 302, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 302, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 303, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 303, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 304, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 304, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 304, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 305, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 305, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 305, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 306, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 306, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 306, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 306, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 306, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 307, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 307, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 307, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 307, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 307, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 308, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 309, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 310, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 310, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 310, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 310, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 310, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 310, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 310, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 311, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 311, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 311, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 311, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 311, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 311, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 311, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 312, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 312, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 312, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 313, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 313, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 313, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 314, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 315, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 315, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 315, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 315, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 315, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 316, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 316, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 316, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 316, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 317, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 318, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 319, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 319, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 319, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 320, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 320, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 320, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 321, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 321, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 322, "RO", 0, 1, 0ull, 0},
- {"VPORT" , 6, 6, 322, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 322, "RAZ", 1, 1, 0, 0},
- {"NCB_WR" , 0, 3, 323, "R/W", 0, 1, 0ull, 0},
- {"NCB_RD" , 3, 3, 323, "R/W", 0, 1, 0ull, 0},
- {"PKO_RD" , 6, 3, 323, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 323, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 324, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 324, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 325, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 325, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 326, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 326, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 327, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 327, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 48, 328, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 328, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 329, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 330, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 330, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"CLKEN" , 15, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"RST_DONE" , 16, 1, 330, "RO", 0, 0, 1ull, 0ull},
- {"USE_SOP" , 17, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 330, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 331, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 332, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 333, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 333, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 334, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 334, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 335, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 335, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 336, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 336, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 336, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 337, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 337, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 337, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 338, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 338, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 338, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 339, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 339, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 340, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 340, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 341, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 341, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 342, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 342, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 343, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 343, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 345, "R/W", 0, 0, 0ull, 1ull},
- {"RADDR" , 0, 3, 346, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 346, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 346, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 346, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 346, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 346, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 347, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 347, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 347, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 347, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_44_63" , 44, 20, 347, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 348, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 348, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 348, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 348, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 348, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 348, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 349, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 349, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 349, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 349, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 349, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 349, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_61_63" , 61, 3, 349, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 350, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 350, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 351, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 351, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 352, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 352, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 352, "R/W", 0, 0, 0ull, 0ull},
- {"PRT_ENB" , 0, 12, 353, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 353, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 354, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 354, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 354, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 354, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 354, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 355, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 355, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 355, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 356, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_35" , 32, 4, 356, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT2" , 36, 4, 356, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_40_63" , 40, 24, 356, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 357, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 357, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 357, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 358, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 358, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 359, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 359, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 360, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 361, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 361, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 361, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 362, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 363, "RAZ", 1, 1, 0, 0},
- {"DISABLE" , 0, 1, 364, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 364, "RAZ", 1, 1, 0, 0},
- {"MAXDRAM" , 4, 4, 364, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_8_63" , 8, 56, 364, "RAZ", 1, 1, 0, 0},
- {"TDFFL" , 0, 1, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_1_3" , 1, 3, 365, "RAZ", 1, 1, 0, 0},
- {"VRTFL" , 4, 1, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_7" , 5, 3, 365, "RAZ", 1, 1, 0, 0},
- {"DUTRESFL" , 8, 1, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_9_11" , 9, 3, 365, "RAZ", 1, 1, 0, 0},
- {"IOCDATFL" , 12, 1, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_13_15" , 13, 3, 365, "RAZ", 1, 1, 0, 0},
- {"IOCCMDFL" , 16, 1, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 365, "RAZ", 1, 1, 0, 0},
- {"DUTFL" , 32, 4, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_36_63" , 36, 28, 365, "RAZ", 1, 1, 0, 0},
- {"VBFFL" , 0, 4, 366, "RO", 1, 0, 0, 0ull},
- {"RDFFL" , 4, 1, 366, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_61" , 5, 57, 366, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 62, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 63, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFL" , 0, 8, 367, "RO", 1, 0, 0, 0ull},
- {"FBFFL" , 8, 8, 367, "RO", 1, 0, 0, 0ull},
- {"SBFFL" , 16, 8, 367, "RO", 1, 0, 0, 0ull},
- {"FBFRSPFL" , 24, 8, 367, "RO", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 367, "RAZ", 1, 1, 0, 0},
- {"TAGFL" , 0, 16, 368, "RO", 1, 0, 0, 0ull},
- {"LRUFL" , 16, 1, 368, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 368, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 369, "R/W", 1, 1, 0, 0},
- {"DISIDXALIAS" , 0, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"DISECC" , 1, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"VAB_THRESH" , 2, 4, 370, "R/W", 0, 0, 0ull, 0ull},
- {"EF_CNT" , 6, 7, 370, "R/W", 0, 0, 0ull, 4ull},
- {"EF_ENA" , 13, 1, 370, "R/W", 0, 0, 0ull, 1ull},
- {"XMC_ARB_MODE" , 14, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"RSP_ARB_MODE" , 15, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"MAXLFB" , 16, 4, 370, "R/W", 0, 0, 0ull, 0ull},
- {"MAXVAB" , 20, 4, 370, "R/W", 0, 0, 0ull, 0ull},
- {"DISCCLK" , 24, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFDBE" , 25, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFSBE" , 26, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"DISSTGL2I" , 27, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"RDF_FAST" , 28, 1, 370, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_29_63" , 29, 35, 370, "RAZ", 1, 1, 0, 0},
- {"VALID" , 0, 1, 371, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_9" , 1, 9, 371, "RAZ", 1, 1, 0, 0},
- {"TAG" , 10, 28, 371, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 371, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 372, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 372, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 4, 16, 372, "RO", 1, 0, 0, 0ull},
- {"RESERVED_20_49" , 20, 30, 372, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 10, 372, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 373, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_6" , 2, 5, 373, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 7, 13, 373, "RO", 1, 0, 0, 0ull},
- {"RESERVED_20_49" , 20, 30, 373, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 6, 373, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_60" , 56, 5, 373, "RAZ", 1, 1, 0, 0},
- {"NOWAY" , 61, 1, 373, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 373, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 373, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 374, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_49" , 2, 48, 374, "RAZ", 1, 1, 0, 0},
- {"VSYN" , 50, 10, 374, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 374, "RO", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 374, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 374, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 38, 375, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_47" , 38, 10, 375, "RAZ", 1, 1, 0, 0},
- {"SID" , 48, 4, 375, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_57" , 52, 6, 375, "RAZ", 1, 1, 0, 0},
- {"CMD" , 58, 6, 375, "RO", 0, 1, 0ull, 0},
- {"HOLERD" , 0, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"HOLEWR" , 1, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"VRTWR" , 2, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"VRTIDRNG" , 3, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"VRTADRNG" , 4, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"VRTPE" , 5, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"BIGWR" , 6, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"BIGRD" , 7, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 376, "RAZ", 1, 1, 0, 0},
- {"HOLERD" , 0, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"HOLEWR" , 1, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTWR" , 2, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTIDRNG" , 3, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTADRNG" , 4, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTPE" , 5, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGWR" , 6, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGRD" , 7, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 377, "RAZ", 1, 1, 0, 0},
- {"TAD0" , 16, 1, 377, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 377, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 378, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 379, "R/W", 0, 1, 0ull, 0},
- {"LVL" , 0, 2, 380, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 380, "RAZ", 1, 1, 0, 0},
- {"DWBLVL" , 4, 2, 380, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 380, "RAZ", 1, 1, 0, 0},
- {"LVL" , 0, 2, 381, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 381, "RAZ", 1, 1, 0, 0},
- {"WGT0" , 0, 8, 382, "R/W", 0, 0, 255ull, 255ull},
- {"WGT1" , 8, 8, 382, "R/W", 0, 0, 255ull, 255ull},
- {"WGT2" , 16, 8, 382, "R/W", 0, 0, 255ull, 255ull},
- {"WGT3" , 24, 8, 382, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 382, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 383, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 384, "R/W", 0, 1, 0ull, 0},
- {"OW0ECC" , 0, 10, 385, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 385, "RAZ", 1, 1, 0, 0},
- {"OW1ECC" , 16, 10, 385, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 385, "RAZ", 1, 1, 0, 0},
- {"OW2ECC" , 32, 10, 385, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 385, "RAZ", 1, 1, 0, 0},
- {"OW3ECC" , 48, 10, 385, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 385, "RAZ", 1, 1, 0, 0},
- {"OW4ECC" , 0, 10, 386, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 386, "RAZ", 1, 1, 0, 0},
- {"OW5ECC" , 16, 10, 386, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 386, "RAZ", 1, 1, 0, 0},
- {"OW6ECC" , 32, 10, 386, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 386, "RAZ", 1, 1, 0, 0},
- {"OW7ECC" , 48, 10, 386, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 386, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 387, "R/W", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"WRDISLMC" , 8, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 387, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 388, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 388, "R/W1C", 0, 0, 0ull, 0ull},
- {"WRDISLMC" , 8, 1, 388, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 388, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 389, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 390, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 391, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 392, "R/W", 0, 1, 0ull, 0},
- {"CNT0SEL" , 0, 8, 393, "R/W", 0, 0, 0ull, 1ull},
- {"CNT1SEL" , 8, 8, 393, "R/W", 0, 0, 0ull, 1ull},
- {"CNT2SEL" , 16, 8, 393, "R/W", 0, 0, 0ull, 1ull},
- {"CNT3SEL" , 24, 8, 393, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 393, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 0, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"DIRTY" , 1, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"VALID" , 2, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"USE" , 3, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_16" , 4, 13, 394, "RAZ", 1, 1, 0, 0},
- {"TAG" , 17, 19, 394, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_39" , 36, 4, 394, "RAZ", 1, 1, 0, 0},
- {"ECC" , 40, 6, 394, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_63" , 46, 18, 394, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 395, "R/W1C", 0, 0, 0ull, 0ull},
- {"MASK" , 0, 1, 396, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 396, "RAZ", 1, 1, 0, 0},
- {"DWB" , 0, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"INVL2" , 1, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 397, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 4, 398, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 398, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 399, "RAZ", 1, 1, 0, 0},
- {"DWBID" , 8, 6, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 399, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 400, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 400, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 401, "R/W", 0, 0, 0ull, 1ull},
- {"NUMID" , 1, 3, 401, "R/W", 0, 0, 5ull, 5ull},
- {"MEMSZ" , 4, 3, 401, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_7_7" , 7, 1, 401, "RAZ", 1, 1, 0, 0},
- {"OOBERR" , 8, 1, 401, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 401, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 32, 402, "R/W", 0, 0, 0ull, 0ull},
- {"PARITY" , 32, 4, 402, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 402, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 403, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 403, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 404, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 404, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 405, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 38, 406, "R/W", 1, 1, 0, 0},
- {"RESERVED_38_56" , 38, 19, 406, "RAZ", 1, 1, 0, 0},
- {"CMD" , 57, 6, 406, "R/W", 1, 1, 0, 0},
- {"INUSE" , 63, 1, 406, "RO", 0, 0, 0ull, 0ull},
- {"COUNT" , 0, 64, 407, "R/W", 0, 1, 0ull, 0},
- {"PRBS" , 0, 32, 408, "R/W", 1, 1, 0, 0},
- {"PROG" , 32, 8, 408, "R/W", 1, 1, 0, 0},
- {"SEL" , 40, 1, 408, "R/W", 1, 1, 0, 0},
- {"EN" , 41, 1, 408, "R/W", 1, 1, 0, 0},
- {"SKEW_ON" , 42, 1, 408, "R/W", 1, 1, 0, 0},
- {"DR" , 43, 1, 408, "R/W", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 408, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 409, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 410, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 410, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 411, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 412, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 412, "R/W", 1, 1, 0, 0},
- {"CKE_MASK" , 0, 2, 413, "R/W", 1, 1, 0, 0},
- {"CS0_N_MASK" , 2, 2, 413, "R/W", 1, 1, 0, 0},
- {"CS1_N_MASK" , 4, 2, 413, "R/W", 1, 1, 0, 0},
- {"ODT0_MASK" , 6, 2, 413, "R/W", 1, 1, 0, 0},
- {"ODT1_MASK" , 8, 2, 413, "R/W", 1, 1, 0, 0},
- {"RAS_N_MASK" , 10, 1, 413, "R/W", 1, 1, 0, 0},
- {"CAS_N_MASK" , 11, 1, 413, "R/W", 1, 1, 0, 0},
- {"WE_N_MASK" , 12, 1, 413, "R/W", 1, 1, 0, 0},
- {"BA_MASK" , 13, 3, 413, "R/W", 1, 1, 0, 0},
- {"A_MASK" , 16, 16, 413, "R/W", 1, 1, 0, 0},
- {"RESET_N_MASK" , 32, 1, 413, "R/W", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 413, "R/W", 1, 1, 0, 0},
- {"DQX_CTL" , 0, 4, 414, "R/W", 0, 1, 4ull, 0},
- {"CK_CTL" , 4, 4, 414, "R/W", 0, 1, 4ull, 0},
- {"CMD_CTL" , 8, 4, 414, "R/W", 0, 1, 4ull, 0},
- {"RODT_CTL" , 12, 4, 414, "R/W", 0, 1, 0ull, 0},
- {"NTUNE" , 16, 4, 414, "R/W", 0, 1, 0ull, 0},
- {"PTUNE" , 20, 4, 414, "R/W", 0, 1, 0ull, 0},
- {"BYP" , 24, 1, 414, "R/W", 0, 1, 0ull, 0},
- {"M180" , 25, 1, 414, "R/W", 0, 1, 0ull, 0},
- {"DDR__NTUNE" , 26, 4, 414, "RO", 1, 1, 0, 0},
- {"DDR__PTUNE" , 30, 4, 414, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 414, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 415, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 415, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 415, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 415, "R/W", 0, 1, 5ull, 0},
- {"IDLEPOWER" , 9, 3, 415, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 12, 4, 415, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 16, 1, 415, "R/W", 0, 0, 0ull, 1ull},
- {"RESET" , 17, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"REF_ZQCS_INT" , 18, 19, 415, "R/W", 1, 1, 0, 0},
- {"SEQUENCE" , 37, 3, 415, "R/W", 0, 0, 0ull, 0ull},
- {"EARLY_DQX" , 40, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"SREF_WITH_DLL" , 41, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RANK_ENA" , 42, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"RANKMASK" , 43, 4, 415, "R/W", 0, 1, 0ull, 0},
- {"MIRRMASK" , 47, 4, 415, "R/W", 0, 1, 0ull, 0},
- {"INIT_STATUS" , 51, 4, 415, "R/W1", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R0" , 55, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R1" , 56, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R0" , 57, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R1" , 58, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"SCRZ" , 59, 1, 415, "R/W1", 0, 1, 0ull, 0},
- {"MODE32B" , 60, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 415, "RAZ", 1, 1, 0, 0},
- {"RDIMM_ENA" , 0, 1, 416, "R/W", 0, 1, 0ull, 0},
- {"BWCNT" , 1, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 2, 1, 416, "R/W", 0, 0, 0ull, 1ull},
- {"POCAS" , 3, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH2" , 4, 2, 416, "R/W", 0, 0, 0ull, 1ull},
- {"THROTTLE_RD" , 6, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"THROTTLE_WR" , 7, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_RD" , 8, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_WR" , 9, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"ELEV_PRIO_DIS" , 10, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"NXM_WRITE_EN" , 11, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 12, 4, 416, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 16, 1, 416, "R/W", 0, 0, 0ull, 1ull},
- {"AUTO_DCLKDIS" , 17, 1, 416, "R/W", 0, 0, 0ull, 1ull},
- {"INT_ZQCS_DIS" , 18, 1, 416, "R/W", 0, 0, 1ull, 0ull},
- {"EXT_ZQCS_DIS" , 19, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 20, 2, 416, "R/W", 0, 0, 0ull, 0ull},
- {"WODT_BPRCH" , 22, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_BPRCH" , 23, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"CRM_MAX" , 24, 5, 416, "R/W", 0, 0, 31ull, 31ull},
- {"CRM_THR" , 29, 5, 416, "R/W", 0, 0, 0ull, 8ull},
- {"CRM_CNT" , 34, 5, 416, "RO", 0, 0, 0ull, 0ull},
- {"THRMAX" , 39, 4, 416, "R/W", 0, 0, 15ull, 2ull},
- {"PERSUB" , 43, 8, 416, "R/W", 0, 0, 0ull, 0ull},
- {"THRCNT" , 51, 12, 416, "RO", 0, 0, 0ull, 0ull},
- {"SCRAMBLE_ENA" , 63, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"DCLKCNT" , 0, 64, 417, "RO", 0, 1, 0ull, 0},
- {"CLKF" , 0, 7, 418, "R/W", 0, 1, 48ull, 0},
- {"RESET_N" , 7, 1, 418, "R/W", 0, 0, 0ull, 1ull},
- {"CPB" , 8, 3, 418, "R/W", 0, 0, 0ull, 1ull},
- {"CPS" , 11, 3, 418, "R/W", 0, 0, 0ull, 1ull},
- {"DIFFAMP" , 14, 4, 418, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_PS_EN" , 18, 3, 418, "R/W", 0, 1, 2ull, 0},
- {"DDR_DIV_RESET" , 21, 1, 418, "R/W", 0, 0, 1ull, 0ull},
- {"DFM_PS_EN" , 22, 3, 418, "R/W", 0, 1, 2ull, 0},
- {"DFM_DIV_RESET" , 25, 1, 418, "R/W", 0, 0, 1ull, 0ull},
- {"JTG_TEST_MODE" , 26, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 418, "RAZ", 1, 1, 0, 0},
- {"RC0" , 0, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC1" , 4, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC2" , 8, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC3" , 12, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC4" , 16, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC5" , 20, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC6" , 24, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC7" , 28, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC8" , 32, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC9" , 36, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC10" , 40, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC11" , 44, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC12" , 48, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC13" , 52, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC14" , 56, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC15" , 60, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"DIMM0_WMASK" , 0, 16, 420, "R/W", 0, 0, 65535ull, 65535ull},
- {"DIMM1_WMASK" , 16, 16, 420, "R/W", 0, 0, 65535ull, 65535ull},
- {"TCWS" , 32, 13, 420, "R/W", 0, 0, 1248ull, 1248ull},
- {"PARITY" , 45, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 420, "RAZ", 1, 1, 0, 0},
- {"BYP_SETTING" , 0, 8, 421, "R/W", 0, 0, 0ull, 0ull},
- {"BYP_SEL" , 8, 4, 421, "R/W", 0, 0, 0ull, 0ull},
- {"QUAD_DLL_ENA" , 12, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 13, 1, 421, "R/W", 0, 0, 1ull, 0ull},
- {"DLL_BRINGUP" , 14, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"INTF_EN" , 15, 1, 421, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 421, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 422, "R/W", 0, 0, 0ull, 0ull},
- {"BYTE_SEL" , 6, 4, 422, "R/W", 0, 0, 0ull, 0ull},
- {"MODE_SEL" , 10, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"LOAD_OFFSET" , 12, 1, 422, "WR0", 0, 0, 0ull, 0ull},
- {"OFFSET_ENA" , 13, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYTE_SEL" , 14, 4, 422, "R/W", 0, 0, 1ull, 1ull},
- {"DLL_MODE" , 18, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"FINE_TUNE_MODE" , 19, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"DLL90_SETTING" , 20, 8, 422, "RO", 1, 1, 0, 0},
- {"DLL_FAST" , 28, 1, 422, "RO", 1, 1, 0, 0},
- {"DCLK90_BYP_SETTING" , 29, 8, 422, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_BYP_SEL" , 37, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_RECAL_DIS" , 38, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_90_DLY_BYP" , 39, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_FWD" , 40, 1, 422, "WR0", 0, 0, 0ull, 0ull},
- {"RESERVED_41_63" , 41, 23, 422, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 423, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 423, "RAZ", 1, 1, 0, 0},
- {"ROW_LSB" , 16, 3, 423, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_19_63" , 19, 45, 423, "RAZ", 1, 1, 0, 0},
- {"MRDSYN0" , 0, 8, 424, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 424, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 424, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 424, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 424, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 14, 425, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 14, 16, 425, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 30, 3, 425, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 33, 1, 425, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 34, 2, 425, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 425, "RAZ", 1, 1, 0, 0},
- {"IFBCNT" , 0, 64, 426, "RO", 0, 1, 1ull, 0},
- {"NXM_WR_ERR" , 0, 1, 427, "R/W1C", 0, 0, 0ull, 0ull},
- {"SEC_ERR" , 1, 4, 427, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 5, 4, 427, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 427, "RAZ", 1, 1, 0, 0},
- {"INTR_NXM_WR_ENA" , 0, 1, 428, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_SEC_ENA" , 1, 1, 428, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 2, 1, 428, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 428, "RAZ", 1, 1, 0, 0},
- {"CWL" , 0, 3, 429, "R/W", 0, 0, 0ull, 0ull},
- {"MPRLOC" , 3, 2, 429, "R/W", 0, 0, 0ull, 0ull},
- {"MPR" , 5, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"DLL" , 6, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"AL" , 7, 2, 429, "R/W", 0, 0, 0ull, 0ull},
- {"WLEV" , 9, 1, 429, "RO", 0, 0, 0ull, 0ull},
- {"TDQS" , 10, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"QOFF" , 11, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"BL" , 12, 2, 429, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 14, 4, 429, "R/W", 0, 0, 2ull, 2ull},
- {"RBT" , 18, 1, 429, "RO", 0, 0, 1ull, 1ull},
- {"TM" , 19, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"DLLR" , 20, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"WRP" , 21, 3, 429, "R/W", 0, 0, 0ull, 0ull},
- {"PPD" , 24, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 429, "RAZ", 1, 1, 0, 0},
- {"PASR_00" , 0, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_00" , 3, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_00" , 4, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_00" , 5, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_00" , 7, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_00" , 9, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_01" , 12, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_01" , 15, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_01" , 16, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_01" , 17, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_01" , 19, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_01" , 21, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_10" , 24, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_10" , 27, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_10" , 28, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_10" , 29, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_10" , 31, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_10" , 33, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_11" , 36, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_11" , 39, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_11" , 40, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_11" , 41, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_11" , 43, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_11" , 45, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 430, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R0" , 8, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R1" , 12, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R0" , 16, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R1" , 20, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R0" , 24, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R1" , 28, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R0" , 32, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R1" , 36, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 431, "RAZ", 1, 1, 0, 0},
- {"OPSCNT" , 0, 64, 432, "RO", 0, 1, 1ull, 0},
- {"TS_STAGGER" , 0, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK_POS" , 1, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK" , 2, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT0" , 3, 4, 433, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE0" , 7, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT1" , 8, 4, 433, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE1" , 12, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"LV_MODE" , 13, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"RX_ALWAYS_ON" , 14, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 433, "RAZ", 1, 1, 0, 0},
- {"DDR3RST" , 0, 1, 434, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PWARM" , 1, 1, 434, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSOFT" , 2, 1, 434, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSV" , 3, 1, 434, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 434, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 435, "R/W", 0, 1, 0ull, 0},
- {"OFFSET" , 4, 4, 435, "R/W", 0, 0, 2ull, 2ull},
- {"OFFSET_EN" , 8, 1, 435, "R/W", 0, 0, 1ull, 1ull},
- {"OR_DIS" , 9, 1, 435, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 10, 8, 435, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_0" , 18, 1, 435, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_1" , 19, 1, 435, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_2" , 20, 1, 435, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_3" , 21, 1, 435, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 435, "RAZ", 1, 1, 0, 0},
- {"BITMASK" , 0, 64, 436, "RO", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 6, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 12, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 18, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 24, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 30, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 36, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 42, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 48, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 54, 2, 437, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 437, "RAZ", 1, 1, 0, 0},
- {"RODT_D0_R0" , 0, 8, 438, "R/W", 0, 1, 0ull, 0},
- {"RODT_D0_R1" , 8, 8, 438, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R0" , 16, 8, 438, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R1" , 24, 8, 438, "R/W", 0, 1, 0ull, 0},
- {"RODT_D2_R0" , 32, 8, 438, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R1" , 40, 8, 438, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R0" , 48, 8, 438, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R1" , 56, 8, 438, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 0, 64, 439, "R/W", 0, 1, 0ull, 0},
- {"KEY" , 0, 64, 440, "R/W", 0, 1, 0ull, 0},
- {"FCOL" , 0, 14, 441, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 14, 16, 441, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 30, 3, 441, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 33, 1, 441, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 34, 2, 441, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 441, "RAZ", 1, 1, 0, 0},
- {"R2R_INIT" , 0, 6, 442, "R/W", 0, 1, 1ull, 0},
- {"R2W_INIT" , 6, 6, 442, "R/W", 0, 1, 6ull, 0},
- {"W2R_INIT" , 12, 6, 442, "R/W", 0, 1, 9ull, 0},
- {"W2W_INIT" , 18, 6, 442, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_24_63" , 24, 40, 442, "RAZ", 1, 1, 0, 0},
- {"R2R_XRANK_INIT" , 0, 6, 443, "R/W", 0, 1, 3ull, 0},
- {"R2W_XRANK_INIT" , 6, 6, 443, "R/W", 0, 1, 6ull, 0},
- {"W2R_XRANK_INIT" , 12, 6, 443, "R/W", 0, 1, 4ull, 0},
- {"W2W_XRANK_INIT" , 18, 6, 443, "R/W", 0, 1, 5ull, 0},
- {"RESERVED_24_63" , 24, 40, 443, "RAZ", 1, 1, 0, 0},
- {"R2R_XDIMM_INIT" , 0, 6, 444, "R/W", 0, 1, 4ull, 0},
- {"R2W_XDIMM_INIT" , 6, 6, 444, "R/W", 0, 1, 7ull, 0},
- {"W2R_XDIMM_INIT" , 12, 6, 444, "R/W", 0, 1, 4ull, 0},
- {"W2W_XDIMM_INIT" , 18, 6, 444, "R/W", 0, 1, 6ull, 0},
- {"RESERVED_24_63" , 24, 40, 444, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_9" , 0, 10, 445, "RAZ", 1, 1, 0, 0},
- {"TZQCS" , 10, 4, 445, "R/W", 0, 0, 4ull, 4ull},
- {"TCKE" , 14, 4, 445, "R/W", 0, 0, 3ull, 3ull},
- {"TXPR" , 18, 4, 445, "R/W", 0, 0, 5ull, 5ull},
- {"TMRD" , 22, 4, 445, "R/W", 0, 0, 4ull, 4ull},
- {"TMOD" , 26, 4, 445, "R/W", 0, 0, 12ull, 12ull},
- {"TDLLK" , 30, 4, 445, "R/W", 0, 0, 2ull, 2ull},
- {"TZQINIT" , 34, 4, 445, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 38, 4, 445, "R/W", 0, 0, 6ull, 6ull},
- {"TCKSRE" , 42, 4, 445, "R/W", 0, 0, 5ull, 5ull},
- {"TRP_EXT" , 46, 1, 445, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 445, "RAZ", 1, 1, 0, 0},
- {"TMPRR" , 0, 4, 446, "R/W", 0, 0, 1ull, 1ull},
- {"TRAS" , 4, 5, 446, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 9, 4, 446, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 13, 4, 446, "R/W", 0, 0, 2ull, 3ull},
- {"TRFC" , 17, 5, 446, "R/W", 0, 0, 6ull, 7ull},
- {"TRRD" , 22, 3, 446, "R/W", 0, 0, 2ull, 2ull},
- {"TXP" , 25, 3, 446, "R/W", 0, 0, 3ull, 3ull},
- {"TWLMRD" , 28, 4, 446, "R/W", 0, 0, 10ull, 10ull},
- {"TWLDQSEN" , 32, 4, 446, "R/W", 0, 0, 7ull, 7ull},
- {"TFAW" , 36, 5, 446, "R/W", 0, 0, 0ull, 9ull},
- {"TXPDLL" , 41, 5, 446, "R/W", 0, 0, 0ull, 10ull},
- {"TRAS_EXT" , 46, 1, 446, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 446, "RAZ", 1, 1, 0, 0},
- {"TRESET" , 0, 1, 447, "R/W", 0, 1, 1ull, 0},
- {"RCLK_CNT" , 1, 32, 447, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 447, "RAZ", 1, 1, 0, 0},
- {"RING_CNT" , 0, 32, 448, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 448, "RAZ", 1, 1, 0, 0},
- {"LANEMASK" , 0, 9, 449, "R/W", 0, 1, 0ull, 0},
- {"SSET" , 9, 1, 449, "R/W", 0, 1, 0ull, 0},
- {"OR_DIS" , 10, 1, 449, "R/W", 0, 1, 0ull, 0},
- {"BITMASK" , 11, 8, 449, "R/W", 0, 1, 0ull, 0},
- {"RTT_NOM" , 19, 3, 449, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 449, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 450, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 4, 8, 450, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 450, "RAZ", 1, 1, 0, 0},
- {"BYTE0" , 0, 5, 451, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 5, 5, 451, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 10, 5, 451, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 15, 5, 451, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 20, 5, 451, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 25, 5, 451, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 30, 5, 451, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 35, 5, 451, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 40, 5, 451, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 45, 2, 451, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_63" , 47, 17, 451, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 452, "R/W", 0, 1, 255ull, 0},
- {"WODT_D0_R1" , 8, 8, 452, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R0" , 16, 8, 452, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R1" , 24, 8, 452, "R/W", 0, 1, 255ull, 0},
- {"WODT_D2_R0" , 32, 8, 452, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D2_R1" , 40, 8, 452, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R0" , 48, 8, 452, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R1" , 56, 8, 452, "R/W", 0, 0, 255ull, 0ull},
- {"STAT" , 0, 12, 453, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 453, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 454, "R/W", 1, 1, 0, 0},
- {"PCTL" , 6, 6, 454, "R/W", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 454, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 455, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 455, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 455, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 456, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 456, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 456, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 457, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 457, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 457, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 458, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 458, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 458, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 458, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 458, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 458, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 458, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 458, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 458, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 458, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 458, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 458, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 458, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 458, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 458, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 459, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 459, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 459, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 460, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 460, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 460, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 461, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 461, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 461, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 462, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 462, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 462, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 462, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 462, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 463, "R/W", 1, 1, 0, 0},
- {"USER0" , 0, 8, 464, "RO", 1, 1, 0, 0},
- {"NAND" , 8, 1, 464, "RO", 1, 1, 0, 0},
- {"TERM" , 9, 2, 464, "RO", 1, 1, 0, 0},
- {"DMACK_P0" , 11, 1, 464, "RO", 1, 1, 0, 0},
- {"DMACK_P1" , 12, 1, 464, "RO", 1, 1, 0, 0},
- {"RESERVED_13_13" , 13, 1, 464, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 14, 1, 464, "RO", 1, 1, 0, 0},
- {"ALE" , 15, 1, 464, "RO", 1, 1, 0, 0},
- {"USER1" , 16, 16, 464, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 464, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 16, 465, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 465, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 465, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 465, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 465, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 465, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 465, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 465, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 465, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 465, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 465, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 465, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 465, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 466, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 466, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 466, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 466, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 466, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 466, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 466, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 466, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 466, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 466, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 466, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 466, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 466, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 467, "R/W", 0, 0, 25ull, 25ull},
- {"RESERVED_6_7" , 6, 2, 467, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 467, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 467, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 467, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 467, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 468, "R/W", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 469, "R/W", 0, 1, 0ull, 0},
- {"BUF_NUM" , 6, 1, 469, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 469, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 1, 469, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 469, "RAZ", 0, 1, 0ull, 0},
- {"BUS_ENA" , 0, 4, 470, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_15" , 4, 12, 470, "RAZ", 0, 1, 0ull, 0},
- {"BOOT_FAIL" , 16, 1, 470, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 470, "RAZ", 0, 1, 0ull, 0},
- {"ARG" , 0, 32, 471, "R/W", 0, 1, 0ull, 0},
- {"CMD_IDX" , 32, 6, 471, "R/W", 0, 1, 0ull, 0},
- {"RTYPE_XOR" , 38, 3, 471, "R/W", 0, 1, 0ull, 0},
- {"CTYPE_XOR" , 41, 2, 471, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_48" , 43, 6, 471, "RAZ", 0, 1, 0ull, 0},
- {"OFFSET" , 49, 6, 471, "R/W", 0, 1, 0ull, 0},
- {"DBUF" , 55, 1, 471, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_56_58" , 56, 3, 471, "RAZ", 0, 1, 0ull, 0},
- {"CMD_VAL" , 59, 1, 471, "R/W", 1, 1, 0, 0},
- {"BUS_ID" , 60, 2, 471, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 471, "RAZ", 0, 1, 0ull, 0},
- {"CARD_ADDR" , 0, 32, 472, "R/W", 0, 1, 0ull, 0},
- {"BLOCK_CNT" , 32, 16, 472, "R/W", 0, 1, 0ull, 0},
- {"MULTI" , 48, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"RW" , 49, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"REL_WR" , 50, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"THRES" , 51, 6, 472, "R/W", 0, 1, 0ull, 0},
- {"DAT_NULL" , 57, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"SECTOR" , 58, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"DMA_VAL" , 59, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"BUS_ID" , 60, 2, 472, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 472, "RAZ", 0, 1, 0ull, 0},
- {"BUF_DONE" , 0, 1, 473, "R/W1C", 1, 1, 0, 0},
- {"CMD_DONE" , 1, 1, 473, "R/W1C", 1, 1, 0, 0},
- {"DMA_DONE" , 2, 1, 473, "R/W1C", 1, 1, 0, 0},
- {"CMD_ERR" , 3, 1, 473, "R/W1C", 1, 1, 0, 0},
- {"DMA_ERR" , 4, 1, 473, "R/W1C", 1, 1, 0, 0},
- {"SWITCH_DONE" , 5, 1, 473, "R/W1C", 1, 1, 0, 0},
- {"SWITCH_ERR" , 6, 1, 473, "R/W1C", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 473, "RAZ", 0, 1, 0ull, 0},
- {"BUF_DONE" , 0, 1, 474, "R/W", 1, 1, 0, 0},
- {"CMD_DONE" , 1, 1, 474, "R/W", 1, 1, 0, 0},
- {"DMA_DONE" , 2, 1, 474, "R/W", 1, 1, 0, 0},
- {"CMD_ERR" , 3, 1, 474, "R/W", 1, 1, 0, 0},
- {"DMA_ERR" , 4, 1, 474, "R/W", 1, 1, 0, 0},
- {"SWITCH_DONE" , 5, 1, 474, "R/W", 1, 1, 0, 0},
- {"SWITCH_ERR" , 6, 1, 474, "R/W", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 474, "RAZ", 0, 1, 0ull, 0},
- {"CLK_LO" , 0, 16, 475, "RO", 0, 1, 2500ull, 0},
- {"CLK_HI" , 16, 16, 475, "RO", 0, 1, 2500ull, 0},
- {"POWER_CLASS" , 32, 4, 475, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 475, "RAZ", 0, 1, 0ull, 0},
- {"BUS_WIDTH" , 40, 3, 475, "RO", 0, 1, 0ull, 0},
- {"RESERVED_43_47" , 43, 5, 475, "RAZ", 0, 1, 0ull, 0},
- {"HS_TIMING" , 48, 1, 475, "RO", 0, 1, 0ull, 0},
- {"RESERVED_49_63" , 49, 15, 475, "RAZ", 0, 1, 0ull, 0},
- {"CARD_RCA" , 0, 16, 476, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 476, "RAZ", 0, 1, 0ull, 0},
- {"DAT" , 0, 64, 477, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 64, 478, "RO", 1, 1, 0, 0},
- {"CMD_DONE" , 0, 1, 479, "RO", 0, 1, 0ull, 0},
- {"CMD_IDX" , 1, 6, 479, "RO", 0, 1, 0ull, 0},
- {"CMD_TYPE" , 7, 2, 479, "RO", 0, 1, 0ull, 0},
- {"RSP_TYPE" , 9, 3, 479, "RO", 0, 1, 0ull, 0},
- {"RSP_VAL" , 12, 1, 479, "RO", 0, 1, 0ull, 0},
- {"RSP_BAD_STS" , 13, 1, 479, "RO", 0, 1, 0ull, 0},
- {"RSP_CRC_ERR" , 14, 1, 479, "RO", 0, 1, 0ull, 0},
- {"RSP_TIMEOUT" , 15, 1, 479, "RO", 0, 1, 0ull, 0},
- {"STP_VAL" , 16, 1, 479, "RO", 0, 1, 0ull, 0},
- {"STP_BAD_STS" , 17, 1, 479, "RO", 0, 1, 0ull, 0},
- {"STP_CRC_ERR" , 18, 1, 479, "RO", 0, 1, 0ull, 0},
- {"STP_TIMEOUT" , 19, 1, 479, "RO", 0, 1, 0ull, 0},
- {"RSP_BUSYBIT" , 20, 1, 479, "RO", 0, 1, 0ull, 0},
- {"BLK_CRC_ERR" , 21, 1, 479, "RO", 0, 1, 0ull, 0},
- {"BLK_TIMEOUT" , 22, 1, 479, "RO", 0, 1, 0ull, 0},
- {"DBUF" , 23, 1, 479, "RO", 0, 1, 0ull, 0},
- {"RESERVED_24_27" , 24, 4, 479, "RAZ", 0, 1, 0ull, 0},
- {"DBUF_ERR" , 28, 1, 479, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_55" , 29, 27, 479, "RAZ", 0, 1, 0ull, 0},
- {"DMA_PEND" , 56, 1, 479, "RO", 0, 1, 0ull, 0},
- {"DMA_VAL" , 57, 1, 479, "RO", 0, 1, 0ull, 0},
- {"SWITCH_VAL" , 58, 1, 479, "RO", 0, 1, 0ull, 0},
- {"CMD_VAL" , 59, 1, 479, "RO", 0, 1, 0ull, 0},
- {"BUS_ID" , 60, 2, 479, "RO", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 479, "RAZ", 0, 1, 0ull, 0},
- {"DAT_CNT" , 0, 10, 480, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 480, "RAZ", 0, 1, 0ull, 0},
- {"CMD_CNT" , 16, 10, 480, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 480, "RAZ", 0, 1, 0ull, 0},
- {"STS_MSK" , 0, 32, 481, "R/W", 0, 1, 3828940928ull, 0},
- {"RESERVED_32_63" , 32, 32, 481, "RAZ", 0, 1, 0ull, 0},
- {"CLK_LO" , 0, 16, 482, "R/W", 0, 1, 2500ull, 0},
- {"CLK_HI" , 16, 16, 482, "R/W", 0, 1, 2500ull, 0},
- {"POWER_CLASS" , 32, 4, 482, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 482, "RAZ", 0, 1, 0ull, 0},
- {"BUS_WIDTH" , 40, 3, 482, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_47" , 43, 5, 482, "RAZ", 0, 1, 0ull, 0},
- {"HS_TIMING" , 48, 1, 482, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_49_55" , 49, 7, 482, "RAZ", 0, 1, 0ull, 0},
- {"SWITCH_ERR2" , 56, 1, 482, "RO", 0, 1, 0ull, 0},
- {"SWITCH_ERR1" , 57, 1, 482, "RO", 0, 1, 0ull, 0},
- {"SWITCH_ERR0" , 58, 1, 482, "RO", 0, 1, 0ull, 0},
- {"SWITCH_EXE" , 59, 1, 482, "R/W", 0, 1, 0ull, 0},
- {"BUS_ID" , 60, 2, 482, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 482, "RAZ", 0, 1, 0ull, 0},
- {"CLK_CNT" , 0, 26, 483, "R/W", 0, 1, 41855000ull, 0},
- {"RESERVED_26_63" , 26, 38, 483, "RAZ", 0, 1, 0ull, 0},
- {"DAT" , 0, 64, 484, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 485, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 485, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 486, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 486, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 4, 487, "RO", 1, 1, 0, 0},
- {"RESERVED_4_15" , 4, 12, 487, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 487, "RO", 1, 1, 0, 0},
- {"RESERVED_24_25" , 24, 2, 487, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 487, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 487, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 487, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 487, "RO", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 487, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 487, "RO", 1, 1, 0, 0},
- {"DORM_CRYPTO" , 34, 1, 487, "RO", 1, 1, 0, 0},
- {"POWER_LIMIT" , 35, 2, 487, "RO", 1, 1, 0, 0},
- {"ROM_INFO" , 37, 10, 487, "RO", 1, 1, 0, 0},
- {"FUS118" , 47, 1, 487, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 487, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 488, "RAZ", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 488, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 488, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 488, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 488, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 488, "RO", 1, 1, 0, 0},
- {"ZIP_INFO" , 29, 2, 488, "RO", 1, 1, 0, 0},
- {"RESERVED_31_31" , 31, 1, 488, "RAZ", 1, 1, 0, 0},
- {"L2C_CRIP" , 32, 3, 488, "RO", 1, 1, 0, 0},
- {"PLL_HALF_DIS" , 35, 1, 488, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_MAN" , 36, 1, 488, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_RSV" , 37, 1, 488, "RO", 1, 1, 0, 0},
- {"EMA" , 38, 2, 488, "RO", 1, 1, 0, 0},
- {"RESERVED_40_40" , 40, 1, 488, "RAZ", 1, 1, 0, 0},
- {"DFA_INFO_CLM" , 41, 4, 488, "RO", 1, 1, 0, 0},
- {"DFA_INFO_DTE" , 45, 3, 488, "RO", 1, 1, 0, 0},
- {"PLL_CTL" , 48, 10, 488, "RO", 1, 1, 0, 0},
- {"RESERVED_58_63" , 58, 6, 488, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 489, "RAZ", 1, 1, 0, 0},
- {"RESERVED_3_3" , 3, 1, 489, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 489, "RAZ", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 489, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 490, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 491, "RAZ", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 491, "RAZ", 0, 1, 0ull, 0},
- {"PNR_COUT_SEL" , 2, 2, 491, "R/W", 0, 1, 0ull, 0},
- {"PNR_COUT_RST" , 4, 1, 491, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_SEL" , 5, 2, 491, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_RST" , 7, 1, 491, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 491, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 492, "R/W", 1, 1, 0, 0},
- {"SOFT" , 1, 1, 492, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 492, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 6, 493, "R/W", 0, 1, 1ull, 0},
- {"SCLK_HI" , 6, 15, 493, "R/W", 0, 1, 5000ull, 0},
- {"SCLK_LO" , 21, 4, 493, "R/W", 0, 1, 1ull, 0},
- {"OUT" , 25, 7, 493, "R/W", 0, 1, 1ull, 0},
- {"PROG_PIN" , 32, 1, 493, "RO", 0, 0, 0ull, 0ull},
- {"FSRC_PIN" , 33, 1, 493, "RO", 0, 0, 0ull, 0ull},
- {"VGATE_PIN" , 34, 1, 493, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 493, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 494, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 494, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 494, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 494, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 494, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 10, 495, "R/W", 0, 1, 999ull, 0},
- {"SDH" , 10, 4, 495, "R/W", 0, 1, 0ull, 0},
- {"PRH" , 14, 4, 495, "R/W", 0, 1, 6ull, 0},
- {"FSH" , 18, 4, 495, "R/W", 0, 1, 15ull, 0},
- {"SCH" , 22, 4, 495, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_26_63" , 26, 38, 495, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 18, 496, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 18, 18, 496, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 36, 18, 496, "RO", 0, 0, 0ull, 0ull},
- {"TOO_MANY" , 54, 1, 496, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 496, "RAZ", 1, 1, 0, 0},
- {"REPAIR3" , 0, 18, 497, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR4" , 18, 18, 497, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR5" , 36, 18, 497, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 497, "RAZ", 1, 1, 0, 0},
- {"REPAIR6" , 0, 18, 498, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 498, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 499, "RAZ", 1, 1, 0, 0},
- {"REPAIR1" , 14, 14, 499, "RAZ", 1, 1, 0, 0},
- {"REPAIR2" , 28, 14, 499, "RAZ", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 499, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 500, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 500, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 63, 501, "RO", 1, 1, 0, 0},
- {"VAL" , 63, 1, 501, "R/W", 1, 1, 0, 0},
- {"ADDR" , 0, 4, 502, "R/W", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 502, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 503, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 6, 6, 503, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_12_63" , 12, 52, 503, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 504, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 504, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 504, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 505, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 505, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 506, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 506, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 507, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 507, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 508, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 508, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 509, "R/W", 0, 0, 18446744073709551615ull, 0ull},
- {"FRNANOSEC" , 0, 32, 510, "R/W", 0, 0, 4294967295ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 510, "RAZ", 1, 1, 0, 0},
- {"PTP_EN" , 0, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EN" , 1, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_IN" , 2, 6, 511, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EN" , 8, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EDGE" , 9, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_IN" , 10, 6, 511, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EN" , 16, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EDGE" , 17, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_IN" , 18, 6, 511, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_EN" , 24, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_INV" , 25, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_OUT" , 26, 4, 511, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_EN" , 30, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_INV" , 31, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_OUT" , 32, 5, 511, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_OUT4" , 37, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EDGE" , 38, 2, 511, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT" , 40, 1, 511, "RO", 1, 0, 0, 0ull},
- {"PPS" , 41, 1, 511, "RO", 1, 0, 0, 0ull},
- {"RESERVED_42_63" , 42, 22, 511, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 512, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 512, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 513, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 514, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 514, "RAZ", 1, 1, 0, 0},
- {"CNTR" , 0, 64, 515, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 516, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 516, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 517, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 517, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 518, "R/W", 0, 0, 18446744073709551615ull, 0ull},
- {"FRNANOSEC" , 0, 32, 519, "R/W", 0, 0, 4294967295ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 519, "RAZ", 1, 1, 0, 0},
- {"NANOSEC" , 0, 64, 520, "R/W", 0, 0, 0ull, 0ull},
- {"QLM_CFG" , 0, 2, 521, "R/W", 1, 1, 0, 0},
- {"RESERVED_2_7" , 2, 6, 521, "RAZ", 1, 1, 0, 0},
- {"QLM_SPD" , 8, 4, 521, "R/W", 1, 1, 0, 0},
- {"RESERVED_12_13" , 12, 2, 521, "RAZ", 1, 1, 0, 0},
- {"PRTMODE" , 14, 1, 521, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 521, "RAZ", 1, 1, 0, 0},
- {"RBOOT_PIN" , 0, 1, 522, "RO", 1, 1, 0, 0},
- {"RBOOT" , 1, 1, 522, "R/W", 1, 1, 0, 0},
- {"LBOOT" , 2, 10, 522, "R/W1C", 1, 1, 0, 0},
- {"QLM0_SPD" , 12, 4, 522, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 16, 4, 522, "RO", 1, 1, 0, 0},
- {"QLM2_SPD" , 20, 4, 522, "RO", 1, 1, 0, 0},
- {"PNR_MUL" , 24, 6, 522, "RO", 1, 1, 0, 0},
- {"C_MUL" , 30, 6, 522, "RO", 1, 1, 0, 0},
- {"RESERVED_36_47" , 36, 12, 522, "RAZ", 1, 1, 0, 0},
- {"LBOOT_EXT" , 48, 2, 522, "R/W1C", 1, 1, 0, 0},
- {"RESERVED_50_57" , 50, 8, 522, "RAZ", 1, 1, 0, 0},
- {"JT_TSTMODE" , 58, 1, 522, "RO", 1, 1, 0, 0},
- {"CKILL_PPDIS" , 59, 1, 522, "R/W", 0, 1, 1ull, 0},
- {"ROMEN" , 60, 1, 522, "R/W", 1, 1, 0, 0},
- {"EJTAGDIS" , 61, 1, 522, "R/W", 1, 1, 0, 0},
- {"JTCSRDIS" , 62, 1, 522, "R/W", 1, 1, 0, 0},
- {"CHIPKILL" , 63, 1, 522, "R/W1", 0, 0, 0ull, 0ull},
- {"SOFT_CLR_BIST" , 0, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"WARM_CLR_BIST" , 1, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"CNTL_CLR_BIST" , 2, 1, 523, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_5" , 3, 3, 523, "RAZ", 1, 1, 0, 0},
- {"BIST_DELAY" , 6, 58, 523, "RO", 1, 1, 0, 0},
- {"TIMER" , 0, 47, 524, "R/W", 0, 1, 17179869183ull, 0},
- {"RESERVED_47_63" , 47, 17, 524, "RAZ", 0, 0, 0ull, 0ull},
- {"RST_VAL" , 0, 1, 525, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 525, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 525, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 525, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 525, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 525, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 525, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 525, "RO", 1, 1, 0, 0},
- {"PRST_LINK" , 9, 1, 525, "R/W", 0, 1, 0ull, 0},
- {"GEN1_ONLY" , 10, 1, 525, "RO", 0, 1, 0ull, 0},
- {"REV_LANES" , 11, 1, 525, "R/W", 1, 1, 0, 0},
- {"IN_REV_LN" , 12, 1, 525, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 525, "RAZ", 1, 1, 0, 0},
- {"RST_VAL" , 0, 1, 526, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 526, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 526, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 526, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 526, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 526, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 526, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 526, "RO", 1, 1, 0, 0},
- {"PRST_LINK" , 9, 1, 526, "R/W", 0, 1, 0ull, 0},
- {"GEN1_ONLY" , 10, 1, 526, "RO", 0, 1, 0ull, 0},
- {"REV_LANES" , 11, 1, 526, "R/W", 1, 1, 0, 0},
- {"IN_REV_LN" , 12, 1, 526, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 526, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST_DLY" , 0, 16, 527, "R/W", 0, 1, 2047ull, 0},
- {"WARM_RST_DLY" , 16, 16, 527, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_32_63" , 32, 32, 527, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 528, "R/W1C", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 528, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 528, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 528, "R/W1C", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 528, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 528, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 529, "R/W", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 529, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 529, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 529, "R/W", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 529, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 529, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 530, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 530, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 530, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 530, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 530, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 530, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 530, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 530, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 530, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 530, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 530, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 530, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 530, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 531, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 531, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 531, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 531, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 531, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 531, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 531, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 531, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 531, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 531, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 531, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 531, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 532, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 532, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 532, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 533, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 533, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 533, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 534, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 534, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 535, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 535, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 536, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 536, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 537, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 537, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 537, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 537, "RAZ", 1, 1, 0, 0},
- {"TXTRIG" , 4, 2, 537, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 537, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 537, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 538, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 538, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 539, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 539, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 539, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 539, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 539, "RAZ", 1, 1, 0, 0},
- {"PTIME" , 7, 1, 539, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 539, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 540, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 540, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 540, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 540, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 541, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 541, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 541, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 541, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 541, "RAZ", 1, 1, 0, 0},
- {"BRK" , 6, 1, 541, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 541, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 541, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 542, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 542, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 542, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 542, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 542, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 542, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 542, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 542, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 542, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 543, "RAZ", 1, 1, 0, 0},
- {"DCTS" , 0, 1, 544, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 544, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 544, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 544, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 544, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 544, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 544, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 544, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 544, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 545, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 545, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 546, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 546, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 547, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 547, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 547, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 547, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 548, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 549, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 549, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 550, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 550, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 551, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 551, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 551, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 551, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 552, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 552, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 553, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 553, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 554, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 554, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 555, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 555, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 556, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 556, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 557, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 557, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 558, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 558, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 558, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 558, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 558, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 558, "RAZ", 1, 1, 0, 0},
- {"ORFDAT" , 0, 1, 559, "RO", 0, 0, 0ull, 0ull},
- {"IRFDAT" , 1, 1, 559, "RO", 0, 0, 0ull, 0ull},
- {"IPFDAT" , 2, 1, 559, "RO", 0, 0, 0ull, 0ull},
- {"MRQDAT" , 3, 1, 559, "RO", 0, 0, 0ull, 0ull},
- {"MRGDAT" , 4, 1, 559, "RO", 0, 0, 0ull, 0ull},
- {"OPFDAT" , 5, 1, 559, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 559, "RAZ", 0, 0, 0ull, 0ull},
- {"MRQ_HWM" , 0, 2, 560, "R/W", 0, 0, 0ull, 1ull},
- {"NBTARB" , 2, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"LENDIAN" , 3, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 4, 1, 560, "R/W", 0, 0, 1ull, 0ull},
- {"EN" , 5, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 6, 1, 560, "RO", 0, 0, 0ull, 0ull},
- {"CRC_STRIP" , 7, 1, 560, "R/W", 0, 0, 0ull, 0ull},
- {"TS_THRESH" , 8, 4, 560, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 560, "RAZ", 1, 1, 0, 0},
- {"OVFENA" , 0, 1, 561, "R/W", 0, 0, 0ull, 0ull},
- {"IVFENA" , 1, 1, 561, "R/W", 0, 0, 0ull, 0ull},
- {"OTHENA" , 2, 1, 561, "R/W", 0, 0, 0ull, 0ull},
- {"ITHENA" , 3, 1, 561, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_DRPENA" , 4, 1, 561, "R/W", 0, 0, 0ull, 0ull},
- {"IRUNENA" , 5, 1, 561, "R/W", 0, 0, 0ull, 0ull},
- {"ORUNENA" , 6, 1, 561, "R/W", 0, 0, 0ull, 0ull},
- {"TSENA" , 7, 1, 561, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 561, "RAZ", 1, 1, 0, 0},
- {"IRCNT" , 0, 20, 562, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 562, "RAZ", 1, 1, 0, 0},
- {"IRHWM" , 0, 20, 563, "R/W", 0, 0, 0ull, 0ull},
- {"IBPLWM" , 20, 20, 563, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 563, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 564, "RAZ", 1, 1, 0, 0},
- {"IBASE" , 3, 37, 564, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 40, 20, 564, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 564, "RAZ", 1, 1, 0, 0},
- {"IDBELL" , 0, 20, 565, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 565, "RAZ", 1, 1, 0, 0},
- {"ITLPTR" , 32, 20, 565, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 565, "RAZ", 1, 1, 0, 0},
- {"ODBLOVF" , 0, 1, 566, "R/W1C", 0, 0, 0ull, 0ull},
- {"IDBLOVF" , 1, 1, 566, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORTHRESH" , 2, 1, 566, "RO", 0, 0, 0ull, 0ull},
- {"IRTHRESH" , 3, 1, 566, "RO", 0, 0, 0ull, 0ull},
- {"DATA_DRP" , 4, 1, 566, "R/W1C", 0, 0, 0ull, 0ull},
- {"IRUN" , 5, 1, 566, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORUN" , 6, 1, 566, "R/W1C", 0, 0, 0ull, 0ull},
- {"TS" , 7, 1, 566, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 566, "RAZ", 1, 1, 0, 0},
- {"ORCNT" , 0, 20, 567, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 567, "RAZ", 1, 1, 0, 0},
- {"ORHWM" , 0, 20, 568, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 568, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 569, "RAZ", 1, 1, 0, 0},
- {"OBASE" , 3, 37, 569, "R/W", 0, 1, 0ull, 0},
- {"OSIZE" , 40, 20, 569, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 569, "RAZ", 1, 1, 0, 0},
- {"ODBELL" , 0, 20, 570, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 570, "RAZ", 1, 1, 0, 0},
- {"OTLPTR" , 32, 20, 570, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 570, "RAZ", 1, 1, 0, 0},
- {"OREMCNT" , 0, 20, 571, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 571, "RAZ", 1, 1, 0, 0},
- {"IREMCNT" , 32, 20, 571, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_52_63" , 52, 12, 571, "RAZ", 1, 1, 0, 0},
- {"TSCNT" , 0, 5, 572, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 572, "RAZ", 1, 1, 0, 0},
- {"TSTOT" , 8, 5, 572, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 572, "RAZ", 1, 1, 0, 0},
- {"TSAVL" , 16, 5, 572, "RO", 0, 0, 4ull, 4ull},
- {"RESERVED_21_63" , 21, 43, 572, "RAZ", 1, 1, 0, 0},
- {"TSTAMP" , 0, 64, 573, "RO", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"IDLELO" , 1, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_CONT" , 2, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"WIREOR" , 3, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 4, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"INT_ENA" , 5, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 574, "RAZ", 1, 1, 0, 0},
- {"CSHI" , 7, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"IDLECLKS" , 8, 2, 574, "R/W", 0, 0, 0ull, 0ull},
- {"TRITX" , 10, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"CSLATE" , 11, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"CSENA0" , 12, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"CSENA1" , 13, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 574, "RAZ", 1, 1, 0, 0},
- {"CLKDIV" , 16, 13, 574, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 574, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 8, 575, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 575, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 576, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 576, "RAZ", 1, 1, 0, 0},
- {"RXNUM" , 8, 5, 576, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 576, "RAZ", 1, 1, 0, 0},
- {"TOTNUM" , 0, 5, 577, "WO", 1, 0, 0, 2ull},
- {"RESERVED_5_7" , 5, 3, 577, "RAZ", 1, 1, 0, 0},
- {"TXNUM" , 8, 5, 577, "WO", 1, 0, 0, 1ull},
- {"RESERVED_13_15" , 13, 3, 577, "RAZ", 1, 1, 0, 0},
- {"LEAVECS" , 16, 1, 577, "WO", 1, 0, 0, 0ull},
- {"RESERVED_17_19" , 17, 3, 577, "RAZ", 1, 1, 0, 0},
- {"CSID" , 20, 1, 577, "WO", 1, 0, 0, 0ull},
- {"RESERVED_21_63" , 21, 43, 577, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 578, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 578, "RO/WRSL", 0, 0, 147ull, 147ull},
- {"ISAE" , 0, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 579, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 579, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 579, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 579, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 580, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 580, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 580, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 580, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 581, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 581, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 581, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 581, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 581, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 582, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 582, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 582, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 582, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 582, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 583, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 583, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 584, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 585, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 586, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 586, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 586, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 586, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 586, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 587, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 587, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 588, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 589, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 590, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 590, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 590, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 590, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 591, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 591, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_8" , 0, 9, 592, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 9, 23, 592, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 593, "WORSL", 0, 0, 511ull, 511ull},
- {"CISP" , 0, 32, 594, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 595, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 595, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 596, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 596, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 596, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 597, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 597, "WORSL", 0, 0, 32767ull, 32767ull},
- {"CP" , 0, 8, 598, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 598, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 599, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 599, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 599, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 599, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 600, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 600, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 600, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 600, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 600, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 600, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 600, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 600, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 600, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 600, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 601, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 601, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 601, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 601, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 601, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 601, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 601, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 601, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 601, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 601, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 601, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 601, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 602, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 602, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 602, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 602, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PVM" , 24, 1, 602, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 602, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 603, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 603, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 604, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 605, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 605, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 606, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 606, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 606, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 606, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 606, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 606, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 606, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 607, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 607, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 607, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 607, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 607, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 607, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 607, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 607, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 607, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 607, "RO", 0, 0, 0ull, 0ull},
- {"FLR_CAP" , 28, 1, 607, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 607, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 608, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 608, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 608, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 608, "R/W", 0, 0, 2ull, 2ull},
- {"I_FLR" , 15, 1, 608, "RO", 0, 0, 0ull, 0ull},
- {"CE_D" , 16, 1, 608, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 608, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 608, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 608, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 608, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 608, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 608, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 609, "RO/WRSL", 1, 1, 0, 0},
- {"MLW" , 4, 6, 609, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"ASLPMS" , 10, 2, 609, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 609, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 609, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 609, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 609, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 609, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 609, "RO", 0, 0, 0ull, 0ull},
- {"ASPM" , 22, 1, 609, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 609, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 609, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 610, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 610, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 610, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 610, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 610, "RO", 0, 0, 1ull, 4ull},
- {"RESERVED_26_26" , 26, 1, 610, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 610, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"LBM" , 30, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 611, "RO", 0, 0, 15ull, 15ull},
- {"CTDS" , 4, 1, 611, "RO", 0, 0, 1ull, 1ull},
- {"ARI" , 5, 1, 611, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OPS" , 6, 1, 611, "RO", 0, 0, 0ull, 0ull},
- {"ATOM32S" , 7, 1, 611, "RO", 0, 0, 0ull, 0ull},
- {"ATOM64S" , 8, 1, 611, "RO", 0, 0, 0ull, 0ull},
- {"ATOM128S" , 9, 1, 611, "RO", 0, 0, 0ull, 0ull},
- {"NOROPRPR" , 10, 1, 611, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 611, "RAZ", 1, 1, 0, 0},
- {"TPH" , 12, 2, 611, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 611, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 612, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"ARI" , 5, 1, 612, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP" , 6, 1, 612, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP_EB" , 7, 1, 612, "RO", 0, 0, 0ull, 0ull},
- {"ID0_RQ" , 8, 1, 612, "RO", 0, 0, 0ull, 0ull},
- {"ID0_CP" , 9, 1, 612, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 612, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 613, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 613, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 613, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 613, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 614, "R/W", 1, 0, 0, 2ull},
- {"EC" , 4, 1, 614, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 614, "RO", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 614, "RO", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 614, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 614, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 614, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 614, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 614, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 614, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 614, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 615, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 615, "RO", 0, 0, 2ull, 2ull},
- {"NCO" , 20, 12, 615, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 616, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 616, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 616, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 616, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 616, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 616, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 616, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 616, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 616, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 616, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 616, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 616, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 616, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 616, "RAZ", 1, 1, 0, 0},
- {"UATOMBS" , 24, 1, 616, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 616, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 617, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 617, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 617, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 617, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 617, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 617, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 617, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 617, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 617, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 617, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 617, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 617, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 617, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 617, "RAZ", 1, 1, 0, 0},
- {"UATOMBM" , 24, 1, 617, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 617, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 618, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 618, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 618, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 618, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 618, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 618, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 618, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 618, "RO", 0, 0, 2ull, 2ull},
- {"UATOMBS" , 24, 1, 618, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 618, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 619, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 619, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 619, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 620, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 620, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 620, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 620, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 620, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 620, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 620, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 620, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 620, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 621, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 621, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 621, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 621, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 622, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 623, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 624, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 625, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 626, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 626, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 627, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 628, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 628, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 628, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 628, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 628, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 628, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 629, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 629, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 629, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 629, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 629, "R/W", 0, 0, 3ull, 3ull},
- {"EASPML1" , 30, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 629, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 630, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 630, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 630, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 630, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 630, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_22_31" , 22, 10, 630, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 631, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 631, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 631, "R/W", 0, 0, 0ull, 0ull},
- {"MFUNCN" , 0, 8, 632, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_13" , 8, 6, 632, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 632, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 632, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 632, "R/W", 0, 0, 0ull, 0ull},
- {"CX_NFUNC" , 29, 3, 632, "R/W", 0, 0, 0ull, 0ull},
- {"SKPIV" , 0, 11, 633, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 633, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 633, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 633, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 634, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 634, "R/W", 0, 0, 0ull, 0ull},
- {"M_DABORT_4UCPL" , 2, 1, 634, "R/W", 0, 0, 0ull, 0ull},
- {"M_HANDLE_FLUSH" , 3, 1, 634, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 634, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 635, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 636, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 637, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 637, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 637, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 638, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 638, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 638, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 639, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 639, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 639, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 640, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 640, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 640, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 640, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 641, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 641, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 641, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 641, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 642, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 642, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 642, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 642, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 643, "RO/WRSL", 0, 0, 56ull, 56ull},
- {"HEADER_CREDITS" , 12, 8, 643, "RO/WRSL", 0, 0, 31ull, 31ull},
- {"RESERVED_20_20" , 20, 1, 643, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 643, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 643, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 643, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 643, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 644, "RO/WRSL", 0, 0, 13ull, 13ull},
- {"HEADER_CREDITS" , 12, 8, 644, "RO/WRSL", 0, 0, 31ull, 31ull},
- {"RESERVED_20_20" , 20, 1, 644, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 644, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 644, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 645, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 645, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 645, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 645, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 645, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 646, "RO/WRSL", 0, 0, 183ull, 183ull},
- {"RESERVED_14_15" , 14, 2, 646, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 646, "RO/WRSL", 0, 0, 37ull, 37ull},
- {"RESERVED_26_31" , 26, 6, 646, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 647, "RO/WRSL", 0, 0, 97ull, 97ull},
- {"RESERVED_14_15" , 14, 2, 647, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 647, "RO/WRSL", 0, 0, 37ull, 37ull},
- {"RESERVED_26_31" , 26, 6, 647, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 648, "RO/WRSL", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 648, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 648, "RO/WRSL", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 648, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 649, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 649, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 649, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 650, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 651, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 652, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 652, "R/W", 0, 0, 147ull, 147ull},
- {"ISAE" , 0, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 653, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 653, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 653, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 653, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 653, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 653, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 653, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 653, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 653, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 653, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 653, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 653, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 653, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 653, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 653, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 653, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 653, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 653, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 654, "R/W", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 654, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 654, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 654, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 655, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 655, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 655, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 655, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 656, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 657, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 658, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 658, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 658, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 658, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 659, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 659, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 659, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 659, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 659, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 659, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 659, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 659, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 659, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 659, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 659, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 660, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 660, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 660, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 660, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 661, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 661, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 661, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 661, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 661, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 661, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 662, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 663, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 664, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 664, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 665, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 665, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 666, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 667, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 667, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 667, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 667, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 667, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 667, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 667, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 667, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 667, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 668, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 668, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 668, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 668, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 668, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 668, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 668, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 669, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 669, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 669, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 669, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 669, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 669, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 669, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 669, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 669, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 669, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 670, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 670, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 670, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 670, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 670, "R/W", 0, 0, 1ull, 1ull},
- {"PVM" , 24, 1, 670, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 670, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 671, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 671, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 672, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 673, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 673, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 674, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 674, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 674, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 674, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 674, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 674, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 675, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 675, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 675, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 675, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 675, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 675, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 675, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 675, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 675, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 675, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 675, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 676, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 676, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 676, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 676, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 676, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 676, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 676, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 676, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 676, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 676, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 676, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 676, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 677, "R/W", 1, 1, 0, 0},
- {"MLW" , 4, 6, 677, "R/W", 0, 0, 4ull, 4ull},
- {"ASLPMS" , 10, 2, 677, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 677, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 677, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 677, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 677, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 677, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ASPM" , 22, 1, 677, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 677, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 677, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 678, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 678, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 678, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 678, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 678, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 678, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 678, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 678, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 678, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 678, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 678, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 678, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 678, "RO", 1, 1, 0, 0},
- {"NLW" , 20, 6, 678, "RO", 0, 0, 1ull, 4ull},
- {"RESERVED_26_26" , 26, 1, 678, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 678, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 678, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 678, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 678, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 678, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 679, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 679, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 679, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 680, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 680, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 680, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 680, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 680, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 681, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 681, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 681, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 681, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 681, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 681, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 681, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 681, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 682, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 682, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 682, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 682, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 683, "RO", 0, 0, 15ull, 15ull},
- {"CTDS" , 4, 1, 683, "RO", 0, 0, 1ull, 1ull},
- {"ARI_FW" , 5, 1, 683, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OPS" , 6, 1, 683, "RO", 0, 0, 0ull, 0ull},
- {"ATOM32S" , 7, 1, 683, "RO", 0, 0, 0ull, 0ull},
- {"ATOM64S" , 8, 1, 683, "RO", 0, 0, 0ull, 0ull},
- {"ATOM128S" , 9, 1, 683, "RO", 0, 0, 0ull, 0ull},
- {"NOROPRPR" , 10, 1, 683, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_11_11" , 11, 1, 683, "RAZ", 1, 1, 0, 0},
- {"TPH" , 12, 2, 683, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 683, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 684, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 684, "R/W", 0, 0, 0ull, 0ull},
- {"ARI" , 5, 1, 684, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP" , 6, 1, 684, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP_EB" , 7, 1, 684, "RO", 0, 0, 0ull, 0ull},
- {"ID0_RQ" , 8, 1, 684, "RO", 0, 0, 0ull, 0ull},
- {"ID0_CP" , 9, 1, 684, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 684, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 685, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 685, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 685, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 685, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 686, "R/W", 1, 1, 0, 0},
- {"EC" , 4, 1, 686, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 686, "R/W", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 686, "R/W", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 686, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 686, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 686, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 686, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 686, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 686, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 686, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 687, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 688, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 689, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 689, "RO", 0, 0, 2ull, 2ull},
- {"NCO" , 20, 12, 689, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 690, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 690, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 690, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 690, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 690, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 690, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 690, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 690, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 690, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 690, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 690, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 690, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 690, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 690, "RAZ", 1, 1, 0, 0},
- {"UATOMBS" , 24, 1, 690, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 690, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 691, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 691, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 691, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 691, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 691, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 691, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 691, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 691, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 691, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 691, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 691, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 691, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 691, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 691, "RAZ", 1, 1, 0, 0},
- {"UATOMBM" , 24, 1, 691, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 691, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 692, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 692, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 692, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 692, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 692, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 692, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 692, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 692, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 692, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 692, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 692, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 692, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 692, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 692, "RO", 0, 0, 2ull, 2ull},
- {"UATOMBS" , 24, 1, 692, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 692, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 693, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 693, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 693, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 693, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 693, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 693, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 693, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 693, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 693, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 694, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 694, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 694, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 694, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 695, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 695, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 695, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 695, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 696, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 697, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 698, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 699, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 700, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 700, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 700, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 700, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 701, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 701, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 701, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 701, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 701, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 701, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 701, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 701, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 701, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 702, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 702, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 703, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 703, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 704, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 705, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 705, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 705, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 705, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 705, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 705, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 706, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 706, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 706, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 706, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 706, "R/W", 0, 0, 3ull, 3ull},
- {"EASPML1" , 30, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 706, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 707, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 707, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 707, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 707, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 707, "R/W", 0, 0, 15ull, 7ull},
- {"RESERVED_22_31" , 22, 10, 707, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 708, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 708, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 708, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 708, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 708, "R/W", 0, 0, 0ull, 0ull},
- {"MFUNCN" , 0, 8, 709, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_13" , 8, 6, 709, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 709, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 709, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 709, "R/W", 0, 0, 0ull, 0ull},
- {"CX_NFUNC" , 29, 3, 709, "R/W", 0, 0, 0ull, 0ull},
- {"SKPIV" , 0, 11, 710, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 710, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 710, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 711, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 711, "R/W", 0, 0, 0ull, 0ull},
- {"M_DABORT_4UCPL" , 2, 1, 711, "R/W", 0, 0, 0ull, 0ull},
- {"M_HANDLE_FLUSH" , 3, 1, 711, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 711, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 712, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 713, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 714, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 714, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 714, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 715, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 715, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 715, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 716, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 716, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 716, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 717, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 717, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 717, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 717, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 718, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 718, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 718, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 718, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 719, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 719, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 719, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 719, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 720, "R/W", 0, 0, 56ull, 56ull},
- {"HEADER_CREDITS" , 12, 8, 720, "R/W", 0, 0, 31ull, 31ull},
- {"RESERVED_20_20" , 20, 1, 720, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 720, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 720, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 720, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 720, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 721, "R/W", 0, 0, 13ull, 13ull},
- {"HEADER_CREDITS" , 12, 8, 721, "R/W", 0, 0, 31ull, 31ull},
- {"RESERVED_20_20" , 20, 1, 721, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 721, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 721, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 722, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 722, "R/W", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 722, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 722, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 722, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 723, "R/W", 0, 0, 183ull, 183ull},
- {"RESERVED_14_15" , 14, 2, 723, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 723, "R/W", 0, 0, 37ull, 37ull},
- {"RESERVED_26_31" , 26, 6, 723, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 724, "R/W", 0, 0, 97ull, 97ull},
- {"RESERVED_14_15" , 14, 2, 724, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 724, "R/W", 0, 0, 37ull, 37ull},
- {"RESERVED_26_31" , 26, 6, 724, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 725, "R/W", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 725, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 725, "R/W", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 725, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 726, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 726, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 726, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 726, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 726, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 726, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 726, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 727, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 728, "R/W", 0, 0, 0ull, 0ull},
- {"THRESH" , 0, 4, 729, "R/W", 0, 0, 0ull, 8ull},
- {"FETCHSIZ" , 4, 4, 729, "R/W", 0, 0, 0ull, 7ull},
- {"TXRD" , 8, 10, 729, "R/W", 0, 0, 0ull, 1ull},
- {"USELDT" , 18, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 729, "RAZ", 1, 1, 0, 0},
- {"RXST" , 20, 10, 729, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_30_31" , 30, 2, 729, "RAZ", 1, 1, 0, 0},
- {"TXSLOTS" , 32, 10, 729, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_42_43" , 42, 2, 729, "RAZ", 1, 1, 0, 0},
- {"RXSLOTS" , 44, 10, 729, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_62" , 54, 9, 729, "RAZ", 1, 1, 0, 0},
- {"RDPEND" , 63, 1, 729, "RO", 0, 0, 0ull, 0ull},
- {"FSYNCMISSED" , 0, 1, 730, "R/W", 0, 0, 0ull, 1ull},
- {"FSYNCEXTRA" , 1, 1, 730, "R/W", 0, 0, 0ull, 1ull},
- {"RXWRAP" , 2, 1, 730, "R/W", 0, 0, 0ull, 1ull},
- {"RXST" , 3, 1, 730, "R/W", 0, 0, 0ull, 1ull},
- {"TXWRAP" , 4, 1, 730, "R/W", 0, 0, 0ull, 1ull},
- {"TXRD" , 5, 1, 730, "R/W", 0, 0, 0ull, 1ull},
- {"TXEMPTY" , 6, 1, 730, "R/W", 0, 0, 0ull, 1ull},
- {"RXOVF" , 7, 1, 730, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 730, "RAZ", 1, 1, 0, 0},
- {"FSYNCMISSED" , 0, 1, 731, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYNCEXTRA" , 1, 1, 731, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXWRAP" , 2, 1, 731, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXST" , 3, 1, 731, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXWRAP" , 4, 1, 731, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXRD" , 5, 1, 731, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXEMPTY" , 6, 1, 731, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXOVF" , 7, 1, 731, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 731, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 732, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 732, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 733, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 733, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 734, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 735, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 736, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 737, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 738, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 739, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 740, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 741, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 742, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 742, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 742, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 743, "R/W", 0, 0, 0ull, 0ull},
- {"USECLK1" , 1, 1, 743, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 2, 1, 743, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 743, "RAZ", 1, 1, 0, 0},
- {"SAMPPT" , 32, 16, 743, "R/W", 0, 1, 0ull, 0},
- {"DRVTIM" , 48, 16, 743, "R/W", 0, 1, 0ull, 0},
- {"DEBUGINFO" , 0, 64, 744, "RO", 1, 1, 0, 0},
- {"FRAM" , 0, 3, 745, "R/W", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 745, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 745, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 746, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 746, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 747, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 748, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 749, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 750, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 751, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 752, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 753, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 754, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 755, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 755, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 755, "RAZ", 1, 1, 0, 0},
- {"ENA" , 0, 1, 756, "R/W", 0, 0, 0ull, 0ull},
- {"FSYNCPOL" , 1, 1, 756, "R/W", 0, 0, 0ull, 0ull},
- {"BCLKPOL" , 2, 1, 756, "R/W", 0, 0, 0ull, 0ull},
- {"BITLEN" , 3, 2, 756, "R/W", 0, 0, 0ull, 0ull},
- {"EXTRABIT" , 5, 1, 756, "R/W", 0, 0, 0ull, 0ull},
- {"NUMSLOTS" , 6, 10, 756, "R/W", 0, 1, 0ull, 0},
- {"FSYNCLOC" , 16, 5, 756, "R/W", 0, 0, 0ull, 0ull},
- {"FSYNCLEN" , 21, 5, 756, "R/W", 0, 0, 0ull, 2ull},
- {"RESERVED_26_31" , 26, 6, 756, "RAZ", 1, 1, 0, 0},
- {"FSYNCSAMP" , 32, 16, 756, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_62" , 48, 15, 756, "RAZ", 1, 1, 0, 0},
- {"FSYNCGOOD" , 63, 1, 756, "RO", 0, 0, 0ull, 1ull},
- {"DEBUGINFO" , 0, 64, 757, "RO", 1, 1, 0, 0},
- {"N" , 0, 32, 758, "R/W", 0, 1, 0ull, 0},
- {"NUMSAMP" , 32, 16, 758, "R/W", 0, 1, 0ull, 0},
- {"DELTASAMP" , 48, 16, 758, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 759, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 759, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 759, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 759, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 759, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 759, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 759, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 759, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 759, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 760, "RO", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 760, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 760, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 760, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 760, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 760, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 761, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 761, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 761, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 761, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 761, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 761, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 761, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 761, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 761, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 762, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 762, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 762, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 762, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 762, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 762, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 763, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 12, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 763, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 12, 1, 764, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 764, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 765, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 765, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 766, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 766, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 766, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 767, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 767, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 767, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 768, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 768, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 768, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 768, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 768, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 768, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 769, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 769, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 769, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 769, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 769, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 769, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 769, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 770, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 770, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 770, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 770, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 770, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 770, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 770, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 771, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 771, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 771, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 772, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 772, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 772, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 772, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 772, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 772, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 772, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 772, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 773, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 773, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 773, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 773, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 773, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 773, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 773, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 774, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 774, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 774, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 774, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 775, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 775, "RAZ", 1, 1, 0, 0},
- {"L0SYNC" , 0, 1, 776, "RO", 0, 0, 0ull, 1ull},
- {"L1SYNC" , 1, 1, 776, "RO", 0, 0, 0ull, 1ull},
- {"L2SYNC" , 2, 1, 776, "RO", 0, 0, 0ull, 1ull},
- {"L3SYNC" , 3, 1, 776, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_4_10" , 4, 7, 776, "RAZ", 1, 1, 0, 0},
- {"PATTST" , 11, 1, 776, "RO", 0, 0, 0ull, 0ull},
- {"ALIGND" , 12, 1, 776, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_63" , 13, 51, 776, "RAZ", 1, 1, 0, 0},
- {"BIST_STATUS" , 0, 1, 777, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 777, "RAZ", 1, 1, 0, 0},
- {"BITLCK0" , 0, 1, 778, "RO", 0, 1, 0ull, 0},
- {"BITLCK1" , 1, 1, 778, "RO", 0, 1, 0ull, 0},
- {"BITLCK2" , 2, 1, 778, "RO", 0, 1, 0ull, 0},
- {"BITLCK3" , 3, 1, 778, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 778, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 779, "RAZ", 1, 1, 0, 0},
- {"SPD" , 2, 4, 779, "RO", 0, 0, 0ull, 0ull},
- {"SPDSEL0" , 6, 1, 779, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_10" , 7, 4, 779, "RAZ", 1, 1, 0, 0},
- {"LO_PWR" , 11, 1, 779, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 779, "RAZ", 1, 1, 0, 0},
- {"SPDSEL1" , 13, 1, 779, "RO", 0, 0, 1ull, 1ull},
- {"LOOPBCK1" , 14, 1, 779, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 779, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 779, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 780, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 780, "RAZ", 1, 1, 0, 0},
- {"TXFLT_EN" , 0, 1, 781, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 1, 1, 781, "R/W", 0, 0, 0ull, 1ull},
- {"RXSYNBAD_EN" , 2, 1, 781, "R/W", 0, 0, 0ull, 1ull},
- {"BITLCKLS_EN" , 3, 1, 781, "R/W", 0, 0, 0ull, 1ull},
- {"SYNLOS_EN" , 4, 1, 781, "R/W", 0, 0, 0ull, 1ull},
- {"ALGNLOS_EN" , 5, 1, 781, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 6, 1, 781, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 781, "RAZ", 1, 1, 0, 0},
- {"TXFLT" , 0, 1, 782, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 1, 1, 782, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXSYNBAD" , 2, 1, 782, "R/W1C", 0, 0, 0ull, 0ull},
- {"BITLCKLS" , 3, 1, 782, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNLOS" , 4, 1, 782, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALGNLOS" , 5, 1, 782, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 6, 1, 782, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 782, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 783, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 783, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 783, "R/W1C", 0, 0, 0ull, 0ull},
- {"DROP_LN" , 4, 2, 783, "R/W", 0, 0, 0ull, 0ull},
- {"ENC_MODE" , 6, 1, 783, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 783, "RAZ", 1, 1, 0, 0},
- {"GMXENO" , 0, 1, 784, "R/W", 0, 0, 0ull, 0ull},
- {"XAUI" , 1, 1, 784, "RO", 1, 1, 0, 0},
- {"RX_SWAP" , 2, 1, 784, "R/W", 0, 1, 0ull, 0},
- {"TX_SWAP" , 3, 1, 784, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 784, "RAZ", 1, 1, 0, 0},
- {"SYNC0ST" , 0, 4, 785, "RO", 0, 1, 0ull, 0},
- {"SYNC1ST" , 4, 4, 785, "RO", 0, 1, 0ull, 0},
- {"SYNC2ST" , 8, 4, 785, "RO", 0, 1, 0ull, 0},
- {"SYNC3ST" , 12, 4, 785, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 785, "RAZ", 1, 1, 0, 0},
- {"TENGB" , 0, 1, 786, "RO", 0, 0, 1ull, 1ull},
- {"TENPASST" , 1, 1, 786, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 786, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 787, "RAZ", 1, 1, 0, 0},
- {"LPABLE" , 1, 1, 787, "RO", 0, 0, 1ull, 1ull},
- {"RCV_LNK" , 2, 1, 787, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_3_6" , 3, 4, 787, "RAZ", 1, 1, 0, 0},
- {"FLT" , 7, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 787, "RAZ", 1, 1, 0, 0},
- {"TENGB_R" , 0, 1, 788, "RO", 0, 0, 0ull, 0ull},
- {"TENGB_X" , 1, 1, 788, "RO", 0, 0, 1ull, 1ull},
- {"TENGB_W" , 2, 1, 788, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_9" , 3, 7, 788, "RAZ", 1, 1, 0, 0},
- {"RCVFLT" , 10, 1, 788, "RC", 0, 0, 0ull, 0ull},
- {"XMTFLT" , 11, 1, 788, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 788, "RAZ", 1, 1, 0, 0},
- {"DEV" , 14, 2, 788, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_16_63" , 16, 48, 788, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 789, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 789, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_TXPLRT" , 2, 4, 789, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_RXPLRT" , 6, 4, 789, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 789, "RAZ", 1, 1, 0, 0},
- {"TX_ST" , 0, 3, 790, "RO", 0, 1, 0ull, 0},
- {"RX_ST" , 3, 2, 790, "RO", 0, 1, 0ull, 0},
- {"ALGN_ST" , 5, 3, 790, "RO", 0, 1, 0ull, 0},
- {"RXBAD" , 8, 1, 790, "RO", 0, 0, 0ull, 0ull},
- {"SYN0BAD" , 9, 1, 790, "RO", 0, 0, 0ull, 0ull},
- {"SYN1BAD" , 10, 1, 790, "RO", 0, 0, 0ull, 0ull},
- {"SYN2BAD" , 11, 1, 790, "RO", 0, 0, 0ull, 0ull},
- {"SYN3BAD" , 12, 1, 790, "RO", 0, 0, 0ull, 0ull},
- {"TERM_ERR" , 13, 1, 790, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 790, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 791, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 791, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 791, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 16, 791, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 791, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 792, "RAZ", 1, 1, 0, 0},
- {"MASK" , 3, 35, 792, "R/W", 0, 0, 34359738367ull, 34359738367ull},
- {"RESERVED_38_63" , 38, 26, 792, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 793, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 793, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 793, "R/W", 0, 0, 0ull, 1ull},
- {"BAR1_SIZ" , 4, 3, 793, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_7_63" , 7, 57, 793, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 794, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 794, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 794, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 3, 1, 794, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 4, 1, 794, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 5, 1, 794, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 6, 1, 794, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 7, 1, 794, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 794, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 795, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 795, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 795, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 795, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 795, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 795, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 6, 1, 795, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 7, 1, 795, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 8, 1, 795, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 9, 1, 795, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 795, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 796, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 796, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 797, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 797, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 798, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 798, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 799, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 799, "R/W", 0, 0, 0ull, 0ull},
- {"FAST_LM" , 2, 1, 799, "R/W", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 799, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 799, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 799, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 799, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 799, "R/W", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 799, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 799, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 799, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 799, "RAZ", 0, 0, 0ull, 0ull},
- {"CFG_RTRY" , 16, 16, 799, "R/W", 0, 0, 0ull, 32ull},
- {"RESERVED_32_33" , 32, 2, 799, "RAZ", 1, 1, 0, 0},
- {"PBUS" , 34, 8, 799, "RO", 1, 1, 0, 0},
- {"DNUM" , 42, 5, 799, "RO", 1, 1, 0, 0},
- {"AUTO_SD" , 47, 1, 799, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 799, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 800, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 800, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 801, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 802, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 802, "RO", 1, 1, 0, 0},
- {"NUM" , 0, 6, 803, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 803, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 804, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 804, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 805, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 805, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 806, "RO", 0, 0, 0ull, 0ull},
- {"SE" , 1, 1, 806, "R/W1C", 0, 0, 0ull, 0ull},
- {"PMEI" , 2, 1, 806, "RO", 0, 0, 0ull, 0ull},
- {"PMEM" , 3, 1, 806, "RO", 0, 0, 0ull, 0ull},
- {"UP_B1" , 4, 1, 806, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_B2" , 5, 1, 806, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_BX" , 6, 1, 806, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B1" , 7, 1, 806, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B2" , 8, 1, 806, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_BX" , 9, 1, 806, "R/W1C", 0, 0, 0ull, 0ull},
- {"EXC" , 10, 1, 806, "RO", 0, 0, 0ull, 0ull},
- {"RDLK" , 11, 1, 806, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_ER" , 12, 1, 806, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_DR" , 13, 1, 806, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 806, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 807, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 807, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 808, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 808, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_40" , 0, 41, 809, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 41, 23, 809, "R/W", 0, 0, 0ull, 0ull},
- {"SLI_P" , 0, 8, 810, "R/W", 0, 0, 128ull, 128ull},
- {"SLI_NP" , 8, 8, 810, "R/W", 0, 0, 16ull, 16ull},
- {"SLI_CPL" , 16, 8, 810, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_24_47" , 24, 24, 810, "RAZ", 1, 1, 0, 0},
- {"PEAI_PPF" , 48, 8, 810, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_56_63" , 56, 8, 810, "RAZ", 1, 1, 0, 0},
- {"SKIP1" , 0, 7, 811, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 811, "RAZ", 1, 1, 0, 0},
- {"SKIP2" , 8, 7, 811, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 811, "RAZ", 1, 1, 0, 0},
- {"SKIP3" , 16, 7, 811, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_31" , 23, 9, 811, "RAZ", 1, 1, 0, 0},
- {"BIT0" , 32, 6, 811, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_39" , 38, 2, 811, "RAZ", 1, 1, 0, 0},
- {"BIT1" , 40, 6, 811, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_55" , 46, 10, 811, "RAZ", 1, 1, 0, 0},
- {"LEN" , 56, 1, 811, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_57_63" , 57, 7, 811, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 812, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 812, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 812, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 812, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 812, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 20, 813, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 813, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 814, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 814, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 16, 9, 814, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_25_31" , 25, 7, 814, "RAZ", 1, 1, 0, 0},
- {"TAG" , 32, 8, 814, "R/W", 0, 1, 0ull, 0},
- {"UPPER_TAG" , 40, 16, 814, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 814, "RAZ", 1, 1, 0, 0},
- {"POS0" , 0, 7, 815, "R/W", 0, 1, 0ull, 0},
- {"POS0_VAL" , 7, 1, 815, "R/W", 0, 1, 0ull, 0},
- {"POS1" , 8, 7, 815, "R/W", 0, 1, 0ull, 0},
- {"POS1_VAL" , 15, 1, 815, "R/W", 0, 1, 0ull, 0},
- {"POS2" , 16, 7, 815, "R/W", 0, 1, 0ull, 0},
- {"POS2_VAL" , 23, 1, 815, "R/W", 0, 1, 0ull, 0},
- {"POS3" , 24, 7, 815, "R/W", 0, 1, 0ull, 0},
- {"POS3_VAL" , 31, 1, 815, "R/W", 0, 1, 0ull, 0},
- {"POS4" , 32, 7, 815, "R/W", 0, 1, 0ull, 0},
- {"POS4_VAL" , 39, 1, 815, "R/W", 0, 1, 0ull, 0},
- {"POS5" , 40, 7, 815, "R/W", 0, 1, 0ull, 0},
- {"POS5_VAL" , 47, 1, 815, "R/W", 0, 1, 0ull, 0},
- {"POS6" , 48, 7, 815, "R/W", 0, 1, 0ull, 0},
- {"POS6_VAL" , 55, 1, 815, "R/W", 0, 1, 0ull, 0},
- {"POS7" , 56, 7, 815, "R/W", 0, 1, 0ull, 0},
- {"POS7_VAL" , 63, 1, 815, "R/W", 0, 1, 0ull, 0},
- {"QOS" , 0, 3, 816, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_7" , 3, 5, 816, "RAZ", 1, 1, 0, 0},
- {"TT" , 8, 2, 816, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 816, "RAZ", 1, 1, 0, 0},
- {"GRP" , 16, 4, 816, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 816, "RAZ", 1, 1, 0, 0},
- {"TAG" , 32, 8, 816, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_59" , 40, 20, 816, "RAZ", 1, 1, 0, 0},
- {"QOS_EN" , 60, 1, 816, "R/W", 0, 1, 0ull, 0},
- {"TT_EN" , 61, 1, 816, "R/W", 0, 1, 0ull, 0},
- {"GRP_EN" , 62, 1, 816, "R/W", 0, 1, 0ull, 0},
- {"TAG_EN" , 63, 1, 816, "R/W", 0, 1, 0ull, 0},
- {"CLKEN" , 0, 1, 817, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 817, "RAZ", 0, 1, 0ull, 0},
- {"DPRT" , 0, 16, 818, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 818, "RAZ", 1, 1, 0, 0},
- {"MAP0" , 0, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 819, "R/W", 0, 0, 0ull, 0ull},
- {"MAP0" , 0, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 820, "R/W", 0, 0, 0ull, 0ull},
- {"MINLEN" , 0, 16, 821, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 821, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 821, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 822, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 822, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 822, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 822, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 822, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 822, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 822, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 822, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 823, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 823, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 823, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 823, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 823, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 823, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 823, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 823, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 823, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 823, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 823, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 823, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 823, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 20, 1, 823, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_23" , 21, 3, 823, "RAZ", 1, 1, 0, 0},
- {"DSA_GRP_SID" , 24, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SCMD" , 25, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_TVID" , 26, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"IHMSK_DIS" , 27, 1, 823, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 823, "RAZ", 1, 1, 0, 0},
- {"PRI" , 0, 6, 824, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 824, "RAZ", 1, 1, 0, 0},
- {"QOS" , 8, 3, 824, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 824, "RAZ", 1, 1, 0, 0},
- {"UP_QOS" , 12, 1, 824, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_13_63" , 13, 51, 824, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 825, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 826, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 827, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 827, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 828, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 828, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 828, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_EN" , 10, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"HIGIG_EN" , 11, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"CRC_EN" , 12, 1, 828, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 828, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VSEL" , 19, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 828, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 828, "R/W", 0, 0, 0ull, 0ull},
- {"HG_QOS" , 27, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT" , 28, 4, 828, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 828, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 828, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 828, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 828, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 828, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 828, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 828, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_63" , 53, 11, 828, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 829, "RAZ", 1, 1, 0, 0},
- {"BSEL_EN" , 32, 1, 829, "R/W", 0, 0, 0ull, 0ull},
- {"BSEL_NUM" , 33, 2, 829, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_35_35" , 35, 1, 829, "RAZ", 1, 1, 0, 0},
- {"ALT_SKP_EN" , 36, 1, 829, "R/W", 0, 1, 0ull, 0},
- {"ALT_SKP_SEL" , 37, 2, 829, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_39_63" , 39, 25, 829, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 830, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 830, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 830, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 830, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 830, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 830, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 830, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 830, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 831, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 831, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 832, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 832, "RAZ", 1, 1, 0, 0},
- {"QOS1" , 4, 3, 832, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 832, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 833, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 833, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 833, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 833, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 833, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 833, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 833, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 833, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 833, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 834, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 834, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 835, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 836, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 836, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 837, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 837, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 838, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 838, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 839, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 839, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 840, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 840, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 841, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 841, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 842, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 842, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 843, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 843, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 844, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 844, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 845, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 845, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 846, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 846, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 847, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 847, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 848, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 848, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 849, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 849, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 850, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 850, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 851, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 851, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 852, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 852, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 853, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 853, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 854, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 854, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 854, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 855, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 855, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 855, "RO", 1, 1, 0, 0},
- {"TYPE0" , 0, 16, 856, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE1" , 16, 16, 856, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE2" , 32, 16, 856, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE3" , 48, 16, 856, "R/W", 0, 0, 33024ull, 33024ull},
- {"COUNT" , 0, 32, 857, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 857, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 858, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 858, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 859, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 859, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 859, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 859, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 860, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 860, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 860, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 860, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 860, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 861, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 861, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 861, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 861, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 862, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 862, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 862, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 862, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 862, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 862, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 862, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 862, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 863, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 863, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 863, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 863, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 864, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 864, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 864, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 864, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 864, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 865, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 866, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 866, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 866, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 866, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 866, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 867, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 868, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 868, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 868, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 868, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 868, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 868, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 868, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 868, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 868, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 868, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 868, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 868, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 868, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 869, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 869, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 869, "RO", 1, 0, 0, 0ull},
- {"MAJOR_3" , 54, 1, 869, "RO", 1, 0, 0, 0ull},
- {"PTP" , 55, 1, 869, "RO", 1, 0, 0, 0ull},
- {"RESERVED_56_63" , 56, 8, 869, "RAZ", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 870, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 870, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 870, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 870, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 870, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 870, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 870, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 870, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 870, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 870, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 870, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 870, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 870, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 871, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 871, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 871, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 871, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 871, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 871, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 872, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 872, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 872, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 872, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 6, 1, 872, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 872, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 872, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 872, "RO", 1, 0, 0, 0ull},
- {"QID_IDX" , 29, 4, 872, "RO", 1, 1, 0, 0},
- {"RESERVED_33_33" , 33, 1, 872, "RAZ", 1, 1, 0, 0},
- {"QID_QQOS" , 34, 8, 872, "RO", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 872, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 873, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 873, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 873, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 873, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 874, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 874, "R/W", 1, 0, 0, 0ull},
- {"BP_PORT" , 10, 6, 874, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_52" , 16, 37, 874, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 874, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 61, 1, 874, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_62_63" , 62, 2, 874, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 875, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 875, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_10_52" , 10, 43, 875, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 875, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 875, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 876, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 876, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 876, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 876, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 876, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 877, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 877, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 877, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 877, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 878, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 878, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 878, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 878, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 878, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 878, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 878, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 878, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 878, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 879, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 879, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 879, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 879, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 879, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 880, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 880, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 880, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 880, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 880, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 880, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 8, 880, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 880, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 880, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 880, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 880, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 3, 880, "RO", 1, 0, 0, 0ull},
- {"OUT_DAT" , 32, 1, 880, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 880, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 880, "RO", 1, 0, 0, 0ull},
- {"RESERVED_35_63" , 35, 29, 880, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 881, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 881, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 881, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 881, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 882, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 883, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 884, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 885, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE1" , 4, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE2" , 8, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE3" , 12, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE4" , 16, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE5" , 20, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE6" , 24, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE7" , 28, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE8" , 32, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE9" , 36, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE10" , 40, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE11" , 44, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE12" , 48, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE13" , 52, 4, 886, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_56_63" , 56, 8, 886, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 14, 887, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 887, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 888, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 889, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_6" , 4, 3, 889, "RAZ", 1, 1, 0, 0},
- {"DIS_PERF2" , 7, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_PERF3" , 8, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 889, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 890, "R/W", 0, 0, 0ull, 0ull},
- {"MODE1" , 3, 3, 890, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 890, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 891, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 891, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 891, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 891, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 16, 892, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 892, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 893, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 893, "RAZ", 1, 1, 0, 0},
- {"PREEMPTER" , 0, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"PREEMPTEE" , 1, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 894, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 895, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 895, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 895, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 896, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 896, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 896, "RAZ", 1, 1, 0, 0},
- {"WQE_WORD" , 0, 4, 897, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_4_63" , 4, 60, 897, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 1, 898, "RO", 0, 0, 0ull, 0ull},
- {"PEND" , 1, 1, 898, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 2, 1, 898, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 3, 1, 898, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 4, 4, 898, "RO", 0, 0, 0ull, 0ull},
- {"NBR" , 8, 3, 898, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 11, 1, 898, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 898, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 4, 898, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 898, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 899, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 899, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 900, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 900, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 900, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 900, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 900, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 900, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 900, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 900, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 900, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 901, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 901, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 902, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 902, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 903, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 903, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 904, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 904, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 905, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 905, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 906, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 906, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 10, 907, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 907, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 908, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_10_63" , 10, 54, 908, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 909, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 909, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 910, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 910, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 910, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 910, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 910, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 910, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 910, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 910, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 910, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 910, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 911, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 911, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 911, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 911, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 911, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 9, 912, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 912, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 9, 912, "R/W", 0, 1, 511ull, 0},
- {"RESERVED_21_23" , 21, 3, 912, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 10, 912, "RO", 0, 1, 503ull, 0},
- {"RESERVED_34_35" , 34, 2, 912, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 36, 10, 912, "RO", 0, 1, 0ull, 0},
- {"RESERVED_46_47" , 46, 2, 912, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 48, 10, 912, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 912, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 913, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 913, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 914, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 914, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 915, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 915, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 916, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 916, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 916, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 10, 917, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_11" , 10, 2, 917, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 12, 10, 917, "RO", 0, 1, 0ull, 0},
- {"RESERVED_22_23" , 22, 2, 917, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 24, 4, 917, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 917, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 918, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 918, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 918, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 918, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 918, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 9, 919, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 919, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 9, 919, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_23" , 21, 3, 919, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 919, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 919, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 919, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 920, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 920, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 921, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 922, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 923, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 924, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 924, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 924, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 924, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 924, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 925, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 925, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 925, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 925, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 925, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 926, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 926, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 926, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 926, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 927, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 927, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 927, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 927, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 927, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 927, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 927, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 927, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 927, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 927, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 928, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 929, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 929, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 929, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 930, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 930, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 930, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 930, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 930, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 930, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 930, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 931, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 931, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 932, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 933, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 934, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 935, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 935, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 935, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 935, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 935, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 935, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 935, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 935, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 935, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 935, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 935, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 935, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 935, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 935, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 935, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 935, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 935, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 935, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 936, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 936, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 936, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 937, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 937, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 938, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 938, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 938, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 939, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 939, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 939, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 939, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 939, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 939, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 939, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 940, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 940, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 941, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 941, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 942, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 942, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 943, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 943, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 943, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 944, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 944, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 944, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 945, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 945, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 945, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 945, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 945, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 945, "R/W", 0, 0, 0ull, 0ull},
- {"EER_VAL" , 9, 1, 945, "RO", 0, 0, 0ull, 0ull},
- {"EER_LCK" , 10, 1, 945, "RO", 0, 0, 0ull, 0ull},
- {"DIS_MAK" , 11, 1, 945, "R/W1", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 945, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 946, "RO", 1, 1, 0, 0},
- {"KEY" , 0, 64, 947, "WO", 0, 0, 0ull, 0ull},
- {"DAT" , 0, 64, 948, "RO", 1, 1, 0, 0},
- {"NCB_CMD" , 0, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_0" , 2, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_1" , 3, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_0" , 4, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_1" , 5, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 949, "RAZ", 1, 1, 0, 0},
- {"P2N1_P1" , 9, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_24" , 19, 6, 949, "RAZ", 1, 1, 0, 0},
- {"CPL_P1" , 25, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_28" , 27, 2, 949, "RAZ", 1, 1, 0, 0},
- {"N2P0_O" , 29, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 949, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 950, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_4" , 1, 4, 950, "R/W", 0, 0, 0ull, 0ull},
- {"PTLP_RO" , 5, 1, 950, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 950, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 950, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 950, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 950, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 950, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 950, "R/W", 0, 0, 3ull, 3ull},
- {"WAITL_COM" , 16, 1, 950, "R/W", 0, 1, 0ull, 0},
- {"DIS_PORT" , 17, 1, 950, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTA" , 18, 1, 950, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 19, 1, 950, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 20, 1, 950, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 21, 1, 950, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 950, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 951, "RO", 1, 1, 0, 0},
- {"P0_NTAGS" , 8, 6, 951, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_14_63" , 14, 50, 951, "R/W", 0, 0, 32ull, 32ull},
- {"P0_FCNT" , 0, 6, 952, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 952, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 952, "RAZ", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 952, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 952, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 953, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 953, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 953, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 32, 954, "R/W", 0, 1, 0ull, 0},
- {"ADBG_SEL" , 32, 1, 954, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 954, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 955, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 955, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 956, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 956, "R/W", 0, 1, 0ull, 0},
- {"TIM" , 0, 32, 957, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 957, "RAZ", 1, 1, 0, 0},
- {"RML_TO" , 0, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 958, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 958, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UP_B0" , 20, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UP_WI" , 21, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UN_B0" , 22, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UN_WI" , 23, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UP_B0" , 24, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UP_WI" , 25, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UN_B0" , 26, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UN_WI" , 27, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 958, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 958, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 958, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 958, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT2_ERR" , 58, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT3_ERR" , 59, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 959, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT1" , 17, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"MAC0_INT" , 18, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"MAC1_INT" , 19, 1, 959, "R/W", 0, 0, 0ull, 1ull},
- {"M2_UP_B0" , 20, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UP_WI" , 21, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UN_B0" , 22, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UN_WI" , 23, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UP_B0" , 24, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UP_WI" , 25, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UN_B0" , 26, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UN_WI" , 27, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 959, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 959, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 959, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 959, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 959, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT2_ERR" , 58, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT3_ERR" , 59, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 959, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT" , 4, 1, 960, "RO", 0, 0, 0ull, 0ull},
- {"PTIME" , 5, 1, 960, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_WI" , 9, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_B0" , 10, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_WI" , 11, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_B0" , 12, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_WI" , 13, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_B0" , 14, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_WI" , 15, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO_INT0" , 16, 1, 960, "RO", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 960, "RO", 0, 0, 0ull, 0ull},
- {"MAC0_INT" , 18, 1, 960, "RO", 0, 0, 0ull, 0ull},
- {"MAC1_INT" , 19, 1, 960, "RO", 0, 0, 0ull, 0ull},
- {"M2_UP_B0" , 20, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M2_UP_WI" , 21, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M2_UN_B0" , 22, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M2_UN_WI" , 23, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UP_B0" , 24, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UP_WI" , 25, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UN_B0" , 26, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UN_WI" , 27, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 960, "RAZ", 1, 1, 0, 0},
- {"DMAFI" , 32, 2, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 960, "RO", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 960, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 960, "RAZ", 1, 1, 0, 0},
- {"PIDBOF" , 48, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT2_ERR" , 58, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT3_ERR" , 59, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 960, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 960, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 961, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 962, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 963, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 964, "RO", 0, 1, 0ull, 0},
- {"P0_PCNT" , 0, 8, 965, "R/W", 0, 0, 128ull, 128ull},
- {"P0_NCNT" , 8, 8, 965, "R/W", 0, 0, 16ull, 16ull},
- {"P0_CCNT" , 16, 8, 965, "R/W", 0, 0, 128ull, 128ull},
- {"P1_PCNT" , 24, 8, 965, "R/W", 0, 0, 128ull, 128ull},
- {"P1_NCNT" , 32, 8, 965, "R/W", 0, 0, 16ull, 16ull},
- {"P1_CCNT" , 40, 8, 965, "R/W", 0, 0, 128ull, 128ull},
- {"P0_P_D" , 48, 1, 965, "R/W", 0, 0, 1ull, 1ull},
- {"P0_N_D" , 49, 1, 965, "R/W", 0, 0, 1ull, 1ull},
- {"P0_C_D" , 50, 1, 965, "R/W", 0, 0, 1ull, 1ull},
- {"P1_P_D" , 51, 1, 965, "R/W", 0, 0, 1ull, 1ull},
- {"P1_N_D" , 52, 1, 965, "R/W", 0, 0, 1ull, 1ull},
- {"P1_C_D" , 53, 1, 965, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_54_63" , 54, 10, 965, "RAZ", 1, 1, 0, 0},
- {"P2_PCNT" , 0, 8, 966, "R/W", 0, 0, 128ull, 128ull},
- {"P2_NCNT" , 8, 8, 966, "R/W", 0, 0, 16ull, 16ull},
- {"P2_CCNT" , 16, 8, 966, "R/W", 0, 0, 128ull, 128ull},
- {"P3_PCNT" , 24, 8, 966, "R/W", 0, 0, 128ull, 128ull},
- {"P3_NCNT" , 32, 8, 966, "R/W", 0, 0, 16ull, 16ull},
- {"P3_CCNT" , 40, 8, 966, "R/W", 0, 0, 128ull, 128ull},
- {"P2_P_D" , 48, 1, 966, "R/W", 0, 0, 1ull, 1ull},
- {"P2_N_D" , 49, 1, 966, "R/W", 0, 0, 1ull, 1ull},
- {"P2_C_D" , 50, 1, 966, "R/W", 0, 0, 1ull, 1ull},
- {"P3_P_D" , 51, 1, 966, "R/W", 0, 0, 1ull, 1ull},
- {"P3_N_D" , 52, 1, 966, "R/W", 0, 0, 1ull, 1ull},
- {"P3_C_D" , 53, 1, 966, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_54_63" , 54, 10, 966, "RAZ", 1, 1, 0, 0},
- {"NUM" , 0, 8, 967, "RO", 1, 1, 0, 0},
- {"A_MODE" , 8, 1, 967, "RO", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 967, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 968, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 968, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 968, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 30, 969, "R/W", 0, 1, 0ull, 0},
- {"RTYPE" , 30, 2, 969, "R/W", 0, 1, 0ull, 0},
- {"WTYPE" , 32, 2, 969, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 969, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 969, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 969, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 3, 969, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 42, 1, 969, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 969, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 970, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 971, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 972, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 973, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 974, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 975, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 976, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 977, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 978, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 978, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 978, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 64, 979, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 980, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 981, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 982, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 983, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 984, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 985, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 986, "R/W", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 987, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 987, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 987, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 988, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 988, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 989, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 989, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 989, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 990, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 990, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 990, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 991, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 991, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 991, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 992, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 32, 22, 992, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 992, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 32, 993, "R/W", 0, 0, 0ull, 0ull},
- {"WMARK" , 32, 32, 993, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_0_2" , 0, 3, 994, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 994, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 995, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 995, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 996, "R/W", 0, 1, 0ull, 0},
- {"FCNT" , 32, 5, 996, "RO", 0, 1, 0ull, 0},
- {"WRP" , 37, 9, 996, "RO", 0, 1, 0ull, 0},
- {"RRP" , 46, 9, 996, "RO", 0, 1, 0ull, 0},
- {"MAX" , 55, 9, 996, "RO", 0, 1, 16ull, 0},
- {"NTAG" , 0, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"NTT" , 1, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"NGRP" , 2, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"NQOS" , 3, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_5" , 4, 2, 997, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 997, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_13" , 13, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 997, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_20" , 16, 5, 997, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"RNTAG" , 22, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"RNTT" , 23, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"RNGRP" , 24, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"RNQOS" , 25, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_27" , 26, 2, 997, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 997, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_35" , 35, 1, 997, "RAZ", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 997, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_42" , 38, 5, 997, "RAZ", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 997, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 997, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 998, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 16, 7, 998, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 998, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 999, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 4, 60, 999, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 1000, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 1001, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1001, "RO", 0, 1, 0ull, 0},
- {"PORT" , 0, 32, 1002, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1002, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1003, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1003, "RAZ", 1, 1, 0, 0},
- {"PKT_BP" , 0, 4, 1004, "R/W", 0, 0, 15ull, 15ull},
- {"RING_EN" , 4, 1, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1004, "RAZ", 1, 1, 0, 0},
- {"ES" , 0, 64, 1005, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 1006, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1006, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 1007, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1007, "RAZ", 1, 1, 0, 0},
- {"DPTR" , 0, 32, 1008, "R/W", 0, 0, 0ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 1008, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 32, 1009, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1009, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1010, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1010, "RO", 0, 1, 0ull, 0},
- {"RD_CNT" , 0, 32, 1011, "RO", 0, 1, 0ull, 0},
- {"WR_CNT" , 32, 32, 1011, "RO", 0, 1, 0ull, 0},
- {"PP" , 0, 64, 1012, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 0, 1, 1013, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 1013, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 1013, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 1013, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 1013, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 1013, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 1013, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 1013, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 22, 1, 1013, "R/W", 0, 0, 0ull, 1ull},
- {"PIN_RST" , 23, 1, 1013, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_39" , 24, 16, 1013, "RAZ", 1, 1, 0, 0},
- {"PRC_IDLE" , 40, 1, 1013, "RO", 0, 1, 0ull, 0},
- {"RESERVED_41_47" , 41, 7, 1013, "RAZ", 1, 1, 0, 0},
- {"GII_RDS" , 48, 7, 1013, "RO", 0, 1, 0ull, 0},
- {"GII_ERST" , 55, 1, 1013, "RO", 0, 1, 0ull, 0},
- {"PRD_RDS" , 56, 7, 1013, "RO", 0, 1, 0ull, 0},
- {"PRD_ERST" , 63, 1, 1013, "RO", 0, 1, 0ull, 0},
- {"ENB" , 0, 32, 1014, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1014, "RAZ", 1, 1, 0, 0},
- {"RDSIZE" , 0, 64, 1015, "R/W", 0, 1, 0ull, 0},
- {"IS_64B" , 0, 32, 1016, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1016, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1017, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 22, 1017, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_63" , 54, 10, 1017, "RAZ", 1, 1, 0, 0},
- {"IPTR" , 0, 32, 1018, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1018, "RAZ", 1, 1, 0, 0},
- {"BMODE" , 0, 32, 1019, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1019, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 1020, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1020, "RAZ", 1, 1, 0, 0},
- {"WMARK" , 0, 32, 1021, "R/W", 0, 0, 0ull, 14ull},
- {"RESERVED_32_63" , 32, 32, 1021, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 64, 1022, "R/W", 0, 1, 0ull, 0},
- {"OUT_RST" , 0, 32, 1023, "RO", 0, 1, 0ull, 0},
- {"IN_RST" , 32, 32, 1023, "RO", 0, 1, 0ull, 0},
- {"ES" , 0, 64, 1024, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 1025, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1025, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 1026, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1026, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1027, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1027, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1028, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1028, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 3, 1029, "R/W", 0, 0, 2ull, 2ull},
- {"BAR0_D" , 3, 1, 1029, "R/W", 1, 1, 0, 0},
- {"WIND_D" , 4, 1, 1029, "R/W", 1, 1, 0, 0},
- {"RESERVED_5_63" , 5, 59, 1029, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 1030, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 1031, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 1032, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 1032, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 1032, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 1032, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 1033, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 1033, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 1033, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 1033, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 1033, "RO", 0, 1, 1ull, 0},
- {"RESERVED_47_47" , 47, 1, 1033, "RAZ", 1, 1, 0, 0},
- {"NNP1" , 48, 8, 1033, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 1033, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 1034, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 1034, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 1034, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 1034, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 1034, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 1035, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 1035, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_51_63" , 51, 13, 1035, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 1036, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 1037, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 1037, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 1037, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 1037, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 1038, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 1039, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1039, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 1040, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 1040, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 1041, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 1041, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 1041, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 1041, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 1041, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 1041, "R/W", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 1041, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 1041, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 1041, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1041, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 1042, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1042, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 1042, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 1042, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 1042, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1042, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1043, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1043, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 1044, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 1044, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 1044, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1044, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 1045, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 1045, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 1045, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1045, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 1046, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_6_7" , 6, 2, 1046, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 6, 1046, "R/W", 0, 0, 19ull, 19ull},
- {"RESERVED_14_63" , 14, 50, 1046, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 1047, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 1047, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 1047, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 1047, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 1047, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 1047, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 1048, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 1048, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 1048, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 1049, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1049, "RO", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 1049, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 1049, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 1049, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 1050, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 1050, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 1050, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 1050, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 1051, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 1051, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 1051, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 1051, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 1051, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 1051, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 1052, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 1052, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 1052, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 1052, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1053, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1053, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 1054, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 1054, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 1054, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1054, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1055, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1056, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 1056, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1056, "RAZ", 1, 1, 0, 0},
- {"TDF" , 0, 1, 1057, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1057, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"CLKALWAYS" , 15, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"RDAT_MD" , 16, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1058, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 1059, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 1059, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 1059, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 1060, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 1060, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 1060, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1060, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 1060, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1061, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1061, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1062, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1062, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1063, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1064, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1064, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1064, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1064, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1064, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 4, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 1066, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 1066, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 1066, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 1066, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1066, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 1067, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 5, 1068, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1068, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1069, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1069, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1070, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1071, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1072, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1072, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1072, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1072, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1072, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 4, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1074, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1074, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1075, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1075, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1076, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1076, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1076, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1076, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1076, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1077, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1077, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1077, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1077, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1077, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 4, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 1079, "R/W", 0, 1, 0ull, 0},
- {"LPL" , 5, 27, 1079, "R/W", 0, 1, 0ull, 0},
- {"CF" , 0, 1, 1080, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_31" , 1, 31, 1080, "R/W", 0, 0, 0ull, 0ull},
- {"CTRLDSSEG" , 0, 32, 1081, "R/W", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1082, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_31" , 14, 18, 1082, "RO", 0, 0, 0ull, 0ull},
- {"CAPLENGTH" , 0, 8, 1083, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_15" , 8, 8, 1083, "RO", 0, 0, 0ull, 0ull},
- {"HCIVERSION" , 16, 16, 1083, "RO", 0, 0, 256ull, 256ull},
- {"AC64" , 0, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"PFLF" , 1, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"ASPC" , 2, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"IST" , 4, 4, 1084, "RO", 0, 0, 2ull, 2ull},
- {"EECP" , 8, 8, 1084, "RO", 0, 0, 160ull, 160ull},
- {"RESERVED_16_31" , 16, 16, 1084, "RO", 0, 0, 0ull, 0ull},
- {"N_PORTS" , 0, 4, 1085, "RO", 0, 0, 2ull, 2ull},
- {"PPC" , 4, 1, 1085, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 1085, "RO", 0, 0, 0ull, 0ull},
- {"PRR" , 7, 1, 1085, "RO", 0, 0, 0ull, 0ull},
- {"N_PCC" , 8, 4, 1085, "RO", 0, 0, 2ull, 2ull},
- {"N_CC" , 12, 4, 1085, "RO", 0, 0, 1ull, 1ull},
- {"P_INDICATOR" , 16, 1, 1085, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 1085, "RO", 0, 0, 0ull, 0ull},
- {"DPN" , 20, 4, 1085, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1085, "RO", 0, 0, 0ull, 0ull},
- {"EN" , 0, 1, 1086, "R/W", 0, 0, 0ull, 0ull},
- {"MFMC" , 1, 13, 1086, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 1086, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_0" , 0, 1, 1087, "R/W", 0, 0, 0ull, 0ull},
- {"TA_OFF" , 1, 8, 1087, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1087, "R/W", 0, 0, 0ull, 0ull},
- {"TXTX_TADAO" , 10, 3, 1087, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 1087, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_RW" , 0, 1, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_FW" , 1, 1, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"PESD" , 2, 1, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1088, "RAZ", 0, 0, 0ull, 0ull},
- {"NAKRF_DIS" , 4, 1, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"AUTO_DIS" , 5, 1, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_30" , 0, 31, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1090, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 1091, "R/W", 0, 1, 0ull, 0},
- {"BADDR" , 12, 20, 1091, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1092, "RO", 0, 0, 0ull, 0ull},
- {"CSC" , 1, 1, 1092, "R/W1C", 0, 0, 0ull, 0ull},
- {"PED" , 2, 1, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"PEDC" , 3, 1, 1092, "R/W1C", 0, 0, 0ull, 0ull},
- {"OCA" , 4, 1, 1092, "RO", 0, 0, 0ull, 0ull},
- {"OCC" , 5, 1, 1092, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPR" , 6, 1, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"SPD" , 7, 1, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"PRST" , 8, 1, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1092, "RO", 0, 0, 0ull, 0ull},
- {"LSTS" , 10, 2, 1092, "RO", 0, 1, 0ull, 0},
- {"PP" , 12, 1, 1092, "RO", 0, 0, 1ull, 1ull},
- {"PO" , 13, 1, 1092, "R/W", 0, 0, 1ull, 0ull},
- {"PIC" , 14, 2, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"PTC" , 16, 4, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"WKCNNT_E" , 20, 1, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"WKDSCNNT_E" , 21, 1, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"WKOC_E" , 22, 1, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 1092, "RO", 0, 0, 0ull, 0ull},
- {"RS" , 0, 1, 1093, "R/W", 0, 0, 0ull, 1ull},
- {"HCRESET" , 1, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"FLS" , 2, 2, 1093, "RO", 0, 0, 0ull, 0ull},
- {"PS_EN" , 4, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"AS_EN" , 5, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"IAA_DB" , 6, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"LHCR" , 7, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"ASPMC" , 8, 2, 1093, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1093, "RO", 0, 0, 0ull, 0ull},
- {"ASPM_EN" , 11, 1, 1093, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 1093, "RO", 0, 0, 0ull, 0ull},
- {"ITC" , 16, 8, 1093, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_24_31" , 24, 8, 1093, "RO", 0, 0, 0ull, 0ull},
- {"USBINT_EN" , 0, 1, 1094, "R/W", 0, 1, 0ull, 0},
- {"USBERRINT_EN" , 1, 1, 1094, "R/W", 0, 1, 0ull, 0},
- {"PCI_EN" , 2, 1, 1094, "R/W", 0, 1, 0ull, 0},
- {"FLRO_EN" , 3, 1, 1094, "R/W", 0, 1, 0ull, 0},
- {"HSERR_EN" , 4, 1, 1094, "R/W", 0, 1, 0ull, 0},
- {"IOAA_EN" , 5, 1, 1094, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 1094, "RO", 0, 0, 0ull, 0ull},
- {"USBINT" , 0, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBERRINT" , 1, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCD" , 2, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLRO" , 3, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSYSERR" , 4, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOAA" , 5, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 1095, "RO", 0, 0, 0ull, 0ull},
- {"HCHTD" , 12, 1, 1095, "RO", 0, 0, 1ull, 0ull},
- {"RECLM" , 13, 1, 1095, "RO", 0, 0, 0ull, 0ull},
- {"PSS" , 14, 1, 1095, "RO", 0, 0, 0ull, 0ull},
- {"ASS" , 15, 1, 1095, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1095, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"BCED" , 4, 28, 1096, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1097, "R/W", 0, 0, 0ull, 0ull},
- {"BHED" , 4, 28, 1097, "R/W", 0, 1, 0ull, 0},
- {"HCR" , 0, 1, 1098, "R/W", 0, 0, 0ull, 0ull},
- {"CLF" , 1, 1, 1098, "R/W", 0, 0, 0ull, 0ull},
- {"BLF" , 2, 1, 1098, "R/W", 0, 0, 0ull, 0ull},
- {"OCR" , 3, 1, 1098, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1098, "RO", 0, 0, 0ull, 0ull},
- {"SOC" , 16, 2, 1098, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 1098, "RO", 0, 0, 0ull, 0ull},
- {"CBSR" , 0, 2, 1099, "R/W", 0, 1, 0ull, 0},
- {"PLE" , 2, 1, 1099, "R/W", 0, 0, 0ull, 0ull},
- {"IE" , 3, 1, 1099, "R/W", 0, 0, 0ull, 0ull},
- {"CLE" , 4, 1, 1099, "R/W", 0, 0, 0ull, 0ull},
- {"BLE" , 5, 1, 1099, "R/W", 0, 0, 0ull, 0ull},
- {"HCFS" , 6, 2, 1099, "R/W", 0, 0, 0ull, 0ull},
- {"IR" , 8, 1, 1099, "R/W", 0, 0, 0ull, 0ull},
- {"RWC" , 9, 1, 1099, "R/W", 0, 0, 0ull, 0ull},
- {"RWE" , 10, 1, 1099, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 1099, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1100, "R/W", 0, 0, 0ull, 0ull},
- {"CCED" , 4, 28, 1100, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1101, "R/W", 0, 0, 0ull, 0ull},
- {"CHED" , 4, 28, 1101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1102, "RO", 0, 0, 0ull, 0ull},
- {"DH" , 4, 28, 1102, "RO", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1103, "R/W", 0, 1, 11999ull, 0},
- {"RESERVED_14_15" , 14, 2, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"FSMPS" , 16, 15, 1103, "R/W", 0, 1, 0ull, 0},
- {"FIT" , 31, 1, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"FN" , 0, 16, 1104, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 1104, "RO", 0, 0, 0ull, 0ull},
- {"FR" , 0, 14, 1105, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_30" , 14, 17, 1105, "RO", 0, 0, 0ull, 0ull},
- {"FRT" , 31, 1, 1105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1106, "R/W", 0, 0, 0ull, 0ull},
- {"HCCA" , 8, 24, 1106, "R/W", 0, 1, 0ull, 0},
- {"SO" , 0, 1, 1107, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1107, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1107, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1107, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1107, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1107, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1107, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1107, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1107, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1107, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1108, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1109, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1109, "R/W1C", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1109, "R/W1C", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1109, "R/W1C", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1109, "R/W1C", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1109, "R/W1C", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1109, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1109, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1109, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1109, "RO", 0, 0, 0ull, 0ull},
- {"LST" , 0, 12, 1110, "R/W", 0, 1, 1576ull, 0},
- {"RESERVED_12_31" , 12, 20, 1110, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1111, "RO", 0, 0, 0ull, 0ull},
- {"PCED" , 4, 28, 1111, "RO", 0, 1, 0ull, 0},
- {"PS" , 0, 14, 1112, "R/W", 0, 0, 0ull, 15975ull},
- {"RESERVED_14_31" , 14, 18, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"REV" , 0, 8, 1113, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_31" , 8, 24, 1113, "RO", 0, 0, 0ull, 0ull},
- {"NDP" , 0, 8, 1114, "RO", 0, 0, 2ull, 2ull},
- {"NPS" , 8, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"PSM" , 9, 1, 1114, "R/W", 0, 0, 1ull, 1ull},
- {"DT" , 10, 1, 1114, "RO", 0, 0, 0ull, 0ull},
- {"OCPM" , 11, 1, 1114, "R/W", 1, 1, 0, 0},
- {"NOCP" , 12, 1, 1114, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_23" , 13, 11, 1114, "RO", 0, 0, 0ull, 0ull},
- {"POTPGT" , 24, 8, 1114, "R/W", 0, 0, 1ull, 1ull},
- {"DR" , 0, 16, 1115, "R/W", 0, 0, 0ull, 0ull},
- {"PPCM" , 16, 16, 1115, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"PES" , 1, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"PSS" , 2, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"POCI" , 3, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"PRS" , 4, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"PPS" , 8, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"LSDA" , 9, 1, 1116, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_15" , 10, 6, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"CSC" , 16, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"PESC" , 17, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"PSSC" , 18, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"OCIC" , 19, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"PRSC" , 20, 1, 1116, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_31" , 21, 11, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"LPS" , 0, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"OCI" , 1, 1, 1117, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_14" , 2, 13, 1117, "RO", 0, 0, 0ull, 0ull},
- {"DRWE" , 15, 1, 1117, "R/W", 0, 1, 0ull, 0},
- {"LPSC" , 16, 1, 1117, "R/W", 0, 1, 0ull, 0},
- {"CCIC" , 17, 1, 1117, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_18_30" , 18, 13, 1117, "RO", 0, 0, 0ull, 0ull},
- {"CRWE" , 31, 1, 1117, "WO", 1, 1, 0, 0},
- {"RESERVED_0_30" , 0, 31, 1118, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1118, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1119, "RO", 0, 0, 0ull, 0ull},
- {"PPAF_BIS" , 0, 1, 1120, "RO", 0, 0, 0ull, 0ull},
- {"WRBM_BIS" , 1, 1, 1120, "RO", 0, 0, 0ull, 0ull},
- {"ORBM_BIS" , 2, 1, 1120, "RO", 0, 0, 0ull, 0ull},
- {"ERBM_BIS" , 3, 1, 1120, "RO", 0, 0, 0ull, 0ull},
- {"DESC_BIS" , 4, 1, 1120, "RO", 0, 0, 0ull, 0ull},
- {"DATA_BIS" , 5, 1, 1120, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1120, "RO", 1, 1, 0, 0},
- {"HRST" , 0, 1, 1121, "R/W", 0, 0, 0ull, 1ull},
- {"P_PRST" , 1, 1, 1121, "R/W", 0, 0, 0ull, 1ull},
- {"P_POR" , 2, 1, 1121, "R/W", 0, 0, 1ull, 0ull},
- {"P_COM_ON" , 3, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 1121, "R/W", 0, 1, 0ull, 0},
- {"P_REFCLK_DIV" , 5, 2, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"P_REFCLK_SEL" , 7, 2, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"H_DIV" , 9, 4, 1121, "R/W", 0, 0, 6ull, 6ull},
- {"O_CLKDIV_EN" , 13, 1, 1121, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_EN" , 14, 1, 1121, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_RST" , 15, 1, 1121, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_BYP" , 16, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"O_CLKDIV_RST" , 17, 1, 1121, "R/W", 0, 0, 0ull, 1ull},
- {"APP_START_CLK" , 18, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_SUSP_LGCY" , 19, 1, 1121, "R/W", 0, 0, 1ull, 1ull},
- {"OHCI_SM" , 20, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_CLKCKTRST" , 21, 1, 1121, "R/W", 0, 0, 1ull, 1ull},
- {"EHCI_SM" , 22, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 23, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 24, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1121, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1122, "R/W", 0, 1, 0ull, 0},
- {"EHCI_64B_ADDR_EN" , 8, 1, 1122, "R/W", 0, 0, 1ull, 1ull},
- {"INV_REG_A2" , 9, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1122, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1122, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"DESC_RBM" , 19, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1122, "RAZ", 1, 1, 0, 0},
- {"FLA" , 0, 6, 1123, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 1123, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 1124, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 5, 27, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1124, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1125, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1125, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1126, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1127, "R/W1C", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1127, "R/W1C", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1127, "R/W1C", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1127, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1127, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1127, "R/W1C", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1127, "R/W1C", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1127, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1127, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1128, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_8" , 8, 1, 1128, "RAZ", 1, 1, 0, 0},
- {"INV_REG_A2" , 9, 1, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1128, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1128, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1128, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1129, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 8, 24, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1129, "RAZ", 1, 1, 0, 0},
- {"WM" , 0, 5, 1130, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_5_63" , 5, 59, 1130, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_EN" , 1, 1, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"UPHY_BIST" , 2, 1, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_EN" , 3, 1, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"SIDDQ" , 4, 1, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 5, 1, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 6, 1, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"HSBIST" , 7, 1, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ERR" , 8, 1, 1131, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 9, 1, 1131, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1131, "RAZ", 1, 1, 0, 0},
- {"TDATA_IN" , 0, 8, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 8, 4, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 12, 1, 1132, "R/W", 0, 0, 1ull, 0ull},
- {"TCLK" , 13, 1, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_EN" , 14, 1, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"COMPDISTUNE" , 15, 3, 1132, "R/W", 0, 0, 4ull, 4ull},
- {"SQRXTUNE" , 18, 3, 1132, "R/W", 0, 0, 4ull, 4ull},
- {"TXFSLSTUNE" , 21, 4, 1132, "R/W", 0, 0, 3ull, 3ull},
- {"TXPREEMPHASISTUNE" , 25, 1, 1132, "R/W", 0, 0, 0ull, 1ull},
- {"TXRISETUNE" , 26, 1, 1132, "R/W", 0, 0, 0ull, 1ull},
- {"TXVREFTUNE" , 27, 4, 1132, "R/W", 0, 0, 5ull, 15ull},
- {"TXHSVXTUNE" , 31, 2, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 33, 1, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"VBUSVLDEXT" , 34, 1, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"DPPULLDOWN" , 35, 1, 1132, "R/W", 0, 0, 1ull, 1ull},
- {"DMPULLDOWN" , 36, 1, 1132, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFEN" , 37, 1, 1132, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFENH" , 38, 1, 1132, "R/W", 0, 0, 1ull, 1ull},
- {"TDATA_OUT" , 39, 4, 1132, "RO", 1, 1, 0, 0},
- {"RESERVED_43_63" , 43, 21, 1132, "RAZ", 1, 1, 0, 0},
- {"ZIP_CTL" , 0, 4, 1133, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 53, 1133, "RO", 1, 0, 0, 0ull},
- {"RESERVED_57_63" , 57, 7, 1133, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 1134, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 1135, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 1135, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1135, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 1136, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 1136, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 1136, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 1136, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 1136, "RO", 0, 0, 31744ull, 31744ull},
- {"SYNCFLUSH_CAPABLE" , 48, 1, 1136, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_49_55" , 49, 7, 1136, "RAZ", 1, 1, 0, 0},
- {"NEXEC" , 56, 8, 1136, "RO", 0, 0, 1ull, 1ull},
- {"ASSERTS" , 0, 17, 1137, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1137, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1138, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1138, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1139, "RAZ", 1, 1, 0, 0},
- {"MAX_INFL" , 0, 4, 1140, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 1140, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn63xxp1[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 14, 0},
- {"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 14},
- {"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 13, 16},
- {"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 1, 29},
- {"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 30},
- {"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 31},
- {"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 32},
- {"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 1, 33},
- {"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 1, 34},
- {"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 35},
- {"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 4, 37},
- {"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 41},
- {"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 11, 43},
- {"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 14, 54},
- {"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 68},
- {"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 70},
- {"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 72},
- {"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 21, 74},
- {"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 21, 95},
- {"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 2, 116},
- {"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 38, 2, 118},
- {"cvmx_agl_gmx_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 4, 120},
- {"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 124},
- {"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 126},
- {"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 128},
- {"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 130},
- {"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 132},
- {"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 134},
- {"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 136},
- {"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 138},
- {"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 140},
- {"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 142},
- {"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 4, 144},
- {"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 2, 148},
- {"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 150},
- {"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 2, 152},
- {"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 70, 4, 154},
- {"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 4, 158},
- {"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 2, 162},
- {"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 3, 164},
- {"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 5, 167},
- {"cvmx_agl_gmx_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 2, 172},
- {"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 3, 174},
- {"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 81, 2, 177},
- {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 179},
- {"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 85, 2, 181},
- {"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 87, 2, 183},
- {"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 89, 2, 185},
- {"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 187},
- {"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 93, 2, 189},
- {"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 95, 2, 191},
- {"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 97, 2, 193},
- {"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 2, 195},
- {"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 197},
- {"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 2, 199},
- {"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 2, 201},
- {"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 2, 203},
- {"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 109, 2, 205},
- {"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 111, 2, 207},
- {"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 2, 209},
- {"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 115, 2, 211},
- {"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 117, 2, 213},
- {"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 118, 2, 215},
- {"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 3, 217},
- {"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 120, 12, 220},
- {"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 121, 12, 232},
- {"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 2, 244},
- {"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 123, 2, 246},
- {"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 124, 6, 248},
- {"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 125, 2, 254},
- {"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 126, 2, 256},
- {"cvmx_agl_prt#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 127, 23, 258},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 129, 2, 281},
- {"cvmx_ciu_block_int" , CVMX_CSR_DB_TYPE_NCB, 64, 130, 37, 283},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 131, 2, 320},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 132, 2, 322},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 133, 2, 324},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 134, 22, 326},
- {"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 148, 22, 348},
- {"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 162, 22, 370},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 176, 33, 392},
- {"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 190, 33, 425},
- {"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 204, 33, 458},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 218, 22, 491},
- {"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 22, 513},
- {"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 230, 22, 535},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 236, 33, 557},
- {"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 242, 33, 590},
- {"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 248, 33, 623},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 254, 22, 656},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 267, 22, 678},
- {"cvmx_ciu_int33_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 273, 22, 700},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 274, 33, 722},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 275, 2, 755},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 281, 2, 757},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 287, 2, 759},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 288, 2, 761},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 289, 2, 763},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 290, 1, 765},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 296, 3, 766},
- {"cvmx_ciu_qlm0" , CVMX_CSR_DB_TYPE_NCB, 64, 297, 8, 769},
- {"cvmx_ciu_qlm1" , CVMX_CSR_DB_TYPE_NCB, 64, 298, 8, 777},
- {"cvmx_ciu_qlm2" , CVMX_CSR_DB_TYPE_NCB, 64, 299, 8, 785},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 300, 6, 793},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 301, 8, 799},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 302, 2, 807},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 303, 2, 809},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 304, 2, 811},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 305, 2, 813},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 306, 3, 815},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 310, 7, 818},
- {"cvmx_dfa_bist0" , CVMX_CSR_DB_TYPE_RSL, 64, 316, 12, 825},
- {"cvmx_dfa_bist1" , CVMX_CSR_DB_TYPE_RSL, 64, 317, 12, 837},
- {"cvmx_dfa_config" , CVMX_CSR_DB_TYPE_RSL, 64, 318, 4, 849},
- {"cvmx_dfa_control" , CVMX_CSR_DB_TYPE_RSL, 64, 319, 7, 853},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 320, 2, 860},
- {"cvmx_dfa_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 321, 1, 862},
- {"cvmx_dfa_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 322, 1, 863},
- {"cvmx_dfa_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 323, 1, 864},
- {"cvmx_dfa_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 324, 1, 865},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 325, 4, 866},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 326, 3, 870},
- {"cvmx_dfa_dtcfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 327, 6, 873},
- {"cvmx_dfa_error" , CVMX_CSR_DB_TYPE_RSL, 64, 328, 5, 879},
- {"cvmx_dfa_intmsk" , CVMX_CSR_DB_TYPE_RSL, 64, 329, 3, 884},
- {"cvmx_dfa_memhidat" , CVMX_CSR_DB_TYPE_NCB, 64, 330, 1, 887},
- {"cvmx_dfa_pfc0_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 331, 1, 888},
- {"cvmx_dfa_pfc0_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 332, 5, 889},
- {"cvmx_dfa_pfc1_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 333, 1, 894},
- {"cvmx_dfa_pfc1_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 334, 5, 895},
- {"cvmx_dfa_pfc2_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 335, 1, 900},
- {"cvmx_dfa_pfc2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 336, 5, 901},
- {"cvmx_dfa_pfc3_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 337, 1, 906},
- {"cvmx_dfa_pfc3_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 338, 5, 907},
- {"cvmx_dfa_pfc_gctl" , CVMX_CSR_DB_TYPE_RSL, 64, 339, 18, 912},
- {"cvmx_dfm_char_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 340, 5, 930},
- {"cvmx_dfm_char_mask0" , CVMX_CSR_DB_TYPE_RSL, 64, 341, 2, 935},
- {"cvmx_dfm_char_mask2" , CVMX_CSR_DB_TYPE_RSL, 64, 342, 2, 937},
- {"cvmx_dfm_comp_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 343, 11, 939},
- {"cvmx_dfm_config" , CVMX_CSR_DB_TYPE_RSL, 64, 344, 17, 950},
- {"cvmx_dfm_control" , CVMX_CSR_DB_TYPE_RSL, 64, 345, 18, 967},
- {"cvmx_dfm_dll_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 346, 6, 985},
- {"cvmx_dfm_dll_ctl3" , CVMX_CSR_DB_TYPE_RSL, 64, 347, 11, 991},
- {"cvmx_dfm_fclk_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 348, 1, 1002},
- {"cvmx_dfm_fnt_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 349, 5, 1003},
- {"cvmx_dfm_fnt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 350, 5, 1008},
- {"cvmx_dfm_fnt_iena" , CVMX_CSR_DB_TYPE_RSL, 64, 351, 3, 1013},
- {"cvmx_dfm_fnt_sclk" , CVMX_CSR_DB_TYPE_RSL, 64, 352, 4, 1016},
- {"cvmx_dfm_fnt_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 353, 6, 1020},
- {"cvmx_dfm_ifb_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 354, 1, 1026},
- {"cvmx_dfm_modereg_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 355, 16, 1027},
- {"cvmx_dfm_modereg_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 356, 25, 1043},
- {"cvmx_dfm_ops_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 357, 1, 1068},
- {"cvmx_dfm_phy_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 358, 9, 1069},
- {"cvmx_dfm_reset_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 359, 5, 1078},
- {"cvmx_dfm_rlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 360, 4, 1083},
- {"cvmx_dfm_rlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 361, 1, 1087},
- {"cvmx_dfm_rlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 362, 5, 1088},
- {"cvmx_dfm_rodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 364, 8, 1093},
- {"cvmx_dfm_slot_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 365, 5, 1101},
- {"cvmx_dfm_slot_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 366, 5, 1106},
- {"cvmx_dfm_timing_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 367, 11, 1111},
- {"cvmx_dfm_timing_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 368, 12, 1122},
- {"cvmx_dfm_wlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 369, 3, 1134},
- {"cvmx_dfm_wlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 370, 3, 1137},
- {"cvmx_dfm_wlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 371, 5, 1140},
- {"cvmx_dfm_wodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 373, 8, 1145},
- {"cvmx_dpi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 374, 2, 1153},
- {"cvmx_dpi_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 375, 3, 1155},
- {"cvmx_dpi_dma#_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 376, 3, 1158},
- {"cvmx_dpi_dma#_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 384, 2, 1161},
- {"cvmx_dpi_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 392, 7, 1163},
- {"cvmx_dpi_dma#_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 400, 2, 1170},
- {"cvmx_dpi_dma#_reqbnk0" , CVMX_CSR_DB_TYPE_NCB, 64, 408, 1, 1172},
- {"cvmx_dpi_dma#_reqbnk1" , CVMX_CSR_DB_TYPE_NCB, 64, 416, 1, 1173},
- {"cvmx_dpi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 424, 17, 1174},
- {"cvmx_dpi_dma_eng#_en" , CVMX_CSR_DB_TYPE_NCB, 64, 425, 2, 1191},
- {"cvmx_dpi_eng#_buf" , CVMX_CSR_DB_TYPE_NCB, 64, 431, 3, 1193},
- {"cvmx_dpi_info_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 437, 3, 1196},
- {"cvmx_dpi_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 438, 15, 1199},
- {"cvmx_dpi_int_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 439, 15, 1214},
- {"cvmx_dpi_pint_info" , CVMX_CSR_DB_TYPE_NCB, 64, 440, 4, 1229},
- {"cvmx_dpi_pkt_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 441, 2, 1233},
- {"cvmx_dpi_req_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 442, 2, 1235},
- {"cvmx_dpi_req_err_rsp_en" , CVMX_CSR_DB_TYPE_NCB, 64, 443, 2, 1237},
- {"cvmx_dpi_req_err_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 444, 2, 1239},
- {"cvmx_dpi_req_err_rst_en" , CVMX_CSR_DB_TYPE_NCB, 64, 445, 2, 1241},
- {"cvmx_dpi_req_gbl_en" , CVMX_CSR_DB_TYPE_NCB, 64, 446, 2, 1243},
- {"cvmx_dpi_sli_prt#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 447, 14, 1245},
- {"cvmx_dpi_sli_prt#_err" , CVMX_CSR_DB_TYPE_NCB, 64, 449, 2, 1259},
- {"cvmx_dpi_sli_prt#_err_info" , CVMX_CSR_DB_TYPE_NCB, 64, 451, 6, 1261},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 453, 6, 1267},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 454, 7, 1273},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 455, 3, 1280},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 462, 2, 1283},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 469, 3, 1285},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 2, 1288},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 29, 1290},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 29, 1319},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 473, 2, 1348},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 481, 2, 1350},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 489, 3, 1352},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 490, 3, 1355},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 7, 1358},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 492, 2, 1365},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 493, 2, 1367},
- {"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 494, 5, 1369},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 495, 7, 1374},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 496, 2, 1381},
- {"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 497, 8, 1383},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 498, 10, 1391},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 502, 1, 1401},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 506, 1, 1402},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 510, 1, 1403},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 514, 1, 1404},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 518, 1, 1405},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 522, 1, 1406},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 526, 2, 1407},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 530, 4, 1409},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 534, 2, 1413},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 538, 9, 1415},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 542, 13, 1424},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 546, 2, 1437},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 550, 27, 1439},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 554, 27, 1466},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 558, 2, 1493},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 562, 2, 1495},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 566, 2, 1497},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 570, 2, 1499},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 574, 2, 1501},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 578, 2, 1503},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 582, 2, 1505},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 586, 2, 1507},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 590, 2, 1509},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 594, 2, 1511},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 598, 2, 1513},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 602, 2, 1515},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 606, 4, 1517},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 610, 2, 1521},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 614, 2, 1523},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 618, 2, 1525},
- {"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 622, 4, 1527},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 623, 4, 1531},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 624, 2, 1535},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 625, 5, 1537},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 626, 2, 1542},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 627, 2, 1544},
- {"cvmx_gmx#_soft_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 631, 3, 1546},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 632, 3, 1549},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 633, 5, 1552},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 637, 2, 1557},
- {"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 641, 2, 1559},
- {"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 642, 2, 1561},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 643, 3, 1563},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 647, 2, 1566},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 651, 2, 1568},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 655, 2, 1570},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 659, 3, 1572},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 663, 2, 1575},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 667, 2, 1577},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 671, 2, 1579},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 675, 2, 1581},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 679, 2, 1583},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 683, 2, 1585},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 687, 2, 1587},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 691, 2, 1589},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 695, 2, 1591},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 699, 2, 1593},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 703, 2, 1595},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 707, 2, 1597},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 711, 2, 1599},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 715, 2, 1601},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 719, 2, 1603},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 723, 2, 1605},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 727, 2, 1607},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 728, 2, 1609},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 729, 2, 1611},
- {"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 730, 2, 1613},
- {"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 731, 2, 1615},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 732, 3, 1617},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 733, 9, 1620},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 734, 9, 1629},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 735, 2, 1638},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 736, 2, 1640},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 737, 6, 1642},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 738, 2, 1648},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 739, 2, 1650},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 740, 2, 1652},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 741, 9, 1654},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 742, 3, 1663},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 743, 10, 1666},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 759, 2, 1676},
- {"cvmx_gpio_clk_qlm#" , CVMX_CSR_DB_TYPE_NCB, 64, 763, 3, 1678},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 765, 2, 1681},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 766, 2, 1683},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 767, 2, 1685},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 768, 2, 1687},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 769, 24, 1689},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 770, 8, 1713},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 771, 3, 1721},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 772, 3, 1724},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 773, 3, 1727},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 774, 5, 1730},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 775, 5, 1735},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 776, 1, 1740},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 777, 1, 1741},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 778, 7, 1742},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 779, 7, 1749},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 780, 3, 1756},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 781, 3, 1759},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 782, 3, 1762},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 783, 5, 1765},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 784, 5, 1770},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 785, 1, 1775},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 786, 1, 1776},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 787, 3, 1777},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 788, 3, 1780},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 789, 3, 1783},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 790, 3, 1786},
- {"cvmx_iob_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 791, 4, 1789},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 792, 2, 1793},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 793, 2, 1795},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 794, 2, 1797},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 795, 19, 1799},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 796, 2, 1818},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 797, 1, 1820},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 798, 16, 1821},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 799, 13, 1837},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 800, 13, 1850},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 801, 2, 1863},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 802, 2, 1865},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 803, 2, 1867},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 804, 3, 1869},
- {"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 812, 3, 1872},
- {"cvmx_ipd_port#_bp_page_cnt3" , CVMX_CSR_DB_TYPE_NCB, 64, 816, 3, 1875},
- {"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 820, 2, 1878},
- {"cvmx_ipd_port_bp_counters3_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 824, 2, 1880},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 828, 2, 1882},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 836, 2, 1884},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 964, 1, 1886},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 967, 1, 1887},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 970, 6, 1888},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 971, 5, 1894},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 972, 6, 1899},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 973, 7, 1905},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 974, 2, 1912},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 982, 2, 1914},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 983, 3, 1916},
- {"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 984, 2, 1919},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 985, 5, 1921},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 993, 3, 1926},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 994, 4, 1929},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 995, 3, 1933},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 996, 2, 1936},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 997, 2, 1938},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 4, 1940},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 999, 3, 1944},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1000, 5, 1947},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1001, 5, 1952},
- {"cvmx_l2c_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 1002, 12, 1957},
- {"cvmx_l2c_bst_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 5, 1969},
- {"cvmx_l2c_bst_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 4, 1974},
- {"cvmx_l2c_bst_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1005, 3, 1978},
- {"cvmx_l2c_cop0_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 1, 1981},
- {"cvmx_l2c_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2798, 11, 1982},
- {"cvmx_l2c_dut_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 2799, 4, 1993},
- {"cvmx_l2c_err_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 4335, 9, 1997},
- {"cvmx_l2c_err_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 4336, 9, 2006},
- {"cvmx_l2c_err_vbf#" , CVMX_CSR_DB_TYPE_RSL, 64, 4337, 6, 2015},
- {"cvmx_l2c_err_xmc" , CVMX_CSR_DB_TYPE_RSL, 64, 4338, 5, 2021},
- {"cvmx_l2c_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 4339, 7, 2026},
- {"cvmx_l2c_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 4340, 9, 2033},
- {"cvmx_l2c_ioc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4341, 1, 2042},
- {"cvmx_l2c_ior#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4342, 1, 2043},
- {"cvmx_l2c_qos_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 4343, 4, 2044},
- {"cvmx_l2c_qos_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 4344, 2, 2048},
- {"cvmx_l2c_qos_wgt" , CVMX_CSR_DB_TYPE_RSL, 64, 4350, 5, 2050},
- {"cvmx_l2c_rsc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4351, 1, 2055},
- {"cvmx_l2c_rsd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4352, 1, 2056},
- {"cvmx_l2c_tad#_ecc0" , CVMX_CSR_DB_TYPE_RSL, 64, 4353, 8, 2057},
- {"cvmx_l2c_tad#_ecc1" , CVMX_CSR_DB_TYPE_RSL, 64, 4354, 8, 2065},
- {"cvmx_l2c_tad#_ien" , CVMX_CSR_DB_TYPE_RSL, 64, 4355, 8, 2073},
- {"cvmx_l2c_tad#_pfc0" , CVMX_CSR_DB_TYPE_RSL, 64, 4356, 1, 2081},
- {"cvmx_l2c_tad#_pfc1" , CVMX_CSR_DB_TYPE_RSL, 64, 4357, 1, 2082},
- {"cvmx_l2c_tad#_pfc2" , CVMX_CSR_DB_TYPE_RSL, 64, 4358, 1, 2083},
- {"cvmx_l2c_tad#_pfc3" , CVMX_CSR_DB_TYPE_RSL, 64, 4359, 1, 2084},
- {"cvmx_l2c_tad#_prf" , CVMX_CSR_DB_TYPE_RSL, 64, 4360, 5, 2085},
- {"cvmx_l2c_tad#_tag" , CVMX_CSR_DB_TYPE_RSL, 64, 4361, 9, 2090},
- {"cvmx_l2c_ver_id" , CVMX_CSR_DB_TYPE_RSL, 64, 4362, 1, 2099},
- {"cvmx_l2c_ver_iob" , CVMX_CSR_DB_TYPE_RSL, 64, 4363, 2, 2100},
- {"cvmx_l2c_ver_pp" , CVMX_CSR_DB_TYPE_RSL, 64, 4364, 2, 2102},
- {"cvmx_l2c_virtid_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 4365, 4, 2104},
- {"cvmx_l2c_virtid_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 4366, 2, 2108},
- {"cvmx_l2c_vrt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4372, 6, 2110},
- {"cvmx_l2c_vrt_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 4373, 3, 2116},
- {"cvmx_l2c_wpar_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 5397, 2, 2119},
- {"cvmx_l2c_wpar_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 5398, 2, 2121},
- {"cvmx_l2c_xmc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 5404, 1, 2123},
- {"cvmx_l2c_xmc_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 5405, 4, 2124},
- {"cvmx_l2c_xmd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 5406, 1, 2128},
- {"cvmx_lmc#_char_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5407, 5, 2129},
- {"cvmx_lmc#_char_mask0" , CVMX_CSR_DB_TYPE_RSL, 64, 5408, 1, 2134},
- {"cvmx_lmc#_char_mask1" , CVMX_CSR_DB_TYPE_RSL, 64, 5409, 2, 2135},
- {"cvmx_lmc#_char_mask2" , CVMX_CSR_DB_TYPE_RSL, 64, 5410, 1, 2137},
- {"cvmx_lmc#_char_mask3" , CVMX_CSR_DB_TYPE_RSL, 64, 5411, 2, 2138},
- {"cvmx_lmc#_char_mask4" , CVMX_CSR_DB_TYPE_RSL, 64, 5412, 12, 2140},
- {"cvmx_lmc#_comp_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 5413, 11, 2152},
- {"cvmx_lmc#_config" , CVMX_CSR_DB_TYPE_RSL, 64, 5414, 17, 2163},
- {"cvmx_lmc#_control" , CVMX_CSR_DB_TYPE_RSL, 64, 5415, 20, 2180},
- {"cvmx_lmc#_dclk_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5416, 1, 2200},
- {"cvmx_lmc#_ddr_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5417, 11, 2201},
- {"cvmx_lmc#_dimm#_params" , CVMX_CSR_DB_TYPE_RSL, 64, 5418, 16, 2212},
- {"cvmx_lmc#_dimm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5420, 5, 2228},
- {"cvmx_lmc#_dll_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 5421, 6, 2233},
- {"cvmx_lmc#_dll_ctl3" , CVMX_CSR_DB_TYPE_RSL, 64, 5422, 11, 2239},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 5423, 4, 2250},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 5424, 5, 2254},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 5425, 6, 2259},
- {"cvmx_lmc#_ifb_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5426, 1, 2265},
- {"cvmx_lmc#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5427, 4, 2266},
- {"cvmx_lmc#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5428, 4, 2270},
- {"cvmx_lmc#_modereg_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 5429, 16, 2274},
- {"cvmx_lmc#_modereg_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 5430, 25, 2290},
- {"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 5431, 10, 2315},
- {"cvmx_lmc#_ops_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5432, 1, 2325},
- {"cvmx_lmc#_phy_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5433, 9, 2326},
- {"cvmx_lmc#_reset_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5434, 5, 2335},
- {"cvmx_lmc#_rlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5435, 4, 2340},
- {"cvmx_lmc#_rlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 5436, 1, 2344},
- {"cvmx_lmc#_rlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 5437, 11, 2345},
- {"cvmx_lmc#_rodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 5441, 8, 2356},
- {"cvmx_lmc#_slot_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 5442, 5, 2364},
- {"cvmx_lmc#_slot_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 5443, 5, 2369},
- {"cvmx_lmc#_slot_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 5444, 5, 2374},
- {"cvmx_lmc#_timing_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 5445, 11, 2379},
- {"cvmx_lmc#_timing_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 5446, 12, 2390},
- {"cvmx_lmc#_tro_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5447, 3, 2402},
- {"cvmx_lmc#_tro_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 5448, 2, 2405},
- {"cvmx_lmc#_wlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5449, 3, 2407},
- {"cvmx_lmc#_wlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 5450, 3, 2410},
- {"cvmx_lmc#_wlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 5451, 11, 2413},
- {"cvmx_lmc#_wodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 5455, 8, 2424},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 5456, 2, 2432},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 5457, 3, 2434},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 5458, 10, 2437},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 5460, 3, 2447},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 5462, 3, 2450},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 5464, 15, 2453},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 5466, 3, 2468},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5467, 3, 2471},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 5468, 3, 2474},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 5469, 5, 2477},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 5471, 1, 2482},
- {"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 5472, 9, 2483},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 5473, 13, 2492},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 5481, 13, 2505},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 5489, 6, 2518},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 5490, 1, 2524},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 5492, 2, 2525},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 5493, 2, 2527},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 5494, 12, 2529},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 5495, 18, 2541},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 5496, 4, 2559},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 5497, 1, 2563},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 5498, 7, 2564},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 5499, 3, 2571},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 5500, 8, 2574},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 5501, 7, 2582},
- {"cvmx_mio_fus_read_times" , CVMX_CSR_DB_TYPE_RSL, 64, 5502, 6, 2589},
- {"cvmx_mio_fus_repair_res0" , CVMX_CSR_DB_TYPE_RSL, 64, 5503, 5, 2595},
- {"cvmx_mio_fus_repair_res1" , CVMX_CSR_DB_TYPE_RSL, 64, 5504, 4, 2600},
- {"cvmx_mio_fus_repair_res2" , CVMX_CSR_DB_TYPE_RSL, 64, 5505, 2, 2604},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 5506, 4, 2606},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 5507, 2, 2610},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 5508, 2, 2612},
- {"cvmx_mio_gpio_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 5509, 3, 2614},
- {"cvmx_mio_ndf_dma_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 5510, 10, 2617},
- {"cvmx_mio_ndf_dma_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5511, 2, 2627},
- {"cvmx_mio_ndf_dma_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5512, 2, 2629},
- {"cvmx_mio_ptp_clock_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5513, 10, 2631},
- {"cvmx_mio_ptp_clock_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 5514, 2, 2641},
- {"cvmx_mio_ptp_clock_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 5515, 1, 2643},
- {"cvmx_mio_ptp_clock_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 5516, 2, 2644},
- {"cvmx_mio_ptp_evt_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5517, 1, 2646},
- {"cvmx_mio_ptp_timestamp" , CVMX_CSR_DB_TYPE_NCB, 64, 5518, 1, 2647},
- {"cvmx_mio_rst_boot" , CVMX_CSR_DB_TYPE_RSL, 64, 5519, 9, 2648},
- {"cvmx_mio_rst_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 5520, 4, 2657},
- {"cvmx_mio_rst_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 5521, 9, 2661},
- {"cvmx_mio_rst_delay" , CVMX_CSR_DB_TYPE_RSL, 64, 5523, 3, 2670},
- {"cvmx_mio_rst_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5524, 6, 2673},
- {"cvmx_mio_rst_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5525, 6, 2679},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5526, 13, 2685},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 5528, 12, 2698},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 5530, 3, 2710},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 5532, 3, 2713},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 5534, 2, 2716},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 5536, 2, 2718},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 5538, 2, 2720},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 5540, 7, 2722},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 5542, 2, 2729},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 5544, 7, 2731},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 5546, 4, 2738},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 5548, 8, 2742},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 5550, 9, 2750},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 5552, 7, 2759},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 5554, 9, 2766},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 5556, 2, 2775},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 5558, 2, 2777},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 5560, 4, 2779},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 5562, 2, 2783},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 5564, 2, 2785},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 5566, 2, 2787},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 5568, 4, 2789},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 5570, 2, 2793},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 5572, 2, 2795},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 5574, 2, 2797},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 5576, 2, 2799},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 5578, 2, 2801},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 5580, 2, 2803},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 5582, 6, 2805},
- {"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 5584, 7, 2811},
- {"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 5586, 9, 2818},
- {"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 5588, 9, 2827},
- {"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5590, 2, 2836},
- {"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 5592, 3, 2838},
- {"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 5594, 4, 2841},
- {"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 5596, 4, 2845},
- {"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 5598, 9, 2849},
- {"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5600, 2, 2858},
- {"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 5602, 2, 2860},
- {"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 5604, 4, 2862},
- {"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 5606, 4, 2866},
- {"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5608, 4, 2870},
- {"cvmx_mix#_tsctl" , CVMX_CSR_DB_TYPE_NCB, 64, 5610, 6, 2874},
- {"cvmx_mix#_tstamp" , CVMX_CSR_DB_TYPE_NCB, 64, 5612, 1, 2880},
- {"cvmx_ndf_bt_pg_info" , CVMX_CSR_DB_TYPE_NCB, 64, 5614, 4, 2881},
- {"cvmx_ndf_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 5615, 1, 2885},
- {"cvmx_ndf_drbell" , CVMX_CSR_DB_TYPE_NCB, 64, 5616, 2, 2886},
- {"cvmx_ndf_ecc_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5617, 3, 2888},
- {"cvmx_ndf_int" , CVMX_CSR_DB_TYPE_NCB, 64, 5618, 8, 2891},
- {"cvmx_ndf_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5619, 8, 2899},
- {"cvmx_ndf_misc" , CVMX_CSR_DB_TYPE_NCB, 64, 5620, 12, 2907},
- {"cvmx_ndf_st_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 5621, 8, 2919},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5622, 2, 2927},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5624, 24, 2929},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5626, 4, 2953},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5628, 5, 2957},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5630, 5, 2962},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5632, 2, 2967},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5634, 1, 2969},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5636, 1, 2970},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5638, 5, 2971},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5640, 2, 2976},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5642, 1, 2978},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5644, 1, 2979},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5646, 4, 2980},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5648, 2, 2984},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5650, 2, 2986},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5652, 1, 2988},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5654, 1, 2989},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5656, 2, 2990},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5658, 3, 2992},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5660, 2, 2995},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5662, 2, 2997},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5664, 4, 2999},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5666, 10, 3003},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5668, 12, 3013},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5670, 7, 3025},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5672, 2, 3032},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5674, 1, 3034},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5676, 2, 3035},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5678, 7, 3037},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5680, 11, 3044},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5682, 19, 3055},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5684, 11, 3074},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5686, 17, 3085},
- {"cvmx_pcieep#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5688, 12, 3102},
- {"cvmx_pcieep#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5690, 22, 3114},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5692, 3, 3136},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5694, 3, 3139},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5696, 1, 3142},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5698, 11, 3143},
- {"cvmx_pcieep#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5700, 1, 3154},
- {"cvmx_pcieep#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5702, 1, 3155},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5704, 3, 3156},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5706, 14, 3159},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5708, 14, 3173},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5710, 14, 3187},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5712, 9, 3201},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5714, 9, 3210},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5716, 6, 3219},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5718, 1, 3225},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5720, 1, 3226},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5722, 1, 3227},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5724, 1, 3228},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5726, 2, 3229},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5728, 1, 3231},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5730, 6, 3232},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5732, 6, 3238},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5734, 13, 3244},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5736, 5, 3257},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5738, 8, 3262},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5740, 19, 3270},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5742, 3, 3289},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5744, 1, 3292},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5746, 1, 3293},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5748, 3, 3294},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5750, 3, 3297},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5752, 3, 3300},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5754, 4, 3303},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5756, 4, 3307},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5758, 4, 3311},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5760, 7, 3315},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5762, 5, 3322},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5764, 5, 3327},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5766, 4, 3332},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5768, 4, 3336},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5770, 4, 3340},
- {"cvmx_pcieep#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5772, 7, 3344},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5774, 1, 3351},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5776, 1, 3352},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5778, 2, 3353},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5780, 24, 3355},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5782, 4, 3379},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5784, 5, 3383},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5786, 1, 3388},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5788, 1, 3389},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5790, 4, 3390},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5792, 17, 3394},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5794, 4, 3411},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5796, 6, 3415},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5798, 1, 3421},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5800, 1, 3422},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5802, 2, 3423},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5804, 2, 3425},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5806, 1, 3427},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5808, 15, 3428},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5810, 10, 3443},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5812, 12, 3453},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5814, 7, 3465},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5816, 2, 3472},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5818, 1, 3474},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5820, 2, 3475},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5822, 7, 3477},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5824, 11, 3484},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5826, 19, 3495},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5828, 11, 3514},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5830, 20, 3525},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5832, 12, 3545},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5834, 22, 3557},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5836, 8, 3579},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5838, 4, 3587},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5840, 3, 3591},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5842, 3, 3594},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5844, 1, 3597},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5846, 11, 3598},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5848, 1, 3609},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5850, 1, 3610},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5852, 3, 3611},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5854, 14, 3614},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5856, 14, 3628},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5858, 14, 3642},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5860, 9, 3656},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5862, 9, 3665},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5864, 6, 3674},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5866, 1, 3680},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5868, 1, 3681},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5870, 1, 3682},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5872, 1, 3683},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5874, 4, 3684},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5876, 9, 3688},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5878, 2, 3697},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5880, 2, 3699},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5882, 1, 3701},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5884, 6, 3702},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5886, 6, 3708},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5888, 13, 3714},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5890, 5, 3727},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5892, 8, 3732},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5894, 19, 3740},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5896, 3, 3759},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5898, 1, 3762},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5900, 1, 3763},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5902, 3, 3764},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5904, 3, 3767},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5906, 3, 3770},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5908, 4, 3773},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5910, 4, 3777},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5912, 4, 3781},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5914, 7, 3785},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5916, 5, 3792},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5918, 5, 3797},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5920, 4, 3802},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5922, 4, 3806},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5924, 4, 3810},
- {"cvmx_pcierc#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5926, 7, 3814},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5928, 1, 3821},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5930, 1, 3822},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5932, 9, 3823},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5936, 6, 3832},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5940, 9, 3838},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5944, 6, 3847},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5948, 14, 3853},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5952, 14, 3867},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 5956, 2, 3881},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5960, 4, 3883},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5964, 8, 3887},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5968, 13, 3895},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5972, 17, 3908},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5976, 7, 3925},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5980, 3, 3932},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5984, 8, 3935},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5988, 7, 3943},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5992, 4, 3950},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 5996, 5, 3954},
- {"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6000, 8, 3959},
- {"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6001, 2, 3967},
- {"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 6002, 5, 3969},
- {"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6003, 10, 3974},
- {"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6004, 2, 3984},
- {"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6005, 8, 3986},
- {"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6006, 8, 3994},
- {"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6007, 6, 4002},
- {"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6008, 5, 4008},
- {"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 6009, 5, 4013},
- {"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6010, 3, 4018},
- {"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6011, 6, 4021},
- {"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6012, 9, 4027},
- {"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 6013, 5, 4036},
- {"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6014, 10, 4041},
- {"cvmx_pem#_bar1_index#" , CVMX_CSR_DB_TYPE_RSL, 64, 6015, 5, 4051},
- {"cvmx_pem#_bar_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6047, 5, 4056},
- {"cvmx_pem#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6049, 9, 4061},
- {"cvmx_pem#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 6051, 11, 4070},
- {"cvmx_pem#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 6053, 2, 4081},
- {"cvmx_pem#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 6055, 2, 4083},
- {"cvmx_pem#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 6057, 2, 4085},
- {"cvmx_pem#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6059, 18, 4087},
- {"cvmx_pem#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 6061, 32, 4105},
- {"cvmx_pem#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 6063, 32, 4137},
- {"cvmx_pem#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6065, 5, 4169},
- {"cvmx_pem#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 6067, 15, 4174},
- {"cvmx_pem#_int_enb_int" , CVMX_CSR_DB_TYPE_RSL, 64, 6069, 15, 4189},
- {"cvmx_pem#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 6071, 15, 4204},
- {"cvmx_pem#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 6073, 2, 4219},
- {"cvmx_pem#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 6075, 2, 4221},
- {"cvmx_pem#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 6077, 2, 4223},
- {"cvmx_pem#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 6079, 2, 4225},
- {"cvmx_pem#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 6087, 2, 4227},
- {"cvmx_pem#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 6095, 8, 4229},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 6097, 5, 4237},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6098, 2, 4242},
- {"cvmx_pip_clken" , CVMX_CSR_DB_TYPE_RSL, 64, 6099, 2, 4244},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 6100, 4, 4246},
- {"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 6104, 16, 4250},
- {"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 6105, 16, 4266},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 6106, 3, 4282},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 6107, 8, 4285},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6108, 23, 4293},
- {"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6109, 6, 4316},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 6110, 14, 4322},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6111, 14, 4336},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 6112, 2, 4350},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 6113, 28, 4352},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 6129, 25, 4380},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 6145, 2, 4405},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 6209, 4, 4407},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 6217, 9, 4411},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 6225, 2, 4420},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 6226, 2, 4422},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6227, 2, 4424},
- {"cvmx_pip_stat10_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6239, 2, 4426},
- {"cvmx_pip_stat11_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6251, 2, 4428},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6263, 2, 4430},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6275, 2, 4432},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6287, 2, 4434},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6299, 2, 4436},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6311, 2, 4438},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6323, 2, 4440},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6335, 2, 4442},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6347, 2, 4444},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6359, 2, 4446},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6371, 2, 4448},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 6372, 2, 4450},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 6388, 2, 4452},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 6404, 2, 4454},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 6420, 2, 4456},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6484, 2, 4458},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 6485, 3, 4460},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 6486, 3, 4463},
- {"cvmx_pip_xstat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6487, 2, 4466},
- {"cvmx_pip_xstat10_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6491, 2, 4468},
- {"cvmx_pip_xstat11_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6495, 2, 4470},
- {"cvmx_pip_xstat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6499, 2, 4472},
- {"cvmx_pip_xstat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6503, 2, 4474},
- {"cvmx_pip_xstat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6507, 2, 4476},
- {"cvmx_pip_xstat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6511, 2, 4478},
- {"cvmx_pip_xstat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6515, 2, 4480},
- {"cvmx_pip_xstat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6519, 2, 4482},
- {"cvmx_pip_xstat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6523, 2, 4484},
- {"cvmx_pip_xstat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6527, 2, 4486},
- {"cvmx_pip_xstat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6531, 2, 4488},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 6535, 2, 4490},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 6536, 2, 4492},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6537, 4, 4494},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6538, 5, 4498},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 6539, 4, 4503},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 6540, 8, 4507},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 6541, 4, 4515},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 6542, 5, 4519},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 6543, 1, 4524},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6544, 5, 4525},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6545, 1, 4530},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 6546, 13, 4531},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 6547, 6, 4544},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 6548, 13, 4550},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 6549, 6, 4563},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 6550, 9, 4569},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 6551, 4, 4578},
- {"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 6552, 7, 4582},
- {"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6553, 5, 4589},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 6554, 5, 4594},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 6555, 4, 4599},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 6556, 9, 4603},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6557, 5, 4612},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 6558, 16, 4617},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 6559, 4, 4633},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6560, 1, 4637},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6561, 1, 4638},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6562, 1, 4639},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6563, 1, 4640},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 6564, 13, 4641},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 6565, 2, 4654},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 6566, 4, 4656},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 6567, 5, 4660},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 6568, 3, 4665},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6569, 4, 4668},
- {"cvmx_pko_reg_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 6570, 2, 4672},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 6571, 2, 4674},
- {"cvmx_pko_reg_queue_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 6572, 3, 4676},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 6573, 3, 4679},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 6574, 3, 4682},
- {"cvmx_pko_reg_timestamp" , CVMX_CSR_DB_TYPE_RSL, 64, 6575, 2, 4685},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 6576, 10, 4687},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6577, 2, 4697},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 6578, 13, 4699},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 6579, 3, 4712},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 6580, 2, 4715},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 6588, 2, 4717},
- {"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 6589, 2, 4719},
- {"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 6590, 2, 4721},
- {"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6591, 2, 4723},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 6599, 2, 4725},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 6600, 2, 4727},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 6601, 2, 4729},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 6602, 10, 4731},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 6608, 5, 4741},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6616, 10, 4746},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6624, 2, 4756},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6625, 2, 4758},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 6626, 2, 4760},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 6634, 3, 4762},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 6635, 6, 4765},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6651, 5, 4771},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6652, 7, 4776},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 6668, 2, 4783},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6684, 1, 4785},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6685, 1, 4786},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6686, 1, 4787},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 6687, 5, 4788},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 6688, 5, 4793},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6689, 4, 4798},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6690, 10, 4802},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6691, 1, 4812},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 6692, 3, 4813},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 6693, 7, 4816},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 6694, 2, 4823},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6695, 1, 4825},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6696, 1, 4826},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 6697, 1, 4827},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 6698, 18, 4828},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 6699, 3, 4846},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 6700, 2, 4849},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 6701, 3, 4851},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 6702, 7, 4854},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 6703, 2, 4861},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6704, 2, 4863},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 6705, 2, 4865},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 6706, 3, 4867},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6707, 3, 4870},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6708, 9, 4873},
- {"cvmx_rnm_eer_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 6709, 1, 4882},
- {"cvmx_rnm_eer_key" , CVMX_CSR_DB_TYPE_RSL, 64, 6710, 1, 4883},
- {"cvmx_sli_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6711, 25, 4884},
- {"cvmx_sli_ctl_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6712, 16, 4909},
- {"cvmx_sli_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6714, 4, 4925},
- {"cvmx_sli_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6715, 5, 4929},
- {"cvmx_sli_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6716, 3, 4934},
- {"cvmx_sli_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6717, 3, 4937},
- {"cvmx_sli_dma#_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6718, 2, 4940},
- {"cvmx_sli_dma#_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6720, 2, 4942},
- {"cvmx_sli_dma#_tim" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6722, 2, 4944},
- {"cvmx_sli_int_enb_ciu" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6724, 35, 4946},
- {"cvmx_sli_int_enb_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6725, 37, 4981},
- {"cvmx_sli_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6727, 37, 5018},
- {"cvmx_sli_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6728, 1, 5055},
- {"cvmx_sli_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6729, 1, 5056},
- {"cvmx_sli_mac_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6730, 7, 5057},
- {"cvmx_sli_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6731, 3, 5064},
- {"cvmx_sli_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6732, 9, 5067},
- {"cvmx_sli_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6748, 1, 5076},
- {"cvmx_sli_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6749, 1, 5077},
- {"cvmx_sli_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6750, 1, 5078},
- {"cvmx_sli_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6751, 1, 5079},
- {"cvmx_sli_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6752, 1, 5080},
- {"cvmx_sli_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6753, 1, 5081},
- {"cvmx_sli_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6754, 1, 5082},
- {"cvmx_sli_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6755, 1, 5083},
- {"cvmx_sli_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6756, 3, 5084},
- {"cvmx_sli_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6757, 1, 5087},
- {"cvmx_sli_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6758, 1, 5088},
- {"cvmx_sli_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6759, 1, 5089},
- {"cvmx_sli_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6760, 1, 5090},
- {"cvmx_sli_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6761, 1, 5091},
- {"cvmx_sli_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6762, 1, 5092},
- {"cvmx_sli_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6763, 1, 5093},
- {"cvmx_sli_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6764, 1, 5094},
- {"cvmx_sli_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6765, 3, 5095},
- {"cvmx_sli_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6766, 2, 5098},
- {"cvmx_sli_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6767, 3, 5100},
- {"cvmx_sli_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6768, 3, 5103},
- {"cvmx_sli_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6769, 3, 5106},
- {"cvmx_sli_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6770, 3, 5109},
- {"cvmx_sli_pkt#_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6802, 2, 5112},
- {"cvmx_sli_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6834, 2, 5114},
- {"cvmx_sli_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6866, 2, 5116},
- {"cvmx_sli_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6898, 5, 5118},
- {"cvmx_sli_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6930, 21, 5123},
- {"cvmx_sli_pkt#_out_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6962, 3, 5144},
- {"cvmx_sli_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6994, 2, 5147},
- {"cvmx_sli_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7026, 2, 5149},
- {"cvmx_sli_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7058, 2, 5151},
- {"cvmx_sli_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7090, 2, 5153},
- {"cvmx_sli_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7091, 2, 5155},
- {"cvmx_sli_pkt_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7092, 3, 5157},
- {"cvmx_sli_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7093, 1, 5160},
- {"cvmx_sli_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7094, 2, 5161},
- {"cvmx_sli_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7095, 2, 5163},
- {"cvmx_sli_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7096, 2, 5165},
- {"cvmx_sli_pkt_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7097, 2, 5167},
- {"cvmx_sli_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7098, 2, 5169},
- {"cvmx_sli_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7130, 2, 5171},
- {"cvmx_sli_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7131, 1, 5173},
- {"cvmx_sli_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7132, 10, 5174},
- {"cvmx_sli_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7133, 2, 5184},
- {"cvmx_sli_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7134, 1, 5186},
- {"cvmx_sli_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7135, 2, 5187},
- {"cvmx_sli_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7136, 3, 5189},
- {"cvmx_sli_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7137, 2, 5192},
- {"cvmx_sli_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7138, 2, 5194},
- {"cvmx_sli_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7139, 2, 5196},
- {"cvmx_sli_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7140, 2, 5198},
- {"cvmx_sli_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7141, 1, 5200},
- {"cvmx_sli_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7142, 2, 5201},
- {"cvmx_sli_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7143, 1, 5203},
- {"cvmx_sli_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7144, 2, 5204},
- {"cvmx_sli_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7145, 2, 5206},
- {"cvmx_sli_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7146, 2, 5208},
- {"cvmx_sli_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7147, 2, 5210},
- {"cvmx_sli_s2m_port#_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7148, 4, 5212},
- {"cvmx_sli_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7150, 1, 5216},
- {"cvmx_sli_scratch_2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7151, 1, 5217},
- {"cvmx_sli_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7152, 4, 5218},
- {"cvmx_sli_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7153, 8, 5222},
- {"cvmx_sli_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7154, 5, 5230},
- {"cvmx_sli_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 7155, 4, 5235},
- {"cvmx_sli_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 7156, 1, 5239},
- {"cvmx_sli_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 7157, 4, 5240},
- {"cvmx_sli_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 7158, 1, 5244},
- {"cvmx_sli_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 7159, 2, 5245},
- {"cvmx_sli_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7160, 2, 5247},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 7161, 10, 5249},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7163, 6, 5259},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 7165, 2, 5265},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7167, 4, 5267},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7169, 4, 5271},
- {"cvmx_smi_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7171, 4, 5275},
- {"cvmx_srio#_acc_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7172, 4, 5279},
- {"cvmx_srio#_asmbly_id" , CVMX_CSR_DB_TYPE_RSL, 64, 7174, 3, 5283},
- {"cvmx_srio#_asmbly_info" , CVMX_CSR_DB_TYPE_RSL, 64, 7176, 3, 5286},
- {"cvmx_srio#_bell_resp_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7178, 5, 5289},
- {"cvmx_srio#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7180, 18, 5294},
- {"cvmx_srio#_imsg_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7182, 14, 5312},
- {"cvmx_srio#_imsg_inst_hdr#" , CVMX_CSR_DB_TYPE_RSL, 64, 7184, 14, 5326},
- {"cvmx_srio#_imsg_qos_grp#" , CVMX_CSR_DB_TYPE_RSL, 64, 7188, 24, 5340},
- {"cvmx_srio#_imsg_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 7252, 24, 5364},
- {"cvmx_srio#_imsg_vport_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 7300, 13, 5388},
- {"cvmx_srio#_int_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 7302, 23, 5401},
- {"cvmx_srio#_int_info0" , CVMX_CSR_DB_TYPE_RSL, 64, 7304, 9, 5424},
- {"cvmx_srio#_int_info1" , CVMX_CSR_DB_TYPE_RSL, 64, 7306, 1, 5433},
- {"cvmx_srio#_int_info2" , CVMX_CSR_DB_TYPE_RSL, 64, 7308, 11, 5434},
- {"cvmx_srio#_int_info3" , CVMX_CSR_DB_TYPE_RSL, 64, 7310, 5, 5445},
- {"cvmx_srio#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7312, 23, 5450},
- {"cvmx_srio#_ip_feature" , CVMX_CSR_DB_TYPE_RSL, 64, 7314, 9, 5473},
- {"cvmx_srio#_maint_op" , CVMX_CSR_DB_TYPE_RSL, 64, 7316, 6, 5482},
- {"cvmx_srio#_maint_rd_data" , CVMX_CSR_DB_TYPE_RSL, 64, 7318, 3, 5488},
- {"cvmx_srio#_mce_tx_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7320, 2, 5491},
- {"cvmx_srio#_mem_op_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7322, 8, 5493},
- {"cvmx_srio#_omsg_ctrl#" , CVMX_CSR_DB_TYPE_RSL, 64, 7324, 10, 5501},
- {"cvmx_srio#_omsg_fmp_mr#" , CVMX_CSR_DB_TYPE_RSL, 64, 7328, 16, 5511},
- {"cvmx_srio#_omsg_nmp_mr#" , CVMX_CSR_DB_TYPE_RSL, 64, 7332, 16, 5527},
- {"cvmx_srio#_omsg_port#" , CVMX_CSR_DB_TYPE_RSL, 64, 7336, 4, 5543},
- {"cvmx_srio#_omsg_sp_mr#" , CVMX_CSR_DB_TYPE_RSL, 64, 7340, 17, 5547},
- {"cvmx_srio#_rx_bell" , CVMX_CSR_DB_TYPE_RSL, 64, 7344, 9, 5564},
- {"cvmx_srio#_rx_bell_seq" , CVMX_CSR_DB_TYPE_RSL, 64, 7346, 3, 5573},
- {"cvmx_srio#_rx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7348, 9, 5576},
- {"cvmx_srio#_s2m_type#" , CVMX_CSR_DB_TYPE_RSL, 64, 7350, 11, 5585},
- {"cvmx_srio#_seq" , CVMX_CSR_DB_TYPE_RSL, 64, 7382, 2, 5596},
- {"cvmx_srio#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7384, 3, 5598},
- {"cvmx_srio#_tag_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7386, 6, 5601},
- {"cvmx_srio#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 7388, 6, 5607},
- {"cvmx_srio#_tx_bell" , CVMX_CSR_DB_TYPE_RSL, 64, 7390, 10, 5613},
- {"cvmx_srio#_tx_bell_info" , CVMX_CSR_DB_TYPE_RSL, 64, 7392, 11, 5623},
- {"cvmx_srio#_tx_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7394, 12, 5634},
- {"cvmx_srio#_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7396, 5, 5646},
- {"cvmx_sriomaint#_asmbly_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7398, 2, 5651},
- {"cvmx_sriomaint#_asmbly_info" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7400, 2, 5653},
- {"cvmx_sriomaint#_bar1_idx#" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7402, 7, 5655},
- {"cvmx_sriomaint#_bell_status" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7434, 2, 5662},
- {"cvmx_sriomaint#_comp_tag" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7436, 1, 5664},
- {"cvmx_sriomaint#_core_enables", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7438, 6, 5665},
- {"cvmx_sriomaint#_dev_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7440, 2, 5671},
- {"cvmx_sriomaint#_dev_rev" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7442, 2, 5673},
- {"cvmx_sriomaint#_dst_ops" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7444, 26, 5675},
- {"cvmx_sriomaint#_erb_attr_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7446, 4, 5701},
- {"cvmx_sriomaint#_erb_err_det" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7448, 14, 5705},
- {"cvmx_sriomaint#_erb_err_rate", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7450, 5, 5719},
- {"cvmx_sriomaint#_erb_err_rate_en", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7452, 14, 5724},
- {"cvmx_sriomaint#_erb_err_rate_thr", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7454, 3, 5738},
- {"cvmx_sriomaint#_erb_hdr" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7456, 2, 5741},
- {"cvmx_sriomaint#_erb_lt_addr_capt_h", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7458, 1, 5743},
- {"cvmx_sriomaint#_erb_lt_addr_capt_l", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7460, 3, 5744},
- {"cvmx_sriomaint#_erb_lt_ctrl_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7462, 9, 5747},
- {"cvmx_sriomaint#_erb_lt_dev_id", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7464, 4, 5756},
- {"cvmx_sriomaint#_erb_lt_dev_id_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7466, 4, 5760},
- {"cvmx_sriomaint#_erb_lt_err_det", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7468, 12, 5764},
- {"cvmx_sriomaint#_erb_lt_err_en", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7470, 12, 5776},
- {"cvmx_sriomaint#_erb_pack_capt_1", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7472, 1, 5788},
- {"cvmx_sriomaint#_erb_pack_capt_2", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7474, 1, 5789},
- {"cvmx_sriomaint#_erb_pack_capt_3", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7476, 1, 5790},
- {"cvmx_sriomaint#_erb_pack_sym_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7478, 1, 5791},
- {"cvmx_sriomaint#_hb_dev_id_lock", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7480, 2, 5792},
- {"cvmx_sriomaint#_ir_buffer_config", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7482, 7, 5794},
- {"cvmx_sriomaint#_ir_pd_phy_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7484, 1, 5801},
- {"cvmx_sriomaint#_ir_pd_phy_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7486, 9, 5802},
- {"cvmx_sriomaint#_ir_pi_phy_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7488, 5, 5811},
- {"cvmx_sriomaint#_ir_pi_phy_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7490, 2, 5816},
- {"cvmx_sriomaint#_ir_sp_rx_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7492, 2, 5818},
- {"cvmx_sriomaint#_ir_sp_rx_data", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7494, 1, 5820},
- {"cvmx_sriomaint#_ir_sp_rx_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7496, 5, 5821},
- {"cvmx_sriomaint#_ir_sp_tx_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7498, 2, 5826},
- {"cvmx_sriomaint#_ir_sp_tx_data", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7500, 1, 5828},
- {"cvmx_sriomaint#_ir_sp_tx_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7502, 5, 5829},
- {"cvmx_sriomaint#_lane_#_status_0", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7504, 15, 5834},
- {"cvmx_sriomaint#_lcs_ba0" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7512, 2, 5849},
- {"cvmx_sriomaint#_lcs_ba1" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7514, 2, 5851},
- {"cvmx_sriomaint#_m2s_bar0_start0", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7516, 2, 5853},
- {"cvmx_sriomaint#_m2s_bar0_start1", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7518, 4, 5855},
- {"cvmx_sriomaint#_m2s_bar1_start0", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7520, 2, 5859},
- {"cvmx_sriomaint#_m2s_bar1_start1", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7522, 5, 5861},
- {"cvmx_sriomaint#_m2s_bar2_start", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7524, 7, 5866},
- {"cvmx_sriomaint#_pe_feat" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7526, 11, 5873},
- {"cvmx_sriomaint#_pe_llc" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7528, 2, 5884},
- {"cvmx_sriomaint#_port_0_ctl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7530, 18, 5886},
- {"cvmx_sriomaint#_port_0_ctl2" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7532, 16, 5904},
- {"cvmx_sriomaint#_port_0_err_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7534, 20, 5920},
- {"cvmx_sriomaint#_port_gen_ctl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7536, 4, 5940},
- {"cvmx_sriomaint#_port_lt_ctl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7538, 2, 5944},
- {"cvmx_sriomaint#_port_mbh0" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7540, 2, 5946},
- {"cvmx_sriomaint#_port_rt_ctl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7542, 2, 5948},
- {"cvmx_sriomaint#_pri_dev_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7544, 3, 5950},
- {"cvmx_sriomaint#_sec_dev_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7546, 3, 5953},
- {"cvmx_sriomaint#_sec_dev_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7548, 3, 5956},
- {"cvmx_sriomaint#_serial_lane_hdr", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7550, 2, 5959},
- {"cvmx_sriomaint#_src_ops" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7552, 26, 5961},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 7554, 6, 5987},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 7555, 3, 5993},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 7556, 5, 5996},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 7557, 4, 6001},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 7558, 6, 6005},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 7559, 4, 6011},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 7560, 2, 6015},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 7561, 4, 6017},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 7562, 2, 6021},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 7563, 3, 6023},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7564, 2, 6026},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7565, 13, 6028},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 7566, 3, 6041},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 7567, 5, 6044},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7568, 2, 6049},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7569, 2, 6051},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7570, 57, 6053},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7571, 20, 6110},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7572, 7, 6130},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7573, 5, 6137},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7574, 1, 6142},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7575, 2, 6143},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7576, 2, 6145},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7577, 57, 6147},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7578, 20, 6204},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7579, 7, 6224},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7580, 2, 6231},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7581, 2, 6233},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7582, 57, 6235},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7583, 20, 6292},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7584, 7, 6312},
- {"cvmx_uahc#_ehci_asynclistaddr", CVMX_CSR_DB_TYPE_NCB, 32, 7585, 2, 6319},
- {"cvmx_uahc#_ehci_configflag" , CVMX_CSR_DB_TYPE_NCB, 32, 7586, 2, 6321},
- {"cvmx_uahc#_ehci_ctrldssegment", CVMX_CSR_DB_TYPE_NCB, 32, 7587, 1, 6323},
- {"cvmx_uahc#_ehci_frindex" , CVMX_CSR_DB_TYPE_NCB, 32, 7588, 2, 6324},
- {"cvmx_uahc#_ehci_hccapbase" , CVMX_CSR_DB_TYPE_NCB, 32, 7589, 3, 6326},
- {"cvmx_uahc#_ehci_hccparams" , CVMX_CSR_DB_TYPE_NCB, 32, 7590, 7, 6329},
- {"cvmx_uahc#_ehci_hcsparams" , CVMX_CSR_DB_TYPE_NCB, 32, 7591, 10, 6336},
- {"cvmx_uahc#_ehci_insnreg00" , CVMX_CSR_DB_TYPE_NCB, 32, 7592, 3, 6346},
- {"cvmx_uahc#_ehci_insnreg03" , CVMX_CSR_DB_TYPE_NCB, 32, 7593, 5, 6349},
- {"cvmx_uahc#_ehci_insnreg04" , CVMX_CSR_DB_TYPE_NCB, 32, 7594, 7, 6354},
- {"cvmx_uahc#_ehci_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 7595, 2, 6361},
- {"cvmx_uahc#_ehci_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 7596, 1, 6363},
- {"cvmx_uahc#_ehci_periodiclistbase", CVMX_CSR_DB_TYPE_NCB, 32, 7597, 2, 6364},
- {"cvmx_uahc#_ehci_portsc#" , CVMX_CSR_DB_TYPE_NCB, 32, 7598, 19, 6366},
- {"cvmx_uahc#_ehci_usbcmd" , CVMX_CSR_DB_TYPE_NCB, 32, 7600, 13, 6385},
- {"cvmx_uahc#_ehci_usbintr" , CVMX_CSR_DB_TYPE_NCB, 32, 7601, 7, 6398},
- {"cvmx_uahc#_ehci_usbsts" , CVMX_CSR_DB_TYPE_NCB, 32, 7602, 12, 6405},
- {"cvmx_uahc#_ohci0_hcbulkcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7603, 2, 6417},
- {"cvmx_uahc#_ohci0_hcbulkheaded", CVMX_CSR_DB_TYPE_NCB, 32, 7604, 2, 6419},
- {"cvmx_uahc#_ohci0_hccommandstatus", CVMX_CSR_DB_TYPE_NCB, 32, 7605, 7, 6421},
- {"cvmx_uahc#_ohci0_hccontrol" , CVMX_CSR_DB_TYPE_NCB, 32, 7606, 10, 6428},
- {"cvmx_uahc#_ohci0_hccontrolcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7607, 2, 6438},
- {"cvmx_uahc#_ohci0_hccontrolheaded", CVMX_CSR_DB_TYPE_NCB, 32, 7608, 2, 6440},
- {"cvmx_uahc#_ohci0_hcdonehead" , CVMX_CSR_DB_TYPE_NCB, 32, 7609, 2, 6442},
- {"cvmx_uahc#_ohci0_hcfminterval", CVMX_CSR_DB_TYPE_NCB, 32, 7610, 4, 6444},
- {"cvmx_uahc#_ohci0_hcfmnumber" , CVMX_CSR_DB_TYPE_NCB, 32, 7611, 2, 6448},
- {"cvmx_uahc#_ohci0_hcfmremaining", CVMX_CSR_DB_TYPE_NCB, 32, 7612, 3, 6450},
- {"cvmx_uahc#_ohci0_hchcca" , CVMX_CSR_DB_TYPE_NCB, 32, 7613, 2, 6453},
- {"cvmx_uahc#_ohci0_hcinterruptdisable", CVMX_CSR_DB_TYPE_NCB, 32, 7614, 10, 6455},
- {"cvmx_uahc#_ohci0_hcinterruptenable", CVMX_CSR_DB_TYPE_NCB, 32, 7615, 10, 6465},
- {"cvmx_uahc#_ohci0_hcinterruptstatus", CVMX_CSR_DB_TYPE_NCB, 32, 7616, 10, 6475},
- {"cvmx_uahc#_ohci0_hclsthreshold", CVMX_CSR_DB_TYPE_NCB, 32, 7617, 2, 6485},
- {"cvmx_uahc#_ohci0_hcperiodcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7618, 2, 6487},
- {"cvmx_uahc#_ohci0_hcperiodicstart", CVMX_CSR_DB_TYPE_NCB, 32, 7619, 2, 6489},
- {"cvmx_uahc#_ohci0_hcrevision" , CVMX_CSR_DB_TYPE_NCB, 32, 7620, 2, 6491},
- {"cvmx_uahc#_ohci0_hcrhdescriptora", CVMX_CSR_DB_TYPE_NCB, 32, 7621, 8, 6493},
- {"cvmx_uahc#_ohci0_hcrhdescriptorb", CVMX_CSR_DB_TYPE_NCB, 32, 7622, 2, 6501},
- {"cvmx_uahc#_ohci0_hcrhportstatus#", CVMX_CSR_DB_TYPE_NCB, 32, 7623, 15, 6503},
- {"cvmx_uahc#_ohci0_hcrhstatus" , CVMX_CSR_DB_TYPE_NCB, 32, 7625, 8, 6518},
- {"cvmx_uahc#_ohci0_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 7626, 2, 6526},
- {"cvmx_uahc#_ohci0_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 7627, 1, 6528},
- {"cvmx_uctl#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7628, 7, 6529},
- {"cvmx_uctl#_clk_rst_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7629, 21, 6536},
- {"cvmx_uctl#_ehci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7630, 12, 6557},
- {"cvmx_uctl#_ehci_fla" , CVMX_CSR_DB_TYPE_RSL, 64, 7631, 2, 6569},
- {"cvmx_uctl#_erto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7632, 3, 6571},
- {"cvmx_uctl#_if_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 7633, 2, 6574},
- {"cvmx_uctl#_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 7634, 9, 6576},
- {"cvmx_uctl#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7635, 9, 6585},
- {"cvmx_uctl#_ohci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7636, 11, 6594},
- {"cvmx_uctl#_orto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7637, 3, 6605},
- {"cvmx_uctl#_ppaf_wm" , CVMX_CSR_DB_TYPE_RSL, 64, 7638, 2, 6608},
- {"cvmx_uctl#_uphy_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7639, 11, 6610},
- {"cvmx_uctl#_uphy_port#_ctl_status", CVMX_CSR_DB_TYPE_RSL, 64, 7640, 20, 6621},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 7642, 3, 6641},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 7643, 5, 6644},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7644, 3, 6649},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 7645, 6, 6652},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 7646, 2, 6658},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 7647, 2, 6660},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 7648, 2, 6662},
- {"cvmx_zip_throttle" , CVMX_CSR_DB_TYPE_RSL, 64, 7649, 2, 6664},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn63xxp1[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"AGL_GMX_BAD_REG" , 0x11800e0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"AGL_GMX_BIST" , 0x11800e0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"AGL_GMX_PRT0_CFG" , 0x11800e0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_PRT1_CFG" , 0x11800e0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_RX0_ADR_CAM0" , 0x11800e0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_RX1_ADR_CAM0" , 0x11800e0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_RX0_ADR_CAM1" , 0x11800e0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX1_ADR_CAM1" , 0x11800e0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX0_ADR_CAM2" , 0x11800e0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX1_ADR_CAM2" , 0x11800e0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX0_ADR_CAM3" , 0x11800e0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX1_ADR_CAM3" , 0x11800e0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX0_ADR_CAM4" , 0x11800e00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX1_ADR_CAM4" , 0x11800e00009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX0_ADR_CAM5" , 0x11800e00001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX1_ADR_CAM5" , 0x11800e00009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800e0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX1_ADR_CAM_EN" , 0x11800e0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX0_ADR_CTL" , 0x11800e0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX1_ADR_CTL" , 0x11800e0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX0_DECISION" , 0x11800e0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX1_DECISION" , 0x11800e0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX0_FRM_CHK" , 0x11800e0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX1_FRM_CHK" , 0x11800e0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX0_FRM_CTL" , 0x11800e0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX1_FRM_CTL" , 0x11800e0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX0_FRM_MAX" , 0x11800e0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX1_FRM_MAX" , 0x11800e0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX0_FRM_MIN" , 0x11800e0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX1_FRM_MIN" , 0x11800e0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX0_IFG" , 0x11800e0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX1_IFG" , 0x11800e0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX0_INT_EN" , 0x11800e0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX1_INT_EN" , 0x11800e0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX0_INT_REG" , 0x11800e0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX1_INT_REG" , 0x11800e0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX0_JABBER" , 0x11800e0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX1_JABBER" , 0x11800e0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800e0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX1_PAUSE_DROP_TIME" , 0x11800e0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX0_RX_INBND" , 0x11800e0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX1_RX_INBND" , 0x11800e0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX0_STATS_CTL" , 0x11800e0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX1_STATS_CTL" , 0x11800e0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX0_STATS_OCTS" , 0x11800e0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX1_STATS_OCTS" , 0x11800e0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800e0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX1_STATS_OCTS_CTL" , 0x11800e0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800e00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX1_STATS_OCTS_DMAC" , 0x11800e00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800e00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX1_STATS_OCTS_DRP" , 0x11800e00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX0_STATS_PKTS" , 0x11800e0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX1_STATS_PKTS" , 0x11800e0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800e00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX1_STATS_PKTS_BAD" , 0x11800e00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800e0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX1_STATS_PKTS_CTL" , 0x11800e0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800e00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX1_STATS_PKTS_DMAC" , 0x11800e00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800e00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX1_STATS_PKTS_DRP" , 0x11800e00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX0_UDD_SKP" , 0x11800e0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX1_UDD_SKP" , 0x11800e0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX_BP_DROP0" , 0x11800e0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_DROP1" , 0x11800e0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_OFF0" , 0x11800e0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_OFF1" , 0x11800e0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_ON0" , 0x11800e0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_BP_ON1" , 0x11800e0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_PRT_INFO" , 0x11800e00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_TX_STATUS" , 0x11800e00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"AGL_GMX_SMAC0" , 0x11800e0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_SMAC1" , 0x11800e0000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_STAT_BP" , 0x11800e0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_TX0_APPEND" , 0x11800e0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX1_APPEND" , 0x11800e0000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX0_CLK" , 0x11800e0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX1_CLK" , 0x11800e0000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX0_CTL" , 0x11800e0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX1_CTL" , 0x11800e0000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX0_MIN_PKT" , 0x11800e0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX1_MIN_PKT" , 0x11800e0000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800e0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX1_PAUSE_PKT_INTERVAL", 0x11800e0000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800e0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX1_PAUSE_PKT_TIME" , 0x11800e0000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800e0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX1_PAUSE_TOGO" , 0x11800e0000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800e0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX1_PAUSE_ZERO" , 0x11800e0000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800e0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX1_SOFT_PAUSE" , 0x11800e0000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX0_STAT0" , 0x11800e0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX1_STAT0" , 0x11800e0000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX0_STAT1" , 0x11800e0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX1_STAT1" , 0x11800e0000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX0_STAT2" , 0x11800e0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX1_STAT2" , 0x11800e0000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX0_STAT3" , 0x11800e0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX1_STAT3" , 0x11800e0000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX0_STAT4" , 0x11800e00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX1_STAT4" , 0x11800e0000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX0_STAT5" , 0x11800e00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX1_STAT5" , 0x11800e0000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX0_STAT6" , 0x11800e00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX1_STAT6" , 0x11800e0000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX0_STAT7" , 0x11800e00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX1_STAT7" , 0x11800e0000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX0_STAT8" , 0x11800e00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX1_STAT8" , 0x11800e0000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX0_STAT9" , 0x11800e00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX1_STAT9" , 0x11800e0000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX0_STATS_CTL" , 0x11800e0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX1_STATS_CTL" , 0x11800e0000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX0_THRESH" , 0x11800e0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX1_THRESH" , 0x11800e0000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX_BP" , 0x11800e00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"AGL_GMX_TX_COL_ATTEMPT" , 0x11800e0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"AGL_GMX_TX_IFG" , 0x11800e0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"AGL_GMX_TX_INT_EN" , 0x11800e0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"AGL_GMX_TX_INT_REG" , 0x11800e0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"AGL_GMX_TX_JAM" , 0x11800e0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"AGL_GMX_TX_LFSR" , 0x11800e00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"AGL_GMX_TX_OVR_BP" , 0x11800e00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800e00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800e00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"AGL_PRT0_CTL" , 0x11800e0002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"AGL_PRT1_CTL" , 0x11800e0002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU_BLOCK_INT" , 0x10700000007c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT10_EN0" , 0x10700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT11_EN0" , 0x10700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT33_EN0" , 0x1070000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT8_EN0_W1C" , 0x1070000002280ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT9_EN0_W1C" , 0x1070000002290ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT10_EN0_W1C" , 0x10700000022a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT11_EN0_W1C" , 0x10700000022b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT33_EN0_W1C" , 0x1070000002410ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT8_EN0_W1S" , 0x1070000006280ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT9_EN0_W1S" , 0x1070000006290ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT10_EN0_W1S" , 0x10700000062a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT11_EN0_W1S" , 0x10700000062b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT33_EN0_W1S" , 0x1070000006410ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT10_EN1" , 0x10700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT11_EN1" , 0x10700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT33_EN1" , 0x1070000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT8_EN1_W1C" , 0x1070000002288ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT9_EN1_W1C" , 0x1070000002298ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT10_EN1_W1C" , 0x10700000022a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT11_EN1_W1C" , 0x10700000022b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT33_EN1_W1C" , 0x1070000002418ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT8_EN1_W1S" , 0x1070000006288ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT9_EN1_W1S" , 0x1070000006298ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT10_EN1_W1S" , 0x10700000062a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT11_EN1_W1S" , 0x10700000062b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT33_EN1_W1S" , 0x1070000006418ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT4_EN4_0" , 0x1070000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT5_EN4_0" , 0x1070000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT0_EN4_0_W1C" , 0x1070000002c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT1_EN4_0_W1C" , 0x1070000002c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT2_EN4_0_W1C" , 0x1070000002ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT3_EN4_0_W1C" , 0x1070000002cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT4_EN4_0_W1C" , 0x1070000002cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT5_EN4_0_W1C" , 0x1070000002cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT0_EN4_0_W1S" , 0x1070000006c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT1_EN4_0_W1S" , 0x1070000006c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT2_EN4_0_W1S" , 0x1070000006ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT3_EN4_0_W1S" , 0x1070000006cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT4_EN4_0_W1S" , 0x1070000006cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT5_EN4_0_W1S" , 0x1070000006cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT4_EN4_1" , 0x1070000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT5_EN4_1" , 0x1070000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT0_EN4_1_W1C" , 0x1070000002c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT1_EN4_1_W1C" , 0x1070000002c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT2_EN4_1_W1C" , 0x1070000002ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT3_EN4_1_W1C" , 0x1070000002cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT4_EN4_1_W1C" , 0x1070000002cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT5_EN4_1_W1C" , 0x1070000002cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT0_EN4_1_W1S" , 0x1070000006c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT1_EN4_1_W1S" , 0x1070000006c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT2_EN4_1_W1S" , 0x1070000006ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT3_EN4_1_W1S" , 0x1070000006cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT4_EN4_1_W1S" , 0x1070000006cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT5_EN4_1_W1S" , 0x1070000006cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT4_SUM4" , 0x1070000000c20ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT5_SUM4" , 0x1070000000c28ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT33_SUM0" , 0x1070000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_MBOX_CLR4" , 0x10700000006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_MBOX_CLR5" , 0x10700000006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_PP_POKE4" , 0x10700000005a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_PP_POKE5" , 0x10700000005a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_QLM0" , 0x1070000000780ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_QLM1" , 0x1070000000788ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_QLM2" , 0x1070000000790ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"DFA_BIST0" , 0x11800370007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
- {"DFA_BIST1" , 0x11800370007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"DFA_CONFIG" , 0x1180037000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"DFA_CONTROL" , 0x1180037000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"DFA_DEBUG0" , 0x1180037000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
- {"DFA_DEBUG1" , 0x1180037000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"DFA_DEBUG2" , 0x1180037000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"DFA_DEBUG3" , 0x1180037000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"DFA_DTCFADR" , 0x1180037000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
- {"DFA_ERROR" , 0x1180037000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"DFA_INTMSK" , 0x1180037000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"DFA_MEMHIDAT" , 0x1370700000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"DFA_PFC0_CNT" , 0x1180037000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
- {"DFA_PFC0_CTL" , 0x1180037000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"DFA_PFC1_CNT" , 0x11800370000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"DFA_PFC1_CTL" , 0x1180037000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"DFA_PFC2_CNT" , 0x11800370000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"DFA_PFC2_CTL" , 0x11800370000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"DFA_PFC3_CNT" , 0x11800370000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"DFA_PFC3_CTL" , 0x11800370000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"DFA_PFC_GCTL" , 0x1180037000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"DFM_CHAR_CTL" , 0x11800d4000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"DFM_CHAR_MASK0" , 0x11800d4000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"DFM_CHAR_MASK2" , 0x11800d4000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"DFM_COMP_CTL2" , 0x11800d40001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"DFM_CONFIG" , 0x11800d4000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"DFM_CONTROL" , 0x11800d4000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"DFM_DLL_CTL2" , 0x11800d40001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"DFM_DLL_CTL3" , 0x11800d4000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"DFM_FCLK_CNT" , 0x11800d40001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"DFM_FNT_BIST" , 0x11800d40007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"DFM_FNT_CTL" , 0x11800d4000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"DFM_FNT_IENA" , 0x11800d4000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"DFM_FNT_SCLK" , 0x11800d4000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"DFM_FNT_STAT" , 0x11800d4000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"DFM_IFB_CNT" , 0x11800d40001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"DFM_MODEREG_PARAMS0" , 0x11800d40001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"DFM_MODEREG_PARAMS1" , 0x11800d4000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"DFM_OPS_CNT" , 0x11800d40001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"DFM_PHY_CTL" , 0x11800d4000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"DFM_RESET_CTL" , 0x11800d4000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"DFM_RLEVEL_CTL" , 0x11800d40002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"DFM_RLEVEL_DBG" , 0x11800d40002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"DFM_RLEVEL_RANK0" , 0x11800d4000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"DFM_RLEVEL_RANK1" , 0x11800d4000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"DFM_RODT_MASK" , 0x11800d4000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"DFM_SLOT_CTL0" , 0x11800d40001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"DFM_SLOT_CTL1" , 0x11800d4000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"DFM_TIMING_PARAMS0" , 0x11800d4000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"DFM_TIMING_PARAMS1" , 0x11800d40001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"DFM_WLEVEL_CTL" , 0x11800d4000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"DFM_WLEVEL_DBG" , 0x11800d4000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"DFM_WLEVEL_RANK0" , 0x11800d40002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"DFM_WLEVEL_RANK1" , 0x11800d40002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"DFM_WODT_MASK" , 0x11800d40001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"DPI_BIST_STATUS" , 0x1df0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"DPI_CTL" , 0x1df0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"DPI_DMA0_COUNTS" , 0x1df0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA1_COUNTS" , 0x1df0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA2_COUNTS" , 0x1df0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA3_COUNTS" , 0x1df0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA4_COUNTS" , 0x1df0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA5_COUNTS" , 0x1df0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA6_COUNTS" , 0x1df0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA7_COUNTS" , 0x1df0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_DMA0_DBELL" , 0x1df0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_DMA1_DBELL" , 0x1df0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_DMA2_DBELL" , 0x1df0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_DMA3_DBELL" , 0x1df0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_DMA4_DBELL" , 0x1df0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_DMA5_DBELL" , 0x1df0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_DMA6_DBELL" , 0x1df0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_DMA7_DBELL" , 0x1df0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_DMA0_IBUFF_SADDR" , 0x1df0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA1_IBUFF_SADDR" , 0x1df0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA2_IBUFF_SADDR" , 0x1df0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA3_IBUFF_SADDR" , 0x1df0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA4_IBUFF_SADDR" , 0x1df00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA5_IBUFF_SADDR" , 0x1df00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA6_IBUFF_SADDR" , 0x1df00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA7_IBUFF_SADDR" , 0x1df00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA0_NADDR" , 0x1df0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA1_NADDR" , 0x1df0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA2_NADDR" , 0x1df0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA3_NADDR" , 0x1df0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA4_NADDR" , 0x1df00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA5_NADDR" , 0x1df00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA6_NADDR" , 0x1df00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA7_NADDR" , 0x1df00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA0_REQBNK0" , 0x1df0000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA1_REQBNK0" , 0x1df0000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA2_REQBNK0" , 0x1df0000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA3_REQBNK0" , 0x1df0000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA4_REQBNK0" , 0x1df0000000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA5_REQBNK0" , 0x1df0000000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA6_REQBNK0" , 0x1df0000000430ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA7_REQBNK0" , 0x1df0000000438ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA0_REQBNK1" , 0x1df0000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA1_REQBNK1" , 0x1df0000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA2_REQBNK1" , 0x1df0000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA3_REQBNK1" , 0x1df0000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA4_REQBNK1" , 0x1df00000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA5_REQBNK1" , 0x1df00000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA6_REQBNK1" , 0x1df00000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA7_REQBNK1" , 0x1df00000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA_CONTROL" , 0x1df0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"DPI_DMA_ENG0_EN" , 0x1df0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA_ENG1_EN" , 0x1df0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA_ENG2_EN" , 0x1df0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA_ENG3_EN" , 0x1df0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA_ENG4_EN" , 0x1df00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA_ENG5_EN" , 0x1df00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_ENG0_BUF" , 0x1df0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"DPI_ENG1_BUF" , 0x1df0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"DPI_ENG2_BUF" , 0x1df0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"DPI_ENG3_BUF" , 0x1df0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"DPI_ENG4_BUF" , 0x1df00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"DPI_ENG5_BUF" , 0x1df00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"DPI_INFO_REG" , 0x1df0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"DPI_INT_EN" , 0x1df0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"DPI_INT_REG" , 0x1df0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"DPI_PINT_INFO" , 0x1df0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"DPI_PKT_ERR_RSP" , 0x1df0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"DPI_REQ_ERR_RSP" , 0x1df0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"DPI_REQ_ERR_RSP_EN" , 0x1df0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"DPI_REQ_ERR_RST" , 0x1df0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
- {"DPI_REQ_ERR_RST_EN" , 0x1df0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 186},
- {"DPI_REQ_GBL_EN" , 0x1df0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
- {"DPI_SLI_PRT0_CFG" , 0x1df0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"DPI_SLI_PRT1_CFG" , 0x1df0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"DPI_SLI_PRT0_ERR" , 0x1df0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"DPI_SLI_PRT1_ERR" , 0x1df0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"DPI_SLI_PRT0_ERR_INFO" , 0x1df0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"DPI_SLI_PRT1_ERR_INFO" , 0x1df0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX0_SOFT_BIST" , 0x11800080007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX0_TX000_CBFC_XOFF" , 0x11800080005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_TX000_CBFC_XON" , 0x11800080005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX003_SGMII_CTL" , 0x1180008001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
- {"GPIO_CLK_QLM0" , 0x10700000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_CLK_QLM1" , 0x10700000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 294},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"IOB_TO_CMB_CREDITS" , 0x11800f00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 325},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"IPD_PORT36_BP_PAGE_CNT2" , 0x14f0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"IPD_PORT37_BP_PAGE_CNT2" , 0x14f0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"IPD_PORT38_BP_PAGE_CNT2" , 0x14f0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"IPD_PORT39_BP_PAGE_CNT2" , 0x14f0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"IPD_PORT40_BP_PAGE_CNT3" , 0x14f00000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"IPD_PORT41_BP_PAGE_CNT3" , 0x14f00000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"IPD_PORT42_BP_PAGE_CNT3" , 0x14f00000003e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"IPD_PORT43_BP_PAGE_CNT3" , 0x14f00000003e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14f0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14f0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14f0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14f00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"IPD_PORT_BP_COUNTERS3_PAIR40", 0x14f00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT_BP_COUNTERS3_PAIR41", 0x14f00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT_BP_COUNTERS3_PAIR42", 0x14f00000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT_BP_COUNTERS3_PAIR43", 0x14f00000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_256_CNT" , 0x14f0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_257_CNT" , 0x14f0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_258_CNT" , 0x14f0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_259_CNT" , 0x14f00000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_260_CNT" , 0x14f00000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_261_CNT" , 0x14f00000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_262_CNT" , 0x14f00000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_263_CNT" , 0x14f00000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_264_CNT" , 0x14f00000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_265_CNT" , 0x14f00000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_266_CNT" , 0x14f00000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_267_CNT" , 0x14f00000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_268_CNT" , 0x14f00000010e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_269_CNT" , 0x14f00000010f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_270_CNT" , 0x14f00000010f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_271_CNT" , 0x14f0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_272_CNT" , 0x14f0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_273_CNT" , 0x14f0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_274_CNT" , 0x14f0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_275_CNT" , 0x14f0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_276_CNT" , 0x14f0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_277_CNT" , 0x14f0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_278_CNT" , 0x14f0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_279_CNT" , 0x14f0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_280_CNT" , 0x14f0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_281_CNT" , 0x14f0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_282_CNT" , 0x14f0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_283_CNT" , 0x14f0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_284_CNT" , 0x14f0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_285_CNT" , 0x14f0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_286_CNT" , 0x14f0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_287_CNT" , 0x14f0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_320_CNT" , 0x14f0000001288ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_321_CNT" , 0x14f0000001290ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_322_CNT" , 0x14f0000001298ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_323_CNT" , 0x14f00000012a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_324_CNT" , 0x14f00000012a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_325_CNT" , 0x14f00000012b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_326_CNT" , 0x14f00000012b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_327_CNT" , 0x14f00000012c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_328_CNT" , 0x14f00000012c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_329_CNT" , 0x14f00000012d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_330_CNT" , 0x14f00000012d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_331_CNT" , 0x14f00000012e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_332_CNT" , 0x14f00000012e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_333_CNT" , 0x14f00000012f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_334_CNT" , 0x14f00000012f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_335_CNT" , 0x14f0000001300ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_336_CNT" , 0x14f0000001308ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_337_CNT" , 0x14f0000001310ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_338_CNT" , 0x14f0000001318ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_339_CNT" , 0x14f0000001320ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_340_CNT" , 0x14f0000001328ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_341_CNT" , 0x14f0000001330ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_342_CNT" , 0x14f0000001338ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_343_CNT" , 0x14f0000001340ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_344_CNT" , 0x14f0000001348ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_345_CNT" , 0x14f0000001350ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_346_CNT" , 0x14f0000001358ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_347_CNT" , 0x14f0000001360ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_348_CNT" , 0x14f0000001368ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_349_CNT" , 0x14f0000001370ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_350_CNT" , 0x14f0000001378ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_351_CNT" , 0x14f0000001380ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT_QOS_INT5" , 0x14f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PORT_QOS_INT_ENB5" , 0x14f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
- {"IPD_RED_PORT_ENABLE2" , 0x14f00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 353},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"L2C_BST" , 0x11800808007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"L2C_BST_MEM0" , 0x1180080c007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"L2C_BST_TDT0" , 0x1180080a007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"L2C_BST_TTG0" , 0x1180080a007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"L2C_COP0_MAP0" , 0x1180080940000ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1" , 0x1180080940008ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP2" , 0x1180080940010ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP3" , 0x1180080940018ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP4" , 0x1180080940020ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP5" , 0x1180080940028ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP6" , 0x1180080940030ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP7" , 0x1180080940038ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP8" , 0x1180080940040ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP9" , 0x1180080940048ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP10" , 0x1180080940050ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP11" , 0x1180080940058ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP12" , 0x1180080940060ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP13" , 0x1180080940068ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP14" , 0x1180080940070ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP15" , 0x1180080940078ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16" , 0x1180080940080ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP17" , 0x1180080940088ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP18" , 0x1180080940090ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP19" , 0x1180080940098ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP20" , 0x11800809400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP21" , 0x11800809400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP22" , 0x11800809400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP23" , 0x11800809400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP24" , 0x11800809400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP25" , 0x11800809400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP26" , 0x11800809400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP27" , 0x11800809400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP28" , 0x11800809400e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP29" , 0x11800809400e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP30" , 0x11800809400f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP31" , 0x11800809400f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP32" , 0x1180080940100ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP33" , 0x1180080940108ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP34" , 0x1180080940110ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP35" , 0x1180080940118ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP36" , 0x1180080940120ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP37" , 0x1180080940128ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP38" , 0x1180080940130ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP39" , 0x1180080940138ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP40" , 0x1180080940140ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP41" , 0x1180080940148ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP42" , 0x1180080940150ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP43" , 0x1180080940158ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP44" , 0x1180080940160ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP45" , 0x1180080940168ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP46" , 0x1180080940170ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP47" , 0x1180080940178ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP48" , 0x1180080940180ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP49" , 0x1180080940188ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP50" , 0x1180080940190ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP51" , 0x1180080940198ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP52" , 0x11800809401a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP53" , 0x11800809401a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP54" , 0x11800809401b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP55" , 0x11800809401b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP56" , 0x11800809401c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP57" , 0x11800809401c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP58" , 0x11800809401d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP59" , 0x11800809401d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP60" , 0x11800809401e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP61" , 0x11800809401e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP62" , 0x11800809401f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP63" , 0x11800809401f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP64" , 0x1180080940200ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP65" , 0x1180080940208ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP66" , 0x1180080940210ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP67" , 0x1180080940218ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP68" , 0x1180080940220ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP69" , 0x1180080940228ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP70" , 0x1180080940230ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP71" , 0x1180080940238ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP72" , 0x1180080940240ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP73" , 0x1180080940248ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP74" , 0x1180080940250ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP75" , 0x1180080940258ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP76" , 0x1180080940260ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP77" , 0x1180080940268ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP78" , 0x1180080940270ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP79" , 0x1180080940278ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP80" , 0x1180080940280ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP81" , 0x1180080940288ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP82" , 0x1180080940290ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP83" , 0x1180080940298ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP84" , 0x11800809402a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP85" , 0x11800809402a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP86" , 0x11800809402b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP87" , 0x11800809402b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP88" , 0x11800809402c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP89" , 0x11800809402c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP90" , 0x11800809402d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP91" , 0x11800809402d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP92" , 0x11800809402e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP93" , 0x11800809402e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP94" , 0x11800809402f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP95" , 0x11800809402f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP96" , 0x1180080940300ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP97" , 0x1180080940308ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP98" , 0x1180080940310ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP99" , 0x1180080940318ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP100" , 0x1180080940320ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP101" , 0x1180080940328ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP102" , 0x1180080940330ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP103" , 0x1180080940338ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP104" , 0x1180080940340ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP105" , 0x1180080940348ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP106" , 0x1180080940350ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP107" , 0x1180080940358ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP108" , 0x1180080940360ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP109" , 0x1180080940368ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP110" , 0x1180080940370ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP111" , 0x1180080940378ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP112" , 0x1180080940380ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP113" , 0x1180080940388ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP114" , 0x1180080940390ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP115" , 0x1180080940398ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP116" , 0x11800809403a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP117" , 0x11800809403a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP118" , 0x11800809403b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP119" , 0x11800809403b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP120" , 0x11800809403c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP121" , 0x11800809403c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP122" , 0x11800809403d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP123" , 0x11800809403d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP124" , 0x11800809403e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP125" , 0x11800809403e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP126" , 0x11800809403f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP127" , 0x11800809403f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP128" , 0x1180080940400ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP129" , 0x1180080940408ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP130" , 0x1180080940410ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP131" , 0x1180080940418ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP132" , 0x1180080940420ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP133" , 0x1180080940428ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP134" , 0x1180080940430ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP135" , 0x1180080940438ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP136" , 0x1180080940440ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP137" , 0x1180080940448ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP138" , 0x1180080940450ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP139" , 0x1180080940458ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP140" , 0x1180080940460ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP141" , 0x1180080940468ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP142" , 0x1180080940470ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP143" , 0x1180080940478ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP144" , 0x1180080940480ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP145" , 0x1180080940488ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP146" , 0x1180080940490ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP147" , 0x1180080940498ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP148" , 0x11800809404a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP149" , 0x11800809404a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP150" , 0x11800809404b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP151" , 0x11800809404b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP152" , 0x11800809404c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP153" , 0x11800809404c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP154" , 0x11800809404d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP155" , 0x11800809404d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP156" , 0x11800809404e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP157" , 0x11800809404e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP158" , 0x11800809404f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP159" , 0x11800809404f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP160" , 0x1180080940500ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP161" , 0x1180080940508ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP162" , 0x1180080940510ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP163" , 0x1180080940518ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP164" , 0x1180080940520ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP165" , 0x1180080940528ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP166" , 0x1180080940530ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP167" , 0x1180080940538ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP168" , 0x1180080940540ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP169" , 0x1180080940548ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP170" , 0x1180080940550ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP171" , 0x1180080940558ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP172" , 0x1180080940560ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP173" , 0x1180080940568ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP174" , 0x1180080940570ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP175" , 0x1180080940578ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP176" , 0x1180080940580ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP177" , 0x1180080940588ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP178" , 0x1180080940590ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP179" , 0x1180080940598ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP180" , 0x11800809405a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP181" , 0x11800809405a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP182" , 0x11800809405b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP183" , 0x11800809405b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP184" , 0x11800809405c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP185" , 0x11800809405c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP186" , 0x11800809405d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP187" , 0x11800809405d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP188" , 0x11800809405e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP189" , 0x11800809405e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP190" , 0x11800809405f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP191" , 0x11800809405f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP192" , 0x1180080940600ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP193" , 0x1180080940608ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP194" , 0x1180080940610ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP195" , 0x1180080940618ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP196" , 0x1180080940620ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP197" , 0x1180080940628ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP198" , 0x1180080940630ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP199" , 0x1180080940638ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP200" , 0x1180080940640ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP201" , 0x1180080940648ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP202" , 0x1180080940650ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP203" , 0x1180080940658ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP204" , 0x1180080940660ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP205" , 0x1180080940668ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP206" , 0x1180080940670ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP207" , 0x1180080940678ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP208" , 0x1180080940680ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP209" , 0x1180080940688ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP210" , 0x1180080940690ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP211" , 0x1180080940698ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP212" , 0x11800809406a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP213" , 0x11800809406a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP214" , 0x11800809406b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP215" , 0x11800809406b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP216" , 0x11800809406c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP217" , 0x11800809406c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP218" , 0x11800809406d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP219" , 0x11800809406d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP220" , 0x11800809406e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP221" , 0x11800809406e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP222" , 0x11800809406f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP223" , 0x11800809406f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP224" , 0x1180080940700ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP225" , 0x1180080940708ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP226" , 0x1180080940710ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP227" , 0x1180080940718ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP228" , 0x1180080940720ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP229" , 0x1180080940728ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP230" , 0x1180080940730ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP231" , 0x1180080940738ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP232" , 0x1180080940740ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP233" , 0x1180080940748ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP234" , 0x1180080940750ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP235" , 0x1180080940758ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP236" , 0x1180080940760ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP237" , 0x1180080940768ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP238" , 0x1180080940770ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP239" , 0x1180080940778ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP240" , 0x1180080940780ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP241" , 0x1180080940788ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP242" , 0x1180080940790ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP243" , 0x1180080940798ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP244" , 0x11800809407a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP245" , 0x11800809407a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP246" , 0x11800809407b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP247" , 0x11800809407b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP248" , 0x11800809407c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP249" , 0x11800809407c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP250" , 0x11800809407d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP251" , 0x11800809407d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP252" , 0x11800809407e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP253" , 0x11800809407e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP254" , 0x11800809407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP255" , 0x11800809407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP256" , 0x1180080940800ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP257" , 0x1180080940808ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP258" , 0x1180080940810ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP259" , 0x1180080940818ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP260" , 0x1180080940820ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP261" , 0x1180080940828ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP262" , 0x1180080940830ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP263" , 0x1180080940838ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP264" , 0x1180080940840ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP265" , 0x1180080940848ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP266" , 0x1180080940850ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP267" , 0x1180080940858ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP268" , 0x1180080940860ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP269" , 0x1180080940868ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP270" , 0x1180080940870ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP271" , 0x1180080940878ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP272" , 0x1180080940880ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP273" , 0x1180080940888ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP274" , 0x1180080940890ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP275" , 0x1180080940898ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP276" , 0x11800809408a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP277" , 0x11800809408a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP278" , 0x11800809408b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP279" , 0x11800809408b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP280" , 0x11800809408c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP281" , 0x11800809408c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP282" , 0x11800809408d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP283" , 0x11800809408d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP284" , 0x11800809408e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP285" , 0x11800809408e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP286" , 0x11800809408f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP287" , 0x11800809408f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP288" , 0x1180080940900ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP289" , 0x1180080940908ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP290" , 0x1180080940910ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP291" , 0x1180080940918ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP292" , 0x1180080940920ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP293" , 0x1180080940928ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP294" , 0x1180080940930ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP295" , 0x1180080940938ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP296" , 0x1180080940940ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP297" , 0x1180080940948ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP298" , 0x1180080940950ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP299" , 0x1180080940958ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP300" , 0x1180080940960ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP301" , 0x1180080940968ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP302" , 0x1180080940970ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP303" , 0x1180080940978ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP304" , 0x1180080940980ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP305" , 0x1180080940988ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP306" , 0x1180080940990ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP307" , 0x1180080940998ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP308" , 0x11800809409a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP309" , 0x11800809409a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP310" , 0x11800809409b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP311" , 0x11800809409b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP312" , 0x11800809409c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP313" , 0x11800809409c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP314" , 0x11800809409d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP315" , 0x11800809409d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP316" , 0x11800809409e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP317" , 0x11800809409e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP318" , 0x11800809409f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP319" , 0x11800809409f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP320" , 0x1180080940a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP321" , 0x1180080940a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP322" , 0x1180080940a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP323" , 0x1180080940a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP324" , 0x1180080940a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP325" , 0x1180080940a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP326" , 0x1180080940a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP327" , 0x1180080940a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP328" , 0x1180080940a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP329" , 0x1180080940a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP330" , 0x1180080940a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP331" , 0x1180080940a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP332" , 0x1180080940a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP333" , 0x1180080940a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP334" , 0x1180080940a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP335" , 0x1180080940a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP336" , 0x1180080940a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP337" , 0x1180080940a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP338" , 0x1180080940a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP339" , 0x1180080940a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP340" , 0x1180080940aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP341" , 0x1180080940aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP342" , 0x1180080940ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP343" , 0x1180080940ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP344" , 0x1180080940ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP345" , 0x1180080940ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP346" , 0x1180080940ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP347" , 0x1180080940ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP348" , 0x1180080940ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP349" , 0x1180080940ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP350" , 0x1180080940af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP351" , 0x1180080940af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP352" , 0x1180080940b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP353" , 0x1180080940b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP354" , 0x1180080940b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP355" , 0x1180080940b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP356" , 0x1180080940b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP357" , 0x1180080940b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP358" , 0x1180080940b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP359" , 0x1180080940b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP360" , 0x1180080940b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP361" , 0x1180080940b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP362" , 0x1180080940b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP363" , 0x1180080940b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP364" , 0x1180080940b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP365" , 0x1180080940b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP366" , 0x1180080940b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP367" , 0x1180080940b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP368" , 0x1180080940b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP369" , 0x1180080940b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP370" , 0x1180080940b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP371" , 0x1180080940b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP372" , 0x1180080940ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP373" , 0x1180080940ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP374" , 0x1180080940bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP375" , 0x1180080940bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP376" , 0x1180080940bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP377" , 0x1180080940bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP378" , 0x1180080940bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP379" , 0x1180080940bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP380" , 0x1180080940be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP381" , 0x1180080940be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP382" , 0x1180080940bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP383" , 0x1180080940bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP384" , 0x1180080940c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP385" , 0x1180080940c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP386" , 0x1180080940c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP387" , 0x1180080940c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP388" , 0x1180080940c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP389" , 0x1180080940c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP390" , 0x1180080940c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP391" , 0x1180080940c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP392" , 0x1180080940c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP393" , 0x1180080940c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP394" , 0x1180080940c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP395" , 0x1180080940c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP396" , 0x1180080940c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP397" , 0x1180080940c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP398" , 0x1180080940c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP399" , 0x1180080940c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP400" , 0x1180080940c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP401" , 0x1180080940c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP402" , 0x1180080940c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP403" , 0x1180080940c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP404" , 0x1180080940ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP405" , 0x1180080940ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP406" , 0x1180080940cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP407" , 0x1180080940cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP408" , 0x1180080940cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP409" , 0x1180080940cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP410" , 0x1180080940cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP411" , 0x1180080940cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP412" , 0x1180080940ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP413" , 0x1180080940ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP414" , 0x1180080940cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP415" , 0x1180080940cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP416" , 0x1180080940d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP417" , 0x1180080940d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP418" , 0x1180080940d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP419" , 0x1180080940d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP420" , 0x1180080940d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP421" , 0x1180080940d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP422" , 0x1180080940d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP423" , 0x1180080940d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP424" , 0x1180080940d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP425" , 0x1180080940d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP426" , 0x1180080940d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP427" , 0x1180080940d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP428" , 0x1180080940d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP429" , 0x1180080940d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP430" , 0x1180080940d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP431" , 0x1180080940d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP432" , 0x1180080940d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP433" , 0x1180080940d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP434" , 0x1180080940d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP435" , 0x1180080940d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP436" , 0x1180080940da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP437" , 0x1180080940da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP438" , 0x1180080940db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP439" , 0x1180080940db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP440" , 0x1180080940dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP441" , 0x1180080940dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP442" , 0x1180080940dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP443" , 0x1180080940dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP444" , 0x1180080940de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP445" , 0x1180080940de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP446" , 0x1180080940df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP447" , 0x1180080940df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP448" , 0x1180080940e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP449" , 0x1180080940e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP450" , 0x1180080940e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP451" , 0x1180080940e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP452" , 0x1180080940e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP453" , 0x1180080940e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP454" , 0x1180080940e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP455" , 0x1180080940e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP456" , 0x1180080940e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP457" , 0x1180080940e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP458" , 0x1180080940e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP459" , 0x1180080940e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP460" , 0x1180080940e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP461" , 0x1180080940e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP462" , 0x1180080940e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP463" , 0x1180080940e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP464" , 0x1180080940e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP465" , 0x1180080940e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP466" , 0x1180080940e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP467" , 0x1180080940e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP468" , 0x1180080940ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP469" , 0x1180080940ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP470" , 0x1180080940eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP471" , 0x1180080940eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP472" , 0x1180080940ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP473" , 0x1180080940ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP474" , 0x1180080940ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP475" , 0x1180080940ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP476" , 0x1180080940ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP477" , 0x1180080940ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP478" , 0x1180080940ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP479" , 0x1180080940ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP480" , 0x1180080940f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP481" , 0x1180080940f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP482" , 0x1180080940f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP483" , 0x1180080940f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP484" , 0x1180080940f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP485" , 0x1180080940f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP486" , 0x1180080940f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP487" , 0x1180080940f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP488" , 0x1180080940f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP489" , 0x1180080940f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP490" , 0x1180080940f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP491" , 0x1180080940f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP492" , 0x1180080940f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP493" , 0x1180080940f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP494" , 0x1180080940f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP495" , 0x1180080940f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP496" , 0x1180080940f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP497" , 0x1180080940f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP498" , 0x1180080940f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP499" , 0x1180080940f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP500" , 0x1180080940fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP501" , 0x1180080940fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP502" , 0x1180080940fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP503" , 0x1180080940fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP504" , 0x1180080940fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP505" , 0x1180080940fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP506" , 0x1180080940fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP507" , 0x1180080940fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP508" , 0x1180080940fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP509" , 0x1180080940fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP510" , 0x1180080940ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP511" , 0x1180080940ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP512" , 0x1180080941000ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP513" , 0x1180080941008ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP514" , 0x1180080941010ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP515" , 0x1180080941018ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP516" , 0x1180080941020ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP517" , 0x1180080941028ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP518" , 0x1180080941030ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP519" , 0x1180080941038ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP520" , 0x1180080941040ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP521" , 0x1180080941048ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP522" , 0x1180080941050ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP523" , 0x1180080941058ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP524" , 0x1180080941060ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP525" , 0x1180080941068ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP526" , 0x1180080941070ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP527" , 0x1180080941078ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP528" , 0x1180080941080ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP529" , 0x1180080941088ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP530" , 0x1180080941090ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP531" , 0x1180080941098ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP532" , 0x11800809410a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP533" , 0x11800809410a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP534" , 0x11800809410b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP535" , 0x11800809410b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP536" , 0x11800809410c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP537" , 0x11800809410c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP538" , 0x11800809410d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP539" , 0x11800809410d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP540" , 0x11800809410e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP541" , 0x11800809410e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP542" , 0x11800809410f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP543" , 0x11800809410f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP544" , 0x1180080941100ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP545" , 0x1180080941108ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP546" , 0x1180080941110ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP547" , 0x1180080941118ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP548" , 0x1180080941120ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP549" , 0x1180080941128ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP550" , 0x1180080941130ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP551" , 0x1180080941138ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP552" , 0x1180080941140ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP553" , 0x1180080941148ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP554" , 0x1180080941150ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP555" , 0x1180080941158ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP556" , 0x1180080941160ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP557" , 0x1180080941168ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP558" , 0x1180080941170ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP559" , 0x1180080941178ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP560" , 0x1180080941180ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP561" , 0x1180080941188ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP562" , 0x1180080941190ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP563" , 0x1180080941198ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP564" , 0x11800809411a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP565" , 0x11800809411a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP566" , 0x11800809411b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP567" , 0x11800809411b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP568" , 0x11800809411c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP569" , 0x11800809411c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP570" , 0x11800809411d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP571" , 0x11800809411d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP572" , 0x11800809411e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP573" , 0x11800809411e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP574" , 0x11800809411f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP575" , 0x11800809411f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP576" , 0x1180080941200ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP577" , 0x1180080941208ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP578" , 0x1180080941210ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP579" , 0x1180080941218ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP580" , 0x1180080941220ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP581" , 0x1180080941228ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP582" , 0x1180080941230ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP583" , 0x1180080941238ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP584" , 0x1180080941240ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP585" , 0x1180080941248ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP586" , 0x1180080941250ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP587" , 0x1180080941258ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP588" , 0x1180080941260ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP589" , 0x1180080941268ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP590" , 0x1180080941270ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP591" , 0x1180080941278ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP592" , 0x1180080941280ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP593" , 0x1180080941288ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP594" , 0x1180080941290ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP595" , 0x1180080941298ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP596" , 0x11800809412a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP597" , 0x11800809412a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP598" , 0x11800809412b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP599" , 0x11800809412b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP600" , 0x11800809412c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP601" , 0x11800809412c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP602" , 0x11800809412d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP603" , 0x11800809412d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP604" , 0x11800809412e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP605" , 0x11800809412e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP606" , 0x11800809412f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP607" , 0x11800809412f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP608" , 0x1180080941300ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP609" , 0x1180080941308ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP610" , 0x1180080941310ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP611" , 0x1180080941318ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP612" , 0x1180080941320ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP613" , 0x1180080941328ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP614" , 0x1180080941330ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP615" , 0x1180080941338ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP616" , 0x1180080941340ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP617" , 0x1180080941348ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP618" , 0x1180080941350ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP619" , 0x1180080941358ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP620" , 0x1180080941360ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP621" , 0x1180080941368ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP622" , 0x1180080941370ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP623" , 0x1180080941378ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP624" , 0x1180080941380ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP625" , 0x1180080941388ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP626" , 0x1180080941390ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP627" , 0x1180080941398ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP628" , 0x11800809413a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP629" , 0x11800809413a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP630" , 0x11800809413b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP631" , 0x11800809413b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP632" , 0x11800809413c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP633" , 0x11800809413c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP634" , 0x11800809413d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP635" , 0x11800809413d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP636" , 0x11800809413e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP637" , 0x11800809413e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP638" , 0x11800809413f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP639" , 0x11800809413f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP640" , 0x1180080941400ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP641" , 0x1180080941408ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP642" , 0x1180080941410ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP643" , 0x1180080941418ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP644" , 0x1180080941420ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP645" , 0x1180080941428ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP646" , 0x1180080941430ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP647" , 0x1180080941438ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP648" , 0x1180080941440ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP649" , 0x1180080941448ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP650" , 0x1180080941450ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP651" , 0x1180080941458ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP652" , 0x1180080941460ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP653" , 0x1180080941468ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP654" , 0x1180080941470ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP655" , 0x1180080941478ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP656" , 0x1180080941480ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP657" , 0x1180080941488ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP658" , 0x1180080941490ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP659" , 0x1180080941498ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP660" , 0x11800809414a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP661" , 0x11800809414a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP662" , 0x11800809414b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP663" , 0x11800809414b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP664" , 0x11800809414c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP665" , 0x11800809414c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP666" , 0x11800809414d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP667" , 0x11800809414d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP668" , 0x11800809414e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP669" , 0x11800809414e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP670" , 0x11800809414f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP671" , 0x11800809414f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP672" , 0x1180080941500ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP673" , 0x1180080941508ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP674" , 0x1180080941510ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP675" , 0x1180080941518ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP676" , 0x1180080941520ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP677" , 0x1180080941528ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP678" , 0x1180080941530ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP679" , 0x1180080941538ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP680" , 0x1180080941540ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP681" , 0x1180080941548ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP682" , 0x1180080941550ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP683" , 0x1180080941558ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP684" , 0x1180080941560ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP685" , 0x1180080941568ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP686" , 0x1180080941570ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP687" , 0x1180080941578ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP688" , 0x1180080941580ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP689" , 0x1180080941588ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP690" , 0x1180080941590ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP691" , 0x1180080941598ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP692" , 0x11800809415a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP693" , 0x11800809415a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP694" , 0x11800809415b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP695" , 0x11800809415b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP696" , 0x11800809415c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP697" , 0x11800809415c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP698" , 0x11800809415d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP699" , 0x11800809415d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP700" , 0x11800809415e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP701" , 0x11800809415e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP702" , 0x11800809415f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP703" , 0x11800809415f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP704" , 0x1180080941600ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP705" , 0x1180080941608ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP706" , 0x1180080941610ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP707" , 0x1180080941618ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP708" , 0x1180080941620ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP709" , 0x1180080941628ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP710" , 0x1180080941630ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP711" , 0x1180080941638ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP712" , 0x1180080941640ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP713" , 0x1180080941648ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP714" , 0x1180080941650ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP715" , 0x1180080941658ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP716" , 0x1180080941660ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP717" , 0x1180080941668ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP718" , 0x1180080941670ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP719" , 0x1180080941678ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP720" , 0x1180080941680ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP721" , 0x1180080941688ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP722" , 0x1180080941690ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP723" , 0x1180080941698ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP724" , 0x11800809416a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP725" , 0x11800809416a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP726" , 0x11800809416b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP727" , 0x11800809416b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP728" , 0x11800809416c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP729" , 0x11800809416c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP730" , 0x11800809416d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP731" , 0x11800809416d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP732" , 0x11800809416e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP733" , 0x11800809416e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP734" , 0x11800809416f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP735" , 0x11800809416f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP736" , 0x1180080941700ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP737" , 0x1180080941708ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP738" , 0x1180080941710ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP739" , 0x1180080941718ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP740" , 0x1180080941720ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP741" , 0x1180080941728ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP742" , 0x1180080941730ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP743" , 0x1180080941738ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP744" , 0x1180080941740ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP745" , 0x1180080941748ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP746" , 0x1180080941750ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP747" , 0x1180080941758ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP748" , 0x1180080941760ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP749" , 0x1180080941768ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP750" , 0x1180080941770ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP751" , 0x1180080941778ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP752" , 0x1180080941780ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP753" , 0x1180080941788ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP754" , 0x1180080941790ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP755" , 0x1180080941798ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP756" , 0x11800809417a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP757" , 0x11800809417a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP758" , 0x11800809417b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP759" , 0x11800809417b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP760" , 0x11800809417c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP761" , 0x11800809417c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP762" , 0x11800809417d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP763" , 0x11800809417d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP764" , 0x11800809417e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP765" , 0x11800809417e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP766" , 0x11800809417f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP767" , 0x11800809417f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP768" , 0x1180080941800ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP769" , 0x1180080941808ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP770" , 0x1180080941810ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP771" , 0x1180080941818ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP772" , 0x1180080941820ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP773" , 0x1180080941828ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP774" , 0x1180080941830ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP775" , 0x1180080941838ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP776" , 0x1180080941840ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP777" , 0x1180080941848ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP778" , 0x1180080941850ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP779" , 0x1180080941858ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP780" , 0x1180080941860ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP781" , 0x1180080941868ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP782" , 0x1180080941870ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP783" , 0x1180080941878ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP784" , 0x1180080941880ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP785" , 0x1180080941888ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP786" , 0x1180080941890ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP787" , 0x1180080941898ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP788" , 0x11800809418a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP789" , 0x11800809418a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP790" , 0x11800809418b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP791" , 0x11800809418b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP792" , 0x11800809418c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP793" , 0x11800809418c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP794" , 0x11800809418d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP795" , 0x11800809418d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP796" , 0x11800809418e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP797" , 0x11800809418e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP798" , 0x11800809418f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP799" , 0x11800809418f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP800" , 0x1180080941900ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP801" , 0x1180080941908ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP802" , 0x1180080941910ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP803" , 0x1180080941918ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP804" , 0x1180080941920ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP805" , 0x1180080941928ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP806" , 0x1180080941930ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP807" , 0x1180080941938ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP808" , 0x1180080941940ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP809" , 0x1180080941948ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP810" , 0x1180080941950ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP811" , 0x1180080941958ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP812" , 0x1180080941960ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP813" , 0x1180080941968ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP814" , 0x1180080941970ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP815" , 0x1180080941978ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP816" , 0x1180080941980ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP817" , 0x1180080941988ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP818" , 0x1180080941990ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP819" , 0x1180080941998ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP820" , 0x11800809419a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP821" , 0x11800809419a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP822" , 0x11800809419b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP823" , 0x11800809419b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP824" , 0x11800809419c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP825" , 0x11800809419c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP826" , 0x11800809419d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP827" , 0x11800809419d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP828" , 0x11800809419e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP829" , 0x11800809419e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP830" , 0x11800809419f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP831" , 0x11800809419f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP832" , 0x1180080941a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP833" , 0x1180080941a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP834" , 0x1180080941a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP835" , 0x1180080941a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP836" , 0x1180080941a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP837" , 0x1180080941a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP838" , 0x1180080941a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP839" , 0x1180080941a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP840" , 0x1180080941a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP841" , 0x1180080941a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP842" , 0x1180080941a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP843" , 0x1180080941a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP844" , 0x1180080941a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP845" , 0x1180080941a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP846" , 0x1180080941a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP847" , 0x1180080941a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP848" , 0x1180080941a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP849" , 0x1180080941a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP850" , 0x1180080941a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP851" , 0x1180080941a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP852" , 0x1180080941aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP853" , 0x1180080941aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP854" , 0x1180080941ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP855" , 0x1180080941ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP856" , 0x1180080941ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP857" , 0x1180080941ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP858" , 0x1180080941ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP859" , 0x1180080941ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP860" , 0x1180080941ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP861" , 0x1180080941ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP862" , 0x1180080941af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP863" , 0x1180080941af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP864" , 0x1180080941b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP865" , 0x1180080941b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP866" , 0x1180080941b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP867" , 0x1180080941b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP868" , 0x1180080941b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP869" , 0x1180080941b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP870" , 0x1180080941b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP871" , 0x1180080941b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP872" , 0x1180080941b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP873" , 0x1180080941b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP874" , 0x1180080941b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP875" , 0x1180080941b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP876" , 0x1180080941b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP877" , 0x1180080941b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP878" , 0x1180080941b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP879" , 0x1180080941b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP880" , 0x1180080941b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP881" , 0x1180080941b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP882" , 0x1180080941b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP883" , 0x1180080941b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP884" , 0x1180080941ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP885" , 0x1180080941ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP886" , 0x1180080941bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP887" , 0x1180080941bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP888" , 0x1180080941bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP889" , 0x1180080941bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP890" , 0x1180080941bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP891" , 0x1180080941bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP892" , 0x1180080941be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP893" , 0x1180080941be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP894" , 0x1180080941bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP895" , 0x1180080941bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP896" , 0x1180080941c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP897" , 0x1180080941c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP898" , 0x1180080941c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP899" , 0x1180080941c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP900" , 0x1180080941c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP901" , 0x1180080941c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP902" , 0x1180080941c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP903" , 0x1180080941c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP904" , 0x1180080941c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP905" , 0x1180080941c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP906" , 0x1180080941c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP907" , 0x1180080941c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP908" , 0x1180080941c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP909" , 0x1180080941c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP910" , 0x1180080941c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP911" , 0x1180080941c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP912" , 0x1180080941c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP913" , 0x1180080941c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP914" , 0x1180080941c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP915" , 0x1180080941c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP916" , 0x1180080941ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP917" , 0x1180080941ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP918" , 0x1180080941cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP919" , 0x1180080941cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP920" , 0x1180080941cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP921" , 0x1180080941cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP922" , 0x1180080941cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP923" , 0x1180080941cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP924" , 0x1180080941ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP925" , 0x1180080941ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP926" , 0x1180080941cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP927" , 0x1180080941cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP928" , 0x1180080941d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP929" , 0x1180080941d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP930" , 0x1180080941d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP931" , 0x1180080941d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP932" , 0x1180080941d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP933" , 0x1180080941d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP934" , 0x1180080941d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP935" , 0x1180080941d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP936" , 0x1180080941d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP937" , 0x1180080941d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP938" , 0x1180080941d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP939" , 0x1180080941d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP940" , 0x1180080941d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP941" , 0x1180080941d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP942" , 0x1180080941d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP943" , 0x1180080941d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP944" , 0x1180080941d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP945" , 0x1180080941d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP946" , 0x1180080941d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP947" , 0x1180080941d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP948" , 0x1180080941da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP949" , 0x1180080941da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP950" , 0x1180080941db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP951" , 0x1180080941db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP952" , 0x1180080941dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP953" , 0x1180080941dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP954" , 0x1180080941dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP955" , 0x1180080941dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP956" , 0x1180080941de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP957" , 0x1180080941de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP958" , 0x1180080941df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP959" , 0x1180080941df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP960" , 0x1180080941e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP961" , 0x1180080941e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP962" , 0x1180080941e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP963" , 0x1180080941e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP964" , 0x1180080941e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP965" , 0x1180080941e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP966" , 0x1180080941e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP967" , 0x1180080941e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP968" , 0x1180080941e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP969" , 0x1180080941e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP970" , 0x1180080941e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP971" , 0x1180080941e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP972" , 0x1180080941e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP973" , 0x1180080941e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP974" , 0x1180080941e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP975" , 0x1180080941e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP976" , 0x1180080941e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP977" , 0x1180080941e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP978" , 0x1180080941e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP979" , 0x1180080941e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP980" , 0x1180080941ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP981" , 0x1180080941ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP982" , 0x1180080941eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP983" , 0x1180080941eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP984" , 0x1180080941ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP985" , 0x1180080941ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP986" , 0x1180080941ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP987" , 0x1180080941ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP988" , 0x1180080941ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP989" , 0x1180080941ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP990" , 0x1180080941ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP991" , 0x1180080941ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP992" , 0x1180080941f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP993" , 0x1180080941f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP994" , 0x1180080941f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP995" , 0x1180080941f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP996" , 0x1180080941f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP997" , 0x1180080941f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP998" , 0x1180080941f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP999" , 0x1180080941f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1000" , 0x1180080941f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1001" , 0x1180080941f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1002" , 0x1180080941f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1003" , 0x1180080941f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1004" , 0x1180080941f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1005" , 0x1180080941f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1006" , 0x1180080941f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1007" , 0x1180080941f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1008" , 0x1180080941f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1009" , 0x1180080941f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1010" , 0x1180080941f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1011" , 0x1180080941f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1012" , 0x1180080941fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1013" , 0x1180080941fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1014" , 0x1180080941fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1015" , 0x1180080941fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1016" , 0x1180080941fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1017" , 0x1180080941fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1018" , 0x1180080941fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1019" , 0x1180080941fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1020" , 0x1180080941fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1021" , 0x1180080941fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1022" , 0x1180080941ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1023" , 0x1180080941ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1024" , 0x1180080942000ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1025" , 0x1180080942008ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1026" , 0x1180080942010ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1027" , 0x1180080942018ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1028" , 0x1180080942020ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1029" , 0x1180080942028ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1030" , 0x1180080942030ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1031" , 0x1180080942038ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1032" , 0x1180080942040ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1033" , 0x1180080942048ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1034" , 0x1180080942050ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1035" , 0x1180080942058ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1036" , 0x1180080942060ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1037" , 0x1180080942068ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1038" , 0x1180080942070ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1039" , 0x1180080942078ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1040" , 0x1180080942080ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1041" , 0x1180080942088ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1042" , 0x1180080942090ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1043" , 0x1180080942098ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1044" , 0x11800809420a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1045" , 0x11800809420a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1046" , 0x11800809420b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1047" , 0x11800809420b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1048" , 0x11800809420c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1049" , 0x11800809420c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1050" , 0x11800809420d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1051" , 0x11800809420d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1052" , 0x11800809420e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1053" , 0x11800809420e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1054" , 0x11800809420f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1055" , 0x11800809420f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1056" , 0x1180080942100ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1057" , 0x1180080942108ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1058" , 0x1180080942110ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1059" , 0x1180080942118ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1060" , 0x1180080942120ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1061" , 0x1180080942128ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1062" , 0x1180080942130ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1063" , 0x1180080942138ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1064" , 0x1180080942140ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1065" , 0x1180080942148ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1066" , 0x1180080942150ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1067" , 0x1180080942158ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1068" , 0x1180080942160ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1069" , 0x1180080942168ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1070" , 0x1180080942170ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1071" , 0x1180080942178ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1072" , 0x1180080942180ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1073" , 0x1180080942188ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1074" , 0x1180080942190ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1075" , 0x1180080942198ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1076" , 0x11800809421a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1077" , 0x11800809421a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1078" , 0x11800809421b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1079" , 0x11800809421b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1080" , 0x11800809421c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1081" , 0x11800809421c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1082" , 0x11800809421d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1083" , 0x11800809421d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1084" , 0x11800809421e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1085" , 0x11800809421e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1086" , 0x11800809421f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1087" , 0x11800809421f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1088" , 0x1180080942200ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1089" , 0x1180080942208ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1090" , 0x1180080942210ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1091" , 0x1180080942218ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1092" , 0x1180080942220ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1093" , 0x1180080942228ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1094" , 0x1180080942230ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1095" , 0x1180080942238ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1096" , 0x1180080942240ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1097" , 0x1180080942248ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1098" , 0x1180080942250ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1099" , 0x1180080942258ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1100" , 0x1180080942260ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1101" , 0x1180080942268ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1102" , 0x1180080942270ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1103" , 0x1180080942278ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1104" , 0x1180080942280ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1105" , 0x1180080942288ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1106" , 0x1180080942290ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1107" , 0x1180080942298ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1108" , 0x11800809422a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1109" , 0x11800809422a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1110" , 0x11800809422b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1111" , 0x11800809422b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1112" , 0x11800809422c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1113" , 0x11800809422c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1114" , 0x11800809422d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1115" , 0x11800809422d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1116" , 0x11800809422e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1117" , 0x11800809422e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1118" , 0x11800809422f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1119" , 0x11800809422f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1120" , 0x1180080942300ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1121" , 0x1180080942308ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1122" , 0x1180080942310ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1123" , 0x1180080942318ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1124" , 0x1180080942320ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1125" , 0x1180080942328ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1126" , 0x1180080942330ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1127" , 0x1180080942338ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1128" , 0x1180080942340ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1129" , 0x1180080942348ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1130" , 0x1180080942350ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1131" , 0x1180080942358ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1132" , 0x1180080942360ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1133" , 0x1180080942368ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1134" , 0x1180080942370ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1135" , 0x1180080942378ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1136" , 0x1180080942380ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1137" , 0x1180080942388ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1138" , 0x1180080942390ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1139" , 0x1180080942398ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1140" , 0x11800809423a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1141" , 0x11800809423a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1142" , 0x11800809423b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1143" , 0x11800809423b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1144" , 0x11800809423c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1145" , 0x11800809423c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1146" , 0x11800809423d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1147" , 0x11800809423d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1148" , 0x11800809423e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1149" , 0x11800809423e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1150" , 0x11800809423f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1151" , 0x11800809423f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1152" , 0x1180080942400ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1153" , 0x1180080942408ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1154" , 0x1180080942410ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1155" , 0x1180080942418ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1156" , 0x1180080942420ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1157" , 0x1180080942428ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1158" , 0x1180080942430ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1159" , 0x1180080942438ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1160" , 0x1180080942440ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1161" , 0x1180080942448ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1162" , 0x1180080942450ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1163" , 0x1180080942458ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1164" , 0x1180080942460ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1165" , 0x1180080942468ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1166" , 0x1180080942470ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1167" , 0x1180080942478ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1168" , 0x1180080942480ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1169" , 0x1180080942488ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1170" , 0x1180080942490ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1171" , 0x1180080942498ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1172" , 0x11800809424a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1173" , 0x11800809424a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1174" , 0x11800809424b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1175" , 0x11800809424b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1176" , 0x11800809424c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1177" , 0x11800809424c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1178" , 0x11800809424d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1179" , 0x11800809424d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1180" , 0x11800809424e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1181" , 0x11800809424e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1182" , 0x11800809424f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1183" , 0x11800809424f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1184" , 0x1180080942500ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1185" , 0x1180080942508ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1186" , 0x1180080942510ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1187" , 0x1180080942518ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1188" , 0x1180080942520ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1189" , 0x1180080942528ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1190" , 0x1180080942530ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1191" , 0x1180080942538ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1192" , 0x1180080942540ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1193" , 0x1180080942548ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1194" , 0x1180080942550ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1195" , 0x1180080942558ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1196" , 0x1180080942560ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1197" , 0x1180080942568ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1198" , 0x1180080942570ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1199" , 0x1180080942578ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1200" , 0x1180080942580ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1201" , 0x1180080942588ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1202" , 0x1180080942590ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1203" , 0x1180080942598ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1204" , 0x11800809425a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1205" , 0x11800809425a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1206" , 0x11800809425b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1207" , 0x11800809425b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1208" , 0x11800809425c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1209" , 0x11800809425c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1210" , 0x11800809425d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1211" , 0x11800809425d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1212" , 0x11800809425e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1213" , 0x11800809425e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1214" , 0x11800809425f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1215" , 0x11800809425f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1216" , 0x1180080942600ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1217" , 0x1180080942608ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1218" , 0x1180080942610ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1219" , 0x1180080942618ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1220" , 0x1180080942620ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1221" , 0x1180080942628ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1222" , 0x1180080942630ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1223" , 0x1180080942638ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1224" , 0x1180080942640ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1225" , 0x1180080942648ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1226" , 0x1180080942650ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1227" , 0x1180080942658ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1228" , 0x1180080942660ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1229" , 0x1180080942668ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1230" , 0x1180080942670ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1231" , 0x1180080942678ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1232" , 0x1180080942680ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1233" , 0x1180080942688ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1234" , 0x1180080942690ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1235" , 0x1180080942698ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1236" , 0x11800809426a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1237" , 0x11800809426a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1238" , 0x11800809426b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1239" , 0x11800809426b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1240" , 0x11800809426c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1241" , 0x11800809426c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1242" , 0x11800809426d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1243" , 0x11800809426d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1244" , 0x11800809426e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1245" , 0x11800809426e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1246" , 0x11800809426f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1247" , 0x11800809426f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1248" , 0x1180080942700ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1249" , 0x1180080942708ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1250" , 0x1180080942710ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1251" , 0x1180080942718ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1252" , 0x1180080942720ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1253" , 0x1180080942728ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1254" , 0x1180080942730ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1255" , 0x1180080942738ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1256" , 0x1180080942740ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1257" , 0x1180080942748ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1258" , 0x1180080942750ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1259" , 0x1180080942758ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1260" , 0x1180080942760ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1261" , 0x1180080942768ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1262" , 0x1180080942770ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1263" , 0x1180080942778ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1264" , 0x1180080942780ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1265" , 0x1180080942788ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1266" , 0x1180080942790ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1267" , 0x1180080942798ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1268" , 0x11800809427a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1269" , 0x11800809427a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1270" , 0x11800809427b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1271" , 0x11800809427b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1272" , 0x11800809427c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1273" , 0x11800809427c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1274" , 0x11800809427d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1275" , 0x11800809427d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1276" , 0x11800809427e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1277" , 0x11800809427e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1278" , 0x11800809427f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1279" , 0x11800809427f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1280" , 0x1180080942800ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1281" , 0x1180080942808ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1282" , 0x1180080942810ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1283" , 0x1180080942818ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1284" , 0x1180080942820ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1285" , 0x1180080942828ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1286" , 0x1180080942830ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1287" , 0x1180080942838ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1288" , 0x1180080942840ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1289" , 0x1180080942848ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1290" , 0x1180080942850ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1291" , 0x1180080942858ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1292" , 0x1180080942860ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1293" , 0x1180080942868ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1294" , 0x1180080942870ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1295" , 0x1180080942878ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1296" , 0x1180080942880ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1297" , 0x1180080942888ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1298" , 0x1180080942890ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1299" , 0x1180080942898ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1300" , 0x11800809428a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1301" , 0x11800809428a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1302" , 0x11800809428b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1303" , 0x11800809428b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1304" , 0x11800809428c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1305" , 0x11800809428c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1306" , 0x11800809428d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1307" , 0x11800809428d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1308" , 0x11800809428e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1309" , 0x11800809428e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1310" , 0x11800809428f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1311" , 0x11800809428f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1312" , 0x1180080942900ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1313" , 0x1180080942908ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1314" , 0x1180080942910ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1315" , 0x1180080942918ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1316" , 0x1180080942920ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1317" , 0x1180080942928ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1318" , 0x1180080942930ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1319" , 0x1180080942938ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1320" , 0x1180080942940ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1321" , 0x1180080942948ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1322" , 0x1180080942950ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1323" , 0x1180080942958ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1324" , 0x1180080942960ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1325" , 0x1180080942968ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1326" , 0x1180080942970ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1327" , 0x1180080942978ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1328" , 0x1180080942980ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1329" , 0x1180080942988ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1330" , 0x1180080942990ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1331" , 0x1180080942998ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1332" , 0x11800809429a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1333" , 0x11800809429a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1334" , 0x11800809429b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1335" , 0x11800809429b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1336" , 0x11800809429c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1337" , 0x11800809429c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1338" , 0x11800809429d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1339" , 0x11800809429d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1340" , 0x11800809429e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1341" , 0x11800809429e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1342" , 0x11800809429f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1343" , 0x11800809429f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1344" , 0x1180080942a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1345" , 0x1180080942a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1346" , 0x1180080942a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1347" , 0x1180080942a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1348" , 0x1180080942a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1349" , 0x1180080942a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1350" , 0x1180080942a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1351" , 0x1180080942a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1352" , 0x1180080942a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1353" , 0x1180080942a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1354" , 0x1180080942a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1355" , 0x1180080942a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1356" , 0x1180080942a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1357" , 0x1180080942a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1358" , 0x1180080942a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1359" , 0x1180080942a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1360" , 0x1180080942a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1361" , 0x1180080942a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1362" , 0x1180080942a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1363" , 0x1180080942a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1364" , 0x1180080942aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1365" , 0x1180080942aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1366" , 0x1180080942ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1367" , 0x1180080942ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1368" , 0x1180080942ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1369" , 0x1180080942ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1370" , 0x1180080942ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1371" , 0x1180080942ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1372" , 0x1180080942ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1373" , 0x1180080942ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1374" , 0x1180080942af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1375" , 0x1180080942af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1376" , 0x1180080942b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1377" , 0x1180080942b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1378" , 0x1180080942b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1379" , 0x1180080942b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1380" , 0x1180080942b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1381" , 0x1180080942b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1382" , 0x1180080942b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1383" , 0x1180080942b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1384" , 0x1180080942b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1385" , 0x1180080942b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1386" , 0x1180080942b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1387" , 0x1180080942b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1388" , 0x1180080942b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1389" , 0x1180080942b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1390" , 0x1180080942b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1391" , 0x1180080942b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1392" , 0x1180080942b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1393" , 0x1180080942b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1394" , 0x1180080942b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1395" , 0x1180080942b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1396" , 0x1180080942ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1397" , 0x1180080942ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1398" , 0x1180080942bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1399" , 0x1180080942bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1400" , 0x1180080942bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1401" , 0x1180080942bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1402" , 0x1180080942bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1403" , 0x1180080942bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1404" , 0x1180080942be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1405" , 0x1180080942be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1406" , 0x1180080942bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1407" , 0x1180080942bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1408" , 0x1180080942c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1409" , 0x1180080942c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1410" , 0x1180080942c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1411" , 0x1180080942c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1412" , 0x1180080942c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1413" , 0x1180080942c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1414" , 0x1180080942c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1415" , 0x1180080942c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1416" , 0x1180080942c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1417" , 0x1180080942c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1418" , 0x1180080942c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1419" , 0x1180080942c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1420" , 0x1180080942c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1421" , 0x1180080942c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1422" , 0x1180080942c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1423" , 0x1180080942c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1424" , 0x1180080942c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1425" , 0x1180080942c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1426" , 0x1180080942c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1427" , 0x1180080942c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1428" , 0x1180080942ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1429" , 0x1180080942ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1430" , 0x1180080942cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1431" , 0x1180080942cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1432" , 0x1180080942cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1433" , 0x1180080942cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1434" , 0x1180080942cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1435" , 0x1180080942cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1436" , 0x1180080942ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1437" , 0x1180080942ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1438" , 0x1180080942cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1439" , 0x1180080942cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1440" , 0x1180080942d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1441" , 0x1180080942d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1442" , 0x1180080942d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1443" , 0x1180080942d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1444" , 0x1180080942d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1445" , 0x1180080942d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1446" , 0x1180080942d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1447" , 0x1180080942d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1448" , 0x1180080942d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1449" , 0x1180080942d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1450" , 0x1180080942d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1451" , 0x1180080942d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1452" , 0x1180080942d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1453" , 0x1180080942d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1454" , 0x1180080942d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1455" , 0x1180080942d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1456" , 0x1180080942d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1457" , 0x1180080942d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1458" , 0x1180080942d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1459" , 0x1180080942d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1460" , 0x1180080942da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1461" , 0x1180080942da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1462" , 0x1180080942db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1463" , 0x1180080942db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1464" , 0x1180080942dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1465" , 0x1180080942dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1466" , 0x1180080942dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1467" , 0x1180080942dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1468" , 0x1180080942de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1469" , 0x1180080942de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1470" , 0x1180080942df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1471" , 0x1180080942df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1472" , 0x1180080942e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1473" , 0x1180080942e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1474" , 0x1180080942e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1475" , 0x1180080942e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1476" , 0x1180080942e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1477" , 0x1180080942e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1478" , 0x1180080942e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1479" , 0x1180080942e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1480" , 0x1180080942e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1481" , 0x1180080942e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1482" , 0x1180080942e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1483" , 0x1180080942e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1484" , 0x1180080942e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1485" , 0x1180080942e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1486" , 0x1180080942e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1487" , 0x1180080942e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1488" , 0x1180080942e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1489" , 0x1180080942e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1490" , 0x1180080942e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1491" , 0x1180080942e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1492" , 0x1180080942ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1493" , 0x1180080942ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1494" , 0x1180080942eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1495" , 0x1180080942eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1496" , 0x1180080942ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1497" , 0x1180080942ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1498" , 0x1180080942ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1499" , 0x1180080942ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1500" , 0x1180080942ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1501" , 0x1180080942ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1502" , 0x1180080942ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1503" , 0x1180080942ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1504" , 0x1180080942f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1505" , 0x1180080942f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1506" , 0x1180080942f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1507" , 0x1180080942f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1508" , 0x1180080942f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1509" , 0x1180080942f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1510" , 0x1180080942f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1511" , 0x1180080942f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1512" , 0x1180080942f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1513" , 0x1180080942f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1514" , 0x1180080942f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1515" , 0x1180080942f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1516" , 0x1180080942f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1517" , 0x1180080942f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1518" , 0x1180080942f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1519" , 0x1180080942f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1520" , 0x1180080942f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1521" , 0x1180080942f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1522" , 0x1180080942f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1523" , 0x1180080942f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1524" , 0x1180080942fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1525" , 0x1180080942fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1526" , 0x1180080942fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1527" , 0x1180080942fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1528" , 0x1180080942fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1529" , 0x1180080942fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1530" , 0x1180080942fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1531" , 0x1180080942fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1532" , 0x1180080942fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1533" , 0x1180080942fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1534" , 0x1180080942ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP1535" , 0x1180080942ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16128" , 0x118008095f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16129" , 0x118008095f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16130" , 0x118008095f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16131" , 0x118008095f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16132" , 0x118008095f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16133" , 0x118008095f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16134" , 0x118008095f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16135" , 0x118008095f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16136" , 0x118008095f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16137" , 0x118008095f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16138" , 0x118008095f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16139" , 0x118008095f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16140" , 0x118008095f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16141" , 0x118008095f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16142" , 0x118008095f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16143" , 0x118008095f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16144" , 0x118008095f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16145" , 0x118008095f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16146" , 0x118008095f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16147" , 0x118008095f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16148" , 0x118008095f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16149" , 0x118008095f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16150" , 0x118008095f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16151" , 0x118008095f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16152" , 0x118008095f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16153" , 0x118008095f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16154" , 0x118008095f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16155" , 0x118008095f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16156" , 0x118008095f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16157" , 0x118008095f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16158" , 0x118008095f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16159" , 0x118008095f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16160" , 0x118008095f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16161" , 0x118008095f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16162" , 0x118008095f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16163" , 0x118008095f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16164" , 0x118008095f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16165" , 0x118008095f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16166" , 0x118008095f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16167" , 0x118008095f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16168" , 0x118008095f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16169" , 0x118008095f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16170" , 0x118008095f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16171" , 0x118008095f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16172" , 0x118008095f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16173" , 0x118008095f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16174" , 0x118008095f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16175" , 0x118008095f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16176" , 0x118008095f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16177" , 0x118008095f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16178" , 0x118008095f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16179" , 0x118008095f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16180" , 0x118008095f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16181" , 0x118008095f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16182" , 0x118008095f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16183" , 0x118008095f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16184" , 0x118008095f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16185" , 0x118008095f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16186" , 0x118008095f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16187" , 0x118008095f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16188" , 0x118008095f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16189" , 0x118008095f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16190" , 0x118008095f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16191" , 0x118008095f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16192" , 0x118008095fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16193" , 0x118008095fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16194" , 0x118008095fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16195" , 0x118008095fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16196" , 0x118008095fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16197" , 0x118008095fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16198" , 0x118008095fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16199" , 0x118008095fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16200" , 0x118008095fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16201" , 0x118008095fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16202" , 0x118008095fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16203" , 0x118008095fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16204" , 0x118008095fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16205" , 0x118008095fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16206" , 0x118008095fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16207" , 0x118008095fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16208" , 0x118008095fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16209" , 0x118008095fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16210" , 0x118008095fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16211" , 0x118008095fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16212" , 0x118008095faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16213" , 0x118008095faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16214" , 0x118008095fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16215" , 0x118008095fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16216" , 0x118008095fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16217" , 0x118008095fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16218" , 0x118008095fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16219" , 0x118008095fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16220" , 0x118008095fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16221" , 0x118008095fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16222" , 0x118008095faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16223" , 0x118008095faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16224" , 0x118008095fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16225" , 0x118008095fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16226" , 0x118008095fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16227" , 0x118008095fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16228" , 0x118008095fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16229" , 0x118008095fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16230" , 0x118008095fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16231" , 0x118008095fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16232" , 0x118008095fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16233" , 0x118008095fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16234" , 0x118008095fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16235" , 0x118008095fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16236" , 0x118008095fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16237" , 0x118008095fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16238" , 0x118008095fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16239" , 0x118008095fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16240" , 0x118008095fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16241" , 0x118008095fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16242" , 0x118008095fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16243" , 0x118008095fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16244" , 0x118008095fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16245" , 0x118008095fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16246" , 0x118008095fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16247" , 0x118008095fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16248" , 0x118008095fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16249" , 0x118008095fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16250" , 0x118008095fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16251" , 0x118008095fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16252" , 0x118008095fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16253" , 0x118008095fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16254" , 0x118008095fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16255" , 0x118008095fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16256" , 0x118008095fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16257" , 0x118008095fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16258" , 0x118008095fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16259" , 0x118008095fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16260" , 0x118008095fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16261" , 0x118008095fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16262" , 0x118008095fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16263" , 0x118008095fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16264" , 0x118008095fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16265" , 0x118008095fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16266" , 0x118008095fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16267" , 0x118008095fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16268" , 0x118008095fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16269" , 0x118008095fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16270" , 0x118008095fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16271" , 0x118008095fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16272" , 0x118008095fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16273" , 0x118008095fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16274" , 0x118008095fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16275" , 0x118008095fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16276" , 0x118008095fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16277" , 0x118008095fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16278" , 0x118008095fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16279" , 0x118008095fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16280" , 0x118008095fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16281" , 0x118008095fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16282" , 0x118008095fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16283" , 0x118008095fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16284" , 0x118008095fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16285" , 0x118008095fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16286" , 0x118008095fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16287" , 0x118008095fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16288" , 0x118008095fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16289" , 0x118008095fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16290" , 0x118008095fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16291" , 0x118008095fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16292" , 0x118008095fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16293" , 0x118008095fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16294" , 0x118008095fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16295" , 0x118008095fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16296" , 0x118008095fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16297" , 0x118008095fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16298" , 0x118008095fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16299" , 0x118008095fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16300" , 0x118008095fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16301" , 0x118008095fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16302" , 0x118008095fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16303" , 0x118008095fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16304" , 0x118008095fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16305" , 0x118008095fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16306" , 0x118008095fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16307" , 0x118008095fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16308" , 0x118008095fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16309" , 0x118008095fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16310" , 0x118008095fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16311" , 0x118008095fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16312" , 0x118008095fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16313" , 0x118008095fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16314" , 0x118008095fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16315" , 0x118008095fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16316" , 0x118008095fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16317" , 0x118008095fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16318" , 0x118008095fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16319" , 0x118008095fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16320" , 0x118008095fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16321" , 0x118008095fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16322" , 0x118008095fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16323" , 0x118008095fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16324" , 0x118008095fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16325" , 0x118008095fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16326" , 0x118008095fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16327" , 0x118008095fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16328" , 0x118008095fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16329" , 0x118008095fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16330" , 0x118008095fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16331" , 0x118008095fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16332" , 0x118008095fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16333" , 0x118008095fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16334" , 0x118008095fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16335" , 0x118008095fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16336" , 0x118008095fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16337" , 0x118008095fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16338" , 0x118008095fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16339" , 0x118008095fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16340" , 0x118008095fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16341" , 0x118008095fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16342" , 0x118008095feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16343" , 0x118008095feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16344" , 0x118008095fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16345" , 0x118008095fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16346" , 0x118008095fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16347" , 0x118008095fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16348" , 0x118008095fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16349" , 0x118008095fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16350" , 0x118008095fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16351" , 0x118008095fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16352" , 0x118008095ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16353" , 0x118008095ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16354" , 0x118008095ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16355" , 0x118008095ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16356" , 0x118008095ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16357" , 0x118008095ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16358" , 0x118008095ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16359" , 0x118008095ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16360" , 0x118008095ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16361" , 0x118008095ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16362" , 0x118008095ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16363" , 0x118008095ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16364" , 0x118008095ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16365" , 0x118008095ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16366" , 0x118008095ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16367" , 0x118008095ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16368" , 0x118008095ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16369" , 0x118008095ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16370" , 0x118008095ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16371" , 0x118008095ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16372" , 0x118008095ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16373" , 0x118008095ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16374" , 0x118008095ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16375" , 0x118008095ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16376" , 0x118008095ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16377" , 0x118008095ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16378" , 0x118008095ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16379" , 0x118008095ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16380" , 0x118008095ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16381" , 0x118008095ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16382" , 0x118008095fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_COP0_MAP16383" , 0x118008095fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_CTL" , 0x1180080800000ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"L2C_DUT_MAP0" , 0x1180080e00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1" , 0x1180080e00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP2" , 0x1180080e00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP3" , 0x1180080e00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP4" , 0x1180080e00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP5" , 0x1180080e00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP6" , 0x1180080e00030ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP7" , 0x1180080e00038ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP8" , 0x1180080e00040ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP9" , 0x1180080e00048ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP10" , 0x1180080e00050ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP11" , 0x1180080e00058ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP12" , 0x1180080e00060ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP13" , 0x1180080e00068ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP14" , 0x1180080e00070ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP15" , 0x1180080e00078ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP16" , 0x1180080e00080ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP17" , 0x1180080e00088ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP18" , 0x1180080e00090ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP19" , 0x1180080e00098ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP20" , 0x1180080e000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP21" , 0x1180080e000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP22" , 0x1180080e000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP23" , 0x1180080e000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP24" , 0x1180080e000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP25" , 0x1180080e000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP26" , 0x1180080e000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP27" , 0x1180080e000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP28" , 0x1180080e000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP29" , 0x1180080e000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP30" , 0x1180080e000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP31" , 0x1180080e000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP32" , 0x1180080e00100ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP33" , 0x1180080e00108ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP34" , 0x1180080e00110ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP35" , 0x1180080e00118ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP36" , 0x1180080e00120ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP37" , 0x1180080e00128ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP38" , 0x1180080e00130ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP39" , 0x1180080e00138ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP40" , 0x1180080e00140ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP41" , 0x1180080e00148ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP42" , 0x1180080e00150ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP43" , 0x1180080e00158ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP44" , 0x1180080e00160ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP45" , 0x1180080e00168ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP46" , 0x1180080e00170ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP47" , 0x1180080e00178ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP48" , 0x1180080e00180ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP49" , 0x1180080e00188ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP50" , 0x1180080e00190ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP51" , 0x1180080e00198ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP52" , 0x1180080e001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP53" , 0x1180080e001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP54" , 0x1180080e001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP55" , 0x1180080e001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP56" , 0x1180080e001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP57" , 0x1180080e001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP58" , 0x1180080e001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP59" , 0x1180080e001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP60" , 0x1180080e001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP61" , 0x1180080e001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP62" , 0x1180080e001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP63" , 0x1180080e001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP64" , 0x1180080e00200ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP65" , 0x1180080e00208ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP66" , 0x1180080e00210ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP67" , 0x1180080e00218ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP68" , 0x1180080e00220ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP69" , 0x1180080e00228ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP70" , 0x1180080e00230ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP71" , 0x1180080e00238ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP72" , 0x1180080e00240ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP73" , 0x1180080e00248ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP74" , 0x1180080e00250ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP75" , 0x1180080e00258ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP76" , 0x1180080e00260ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP77" , 0x1180080e00268ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP78" , 0x1180080e00270ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP79" , 0x1180080e00278ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP80" , 0x1180080e00280ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP81" , 0x1180080e00288ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP82" , 0x1180080e00290ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP83" , 0x1180080e00298ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP84" , 0x1180080e002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP85" , 0x1180080e002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP86" , 0x1180080e002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP87" , 0x1180080e002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP88" , 0x1180080e002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP89" , 0x1180080e002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP90" , 0x1180080e002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP91" , 0x1180080e002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP92" , 0x1180080e002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP93" , 0x1180080e002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP94" , 0x1180080e002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP95" , 0x1180080e002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP96" , 0x1180080e00300ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP97" , 0x1180080e00308ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP98" , 0x1180080e00310ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP99" , 0x1180080e00318ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP100" , 0x1180080e00320ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP101" , 0x1180080e00328ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP102" , 0x1180080e00330ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP103" , 0x1180080e00338ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP104" , 0x1180080e00340ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP105" , 0x1180080e00348ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP106" , 0x1180080e00350ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP107" , 0x1180080e00358ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP108" , 0x1180080e00360ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP109" , 0x1180080e00368ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP110" , 0x1180080e00370ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP111" , 0x1180080e00378ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP112" , 0x1180080e00380ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP113" , 0x1180080e00388ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP114" , 0x1180080e00390ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP115" , 0x1180080e00398ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP116" , 0x1180080e003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP117" , 0x1180080e003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP118" , 0x1180080e003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP119" , 0x1180080e003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP120" , 0x1180080e003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP121" , 0x1180080e003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP122" , 0x1180080e003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP123" , 0x1180080e003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP124" , 0x1180080e003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP125" , 0x1180080e003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP126" , 0x1180080e003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP127" , 0x1180080e003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP128" , 0x1180080e00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP129" , 0x1180080e00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP130" , 0x1180080e00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP131" , 0x1180080e00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP132" , 0x1180080e00420ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP133" , 0x1180080e00428ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP134" , 0x1180080e00430ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP135" , 0x1180080e00438ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP136" , 0x1180080e00440ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP137" , 0x1180080e00448ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP138" , 0x1180080e00450ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP139" , 0x1180080e00458ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP140" , 0x1180080e00460ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP141" , 0x1180080e00468ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP142" , 0x1180080e00470ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP143" , 0x1180080e00478ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP144" , 0x1180080e00480ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP145" , 0x1180080e00488ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP146" , 0x1180080e00490ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP147" , 0x1180080e00498ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP148" , 0x1180080e004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP149" , 0x1180080e004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP150" , 0x1180080e004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP151" , 0x1180080e004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP152" , 0x1180080e004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP153" , 0x1180080e004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP154" , 0x1180080e004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP155" , 0x1180080e004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP156" , 0x1180080e004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP157" , 0x1180080e004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP158" , 0x1180080e004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP159" , 0x1180080e004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP160" , 0x1180080e00500ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP161" , 0x1180080e00508ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP162" , 0x1180080e00510ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP163" , 0x1180080e00518ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP164" , 0x1180080e00520ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP165" , 0x1180080e00528ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP166" , 0x1180080e00530ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP167" , 0x1180080e00538ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP168" , 0x1180080e00540ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP169" , 0x1180080e00548ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP170" , 0x1180080e00550ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP171" , 0x1180080e00558ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP172" , 0x1180080e00560ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP173" , 0x1180080e00568ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP174" , 0x1180080e00570ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP175" , 0x1180080e00578ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP176" , 0x1180080e00580ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP177" , 0x1180080e00588ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP178" , 0x1180080e00590ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP179" , 0x1180080e00598ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP180" , 0x1180080e005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP181" , 0x1180080e005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP182" , 0x1180080e005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP183" , 0x1180080e005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP184" , 0x1180080e005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP185" , 0x1180080e005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP186" , 0x1180080e005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP187" , 0x1180080e005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP188" , 0x1180080e005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP189" , 0x1180080e005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP190" , 0x1180080e005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP191" , 0x1180080e005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP192" , 0x1180080e00600ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP193" , 0x1180080e00608ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP194" , 0x1180080e00610ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP195" , 0x1180080e00618ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP196" , 0x1180080e00620ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP197" , 0x1180080e00628ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP198" , 0x1180080e00630ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP199" , 0x1180080e00638ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP200" , 0x1180080e00640ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP201" , 0x1180080e00648ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP202" , 0x1180080e00650ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP203" , 0x1180080e00658ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP204" , 0x1180080e00660ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP205" , 0x1180080e00668ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP206" , 0x1180080e00670ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP207" , 0x1180080e00678ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP208" , 0x1180080e00680ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP209" , 0x1180080e00688ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP210" , 0x1180080e00690ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP211" , 0x1180080e00698ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP212" , 0x1180080e006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP213" , 0x1180080e006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP214" , 0x1180080e006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP215" , 0x1180080e006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP216" , 0x1180080e006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP217" , 0x1180080e006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP218" , 0x1180080e006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP219" , 0x1180080e006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP220" , 0x1180080e006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP221" , 0x1180080e006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP222" , 0x1180080e006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP223" , 0x1180080e006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP224" , 0x1180080e00700ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP225" , 0x1180080e00708ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP226" , 0x1180080e00710ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP227" , 0x1180080e00718ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP228" , 0x1180080e00720ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP229" , 0x1180080e00728ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP230" , 0x1180080e00730ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP231" , 0x1180080e00738ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP232" , 0x1180080e00740ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP233" , 0x1180080e00748ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP234" , 0x1180080e00750ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP235" , 0x1180080e00758ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP236" , 0x1180080e00760ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP237" , 0x1180080e00768ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP238" , 0x1180080e00770ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP239" , 0x1180080e00778ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP240" , 0x1180080e00780ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP241" , 0x1180080e00788ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP242" , 0x1180080e00790ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP243" , 0x1180080e00798ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP244" , 0x1180080e007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP245" , 0x1180080e007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP246" , 0x1180080e007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP247" , 0x1180080e007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP248" , 0x1180080e007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP249" , 0x1180080e007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP250" , 0x1180080e007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP251" , 0x1180080e007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP252" , 0x1180080e007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP253" , 0x1180080e007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP254" , 0x1180080e007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP255" , 0x1180080e007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP256" , 0x1180080e00800ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP257" , 0x1180080e00808ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP258" , 0x1180080e00810ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP259" , 0x1180080e00818ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP260" , 0x1180080e00820ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP261" , 0x1180080e00828ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP262" , 0x1180080e00830ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP263" , 0x1180080e00838ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP264" , 0x1180080e00840ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP265" , 0x1180080e00848ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP266" , 0x1180080e00850ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP267" , 0x1180080e00858ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP268" , 0x1180080e00860ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP269" , 0x1180080e00868ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP270" , 0x1180080e00870ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP271" , 0x1180080e00878ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP272" , 0x1180080e00880ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP273" , 0x1180080e00888ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP274" , 0x1180080e00890ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP275" , 0x1180080e00898ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP276" , 0x1180080e008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP277" , 0x1180080e008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP278" , 0x1180080e008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP279" , 0x1180080e008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP280" , 0x1180080e008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP281" , 0x1180080e008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP282" , 0x1180080e008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP283" , 0x1180080e008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP284" , 0x1180080e008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP285" , 0x1180080e008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP286" , 0x1180080e008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP287" , 0x1180080e008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP288" , 0x1180080e00900ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP289" , 0x1180080e00908ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP290" , 0x1180080e00910ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP291" , 0x1180080e00918ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP292" , 0x1180080e00920ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP293" , 0x1180080e00928ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP294" , 0x1180080e00930ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP295" , 0x1180080e00938ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP296" , 0x1180080e00940ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP297" , 0x1180080e00948ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP298" , 0x1180080e00950ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP299" , 0x1180080e00958ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP300" , 0x1180080e00960ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP301" , 0x1180080e00968ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP302" , 0x1180080e00970ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP303" , 0x1180080e00978ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP304" , 0x1180080e00980ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP305" , 0x1180080e00988ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP306" , 0x1180080e00990ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP307" , 0x1180080e00998ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP308" , 0x1180080e009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP309" , 0x1180080e009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP310" , 0x1180080e009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP311" , 0x1180080e009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP312" , 0x1180080e009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP313" , 0x1180080e009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP314" , 0x1180080e009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP315" , 0x1180080e009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP316" , 0x1180080e009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP317" , 0x1180080e009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP318" , 0x1180080e009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP319" , 0x1180080e009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP320" , 0x1180080e00a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP321" , 0x1180080e00a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP322" , 0x1180080e00a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP323" , 0x1180080e00a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP324" , 0x1180080e00a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP325" , 0x1180080e00a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP326" , 0x1180080e00a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP327" , 0x1180080e00a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP328" , 0x1180080e00a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP329" , 0x1180080e00a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP330" , 0x1180080e00a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP331" , 0x1180080e00a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP332" , 0x1180080e00a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP333" , 0x1180080e00a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP334" , 0x1180080e00a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP335" , 0x1180080e00a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP336" , 0x1180080e00a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP337" , 0x1180080e00a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP338" , 0x1180080e00a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP339" , 0x1180080e00a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP340" , 0x1180080e00aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP341" , 0x1180080e00aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP342" , 0x1180080e00ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP343" , 0x1180080e00ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP344" , 0x1180080e00ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP345" , 0x1180080e00ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP346" , 0x1180080e00ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP347" , 0x1180080e00ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP348" , 0x1180080e00ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP349" , 0x1180080e00ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP350" , 0x1180080e00af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP351" , 0x1180080e00af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP352" , 0x1180080e00b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP353" , 0x1180080e00b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP354" , 0x1180080e00b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP355" , 0x1180080e00b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP356" , 0x1180080e00b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP357" , 0x1180080e00b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP358" , 0x1180080e00b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP359" , 0x1180080e00b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP360" , 0x1180080e00b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP361" , 0x1180080e00b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP362" , 0x1180080e00b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP363" , 0x1180080e00b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP364" , 0x1180080e00b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP365" , 0x1180080e00b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP366" , 0x1180080e00b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP367" , 0x1180080e00b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP368" , 0x1180080e00b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP369" , 0x1180080e00b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP370" , 0x1180080e00b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP371" , 0x1180080e00b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP372" , 0x1180080e00ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP373" , 0x1180080e00ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP374" , 0x1180080e00bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP375" , 0x1180080e00bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP376" , 0x1180080e00bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP377" , 0x1180080e00bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP378" , 0x1180080e00bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP379" , 0x1180080e00bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP380" , 0x1180080e00be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP381" , 0x1180080e00be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP382" , 0x1180080e00bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP383" , 0x1180080e00bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP384" , 0x1180080e00c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP385" , 0x1180080e00c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP386" , 0x1180080e00c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP387" , 0x1180080e00c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP388" , 0x1180080e00c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP389" , 0x1180080e00c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP390" , 0x1180080e00c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP391" , 0x1180080e00c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP392" , 0x1180080e00c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP393" , 0x1180080e00c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP394" , 0x1180080e00c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP395" , 0x1180080e00c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP396" , 0x1180080e00c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP397" , 0x1180080e00c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP398" , 0x1180080e00c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP399" , 0x1180080e00c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP400" , 0x1180080e00c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP401" , 0x1180080e00c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP402" , 0x1180080e00c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP403" , 0x1180080e00c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP404" , 0x1180080e00ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP405" , 0x1180080e00ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP406" , 0x1180080e00cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP407" , 0x1180080e00cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP408" , 0x1180080e00cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP409" , 0x1180080e00cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP410" , 0x1180080e00cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP411" , 0x1180080e00cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP412" , 0x1180080e00ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP413" , 0x1180080e00ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP414" , 0x1180080e00cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP415" , 0x1180080e00cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP416" , 0x1180080e00d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP417" , 0x1180080e00d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP418" , 0x1180080e00d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP419" , 0x1180080e00d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP420" , 0x1180080e00d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP421" , 0x1180080e00d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP422" , 0x1180080e00d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP423" , 0x1180080e00d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP424" , 0x1180080e00d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP425" , 0x1180080e00d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP426" , 0x1180080e00d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP427" , 0x1180080e00d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP428" , 0x1180080e00d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP429" , 0x1180080e00d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP430" , 0x1180080e00d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP431" , 0x1180080e00d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP432" , 0x1180080e00d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP433" , 0x1180080e00d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP434" , 0x1180080e00d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP435" , 0x1180080e00d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP436" , 0x1180080e00da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP437" , 0x1180080e00da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP438" , 0x1180080e00db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP439" , 0x1180080e00db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP440" , 0x1180080e00dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP441" , 0x1180080e00dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP442" , 0x1180080e00dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP443" , 0x1180080e00dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP444" , 0x1180080e00de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP445" , 0x1180080e00de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP446" , 0x1180080e00df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP447" , 0x1180080e00df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP448" , 0x1180080e00e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP449" , 0x1180080e00e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP450" , 0x1180080e00e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP451" , 0x1180080e00e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP452" , 0x1180080e00e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP453" , 0x1180080e00e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP454" , 0x1180080e00e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP455" , 0x1180080e00e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP456" , 0x1180080e00e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP457" , 0x1180080e00e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP458" , 0x1180080e00e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP459" , 0x1180080e00e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP460" , 0x1180080e00e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP461" , 0x1180080e00e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP462" , 0x1180080e00e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP463" , 0x1180080e00e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP464" , 0x1180080e00e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP465" , 0x1180080e00e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP466" , 0x1180080e00e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP467" , 0x1180080e00e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP468" , 0x1180080e00ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP469" , 0x1180080e00ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP470" , 0x1180080e00eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP471" , 0x1180080e00eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP472" , 0x1180080e00ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP473" , 0x1180080e00ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP474" , 0x1180080e00ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP475" , 0x1180080e00ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP476" , 0x1180080e00ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP477" , 0x1180080e00ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP478" , 0x1180080e00ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP479" , 0x1180080e00ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP480" , 0x1180080e00f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP481" , 0x1180080e00f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP482" , 0x1180080e00f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP483" , 0x1180080e00f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP484" , 0x1180080e00f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP485" , 0x1180080e00f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP486" , 0x1180080e00f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP487" , 0x1180080e00f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP488" , 0x1180080e00f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP489" , 0x1180080e00f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP490" , 0x1180080e00f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP491" , 0x1180080e00f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP492" , 0x1180080e00f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP493" , 0x1180080e00f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP494" , 0x1180080e00f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP495" , 0x1180080e00f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP496" , 0x1180080e00f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP497" , 0x1180080e00f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP498" , 0x1180080e00f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP499" , 0x1180080e00f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP500" , 0x1180080e00fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP501" , 0x1180080e00fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP502" , 0x1180080e00fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP503" , 0x1180080e00fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP504" , 0x1180080e00fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP505" , 0x1180080e00fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP506" , 0x1180080e00fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP507" , 0x1180080e00fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP508" , 0x1180080e00fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP509" , 0x1180080e00fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP510" , 0x1180080e00ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP511" , 0x1180080e00ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP512" , 0x1180080e01000ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP513" , 0x1180080e01008ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP514" , 0x1180080e01010ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP515" , 0x1180080e01018ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP516" , 0x1180080e01020ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP517" , 0x1180080e01028ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP518" , 0x1180080e01030ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP519" , 0x1180080e01038ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP520" , 0x1180080e01040ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP521" , 0x1180080e01048ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP522" , 0x1180080e01050ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP523" , 0x1180080e01058ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP524" , 0x1180080e01060ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP525" , 0x1180080e01068ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP526" , 0x1180080e01070ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP527" , 0x1180080e01078ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP528" , 0x1180080e01080ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP529" , 0x1180080e01088ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP530" , 0x1180080e01090ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP531" , 0x1180080e01098ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP532" , 0x1180080e010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP533" , 0x1180080e010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP534" , 0x1180080e010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP535" , 0x1180080e010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP536" , 0x1180080e010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP537" , 0x1180080e010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP538" , 0x1180080e010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP539" , 0x1180080e010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP540" , 0x1180080e010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP541" , 0x1180080e010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP542" , 0x1180080e010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP543" , 0x1180080e010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP544" , 0x1180080e01100ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP545" , 0x1180080e01108ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP546" , 0x1180080e01110ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP547" , 0x1180080e01118ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP548" , 0x1180080e01120ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP549" , 0x1180080e01128ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP550" , 0x1180080e01130ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP551" , 0x1180080e01138ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP552" , 0x1180080e01140ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP553" , 0x1180080e01148ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP554" , 0x1180080e01150ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP555" , 0x1180080e01158ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP556" , 0x1180080e01160ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP557" , 0x1180080e01168ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP558" , 0x1180080e01170ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP559" , 0x1180080e01178ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP560" , 0x1180080e01180ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP561" , 0x1180080e01188ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP562" , 0x1180080e01190ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP563" , 0x1180080e01198ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP564" , 0x1180080e011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP565" , 0x1180080e011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP566" , 0x1180080e011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP567" , 0x1180080e011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP568" , 0x1180080e011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP569" , 0x1180080e011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP570" , 0x1180080e011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP571" , 0x1180080e011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP572" , 0x1180080e011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP573" , 0x1180080e011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP574" , 0x1180080e011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP575" , 0x1180080e011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP576" , 0x1180080e01200ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP577" , 0x1180080e01208ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP578" , 0x1180080e01210ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP579" , 0x1180080e01218ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP580" , 0x1180080e01220ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP581" , 0x1180080e01228ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP582" , 0x1180080e01230ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP583" , 0x1180080e01238ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP584" , 0x1180080e01240ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP585" , 0x1180080e01248ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP586" , 0x1180080e01250ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP587" , 0x1180080e01258ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP588" , 0x1180080e01260ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP589" , 0x1180080e01268ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP590" , 0x1180080e01270ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP591" , 0x1180080e01278ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP592" , 0x1180080e01280ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP593" , 0x1180080e01288ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP594" , 0x1180080e01290ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP595" , 0x1180080e01298ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP596" , 0x1180080e012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP597" , 0x1180080e012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP598" , 0x1180080e012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP599" , 0x1180080e012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP600" , 0x1180080e012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP601" , 0x1180080e012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP602" , 0x1180080e012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP603" , 0x1180080e012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP604" , 0x1180080e012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP605" , 0x1180080e012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP606" , 0x1180080e012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP607" , 0x1180080e012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP608" , 0x1180080e01300ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP609" , 0x1180080e01308ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP610" , 0x1180080e01310ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP611" , 0x1180080e01318ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP612" , 0x1180080e01320ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP613" , 0x1180080e01328ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP614" , 0x1180080e01330ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP615" , 0x1180080e01338ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP616" , 0x1180080e01340ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP617" , 0x1180080e01348ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP618" , 0x1180080e01350ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP619" , 0x1180080e01358ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP620" , 0x1180080e01360ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP621" , 0x1180080e01368ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP622" , 0x1180080e01370ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP623" , 0x1180080e01378ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP624" , 0x1180080e01380ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP625" , 0x1180080e01388ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP626" , 0x1180080e01390ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP627" , 0x1180080e01398ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP628" , 0x1180080e013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP629" , 0x1180080e013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP630" , 0x1180080e013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP631" , 0x1180080e013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP632" , 0x1180080e013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP633" , 0x1180080e013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP634" , 0x1180080e013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP635" , 0x1180080e013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP636" , 0x1180080e013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP637" , 0x1180080e013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP638" , 0x1180080e013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP639" , 0x1180080e013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP640" , 0x1180080e01400ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP641" , 0x1180080e01408ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP642" , 0x1180080e01410ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP643" , 0x1180080e01418ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP644" , 0x1180080e01420ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP645" , 0x1180080e01428ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP646" , 0x1180080e01430ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP647" , 0x1180080e01438ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP648" , 0x1180080e01440ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP649" , 0x1180080e01448ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP650" , 0x1180080e01450ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP651" , 0x1180080e01458ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP652" , 0x1180080e01460ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP653" , 0x1180080e01468ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP654" , 0x1180080e01470ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP655" , 0x1180080e01478ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP656" , 0x1180080e01480ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP657" , 0x1180080e01488ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP658" , 0x1180080e01490ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP659" , 0x1180080e01498ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP660" , 0x1180080e014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP661" , 0x1180080e014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP662" , 0x1180080e014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP663" , 0x1180080e014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP664" , 0x1180080e014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP665" , 0x1180080e014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP666" , 0x1180080e014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP667" , 0x1180080e014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP668" , 0x1180080e014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP669" , 0x1180080e014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP670" , 0x1180080e014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP671" , 0x1180080e014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP672" , 0x1180080e01500ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP673" , 0x1180080e01508ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP674" , 0x1180080e01510ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP675" , 0x1180080e01518ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP676" , 0x1180080e01520ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP677" , 0x1180080e01528ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP678" , 0x1180080e01530ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP679" , 0x1180080e01538ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP680" , 0x1180080e01540ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP681" , 0x1180080e01548ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP682" , 0x1180080e01550ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP683" , 0x1180080e01558ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP684" , 0x1180080e01560ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP685" , 0x1180080e01568ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP686" , 0x1180080e01570ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP687" , 0x1180080e01578ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP688" , 0x1180080e01580ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP689" , 0x1180080e01588ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP690" , 0x1180080e01590ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP691" , 0x1180080e01598ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP692" , 0x1180080e015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP693" , 0x1180080e015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP694" , 0x1180080e015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP695" , 0x1180080e015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP696" , 0x1180080e015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP697" , 0x1180080e015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP698" , 0x1180080e015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP699" , 0x1180080e015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP700" , 0x1180080e015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP701" , 0x1180080e015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP702" , 0x1180080e015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP703" , 0x1180080e015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP704" , 0x1180080e01600ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP705" , 0x1180080e01608ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP706" , 0x1180080e01610ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP707" , 0x1180080e01618ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP708" , 0x1180080e01620ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP709" , 0x1180080e01628ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP710" , 0x1180080e01630ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP711" , 0x1180080e01638ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP712" , 0x1180080e01640ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP713" , 0x1180080e01648ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP714" , 0x1180080e01650ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP715" , 0x1180080e01658ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP716" , 0x1180080e01660ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP717" , 0x1180080e01668ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP718" , 0x1180080e01670ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP719" , 0x1180080e01678ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP720" , 0x1180080e01680ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP721" , 0x1180080e01688ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP722" , 0x1180080e01690ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP723" , 0x1180080e01698ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP724" , 0x1180080e016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP725" , 0x1180080e016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP726" , 0x1180080e016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP727" , 0x1180080e016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP728" , 0x1180080e016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP729" , 0x1180080e016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP730" , 0x1180080e016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP731" , 0x1180080e016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP732" , 0x1180080e016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP733" , 0x1180080e016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP734" , 0x1180080e016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP735" , 0x1180080e016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP736" , 0x1180080e01700ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP737" , 0x1180080e01708ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP738" , 0x1180080e01710ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP739" , 0x1180080e01718ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP740" , 0x1180080e01720ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP741" , 0x1180080e01728ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP742" , 0x1180080e01730ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP743" , 0x1180080e01738ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP744" , 0x1180080e01740ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP745" , 0x1180080e01748ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP746" , 0x1180080e01750ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP747" , 0x1180080e01758ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP748" , 0x1180080e01760ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP749" , 0x1180080e01768ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP750" , 0x1180080e01770ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP751" , 0x1180080e01778ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP752" , 0x1180080e01780ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP753" , 0x1180080e01788ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP754" , 0x1180080e01790ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP755" , 0x1180080e01798ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP756" , 0x1180080e017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP757" , 0x1180080e017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP758" , 0x1180080e017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP759" , 0x1180080e017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP760" , 0x1180080e017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP761" , 0x1180080e017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP762" , 0x1180080e017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP763" , 0x1180080e017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP764" , 0x1180080e017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP765" , 0x1180080e017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP766" , 0x1180080e017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP767" , 0x1180080e017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP768" , 0x1180080e01800ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP769" , 0x1180080e01808ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP770" , 0x1180080e01810ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP771" , 0x1180080e01818ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP772" , 0x1180080e01820ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP773" , 0x1180080e01828ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP774" , 0x1180080e01830ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP775" , 0x1180080e01838ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP776" , 0x1180080e01840ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP777" , 0x1180080e01848ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP778" , 0x1180080e01850ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP779" , 0x1180080e01858ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP780" , 0x1180080e01860ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP781" , 0x1180080e01868ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP782" , 0x1180080e01870ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP783" , 0x1180080e01878ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP784" , 0x1180080e01880ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP785" , 0x1180080e01888ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP786" , 0x1180080e01890ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP787" , 0x1180080e01898ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP788" , 0x1180080e018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP789" , 0x1180080e018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP790" , 0x1180080e018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP791" , 0x1180080e018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP792" , 0x1180080e018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP793" , 0x1180080e018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP794" , 0x1180080e018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP795" , 0x1180080e018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP796" , 0x1180080e018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP797" , 0x1180080e018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP798" , 0x1180080e018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP799" , 0x1180080e018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP800" , 0x1180080e01900ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP801" , 0x1180080e01908ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP802" , 0x1180080e01910ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP803" , 0x1180080e01918ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP804" , 0x1180080e01920ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP805" , 0x1180080e01928ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP806" , 0x1180080e01930ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP807" , 0x1180080e01938ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP808" , 0x1180080e01940ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP809" , 0x1180080e01948ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP810" , 0x1180080e01950ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP811" , 0x1180080e01958ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP812" , 0x1180080e01960ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP813" , 0x1180080e01968ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP814" , 0x1180080e01970ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP815" , 0x1180080e01978ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP816" , 0x1180080e01980ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP817" , 0x1180080e01988ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP818" , 0x1180080e01990ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP819" , 0x1180080e01998ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP820" , 0x1180080e019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP821" , 0x1180080e019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP822" , 0x1180080e019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP823" , 0x1180080e019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP824" , 0x1180080e019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP825" , 0x1180080e019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP826" , 0x1180080e019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP827" , 0x1180080e019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP828" , 0x1180080e019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP829" , 0x1180080e019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP830" , 0x1180080e019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP831" , 0x1180080e019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP832" , 0x1180080e01a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP833" , 0x1180080e01a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP834" , 0x1180080e01a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP835" , 0x1180080e01a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP836" , 0x1180080e01a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP837" , 0x1180080e01a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP838" , 0x1180080e01a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP839" , 0x1180080e01a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP840" , 0x1180080e01a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP841" , 0x1180080e01a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP842" , 0x1180080e01a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP843" , 0x1180080e01a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP844" , 0x1180080e01a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP845" , 0x1180080e01a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP846" , 0x1180080e01a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP847" , 0x1180080e01a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP848" , 0x1180080e01a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP849" , 0x1180080e01a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP850" , 0x1180080e01a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP851" , 0x1180080e01a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP852" , 0x1180080e01aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP853" , 0x1180080e01aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP854" , 0x1180080e01ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP855" , 0x1180080e01ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP856" , 0x1180080e01ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP857" , 0x1180080e01ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP858" , 0x1180080e01ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP859" , 0x1180080e01ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP860" , 0x1180080e01ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP861" , 0x1180080e01ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP862" , 0x1180080e01af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP863" , 0x1180080e01af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP864" , 0x1180080e01b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP865" , 0x1180080e01b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP866" , 0x1180080e01b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP867" , 0x1180080e01b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP868" , 0x1180080e01b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP869" , 0x1180080e01b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP870" , 0x1180080e01b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP871" , 0x1180080e01b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP872" , 0x1180080e01b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP873" , 0x1180080e01b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP874" , 0x1180080e01b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP875" , 0x1180080e01b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP876" , 0x1180080e01b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP877" , 0x1180080e01b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP878" , 0x1180080e01b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP879" , 0x1180080e01b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP880" , 0x1180080e01b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP881" , 0x1180080e01b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP882" , 0x1180080e01b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP883" , 0x1180080e01b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP884" , 0x1180080e01ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP885" , 0x1180080e01ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP886" , 0x1180080e01bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP887" , 0x1180080e01bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP888" , 0x1180080e01bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP889" , 0x1180080e01bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP890" , 0x1180080e01bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP891" , 0x1180080e01bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP892" , 0x1180080e01be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP893" , 0x1180080e01be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP894" , 0x1180080e01bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP895" , 0x1180080e01bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP896" , 0x1180080e01c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP897" , 0x1180080e01c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP898" , 0x1180080e01c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP899" , 0x1180080e01c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP900" , 0x1180080e01c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP901" , 0x1180080e01c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP902" , 0x1180080e01c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP903" , 0x1180080e01c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP904" , 0x1180080e01c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP905" , 0x1180080e01c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP906" , 0x1180080e01c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP907" , 0x1180080e01c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP908" , 0x1180080e01c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP909" , 0x1180080e01c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP910" , 0x1180080e01c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP911" , 0x1180080e01c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP912" , 0x1180080e01c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP913" , 0x1180080e01c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP914" , 0x1180080e01c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP915" , 0x1180080e01c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP916" , 0x1180080e01ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP917" , 0x1180080e01ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP918" , 0x1180080e01cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP919" , 0x1180080e01cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP920" , 0x1180080e01cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP921" , 0x1180080e01cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP922" , 0x1180080e01cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP923" , 0x1180080e01cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP924" , 0x1180080e01ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP925" , 0x1180080e01ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP926" , 0x1180080e01cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP927" , 0x1180080e01cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP928" , 0x1180080e01d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP929" , 0x1180080e01d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP930" , 0x1180080e01d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP931" , 0x1180080e01d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP932" , 0x1180080e01d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP933" , 0x1180080e01d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP934" , 0x1180080e01d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP935" , 0x1180080e01d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP936" , 0x1180080e01d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP937" , 0x1180080e01d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP938" , 0x1180080e01d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP939" , 0x1180080e01d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP940" , 0x1180080e01d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP941" , 0x1180080e01d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP942" , 0x1180080e01d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP943" , 0x1180080e01d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP944" , 0x1180080e01d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP945" , 0x1180080e01d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP946" , 0x1180080e01d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP947" , 0x1180080e01d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP948" , 0x1180080e01da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP949" , 0x1180080e01da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP950" , 0x1180080e01db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP951" , 0x1180080e01db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP952" , 0x1180080e01dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP953" , 0x1180080e01dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP954" , 0x1180080e01dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP955" , 0x1180080e01dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP956" , 0x1180080e01de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP957" , 0x1180080e01de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP958" , 0x1180080e01df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP959" , 0x1180080e01df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP960" , 0x1180080e01e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP961" , 0x1180080e01e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP962" , 0x1180080e01e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP963" , 0x1180080e01e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP964" , 0x1180080e01e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP965" , 0x1180080e01e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP966" , 0x1180080e01e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP967" , 0x1180080e01e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP968" , 0x1180080e01e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP969" , 0x1180080e01e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP970" , 0x1180080e01e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP971" , 0x1180080e01e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP972" , 0x1180080e01e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP973" , 0x1180080e01e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP974" , 0x1180080e01e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP975" , 0x1180080e01e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP976" , 0x1180080e01e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP977" , 0x1180080e01e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP978" , 0x1180080e01e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP979" , 0x1180080e01e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP980" , 0x1180080e01ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP981" , 0x1180080e01ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP982" , 0x1180080e01eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP983" , 0x1180080e01eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP984" , 0x1180080e01ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP985" , 0x1180080e01ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP986" , 0x1180080e01ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP987" , 0x1180080e01ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP988" , 0x1180080e01ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP989" , 0x1180080e01ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP990" , 0x1180080e01ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP991" , 0x1180080e01ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP992" , 0x1180080e01f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP993" , 0x1180080e01f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP994" , 0x1180080e01f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP995" , 0x1180080e01f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP996" , 0x1180080e01f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP997" , 0x1180080e01f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP998" , 0x1180080e01f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP999" , 0x1180080e01f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1000" , 0x1180080e01f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1001" , 0x1180080e01f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1002" , 0x1180080e01f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1003" , 0x1180080e01f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1004" , 0x1180080e01f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1005" , 0x1180080e01f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1006" , 0x1180080e01f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1007" , 0x1180080e01f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1008" , 0x1180080e01f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1009" , 0x1180080e01f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1010" , 0x1180080e01f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1011" , 0x1180080e01f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1012" , 0x1180080e01fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1013" , 0x1180080e01fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1014" , 0x1180080e01fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1015" , 0x1180080e01fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1016" , 0x1180080e01fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1017" , 0x1180080e01fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1018" , 0x1180080e01fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1019" , 0x1180080e01fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1020" , 0x1180080e01fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1021" , 0x1180080e01fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1022" , 0x1180080e01ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1023" , 0x1180080e01ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1024" , 0x1180080e02000ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1025" , 0x1180080e02008ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1026" , 0x1180080e02010ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1027" , 0x1180080e02018ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1028" , 0x1180080e02020ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1029" , 0x1180080e02028ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1030" , 0x1180080e02030ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1031" , 0x1180080e02038ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1032" , 0x1180080e02040ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1033" , 0x1180080e02048ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1034" , 0x1180080e02050ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1035" , 0x1180080e02058ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1036" , 0x1180080e02060ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1037" , 0x1180080e02068ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1038" , 0x1180080e02070ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1039" , 0x1180080e02078ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1040" , 0x1180080e02080ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1041" , 0x1180080e02088ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1042" , 0x1180080e02090ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1043" , 0x1180080e02098ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1044" , 0x1180080e020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1045" , 0x1180080e020a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1046" , 0x1180080e020b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1047" , 0x1180080e020b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1048" , 0x1180080e020c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1049" , 0x1180080e020c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1050" , 0x1180080e020d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1051" , 0x1180080e020d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1052" , 0x1180080e020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1053" , 0x1180080e020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1054" , 0x1180080e020f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1055" , 0x1180080e020f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1056" , 0x1180080e02100ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1057" , 0x1180080e02108ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1058" , 0x1180080e02110ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1059" , 0x1180080e02118ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1060" , 0x1180080e02120ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1061" , 0x1180080e02128ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1062" , 0x1180080e02130ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1063" , 0x1180080e02138ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1064" , 0x1180080e02140ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1065" , 0x1180080e02148ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1066" , 0x1180080e02150ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1067" , 0x1180080e02158ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1068" , 0x1180080e02160ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1069" , 0x1180080e02168ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1070" , 0x1180080e02170ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1071" , 0x1180080e02178ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1072" , 0x1180080e02180ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1073" , 0x1180080e02188ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1074" , 0x1180080e02190ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1075" , 0x1180080e02198ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1076" , 0x1180080e021a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1077" , 0x1180080e021a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1078" , 0x1180080e021b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1079" , 0x1180080e021b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1080" , 0x1180080e021c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1081" , 0x1180080e021c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1082" , 0x1180080e021d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1083" , 0x1180080e021d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1084" , 0x1180080e021e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1085" , 0x1180080e021e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1086" , 0x1180080e021f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1087" , 0x1180080e021f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1088" , 0x1180080e02200ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1089" , 0x1180080e02208ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1090" , 0x1180080e02210ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1091" , 0x1180080e02218ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1092" , 0x1180080e02220ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1093" , 0x1180080e02228ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1094" , 0x1180080e02230ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1095" , 0x1180080e02238ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1096" , 0x1180080e02240ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1097" , 0x1180080e02248ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1098" , 0x1180080e02250ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1099" , 0x1180080e02258ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1100" , 0x1180080e02260ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1101" , 0x1180080e02268ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1102" , 0x1180080e02270ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1103" , 0x1180080e02278ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1104" , 0x1180080e02280ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1105" , 0x1180080e02288ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1106" , 0x1180080e02290ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1107" , 0x1180080e02298ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1108" , 0x1180080e022a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1109" , 0x1180080e022a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1110" , 0x1180080e022b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1111" , 0x1180080e022b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1112" , 0x1180080e022c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1113" , 0x1180080e022c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1114" , 0x1180080e022d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1115" , 0x1180080e022d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1116" , 0x1180080e022e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1117" , 0x1180080e022e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1118" , 0x1180080e022f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1119" , 0x1180080e022f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1120" , 0x1180080e02300ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1121" , 0x1180080e02308ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1122" , 0x1180080e02310ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1123" , 0x1180080e02318ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1124" , 0x1180080e02320ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1125" , 0x1180080e02328ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1126" , 0x1180080e02330ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1127" , 0x1180080e02338ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1128" , 0x1180080e02340ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1129" , 0x1180080e02348ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1130" , 0x1180080e02350ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1131" , 0x1180080e02358ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1132" , 0x1180080e02360ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1133" , 0x1180080e02368ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1134" , 0x1180080e02370ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1135" , 0x1180080e02378ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1136" , 0x1180080e02380ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1137" , 0x1180080e02388ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1138" , 0x1180080e02390ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1139" , 0x1180080e02398ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1140" , 0x1180080e023a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1141" , 0x1180080e023a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1142" , 0x1180080e023b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1143" , 0x1180080e023b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1144" , 0x1180080e023c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1145" , 0x1180080e023c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1146" , 0x1180080e023d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1147" , 0x1180080e023d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1148" , 0x1180080e023e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1149" , 0x1180080e023e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1150" , 0x1180080e023f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1151" , 0x1180080e023f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1152" , 0x1180080e02400ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1153" , 0x1180080e02408ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1154" , 0x1180080e02410ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1155" , 0x1180080e02418ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1156" , 0x1180080e02420ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1157" , 0x1180080e02428ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1158" , 0x1180080e02430ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1159" , 0x1180080e02438ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1160" , 0x1180080e02440ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1161" , 0x1180080e02448ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1162" , 0x1180080e02450ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1163" , 0x1180080e02458ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1164" , 0x1180080e02460ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1165" , 0x1180080e02468ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1166" , 0x1180080e02470ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1167" , 0x1180080e02478ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1168" , 0x1180080e02480ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1169" , 0x1180080e02488ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1170" , 0x1180080e02490ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1171" , 0x1180080e02498ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1172" , 0x1180080e024a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1173" , 0x1180080e024a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1174" , 0x1180080e024b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1175" , 0x1180080e024b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1176" , 0x1180080e024c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1177" , 0x1180080e024c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1178" , 0x1180080e024d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1179" , 0x1180080e024d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1180" , 0x1180080e024e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1181" , 0x1180080e024e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1182" , 0x1180080e024f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1183" , 0x1180080e024f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1184" , 0x1180080e02500ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1185" , 0x1180080e02508ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1186" , 0x1180080e02510ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1187" , 0x1180080e02518ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1188" , 0x1180080e02520ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1189" , 0x1180080e02528ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1190" , 0x1180080e02530ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1191" , 0x1180080e02538ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1192" , 0x1180080e02540ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1193" , 0x1180080e02548ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1194" , 0x1180080e02550ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1195" , 0x1180080e02558ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1196" , 0x1180080e02560ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1197" , 0x1180080e02568ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1198" , 0x1180080e02570ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1199" , 0x1180080e02578ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1200" , 0x1180080e02580ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1201" , 0x1180080e02588ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1202" , 0x1180080e02590ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1203" , 0x1180080e02598ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1204" , 0x1180080e025a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1205" , 0x1180080e025a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1206" , 0x1180080e025b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1207" , 0x1180080e025b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1208" , 0x1180080e025c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1209" , 0x1180080e025c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1210" , 0x1180080e025d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1211" , 0x1180080e025d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1212" , 0x1180080e025e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1213" , 0x1180080e025e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1214" , 0x1180080e025f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1215" , 0x1180080e025f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1216" , 0x1180080e02600ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1217" , 0x1180080e02608ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1218" , 0x1180080e02610ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1219" , 0x1180080e02618ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1220" , 0x1180080e02620ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1221" , 0x1180080e02628ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1222" , 0x1180080e02630ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1223" , 0x1180080e02638ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1224" , 0x1180080e02640ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1225" , 0x1180080e02648ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1226" , 0x1180080e02650ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1227" , 0x1180080e02658ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1228" , 0x1180080e02660ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1229" , 0x1180080e02668ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1230" , 0x1180080e02670ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1231" , 0x1180080e02678ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1232" , 0x1180080e02680ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1233" , 0x1180080e02688ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1234" , 0x1180080e02690ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1235" , 0x1180080e02698ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1236" , 0x1180080e026a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1237" , 0x1180080e026a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1238" , 0x1180080e026b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1239" , 0x1180080e026b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1240" , 0x1180080e026c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1241" , 0x1180080e026c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1242" , 0x1180080e026d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1243" , 0x1180080e026d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1244" , 0x1180080e026e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1245" , 0x1180080e026e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1246" , 0x1180080e026f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1247" , 0x1180080e026f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1248" , 0x1180080e02700ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1249" , 0x1180080e02708ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1250" , 0x1180080e02710ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1251" , 0x1180080e02718ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1252" , 0x1180080e02720ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1253" , 0x1180080e02728ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1254" , 0x1180080e02730ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1255" , 0x1180080e02738ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1256" , 0x1180080e02740ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1257" , 0x1180080e02748ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1258" , 0x1180080e02750ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1259" , 0x1180080e02758ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1260" , 0x1180080e02760ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1261" , 0x1180080e02768ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1262" , 0x1180080e02770ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1263" , 0x1180080e02778ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1264" , 0x1180080e02780ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1265" , 0x1180080e02788ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1266" , 0x1180080e02790ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1267" , 0x1180080e02798ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1268" , 0x1180080e027a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1269" , 0x1180080e027a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1270" , 0x1180080e027b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1271" , 0x1180080e027b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1272" , 0x1180080e027c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1273" , 0x1180080e027c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1274" , 0x1180080e027d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1275" , 0x1180080e027d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1276" , 0x1180080e027e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1277" , 0x1180080e027e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1278" , 0x1180080e027f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1279" , 0x1180080e027f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1280" , 0x1180080e02800ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1281" , 0x1180080e02808ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1282" , 0x1180080e02810ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1283" , 0x1180080e02818ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1284" , 0x1180080e02820ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1285" , 0x1180080e02828ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1286" , 0x1180080e02830ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1287" , 0x1180080e02838ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1288" , 0x1180080e02840ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1289" , 0x1180080e02848ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1290" , 0x1180080e02850ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1291" , 0x1180080e02858ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1292" , 0x1180080e02860ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1293" , 0x1180080e02868ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1294" , 0x1180080e02870ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1295" , 0x1180080e02878ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1296" , 0x1180080e02880ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1297" , 0x1180080e02888ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1298" , 0x1180080e02890ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1299" , 0x1180080e02898ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1300" , 0x1180080e028a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1301" , 0x1180080e028a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1302" , 0x1180080e028b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1303" , 0x1180080e028b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1304" , 0x1180080e028c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1305" , 0x1180080e028c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1306" , 0x1180080e028d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1307" , 0x1180080e028d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1308" , 0x1180080e028e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1309" , 0x1180080e028e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1310" , 0x1180080e028f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1311" , 0x1180080e028f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1312" , 0x1180080e02900ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1313" , 0x1180080e02908ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1314" , 0x1180080e02910ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1315" , 0x1180080e02918ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1316" , 0x1180080e02920ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1317" , 0x1180080e02928ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1318" , 0x1180080e02930ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1319" , 0x1180080e02938ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1320" , 0x1180080e02940ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1321" , 0x1180080e02948ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1322" , 0x1180080e02950ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1323" , 0x1180080e02958ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1324" , 0x1180080e02960ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1325" , 0x1180080e02968ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1326" , 0x1180080e02970ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1327" , 0x1180080e02978ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1328" , 0x1180080e02980ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1329" , 0x1180080e02988ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1330" , 0x1180080e02990ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1331" , 0x1180080e02998ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1332" , 0x1180080e029a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1333" , 0x1180080e029a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1334" , 0x1180080e029b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1335" , 0x1180080e029b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1336" , 0x1180080e029c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1337" , 0x1180080e029c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1338" , 0x1180080e029d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1339" , 0x1180080e029d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1340" , 0x1180080e029e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1341" , 0x1180080e029e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1342" , 0x1180080e029f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1343" , 0x1180080e029f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1344" , 0x1180080e02a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1345" , 0x1180080e02a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1346" , 0x1180080e02a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1347" , 0x1180080e02a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1348" , 0x1180080e02a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1349" , 0x1180080e02a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1350" , 0x1180080e02a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1351" , 0x1180080e02a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1352" , 0x1180080e02a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1353" , 0x1180080e02a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1354" , 0x1180080e02a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1355" , 0x1180080e02a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1356" , 0x1180080e02a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1357" , 0x1180080e02a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1358" , 0x1180080e02a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1359" , 0x1180080e02a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1360" , 0x1180080e02a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1361" , 0x1180080e02a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1362" , 0x1180080e02a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1363" , 0x1180080e02a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1364" , 0x1180080e02aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1365" , 0x1180080e02aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1366" , 0x1180080e02ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1367" , 0x1180080e02ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1368" , 0x1180080e02ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1369" , 0x1180080e02ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1370" , 0x1180080e02ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1371" , 0x1180080e02ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1372" , 0x1180080e02ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1373" , 0x1180080e02ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1374" , 0x1180080e02af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1375" , 0x1180080e02af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1376" , 0x1180080e02b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1377" , 0x1180080e02b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1378" , 0x1180080e02b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1379" , 0x1180080e02b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1380" , 0x1180080e02b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1381" , 0x1180080e02b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1382" , 0x1180080e02b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1383" , 0x1180080e02b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1384" , 0x1180080e02b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1385" , 0x1180080e02b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1386" , 0x1180080e02b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1387" , 0x1180080e02b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1388" , 0x1180080e02b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1389" , 0x1180080e02b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1390" , 0x1180080e02b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1391" , 0x1180080e02b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1392" , 0x1180080e02b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1393" , 0x1180080e02b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1394" , 0x1180080e02b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1395" , 0x1180080e02b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1396" , 0x1180080e02ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1397" , 0x1180080e02ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1398" , 0x1180080e02bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1399" , 0x1180080e02bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1400" , 0x1180080e02bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1401" , 0x1180080e02bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1402" , 0x1180080e02bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1403" , 0x1180080e02bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1404" , 0x1180080e02be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1405" , 0x1180080e02be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1406" , 0x1180080e02bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1407" , 0x1180080e02bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1408" , 0x1180080e02c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1409" , 0x1180080e02c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1410" , 0x1180080e02c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1411" , 0x1180080e02c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1412" , 0x1180080e02c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1413" , 0x1180080e02c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1414" , 0x1180080e02c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1415" , 0x1180080e02c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1416" , 0x1180080e02c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1417" , 0x1180080e02c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1418" , 0x1180080e02c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1419" , 0x1180080e02c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1420" , 0x1180080e02c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1421" , 0x1180080e02c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1422" , 0x1180080e02c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1423" , 0x1180080e02c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1424" , 0x1180080e02c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1425" , 0x1180080e02c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1426" , 0x1180080e02c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1427" , 0x1180080e02c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1428" , 0x1180080e02ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1429" , 0x1180080e02ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1430" , 0x1180080e02cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1431" , 0x1180080e02cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1432" , 0x1180080e02cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1433" , 0x1180080e02cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1434" , 0x1180080e02cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1435" , 0x1180080e02cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1436" , 0x1180080e02ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1437" , 0x1180080e02ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1438" , 0x1180080e02cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1439" , 0x1180080e02cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1440" , 0x1180080e02d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1441" , 0x1180080e02d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1442" , 0x1180080e02d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1443" , 0x1180080e02d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1444" , 0x1180080e02d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1445" , 0x1180080e02d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1446" , 0x1180080e02d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1447" , 0x1180080e02d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1448" , 0x1180080e02d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1449" , 0x1180080e02d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1450" , 0x1180080e02d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1451" , 0x1180080e02d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1452" , 0x1180080e02d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1453" , 0x1180080e02d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1454" , 0x1180080e02d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1455" , 0x1180080e02d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1456" , 0x1180080e02d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1457" , 0x1180080e02d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1458" , 0x1180080e02d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1459" , 0x1180080e02d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1460" , 0x1180080e02da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1461" , 0x1180080e02da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1462" , 0x1180080e02db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1463" , 0x1180080e02db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1464" , 0x1180080e02dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1465" , 0x1180080e02dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1466" , 0x1180080e02dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1467" , 0x1180080e02dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1468" , 0x1180080e02de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1469" , 0x1180080e02de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1470" , 0x1180080e02df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1471" , 0x1180080e02df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1472" , 0x1180080e02e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1473" , 0x1180080e02e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1474" , 0x1180080e02e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1475" , 0x1180080e02e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1476" , 0x1180080e02e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1477" , 0x1180080e02e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1478" , 0x1180080e02e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1479" , 0x1180080e02e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1480" , 0x1180080e02e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1481" , 0x1180080e02e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1482" , 0x1180080e02e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1483" , 0x1180080e02e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1484" , 0x1180080e02e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1485" , 0x1180080e02e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1486" , 0x1180080e02e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1487" , 0x1180080e02e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1488" , 0x1180080e02e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1489" , 0x1180080e02e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1490" , 0x1180080e02e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1491" , 0x1180080e02e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1492" , 0x1180080e02ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1493" , 0x1180080e02ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1494" , 0x1180080e02eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1495" , 0x1180080e02eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1496" , 0x1180080e02ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1497" , 0x1180080e02ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1498" , 0x1180080e02ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1499" , 0x1180080e02ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1500" , 0x1180080e02ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1501" , 0x1180080e02ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1502" , 0x1180080e02ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1503" , 0x1180080e02ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1504" , 0x1180080e02f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1505" , 0x1180080e02f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1506" , 0x1180080e02f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1507" , 0x1180080e02f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1508" , 0x1180080e02f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1509" , 0x1180080e02f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1510" , 0x1180080e02f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1511" , 0x1180080e02f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1512" , 0x1180080e02f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1513" , 0x1180080e02f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1514" , 0x1180080e02f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1515" , 0x1180080e02f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1516" , 0x1180080e02f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1517" , 0x1180080e02f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1518" , 0x1180080e02f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1519" , 0x1180080e02f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1520" , 0x1180080e02f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1521" , 0x1180080e02f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1522" , 0x1180080e02f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1523" , 0x1180080e02f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1524" , 0x1180080e02fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1525" , 0x1180080e02fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1526" , 0x1180080e02fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1527" , 0x1180080e02fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1528" , 0x1180080e02fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1529" , 0x1180080e02fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1530" , 0x1180080e02fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1531" , 0x1180080e02fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1532" , 0x1180080e02fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1533" , 0x1180080e02fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1534" , 0x1180080e02ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_DUT_MAP1535" , 0x1180080e02ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_ERR_TDT0" , 0x1180080a007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"L2C_ERR_TTG0" , 0x1180080a007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"L2C_ERR_VBF0" , 0x1180080c007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"L2C_ERR_XMC" , 0x11800808007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_INT_ENA" , 0x1180080800020ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"L2C_INT_REG" , 0x1180080800018ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_IOC0_PFC" , 0x1180080800420ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"L2C_IOR0_PFC" , 0x1180080800428ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"L2C_QOS_IOB0" , 0x1180080880200ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"L2C_QOS_PP0" , 0x1180080880000ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"L2C_QOS_PP1" , 0x1180080880008ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"L2C_QOS_PP2" , 0x1180080880010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"L2C_QOS_PP3" , 0x1180080880018ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"L2C_QOS_PP4" , 0x1180080880020ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"L2C_QOS_PP5" , 0x1180080880028ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"L2C_QOS_WGT" , 0x1180080800008ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"L2C_RSC0_PFC" , 0x1180080800410ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"L2C_RSD0_PFC" , 0x1180080800418ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"L2C_TAD0_ECC0" , 0x1180080a00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"L2C_TAD0_ECC1" , 0x1180080a00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"L2C_TAD0_IEN" , 0x1180080a00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_TAD0_PFC0" , 0x1180080a00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"L2C_TAD0_PFC1" , 0x1180080a00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"L2C_TAD0_PFC2" , 0x1180080a00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"L2C_TAD0_PFC3" , 0x1180080a00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"L2C_TAD0_PRF" , 0x1180080a00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"L2C_TAD0_TAG" , 0x1180080a00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"L2C_VER_ID" , 0x11800808007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"L2C_VER_IOB" , 0x11800808007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"L2C_VER_PP" , 0x11800808007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"L2C_VIRTID_IOB0" , 0x11800808c0200ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"L2C_VIRTID_PP0" , 0x11800808c0000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"L2C_VIRTID_PP1" , 0x11800808c0008ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"L2C_VIRTID_PP2" , 0x11800808c0010ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"L2C_VIRTID_PP3" , 0x11800808c0018ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"L2C_VIRTID_PP4" , 0x11800808c0020ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"L2C_VIRTID_PP5" , 0x11800808c0028ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"L2C_VRT_CTL" , 0x1180080800010ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"L2C_VRT_MEM0" , 0x1180080900000ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1" , 0x1180080900008ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM2" , 0x1180080900010ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM3" , 0x1180080900018ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM4" , 0x1180080900020ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM5" , 0x1180080900028ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM6" , 0x1180080900030ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM7" , 0x1180080900038ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM8" , 0x1180080900040ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM9" , 0x1180080900048ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM10" , 0x1180080900050ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM11" , 0x1180080900058ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM12" , 0x1180080900060ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM13" , 0x1180080900068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM14" , 0x1180080900070ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM15" , 0x1180080900078ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM16" , 0x1180080900080ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM17" , 0x1180080900088ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM18" , 0x1180080900090ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM19" , 0x1180080900098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM20" , 0x11800809000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM21" , 0x11800809000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM22" , 0x11800809000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM23" , 0x11800809000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM24" , 0x11800809000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM25" , 0x11800809000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM26" , 0x11800809000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM27" , 0x11800809000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM28" , 0x11800809000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM29" , 0x11800809000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM30" , 0x11800809000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM31" , 0x11800809000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM32" , 0x1180080900100ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM33" , 0x1180080900108ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM34" , 0x1180080900110ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM35" , 0x1180080900118ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM36" , 0x1180080900120ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM37" , 0x1180080900128ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM38" , 0x1180080900130ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM39" , 0x1180080900138ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM40" , 0x1180080900140ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM41" , 0x1180080900148ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM42" , 0x1180080900150ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM43" , 0x1180080900158ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM44" , 0x1180080900160ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM45" , 0x1180080900168ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM46" , 0x1180080900170ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM47" , 0x1180080900178ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM48" , 0x1180080900180ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM49" , 0x1180080900188ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM50" , 0x1180080900190ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM51" , 0x1180080900198ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM52" , 0x11800809001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM53" , 0x11800809001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM54" , 0x11800809001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM55" , 0x11800809001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM56" , 0x11800809001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM57" , 0x11800809001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM58" , 0x11800809001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM59" , 0x11800809001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM60" , 0x11800809001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM61" , 0x11800809001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM62" , 0x11800809001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM63" , 0x11800809001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM64" , 0x1180080900200ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM65" , 0x1180080900208ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM66" , 0x1180080900210ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM67" , 0x1180080900218ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM68" , 0x1180080900220ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM69" , 0x1180080900228ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM70" , 0x1180080900230ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM71" , 0x1180080900238ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM72" , 0x1180080900240ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM73" , 0x1180080900248ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM74" , 0x1180080900250ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM75" , 0x1180080900258ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM76" , 0x1180080900260ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM77" , 0x1180080900268ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM78" , 0x1180080900270ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM79" , 0x1180080900278ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM80" , 0x1180080900280ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM81" , 0x1180080900288ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM82" , 0x1180080900290ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM83" , 0x1180080900298ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM84" , 0x11800809002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM85" , 0x11800809002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM86" , 0x11800809002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM87" , 0x11800809002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM88" , 0x11800809002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM89" , 0x11800809002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM90" , 0x11800809002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM91" , 0x11800809002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM92" , 0x11800809002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM93" , 0x11800809002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM94" , 0x11800809002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM95" , 0x11800809002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM96" , 0x1180080900300ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM97" , 0x1180080900308ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM98" , 0x1180080900310ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM99" , 0x1180080900318ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM100" , 0x1180080900320ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM101" , 0x1180080900328ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM102" , 0x1180080900330ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM103" , 0x1180080900338ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM104" , 0x1180080900340ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM105" , 0x1180080900348ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM106" , 0x1180080900350ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM107" , 0x1180080900358ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM108" , 0x1180080900360ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM109" , 0x1180080900368ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM110" , 0x1180080900370ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM111" , 0x1180080900378ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM112" , 0x1180080900380ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM113" , 0x1180080900388ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM114" , 0x1180080900390ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM115" , 0x1180080900398ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM116" , 0x11800809003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM117" , 0x11800809003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM118" , 0x11800809003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM119" , 0x11800809003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM120" , 0x11800809003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM121" , 0x11800809003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM122" , 0x11800809003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM123" , 0x11800809003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM124" , 0x11800809003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM125" , 0x11800809003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM126" , 0x11800809003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM127" , 0x11800809003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM128" , 0x1180080900400ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM129" , 0x1180080900408ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM130" , 0x1180080900410ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM131" , 0x1180080900418ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM132" , 0x1180080900420ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM133" , 0x1180080900428ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM134" , 0x1180080900430ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM135" , 0x1180080900438ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM136" , 0x1180080900440ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM137" , 0x1180080900448ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM138" , 0x1180080900450ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM139" , 0x1180080900458ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM140" , 0x1180080900460ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM141" , 0x1180080900468ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM142" , 0x1180080900470ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM143" , 0x1180080900478ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM144" , 0x1180080900480ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM145" , 0x1180080900488ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM146" , 0x1180080900490ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM147" , 0x1180080900498ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM148" , 0x11800809004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM149" , 0x11800809004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM150" , 0x11800809004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM151" , 0x11800809004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM152" , 0x11800809004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM153" , 0x11800809004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM154" , 0x11800809004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM155" , 0x11800809004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM156" , 0x11800809004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM157" , 0x11800809004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM158" , 0x11800809004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM159" , 0x11800809004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM160" , 0x1180080900500ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM161" , 0x1180080900508ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM162" , 0x1180080900510ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM163" , 0x1180080900518ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM164" , 0x1180080900520ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM165" , 0x1180080900528ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM166" , 0x1180080900530ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM167" , 0x1180080900538ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM168" , 0x1180080900540ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM169" , 0x1180080900548ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM170" , 0x1180080900550ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM171" , 0x1180080900558ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM172" , 0x1180080900560ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM173" , 0x1180080900568ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM174" , 0x1180080900570ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM175" , 0x1180080900578ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM176" , 0x1180080900580ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM177" , 0x1180080900588ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM178" , 0x1180080900590ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM179" , 0x1180080900598ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM180" , 0x11800809005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM181" , 0x11800809005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM182" , 0x11800809005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM183" , 0x11800809005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM184" , 0x11800809005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM185" , 0x11800809005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM186" , 0x11800809005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM187" , 0x11800809005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM188" , 0x11800809005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM189" , 0x11800809005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM190" , 0x11800809005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM191" , 0x11800809005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM192" , 0x1180080900600ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM193" , 0x1180080900608ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM194" , 0x1180080900610ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM195" , 0x1180080900618ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM196" , 0x1180080900620ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM197" , 0x1180080900628ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM198" , 0x1180080900630ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM199" , 0x1180080900638ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM200" , 0x1180080900640ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM201" , 0x1180080900648ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM202" , 0x1180080900650ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM203" , 0x1180080900658ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM204" , 0x1180080900660ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM205" , 0x1180080900668ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM206" , 0x1180080900670ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM207" , 0x1180080900678ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM208" , 0x1180080900680ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM209" , 0x1180080900688ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM210" , 0x1180080900690ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM211" , 0x1180080900698ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM212" , 0x11800809006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM213" , 0x11800809006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM214" , 0x11800809006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM215" , 0x11800809006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM216" , 0x11800809006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM217" , 0x11800809006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM218" , 0x11800809006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM219" , 0x11800809006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM220" , 0x11800809006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM221" , 0x11800809006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM222" , 0x11800809006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM223" , 0x11800809006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM224" , 0x1180080900700ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM225" , 0x1180080900708ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM226" , 0x1180080900710ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM227" , 0x1180080900718ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM228" , 0x1180080900720ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM229" , 0x1180080900728ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM230" , 0x1180080900730ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM231" , 0x1180080900738ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM232" , 0x1180080900740ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM233" , 0x1180080900748ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM234" , 0x1180080900750ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM235" , 0x1180080900758ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM236" , 0x1180080900760ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM237" , 0x1180080900768ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM238" , 0x1180080900770ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM239" , 0x1180080900778ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM240" , 0x1180080900780ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM241" , 0x1180080900788ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM242" , 0x1180080900790ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM243" , 0x1180080900798ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM244" , 0x11800809007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM245" , 0x11800809007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM246" , 0x11800809007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM247" , 0x11800809007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM248" , 0x11800809007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM249" , 0x11800809007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM250" , 0x11800809007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM251" , 0x11800809007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM252" , 0x11800809007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM253" , 0x11800809007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM254" , 0x11800809007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM255" , 0x11800809007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM256" , 0x1180080900800ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM257" , 0x1180080900808ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM258" , 0x1180080900810ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM259" , 0x1180080900818ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM260" , 0x1180080900820ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM261" , 0x1180080900828ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM262" , 0x1180080900830ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM263" , 0x1180080900838ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM264" , 0x1180080900840ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM265" , 0x1180080900848ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM266" , 0x1180080900850ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM267" , 0x1180080900858ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM268" , 0x1180080900860ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM269" , 0x1180080900868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM270" , 0x1180080900870ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM271" , 0x1180080900878ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM272" , 0x1180080900880ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM273" , 0x1180080900888ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM274" , 0x1180080900890ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM275" , 0x1180080900898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM276" , 0x11800809008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM277" , 0x11800809008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM278" , 0x11800809008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM279" , 0x11800809008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM280" , 0x11800809008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM281" , 0x11800809008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM282" , 0x11800809008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM283" , 0x11800809008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM284" , 0x11800809008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM285" , 0x11800809008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM286" , 0x11800809008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM287" , 0x11800809008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM288" , 0x1180080900900ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM289" , 0x1180080900908ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM290" , 0x1180080900910ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM291" , 0x1180080900918ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM292" , 0x1180080900920ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM293" , 0x1180080900928ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM294" , 0x1180080900930ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM295" , 0x1180080900938ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM296" , 0x1180080900940ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM297" , 0x1180080900948ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM298" , 0x1180080900950ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM299" , 0x1180080900958ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM300" , 0x1180080900960ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM301" , 0x1180080900968ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM302" , 0x1180080900970ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM303" , 0x1180080900978ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM304" , 0x1180080900980ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM305" , 0x1180080900988ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM306" , 0x1180080900990ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM307" , 0x1180080900998ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM308" , 0x11800809009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM309" , 0x11800809009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM310" , 0x11800809009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM311" , 0x11800809009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM312" , 0x11800809009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM313" , 0x11800809009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM314" , 0x11800809009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM315" , 0x11800809009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM316" , 0x11800809009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM317" , 0x11800809009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM318" , 0x11800809009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM319" , 0x11800809009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM320" , 0x1180080900a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM321" , 0x1180080900a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM322" , 0x1180080900a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM323" , 0x1180080900a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM324" , 0x1180080900a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM325" , 0x1180080900a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM326" , 0x1180080900a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM327" , 0x1180080900a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM328" , 0x1180080900a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM329" , 0x1180080900a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM330" , 0x1180080900a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM331" , 0x1180080900a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM332" , 0x1180080900a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM333" , 0x1180080900a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM334" , 0x1180080900a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM335" , 0x1180080900a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM336" , 0x1180080900a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM337" , 0x1180080900a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM338" , 0x1180080900a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM339" , 0x1180080900a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM340" , 0x1180080900aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM341" , 0x1180080900aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM342" , 0x1180080900ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM343" , 0x1180080900ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM344" , 0x1180080900ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM345" , 0x1180080900ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM346" , 0x1180080900ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM347" , 0x1180080900ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM348" , 0x1180080900ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM349" , 0x1180080900ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM350" , 0x1180080900af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM351" , 0x1180080900af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM352" , 0x1180080900b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM353" , 0x1180080900b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM354" , 0x1180080900b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM355" , 0x1180080900b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM356" , 0x1180080900b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM357" , 0x1180080900b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM358" , 0x1180080900b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM359" , 0x1180080900b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM360" , 0x1180080900b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM361" , 0x1180080900b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM362" , 0x1180080900b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM363" , 0x1180080900b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM364" , 0x1180080900b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM365" , 0x1180080900b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM366" , 0x1180080900b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM367" , 0x1180080900b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM368" , 0x1180080900b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM369" , 0x1180080900b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM370" , 0x1180080900b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM371" , 0x1180080900b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM372" , 0x1180080900ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM373" , 0x1180080900ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM374" , 0x1180080900bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM375" , 0x1180080900bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM376" , 0x1180080900bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM377" , 0x1180080900bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM378" , 0x1180080900bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM379" , 0x1180080900bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM380" , 0x1180080900be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM381" , 0x1180080900be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM382" , 0x1180080900bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM383" , 0x1180080900bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM384" , 0x1180080900c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM385" , 0x1180080900c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM386" , 0x1180080900c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM387" , 0x1180080900c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM388" , 0x1180080900c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM389" , 0x1180080900c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM390" , 0x1180080900c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM391" , 0x1180080900c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM392" , 0x1180080900c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM393" , 0x1180080900c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM394" , 0x1180080900c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM395" , 0x1180080900c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM396" , 0x1180080900c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM397" , 0x1180080900c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM398" , 0x1180080900c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM399" , 0x1180080900c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM400" , 0x1180080900c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM401" , 0x1180080900c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM402" , 0x1180080900c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM403" , 0x1180080900c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM404" , 0x1180080900ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM405" , 0x1180080900ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM406" , 0x1180080900cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM407" , 0x1180080900cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM408" , 0x1180080900cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM409" , 0x1180080900cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM410" , 0x1180080900cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM411" , 0x1180080900cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM412" , 0x1180080900ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM413" , 0x1180080900ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM414" , 0x1180080900cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM415" , 0x1180080900cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM416" , 0x1180080900d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM417" , 0x1180080900d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM418" , 0x1180080900d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM419" , 0x1180080900d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM420" , 0x1180080900d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM421" , 0x1180080900d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM422" , 0x1180080900d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM423" , 0x1180080900d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM424" , 0x1180080900d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM425" , 0x1180080900d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM426" , 0x1180080900d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM427" , 0x1180080900d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM428" , 0x1180080900d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM429" , 0x1180080900d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM430" , 0x1180080900d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM431" , 0x1180080900d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM432" , 0x1180080900d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM433" , 0x1180080900d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM434" , 0x1180080900d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM435" , 0x1180080900d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM436" , 0x1180080900da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM437" , 0x1180080900da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM438" , 0x1180080900db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM439" , 0x1180080900db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM440" , 0x1180080900dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM441" , 0x1180080900dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM442" , 0x1180080900dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM443" , 0x1180080900dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM444" , 0x1180080900de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM445" , 0x1180080900de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM446" , 0x1180080900df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM447" , 0x1180080900df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM448" , 0x1180080900e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM449" , 0x1180080900e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM450" , 0x1180080900e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM451" , 0x1180080900e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM452" , 0x1180080900e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM453" , 0x1180080900e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM454" , 0x1180080900e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM455" , 0x1180080900e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM456" , 0x1180080900e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM457" , 0x1180080900e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM458" , 0x1180080900e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM459" , 0x1180080900e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM460" , 0x1180080900e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM461" , 0x1180080900e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM462" , 0x1180080900e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM463" , 0x1180080900e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM464" , 0x1180080900e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM465" , 0x1180080900e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM466" , 0x1180080900e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM467" , 0x1180080900e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM468" , 0x1180080900ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM469" , 0x1180080900ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM470" , 0x1180080900eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM471" , 0x1180080900eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM472" , 0x1180080900ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM473" , 0x1180080900ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM474" , 0x1180080900ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM475" , 0x1180080900ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM476" , 0x1180080900ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM477" , 0x1180080900ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM478" , 0x1180080900ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM479" , 0x1180080900ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM480" , 0x1180080900f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM481" , 0x1180080900f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM482" , 0x1180080900f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM483" , 0x1180080900f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM484" , 0x1180080900f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM485" , 0x1180080900f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM486" , 0x1180080900f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM487" , 0x1180080900f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM488" , 0x1180080900f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM489" , 0x1180080900f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM490" , 0x1180080900f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM491" , 0x1180080900f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM492" , 0x1180080900f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM493" , 0x1180080900f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM494" , 0x1180080900f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM495" , 0x1180080900f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM496" , 0x1180080900f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM497" , 0x1180080900f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM498" , 0x1180080900f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM499" , 0x1180080900f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM500" , 0x1180080900fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM501" , 0x1180080900fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM502" , 0x1180080900fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM503" , 0x1180080900fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM504" , 0x1180080900fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM505" , 0x1180080900fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM506" , 0x1180080900fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM507" , 0x1180080900fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM508" , 0x1180080900fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM509" , 0x1180080900fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM510" , 0x1180080900ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM511" , 0x1180080900ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM512" , 0x1180080901000ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM513" , 0x1180080901008ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM514" , 0x1180080901010ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM515" , 0x1180080901018ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM516" , 0x1180080901020ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM517" , 0x1180080901028ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM518" , 0x1180080901030ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM519" , 0x1180080901038ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM520" , 0x1180080901040ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM521" , 0x1180080901048ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM522" , 0x1180080901050ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM523" , 0x1180080901058ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM524" , 0x1180080901060ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM525" , 0x1180080901068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM526" , 0x1180080901070ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM527" , 0x1180080901078ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM528" , 0x1180080901080ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM529" , 0x1180080901088ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM530" , 0x1180080901090ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM531" , 0x1180080901098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM532" , 0x11800809010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM533" , 0x11800809010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM534" , 0x11800809010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM535" , 0x11800809010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM536" , 0x11800809010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM537" , 0x11800809010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM538" , 0x11800809010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM539" , 0x11800809010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM540" , 0x11800809010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM541" , 0x11800809010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM542" , 0x11800809010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM543" , 0x11800809010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM544" , 0x1180080901100ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM545" , 0x1180080901108ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM546" , 0x1180080901110ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM547" , 0x1180080901118ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM548" , 0x1180080901120ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM549" , 0x1180080901128ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM550" , 0x1180080901130ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM551" , 0x1180080901138ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM552" , 0x1180080901140ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM553" , 0x1180080901148ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM554" , 0x1180080901150ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM555" , 0x1180080901158ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM556" , 0x1180080901160ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM557" , 0x1180080901168ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM558" , 0x1180080901170ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM559" , 0x1180080901178ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM560" , 0x1180080901180ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM561" , 0x1180080901188ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM562" , 0x1180080901190ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM563" , 0x1180080901198ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM564" , 0x11800809011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM565" , 0x11800809011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM566" , 0x11800809011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM567" , 0x11800809011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM568" , 0x11800809011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM569" , 0x11800809011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM570" , 0x11800809011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM571" , 0x11800809011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM572" , 0x11800809011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM573" , 0x11800809011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM574" , 0x11800809011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM575" , 0x11800809011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM576" , 0x1180080901200ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM577" , 0x1180080901208ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM578" , 0x1180080901210ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM579" , 0x1180080901218ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM580" , 0x1180080901220ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM581" , 0x1180080901228ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM582" , 0x1180080901230ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM583" , 0x1180080901238ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM584" , 0x1180080901240ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM585" , 0x1180080901248ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM586" , 0x1180080901250ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM587" , 0x1180080901258ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM588" , 0x1180080901260ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM589" , 0x1180080901268ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM590" , 0x1180080901270ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM591" , 0x1180080901278ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM592" , 0x1180080901280ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM593" , 0x1180080901288ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM594" , 0x1180080901290ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM595" , 0x1180080901298ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM596" , 0x11800809012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM597" , 0x11800809012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM598" , 0x11800809012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM599" , 0x11800809012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM600" , 0x11800809012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM601" , 0x11800809012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM602" , 0x11800809012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM603" , 0x11800809012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM604" , 0x11800809012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM605" , 0x11800809012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM606" , 0x11800809012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM607" , 0x11800809012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM608" , 0x1180080901300ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM609" , 0x1180080901308ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM610" , 0x1180080901310ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM611" , 0x1180080901318ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM612" , 0x1180080901320ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM613" , 0x1180080901328ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM614" , 0x1180080901330ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM615" , 0x1180080901338ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM616" , 0x1180080901340ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM617" , 0x1180080901348ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM618" , 0x1180080901350ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM619" , 0x1180080901358ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM620" , 0x1180080901360ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM621" , 0x1180080901368ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM622" , 0x1180080901370ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM623" , 0x1180080901378ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM624" , 0x1180080901380ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM625" , 0x1180080901388ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM626" , 0x1180080901390ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM627" , 0x1180080901398ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM628" , 0x11800809013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM629" , 0x11800809013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM630" , 0x11800809013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM631" , 0x11800809013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM632" , 0x11800809013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM633" , 0x11800809013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM634" , 0x11800809013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM635" , 0x11800809013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM636" , 0x11800809013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM637" , 0x11800809013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM638" , 0x11800809013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM639" , 0x11800809013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM640" , 0x1180080901400ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM641" , 0x1180080901408ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM642" , 0x1180080901410ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM643" , 0x1180080901418ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM644" , 0x1180080901420ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM645" , 0x1180080901428ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM646" , 0x1180080901430ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM647" , 0x1180080901438ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM648" , 0x1180080901440ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM649" , 0x1180080901448ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM650" , 0x1180080901450ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM651" , 0x1180080901458ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM652" , 0x1180080901460ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM653" , 0x1180080901468ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM654" , 0x1180080901470ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM655" , 0x1180080901478ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM656" , 0x1180080901480ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM657" , 0x1180080901488ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM658" , 0x1180080901490ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM659" , 0x1180080901498ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM660" , 0x11800809014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM661" , 0x11800809014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM662" , 0x11800809014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM663" , 0x11800809014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM664" , 0x11800809014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM665" , 0x11800809014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM666" , 0x11800809014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM667" , 0x11800809014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM668" , 0x11800809014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM669" , 0x11800809014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM670" , 0x11800809014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM671" , 0x11800809014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM672" , 0x1180080901500ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM673" , 0x1180080901508ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM674" , 0x1180080901510ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM675" , 0x1180080901518ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM676" , 0x1180080901520ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM677" , 0x1180080901528ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM678" , 0x1180080901530ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM679" , 0x1180080901538ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM680" , 0x1180080901540ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM681" , 0x1180080901548ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM682" , 0x1180080901550ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM683" , 0x1180080901558ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM684" , 0x1180080901560ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM685" , 0x1180080901568ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM686" , 0x1180080901570ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM687" , 0x1180080901578ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM688" , 0x1180080901580ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM689" , 0x1180080901588ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM690" , 0x1180080901590ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM691" , 0x1180080901598ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM692" , 0x11800809015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM693" , 0x11800809015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM694" , 0x11800809015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM695" , 0x11800809015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM696" , 0x11800809015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM697" , 0x11800809015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM698" , 0x11800809015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM699" , 0x11800809015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM700" , 0x11800809015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM701" , 0x11800809015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM702" , 0x11800809015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM703" , 0x11800809015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM704" , 0x1180080901600ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM705" , 0x1180080901608ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM706" , 0x1180080901610ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM707" , 0x1180080901618ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM708" , 0x1180080901620ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM709" , 0x1180080901628ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM710" , 0x1180080901630ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM711" , 0x1180080901638ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM712" , 0x1180080901640ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM713" , 0x1180080901648ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM714" , 0x1180080901650ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM715" , 0x1180080901658ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM716" , 0x1180080901660ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM717" , 0x1180080901668ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM718" , 0x1180080901670ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM719" , 0x1180080901678ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM720" , 0x1180080901680ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM721" , 0x1180080901688ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM722" , 0x1180080901690ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM723" , 0x1180080901698ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM724" , 0x11800809016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM725" , 0x11800809016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM726" , 0x11800809016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM727" , 0x11800809016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM728" , 0x11800809016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM729" , 0x11800809016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM730" , 0x11800809016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM731" , 0x11800809016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM732" , 0x11800809016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM733" , 0x11800809016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM734" , 0x11800809016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM735" , 0x11800809016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM736" , 0x1180080901700ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM737" , 0x1180080901708ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM738" , 0x1180080901710ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM739" , 0x1180080901718ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM740" , 0x1180080901720ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM741" , 0x1180080901728ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM742" , 0x1180080901730ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM743" , 0x1180080901738ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM744" , 0x1180080901740ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM745" , 0x1180080901748ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM746" , 0x1180080901750ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM747" , 0x1180080901758ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM748" , 0x1180080901760ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM749" , 0x1180080901768ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM750" , 0x1180080901770ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM751" , 0x1180080901778ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM752" , 0x1180080901780ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM753" , 0x1180080901788ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM754" , 0x1180080901790ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM755" , 0x1180080901798ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM756" , 0x11800809017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM757" , 0x11800809017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM758" , 0x11800809017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM759" , 0x11800809017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM760" , 0x11800809017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM761" , 0x11800809017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM762" , 0x11800809017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM763" , 0x11800809017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM764" , 0x11800809017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM765" , 0x11800809017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM766" , 0x11800809017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM767" , 0x11800809017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM768" , 0x1180080901800ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM769" , 0x1180080901808ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM770" , 0x1180080901810ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM771" , 0x1180080901818ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM772" , 0x1180080901820ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM773" , 0x1180080901828ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM774" , 0x1180080901830ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM775" , 0x1180080901838ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM776" , 0x1180080901840ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM777" , 0x1180080901848ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM778" , 0x1180080901850ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM779" , 0x1180080901858ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM780" , 0x1180080901860ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM781" , 0x1180080901868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM782" , 0x1180080901870ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM783" , 0x1180080901878ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM784" , 0x1180080901880ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM785" , 0x1180080901888ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM786" , 0x1180080901890ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM787" , 0x1180080901898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM788" , 0x11800809018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM789" , 0x11800809018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM790" , 0x11800809018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM791" , 0x11800809018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM792" , 0x11800809018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM793" , 0x11800809018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM794" , 0x11800809018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM795" , 0x11800809018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM796" , 0x11800809018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM797" , 0x11800809018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM798" , 0x11800809018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM799" , 0x11800809018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM800" , 0x1180080901900ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM801" , 0x1180080901908ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM802" , 0x1180080901910ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM803" , 0x1180080901918ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM804" , 0x1180080901920ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM805" , 0x1180080901928ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM806" , 0x1180080901930ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM807" , 0x1180080901938ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM808" , 0x1180080901940ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM809" , 0x1180080901948ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM810" , 0x1180080901950ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM811" , 0x1180080901958ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM812" , 0x1180080901960ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM813" , 0x1180080901968ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM814" , 0x1180080901970ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM815" , 0x1180080901978ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM816" , 0x1180080901980ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM817" , 0x1180080901988ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM818" , 0x1180080901990ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM819" , 0x1180080901998ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM820" , 0x11800809019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM821" , 0x11800809019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM822" , 0x11800809019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM823" , 0x11800809019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM824" , 0x11800809019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM825" , 0x11800809019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM826" , 0x11800809019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM827" , 0x11800809019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM828" , 0x11800809019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM829" , 0x11800809019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM830" , 0x11800809019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM831" , 0x11800809019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM832" , 0x1180080901a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM833" , 0x1180080901a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM834" , 0x1180080901a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM835" , 0x1180080901a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM836" , 0x1180080901a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM837" , 0x1180080901a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM838" , 0x1180080901a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM839" , 0x1180080901a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM840" , 0x1180080901a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM841" , 0x1180080901a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM842" , 0x1180080901a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM843" , 0x1180080901a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM844" , 0x1180080901a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM845" , 0x1180080901a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM846" , 0x1180080901a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM847" , 0x1180080901a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM848" , 0x1180080901a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM849" , 0x1180080901a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM850" , 0x1180080901a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM851" , 0x1180080901a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM852" , 0x1180080901aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM853" , 0x1180080901aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM854" , 0x1180080901ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM855" , 0x1180080901ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM856" , 0x1180080901ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM857" , 0x1180080901ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM858" , 0x1180080901ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM859" , 0x1180080901ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM860" , 0x1180080901ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM861" , 0x1180080901ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM862" , 0x1180080901af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM863" , 0x1180080901af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM864" , 0x1180080901b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM865" , 0x1180080901b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM866" , 0x1180080901b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM867" , 0x1180080901b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM868" , 0x1180080901b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM869" , 0x1180080901b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM870" , 0x1180080901b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM871" , 0x1180080901b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM872" , 0x1180080901b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM873" , 0x1180080901b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM874" , 0x1180080901b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM875" , 0x1180080901b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM876" , 0x1180080901b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM877" , 0x1180080901b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM878" , 0x1180080901b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM879" , 0x1180080901b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM880" , 0x1180080901b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM881" , 0x1180080901b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM882" , 0x1180080901b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM883" , 0x1180080901b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM884" , 0x1180080901ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM885" , 0x1180080901ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM886" , 0x1180080901bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM887" , 0x1180080901bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM888" , 0x1180080901bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM889" , 0x1180080901bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM890" , 0x1180080901bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM891" , 0x1180080901bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM892" , 0x1180080901be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM893" , 0x1180080901be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM894" , 0x1180080901bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM895" , 0x1180080901bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM896" , 0x1180080901c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM897" , 0x1180080901c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM898" , 0x1180080901c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM899" , 0x1180080901c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM900" , 0x1180080901c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM901" , 0x1180080901c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM902" , 0x1180080901c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM903" , 0x1180080901c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM904" , 0x1180080901c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM905" , 0x1180080901c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM906" , 0x1180080901c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM907" , 0x1180080901c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM908" , 0x1180080901c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM909" , 0x1180080901c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM910" , 0x1180080901c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM911" , 0x1180080901c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM912" , 0x1180080901c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM913" , 0x1180080901c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM914" , 0x1180080901c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM915" , 0x1180080901c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM916" , 0x1180080901ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM917" , 0x1180080901ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM918" , 0x1180080901cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM919" , 0x1180080901cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM920" , 0x1180080901cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM921" , 0x1180080901cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM922" , 0x1180080901cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM923" , 0x1180080901cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM924" , 0x1180080901ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM925" , 0x1180080901ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM926" , 0x1180080901cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM927" , 0x1180080901cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM928" , 0x1180080901d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM929" , 0x1180080901d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM930" , 0x1180080901d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM931" , 0x1180080901d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM932" , 0x1180080901d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM933" , 0x1180080901d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM934" , 0x1180080901d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM935" , 0x1180080901d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM936" , 0x1180080901d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM937" , 0x1180080901d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM938" , 0x1180080901d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM939" , 0x1180080901d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM940" , 0x1180080901d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM941" , 0x1180080901d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM942" , 0x1180080901d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM943" , 0x1180080901d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM944" , 0x1180080901d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM945" , 0x1180080901d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM946" , 0x1180080901d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM947" , 0x1180080901d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM948" , 0x1180080901da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM949" , 0x1180080901da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM950" , 0x1180080901db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM951" , 0x1180080901db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM952" , 0x1180080901dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM953" , 0x1180080901dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM954" , 0x1180080901dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM955" , 0x1180080901dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM956" , 0x1180080901de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM957" , 0x1180080901de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM958" , 0x1180080901df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM959" , 0x1180080901df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM960" , 0x1180080901e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM961" , 0x1180080901e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM962" , 0x1180080901e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM963" , 0x1180080901e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM964" , 0x1180080901e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM965" , 0x1180080901e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM966" , 0x1180080901e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM967" , 0x1180080901e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM968" , 0x1180080901e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM969" , 0x1180080901e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM970" , 0x1180080901e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM971" , 0x1180080901e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM972" , 0x1180080901e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM973" , 0x1180080901e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM974" , 0x1180080901e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM975" , 0x1180080901e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM976" , 0x1180080901e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM977" , 0x1180080901e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM978" , 0x1180080901e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM979" , 0x1180080901e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM980" , 0x1180080901ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM981" , 0x1180080901ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM982" , 0x1180080901eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM983" , 0x1180080901eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM984" , 0x1180080901ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM985" , 0x1180080901ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM986" , 0x1180080901ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM987" , 0x1180080901ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM988" , 0x1180080901ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM989" , 0x1180080901ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM990" , 0x1180080901ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM991" , 0x1180080901ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM992" , 0x1180080901f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM993" , 0x1180080901f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM994" , 0x1180080901f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM995" , 0x1180080901f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM996" , 0x1180080901f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM997" , 0x1180080901f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM998" , 0x1180080901f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM999" , 0x1180080901f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1000" , 0x1180080901f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1001" , 0x1180080901f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1002" , 0x1180080901f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1003" , 0x1180080901f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1004" , 0x1180080901f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1005" , 0x1180080901f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1006" , 0x1180080901f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1007" , 0x1180080901f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1008" , 0x1180080901f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1009" , 0x1180080901f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1010" , 0x1180080901f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1011" , 0x1180080901f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1012" , 0x1180080901fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1013" , 0x1180080901fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1014" , 0x1180080901fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1015" , 0x1180080901fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1016" , 0x1180080901fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1017" , 0x1180080901fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1018" , 0x1180080901fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1019" , 0x1180080901fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1020" , 0x1180080901fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1021" , 0x1180080901fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1022" , 0x1180080901ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VRT_MEM1023" , 0x1180080901ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_WPAR_IOB0" , 0x1180080840200ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"L2C_WPAR_PP0" , 0x1180080840000ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"L2C_WPAR_PP1" , 0x1180080840008ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"L2C_WPAR_PP2" , 0x1180080840010ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"L2C_WPAR_PP3" , 0x1180080840018ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"L2C_WPAR_PP4" , 0x1180080840020ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"L2C_WPAR_PP5" , 0x1180080840028ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"L2C_XMC0_PFC" , 0x1180080800400ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"L2C_XMC_CMD" , 0x1180080800028ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"L2C_XMD0_PFC" , 0x1180080800408ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"LMC0_CHAR_CTL" , 0x1180088000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"LMC0_CHAR_MASK0" , 0x1180088000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"LMC0_CHAR_MASK1" , 0x1180088000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"LMC0_CHAR_MASK2" , 0x1180088000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"LMC0_CHAR_MASK3" , 0x1180088000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"LMC0_CHAR_MASK4" , 0x1180088000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"LMC0_COMP_CTL2" , 0x11800880001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"LMC0_CONFIG" , 0x1180088000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"LMC0_CONTROL" , 0x1180088000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"LMC0_DCLK_CNT" , 0x11800880001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"LMC0_DDR_PLL_CTL" , 0x1180088000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"LMC0_DIMM000_PARAMS" , 0x1180088000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"LMC0_DIMM001_PARAMS" , 0x1180088000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"LMC0_DIMM_CTL" , 0x1180088000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"LMC0_DLL_CTL2" , 0x11800880001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"LMC0_DLL_CTL3" , 0x1180088000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"LMC0_IFB_CNT" , 0x11800880001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"LMC0_INT" , 0x11800880001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"LMC0_INT_EN" , 0x11800880001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"LMC0_MODEREG_PARAMS0" , 0x11800880001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"LMC0_MODEREG_PARAMS1" , 0x1180088000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"LMC0_NXM" , 0x11800880000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"LMC0_OPS_CNT" , 0x11800880001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"LMC0_PHY_CTL" , 0x1180088000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"LMC0_RESET_CTL" , 0x1180088000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"LMC0_RLEVEL_CTL" , 0x11800880002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"LMC0_RLEVEL_DBG" , 0x11800880002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"LMC0_RLEVEL_RANK000" , 0x1180088000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"LMC0_RLEVEL_RANK001" , 0x1180088000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"LMC0_RLEVEL_RANK002" , 0x1180088000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"LMC0_RLEVEL_RANK003" , 0x1180088000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"LMC0_RODT_MASK" , 0x1180088000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"LMC0_SLOT_CTL0" , 0x11800880001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"LMC0_SLOT_CTL1" , 0x1180088000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"LMC0_SLOT_CTL2" , 0x1180088000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"LMC0_TIMING_PARAMS0" , 0x1180088000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"LMC0_TIMING_PARAMS1" , 0x11800880001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"LMC0_TRO_CTL" , 0x1180088000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"LMC0_TRO_STAT" , 0x1180088000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"LMC0_WLEVEL_CTL" , 0x1180088000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"LMC0_WLEVEL_DBG" , 0x1180088000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"LMC0_WLEVEL_RANK000" , 0x11800880002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"LMC0_WLEVEL_RANK001" , 0x11800880002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"LMC0_WLEVEL_RANK002" , 0x11800880002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"LMC0_WLEVEL_RANK003" , 0x11800880002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"LMC0_WODT_MASK" , 0x11800880001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"MIO_BOOT_PIN_DEFS" , 0x11800000000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"MIO_FUS_READ_TIMES" , 0x1180000001570ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"MIO_FUS_REPAIR_RES0" , 0x1180000001558ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"MIO_FUS_REPAIR_RES1" , 0x1180000001560ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"MIO_FUS_REPAIR_RES2" , 0x1180000001568ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"MIO_GPIO_COMP" , 0x11800000000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"MIO_NDF_DMA_CFG" , 0x1180000000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"MIO_NDF_DMA_INT" , 0x1180000000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"MIO_NDF_DMA_INT_EN" , 0x1180000000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"MIO_PTP_CLOCK_CFG" , 0x1070000000f00ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
- {"MIO_PTP_CLOCK_COMP" , 0x1070000000f18ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
- {"MIO_PTP_CLOCK_HI" , 0x1070000000f10ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
- {"MIO_PTP_CLOCK_LO" , 0x1070000000f08ull, CVMX_CSR_DB_TYPE_NCB, 64, 482},
- {"MIO_PTP_EVT_CNT" , 0x1070000000f28ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
- {"MIO_PTP_TIMESTAMP" , 0x1070000000f20ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
- {"MIO_RST_BOOT" , 0x1180000001600ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"MIO_RST_CFG" , 0x1180000001610ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"MIO_RST_CTL0" , 0x1180000001618ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"MIO_RST_CTL1" , 0x1180000001620ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"MIO_RST_DELAY" , 0x1180000001608ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"MIO_RST_INT" , 0x1180000001628ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"MIO_RST_INT_EN" , 0x1180000001630ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"MIX1_BIST" , 0x1070000100878ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
- {"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
- {"MIX1_CTL" , 0x1070000100820ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
- {"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 522},
- {"MIX1_INTENA" , 0x1070000100850ull, CVMX_CSR_DB_TYPE_NCB, 64, 522},
- {"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 523},
- {"MIX1_IRCNT" , 0x1070000100830ull, CVMX_CSR_DB_TYPE_NCB, 64, 523},
- {"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
- {"MIX1_IRHWM" , 0x1070000100828ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
- {"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 525},
- {"MIX1_IRING1" , 0x1070000100810ull, CVMX_CSR_DB_TYPE_NCB, 64, 525},
- {"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"MIX1_IRING2" , 0x1070000100818ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 527},
- {"MIX1_ISR" , 0x1070000100848ull, CVMX_CSR_DB_TYPE_NCB, 64, 527},
- {"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"MIX1_ORCNT" , 0x1070000100840ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"MIX1_ORHWM" , 0x1070000100838ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 530},
- {"MIX1_ORING1" , 0x1070000100800ull, CVMX_CSR_DB_TYPE_NCB, 64, 530},
- {"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 531},
- {"MIX1_ORING2" , 0x1070000100808ull, CVMX_CSR_DB_TYPE_NCB, 64, 531},
- {"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 532},
- {"MIX1_REMCNT" , 0x1070000100858ull, CVMX_CSR_DB_TYPE_NCB, 64, 532},
- {"MIX0_TSCTL" , 0x1070000100068ull, CVMX_CSR_DB_TYPE_NCB, 64, 533},
- {"MIX1_TSCTL" , 0x1070000100868ull, CVMX_CSR_DB_TYPE_NCB, 64, 533},
- {"MIX0_TSTAMP" , 0x1070000100060ull, CVMX_CSR_DB_TYPE_NCB, 64, 534},
- {"MIX1_TSTAMP" , 0x1070000100860ull, CVMX_CSR_DB_TYPE_NCB, 64, 534},
- {"NDF_BT_PG_INFO" , 0x1070001000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 535},
- {"NDF_CMD" , 0x1070001000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 536},
- {"NDF_DRBELL" , 0x1070001000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 537},
- {"NDF_ECC_CNT" , 0x1070001000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 538},
- {"NDF_INT" , 0x1070001000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 539},
- {"NDF_INT_EN" , 0x1070001000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 540},
- {"NDF_MISC" , 0x1070001000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 541},
- {"NDF_ST_REG" , 0x1070001000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 542},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 543},
- {"PCIEEP1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 543},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 544},
- {"PCIEEP1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 544},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 545},
- {"PCIEEP1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 545},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 546},
- {"PCIEEP1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 546},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 547},
- {"PCIEEP1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 547},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 548},
- {"PCIEEP1_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 548},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 549},
- {"PCIEEP1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 549},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 550},
- {"PCIEEP1_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 550},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 551},
- {"PCIEEP1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 551},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 552},
- {"PCIEEP1_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 552},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 553},
- {"PCIEEP1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 553},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 554},
- {"PCIEEP1_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 554},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 555},
- {"PCIEEP1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 555},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 556},
- {"PCIEEP1_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 556},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 557},
- {"PCIEEP1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 557},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 558},
- {"PCIEEP1_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 558},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 559},
- {"PCIEEP1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 559},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 560},
- {"PCIEEP1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 560},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 561},
- {"PCIEEP1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 561},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 562},
- {"PCIEEP1_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 562},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 563},
- {"PCIEEP1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 563},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 564},
- {"PCIEEP1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 564},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 565},
- {"PCIEEP1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 565},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 566},
- {"PCIEEP1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 566},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 567},
- {"PCIEEP1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 567},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 568},
- {"PCIEEP1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 568},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 569},
- {"PCIEEP1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 569},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 570},
- {"PCIEEP1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 570},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 571},
- {"PCIEEP1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 571},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 572},
- {"PCIEEP1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 572},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 573},
- {"PCIEEP1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 573},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 574},
- {"PCIEEP1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 574},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 575},
- {"PCIEEP1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 575},
- {"PCIEEP0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 576},
- {"PCIEEP1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 576},
- {"PCIEEP0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 577},
- {"PCIEEP1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 577},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 578},
- {"PCIEEP1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 578},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 579},
- {"PCIEEP1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 579},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 580},
- {"PCIEEP1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 580},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 581},
- {"PCIEEP1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 581},
- {"PCIEEP0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 582},
- {"PCIEEP1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 582},
- {"PCIEEP0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 583},
- {"PCIEEP1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 583},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 584},
- {"PCIEEP1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 584},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 585},
- {"PCIEEP1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 585},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 586},
- {"PCIEEP1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 586},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 587},
- {"PCIEEP1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 587},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 588},
- {"PCIEEP1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 588},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 589},
- {"PCIEEP1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 589},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 590},
- {"PCIEEP1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 590},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 591},
- {"PCIEEP1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 591},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 592},
- {"PCIEEP1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 592},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 593},
- {"PCIEEP1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 593},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 594},
- {"PCIEEP1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 594},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 595},
- {"PCIEEP1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 595},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 596},
- {"PCIEEP1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 596},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 597},
- {"PCIEEP1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 597},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 598},
- {"PCIEEP1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 598},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 599},
- {"PCIEEP1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 599},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 600},
- {"PCIEEP1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 600},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 601},
- {"PCIEEP1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 601},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 602},
- {"PCIEEP1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 602},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 603},
- {"PCIEEP1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 603},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 604},
- {"PCIEEP1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 604},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 605},
- {"PCIEEP1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 605},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 606},
- {"PCIEEP1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 606},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 607},
- {"PCIEEP1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 607},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 608},
- {"PCIEEP1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 608},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 609},
- {"PCIEEP1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 609},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 610},
- {"PCIEEP1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 610},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 611},
- {"PCIEEP1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 611},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 612},
- {"PCIEEP1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 612},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 613},
- {"PCIEEP1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 613},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 614},
- {"PCIEEP1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 614},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 615},
- {"PCIEEP1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 615},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 616},
- {"PCIEEP1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 616},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 617},
- {"PCIEEP1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 617},
- {"PCIEEP0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 618},
- {"PCIEEP1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 618},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 619},
- {"PCIEEP1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 619},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 620},
- {"PCIEEP1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 620},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 623},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 623},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 624},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 624},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 625},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 625},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 626},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 626},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 627},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 627},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 628},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 628},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 694},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 694},
- {"PCIERC0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 695},
- {"PCIERC1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 695},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 696},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 696},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 697},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 697},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PCS0_AN002_ADV_REG" , 0x11800b0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PCS0_AN003_ADV_REG" , 0x11800b0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PCS0_AN002_EXT_ST_REG" , 0x11800b0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PCS0_AN003_EXT_ST_REG" , 0x11800b0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PCS0_AN002_LP_ABIL_REG" , 0x11800b0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PCS0_AN003_LP_ABIL_REG" , 0x11800b0001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PCS0_AN002_RESULTS_REG" , 0x11800b0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PCS0_AN003_RESULTS_REG" , 0x11800b0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PCS0_INT002_EN_REG" , 0x11800b0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PCS0_INT003_EN_REG" , 0x11800b0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PCS0_INT002_REG" , 0x11800b0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PCS0_INT003_REG" , 0x11800b0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PCS0_LINK002_TIMER_COUNT_REG", 0x11800b0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PCS0_LINK003_TIMER_COUNT_REG", 0x11800b0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PCS0_LOG_ANL002_REG" , 0x11800b0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PCS0_LOG_ANL003_REG" , 0x11800b0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_MISC002_CTL_REG" , 0x11800b0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_MISC003_CTL_REG" , 0x11800b0001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_MR002_CONTROL_REG" , 0x11800b0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_MR003_CONTROL_REG" , 0x11800b0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_MR002_STATUS_REG" , 0x11800b0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_MR003_STATUS_REG" , 0x11800b0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_RX002_STATES_REG" , 0x11800b0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_RX003_STATES_REG" , 0x11800b0001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_RX002_SYNC_REG" , 0x11800b0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_RX003_SYNC_REG" , 0x11800b0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PCS0_SGM002_AN_ADV_REG" , 0x11800b0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PCS0_SGM003_AN_ADV_REG" , 0x11800b0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PCS0_SGM002_LP_ADV_REG" , 0x11800b0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PCS0_SGM003_LP_ADV_REG" , 0x11800b0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PCS0_TX002_STATES_REG" , 0x11800b0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PCS0_TX003_STATES_REG" , 0x11800b0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PCS0_TX_RX002_POLARITY_REG" , 0x11800b0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PCS0_TX_RX003_POLARITY_REG" , 0x11800b0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PCSX0_10GBX_STATUS_REG" , 0x11800b0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"PCSX0_BIST_STATUS_REG" , 0x11800b0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800b0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"PCSX0_CONTROL1_REG" , 0x11800b0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"PCSX0_CONTROL2_REG" , 0x11800b0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"PCSX0_INT_EN_REG" , 0x11800b0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"PCSX0_INT_REG" , 0x11800b0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"PCSX0_LOG_ANL_REG" , 0x11800b0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"PCSX0_MISC_CTL_REG" , 0x11800b0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
- {"PCSX0_RX_SYNC_STATES_REG" , 0x11800b0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PCSX0_SPD_ABIL_REG" , 0x11800b0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PCSX0_STATUS1_REG" , 0x11800b0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
- {"PCSX0_STATUS2_REG" , 0x11800b0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
- {"PCSX0_TX_RX_POLARITY_REG" , 0x11800b0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
- {"PCSX0_TX_RX_STATES_REG" , 0x11800b0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"PEM0_BAR1_INDEX000" , 0x11800c00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX001" , 0x11800c00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX002" , 0x11800c00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX003" , 0x11800c00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX004" , 0x11800c00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX005" , 0x11800c00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX006" , 0x11800c00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX007" , 0x11800c00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX008" , 0x11800c00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX009" , 0x11800c00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX010" , 0x11800c00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX011" , 0x11800c0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX012" , 0x11800c0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX013" , 0x11800c0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX014" , 0x11800c0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR1_INDEX015" , 0x11800c0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX000" , 0x11800c10000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX001" , 0x11800c10000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX002" , 0x11800c10000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX003" , 0x11800c10000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX004" , 0x11800c10000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX005" , 0x11800c10000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX006" , 0x11800c10000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX007" , 0x11800c10000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX008" , 0x11800c10000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX009" , 0x11800c10000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX010" , 0x11800c10000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX011" , 0x11800c1000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX012" , 0x11800c1000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX013" , 0x11800c1000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX014" , 0x11800c1000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM1_BAR1_INDEX015" , 0x11800c1000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PEM0_BAR_CTL" , 0x11800c0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
- {"PEM1_BAR_CTL" , 0x11800c1000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
- {"PEM0_BIST_STATUS" , 0x11800c0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"PEM1_BIST_STATUS" , 0x11800c1000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"PEM0_BIST_STATUS2" , 0x11800c0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
- {"PEM1_BIST_STATUS2" , 0x11800c1000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
- {"PEM0_CFG_RD" , 0x11800c0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
- {"PEM1_CFG_RD" , 0x11800c1000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
- {"PEM0_CFG_WR" , 0x11800c0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
- {"PEM1_CFG_WR" , 0x11800c1000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
- {"PEM0_CPL_LUT_VALID" , 0x11800c0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
- {"PEM1_CPL_LUT_VALID" , 0x11800c1000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
- {"PEM0_CTL_STATUS" , 0x11800c0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
- {"PEM1_CTL_STATUS" , 0x11800c1000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
- {"PEM0_DBG_INFO" , 0x11800c0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_DBG_INFO" , 0x11800c1000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_DBG_INFO_EN" , 0x11800c00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PEM1_DBG_INFO_EN" , 0x11800c10000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PEM0_DIAG_STATUS" , 0x11800c0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PEM1_DIAG_STATUS" , 0x11800c1000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PEM0_INT_ENB" , 0x11800c0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PEM1_INT_ENB" , 0x11800c1000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PEM0_INT_ENB_INT" , 0x11800c0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PEM1_INT_ENB_INT" , 0x11800c1000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PEM0_INT_SUM" , 0x11800c0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PEM1_INT_SUM" , 0x11800c1000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PEM0_P2N_BAR0_START" , 0x11800c0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
- {"PEM1_P2N_BAR0_START" , 0x11800c1000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
- {"PEM0_P2N_BAR1_START" , 0x11800c0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
- {"PEM1_P2N_BAR1_START" , 0x11800c1000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
- {"PEM0_P2N_BAR2_START" , 0x11800c0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PEM1_P2N_BAR2_START" , 0x11800c1000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PEM0_P2P_BAR000_END" , 0x11800c0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PEM0_P2P_BAR001_END" , 0x11800c0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PEM0_P2P_BAR002_END" , 0x11800c0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PEM0_P2P_BAR003_END" , 0x11800c0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PEM1_P2P_BAR000_END" , 0x11800c1000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PEM1_P2P_BAR001_END" , 0x11800c1000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PEM1_P2P_BAR002_END" , 0x11800c1000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PEM1_P2P_BAR003_END" , 0x11800c1000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PEM0_P2P_BAR000_START" , 0x11800c0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PEM0_P2P_BAR001_START" , 0x11800c0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PEM0_P2P_BAR002_START" , 0x11800c0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PEM0_P2P_BAR003_START" , 0x11800c0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PEM1_P2P_BAR000_START" , 0x11800c1000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PEM1_P2P_BAR001_START" , 0x11800c1000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PEM1_P2P_BAR002_START" , 0x11800c1000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PEM1_P2P_BAR003_START" , 0x11800c1000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PEM0_TLP_CREDITS" , 0x11800c0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PEM1_TLP_CREDITS" , 0x11800c1000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PIP_CLKEN" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PIP_DSA_SRC_GRP" , 0x11800a0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PIP_DSA_VID_GRP" , 0x11800a0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_HG_PRI_QOS" , 0x11800a00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG40" , 0x11800a0000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG41" , 0x11800a0000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG42" , 0x11800a0000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_CFG43" , 0x11800a0000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG40" , 0x11800a0000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG41" , 0x11800a0000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG42" , 0x11800a0000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_PRT_TAG43" , 0x11800a0000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT36" , 0x11800a0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT37" , 0x11800a0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT38" , 0x11800a00013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT0_PRT39" , 0x11800a0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_STAT10_PRT0" , 0x11800a0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT1" , 0x11800a0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT2" , 0x11800a00014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT3" , 0x11800a00014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT32" , 0x11800a0001680ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT33" , 0x11800a0001690ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT34" , 0x11800a00016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT35" , 0x11800a00016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT36" , 0x11800a00016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT37" , 0x11800a00016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT38" , 0x11800a00016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT10_PRT39" , 0x11800a00016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_STAT11_PRT0" , 0x11800a0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT1" , 0x11800a0001498ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT2" , 0x11800a00014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT3" , 0x11800a00014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT32" , 0x11800a0001688ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT33" , 0x11800a0001698ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT34" , 0x11800a00016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT35" , 0x11800a00016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT36" , 0x11800a00016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT37" , 0x11800a00016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT38" , 0x11800a00016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT11_PRT39" , 0x11800a00016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT36" , 0x11800a0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT37" , 0x11800a0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT38" , 0x11800a00013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT1_PRT39" , 0x11800a0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT36" , 0x11800a0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT37" , 0x11800a00013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT38" , 0x11800a00013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT2_PRT39" , 0x11800a0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT36" , 0x11800a0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT37" , 0x11800a00013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT38" , 0x11800a00013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT3_PRT39" , 0x11800a0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT36" , 0x11800a0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT37" , 0x11800a00013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT38" , 0x11800a0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT4_PRT39" , 0x11800a0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT36" , 0x11800a0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT37" , 0x11800a00013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT38" , 0x11800a0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT5_PRT39" , 0x11800a0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT36" , 0x11800a0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT37" , 0x11800a00013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT38" , 0x11800a0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT6_PRT39" , 0x11800a0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT36" , 0x11800a0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT37" , 0x11800a00013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT38" , 0x11800a0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT7_PRT39" , 0x11800a0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT36" , 0x11800a0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT37" , 0x11800a00013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT38" , 0x11800a0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT8_PRT39" , 0x11800a0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT36" , 0x11800a0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT37" , 0x11800a00013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT38" , 0x11800a0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT9_PRT39" , 0x11800a0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS36" , 0x11800a0001e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS37" , 0x11800a0001eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS38" , 0x11800a0001ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS39" , 0x11800a0001ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS40" , 0x11800a0001f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS41" , 0x11800a0001f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS42" , 0x11800a0001f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_ERRS43" , 0x11800a0001f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS36" , 0x11800a0001e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS37" , 0x11800a0001ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS38" , 0x11800a0001ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS39" , 0x11800a0001ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS40" , 0x11800a0001f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS41" , 0x11800a0001f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS42" , 0x11800a0001f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_OCTS43" , 0x11800a0001f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS36" , 0x11800a0001e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS37" , 0x11800a0001ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS38" , 0x11800a0001ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS39" , 0x11800a0001ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS40" , 0x11800a0001f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS41" , 0x11800a0001f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS42" , 0x11800a0001f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT_INB_PKTS43" , 0x11800a0001f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_XSTAT0_PRT40" , 0x11800a0002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PIP_XSTAT0_PRT41" , 0x11800a0002050ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PIP_XSTAT0_PRT42" , 0x11800a00020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PIP_XSTAT0_PRT43" , 0x11800a00020f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PIP_XSTAT10_PRT40" , 0x11800a0001700ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_XSTAT10_PRT41" , 0x11800a0001710ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_XSTAT10_PRT42" , 0x11800a0001720ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_XSTAT10_PRT43" , 0x11800a0001730ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_XSTAT11_PRT40" , 0x11800a0001708ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_XSTAT11_PRT41" , 0x11800a0001718ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_XSTAT11_PRT42" , 0x11800a0001728ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_XSTAT11_PRT43" , 0x11800a0001738ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_XSTAT1_PRT40" , 0x11800a0002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_XSTAT1_PRT41" , 0x11800a0002058ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_XSTAT1_PRT42" , 0x11800a00020a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_XSTAT1_PRT43" , 0x11800a00020f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_XSTAT2_PRT40" , 0x11800a0002010ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_XSTAT2_PRT41" , 0x11800a0002060ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_XSTAT2_PRT42" , 0x11800a00020b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_XSTAT2_PRT43" , 0x11800a0002100ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_XSTAT3_PRT40" , 0x11800a0002018ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PIP_XSTAT3_PRT41" , 0x11800a0002068ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PIP_XSTAT3_PRT42" , 0x11800a00020b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PIP_XSTAT3_PRT43" , 0x11800a0002108ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PIP_XSTAT4_PRT40" , 0x11800a0002020ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PIP_XSTAT4_PRT41" , 0x11800a0002070ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PIP_XSTAT4_PRT42" , 0x11800a00020c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PIP_XSTAT4_PRT43" , 0x11800a0002110ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PIP_XSTAT5_PRT40" , 0x11800a0002028ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PIP_XSTAT5_PRT41" , 0x11800a0002078ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PIP_XSTAT5_PRT42" , 0x11800a00020c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PIP_XSTAT5_PRT43" , 0x11800a0002118ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PIP_XSTAT6_PRT40" , 0x11800a0002030ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PIP_XSTAT6_PRT41" , 0x11800a0002080ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PIP_XSTAT6_PRT42" , 0x11800a00020d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PIP_XSTAT6_PRT43" , 0x11800a0002120ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PIP_XSTAT7_PRT40" , 0x11800a0002038ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PIP_XSTAT7_PRT41" , 0x11800a0002088ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PIP_XSTAT7_PRT42" , 0x11800a00020d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PIP_XSTAT7_PRT43" , 0x11800a0002128ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PIP_XSTAT8_PRT40" , 0x11800a0002040ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PIP_XSTAT8_PRT41" , 0x11800a0002090ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PIP_XSTAT8_PRT42" , 0x11800a00020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PIP_XSTAT8_PRT43" , 0x11800a0002130ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PIP_XSTAT9_PRT40" , 0x11800a0002048ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PIP_XSTAT9_PRT41" , 0x11800a0002098ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PIP_XSTAT9_PRT42" , 0x11800a00020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PIP_XSTAT9_PRT43" , 0x11800a0002138ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 812},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 813},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 817},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
- {"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 819},
- {"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 820},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 821},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 822},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 823},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PKO_REG_PREEMPT" , 0x1180050000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PKO_REG_QUEUE_PREEMPT" , 0x1180050000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PKO_REG_TIMESTAMP" , 0x1180050000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 843},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 844},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 845},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 846},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 848},
- {"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 849},
- {"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 850},
- {"POW_IQ_THR0" , 0x16700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"POW_IQ_THR1" , 0x16700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"POW_IQ_THR2" , 0x16700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"POW_IQ_THR3" , 0x16700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"POW_IQ_THR4" , 0x16700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"POW_IQ_THR5" , 0x16700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"POW_IQ_THR6" , 0x16700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"POW_IQ_THR7" , 0x16700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 852},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 853},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 854},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 856},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 856},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 856},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 856},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 856},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 856},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 856},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 856},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 857},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 857},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 857},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 857},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 857},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 857},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 857},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 857},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 858},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 859},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 860},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 860},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 860},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 860},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 860},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 860},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 860},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 860},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 861},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 863},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 869},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 870},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 871},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 874},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 875},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 876},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 877},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 878},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 879},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 880},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 883},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 884},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 885},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 886},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 887},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 888},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 889},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 890},
- {"RNM_EER_DBG" , 0x1180040000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 891},
- {"RNM_EER_KEY" , 0x1180040000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
- {"SLI_BIST_STATUS" , 0x11f0000010580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 893},
- {"SLI_CTL_PORT0" , 0x11f0000010050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 894},
- {"SLI_CTL_PORT1" , 0x11f0000010060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 894},
- {"SLI_CTL_STATUS" , 0x11f0000010570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 895},
- {"SLI_DATA_OUT_CNT" , 0x11f00000105f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 896},
- {"SLI_DBG_DATA" , 0x11f0000010310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 897},
- {"SLI_DBG_SELECT" , 0x11f0000010300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 898},
- {"SLI_DMA0_CNT" , 0x11f0000010400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 899},
- {"SLI_DMA1_CNT" , 0x11f0000010410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 899},
- {"SLI_DMA0_INT_LEVEL" , 0x11f00000103e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 900},
- {"SLI_DMA1_INT_LEVEL" , 0x11f00000103f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 900},
- {"SLI_DMA0_TIM" , 0x11f0000010420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 901},
- {"SLI_DMA1_TIM" , 0x11f0000010430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 901},
- {"SLI_INT_ENB_CIU" , 0x11f0000013cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 902},
- {"SLI_INT_ENB_PORT0" , 0x11f0000010340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 903},
- {"SLI_INT_ENB_PORT1" , 0x11f0000010350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 903},
- {"SLI_INT_SUM" , 0x11f0000010330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 904},
- {"SLI_LAST_WIN_RDATA0" , 0x11f0000010600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 905},
- {"SLI_LAST_WIN_RDATA1" , 0x11f0000010610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 906},
- {"SLI_MAC_CREDIT_CNT" , 0x11f0000013d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 907},
- {"SLI_MEM_ACCESS_CTL" , 0x11f00000102f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 908},
- {"SLI_MEM_ACCESS_SUBID12" , 0x11f00000100e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID13" , 0x11f00000100f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID14" , 0x11f0000010100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID15" , 0x11f0000010110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID16" , 0x11f0000010120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID17" , 0x11f0000010130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID18" , 0x11f0000010140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID19" , 0x11f0000010150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID20" , 0x11f0000010160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID21" , 0x11f0000010170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID22" , 0x11f0000010180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID23" , 0x11f0000010190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID24" , 0x11f00000101a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID25" , 0x11f00000101b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID26" , 0x11f00000101c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MEM_ACCESS_SUBID27" , 0x11f00000101d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_MSI_ENB0" , 0x11f0000013c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 910},
- {"SLI_MSI_ENB1" , 0x11f0000013c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 911},
- {"SLI_MSI_ENB2" , 0x11f0000013c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 912},
- {"SLI_MSI_ENB3" , 0x11f0000013c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 913},
- {"SLI_MSI_RCV0" , 0x11f0000013c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 914},
- {"SLI_MSI_RCV1" , 0x11f0000013c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 915},
- {"SLI_MSI_RCV2" , 0x11f0000013c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 916},
- {"SLI_MSI_RCV3" , 0x11f0000013c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 917},
- {"SLI_MSI_RD_MAP" , 0x11f0000013ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 918},
- {"SLI_MSI_W1C_ENB0" , 0x11f0000013cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MSI_W1C_ENB1" , 0x11f0000013d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 920},
- {"SLI_MSI_W1C_ENB2" , 0x11f0000013d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 921},
- {"SLI_MSI_W1C_ENB3" , 0x11f0000013d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 922},
- {"SLI_MSI_W1S_ENB0" , 0x11f0000013d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 923},
- {"SLI_MSI_W1S_ENB1" , 0x11f0000013d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 924},
- {"SLI_MSI_W1S_ENB2" , 0x11f0000013d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 925},
- {"SLI_MSI_W1S_ENB3" , 0x11f0000013d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 926},
- {"SLI_MSI_WR_MAP" , 0x11f0000013c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 927},
- {"SLI_PCIE_MSI_RCV" , 0x11f0000013cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 928},
- {"SLI_PCIE_MSI_RCV_B1" , 0x11f0000010650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 929},
- {"SLI_PCIE_MSI_RCV_B2" , 0x11f0000010660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 930},
- {"SLI_PCIE_MSI_RCV_B3" , 0x11f0000010670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 931},
- {"SLI_PKT0_CNTS" , 0x11f0000012400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT1_CNTS" , 0x11f0000012410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT2_CNTS" , 0x11f0000012420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT3_CNTS" , 0x11f0000012430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT4_CNTS" , 0x11f0000012440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT5_CNTS" , 0x11f0000012450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT6_CNTS" , 0x11f0000012460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT7_CNTS" , 0x11f0000012470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT8_CNTS" , 0x11f0000012480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT9_CNTS" , 0x11f0000012490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT10_CNTS" , 0x11f00000124a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT11_CNTS" , 0x11f00000124b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT12_CNTS" , 0x11f00000124c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT13_CNTS" , 0x11f00000124d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT14_CNTS" , 0x11f00000124e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT15_CNTS" , 0x11f00000124f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT16_CNTS" , 0x11f0000012500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT17_CNTS" , 0x11f0000012510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT18_CNTS" , 0x11f0000012520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT19_CNTS" , 0x11f0000012530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT20_CNTS" , 0x11f0000012540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT21_CNTS" , 0x11f0000012550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT22_CNTS" , 0x11f0000012560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT23_CNTS" , 0x11f0000012570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT24_CNTS" , 0x11f0000012580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT25_CNTS" , 0x11f0000012590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT26_CNTS" , 0x11f00000125a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT27_CNTS" , 0x11f00000125b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT28_CNTS" , 0x11f00000125c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT29_CNTS" , 0x11f00000125d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT30_CNTS" , 0x11f00000125e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT31_CNTS" , 0x11f00000125f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_PKT0_IN_BP" , 0x11f0000013800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT1_IN_BP" , 0x11f0000013810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT2_IN_BP" , 0x11f0000013820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT3_IN_BP" , 0x11f0000013830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT4_IN_BP" , 0x11f0000013840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT5_IN_BP" , 0x11f0000013850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT6_IN_BP" , 0x11f0000013860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT7_IN_BP" , 0x11f0000013870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT8_IN_BP" , 0x11f0000013880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT9_IN_BP" , 0x11f0000013890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT10_IN_BP" , 0x11f00000138a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT11_IN_BP" , 0x11f00000138b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT12_IN_BP" , 0x11f00000138c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT13_IN_BP" , 0x11f00000138d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT14_IN_BP" , 0x11f00000138e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT15_IN_BP" , 0x11f00000138f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT16_IN_BP" , 0x11f0000013900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT17_IN_BP" , 0x11f0000013910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT18_IN_BP" , 0x11f0000013920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT19_IN_BP" , 0x11f0000013930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT20_IN_BP" , 0x11f0000013940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT21_IN_BP" , 0x11f0000013950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT22_IN_BP" , 0x11f0000013960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT23_IN_BP" , 0x11f0000013970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT24_IN_BP" , 0x11f0000013980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT25_IN_BP" , 0x11f0000013990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT26_IN_BP" , 0x11f00000139a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT27_IN_BP" , 0x11f00000139b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT28_IN_BP" , 0x11f00000139c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT29_IN_BP" , 0x11f00000139d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT30_IN_BP" , 0x11f00000139e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT31_IN_BP" , 0x11f00000139f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_PKT0_INSTR_BADDR" , 0x11f0000012800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT1_INSTR_BADDR" , 0x11f0000012810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT2_INSTR_BADDR" , 0x11f0000012820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT3_INSTR_BADDR" , 0x11f0000012830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT4_INSTR_BADDR" , 0x11f0000012840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT5_INSTR_BADDR" , 0x11f0000012850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT6_INSTR_BADDR" , 0x11f0000012860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT7_INSTR_BADDR" , 0x11f0000012870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT8_INSTR_BADDR" , 0x11f0000012880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT9_INSTR_BADDR" , 0x11f0000012890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT10_INSTR_BADDR" , 0x11f00000128a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT11_INSTR_BADDR" , 0x11f00000128b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT12_INSTR_BADDR" , 0x11f00000128c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT13_INSTR_BADDR" , 0x11f00000128d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT14_INSTR_BADDR" , 0x11f00000128e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT15_INSTR_BADDR" , 0x11f00000128f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT16_INSTR_BADDR" , 0x11f0000012900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT17_INSTR_BADDR" , 0x11f0000012910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT18_INSTR_BADDR" , 0x11f0000012920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT19_INSTR_BADDR" , 0x11f0000012930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT20_INSTR_BADDR" , 0x11f0000012940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT21_INSTR_BADDR" , 0x11f0000012950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT22_INSTR_BADDR" , 0x11f0000012960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT23_INSTR_BADDR" , 0x11f0000012970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT24_INSTR_BADDR" , 0x11f0000012980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT25_INSTR_BADDR" , 0x11f0000012990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT26_INSTR_BADDR" , 0x11f00000129a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT27_INSTR_BADDR" , 0x11f00000129b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT28_INSTR_BADDR" , 0x11f00000129c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT29_INSTR_BADDR" , 0x11f00000129d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT30_INSTR_BADDR" , 0x11f00000129e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT31_INSTR_BADDR" , 0x11f00000129f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_PKT0_INSTR_BAOFF_DBELL" , 0x11f0000012c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT1_INSTR_BAOFF_DBELL" , 0x11f0000012c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT2_INSTR_BAOFF_DBELL" , 0x11f0000012c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT3_INSTR_BAOFF_DBELL" , 0x11f0000012c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT4_INSTR_BAOFF_DBELL" , 0x11f0000012c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT5_INSTR_BAOFF_DBELL" , 0x11f0000012c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT6_INSTR_BAOFF_DBELL" , 0x11f0000012c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT7_INSTR_BAOFF_DBELL" , 0x11f0000012c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT8_INSTR_BAOFF_DBELL" , 0x11f0000012c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT9_INSTR_BAOFF_DBELL" , 0x11f0000012c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT10_INSTR_BAOFF_DBELL" , 0x11f0000012ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT11_INSTR_BAOFF_DBELL" , 0x11f0000012cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT12_INSTR_BAOFF_DBELL" , 0x11f0000012cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT13_INSTR_BAOFF_DBELL" , 0x11f0000012cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT14_INSTR_BAOFF_DBELL" , 0x11f0000012ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT15_INSTR_BAOFF_DBELL" , 0x11f0000012cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT16_INSTR_BAOFF_DBELL" , 0x11f0000012d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT17_INSTR_BAOFF_DBELL" , 0x11f0000012d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT18_INSTR_BAOFF_DBELL" , 0x11f0000012d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT19_INSTR_BAOFF_DBELL" , 0x11f0000012d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT20_INSTR_BAOFF_DBELL" , 0x11f0000012d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT21_INSTR_BAOFF_DBELL" , 0x11f0000012d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT22_INSTR_BAOFF_DBELL" , 0x11f0000012d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT23_INSTR_BAOFF_DBELL" , 0x11f0000012d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT24_INSTR_BAOFF_DBELL" , 0x11f0000012d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT25_INSTR_BAOFF_DBELL" , 0x11f0000012d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT26_INSTR_BAOFF_DBELL" , 0x11f0000012da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT27_INSTR_BAOFF_DBELL" , 0x11f0000012db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT28_INSTR_BAOFF_DBELL" , 0x11f0000012dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT29_INSTR_BAOFF_DBELL" , 0x11f0000012dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT30_INSTR_BAOFF_DBELL" , 0x11f0000012de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT31_INSTR_BAOFF_DBELL" , 0x11f0000012df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_PKT0_INSTR_FIFO_RSIZE" , 0x11f0000013000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT1_INSTR_FIFO_RSIZE" , 0x11f0000013010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT2_INSTR_FIFO_RSIZE" , 0x11f0000013020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT3_INSTR_FIFO_RSIZE" , 0x11f0000013030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT4_INSTR_FIFO_RSIZE" , 0x11f0000013040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT5_INSTR_FIFO_RSIZE" , 0x11f0000013050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT6_INSTR_FIFO_RSIZE" , 0x11f0000013060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT7_INSTR_FIFO_RSIZE" , 0x11f0000013070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT8_INSTR_FIFO_RSIZE" , 0x11f0000013080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT9_INSTR_FIFO_RSIZE" , 0x11f0000013090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT10_INSTR_FIFO_RSIZE" , 0x11f00000130a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT11_INSTR_FIFO_RSIZE" , 0x11f00000130b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT12_INSTR_FIFO_RSIZE" , 0x11f00000130c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT13_INSTR_FIFO_RSIZE" , 0x11f00000130d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT14_INSTR_FIFO_RSIZE" , 0x11f00000130e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT15_INSTR_FIFO_RSIZE" , 0x11f00000130f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT16_INSTR_FIFO_RSIZE" , 0x11f0000013100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT17_INSTR_FIFO_RSIZE" , 0x11f0000013110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT18_INSTR_FIFO_RSIZE" , 0x11f0000013120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT19_INSTR_FIFO_RSIZE" , 0x11f0000013130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT20_INSTR_FIFO_RSIZE" , 0x11f0000013140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT21_INSTR_FIFO_RSIZE" , 0x11f0000013150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT22_INSTR_FIFO_RSIZE" , 0x11f0000013160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT23_INSTR_FIFO_RSIZE" , 0x11f0000013170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT24_INSTR_FIFO_RSIZE" , 0x11f0000013180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT25_INSTR_FIFO_RSIZE" , 0x11f0000013190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT26_INSTR_FIFO_RSIZE" , 0x11f00000131a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT27_INSTR_FIFO_RSIZE" , 0x11f00000131b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT28_INSTR_FIFO_RSIZE" , 0x11f00000131c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT29_INSTR_FIFO_RSIZE" , 0x11f00000131d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT30_INSTR_FIFO_RSIZE" , 0x11f00000131e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT31_INSTR_FIFO_RSIZE" , 0x11f00000131f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_PKT0_INSTR_HEADER" , 0x11f0000013400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT1_INSTR_HEADER" , 0x11f0000013410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT2_INSTR_HEADER" , 0x11f0000013420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT3_INSTR_HEADER" , 0x11f0000013430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT4_INSTR_HEADER" , 0x11f0000013440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT5_INSTR_HEADER" , 0x11f0000013450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT6_INSTR_HEADER" , 0x11f0000013460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT7_INSTR_HEADER" , 0x11f0000013470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT8_INSTR_HEADER" , 0x11f0000013480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT9_INSTR_HEADER" , 0x11f0000013490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT10_INSTR_HEADER" , 0x11f00000134a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT11_INSTR_HEADER" , 0x11f00000134b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT12_INSTR_HEADER" , 0x11f00000134c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT13_INSTR_HEADER" , 0x11f00000134d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT14_INSTR_HEADER" , 0x11f00000134e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT15_INSTR_HEADER" , 0x11f00000134f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT16_INSTR_HEADER" , 0x11f0000013500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT17_INSTR_HEADER" , 0x11f0000013510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT18_INSTR_HEADER" , 0x11f0000013520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT19_INSTR_HEADER" , 0x11f0000013530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT20_INSTR_HEADER" , 0x11f0000013540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT21_INSTR_HEADER" , 0x11f0000013550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT22_INSTR_HEADER" , 0x11f0000013560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT23_INSTR_HEADER" , 0x11f0000013570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT24_INSTR_HEADER" , 0x11f0000013580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT25_INSTR_HEADER" , 0x11f0000013590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT26_INSTR_HEADER" , 0x11f00000135a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT27_INSTR_HEADER" , 0x11f00000135b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT28_INSTR_HEADER" , 0x11f00000135c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT29_INSTR_HEADER" , 0x11f00000135d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT30_INSTR_HEADER" , 0x11f00000135e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT31_INSTR_HEADER" , 0x11f00000135f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PKT0_OUT_SIZE" , 0x11f0000010c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT1_OUT_SIZE" , 0x11f0000010c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT2_OUT_SIZE" , 0x11f0000010c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT3_OUT_SIZE" , 0x11f0000010c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT4_OUT_SIZE" , 0x11f0000010c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT5_OUT_SIZE" , 0x11f0000010c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT6_OUT_SIZE" , 0x11f0000010c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT7_OUT_SIZE" , 0x11f0000010c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT8_OUT_SIZE" , 0x11f0000010c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT9_OUT_SIZE" , 0x11f0000010c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT10_OUT_SIZE" , 0x11f0000010ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT11_OUT_SIZE" , 0x11f0000010cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT12_OUT_SIZE" , 0x11f0000010cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT13_OUT_SIZE" , 0x11f0000010cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT14_OUT_SIZE" , 0x11f0000010ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT15_OUT_SIZE" , 0x11f0000010cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT16_OUT_SIZE" , 0x11f0000010d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT17_OUT_SIZE" , 0x11f0000010d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT18_OUT_SIZE" , 0x11f0000010d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT19_OUT_SIZE" , 0x11f0000010d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT20_OUT_SIZE" , 0x11f0000010d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT21_OUT_SIZE" , 0x11f0000010d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT22_OUT_SIZE" , 0x11f0000010d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT23_OUT_SIZE" , 0x11f0000010d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT24_OUT_SIZE" , 0x11f0000010d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT25_OUT_SIZE" , 0x11f0000010d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT26_OUT_SIZE" , 0x11f0000010da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT27_OUT_SIZE" , 0x11f0000010db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT28_OUT_SIZE" , 0x11f0000010dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT29_OUT_SIZE" , 0x11f0000010dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT30_OUT_SIZE" , 0x11f0000010de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT31_OUT_SIZE" , 0x11f0000010df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PKT0_SLIST_BADDR" , 0x11f0000011400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT1_SLIST_BADDR" , 0x11f0000011410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT2_SLIST_BADDR" , 0x11f0000011420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT3_SLIST_BADDR" , 0x11f0000011430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT4_SLIST_BADDR" , 0x11f0000011440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT5_SLIST_BADDR" , 0x11f0000011450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT6_SLIST_BADDR" , 0x11f0000011460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT7_SLIST_BADDR" , 0x11f0000011470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT8_SLIST_BADDR" , 0x11f0000011480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT9_SLIST_BADDR" , 0x11f0000011490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT10_SLIST_BADDR" , 0x11f00000114a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT11_SLIST_BADDR" , 0x11f00000114b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT12_SLIST_BADDR" , 0x11f00000114c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT13_SLIST_BADDR" , 0x11f00000114d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT14_SLIST_BADDR" , 0x11f00000114e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT15_SLIST_BADDR" , 0x11f00000114f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT16_SLIST_BADDR" , 0x11f0000011500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT17_SLIST_BADDR" , 0x11f0000011510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT18_SLIST_BADDR" , 0x11f0000011520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT19_SLIST_BADDR" , 0x11f0000011530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT20_SLIST_BADDR" , 0x11f0000011540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT21_SLIST_BADDR" , 0x11f0000011550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT22_SLIST_BADDR" , 0x11f0000011560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT23_SLIST_BADDR" , 0x11f0000011570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT24_SLIST_BADDR" , 0x11f0000011580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT25_SLIST_BADDR" , 0x11f0000011590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT26_SLIST_BADDR" , 0x11f00000115a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT27_SLIST_BADDR" , 0x11f00000115b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT28_SLIST_BADDR" , 0x11f00000115c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT29_SLIST_BADDR" , 0x11f00000115d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT30_SLIST_BADDR" , 0x11f00000115e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT31_SLIST_BADDR" , 0x11f00000115f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PKT0_SLIST_BAOFF_DBELL" , 0x11f0000011800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT1_SLIST_BAOFF_DBELL" , 0x11f0000011810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT2_SLIST_BAOFF_DBELL" , 0x11f0000011820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT3_SLIST_BAOFF_DBELL" , 0x11f0000011830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT4_SLIST_BAOFF_DBELL" , 0x11f0000011840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT5_SLIST_BAOFF_DBELL" , 0x11f0000011850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT6_SLIST_BAOFF_DBELL" , 0x11f0000011860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT7_SLIST_BAOFF_DBELL" , 0x11f0000011870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT8_SLIST_BAOFF_DBELL" , 0x11f0000011880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT9_SLIST_BAOFF_DBELL" , 0x11f0000011890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT10_SLIST_BAOFF_DBELL" , 0x11f00000118a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT11_SLIST_BAOFF_DBELL" , 0x11f00000118b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT12_SLIST_BAOFF_DBELL" , 0x11f00000118c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT13_SLIST_BAOFF_DBELL" , 0x11f00000118d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT14_SLIST_BAOFF_DBELL" , 0x11f00000118e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT15_SLIST_BAOFF_DBELL" , 0x11f00000118f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT16_SLIST_BAOFF_DBELL" , 0x11f0000011900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT17_SLIST_BAOFF_DBELL" , 0x11f0000011910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT18_SLIST_BAOFF_DBELL" , 0x11f0000011920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT19_SLIST_BAOFF_DBELL" , 0x11f0000011930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT20_SLIST_BAOFF_DBELL" , 0x11f0000011940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT21_SLIST_BAOFF_DBELL" , 0x11f0000011950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT22_SLIST_BAOFF_DBELL" , 0x11f0000011960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT23_SLIST_BAOFF_DBELL" , 0x11f0000011970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT24_SLIST_BAOFF_DBELL" , 0x11f0000011980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT25_SLIST_BAOFF_DBELL" , 0x11f0000011990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT26_SLIST_BAOFF_DBELL" , 0x11f00000119a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT27_SLIST_BAOFF_DBELL" , 0x11f00000119b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT28_SLIST_BAOFF_DBELL" , 0x11f00000119c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT29_SLIST_BAOFF_DBELL" , 0x11f00000119d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT30_SLIST_BAOFF_DBELL" , 0x11f00000119e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT31_SLIST_BAOFF_DBELL" , 0x11f00000119f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PKT0_SLIST_FIFO_RSIZE" , 0x11f0000011c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT1_SLIST_FIFO_RSIZE" , 0x11f0000011c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT2_SLIST_FIFO_RSIZE" , 0x11f0000011c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT3_SLIST_FIFO_RSIZE" , 0x11f0000011c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT4_SLIST_FIFO_RSIZE" , 0x11f0000011c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT5_SLIST_FIFO_RSIZE" , 0x11f0000011c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT6_SLIST_FIFO_RSIZE" , 0x11f0000011c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT7_SLIST_FIFO_RSIZE" , 0x11f0000011c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT8_SLIST_FIFO_RSIZE" , 0x11f0000011c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT9_SLIST_FIFO_RSIZE" , 0x11f0000011c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT10_SLIST_FIFO_RSIZE" , 0x11f0000011ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT11_SLIST_FIFO_RSIZE" , 0x11f0000011cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT12_SLIST_FIFO_RSIZE" , 0x11f0000011cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT13_SLIST_FIFO_RSIZE" , 0x11f0000011cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT14_SLIST_FIFO_RSIZE" , 0x11f0000011ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT15_SLIST_FIFO_RSIZE" , 0x11f0000011cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT16_SLIST_FIFO_RSIZE" , 0x11f0000011d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT17_SLIST_FIFO_RSIZE" , 0x11f0000011d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT18_SLIST_FIFO_RSIZE" , 0x11f0000011d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT19_SLIST_FIFO_RSIZE" , 0x11f0000011d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT20_SLIST_FIFO_RSIZE" , 0x11f0000011d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT21_SLIST_FIFO_RSIZE" , 0x11f0000011d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT22_SLIST_FIFO_RSIZE" , 0x11f0000011d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT23_SLIST_FIFO_RSIZE" , 0x11f0000011d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT24_SLIST_FIFO_RSIZE" , 0x11f0000011d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT25_SLIST_FIFO_RSIZE" , 0x11f0000011d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT26_SLIST_FIFO_RSIZE" , 0x11f0000011da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT27_SLIST_FIFO_RSIZE" , 0x11f0000011db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT28_SLIST_FIFO_RSIZE" , 0x11f0000011dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT29_SLIST_FIFO_RSIZE" , 0x11f0000011dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT30_SLIST_FIFO_RSIZE" , 0x11f0000011de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT31_SLIST_FIFO_RSIZE" , 0x11f0000011df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT_CNT_INT" , 0x11f0000011130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT_CNT_INT_ENB" , 0x11f0000011150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT_CTL" , 0x11f0000011220ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT_DATA_OUT_ES" , 0x11f00000110b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT_DATA_OUT_NS" , 0x11f00000110a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT_DATA_OUT_ROR" , 0x11f0000011090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT_DPADDR" , 0x11f0000011080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT_IN_BP" , 0x11f0000011210ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT_IN_DONE0_CNTS" , 0x11f0000012000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE1_CNTS" , 0x11f0000012010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE2_CNTS" , 0x11f0000012020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE3_CNTS" , 0x11f0000012030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE4_CNTS" , 0x11f0000012040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE5_CNTS" , 0x11f0000012050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE6_CNTS" , 0x11f0000012060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE7_CNTS" , 0x11f0000012070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE8_CNTS" , 0x11f0000012080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE9_CNTS" , 0x11f0000012090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE10_CNTS" , 0x11f00000120a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE11_CNTS" , 0x11f00000120b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE12_CNTS" , 0x11f00000120c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE13_CNTS" , 0x11f00000120d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE14_CNTS" , 0x11f00000120e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE15_CNTS" , 0x11f00000120f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE16_CNTS" , 0x11f0000012100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE17_CNTS" , 0x11f0000012110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE18_CNTS" , 0x11f0000012120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE19_CNTS" , 0x11f0000012130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE20_CNTS" , 0x11f0000012140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE21_CNTS" , 0x11f0000012150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE22_CNTS" , 0x11f0000012160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE23_CNTS" , 0x11f0000012170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE24_CNTS" , 0x11f0000012180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE25_CNTS" , 0x11f0000012190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE26_CNTS" , 0x11f00000121a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE27_CNTS" , 0x11f00000121b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE28_CNTS" , 0x11f00000121c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE29_CNTS" , 0x11f00000121d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE30_CNTS" , 0x11f00000121e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_DONE31_CNTS" , 0x11f00000121f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT_IN_INSTR_COUNTS" , 0x11f0000011200ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT_IN_PCIE_PORT" , 0x11f00000111b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 952},
- {"SLI_PKT_INPUT_CONTROL" , 0x11f0000011170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 953},
- {"SLI_PKT_INSTR_ENB" , 0x11f0000011000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 954},
- {"SLI_PKT_INSTR_RD_SIZE" , 0x11f00000111a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 955},
- {"SLI_PKT_INSTR_SIZE" , 0x11f0000011020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 956},
- {"SLI_PKT_INT_LEVELS" , 0x11f0000011120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 957},
- {"SLI_PKT_IPTR" , 0x11f0000011070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 958},
- {"SLI_PKT_OUT_BMODE" , 0x11f00000110d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 959},
- {"SLI_PKT_OUT_ENB" , 0x11f0000011010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_OUTPUT_WMARK" , 0x11f0000011180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 961},
- {"SLI_PKT_PCIE_PORT" , 0x11f00000110e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 962},
- {"SLI_PKT_PORT_IN_RST" , 0x11f00000111f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 963},
- {"SLI_PKT_SLIST_ES" , 0x11f0000011050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 964},
- {"SLI_PKT_SLIST_NS" , 0x11f0000011040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 965},
- {"SLI_PKT_SLIST_ROR" , 0x11f0000011030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 966},
- {"SLI_PKT_TIME_INT" , 0x11f0000011140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 967},
- {"SLI_PKT_TIME_INT_ENB" , 0x11f0000011160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 968},
- {"SLI_S2M_PORT0_CTL" , 0x11f0000013d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_S2M_PORT1_CTL" , 0x11f0000013d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_SCRATCH_1" , 0x11f00000103c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 970},
- {"SLI_SCRATCH_2" , 0x11f00000103d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 971},
- {"SLI_STATE1" , 0x11f0000010620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 972},
- {"SLI_STATE2" , 0x11f0000010630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 973},
- {"SLI_STATE3" , 0x11f0000010640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 974},
- {"SLI_WIN_RD_ADDR" , 0x10ull, CVMX_CSR_DB_TYPE_PEXP, 64, 975},
- {"SLI_WIN_RD_DATA" , 0x40ull, CVMX_CSR_DB_TYPE_PEXP, 64, 976},
- {"SLI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PEXP, 64, 977},
- {"SLI_WIN_WR_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PEXP, 64, 978},
- {"SLI_WIN_WR_MASK" , 0x30ull, CVMX_CSR_DB_TYPE_PEXP, 64, 979},
- {"SLI_WINDOW_CTL" , 0x11f00000102e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 980},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 981},
- {"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 981},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 982},
- {"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 982},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 983},
- {"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 983},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 984},
- {"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 984},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 985},
- {"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 985},
- {"SMI_DRV_CTL" , 0x1180000001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"SRIO0_ACC_CTRL" , 0x11800c8000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 987},
- {"SRIO1_ACC_CTRL" , 0x11800c9000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 987},
- {"SRIO0_ASMBLY_ID" , 0x11800c8000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 988},
- {"SRIO1_ASMBLY_ID" , 0x11800c9000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 988},
- {"SRIO0_ASMBLY_INFO" , 0x11800c8000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"SRIO1_ASMBLY_INFO" , 0x11800c9000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"SRIO0_BELL_RESP_CTRL" , 0x11800c8000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"SRIO1_BELL_RESP_CTRL" , 0x11800c9000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"SRIO0_BIST_STATUS" , 0x11800c8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 991},
- {"SRIO1_BIST_STATUS" , 0x11800c9000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 991},
- {"SRIO0_IMSG_CTRL" , 0x11800c8000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 992},
- {"SRIO1_IMSG_CTRL" , 0x11800c9000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 992},
- {"SRIO0_IMSG_INST_HDR000" , 0x11800c8000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 993},
- {"SRIO0_IMSG_INST_HDR001" , 0x11800c8000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 993},
- {"SRIO1_IMSG_INST_HDR000" , 0x11800c9000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 993},
- {"SRIO1_IMSG_INST_HDR001" , 0x11800c9000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 993},
- {"SRIO0_IMSG_QOS_GRP000" , 0x11800c8000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP001" , 0x11800c8000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP002" , 0x11800c8000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP003" , 0x11800c8000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP004" , 0x11800c8000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP005" , 0x11800c8000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP006" , 0x11800c8000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP007" , 0x11800c8000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP008" , 0x11800c8000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP009" , 0x11800c8000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP010" , 0x11800c8000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP011" , 0x11800c8000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP012" , 0x11800c8000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP013" , 0x11800c8000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP014" , 0x11800c8000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP015" , 0x11800c8000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP016" , 0x11800c8000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP017" , 0x11800c8000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP018" , 0x11800c8000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP019" , 0x11800c8000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP020" , 0x11800c80006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP021" , 0x11800c80006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP022" , 0x11800c80006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP023" , 0x11800c80006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP024" , 0x11800c80006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP025" , 0x11800c80006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP026" , 0x11800c80006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP027" , 0x11800c80006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP028" , 0x11800c80006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP029" , 0x11800c80006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP030" , 0x11800c80006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_QOS_GRP031" , 0x11800c80006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP000" , 0x11800c9000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP001" , 0x11800c9000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP002" , 0x11800c9000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP003" , 0x11800c9000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP004" , 0x11800c9000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP005" , 0x11800c9000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP006" , 0x11800c9000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP007" , 0x11800c9000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP008" , 0x11800c9000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP009" , 0x11800c9000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP010" , 0x11800c9000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP011" , 0x11800c9000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP012" , 0x11800c9000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP013" , 0x11800c9000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP014" , 0x11800c9000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP015" , 0x11800c9000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP016" , 0x11800c9000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP017" , 0x11800c9000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP018" , 0x11800c9000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP019" , 0x11800c9000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP020" , 0x11800c90006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP021" , 0x11800c90006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP022" , 0x11800c90006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP023" , 0x11800c90006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP024" , 0x11800c90006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP025" , 0x11800c90006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP026" , 0x11800c90006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP027" , 0x11800c90006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP028" , 0x11800c90006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP029" , 0x11800c90006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP030" , 0x11800c90006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO1_IMSG_QOS_GRP031" , 0x11800c90006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SRIO0_IMSG_STATUS000" , 0x11800c8000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS001" , 0x11800c8000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS002" , 0x11800c8000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS003" , 0x11800c8000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS004" , 0x11800c8000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS005" , 0x11800c8000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS006" , 0x11800c8000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS007" , 0x11800c8000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS008" , 0x11800c8000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS009" , 0x11800c8000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS010" , 0x11800c8000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS011" , 0x11800c8000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS012" , 0x11800c8000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS013" , 0x11800c8000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS014" , 0x11800c8000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS015" , 0x11800c8000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS016" , 0x11800c8000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS017" , 0x11800c8000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS018" , 0x11800c8000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS019" , 0x11800c8000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS020" , 0x11800c80007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS021" , 0x11800c80007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS022" , 0x11800c80007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_STATUS023" , 0x11800c80007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS000" , 0x11800c9000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS001" , 0x11800c9000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS002" , 0x11800c9000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS003" , 0x11800c9000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS004" , 0x11800c9000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS005" , 0x11800c9000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS006" , 0x11800c9000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS007" , 0x11800c9000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS008" , 0x11800c9000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS009" , 0x11800c9000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS010" , 0x11800c9000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS011" , 0x11800c9000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS012" , 0x11800c9000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS013" , 0x11800c9000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS014" , 0x11800c9000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS015" , 0x11800c9000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS016" , 0x11800c9000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS017" , 0x11800c9000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS018" , 0x11800c9000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS019" , 0x11800c9000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS020" , 0x11800c90007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS021" , 0x11800c90007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS022" , 0x11800c90007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO1_IMSG_STATUS023" , 0x11800c90007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SRIO0_IMSG_VPORT_THR" , 0x11800c8000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 996},
- {"SRIO1_IMSG_VPORT_THR" , 0x11800c9000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 996},
- {"SRIO0_INT_ENABLE" , 0x11800c8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 997},
- {"SRIO1_INT_ENABLE" , 0x11800c9000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 997},
- {"SRIO0_INT_INFO0" , 0x11800c8000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 998},
- {"SRIO1_INT_INFO0" , 0x11800c9000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 998},
- {"SRIO0_INT_INFO1" , 0x11800c8000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 999},
- {"SRIO1_INT_INFO1" , 0x11800c9000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 999},
- {"SRIO0_INT_INFO2" , 0x11800c8000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1000},
- {"SRIO1_INT_INFO2" , 0x11800c9000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1000},
- {"SRIO0_INT_INFO3" , 0x11800c8000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1001},
- {"SRIO1_INT_INFO3" , 0x11800c9000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1001},
- {"SRIO0_INT_REG" , 0x11800c8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1002},
- {"SRIO1_INT_REG" , 0x11800c9000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1002},
- {"SRIO0_IP_FEATURE" , 0x11800c80003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1003},
- {"SRIO1_IP_FEATURE" , 0x11800c90003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1003},
- {"SRIO0_MAINT_OP" , 0x11800c8000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_MAINT_OP" , 0x11800c9000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_MAINT_RD_DATA" , 0x11800c8000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_MAINT_RD_DATA" , 0x11800c9000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_MCE_TX_CTL" , 0x11800c8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"SRIO1_MCE_TX_CTL" , 0x11800c9000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"SRIO0_MEM_OP_CTRL" , 0x11800c8000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"SRIO1_MEM_OP_CTRL" , 0x11800c9000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"SRIO0_OMSG_CTRL000" , 0x11800c8000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"SRIO0_OMSG_CTRL001" , 0x11800c80004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"SRIO1_OMSG_CTRL000" , 0x11800c9000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"SRIO1_OMSG_CTRL001" , 0x11800c90004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"SRIO0_OMSG_FMP_MR000" , 0x11800c8000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1009},
- {"SRIO0_OMSG_FMP_MR001" , 0x11800c80004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1009},
- {"SRIO1_OMSG_FMP_MR000" , 0x11800c9000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1009},
- {"SRIO1_OMSG_FMP_MR001" , 0x11800c90004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1009},
- {"SRIO0_OMSG_NMP_MR000" , 0x11800c80004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1010},
- {"SRIO0_OMSG_NMP_MR001" , 0x11800c80004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1010},
- {"SRIO1_OMSG_NMP_MR000" , 0x11800c90004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1010},
- {"SRIO1_OMSG_NMP_MR001" , 0x11800c90004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1010},
- {"SRIO0_OMSG_PORT000" , 0x11800c8000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"SRIO0_OMSG_PORT001" , 0x11800c80004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"SRIO1_OMSG_PORT000" , 0x11800c9000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"SRIO1_OMSG_PORT001" , 0x11800c90004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"SRIO0_OMSG_SP_MR000" , 0x11800c8000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"SRIO0_OMSG_SP_MR001" , 0x11800c80004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"SRIO1_OMSG_SP_MR000" , 0x11800c9000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"SRIO1_OMSG_SP_MR001" , 0x11800c90004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"SRIO0_RX_BELL" , 0x11800c8000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"SRIO1_RX_BELL" , 0x11800c9000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"SRIO0_RX_BELL_SEQ" , 0x11800c8000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"SRIO1_RX_BELL_SEQ" , 0x11800c9000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"SRIO0_RX_STATUS" , 0x11800c8000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"SRIO1_RX_STATUS" , 0x11800c9000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"SRIO0_S2M_TYPE000" , 0x11800c8000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE001" , 0x11800c8000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE002" , 0x11800c8000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE003" , 0x11800c8000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE004" , 0x11800c80001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE005" , 0x11800c80001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE006" , 0x11800c80001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE007" , 0x11800c80001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE008" , 0x11800c80001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE009" , 0x11800c80001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE010" , 0x11800c80001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE011" , 0x11800c80001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE012" , 0x11800c80001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE013" , 0x11800c80001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE014" , 0x11800c80001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_S2M_TYPE015" , 0x11800c80001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE000" , 0x11800c9000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE001" , 0x11800c9000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE002" , 0x11800c9000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE003" , 0x11800c9000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE004" , 0x11800c90001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE005" , 0x11800c90001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE006" , 0x11800c90001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE007" , 0x11800c90001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE008" , 0x11800c90001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE009" , 0x11800c90001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE010" , 0x11800c90001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE011" , 0x11800c90001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE012" , 0x11800c90001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE013" , 0x11800c90001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE014" , 0x11800c90001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_S2M_TYPE015" , 0x11800c90001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_SEQ" , 0x11800c8000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"SRIO1_SEQ" , 0x11800c9000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"SRIO0_STATUS_REG" , 0x11800c8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"SRIO1_STATUS_REG" , 0x11800c9000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"SRIO0_TAG_CTRL" , 0x11800c8000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"SRIO1_TAG_CTRL" , 0x11800c9000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"SRIO0_TLP_CREDITS" , 0x11800c8000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"SRIO1_TLP_CREDITS" , 0x11800c9000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"SRIO0_TX_BELL" , 0x11800c8000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"SRIO1_TX_BELL" , 0x11800c9000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"SRIO0_TX_BELL_INFO" , 0x11800c8000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"SRIO1_TX_BELL_INFO" , 0x11800c9000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"SRIO0_TX_CTRL" , 0x11800c8000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1023},
- {"SRIO1_TX_CTRL" , 0x11800c9000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1023},
- {"SRIO0_TX_STATUS" , 0x11800c8000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"SRIO1_TX_STATUS" , 0x11800c9000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"SRIOMAINT0_ASMBLY_ID" , 0x8ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1025},
- {"SRIOMAINT1_ASMBLY_ID" , 0x8ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1025},
- {"SRIOMAINT0_ASMBLY_INFO" , 0xcull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1026},
- {"SRIOMAINT1_ASMBLY_INFO" , 0xcull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1026},
- {"SRIOMAINT0_BAR1_IDX000" , 0x200010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX001" , 0x200014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX002" , 0x200018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX003" , 0x20001cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX004" , 0x200020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX005" , 0x200024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX006" , 0x200028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX007" , 0x20002cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX008" , 0x200030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX009" , 0x200034ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX010" , 0x200038ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX011" , 0x20003cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX012" , 0x200040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX013" , 0x200044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX014" , 0x200048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BAR1_IDX015" , 0x20004cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX000" , 0x200010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX001" , 0x200014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX002" , 0x200018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX003" , 0x20001cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX004" , 0x200020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX005" , 0x200024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX006" , 0x200028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX007" , 0x20002cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX008" , 0x200030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX009" , 0x200034ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX010" , 0x200038ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX011" , 0x20003cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX012" , 0x200040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX013" , 0x200044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX014" , 0x200048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT1_BAR1_IDX015" , 0x20004cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1027},
- {"SRIOMAINT0_BELL_STATUS" , 0x200080ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1028},
- {"SRIOMAINT1_BELL_STATUS" , 0x200080ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1028},
- {"SRIOMAINT0_COMP_TAG" , 0x6cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1029},
- {"SRIOMAINT1_COMP_TAG" , 0x6cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1029},
- {"SRIOMAINT0_CORE_ENABLES" , 0x200070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1030},
- {"SRIOMAINT1_CORE_ENABLES" , 0x200070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1030},
- {"SRIOMAINT0_DEV_ID" , 0x0ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1031},
- {"SRIOMAINT1_DEV_ID" , 0x0ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1031},
- {"SRIOMAINT0_DEV_REV" , 0x4ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1032},
- {"SRIOMAINT1_DEV_REV" , 0x4ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1032},
- {"SRIOMAINT0_DST_OPS" , 0x1cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1033},
- {"SRIOMAINT1_DST_OPS" , 0x1cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1033},
- {"SRIOMAINT0_ERB_ATTR_CAPT" , 0x2048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1034},
- {"SRIOMAINT1_ERB_ATTR_CAPT" , 0x2048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1034},
- {"SRIOMAINT0_ERB_ERR_DET" , 0x2040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1035},
- {"SRIOMAINT1_ERB_ERR_DET" , 0x2040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1035},
- {"SRIOMAINT0_ERB_ERR_RATE" , 0x2068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1036},
- {"SRIOMAINT1_ERB_ERR_RATE" , 0x2068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1036},
- {"SRIOMAINT0_ERB_ERR_RATE_EN" , 0x2044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1037},
- {"SRIOMAINT1_ERB_ERR_RATE_EN" , 0x2044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1037},
- {"SRIOMAINT0_ERB_ERR_RATE_THR" , 0x206cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1038},
- {"SRIOMAINT1_ERB_ERR_RATE_THR" , 0x206cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1038},
- {"SRIOMAINT0_ERB_HDR" , 0x2000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1039},
- {"SRIOMAINT1_ERB_HDR" , 0x2000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1039},
- {"SRIOMAINT0_ERB_LT_ADDR_CAPT_H", 0x2010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1040},
- {"SRIOMAINT1_ERB_LT_ADDR_CAPT_H", 0x2010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1040},
- {"SRIOMAINT0_ERB_LT_ADDR_CAPT_L", 0x2014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1041},
- {"SRIOMAINT1_ERB_LT_ADDR_CAPT_L", 0x2014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1041},
- {"SRIOMAINT0_ERB_LT_CTRL_CAPT" , 0x201cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1042},
- {"SRIOMAINT1_ERB_LT_CTRL_CAPT" , 0x201cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1042},
- {"SRIOMAINT0_ERB_LT_DEV_ID" , 0x2028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1043},
- {"SRIOMAINT1_ERB_LT_DEV_ID" , 0x2028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1043},
- {"SRIOMAINT0_ERB_LT_DEV_ID_CAPT", 0x2018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1044},
- {"SRIOMAINT1_ERB_LT_DEV_ID_CAPT", 0x2018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1044},
- {"SRIOMAINT0_ERB_LT_ERR_DET" , 0x2008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_ERB_LT_ERR_DET" , 0x2008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_ERB_LT_ERR_EN" , 0x200cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1046},
- {"SRIOMAINT1_ERB_LT_ERR_EN" , 0x200cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1046},
- {"SRIOMAINT0_ERB_PACK_CAPT_1" , 0x2050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1047},
- {"SRIOMAINT1_ERB_PACK_CAPT_1" , 0x2050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1047},
- {"SRIOMAINT0_ERB_PACK_CAPT_2" , 0x2054ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1048},
- {"SRIOMAINT1_ERB_PACK_CAPT_2" , 0x2054ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1048},
- {"SRIOMAINT0_ERB_PACK_CAPT_3" , 0x2058ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1049},
- {"SRIOMAINT1_ERB_PACK_CAPT_3" , 0x2058ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1049},
- {"SRIOMAINT0_ERB_PACK_SYM_CAPT", 0x204cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1050},
- {"SRIOMAINT1_ERB_PACK_SYM_CAPT", 0x204cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1050},
- {"SRIOMAINT0_HB_DEV_ID_LOCK" , 0x68ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1051},
- {"SRIOMAINT1_HB_DEV_ID_LOCK" , 0x68ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1051},
- {"SRIOMAINT0_IR_BUFFER_CONFIG" , 0x102000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1052},
- {"SRIOMAINT1_IR_BUFFER_CONFIG" , 0x102000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1052},
- {"SRIOMAINT0_IR_PD_PHY_CTRL" , 0x107028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1053},
- {"SRIOMAINT1_IR_PD_PHY_CTRL" , 0x107028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1053},
- {"SRIOMAINT0_IR_PD_PHY_STAT" , 0x10702cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1054},
- {"SRIOMAINT1_IR_PD_PHY_STAT" , 0x10702cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1054},
- {"SRIOMAINT0_IR_PI_PHY_CTRL" , 0x107020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1055},
- {"SRIOMAINT1_IR_PI_PHY_CTRL" , 0x107020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1055},
- {"SRIOMAINT0_IR_PI_PHY_STAT" , 0x107024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1056},
- {"SRIOMAINT1_IR_PI_PHY_STAT" , 0x107024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1056},
- {"SRIOMAINT0_IR_SP_RX_CTRL" , 0x10700cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1057},
- {"SRIOMAINT1_IR_SP_RX_CTRL" , 0x10700cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1057},
- {"SRIOMAINT0_IR_SP_RX_DATA" , 0x107014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1058},
- {"SRIOMAINT1_IR_SP_RX_DATA" , 0x107014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1058},
- {"SRIOMAINT0_IR_SP_RX_STAT" , 0x107010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1059},
- {"SRIOMAINT1_IR_SP_RX_STAT" , 0x107010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1059},
- {"SRIOMAINT0_IR_SP_TX_CTRL" , 0x107000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1060},
- {"SRIOMAINT1_IR_SP_TX_CTRL" , 0x107000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1060},
- {"SRIOMAINT0_IR_SP_TX_DATA" , 0x107008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1061},
- {"SRIOMAINT1_IR_SP_TX_DATA" , 0x107008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1061},
- {"SRIOMAINT0_IR_SP_TX_STAT" , 0x107004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1062},
- {"SRIOMAINT1_IR_SP_TX_STAT" , 0x107004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1062},
- {"SRIOMAINT0_LANE_000_STATUS_0", 0x1010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1063},
- {"SRIOMAINT0_LANE_001_STATUS_0", 0x1030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1063},
- {"SRIOMAINT0_LANE_002_STATUS_0", 0x1050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1063},
- {"SRIOMAINT0_LANE_003_STATUS_0", 0x1070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1063},
- {"SRIOMAINT1_LANE_000_STATUS_0", 0x1010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1063},
- {"SRIOMAINT1_LANE_001_STATUS_0", 0x1030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1063},
- {"SRIOMAINT1_LANE_002_STATUS_0", 0x1050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1063},
- {"SRIOMAINT1_LANE_003_STATUS_0", 0x1070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1063},
- {"SRIOMAINT0_LCS_BA0" , 0x58ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1064},
- {"SRIOMAINT1_LCS_BA0" , 0x58ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1064},
- {"SRIOMAINT0_LCS_BA1" , 0x5cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1065},
- {"SRIOMAINT1_LCS_BA1" , 0x5cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1065},
- {"SRIOMAINT0_M2S_BAR0_START0" , 0x200000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1066},
- {"SRIOMAINT1_M2S_BAR0_START0" , 0x200000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1066},
- {"SRIOMAINT0_M2S_BAR0_START1" , 0x200004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1067},
- {"SRIOMAINT1_M2S_BAR0_START1" , 0x200004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1067},
- {"SRIOMAINT0_M2S_BAR1_START0" , 0x200008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1068},
- {"SRIOMAINT1_M2S_BAR1_START0" , 0x200008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1068},
- {"SRIOMAINT0_M2S_BAR1_START1" , 0x20000cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1069},
- {"SRIOMAINT1_M2S_BAR1_START1" , 0x20000cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1069},
- {"SRIOMAINT0_M2S_BAR2_START" , 0x200050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1070},
- {"SRIOMAINT1_M2S_BAR2_START" , 0x200050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1070},
- {"SRIOMAINT0_PE_FEAT" , 0x10ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1071},
- {"SRIOMAINT1_PE_FEAT" , 0x10ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1071},
- {"SRIOMAINT0_PE_LLC" , 0x4cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1072},
- {"SRIOMAINT1_PE_LLC" , 0x4cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1072},
- {"SRIOMAINT0_PORT_0_CTL" , 0x15cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1073},
- {"SRIOMAINT1_PORT_0_CTL" , 0x15cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1073},
- {"SRIOMAINT0_PORT_0_CTL2" , 0x154ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1074},
- {"SRIOMAINT1_PORT_0_CTL2" , 0x154ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1074},
- {"SRIOMAINT0_PORT_0_ERR_STAT" , 0x158ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1075},
- {"SRIOMAINT1_PORT_0_ERR_STAT" , 0x158ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1075},
- {"SRIOMAINT0_PORT_GEN_CTL" , 0x13cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1076},
- {"SRIOMAINT1_PORT_GEN_CTL" , 0x13cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1076},
- {"SRIOMAINT0_PORT_LT_CTL" , 0x120ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1077},
- {"SRIOMAINT1_PORT_LT_CTL" , 0x120ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1077},
- {"SRIOMAINT0_PORT_MBH0" , 0x100ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1078},
- {"SRIOMAINT1_PORT_MBH0" , 0x100ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1078},
- {"SRIOMAINT0_PORT_RT_CTL" , 0x124ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1079},
- {"SRIOMAINT1_PORT_RT_CTL" , 0x124ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1079},
- {"SRIOMAINT0_PRI_DEV_ID" , 0x60ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1080},
- {"SRIOMAINT1_PRI_DEV_ID" , 0x60ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1080},
- {"SRIOMAINT0_SEC_DEV_CTRL" , 0x200064ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1081},
- {"SRIOMAINT1_SEC_DEV_CTRL" , 0x200064ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1081},
- {"SRIOMAINT0_SEC_DEV_ID" , 0x200060ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1082},
- {"SRIOMAINT1_SEC_DEV_ID" , 0x200060ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1082},
- {"SRIOMAINT0_SERIAL_LANE_HDR" , 0x1000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1083},
- {"SRIOMAINT1_SERIAL_LANE_HDR" , 0x1000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1083},
- {"SRIOMAINT0_SRC_OPS" , 0x18ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1084},
- {"SRIOMAINT1_SRC_OPS" , 0x18ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1084},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1085},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1086},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1088},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1089},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1090},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1092},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1093},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1094},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1095},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1096},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1097},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1098},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1099},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1100},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1101},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1102},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1103},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1104},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1105},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1106},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1107},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1108},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1109},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1110},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1111},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1112},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1113},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1114},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1115},
- {"UAHC0_EHCI_ASYNCLISTADDR" , 0x16f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 1116},
- {"UAHC0_EHCI_CONFIGFLAG" , 0x16f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 1117},
- {"UAHC0_EHCI_CTRLDSSEGMENT" , 0x16f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 1118},
- {"UAHC0_EHCI_FRINDEX" , 0x16f000000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 1119},
- {"UAHC0_EHCI_HCCAPBASE" , 0x16f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 1120},
- {"UAHC0_EHCI_HCCPARAMS" , 0x16f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 1121},
- {"UAHC0_EHCI_HCSPARAMS" , 0x16f0000000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 1122},
- {"UAHC0_EHCI_INSNREG00" , 0x16f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 32, 1123},
- {"UAHC0_EHCI_INSNREG03" , 0x16f000000009cull, CVMX_CSR_DB_TYPE_NCB, 32, 1124},
- {"UAHC0_EHCI_INSNREG04" , 0x16f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 1125},
- {"UAHC0_EHCI_INSNREG06" , 0x16f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 1126},
- {"UAHC0_EHCI_INSNREG07" , 0x16f00000000ecull, CVMX_CSR_DB_TYPE_NCB, 32, 1127},
- {"UAHC0_EHCI_PERIODICLISTBASE" , 0x16f0000000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 1128},
- {"UAHC0_EHCI_PORTSC001" , 0x16f0000000054ull, CVMX_CSR_DB_TYPE_NCB, 32, 1129},
- {"UAHC0_EHCI_PORTSC002" , 0x16f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 32, 1129},
- {"UAHC0_EHCI_USBCMD" , 0x16f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 1130},
- {"UAHC0_EHCI_USBINTR" , 0x16f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 1131},
- {"UAHC0_EHCI_USBSTS" , 0x16f0000000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 1132},
- {"UAHC0_OHCI0_HCBULKCURRENTED" , 0x16f000000042cull, CVMX_CSR_DB_TYPE_NCB, 32, 1133},
- {"UAHC0_OHCI0_HCBULKHEADED" , 0x16f0000000428ull, CVMX_CSR_DB_TYPE_NCB, 32, 1134},
- {"UAHC0_OHCI0_HCCOMMANDSTATUS" , 0x16f0000000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 1135},
- {"UAHC0_OHCI0_HCCONTROL" , 0x16f0000000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 1136},
- {"UAHC0_OHCI0_HCCONTROLCURRENTED", 0x16f0000000424ull, CVMX_CSR_DB_TYPE_NCB, 32, 1137},
- {"UAHC0_OHCI0_HCCONTROLHEADED" , 0x16f0000000420ull, CVMX_CSR_DB_TYPE_NCB, 32, 1138},
- {"UAHC0_OHCI0_HCDONEHEAD" , 0x16f0000000430ull, CVMX_CSR_DB_TYPE_NCB, 32, 1139},
- {"UAHC0_OHCI0_HCFMINTERVAL" , 0x16f0000000434ull, CVMX_CSR_DB_TYPE_NCB, 32, 1140},
- {"UAHC0_OHCI0_HCFMNUMBER" , 0x16f000000043cull, CVMX_CSR_DB_TYPE_NCB, 32, 1141},
- {"UAHC0_OHCI0_HCFMREMAINING" , 0x16f0000000438ull, CVMX_CSR_DB_TYPE_NCB, 32, 1142},
- {"UAHC0_OHCI0_HCHCCA" , 0x16f0000000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 1143},
- {"UAHC0_OHCI0_HCINTERRUPTDISABLE", 0x16f0000000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 1144},
- {"UAHC0_OHCI0_HCINTERRUPTENABLE", 0x16f0000000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 1145},
- {"UAHC0_OHCI0_HCINTERRUPTSTATUS", 0x16f000000040cull, CVMX_CSR_DB_TYPE_NCB, 32, 1146},
- {"UAHC0_OHCI0_HCLSTHRESHOLD" , 0x16f0000000444ull, CVMX_CSR_DB_TYPE_NCB, 32, 1147},
- {"UAHC0_OHCI0_HCPERIODCURRENTED", 0x16f000000041cull, CVMX_CSR_DB_TYPE_NCB, 32, 1148},
- {"UAHC0_OHCI0_HCPERIODICSTART" , 0x16f0000000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 1149},
- {"UAHC0_OHCI0_HCREVISION" , 0x16f0000000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 1150},
- {"UAHC0_OHCI0_HCRHDESCRIPTORA" , 0x16f0000000448ull, CVMX_CSR_DB_TYPE_NCB, 32, 1151},
- {"UAHC0_OHCI0_HCRHDESCRIPTORB" , 0x16f000000044cull, CVMX_CSR_DB_TYPE_NCB, 32, 1152},
- {"UAHC0_OHCI0_HCRHPORTSTATUS001", 0x16f0000000454ull, CVMX_CSR_DB_TYPE_NCB, 32, 1153},
- {"UAHC0_OHCI0_HCRHPORTSTATUS002", 0x16f0000000458ull, CVMX_CSR_DB_TYPE_NCB, 32, 1153},
- {"UAHC0_OHCI0_HCRHSTATUS" , 0x16f0000000450ull, CVMX_CSR_DB_TYPE_NCB, 32, 1154},
- {"UAHC0_OHCI0_INSNREG06" , 0x16f0000000498ull, CVMX_CSR_DB_TYPE_NCB, 32, 1155},
- {"UAHC0_OHCI0_INSNREG07" , 0x16f000000049cull, CVMX_CSR_DB_TYPE_NCB, 32, 1156},
- {"UCTL0_BIST_STATUS" , 0x118006f0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1157},
- {"UCTL0_CLK_RST_CTL" , 0x118006f000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1158},
- {"UCTL0_EHCI_CTL" , 0x118006f000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1159},
- {"UCTL0_EHCI_FLA" , 0x118006f0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1160},
- {"UCTL0_ERTO_CTL" , 0x118006f000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1161},
- {"UCTL0_IF_ENA" , 0x118006f000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1162},
- {"UCTL0_INT_ENA" , 0x118006f000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1163},
- {"UCTL0_INT_REG" , 0x118006f000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1164},
- {"UCTL0_OHCI_CTL" , 0x118006f000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1165},
- {"UCTL0_ORTO_CTL" , 0x118006f000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1166},
- {"UCTL0_PPAF_WM" , 0x118006f000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1167},
- {"UCTL0_UPHY_CTL_STATUS" , 0x118006f000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1168},
- {"UCTL0_UPHY_PORT000_CTL_STATUS", 0x118006f000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1169},
- {"UCTL0_UPHY_PORT001_CTL_STATUS", 0x118006f000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1169},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1170},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1171},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1172},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1173},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1174},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1175},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1176},
- {"ZIP_THROTTLE" , 0x1180038000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1177},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xxp1[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_21" , 4, 18, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_24_25" , 24, 2, 0, "RAZ", 1, 1, 0, 0},
- {"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRFLW1" , 35, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP1" , 36, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH1" , 37, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 0, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"RX_EN" , 4, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"TX_EN" , 5, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"BURST" , 6, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 2, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 2, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 2, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 2, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 3, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 4, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 9, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 10, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 10, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 10, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 10, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 11, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 12, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 13, "RO", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 7, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"NULL_DIS" , 10, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 13, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 13, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 14, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 14, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 15, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 15, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 16, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 16, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 17, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 18, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 19, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 19, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 20, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 20, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 21, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 21, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 21, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 22, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 22, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 23, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 23, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 27, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 27, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 32, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 32, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 33, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 33, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 34, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 35, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 35, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 36, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 36, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 37, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 37, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 38, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 38, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 39, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 39, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 40, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 41, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 60, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 2, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 61, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 64, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 64, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 64, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 64, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 64, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 64, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 65, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 65, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 65, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 65, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 65, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 65, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 68, "RAZ", 1, 1, 0, 0},
- {"BP" , 4, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 68, "RAZ", 1, 1, 0, 0},
- {"EN" , 8, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 68, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 1, 71, "R/W", 0, 1, 1ull, 0},
- {"CLKRST" , 1, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"ENABLE" , 2, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"COMP" , 3, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"DLLRST" , 4, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_SET" , 8, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_14" , 13, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_BYP" , 15, 1, 71, "R/W", 0, 1, 1ull, 0},
- {"CLKRX_SET" , 16, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_22" , 21, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKRX_BYP" , 23, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"CLK_SET" , 24, 5, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_NCTL" , 32, 6, 71, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_38_39" , 38, 2, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_PCTL" , 40, 6, 71, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_46_47" , 46, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_NCTL" , 48, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_54_55" , 54, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_PCTL" , 56, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_BYP" , 63, 1, 71, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 5, 72, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 72, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 73, "RAZ", 1, 1, 0, 0},
- {"SLI" , 3, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 73, "RAZ", 1, 1, 0, 0},
- {"IPD" , 9, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 14, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 73, "RAZ", 1, 1, 0, 0},
- {"L2C" , 16, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 17, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 73, "RAZ", 1, 1, 0, 0},
- {"PIP" , 20, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 73, "RAZ", 1, 1, 0, 0},
- {"ASXPCS0" , 22, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_24" , 23, 2, 73, "RAZ", 1, 1, 0, 0},
- {"PEM0" , 25, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 26, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 73, "RAZ", 1, 1, 0, 0},
- {"AGL" , 28, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_29" , 29, 1, 73, "RAZ", 1, 1, 0, 0},
- {"IOB" , 30, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 73, "RAZ", 1, 1, 0, 0},
- {"SRIO0" , 32, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"SRIO1" , 33, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 73, "RAZ", 1, 1, 0, 0},
- {"DFM" , 40, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 41, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 42, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 73, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 6, 74, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 74, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 6, 75, "RO", 1, 1, 0, 0},
- {"RESERVED_6_63" , 6, 58, 75, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 76, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 77, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 77, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 77, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 77, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 77, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 78, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 78, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 78, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 78, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 79, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 79, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 79, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 79, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 80, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 80, "R/W", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 80, "R/W", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 81, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 82, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 83, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 83, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 83, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 83, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 83, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 83, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 83, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 83, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 83, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 83, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 84, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 84, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 84, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 84, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 85, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 85, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 85, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 85, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 86, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 86, "R/W", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 86, "R/W", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 87, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 88, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 89, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 89, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 89, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 89, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 89, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 89, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 89, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 89, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 89, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 90, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 90, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 90, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 90, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 90, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 90, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 90, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 90, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 90, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 91, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 91, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 91, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 91, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 91, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 91, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 91, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 91, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 91, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 91, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 92, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 92, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 92, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 92, "RAZ", 1, 1, 0, 0},
- {"DFM" , 56, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 92, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 92, "RO", 0, 0, 0ull, 0ull},
- {"BITS" , 0, 32, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 93, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 94, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 6, 95, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 95, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 96, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 96, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 6, 97, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 97, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 98, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 99, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 5, 99, "R/W", 0, 0, 31ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 99, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 100, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 100, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 100, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 100, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 4, 100, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_30" , 20, 11, 100, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 100, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 100, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 101, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 101, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 101, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 4, 101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_30" , 20, 11, 101, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 101, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 102, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 102, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 102, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 102, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 4, 102, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_30" , 20, 11, 102, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 102, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 102, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 3, 103, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 103, "RAZ", 1, 1, 0, 0},
- {"MUX_SEL" , 4, 2, 103, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 103, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 103, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 103, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 104, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_39" , 37, 3, 104, "RAZ", 1, 1, 0, 0},
- {"SELECT" , 40, 3, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_60" , 43, 18, 104, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 104, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 104, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 104, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 105, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 105, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 106, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 106, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 107, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 107, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 108, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 108, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 109, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 109, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 109, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 110, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 110, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 110, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 110, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 110, "RAZ", 1, 1, 0, 0},
- {"PDB" , 0, 1, 111, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 111, "RAZ", 0, 0, 0ull, 0ull},
- {"RDF" , 4, 1, 111, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 111, "RAZ", 0, 0, 0ull, 0ull},
- {"DTX" , 8, 2, 111, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 111, "RAZ", 0, 0, 0ull, 0ull},
- {"STX" , 16, 2, 111, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_23" , 18, 6, 111, "RAZ", 0, 0, 0ull, 0ull},
- {"GFB" , 24, 1, 111, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 111, "RAZ", 0, 0, 0ull, 0ull},
- {"MWB" , 28, 1, 111, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 111, "RAZ", 0, 0, 0ull, 0ull},
- {"GFU" , 0, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"GIB" , 1, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"GIF" , 2, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"NCD" , 3, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"GUTP" , 4, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 112, "RAZ", 0, 0, 0ull, 0ull},
- {"GUTV" , 8, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 9, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"RAM1" , 10, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"RAM2" , 11, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"RAM3" , 12, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 112, "RAZ", 0, 0, 0ull, 0ull},
- {"DTECLKDIS" , 0, 1, 113, "R/W", 0, 0, 1ull, 0ull},
- {"CLDTECRIP" , 1, 3, 113, "R/W", 0, 0, 0ull, 0ull},
- {"CLMSKCRIP" , 4, 4, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 113, "RAZ", 1, 1, 0, 0},
- {"IMODE" , 0, 1, 114, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 1, 1, 114, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 2, 1, 114, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_4" , 3, 2, 114, "RAZ", 1, 1, 0, 0},
- {"SBDLCK" , 5, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"SBDNUM" , 6, 4, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 114, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 20, 115, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 115, "RAZ", 1, 1, 0, 0},
- {"SBD0" , 0, 64, 116, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 117, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 118, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 119, "RO", 1, 1, 0, 0},
- {"SIZE" , 0, 9, 120, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 120, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 120, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_20_63" , 20, 44, 120, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 121, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 35, 121, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 121, "RAZ", 1, 1, 0, 0},
- {"RAM1FADR" , 0, 14, 122, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 122, "RAZ", 1, 1, 0, 0},
- {"RAM2FADR" , 16, 9, 122, "RO", 1, 1, 0, 0},
- {"RESERVED_25_31" , 25, 7, 122, "RAZ", 1, 1, 0, 0},
- {"RAM3FADR" , 32, 12, 122, "RO", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 122, "RAZ", 1, 1, 0, 0},
- {"DBLOVF" , 0, 1, 123, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC0PERR" , 1, 3, 123, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 123, "RAZ", 1, 1, 0, 0},
- {"CNDRD" , 16, 1, 123, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 123, "RAZ", 1, 1, 0, 0},
- {"DBLINA" , 0, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"DC0PENA" , 1, 3, 124, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 124, "RAZ", 1, 1, 0, 0},
- {"HIDAT" , 0, 64, 125, "R/W", 1, 1, 0, 0},
- {"PFCNT0" , 0, 64, 126, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 127, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 127, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 127, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 127, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 127, "RAZ", 1, 1, 0, 0},
- {"PFCNT1" , 0, 64, 128, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 129, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 129, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 129, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 129, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 129, "RAZ", 1, 1, 0, 0},
- {"PFCNT2" , 0, 64, 130, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 131, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 131, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 131, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 131, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 131, "RAZ", 1, 1, 0, 0},
- {"PFCNT3" , 0, 64, 132, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 133, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 133, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 133, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 133, "RAZ", 1, 1, 0, 0},
- {"CNT0ENA" , 0, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 1, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 2, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 3, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0WCLR" , 4, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1WCLR" , 5, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2WCLR" , 6, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3WCLR" , 7, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RCLR" , 8, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RCLR" , 9, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RCLR" , 10, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RCLR" , 11, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"SNODE" , 12, 3, 134, "R/W", 0, 0, 0ull, 0ull},
- {"ENODE" , 15, 3, 134, "R/W", 0, 0, 0ull, 0ull},
- {"EDNODE" , 18, 2, 134, "R/W", 0, 0, 0ull, 0ull},
- {"PMODE" , 20, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"VGID" , 21, 8, 134, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 134, "RAZ", 1, 1, 0, 0},
- {"PRBS" , 0, 32, 135, "R/W", 1, 1, 0, 0},
- {"PROG" , 32, 8, 135, "R/W", 1, 1, 0, 0},
- {"SEL" , 40, 1, 135, "R/W", 1, 1, 0, 0},
- {"EN" , 41, 1, 135, "R/W", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 135, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 16, 136, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 136, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 16, 137, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 137, "R/W", 1, 1, 0, 0},
- {"DQX_CTL" , 0, 4, 138, "R/W", 0, 1, 4ull, 0},
- {"CK_CTL" , 4, 4, 138, "R/W", 0, 1, 4ull, 0},
- {"CMD_CTL" , 8, 4, 138, "R/W", 0, 1, 4ull, 0},
- {"RODT_CTL" , 12, 4, 138, "R/W", 0, 1, 0ull, 0},
- {"NTUNE" , 16, 4, 138, "R/W", 0, 1, 0ull, 0},
- {"PTUNE" , 20, 4, 138, "R/W", 0, 1, 0ull, 0},
- {"BYP" , 24, 1, 138, "R/W", 0, 1, 0ull, 0},
- {"M180" , 25, 1, 138, "R/W", 0, 1, 0ull, 0},
- {"DDR__NTUNE" , 26, 4, 138, "RO", 1, 1, 0, 0},
- {"DDR__PTUNE" , 30, 4, 138, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 138, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 139, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 139, "R/W", 0, 0, 0ull, 0ull},
- {"ROW_LSB" , 2, 3, 139, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 139, "R/W", 0, 1, 5ull, 0},
- {"IDLEPOWER" , 9, 3, 139, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 12, 4, 139, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 16, 1, 139, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 139, "R/W", 0, 1, 0ull, 0},
- {"REF_ZQCS_INT" , 18, 19, 139, "R/W", 1, 1, 0, 0},
- {"SEQUENCE" , 37, 3, 139, "R/W", 0, 0, 0ull, 0ull},
- {"EARLY_DQX" , 40, 1, 139, "R/W", 0, 0, 0ull, 0ull},
- {"SREF_WITH_DLL" , 41, 1, 139, "R/W", 0, 0, 0ull, 0ull},
- {"RANK_ENA" , 42, 1, 139, "R/W", 0, 1, 0ull, 0},
- {"RANKMASK" , 43, 4, 139, "R/W", 0, 1, 0ull, 0},
- {"MIRRMASK" , 47, 4, 139, "R/W", 0, 1, 0ull, 0},
- {"INIT_STATUS" , 51, 4, 139, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_55_63" , 55, 9, 139, "RAZ", 1, 1, 0, 0},
- {"RDIMM_ENA" , 0, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"BWCNT" , 1, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 2, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 3, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH2" , 4, 2, 140, "R/W", 0, 0, 0ull, 1ull},
- {"THROTTLE_RD" , 6, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"THROTTLE_WR" , 7, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_RD" , 8, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_WR" , 9, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"ELEV_PRIO_DIS" , 10, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"NXM_WRITE_EN" , 11, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 12, 4, 140, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 16, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"AUTO_FCLKDIS" , 17, 1, 140, "R/W", 0, 0, 0ull, 1ull},
- {"INT_ZQCS_DIS" , 18, 1, 140, "R/W", 0, 0, 1ull, 0ull},
- {"EXT_ZQCS_DIS" , 19, 1, 140, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 20, 2, 140, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 140, "RAZ", 1, 1, 0, 0},
- {"BYP_SETTING" , 0, 8, 141, "R/W", 0, 0, 0ull, 0ull},
- {"BYP_SEL" , 8, 4, 141, "R/W", 0, 0, 0ull, 0ull},
- {"QUAD_DLL_ENA" , 12, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 13, 1, 141, "R/W", 0, 0, 1ull, 0ull},
- {"DLL_BRINGUP" , 14, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 141, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 142, "R/W", 0, 0, 0ull, 0ull},
- {"BYTE_SEL" , 6, 4, 142, "R/W", 0, 0, 0ull, 0ull},
- {"MODE_SEL" , 10, 2, 142, "R/W", 0, 0, 0ull, 0ull},
- {"LOAD_OFFSET" , 12, 1, 142, "WR0", 0, 0, 0ull, 0ull},
- {"OFFSET_ENA" , 13, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYTE_SEL" , 14, 4, 142, "R/W", 0, 0, 1ull, 1ull},
- {"DLL_MODE" , 18, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"FINE_TUNE_MODE" , 19, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_SETTING" , 20, 8, 142, "RO", 1, 1, 0, 0},
- {"DLL_FAST" , 28, 1, 142, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 142, "RAZ", 1, 1, 0, 0},
- {"FCLKCNT" , 0, 64, 143, "RO", 0, 1, 0ull, 0},
- {"MWB" , 0, 1, 144, "RO", 0, 0, 0ull, 0ull},
- {"RPB" , 1, 1, 144, "RO", 0, 0, 0ull, 0ull},
- {"MFF" , 2, 1, 144, "RO", 0, 0, 0ull, 0ull},
- {"MRQ" , 3, 1, 144, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 144, "RAZ", 1, 1, 0, 0},
- {"DFR_ENA" , 0, 1, 145, "R/W", 0, 0, 0ull, 1ull},
- {"RECC_ENA" , 1, 1, 145, "R/W", 0, 0, 0ull, 1ull},
- {"WECC_ENA" , 2, 1, 145, "R/W", 0, 0, 0ull, 1ull},
- {"SBE_ENA" , 3, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 145, "RAZ", 1, 1, 0, 0},
- {"SBE_INTENA" , 0, 1, 146, "R/W", 0, 0, 0ull, 1ull},
- {"DBE_INTENA" , 1, 1, 146, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 146, "RAZ", 1, 1, 0, 0},
- {"SCLKDIS" , 0, 1, 147, "R/W", 0, 0, 1ull, 0ull},
- {"BIST_START" , 1, 1, 147, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 2, 1, 147, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 147, "RAZ", 1, 1, 0, 0},
- {"SBE_ERR" , 0, 1, 148, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE_ERR" , 1, 1, 148, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 148, "RAZ", 1, 1, 0, 0},
- {"FADR" , 4, 28, 148, "RO", 0, 0, 0ull, 0ull},
- {"FSYN" , 32, 10, 148, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 148, "RAZ", 1, 1, 0, 0},
- {"IFBCNT" , 0, 64, 149, "RO", 0, 1, 1ull, 0},
- {"CWL" , 0, 3, 150, "R/W", 0, 0, 0ull, 0ull},
- {"MPRLOC" , 3, 2, 150, "R/W", 0, 0, 0ull, 0ull},
- {"MPR" , 5, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"DLL" , 6, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"AL" , 7, 2, 150, "R/W", 0, 0, 0ull, 0ull},
- {"WLEV" , 9, 1, 150, "RO", 0, 0, 0ull, 0ull},
- {"TDQS" , 10, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"QOFF" , 11, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"BL" , 12, 2, 150, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 14, 4, 150, "R/W", 0, 0, 2ull, 2ull},
- {"RBT" , 18, 1, 150, "RO", 0, 0, 1ull, 1ull},
- {"TM" , 19, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"DLLR" , 20, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"WRP" , 21, 3, 150, "R/W", 0, 0, 0ull, 0ull},
- {"PPD" , 24, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 150, "RAZ", 1, 1, 0, 0},
- {"PASR_00" , 0, 3, 151, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_00" , 3, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_00" , 4, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_00" , 5, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_00" , 7, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_00" , 9, 3, 151, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_01" , 12, 3, 151, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_01" , 15, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_01" , 16, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_01" , 17, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_01" , 19, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_01" , 21, 3, 151, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_10" , 24, 3, 151, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_10" , 27, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_10" , 28, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_10" , 29, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_10" , 31, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_10" , 33, 3, 151, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_11" , 36, 3, 151, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_11" , 39, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_11" , 40, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_11" , 41, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_11" , 43, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_11" , 45, 3, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 151, "RAZ", 1, 1, 0, 0},
- {"OPSCNT" , 0, 64, 152, "RO", 0, 1, 1ull, 0},
- {"TS_STAGGER" , 0, 1, 153, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK_POS" , 1, 1, 153, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK" , 2, 1, 153, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT0" , 3, 4, 153, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE0" , 7, 1, 153, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT1" , 8, 4, 153, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE1" , 12, 1, 153, "R/W", 0, 1, 0ull, 0},
- {"LV_MODE" , 13, 1, 153, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 153, "RAZ", 1, 1, 0, 0},
- {"DDR3RST" , 0, 1, 154, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PWARM" , 1, 1, 154, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSOFT" , 2, 1, 154, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSV" , 3, 1, 154, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 154, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 155, "R/W", 0, 1, 0ull, 0},
- {"OFFSET" , 4, 4, 155, "R/W", 0, 0, 2ull, 2ull},
- {"OFFSET_EN" , 8, 1, 155, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 155, "RAZ", 1, 1, 0, 0},
- {"BITMASK" , 0, 64, 156, "RO", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 6, 157, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 6, 6, 157, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_53" , 12, 42, 157, "R/W", 1, 1, 0, 0},
- {"STATUS" , 54, 2, 157, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 157, "RAZ", 1, 1, 0, 0},
- {"RODT_D0_R0" , 0, 8, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D0_R1" , 8, 8, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D1_R0" , 16, 8, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D1_R1" , 24, 8, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R0" , 32, 8, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R1" , 40, 8, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R0" , 48, 8, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R1" , 56, 8, 158, "R/W", 0, 0, 0ull, 0ull},
- {"R2R_INIT" , 0, 6, 159, "R/W", 0, 1, 1ull, 0},
- {"R2W_INIT" , 6, 6, 159, "R/W", 0, 1, 6ull, 0},
- {"W2R_INIT" , 12, 6, 159, "R/W", 0, 1, 9ull, 0},
- {"W2W_INIT" , 18, 6, 159, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_24_63" , 24, 40, 159, "RAZ", 1, 1, 0, 0},
- {"R2R_XRANK_INIT" , 0, 6, 160, "R/W", 0, 1, 3ull, 0},
- {"R2W_XRANK_INIT" , 6, 6, 160, "R/W", 0, 1, 6ull, 0},
- {"W2R_XRANK_INIT" , 12, 6, 160, "R/W", 0, 1, 4ull, 0},
- {"W2W_XRANK_INIT" , 18, 6, 160, "R/W", 0, 1, 5ull, 0},
- {"RESERVED_24_63" , 24, 40, 160, "RAZ", 1, 1, 0, 0},
- {"TCKEON" , 0, 10, 161, "R/W", 0, 0, 329ull, 0ull},
- {"TZQCS" , 10, 4, 161, "R/W", 0, 0, 4ull, 4ull},
- {"TCKE" , 14, 4, 161, "R/W", 0, 0, 3ull, 3ull},
- {"TXPR" , 18, 4, 161, "R/W", 0, 0, 5ull, 5ull},
- {"TMRD" , 22, 4, 161, "R/W", 0, 0, 4ull, 4ull},
- {"TMOD" , 26, 4, 161, "R/W", 0, 0, 12ull, 12ull},
- {"TDLLK" , 30, 4, 161, "R/W", 0, 0, 2ull, 2ull},
- {"TZQINIT" , 34, 4, 161, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 38, 4, 161, "R/W", 0, 0, 6ull, 6ull},
- {"TCKSRE" , 42, 4, 161, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_46_63" , 46, 18, 161, "RAZ", 1, 1, 0, 0},
- {"TMPRR" , 0, 4, 162, "R/W", 0, 0, 1ull, 1ull},
- {"TRAS" , 4, 5, 162, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 9, 4, 162, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 13, 4, 162, "R/W", 0, 0, 2ull, 2ull},
- {"TRFC" , 17, 5, 162, "R/W", 0, 0, 6ull, 7ull},
- {"TRRD" , 22, 3, 162, "R/W", 0, 0, 2ull, 2ull},
- {"TXP" , 25, 3, 162, "R/W", 0, 0, 3ull, 3ull},
- {"TWLMRD" , 28, 4, 162, "R/W", 0, 0, 10ull, 10ull},
- {"TWLDQSEN" , 32, 4, 162, "R/W", 0, 0, 7ull, 7ull},
- {"TFAW" , 36, 5, 162, "R/W", 0, 0, 0ull, 9ull},
- {"TXPDLL" , 41, 5, 162, "R/W", 0, 0, 0ull, 10ull},
- {"RESERVED_46_63" , 46, 18, 162, "RAZ", 1, 1, 0, 0},
- {"LANEMASK" , 0, 9, 163, "R/W", 0, 1, 0ull, 0},
- {"SSET" , 9, 1, 163, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 163, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 164, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 4, 8, 164, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 164, "RAZ", 1, 1, 0, 0},
- {"BYTE0" , 0, 5, 165, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 5, 5, 165, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_44" , 10, 35, 165, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 45, 2, 165, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_63" , 47, 17, 165, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 166, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D0_R1" , 8, 8, 166, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R0" , 16, 8, 166, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R1" , 24, 8, 166, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R0" , 32, 8, 166, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R1" , 40, 8, 166, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R0" , 48, 8, 166, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R1" , 56, 8, 166, "R/W", 0, 0, 255ull, 255ull},
- {"BIST" , 0, 37, 167, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 167, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 168, "R/W", 0, 0, 0ull, 1ull},
- {"CLK" , 1, 1, 168, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 168, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 169, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 169, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 169, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 170, "WO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 170, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 171, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 29, 171, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 171, "RAZ", 1, 1, 0, 0},
- {"IDLE" , 40, 1, 171, "RO", 0, 1, 1ull, 0},
- {"RESERVED_41_47" , 41, 7, 171, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 48, 14, 171, "R/W", 0, 1, 64ull, 0},
- {"RESERVED_62_63" , 62, 2, 171, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 172, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 172, "RAZ", 1, 1, 0, 0},
- {"STATE" , 0, 64, 173, "RO", 0, 1, 0ull, 0},
- {"STATE" , 0, 64, 174, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_13" , 0, 14, 175, "RAZ", 1, 1, 0, 0},
- {"O_MODE" , 14, 1, 175, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 175, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 175, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 175, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 175, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 175, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 175, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 175, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_47" , 34, 14, 175, "RAZ", 1, 1, 0, 0},
- {"DMA_ENB" , 48, 6, 175, "R/W", 0, 0, 0ull, 63ull},
- {"RESERVED_54_55" , 54, 2, 175, "RAZ", 1, 1, 0, 0},
- {"PKT_EN" , 56, 1, 175, "R/W", 0, 1, 0ull, 0},
- {"PKT_HP" , 57, 1, 175, "R/W", 0, 1, 0ull, 0},
- {"COMMIT_MODE" , 58, 1, 175, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_59_63" , 59, 5, 175, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 176, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 176, "RAZ", 1, 1, 0, 0},
- {"BLKS" , 0, 4, 177, "R/W", 0, 1, 2ull, 0},
- {"BASE" , 4, 4, 177, "RO", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 177, "RAZ", 1, 1, 0, 0},
- {"RSL" , 0, 1, 178, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB" , 1, 1, 178, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 178, "RAZ", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 179, "R/W", 0, 0, 0ull, 0ull},
- {"DMADBO" , 8, 8, 179, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 179, "R/W", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 179, "R/W", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 180, "RAZ", 1, 1, 0, 0},
- {"DMADBO" , 8, 8, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 180, "RAZ", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 180, "RAZ", 1, 1, 0, 0},
- {"SINFO" , 0, 6, 181, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 181, "RAZ", 1, 1, 0, 0},
- {"IINFO" , 8, 6, 181, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 181, "RAZ", 1, 1, 0, 0},
- {"PKTERR" , 0, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 182, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 183, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 183, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 184, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 184, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 185, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 185, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 186, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 186, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 187, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 187, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 2, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 188, "RAZ", 1, 1, 0, 0},
- {"MRRS_LIM" , 3, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"MPS" , 4, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 188, "RAZ", 1, 1, 0, 0},
- {"MPS_LIM" , 7, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"MOLR" , 8, 6, 188, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_14_15" , 14, 2, 188, "RAZ", 1, 1, 0, 0},
- {"RD_MODE" , 16, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 188, "RAZ", 1, 1, 0, 0},
- {"QLM_CFG" , 20, 1, 188, "RO", 1, 1, 0, 0},
- {"RESERVED_21_23" , 21, 3, 188, "RAZ", 1, 1, 0, 0},
- {"HALT" , 24, 1, 188, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 188, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 189, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 189, "RO", 0, 1, 0ull, 0},
- {"REQQ" , 0, 3, 190, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 190, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 4, 1, 190, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 190, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 8, 1, 190, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 190, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 191, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 192, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 192, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 192, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 193, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 193, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 193, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 194, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 194, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 195, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 195, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 195, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 196, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 196, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 197, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 197, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 198, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 199, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 199, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 200, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 200, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 201, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 201, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 201, "RO", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 202, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 202, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 202, "RO", 0, 0, 0ull, 7ull},
- {"RESERVED_0_1" , 0, 2, 203, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 203, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 203, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 203, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 203, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 203, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 203, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 204, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 205, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 205, "RAZ", 1, 1, 0, 0},
- {"LOGL_EN" , 0, 16, 206, "R/W", 0, 1, 65535ull, 0},
- {"PHYS_EN" , 16, 1, 206, "R/W", 0, 1, 1ull, 0},
- {"HG2RX_EN" , 17, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"HG2TX_EN" , 18, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 206, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 207, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 207, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 207, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 1, 207, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 207, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 4, 207, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 207, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 208, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 208, "RAZ", 1, 1, 0, 0},
- {"RX_EN" , 0, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EN" , 1, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"DRP_EN" , 2, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"BCK_EN" , 3, 1, 209, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 209, "RAZ", 1, 1, 0, 0},
- {"PHYS_BP" , 16, 16, 209, "R/W", 0, 1, 65535ull, 0},
- {"LOGL_EN" , 32, 16, 209, "R/W", 0, 0, 255ull, 255ull},
- {"PHYS_EN" , 48, 16, 209, "R/W", 0, 0, 255ull, 255ull},
- {"EN" , 0, 1, 210, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 210, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 210, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 210, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 210, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 210, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 210, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 210, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 210, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 210, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 211, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 212, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 213, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 214, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 215, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 216, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 217, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 217, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 218, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 218, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 218, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 218, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 219, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 219, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 220, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 220, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 220, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 220, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 220, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 220, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 220, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 220, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 220, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 221, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 221, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 221, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 221, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 221, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 221, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 221, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 221, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 221, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 222, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 222, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 223, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 223, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 223, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 223, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 223, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 224, "R/W1C", 0, 1, 0ull, 0},
- {"CAREXT" , 1, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 224, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 224, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 224, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 224, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 224, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 224, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 225, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 225, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 226, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 226, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 227, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 228, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 228, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 229, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 229, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 230, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 230, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 231, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 231, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 232, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 232, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 233, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 233, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 234, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 234, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 235, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 235, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 236, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 236, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 237, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 237, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 237, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 238, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 238, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 239, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 239, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 240, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 240, "RAZ", 1, 1, 0, 0},
- {"LGTIM2GO" , 0, 16, 241, "RO", 0, 1, 0ull, 0},
- {"XOF" , 16, 16, 241, "RO", 0, 0, 0ull, 0ull},
- {"PHTIM2GO" , 32, 16, 241, "RO", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 241, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 4, 242, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 242, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 4, 242, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 242, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 243, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 243, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 244, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 244, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 244, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 244, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 244, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 245, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 245, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 246, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 246, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 0, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"START_BIST" , 1, 1, 247, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 247, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 248, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 248, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 249, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 249, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 249, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 249, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 249, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 250, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 250, "RAZ", 1, 1, 0, 0},
- {"XOFF" , 0, 16, 251, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 251, "RAZ", 1, 1, 0, 0},
- {"XON" , 0, 16, 252, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 252, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 253, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 253, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 253, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 254, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 254, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 255, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 255, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 256, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 256, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 257, "RO", 1, 1, 0, 0},
- {"MSG_TIME" , 16, 16, 257, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 257, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 258, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 258, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 259, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 259, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 260, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 260, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 261, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 261, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 262, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 262, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 263, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 263, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 264, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 264, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 265, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 265, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 266, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 266, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 267, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 267, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 268, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 268, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 269, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 269, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 270, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 270, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 271, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 271, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 272, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 272, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 273, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 273, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 274, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 274, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 275, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 275, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 276, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 276, "RAZ", 1, 1, 0, 0},
- {"TX_XOF" , 0, 16, 277, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 277, "RAZ", 1, 1, 0, 0},
- {"TX_XON" , 0, 16, 278, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 278, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 279, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 279, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 279, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 280, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 280, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 280, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 280, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 280, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 280, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 280, "R/W", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 280, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 280, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 281, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 281, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 281, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 281, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 281, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 281, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 281, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 281, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 281, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 282, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 282, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 283, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 283, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 284, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 284, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 284, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 284, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 284, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 284, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 285, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 285, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 286, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 286, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 287, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_5_63" , 5, 59, 287, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 288, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 288, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 288, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 288, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 288, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 288, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 288, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 288, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 288, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 289, "R/W", 0, 0, 6ull, 6ull},
- {"EN" , 4, 1, 289, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 289, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 290, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 290, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 290, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCE_SEL" , 15, 2, 290, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 290, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 291, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 291, "RAZ", 1, 1, 0, 0},
- {"LANE_SEL" , 0, 2, 292, "R/W", 0, 0, 0ull, 0ull},
- {"DIV" , 2, 1, 292, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 292, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 293, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 293, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 294, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 294, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 295, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 295, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 296, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 296, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"IOCFIF" , 18, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"RSDFIF" , 19, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"IORFIF" , 20, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"XMCFIF" , 21, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"XMDFIF" , 22, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 297, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 298, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 298, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 298, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 298, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 298, "R/W1C", 0, 0, 0ull, 0ull},
- {"RR_MODE" , 5, 1, 298, "R/W", 0, 0, 0ull, 0ull},
- {"XMC_PER" , 6, 4, 298, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 298, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 299, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 299, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 299, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 300, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 300, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 300, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 301, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 301, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 301, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 302, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 302, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 302, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 302, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 302, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 303, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 303, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 303, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 303, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 303, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 304, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 305, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 306, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 306, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 306, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 306, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 306, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 306, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 306, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 307, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 308, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 308, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 308, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 309, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 309, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 310, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 310, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 310, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 311, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 311, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 311, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 311, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 311, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 312, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 312, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 312, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 312, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 312, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 313, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 314, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 315, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 315, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 315, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 316, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 316, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 316, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 317, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 317, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 318, "RO", 0, 1, 0ull, 0},
- {"VPORT" , 6, 6, 318, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 318, "RAZ", 1, 1, 0, 0},
- {"NCB_WR" , 0, 3, 319, "R/W", 0, 1, 0ull, 0},
- {"NCB_RD" , 3, 3, 319, "R/W", 0, 1, 0ull, 0},
- {"PKO_RD" , 6, 3, 319, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 319, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 320, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 320, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 321, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 321, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 322, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 322, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 323, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 323, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 44, 324, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_63" , 44, 20, 324, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 325, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 326, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 326, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"CLKEN" , 15, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 326, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 327, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 328, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 329, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 329, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 330, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 330, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 331, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 331, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 332, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 332, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 333, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 333, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 334, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 334, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 334, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 335, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 335, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 336, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 336, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 337, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 337, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 338, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 338, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 339, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 340, "R/W", 0, 0, 0ull, 1ull},
- {"RADDR" , 0, 3, 341, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 341, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 341, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 341, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 341, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 341, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 342, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 342, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 342, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 342, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_44_63" , 44, 20, 342, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 343, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 343, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 343, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 343, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 344, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 344, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 344, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 344, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 344, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 344, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_61_63" , 61, 3, 344, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 345, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 345, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 346, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 346, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 347, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 347, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 347, "R/W", 0, 0, 0ull, 0ull},
- {"PRT_ENB" , 0, 8, 348, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 348, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 349, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 349, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 349, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 349, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 349, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 350, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 350, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 350, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 351, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_35" , 32, 4, 351, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT2" , 36, 4, 351, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_40_63" , 40, 24, 351, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 352, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 352, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 352, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 353, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 353, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 354, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 354, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 355, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 355, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 355, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 355, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 356, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 356, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 356, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 357, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 357, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 357, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 357, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 357, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 358, "RAZ", 1, 1, 0, 0},
- {"TDFFL" , 0, 1, 359, "RO", 1, 0, 0, 0ull},
- {"RESERVED_1_3" , 1, 3, 359, "RAZ", 1, 1, 0, 0},
- {"VRTFL" , 4, 1, 359, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_7" , 5, 3, 359, "RAZ", 1, 1, 0, 0},
- {"DUTRESFL" , 8, 1, 359, "RO", 1, 0, 0, 0ull},
- {"RESERVED_9_11" , 9, 3, 359, "RAZ", 1, 1, 0, 0},
- {"IOCDATFL" , 12, 1, 359, "RO", 1, 0, 0, 0ull},
- {"RESERVED_13_15" , 13, 3, 359, "RAZ", 1, 1, 0, 0},
- {"IOCCMDFL" , 16, 1, 359, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 359, "RAZ", 1, 1, 0, 0},
- {"DUTFL" , 32, 6, 359, "RO", 1, 0, 0, 0ull},
- {"RESERVED_38_63" , 38, 26, 359, "RAZ", 1, 1, 0, 0},
- {"VBFFL" , 0, 4, 360, "RO", 1, 0, 0, 0ull},
- {"RDFFL" , 4, 1, 360, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_61" , 5, 57, 360, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 62, 1, 360, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 63, 1, 360, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFL" , 0, 8, 361, "RO", 1, 0, 0, 0ull},
- {"FBFFL" , 8, 8, 361, "RO", 1, 0, 0, 0ull},
- {"SBFFL" , 16, 8, 361, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 361, "RAZ", 1, 1, 0, 0},
- {"TAGFL" , 0, 16, 362, "RO", 1, 0, 0, 0ull},
- {"LRUFL" , 16, 1, 362, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 362, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 363, "R/W", 1, 1, 0, 0},
- {"DISIDXALIAS" , 0, 1, 364, "R/W", 0, 0, 0ull, 0ull},
- {"DISECC" , 1, 1, 364, "R/W", 0, 0, 0ull, 0ull},
- {"VAB_THRESH" , 2, 4, 364, "R/W", 0, 0, 0ull, 0ull},
- {"EF_CNT" , 6, 7, 364, "R/W", 0, 0, 0ull, 4ull},
- {"EF_ENA" , 13, 1, 364, "R/W", 0, 0, 0ull, 1ull},
- {"XMC_ARB_MODE" , 14, 1, 364, "R/W", 0, 0, 0ull, 0ull},
- {"RSP_ARB_MODE" , 15, 1, 364, "R/W", 0, 0, 0ull, 0ull},
- {"MAXLFB" , 16, 4, 364, "R/W", 0, 0, 0ull, 0ull},
- {"MAXVAB" , 20, 4, 364, "R/W", 0, 0, 0ull, 0ull},
- {"DISCCLK" , 24, 1, 364, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 364, "RAZ", 1, 1, 0, 0},
- {"VALID" , 0, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_9" , 1, 9, 365, "RAZ", 1, 1, 0, 0},
- {"TAG" , 10, 28, 365, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 365, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 366, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 366, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 4, 17, 366, "RO", 1, 0, 0, 0ull},
- {"RESERVED_21_49" , 21, 29, 366, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 10, 366, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 366, "R/W1C", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 366, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 366, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 366, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 367, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_6" , 2, 5, 367, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 7, 14, 367, "RO", 1, 0, 0, 0ull},
- {"RESERVED_21_49" , 21, 29, 367, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 6, 367, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_60" , 56, 5, 367, "RAZ", 1, 1, 0, 0},
- {"NOWAY" , 61, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 368, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_49" , 2, 48, 368, "RAZ", 1, 1, 0, 0},
- {"VSYN" , 50, 10, 368, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 368, "RO", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 368, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 368, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 38, 369, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_47" , 38, 10, 369, "RAZ", 1, 1, 0, 0},
- {"SID" , 48, 4, 369, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_57" , 52, 6, 369, "RAZ", 1, 1, 0, 0},
- {"CMD" , 58, 6, 369, "RO", 0, 1, 0ull, 0},
- {"HOLERD" , 0, 1, 370, "R/W", 0, 0, 0ull, 1ull},
- {"HOLEWR" , 1, 1, 370, "R/W", 0, 0, 0ull, 1ull},
- {"VRTWR" , 2, 1, 370, "R/W", 0, 0, 0ull, 1ull},
- {"VRTIDRNG" , 3, 1, 370, "R/W", 0, 0, 0ull, 1ull},
- {"VRTADRNG" , 4, 1, 370, "R/W", 0, 0, 0ull, 1ull},
- {"VRTPE" , 5, 1, 370, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 370, "RAZ", 1, 1, 0, 0},
- {"HOLERD" , 0, 1, 371, "R/W1C", 0, 0, 0ull, 0ull},
- {"HOLEWR" , 1, 1, 371, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTWR" , 2, 1, 371, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTIDRNG" , 3, 1, 371, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTADRNG" , 4, 1, 371, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTPE" , 5, 1, 371, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_15" , 6, 10, 371, "RAZ", 1, 1, 0, 0},
- {"TAD0" , 16, 1, 371, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 371, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 372, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 373, "R/W", 0, 1, 0ull, 0},
- {"LVL" , 0, 2, 374, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 374, "RAZ", 1, 1, 0, 0},
- {"DWBLVL" , 4, 2, 374, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 374, "RAZ", 1, 1, 0, 0},
- {"LVL" , 0, 2, 375, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 375, "RAZ", 1, 1, 0, 0},
- {"WGT0" , 0, 8, 376, "R/W", 0, 0, 255ull, 255ull},
- {"WGT1" , 8, 8, 376, "R/W", 0, 0, 255ull, 255ull},
- {"WGT2" , 16, 8, 376, "R/W", 0, 0, 255ull, 255ull},
- {"WGT3" , 24, 8, 376, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 376, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 377, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 378, "R/W", 0, 1, 0ull, 0},
- {"OW0ECC" , 0, 10, 379, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 379, "RAZ", 1, 1, 0, 0},
- {"OW1ECC" , 16, 10, 379, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 379, "RAZ", 1, 1, 0, 0},
- {"OW2ECC" , 32, 10, 379, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 379, "RAZ", 1, 1, 0, 0},
- {"OW3ECC" , 48, 10, 379, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 379, "RAZ", 1, 1, 0, 0},
- {"OW4ECC" , 0, 10, 380, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 380, "RAZ", 1, 1, 0, 0},
- {"OW5ECC" , 16, 10, 380, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 380, "RAZ", 1, 1, 0, 0},
- {"OW6ECC" , 32, 10, 380, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 380, "RAZ", 1, 1, 0, 0},
- {"OW7ECC" , 48, 10, 380, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 380, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 381, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 381, "R/W", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 381, "R/W", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 381, "R/W", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 381, "R/W", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 381, "R/W", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 381, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 381, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 382, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 383, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 384, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 385, "R/W", 0, 1, 0ull, 0},
- {"CNT0SEL" , 0, 8, 386, "R/W", 0, 0, 0ull, 1ull},
- {"CNT1SEL" , 8, 8, 386, "R/W", 0, 0, 0ull, 1ull},
- {"CNT2SEL" , 16, 8, 386, "R/W", 0, 0, 0ull, 1ull},
- {"CNT3SEL" , 24, 8, 386, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 386, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 0, 1, 387, "R/W", 0, 0, 0ull, 0ull},
- {"DIRTY" , 1, 1, 387, "R/W", 0, 0, 0ull, 0ull},
- {"VALID" , 2, 1, 387, "R/W", 0, 0, 0ull, 0ull},
- {"USE" , 3, 1, 387, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_16" , 4, 13, 387, "RAZ", 1, 1, 0, 0},
- {"TAG" , 17, 19, 387, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_39" , 36, 4, 387, "RAZ", 1, 1, 0, 0},
- {"ECC" , 40, 6, 387, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_63" , 46, 18, 387, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 388, "R/W1C", 0, 0, 0ull, 0ull},
- {"MASK" , 0, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 389, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 6, 390, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 390, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 391, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 391, "RAZ", 1, 1, 0, 0},
- {"DWBID" , 8, 6, 391, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 391, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 392, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 392, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 393, "R/W", 0, 0, 0ull, 1ull},
- {"NUMID" , 1, 3, 393, "R/W", 0, 0, 5ull, 5ull},
- {"MEMSZ" , 4, 3, 393, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_7_7" , 7, 1, 393, "RAZ", 1, 1, 0, 0},
- {"OOBERR" , 8, 1, 393, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 393, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 32, 394, "R/W", 0, 0, 0ull, 0ull},
- {"PARITY" , 32, 4, 394, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 394, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 395, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 395, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 396, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 396, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 397, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 38, 398, "R/W", 1, 1, 0, 0},
- {"RESERVED_38_56" , 38, 19, 398, "RAZ", 1, 1, 0, 0},
- {"CMD" , 57, 6, 398, "R/W", 1, 1, 0, 0},
- {"INUSE" , 63, 1, 398, "RO", 0, 0, 0ull, 0ull},
- {"COUNT" , 0, 64, 399, "R/W", 0, 1, 0ull, 0},
- {"PRBS" , 0, 32, 400, "R/W", 1, 1, 0, 0},
- {"PROG" , 32, 8, 400, "R/W", 1, 1, 0, 0},
- {"SEL" , 40, 1, 400, "R/W", 1, 1, 0, 0},
- {"EN" , 41, 1, 400, "R/W", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 400, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 401, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 402, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 402, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 403, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 404, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 404, "R/W", 1, 1, 0, 0},
- {"CKE_MASK" , 0, 2, 405, "R/W", 1, 1, 0, 0},
- {"CS0_N_MASK" , 2, 2, 405, "R/W", 1, 1, 0, 0},
- {"CS1_N_MASK" , 4, 2, 405, "R/W", 1, 1, 0, 0},
- {"ODT0_MASK" , 6, 2, 405, "R/W", 1, 1, 0, 0},
- {"ODT1_MASK" , 8, 2, 405, "R/W", 1, 1, 0, 0},
- {"RAS_N_MASK" , 10, 1, 405, "R/W", 1, 1, 0, 0},
- {"CAS_N_MASK" , 11, 1, 405, "R/W", 1, 1, 0, 0},
- {"WE_N_MASK" , 12, 1, 405, "R/W", 1, 1, 0, 0},
- {"BA_MASK" , 13, 3, 405, "R/W", 1, 1, 0, 0},
- {"A_MASK" , 16, 16, 405, "R/W", 1, 1, 0, 0},
- {"RESET_N_MASK" , 32, 1, 405, "R/W", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 405, "R/W", 1, 1, 0, 0},
- {"DQX_CTL" , 0, 4, 406, "R/W", 0, 1, 4ull, 0},
- {"CK_CTL" , 4, 4, 406, "R/W", 0, 1, 4ull, 0},
- {"CMD_CTL" , 8, 4, 406, "R/W", 0, 1, 4ull, 0},
- {"RODT_CTL" , 12, 4, 406, "R/W", 0, 1, 0ull, 0},
- {"NTUNE" , 16, 4, 406, "R/W", 0, 1, 0ull, 0},
- {"PTUNE" , 20, 4, 406, "R/W", 0, 1, 0ull, 0},
- {"BYP" , 24, 1, 406, "R/W", 0, 1, 0ull, 0},
- {"M180" , 25, 1, 406, "R/W", 0, 1, 0ull, 0},
- {"DDR__NTUNE" , 26, 4, 406, "RO", 1, 1, 0, 0},
- {"DDR__PTUNE" , 30, 4, 406, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 406, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 407, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 407, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 407, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 407, "R/W", 0, 1, 5ull, 0},
- {"IDLEPOWER" , 9, 3, 407, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 12, 4, 407, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 16, 1, 407, "R/W", 0, 0, 0ull, 1ull},
- {"RESET" , 17, 1, 407, "R/W", 0, 1, 0ull, 0},
- {"REF_ZQCS_INT" , 18, 19, 407, "R/W", 1, 1, 0, 0},
- {"SEQUENCE" , 37, 3, 407, "R/W", 0, 0, 0ull, 0ull},
- {"EARLY_DQX" , 40, 1, 407, "R/W", 0, 0, 0ull, 0ull},
- {"SREF_WITH_DLL" , 41, 1, 407, "R/W", 0, 0, 0ull, 0ull},
- {"RANK_ENA" , 42, 1, 407, "R/W", 0, 1, 0ull, 0},
- {"RANKMASK" , 43, 4, 407, "R/W", 0, 1, 0ull, 0},
- {"MIRRMASK" , 47, 4, 407, "R/W", 0, 1, 0ull, 0},
- {"INIT_STATUS" , 51, 4, 407, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_55_63" , 55, 9, 407, "RAZ", 1, 1, 0, 0},
- {"RDIMM_ENA" , 0, 1, 408, "R/W", 0, 1, 0ull, 0},
- {"BWCNT" , 1, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 2, 1, 408, "R/W", 0, 0, 0ull, 1ull},
- {"POCAS" , 3, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH2" , 4, 2, 408, "R/W", 0, 0, 0ull, 1ull},
- {"THROTTLE_RD" , 6, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"THROTTLE_WR" , 7, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_RD" , 8, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_WR" , 9, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"ELEV_PRIO_DIS" , 10, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"NXM_WRITE_EN" , 11, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 12, 4, 408, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 16, 1, 408, "R/W", 0, 0, 0ull, 1ull},
- {"AUTO_DCLKDIS" , 17, 1, 408, "R/W", 0, 0, 0ull, 1ull},
- {"INT_ZQCS_DIS" , 18, 1, 408, "R/W", 0, 0, 1ull, 0ull},
- {"EXT_ZQCS_DIS" , 19, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 20, 2, 408, "R/W", 0, 0, 0ull, 0ull},
- {"WODT_BPRCH" , 22, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_BPRCH" , 23, 1, 408, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 408, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT" , 0, 64, 409, "RO", 0, 1, 0ull, 0},
- {"CLKF" , 0, 7, 410, "R/W", 0, 1, 48ull, 0},
- {"RESET_N" , 7, 1, 410, "R/W", 0, 0, 0ull, 1ull},
- {"CPB" , 8, 3, 410, "R/W", 0, 0, 0ull, 1ull},
- {"CPS" , 11, 3, 410, "R/W", 0, 0, 0ull, 1ull},
- {"DIFFAMP" , 14, 4, 410, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_PS_EN" , 18, 3, 410, "R/W", 0, 1, 2ull, 0},
- {"DDR_DIV_RESET" , 21, 1, 410, "R/W", 0, 0, 1ull, 0ull},
- {"DFM_PS_EN" , 22, 3, 410, "R/W", 0, 1, 2ull, 0},
- {"DFM_DIV_RESET" , 25, 1, 410, "R/W", 0, 0, 1ull, 0ull},
- {"JTG_TEST_MODE" , 26, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 410, "RAZ", 1, 1, 0, 0},
- {"RC0" , 0, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC1" , 4, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC2" , 8, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC3" , 12, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC4" , 16, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC5" , 20, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC6" , 24, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC7" , 28, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC8" , 32, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC9" , 36, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC10" , 40, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC11" , 44, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC12" , 48, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC13" , 52, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC14" , 56, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"RC15" , 60, 4, 411, "R/W", 0, 0, 0ull, 0ull},
- {"DIMM0_WMASK" , 0, 16, 412, "R/W", 0, 0, 65535ull, 65535ull},
- {"DIMM1_WMASK" , 16, 16, 412, "R/W", 0, 0, 65535ull, 65535ull},
- {"TCWS" , 32, 13, 412, "R/W", 0, 0, 1248ull, 1248ull},
- {"PARITY" , 45, 1, 412, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 412, "RAZ", 1, 1, 0, 0},
- {"BYP_SETTING" , 0, 8, 413, "R/W", 0, 0, 0ull, 0ull},
- {"BYP_SEL" , 8, 4, 413, "R/W", 0, 0, 0ull, 0ull},
- {"QUAD_DLL_ENA" , 12, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 13, 1, 413, "R/W", 0, 0, 1ull, 0ull},
- {"DLL_BRINGUP" , 14, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 413, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 414, "R/W", 0, 0, 0ull, 0ull},
- {"BYTE_SEL" , 6, 4, 414, "R/W", 0, 0, 0ull, 0ull},
- {"MODE_SEL" , 10, 2, 414, "R/W", 0, 0, 0ull, 0ull},
- {"LOAD_OFFSET" , 12, 1, 414, "WR0", 0, 0, 0ull, 0ull},
- {"OFFSET_ENA" , 13, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYTE_SEL" , 14, 4, 414, "R/W", 0, 0, 1ull, 1ull},
- {"DLL_MODE" , 18, 1, 414, "R/W", 0, 0, 0ull, 0ull},
- {"FINE_TUNE_MODE" , 19, 1, 414, "R/W", 0, 0, 0ull, 1ull},
- {"DLL90_SETTING" , 20, 8, 414, "RO", 1, 1, 0, 0},
- {"DLL_FAST" , 28, 1, 414, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 414, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 415, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 415, "RAZ", 1, 1, 0, 0},
- {"ROW_LSB" , 16, 3, 415, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_19_63" , 19, 45, 415, "RAZ", 1, 1, 0, 0},
- {"MRDSYN0" , 0, 8, 416, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 416, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 416, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 416, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 416, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 14, 417, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 14, 16, 417, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 30, 3, 417, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 33, 1, 417, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 34, 2, 417, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 417, "RAZ", 1, 1, 0, 0},
- {"IFBCNT" , 0, 64, 418, "RO", 0, 1, 1ull, 0},
- {"NXM_WR_ERR" , 0, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
- {"SEC_ERR" , 1, 4, 419, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 5, 4, 419, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 419, "RAZ", 1, 1, 0, 0},
- {"INTR_NXM_WR_ENA" , 0, 1, 420, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_SEC_ENA" , 1, 1, 420, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 2, 1, 420, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 420, "RAZ", 1, 1, 0, 0},
- {"CWL" , 0, 3, 421, "R/W", 0, 0, 0ull, 0ull},
- {"MPRLOC" , 3, 2, 421, "R/W", 0, 0, 0ull, 0ull},
- {"MPR" , 5, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"DLL" , 6, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"AL" , 7, 2, 421, "R/W", 0, 0, 0ull, 0ull},
- {"WLEV" , 9, 1, 421, "RO", 0, 0, 0ull, 0ull},
- {"TDQS" , 10, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"QOFF" , 11, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"BL" , 12, 2, 421, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 14, 4, 421, "R/W", 0, 0, 2ull, 2ull},
- {"RBT" , 18, 1, 421, "RO", 0, 0, 1ull, 1ull},
- {"TM" , 19, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"DLLR" , 20, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"WRP" , 21, 3, 421, "R/W", 0, 0, 0ull, 0ull},
- {"PPD" , 24, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 421, "RAZ", 1, 1, 0, 0},
- {"PASR_00" , 0, 3, 422, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_00" , 3, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_00" , 4, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_00" , 5, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_00" , 7, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_00" , 9, 3, 422, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_01" , 12, 3, 422, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_01" , 15, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_01" , 16, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_01" , 17, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_01" , 19, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_01" , 21, 3, 422, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_10" , 24, 3, 422, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_10" , 27, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_10" , 28, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_10" , 29, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_10" , 31, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_10" , 33, 3, 422, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_11" , 36, 3, 422, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_11" , 39, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_11" , 40, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_11" , 41, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_11" , 43, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_11" , 45, 3, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 422, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 423, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R0" , 8, 4, 423, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R1" , 12, 4, 423, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R0" , 16, 4, 423, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R1" , 20, 4, 423, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R0" , 24, 4, 423, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R1" , 28, 4, 423, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R0" , 32, 4, 423, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R1" , 36, 4, 423, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 423, "RAZ", 1, 1, 0, 0},
- {"OPSCNT" , 0, 64, 424, "RO", 0, 1, 1ull, 0},
- {"TS_STAGGER" , 0, 1, 425, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK_POS" , 1, 1, 425, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK" , 2, 1, 425, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT0" , 3, 4, 425, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE0" , 7, 1, 425, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT1" , 8, 4, 425, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE1" , 12, 1, 425, "R/W", 0, 1, 0ull, 0},
- {"LV_MODE" , 13, 1, 425, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 425, "RAZ", 1, 1, 0, 0},
- {"DDR3RST" , 0, 1, 426, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PWARM" , 1, 1, 426, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSOFT" , 2, 1, 426, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSV" , 3, 1, 426, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 426, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 427, "R/W", 0, 1, 0ull, 0},
- {"OFFSET" , 4, 4, 427, "R/W", 0, 0, 2ull, 2ull},
- {"OFFSET_EN" , 8, 1, 427, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 427, "RAZ", 1, 1, 0, 0},
- {"BITMASK" , 0, 64, 428, "RO", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 6, 429, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 6, 6, 429, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 12, 6, 429, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 18, 6, 429, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 24, 6, 429, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 30, 6, 429, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 36, 6, 429, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 42, 6, 429, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 48, 6, 429, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 54, 2, 429, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 429, "RAZ", 1, 1, 0, 0},
- {"RODT_D0_R0" , 0, 8, 430, "R/W", 0, 1, 0ull, 0},
- {"RODT_D0_R1" , 8, 8, 430, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R0" , 16, 8, 430, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R1" , 24, 8, 430, "R/W", 0, 1, 0ull, 0},
- {"RODT_D2_R0" , 32, 8, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R1" , 40, 8, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R0" , 48, 8, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R1" , 56, 8, 430, "R/W", 0, 0, 0ull, 0ull},
- {"R2R_INIT" , 0, 6, 431, "R/W", 0, 1, 1ull, 0},
- {"R2W_INIT" , 6, 6, 431, "R/W", 0, 1, 6ull, 0},
- {"W2R_INIT" , 12, 6, 431, "R/W", 0, 1, 9ull, 0},
- {"W2W_INIT" , 18, 6, 431, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_24_63" , 24, 40, 431, "RAZ", 1, 1, 0, 0},
- {"R2R_XRANK_INIT" , 0, 6, 432, "R/W", 0, 1, 3ull, 0},
- {"R2W_XRANK_INIT" , 6, 6, 432, "R/W", 0, 1, 6ull, 0},
- {"W2R_XRANK_INIT" , 12, 6, 432, "R/W", 0, 1, 4ull, 0},
- {"W2W_XRANK_INIT" , 18, 6, 432, "R/W", 0, 1, 5ull, 0},
- {"RESERVED_24_63" , 24, 40, 432, "RAZ", 1, 1, 0, 0},
- {"R2R_XDIMM_INIT" , 0, 6, 433, "R/W", 0, 1, 4ull, 0},
- {"R2W_XDIMM_INIT" , 6, 6, 433, "R/W", 0, 1, 7ull, 0},
- {"W2R_XDIMM_INIT" , 12, 6, 433, "R/W", 0, 1, 4ull, 0},
- {"W2W_XDIMM_INIT" , 18, 6, 433, "R/W", 0, 1, 6ull, 0},
- {"RESERVED_24_63" , 24, 40, 433, "RAZ", 1, 1, 0, 0},
- {"TCKEON" , 0, 10, 434, "R/W", 0, 0, 329ull, 0ull},
- {"TZQCS" , 10, 4, 434, "R/W", 0, 0, 4ull, 4ull},
- {"TCKE" , 14, 4, 434, "R/W", 0, 0, 3ull, 3ull},
- {"TXPR" , 18, 4, 434, "R/W", 0, 0, 5ull, 5ull},
- {"TMRD" , 22, 4, 434, "R/W", 0, 0, 4ull, 4ull},
- {"TMOD" , 26, 4, 434, "R/W", 0, 0, 12ull, 12ull},
- {"TDLLK" , 30, 4, 434, "R/W", 0, 0, 2ull, 2ull},
- {"TZQINIT" , 34, 4, 434, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 38, 4, 434, "R/W", 0, 0, 6ull, 6ull},
- {"TCKSRE" , 42, 4, 434, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_46_63" , 46, 18, 434, "RAZ", 1, 1, 0, 0},
- {"TMPRR" , 0, 4, 435, "R/W", 0, 0, 1ull, 1ull},
- {"TRAS" , 4, 5, 435, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 9, 4, 435, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 13, 4, 435, "R/W", 0, 0, 2ull, 3ull},
- {"TRFC" , 17, 5, 435, "R/W", 0, 0, 6ull, 7ull},
- {"TRRD" , 22, 3, 435, "R/W", 0, 0, 2ull, 2ull},
- {"TXP" , 25, 3, 435, "R/W", 0, 0, 3ull, 3ull},
- {"TWLMRD" , 28, 4, 435, "R/W", 0, 0, 10ull, 10ull},
- {"TWLDQSEN" , 32, 4, 435, "R/W", 0, 0, 7ull, 7ull},
- {"TFAW" , 36, 5, 435, "R/W", 0, 0, 0ull, 9ull},
- {"TXPDLL" , 41, 5, 435, "R/W", 0, 0, 0ull, 10ull},
- {"RESERVED_46_63" , 46, 18, 435, "RAZ", 1, 1, 0, 0},
- {"TRESET" , 0, 1, 436, "R/W", 0, 1, 1ull, 0},
- {"RCLK_CNT" , 1, 32, 436, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 436, "RAZ", 1, 1, 0, 0},
- {"RING_CNT" , 0, 32, 437, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 437, "RAZ", 1, 1, 0, 0},
- {"LANEMASK" , 0, 9, 438, "R/W", 0, 1, 0ull, 0},
- {"SSET" , 9, 1, 438, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 438, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 439, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 4, 8, 439, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 439, "RAZ", 1, 1, 0, 0},
- {"BYTE0" , 0, 5, 440, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 5, 5, 440, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 10, 5, 440, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 15, 5, 440, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 20, 5, 440, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 25, 5, 440, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 30, 5, 440, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 35, 5, 440, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 40, 5, 440, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 45, 2, 440, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_63" , 47, 17, 440, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 441, "R/W", 0, 1, 255ull, 0},
- {"WODT_D0_R1" , 8, 8, 441, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R0" , 16, 8, 441, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R1" , 24, 8, 441, "R/W", 0, 1, 255ull, 0},
- {"WODT_D2_R0" , 32, 8, 441, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D2_R1" , 40, 8, 441, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R0" , 48, 8, 441, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R1" , 56, 8, 441, "R/W", 0, 0, 255ull, 0ull},
- {"STAT" , 0, 9, 442, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 442, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 443, "R/W", 1, 1, 0, 0},
- {"PCTL" , 6, 6, 443, "R/W", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 443, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 444, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 444, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 444, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 444, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 445, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 445, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 445, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 446, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 446, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 446, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 447, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 447, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 447, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 447, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 447, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 447, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 447, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 447, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 447, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 447, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 447, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 447, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 447, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 447, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 447, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 448, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 448, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 448, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 449, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 449, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 449, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 450, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 450, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 450, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 451, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 451, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 451, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 451, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 451, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 452, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 453, "RAZ", 1, 1, 0, 0},
- {"NAND" , 8, 1, 453, "RO", 1, 1, 0, 0},
- {"TERM" , 9, 2, 453, "RO", 1, 1, 0, 0},
- {"DMACK_P0" , 11, 1, 453, "RO", 1, 1, 0, 0},
- {"DMACK_P1" , 12, 1, 453, "RO", 1, 1, 0, 0},
- {"RESERVED_13_13" , 13, 1, 453, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 14, 1, 453, "RO", 1, 1, 0, 0},
- {"ALE" , 15, 1, 453, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 453, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 16, 454, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 454, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 454, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 454, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 454, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 454, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 454, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 454, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 454, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 454, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 454, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 454, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 454, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 455, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 456, "R/W", 0, 0, 25ull, 25ull},
- {"RESERVED_6_7" , 6, 2, 456, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 456, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 456, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 456, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 456, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 457, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 458, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 458, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 459, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 459, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 6, 460, "RO", 1, 1, 0, 0},
- {"RESERVED_6_15" , 6, 10, 460, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 460, "RO", 1, 1, 0, 0},
- {"RESERVED_24_25" , 24, 2, 460, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 460, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 460, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 460, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 460, "RO", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 460, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 460, "RO", 1, 1, 0, 0},
- {"DORM_CRYPTO" , 34, 1, 460, "RO", 1, 1, 0, 0},
- {"RESERVED_35_63" , 35, 29, 460, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 461, "RAZ", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 461, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 461, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 461, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 461, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 461, "RO", 1, 1, 0, 0},
- {"ZIP_INFO" , 29, 2, 461, "RO", 1, 1, 0, 0},
- {"RESERVED_31_31" , 31, 1, 461, "RAZ", 1, 1, 0, 0},
- {"L2C_CRIP" , 32, 3, 461, "RO", 1, 1, 0, 0},
- {"PLL_HALF_DIS" , 35, 1, 461, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_MAN" , 36, 1, 461, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_RSV" , 37, 1, 461, "RO", 1, 1, 0, 0},
- {"EMA" , 38, 2, 461, "RO", 1, 1, 0, 0},
- {"RESERVED_40_40" , 40, 1, 461, "RAZ", 1, 1, 0, 0},
- {"DFA_INFO_CLM" , 41, 4, 461, "RO", 1, 1, 0, 0},
- {"DFA_INFO_DTE" , 45, 3, 461, "RO", 1, 1, 0, 0},
- {"PLL_CTL" , 48, 10, 461, "RO", 1, 1, 0, 0},
- {"RESERVED_58_63" , 58, 6, 461, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 462, "RAZ", 1, 1, 0, 0},
- {"RESERVED_3_3" , 3, 1, 462, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 462, "RAZ", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 462, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 463, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 464, "RAZ", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 464, "RAZ", 0, 1, 0ull, 0},
- {"PNR_COUT_SEL" , 2, 2, 464, "R/W", 0, 1, 0ull, 0},
- {"PNR_COUT_RST" , 4, 1, 464, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_SEL" , 5, 2, 464, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_RST" , 7, 1, 464, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 464, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 465, "R/W", 1, 1, 0, 0},
- {"SOFT" , 1, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 465, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 6, 466, "R/W", 0, 1, 1ull, 0},
- {"SCLK_HI" , 6, 15, 466, "R/W", 0, 1, 20000ull, 0},
- {"SCLK_LO" , 21, 4, 466, "R/W", 0, 1, 1ull, 0},
- {"OUT" , 25, 7, 466, "R/W", 0, 1, 1ull, 0},
- {"PROG_PIN" , 32, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"FSRC_PIN" , 33, 1, 466, "RO", 0, 0, 0ull, 0ull},
- {"VGATE_PIN" , 34, 1, 466, "RO", 0, 0, 1ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 466, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 467, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 467, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 467, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 467, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 467, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 467, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 467, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 10, 468, "R/W", 0, 1, 999ull, 0},
- {"SDH" , 10, 4, 468, "R/W", 0, 1, 0ull, 0},
- {"PRH" , 14, 4, 468, "R/W", 0, 1, 6ull, 0},
- {"FSH" , 18, 4, 468, "R/W", 0, 1, 15ull, 0},
- {"SCH" , 22, 4, 468, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_26_63" , 26, 38, 468, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 18, 469, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 18, 18, 469, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 36, 18, 469, "RO", 0, 0, 0ull, 0ull},
- {"TOO_MANY" , 54, 1, 469, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 469, "RAZ", 1, 1, 0, 0},
- {"REPAIR3" , 0, 18, 470, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR4" , 18, 18, 470, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR5" , 36, 18, 470, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 470, "RAZ", 1, 1, 0, 0},
- {"REPAIR6" , 0, 18, 471, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 471, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 472, "RAZ", 1, 1, 0, 0},
- {"REPAIR1" , 14, 14, 472, "RAZ", 1, 1, 0, 0},
- {"REPAIR2" , 28, 14, 472, "RAZ", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 472, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 473, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 473, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 4, 474, "R/W", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 474, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 475, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 6, 6, 475, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_12_63" , 12, 52, 475, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 476, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 476, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 476, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 477, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 477, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 478, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 478, "RAZ", 1, 1, 0, 0},
- {"PTP_EN" , 0, 1, 479, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EN" , 1, 1, 479, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_IN" , 2, 6, 479, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EN" , 8, 1, 479, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EDGE" , 9, 1, 479, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_IN" , 10, 6, 479, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EN" , 16, 1, 479, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EDGE" , 17, 1, 479, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_IN" , 18, 6, 479, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 479, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 480, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 480, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 481, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 482, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 482, "RAZ", 1, 1, 0, 0},
- {"CNTR" , 0, 64, 483, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 484, "R/W", 0, 0, 0ull, 0ull},
- {"RBOOT_PIN" , 0, 1, 485, "RO", 1, 1, 0, 0},
- {"RBOOT" , 1, 1, 485, "R/W", 1, 1, 0, 0},
- {"LBOOT" , 2, 10, 485, "R/W1C", 1, 1, 0, 0},
- {"QLM0_SPD" , 12, 4, 485, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 16, 4, 485, "RO", 1, 1, 0, 0},
- {"QLM2_SPD" , 20, 4, 485, "RO", 1, 1, 0, 0},
- {"PNR_MUL" , 24, 6, 485, "RO", 1, 1, 0, 0},
- {"C_MUL" , 30, 6, 485, "RO", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 485, "RAZ", 1, 1, 0, 0},
- {"SOFT_CLR_BIST" , 0, 1, 486, "R/W", 0, 0, 0ull, 0ull},
- {"WARM_CLR_BIST" , 1, 1, 486, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_5" , 2, 4, 486, "RAZ", 1, 1, 0, 0},
- {"BIST_DELAY" , 6, 58, 486, "RO", 1, 1, 0, 0},
- {"RST_VAL" , 0, 1, 487, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 487, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 487, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 487, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 487, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 487, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 487, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 487, "RO", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 487, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST_DLY" , 0, 16, 488, "R/W", 0, 1, 2047ull, 0},
- {"WARM_RST_DLY" , 16, 16, 488, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_32_63" , 32, 32, 488, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 489, "R/W1C", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 489, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 489, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 489, "R/W1C", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 489, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 489, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 490, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 490, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 491, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 491, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 491, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 491, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 491, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 491, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 491, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 491, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 491, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 491, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 491, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 491, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 491, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 492, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 492, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 492, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 492, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 492, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 492, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 492, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 492, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 492, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 492, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 492, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 492, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 493, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 493, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 493, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 494, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 494, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 494, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 495, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 495, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 496, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 496, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 497, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 497, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 498, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 498, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 498, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 498, "RAZ", 1, 1, 0, 0},
- {"TXTRIG" , 4, 2, 498, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 498, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 498, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 499, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 499, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 500, "RAZ", 1, 1, 0, 0},
- {"PTIME" , 7, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 500, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 501, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 501, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 501, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 501, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 502, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 502, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 502, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 502, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 502, "RAZ", 1, 1, 0, 0},
- {"BRK" , 6, 1, 502, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 502, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 502, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 503, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 503, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 503, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 503, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 503, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 503, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 503, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 503, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 503, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 504, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 504, "RAZ", 1, 1, 0, 0},
- {"DCTS" , 0, 1, 505, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 505, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 505, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 505, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 505, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 505, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 505, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 505, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 505, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 506, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 506, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 507, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 507, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 508, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 508, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 508, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 508, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 509, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 509, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 510, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 510, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 511, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 511, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 512, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 512, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 512, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 512, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 513, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 513, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 514, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 514, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 515, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 515, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 516, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 516, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 517, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 517, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 518, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 518, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 519, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 519, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 519, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 519, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 519, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 519, "RAZ", 1, 1, 0, 0},
- {"ORFDAT" , 0, 1, 520, "RO", 0, 0, 0ull, 0ull},
- {"IRFDAT" , 1, 1, 520, "RO", 0, 0, 0ull, 0ull},
- {"IPFDAT" , 2, 1, 520, "RO", 0, 0, 0ull, 0ull},
- {"MRQDAT" , 3, 1, 520, "RO", 0, 0, 0ull, 0ull},
- {"MRGDAT" , 4, 1, 520, "RO", 0, 0, 0ull, 0ull},
- {"OPFDAT" , 5, 1, 520, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 520, "RAZ", 0, 0, 0ull, 0ull},
- {"MRQ_HWM" , 0, 2, 521, "R/W", 0, 0, 0ull, 1ull},
- {"NBTARB" , 2, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"LENDIAN" , 3, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 4, 1, 521, "R/W", 0, 0, 1ull, 0ull},
- {"EN" , 5, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 6, 1, 521, "RO", 0, 0, 0ull, 0ull},
- {"CRC_STRIP" , 7, 1, 521, "R/W", 0, 0, 0ull, 0ull},
- {"TS_THRESH" , 8, 4, 521, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 521, "RAZ", 1, 1, 0, 0},
- {"OVFENA" , 0, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"IVFENA" , 1, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"OTHENA" , 2, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"ITHENA" , 3, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_DRPENA" , 4, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"IRUNENA" , 5, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"ORUNENA" , 6, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"TSENA" , 7, 1, 522, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 522, "RAZ", 1, 1, 0, 0},
- {"IRCNT" , 0, 20, 523, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 523, "RAZ", 1, 1, 0, 0},
- {"IRHWM" , 0, 20, 524, "R/W", 0, 0, 0ull, 0ull},
- {"IBPLWM" , 20, 20, 524, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 524, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 525, "RAZ", 1, 1, 0, 0},
- {"IBASE" , 3, 37, 525, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 40, 20, 525, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 525, "RAZ", 1, 1, 0, 0},
- {"IDBELL" , 0, 20, 526, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 526, "RAZ", 1, 1, 0, 0},
- {"ITLPTR" , 32, 20, 526, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 526, "RAZ", 1, 1, 0, 0},
- {"ODBLOVF" , 0, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"IDBLOVF" , 1, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORTHRESH" , 2, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"IRTHRESH" , 3, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"DATA_DRP" , 4, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"IRUN" , 5, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORUN" , 6, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
- {"TS" , 7, 1, 527, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 527, "RAZ", 1, 1, 0, 0},
- {"ORCNT" , 0, 20, 528, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 528, "RAZ", 1, 1, 0, 0},
- {"ORHWM" , 0, 20, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 529, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 530, "RAZ", 1, 1, 0, 0},
- {"OBASE" , 3, 37, 530, "R/W", 0, 1, 0ull, 0},
- {"OSIZE" , 40, 20, 530, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 530, "RAZ", 1, 1, 0, 0},
- {"ODBELL" , 0, 20, 531, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 531, "RAZ", 1, 1, 0, 0},
- {"OTLPTR" , 32, 20, 531, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 531, "RAZ", 1, 1, 0, 0},
- {"OREMCNT" , 0, 20, 532, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 532, "RAZ", 1, 1, 0, 0},
- {"IREMCNT" , 32, 20, 532, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_52_63" , 52, 12, 532, "RAZ", 1, 1, 0, 0},
- {"TSCNT" , 0, 5, 533, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 533, "RAZ", 1, 1, 0, 0},
- {"TSTOT" , 8, 5, 533, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 533, "RAZ", 1, 1, 0, 0},
- {"TSAVL" , 16, 5, 533, "RO", 0, 0, 4ull, 4ull},
- {"RESERVED_21_63" , 21, 43, 533, "RAZ", 1, 1, 0, 0},
- {"TSTAMP" , 0, 64, 534, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 3, 535, "R/W", 0, 1, 0ull, 0},
- {"ADR_CYC" , 3, 4, 535, "R/W", 0, 1, 8ull, 0},
- {"T_MULT" , 7, 4, 535, "R/W", 0, 1, 9ull, 0},
- {"RESERVED_11_63" , 11, 53, 535, "RAZ", 1, 1, 0, 0},
- {"NF_CMD" , 0, 64, 536, "R/W", 0, 1, 0ull, 0},
- {"CNT" , 0, 8, 537, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 537, "RAZ", 1, 1, 0, 0},
- {"ECC_ERR" , 0, 8, 538, "RO", 0, 1, 0ull, 0},
- {"XOR_ECC" , 8, 24, 538, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 538, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 539, "R/W1C", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 539, "R/W1C", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 539, "R/W1C", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 539, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 539, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 539, "R/W1C", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 539, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 539, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 540, "R/W", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 540, "R/W", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 540, "R/W", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 540, "R/W", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 540, "R/W", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 540, "R/W", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 540, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 540, "RAZ", 1, 1, 0, 0},
- {"RST_FF" , 0, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"EX_DIS" , 1, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"BT_DIS" , 2, 1, 541, "R/W", 0, 0, 0ull, 1ull},
- {"BT_DMA" , 3, 1, 541, "R/W", 0, 1, 0ull, 0},
- {"RD_CMD" , 4, 1, 541, "R/W", 0, 0, 0ull, 0ull},
- {"RD_VAL" , 5, 1, 541, "RO", 0, 1, 0ull, 0},
- {"RD_DONE" , 6, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
- {"FR_BYT" , 7, 11, 541, "RO", 0, 1, 0ull, 0},
- {"WAIT_CNT" , 18, 6, 541, "R/W", 0, 1, 20ull, 0},
- {"NBR_HWM" , 24, 3, 541, "R/W", 0, 0, 3ull, 3ull},
- {"MB_DIS" , 27, 1, 541, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 541, "RAZ", 1, 1, 0, 0},
- {"MAIN_SM" , 0, 3, 542, "RO", 0, 1, 0ull, 0},
- {"MAIN_BAD" , 3, 1, 542, "RO", 0, 1, 0ull, 0},
- {"RD_FF" , 4, 2, 542, "RO", 0, 1, 0ull, 0},
- {"RD_FF_BAD" , 6, 1, 542, "RO", 0, 1, 0ull, 0},
- {"BT_SM" , 7, 4, 542, "RO", 0, 1, 0ull, 0},
- {"EXE_SM" , 11, 4, 542, "RO", 0, 1, 0ull, 0},
- {"EXE_IDLE" , 15, 1, 542, "RO", 0, 1, 1ull, 0},
- {"RESERVED_16_63" , 16, 48, 542, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 543, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 543, "RO/WRSL", 0, 0, 144ull, 144ull},
- {"ISAE" , 0, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 544, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 544, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 544, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 544, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 544, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 544, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 544, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 544, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 544, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 544, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 544, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 544, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 544, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 544, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 544, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 544, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 544, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 544, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 545, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PI" , 8, 8, 545, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 545, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 545, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 546, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 546, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 546, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 546, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 546, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 547, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 547, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 547, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 547, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 547, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 548, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 548, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 549, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 550, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 551, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 551, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 551, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 551, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 551, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 552, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 552, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 553, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 554, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 555, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 555, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 555, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 555, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 556, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 556, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_8" , 0, 9, 557, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 9, 23, 557, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 558, "WORSL", 0, 0, 511ull, 511ull},
- {"CISP" , 0, 32, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 560, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 560, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 561, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 561, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 561, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 562, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 562, "WORSL", 0, 0, 32767ull, 32767ull},
- {"CP" , 0, 8, 563, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 563, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 564, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 564, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 564, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 564, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 565, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 565, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 565, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 565, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 565, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 565, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 565, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 565, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 565, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 565, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 566, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 566, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 566, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 566, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 566, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 566, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 566, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 566, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 566, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 566, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 566, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 566, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 567, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 567, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 567, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 567, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 567, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 567, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 567, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 568, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 568, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 569, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 570, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 570, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 571, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 571, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 571, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 571, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 571, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 571, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 571, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 572, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 572, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 572, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 572, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 572, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 572, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 572, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 572, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 572, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 572, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 572, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 573, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 573, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 573, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 573, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 573, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 573, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 573, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 573, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 573, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 573, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 573, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 573, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 573, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 574, "RO/WRSL", 0, 1, 2ull, 0},
- {"MLW" , 4, 6, 574, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"ASLPMS" , 10, 2, 574, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 574, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 574, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 574, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 574, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 574, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 574, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 575, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 575, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 575, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 575, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 575, "RO", 0, 0, 0ull, 8ull},
- {"RESERVED_26_26" , 26, 1, 575, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 575, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 575, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 575, "RAZ", 1, 1, 0, 0},
- {"ABP" , 0, 1, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 576, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 577, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 577, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 577, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 577, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 577, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 577, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 577, "R/W", 0, 0, 0ull, 0ull},
- {"PIC" , 8, 2, 577, "R/W", 0, 0, 0ull, 0ull},
- {"PCC" , 10, 1, 577, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 577, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 577, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 577, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 577, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 577, "RO", 0, 0, 0ull, 0ull},
- {"EMIS" , 23, 1, 577, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 577, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 577, "RAZ", 1, 1, 0, 0},
- {"CTRS" , 0, 4, 578, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 578, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 578, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 579, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 579, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 580, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 581, "R/W", 1, 1, 0, 0},
- {"EC" , 4, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 581, "RO", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 581, "RO", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 581, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 581, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 581, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 581, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 582, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 583, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 584, "RO", 0, 0, 1ull, 0ull},
- {"CV" , 16, 4, 584, "RO", 0, 0, 1ull, 0ull},
- {"NCO" , 20, 12, 584, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 585, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 585, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 585, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 586, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 586, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 586, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 586, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 586, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 587, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 587, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 587, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 587, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 587, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 587, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 587, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 587, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 588, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 588, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 588, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 589, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 589, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 589, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 589, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 590, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 590, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 590, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 590, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 590, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 590, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 591, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 592, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 593, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 594, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 595, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 595, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 596, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 597, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 597, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 597, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 597, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 598, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 598, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 598, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 598, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 598, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 598, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 599, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 599, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 599, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 599, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 599, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_22_24" , 22, 3, 599, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 599, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 599, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 600, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 600, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 601, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 601, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 601, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 601, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 601, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 601, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 601, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 601, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 602, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 602, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 602, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 603, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 603, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 603, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 604, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 605, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 606, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 606, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 606, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 607, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 607, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 607, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 608, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 608, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 608, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 609, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 609, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 609, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 609, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 610, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 610, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 610, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 610, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 611, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 611, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 611, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 611, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 612, "RO/WRSL", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 612, "RO/WRSL", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 612, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 612, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 612, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 612, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 612, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 613, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"HEADER_CREDITS" , 12, 8, 613, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 613, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 613, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 613, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 614, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 614, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 614, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 614, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 614, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 615, "RO/WRSL", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 615, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 615, "RO/WRSL", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 615, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 616, "RO/WRSL", 0, 0, 136ull, 136ull},
- {"RESERVED_14_15" , 14, 2, 616, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 616, "RO/WRSL", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 616, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 617, "RO/WRSL", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 617, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 617, "RO/WRSL", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 617, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 618, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 618, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 618, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 618, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 619, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 620, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 621, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 621, "R/W", 0, 0, 144ull, 144ull},
- {"ISAE" , 0, 1, 622, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 622, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 622, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 622, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 622, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 622, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 622, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 622, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 622, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 622, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 622, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 622, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 622, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 622, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 622, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 622, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 622, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 622, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 622, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 622, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 622, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 622, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 622, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 622, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 623, "R/W", 0, 0, 0ull, 0ull},
- {"PI" , 8, 8, 623, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 623, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 623, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 624, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 624, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 624, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 624, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 624, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 625, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 626, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 627, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 627, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 627, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 627, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 628, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 628, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 628, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 628, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 628, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 628, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 628, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 628, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 628, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 628, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 628, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 629, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 629, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 629, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 629, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 630, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 630, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 630, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 630, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 630, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 630, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 631, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 632, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 633, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 633, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 634, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 634, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 635, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 636, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 636, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 636, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 637, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 637, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 637, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 637, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 637, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 637, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 637, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 637, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 637, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 638, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 638, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 638, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 638, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 638, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 638, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 638, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 638, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 638, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 638, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 638, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 638, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 639, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 639, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 639, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 639, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 639, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 639, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 639, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 640, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 640, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 641, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 642, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 642, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 643, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 643, "R/W", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 643, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 643, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 643, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 643, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 644, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 644, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 644, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 644, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 644, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 644, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 644, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 644, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 644, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 644, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 645, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 645, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 645, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 645, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 645, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 645, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 645, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 645, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 645, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 645, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 645, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 645, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 646, "R/W", 0, 1, 2ull, 0},
- {"MLW" , 4, 6, 646, "R/W", 0, 0, 8ull, 4ull},
- {"ASLPMS" , 10, 2, 646, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 646, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 646, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 646, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 646, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 646, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_23" , 22, 2, 646, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 646, "R/W", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 647, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 647, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 647, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 647, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 647, "RO", 1, 1, 0, 0},
- {"NLW" , 20, 6, 647, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 647, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 647, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 647, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 647, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 647, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 647, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 648, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 648, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 648, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 649, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 649, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 649, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 649, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 649, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 649, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 649, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 649, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 649, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 649, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 649, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 649, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 649, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 650, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 650, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 650, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 650, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 650, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 650, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 650, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 650, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 651, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 651, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 651, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 651, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 652, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 652, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 652, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 653, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 653, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 654, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 655, "R/W", 1, 1, 0, 0},
- {"EC" , 4, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 655, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 655, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 655, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 656, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 657, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 658, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 658, "RO", 0, 0, 1ull, 1ull},
- {"NCO" , 20, 12, 658, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 659, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 659, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 659, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 659, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 660, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 660, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 660, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 660, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 661, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 661, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 661, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 661, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 661, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 661, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 661, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 661, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 662, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 662, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 662, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 663, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 663, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 663, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 663, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 664, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 664, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 664, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 664, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 664, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 664, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 665, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 666, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 667, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 668, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 669, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 670, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 670, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 671, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 671, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 672, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 672, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 673, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 674, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 674, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 674, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 674, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 674, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 674, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 675, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 675, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 675, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 675, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 675, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 675, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 676, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 676, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 676, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 676, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 676, "R/W", 0, 0, 15ull, 7ull},
- {"RESERVED_22_24" , 22, 3, 676, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 676, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 677, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 677, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 678, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 678, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 678, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 678, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 678, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 678, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 678, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 678, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 679, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 679, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 679, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 680, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 681, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 682, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 683, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 683, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 683, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 684, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 684, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 684, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 685, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 685, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 685, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 686, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 686, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 686, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 686, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 687, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 687, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 687, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 687, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 688, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 688, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 688, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 688, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 689, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 689, "R/W", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 689, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 689, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 689, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 689, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 689, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 690, "R/W", 0, 0, 32ull, 32ull},
- {"HEADER_CREDITS" , 12, 8, 690, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 690, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 690, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 690, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 691, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 691, "R/W", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 691, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 691, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 691, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 692, "R/W", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 692, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 692, "R/W", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 692, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 693, "R/W", 0, 0, 136ull, 136ull},
- {"RESERVED_14_15" , 14, 2, 693, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 693, "R/W", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 693, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 694, "R/W", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 694, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 694, "R/W", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 694, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 695, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 695, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 695, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 696, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 697, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 698, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 698, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 698, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 698, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 698, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 698, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 698, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 698, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 698, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 699, "RO", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 699, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 699, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 699, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 699, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 699, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 700, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 700, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 700, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 700, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 700, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 700, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 700, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 700, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 700, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 701, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 701, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 701, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 701, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 701, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 701, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 702, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 12, 1, 702, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 702, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 12, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 703, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 704, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 704, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 705, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 705, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 705, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 705, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 706, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 706, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 706, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 707, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 707, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 707, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 707, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 707, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 707, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 708, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 708, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 708, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 708, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 708, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 708, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 708, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 709, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 709, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 709, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 709, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 709, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 709, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 709, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 710, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 711, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 711, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 711, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 711, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 711, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 711, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 711, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 712, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 712, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 712, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 712, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 712, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 712, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 712, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 713, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 713, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 713, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 713, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 714, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 714, "RAZ", 1, 1, 0, 0},
- {"L0SYNC" , 0, 1, 715, "RO", 0, 0, 0ull, 1ull},
- {"L1SYNC" , 1, 1, 715, "RO", 0, 0, 0ull, 1ull},
- {"L2SYNC" , 2, 1, 715, "RO", 0, 0, 0ull, 1ull},
- {"L3SYNC" , 3, 1, 715, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_4_10" , 4, 7, 715, "RAZ", 1, 1, 0, 0},
- {"PATTST" , 11, 1, 715, "RO", 0, 0, 0ull, 0ull},
- {"ALIGND" , 12, 1, 715, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_63" , 13, 51, 715, "RAZ", 1, 1, 0, 0},
- {"BIST_STATUS" , 0, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 716, "RAZ", 1, 1, 0, 0},
- {"BITLCK0" , 0, 1, 717, "RO", 0, 1, 0ull, 0},
- {"BITLCK1" , 1, 1, 717, "RO", 0, 1, 0ull, 0},
- {"BITLCK2" , 2, 1, 717, "RO", 0, 1, 0ull, 0},
- {"BITLCK3" , 3, 1, 717, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 717, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 718, "RAZ", 1, 1, 0, 0},
- {"SPD" , 2, 4, 718, "RO", 0, 0, 0ull, 0ull},
- {"SPDSEL0" , 6, 1, 718, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_10" , 7, 4, 718, "RAZ", 1, 1, 0, 0},
- {"LO_PWR" , 11, 1, 718, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 718, "RAZ", 1, 1, 0, 0},
- {"SPDSEL1" , 13, 1, 718, "RO", 0, 0, 1ull, 1ull},
- {"LOOPBCK1" , 14, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 718, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 718, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 719, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 719, "RAZ", 1, 1, 0, 0},
- {"TXFLT_EN" , 0, 1, 720, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 1, 1, 720, "R/W", 0, 0, 0ull, 1ull},
- {"RXSYNBAD_EN" , 2, 1, 720, "R/W", 0, 0, 0ull, 1ull},
- {"BITLCKLS_EN" , 3, 1, 720, "R/W", 0, 0, 0ull, 1ull},
- {"SYNLOS_EN" , 4, 1, 720, "R/W", 0, 0, 0ull, 1ull},
- {"ALGNLOS_EN" , 5, 1, 720, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 6, 1, 720, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 720, "RAZ", 1, 1, 0, 0},
- {"TXFLT" , 0, 1, 721, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 1, 1, 721, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXSYNBAD" , 2, 1, 721, "R/W1C", 0, 0, 0ull, 0ull},
- {"BITLCKLS" , 3, 1, 721, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNLOS" , 4, 1, 721, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALGNLOS" , 5, 1, 721, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 6, 1, 721, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 721, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 722, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 722, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 722, "R/W1C", 0, 0, 0ull, 0ull},
- {"DROP_LN" , 4, 2, 722, "R/W", 0, 0, 0ull, 0ull},
- {"ENC_MODE" , 6, 1, 722, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 722, "RAZ", 1, 1, 0, 0},
- {"GMXENO" , 0, 1, 723, "R/W", 0, 0, 0ull, 0ull},
- {"XAUI" , 1, 1, 723, "RO", 1, 1, 0, 0},
- {"RX_SWAP" , 2, 1, 723, "R/W", 0, 1, 0ull, 0},
- {"TX_SWAP" , 3, 1, 723, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 723, "RAZ", 1, 1, 0, 0},
- {"SYNC0ST" , 0, 4, 724, "RO", 0, 1, 0ull, 0},
- {"SYNC1ST" , 4, 4, 724, "RO", 0, 1, 0ull, 0},
- {"SYNC2ST" , 8, 4, 724, "RO", 0, 1, 0ull, 0},
- {"SYNC3ST" , 12, 4, 724, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 724, "RAZ", 1, 1, 0, 0},
- {"TENGB" , 0, 1, 725, "RO", 0, 0, 1ull, 1ull},
- {"TENPASST" , 1, 1, 725, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 725, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 726, "RAZ", 1, 1, 0, 0},
- {"LPABLE" , 1, 1, 726, "RO", 0, 0, 1ull, 1ull},
- {"RCV_LNK" , 2, 1, 726, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_3_6" , 3, 4, 726, "RAZ", 1, 1, 0, 0},
- {"FLT" , 7, 1, 726, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 726, "RAZ", 1, 1, 0, 0},
- {"TENGB_R" , 0, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"TENGB_X" , 1, 1, 727, "RO", 0, 0, 1ull, 1ull},
- {"TENGB_W" , 2, 1, 727, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_9" , 3, 7, 727, "RAZ", 1, 1, 0, 0},
- {"RCVFLT" , 10, 1, 727, "RC", 0, 0, 0ull, 0ull},
- {"XMTFLT" , 11, 1, 727, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 727, "RAZ", 1, 1, 0, 0},
- {"DEV" , 14, 2, 727, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_16_63" , 16, 48, 727, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 728, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 728, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_TXPLRT" , 2, 4, 728, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_RXPLRT" , 6, 4, 728, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 728, "RAZ", 1, 1, 0, 0},
- {"TX_ST" , 0, 3, 729, "RO", 0, 1, 0ull, 0},
- {"RX_ST" , 3, 2, 729, "RO", 0, 1, 0ull, 0},
- {"ALGN_ST" , 5, 3, 729, "RO", 0, 1, 0ull, 0},
- {"RXBAD" , 8, 1, 729, "RO", 0, 0, 0ull, 0ull},
- {"SYN0BAD" , 9, 1, 729, "RO", 0, 0, 0ull, 0ull},
- {"SYN1BAD" , 10, 1, 729, "RO", 0, 0, 0ull, 0ull},
- {"SYN2BAD" , 11, 1, 729, "RO", 0, 0, 0ull, 0ull},
- {"SYN3BAD" , 12, 1, 729, "RO", 0, 0, 0ull, 0ull},
- {"TERM_ERR" , 13, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 729, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 730, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 730, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 730, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 16, 730, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 730, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 731, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 731, "R/W", 0, 0, 0ull, 1ull},
- {"BAR1_SIZ" , 4, 3, 731, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_7_63" , 7, 57, 731, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 732, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 732, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 732, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 3, 1, 732, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 4, 1, 732, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 5, 1, 732, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 6, 1, 732, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 7, 1, 732, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 732, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 6, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 7, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 8, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 9, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 733, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 734, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 734, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 735, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 735, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 736, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 736, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"FAST_LM" , 2, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 737, "R/W", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 737, "RAZ", 0, 0, 0ull, 0ull},
- {"CFG_RTRY" , 16, 16, 737, "R/W", 0, 0, 0ull, 32ull},
- {"RESERVED_32_33" , 32, 2, 737, "RAZ", 1, 1, 0, 0},
- {"PBUS" , 34, 8, 737, "RO", 1, 1, 0, 0},
- {"DNUM" , 42, 5, 737, "RO", 1, 1, 0, 0},
- {"AUTO_SD" , 47, 1, 737, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 737, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 738, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 739, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 740, "RO", 1, 1, 0, 0},
- {"AERI" , 0, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 741, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 741, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 742, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 742, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 743, "RO", 0, 0, 0ull, 0ull},
- {"SE" , 1, 1, 743, "R/W1C", 0, 0, 0ull, 0ull},
- {"PMEI" , 2, 1, 743, "RO", 0, 0, 0ull, 0ull},
- {"PMEM" , 3, 1, 743, "RO", 0, 0, 0ull, 0ull},
- {"UP_B1" , 4, 1, 743, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_B2" , 5, 1, 743, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_BX" , 6, 1, 743, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B1" , 7, 1, 743, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B2" , 8, 1, 743, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_BX" , 9, 1, 743, "R/W1C", 0, 0, 0ull, 0ull},
- {"EXC" , 10, 1, 743, "RO", 0, 0, 0ull, 0ull},
- {"RDLK" , 11, 1, 743, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_ER" , 12, 1, 743, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_DR" , 13, 1, 743, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 743, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 744, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 744, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 745, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 745, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_40" , 0, 41, 746, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 41, 23, 746, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 747, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 747, "R/W", 0, 1, 4503599627370495ull, 0},
- {"RESERVED_0_11" , 0, 12, 748, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 748, "R/W", 0, 1, 4503599627370495ull, 0},
- {"SLI_P" , 0, 8, 749, "R/W", 0, 0, 128ull, 128ull},
- {"SLI_NP" , 8, 8, 749, "R/W", 0, 0, 16ull, 16ull},
- {"SLI_CPL" , 16, 8, 749, "R/W", 0, 0, 128ull, 128ull},
- {"PEM_P" , 24, 8, 749, "R/W", 0, 0, 128ull, 128ull},
- {"PEM_NP" , 32, 8, 749, "R/W", 0, 0, 16ull, 16ull},
- {"PEM_CPL" , 40, 8, 749, "R/W", 0, 0, 128ull, 128ull},
- {"PEAI_PPF" , 48, 8, 749, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_56_63" , 56, 8, 749, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 750, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 750, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 750, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 750, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 750, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 18, 751, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 751, "RAZ", 1, 1, 0, 0},
- {"CLKEN" , 0, 1, 752, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 752, "RAZ", 0, 1, 0ull, 0},
- {"DPRT" , 0, 16, 753, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 753, "RAZ", 1, 1, 0, 0},
- {"MAP0" , 0, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 754, "R/W", 0, 0, 0ull, 0ull},
- {"MAP0" , 0, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"MINLEN" , 0, 16, 756, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 756, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 756, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 757, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 757, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 757, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 757, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 757, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 757, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 757, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 757, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 758, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 758, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 758, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 758, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 758, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 758, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 758, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 758, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 758, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 758, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 758, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 758, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 758, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 758, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 758, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 758, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 20, 1, 758, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_23" , 21, 3, 758, "RAZ", 1, 1, 0, 0},
- {"DSA_GRP_SID" , 24, 1, 758, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SCMD" , 25, 1, 758, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_TVID" , 26, 1, 758, "R/W", 0, 0, 0ull, 0ull},
- {"IHMSK_DIS" , 27, 1, 758, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 758, "RAZ", 1, 1, 0, 0},
- {"PRI" , 0, 6, 759, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 759, "RAZ", 1, 1, 0, 0},
- {"QOS" , 8, 3, 759, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 759, "RAZ", 1, 1, 0, 0},
- {"UP_QOS" , 12, 1, 759, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_13_63" , 13, 51, 759, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 760, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 761, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 762, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 762, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 763, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 763, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 763, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_EN" , 10, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"HIGIG_EN" , 11, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"CRC_EN" , 12, 1, 763, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 763, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VSEL" , 19, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 763, "R/W", 0, 0, 0ull, 0ull},
- {"HG_QOS" , 27, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT" , 28, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 763, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 763, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 763, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 763, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 763, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_63" , 53, 11, 763, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 764, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 764, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 764, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 764, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 764, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 764, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 764, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 764, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 765, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 765, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 766, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 766, "RAZ", 1, 1, 0, 0},
- {"QOS1" , 4, 3, 766, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 766, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 767, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 767, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 767, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 767, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 767, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 767, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 767, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 767, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 767, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 768, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 768, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 769, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 769, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 770, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 770, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 771, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 771, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 772, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 772, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 773, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 773, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 774, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 774, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 775, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 775, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 776, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 776, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 777, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 777, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 778, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 778, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 779, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 779, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 780, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 780, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 781, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 781, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 782, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 782, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 783, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 783, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 784, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 784, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 785, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 785, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 786, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 786, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 787, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 787, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 788, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 788, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 788, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 789, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 789, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 789, "RO", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 790, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 790, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 791, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 791, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 792, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 792, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 793, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 793, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 794, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 794, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 795, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 795, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 796, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 796, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 797, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 797, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 798, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 798, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 799, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 799, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 800, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 800, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 801, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 801, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 32, 802, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 802, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 803, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 803, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 804, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 804, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 804, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 804, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 805, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 805, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 805, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 805, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 805, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 806, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 806, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 806, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 806, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 807, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 807, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 807, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 807, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 807, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 807, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 807, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 807, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 808, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 808, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 808, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 808, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 809, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 809, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 809, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 809, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 809, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 810, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 811, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 811, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 811, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 811, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 811, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 812, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 813, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 813, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 813, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 813, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 813, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 813, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 813, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 813, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 813, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 813, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 813, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 813, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 813, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 814, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 814, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 814, "RO", 1, 0, 0, 0ull},
- {"MAJOR_3" , 54, 1, 814, "RO", 1, 0, 0, 0ull},
- {"PTP" , 55, 1, 814, "RO", 1, 0, 0, 0ull},
- {"RESERVED_56_63" , 56, 8, 814, "RAZ", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 815, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 815, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 815, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 815, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 815, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 815, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 815, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 815, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 815, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 815, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 815, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 815, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 815, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 816, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 816, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 816, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 816, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 816, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 816, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 817, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 817, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 817, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 817, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 6, 1, 817, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 817, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 817, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 817, "RO", 1, 0, 0, 0ull},
- {"RESERVED_29_63" , 29, 35, 817, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 818, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 818, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 818, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 818, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 819, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 819, "R/W", 1, 0, 0, 0ull},
- {"BP_PORT" , 10, 6, 819, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_52" , 16, 37, 819, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 819, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 61, 1, 819, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_62_63" , 62, 2, 819, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 820, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 820, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_10_52" , 10, 43, 820, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 820, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 820, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 821, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 821, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 821, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 821, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 821, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 822, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 822, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 822, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 822, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 823, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 823, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 823, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 823, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 823, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 823, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 823, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 823, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 823, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 824, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 824, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 824, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 824, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 824, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 825, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 825, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 825, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 825, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 825, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 825, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 8, 825, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 825, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 825, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 825, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 825, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 3, 825, "RO", 1, 0, 0, 0ull},
- {"OUT_DAT" , 32, 1, 825, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 825, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 825, "RO", 1, 0, 0, 0ull},
- {"RESERVED_35_63" , 35, 29, 825, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 826, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 826, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 826, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 826, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 827, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 828, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 829, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 830, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 831, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE1" , 4, 4, 831, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE2" , 8, 4, 831, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE3" , 12, 4, 831, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE4" , 16, 4, 831, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE5" , 20, 4, 831, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE6" , 24, 4, 831, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE7" , 28, 4, 831, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE8" , 32, 4, 831, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE9" , 36, 4, 831, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE10" , 40, 4, 831, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE11" , 44, 4, 831, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_48_63" , 48, 16, 831, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 12, 832, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 832, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 833, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 833, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 833, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 833, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 834, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 834, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 834, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 834, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 834, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 835, "R/W", 0, 0, 2ull, 2ull},
- {"MODE1" , 3, 3, 835, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 835, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 836, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 836, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 836, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 836, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 16, 837, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 837, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 838, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 838, "RAZ", 1, 1, 0, 0},
- {"PREEMPTER" , 0, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"PREEMPTEE" , 1, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 839, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 840, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 840, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 840, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 841, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 841, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 841, "RAZ", 1, 1, 0, 0},
- {"WQE_WORD" , 0, 4, 842, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_4_63" , 4, 60, 842, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 1, 843, "RO", 0, 0, 0ull, 0ull},
- {"PEND" , 1, 1, 843, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 2, 1, 843, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 3, 1, 843, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 4, 4, 843, "RO", 0, 0, 0ull, 0ull},
- {"NBR" , 8, 3, 843, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 11, 1, 843, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 843, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 6, 843, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 843, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 844, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 844, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 845, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 845, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 845, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 845, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 845, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 845, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 845, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 845, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 845, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 845, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 845, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 845, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 845, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 846, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 846, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 846, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 847, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 847, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 848, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 848, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 849, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 849, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 850, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 850, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 851, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 851, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 11, 852, "RO", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 852, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 853, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_10_63" , 10, 54, 853, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 854, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 854, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 855, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 855, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 855, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 855, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 855, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 855, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 855, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 855, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 855, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 855, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 856, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 856, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 856, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 856, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 856, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 10, 857, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_11" , 10, 2, 857, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 10, 857, "R/W", 0, 1, 1023ull, 0},
- {"RESERVED_22_23" , 22, 2, 857, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 11, 857, "RO", 0, 1, 1011ull, 0},
- {"RESERVED_35_35" , 35, 1, 857, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 36, 11, 857, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_47" , 47, 1, 857, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 48, 11, 857, "RO", 0, 1, 0ull, 0},
- {"RESERVED_59_63" , 59, 5, 857, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 858, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 858, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 859, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 859, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 860, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 860, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 861, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 861, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 861, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 11, 862, "RO", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 862, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 12, 11, 862, "RO", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 862, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 24, 4, 862, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 862, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 863, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 863, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 863, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 863, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 863, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 10, 864, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_11" , 10, 2, 864, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 10, 864, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_23" , 22, 2, 864, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 864, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 864, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 864, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 865, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 865, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 866, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 867, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 868, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 869, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 869, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 869, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 869, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 869, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 870, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 870, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 870, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 870, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 870, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 871, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 871, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 871, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 872, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 872, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 872, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 872, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 872, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 872, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 872, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 872, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 872, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 872, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 873, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 874, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 874, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 874, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 875, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 875, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 875, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 875, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 875, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 875, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 875, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 876, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 876, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 877, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 878, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 879, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 880, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 880, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 880, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 880, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 880, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 880, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 880, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 880, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 880, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 880, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 880, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 880, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 880, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 880, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 880, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 880, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 880, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 880, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 881, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 881, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 881, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 882, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 882, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 883, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 883, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 883, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 884, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 884, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 884, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 884, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 884, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 884, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 884, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 885, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 885, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 886, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 886, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 887, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 887, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 888, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 888, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 888, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 889, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 889, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 889, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 890, "R/W", 0, 0, 0ull, 0ull},
- {"EER_VAL" , 9, 1, 890, "RO", 0, 0, 0ull, 0ull},
- {"EER_LCK" , 10, 1, 890, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 890, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 891, "RO", 1, 1, 0, 0},
- {"KEY" , 0, 64, 892, "WO", 0, 0, 0ull, 0ull},
- {"NCB_CMD" , 0, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_0" , 2, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_1" , 3, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_0" , 4, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_1" , 5, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 893, "RAZ", 1, 1, 0, 0},
- {"P2N1_P1" , 9, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_24" , 19, 6, 893, "RAZ", 1, 1, 0, 0},
- {"CPL_P1" , 25, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_O" , 27, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_C" , 28, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_O" , 29, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 893, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_4" , 1, 4, 894, "R/W", 0, 0, 0ull, 0ull},
- {"PTLP_RO" , 5, 1, 894, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 894, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 894, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 894, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 894, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 894, "R/W", 0, 0, 3ull, 3ull},
- {"WAITL_COM" , 16, 1, 894, "R/W", 0, 1, 0ull, 0},
- {"DIS_PORT" , 17, 1, 894, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTA" , 18, 1, 894, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 19, 1, 894, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 20, 1, 894, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 21, 1, 894, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 894, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 895, "RO", 1, 1, 0, 0},
- {"P0_NTAGS" , 8, 6, 895, "R/W", 0, 0, 32ull, 32ull},
- {"P1_NTAGS" , 14, 6, 895, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_63" , 20, 44, 895, "RAZ", 1, 1, 0, 0},
- {"P0_FCNT" , 0, 6, 896, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 896, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 896, "RO", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 896, "RO", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 896, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 897, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 897, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 897, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 32, 898, "R/W", 0, 1, 0ull, 0},
- {"ADBG_SEL" , 32, 1, 898, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 898, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 899, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 899, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 900, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 900, "R/W", 0, 1, 0ull, 0},
- {"TIM" , 0, 32, 901, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 901, "RAZ", 1, 1, 0, 0},
- {"RML_TO" , 0, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 902, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 902, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 902, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 902, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 902, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 902, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 902, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 902, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 902, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 903, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT1" , 17, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"MAC0_INT" , 18, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"MAC1_INT" , 19, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_31" , 20, 12, 903, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 903, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 903, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 903, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 903, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT" , 4, 1, 904, "RO", 0, 0, 0ull, 0ull},
- {"PTIME" , 5, 1, 904, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_WI" , 9, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_B0" , 10, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_WI" , 11, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_B0" , 12, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_WI" , 13, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_B0" , 14, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_WI" , 15, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO_INT0" , 16, 1, 904, "RO", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 904, "RO", 0, 0, 0ull, 0ull},
- {"MAC0_INT" , 18, 1, 904, "RO", 0, 0, 0ull, 0ull},
- {"MAC1_INT" , 19, 1, 904, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 904, "RAZ", 1, 1, 0, 0},
- {"DMAFI" , 32, 2, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 904, "RO", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 904, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 904, "RAZ", 1, 1, 0, 0},
- {"PIDBOF" , 48, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 904, "RAZ", 1, 1, 0, 0},
- {"ILL_PAD" , 60, 1, 904, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 904, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 905, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 906, "RO", 0, 1, 0ull, 0},
- {"P0_PCNT" , 0, 8, 907, "R/W", 0, 0, 128ull, 128ull},
- {"P0_NCNT" , 8, 8, 907, "R/W", 0, 0, 16ull, 16ull},
- {"P0_CCNT" , 16, 8, 907, "R/W", 0, 0, 128ull, 128ull},
- {"P1_PCNT" , 24, 8, 907, "R/W", 0, 0, 128ull, 128ull},
- {"P1_NCNT" , 32, 8, 907, "R/W", 0, 0, 16ull, 16ull},
- {"P1_CCNT" , 40, 8, 907, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_48_63" , 48, 16, 907, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 908, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 908, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 908, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 30, 909, "R/W", 0, 1, 0ull, 0},
- {"RTYPE" , 30, 2, 909, "R/W", 0, 1, 0ull, 0},
- {"WTYPE" , 32, 2, 909, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 909, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 909, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 3, 909, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 42, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 909, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 910, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 911, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 912, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 913, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 914, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 916, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 917, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 918, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 918, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 918, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 64, 919, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 920, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 921, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 922, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 923, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 924, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 925, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 926, "R/W", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 927, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 927, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 927, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 928, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 928, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 929, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 929, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 929, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 930, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 930, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 930, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 931, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 931, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 931, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 932, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 32, 22, 932, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 932, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 32, 933, "R/W", 0, 0, 0ull, 0ull},
- {"WMARK" , 32, 32, 933, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_0_2" , 0, 3, 934, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 934, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 935, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 935, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 936, "R/W", 0, 1, 0ull, 0},
- {"FCNT" , 32, 5, 936, "RO", 0, 1, 0ull, 0},
- {"WRP" , 37, 9, 936, "RO", 0, 1, 0ull, 0},
- {"RRP" , 46, 9, 936, "RO", 0, 1, 0ull, 0},
- {"MAX" , 55, 9, 936, "RO", 0, 1, 16ull, 0},
- {"NTAG" , 0, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"NTT" , 1, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"NGRP" , 2, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"NQOS" , 3, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_5" , 4, 2, 937, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 937, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_13" , 13, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 937, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_20" , 16, 5, 937, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"RNTAG" , 22, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"RNTT" , 23, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"RNGRP" , 24, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"RNQOS" , 25, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_27" , 26, 2, 937, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 937, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_35" , 35, 1, 937, "RAZ", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 937, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_42" , 38, 5, 937, "RAZ", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 937, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 937, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 938, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 16, 7, 938, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 938, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 939, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 4, 60, 939, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 940, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 940, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 941, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 941, "RO", 0, 1, 0ull, 0},
- {"PORT" , 0, 32, 942, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 942, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 943, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 943, "RAZ", 1, 1, 0, 0},
- {"PKT_BP" , 0, 4, 944, "R/W", 0, 0, 15ull, 15ull},
- {"RING_EN" , 4, 1, 944, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 944, "RAZ", 1, 1, 0, 0},
- {"ES" , 0, 64, 945, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 946, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 946, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 947, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 947, "RAZ", 1, 1, 0, 0},
- {"DPTR" , 0, 32, 948, "R/W", 0, 0, 0ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 948, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 32, 949, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 949, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 950, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 950, "RO", 0, 1, 0ull, 0},
- {"RD_CNT" , 0, 32, 951, "RO", 0, 1, 0ull, 0},
- {"WR_CNT" , 32, 32, 951, "RO", 0, 1, 0ull, 0},
- {"PP" , 0, 64, 952, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 0, 1, 953, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 953, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 953, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 953, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 953, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 953, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 953, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 953, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 22, 1, 953, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_23_63" , 23, 41, 953, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 954, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 954, "RAZ", 1, 1, 0, 0},
- {"RDSIZE" , 0, 64, 955, "R/W", 0, 1, 0ull, 0},
- {"IS_64B" , 0, 32, 956, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 956, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 957, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 22, 957, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_63" , 54, 10, 957, "RAZ", 1, 1, 0, 0},
- {"IPTR" , 0, 32, 958, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 958, "RAZ", 1, 1, 0, 0},
- {"BMODE" , 0, 32, 959, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 959, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 960, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 960, "RAZ", 1, 1, 0, 0},
- {"WMARK" , 0, 32, 961, "R/W", 0, 0, 0ull, 14ull},
- {"RESERVED_32_63" , 32, 32, 961, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 64, 962, "R/W", 0, 1, 0ull, 0},
- {"OUT_RST" , 0, 32, 963, "RO", 0, 1, 0ull, 0},
- {"IN_RST" , 32, 32, 963, "RO", 0, 1, 0ull, 0},
- {"ES" , 0, 64, 964, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 965, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 965, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 966, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 966, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 967, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 967, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 968, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 968, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 3, 969, "R/W", 0, 0, 2ull, 2ull},
- {"BAR0_D" , 3, 1, 969, "R/W", 0, 0, 0ull, 0ull},
- {"WIND_D" , 4, 1, 969, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 969, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 970, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 971, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 972, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 972, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 972, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 972, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 973, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 973, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 973, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 973, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 973, "RO", 0, 1, 1ull, 0},
- {"RESERVED_47_47" , 47, 1, 973, "RAZ", 1, 1, 0, 0},
- {"NNP1" , 48, 8, 973, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 973, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 974, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 974, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 974, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 974, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 974, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 975, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 975, "R/W", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 975, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_51_63" , 51, 13, 975, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 976, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 977, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 977, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 977, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 977, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 978, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 979, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 979, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 980, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 980, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 981, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 981, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 981, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 981, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 981, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 981, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 982, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 982, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 982, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 982, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 982, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 982, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 983, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 984, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 984, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 984, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 984, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 985, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 985, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 985, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 985, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 986, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_6_7" , 6, 2, 986, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 6, 986, "R/W", 0, 0, 19ull, 19ull},
- {"RESERVED_14_63" , 14, 50, 986, "RAZ", 1, 1, 0, 0},
- {"DENY_BAR0" , 0, 1, 987, "R/W", 0, 0, 0ull, 0ull},
- {"DENY_BAR1" , 1, 1, 987, "R/W", 0, 0, 0ull, 0ull},
- {"DENY_BAR2" , 2, 1, 987, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 987, "RAZ", 1, 1, 0, 0},
- {"ASSY_VEN" , 0, 16, 988, "R/W", 0, 0, 140ull, 0ull},
- {"ASSY_ID" , 16, 16, 988, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 988, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 989, "RAZ", 1, 1, 0, 0},
- {"ASSY_REV" , 16, 16, 989, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 989, "RAZ", 1, 1, 0, 0},
- {"RP0_PID" , 0, 2, 990, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_PID" , 2, 1, 990, "R/W", 0, 0, 0ull, 0ull},
- {"RP0_SID" , 3, 2, 990, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_SID" , 5, 1, 990, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 990, "RAZ", 1, 1, 0, 0},
- {"OMSG" , 0, 7, 991, "RO", 0, 0, 0ull, 0ull},
- {"IMSG" , 7, 5, 991, "RO", 0, 0, 0ull, 0ull},
- {"RXBUF" , 12, 2, 991, "RO", 0, 0, 0ull, 0ull},
- {"TXBUF" , 14, 2, 991, "RO", 0, 0, 0ull, 0ull},
- {"OSPF" , 16, 1, 991, "RO", 0, 0, 0ull, 0ull},
- {"ISPF" , 17, 1, 991, "RO", 0, 0, 0ull, 0ull},
- {"OARB" , 18, 2, 991, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_23" , 20, 4, 991, "RAZ", 1, 1, 0, 0},
- {"OPTRS" , 24, 4, 991, "RO", 0, 0, 0ull, 0ull},
- {"OBULK" , 28, 4, 991, "RO", 0, 0, 0ull, 0ull},
- {"RTN" , 32, 2, 991, "RO", 0, 0, 0ull, 0ull},
- {"OFREE" , 34, 1, 991, "RO", 0, 0, 0ull, 0ull},
- {"ITAG" , 35, 1, 991, "RO", 0, 0, 0ull, 0ull},
- {"OTAG" , 36, 2, 991, "RO", 0, 0, 0ull, 0ull},
- {"BELL" , 38, 2, 991, "RO", 0, 0, 0ull, 0ull},
- {"CRAM" , 40, 2, 991, "RO", 0, 0, 0ull, 0ull},
- {"MRAM" , 42, 2, 991, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_44_63" , 44, 20, 991, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 992, "R/W", 0, 1, 0ull, 0},
- {"PRIO" , 4, 4, 992, "R/W", 0, 1, 0ull, 0},
- {"LTTR" , 8, 4, 992, "R/W", 0, 1, 0ull, 0},
- {"PRT_SEL" , 12, 3, 992, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 992, "RAZ", 1, 1, 0, 0},
- {"RP0_PID" , 16, 2, 992, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_PID" , 18, 1, 992, "R/W", 0, 0, 0ull, 0ull},
- {"RP0_SID" , 19, 2, 992, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_SID" , 21, 1, 992, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 992, "RAZ", 1, 1, 0, 0},
- {"RSP_THR" , 24, 6, 992, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 992, "RAZ", 1, 1, 0, 0},
- {"TO_MODE" , 31, 1, 992, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 992, "RAZ", 1, 1, 0, 0},
- {"TAG" , 0, 32, 993, "R/W", 0, 1, 0ull, 0},
- {"TT" , 32, 2, 993, "R/W", 0, 1, 0ull, 0},
- {"RS" , 34, 1, 993, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_41" , 35, 7, 993, "RAZ", 1, 1, 0, 0},
- {"NTAG" , 42, 1, 993, "R/W", 0, 1, 0ull, 0},
- {"NTT" , 43, 1, 993, "R/W", 0, 1, 0ull, 0},
- {"NGRP" , 44, 1, 993, "R/W", 0, 1, 0ull, 0},
- {"NQOS" , 45, 1, 993, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_47" , 46, 2, 993, "RAZ", 1, 1, 0, 0},
- {"SL" , 48, 7, 993, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_55_55" , 55, 1, 993, "RAZ", 1, 1, 0, 0},
- {"PM" , 56, 2, 993, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_62" , 58, 5, 993, "RAZ", 1, 1, 0, 0},
- {"R" , 63, 1, 993, "R/W", 0, 1, 0ull, 0},
- {"GRP0" , 0, 4, 994, "R/W", 0, 1, 0ull, 0},
- {"QOS0" , 4, 3, 994, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 994, "RAZ", 1, 1, 0, 0},
- {"GRP1" , 8, 4, 994, "R/W", 0, 1, 0ull, 0},
- {"QOS1" , 12, 3, 994, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 994, "RAZ", 1, 1, 0, 0},
- {"GRP2" , 16, 4, 994, "R/W", 0, 1, 0ull, 0},
- {"QOS2" , 20, 3, 994, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 994, "RAZ", 1, 1, 0, 0},
- {"GRP3" , 24, 4, 994, "R/W", 0, 1, 0ull, 0},
- {"QOS3" , 28, 3, 994, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_31_31" , 31, 1, 994, "RAZ", 1, 1, 0, 0},
- {"GRP4" , 32, 4, 994, "R/W", 0, 1, 0ull, 0},
- {"QOS4" , 36, 3, 994, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_39_39" , 39, 1, 994, "RAZ", 1, 1, 0, 0},
- {"GRP5" , 40, 4, 994, "R/W", 0, 1, 0ull, 0},
- {"QOS5" , 44, 3, 994, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_47_47" , 47, 1, 994, "RAZ", 1, 1, 0, 0},
- {"GRP6" , 48, 4, 994, "R/W", 0, 1, 0ull, 0},
- {"QOS6" , 52, 3, 994, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_55_55" , 55, 1, 994, "RAZ", 1, 1, 0, 0},
- {"GRP7" , 56, 4, 994, "R/W", 0, 1, 0ull, 0},
- {"QOS7" , 60, 3, 994, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_63_63" , 63, 1, 994, "RAZ", 1, 1, 0, 0},
- {"SID0" , 0, 16, 995, "RO", 0, 1, 0ull, 0},
- {"LTTR0" , 16, 2, 995, "RO", 0, 1, 0ull, 0},
- {"MBOX0" , 18, 2, 995, "RO", 0, 1, 0ull, 0},
- {"SEG0" , 20, 4, 995, "RO", 0, 1, 0ull, 0},
- {"DIS0" , 24, 1, 995, "RO", 0, 1, 0ull, 0},
- {"TT0" , 25, 1, 995, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_26" , 26, 1, 995, "RAZ", 1, 1, 0, 0},
- {"PRT0" , 27, 1, 995, "RO", 0, 1, 0ull, 0},
- {"TOC0" , 28, 1, 995, "RO", 0, 1, 0ull, 0},
- {"TOE0" , 29, 1, 995, "RO", 0, 1, 0ull, 0},
- {"ERR0" , 30, 1, 995, "RO", 0, 1, 0ull, 0},
- {"VAL0" , 31, 1, 995, "RO", 0, 1, 0ull, 0},
- {"SID1" , 32, 16, 995, "RO", 0, 1, 0ull, 0},
- {"LTTR1" , 48, 2, 995, "RO", 0, 1, 0ull, 0},
- {"MBOX1" , 50, 2, 995, "RO", 0, 1, 0ull, 0},
- {"SEG1" , 52, 4, 995, "RO", 0, 1, 0ull, 0},
- {"DIS1" , 56, 1, 995, "RO", 0, 1, 0ull, 0},
- {"TT1" , 57, 1, 995, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_58" , 58, 1, 995, "RAZ", 1, 1, 0, 0},
- {"PRT1" , 59, 1, 995, "RO", 0, 1, 0ull, 0},
- {"TOC1" , 60, 1, 995, "RO", 0, 1, 0ull, 0},
- {"TOE1" , 61, 1, 995, "RO", 0, 1, 0ull, 0},
- {"ERR1" , 62, 1, 995, "RO", 0, 1, 0ull, 0},
- {"VAL1" , 63, 1, 995, "RO", 0, 1, 0ull, 0},
- {"MAX_P0" , 0, 6, 996, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_6_7" , 6, 2, 996, "RAZ", 1, 1, 0, 0},
- {"MAX_P1" , 8, 6, 996, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_14_15" , 14, 2, 996, "RAZ", 1, 1, 0, 0},
- {"BUF_THR" , 16, 4, 996, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_30" , 20, 11, 996, "RAZ", 1, 1, 0, 0},
- {"SP_VPORT" , 31, 1, 996, "R/W", 0, 0, 1ull, 1ull},
- {"MAX_S0" , 32, 6, 996, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_38_39" , 38, 2, 996, "RAZ", 1, 1, 0, 0},
- {"MAX_S1" , 40, 6, 996, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_46_47" , 46, 2, 996, "RAZ", 1, 1, 0, 0},
- {"MAX_TOT" , 48, 6, 996, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_54_63" , 54, 10, 996, "RAZ", 1, 1, 0, 0},
- {"TXBELL" , 0, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"BELL_ERR" , 1, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"RXBELL" , 2, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"MAINT_OP" , 3, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"BAR_ERR" , 4, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"DENY_WR" , 5, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"SLI_ERR" , 6, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"WR_DONE" , 7, 1, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MCE_TX" , 8, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"MCE_RX" , 9, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"SOFT_TX" , 10, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"SOFT_RX" , 11, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"LOG_ERB" , 12, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"PHY_ERB" , 13, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"LINK_DWN" , 14, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"LINK_UP" , 15, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"OMSG0" , 16, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"OMSG1" , 17, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"OMSG_ERR" , 18, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"PKO_ERR" , 19, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"RTRY_ERR" , 20, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"F_ERROR" , 21, 1, 997, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 997, "RAZ", 1, 1, 0, 0},
- {"BE1" , 0, 8, 998, "RO", 0, 1, 0ull, 0},
- {"BE0" , 8, 8, 998, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_28" , 16, 13, 998, "RO", 1, 1, 0, 0},
- {"STATUS" , 29, 3, 998, "RO", 0, 1, 0ull, 0},
- {"LENGTH" , 32, 10, 998, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 998, "RO", 1, 1, 0, 0},
- {"TAG" , 48, 8, 998, "RO", 0, 1, 0ull, 0},
- {"TYPE" , 56, 4, 998, "RO", 0, 1, 0ull, 0},
- {"CMD" , 60, 4, 998, "RO", 0, 1, 0ull, 0},
- {"INFO1" , 0, 64, 999, "RO", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 1, 1000, "RO", 0, 1, 0ull, 0},
- {"LNS" , 1, 1, 1000, "RO", 0, 1, 0ull, 0},
- {"RSRVD" , 2, 30, 1000, "RO", 0, 1, 0ull, 0},
- {"LETTER" , 32, 2, 1000, "RO", 0, 1, 0ull, 0},
- {"MBOX" , 34, 2, 1000, "RO", 0, 1, 0ull, 0},
- {"XMBOX" , 36, 4, 1000, "RO", 0, 1, 0ull, 0},
- {"DID" , 40, 16, 1000, "RO", 0, 1, 0ull, 0},
- {"SSIZE" , 56, 4, 1000, "RO", 0, 1, 0ull, 0},
- {"SIS" , 60, 1, 1000, "RO", 0, 1, 0ull, 0},
- {"TT" , 61, 1, 1000, "RO", 0, 1, 0ull, 0},
- {"PRIO" , 62, 2, 1000, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_7" , 0, 8, 1001, "RAZ", 1, 1, 0, 0},
- {"OTHER" , 8, 48, 1001, "RO", 0, 1, 0ull, 0},
- {"TYPE" , 56, 4, 1001, "RO", 0, 1, 0ull, 0},
- {"TT" , 60, 2, 1001, "RO", 0, 1, 0ull, 0},
- {"PRIO" , 62, 2, 1001, "RO", 0, 1, 0ull, 0},
- {"TXBELL" , 0, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"BELL_ERR" , 1, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBELL" , 2, 1, 1002, "RO", 0, 0, 0ull, 0ull},
- {"MAINT_OP" , 3, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR_ERR" , 4, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"DENY_WR" , 5, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI_ERR" , 6, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"WR_DONE" , 7, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCE_TX" , 8, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCE_RX" , 9, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"SOFT_TX" , 10, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"SOFT_RX" , 11, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOG_ERB" , 12, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_ERB" , 13, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"LINK_DWN" , 14, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"LINK_UP" , 15, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"OMSG0" , 16, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"OMSG1" , 17, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"OMSG_ERR" , 18, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO_ERR" , 19, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTRY_ERR" , 20, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"F_ERROR" , 21, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 1002, "RAZ", 1, 1, 0, 0},
- {"RX_POL" , 0, 4, 1003, "R/W", 0, 0, 0ull, 0ull},
- {"TX_POL" , 4, 4, 1003, "R/W", 0, 0, 0ull, 0ull},
- {"PT_WIDTH" , 8, 2, 1003, "R/W", 0, 0, 2ull, 2ull},
- {"TX_FLOW" , 10, 1, 1003, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 1003, "RAZ", 1, 1, 0, 0},
- {"A50" , 12, 1, 1003, "R/W", 0, 0, 1ull, 1ull},
- {"A66" , 13, 1, 1003, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 1003, "RAZ", 1, 1, 0, 0},
- {"OPS" , 32, 32, 1003, "R/W", 0, 0, 64756ull, 64756ull},
- {"ADDR" , 0, 24, 1004, "R/W", 0, 1, 0ull, 0},
- {"OP" , 24, 1, 1004, "R/W", 0, 1, 0ull, 0},
- {"PENDING" , 25, 1, 1004, "RO", 0, 1, 0ull, 0},
- {"FAIL" , 26, 1, 1004, "RO", 0, 1, 0ull, 0},
- {"RESERVED_27_31" , 27, 5, 1004, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 32, 32, 1004, "R/W", 0, 1, 0ull, 0},
- {"RD_DATA" , 0, 32, 1005, "RO", 0, 1, 0ull, 0},
- {"VALID" , 32, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 1005, "RAZ", 1, 1, 0, 0},
- {"MCE" , 0, 1, 1006, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1006, "RAZ", 1, 1, 0, 0},
- {"RP0_PID" , 0, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_PID" , 2, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"RP0_SID" , 3, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_SID" , 5, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 1007, "RAZ", 1, 1, 0, 0},
- {"W_RO" , 8, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"RR_RO" , 9, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1007, "RAZ", 1, 1, 0, 0},
- {"LTTR_MP" , 0, 4, 1008, "R/W", 0, 1, 15ull, 0},
- {"LTTR_SP" , 4, 4, 1008, "R/W", 0, 1, 15ull, 0},
- {"IDM_DID" , 8, 1, 1008, "R/W", 0, 1, 1ull, 0},
- {"IDM_SIS" , 9, 1, 1008, "R/W", 0, 1, 1ull, 0},
- {"IDM_TT" , 10, 1, 1008, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_11_14" , 11, 4, 1008, "RAZ", 1, 1, 0, 0},
- {"RTRY_EN" , 15, 1, 1008, "R/W", 0, 1, 0ull, 0},
- {"RTRY_THR" , 16, 16, 1008, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_62" , 32, 31, 1008, "RAZ", 1, 1, 0, 0},
- {"TESTMODE" , 63, 1, 1008, "R/W", 0, 0, 0ull, 0ull},
- {"ALL_PSD" , 0, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"ALL_NMP" , 1, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"ALL_FMP" , 2, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"ALL_SP" , 3, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"MBOX_PSD" , 4, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"MBOX_NMP" , 5, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"MBOX_FMP" , 6, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"MBOX_SP" , 7, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"ID_PSD" , 8, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"ID_NMP" , 9, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"ID_FMP" , 10, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"ID_SP" , 11, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"CTLR_NMP" , 12, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"CTLR_FMP" , 13, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"CTLR_SP" , 14, 1, 1009, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 1009, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 1010, "R/W", 0, 0, 0ull, 0ull},
- {"ALL_NMP" , 1, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"ALL_FMP" , 2, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"ALL_SP" , 3, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_4" , 4, 1, 1010, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX_NMP" , 5, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"MBOX_FMP" , 6, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"MBOX_SP" , 7, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_8" , 8, 1, 1010, "R/W", 0, 0, 0ull, 0ull},
- {"ID_NMP" , 9, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"ID_FMP" , 10, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"ID_SP" , 11, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"CTLR_NMP" , 12, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"CTLR_FMP" , 13, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"CTLR_SP" , 14, 1, 1010, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 1010, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 2, 1011, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_30" , 2, 29, 1011, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 31, 1, 1011, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1011, "RAZ", 1, 1, 0, 0},
- {"ALL_PSD" , 0, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"ALL_NMP" , 1, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"ALL_FMP" , 2, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"ALL_SP" , 3, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"MBOX_PSD" , 4, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"MBOX_NMP" , 5, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"MBOX_FMP" , 6, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"MBOX_SP" , 7, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"ID_PSD" , 8, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"ID_NMP" , 9, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"ID_FMP" , 10, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"ID_SP" , 11, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"CTLR_NMP" , 12, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"CTLR_FMP" , 13, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"CTLR_SP" , 14, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"XMBOX_SP" , 15, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1012, "RAZ", 1, 1, 0, 0},
- {"PRIORITY" , 0, 2, 1013, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1013, "RAZ", 1, 1, 0, 0},
- {"ID16" , 3, 1, 1013, "RO", 0, 0, 0ull, 0ull},
- {"DEST_ID" , 4, 1, 1013, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 1013, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 8, 8, 1013, "RO", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 16, 16, 1013, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 32, 16, 1013, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1013, "RAZ", 1, 1, 0, 0},
- {"SEQ" , 0, 32, 1014, "RO", 0, 1, 0ull, 0},
- {"COUNT" , 32, 8, 1014, "RO", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 1014, "RAZ", 1, 1, 0, 0},
- {"POST" , 0, 8, 1015, "RO", 0, 1, 128ull, 0},
- {"N_POST" , 8, 5, 1015, "RO", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 1015, "RAZ", 1, 1, 0, 0},
- {"COMP" , 16, 8, 1015, "RO", 0, 1, 128ull, 0},
- {"MBOX" , 24, 4, 1015, "RO", 0, 1, 8ull, 0},
- {"RESERVED_28_39" , 28, 12, 1015, "RAZ", 1, 1, 0, 0},
- {"RTN_PR1" , 40, 8, 1015, "RO", 0, 1, 0ull, 0},
- {"RTN_PR2" , 48, 8, 1015, "RO", 0, 1, 0ull, 0},
- {"RTN_PR3" , 56, 8, 1015, "RO", 0, 1, 0ull, 0},
- {"IAOW_SEL" , 0, 2, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 1016, "RAZ", 1, 1, 0, 0},
- {"ID16" , 4, 1, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 5, 1, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 1016, "RAZ", 1, 1, 0, 0},
- {"RD_PRIOR" , 8, 2, 1016, "R/W", 0, 0, 1ull, 1ull},
- {"WR_PRIOR" , 10, 2, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"RD_OP" , 12, 3, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 1016, "RAZ", 1, 1, 0, 0},
- {"WR_OP" , 16, 3, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1016, "RAZ", 1, 1, 0, 0},
- {"SEQ" , 0, 32, 1017, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1017, "RAZ", 1, 1, 0, 0},
- {"SRIO" , 0, 1, 1018, "RO", 1, 1, 0, 0},
- {"ACCESS" , 1, 1, 1018, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 1018, "RAZ", 1, 1, 0, 0},
- {"ITAG" , 0, 5, 1019, "RO", 0, 1, 16ull, 0},
- {"RESERVED_5_7" , 5, 3, 1019, "RAZ", 1, 1, 0, 0},
- {"OTAG" , 8, 5, 1019, "RO", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 1019, "RAZ", 1, 1, 0, 0},
- {"O_CLR" , 16, 1, 1019, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1019, "RAZ", 1, 1, 0, 0},
- {"POST" , 0, 8, 1020, "R/W", 0, 0, 128ull, 128ull},
- {"N_POST" , 8, 5, 1020, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_13_15" , 13, 3, 1020, "RAZ", 1, 1, 0, 0},
- {"COMP" , 16, 8, 1020, "R/W", 0, 0, 128ull, 128ull},
- {"MBOX" , 24, 4, 1020, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_28_63" , 28, 36, 1020, "RAZ", 1, 1, 0, 0},
- {"PRIORITY" , 0, 2, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1021, "RAZ", 1, 1, 0, 0},
- {"ID16" , 3, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 4, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 1021, "RAZ", 1, 1, 0, 0},
- {"PENDING" , 8, 1, 1021, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 1021, "RAZ", 1, 1, 0, 0},
- {"DEST_ID" , 16, 16, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"DATA" , 32, 16, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1021, "RAZ", 1, 1, 0, 0},
- {"PRIORITY" , 0, 2, 1022, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1022, "RAZ", 1, 1, 0, 0},
- {"ID16" , 3, 1, 1022, "RO", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 4, 1, 1022, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 5, 1, 1022, "RO", 0, 0, 0ull, 0ull},
- {"ERROR" , 6, 1, 1022, "RO", 0, 0, 0ull, 0ull},
- {"TIMEOUT" , 7, 1, 1022, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1022, "RAZ", 1, 1, 0, 0},
- {"DEST_ID" , 16, 16, 1022, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 32, 16, 1022, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1022, "RAZ", 1, 1, 0, 0},
- {"TX_TH0" , 0, 4, 1023, "R/W", 0, 0, 6ull, 3ull},
- {"RESERVED_4_7" , 4, 4, 1023, "RAZ", 1, 1, 0, 0},
- {"TX_TH1" , 8, 4, 1023, "R/W", 0, 0, 4ull, 2ull},
- {"RESERVED_12_15" , 12, 4, 1023, "RAZ", 1, 1, 0, 0},
- {"TX_TH2" , 16, 4, 1023, "R/W", 0, 0, 2ull, 1ull},
- {"RESERVED_20_31" , 20, 12, 1023, "RAZ", 1, 1, 0, 0},
- {"TAG_TH0" , 32, 5, 1023, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_37_39" , 37, 3, 1023, "RAZ", 1, 1, 0, 0},
- {"TAG_TH1" , 40, 5, 1023, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_45_47" , 45, 3, 1023, "RAZ", 1, 1, 0, 0},
- {"TAG_TH2" , 48, 5, 1023, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_53_63" , 53, 11, 1023, "RAZ", 1, 1, 0, 0},
- {"S2M_PR0" , 0, 8, 1024, "RO", 0, 1, 0ull, 0},
- {"S2M_PR1" , 8, 8, 1024, "RO", 0, 1, 0ull, 0},
- {"S2M_PR2" , 16, 8, 1024, "RO", 0, 1, 0ull, 0},
- {"S2M_PR3" , 24, 8, 1024, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1024, "RAZ", 1, 1, 0, 0},
- {"ASSY_VEN" , 0, 16, 1025, "RO", 0, 0, 140ull, 0ull},
- {"ASSY_ID" , 16, 16, 1025, "RO", 0, 0, 0ull, 0ull},
- {"EXT_FPTR" , 0, 16, 1026, "RO", 0, 0, 256ull, 256ull},
- {"ASSY_REV" , 16, 16, 1026, "RO", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_2" , 1, 2, 1027, "RAZ", 1, 1, 0, 0},
- {"NCA" , 3, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 4, 2, 1027, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 1027, "RAZ", 1, 1, 0, 0},
- {"LA" , 8, 22, 1027, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 1027, "RAZ", 1, 1, 0, 0},
- {"FULL" , 0, 1, 1028, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 1028, "RAZ", 1, 1, 0, 0},
- {"COMP_TAG" , 0, 32, 1029, "R/W", 0, 0, 0ull, 0ull},
- {"MEMORY" , 0, 1, 1030, "R/W", 0, 0, 0ull, 1ull},
- {"DOORBELL" , 1, 1, 1030, "R/W", 0, 0, 0ull, 1ull},
- {"IMSG0" , 2, 1, 1030, "R/W", 0, 0, 0ull, 1ull},
- {"IMSG1" , 3, 1, 1030, "R/W", 0, 0, 0ull, 1ull},
- {"HALT" , 4, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 1030, "RAZ", 1, 1, 0, 0},
- {"VENDOR" , 0, 16, 1031, "RO", 0, 0, 140ull, 140ull},
- {"DEVICE" , 16, 16, 1031, "RO", 0, 1, 144ull, 0},
- {"REVISION" , 0, 8, 1032, "RO", 1, 1, 0, 0},
- {"RESERVED_8_31" , 8, 24, 1032, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 1033, "RAZ", 1, 1, 0, 0},
- {"PORT_WR" , 2, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SWP" , 3, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_CLR" , 4, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SET" , 5, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_DEC" , 6, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_INC" , 7, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"TESTSWAP" , 8, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"COMPSWAP" , 9, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 10, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"MSG" , 11, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"WRITE_R" , 12, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"SWRITE" , 13, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"WRITE" , 14, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"READ" , 15, 1, 1033, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_21" , 16, 6, 1033, "RAZ", 1, 1, 0, 0},
- {"TLB_INVS" , 22, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"TLB_INV" , 23, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"I_INVALD" , 24, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"IO_READ" , 25, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"D_FLUSH" , 26, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"CASTOUT" , 27, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"D_INVALD" , 28, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"RD_OWN" , 29, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"I_READ" , 30, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"GSM_READ" , 31, 1, 1033, "RO", 0, 0, 0ull, 0ull},
- {"VALID" , 0, 1, 1034, "R/W0C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_23" , 1, 23, 1034, "RAZ", 1, 1, 0, 0},
- {"ERR_TYPE" , 24, 5, 1034, "R/W", 0, 0, 0ull, 0ull},
- {"INF_TYPE" , 29, 3, 1034, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_TOUT" , 0, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ACK" , 1, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"DEL_ERR" , 2, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"F_TOGGLE" , 3, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"PROTERR" , 4, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_ACK" , 5, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_16" , 6, 11, 1035, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 17, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CRC" , 18, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"OUT_ACK" , 19, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"NACK" , 20, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ID" , 21, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"CTL_CRC" , 22, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"RATE_CNT" , 0, 8, 1036, "R/W", 0, 1, 0ull, 0},
- {"PK_RATE" , 8, 8, 1036, "R/W", 0, 1, 0ull, 0},
- {"RATE_LIM" , 16, 2, 1036, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_23" , 18, 6, 1036, "RAZ", 1, 1, 0, 0},
- {"ERR_BIAS" , 24, 8, 1036, "R/W", 0, 0, 128ull, 128ull},
- {"LNK_TOUT" , 0, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ACK" , 1, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"DEL_ERR" , 2, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"F_TOGGLE" , 3, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"PROTERR" , 4, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_ACK" , 5, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_16" , 6, 11, 1037, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 17, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CRC" , 18, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"OUT_ACK" , 19, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"NACK" , 20, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ID" , 21, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"CTL_CRC" , 22, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_15" , 0, 16, 1038, "RAZ", 1, 1, 0, 0},
- {"DGRAD_TH" , 16, 8, 1038, "R/W", 0, 0, 255ull, 128ull},
- {"FAIL_TH" , 24, 8, 1038, "R/W", 0, 0, 255ull, 255ull},
- {"EF_ID" , 0, 16, 1039, "RO", 0, 0, 7ull, 7ull},
- {"EF_PTR" , 16, 16, 1039, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 32, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"XADDR" , 0, 2, 1041, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1041, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 29, 1041, "R/W", 0, 0, 0ull, 0ull},
- {"CAPT_IDX" , 0, 5, 1042, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_5" , 5, 1, 1042, "R/W", 0, 0, 0ull, 0ull},
- {"WDPTR" , 6, 1, 1042, "R/W", 0, 0, 0ull, 0ull},
- {"TT" , 7, 1, 1042, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 8, 4, 1042, "R/W", 0, 0, 0ull, 0ull},
- {"STATUS" , 12, 4, 1042, "R/W", 0, 0, 0ull, 0ull},
- {"EXTRA" , 16, 8, 1042, "R/W", 0, 0, 0ull, 0ull},
- {"TTYPE" , 24, 4, 1042, "R/W", 0, 0, 0ull, 0ull},
- {"FTYPE" , 28, 4, 1042, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_14" , 0, 15, 1043, "RAZ", 1, 1, 0, 0},
- {"TT" , 15, 1, 1043, "R/W", 0, 0, 0ull, 0ull},
- {"ID8" , 16, 8, 1043, "R/W", 0, 0, 0ull, 0ull},
- {"ID16" , 24, 8, 1043, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID8" , 0, 8, 1044, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID16" , 8, 8, 1044, "R/W", 0, 0, 0ull, 0ull},
- {"DST_ID8" , 16, 8, 1044, "R/W", 0, 0, 0ull, 0ull},
- {"DST_ID16" , 24, 8, 1044, "R/W", 0, 0, 0ull, 0ull},
- {"RESP_SZ" , 0, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_21" , 1, 21, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_TRAN" , 22, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_RESP" , 23, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_TOUT" , 24, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_TOUT" , 25, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TGT" , 26, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TRAN" , 27, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_FMT" , 28, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"GSM_ERR" , 29, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_ERR" , 30, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"IO_ERR" , 31, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"RESP_SZ" , 0, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_21" , 1, 21, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_TRAN" , 22, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_RESP" , 23, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_TOUT" , 24, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_TOUT" , 25, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TGT" , 26, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TRAN" , 27, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_FMT" , 28, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"GSM_ERR" , 29, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_ERR" , 30, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"IO_ERR" , 31, 1, 1046, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1047, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1048, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1049, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1050, "R/W", 0, 0, 0ull, 0ull},
- {"HOSTID" , 0, 16, 1051, "R/W", 0, 0, 65535ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1051, "RAZ", 1, 1, 0, 0},
- {"RX_SYNC" , 0, 1, 1052, "R/W", 0, 0, 0ull, 0ull},
- {"TX_SYNC" , 1, 1, 1052, "R/W", 0, 0, 0ull, 0ull},
- {"TX_FLOW" , 2, 1, 1052, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_19" , 3, 17, 1052, "R/W", 0, 0, 0ull, 0ull},
- {"TX_WM2" , 20, 4, 1052, "R/W", 0, 0, 2ull, 1ull},
- {"TX_WM1" , 24, 4, 1052, "R/W", 0, 0, 3ull, 2ull},
- {"TX_WM0" , 28, 4, 1052, "R/W", 0, 0, 4ull, 3ull},
- {"PD_CTRL" , 0, 32, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"LN0_DIS" , 0, 1, 1054, "RO", 0, 0, 0ull, 0ull},
- {"LN0_RX" , 1, 3, 1054, "RO", 0, 0, 0ull, 0ull},
- {"LN1_DIS" , 4, 1, 1054, "RO", 0, 0, 0ull, 0ull},
- {"LN1_RX" , 5, 3, 1054, "RO", 0, 0, 0ull, 0ull},
- {"LN2_DIS" , 8, 1, 1054, "RO", 0, 0, 0ull, 0ull},
- {"LN2_RX" , 9, 3, 1054, "RO", 0, 0, 0ull, 0ull},
- {"LN3_DIS" , 12, 1, 1054, "RO", 0, 0, 0ull, 0ull},
- {"LN3_RX" , 13, 3, 1054, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1054, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_26" , 0, 27, 1055, "RAZ", 1, 1, 0, 0},
- {"LOOPBACK" , 27, 2, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_29" , 29, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"RX_RESET" , 30, 1, 1055, "R/W", 0, 0, 1ull, 1ull},
- {"TX_RESET" , 31, 1, 1055, "R/W", 0, 0, 1ull, 1ull},
- {"INIT_SM" , 0, 10, 1056, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 1056, "RAZ", 1, 1, 0, 0},
- {"OVERWRT" , 0, 1, 1057, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 1057, "RAZ", 1, 1, 0, 0},
- {"PKT_DATA" , 0, 32, 1058, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_ST" , 0, 4, 1059, "RO", 0, 0, 0ull, 0ull},
- {"FULL" , 4, 1, 1059, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_11" , 5, 7, 1059, "RAZ", 1, 1, 0, 0},
- {"BUFFERS" , 12, 4, 1059, "RO", 0, 0, 0ull, 0ull},
- {"OCTETS" , 16, 16, 1059, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_15" , 0, 16, 1060, "RAZ", 1, 1, 0, 0},
- {"OCTETS" , 16, 16, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_DATA" , 0, 32, 1061, "R/W", 0, 0, 0ull, 0ull},
- {"FIFO_ST" , 0, 4, 1062, "RO", 0, 0, 0ull, 0ull},
- {"FULL" , 4, 1, 1062, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_11" , 5, 7, 1062, "RAZ", 1, 1, 0, 0},
- {"BUFFERS" , 12, 4, 1062, "RO", 0, 0, 0ull, 0ull},
- {"OCTETS" , 16, 16, 1062, "RO", 0, 0, 0ull, 0ull},
- {"STATUSN" , 0, 3, 1063, "RO", 0, 0, 0ull, 0ull},
- {"STATUS1" , 3, 1, 1063, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_5" , 4, 2, 1063, "RAZ", 1, 1, 0, 0},
- {"XTRAIN" , 6, 1, 1063, "RO", 0, 0, 0ull, 0ull},
- {"XSYNC" , 7, 1, 1063, "RO", 0, 0, 0ull, 0ull},
- {"DEC_ERR" , 8, 4, 1063, "RO", 0, 0, 0ull, 0ull},
- {"RX_TRAIN" , 12, 1, 1063, "RO", 0, 0, 0ull, 0ull},
- {"RX_SYNC" , 13, 1, 1063, "RO", 0, 0, 0ull, 0ull},
- {"RX_ADAPT" , 14, 1, 1063, "RO", 0, 0, 1ull, 1ull},
- {"RX_INV" , 15, 1, 1063, "RO", 0, 0, 0ull, 0ull},
- {"RX_TYPE" , 16, 2, 1063, "RO", 0, 0, 0ull, 0ull},
- {"TX_MODE" , 18, 1, 1063, "RO", 0, 0, 0ull, 0ull},
- {"TX_TYPE" , 19, 1, 1063, "RO", 0, 0, 0ull, 0ull},
- {"LANE" , 20, 4, 1063, "RO", 0, 0, 0ull, 0ull},
- {"PORT" , 24, 8, 1063, "RO", 0, 0, 0ull, 0ull},
- {"LCSBA" , 0, 31, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1064, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_20" , 0, 21, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"LCSBA" , 21, 11, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR48" , 0, 16, 1066, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR64" , 16, 16, 1066, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1067, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR66" , 1, 2, 1067, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_13" , 3, 11, 1067, "RAZ", 1, 1, 0, 0},
- {"ADDR32" , 14, 18, 1067, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR48" , 0, 16, 1068, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR64" , 16, 16, 1068, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1069, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR66" , 1, 2, 1069, "R/W", 0, 0, 0ull, 0ull},
- {"BARSIZE" , 3, 3, 1069, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_19" , 6, 14, 1069, "RAZ", 1, 1, 0, 0},
- {"ADDR32" , 20, 12, 1069, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR66" , 1, 2, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"CAX" , 3, 1, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"ESX" , 4, 2, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 1070, "RAZ", 1, 1, 0, 0},
- {"ADDR48" , 9, 7, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR64" , 16, 16, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"EX_ADDR" , 0, 3, 1071, "RO", 0, 0, 7ull, 7ull},
- {"EX_FEAT" , 3, 1, 1071, "RO", 0, 0, 1ull, 1ull},
- {"LG_TRAN" , 4, 1, 1071, "RO", 0, 0, 1ull, 1ull},
- {"CRF" , 5, 1, 1071, "RO", 0, 0, 0ull, 0ull},
- {"SUPPRESS" , 6, 1, 1071, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 1071, "RAZ", 1, 1, 0, 0},
- {"MULT_PRT" , 27, 1, 1071, "RO", 0, 0, 0ull, 0ull},
- {"SWITCHF" , 28, 1, 1071, "RO", 0, 0, 0ull, 0ull},
- {"PROC" , 29, 1, 1071, "RO", 0, 0, 1ull, 1ull},
- {"MEMORY" , 30, 1, 1071, "RO", 0, 0, 1ull, 1ull},
- {"BRIDGE" , 31, 1, 1071, "RO", 0, 0, 0ull, 0ull},
- {"EX_ADDR" , 0, 3, 1072, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_31" , 3, 29, 1072, "RAZ", 1, 1, 0, 0},
- {"PT_TYPE" , 0, 1, 1073, "RO", 0, 0, 1ull, 1ull},
- {"PRT_LOCK" , 1, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"DROP_PKT" , 2, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"STP_PORT" , 3, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"SUPPRESS" , 4, 8, 1073, "RO", 0, 0, 0ull, 0ull},
- {"EX_STAT" , 12, 2, 1073, "RO", 0, 0, 0ull, 0ull},
- {"EX_WIDTH" , 14, 2, 1073, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 1073, "RAZ", 1, 1, 0, 0},
- {"ENUMB" , 17, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_18" , 18, 1, 1073, "RAZ", 1, 1, 0, 0},
- {"MCAST" , 19, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_ERR" , 20, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"I_ENABLE" , 21, 1, 1073, "R/W", 0, 0, 0ull, 1ull},
- {"O_ENABLE" , 22, 1, 1073, "R/W", 0, 0, 0ull, 1ull},
- {"DISABLE" , 23, 1, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"OV_WIDTH" , 24, 3, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"IT_WIDTH" , 27, 3, 1073, "RO", 0, 1, 0ull, 0},
- {"PT_WIDTH" , 30, 2, 1073, "RO", 0, 0, 2ull, 2ull},
- {"EMPH_EN" , 0, 1, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EMPH" , 1, 1, 1074, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"ENB_625G" , 16, 1, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"SUP_625G" , 17, 1, 1074, "RO", 0, 0, 0ull, 0ull},
- {"ENB_500G" , 18, 1, 1074, "R/W", 1, 1, 0, 0},
- {"SUB_500G" , 19, 1, 1074, "RO", 1, 1, 0, 0},
- {"ENB_312G" , 20, 1, 1074, "R/W", 1, 1, 0, 0},
- {"SUP_312G" , 21, 1, 1074, "RO", 1, 1, 0, 0},
- {"ENB_250G" , 22, 1, 1074, "R/W", 1, 1, 0, 0},
- {"SUP_250G" , 23, 1, 1074, "RO", 1, 1, 0, 0},
- {"ENB_125G" , 24, 1, 1074, "R/W", 1, 1, 0, 0},
- {"SUP_125G" , 25, 1, 1074, "RO", 1, 1, 0, 0},
- {"BAUD_ENB" , 26, 1, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"BAUD_SUP" , 27, 1, 1074, "RO", 0, 0, 0ull, 0ull},
- {"SEL_BAUD" , 28, 4, 1074, "RO", 0, 1, 0ull, 0},
- {"PT_UINIT" , 0, 1, 1075, "RO", 0, 0, 1ull, 0ull},
- {"PT_OK" , 1, 1, 1075, "RO", 0, 0, 0ull, 1ull},
- {"PT_ERROR" , 2, 1, 1075, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1075, "RAZ", 1, 1, 0, 0},
- {"PT_WRITE" , 4, 1, 1075, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 1075, "RAZ", 1, 1, 0, 0},
- {"I_SM_ERR" , 8, 1, 1075, "RO", 0, 0, 0ull, 0ull},
- {"I_ERROR" , 9, 1, 1075, "R/W1C", 0, 0, 0ull, 0ull},
- {"I_SM_RET" , 10, 1, 1075, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 1075, "RAZ", 1, 1, 0, 0},
- {"O_SM_ERR" , 16, 1, 1075, "RO", 0, 0, 0ull, 0ull},
- {"O_ERROR" , 17, 1, 1075, "R/W1C", 0, 0, 0ull, 0ull},
- {"O_SM_RET" , 18, 1, 1075, "RO", 0, 0, 0ull, 0ull},
- {"O_RTRIED" , 19, 1, 1075, "RO", 0, 0, 0ull, 0ull},
- {"O_RETRY" , 20, 1, 1075, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 1075, "RAZ", 1, 1, 0, 0},
- {"O_DGRAD" , 24, 1, 1075, "R/W1C", 0, 0, 0ull, 0ull},
- {"O_FAIL" , 25, 1, 1075, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKT_DROP" , 26, 1, 1075, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 1075, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_28" , 0, 29, 1076, "RAZ", 1, 1, 0, 0},
- {"DISCOVER" , 29, 1, 1076, "R/W", 0, 0, 0ull, 1ull},
- {"MENABLE" , 30, 1, 1076, "R/W", 1, 0, 0, 1ull},
- {"HOST" , 31, 1, 1076, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1077, "RAZ", 1, 1, 0, 0},
- {"TIMEOUT" , 8, 24, 1077, "R/W", 0, 0, 16777215ull, 0ull},
- {"EF_ID" , 0, 16, 1078, "RO", 0, 0, 1ull, 0ull},
- {"EF_PTR" , 16, 16, 1078, "RO", 0, 0, 4096ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1079, "RAZ", 1, 1, 0, 0},
- {"TIMEOUT" , 8, 24, 1079, "R/W", 0, 0, 16777215ull, 0ull},
- {"ID16" , 0, 16, 1080, "R/W", 0, 0, 65535ull, 0ull},
- {"ID8" , 16, 8, 1080, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1080, "RAZ", 1, 1, 0, 0},
- {"ENABLE16" , 0, 1, 1081, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE8" , 1, 1, 1081, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 1081, "RAZ", 1, 1, 0, 0},
- {"ID16" , 0, 16, 1082, "R/W", 0, 0, 65535ull, 0ull},
- {"ID8" , 16, 8, 1082, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1082, "RAZ", 1, 1, 0, 0},
- {"EF_ID" , 0, 16, 1083, "RO", 0, 0, 13ull, 13ull},
- {"EF_PTR" , 16, 16, 1083, "RO", 0, 0, 8192ull, 0ull},
- {"RESERVED_0_1" , 0, 2, 1084, "RAZ", 1, 1, 0, 0},
- {"PORT_WR" , 2, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SWP" , 3, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_CLR" , 4, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SET" , 5, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_DEC" , 6, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_INC" , 7, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"TESTSWAP" , 8, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"COMPSWAP" , 9, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 10, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"MSG" , 11, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"WRITE_R" , 12, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"SWRITE" , 13, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"WRITE" , 14, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"READ" , 15, 1, 1084, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_21" , 16, 6, 1084, "RAZ", 1, 1, 0, 0},
- {"TLB_INVS" , 22, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"TLB_INV" , 23, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"I_INVALD" , 24, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"IO_READ" , 25, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"D_FLUSH" , 26, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"CASTOUT" , 27, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"D_INVALD" , 28, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"RD_OWN" , 29, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"I_READ" , 30, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"GSM_READ" , 31, 1, 1084, "RO", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 0, 22, 1085, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 1085, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 1085, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 1085, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 1085, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 1085, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 1086, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 1086, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 1086, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 1087, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1087, "RO", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 1087, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 1087, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 1087, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 1088, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 1089, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 1090, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 1090, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 1090, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 1090, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1091, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1091, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 1092, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1092, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1093, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1094, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 1094, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1094, "RAZ", 1, 1, 0, 0},
- {"TDF" , 0, 1, 1095, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1095, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"CLKALWAYS" , 15, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1096, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 1097, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 1097, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 1097, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 1098, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 1098, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 1098, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1098, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 1098, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1099, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1099, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1100, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1100, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1101, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1101, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1101, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1101, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1101, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1101, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1102, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1102, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1102, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1102, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1102, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 6, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_15" , 6, 10, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 1104, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 1104, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 1104, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 1104, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1104, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 1105, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1106, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1106, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1107, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1107, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1109, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1109, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1109, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1109, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1109, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 6, 1110, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_15" , 6, 10, 1110, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1110, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1110, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1110, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1110, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1110, "R/W", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1111, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1111, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1112, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1113, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1113, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1113, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1113, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1113, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1113, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1114, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1114, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1114, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1114, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1114, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 6, 1115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_15" , 6, 10, 1115, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1115, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1115, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1115, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 1116, "R/W", 0, 1, 0ull, 0},
- {"LPL" , 5, 27, 1116, "R/W", 0, 1, 0ull, 0},
- {"CF" , 0, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_31" , 1, 31, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"CTRLDSSEG" , 0, 32, 1118, "R/W", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1119, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_31" , 14, 18, 1119, "RO", 0, 0, 0ull, 0ull},
- {"CAPLENGTH" , 0, 8, 1120, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_15" , 8, 8, 1120, "RO", 0, 0, 0ull, 0ull},
- {"HCIVERSION" , 16, 16, 1120, "RO", 0, 0, 256ull, 256ull},
- {"AC64" , 0, 1, 1121, "RO", 0, 0, 1ull, 1ull},
- {"PFLF" , 1, 1, 1121, "RO", 0, 0, 0ull, 0ull},
- {"ASPC" , 2, 1, 1121, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1121, "RO", 0, 0, 0ull, 0ull},
- {"IST" , 4, 4, 1121, "RO", 0, 0, 2ull, 2ull},
- {"EECP" , 8, 8, 1121, "RO", 0, 0, 160ull, 160ull},
- {"RESERVED_16_31" , 16, 16, 1121, "RO", 0, 0, 0ull, 0ull},
- {"N_PORTS" , 0, 4, 1122, "RO", 0, 0, 2ull, 2ull},
- {"PPC" , 4, 1, 1122, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 1122, "RO", 0, 0, 0ull, 0ull},
- {"PRR" , 7, 1, 1122, "RO", 0, 0, 0ull, 0ull},
- {"N_PCC" , 8, 4, 1122, "RO", 0, 0, 2ull, 2ull},
- {"N_CC" , 12, 4, 1122, "RO", 0, 0, 1ull, 1ull},
- {"P_INDICATOR" , 16, 1, 1122, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 1122, "RO", 0, 0, 0ull, 0ull},
- {"DPN" , 20, 4, 1122, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1122, "RO", 0, 0, 0ull, 0ull},
- {"EN" , 0, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"MFMC" , 1, 13, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_0" , 0, 1, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"TA_OFF" , 1, 8, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"TXTX_TADAO" , 10, 3, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_RW" , 0, 1, 1125, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_FW" , 1, 1, 1125, "R/W", 0, 0, 0ull, 0ull},
- {"PESD" , 2, 1, 1125, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1125, "RAZ", 0, 0, 0ull, 0ull},
- {"NAKRF_DIS" , 4, 1, 1125, "R/W", 0, 0, 0ull, 0ull},
- {"AUTO_DIS" , 5, 1, 1125, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 1125, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_30" , 0, 31, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1127, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 1128, "R/W", 0, 1, 0ull, 0},
- {"BADDR" , 12, 20, 1128, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1129, "RO", 0, 0, 0ull, 0ull},
- {"CSC" , 1, 1, 1129, "R/W1C", 0, 0, 0ull, 0ull},
- {"PED" , 2, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"PEDC" , 3, 1, 1129, "R/W1C", 0, 0, 0ull, 0ull},
- {"OCA" , 4, 1, 1129, "RO", 0, 0, 0ull, 0ull},
- {"OCC" , 5, 1, 1129, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPR" , 6, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"SPD" , 7, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"PRST" , 8, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1129, "RO", 0, 0, 0ull, 0ull},
- {"LSTS" , 10, 2, 1129, "RO", 0, 1, 0ull, 0},
- {"PP" , 12, 1, 1129, "RO", 0, 0, 1ull, 1ull},
- {"PO" , 13, 1, 1129, "R/W", 0, 0, 1ull, 0ull},
- {"PIC" , 14, 2, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"PTC" , 16, 4, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"WKCNNT_E" , 20, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"WKDSCNNT_E" , 21, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"WKOC_E" , 22, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 1129, "RO", 0, 0, 0ull, 0ull},
- {"RS" , 0, 1, 1130, "R/W", 0, 0, 0ull, 1ull},
- {"HCRESET" , 1, 1, 1130, "R/W", 0, 0, 0ull, 0ull},
- {"FLS" , 2, 2, 1130, "RO", 0, 0, 0ull, 0ull},
- {"PS_EN" , 4, 1, 1130, "R/W", 0, 0, 0ull, 0ull},
- {"AS_EN" , 5, 1, 1130, "R/W", 0, 0, 0ull, 0ull},
- {"IAA_DB" , 6, 1, 1130, "R/W", 0, 0, 0ull, 0ull},
- {"LHCR" , 7, 1, 1130, "R/W", 0, 0, 0ull, 0ull},
- {"ASPMC" , 8, 2, 1130, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1130, "RO", 0, 0, 0ull, 0ull},
- {"ASPM_EN" , 11, 1, 1130, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 1130, "RO", 0, 0, 0ull, 0ull},
- {"ITC" , 16, 8, 1130, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_24_31" , 24, 8, 1130, "RO", 0, 0, 0ull, 0ull},
- {"USBINT_EN" , 0, 1, 1131, "R/W", 0, 1, 0ull, 0},
- {"USBERRINT_EN" , 1, 1, 1131, "R/W", 0, 1, 0ull, 0},
- {"PCI_EN" , 2, 1, 1131, "R/W", 0, 1, 0ull, 0},
- {"FLRO_EN" , 3, 1, 1131, "R/W", 0, 1, 0ull, 0},
- {"HSERR_EN" , 4, 1, 1131, "R/W", 0, 1, 0ull, 0},
- {"IOAA_EN" , 5, 1, 1131, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 1131, "RO", 0, 0, 0ull, 0ull},
- {"USBINT" , 0, 1, 1132, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBERRINT" , 1, 1, 1132, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCD" , 2, 1, 1132, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLRO" , 3, 1, 1132, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSYSERR" , 4, 1, 1132, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOAA" , 5, 1, 1132, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 1132, "RO", 0, 0, 0ull, 0ull},
- {"HCHTD" , 12, 1, 1132, "RO", 0, 0, 1ull, 0ull},
- {"RECLM" , 13, 1, 1132, "RO", 0, 0, 0ull, 0ull},
- {"PSS" , 14, 1, 1132, "RO", 0, 0, 0ull, 0ull},
- {"ASS" , 15, 1, 1132, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1132, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1133, "R/W", 0, 0, 0ull, 0ull},
- {"BCED" , 4, 28, 1133, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"BHED" , 4, 28, 1134, "R/W", 0, 1, 0ull, 0},
- {"HCR" , 0, 1, 1135, "R/W", 0, 0, 0ull, 0ull},
- {"CLF" , 1, 1, 1135, "R/W", 0, 0, 0ull, 0ull},
- {"BLF" , 2, 1, 1135, "R/W", 0, 0, 0ull, 0ull},
- {"OCR" , 3, 1, 1135, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1135, "RO", 0, 0, 0ull, 0ull},
- {"SOC" , 16, 2, 1135, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 1135, "RO", 0, 0, 0ull, 0ull},
- {"CBSR" , 0, 2, 1136, "R/W", 0, 1, 0ull, 0},
- {"PLE" , 2, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"IE" , 3, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"CLE" , 4, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"BLE" , 5, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"HCFS" , 6, 2, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"IR" , 8, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"RWC" , 9, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"RWE" , 10, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 1136, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"CCED" , 4, 28, 1137, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"CHED" , 4, 28, 1138, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1139, "RO", 0, 0, 0ull, 0ull},
- {"DH" , 4, 28, 1139, "RO", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1140, "R/W", 0, 1, 11999ull, 0},
- {"RESERVED_14_15" , 14, 2, 1140, "R/W", 0, 0, 0ull, 0ull},
- {"FSMPS" , 16, 15, 1140, "R/W", 0, 1, 0ull, 0},
- {"FIT" , 31, 1, 1140, "R/W", 0, 0, 0ull, 0ull},
- {"FN" , 0, 16, 1141, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 1141, "RO", 0, 0, 0ull, 0ull},
- {"FR" , 0, 14, 1142, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_30" , 14, 17, 1142, "RO", 0, 0, 0ull, 0ull},
- {"FRT" , 31, 1, 1142, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1143, "R/W", 0, 0, 0ull, 0ull},
- {"HCCA" , 8, 24, 1143, "R/W", 0, 1, 0ull, 0},
- {"SO" , 0, 1, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1144, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1145, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1146, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1146, "R/W1C", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1146, "R/W1C", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1146, "R/W1C", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1146, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1146, "RO", 0, 0, 0ull, 0ull},
- {"LST" , 0, 12, 1147, "R/W", 0, 1, 1576ull, 0},
- {"RESERVED_12_31" , 12, 20, 1147, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1148, "RO", 0, 0, 0ull, 0ull},
- {"PCED" , 4, 28, 1148, "RO", 0, 1, 0ull, 0},
- {"PS" , 0, 14, 1149, "R/W", 0, 0, 0ull, 15975ull},
- {"RESERVED_14_31" , 14, 18, 1149, "R/W", 0, 0, 0ull, 0ull},
- {"REV" , 0, 8, 1150, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_31" , 8, 24, 1150, "RO", 0, 0, 0ull, 0ull},
- {"NDP" , 0, 8, 1151, "RO", 0, 0, 2ull, 2ull},
- {"NPS" , 8, 1, 1151, "R/W", 0, 0, 0ull, 0ull},
- {"PSM" , 9, 1, 1151, "R/W", 0, 0, 1ull, 1ull},
- {"DT" , 10, 1, 1151, "RO", 0, 0, 0ull, 0ull},
- {"OCPM" , 11, 1, 1151, "R/W", 1, 1, 0, 0},
- {"NOCP" , 12, 1, 1151, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_23" , 13, 11, 1151, "RO", 0, 0, 0ull, 0ull},
- {"POTPGT" , 24, 8, 1151, "R/W", 0, 0, 1ull, 1ull},
- {"DR" , 0, 16, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"PPCM" , 16, 16, 1152, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"PES" , 1, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"PSS" , 2, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"POCI" , 3, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"PRS" , 4, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1153, "R/W", 0, 0, 0ull, 0ull},
- {"PPS" , 8, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"LSDA" , 9, 1, 1153, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_15" , 10, 6, 1153, "R/W", 0, 0, 0ull, 0ull},
- {"CSC" , 16, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"PESC" , 17, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"PSSC" , 18, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"OCIC" , 19, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"PRSC" , 20, 1, 1153, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_31" , 21, 11, 1153, "R/W", 0, 0, 0ull, 0ull},
- {"LPS" , 0, 1, 1154, "R/W", 0, 0, 0ull, 0ull},
- {"OCI" , 1, 1, 1154, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_14" , 2, 13, 1154, "RO", 0, 0, 0ull, 0ull},
- {"DRWE" , 15, 1, 1154, "R/W", 0, 1, 0ull, 0},
- {"LPSC" , 16, 1, 1154, "R/W", 0, 1, 0ull, 0},
- {"CCIC" , 17, 1, 1154, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_18_30" , 18, 13, 1154, "RO", 0, 0, 0ull, 0ull},
- {"CRWE" , 31, 1, 1154, "WO", 1, 1, 0, 0},
- {"RESERVED_0_30" , 0, 31, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1156, "RO", 0, 0, 0ull, 0ull},
- {"PPAF_BIS" , 0, 1, 1157, "RO", 0, 0, 0ull, 0ull},
- {"WRBM_BIS" , 1, 1, 1157, "RO", 0, 0, 0ull, 0ull},
- {"ORBM_BIS" , 2, 1, 1157, "RO", 0, 0, 0ull, 0ull},
- {"ERBM_BIS" , 3, 1, 1157, "RO", 0, 0, 0ull, 0ull},
- {"DESC_BIS" , 4, 1, 1157, "RO", 0, 0, 0ull, 0ull},
- {"DATA_BIS" , 5, 1, 1157, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1157, "RO", 1, 1, 0, 0},
- {"HRST" , 0, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"P_PRST" , 1, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"P_POR" , 2, 1, 1158, "R/W", 0, 0, 1ull, 0ull},
- {"P_COM_ON" , 3, 1, 1158, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 1158, "R/W", 0, 1, 0ull, 0},
- {"P_REFCLK_DIV" , 5, 2, 1158, "R/W", 0, 0, 0ull, 0ull},
- {"P_REFCLK_SEL" , 7, 2, 1158, "R/W", 0, 0, 0ull, 0ull},
- {"H_DIV" , 9, 4, 1158, "R/W", 0, 0, 6ull, 6ull},
- {"O_CLKDIV_EN" , 13, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_EN" , 14, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_RST" , 15, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_BYP" , 16, 1, 1158, "R/W", 0, 0, 0ull, 0ull},
- {"O_CLKDIV_RST" , 17, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"APP_START_CLK" , 18, 1, 1158, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_SUSP_LGCY" , 19, 1, 1158, "R/W", 0, 0, 1ull, 1ull},
- {"OHCI_SM" , 20, 1, 1158, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_CLKCKTRST" , 21, 1, 1158, "R/W", 0, 0, 1ull, 1ull},
- {"EHCI_SM" , 22, 1, 1158, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 23, 1, 1158, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 24, 1, 1158, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1158, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1159, "R/W", 0, 1, 0ull, 0},
- {"EHCI_64B_ADDR_EN" , 8, 1, 1159, "R/W", 0, 0, 1ull, 1ull},
- {"INV_REG_A2" , 9, 1, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1159, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1159, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"DESC_RBM" , 19, 1, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1159, "RAZ", 1, 1, 0, 0},
- {"FLA" , 0, 6, 1160, "R/W", 0, 0, 0ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 1160, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 1161, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 5, 27, 1161, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1161, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1162, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1162, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1163, "R/W", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1163, "R/W", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1163, "R/W", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1163, "R/W", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1163, "R/W", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1163, "R/W", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1163, "R/W", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1163, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1163, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1164, "R/W1C", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1164, "R/W1C", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1164, "R/W1C", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1164, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1164, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1164, "R/W1C", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1164, "R/W1C", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1164, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1164, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1165, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_8" , 8, 1, 1165, "RAZ", 1, 1, 0, 0},
- {"INV_REG_A2" , 9, 1, 1165, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1165, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1165, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1165, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1165, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1165, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1165, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1165, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1165, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1166, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 8, 24, 1166, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1166, "RAZ", 1, 1, 0, 0},
- {"WM" , 0, 5, 1167, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_5_63" , 5, 59, 1167, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_EN" , 1, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"UPHY_BIST" , 2, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_EN" , 3, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"SIDDQ" , 4, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 5, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 6, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"HSBIST" , 7, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ERR" , 8, 1, 1168, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 9, 1, 1168, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1168, "RAZ", 1, 1, 0, 0},
- {"TDATA_IN" , 0, 8, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 8, 4, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 12, 1, 1169, "R/W", 0, 0, 1ull, 0ull},
- {"TCLK" , 13, 1, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_EN" , 14, 1, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"COMPDISTUNE" , 15, 3, 1169, "R/W", 0, 0, 4ull, 4ull},
- {"SQRXTUNE" , 18, 3, 1169, "R/W", 0, 0, 4ull, 4ull},
- {"TXFSLSTUNE" , 21, 4, 1169, "R/W", 0, 0, 3ull, 3ull},
- {"TXPREEMPHASISTUNE" , 25, 1, 1169, "R/W", 0, 0, 0ull, 1ull},
- {"TXRISETUNE" , 26, 1, 1169, "R/W", 0, 0, 0ull, 1ull},
- {"TXVREFTUNE" , 27, 4, 1169, "R/W", 0, 0, 5ull, 15ull},
- {"TXHSVXTUNE" , 31, 2, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 33, 1, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"VBUSVLDEXT" , 34, 1, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"DPPULLDOWN" , 35, 1, 1169, "R/W", 0, 0, 1ull, 1ull},
- {"DMPULLDOWN" , 36, 1, 1169, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFEN" , 37, 1, 1169, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFENH" , 38, 1, 1169, "R/W", 0, 0, 1ull, 1ull},
- {"TDATA_OUT" , 39, 4, 1169, "RO", 1, 1, 0, 0},
- {"RESERVED_43_63" , 43, 21, 1169, "RAZ", 1, 1, 0, 0},
- {"ZIP_CTL" , 0, 4, 1170, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 39, 1170, "RO", 1, 0, 0, 0ull},
- {"RESERVED_43_63" , 43, 21, 1170, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 1171, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 1172, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 1172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1172, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 1173, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 1173, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 1173, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 1173, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 1173, "RO", 0, 0, 31744ull, 31744ull},
- {"RESERVED_48_63" , 48, 16, 1173, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 17, 1174, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1174, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1175, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1175, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1176, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1176, "RAZ", 1, 1, 0, 0},
- {"MAX_INFL" , 0, 4, 1177, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 1177, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn63xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 14, 0},
- {"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 14},
- {"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 13, 16},
- {"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 1, 29},
- {"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 30},
- {"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 31},
- {"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 32},
- {"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 1, 33},
- {"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 1, 34},
- {"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 35},
- {"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 4, 37},
- {"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 41},
- {"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 11, 43},
- {"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 14, 54},
- {"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 68},
- {"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 70},
- {"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 72},
- {"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 21, 74},
- {"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 21, 95},
- {"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 2, 116},
- {"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 38, 2, 118},
- {"cvmx_agl_gmx_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 4, 120},
- {"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 124},
- {"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 126},
- {"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 128},
- {"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 130},
- {"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 132},
- {"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 134},
- {"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 136},
- {"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 138},
- {"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 140},
- {"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 142},
- {"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 4, 144},
- {"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 2, 148},
- {"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 150},
- {"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 2, 152},
- {"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 70, 4, 154},
- {"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 4, 158},
- {"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 2, 162},
- {"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 3, 164},
- {"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 5, 167},
- {"cvmx_agl_gmx_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 2, 172},
- {"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 3, 174},
- {"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 81, 2, 177},
- {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 179},
- {"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 85, 2, 181},
- {"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 87, 2, 183},
- {"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 89, 2, 185},
- {"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 187},
- {"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 93, 2, 189},
- {"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 95, 2, 191},
- {"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 97, 2, 193},
- {"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 2, 195},
- {"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 197},
- {"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 2, 199},
- {"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 2, 201},
- {"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 2, 203},
- {"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 109, 2, 205},
- {"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 111, 2, 207},
- {"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 2, 209},
- {"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 115, 2, 211},
- {"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 117, 2, 213},
- {"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 118, 2, 215},
- {"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 3, 217},
- {"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 120, 12, 220},
- {"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 121, 12, 232},
- {"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 2, 244},
- {"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 123, 2, 246},
- {"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 124, 6, 248},
- {"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 125, 2, 254},
- {"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 126, 2, 256},
- {"cvmx_agl_prt#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 127, 23, 258},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 129, 2, 281},
- {"cvmx_ciu_block_int" , CVMX_CSR_DB_TYPE_NCB, 64, 130, 37, 283},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 131, 2, 320},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 132, 2, 322},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 133, 2, 324},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 134, 22, 326},
- {"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 148, 22, 348},
- {"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 162, 22, 370},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 176, 33, 392},
- {"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 190, 33, 425},
- {"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 204, 33, 458},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 218, 22, 491},
- {"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 22, 513},
- {"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 230, 22, 535},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 236, 33, 557},
- {"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 242, 33, 590},
- {"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 248, 33, 623},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 254, 22, 656},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 267, 22, 678},
- {"cvmx_ciu_int33_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 273, 22, 700},
- {"cvmx_ciu_int_dbg_sel" , CVMX_CSR_DB_TYPE_NCB, 64, 274, 6, 722},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 275, 33, 728},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 276, 2, 761},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 282, 2, 763},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 288, 2, 765},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 289, 2, 767},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 290, 2, 769},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 291, 1, 771},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 297, 3, 772},
- {"cvmx_ciu_qlm0" , CVMX_CSR_DB_TYPE_NCB, 64, 298, 13, 775},
- {"cvmx_ciu_qlm1" , CVMX_CSR_DB_TYPE_NCB, 64, 299, 13, 788},
- {"cvmx_ciu_qlm2" , CVMX_CSR_DB_TYPE_NCB, 64, 300, 8, 801},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 301, 6, 809},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 302, 8, 815},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 303, 2, 823},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 304, 2, 825},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 305, 2, 827},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 306, 2, 829},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 307, 3, 831},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 311, 7, 834},
- {"cvmx_dfa_bist0" , CVMX_CSR_DB_TYPE_RSL, 64, 317, 12, 841},
- {"cvmx_dfa_bist1" , CVMX_CSR_DB_TYPE_RSL, 64, 318, 12, 853},
- {"cvmx_dfa_config" , CVMX_CSR_DB_TYPE_RSL, 64, 319, 5, 865},
- {"cvmx_dfa_control" , CVMX_CSR_DB_TYPE_RSL, 64, 320, 7, 870},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 321, 2, 877},
- {"cvmx_dfa_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 322, 1, 879},
- {"cvmx_dfa_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 323, 1, 880},
- {"cvmx_dfa_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 324, 1, 881},
- {"cvmx_dfa_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 325, 1, 882},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 326, 4, 883},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 327, 3, 887},
- {"cvmx_dfa_dtcfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 328, 6, 890},
- {"cvmx_dfa_error" , CVMX_CSR_DB_TYPE_RSL, 64, 329, 5, 896},
- {"cvmx_dfa_intmsk" , CVMX_CSR_DB_TYPE_RSL, 64, 330, 3, 901},
- {"cvmx_dfa_memhidat" , CVMX_CSR_DB_TYPE_NCB, 64, 331, 1, 904},
- {"cvmx_dfa_pfc0_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 332, 1, 905},
- {"cvmx_dfa_pfc0_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 333, 5, 906},
- {"cvmx_dfa_pfc1_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 334, 1, 911},
- {"cvmx_dfa_pfc1_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 335, 5, 912},
- {"cvmx_dfa_pfc2_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 336, 1, 917},
- {"cvmx_dfa_pfc2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 337, 5, 918},
- {"cvmx_dfa_pfc3_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 338, 1, 923},
- {"cvmx_dfa_pfc3_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 339, 5, 924},
- {"cvmx_dfa_pfc_gctl" , CVMX_CSR_DB_TYPE_RSL, 64, 340, 18, 929},
- {"cvmx_dfm_char_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 341, 5, 947},
- {"cvmx_dfm_char_mask0" , CVMX_CSR_DB_TYPE_RSL, 64, 342, 2, 952},
- {"cvmx_dfm_char_mask2" , CVMX_CSR_DB_TYPE_RSL, 64, 343, 2, 954},
- {"cvmx_dfm_char_mask4" , CVMX_CSR_DB_TYPE_RSL, 64, 344, 12, 956},
- {"cvmx_dfm_comp_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 345, 11, 968},
- {"cvmx_dfm_config" , CVMX_CSR_DB_TYPE_RSL, 64, 346, 21, 979},
- {"cvmx_dfm_control" , CVMX_CSR_DB_TYPE_RSL, 64, 347, 20, 1000},
- {"cvmx_dfm_dll_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 348, 6, 1020},
- {"cvmx_dfm_dll_ctl3" , CVMX_CSR_DB_TYPE_RSL, 64, 349, 11, 1026},
- {"cvmx_dfm_fclk_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 350, 1, 1037},
- {"cvmx_dfm_fnt_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 351, 6, 1038},
- {"cvmx_dfm_fnt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 352, 5, 1044},
- {"cvmx_dfm_fnt_iena" , CVMX_CSR_DB_TYPE_RSL, 64, 353, 3, 1049},
- {"cvmx_dfm_fnt_sclk" , CVMX_CSR_DB_TYPE_RSL, 64, 354, 4, 1052},
- {"cvmx_dfm_fnt_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 355, 6, 1056},
- {"cvmx_dfm_ifb_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 356, 1, 1062},
- {"cvmx_dfm_modereg_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 357, 16, 1063},
- {"cvmx_dfm_modereg_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 358, 25, 1079},
- {"cvmx_dfm_ops_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 359, 1, 1104},
- {"cvmx_dfm_phy_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 360, 10, 1105},
- {"cvmx_dfm_reset_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 361, 5, 1115},
- {"cvmx_dfm_rlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 362, 10, 1120},
- {"cvmx_dfm_rlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 363, 1, 1130},
- {"cvmx_dfm_rlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 364, 5, 1131},
- {"cvmx_dfm_rodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 366, 8, 1136},
- {"cvmx_dfm_slot_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 367, 5, 1144},
- {"cvmx_dfm_slot_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 368, 5, 1149},
- {"cvmx_dfm_timing_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 369, 12, 1154},
- {"cvmx_dfm_timing_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 370, 13, 1166},
- {"cvmx_dfm_wlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 371, 6, 1179},
- {"cvmx_dfm_wlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 372, 3, 1185},
- {"cvmx_dfm_wlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 373, 5, 1188},
- {"cvmx_dfm_wodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 375, 8, 1193},
- {"cvmx_dpi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 376, 2, 1201},
- {"cvmx_dpi_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 377, 3, 1203},
- {"cvmx_dpi_dma#_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 378, 3, 1206},
- {"cvmx_dpi_dma#_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 386, 2, 1209},
- {"cvmx_dpi_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 394, 7, 1211},
- {"cvmx_dpi_dma#_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 402, 2, 1218},
- {"cvmx_dpi_dma#_reqbnk0" , CVMX_CSR_DB_TYPE_NCB, 64, 410, 1, 1220},
- {"cvmx_dpi_dma#_reqbnk1" , CVMX_CSR_DB_TYPE_NCB, 64, 418, 1, 1221},
- {"cvmx_dpi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 426, 19, 1222},
- {"cvmx_dpi_dma_eng#_en" , CVMX_CSR_DB_TYPE_NCB, 64, 427, 2, 1241},
- {"cvmx_dpi_eng#_buf" , CVMX_CSR_DB_TYPE_NCB, 64, 433, 3, 1243},
- {"cvmx_dpi_info_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 439, 5, 1246},
- {"cvmx_dpi_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 440, 15, 1251},
- {"cvmx_dpi_int_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 441, 15, 1266},
- {"cvmx_dpi_pint_info" , CVMX_CSR_DB_TYPE_NCB, 64, 442, 4, 1281},
- {"cvmx_dpi_pkt_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 443, 2, 1285},
- {"cvmx_dpi_req_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 444, 2, 1287},
- {"cvmx_dpi_req_err_rsp_en" , CVMX_CSR_DB_TYPE_NCB, 64, 445, 2, 1289},
- {"cvmx_dpi_req_err_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 446, 2, 1291},
- {"cvmx_dpi_req_err_rst_en" , CVMX_CSR_DB_TYPE_NCB, 64, 447, 2, 1293},
- {"cvmx_dpi_req_gbl_en" , CVMX_CSR_DB_TYPE_NCB, 64, 448, 2, 1295},
- {"cvmx_dpi_sli_prt#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 449, 14, 1297},
- {"cvmx_dpi_sli_prt#_err" , CVMX_CSR_DB_TYPE_NCB, 64, 451, 2, 1311},
- {"cvmx_dpi_sli_prt#_err_info" , CVMX_CSR_DB_TYPE_NCB, 64, 453, 6, 1313},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 455, 6, 1319},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 10, 1325},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 457, 3, 1335},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 2, 1338},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 3, 1340},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 2, 1343},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 473, 45, 1345},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 474, 45, 1390},
- {"cvmx_fpa_packet_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 475, 2, 1435},
- {"cvmx_fpa_pool#_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 476, 2, 1437},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 484, 2, 1439},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 492, 2, 1441},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 500, 3, 1443},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 501, 3, 1446},
- {"cvmx_fpa_wqe_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 502, 2, 1449},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 7, 1451},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 504, 2, 1458},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 505, 2, 1460},
- {"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 506, 5, 1462},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 7, 1467},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 508, 2, 1474},
- {"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 509, 8, 1476},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 510, 10, 1484},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 514, 1, 1494},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 518, 1, 1495},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 522, 1, 1496},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 526, 1, 1497},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 530, 1, 1498},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 534, 1, 1499},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 538, 2, 1500},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 542, 4, 1502},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 546, 2, 1506},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 550, 9, 1508},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 554, 13, 1517},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 558, 2, 1530},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 562, 27, 1532},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 566, 27, 1559},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 570, 2, 1586},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 574, 2, 1588},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 578, 2, 1590},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 582, 2, 1592},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 586, 2, 1594},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 590, 2, 1596},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 594, 2, 1598},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 598, 2, 1600},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 602, 2, 1602},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 606, 2, 1604},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 610, 2, 1606},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 614, 2, 1608},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 618, 4, 1610},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 622, 2, 1614},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 626, 2, 1616},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 630, 2, 1618},
- {"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 634, 4, 1620},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 635, 4, 1624},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 636, 2, 1628},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 637, 5, 1630},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 638, 2, 1635},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 639, 2, 1637},
- {"cvmx_gmx#_soft_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 643, 3, 1639},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 644, 3, 1642},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 645, 5, 1645},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 649, 2, 1650},
- {"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 653, 2, 1652},
- {"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 654, 2, 1654},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 655, 3, 1656},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 659, 2, 1659},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 663, 2, 1661},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 667, 2, 1663},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 671, 3, 1665},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 675, 2, 1668},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 679, 2, 1670},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 683, 2, 1672},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 687, 2, 1674},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 691, 2, 1676},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 695, 2, 1678},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 699, 2, 1680},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 703, 2, 1682},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 707, 2, 1684},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 711, 2, 1686},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 715, 2, 1688},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 719, 2, 1690},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 723, 2, 1692},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 727, 2, 1694},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 731, 2, 1696},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 735, 2, 1698},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 739, 2, 1700},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 740, 2, 1702},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 741, 2, 1704},
- {"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 742, 2, 1706},
- {"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 743, 2, 1708},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 744, 3, 1710},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 745, 9, 1713},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 746, 9, 1722},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 747, 2, 1731},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 748, 2, 1733},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 749, 6, 1735},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 2, 1741},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 751, 2, 1743},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 752, 2, 1745},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 753, 9, 1747},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 754, 3, 1756},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 755, 10, 1759},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 771, 2, 1769},
- {"cvmx_gpio_clk_qlm#" , CVMX_CSR_DB_TYPE_NCB, 64, 775, 3, 1771},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 777, 2, 1774},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 778, 2, 1776},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 779, 2, 1778},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 780, 2, 1780},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 781, 24, 1782},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 782, 8, 1806},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 783, 3, 1814},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 784, 3, 1817},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 785, 3, 1820},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 786, 5, 1823},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 787, 5, 1828},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 788, 1, 1833},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 789, 1, 1834},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 790, 7, 1835},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 791, 7, 1842},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 792, 3, 1849},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 793, 3, 1852},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 794, 3, 1855},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 5, 1858},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 796, 5, 1863},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 797, 1, 1868},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 798, 1, 1869},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 799, 3, 1870},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 800, 3, 1873},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 801, 3, 1876},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 3, 1879},
- {"cvmx_iob_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 4, 1882},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 804, 2, 1886},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 805, 2, 1888},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 806, 2, 1890},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 807, 19, 1892},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 808, 2, 1911},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 809, 1, 1913},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 810, 18, 1914},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 811, 13, 1932},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 812, 13, 1945},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 813, 2, 1958},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 814, 2, 1960},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 815, 2, 1962},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 816, 3, 1964},
- {"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 824, 3, 1967},
- {"cvmx_ipd_port#_bp_page_cnt3" , CVMX_CSR_DB_TYPE_NCB, 64, 828, 3, 1970},
- {"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 832, 2, 1973},
- {"cvmx_ipd_port_bp_counters3_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 836, 2, 1975},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 840, 2, 1977},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 848, 2, 1979},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 976, 1, 1981},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 979, 1, 1982},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 982, 6, 1983},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 983, 5, 1989},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 984, 6, 1994},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 985, 7, 2000},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 986, 2, 2007},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 994, 2, 2009},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 995, 3, 2011},
- {"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 996, 2, 2014},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 997, 5, 2016},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 1005, 3, 2021},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 1006, 4, 2024},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1007, 3, 2028},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 1008, 2, 2031},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1009, 2, 2033},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1010, 4, 2035},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1011, 3, 2039},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1012, 5, 2042},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1013, 5, 2047},
- {"cvmx_l2c_big_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1014, 4, 2052},
- {"cvmx_l2c_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 1015, 12, 2056},
- {"cvmx_l2c_bst_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 1016, 5, 2068},
- {"cvmx_l2c_bst_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1017, 5, 2073},
- {"cvmx_l2c_bst_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1018, 3, 2078},
- {"cvmx_l2c_cop0_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 1, 2081},
- {"cvmx_l2c_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2811, 14, 2082},
- {"cvmx_l2c_dut_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 2812, 4, 2096},
- {"cvmx_l2c_err_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 4348, 9, 2100},
- {"cvmx_l2c_err_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 4349, 9, 2109},
- {"cvmx_l2c_err_vbf#" , CVMX_CSR_DB_TYPE_RSL, 64, 4350, 6, 2118},
- {"cvmx_l2c_err_xmc" , CVMX_CSR_DB_TYPE_RSL, 64, 4351, 5, 2124},
- {"cvmx_l2c_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 4352, 9, 2129},
- {"cvmx_l2c_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 4353, 11, 2138},
- {"cvmx_l2c_ioc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4354, 1, 2149},
- {"cvmx_l2c_ior#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4355, 1, 2150},
- {"cvmx_l2c_qos_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 4356, 4, 2151},
- {"cvmx_l2c_qos_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 4357, 2, 2155},
- {"cvmx_l2c_qos_wgt" , CVMX_CSR_DB_TYPE_RSL, 64, 4363, 5, 2157},
- {"cvmx_l2c_rsc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4364, 1, 2162},
- {"cvmx_l2c_rsd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4365, 1, 2163},
- {"cvmx_l2c_tad#_ecc0" , CVMX_CSR_DB_TYPE_RSL, 64, 4366, 8, 2164},
- {"cvmx_l2c_tad#_ecc1" , CVMX_CSR_DB_TYPE_RSL, 64, 4367, 8, 2172},
- {"cvmx_l2c_tad#_ien" , CVMX_CSR_DB_TYPE_RSL, 64, 4368, 10, 2180},
- {"cvmx_l2c_tad#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4369, 10, 2190},
- {"cvmx_l2c_tad#_pfc0" , CVMX_CSR_DB_TYPE_RSL, 64, 4370, 1, 2200},
- {"cvmx_l2c_tad#_pfc1" , CVMX_CSR_DB_TYPE_RSL, 64, 4371, 1, 2201},
- {"cvmx_l2c_tad#_pfc2" , CVMX_CSR_DB_TYPE_RSL, 64, 4372, 1, 2202},
- {"cvmx_l2c_tad#_pfc3" , CVMX_CSR_DB_TYPE_RSL, 64, 4373, 1, 2203},
- {"cvmx_l2c_tad#_prf" , CVMX_CSR_DB_TYPE_RSL, 64, 4374, 5, 2204},
- {"cvmx_l2c_tad#_tag" , CVMX_CSR_DB_TYPE_RSL, 64, 4375, 9, 2209},
- {"cvmx_l2c_ver_id" , CVMX_CSR_DB_TYPE_RSL, 64, 4376, 1, 2218},
- {"cvmx_l2c_ver_iob" , CVMX_CSR_DB_TYPE_RSL, 64, 4377, 2, 2219},
- {"cvmx_l2c_ver_msc" , CVMX_CSR_DB_TYPE_RSL, 64, 4378, 3, 2221},
- {"cvmx_l2c_ver_pp" , CVMX_CSR_DB_TYPE_RSL, 64, 4379, 2, 2224},
- {"cvmx_l2c_virtid_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 4380, 4, 2226},
- {"cvmx_l2c_virtid_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 4381, 2, 2230},
- {"cvmx_l2c_vrt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4387, 6, 2232},
- {"cvmx_l2c_vrt_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 4388, 3, 2238},
- {"cvmx_l2c_wpar_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 5412, 2, 2241},
- {"cvmx_l2c_wpar_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 5413, 2, 2243},
- {"cvmx_l2c_xmc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 5419, 1, 2245},
- {"cvmx_l2c_xmc_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 5420, 4, 2246},
- {"cvmx_l2c_xmd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 5421, 1, 2250},
- {"cvmx_lmc#_char_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5422, 5, 2251},
- {"cvmx_lmc#_char_mask0" , CVMX_CSR_DB_TYPE_RSL, 64, 5423, 1, 2256},
- {"cvmx_lmc#_char_mask1" , CVMX_CSR_DB_TYPE_RSL, 64, 5424, 2, 2257},
- {"cvmx_lmc#_char_mask2" , CVMX_CSR_DB_TYPE_RSL, 64, 5425, 1, 2259},
- {"cvmx_lmc#_char_mask3" , CVMX_CSR_DB_TYPE_RSL, 64, 5426, 2, 2260},
- {"cvmx_lmc#_char_mask4" , CVMX_CSR_DB_TYPE_RSL, 64, 5427, 12, 2262},
- {"cvmx_lmc#_comp_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 5428, 11, 2274},
- {"cvmx_lmc#_config" , CVMX_CSR_DB_TYPE_RSL, 64, 5429, 21, 2285},
- {"cvmx_lmc#_control" , CVMX_CSR_DB_TYPE_RSL, 64, 5430, 20, 2306},
- {"cvmx_lmc#_dclk_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5431, 1, 2326},
- {"cvmx_lmc#_ddr_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5432, 11, 2327},
- {"cvmx_lmc#_dimm#_params" , CVMX_CSR_DB_TYPE_RSL, 64, 5433, 16, 2338},
- {"cvmx_lmc#_dimm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5435, 5, 2354},
- {"cvmx_lmc#_dll_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 5436, 6, 2359},
- {"cvmx_lmc#_dll_ctl3" , CVMX_CSR_DB_TYPE_RSL, 64, 5437, 11, 2365},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 5438, 4, 2376},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 5439, 5, 2380},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 5440, 6, 2385},
- {"cvmx_lmc#_ifb_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5441, 1, 2391},
- {"cvmx_lmc#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5442, 4, 2392},
- {"cvmx_lmc#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5443, 4, 2396},
- {"cvmx_lmc#_modereg_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 5444, 16, 2400},
- {"cvmx_lmc#_modereg_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 5445, 25, 2416},
- {"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 5446, 10, 2441},
- {"cvmx_lmc#_ops_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5447, 1, 2451},
- {"cvmx_lmc#_phy_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5448, 10, 2452},
- {"cvmx_lmc#_reset_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5449, 5, 2462},
- {"cvmx_lmc#_rlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5450, 10, 2467},
- {"cvmx_lmc#_rlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 5451, 1, 2477},
- {"cvmx_lmc#_rlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 5452, 11, 2478},
- {"cvmx_lmc#_rodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 5456, 8, 2489},
- {"cvmx_lmc#_slot_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 5457, 5, 2497},
- {"cvmx_lmc#_slot_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 5458, 5, 2502},
- {"cvmx_lmc#_slot_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 5459, 5, 2507},
- {"cvmx_lmc#_timing_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 5460, 12, 2512},
- {"cvmx_lmc#_timing_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 5461, 13, 2524},
- {"cvmx_lmc#_tro_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5462, 3, 2537},
- {"cvmx_lmc#_tro_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 5463, 2, 2540},
- {"cvmx_lmc#_wlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5464, 6, 2542},
- {"cvmx_lmc#_wlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 5465, 3, 2548},
- {"cvmx_lmc#_wlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 5466, 11, 2551},
- {"cvmx_lmc#_wodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 5470, 8, 2562},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 5471, 2, 2570},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 5472, 3, 2572},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 5473, 10, 2575},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 5475, 3, 2585},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 5477, 3, 2588},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 5479, 15, 2591},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 5481, 3, 2606},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5482, 3, 2609},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 5483, 3, 2612},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 5484, 5, 2615},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 5486, 1, 2620},
- {"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 5487, 9, 2621},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 5488, 13, 2630},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 5496, 13, 2643},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 5504, 6, 2656},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 5505, 1, 2662},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 5507, 2, 2663},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 5508, 2, 2665},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 5509, 12, 2667},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 5510, 18, 2679},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 5511, 4, 2697},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 5512, 1, 2701},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 5513, 7, 2702},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 5514, 3, 2709},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 5515, 8, 2712},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 5516, 7, 2720},
- {"cvmx_mio_fus_read_times" , CVMX_CSR_DB_TYPE_RSL, 64, 5517, 6, 2727},
- {"cvmx_mio_fus_repair_res0" , CVMX_CSR_DB_TYPE_RSL, 64, 5518, 5, 2733},
- {"cvmx_mio_fus_repair_res1" , CVMX_CSR_DB_TYPE_RSL, 64, 5519, 4, 2738},
- {"cvmx_mio_fus_repair_res2" , CVMX_CSR_DB_TYPE_RSL, 64, 5520, 2, 2742},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 5521, 4, 2744},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 5522, 2, 2748},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 5523, 2, 2750},
- {"cvmx_mio_gpio_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 5524, 3, 2752},
- {"cvmx_mio_ndf_dma_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 5525, 10, 2755},
- {"cvmx_mio_ndf_dma_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5526, 2, 2765},
- {"cvmx_mio_ndf_dma_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5527, 2, 2767},
- {"cvmx_mio_ptp_clock_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5528, 10, 2769},
- {"cvmx_mio_ptp_clock_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 5529, 2, 2779},
- {"cvmx_mio_ptp_clock_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 5530, 1, 2781},
- {"cvmx_mio_ptp_clock_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 5531, 2, 2782},
- {"cvmx_mio_ptp_evt_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5532, 1, 2784},
- {"cvmx_mio_ptp_timestamp" , CVMX_CSR_DB_TYPE_NCB, 64, 5533, 1, 2785},
- {"cvmx_mio_rst_boot" , CVMX_CSR_DB_TYPE_RSL, 64, 5534, 9, 2786},
- {"cvmx_mio_rst_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 5535, 5, 2795},
- {"cvmx_mio_rst_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 5536, 10, 2800},
- {"cvmx_mio_rst_delay" , CVMX_CSR_DB_TYPE_RSL, 64, 5538, 3, 2810},
- {"cvmx_mio_rst_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5539, 6, 2813},
- {"cvmx_mio_rst_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5540, 6, 2819},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5541, 13, 2825},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 5543, 12, 2838},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 5545, 3, 2850},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 5547, 3, 2853},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 5549, 2, 2856},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 5551, 2, 2858},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 5553, 2, 2860},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 5555, 7, 2862},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 5557, 2, 2869},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 5559, 7, 2871},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 5561, 4, 2878},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 5563, 8, 2882},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 5565, 9, 2890},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 5567, 7, 2899},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 5569, 9, 2906},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 5571, 2, 2915},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 5573, 2, 2917},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 5575, 4, 2919},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 5577, 2, 2923},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 5579, 2, 2925},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 5581, 2, 2927},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 5583, 4, 2929},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 5585, 2, 2933},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 5587, 2, 2935},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 5589, 2, 2937},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 5591, 2, 2939},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 5593, 2, 2941},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 5595, 2, 2943},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 5597, 6, 2945},
- {"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 5599, 7, 2951},
- {"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 5601, 9, 2958},
- {"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 5603, 9, 2967},
- {"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5605, 2, 2976},
- {"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 5607, 3, 2978},
- {"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 5609, 4, 2981},
- {"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 5611, 4, 2985},
- {"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 5613, 9, 2989},
- {"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5615, 2, 2998},
- {"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 5617, 2, 3000},
- {"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 5619, 4, 3002},
- {"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 5621, 4, 3006},
- {"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5623, 4, 3010},
- {"cvmx_mix#_tsctl" , CVMX_CSR_DB_TYPE_NCB, 64, 5625, 6, 3014},
- {"cvmx_mix#_tstamp" , CVMX_CSR_DB_TYPE_NCB, 64, 5627, 1, 3020},
- {"cvmx_ndf_bt_pg_info" , CVMX_CSR_DB_TYPE_NCB, 64, 5629, 4, 3021},
- {"cvmx_ndf_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 5630, 1, 3025},
- {"cvmx_ndf_drbell" , CVMX_CSR_DB_TYPE_NCB, 64, 5631, 2, 3026},
- {"cvmx_ndf_ecc_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5632, 3, 3028},
- {"cvmx_ndf_int" , CVMX_CSR_DB_TYPE_NCB, 64, 5633, 8, 3031},
- {"cvmx_ndf_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5634, 8, 3039},
- {"cvmx_ndf_misc" , CVMX_CSR_DB_TYPE_NCB, 64, 5635, 12, 3047},
- {"cvmx_ndf_st_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 5636, 8, 3059},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5637, 2, 3067},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5639, 24, 3069},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5641, 4, 3093},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5643, 5, 3097},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5645, 5, 3102},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5647, 2, 3107},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5649, 1, 3109},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5651, 1, 3110},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5653, 5, 3111},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5655, 2, 3116},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5657, 1, 3118},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5659, 1, 3119},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5661, 4, 3120},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5663, 2, 3124},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5665, 2, 3126},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5667, 1, 3128},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5669, 1, 3129},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5671, 2, 3130},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5673, 3, 3132},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5675, 2, 3135},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5677, 2, 3137},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5679, 4, 3139},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5681, 10, 3143},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5683, 12, 3153},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5685, 7, 3165},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5687, 2, 3172},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5689, 1, 3174},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5691, 2, 3175},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5693, 7, 3177},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5695, 11, 3184},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5697, 19, 3195},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5699, 11, 3214},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5701, 17, 3225},
- {"cvmx_pcieep#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5703, 12, 3242},
- {"cvmx_pcieep#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5705, 22, 3254},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5707, 3, 3276},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5709, 3, 3279},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5711, 4, 3282},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5713, 11, 3286},
- {"cvmx_pcieep#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5715, 1, 3297},
- {"cvmx_pcieep#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5717, 1, 3298},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5719, 3, 3299},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5721, 14, 3302},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5723, 14, 3316},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5725, 14, 3330},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5727, 9, 3344},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5729, 9, 3353},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5731, 6, 3362},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5733, 1, 3368},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5735, 1, 3369},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5737, 1, 3370},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5739, 1, 3371},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5741, 2, 3372},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5743, 1, 3374},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5745, 6, 3375},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5747, 6, 3381},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5749, 13, 3387},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5751, 5, 3400},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5753, 8, 3405},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5755, 19, 3413},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5757, 3, 3432},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5759, 1, 3435},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5761, 1, 3436},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5763, 3, 3437},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5765, 3, 3440},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5767, 3, 3443},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5769, 4, 3446},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5771, 4, 3450},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5773, 4, 3454},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5775, 7, 3458},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5777, 5, 3465},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5779, 5, 3470},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5781, 4, 3475},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5783, 4, 3479},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5785, 4, 3483},
- {"cvmx_pcieep#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5787, 7, 3487},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5789, 1, 3494},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5791, 1, 3495},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5793, 2, 3496},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5795, 24, 3498},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5797, 4, 3522},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5799, 5, 3526},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5801, 1, 3531},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5803, 1, 3532},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5805, 4, 3533},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5807, 17, 3537},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5809, 4, 3554},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5811, 6, 3558},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5813, 1, 3564},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5815, 1, 3565},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5817, 2, 3566},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5819, 2, 3568},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5821, 1, 3570},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5823, 15, 3571},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5825, 10, 3586},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5827, 12, 3596},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5829, 7, 3608},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5831, 2, 3615},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5833, 1, 3617},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5835, 2, 3618},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5837, 7, 3620},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5839, 11, 3627},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5841, 19, 3638},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5843, 11, 3657},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5845, 20, 3668},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5847, 12, 3688},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5849, 22, 3700},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5851, 8, 3722},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5853, 4, 3730},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5855, 3, 3734},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5857, 3, 3737},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5859, 4, 3740},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5861, 11, 3744},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5863, 1, 3755},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5865, 1, 3756},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5867, 3, 3757},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5869, 14, 3760},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5871, 14, 3774},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5873, 14, 3788},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5875, 9, 3802},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5877, 9, 3811},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5879, 6, 3820},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5881, 1, 3826},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5883, 1, 3827},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5885, 1, 3828},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5887, 1, 3829},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5889, 4, 3830},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5891, 9, 3834},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5893, 2, 3843},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5895, 2, 3845},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5897, 1, 3847},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5899, 6, 3848},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5901, 6, 3854},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5903, 13, 3860},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5905, 5, 3873},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5907, 8, 3878},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5909, 19, 3886},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5911, 3, 3905},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5913, 1, 3908},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5915, 1, 3909},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5917, 3, 3910},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5919, 3, 3913},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5921, 3, 3916},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5923, 4, 3919},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5925, 4, 3923},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5927, 4, 3927},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5929, 7, 3931},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5931, 5, 3938},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5933, 5, 3943},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5935, 4, 3948},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5937, 4, 3952},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5939, 4, 3956},
- {"cvmx_pcierc#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5941, 7, 3960},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5943, 1, 3967},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5945, 1, 3968},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5947, 9, 3969},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5951, 6, 3978},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5955, 9, 3984},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5959, 6, 3993},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5963, 14, 3999},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5967, 14, 4013},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 5971, 2, 4027},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5975, 4, 4029},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5979, 8, 4033},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5983, 13, 4041},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5987, 17, 4054},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5991, 7, 4071},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5995, 3, 4078},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5999, 8, 4081},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6003, 7, 4089},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6007, 4, 4096},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 6011, 5, 4100},
- {"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6015, 8, 4105},
- {"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6016, 2, 4113},
- {"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 6017, 5, 4115},
- {"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6018, 10, 4120},
- {"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6019, 2, 4130},
- {"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6020, 8, 4132},
- {"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6021, 8, 4140},
- {"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6022, 6, 4148},
- {"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6023, 5, 4154},
- {"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 6024, 5, 4159},
- {"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6025, 3, 4164},
- {"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6026, 6, 4167},
- {"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6027, 9, 4173},
- {"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 6028, 5, 4182},
- {"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6029, 10, 4187},
- {"cvmx_pem#_bar1_index#" , CVMX_CSR_DB_TYPE_RSL, 64, 6030, 5, 4197},
- {"cvmx_pem#_bar_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6062, 5, 4202},
- {"cvmx_pem#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6064, 9, 4207},
- {"cvmx_pem#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 6066, 11, 4216},
- {"cvmx_pem#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 6068, 2, 4227},
- {"cvmx_pem#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 6070, 2, 4229},
- {"cvmx_pem#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 6072, 2, 4231},
- {"cvmx_pem#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6074, 18, 4233},
- {"cvmx_pem#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 6076, 32, 4251},
- {"cvmx_pem#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 6078, 32, 4283},
- {"cvmx_pem#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6080, 5, 4315},
- {"cvmx_pem#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 6082, 15, 4320},
- {"cvmx_pem#_int_enb_int" , CVMX_CSR_DB_TYPE_RSL, 64, 6084, 15, 4335},
- {"cvmx_pem#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 6086, 15, 4350},
- {"cvmx_pem#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 6088, 2, 4365},
- {"cvmx_pem#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 6090, 2, 4367},
- {"cvmx_pem#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 6092, 2, 4369},
- {"cvmx_pem#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 6094, 2, 4371},
- {"cvmx_pem#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 6102, 2, 4373},
- {"cvmx_pem#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 6110, 8, 4375},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 6112, 5, 4383},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6113, 2, 4388},
- {"cvmx_pip_clken" , CVMX_CSR_DB_TYPE_RSL, 64, 6114, 2, 4390},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 6115, 4, 4392},
- {"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 6119, 16, 4396},
- {"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 6120, 16, 4412},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 6121, 3, 4428},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 6122, 8, 4431},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6123, 23, 4439},
- {"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6124, 6, 4462},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 6125, 14, 4468},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6126, 14, 4482},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 6127, 2, 4496},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 6128, 28, 4498},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 6144, 25, 4526},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 6160, 2, 4551},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 6224, 4, 4553},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 6232, 9, 4557},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 6240, 2, 4566},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 6241, 2, 4568},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6242, 2, 4570},
- {"cvmx_pip_stat10_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6254, 2, 4572},
- {"cvmx_pip_stat11_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6266, 2, 4574},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6278, 2, 4576},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6290, 2, 4578},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6302, 2, 4580},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6314, 2, 4582},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6326, 2, 4584},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6338, 2, 4586},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6350, 2, 4588},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6362, 2, 4590},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6374, 2, 4592},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6386, 2, 4594},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 6387, 2, 4596},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 6403, 2, 4598},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 6419, 2, 4600},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 6435, 2, 4602},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6499, 2, 4604},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 6500, 3, 4606},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 6501, 3, 4609},
- {"cvmx_pip_xstat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6502, 2, 4612},
- {"cvmx_pip_xstat10_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6506, 2, 4614},
- {"cvmx_pip_xstat11_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6510, 2, 4616},
- {"cvmx_pip_xstat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6514, 2, 4618},
- {"cvmx_pip_xstat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6518, 2, 4620},
- {"cvmx_pip_xstat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6522, 2, 4622},
- {"cvmx_pip_xstat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6526, 2, 4624},
- {"cvmx_pip_xstat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6530, 2, 4626},
- {"cvmx_pip_xstat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6534, 2, 4628},
- {"cvmx_pip_xstat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6538, 2, 4630},
- {"cvmx_pip_xstat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6542, 2, 4632},
- {"cvmx_pip_xstat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6546, 2, 4634},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 6550, 2, 4636},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 6551, 2, 4638},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6552, 4, 4640},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6553, 5, 4644},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 6554, 4, 4649},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 6555, 8, 4653},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 6556, 4, 4661},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 6557, 5, 4665},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 6558, 1, 4670},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6559, 5, 4671},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6560, 1, 4676},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 6561, 13, 4677},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 6562, 6, 4690},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 6563, 13, 4696},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 6564, 6, 4709},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 6565, 9, 4715},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 6566, 4, 4724},
- {"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 6567, 7, 4728},
- {"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6568, 5, 4735},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 6569, 5, 4740},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 6570, 4, 4745},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 6571, 9, 4749},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6572, 5, 4758},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 6573, 16, 4763},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 6574, 4, 4779},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6575, 1, 4783},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6576, 1, 4784},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6577, 1, 4785},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6578, 1, 4786},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 6579, 13, 4787},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 6580, 2, 4800},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 6581, 4, 4802},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 6582, 5, 4806},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 6583, 3, 4811},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6584, 4, 4814},
- {"cvmx_pko_reg_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 6585, 2, 4818},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 6586, 2, 4820},
- {"cvmx_pko_reg_queue_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 6587, 3, 4822},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 6588, 3, 4825},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 6589, 3, 4828},
- {"cvmx_pko_reg_timestamp" , CVMX_CSR_DB_TYPE_RSL, 64, 6590, 2, 4831},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 6591, 10, 4833},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6592, 2, 4843},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 6593, 13, 4845},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 6594, 3, 4858},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 6595, 2, 4861},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 6603, 2, 4863},
- {"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 6604, 2, 4865},
- {"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 6605, 2, 4867},
- {"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6606, 2, 4869},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 6614, 2, 4871},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 6615, 2, 4873},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 6616, 2, 4875},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 6617, 10, 4877},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 6623, 5, 4887},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6631, 10, 4892},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6639, 2, 4902},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6640, 2, 4904},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 6641, 2, 4906},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 6649, 3, 4908},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 6650, 6, 4911},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6666, 5, 4917},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6667, 7, 4922},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 6683, 2, 4929},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6699, 1, 4931},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6700, 1, 4932},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6701, 1, 4933},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 6702, 5, 4934},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 6703, 5, 4939},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6704, 4, 4944},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6705, 10, 4948},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6706, 1, 4958},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 6707, 3, 4959},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 6708, 7, 4962},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 6709, 2, 4969},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6710, 1, 4971},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6711, 1, 4972},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 6712, 1, 4973},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 6713, 18, 4974},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 6714, 3, 4992},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 6715, 2, 4995},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 6716, 3, 4997},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 6717, 7, 5000},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 6718, 2, 5007},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6719, 2, 5009},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 6720, 2, 5011},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 6721, 3, 5013},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6722, 3, 5016},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6723, 9, 5019},
- {"cvmx_rnm_eer_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 6724, 1, 5028},
- {"cvmx_rnm_eer_key" , CVMX_CSR_DB_TYPE_RSL, 64, 6725, 1, 5029},
- {"cvmx_rnm_serial_num" , CVMX_CSR_DB_TYPE_RSL, 64, 6726, 1, 5030},
- {"cvmx_sli_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6727, 25, 5031},
- {"cvmx_sli_ctl_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6728, 16, 5056},
- {"cvmx_sli_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6730, 4, 5072},
- {"cvmx_sli_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6731, 5, 5076},
- {"cvmx_sli_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6732, 3, 5081},
- {"cvmx_sli_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6733, 3, 5084},
- {"cvmx_sli_dma#_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6734, 2, 5087},
- {"cvmx_sli_dma#_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6736, 2, 5089},
- {"cvmx_sli_dma#_tim" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6738, 2, 5091},
- {"cvmx_sli_int_enb_ciu" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6740, 35, 5093},
- {"cvmx_sli_int_enb_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6741, 37, 5128},
- {"cvmx_sli_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6743, 37, 5165},
- {"cvmx_sli_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6744, 1, 5202},
- {"cvmx_sli_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6745, 1, 5203},
- {"cvmx_sli_mac_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6746, 13, 5204},
- {"cvmx_sli_mac_number" , CVMX_CSR_DB_TYPE_PEXP, 64, 6747, 2, 5217},
- {"cvmx_sli_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6748, 3, 5219},
- {"cvmx_sli_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6749, 9, 5222},
- {"cvmx_sli_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6765, 1, 5231},
- {"cvmx_sli_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6766, 1, 5232},
- {"cvmx_sli_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6767, 1, 5233},
- {"cvmx_sli_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6768, 1, 5234},
- {"cvmx_sli_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6769, 1, 5235},
- {"cvmx_sli_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6770, 1, 5236},
- {"cvmx_sli_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6771, 1, 5237},
- {"cvmx_sli_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6772, 1, 5238},
- {"cvmx_sli_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6773, 3, 5239},
- {"cvmx_sli_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6774, 1, 5242},
- {"cvmx_sli_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6775, 1, 5243},
- {"cvmx_sli_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6776, 1, 5244},
- {"cvmx_sli_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6777, 1, 5245},
- {"cvmx_sli_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6778, 1, 5246},
- {"cvmx_sli_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6779, 1, 5247},
- {"cvmx_sli_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6780, 1, 5248},
- {"cvmx_sli_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6781, 1, 5249},
- {"cvmx_sli_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6782, 3, 5250},
- {"cvmx_sli_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6783, 2, 5253},
- {"cvmx_sli_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6784, 3, 5255},
- {"cvmx_sli_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6785, 3, 5258},
- {"cvmx_sli_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6786, 3, 5261},
- {"cvmx_sli_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6787, 3, 5264},
- {"cvmx_sli_pkt#_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6819, 2, 5267},
- {"cvmx_sli_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6851, 2, 5269},
- {"cvmx_sli_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6883, 2, 5271},
- {"cvmx_sli_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6915, 5, 5273},
- {"cvmx_sli_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6947, 21, 5278},
- {"cvmx_sli_pkt#_out_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6979, 3, 5299},
- {"cvmx_sli_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7011, 2, 5302},
- {"cvmx_sli_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7043, 2, 5304},
- {"cvmx_sli_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7075, 2, 5306},
- {"cvmx_sli_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7107, 2, 5308},
- {"cvmx_sli_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7108, 2, 5310},
- {"cvmx_sli_pkt_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7109, 3, 5312},
- {"cvmx_sli_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7110, 1, 5315},
- {"cvmx_sli_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7111, 2, 5316},
- {"cvmx_sli_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7112, 2, 5318},
- {"cvmx_sli_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7113, 2, 5320},
- {"cvmx_sli_pkt_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7114, 2, 5322},
- {"cvmx_sli_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7115, 2, 5324},
- {"cvmx_sli_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7147, 2, 5326},
- {"cvmx_sli_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7148, 1, 5328},
- {"cvmx_sli_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7149, 10, 5329},
- {"cvmx_sli_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7150, 2, 5339},
- {"cvmx_sli_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7151, 1, 5341},
- {"cvmx_sli_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7152, 2, 5342},
- {"cvmx_sli_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7153, 3, 5344},
- {"cvmx_sli_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7154, 2, 5347},
- {"cvmx_sli_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7155, 2, 5349},
- {"cvmx_sli_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7156, 2, 5351},
- {"cvmx_sli_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7157, 2, 5353},
- {"cvmx_sli_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7158, 1, 5355},
- {"cvmx_sli_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7159, 2, 5356},
- {"cvmx_sli_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7160, 1, 5358},
- {"cvmx_sli_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7161, 2, 5359},
- {"cvmx_sli_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7162, 2, 5361},
- {"cvmx_sli_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7163, 2, 5363},
- {"cvmx_sli_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7164, 2, 5365},
- {"cvmx_sli_s2m_port#_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7165, 4, 5367},
- {"cvmx_sli_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7167, 1, 5371},
- {"cvmx_sli_scratch_2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7168, 1, 5372},
- {"cvmx_sli_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7169, 4, 5373},
- {"cvmx_sli_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7170, 8, 5377},
- {"cvmx_sli_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7171, 5, 5385},
- {"cvmx_sli_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 7172, 4, 5390},
- {"cvmx_sli_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 7173, 1, 5394},
- {"cvmx_sli_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 7174, 4, 5395},
- {"cvmx_sli_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 7175, 1, 5399},
- {"cvmx_sli_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 7176, 2, 5400},
- {"cvmx_sli_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7177, 2, 5402},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 7178, 10, 5404},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7180, 6, 5414},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 7182, 2, 5420},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7184, 4, 5422},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7186, 4, 5426},
- {"cvmx_smi_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7188, 4, 5430},
- {"cvmx_srio#_acc_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7189, 4, 5434},
- {"cvmx_srio#_asmbly_id" , CVMX_CSR_DB_TYPE_RSL, 64, 7191, 3, 5438},
- {"cvmx_srio#_asmbly_info" , CVMX_CSR_DB_TYPE_RSL, 64, 7193, 3, 5441},
- {"cvmx_srio#_bell_resp_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7195, 5, 5444},
- {"cvmx_srio#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7197, 19, 5449},
- {"cvmx_srio#_imsg_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7199, 14, 5468},
- {"cvmx_srio#_imsg_inst_hdr#" , CVMX_CSR_DB_TYPE_RSL, 64, 7201, 14, 5482},
- {"cvmx_srio#_imsg_qos_grp#" , CVMX_CSR_DB_TYPE_RSL, 64, 7205, 24, 5496},
- {"cvmx_srio#_imsg_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 7269, 24, 5520},
- {"cvmx_srio#_imsg_vport_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 7317, 13, 5544},
- {"cvmx_srio#_int2_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 7319, 2, 5557},
- {"cvmx_srio#_int2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7321, 4, 5559},
- {"cvmx_srio#_int_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 7323, 28, 5563},
- {"cvmx_srio#_int_info0" , CVMX_CSR_DB_TYPE_RSL, 64, 7325, 9, 5591},
- {"cvmx_srio#_int_info1" , CVMX_CSR_DB_TYPE_RSL, 64, 7327, 1, 5600},
- {"cvmx_srio#_int_info2" , CVMX_CSR_DB_TYPE_RSL, 64, 7329, 11, 5601},
- {"cvmx_srio#_int_info3" , CVMX_CSR_DB_TYPE_RSL, 64, 7331, 5, 5612},
- {"cvmx_srio#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7333, 30, 5617},
- {"cvmx_srio#_ip_feature" , CVMX_CSR_DB_TYPE_RSL, 64, 7335, 9, 5647},
- {"cvmx_srio#_mac_buffers" , CVMX_CSR_DB_TYPE_RSL, 64, 7337, 10, 5656},
- {"cvmx_srio#_maint_op" , CVMX_CSR_DB_TYPE_RSL, 64, 7339, 6, 5666},
- {"cvmx_srio#_maint_rd_data" , CVMX_CSR_DB_TYPE_RSL, 64, 7341, 3, 5672},
- {"cvmx_srio#_mce_tx_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7343, 2, 5675},
- {"cvmx_srio#_mem_op_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7345, 8, 5677},
- {"cvmx_srio#_omsg_ctrl#" , CVMX_CSR_DB_TYPE_RSL, 64, 7347, 11, 5685},
- {"cvmx_srio#_omsg_done_counts#", CVMX_CSR_DB_TYPE_RSL, 64, 7351, 3, 5696},
- {"cvmx_srio#_omsg_fmp_mr#" , CVMX_CSR_DB_TYPE_RSL, 64, 7355, 16, 5699},
- {"cvmx_srio#_omsg_nmp_mr#" , CVMX_CSR_DB_TYPE_RSL, 64, 7359, 16, 5715},
- {"cvmx_srio#_omsg_port#" , CVMX_CSR_DB_TYPE_RSL, 64, 7363, 4, 5731},
- {"cvmx_srio#_omsg_silo_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 7367, 2, 5735},
- {"cvmx_srio#_omsg_sp_mr#" , CVMX_CSR_DB_TYPE_RSL, 64, 7369, 17, 5737},
- {"cvmx_srio#_prio#_in_use" , CVMX_CSR_DB_TYPE_RSL, 64, 7373, 3, 5754},
- {"cvmx_srio#_rx_bell" , CVMX_CSR_DB_TYPE_RSL, 64, 7381, 9, 5757},
- {"cvmx_srio#_rx_bell_seq" , CVMX_CSR_DB_TYPE_RSL, 64, 7383, 3, 5766},
- {"cvmx_srio#_rx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7385, 9, 5769},
- {"cvmx_srio#_s2m_type#" , CVMX_CSR_DB_TYPE_RSL, 64, 7387, 11, 5778},
- {"cvmx_srio#_seq" , CVMX_CSR_DB_TYPE_RSL, 64, 7419, 2, 5789},
- {"cvmx_srio#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7421, 3, 5791},
- {"cvmx_srio#_tag_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7423, 6, 5794},
- {"cvmx_srio#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 7425, 6, 5800},
- {"cvmx_srio#_tx_bell" , CVMX_CSR_DB_TYPE_RSL, 64, 7427, 10, 5806},
- {"cvmx_srio#_tx_bell_info" , CVMX_CSR_DB_TYPE_RSL, 64, 7429, 11, 5816},
- {"cvmx_srio#_tx_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 7431, 12, 5827},
- {"cvmx_srio#_tx_emphasis" , CVMX_CSR_DB_TYPE_RSL, 64, 7433, 2, 5839},
- {"cvmx_srio#_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7435, 5, 5841},
- {"cvmx_srio#_wr_done_counts" , CVMX_CSR_DB_TYPE_RSL, 64, 7437, 3, 5846},
- {"cvmx_sriomaint#_asmbly_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7439, 2, 5849},
- {"cvmx_sriomaint#_asmbly_info" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7441, 2, 5851},
- {"cvmx_sriomaint#_bar1_idx#" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7443, 7, 5853},
- {"cvmx_sriomaint#_bell_status" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7475, 2, 5860},
- {"cvmx_sriomaint#_comp_tag" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7477, 1, 5862},
- {"cvmx_sriomaint#_core_enables", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7479, 6, 5863},
- {"cvmx_sriomaint#_dev_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7481, 2, 5869},
- {"cvmx_sriomaint#_dev_rev" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7483, 2, 5871},
- {"cvmx_sriomaint#_dst_ops" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7485, 26, 5873},
- {"cvmx_sriomaint#_erb_attr_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7487, 5, 5899},
- {"cvmx_sriomaint#_erb_err_det" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7489, 17, 5904},
- {"cvmx_sriomaint#_erb_err_rate", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7491, 5, 5921},
- {"cvmx_sriomaint#_erb_err_rate_en", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7493, 17, 5926},
- {"cvmx_sriomaint#_erb_err_rate_thr", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7495, 3, 5943},
- {"cvmx_sriomaint#_erb_hdr" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7497, 2, 5946},
- {"cvmx_sriomaint#_erb_lt_addr_capt_h", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7499, 1, 5948},
- {"cvmx_sriomaint#_erb_lt_addr_capt_l", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7501, 3, 5949},
- {"cvmx_sriomaint#_erb_lt_ctrl_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7503, 9, 5952},
- {"cvmx_sriomaint#_erb_lt_dev_id", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7505, 4, 5961},
- {"cvmx_sriomaint#_erb_lt_dev_id_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7507, 4, 5965},
- {"cvmx_sriomaint#_erb_lt_err_det", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7509, 12, 5969},
- {"cvmx_sriomaint#_erb_lt_err_en", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7511, 12, 5981},
- {"cvmx_sriomaint#_erb_pack_capt_1", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7513, 1, 5993},
- {"cvmx_sriomaint#_erb_pack_capt_2", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7515, 1, 5994},
- {"cvmx_sriomaint#_erb_pack_capt_3", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7517, 1, 5995},
- {"cvmx_sriomaint#_erb_pack_sym_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7519, 1, 5996},
- {"cvmx_sriomaint#_hb_dev_id_lock", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7521, 2, 5997},
- {"cvmx_sriomaint#_ir_buffer_config", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7523, 7, 5999},
- {"cvmx_sriomaint#_ir_buffer_config2", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7525, 8, 6006},
- {"cvmx_sriomaint#_ir_pd_phy_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7527, 1, 6014},
- {"cvmx_sriomaint#_ir_pd_phy_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7529, 9, 6015},
- {"cvmx_sriomaint#_ir_pi_phy_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7531, 5, 6024},
- {"cvmx_sriomaint#_ir_pi_phy_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7533, 4, 6029},
- {"cvmx_sriomaint#_ir_sp_rx_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7535, 2, 6033},
- {"cvmx_sriomaint#_ir_sp_rx_data", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7537, 1, 6035},
- {"cvmx_sriomaint#_ir_sp_rx_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7539, 5, 6036},
- {"cvmx_sriomaint#_ir_sp_tx_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7541, 2, 6041},
- {"cvmx_sriomaint#_ir_sp_tx_data", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7543, 1, 6043},
- {"cvmx_sriomaint#_ir_sp_tx_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7545, 5, 6044},
- {"cvmx_sriomaint#_lane_#_status_0", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7547, 15, 6049},
- {"cvmx_sriomaint#_lcs_ba0" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7555, 2, 6064},
- {"cvmx_sriomaint#_lcs_ba1" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7557, 2, 6066},
- {"cvmx_sriomaint#_m2s_bar0_start0", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7559, 2, 6068},
- {"cvmx_sriomaint#_m2s_bar0_start1", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7561, 4, 6070},
- {"cvmx_sriomaint#_m2s_bar1_start0", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7563, 2, 6074},
- {"cvmx_sriomaint#_m2s_bar1_start1", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7565, 5, 6076},
- {"cvmx_sriomaint#_m2s_bar2_start", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7567, 7, 6081},
- {"cvmx_sriomaint#_mac_ctrl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7569, 6, 6088},
- {"cvmx_sriomaint#_pe_feat" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7571, 11, 6094},
- {"cvmx_sriomaint#_pe_llc" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7573, 2, 6105},
- {"cvmx_sriomaint#_port_0_ctl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7575, 18, 6107},
- {"cvmx_sriomaint#_port_0_ctl2" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7577, 16, 6125},
- {"cvmx_sriomaint#_port_0_err_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7579, 20, 6141},
- {"cvmx_sriomaint#_port_0_link_req", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7581, 2, 6161},
- {"cvmx_sriomaint#_port_0_link_resp", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7583, 4, 6163},
- {"cvmx_sriomaint#_port_0_local_ackid", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7585, 6, 6167},
- {"cvmx_sriomaint#_port_gen_ctl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7587, 4, 6173},
- {"cvmx_sriomaint#_port_lt_ctl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7589, 2, 6177},
- {"cvmx_sriomaint#_port_mbh0" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7591, 2, 6179},
- {"cvmx_sriomaint#_port_rt_ctl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7593, 2, 6181},
- {"cvmx_sriomaint#_port_ttl_ctl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7595, 2, 6183},
- {"cvmx_sriomaint#_pri_dev_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7597, 3, 6185},
- {"cvmx_sriomaint#_sec_dev_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7599, 3, 6188},
- {"cvmx_sriomaint#_sec_dev_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7601, 3, 6191},
- {"cvmx_sriomaint#_serial_lane_hdr", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7603, 2, 6194},
- {"cvmx_sriomaint#_src_ops" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7605, 26, 6196},
- {"cvmx_sriomaint#_tx_drop" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 7607, 3, 6222},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 7609, 6, 6225},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 7610, 3, 6231},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 7611, 5, 6234},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 7612, 4, 6239},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 7613, 6, 6243},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 7614, 4, 6249},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 7615, 2, 6253},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 7616, 4, 6255},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 7617, 2, 6259},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 7618, 3, 6261},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7619, 2, 6264},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7620, 14, 6266},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 7621, 3, 6280},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 7622, 5, 6283},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7623, 2, 6288},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7624, 2, 6290},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7625, 57, 6292},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7626, 20, 6349},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7627, 7, 6369},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7628, 5, 6376},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7629, 1, 6381},
- {"cvmx_tra#_read_dat_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 7630, 2, 6382},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7631, 2, 6384},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7632, 2, 6386},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7633, 57, 6388},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7634, 20, 6445},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7635, 7, 6465},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7636, 2, 6472},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7637, 2, 6474},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7638, 57, 6476},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7639, 20, 6533},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7640, 7, 6553},
- {"cvmx_uahc#_ehci_asynclistaddr", CVMX_CSR_DB_TYPE_NCB, 32, 7641, 2, 6560},
- {"cvmx_uahc#_ehci_configflag" , CVMX_CSR_DB_TYPE_NCB, 32, 7642, 2, 6562},
- {"cvmx_uahc#_ehci_ctrldssegment", CVMX_CSR_DB_TYPE_NCB, 32, 7643, 1, 6564},
- {"cvmx_uahc#_ehci_frindex" , CVMX_CSR_DB_TYPE_NCB, 32, 7644, 2, 6565},
- {"cvmx_uahc#_ehci_hccapbase" , CVMX_CSR_DB_TYPE_NCB, 32, 7645, 3, 6567},
- {"cvmx_uahc#_ehci_hccparams" , CVMX_CSR_DB_TYPE_NCB, 32, 7646, 7, 6570},
- {"cvmx_uahc#_ehci_hcsparams" , CVMX_CSR_DB_TYPE_NCB, 32, 7647, 10, 6577},
- {"cvmx_uahc#_ehci_insnreg00" , CVMX_CSR_DB_TYPE_NCB, 32, 7648, 3, 6587},
- {"cvmx_uahc#_ehci_insnreg03" , CVMX_CSR_DB_TYPE_NCB, 32, 7649, 5, 6590},
- {"cvmx_uahc#_ehci_insnreg04" , CVMX_CSR_DB_TYPE_NCB, 32, 7650, 7, 6595},
- {"cvmx_uahc#_ehci_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 7651, 2, 6602},
- {"cvmx_uahc#_ehci_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 7652, 1, 6604},
- {"cvmx_uahc#_ehci_periodiclistbase", CVMX_CSR_DB_TYPE_NCB, 32, 7653, 2, 6605},
- {"cvmx_uahc#_ehci_portsc#" , CVMX_CSR_DB_TYPE_NCB, 32, 7654, 19, 6607},
- {"cvmx_uahc#_ehci_usbcmd" , CVMX_CSR_DB_TYPE_NCB, 32, 7656, 13, 6626},
- {"cvmx_uahc#_ehci_usbintr" , CVMX_CSR_DB_TYPE_NCB, 32, 7657, 7, 6639},
- {"cvmx_uahc#_ehci_usbsts" , CVMX_CSR_DB_TYPE_NCB, 32, 7658, 12, 6646},
- {"cvmx_uahc#_ohci0_hcbulkcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7659, 2, 6658},
- {"cvmx_uahc#_ohci0_hcbulkheaded", CVMX_CSR_DB_TYPE_NCB, 32, 7660, 2, 6660},
- {"cvmx_uahc#_ohci0_hccommandstatus", CVMX_CSR_DB_TYPE_NCB, 32, 7661, 7, 6662},
- {"cvmx_uahc#_ohci0_hccontrol" , CVMX_CSR_DB_TYPE_NCB, 32, 7662, 10, 6669},
- {"cvmx_uahc#_ohci0_hccontrolcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7663, 2, 6679},
- {"cvmx_uahc#_ohci0_hccontrolheaded", CVMX_CSR_DB_TYPE_NCB, 32, 7664, 2, 6681},
- {"cvmx_uahc#_ohci0_hcdonehead" , CVMX_CSR_DB_TYPE_NCB, 32, 7665, 2, 6683},
- {"cvmx_uahc#_ohci0_hcfminterval", CVMX_CSR_DB_TYPE_NCB, 32, 7666, 4, 6685},
- {"cvmx_uahc#_ohci0_hcfmnumber" , CVMX_CSR_DB_TYPE_NCB, 32, 7667, 2, 6689},
- {"cvmx_uahc#_ohci0_hcfmremaining", CVMX_CSR_DB_TYPE_NCB, 32, 7668, 3, 6691},
- {"cvmx_uahc#_ohci0_hchcca" , CVMX_CSR_DB_TYPE_NCB, 32, 7669, 2, 6694},
- {"cvmx_uahc#_ohci0_hcinterruptdisable", CVMX_CSR_DB_TYPE_NCB, 32, 7670, 10, 6696},
- {"cvmx_uahc#_ohci0_hcinterruptenable", CVMX_CSR_DB_TYPE_NCB, 32, 7671, 10, 6706},
- {"cvmx_uahc#_ohci0_hcinterruptstatus", CVMX_CSR_DB_TYPE_NCB, 32, 7672, 10, 6716},
- {"cvmx_uahc#_ohci0_hclsthreshold", CVMX_CSR_DB_TYPE_NCB, 32, 7673, 2, 6726},
- {"cvmx_uahc#_ohci0_hcperiodcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7674, 2, 6728},
- {"cvmx_uahc#_ohci0_hcperiodicstart", CVMX_CSR_DB_TYPE_NCB, 32, 7675, 2, 6730},
- {"cvmx_uahc#_ohci0_hcrevision" , CVMX_CSR_DB_TYPE_NCB, 32, 7676, 2, 6732},
- {"cvmx_uahc#_ohci0_hcrhdescriptora", CVMX_CSR_DB_TYPE_NCB, 32, 7677, 8, 6734},
- {"cvmx_uahc#_ohci0_hcrhdescriptorb", CVMX_CSR_DB_TYPE_NCB, 32, 7678, 2, 6742},
- {"cvmx_uahc#_ohci0_hcrhportstatus#", CVMX_CSR_DB_TYPE_NCB, 32, 7679, 15, 6744},
- {"cvmx_uahc#_ohci0_hcrhstatus" , CVMX_CSR_DB_TYPE_NCB, 32, 7681, 8, 6759},
- {"cvmx_uahc#_ohci0_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 7682, 2, 6767},
- {"cvmx_uahc#_ohci0_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 7683, 1, 6769},
- {"cvmx_uctl#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7684, 7, 6770},
- {"cvmx_uctl#_clk_rst_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7685, 21, 6777},
- {"cvmx_uctl#_ehci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7686, 12, 6798},
- {"cvmx_uctl#_ehci_fla" , CVMX_CSR_DB_TYPE_RSL, 64, 7687, 2, 6810},
- {"cvmx_uctl#_erto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7688, 3, 6812},
- {"cvmx_uctl#_if_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 7689, 2, 6815},
- {"cvmx_uctl#_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 7690, 9, 6817},
- {"cvmx_uctl#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7691, 9, 6826},
- {"cvmx_uctl#_ohci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7692, 11, 6835},
- {"cvmx_uctl#_orto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7693, 3, 6846},
- {"cvmx_uctl#_ppaf_wm" , CVMX_CSR_DB_TYPE_RSL, 64, 7694, 2, 6849},
- {"cvmx_uctl#_uphy_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7695, 11, 6851},
- {"cvmx_uctl#_uphy_port#_ctl_status", CVMX_CSR_DB_TYPE_RSL, 64, 7696, 20, 6862},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 7698, 3, 6882},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 7699, 5, 6885},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7700, 3, 6890},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 7701, 6, 6893},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 7702, 2, 6899},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 7703, 2, 6901},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 7704, 2, 6903},
- {"cvmx_zip_throttle" , CVMX_CSR_DB_TYPE_RSL, 64, 7705, 2, 6905},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn63xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"AGL_GMX_BAD_REG" , 0x11800e0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"AGL_GMX_BIST" , 0x11800e0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"AGL_GMX_PRT0_CFG" , 0x11800e0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_PRT1_CFG" , 0x11800e0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_RX0_ADR_CAM0" , 0x11800e0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_RX1_ADR_CAM0" , 0x11800e0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_RX0_ADR_CAM1" , 0x11800e0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX1_ADR_CAM1" , 0x11800e0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX0_ADR_CAM2" , 0x11800e0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX1_ADR_CAM2" , 0x11800e0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX0_ADR_CAM3" , 0x11800e0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX1_ADR_CAM3" , 0x11800e0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX0_ADR_CAM4" , 0x11800e00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX1_ADR_CAM4" , 0x11800e00009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX0_ADR_CAM5" , 0x11800e00001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX1_ADR_CAM5" , 0x11800e00009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800e0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX1_ADR_CAM_EN" , 0x11800e0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX0_ADR_CTL" , 0x11800e0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX1_ADR_CTL" , 0x11800e0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX0_DECISION" , 0x11800e0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX1_DECISION" , 0x11800e0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX0_FRM_CHK" , 0x11800e0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX1_FRM_CHK" , 0x11800e0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX0_FRM_CTL" , 0x11800e0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX1_FRM_CTL" , 0x11800e0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX0_FRM_MAX" , 0x11800e0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX1_FRM_MAX" , 0x11800e0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX0_FRM_MIN" , 0x11800e0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX1_FRM_MIN" , 0x11800e0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX0_IFG" , 0x11800e0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX1_IFG" , 0x11800e0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX0_INT_EN" , 0x11800e0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX1_INT_EN" , 0x11800e0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX0_INT_REG" , 0x11800e0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX1_INT_REG" , 0x11800e0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX0_JABBER" , 0x11800e0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX1_JABBER" , 0x11800e0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800e0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX1_PAUSE_DROP_TIME" , 0x11800e0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX0_RX_INBND" , 0x11800e0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX1_RX_INBND" , 0x11800e0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX0_STATS_CTL" , 0x11800e0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX1_STATS_CTL" , 0x11800e0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX0_STATS_OCTS" , 0x11800e0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX1_STATS_OCTS" , 0x11800e0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800e0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX1_STATS_OCTS_CTL" , 0x11800e0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800e00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX1_STATS_OCTS_DMAC" , 0x11800e00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800e00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX1_STATS_OCTS_DRP" , 0x11800e00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX0_STATS_PKTS" , 0x11800e0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX1_STATS_PKTS" , 0x11800e0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800e00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX1_STATS_PKTS_BAD" , 0x11800e00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800e0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX1_STATS_PKTS_CTL" , 0x11800e0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800e00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX1_STATS_PKTS_DMAC" , 0x11800e00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800e00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX1_STATS_PKTS_DRP" , 0x11800e00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX0_UDD_SKP" , 0x11800e0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX1_UDD_SKP" , 0x11800e0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX_BP_DROP0" , 0x11800e0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_DROP1" , 0x11800e0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_OFF0" , 0x11800e0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_OFF1" , 0x11800e0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_ON0" , 0x11800e0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_BP_ON1" , 0x11800e0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_PRT_INFO" , 0x11800e00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_TX_STATUS" , 0x11800e00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"AGL_GMX_SMAC0" , 0x11800e0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_SMAC1" , 0x11800e0000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_STAT_BP" , 0x11800e0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_TX0_APPEND" , 0x11800e0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX1_APPEND" , 0x11800e0000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX0_CLK" , 0x11800e0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX1_CLK" , 0x11800e0000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX0_CTL" , 0x11800e0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX1_CTL" , 0x11800e0000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX0_MIN_PKT" , 0x11800e0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX1_MIN_PKT" , 0x11800e0000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800e0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX1_PAUSE_PKT_INTERVAL", 0x11800e0000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800e0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX1_PAUSE_PKT_TIME" , 0x11800e0000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800e0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX1_PAUSE_TOGO" , 0x11800e0000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800e0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX1_PAUSE_ZERO" , 0x11800e0000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800e0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX1_SOFT_PAUSE" , 0x11800e0000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX0_STAT0" , 0x11800e0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX1_STAT0" , 0x11800e0000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX0_STAT1" , 0x11800e0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX1_STAT1" , 0x11800e0000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX0_STAT2" , 0x11800e0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX1_STAT2" , 0x11800e0000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX0_STAT3" , 0x11800e0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX1_STAT3" , 0x11800e0000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX0_STAT4" , 0x11800e00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX1_STAT4" , 0x11800e0000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX0_STAT5" , 0x11800e00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX1_STAT5" , 0x11800e0000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX0_STAT6" , 0x11800e00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX1_STAT6" , 0x11800e0000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX0_STAT7" , 0x11800e00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX1_STAT7" , 0x11800e0000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX0_STAT8" , 0x11800e00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX1_STAT8" , 0x11800e0000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX0_STAT9" , 0x11800e00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX1_STAT9" , 0x11800e0000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX0_STATS_CTL" , 0x11800e0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX1_STATS_CTL" , 0x11800e0000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX0_THRESH" , 0x11800e0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX1_THRESH" , 0x11800e0000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX_BP" , 0x11800e00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"AGL_GMX_TX_COL_ATTEMPT" , 0x11800e0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"AGL_GMX_TX_IFG" , 0x11800e0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"AGL_GMX_TX_INT_EN" , 0x11800e0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"AGL_GMX_TX_INT_REG" , 0x11800e0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"AGL_GMX_TX_JAM" , 0x11800e0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"AGL_GMX_TX_LFSR" , 0x11800e00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"AGL_GMX_TX_OVR_BP" , 0x11800e00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800e00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800e00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"AGL_PRT0_CTL" , 0x11800e0002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"AGL_PRT1_CTL" , 0x11800e0002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU_BLOCK_INT" , 0x10700000007c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT10_EN0" , 0x10700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT11_EN0" , 0x10700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT33_EN0" , 0x1070000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT8_EN0_W1C" , 0x1070000002280ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT9_EN0_W1C" , 0x1070000002290ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT10_EN0_W1C" , 0x10700000022a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT11_EN0_W1C" , 0x10700000022b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT33_EN0_W1C" , 0x1070000002410ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT8_EN0_W1S" , 0x1070000006280ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT9_EN0_W1S" , 0x1070000006290ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT10_EN0_W1S" , 0x10700000062a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT11_EN0_W1S" , 0x10700000062b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT33_EN0_W1S" , 0x1070000006410ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT10_EN1" , 0x10700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT11_EN1" , 0x10700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT33_EN1" , 0x1070000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT8_EN1_W1C" , 0x1070000002288ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT9_EN1_W1C" , 0x1070000002298ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT10_EN1_W1C" , 0x10700000022a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT11_EN1_W1C" , 0x10700000022b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT33_EN1_W1C" , 0x1070000002418ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT8_EN1_W1S" , 0x1070000006288ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT9_EN1_W1S" , 0x1070000006298ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT10_EN1_W1S" , 0x10700000062a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT11_EN1_W1S" , 0x10700000062b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT33_EN1_W1S" , 0x1070000006418ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT4_EN4_0" , 0x1070000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT5_EN4_0" , 0x1070000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_INT0_EN4_0_W1C" , 0x1070000002c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT1_EN4_0_W1C" , 0x1070000002c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT2_EN4_0_W1C" , 0x1070000002ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT3_EN4_0_W1C" , 0x1070000002cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT4_EN4_0_W1C" , 0x1070000002cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT5_EN4_0_W1C" , 0x1070000002cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_INT0_EN4_0_W1S" , 0x1070000006c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT1_EN4_0_W1S" , 0x1070000006c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT2_EN4_0_W1S" , 0x1070000006ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT3_EN4_0_W1S" , 0x1070000006cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT4_EN4_0_W1S" , 0x1070000006cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT5_EN4_0_W1S" , 0x1070000006cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT4_EN4_1" , 0x1070000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT5_EN4_1" , 0x1070000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_INT0_EN4_1_W1C" , 0x1070000002c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT1_EN4_1_W1C" , 0x1070000002c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT2_EN4_1_W1C" , 0x1070000002ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT3_EN4_1_W1C" , 0x1070000002cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT4_EN4_1_W1C" , 0x1070000002cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT5_EN4_1_W1C" , 0x1070000002cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_INT0_EN4_1_W1S" , 0x1070000006c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT1_EN4_1_W1S" , 0x1070000006c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT2_EN4_1_W1S" , 0x1070000006ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT3_EN4_1_W1S" , 0x1070000006cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT4_EN4_1_W1S" , 0x1070000006cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT5_EN4_1_W1S" , 0x1070000006cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT4_SUM4" , 0x1070000000c20ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT5_SUM4" , 0x1070000000c28ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT33_SUM0" , 0x1070000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT_DBG_SEL" , 0x10700000007d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_CLR4" , 0x10700000006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_CLR5" , 0x10700000006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_PP_POKE4" , 0x10700000005a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_PP_POKE5" , 0x10700000005a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_QLM0" , 0x1070000000780ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_QLM1" , 0x1070000000788ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_QLM2" , 0x1070000000790ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"DFA_BIST0" , 0x11800370007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
- {"DFA_BIST1" , 0x11800370007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
- {"DFA_CONFIG" , 0x1180037000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
- {"DFA_CONTROL" , 0x1180037000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"DFA_DEBUG0" , 0x1180037000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
- {"DFA_DEBUG1" , 0x1180037000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
- {"DFA_DEBUG2" , 0x1180037000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
- {"DFA_DEBUG3" , 0x1180037000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"DFA_DTCFADR" , 0x1180037000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
- {"DFA_ERROR" , 0x1180037000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
- {"DFA_INTMSK" , 0x1180037000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
- {"DFA_MEMHIDAT" , 0x1370700000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"DFA_PFC0_CNT" , 0x1180037000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
- {"DFA_PFC0_CTL" , 0x1180037000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
- {"DFA_PFC1_CNT" , 0x11800370000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
- {"DFA_PFC1_CTL" , 0x1180037000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
- {"DFA_PFC2_CNT" , 0x11800370000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
- {"DFA_PFC2_CTL" , 0x11800370000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
- {"DFA_PFC3_CNT" , 0x11800370000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
- {"DFA_PFC3_CTL" , 0x11800370000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
- {"DFA_PFC_GCTL" , 0x1180037000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"DFM_CHAR_CTL" , 0x11800d4000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"DFM_CHAR_MASK0" , 0x11800d4000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"DFM_CHAR_MASK2" , 0x11800d4000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"DFM_CHAR_MASK4" , 0x11800d4000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
- {"DFM_COMP_CTL2" , 0x11800d40001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"DFM_CONFIG" , 0x11800d4000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"DFM_CONTROL" , 0x11800d4000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"DFM_DLL_CTL2" , 0x11800d40001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"DFM_DLL_CTL3" , 0x11800d4000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
- {"DFM_FCLK_CNT" , 0x11800d40001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
- {"DFM_FNT_BIST" , 0x11800d40007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"DFM_FNT_CTL" , 0x11800d4000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"DFM_FNT_IENA" , 0x11800d4000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"DFM_FNT_SCLK" , 0x11800d4000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
- {"DFM_FNT_STAT" , 0x11800d4000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"DFM_IFB_CNT" , 0x11800d40001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"DFM_MODEREG_PARAMS0" , 0x11800d40001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"DFM_MODEREG_PARAMS1" , 0x11800d4000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"DFM_OPS_CNT" , 0x11800d40001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"DFM_PHY_CTL" , 0x11800d4000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"DFM_RESET_CTL" , 0x11800d4000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"DFM_RLEVEL_CTL" , 0x11800d40002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"DFM_RLEVEL_DBG" , 0x11800d40002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"DFM_RLEVEL_RANK0" , 0x11800d4000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"DFM_RLEVEL_RANK1" , 0x11800d4000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"DFM_RODT_MASK" , 0x11800d4000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"DFM_SLOT_CTL0" , 0x11800d40001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"DFM_SLOT_CTL1" , 0x11800d4000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"DFM_TIMING_PARAMS0" , 0x11800d4000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"DFM_TIMING_PARAMS1" , 0x11800d40001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"DFM_WLEVEL_CTL" , 0x11800d4000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"DFM_WLEVEL_DBG" , 0x11800d4000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"DFM_WLEVEL_RANK0" , 0x11800d40002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"DFM_WLEVEL_RANK1" , 0x11800d40002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"DFM_WODT_MASK" , 0x11800d40001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"DPI_BIST_STATUS" , 0x1df0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"DPI_CTL" , 0x1df0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"DPI_DMA0_COUNTS" , 0x1df0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA1_COUNTS" , 0x1df0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA2_COUNTS" , 0x1df0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA3_COUNTS" , 0x1df0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA4_COUNTS" , 0x1df0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA5_COUNTS" , 0x1df0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA6_COUNTS" , 0x1df0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA7_COUNTS" , 0x1df0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"DPI_DMA0_DBELL" , 0x1df0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA1_DBELL" , 0x1df0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA2_DBELL" , 0x1df0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA3_DBELL" , 0x1df0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA4_DBELL" , 0x1df0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA5_DBELL" , 0x1df0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA6_DBELL" , 0x1df0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA7_DBELL" , 0x1df0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"DPI_DMA0_IBUFF_SADDR" , 0x1df0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA1_IBUFF_SADDR" , 0x1df0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA2_IBUFF_SADDR" , 0x1df0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA3_IBUFF_SADDR" , 0x1df0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA4_IBUFF_SADDR" , 0x1df00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA5_IBUFF_SADDR" , 0x1df00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA6_IBUFF_SADDR" , 0x1df00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA7_IBUFF_SADDR" , 0x1df00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"DPI_DMA0_NADDR" , 0x1df0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA1_NADDR" , 0x1df0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA2_NADDR" , 0x1df0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA3_NADDR" , 0x1df0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA4_NADDR" , 0x1df00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA5_NADDR" , 0x1df00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA6_NADDR" , 0x1df00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA7_NADDR" , 0x1df00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"DPI_DMA0_REQBNK0" , 0x1df0000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"DPI_DMA1_REQBNK0" , 0x1df0000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"DPI_DMA2_REQBNK0" , 0x1df0000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"DPI_DMA3_REQBNK0" , 0x1df0000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"DPI_DMA4_REQBNK0" , 0x1df0000000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"DPI_DMA5_REQBNK0" , 0x1df0000000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"DPI_DMA6_REQBNK0" , 0x1df0000000430ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"DPI_DMA7_REQBNK0" , 0x1df0000000438ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"DPI_DMA0_REQBNK1" , 0x1df0000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA1_REQBNK1" , 0x1df0000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA2_REQBNK1" , 0x1df0000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA3_REQBNK1" , 0x1df0000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA4_REQBNK1" , 0x1df00000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA5_REQBNK1" , 0x1df00000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA6_REQBNK1" , 0x1df00000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA7_REQBNK1" , 0x1df00000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"DPI_DMA_CONTROL" , 0x1df0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"DPI_DMA_ENG0_EN" , 0x1df0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"DPI_DMA_ENG1_EN" , 0x1df0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"DPI_DMA_ENG2_EN" , 0x1df0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"DPI_DMA_ENG3_EN" , 0x1df0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"DPI_DMA_ENG4_EN" , 0x1df00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"DPI_DMA_ENG5_EN" , 0x1df00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"DPI_ENG0_BUF" , 0x1df0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"DPI_ENG1_BUF" , 0x1df0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"DPI_ENG2_BUF" , 0x1df0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"DPI_ENG3_BUF" , 0x1df0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"DPI_ENG4_BUF" , 0x1df00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"DPI_ENG5_BUF" , 0x1df00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"DPI_INFO_REG" , 0x1df0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"DPI_INT_EN" , 0x1df0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"DPI_INT_REG" , 0x1df0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"DPI_PINT_INFO" , 0x1df0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"DPI_PKT_ERR_RSP" , 0x1df0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"DPI_REQ_ERR_RSP" , 0x1df0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
- {"DPI_REQ_ERR_RSP_EN" , 0x1df0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 186},
- {"DPI_REQ_ERR_RST" , 0x1df0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
- {"DPI_REQ_ERR_RST_EN" , 0x1df0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"DPI_REQ_GBL_EN" , 0x1df0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"DPI_SLI_PRT0_CFG" , 0x1df0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"DPI_SLI_PRT1_CFG" , 0x1df0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"DPI_SLI_PRT0_ERR" , 0x1df0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"DPI_SLI_PRT1_ERR" , 0x1df0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"DPI_SLI_PRT0_ERR_INFO" , 0x1df0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"DPI_SLI_PRT1_ERR_INFO" , 0x1df0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
- {"FPA_PACKET_THRESHOLD" , 0x1180028000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
- {"FPA_POOL0_THRESHOLD" , 0x1180028000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"FPA_POOL1_THRESHOLD" , 0x1180028000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"FPA_POOL2_THRESHOLD" , 0x1180028000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"FPA_POOL3_THRESHOLD" , 0x1180028000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"FPA_POOL4_THRESHOLD" , 0x1180028000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"FPA_POOL5_THRESHOLD" , 0x1180028000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"FPA_POOL6_THRESHOLD" , 0x1180028000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"FPA_POOL7_THRESHOLD" , 0x1180028000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
- {"FPA_WQE_THRESHOLD" , 0x1180028000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
- {"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
- {"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_SOFT_BIST" , 0x11800080007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_TX000_CBFC_XOFF" , 0x11800080005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_TX000_CBFC_XON" , 0x11800080005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX003_SGMII_CTL" , 0x1180008001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
- {"GPIO_CLK_QLM0" , 0x10700000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 297},
- {"GPIO_CLK_QLM1" , 0x10700000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 297},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 298},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"IOB_TO_CMB_CREDITS" , 0x11800f00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 325},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"IPD_PORT36_BP_PAGE_CNT2" , 0x14f0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT37_BP_PAGE_CNT2" , 0x14f0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT38_BP_PAGE_CNT2" , 0x14f0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT39_BP_PAGE_CNT2" , 0x14f0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"IPD_PORT40_BP_PAGE_CNT3" , 0x14f00000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT41_BP_PAGE_CNT3" , 0x14f00000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT42_BP_PAGE_CNT3" , 0x14f00000003e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT43_BP_PAGE_CNT3" , 0x14f00000003e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14f0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14f0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14f0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14f00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"IPD_PORT_BP_COUNTERS3_PAIR40", 0x14f00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"IPD_PORT_BP_COUNTERS3_PAIR41", 0x14f00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"IPD_PORT_BP_COUNTERS3_PAIR42", 0x14f00000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"IPD_PORT_BP_COUNTERS3_PAIR43", 0x14f00000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_256_CNT" , 0x14f0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_257_CNT" , 0x14f0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_258_CNT" , 0x14f0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_259_CNT" , 0x14f00000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_260_CNT" , 0x14f00000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_261_CNT" , 0x14f00000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_262_CNT" , 0x14f00000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_263_CNT" , 0x14f00000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_264_CNT" , 0x14f00000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_265_CNT" , 0x14f00000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_266_CNT" , 0x14f00000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_267_CNT" , 0x14f00000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_268_CNT" , 0x14f00000010e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_269_CNT" , 0x14f00000010f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_270_CNT" , 0x14f00000010f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_271_CNT" , 0x14f0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_272_CNT" , 0x14f0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_273_CNT" , 0x14f0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_274_CNT" , 0x14f0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_275_CNT" , 0x14f0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_276_CNT" , 0x14f0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_277_CNT" , 0x14f0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_278_CNT" , 0x14f0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_279_CNT" , 0x14f0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_280_CNT" , 0x14f0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_281_CNT" , 0x14f0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_282_CNT" , 0x14f0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_283_CNT" , 0x14f0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_284_CNT" , 0x14f0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_285_CNT" , 0x14f0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_286_CNT" , 0x14f0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_287_CNT" , 0x14f0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_320_CNT" , 0x14f0000001288ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_321_CNT" , 0x14f0000001290ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_322_CNT" , 0x14f0000001298ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_323_CNT" , 0x14f00000012a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_324_CNT" , 0x14f00000012a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_325_CNT" , 0x14f00000012b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_326_CNT" , 0x14f00000012b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_327_CNT" , 0x14f00000012c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_328_CNT" , 0x14f00000012c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_329_CNT" , 0x14f00000012d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_330_CNT" , 0x14f00000012d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_331_CNT" , 0x14f00000012e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_332_CNT" , 0x14f00000012e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_333_CNT" , 0x14f00000012f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_334_CNT" , 0x14f00000012f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_335_CNT" , 0x14f0000001300ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_336_CNT" , 0x14f0000001308ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_337_CNT" , 0x14f0000001310ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_338_CNT" , 0x14f0000001318ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_339_CNT" , 0x14f0000001320ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_340_CNT" , 0x14f0000001328ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_341_CNT" , 0x14f0000001330ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_342_CNT" , 0x14f0000001338ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_343_CNT" , 0x14f0000001340ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_344_CNT" , 0x14f0000001348ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_345_CNT" , 0x14f0000001350ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_346_CNT" , 0x14f0000001358ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_347_CNT" , 0x14f0000001360ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_348_CNT" , 0x14f0000001368ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_349_CNT" , 0x14f0000001370ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_350_CNT" , 0x14f0000001378ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_351_CNT" , 0x14f0000001380ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"IPD_PORT_QOS_INT5" , 0x14f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_PORT_QOS_INT_ENB5" , 0x14f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
- {"IPD_RED_PORT_ENABLE2" , 0x14f00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 353},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 355},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 357},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"L2C_BIG_CTL" , 0x1180080800030ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"L2C_BST" , 0x11800808007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"L2C_BST_MEM0" , 0x1180080c007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"L2C_BST_TDT0" , 0x1180080a007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"L2C_BST_TTG0" , 0x1180080a007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"L2C_COP0_MAP0" , 0x1180080940000ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1" , 0x1180080940008ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP2" , 0x1180080940010ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP3" , 0x1180080940018ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP4" , 0x1180080940020ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP5" , 0x1180080940028ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP6" , 0x1180080940030ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP7" , 0x1180080940038ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP8" , 0x1180080940040ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP9" , 0x1180080940048ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP10" , 0x1180080940050ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP11" , 0x1180080940058ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP12" , 0x1180080940060ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP13" , 0x1180080940068ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP14" , 0x1180080940070ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP15" , 0x1180080940078ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16" , 0x1180080940080ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP17" , 0x1180080940088ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP18" , 0x1180080940090ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP19" , 0x1180080940098ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP20" , 0x11800809400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP21" , 0x11800809400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP22" , 0x11800809400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP23" , 0x11800809400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP24" , 0x11800809400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP25" , 0x11800809400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP26" , 0x11800809400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP27" , 0x11800809400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP28" , 0x11800809400e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP29" , 0x11800809400e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP30" , 0x11800809400f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP31" , 0x11800809400f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP32" , 0x1180080940100ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP33" , 0x1180080940108ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP34" , 0x1180080940110ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP35" , 0x1180080940118ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP36" , 0x1180080940120ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP37" , 0x1180080940128ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP38" , 0x1180080940130ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP39" , 0x1180080940138ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP40" , 0x1180080940140ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP41" , 0x1180080940148ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP42" , 0x1180080940150ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP43" , 0x1180080940158ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP44" , 0x1180080940160ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP45" , 0x1180080940168ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP46" , 0x1180080940170ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP47" , 0x1180080940178ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP48" , 0x1180080940180ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP49" , 0x1180080940188ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP50" , 0x1180080940190ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP51" , 0x1180080940198ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP52" , 0x11800809401a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP53" , 0x11800809401a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP54" , 0x11800809401b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP55" , 0x11800809401b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP56" , 0x11800809401c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP57" , 0x11800809401c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP58" , 0x11800809401d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP59" , 0x11800809401d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP60" , 0x11800809401e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP61" , 0x11800809401e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP62" , 0x11800809401f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP63" , 0x11800809401f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP64" , 0x1180080940200ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP65" , 0x1180080940208ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP66" , 0x1180080940210ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP67" , 0x1180080940218ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP68" , 0x1180080940220ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP69" , 0x1180080940228ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP70" , 0x1180080940230ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP71" , 0x1180080940238ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP72" , 0x1180080940240ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP73" , 0x1180080940248ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP74" , 0x1180080940250ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP75" , 0x1180080940258ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP76" , 0x1180080940260ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP77" , 0x1180080940268ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP78" , 0x1180080940270ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP79" , 0x1180080940278ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP80" , 0x1180080940280ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP81" , 0x1180080940288ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP82" , 0x1180080940290ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP83" , 0x1180080940298ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP84" , 0x11800809402a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP85" , 0x11800809402a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP86" , 0x11800809402b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP87" , 0x11800809402b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP88" , 0x11800809402c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP89" , 0x11800809402c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP90" , 0x11800809402d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP91" , 0x11800809402d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP92" , 0x11800809402e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP93" , 0x11800809402e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP94" , 0x11800809402f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP95" , 0x11800809402f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP96" , 0x1180080940300ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP97" , 0x1180080940308ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP98" , 0x1180080940310ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP99" , 0x1180080940318ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP100" , 0x1180080940320ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP101" , 0x1180080940328ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP102" , 0x1180080940330ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP103" , 0x1180080940338ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP104" , 0x1180080940340ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP105" , 0x1180080940348ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP106" , 0x1180080940350ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP107" , 0x1180080940358ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP108" , 0x1180080940360ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP109" , 0x1180080940368ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP110" , 0x1180080940370ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP111" , 0x1180080940378ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP112" , 0x1180080940380ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP113" , 0x1180080940388ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP114" , 0x1180080940390ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP115" , 0x1180080940398ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP116" , 0x11800809403a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP117" , 0x11800809403a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP118" , 0x11800809403b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP119" , 0x11800809403b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP120" , 0x11800809403c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP121" , 0x11800809403c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP122" , 0x11800809403d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP123" , 0x11800809403d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP124" , 0x11800809403e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP125" , 0x11800809403e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP126" , 0x11800809403f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP127" , 0x11800809403f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP128" , 0x1180080940400ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP129" , 0x1180080940408ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP130" , 0x1180080940410ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP131" , 0x1180080940418ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP132" , 0x1180080940420ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP133" , 0x1180080940428ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP134" , 0x1180080940430ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP135" , 0x1180080940438ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP136" , 0x1180080940440ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP137" , 0x1180080940448ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP138" , 0x1180080940450ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP139" , 0x1180080940458ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP140" , 0x1180080940460ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP141" , 0x1180080940468ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP142" , 0x1180080940470ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP143" , 0x1180080940478ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP144" , 0x1180080940480ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP145" , 0x1180080940488ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP146" , 0x1180080940490ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP147" , 0x1180080940498ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP148" , 0x11800809404a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP149" , 0x11800809404a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP150" , 0x11800809404b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP151" , 0x11800809404b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP152" , 0x11800809404c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP153" , 0x11800809404c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP154" , 0x11800809404d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP155" , 0x11800809404d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP156" , 0x11800809404e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP157" , 0x11800809404e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP158" , 0x11800809404f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP159" , 0x11800809404f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP160" , 0x1180080940500ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP161" , 0x1180080940508ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP162" , 0x1180080940510ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP163" , 0x1180080940518ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP164" , 0x1180080940520ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP165" , 0x1180080940528ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP166" , 0x1180080940530ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP167" , 0x1180080940538ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP168" , 0x1180080940540ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP169" , 0x1180080940548ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP170" , 0x1180080940550ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP171" , 0x1180080940558ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP172" , 0x1180080940560ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP173" , 0x1180080940568ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP174" , 0x1180080940570ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP175" , 0x1180080940578ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP176" , 0x1180080940580ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP177" , 0x1180080940588ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP178" , 0x1180080940590ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP179" , 0x1180080940598ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP180" , 0x11800809405a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP181" , 0x11800809405a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP182" , 0x11800809405b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP183" , 0x11800809405b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP184" , 0x11800809405c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP185" , 0x11800809405c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP186" , 0x11800809405d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP187" , 0x11800809405d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP188" , 0x11800809405e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP189" , 0x11800809405e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP190" , 0x11800809405f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP191" , 0x11800809405f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP192" , 0x1180080940600ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP193" , 0x1180080940608ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP194" , 0x1180080940610ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP195" , 0x1180080940618ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP196" , 0x1180080940620ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP197" , 0x1180080940628ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP198" , 0x1180080940630ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP199" , 0x1180080940638ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP200" , 0x1180080940640ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP201" , 0x1180080940648ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP202" , 0x1180080940650ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP203" , 0x1180080940658ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP204" , 0x1180080940660ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP205" , 0x1180080940668ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP206" , 0x1180080940670ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP207" , 0x1180080940678ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP208" , 0x1180080940680ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP209" , 0x1180080940688ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP210" , 0x1180080940690ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP211" , 0x1180080940698ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP212" , 0x11800809406a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP213" , 0x11800809406a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP214" , 0x11800809406b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP215" , 0x11800809406b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP216" , 0x11800809406c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP217" , 0x11800809406c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP218" , 0x11800809406d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP219" , 0x11800809406d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP220" , 0x11800809406e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP221" , 0x11800809406e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP222" , 0x11800809406f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP223" , 0x11800809406f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP224" , 0x1180080940700ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP225" , 0x1180080940708ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP226" , 0x1180080940710ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP227" , 0x1180080940718ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP228" , 0x1180080940720ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP229" , 0x1180080940728ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP230" , 0x1180080940730ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP231" , 0x1180080940738ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP232" , 0x1180080940740ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP233" , 0x1180080940748ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP234" , 0x1180080940750ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP235" , 0x1180080940758ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP236" , 0x1180080940760ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP237" , 0x1180080940768ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP238" , 0x1180080940770ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP239" , 0x1180080940778ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP240" , 0x1180080940780ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP241" , 0x1180080940788ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP242" , 0x1180080940790ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP243" , 0x1180080940798ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP244" , 0x11800809407a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP245" , 0x11800809407a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP246" , 0x11800809407b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP247" , 0x11800809407b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP248" , 0x11800809407c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP249" , 0x11800809407c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP250" , 0x11800809407d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP251" , 0x11800809407d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP252" , 0x11800809407e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP253" , 0x11800809407e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP254" , 0x11800809407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP255" , 0x11800809407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP256" , 0x1180080940800ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP257" , 0x1180080940808ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP258" , 0x1180080940810ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP259" , 0x1180080940818ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP260" , 0x1180080940820ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP261" , 0x1180080940828ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP262" , 0x1180080940830ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP263" , 0x1180080940838ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP264" , 0x1180080940840ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP265" , 0x1180080940848ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP266" , 0x1180080940850ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP267" , 0x1180080940858ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP268" , 0x1180080940860ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP269" , 0x1180080940868ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP270" , 0x1180080940870ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP271" , 0x1180080940878ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP272" , 0x1180080940880ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP273" , 0x1180080940888ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP274" , 0x1180080940890ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP275" , 0x1180080940898ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP276" , 0x11800809408a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP277" , 0x11800809408a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP278" , 0x11800809408b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP279" , 0x11800809408b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP280" , 0x11800809408c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP281" , 0x11800809408c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP282" , 0x11800809408d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP283" , 0x11800809408d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP284" , 0x11800809408e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP285" , 0x11800809408e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP286" , 0x11800809408f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP287" , 0x11800809408f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP288" , 0x1180080940900ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP289" , 0x1180080940908ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP290" , 0x1180080940910ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP291" , 0x1180080940918ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP292" , 0x1180080940920ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP293" , 0x1180080940928ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP294" , 0x1180080940930ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP295" , 0x1180080940938ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP296" , 0x1180080940940ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP297" , 0x1180080940948ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP298" , 0x1180080940950ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP299" , 0x1180080940958ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP300" , 0x1180080940960ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP301" , 0x1180080940968ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP302" , 0x1180080940970ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP303" , 0x1180080940978ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP304" , 0x1180080940980ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP305" , 0x1180080940988ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP306" , 0x1180080940990ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP307" , 0x1180080940998ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP308" , 0x11800809409a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP309" , 0x11800809409a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP310" , 0x11800809409b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP311" , 0x11800809409b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP312" , 0x11800809409c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP313" , 0x11800809409c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP314" , 0x11800809409d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP315" , 0x11800809409d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP316" , 0x11800809409e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP317" , 0x11800809409e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP318" , 0x11800809409f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP319" , 0x11800809409f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP320" , 0x1180080940a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP321" , 0x1180080940a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP322" , 0x1180080940a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP323" , 0x1180080940a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP324" , 0x1180080940a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP325" , 0x1180080940a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP326" , 0x1180080940a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP327" , 0x1180080940a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP328" , 0x1180080940a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP329" , 0x1180080940a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP330" , 0x1180080940a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP331" , 0x1180080940a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP332" , 0x1180080940a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP333" , 0x1180080940a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP334" , 0x1180080940a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP335" , 0x1180080940a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP336" , 0x1180080940a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP337" , 0x1180080940a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP338" , 0x1180080940a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP339" , 0x1180080940a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP340" , 0x1180080940aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP341" , 0x1180080940aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP342" , 0x1180080940ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP343" , 0x1180080940ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP344" , 0x1180080940ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP345" , 0x1180080940ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP346" , 0x1180080940ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP347" , 0x1180080940ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP348" , 0x1180080940ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP349" , 0x1180080940ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP350" , 0x1180080940af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP351" , 0x1180080940af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP352" , 0x1180080940b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP353" , 0x1180080940b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP354" , 0x1180080940b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP355" , 0x1180080940b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP356" , 0x1180080940b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP357" , 0x1180080940b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP358" , 0x1180080940b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP359" , 0x1180080940b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP360" , 0x1180080940b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP361" , 0x1180080940b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP362" , 0x1180080940b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP363" , 0x1180080940b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP364" , 0x1180080940b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP365" , 0x1180080940b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP366" , 0x1180080940b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP367" , 0x1180080940b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP368" , 0x1180080940b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP369" , 0x1180080940b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP370" , 0x1180080940b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP371" , 0x1180080940b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP372" , 0x1180080940ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP373" , 0x1180080940ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP374" , 0x1180080940bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP375" , 0x1180080940bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP376" , 0x1180080940bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP377" , 0x1180080940bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP378" , 0x1180080940bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP379" , 0x1180080940bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP380" , 0x1180080940be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP381" , 0x1180080940be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP382" , 0x1180080940bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP383" , 0x1180080940bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP384" , 0x1180080940c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP385" , 0x1180080940c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP386" , 0x1180080940c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP387" , 0x1180080940c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP388" , 0x1180080940c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP389" , 0x1180080940c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP390" , 0x1180080940c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP391" , 0x1180080940c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP392" , 0x1180080940c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP393" , 0x1180080940c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP394" , 0x1180080940c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP395" , 0x1180080940c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP396" , 0x1180080940c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP397" , 0x1180080940c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP398" , 0x1180080940c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP399" , 0x1180080940c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP400" , 0x1180080940c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP401" , 0x1180080940c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP402" , 0x1180080940c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP403" , 0x1180080940c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP404" , 0x1180080940ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP405" , 0x1180080940ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP406" , 0x1180080940cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP407" , 0x1180080940cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP408" , 0x1180080940cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP409" , 0x1180080940cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP410" , 0x1180080940cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP411" , 0x1180080940cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP412" , 0x1180080940ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP413" , 0x1180080940ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP414" , 0x1180080940cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP415" , 0x1180080940cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP416" , 0x1180080940d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP417" , 0x1180080940d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP418" , 0x1180080940d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP419" , 0x1180080940d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP420" , 0x1180080940d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP421" , 0x1180080940d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP422" , 0x1180080940d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP423" , 0x1180080940d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP424" , 0x1180080940d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP425" , 0x1180080940d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP426" , 0x1180080940d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP427" , 0x1180080940d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP428" , 0x1180080940d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP429" , 0x1180080940d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP430" , 0x1180080940d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP431" , 0x1180080940d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP432" , 0x1180080940d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP433" , 0x1180080940d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP434" , 0x1180080940d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP435" , 0x1180080940d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP436" , 0x1180080940da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP437" , 0x1180080940da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP438" , 0x1180080940db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP439" , 0x1180080940db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP440" , 0x1180080940dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP441" , 0x1180080940dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP442" , 0x1180080940dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP443" , 0x1180080940dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP444" , 0x1180080940de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP445" , 0x1180080940de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP446" , 0x1180080940df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP447" , 0x1180080940df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP448" , 0x1180080940e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP449" , 0x1180080940e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP450" , 0x1180080940e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP451" , 0x1180080940e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP452" , 0x1180080940e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP453" , 0x1180080940e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP454" , 0x1180080940e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP455" , 0x1180080940e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP456" , 0x1180080940e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP457" , 0x1180080940e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP458" , 0x1180080940e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP459" , 0x1180080940e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP460" , 0x1180080940e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP461" , 0x1180080940e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP462" , 0x1180080940e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP463" , 0x1180080940e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP464" , 0x1180080940e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP465" , 0x1180080940e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP466" , 0x1180080940e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP467" , 0x1180080940e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP468" , 0x1180080940ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP469" , 0x1180080940ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP470" , 0x1180080940eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP471" , 0x1180080940eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP472" , 0x1180080940ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP473" , 0x1180080940ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP474" , 0x1180080940ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP475" , 0x1180080940ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP476" , 0x1180080940ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP477" , 0x1180080940ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP478" , 0x1180080940ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP479" , 0x1180080940ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP480" , 0x1180080940f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP481" , 0x1180080940f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP482" , 0x1180080940f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP483" , 0x1180080940f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP484" , 0x1180080940f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP485" , 0x1180080940f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP486" , 0x1180080940f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP487" , 0x1180080940f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP488" , 0x1180080940f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP489" , 0x1180080940f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP490" , 0x1180080940f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP491" , 0x1180080940f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP492" , 0x1180080940f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP493" , 0x1180080940f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP494" , 0x1180080940f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP495" , 0x1180080940f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP496" , 0x1180080940f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP497" , 0x1180080940f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP498" , 0x1180080940f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP499" , 0x1180080940f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP500" , 0x1180080940fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP501" , 0x1180080940fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP502" , 0x1180080940fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP503" , 0x1180080940fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP504" , 0x1180080940fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP505" , 0x1180080940fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP506" , 0x1180080940fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP507" , 0x1180080940fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP508" , 0x1180080940fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP509" , 0x1180080940fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP510" , 0x1180080940ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP511" , 0x1180080940ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP512" , 0x1180080941000ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP513" , 0x1180080941008ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP514" , 0x1180080941010ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP515" , 0x1180080941018ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP516" , 0x1180080941020ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP517" , 0x1180080941028ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP518" , 0x1180080941030ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP519" , 0x1180080941038ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP520" , 0x1180080941040ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP521" , 0x1180080941048ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP522" , 0x1180080941050ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP523" , 0x1180080941058ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP524" , 0x1180080941060ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP525" , 0x1180080941068ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP526" , 0x1180080941070ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP527" , 0x1180080941078ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP528" , 0x1180080941080ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP529" , 0x1180080941088ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP530" , 0x1180080941090ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP531" , 0x1180080941098ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP532" , 0x11800809410a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP533" , 0x11800809410a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP534" , 0x11800809410b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP535" , 0x11800809410b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP536" , 0x11800809410c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP537" , 0x11800809410c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP538" , 0x11800809410d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP539" , 0x11800809410d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP540" , 0x11800809410e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP541" , 0x11800809410e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP542" , 0x11800809410f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP543" , 0x11800809410f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP544" , 0x1180080941100ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP545" , 0x1180080941108ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP546" , 0x1180080941110ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP547" , 0x1180080941118ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP548" , 0x1180080941120ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP549" , 0x1180080941128ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP550" , 0x1180080941130ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP551" , 0x1180080941138ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP552" , 0x1180080941140ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP553" , 0x1180080941148ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP554" , 0x1180080941150ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP555" , 0x1180080941158ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP556" , 0x1180080941160ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP557" , 0x1180080941168ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP558" , 0x1180080941170ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP559" , 0x1180080941178ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP560" , 0x1180080941180ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP561" , 0x1180080941188ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP562" , 0x1180080941190ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP563" , 0x1180080941198ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP564" , 0x11800809411a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP565" , 0x11800809411a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP566" , 0x11800809411b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP567" , 0x11800809411b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP568" , 0x11800809411c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP569" , 0x11800809411c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP570" , 0x11800809411d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP571" , 0x11800809411d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP572" , 0x11800809411e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP573" , 0x11800809411e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP574" , 0x11800809411f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP575" , 0x11800809411f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP576" , 0x1180080941200ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP577" , 0x1180080941208ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP578" , 0x1180080941210ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP579" , 0x1180080941218ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP580" , 0x1180080941220ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP581" , 0x1180080941228ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP582" , 0x1180080941230ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP583" , 0x1180080941238ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP584" , 0x1180080941240ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP585" , 0x1180080941248ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP586" , 0x1180080941250ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP587" , 0x1180080941258ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP588" , 0x1180080941260ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP589" , 0x1180080941268ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP590" , 0x1180080941270ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP591" , 0x1180080941278ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP592" , 0x1180080941280ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP593" , 0x1180080941288ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP594" , 0x1180080941290ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP595" , 0x1180080941298ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP596" , 0x11800809412a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP597" , 0x11800809412a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP598" , 0x11800809412b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP599" , 0x11800809412b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP600" , 0x11800809412c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP601" , 0x11800809412c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP602" , 0x11800809412d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP603" , 0x11800809412d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP604" , 0x11800809412e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP605" , 0x11800809412e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP606" , 0x11800809412f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP607" , 0x11800809412f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP608" , 0x1180080941300ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP609" , 0x1180080941308ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP610" , 0x1180080941310ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP611" , 0x1180080941318ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP612" , 0x1180080941320ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP613" , 0x1180080941328ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP614" , 0x1180080941330ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP615" , 0x1180080941338ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP616" , 0x1180080941340ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP617" , 0x1180080941348ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP618" , 0x1180080941350ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP619" , 0x1180080941358ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP620" , 0x1180080941360ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP621" , 0x1180080941368ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP622" , 0x1180080941370ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP623" , 0x1180080941378ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP624" , 0x1180080941380ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP625" , 0x1180080941388ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP626" , 0x1180080941390ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP627" , 0x1180080941398ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP628" , 0x11800809413a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP629" , 0x11800809413a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP630" , 0x11800809413b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP631" , 0x11800809413b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP632" , 0x11800809413c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP633" , 0x11800809413c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP634" , 0x11800809413d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP635" , 0x11800809413d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP636" , 0x11800809413e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP637" , 0x11800809413e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP638" , 0x11800809413f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP639" , 0x11800809413f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP640" , 0x1180080941400ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP641" , 0x1180080941408ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP642" , 0x1180080941410ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP643" , 0x1180080941418ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP644" , 0x1180080941420ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP645" , 0x1180080941428ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP646" , 0x1180080941430ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP647" , 0x1180080941438ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP648" , 0x1180080941440ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP649" , 0x1180080941448ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP650" , 0x1180080941450ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP651" , 0x1180080941458ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP652" , 0x1180080941460ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP653" , 0x1180080941468ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP654" , 0x1180080941470ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP655" , 0x1180080941478ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP656" , 0x1180080941480ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP657" , 0x1180080941488ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP658" , 0x1180080941490ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP659" , 0x1180080941498ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP660" , 0x11800809414a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP661" , 0x11800809414a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP662" , 0x11800809414b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP663" , 0x11800809414b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP664" , 0x11800809414c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP665" , 0x11800809414c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP666" , 0x11800809414d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP667" , 0x11800809414d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP668" , 0x11800809414e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP669" , 0x11800809414e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP670" , 0x11800809414f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP671" , 0x11800809414f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP672" , 0x1180080941500ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP673" , 0x1180080941508ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP674" , 0x1180080941510ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP675" , 0x1180080941518ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP676" , 0x1180080941520ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP677" , 0x1180080941528ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP678" , 0x1180080941530ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP679" , 0x1180080941538ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP680" , 0x1180080941540ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP681" , 0x1180080941548ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP682" , 0x1180080941550ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP683" , 0x1180080941558ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP684" , 0x1180080941560ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP685" , 0x1180080941568ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP686" , 0x1180080941570ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP687" , 0x1180080941578ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP688" , 0x1180080941580ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP689" , 0x1180080941588ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP690" , 0x1180080941590ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP691" , 0x1180080941598ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP692" , 0x11800809415a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP693" , 0x11800809415a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP694" , 0x11800809415b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP695" , 0x11800809415b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP696" , 0x11800809415c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP697" , 0x11800809415c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP698" , 0x11800809415d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP699" , 0x11800809415d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP700" , 0x11800809415e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP701" , 0x11800809415e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP702" , 0x11800809415f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP703" , 0x11800809415f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP704" , 0x1180080941600ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP705" , 0x1180080941608ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP706" , 0x1180080941610ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP707" , 0x1180080941618ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP708" , 0x1180080941620ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP709" , 0x1180080941628ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP710" , 0x1180080941630ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP711" , 0x1180080941638ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP712" , 0x1180080941640ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP713" , 0x1180080941648ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP714" , 0x1180080941650ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP715" , 0x1180080941658ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP716" , 0x1180080941660ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP717" , 0x1180080941668ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP718" , 0x1180080941670ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP719" , 0x1180080941678ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP720" , 0x1180080941680ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP721" , 0x1180080941688ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP722" , 0x1180080941690ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP723" , 0x1180080941698ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP724" , 0x11800809416a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP725" , 0x11800809416a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP726" , 0x11800809416b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP727" , 0x11800809416b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP728" , 0x11800809416c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP729" , 0x11800809416c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP730" , 0x11800809416d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP731" , 0x11800809416d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP732" , 0x11800809416e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP733" , 0x11800809416e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP734" , 0x11800809416f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP735" , 0x11800809416f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP736" , 0x1180080941700ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP737" , 0x1180080941708ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP738" , 0x1180080941710ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP739" , 0x1180080941718ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP740" , 0x1180080941720ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP741" , 0x1180080941728ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP742" , 0x1180080941730ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP743" , 0x1180080941738ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP744" , 0x1180080941740ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP745" , 0x1180080941748ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP746" , 0x1180080941750ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP747" , 0x1180080941758ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP748" , 0x1180080941760ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP749" , 0x1180080941768ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP750" , 0x1180080941770ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP751" , 0x1180080941778ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP752" , 0x1180080941780ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP753" , 0x1180080941788ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP754" , 0x1180080941790ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP755" , 0x1180080941798ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP756" , 0x11800809417a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP757" , 0x11800809417a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP758" , 0x11800809417b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP759" , 0x11800809417b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP760" , 0x11800809417c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP761" , 0x11800809417c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP762" , 0x11800809417d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP763" , 0x11800809417d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP764" , 0x11800809417e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP765" , 0x11800809417e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP766" , 0x11800809417f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP767" , 0x11800809417f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP768" , 0x1180080941800ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP769" , 0x1180080941808ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP770" , 0x1180080941810ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP771" , 0x1180080941818ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP772" , 0x1180080941820ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP773" , 0x1180080941828ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP774" , 0x1180080941830ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP775" , 0x1180080941838ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP776" , 0x1180080941840ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP777" , 0x1180080941848ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP778" , 0x1180080941850ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP779" , 0x1180080941858ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP780" , 0x1180080941860ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP781" , 0x1180080941868ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP782" , 0x1180080941870ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP783" , 0x1180080941878ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP784" , 0x1180080941880ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP785" , 0x1180080941888ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP786" , 0x1180080941890ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP787" , 0x1180080941898ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP788" , 0x11800809418a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP789" , 0x11800809418a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP790" , 0x11800809418b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP791" , 0x11800809418b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP792" , 0x11800809418c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP793" , 0x11800809418c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP794" , 0x11800809418d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP795" , 0x11800809418d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP796" , 0x11800809418e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP797" , 0x11800809418e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP798" , 0x11800809418f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP799" , 0x11800809418f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP800" , 0x1180080941900ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP801" , 0x1180080941908ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP802" , 0x1180080941910ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP803" , 0x1180080941918ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP804" , 0x1180080941920ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP805" , 0x1180080941928ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP806" , 0x1180080941930ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP807" , 0x1180080941938ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP808" , 0x1180080941940ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP809" , 0x1180080941948ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP810" , 0x1180080941950ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP811" , 0x1180080941958ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP812" , 0x1180080941960ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP813" , 0x1180080941968ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP814" , 0x1180080941970ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP815" , 0x1180080941978ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP816" , 0x1180080941980ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP817" , 0x1180080941988ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP818" , 0x1180080941990ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP819" , 0x1180080941998ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP820" , 0x11800809419a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP821" , 0x11800809419a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP822" , 0x11800809419b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP823" , 0x11800809419b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP824" , 0x11800809419c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP825" , 0x11800809419c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP826" , 0x11800809419d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP827" , 0x11800809419d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP828" , 0x11800809419e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP829" , 0x11800809419e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP830" , 0x11800809419f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP831" , 0x11800809419f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP832" , 0x1180080941a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP833" , 0x1180080941a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP834" , 0x1180080941a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP835" , 0x1180080941a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP836" , 0x1180080941a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP837" , 0x1180080941a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP838" , 0x1180080941a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP839" , 0x1180080941a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP840" , 0x1180080941a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP841" , 0x1180080941a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP842" , 0x1180080941a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP843" , 0x1180080941a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP844" , 0x1180080941a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP845" , 0x1180080941a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP846" , 0x1180080941a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP847" , 0x1180080941a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP848" , 0x1180080941a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP849" , 0x1180080941a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP850" , 0x1180080941a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP851" , 0x1180080941a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP852" , 0x1180080941aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP853" , 0x1180080941aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP854" , 0x1180080941ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP855" , 0x1180080941ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP856" , 0x1180080941ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP857" , 0x1180080941ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP858" , 0x1180080941ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP859" , 0x1180080941ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP860" , 0x1180080941ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP861" , 0x1180080941ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP862" , 0x1180080941af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP863" , 0x1180080941af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP864" , 0x1180080941b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP865" , 0x1180080941b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP866" , 0x1180080941b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP867" , 0x1180080941b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP868" , 0x1180080941b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP869" , 0x1180080941b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP870" , 0x1180080941b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP871" , 0x1180080941b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP872" , 0x1180080941b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP873" , 0x1180080941b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP874" , 0x1180080941b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP875" , 0x1180080941b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP876" , 0x1180080941b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP877" , 0x1180080941b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP878" , 0x1180080941b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP879" , 0x1180080941b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP880" , 0x1180080941b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP881" , 0x1180080941b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP882" , 0x1180080941b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP883" , 0x1180080941b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP884" , 0x1180080941ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP885" , 0x1180080941ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP886" , 0x1180080941bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP887" , 0x1180080941bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP888" , 0x1180080941bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP889" , 0x1180080941bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP890" , 0x1180080941bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP891" , 0x1180080941bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP892" , 0x1180080941be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP893" , 0x1180080941be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP894" , 0x1180080941bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP895" , 0x1180080941bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP896" , 0x1180080941c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP897" , 0x1180080941c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP898" , 0x1180080941c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP899" , 0x1180080941c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP900" , 0x1180080941c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP901" , 0x1180080941c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP902" , 0x1180080941c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP903" , 0x1180080941c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP904" , 0x1180080941c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP905" , 0x1180080941c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP906" , 0x1180080941c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP907" , 0x1180080941c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP908" , 0x1180080941c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP909" , 0x1180080941c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP910" , 0x1180080941c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP911" , 0x1180080941c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP912" , 0x1180080941c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP913" , 0x1180080941c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP914" , 0x1180080941c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP915" , 0x1180080941c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP916" , 0x1180080941ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP917" , 0x1180080941ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP918" , 0x1180080941cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP919" , 0x1180080941cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP920" , 0x1180080941cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP921" , 0x1180080941cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP922" , 0x1180080941cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP923" , 0x1180080941cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP924" , 0x1180080941ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP925" , 0x1180080941ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP926" , 0x1180080941cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP927" , 0x1180080941cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP928" , 0x1180080941d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP929" , 0x1180080941d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP930" , 0x1180080941d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP931" , 0x1180080941d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP932" , 0x1180080941d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP933" , 0x1180080941d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP934" , 0x1180080941d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP935" , 0x1180080941d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP936" , 0x1180080941d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP937" , 0x1180080941d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP938" , 0x1180080941d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP939" , 0x1180080941d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP940" , 0x1180080941d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP941" , 0x1180080941d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP942" , 0x1180080941d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP943" , 0x1180080941d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP944" , 0x1180080941d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP945" , 0x1180080941d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP946" , 0x1180080941d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP947" , 0x1180080941d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP948" , 0x1180080941da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP949" , 0x1180080941da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP950" , 0x1180080941db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP951" , 0x1180080941db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP952" , 0x1180080941dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP953" , 0x1180080941dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP954" , 0x1180080941dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP955" , 0x1180080941dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP956" , 0x1180080941de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP957" , 0x1180080941de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP958" , 0x1180080941df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP959" , 0x1180080941df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP960" , 0x1180080941e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP961" , 0x1180080941e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP962" , 0x1180080941e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP963" , 0x1180080941e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP964" , 0x1180080941e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP965" , 0x1180080941e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP966" , 0x1180080941e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP967" , 0x1180080941e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP968" , 0x1180080941e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP969" , 0x1180080941e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP970" , 0x1180080941e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP971" , 0x1180080941e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP972" , 0x1180080941e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP973" , 0x1180080941e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP974" , 0x1180080941e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP975" , 0x1180080941e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP976" , 0x1180080941e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP977" , 0x1180080941e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP978" , 0x1180080941e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP979" , 0x1180080941e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP980" , 0x1180080941ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP981" , 0x1180080941ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP982" , 0x1180080941eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP983" , 0x1180080941eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP984" , 0x1180080941ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP985" , 0x1180080941ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP986" , 0x1180080941ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP987" , 0x1180080941ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP988" , 0x1180080941ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP989" , 0x1180080941ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP990" , 0x1180080941ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP991" , 0x1180080941ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP992" , 0x1180080941f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP993" , 0x1180080941f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP994" , 0x1180080941f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP995" , 0x1180080941f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP996" , 0x1180080941f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP997" , 0x1180080941f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP998" , 0x1180080941f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP999" , 0x1180080941f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1000" , 0x1180080941f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1001" , 0x1180080941f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1002" , 0x1180080941f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1003" , 0x1180080941f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1004" , 0x1180080941f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1005" , 0x1180080941f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1006" , 0x1180080941f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1007" , 0x1180080941f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1008" , 0x1180080941f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1009" , 0x1180080941f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1010" , 0x1180080941f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1011" , 0x1180080941f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1012" , 0x1180080941fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1013" , 0x1180080941fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1014" , 0x1180080941fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1015" , 0x1180080941fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1016" , 0x1180080941fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1017" , 0x1180080941fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1018" , 0x1180080941fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1019" , 0x1180080941fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1020" , 0x1180080941fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1021" , 0x1180080941fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1022" , 0x1180080941ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1023" , 0x1180080941ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1024" , 0x1180080942000ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1025" , 0x1180080942008ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1026" , 0x1180080942010ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1027" , 0x1180080942018ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1028" , 0x1180080942020ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1029" , 0x1180080942028ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1030" , 0x1180080942030ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1031" , 0x1180080942038ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1032" , 0x1180080942040ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1033" , 0x1180080942048ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1034" , 0x1180080942050ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1035" , 0x1180080942058ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1036" , 0x1180080942060ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1037" , 0x1180080942068ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1038" , 0x1180080942070ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1039" , 0x1180080942078ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1040" , 0x1180080942080ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1041" , 0x1180080942088ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1042" , 0x1180080942090ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1043" , 0x1180080942098ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1044" , 0x11800809420a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1045" , 0x11800809420a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1046" , 0x11800809420b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1047" , 0x11800809420b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1048" , 0x11800809420c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1049" , 0x11800809420c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1050" , 0x11800809420d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1051" , 0x11800809420d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1052" , 0x11800809420e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1053" , 0x11800809420e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1054" , 0x11800809420f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1055" , 0x11800809420f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1056" , 0x1180080942100ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1057" , 0x1180080942108ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1058" , 0x1180080942110ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1059" , 0x1180080942118ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1060" , 0x1180080942120ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1061" , 0x1180080942128ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1062" , 0x1180080942130ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1063" , 0x1180080942138ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1064" , 0x1180080942140ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1065" , 0x1180080942148ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1066" , 0x1180080942150ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1067" , 0x1180080942158ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1068" , 0x1180080942160ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1069" , 0x1180080942168ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1070" , 0x1180080942170ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1071" , 0x1180080942178ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1072" , 0x1180080942180ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1073" , 0x1180080942188ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1074" , 0x1180080942190ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1075" , 0x1180080942198ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1076" , 0x11800809421a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1077" , 0x11800809421a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1078" , 0x11800809421b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1079" , 0x11800809421b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1080" , 0x11800809421c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1081" , 0x11800809421c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1082" , 0x11800809421d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1083" , 0x11800809421d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1084" , 0x11800809421e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1085" , 0x11800809421e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1086" , 0x11800809421f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1087" , 0x11800809421f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1088" , 0x1180080942200ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1089" , 0x1180080942208ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1090" , 0x1180080942210ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1091" , 0x1180080942218ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1092" , 0x1180080942220ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1093" , 0x1180080942228ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1094" , 0x1180080942230ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1095" , 0x1180080942238ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1096" , 0x1180080942240ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1097" , 0x1180080942248ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1098" , 0x1180080942250ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1099" , 0x1180080942258ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1100" , 0x1180080942260ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1101" , 0x1180080942268ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1102" , 0x1180080942270ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1103" , 0x1180080942278ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1104" , 0x1180080942280ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1105" , 0x1180080942288ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1106" , 0x1180080942290ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1107" , 0x1180080942298ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1108" , 0x11800809422a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1109" , 0x11800809422a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1110" , 0x11800809422b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1111" , 0x11800809422b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1112" , 0x11800809422c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1113" , 0x11800809422c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1114" , 0x11800809422d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1115" , 0x11800809422d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1116" , 0x11800809422e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1117" , 0x11800809422e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1118" , 0x11800809422f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1119" , 0x11800809422f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1120" , 0x1180080942300ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1121" , 0x1180080942308ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1122" , 0x1180080942310ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1123" , 0x1180080942318ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1124" , 0x1180080942320ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1125" , 0x1180080942328ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1126" , 0x1180080942330ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1127" , 0x1180080942338ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1128" , 0x1180080942340ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1129" , 0x1180080942348ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1130" , 0x1180080942350ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1131" , 0x1180080942358ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1132" , 0x1180080942360ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1133" , 0x1180080942368ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1134" , 0x1180080942370ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1135" , 0x1180080942378ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1136" , 0x1180080942380ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1137" , 0x1180080942388ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1138" , 0x1180080942390ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1139" , 0x1180080942398ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1140" , 0x11800809423a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1141" , 0x11800809423a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1142" , 0x11800809423b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1143" , 0x11800809423b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1144" , 0x11800809423c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1145" , 0x11800809423c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1146" , 0x11800809423d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1147" , 0x11800809423d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1148" , 0x11800809423e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1149" , 0x11800809423e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1150" , 0x11800809423f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1151" , 0x11800809423f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1152" , 0x1180080942400ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1153" , 0x1180080942408ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1154" , 0x1180080942410ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1155" , 0x1180080942418ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1156" , 0x1180080942420ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1157" , 0x1180080942428ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1158" , 0x1180080942430ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1159" , 0x1180080942438ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1160" , 0x1180080942440ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1161" , 0x1180080942448ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1162" , 0x1180080942450ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1163" , 0x1180080942458ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1164" , 0x1180080942460ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1165" , 0x1180080942468ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1166" , 0x1180080942470ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1167" , 0x1180080942478ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1168" , 0x1180080942480ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1169" , 0x1180080942488ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1170" , 0x1180080942490ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1171" , 0x1180080942498ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1172" , 0x11800809424a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1173" , 0x11800809424a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1174" , 0x11800809424b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1175" , 0x11800809424b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1176" , 0x11800809424c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1177" , 0x11800809424c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1178" , 0x11800809424d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1179" , 0x11800809424d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1180" , 0x11800809424e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1181" , 0x11800809424e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1182" , 0x11800809424f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1183" , 0x11800809424f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1184" , 0x1180080942500ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1185" , 0x1180080942508ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1186" , 0x1180080942510ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1187" , 0x1180080942518ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1188" , 0x1180080942520ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1189" , 0x1180080942528ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1190" , 0x1180080942530ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1191" , 0x1180080942538ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1192" , 0x1180080942540ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1193" , 0x1180080942548ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1194" , 0x1180080942550ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1195" , 0x1180080942558ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1196" , 0x1180080942560ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1197" , 0x1180080942568ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1198" , 0x1180080942570ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1199" , 0x1180080942578ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1200" , 0x1180080942580ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1201" , 0x1180080942588ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1202" , 0x1180080942590ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1203" , 0x1180080942598ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1204" , 0x11800809425a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1205" , 0x11800809425a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1206" , 0x11800809425b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1207" , 0x11800809425b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1208" , 0x11800809425c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1209" , 0x11800809425c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1210" , 0x11800809425d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1211" , 0x11800809425d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1212" , 0x11800809425e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1213" , 0x11800809425e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1214" , 0x11800809425f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1215" , 0x11800809425f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1216" , 0x1180080942600ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1217" , 0x1180080942608ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1218" , 0x1180080942610ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1219" , 0x1180080942618ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1220" , 0x1180080942620ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1221" , 0x1180080942628ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1222" , 0x1180080942630ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1223" , 0x1180080942638ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1224" , 0x1180080942640ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1225" , 0x1180080942648ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1226" , 0x1180080942650ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1227" , 0x1180080942658ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1228" , 0x1180080942660ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1229" , 0x1180080942668ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1230" , 0x1180080942670ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1231" , 0x1180080942678ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1232" , 0x1180080942680ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1233" , 0x1180080942688ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1234" , 0x1180080942690ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1235" , 0x1180080942698ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1236" , 0x11800809426a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1237" , 0x11800809426a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1238" , 0x11800809426b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1239" , 0x11800809426b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1240" , 0x11800809426c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1241" , 0x11800809426c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1242" , 0x11800809426d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1243" , 0x11800809426d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1244" , 0x11800809426e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1245" , 0x11800809426e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1246" , 0x11800809426f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1247" , 0x11800809426f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1248" , 0x1180080942700ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1249" , 0x1180080942708ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1250" , 0x1180080942710ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1251" , 0x1180080942718ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1252" , 0x1180080942720ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1253" , 0x1180080942728ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1254" , 0x1180080942730ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1255" , 0x1180080942738ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1256" , 0x1180080942740ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1257" , 0x1180080942748ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1258" , 0x1180080942750ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1259" , 0x1180080942758ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1260" , 0x1180080942760ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1261" , 0x1180080942768ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1262" , 0x1180080942770ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1263" , 0x1180080942778ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1264" , 0x1180080942780ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1265" , 0x1180080942788ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1266" , 0x1180080942790ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1267" , 0x1180080942798ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1268" , 0x11800809427a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1269" , 0x11800809427a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1270" , 0x11800809427b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1271" , 0x11800809427b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1272" , 0x11800809427c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1273" , 0x11800809427c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1274" , 0x11800809427d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1275" , 0x11800809427d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1276" , 0x11800809427e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1277" , 0x11800809427e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1278" , 0x11800809427f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1279" , 0x11800809427f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1280" , 0x1180080942800ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1281" , 0x1180080942808ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1282" , 0x1180080942810ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1283" , 0x1180080942818ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1284" , 0x1180080942820ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1285" , 0x1180080942828ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1286" , 0x1180080942830ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1287" , 0x1180080942838ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1288" , 0x1180080942840ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1289" , 0x1180080942848ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1290" , 0x1180080942850ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1291" , 0x1180080942858ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1292" , 0x1180080942860ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1293" , 0x1180080942868ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1294" , 0x1180080942870ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1295" , 0x1180080942878ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1296" , 0x1180080942880ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1297" , 0x1180080942888ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1298" , 0x1180080942890ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1299" , 0x1180080942898ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1300" , 0x11800809428a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1301" , 0x11800809428a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1302" , 0x11800809428b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1303" , 0x11800809428b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1304" , 0x11800809428c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1305" , 0x11800809428c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1306" , 0x11800809428d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1307" , 0x11800809428d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1308" , 0x11800809428e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1309" , 0x11800809428e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1310" , 0x11800809428f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1311" , 0x11800809428f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1312" , 0x1180080942900ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1313" , 0x1180080942908ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1314" , 0x1180080942910ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1315" , 0x1180080942918ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1316" , 0x1180080942920ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1317" , 0x1180080942928ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1318" , 0x1180080942930ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1319" , 0x1180080942938ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1320" , 0x1180080942940ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1321" , 0x1180080942948ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1322" , 0x1180080942950ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1323" , 0x1180080942958ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1324" , 0x1180080942960ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1325" , 0x1180080942968ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1326" , 0x1180080942970ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1327" , 0x1180080942978ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1328" , 0x1180080942980ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1329" , 0x1180080942988ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1330" , 0x1180080942990ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1331" , 0x1180080942998ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1332" , 0x11800809429a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1333" , 0x11800809429a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1334" , 0x11800809429b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1335" , 0x11800809429b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1336" , 0x11800809429c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1337" , 0x11800809429c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1338" , 0x11800809429d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1339" , 0x11800809429d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1340" , 0x11800809429e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1341" , 0x11800809429e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1342" , 0x11800809429f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1343" , 0x11800809429f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1344" , 0x1180080942a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1345" , 0x1180080942a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1346" , 0x1180080942a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1347" , 0x1180080942a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1348" , 0x1180080942a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1349" , 0x1180080942a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1350" , 0x1180080942a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1351" , 0x1180080942a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1352" , 0x1180080942a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1353" , 0x1180080942a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1354" , 0x1180080942a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1355" , 0x1180080942a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1356" , 0x1180080942a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1357" , 0x1180080942a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1358" , 0x1180080942a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1359" , 0x1180080942a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1360" , 0x1180080942a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1361" , 0x1180080942a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1362" , 0x1180080942a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1363" , 0x1180080942a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1364" , 0x1180080942aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1365" , 0x1180080942aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1366" , 0x1180080942ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1367" , 0x1180080942ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1368" , 0x1180080942ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1369" , 0x1180080942ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1370" , 0x1180080942ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1371" , 0x1180080942ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1372" , 0x1180080942ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1373" , 0x1180080942ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1374" , 0x1180080942af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1375" , 0x1180080942af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1376" , 0x1180080942b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1377" , 0x1180080942b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1378" , 0x1180080942b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1379" , 0x1180080942b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1380" , 0x1180080942b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1381" , 0x1180080942b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1382" , 0x1180080942b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1383" , 0x1180080942b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1384" , 0x1180080942b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1385" , 0x1180080942b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1386" , 0x1180080942b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1387" , 0x1180080942b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1388" , 0x1180080942b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1389" , 0x1180080942b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1390" , 0x1180080942b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1391" , 0x1180080942b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1392" , 0x1180080942b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1393" , 0x1180080942b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1394" , 0x1180080942b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1395" , 0x1180080942b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1396" , 0x1180080942ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1397" , 0x1180080942ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1398" , 0x1180080942bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1399" , 0x1180080942bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1400" , 0x1180080942bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1401" , 0x1180080942bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1402" , 0x1180080942bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1403" , 0x1180080942bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1404" , 0x1180080942be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1405" , 0x1180080942be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1406" , 0x1180080942bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1407" , 0x1180080942bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1408" , 0x1180080942c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1409" , 0x1180080942c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1410" , 0x1180080942c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1411" , 0x1180080942c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1412" , 0x1180080942c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1413" , 0x1180080942c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1414" , 0x1180080942c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1415" , 0x1180080942c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1416" , 0x1180080942c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1417" , 0x1180080942c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1418" , 0x1180080942c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1419" , 0x1180080942c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1420" , 0x1180080942c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1421" , 0x1180080942c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1422" , 0x1180080942c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1423" , 0x1180080942c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1424" , 0x1180080942c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1425" , 0x1180080942c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1426" , 0x1180080942c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1427" , 0x1180080942c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1428" , 0x1180080942ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1429" , 0x1180080942ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1430" , 0x1180080942cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1431" , 0x1180080942cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1432" , 0x1180080942cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1433" , 0x1180080942cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1434" , 0x1180080942cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1435" , 0x1180080942cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1436" , 0x1180080942ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1437" , 0x1180080942ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1438" , 0x1180080942cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1439" , 0x1180080942cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1440" , 0x1180080942d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1441" , 0x1180080942d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1442" , 0x1180080942d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1443" , 0x1180080942d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1444" , 0x1180080942d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1445" , 0x1180080942d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1446" , 0x1180080942d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1447" , 0x1180080942d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1448" , 0x1180080942d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1449" , 0x1180080942d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1450" , 0x1180080942d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1451" , 0x1180080942d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1452" , 0x1180080942d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1453" , 0x1180080942d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1454" , 0x1180080942d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1455" , 0x1180080942d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1456" , 0x1180080942d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1457" , 0x1180080942d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1458" , 0x1180080942d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1459" , 0x1180080942d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1460" , 0x1180080942da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1461" , 0x1180080942da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1462" , 0x1180080942db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1463" , 0x1180080942db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1464" , 0x1180080942dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1465" , 0x1180080942dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1466" , 0x1180080942dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1467" , 0x1180080942dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1468" , 0x1180080942de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1469" , 0x1180080942de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1470" , 0x1180080942df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1471" , 0x1180080942df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1472" , 0x1180080942e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1473" , 0x1180080942e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1474" , 0x1180080942e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1475" , 0x1180080942e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1476" , 0x1180080942e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1477" , 0x1180080942e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1478" , 0x1180080942e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1479" , 0x1180080942e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1480" , 0x1180080942e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1481" , 0x1180080942e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1482" , 0x1180080942e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1483" , 0x1180080942e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1484" , 0x1180080942e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1485" , 0x1180080942e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1486" , 0x1180080942e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1487" , 0x1180080942e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1488" , 0x1180080942e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1489" , 0x1180080942e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1490" , 0x1180080942e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1491" , 0x1180080942e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1492" , 0x1180080942ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1493" , 0x1180080942ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1494" , 0x1180080942eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1495" , 0x1180080942eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1496" , 0x1180080942ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1497" , 0x1180080942ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1498" , 0x1180080942ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1499" , 0x1180080942ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1500" , 0x1180080942ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1501" , 0x1180080942ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1502" , 0x1180080942ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1503" , 0x1180080942ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1504" , 0x1180080942f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1505" , 0x1180080942f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1506" , 0x1180080942f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1507" , 0x1180080942f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1508" , 0x1180080942f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1509" , 0x1180080942f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1510" , 0x1180080942f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1511" , 0x1180080942f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1512" , 0x1180080942f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1513" , 0x1180080942f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1514" , 0x1180080942f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1515" , 0x1180080942f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1516" , 0x1180080942f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1517" , 0x1180080942f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1518" , 0x1180080942f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1519" , 0x1180080942f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1520" , 0x1180080942f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1521" , 0x1180080942f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1522" , 0x1180080942f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1523" , 0x1180080942f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1524" , 0x1180080942fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1525" , 0x1180080942fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1526" , 0x1180080942fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1527" , 0x1180080942fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1528" , 0x1180080942fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1529" , 0x1180080942fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1530" , 0x1180080942fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1531" , 0x1180080942fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1532" , 0x1180080942fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1533" , 0x1180080942fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1534" , 0x1180080942ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP1535" , 0x1180080942ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16128" , 0x118008095f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16129" , 0x118008095f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16130" , 0x118008095f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16131" , 0x118008095f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16132" , 0x118008095f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16133" , 0x118008095f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16134" , 0x118008095f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16135" , 0x118008095f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16136" , 0x118008095f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16137" , 0x118008095f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16138" , 0x118008095f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16139" , 0x118008095f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16140" , 0x118008095f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16141" , 0x118008095f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16142" , 0x118008095f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16143" , 0x118008095f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16144" , 0x118008095f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16145" , 0x118008095f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16146" , 0x118008095f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16147" , 0x118008095f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16148" , 0x118008095f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16149" , 0x118008095f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16150" , 0x118008095f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16151" , 0x118008095f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16152" , 0x118008095f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16153" , 0x118008095f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16154" , 0x118008095f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16155" , 0x118008095f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16156" , 0x118008095f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16157" , 0x118008095f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16158" , 0x118008095f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16159" , 0x118008095f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16160" , 0x118008095f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16161" , 0x118008095f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16162" , 0x118008095f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16163" , 0x118008095f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16164" , 0x118008095f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16165" , 0x118008095f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16166" , 0x118008095f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16167" , 0x118008095f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16168" , 0x118008095f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16169" , 0x118008095f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16170" , 0x118008095f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16171" , 0x118008095f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16172" , 0x118008095f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16173" , 0x118008095f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16174" , 0x118008095f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16175" , 0x118008095f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16176" , 0x118008095f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16177" , 0x118008095f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16178" , 0x118008095f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16179" , 0x118008095f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16180" , 0x118008095f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16181" , 0x118008095f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16182" , 0x118008095f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16183" , 0x118008095f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16184" , 0x118008095f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16185" , 0x118008095f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16186" , 0x118008095f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16187" , 0x118008095f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16188" , 0x118008095f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16189" , 0x118008095f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16190" , 0x118008095f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16191" , 0x118008095f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16192" , 0x118008095fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16193" , 0x118008095fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16194" , 0x118008095fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16195" , 0x118008095fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16196" , 0x118008095fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16197" , 0x118008095fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16198" , 0x118008095fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16199" , 0x118008095fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16200" , 0x118008095fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16201" , 0x118008095fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16202" , 0x118008095fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16203" , 0x118008095fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16204" , 0x118008095fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16205" , 0x118008095fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16206" , 0x118008095fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16207" , 0x118008095fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16208" , 0x118008095fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16209" , 0x118008095fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16210" , 0x118008095fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16211" , 0x118008095fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16212" , 0x118008095faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16213" , 0x118008095faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16214" , 0x118008095fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16215" , 0x118008095fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16216" , 0x118008095fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16217" , 0x118008095fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16218" , 0x118008095fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16219" , 0x118008095fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16220" , 0x118008095fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16221" , 0x118008095fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16222" , 0x118008095faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16223" , 0x118008095faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16224" , 0x118008095fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16225" , 0x118008095fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16226" , 0x118008095fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16227" , 0x118008095fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16228" , 0x118008095fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16229" , 0x118008095fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16230" , 0x118008095fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16231" , 0x118008095fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16232" , 0x118008095fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16233" , 0x118008095fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16234" , 0x118008095fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16235" , 0x118008095fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16236" , 0x118008095fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16237" , 0x118008095fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16238" , 0x118008095fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16239" , 0x118008095fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16240" , 0x118008095fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16241" , 0x118008095fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16242" , 0x118008095fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16243" , 0x118008095fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16244" , 0x118008095fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16245" , 0x118008095fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16246" , 0x118008095fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16247" , 0x118008095fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16248" , 0x118008095fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16249" , 0x118008095fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16250" , 0x118008095fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16251" , 0x118008095fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16252" , 0x118008095fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16253" , 0x118008095fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16254" , 0x118008095fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16255" , 0x118008095fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16256" , 0x118008095fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16257" , 0x118008095fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16258" , 0x118008095fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16259" , 0x118008095fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16260" , 0x118008095fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16261" , 0x118008095fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16262" , 0x118008095fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16263" , 0x118008095fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16264" , 0x118008095fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16265" , 0x118008095fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16266" , 0x118008095fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16267" , 0x118008095fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16268" , 0x118008095fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16269" , 0x118008095fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16270" , 0x118008095fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16271" , 0x118008095fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16272" , 0x118008095fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16273" , 0x118008095fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16274" , 0x118008095fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16275" , 0x118008095fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16276" , 0x118008095fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16277" , 0x118008095fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16278" , 0x118008095fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16279" , 0x118008095fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16280" , 0x118008095fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16281" , 0x118008095fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16282" , 0x118008095fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16283" , 0x118008095fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16284" , 0x118008095fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16285" , 0x118008095fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16286" , 0x118008095fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16287" , 0x118008095fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16288" , 0x118008095fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16289" , 0x118008095fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16290" , 0x118008095fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16291" , 0x118008095fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16292" , 0x118008095fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16293" , 0x118008095fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16294" , 0x118008095fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16295" , 0x118008095fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16296" , 0x118008095fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16297" , 0x118008095fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16298" , 0x118008095fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16299" , 0x118008095fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16300" , 0x118008095fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16301" , 0x118008095fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16302" , 0x118008095fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16303" , 0x118008095fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16304" , 0x118008095fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16305" , 0x118008095fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16306" , 0x118008095fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16307" , 0x118008095fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16308" , 0x118008095fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16309" , 0x118008095fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16310" , 0x118008095fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16311" , 0x118008095fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16312" , 0x118008095fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16313" , 0x118008095fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16314" , 0x118008095fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16315" , 0x118008095fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16316" , 0x118008095fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16317" , 0x118008095fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16318" , 0x118008095fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16319" , 0x118008095fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16320" , 0x118008095fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16321" , 0x118008095fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16322" , 0x118008095fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16323" , 0x118008095fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16324" , 0x118008095fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16325" , 0x118008095fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16326" , 0x118008095fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16327" , 0x118008095fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16328" , 0x118008095fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16329" , 0x118008095fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16330" , 0x118008095fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16331" , 0x118008095fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16332" , 0x118008095fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16333" , 0x118008095fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16334" , 0x118008095fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16335" , 0x118008095fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16336" , 0x118008095fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16337" , 0x118008095fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16338" , 0x118008095fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16339" , 0x118008095fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16340" , 0x118008095fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16341" , 0x118008095fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16342" , 0x118008095feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16343" , 0x118008095feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16344" , 0x118008095fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16345" , 0x118008095fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16346" , 0x118008095fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16347" , 0x118008095fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16348" , 0x118008095fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16349" , 0x118008095fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16350" , 0x118008095fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16351" , 0x118008095fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16352" , 0x118008095ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16353" , 0x118008095ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16354" , 0x118008095ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16355" , 0x118008095ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16356" , 0x118008095ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16357" , 0x118008095ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16358" , 0x118008095ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16359" , 0x118008095ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16360" , 0x118008095ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16361" , 0x118008095ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16362" , 0x118008095ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16363" , 0x118008095ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16364" , 0x118008095ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16365" , 0x118008095ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16366" , 0x118008095ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16367" , 0x118008095ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16368" , 0x118008095ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16369" , 0x118008095ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16370" , 0x118008095ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16371" , 0x118008095ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16372" , 0x118008095ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16373" , 0x118008095ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16374" , 0x118008095ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16375" , 0x118008095ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16376" , 0x118008095ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16377" , 0x118008095ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16378" , 0x118008095ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16379" , 0x118008095ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16380" , 0x118008095ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16381" , 0x118008095ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16382" , 0x118008095fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_COP0_MAP16383" , 0x118008095fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"L2C_CTL" , 0x1180080800000ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"L2C_DUT_MAP0" , 0x1180080e00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1" , 0x1180080e00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP2" , 0x1180080e00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP3" , 0x1180080e00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP4" , 0x1180080e00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP5" , 0x1180080e00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP6" , 0x1180080e00030ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP7" , 0x1180080e00038ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP8" , 0x1180080e00040ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP9" , 0x1180080e00048ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP10" , 0x1180080e00050ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP11" , 0x1180080e00058ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP12" , 0x1180080e00060ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP13" , 0x1180080e00068ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP14" , 0x1180080e00070ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP15" , 0x1180080e00078ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP16" , 0x1180080e00080ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP17" , 0x1180080e00088ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP18" , 0x1180080e00090ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP19" , 0x1180080e00098ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP20" , 0x1180080e000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP21" , 0x1180080e000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP22" , 0x1180080e000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP23" , 0x1180080e000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP24" , 0x1180080e000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP25" , 0x1180080e000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP26" , 0x1180080e000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP27" , 0x1180080e000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP28" , 0x1180080e000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP29" , 0x1180080e000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP30" , 0x1180080e000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP31" , 0x1180080e000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP32" , 0x1180080e00100ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP33" , 0x1180080e00108ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP34" , 0x1180080e00110ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP35" , 0x1180080e00118ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP36" , 0x1180080e00120ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP37" , 0x1180080e00128ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP38" , 0x1180080e00130ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP39" , 0x1180080e00138ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP40" , 0x1180080e00140ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP41" , 0x1180080e00148ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP42" , 0x1180080e00150ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP43" , 0x1180080e00158ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP44" , 0x1180080e00160ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP45" , 0x1180080e00168ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP46" , 0x1180080e00170ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP47" , 0x1180080e00178ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP48" , 0x1180080e00180ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP49" , 0x1180080e00188ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP50" , 0x1180080e00190ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP51" , 0x1180080e00198ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP52" , 0x1180080e001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP53" , 0x1180080e001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP54" , 0x1180080e001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP55" , 0x1180080e001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP56" , 0x1180080e001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP57" , 0x1180080e001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP58" , 0x1180080e001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP59" , 0x1180080e001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP60" , 0x1180080e001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP61" , 0x1180080e001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP62" , 0x1180080e001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP63" , 0x1180080e001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP64" , 0x1180080e00200ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP65" , 0x1180080e00208ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP66" , 0x1180080e00210ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP67" , 0x1180080e00218ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP68" , 0x1180080e00220ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP69" , 0x1180080e00228ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP70" , 0x1180080e00230ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP71" , 0x1180080e00238ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP72" , 0x1180080e00240ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP73" , 0x1180080e00248ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP74" , 0x1180080e00250ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP75" , 0x1180080e00258ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP76" , 0x1180080e00260ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP77" , 0x1180080e00268ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP78" , 0x1180080e00270ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP79" , 0x1180080e00278ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP80" , 0x1180080e00280ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP81" , 0x1180080e00288ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP82" , 0x1180080e00290ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP83" , 0x1180080e00298ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP84" , 0x1180080e002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP85" , 0x1180080e002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP86" , 0x1180080e002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP87" , 0x1180080e002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP88" , 0x1180080e002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP89" , 0x1180080e002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP90" , 0x1180080e002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP91" , 0x1180080e002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP92" , 0x1180080e002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP93" , 0x1180080e002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP94" , 0x1180080e002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP95" , 0x1180080e002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP96" , 0x1180080e00300ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP97" , 0x1180080e00308ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP98" , 0x1180080e00310ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP99" , 0x1180080e00318ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP100" , 0x1180080e00320ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP101" , 0x1180080e00328ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP102" , 0x1180080e00330ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP103" , 0x1180080e00338ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP104" , 0x1180080e00340ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP105" , 0x1180080e00348ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP106" , 0x1180080e00350ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP107" , 0x1180080e00358ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP108" , 0x1180080e00360ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP109" , 0x1180080e00368ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP110" , 0x1180080e00370ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP111" , 0x1180080e00378ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP112" , 0x1180080e00380ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP113" , 0x1180080e00388ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP114" , 0x1180080e00390ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP115" , 0x1180080e00398ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP116" , 0x1180080e003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP117" , 0x1180080e003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP118" , 0x1180080e003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP119" , 0x1180080e003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP120" , 0x1180080e003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP121" , 0x1180080e003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP122" , 0x1180080e003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP123" , 0x1180080e003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP124" , 0x1180080e003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP125" , 0x1180080e003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP126" , 0x1180080e003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP127" , 0x1180080e003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP128" , 0x1180080e00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP129" , 0x1180080e00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP130" , 0x1180080e00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP131" , 0x1180080e00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP132" , 0x1180080e00420ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP133" , 0x1180080e00428ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP134" , 0x1180080e00430ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP135" , 0x1180080e00438ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP136" , 0x1180080e00440ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP137" , 0x1180080e00448ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP138" , 0x1180080e00450ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP139" , 0x1180080e00458ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP140" , 0x1180080e00460ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP141" , 0x1180080e00468ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP142" , 0x1180080e00470ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP143" , 0x1180080e00478ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP144" , 0x1180080e00480ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP145" , 0x1180080e00488ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP146" , 0x1180080e00490ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP147" , 0x1180080e00498ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP148" , 0x1180080e004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP149" , 0x1180080e004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP150" , 0x1180080e004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP151" , 0x1180080e004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP152" , 0x1180080e004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP153" , 0x1180080e004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP154" , 0x1180080e004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP155" , 0x1180080e004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP156" , 0x1180080e004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP157" , 0x1180080e004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP158" , 0x1180080e004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP159" , 0x1180080e004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP160" , 0x1180080e00500ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP161" , 0x1180080e00508ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP162" , 0x1180080e00510ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP163" , 0x1180080e00518ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP164" , 0x1180080e00520ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP165" , 0x1180080e00528ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP166" , 0x1180080e00530ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP167" , 0x1180080e00538ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP168" , 0x1180080e00540ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP169" , 0x1180080e00548ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP170" , 0x1180080e00550ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP171" , 0x1180080e00558ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP172" , 0x1180080e00560ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP173" , 0x1180080e00568ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP174" , 0x1180080e00570ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP175" , 0x1180080e00578ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP176" , 0x1180080e00580ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP177" , 0x1180080e00588ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP178" , 0x1180080e00590ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP179" , 0x1180080e00598ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP180" , 0x1180080e005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP181" , 0x1180080e005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP182" , 0x1180080e005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP183" , 0x1180080e005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP184" , 0x1180080e005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP185" , 0x1180080e005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP186" , 0x1180080e005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP187" , 0x1180080e005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP188" , 0x1180080e005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP189" , 0x1180080e005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP190" , 0x1180080e005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP191" , 0x1180080e005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP192" , 0x1180080e00600ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP193" , 0x1180080e00608ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP194" , 0x1180080e00610ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP195" , 0x1180080e00618ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP196" , 0x1180080e00620ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP197" , 0x1180080e00628ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP198" , 0x1180080e00630ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP199" , 0x1180080e00638ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP200" , 0x1180080e00640ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP201" , 0x1180080e00648ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP202" , 0x1180080e00650ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP203" , 0x1180080e00658ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP204" , 0x1180080e00660ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP205" , 0x1180080e00668ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP206" , 0x1180080e00670ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP207" , 0x1180080e00678ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP208" , 0x1180080e00680ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP209" , 0x1180080e00688ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP210" , 0x1180080e00690ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP211" , 0x1180080e00698ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP212" , 0x1180080e006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP213" , 0x1180080e006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP214" , 0x1180080e006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP215" , 0x1180080e006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP216" , 0x1180080e006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP217" , 0x1180080e006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP218" , 0x1180080e006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP219" , 0x1180080e006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP220" , 0x1180080e006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP221" , 0x1180080e006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP222" , 0x1180080e006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP223" , 0x1180080e006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP224" , 0x1180080e00700ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP225" , 0x1180080e00708ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP226" , 0x1180080e00710ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP227" , 0x1180080e00718ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP228" , 0x1180080e00720ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP229" , 0x1180080e00728ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP230" , 0x1180080e00730ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP231" , 0x1180080e00738ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP232" , 0x1180080e00740ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP233" , 0x1180080e00748ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP234" , 0x1180080e00750ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP235" , 0x1180080e00758ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP236" , 0x1180080e00760ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP237" , 0x1180080e00768ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP238" , 0x1180080e00770ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP239" , 0x1180080e00778ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP240" , 0x1180080e00780ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP241" , 0x1180080e00788ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP242" , 0x1180080e00790ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP243" , 0x1180080e00798ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP244" , 0x1180080e007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP245" , 0x1180080e007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP246" , 0x1180080e007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP247" , 0x1180080e007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP248" , 0x1180080e007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP249" , 0x1180080e007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP250" , 0x1180080e007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP251" , 0x1180080e007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP252" , 0x1180080e007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP253" , 0x1180080e007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP254" , 0x1180080e007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP255" , 0x1180080e007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP256" , 0x1180080e00800ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP257" , 0x1180080e00808ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP258" , 0x1180080e00810ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP259" , 0x1180080e00818ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP260" , 0x1180080e00820ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP261" , 0x1180080e00828ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP262" , 0x1180080e00830ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP263" , 0x1180080e00838ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP264" , 0x1180080e00840ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP265" , 0x1180080e00848ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP266" , 0x1180080e00850ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP267" , 0x1180080e00858ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP268" , 0x1180080e00860ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP269" , 0x1180080e00868ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP270" , 0x1180080e00870ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP271" , 0x1180080e00878ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP272" , 0x1180080e00880ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP273" , 0x1180080e00888ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP274" , 0x1180080e00890ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP275" , 0x1180080e00898ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP276" , 0x1180080e008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP277" , 0x1180080e008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP278" , 0x1180080e008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP279" , 0x1180080e008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP280" , 0x1180080e008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP281" , 0x1180080e008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP282" , 0x1180080e008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP283" , 0x1180080e008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP284" , 0x1180080e008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP285" , 0x1180080e008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP286" , 0x1180080e008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP287" , 0x1180080e008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP288" , 0x1180080e00900ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP289" , 0x1180080e00908ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP290" , 0x1180080e00910ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP291" , 0x1180080e00918ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP292" , 0x1180080e00920ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP293" , 0x1180080e00928ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP294" , 0x1180080e00930ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP295" , 0x1180080e00938ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP296" , 0x1180080e00940ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP297" , 0x1180080e00948ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP298" , 0x1180080e00950ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP299" , 0x1180080e00958ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP300" , 0x1180080e00960ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP301" , 0x1180080e00968ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP302" , 0x1180080e00970ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP303" , 0x1180080e00978ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP304" , 0x1180080e00980ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP305" , 0x1180080e00988ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP306" , 0x1180080e00990ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP307" , 0x1180080e00998ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP308" , 0x1180080e009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP309" , 0x1180080e009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP310" , 0x1180080e009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP311" , 0x1180080e009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP312" , 0x1180080e009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP313" , 0x1180080e009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP314" , 0x1180080e009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP315" , 0x1180080e009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP316" , 0x1180080e009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP317" , 0x1180080e009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP318" , 0x1180080e009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP319" , 0x1180080e009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP320" , 0x1180080e00a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP321" , 0x1180080e00a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP322" , 0x1180080e00a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP323" , 0x1180080e00a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP324" , 0x1180080e00a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP325" , 0x1180080e00a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP326" , 0x1180080e00a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP327" , 0x1180080e00a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP328" , 0x1180080e00a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP329" , 0x1180080e00a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP330" , 0x1180080e00a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP331" , 0x1180080e00a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP332" , 0x1180080e00a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP333" , 0x1180080e00a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP334" , 0x1180080e00a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP335" , 0x1180080e00a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP336" , 0x1180080e00a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP337" , 0x1180080e00a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP338" , 0x1180080e00a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP339" , 0x1180080e00a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP340" , 0x1180080e00aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP341" , 0x1180080e00aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP342" , 0x1180080e00ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP343" , 0x1180080e00ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP344" , 0x1180080e00ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP345" , 0x1180080e00ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP346" , 0x1180080e00ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP347" , 0x1180080e00ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP348" , 0x1180080e00ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP349" , 0x1180080e00ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP350" , 0x1180080e00af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP351" , 0x1180080e00af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP352" , 0x1180080e00b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP353" , 0x1180080e00b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP354" , 0x1180080e00b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP355" , 0x1180080e00b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP356" , 0x1180080e00b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP357" , 0x1180080e00b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP358" , 0x1180080e00b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP359" , 0x1180080e00b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP360" , 0x1180080e00b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP361" , 0x1180080e00b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP362" , 0x1180080e00b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP363" , 0x1180080e00b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP364" , 0x1180080e00b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP365" , 0x1180080e00b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP366" , 0x1180080e00b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP367" , 0x1180080e00b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP368" , 0x1180080e00b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP369" , 0x1180080e00b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP370" , 0x1180080e00b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP371" , 0x1180080e00b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP372" , 0x1180080e00ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP373" , 0x1180080e00ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP374" , 0x1180080e00bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP375" , 0x1180080e00bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP376" , 0x1180080e00bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP377" , 0x1180080e00bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP378" , 0x1180080e00bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP379" , 0x1180080e00bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP380" , 0x1180080e00be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP381" , 0x1180080e00be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP382" , 0x1180080e00bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP383" , 0x1180080e00bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP384" , 0x1180080e00c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP385" , 0x1180080e00c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP386" , 0x1180080e00c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP387" , 0x1180080e00c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP388" , 0x1180080e00c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP389" , 0x1180080e00c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP390" , 0x1180080e00c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP391" , 0x1180080e00c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP392" , 0x1180080e00c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP393" , 0x1180080e00c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP394" , 0x1180080e00c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP395" , 0x1180080e00c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP396" , 0x1180080e00c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP397" , 0x1180080e00c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP398" , 0x1180080e00c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP399" , 0x1180080e00c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP400" , 0x1180080e00c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP401" , 0x1180080e00c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP402" , 0x1180080e00c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP403" , 0x1180080e00c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP404" , 0x1180080e00ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP405" , 0x1180080e00ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP406" , 0x1180080e00cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP407" , 0x1180080e00cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP408" , 0x1180080e00cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP409" , 0x1180080e00cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP410" , 0x1180080e00cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP411" , 0x1180080e00cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP412" , 0x1180080e00ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP413" , 0x1180080e00ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP414" , 0x1180080e00cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP415" , 0x1180080e00cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP416" , 0x1180080e00d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP417" , 0x1180080e00d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP418" , 0x1180080e00d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP419" , 0x1180080e00d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP420" , 0x1180080e00d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP421" , 0x1180080e00d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP422" , 0x1180080e00d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP423" , 0x1180080e00d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP424" , 0x1180080e00d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP425" , 0x1180080e00d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP426" , 0x1180080e00d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP427" , 0x1180080e00d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP428" , 0x1180080e00d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP429" , 0x1180080e00d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP430" , 0x1180080e00d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP431" , 0x1180080e00d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP432" , 0x1180080e00d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP433" , 0x1180080e00d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP434" , 0x1180080e00d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP435" , 0x1180080e00d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP436" , 0x1180080e00da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP437" , 0x1180080e00da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP438" , 0x1180080e00db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP439" , 0x1180080e00db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP440" , 0x1180080e00dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP441" , 0x1180080e00dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP442" , 0x1180080e00dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP443" , 0x1180080e00dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP444" , 0x1180080e00de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP445" , 0x1180080e00de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP446" , 0x1180080e00df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP447" , 0x1180080e00df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP448" , 0x1180080e00e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP449" , 0x1180080e00e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP450" , 0x1180080e00e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP451" , 0x1180080e00e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP452" , 0x1180080e00e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP453" , 0x1180080e00e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP454" , 0x1180080e00e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP455" , 0x1180080e00e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP456" , 0x1180080e00e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP457" , 0x1180080e00e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP458" , 0x1180080e00e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP459" , 0x1180080e00e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP460" , 0x1180080e00e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP461" , 0x1180080e00e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP462" , 0x1180080e00e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP463" , 0x1180080e00e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP464" , 0x1180080e00e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP465" , 0x1180080e00e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP466" , 0x1180080e00e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP467" , 0x1180080e00e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP468" , 0x1180080e00ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP469" , 0x1180080e00ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP470" , 0x1180080e00eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP471" , 0x1180080e00eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP472" , 0x1180080e00ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP473" , 0x1180080e00ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP474" , 0x1180080e00ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP475" , 0x1180080e00ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP476" , 0x1180080e00ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP477" , 0x1180080e00ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP478" , 0x1180080e00ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP479" , 0x1180080e00ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP480" , 0x1180080e00f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP481" , 0x1180080e00f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP482" , 0x1180080e00f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP483" , 0x1180080e00f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP484" , 0x1180080e00f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP485" , 0x1180080e00f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP486" , 0x1180080e00f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP487" , 0x1180080e00f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP488" , 0x1180080e00f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP489" , 0x1180080e00f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP490" , 0x1180080e00f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP491" , 0x1180080e00f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP492" , 0x1180080e00f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP493" , 0x1180080e00f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP494" , 0x1180080e00f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP495" , 0x1180080e00f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP496" , 0x1180080e00f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP497" , 0x1180080e00f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP498" , 0x1180080e00f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP499" , 0x1180080e00f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP500" , 0x1180080e00fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP501" , 0x1180080e00fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP502" , 0x1180080e00fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP503" , 0x1180080e00fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP504" , 0x1180080e00fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP505" , 0x1180080e00fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP506" , 0x1180080e00fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP507" , 0x1180080e00fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP508" , 0x1180080e00fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP509" , 0x1180080e00fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP510" , 0x1180080e00ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP511" , 0x1180080e00ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP512" , 0x1180080e01000ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP513" , 0x1180080e01008ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP514" , 0x1180080e01010ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP515" , 0x1180080e01018ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP516" , 0x1180080e01020ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP517" , 0x1180080e01028ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP518" , 0x1180080e01030ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP519" , 0x1180080e01038ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP520" , 0x1180080e01040ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP521" , 0x1180080e01048ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP522" , 0x1180080e01050ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP523" , 0x1180080e01058ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP524" , 0x1180080e01060ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP525" , 0x1180080e01068ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP526" , 0x1180080e01070ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP527" , 0x1180080e01078ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP528" , 0x1180080e01080ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP529" , 0x1180080e01088ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP530" , 0x1180080e01090ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP531" , 0x1180080e01098ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP532" , 0x1180080e010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP533" , 0x1180080e010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP534" , 0x1180080e010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP535" , 0x1180080e010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP536" , 0x1180080e010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP537" , 0x1180080e010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP538" , 0x1180080e010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP539" , 0x1180080e010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP540" , 0x1180080e010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP541" , 0x1180080e010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP542" , 0x1180080e010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP543" , 0x1180080e010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP544" , 0x1180080e01100ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP545" , 0x1180080e01108ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP546" , 0x1180080e01110ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP547" , 0x1180080e01118ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP548" , 0x1180080e01120ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP549" , 0x1180080e01128ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP550" , 0x1180080e01130ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP551" , 0x1180080e01138ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP552" , 0x1180080e01140ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP553" , 0x1180080e01148ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP554" , 0x1180080e01150ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP555" , 0x1180080e01158ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP556" , 0x1180080e01160ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP557" , 0x1180080e01168ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP558" , 0x1180080e01170ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP559" , 0x1180080e01178ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP560" , 0x1180080e01180ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP561" , 0x1180080e01188ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP562" , 0x1180080e01190ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP563" , 0x1180080e01198ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP564" , 0x1180080e011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP565" , 0x1180080e011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP566" , 0x1180080e011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP567" , 0x1180080e011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP568" , 0x1180080e011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP569" , 0x1180080e011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP570" , 0x1180080e011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP571" , 0x1180080e011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP572" , 0x1180080e011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP573" , 0x1180080e011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP574" , 0x1180080e011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP575" , 0x1180080e011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP576" , 0x1180080e01200ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP577" , 0x1180080e01208ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP578" , 0x1180080e01210ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP579" , 0x1180080e01218ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP580" , 0x1180080e01220ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP581" , 0x1180080e01228ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP582" , 0x1180080e01230ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP583" , 0x1180080e01238ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP584" , 0x1180080e01240ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP585" , 0x1180080e01248ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP586" , 0x1180080e01250ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP587" , 0x1180080e01258ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP588" , 0x1180080e01260ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP589" , 0x1180080e01268ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP590" , 0x1180080e01270ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP591" , 0x1180080e01278ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP592" , 0x1180080e01280ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP593" , 0x1180080e01288ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP594" , 0x1180080e01290ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP595" , 0x1180080e01298ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP596" , 0x1180080e012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP597" , 0x1180080e012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP598" , 0x1180080e012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP599" , 0x1180080e012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP600" , 0x1180080e012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP601" , 0x1180080e012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP602" , 0x1180080e012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP603" , 0x1180080e012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP604" , 0x1180080e012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP605" , 0x1180080e012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP606" , 0x1180080e012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP607" , 0x1180080e012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP608" , 0x1180080e01300ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP609" , 0x1180080e01308ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP610" , 0x1180080e01310ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP611" , 0x1180080e01318ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP612" , 0x1180080e01320ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP613" , 0x1180080e01328ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP614" , 0x1180080e01330ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP615" , 0x1180080e01338ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP616" , 0x1180080e01340ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP617" , 0x1180080e01348ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP618" , 0x1180080e01350ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP619" , 0x1180080e01358ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP620" , 0x1180080e01360ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP621" , 0x1180080e01368ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP622" , 0x1180080e01370ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP623" , 0x1180080e01378ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP624" , 0x1180080e01380ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP625" , 0x1180080e01388ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP626" , 0x1180080e01390ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP627" , 0x1180080e01398ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP628" , 0x1180080e013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP629" , 0x1180080e013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP630" , 0x1180080e013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP631" , 0x1180080e013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP632" , 0x1180080e013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP633" , 0x1180080e013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP634" , 0x1180080e013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP635" , 0x1180080e013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP636" , 0x1180080e013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP637" , 0x1180080e013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP638" , 0x1180080e013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP639" , 0x1180080e013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP640" , 0x1180080e01400ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP641" , 0x1180080e01408ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP642" , 0x1180080e01410ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP643" , 0x1180080e01418ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP644" , 0x1180080e01420ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP645" , 0x1180080e01428ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP646" , 0x1180080e01430ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP647" , 0x1180080e01438ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP648" , 0x1180080e01440ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP649" , 0x1180080e01448ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP650" , 0x1180080e01450ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP651" , 0x1180080e01458ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP652" , 0x1180080e01460ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP653" , 0x1180080e01468ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP654" , 0x1180080e01470ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP655" , 0x1180080e01478ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP656" , 0x1180080e01480ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP657" , 0x1180080e01488ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP658" , 0x1180080e01490ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP659" , 0x1180080e01498ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP660" , 0x1180080e014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP661" , 0x1180080e014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP662" , 0x1180080e014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP663" , 0x1180080e014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP664" , 0x1180080e014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP665" , 0x1180080e014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP666" , 0x1180080e014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP667" , 0x1180080e014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP668" , 0x1180080e014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP669" , 0x1180080e014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP670" , 0x1180080e014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP671" , 0x1180080e014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP672" , 0x1180080e01500ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP673" , 0x1180080e01508ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP674" , 0x1180080e01510ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP675" , 0x1180080e01518ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP676" , 0x1180080e01520ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP677" , 0x1180080e01528ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP678" , 0x1180080e01530ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP679" , 0x1180080e01538ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP680" , 0x1180080e01540ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP681" , 0x1180080e01548ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP682" , 0x1180080e01550ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP683" , 0x1180080e01558ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP684" , 0x1180080e01560ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP685" , 0x1180080e01568ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP686" , 0x1180080e01570ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP687" , 0x1180080e01578ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP688" , 0x1180080e01580ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP689" , 0x1180080e01588ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP690" , 0x1180080e01590ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP691" , 0x1180080e01598ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP692" , 0x1180080e015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP693" , 0x1180080e015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP694" , 0x1180080e015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP695" , 0x1180080e015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP696" , 0x1180080e015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP697" , 0x1180080e015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP698" , 0x1180080e015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP699" , 0x1180080e015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP700" , 0x1180080e015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP701" , 0x1180080e015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP702" , 0x1180080e015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP703" , 0x1180080e015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP704" , 0x1180080e01600ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP705" , 0x1180080e01608ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP706" , 0x1180080e01610ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP707" , 0x1180080e01618ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP708" , 0x1180080e01620ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP709" , 0x1180080e01628ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP710" , 0x1180080e01630ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP711" , 0x1180080e01638ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP712" , 0x1180080e01640ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP713" , 0x1180080e01648ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP714" , 0x1180080e01650ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP715" , 0x1180080e01658ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP716" , 0x1180080e01660ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP717" , 0x1180080e01668ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP718" , 0x1180080e01670ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP719" , 0x1180080e01678ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP720" , 0x1180080e01680ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP721" , 0x1180080e01688ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP722" , 0x1180080e01690ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP723" , 0x1180080e01698ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP724" , 0x1180080e016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP725" , 0x1180080e016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP726" , 0x1180080e016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP727" , 0x1180080e016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP728" , 0x1180080e016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP729" , 0x1180080e016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP730" , 0x1180080e016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP731" , 0x1180080e016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP732" , 0x1180080e016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP733" , 0x1180080e016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP734" , 0x1180080e016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP735" , 0x1180080e016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP736" , 0x1180080e01700ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP737" , 0x1180080e01708ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP738" , 0x1180080e01710ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP739" , 0x1180080e01718ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP740" , 0x1180080e01720ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP741" , 0x1180080e01728ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP742" , 0x1180080e01730ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP743" , 0x1180080e01738ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP744" , 0x1180080e01740ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP745" , 0x1180080e01748ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP746" , 0x1180080e01750ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP747" , 0x1180080e01758ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP748" , 0x1180080e01760ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP749" , 0x1180080e01768ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP750" , 0x1180080e01770ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP751" , 0x1180080e01778ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP752" , 0x1180080e01780ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP753" , 0x1180080e01788ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP754" , 0x1180080e01790ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP755" , 0x1180080e01798ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP756" , 0x1180080e017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP757" , 0x1180080e017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP758" , 0x1180080e017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP759" , 0x1180080e017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP760" , 0x1180080e017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP761" , 0x1180080e017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP762" , 0x1180080e017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP763" , 0x1180080e017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP764" , 0x1180080e017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP765" , 0x1180080e017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP766" , 0x1180080e017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP767" , 0x1180080e017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP768" , 0x1180080e01800ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP769" , 0x1180080e01808ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP770" , 0x1180080e01810ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP771" , 0x1180080e01818ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP772" , 0x1180080e01820ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP773" , 0x1180080e01828ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP774" , 0x1180080e01830ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP775" , 0x1180080e01838ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP776" , 0x1180080e01840ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP777" , 0x1180080e01848ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP778" , 0x1180080e01850ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP779" , 0x1180080e01858ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP780" , 0x1180080e01860ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP781" , 0x1180080e01868ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP782" , 0x1180080e01870ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP783" , 0x1180080e01878ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP784" , 0x1180080e01880ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP785" , 0x1180080e01888ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP786" , 0x1180080e01890ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP787" , 0x1180080e01898ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP788" , 0x1180080e018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP789" , 0x1180080e018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP790" , 0x1180080e018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP791" , 0x1180080e018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP792" , 0x1180080e018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP793" , 0x1180080e018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP794" , 0x1180080e018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP795" , 0x1180080e018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP796" , 0x1180080e018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP797" , 0x1180080e018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP798" , 0x1180080e018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP799" , 0x1180080e018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP800" , 0x1180080e01900ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP801" , 0x1180080e01908ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP802" , 0x1180080e01910ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP803" , 0x1180080e01918ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP804" , 0x1180080e01920ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP805" , 0x1180080e01928ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP806" , 0x1180080e01930ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP807" , 0x1180080e01938ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP808" , 0x1180080e01940ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP809" , 0x1180080e01948ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP810" , 0x1180080e01950ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP811" , 0x1180080e01958ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP812" , 0x1180080e01960ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP813" , 0x1180080e01968ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP814" , 0x1180080e01970ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP815" , 0x1180080e01978ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP816" , 0x1180080e01980ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP817" , 0x1180080e01988ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP818" , 0x1180080e01990ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP819" , 0x1180080e01998ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP820" , 0x1180080e019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP821" , 0x1180080e019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP822" , 0x1180080e019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP823" , 0x1180080e019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP824" , 0x1180080e019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP825" , 0x1180080e019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP826" , 0x1180080e019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP827" , 0x1180080e019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP828" , 0x1180080e019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP829" , 0x1180080e019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP830" , 0x1180080e019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP831" , 0x1180080e019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP832" , 0x1180080e01a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP833" , 0x1180080e01a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP834" , 0x1180080e01a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP835" , 0x1180080e01a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP836" , 0x1180080e01a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP837" , 0x1180080e01a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP838" , 0x1180080e01a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP839" , 0x1180080e01a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP840" , 0x1180080e01a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP841" , 0x1180080e01a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP842" , 0x1180080e01a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP843" , 0x1180080e01a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP844" , 0x1180080e01a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP845" , 0x1180080e01a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP846" , 0x1180080e01a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP847" , 0x1180080e01a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP848" , 0x1180080e01a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP849" , 0x1180080e01a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP850" , 0x1180080e01a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP851" , 0x1180080e01a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP852" , 0x1180080e01aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP853" , 0x1180080e01aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP854" , 0x1180080e01ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP855" , 0x1180080e01ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP856" , 0x1180080e01ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP857" , 0x1180080e01ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP858" , 0x1180080e01ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP859" , 0x1180080e01ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP860" , 0x1180080e01ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP861" , 0x1180080e01ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP862" , 0x1180080e01af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP863" , 0x1180080e01af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP864" , 0x1180080e01b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP865" , 0x1180080e01b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP866" , 0x1180080e01b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP867" , 0x1180080e01b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP868" , 0x1180080e01b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP869" , 0x1180080e01b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP870" , 0x1180080e01b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP871" , 0x1180080e01b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP872" , 0x1180080e01b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP873" , 0x1180080e01b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP874" , 0x1180080e01b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP875" , 0x1180080e01b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP876" , 0x1180080e01b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP877" , 0x1180080e01b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP878" , 0x1180080e01b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP879" , 0x1180080e01b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP880" , 0x1180080e01b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP881" , 0x1180080e01b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP882" , 0x1180080e01b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP883" , 0x1180080e01b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP884" , 0x1180080e01ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP885" , 0x1180080e01ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP886" , 0x1180080e01bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP887" , 0x1180080e01bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP888" , 0x1180080e01bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP889" , 0x1180080e01bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP890" , 0x1180080e01bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP891" , 0x1180080e01bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP892" , 0x1180080e01be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP893" , 0x1180080e01be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP894" , 0x1180080e01bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP895" , 0x1180080e01bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP896" , 0x1180080e01c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP897" , 0x1180080e01c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP898" , 0x1180080e01c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP899" , 0x1180080e01c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP900" , 0x1180080e01c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP901" , 0x1180080e01c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP902" , 0x1180080e01c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP903" , 0x1180080e01c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP904" , 0x1180080e01c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP905" , 0x1180080e01c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP906" , 0x1180080e01c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP907" , 0x1180080e01c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP908" , 0x1180080e01c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP909" , 0x1180080e01c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP910" , 0x1180080e01c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP911" , 0x1180080e01c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP912" , 0x1180080e01c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP913" , 0x1180080e01c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP914" , 0x1180080e01c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP915" , 0x1180080e01c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP916" , 0x1180080e01ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP917" , 0x1180080e01ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP918" , 0x1180080e01cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP919" , 0x1180080e01cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP920" , 0x1180080e01cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP921" , 0x1180080e01cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP922" , 0x1180080e01cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP923" , 0x1180080e01cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP924" , 0x1180080e01ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP925" , 0x1180080e01ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP926" , 0x1180080e01cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP927" , 0x1180080e01cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP928" , 0x1180080e01d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP929" , 0x1180080e01d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP930" , 0x1180080e01d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP931" , 0x1180080e01d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP932" , 0x1180080e01d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP933" , 0x1180080e01d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP934" , 0x1180080e01d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP935" , 0x1180080e01d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP936" , 0x1180080e01d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP937" , 0x1180080e01d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP938" , 0x1180080e01d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP939" , 0x1180080e01d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP940" , 0x1180080e01d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP941" , 0x1180080e01d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP942" , 0x1180080e01d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP943" , 0x1180080e01d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP944" , 0x1180080e01d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP945" , 0x1180080e01d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP946" , 0x1180080e01d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP947" , 0x1180080e01d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP948" , 0x1180080e01da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP949" , 0x1180080e01da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP950" , 0x1180080e01db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP951" , 0x1180080e01db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP952" , 0x1180080e01dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP953" , 0x1180080e01dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP954" , 0x1180080e01dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP955" , 0x1180080e01dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP956" , 0x1180080e01de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP957" , 0x1180080e01de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP958" , 0x1180080e01df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP959" , 0x1180080e01df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP960" , 0x1180080e01e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP961" , 0x1180080e01e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP962" , 0x1180080e01e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP963" , 0x1180080e01e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP964" , 0x1180080e01e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP965" , 0x1180080e01e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP966" , 0x1180080e01e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP967" , 0x1180080e01e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP968" , 0x1180080e01e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP969" , 0x1180080e01e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP970" , 0x1180080e01e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP971" , 0x1180080e01e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP972" , 0x1180080e01e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP973" , 0x1180080e01e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP974" , 0x1180080e01e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP975" , 0x1180080e01e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP976" , 0x1180080e01e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP977" , 0x1180080e01e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP978" , 0x1180080e01e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP979" , 0x1180080e01e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP980" , 0x1180080e01ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP981" , 0x1180080e01ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP982" , 0x1180080e01eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP983" , 0x1180080e01eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP984" , 0x1180080e01ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP985" , 0x1180080e01ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP986" , 0x1180080e01ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP987" , 0x1180080e01ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP988" , 0x1180080e01ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP989" , 0x1180080e01ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP990" , 0x1180080e01ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP991" , 0x1180080e01ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP992" , 0x1180080e01f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP993" , 0x1180080e01f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP994" , 0x1180080e01f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP995" , 0x1180080e01f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP996" , 0x1180080e01f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP997" , 0x1180080e01f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP998" , 0x1180080e01f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP999" , 0x1180080e01f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1000" , 0x1180080e01f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1001" , 0x1180080e01f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1002" , 0x1180080e01f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1003" , 0x1180080e01f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1004" , 0x1180080e01f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1005" , 0x1180080e01f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1006" , 0x1180080e01f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1007" , 0x1180080e01f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1008" , 0x1180080e01f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1009" , 0x1180080e01f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1010" , 0x1180080e01f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1011" , 0x1180080e01f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1012" , 0x1180080e01fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1013" , 0x1180080e01fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1014" , 0x1180080e01fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1015" , 0x1180080e01fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1016" , 0x1180080e01fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1017" , 0x1180080e01fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1018" , 0x1180080e01fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1019" , 0x1180080e01fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1020" , 0x1180080e01fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1021" , 0x1180080e01fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1022" , 0x1180080e01ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1023" , 0x1180080e01ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1024" , 0x1180080e02000ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1025" , 0x1180080e02008ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1026" , 0x1180080e02010ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1027" , 0x1180080e02018ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1028" , 0x1180080e02020ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1029" , 0x1180080e02028ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1030" , 0x1180080e02030ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1031" , 0x1180080e02038ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1032" , 0x1180080e02040ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1033" , 0x1180080e02048ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1034" , 0x1180080e02050ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1035" , 0x1180080e02058ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1036" , 0x1180080e02060ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1037" , 0x1180080e02068ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1038" , 0x1180080e02070ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1039" , 0x1180080e02078ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1040" , 0x1180080e02080ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1041" , 0x1180080e02088ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1042" , 0x1180080e02090ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1043" , 0x1180080e02098ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1044" , 0x1180080e020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1045" , 0x1180080e020a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1046" , 0x1180080e020b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1047" , 0x1180080e020b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1048" , 0x1180080e020c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1049" , 0x1180080e020c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1050" , 0x1180080e020d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1051" , 0x1180080e020d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1052" , 0x1180080e020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1053" , 0x1180080e020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1054" , 0x1180080e020f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1055" , 0x1180080e020f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1056" , 0x1180080e02100ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1057" , 0x1180080e02108ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1058" , 0x1180080e02110ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1059" , 0x1180080e02118ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1060" , 0x1180080e02120ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1061" , 0x1180080e02128ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1062" , 0x1180080e02130ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1063" , 0x1180080e02138ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1064" , 0x1180080e02140ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1065" , 0x1180080e02148ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1066" , 0x1180080e02150ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1067" , 0x1180080e02158ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1068" , 0x1180080e02160ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1069" , 0x1180080e02168ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1070" , 0x1180080e02170ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1071" , 0x1180080e02178ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1072" , 0x1180080e02180ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1073" , 0x1180080e02188ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1074" , 0x1180080e02190ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1075" , 0x1180080e02198ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1076" , 0x1180080e021a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1077" , 0x1180080e021a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1078" , 0x1180080e021b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1079" , 0x1180080e021b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1080" , 0x1180080e021c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1081" , 0x1180080e021c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1082" , 0x1180080e021d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1083" , 0x1180080e021d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1084" , 0x1180080e021e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1085" , 0x1180080e021e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1086" , 0x1180080e021f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1087" , 0x1180080e021f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1088" , 0x1180080e02200ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1089" , 0x1180080e02208ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1090" , 0x1180080e02210ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1091" , 0x1180080e02218ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1092" , 0x1180080e02220ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1093" , 0x1180080e02228ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1094" , 0x1180080e02230ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1095" , 0x1180080e02238ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1096" , 0x1180080e02240ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1097" , 0x1180080e02248ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1098" , 0x1180080e02250ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1099" , 0x1180080e02258ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1100" , 0x1180080e02260ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1101" , 0x1180080e02268ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1102" , 0x1180080e02270ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1103" , 0x1180080e02278ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1104" , 0x1180080e02280ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1105" , 0x1180080e02288ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1106" , 0x1180080e02290ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1107" , 0x1180080e02298ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1108" , 0x1180080e022a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1109" , 0x1180080e022a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1110" , 0x1180080e022b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1111" , 0x1180080e022b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1112" , 0x1180080e022c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1113" , 0x1180080e022c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1114" , 0x1180080e022d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1115" , 0x1180080e022d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1116" , 0x1180080e022e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1117" , 0x1180080e022e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1118" , 0x1180080e022f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1119" , 0x1180080e022f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1120" , 0x1180080e02300ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1121" , 0x1180080e02308ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1122" , 0x1180080e02310ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1123" , 0x1180080e02318ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1124" , 0x1180080e02320ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1125" , 0x1180080e02328ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1126" , 0x1180080e02330ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1127" , 0x1180080e02338ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1128" , 0x1180080e02340ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1129" , 0x1180080e02348ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1130" , 0x1180080e02350ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1131" , 0x1180080e02358ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1132" , 0x1180080e02360ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1133" , 0x1180080e02368ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1134" , 0x1180080e02370ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1135" , 0x1180080e02378ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1136" , 0x1180080e02380ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1137" , 0x1180080e02388ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1138" , 0x1180080e02390ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1139" , 0x1180080e02398ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1140" , 0x1180080e023a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1141" , 0x1180080e023a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1142" , 0x1180080e023b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1143" , 0x1180080e023b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1144" , 0x1180080e023c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1145" , 0x1180080e023c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1146" , 0x1180080e023d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1147" , 0x1180080e023d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1148" , 0x1180080e023e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1149" , 0x1180080e023e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1150" , 0x1180080e023f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1151" , 0x1180080e023f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1152" , 0x1180080e02400ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1153" , 0x1180080e02408ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1154" , 0x1180080e02410ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1155" , 0x1180080e02418ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1156" , 0x1180080e02420ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1157" , 0x1180080e02428ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1158" , 0x1180080e02430ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1159" , 0x1180080e02438ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1160" , 0x1180080e02440ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1161" , 0x1180080e02448ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1162" , 0x1180080e02450ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1163" , 0x1180080e02458ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1164" , 0x1180080e02460ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1165" , 0x1180080e02468ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1166" , 0x1180080e02470ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1167" , 0x1180080e02478ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1168" , 0x1180080e02480ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1169" , 0x1180080e02488ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1170" , 0x1180080e02490ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1171" , 0x1180080e02498ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1172" , 0x1180080e024a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1173" , 0x1180080e024a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1174" , 0x1180080e024b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1175" , 0x1180080e024b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1176" , 0x1180080e024c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1177" , 0x1180080e024c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1178" , 0x1180080e024d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1179" , 0x1180080e024d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1180" , 0x1180080e024e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1181" , 0x1180080e024e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1182" , 0x1180080e024f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1183" , 0x1180080e024f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1184" , 0x1180080e02500ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1185" , 0x1180080e02508ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1186" , 0x1180080e02510ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1187" , 0x1180080e02518ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1188" , 0x1180080e02520ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1189" , 0x1180080e02528ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1190" , 0x1180080e02530ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1191" , 0x1180080e02538ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1192" , 0x1180080e02540ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1193" , 0x1180080e02548ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1194" , 0x1180080e02550ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1195" , 0x1180080e02558ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1196" , 0x1180080e02560ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1197" , 0x1180080e02568ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1198" , 0x1180080e02570ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1199" , 0x1180080e02578ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1200" , 0x1180080e02580ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1201" , 0x1180080e02588ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1202" , 0x1180080e02590ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1203" , 0x1180080e02598ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1204" , 0x1180080e025a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1205" , 0x1180080e025a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1206" , 0x1180080e025b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1207" , 0x1180080e025b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1208" , 0x1180080e025c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1209" , 0x1180080e025c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1210" , 0x1180080e025d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1211" , 0x1180080e025d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1212" , 0x1180080e025e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1213" , 0x1180080e025e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1214" , 0x1180080e025f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1215" , 0x1180080e025f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1216" , 0x1180080e02600ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1217" , 0x1180080e02608ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1218" , 0x1180080e02610ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1219" , 0x1180080e02618ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1220" , 0x1180080e02620ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1221" , 0x1180080e02628ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1222" , 0x1180080e02630ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1223" , 0x1180080e02638ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1224" , 0x1180080e02640ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1225" , 0x1180080e02648ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1226" , 0x1180080e02650ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1227" , 0x1180080e02658ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1228" , 0x1180080e02660ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1229" , 0x1180080e02668ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1230" , 0x1180080e02670ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1231" , 0x1180080e02678ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1232" , 0x1180080e02680ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1233" , 0x1180080e02688ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1234" , 0x1180080e02690ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1235" , 0x1180080e02698ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1236" , 0x1180080e026a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1237" , 0x1180080e026a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1238" , 0x1180080e026b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1239" , 0x1180080e026b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1240" , 0x1180080e026c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1241" , 0x1180080e026c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1242" , 0x1180080e026d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1243" , 0x1180080e026d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1244" , 0x1180080e026e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1245" , 0x1180080e026e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1246" , 0x1180080e026f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1247" , 0x1180080e026f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1248" , 0x1180080e02700ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1249" , 0x1180080e02708ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1250" , 0x1180080e02710ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1251" , 0x1180080e02718ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1252" , 0x1180080e02720ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1253" , 0x1180080e02728ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1254" , 0x1180080e02730ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1255" , 0x1180080e02738ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1256" , 0x1180080e02740ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1257" , 0x1180080e02748ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1258" , 0x1180080e02750ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1259" , 0x1180080e02758ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1260" , 0x1180080e02760ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1261" , 0x1180080e02768ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1262" , 0x1180080e02770ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1263" , 0x1180080e02778ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1264" , 0x1180080e02780ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1265" , 0x1180080e02788ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1266" , 0x1180080e02790ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1267" , 0x1180080e02798ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1268" , 0x1180080e027a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1269" , 0x1180080e027a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1270" , 0x1180080e027b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1271" , 0x1180080e027b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1272" , 0x1180080e027c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1273" , 0x1180080e027c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1274" , 0x1180080e027d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1275" , 0x1180080e027d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1276" , 0x1180080e027e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1277" , 0x1180080e027e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1278" , 0x1180080e027f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1279" , 0x1180080e027f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1280" , 0x1180080e02800ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1281" , 0x1180080e02808ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1282" , 0x1180080e02810ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1283" , 0x1180080e02818ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1284" , 0x1180080e02820ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1285" , 0x1180080e02828ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1286" , 0x1180080e02830ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1287" , 0x1180080e02838ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1288" , 0x1180080e02840ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1289" , 0x1180080e02848ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1290" , 0x1180080e02850ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1291" , 0x1180080e02858ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1292" , 0x1180080e02860ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1293" , 0x1180080e02868ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1294" , 0x1180080e02870ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1295" , 0x1180080e02878ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1296" , 0x1180080e02880ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1297" , 0x1180080e02888ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1298" , 0x1180080e02890ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1299" , 0x1180080e02898ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1300" , 0x1180080e028a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1301" , 0x1180080e028a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1302" , 0x1180080e028b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1303" , 0x1180080e028b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1304" , 0x1180080e028c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1305" , 0x1180080e028c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1306" , 0x1180080e028d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1307" , 0x1180080e028d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1308" , 0x1180080e028e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1309" , 0x1180080e028e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1310" , 0x1180080e028f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1311" , 0x1180080e028f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1312" , 0x1180080e02900ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1313" , 0x1180080e02908ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1314" , 0x1180080e02910ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1315" , 0x1180080e02918ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1316" , 0x1180080e02920ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1317" , 0x1180080e02928ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1318" , 0x1180080e02930ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1319" , 0x1180080e02938ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1320" , 0x1180080e02940ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1321" , 0x1180080e02948ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1322" , 0x1180080e02950ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1323" , 0x1180080e02958ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1324" , 0x1180080e02960ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1325" , 0x1180080e02968ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1326" , 0x1180080e02970ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1327" , 0x1180080e02978ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1328" , 0x1180080e02980ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1329" , 0x1180080e02988ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1330" , 0x1180080e02990ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1331" , 0x1180080e02998ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1332" , 0x1180080e029a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1333" , 0x1180080e029a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1334" , 0x1180080e029b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1335" , 0x1180080e029b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1336" , 0x1180080e029c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1337" , 0x1180080e029c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1338" , 0x1180080e029d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1339" , 0x1180080e029d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1340" , 0x1180080e029e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1341" , 0x1180080e029e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1342" , 0x1180080e029f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1343" , 0x1180080e029f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1344" , 0x1180080e02a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1345" , 0x1180080e02a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1346" , 0x1180080e02a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1347" , 0x1180080e02a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1348" , 0x1180080e02a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1349" , 0x1180080e02a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1350" , 0x1180080e02a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1351" , 0x1180080e02a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1352" , 0x1180080e02a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1353" , 0x1180080e02a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1354" , 0x1180080e02a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1355" , 0x1180080e02a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1356" , 0x1180080e02a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1357" , 0x1180080e02a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1358" , 0x1180080e02a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1359" , 0x1180080e02a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1360" , 0x1180080e02a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1361" , 0x1180080e02a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1362" , 0x1180080e02a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1363" , 0x1180080e02a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1364" , 0x1180080e02aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1365" , 0x1180080e02aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1366" , 0x1180080e02ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1367" , 0x1180080e02ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1368" , 0x1180080e02ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1369" , 0x1180080e02ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1370" , 0x1180080e02ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1371" , 0x1180080e02ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1372" , 0x1180080e02ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1373" , 0x1180080e02ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1374" , 0x1180080e02af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1375" , 0x1180080e02af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1376" , 0x1180080e02b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1377" , 0x1180080e02b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1378" , 0x1180080e02b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1379" , 0x1180080e02b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1380" , 0x1180080e02b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1381" , 0x1180080e02b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1382" , 0x1180080e02b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1383" , 0x1180080e02b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1384" , 0x1180080e02b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1385" , 0x1180080e02b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1386" , 0x1180080e02b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1387" , 0x1180080e02b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1388" , 0x1180080e02b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1389" , 0x1180080e02b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1390" , 0x1180080e02b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1391" , 0x1180080e02b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1392" , 0x1180080e02b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1393" , 0x1180080e02b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1394" , 0x1180080e02b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1395" , 0x1180080e02b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1396" , 0x1180080e02ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1397" , 0x1180080e02ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1398" , 0x1180080e02bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1399" , 0x1180080e02bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1400" , 0x1180080e02bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1401" , 0x1180080e02bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1402" , 0x1180080e02bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1403" , 0x1180080e02bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1404" , 0x1180080e02be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1405" , 0x1180080e02be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1406" , 0x1180080e02bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1407" , 0x1180080e02bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1408" , 0x1180080e02c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1409" , 0x1180080e02c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1410" , 0x1180080e02c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1411" , 0x1180080e02c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1412" , 0x1180080e02c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1413" , 0x1180080e02c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1414" , 0x1180080e02c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1415" , 0x1180080e02c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1416" , 0x1180080e02c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1417" , 0x1180080e02c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1418" , 0x1180080e02c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1419" , 0x1180080e02c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1420" , 0x1180080e02c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1421" , 0x1180080e02c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1422" , 0x1180080e02c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1423" , 0x1180080e02c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1424" , 0x1180080e02c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1425" , 0x1180080e02c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1426" , 0x1180080e02c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1427" , 0x1180080e02c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1428" , 0x1180080e02ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1429" , 0x1180080e02ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1430" , 0x1180080e02cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1431" , 0x1180080e02cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1432" , 0x1180080e02cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1433" , 0x1180080e02cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1434" , 0x1180080e02cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1435" , 0x1180080e02cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1436" , 0x1180080e02ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1437" , 0x1180080e02ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1438" , 0x1180080e02cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1439" , 0x1180080e02cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1440" , 0x1180080e02d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1441" , 0x1180080e02d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1442" , 0x1180080e02d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1443" , 0x1180080e02d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1444" , 0x1180080e02d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1445" , 0x1180080e02d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1446" , 0x1180080e02d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1447" , 0x1180080e02d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1448" , 0x1180080e02d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1449" , 0x1180080e02d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1450" , 0x1180080e02d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1451" , 0x1180080e02d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1452" , 0x1180080e02d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1453" , 0x1180080e02d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1454" , 0x1180080e02d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1455" , 0x1180080e02d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1456" , 0x1180080e02d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1457" , 0x1180080e02d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1458" , 0x1180080e02d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1459" , 0x1180080e02d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1460" , 0x1180080e02da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1461" , 0x1180080e02da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1462" , 0x1180080e02db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1463" , 0x1180080e02db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1464" , 0x1180080e02dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1465" , 0x1180080e02dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1466" , 0x1180080e02dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1467" , 0x1180080e02dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1468" , 0x1180080e02de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1469" , 0x1180080e02de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1470" , 0x1180080e02df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1471" , 0x1180080e02df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1472" , 0x1180080e02e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1473" , 0x1180080e02e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1474" , 0x1180080e02e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1475" , 0x1180080e02e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1476" , 0x1180080e02e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1477" , 0x1180080e02e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1478" , 0x1180080e02e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1479" , 0x1180080e02e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1480" , 0x1180080e02e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1481" , 0x1180080e02e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1482" , 0x1180080e02e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1483" , 0x1180080e02e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1484" , 0x1180080e02e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1485" , 0x1180080e02e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1486" , 0x1180080e02e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1487" , 0x1180080e02e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1488" , 0x1180080e02e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1489" , 0x1180080e02e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1490" , 0x1180080e02e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1491" , 0x1180080e02e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1492" , 0x1180080e02ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1493" , 0x1180080e02ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1494" , 0x1180080e02eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1495" , 0x1180080e02eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1496" , 0x1180080e02ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1497" , 0x1180080e02ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1498" , 0x1180080e02ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1499" , 0x1180080e02ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1500" , 0x1180080e02ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1501" , 0x1180080e02ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1502" , 0x1180080e02ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1503" , 0x1180080e02ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1504" , 0x1180080e02f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1505" , 0x1180080e02f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1506" , 0x1180080e02f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1507" , 0x1180080e02f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1508" , 0x1180080e02f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1509" , 0x1180080e02f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1510" , 0x1180080e02f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1511" , 0x1180080e02f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1512" , 0x1180080e02f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1513" , 0x1180080e02f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1514" , 0x1180080e02f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1515" , 0x1180080e02f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1516" , 0x1180080e02f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1517" , 0x1180080e02f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1518" , 0x1180080e02f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1519" , 0x1180080e02f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1520" , 0x1180080e02f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1521" , 0x1180080e02f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1522" , 0x1180080e02f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1523" , 0x1180080e02f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1524" , 0x1180080e02fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1525" , 0x1180080e02fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1526" , 0x1180080e02fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1527" , 0x1180080e02fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1528" , 0x1180080e02fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1529" , 0x1180080e02fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1530" , 0x1180080e02fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1531" , 0x1180080e02fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1532" , 0x1180080e02fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1533" , 0x1180080e02fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1534" , 0x1180080e02ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_DUT_MAP1535" , 0x1180080e02ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"L2C_ERR_TDT0" , 0x1180080a007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"L2C_ERR_TTG0" , 0x1180080a007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"L2C_ERR_VBF0" , 0x1180080c007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"L2C_ERR_XMC" , 0x11800808007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"L2C_INT_ENA" , 0x1180080800020ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"L2C_INT_REG" , 0x1180080800018ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"L2C_IOC0_PFC" , 0x1180080800420ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"L2C_IOR0_PFC" , 0x1180080800428ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"L2C_QOS_IOB0" , 0x1180080880200ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"L2C_QOS_PP0" , 0x1180080880000ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_QOS_PP1" , 0x1180080880008ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_QOS_PP2" , 0x1180080880010ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_QOS_PP3" , 0x1180080880018ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_QOS_PP4" , 0x1180080880020ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_QOS_PP5" , 0x1180080880028ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"L2C_QOS_WGT" , 0x1180080800008ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"L2C_RSC0_PFC" , 0x1180080800410ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"L2C_RSD0_PFC" , 0x1180080800418ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"L2C_TAD0_ECC0" , 0x1180080a00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"L2C_TAD0_ECC1" , 0x1180080a00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"L2C_TAD0_IEN" , 0x1180080a00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"L2C_TAD0_INT" , 0x1180080a00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"L2C_TAD0_PFC0" , 0x1180080a00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"L2C_TAD0_PFC1" , 0x1180080a00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"L2C_TAD0_PFC2" , 0x1180080a00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"L2C_TAD0_PFC3" , 0x1180080a00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"L2C_TAD0_PRF" , 0x1180080a00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"L2C_TAD0_TAG" , 0x1180080a00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"L2C_VER_ID" , 0x11800808007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"L2C_VER_IOB" , 0x11800808007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"L2C_VER_MSC" , 0x11800808007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"L2C_VER_PP" , 0x11800808007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"L2C_VIRTID_IOB0" , 0x11800808c0200ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"L2C_VIRTID_PP0" , 0x11800808c0000ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_VIRTID_PP1" , 0x11800808c0008ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_VIRTID_PP2" , 0x11800808c0010ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_VIRTID_PP3" , 0x11800808c0018ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_VIRTID_PP4" , 0x11800808c0020ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_VIRTID_PP5" , 0x11800808c0028ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_VRT_CTL" , 0x1180080800010ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"L2C_VRT_MEM0" , 0x1180080900000ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1" , 0x1180080900008ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM2" , 0x1180080900010ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM3" , 0x1180080900018ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM4" , 0x1180080900020ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM5" , 0x1180080900028ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM6" , 0x1180080900030ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM7" , 0x1180080900038ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM8" , 0x1180080900040ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM9" , 0x1180080900048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM10" , 0x1180080900050ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM11" , 0x1180080900058ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM12" , 0x1180080900060ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM13" , 0x1180080900068ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM14" , 0x1180080900070ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM15" , 0x1180080900078ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM16" , 0x1180080900080ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM17" , 0x1180080900088ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM18" , 0x1180080900090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM19" , 0x1180080900098ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM20" , 0x11800809000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM21" , 0x11800809000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM22" , 0x11800809000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM23" , 0x11800809000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM24" , 0x11800809000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM25" , 0x11800809000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM26" , 0x11800809000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM27" , 0x11800809000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM28" , 0x11800809000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM29" , 0x11800809000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM30" , 0x11800809000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM31" , 0x11800809000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM32" , 0x1180080900100ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM33" , 0x1180080900108ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM34" , 0x1180080900110ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM35" , 0x1180080900118ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM36" , 0x1180080900120ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM37" , 0x1180080900128ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM38" , 0x1180080900130ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM39" , 0x1180080900138ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM40" , 0x1180080900140ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM41" , 0x1180080900148ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM42" , 0x1180080900150ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM43" , 0x1180080900158ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM44" , 0x1180080900160ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM45" , 0x1180080900168ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM46" , 0x1180080900170ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM47" , 0x1180080900178ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM48" , 0x1180080900180ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM49" , 0x1180080900188ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM50" , 0x1180080900190ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM51" , 0x1180080900198ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM52" , 0x11800809001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM53" , 0x11800809001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM54" , 0x11800809001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM55" , 0x11800809001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM56" , 0x11800809001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM57" , 0x11800809001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM58" , 0x11800809001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM59" , 0x11800809001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM60" , 0x11800809001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM61" , 0x11800809001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM62" , 0x11800809001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM63" , 0x11800809001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM64" , 0x1180080900200ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM65" , 0x1180080900208ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM66" , 0x1180080900210ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM67" , 0x1180080900218ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM68" , 0x1180080900220ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM69" , 0x1180080900228ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM70" , 0x1180080900230ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM71" , 0x1180080900238ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM72" , 0x1180080900240ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM73" , 0x1180080900248ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM74" , 0x1180080900250ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM75" , 0x1180080900258ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM76" , 0x1180080900260ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM77" , 0x1180080900268ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM78" , 0x1180080900270ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM79" , 0x1180080900278ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM80" , 0x1180080900280ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM81" , 0x1180080900288ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM82" , 0x1180080900290ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM83" , 0x1180080900298ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM84" , 0x11800809002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM85" , 0x11800809002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM86" , 0x11800809002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM87" , 0x11800809002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM88" , 0x11800809002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM89" , 0x11800809002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM90" , 0x11800809002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM91" , 0x11800809002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM92" , 0x11800809002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM93" , 0x11800809002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM94" , 0x11800809002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM95" , 0x11800809002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM96" , 0x1180080900300ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM97" , 0x1180080900308ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM98" , 0x1180080900310ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM99" , 0x1180080900318ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM100" , 0x1180080900320ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM101" , 0x1180080900328ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM102" , 0x1180080900330ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM103" , 0x1180080900338ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM104" , 0x1180080900340ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM105" , 0x1180080900348ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM106" , 0x1180080900350ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM107" , 0x1180080900358ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM108" , 0x1180080900360ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM109" , 0x1180080900368ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM110" , 0x1180080900370ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM111" , 0x1180080900378ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM112" , 0x1180080900380ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM113" , 0x1180080900388ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM114" , 0x1180080900390ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM115" , 0x1180080900398ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM116" , 0x11800809003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM117" , 0x11800809003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM118" , 0x11800809003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM119" , 0x11800809003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM120" , 0x11800809003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM121" , 0x11800809003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM122" , 0x11800809003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM123" , 0x11800809003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM124" , 0x11800809003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM125" , 0x11800809003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM126" , 0x11800809003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM127" , 0x11800809003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM128" , 0x1180080900400ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM129" , 0x1180080900408ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM130" , 0x1180080900410ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM131" , 0x1180080900418ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM132" , 0x1180080900420ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM133" , 0x1180080900428ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM134" , 0x1180080900430ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM135" , 0x1180080900438ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM136" , 0x1180080900440ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM137" , 0x1180080900448ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM138" , 0x1180080900450ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM139" , 0x1180080900458ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM140" , 0x1180080900460ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM141" , 0x1180080900468ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM142" , 0x1180080900470ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM143" , 0x1180080900478ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM144" , 0x1180080900480ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM145" , 0x1180080900488ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM146" , 0x1180080900490ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM147" , 0x1180080900498ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM148" , 0x11800809004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM149" , 0x11800809004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM150" , 0x11800809004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM151" , 0x11800809004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM152" , 0x11800809004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM153" , 0x11800809004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM154" , 0x11800809004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM155" , 0x11800809004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM156" , 0x11800809004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM157" , 0x11800809004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM158" , 0x11800809004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM159" , 0x11800809004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM160" , 0x1180080900500ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM161" , 0x1180080900508ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM162" , 0x1180080900510ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM163" , 0x1180080900518ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM164" , 0x1180080900520ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM165" , 0x1180080900528ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM166" , 0x1180080900530ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM167" , 0x1180080900538ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM168" , 0x1180080900540ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM169" , 0x1180080900548ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM170" , 0x1180080900550ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM171" , 0x1180080900558ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM172" , 0x1180080900560ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM173" , 0x1180080900568ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM174" , 0x1180080900570ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM175" , 0x1180080900578ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM176" , 0x1180080900580ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM177" , 0x1180080900588ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM178" , 0x1180080900590ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM179" , 0x1180080900598ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM180" , 0x11800809005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM181" , 0x11800809005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM182" , 0x11800809005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM183" , 0x11800809005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM184" , 0x11800809005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM185" , 0x11800809005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM186" , 0x11800809005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM187" , 0x11800809005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM188" , 0x11800809005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM189" , 0x11800809005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM190" , 0x11800809005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM191" , 0x11800809005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM192" , 0x1180080900600ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM193" , 0x1180080900608ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM194" , 0x1180080900610ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM195" , 0x1180080900618ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM196" , 0x1180080900620ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM197" , 0x1180080900628ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM198" , 0x1180080900630ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM199" , 0x1180080900638ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM200" , 0x1180080900640ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM201" , 0x1180080900648ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM202" , 0x1180080900650ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM203" , 0x1180080900658ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM204" , 0x1180080900660ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM205" , 0x1180080900668ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM206" , 0x1180080900670ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM207" , 0x1180080900678ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM208" , 0x1180080900680ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM209" , 0x1180080900688ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM210" , 0x1180080900690ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM211" , 0x1180080900698ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM212" , 0x11800809006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM213" , 0x11800809006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM214" , 0x11800809006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM215" , 0x11800809006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM216" , 0x11800809006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM217" , 0x11800809006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM218" , 0x11800809006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM219" , 0x11800809006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM220" , 0x11800809006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM221" , 0x11800809006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM222" , 0x11800809006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM223" , 0x11800809006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM224" , 0x1180080900700ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM225" , 0x1180080900708ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM226" , 0x1180080900710ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM227" , 0x1180080900718ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM228" , 0x1180080900720ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM229" , 0x1180080900728ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM230" , 0x1180080900730ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM231" , 0x1180080900738ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM232" , 0x1180080900740ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM233" , 0x1180080900748ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM234" , 0x1180080900750ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM235" , 0x1180080900758ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM236" , 0x1180080900760ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM237" , 0x1180080900768ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM238" , 0x1180080900770ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM239" , 0x1180080900778ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM240" , 0x1180080900780ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM241" , 0x1180080900788ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM242" , 0x1180080900790ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM243" , 0x1180080900798ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM244" , 0x11800809007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM245" , 0x11800809007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM246" , 0x11800809007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM247" , 0x11800809007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM248" , 0x11800809007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM249" , 0x11800809007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM250" , 0x11800809007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM251" , 0x11800809007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM252" , 0x11800809007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM253" , 0x11800809007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM254" , 0x11800809007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM255" , 0x11800809007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM256" , 0x1180080900800ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM257" , 0x1180080900808ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM258" , 0x1180080900810ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM259" , 0x1180080900818ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM260" , 0x1180080900820ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM261" , 0x1180080900828ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM262" , 0x1180080900830ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM263" , 0x1180080900838ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM264" , 0x1180080900840ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM265" , 0x1180080900848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM266" , 0x1180080900850ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM267" , 0x1180080900858ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM268" , 0x1180080900860ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM269" , 0x1180080900868ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM270" , 0x1180080900870ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM271" , 0x1180080900878ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM272" , 0x1180080900880ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM273" , 0x1180080900888ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM274" , 0x1180080900890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM275" , 0x1180080900898ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM276" , 0x11800809008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM277" , 0x11800809008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM278" , 0x11800809008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM279" , 0x11800809008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM280" , 0x11800809008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM281" , 0x11800809008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM282" , 0x11800809008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM283" , 0x11800809008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM284" , 0x11800809008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM285" , 0x11800809008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM286" , 0x11800809008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM287" , 0x11800809008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM288" , 0x1180080900900ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM289" , 0x1180080900908ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM290" , 0x1180080900910ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM291" , 0x1180080900918ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM292" , 0x1180080900920ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM293" , 0x1180080900928ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM294" , 0x1180080900930ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM295" , 0x1180080900938ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM296" , 0x1180080900940ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM297" , 0x1180080900948ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM298" , 0x1180080900950ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM299" , 0x1180080900958ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM300" , 0x1180080900960ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM301" , 0x1180080900968ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM302" , 0x1180080900970ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM303" , 0x1180080900978ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM304" , 0x1180080900980ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM305" , 0x1180080900988ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM306" , 0x1180080900990ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM307" , 0x1180080900998ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM308" , 0x11800809009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM309" , 0x11800809009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM310" , 0x11800809009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM311" , 0x11800809009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM312" , 0x11800809009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM313" , 0x11800809009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM314" , 0x11800809009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM315" , 0x11800809009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM316" , 0x11800809009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM317" , 0x11800809009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM318" , 0x11800809009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM319" , 0x11800809009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM320" , 0x1180080900a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM321" , 0x1180080900a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM322" , 0x1180080900a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM323" , 0x1180080900a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM324" , 0x1180080900a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM325" , 0x1180080900a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM326" , 0x1180080900a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM327" , 0x1180080900a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM328" , 0x1180080900a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM329" , 0x1180080900a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM330" , 0x1180080900a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM331" , 0x1180080900a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM332" , 0x1180080900a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM333" , 0x1180080900a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM334" , 0x1180080900a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM335" , 0x1180080900a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM336" , 0x1180080900a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM337" , 0x1180080900a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM338" , 0x1180080900a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM339" , 0x1180080900a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM340" , 0x1180080900aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM341" , 0x1180080900aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM342" , 0x1180080900ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM343" , 0x1180080900ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM344" , 0x1180080900ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM345" , 0x1180080900ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM346" , 0x1180080900ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM347" , 0x1180080900ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM348" , 0x1180080900ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM349" , 0x1180080900ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM350" , 0x1180080900af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM351" , 0x1180080900af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM352" , 0x1180080900b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM353" , 0x1180080900b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM354" , 0x1180080900b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM355" , 0x1180080900b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM356" , 0x1180080900b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM357" , 0x1180080900b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM358" , 0x1180080900b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM359" , 0x1180080900b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM360" , 0x1180080900b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM361" , 0x1180080900b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM362" , 0x1180080900b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM363" , 0x1180080900b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM364" , 0x1180080900b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM365" , 0x1180080900b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM366" , 0x1180080900b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM367" , 0x1180080900b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM368" , 0x1180080900b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM369" , 0x1180080900b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM370" , 0x1180080900b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM371" , 0x1180080900b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM372" , 0x1180080900ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM373" , 0x1180080900ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM374" , 0x1180080900bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM375" , 0x1180080900bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM376" , 0x1180080900bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM377" , 0x1180080900bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM378" , 0x1180080900bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM379" , 0x1180080900bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM380" , 0x1180080900be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM381" , 0x1180080900be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM382" , 0x1180080900bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM383" , 0x1180080900bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM384" , 0x1180080900c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM385" , 0x1180080900c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM386" , 0x1180080900c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM387" , 0x1180080900c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM388" , 0x1180080900c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM389" , 0x1180080900c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM390" , 0x1180080900c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM391" , 0x1180080900c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM392" , 0x1180080900c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM393" , 0x1180080900c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM394" , 0x1180080900c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM395" , 0x1180080900c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM396" , 0x1180080900c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM397" , 0x1180080900c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM398" , 0x1180080900c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM399" , 0x1180080900c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM400" , 0x1180080900c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM401" , 0x1180080900c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM402" , 0x1180080900c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM403" , 0x1180080900c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM404" , 0x1180080900ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM405" , 0x1180080900ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM406" , 0x1180080900cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM407" , 0x1180080900cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM408" , 0x1180080900cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM409" , 0x1180080900cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM410" , 0x1180080900cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM411" , 0x1180080900cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM412" , 0x1180080900ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM413" , 0x1180080900ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM414" , 0x1180080900cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM415" , 0x1180080900cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM416" , 0x1180080900d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM417" , 0x1180080900d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM418" , 0x1180080900d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM419" , 0x1180080900d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM420" , 0x1180080900d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM421" , 0x1180080900d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM422" , 0x1180080900d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM423" , 0x1180080900d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM424" , 0x1180080900d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM425" , 0x1180080900d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM426" , 0x1180080900d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM427" , 0x1180080900d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM428" , 0x1180080900d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM429" , 0x1180080900d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM430" , 0x1180080900d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM431" , 0x1180080900d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM432" , 0x1180080900d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM433" , 0x1180080900d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM434" , 0x1180080900d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM435" , 0x1180080900d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM436" , 0x1180080900da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM437" , 0x1180080900da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM438" , 0x1180080900db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM439" , 0x1180080900db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM440" , 0x1180080900dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM441" , 0x1180080900dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM442" , 0x1180080900dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM443" , 0x1180080900dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM444" , 0x1180080900de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM445" , 0x1180080900de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM446" , 0x1180080900df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM447" , 0x1180080900df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM448" , 0x1180080900e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM449" , 0x1180080900e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM450" , 0x1180080900e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM451" , 0x1180080900e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM452" , 0x1180080900e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM453" , 0x1180080900e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM454" , 0x1180080900e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM455" , 0x1180080900e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM456" , 0x1180080900e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM457" , 0x1180080900e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM458" , 0x1180080900e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM459" , 0x1180080900e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM460" , 0x1180080900e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM461" , 0x1180080900e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM462" , 0x1180080900e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM463" , 0x1180080900e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM464" , 0x1180080900e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM465" , 0x1180080900e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM466" , 0x1180080900e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM467" , 0x1180080900e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM468" , 0x1180080900ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM469" , 0x1180080900ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM470" , 0x1180080900eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM471" , 0x1180080900eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM472" , 0x1180080900ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM473" , 0x1180080900ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM474" , 0x1180080900ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM475" , 0x1180080900ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM476" , 0x1180080900ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM477" , 0x1180080900ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM478" , 0x1180080900ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM479" , 0x1180080900ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM480" , 0x1180080900f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM481" , 0x1180080900f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM482" , 0x1180080900f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM483" , 0x1180080900f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM484" , 0x1180080900f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM485" , 0x1180080900f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM486" , 0x1180080900f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM487" , 0x1180080900f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM488" , 0x1180080900f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM489" , 0x1180080900f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM490" , 0x1180080900f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM491" , 0x1180080900f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM492" , 0x1180080900f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM493" , 0x1180080900f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM494" , 0x1180080900f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM495" , 0x1180080900f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM496" , 0x1180080900f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM497" , 0x1180080900f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM498" , 0x1180080900f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM499" , 0x1180080900f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM500" , 0x1180080900fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM501" , 0x1180080900fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM502" , 0x1180080900fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM503" , 0x1180080900fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM504" , 0x1180080900fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM505" , 0x1180080900fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM506" , 0x1180080900fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM507" , 0x1180080900fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM508" , 0x1180080900fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM509" , 0x1180080900fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM510" , 0x1180080900ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM511" , 0x1180080900ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM512" , 0x1180080901000ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM513" , 0x1180080901008ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM514" , 0x1180080901010ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM515" , 0x1180080901018ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM516" , 0x1180080901020ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM517" , 0x1180080901028ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM518" , 0x1180080901030ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM519" , 0x1180080901038ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM520" , 0x1180080901040ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM521" , 0x1180080901048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM522" , 0x1180080901050ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM523" , 0x1180080901058ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM524" , 0x1180080901060ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM525" , 0x1180080901068ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM526" , 0x1180080901070ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM527" , 0x1180080901078ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM528" , 0x1180080901080ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM529" , 0x1180080901088ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM530" , 0x1180080901090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM531" , 0x1180080901098ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM532" , 0x11800809010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM533" , 0x11800809010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM534" , 0x11800809010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM535" , 0x11800809010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM536" , 0x11800809010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM537" , 0x11800809010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM538" , 0x11800809010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM539" , 0x11800809010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM540" , 0x11800809010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM541" , 0x11800809010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM542" , 0x11800809010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM543" , 0x11800809010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM544" , 0x1180080901100ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM545" , 0x1180080901108ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM546" , 0x1180080901110ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM547" , 0x1180080901118ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM548" , 0x1180080901120ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM549" , 0x1180080901128ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM550" , 0x1180080901130ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM551" , 0x1180080901138ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM552" , 0x1180080901140ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM553" , 0x1180080901148ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM554" , 0x1180080901150ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM555" , 0x1180080901158ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM556" , 0x1180080901160ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM557" , 0x1180080901168ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM558" , 0x1180080901170ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM559" , 0x1180080901178ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM560" , 0x1180080901180ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM561" , 0x1180080901188ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM562" , 0x1180080901190ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM563" , 0x1180080901198ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM564" , 0x11800809011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM565" , 0x11800809011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM566" , 0x11800809011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM567" , 0x11800809011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM568" , 0x11800809011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM569" , 0x11800809011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM570" , 0x11800809011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM571" , 0x11800809011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM572" , 0x11800809011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM573" , 0x11800809011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM574" , 0x11800809011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM575" , 0x11800809011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM576" , 0x1180080901200ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM577" , 0x1180080901208ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM578" , 0x1180080901210ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM579" , 0x1180080901218ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM580" , 0x1180080901220ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM581" , 0x1180080901228ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM582" , 0x1180080901230ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM583" , 0x1180080901238ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM584" , 0x1180080901240ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM585" , 0x1180080901248ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM586" , 0x1180080901250ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM587" , 0x1180080901258ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM588" , 0x1180080901260ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM589" , 0x1180080901268ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM590" , 0x1180080901270ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM591" , 0x1180080901278ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM592" , 0x1180080901280ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM593" , 0x1180080901288ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM594" , 0x1180080901290ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM595" , 0x1180080901298ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM596" , 0x11800809012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM597" , 0x11800809012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM598" , 0x11800809012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM599" , 0x11800809012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM600" , 0x11800809012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM601" , 0x11800809012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM602" , 0x11800809012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM603" , 0x11800809012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM604" , 0x11800809012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM605" , 0x11800809012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM606" , 0x11800809012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM607" , 0x11800809012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM608" , 0x1180080901300ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM609" , 0x1180080901308ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM610" , 0x1180080901310ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM611" , 0x1180080901318ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM612" , 0x1180080901320ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM613" , 0x1180080901328ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM614" , 0x1180080901330ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM615" , 0x1180080901338ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM616" , 0x1180080901340ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM617" , 0x1180080901348ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM618" , 0x1180080901350ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM619" , 0x1180080901358ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM620" , 0x1180080901360ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM621" , 0x1180080901368ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM622" , 0x1180080901370ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM623" , 0x1180080901378ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM624" , 0x1180080901380ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM625" , 0x1180080901388ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM626" , 0x1180080901390ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM627" , 0x1180080901398ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM628" , 0x11800809013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM629" , 0x11800809013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM630" , 0x11800809013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM631" , 0x11800809013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM632" , 0x11800809013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM633" , 0x11800809013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM634" , 0x11800809013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM635" , 0x11800809013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM636" , 0x11800809013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM637" , 0x11800809013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM638" , 0x11800809013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM639" , 0x11800809013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM640" , 0x1180080901400ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM641" , 0x1180080901408ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM642" , 0x1180080901410ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM643" , 0x1180080901418ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM644" , 0x1180080901420ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM645" , 0x1180080901428ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM646" , 0x1180080901430ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM647" , 0x1180080901438ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM648" , 0x1180080901440ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM649" , 0x1180080901448ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM650" , 0x1180080901450ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM651" , 0x1180080901458ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM652" , 0x1180080901460ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM653" , 0x1180080901468ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM654" , 0x1180080901470ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM655" , 0x1180080901478ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM656" , 0x1180080901480ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM657" , 0x1180080901488ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM658" , 0x1180080901490ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM659" , 0x1180080901498ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM660" , 0x11800809014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM661" , 0x11800809014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM662" , 0x11800809014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM663" , 0x11800809014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM664" , 0x11800809014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM665" , 0x11800809014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM666" , 0x11800809014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM667" , 0x11800809014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM668" , 0x11800809014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM669" , 0x11800809014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM670" , 0x11800809014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM671" , 0x11800809014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM672" , 0x1180080901500ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM673" , 0x1180080901508ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM674" , 0x1180080901510ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM675" , 0x1180080901518ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM676" , 0x1180080901520ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM677" , 0x1180080901528ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM678" , 0x1180080901530ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM679" , 0x1180080901538ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM680" , 0x1180080901540ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM681" , 0x1180080901548ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM682" , 0x1180080901550ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM683" , 0x1180080901558ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM684" , 0x1180080901560ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM685" , 0x1180080901568ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM686" , 0x1180080901570ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM687" , 0x1180080901578ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM688" , 0x1180080901580ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM689" , 0x1180080901588ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM690" , 0x1180080901590ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM691" , 0x1180080901598ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM692" , 0x11800809015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM693" , 0x11800809015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM694" , 0x11800809015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM695" , 0x11800809015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM696" , 0x11800809015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM697" , 0x11800809015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM698" , 0x11800809015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM699" , 0x11800809015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM700" , 0x11800809015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM701" , 0x11800809015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM702" , 0x11800809015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM703" , 0x11800809015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM704" , 0x1180080901600ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM705" , 0x1180080901608ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM706" , 0x1180080901610ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM707" , 0x1180080901618ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM708" , 0x1180080901620ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM709" , 0x1180080901628ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM710" , 0x1180080901630ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM711" , 0x1180080901638ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM712" , 0x1180080901640ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM713" , 0x1180080901648ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM714" , 0x1180080901650ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM715" , 0x1180080901658ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM716" , 0x1180080901660ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM717" , 0x1180080901668ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM718" , 0x1180080901670ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM719" , 0x1180080901678ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM720" , 0x1180080901680ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM721" , 0x1180080901688ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM722" , 0x1180080901690ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM723" , 0x1180080901698ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM724" , 0x11800809016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM725" , 0x11800809016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM726" , 0x11800809016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM727" , 0x11800809016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM728" , 0x11800809016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM729" , 0x11800809016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM730" , 0x11800809016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM731" , 0x11800809016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM732" , 0x11800809016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM733" , 0x11800809016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM734" , 0x11800809016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM735" , 0x11800809016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM736" , 0x1180080901700ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM737" , 0x1180080901708ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM738" , 0x1180080901710ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM739" , 0x1180080901718ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM740" , 0x1180080901720ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM741" , 0x1180080901728ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM742" , 0x1180080901730ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM743" , 0x1180080901738ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM744" , 0x1180080901740ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM745" , 0x1180080901748ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM746" , 0x1180080901750ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM747" , 0x1180080901758ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM748" , 0x1180080901760ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM749" , 0x1180080901768ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM750" , 0x1180080901770ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM751" , 0x1180080901778ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM752" , 0x1180080901780ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM753" , 0x1180080901788ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM754" , 0x1180080901790ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM755" , 0x1180080901798ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM756" , 0x11800809017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM757" , 0x11800809017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM758" , 0x11800809017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM759" , 0x11800809017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM760" , 0x11800809017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM761" , 0x11800809017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM762" , 0x11800809017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM763" , 0x11800809017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM764" , 0x11800809017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM765" , 0x11800809017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM766" , 0x11800809017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM767" , 0x11800809017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM768" , 0x1180080901800ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM769" , 0x1180080901808ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM770" , 0x1180080901810ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM771" , 0x1180080901818ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM772" , 0x1180080901820ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM773" , 0x1180080901828ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM774" , 0x1180080901830ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM775" , 0x1180080901838ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM776" , 0x1180080901840ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM777" , 0x1180080901848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM778" , 0x1180080901850ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM779" , 0x1180080901858ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM780" , 0x1180080901860ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM781" , 0x1180080901868ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM782" , 0x1180080901870ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM783" , 0x1180080901878ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM784" , 0x1180080901880ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM785" , 0x1180080901888ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM786" , 0x1180080901890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM787" , 0x1180080901898ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM788" , 0x11800809018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM789" , 0x11800809018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM790" , 0x11800809018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM791" , 0x11800809018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM792" , 0x11800809018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM793" , 0x11800809018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM794" , 0x11800809018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM795" , 0x11800809018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM796" , 0x11800809018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM797" , 0x11800809018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM798" , 0x11800809018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM799" , 0x11800809018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM800" , 0x1180080901900ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM801" , 0x1180080901908ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM802" , 0x1180080901910ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM803" , 0x1180080901918ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM804" , 0x1180080901920ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM805" , 0x1180080901928ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM806" , 0x1180080901930ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM807" , 0x1180080901938ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM808" , 0x1180080901940ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM809" , 0x1180080901948ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM810" , 0x1180080901950ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM811" , 0x1180080901958ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM812" , 0x1180080901960ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM813" , 0x1180080901968ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM814" , 0x1180080901970ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM815" , 0x1180080901978ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM816" , 0x1180080901980ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM817" , 0x1180080901988ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM818" , 0x1180080901990ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM819" , 0x1180080901998ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM820" , 0x11800809019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM821" , 0x11800809019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM822" , 0x11800809019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM823" , 0x11800809019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM824" , 0x11800809019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM825" , 0x11800809019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM826" , 0x11800809019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM827" , 0x11800809019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM828" , 0x11800809019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM829" , 0x11800809019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM830" , 0x11800809019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM831" , 0x11800809019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM832" , 0x1180080901a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM833" , 0x1180080901a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM834" , 0x1180080901a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM835" , 0x1180080901a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM836" , 0x1180080901a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM837" , 0x1180080901a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM838" , 0x1180080901a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM839" , 0x1180080901a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM840" , 0x1180080901a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM841" , 0x1180080901a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM842" , 0x1180080901a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM843" , 0x1180080901a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM844" , 0x1180080901a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM845" , 0x1180080901a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM846" , 0x1180080901a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM847" , 0x1180080901a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM848" , 0x1180080901a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM849" , 0x1180080901a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM850" , 0x1180080901a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM851" , 0x1180080901a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM852" , 0x1180080901aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM853" , 0x1180080901aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM854" , 0x1180080901ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM855" , 0x1180080901ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM856" , 0x1180080901ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM857" , 0x1180080901ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM858" , 0x1180080901ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM859" , 0x1180080901ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM860" , 0x1180080901ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM861" , 0x1180080901ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM862" , 0x1180080901af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM863" , 0x1180080901af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM864" , 0x1180080901b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM865" , 0x1180080901b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM866" , 0x1180080901b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM867" , 0x1180080901b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM868" , 0x1180080901b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM869" , 0x1180080901b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM870" , 0x1180080901b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM871" , 0x1180080901b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM872" , 0x1180080901b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM873" , 0x1180080901b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM874" , 0x1180080901b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM875" , 0x1180080901b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM876" , 0x1180080901b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM877" , 0x1180080901b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM878" , 0x1180080901b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM879" , 0x1180080901b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM880" , 0x1180080901b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM881" , 0x1180080901b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM882" , 0x1180080901b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM883" , 0x1180080901b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM884" , 0x1180080901ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM885" , 0x1180080901ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM886" , 0x1180080901bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM887" , 0x1180080901bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM888" , 0x1180080901bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM889" , 0x1180080901bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM890" , 0x1180080901bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM891" , 0x1180080901bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM892" , 0x1180080901be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM893" , 0x1180080901be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM894" , 0x1180080901bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM895" , 0x1180080901bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM896" , 0x1180080901c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM897" , 0x1180080901c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM898" , 0x1180080901c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM899" , 0x1180080901c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM900" , 0x1180080901c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM901" , 0x1180080901c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM902" , 0x1180080901c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM903" , 0x1180080901c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM904" , 0x1180080901c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM905" , 0x1180080901c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM906" , 0x1180080901c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM907" , 0x1180080901c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM908" , 0x1180080901c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM909" , 0x1180080901c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM910" , 0x1180080901c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM911" , 0x1180080901c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM912" , 0x1180080901c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM913" , 0x1180080901c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM914" , 0x1180080901c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM915" , 0x1180080901c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM916" , 0x1180080901ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM917" , 0x1180080901ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM918" , 0x1180080901cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM919" , 0x1180080901cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM920" , 0x1180080901cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM921" , 0x1180080901cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM922" , 0x1180080901cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM923" , 0x1180080901cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM924" , 0x1180080901ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM925" , 0x1180080901ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM926" , 0x1180080901cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM927" , 0x1180080901cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM928" , 0x1180080901d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM929" , 0x1180080901d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM930" , 0x1180080901d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM931" , 0x1180080901d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM932" , 0x1180080901d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM933" , 0x1180080901d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM934" , 0x1180080901d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM935" , 0x1180080901d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM936" , 0x1180080901d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM937" , 0x1180080901d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM938" , 0x1180080901d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM939" , 0x1180080901d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM940" , 0x1180080901d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM941" , 0x1180080901d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM942" , 0x1180080901d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM943" , 0x1180080901d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM944" , 0x1180080901d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM945" , 0x1180080901d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM946" , 0x1180080901d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM947" , 0x1180080901d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM948" , 0x1180080901da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM949" , 0x1180080901da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM950" , 0x1180080901db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM951" , 0x1180080901db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM952" , 0x1180080901dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM953" , 0x1180080901dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM954" , 0x1180080901dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM955" , 0x1180080901dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM956" , 0x1180080901de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM957" , 0x1180080901de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM958" , 0x1180080901df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM959" , 0x1180080901df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM960" , 0x1180080901e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM961" , 0x1180080901e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM962" , 0x1180080901e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM963" , 0x1180080901e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM964" , 0x1180080901e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM965" , 0x1180080901e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM966" , 0x1180080901e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM967" , 0x1180080901e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM968" , 0x1180080901e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM969" , 0x1180080901e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM970" , 0x1180080901e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM971" , 0x1180080901e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM972" , 0x1180080901e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM973" , 0x1180080901e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM974" , 0x1180080901e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM975" , 0x1180080901e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM976" , 0x1180080901e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM977" , 0x1180080901e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM978" , 0x1180080901e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM979" , 0x1180080901e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM980" , 0x1180080901ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM981" , 0x1180080901ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM982" , 0x1180080901eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM983" , 0x1180080901eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM984" , 0x1180080901ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM985" , 0x1180080901ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM986" , 0x1180080901ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM987" , 0x1180080901ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM988" , 0x1180080901ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM989" , 0x1180080901ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM990" , 0x1180080901ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM991" , 0x1180080901ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM992" , 0x1180080901f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM993" , 0x1180080901f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM994" , 0x1180080901f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM995" , 0x1180080901f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM996" , 0x1180080901f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM997" , 0x1180080901f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM998" , 0x1180080901f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM999" , 0x1180080901f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1000" , 0x1180080901f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1001" , 0x1180080901f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1002" , 0x1180080901f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1003" , 0x1180080901f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1004" , 0x1180080901f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1005" , 0x1180080901f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1006" , 0x1180080901f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1007" , 0x1180080901f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1008" , 0x1180080901f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1009" , 0x1180080901f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1010" , 0x1180080901f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1011" , 0x1180080901f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1012" , 0x1180080901fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1013" , 0x1180080901fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1014" , 0x1180080901fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1015" , 0x1180080901fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1016" , 0x1180080901fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1017" , 0x1180080901fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1018" , 0x1180080901fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1019" , 0x1180080901fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1020" , 0x1180080901fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1021" , 0x1180080901fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1022" , 0x1180080901ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_VRT_MEM1023" , 0x1180080901ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_WPAR_IOB0" , 0x1180080840200ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"L2C_WPAR_PP0" , 0x1180080840000ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_WPAR_PP1" , 0x1180080840008ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_WPAR_PP2" , 0x1180080840010ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_WPAR_PP3" , 0x1180080840018ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_WPAR_PP4" , 0x1180080840020ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_WPAR_PP5" , 0x1180080840028ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_XMC0_PFC" , 0x1180080800400ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"L2C_XMC_CMD" , 0x1180080800028ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_XMD0_PFC" , 0x1180080800408ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"LMC0_CHAR_CTL" , 0x1180088000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"LMC0_CHAR_MASK0" , 0x1180088000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"LMC0_CHAR_MASK1" , 0x1180088000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"LMC0_CHAR_MASK2" , 0x1180088000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"LMC0_CHAR_MASK3" , 0x1180088000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"LMC0_CHAR_MASK4" , 0x1180088000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"LMC0_COMP_CTL2" , 0x11800880001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"LMC0_CONFIG" , 0x1180088000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"LMC0_CONTROL" , 0x1180088000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"LMC0_DCLK_CNT" , 0x11800880001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"LMC0_DDR_PLL_CTL" , 0x1180088000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"LMC0_DIMM000_PARAMS" , 0x1180088000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"LMC0_DIMM001_PARAMS" , 0x1180088000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"LMC0_DIMM_CTL" , 0x1180088000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"LMC0_DLL_CTL2" , 0x11800880001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"LMC0_DLL_CTL3" , 0x1180088000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"LMC0_IFB_CNT" , 0x11800880001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"LMC0_INT" , 0x11800880001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"LMC0_INT_EN" , 0x11800880001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"LMC0_MODEREG_PARAMS0" , 0x11800880001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"LMC0_MODEREG_PARAMS1" , 0x1180088000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"LMC0_NXM" , 0x11800880000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"LMC0_OPS_CNT" , 0x11800880001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"LMC0_PHY_CTL" , 0x1180088000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"LMC0_RESET_CTL" , 0x1180088000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"LMC0_RLEVEL_CTL" , 0x11800880002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"LMC0_RLEVEL_DBG" , 0x11800880002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"LMC0_RLEVEL_RANK000" , 0x1180088000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"LMC0_RLEVEL_RANK001" , 0x1180088000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"LMC0_RLEVEL_RANK002" , 0x1180088000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"LMC0_RLEVEL_RANK003" , 0x1180088000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"LMC0_RODT_MASK" , 0x1180088000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"LMC0_SLOT_CTL0" , 0x11800880001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"LMC0_SLOT_CTL1" , 0x1180088000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"LMC0_SLOT_CTL2" , 0x1180088000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"LMC0_TIMING_PARAMS0" , 0x1180088000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"LMC0_TIMING_PARAMS1" , 0x11800880001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"LMC0_TRO_CTL" , 0x1180088000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"LMC0_TRO_STAT" , 0x1180088000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"LMC0_WLEVEL_CTL" , 0x1180088000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"LMC0_WLEVEL_DBG" , 0x1180088000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"LMC0_WLEVEL_RANK000" , 0x11800880002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"LMC0_WLEVEL_RANK001" , 0x11800880002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"LMC0_WLEVEL_RANK002" , 0x11800880002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"LMC0_WLEVEL_RANK003" , 0x11800880002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"LMC0_WODT_MASK" , 0x11800880001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"MIO_BOOT_PIN_DEFS" , 0x11800000000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"MIO_FUS_READ_TIMES" , 0x1180000001570ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"MIO_FUS_REPAIR_RES0" , 0x1180000001558ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"MIO_FUS_REPAIR_RES1" , 0x1180000001560ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"MIO_FUS_REPAIR_RES2" , 0x1180000001568ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"MIO_GPIO_COMP" , 0x11800000000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"MIO_NDF_DMA_CFG" , 0x1180000000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"MIO_NDF_DMA_INT" , 0x1180000000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"MIO_NDF_DMA_INT_EN" , 0x1180000000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"MIO_PTP_CLOCK_CFG" , 0x1070000000f00ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
- {"MIO_PTP_CLOCK_COMP" , 0x1070000000f18ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
- {"MIO_PTP_CLOCK_HI" , 0x1070000000f10ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
- {"MIO_PTP_CLOCK_LO" , 0x1070000000f08ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
- {"MIO_PTP_EVT_CNT" , 0x1070000000f28ull, CVMX_CSR_DB_TYPE_NCB, 64, 491},
- {"MIO_PTP_TIMESTAMP" , 0x1070000000f20ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
- {"MIO_RST_BOOT" , 0x1180000001600ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"MIO_RST_CFG" , 0x1180000001610ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"MIO_RST_CTL0" , 0x1180000001618ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"MIO_RST_CTL1" , 0x1180000001620ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"MIO_RST_DELAY" , 0x1180000001608ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"MIO_RST_INT" , 0x1180000001628ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"MIO_RST_INT_EN" , 0x1180000001630ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"MIX1_BIST" , 0x1070000100878ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"MIX1_CTL" , 0x1070000100820ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 530},
- {"MIX1_INTENA" , 0x1070000100850ull, CVMX_CSR_DB_TYPE_NCB, 64, 530},
- {"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 531},
- {"MIX1_IRCNT" , 0x1070000100830ull, CVMX_CSR_DB_TYPE_NCB, 64, 531},
- {"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 532},
- {"MIX1_IRHWM" , 0x1070000100828ull, CVMX_CSR_DB_TYPE_NCB, 64, 532},
- {"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 533},
- {"MIX1_IRING1" , 0x1070000100810ull, CVMX_CSR_DB_TYPE_NCB, 64, 533},
- {"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 534},
- {"MIX1_IRING2" , 0x1070000100818ull, CVMX_CSR_DB_TYPE_NCB, 64, 534},
- {"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 535},
- {"MIX1_ISR" , 0x1070000100848ull, CVMX_CSR_DB_TYPE_NCB, 64, 535},
- {"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 536},
- {"MIX1_ORCNT" , 0x1070000100840ull, CVMX_CSR_DB_TYPE_NCB, 64, 536},
- {"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 537},
- {"MIX1_ORHWM" , 0x1070000100838ull, CVMX_CSR_DB_TYPE_NCB, 64, 537},
- {"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 538},
- {"MIX1_ORING1" , 0x1070000100800ull, CVMX_CSR_DB_TYPE_NCB, 64, 538},
- {"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 539},
- {"MIX1_ORING2" , 0x1070000100808ull, CVMX_CSR_DB_TYPE_NCB, 64, 539},
- {"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 540},
- {"MIX1_REMCNT" , 0x1070000100858ull, CVMX_CSR_DB_TYPE_NCB, 64, 540},
- {"MIX0_TSCTL" , 0x1070000100068ull, CVMX_CSR_DB_TYPE_NCB, 64, 541},
- {"MIX1_TSCTL" , 0x1070000100868ull, CVMX_CSR_DB_TYPE_NCB, 64, 541},
- {"MIX0_TSTAMP" , 0x1070000100060ull, CVMX_CSR_DB_TYPE_NCB, 64, 542},
- {"MIX1_TSTAMP" , 0x1070000100860ull, CVMX_CSR_DB_TYPE_NCB, 64, 542},
- {"NDF_BT_PG_INFO" , 0x1070001000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 543},
- {"NDF_CMD" , 0x1070001000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 544},
- {"NDF_DRBELL" , 0x1070001000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 545},
- {"NDF_ECC_CNT" , 0x1070001000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 546},
- {"NDF_INT" , 0x1070001000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 547},
- {"NDF_INT_EN" , 0x1070001000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 548},
- {"NDF_MISC" , 0x1070001000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 549},
- {"NDF_ST_REG" , 0x1070001000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 550},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 551},
- {"PCIEEP1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 551},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 552},
- {"PCIEEP1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 552},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 553},
- {"PCIEEP1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 553},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 554},
- {"PCIEEP1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 554},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 555},
- {"PCIEEP1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 555},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 556},
- {"PCIEEP1_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 556},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 557},
- {"PCIEEP1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 557},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 558},
- {"PCIEEP1_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 558},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 559},
- {"PCIEEP1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 559},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 560},
- {"PCIEEP1_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 560},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 561},
- {"PCIEEP1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 561},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 562},
- {"PCIEEP1_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 562},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 563},
- {"PCIEEP1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 563},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 564},
- {"PCIEEP1_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 564},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 565},
- {"PCIEEP1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 565},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 566},
- {"PCIEEP1_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 566},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 567},
- {"PCIEEP1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 567},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 568},
- {"PCIEEP1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 568},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 569},
- {"PCIEEP1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 569},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 570},
- {"PCIEEP1_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 570},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 571},
- {"PCIEEP1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 571},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 572},
- {"PCIEEP1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 572},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 573},
- {"PCIEEP1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 573},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 574},
- {"PCIEEP1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 574},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 575},
- {"PCIEEP1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 575},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 576},
- {"PCIEEP1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 576},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 577},
- {"PCIEEP1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 577},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 578},
- {"PCIEEP1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 578},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 579},
- {"PCIEEP1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 579},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 580},
- {"PCIEEP1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 580},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 581},
- {"PCIEEP1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 581},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 582},
- {"PCIEEP1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 582},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 583},
- {"PCIEEP1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 583},
- {"PCIEEP0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 584},
- {"PCIEEP1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 584},
- {"PCIEEP0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 585},
- {"PCIEEP1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 585},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 586},
- {"PCIEEP1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 586},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 587},
- {"PCIEEP1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 587},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 588},
- {"PCIEEP1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 588},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 589},
- {"PCIEEP1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 589},
- {"PCIEEP0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 590},
- {"PCIEEP1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 590},
- {"PCIEEP0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 591},
- {"PCIEEP1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 591},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 592},
- {"PCIEEP1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 592},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 593},
- {"PCIEEP1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 593},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 594},
- {"PCIEEP1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 594},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 595},
- {"PCIEEP1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 595},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 596},
- {"PCIEEP1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 596},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 597},
- {"PCIEEP1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 597},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 598},
- {"PCIEEP1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 598},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 599},
- {"PCIEEP1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 599},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 600},
- {"PCIEEP1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 600},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 601},
- {"PCIEEP1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 601},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 602},
- {"PCIEEP1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 602},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 603},
- {"PCIEEP1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 603},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 604},
- {"PCIEEP1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 604},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 605},
- {"PCIEEP1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 605},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 606},
- {"PCIEEP1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 606},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 607},
- {"PCIEEP1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 607},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 608},
- {"PCIEEP1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 608},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 609},
- {"PCIEEP1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 609},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 610},
- {"PCIEEP1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 610},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 611},
- {"PCIEEP1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 611},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 612},
- {"PCIEEP1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 612},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 613},
- {"PCIEEP1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 613},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 614},
- {"PCIEEP1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 614},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 615},
- {"PCIEEP1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 615},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 616},
- {"PCIEEP1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 616},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 617},
- {"PCIEEP1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 617},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 618},
- {"PCIEEP1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 618},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 619},
- {"PCIEEP1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 619},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 620},
- {"PCIEEP1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 620},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 621},
- {"PCIEEP1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 621},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 622},
- {"PCIEEP1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 622},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 623},
- {"PCIEEP1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 623},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 624},
- {"PCIEEP1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 624},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 625},
- {"PCIEEP1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 625},
- {"PCIEEP0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 626},
- {"PCIEEP1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 626},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 627},
- {"PCIEEP1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 627},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 628},
- {"PCIEEP1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 628},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 694},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 694},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 695},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 695},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 696},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 696},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 697},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 697},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 698},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 698},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 699},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 699},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 700},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 700},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 701},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 701},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 702},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 702},
- {"PCIERC0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 703},
- {"PCIERC1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 703},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 704},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 704},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 705},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 705},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_AN002_ADV_REG" , 0x11800b0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_AN003_ADV_REG" , 0x11800b0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_AN002_EXT_ST_REG" , 0x11800b0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_AN003_EXT_ST_REG" , 0x11800b0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_AN002_LP_ABIL_REG" , 0x11800b0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_AN003_LP_ABIL_REG" , 0x11800b0001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_AN002_RESULTS_REG" , 0x11800b0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_AN003_RESULTS_REG" , 0x11800b0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_INT002_EN_REG" , 0x11800b0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_INT003_EN_REG" , 0x11800b0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PCS0_INT002_REG" , 0x11800b0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PCS0_INT003_REG" , 0x11800b0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PCS0_LINK002_TIMER_COUNT_REG", 0x11800b0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PCS0_LINK003_TIMER_COUNT_REG", 0x11800b0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PCS0_LOG_ANL002_REG" , 0x11800b0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PCS0_LOG_ANL003_REG" , 0x11800b0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PCS0_MISC002_CTL_REG" , 0x11800b0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PCS0_MISC003_CTL_REG" , 0x11800b0001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"PCS0_MR002_CONTROL_REG" , 0x11800b0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"PCS0_MR003_CONTROL_REG" , 0x11800b0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"PCS0_MR002_STATUS_REG" , 0x11800b0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"PCS0_MR003_STATUS_REG" , 0x11800b0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"PCS0_RX002_STATES_REG" , 0x11800b0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"PCS0_RX003_STATES_REG" , 0x11800b0001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"PCS0_RX002_SYNC_REG" , 0x11800b0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"PCS0_RX003_SYNC_REG" , 0x11800b0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"PCS0_SGM002_AN_ADV_REG" , 0x11800b0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"PCS0_SGM003_AN_ADV_REG" , 0x11800b0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"PCS0_SGM002_LP_ADV_REG" , 0x11800b0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"PCS0_SGM003_LP_ADV_REG" , 0x11800b0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"PCS0_TX002_STATES_REG" , 0x11800b0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"PCS0_TX003_STATES_REG" , 0x11800b0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"PCS0_TX_RX002_POLARITY_REG" , 0x11800b0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"PCS0_TX_RX003_POLARITY_REG" , 0x11800b0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"PCSX0_10GBX_STATUS_REG" , 0x11800b0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
- {"PCSX0_BIST_STATUS_REG" , 0x11800b0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800b0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"PCSX0_CONTROL1_REG" , 0x11800b0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
- {"PCSX0_CONTROL2_REG" , 0x11800b0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
- {"PCSX0_INT_EN_REG" , 0x11800b0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
- {"PCSX0_INT_REG" , 0x11800b0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"PCSX0_LOG_ANL_REG" , 0x11800b0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"PCSX0_MISC_CTL_REG" , 0x11800b0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
- {"PCSX0_RX_SYNC_STATES_REG" , 0x11800b0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"PCSX0_SPD_ABIL_REG" , 0x11800b0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
- {"PCSX0_STATUS1_REG" , 0x11800b0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
- {"PCSX0_STATUS2_REG" , 0x11800b0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
- {"PCSX0_TX_RX_POLARITY_REG" , 0x11800b0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
- {"PCSX0_TX_RX_STATES_REG" , 0x11800b0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
- {"PEM0_BAR1_INDEX000" , 0x11800c00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX001" , 0x11800c00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX002" , 0x11800c00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX003" , 0x11800c00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX004" , 0x11800c00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX005" , 0x11800c00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX006" , 0x11800c00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX007" , 0x11800c00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX008" , 0x11800c00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX009" , 0x11800c00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX010" , 0x11800c00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX011" , 0x11800c0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX012" , 0x11800c0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX013" , 0x11800c0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX014" , 0x11800c0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR1_INDEX015" , 0x11800c0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX000" , 0x11800c10000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX001" , 0x11800c10000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX002" , 0x11800c10000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX003" , 0x11800c10000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX004" , 0x11800c10000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX005" , 0x11800c10000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX006" , 0x11800c10000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX007" , 0x11800c10000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX008" , 0x11800c10000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX009" , 0x11800c10000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX010" , 0x11800c10000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX011" , 0x11800c1000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX012" , 0x11800c1000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX013" , 0x11800c1000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX014" , 0x11800c1000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM1_BAR1_INDEX015" , 0x11800c1000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"PEM0_BAR_CTL" , 0x11800c0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PEM1_BAR_CTL" , 0x11800c1000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"PEM0_BIST_STATUS" , 0x11800c0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PEM1_BIST_STATUS" , 0x11800c1000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"PEM0_BIST_STATUS2" , 0x11800c0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PEM1_BIST_STATUS2" , 0x11800c1000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"PEM0_CFG_RD" , 0x11800c0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PEM1_CFG_RD" , 0x11800c1000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"PEM0_CFG_WR" , 0x11800c0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PEM1_CFG_WR" , 0x11800c1000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"PEM0_CPL_LUT_VALID" , 0x11800c0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
- {"PEM1_CPL_LUT_VALID" , 0x11800c1000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
- {"PEM0_CTL_STATUS" , 0x11800c0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
- {"PEM1_CTL_STATUS" , 0x11800c1000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
- {"PEM0_DBG_INFO" , 0x11800c0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PEM1_DBG_INFO" , 0x11800c1000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"PEM0_DBG_INFO_EN" , 0x11800c00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PEM1_DBG_INFO_EN" , 0x11800c10000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"PEM0_DIAG_STATUS" , 0x11800c0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PEM1_DIAG_STATUS" , 0x11800c1000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"PEM0_INT_ENB" , 0x11800c0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PEM1_INT_ENB" , 0x11800c1000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"PEM0_INT_ENB_INT" , 0x11800c0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PEM1_INT_ENB_INT" , 0x11800c1000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"PEM0_INT_SUM" , 0x11800c0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PEM1_INT_SUM" , 0x11800c1000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"PEM0_P2N_BAR0_START" , 0x11800c0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PEM1_P2N_BAR0_START" , 0x11800c1000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"PEM0_P2N_BAR1_START" , 0x11800c0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PEM1_P2N_BAR1_START" , 0x11800c1000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"PEM0_P2N_BAR2_START" , 0x11800c0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PEM1_P2N_BAR2_START" , 0x11800c1000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"PEM0_P2P_BAR000_END" , 0x11800c0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PEM0_P2P_BAR001_END" , 0x11800c0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PEM0_P2P_BAR002_END" , 0x11800c0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PEM0_P2P_BAR003_END" , 0x11800c0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PEM1_P2P_BAR000_END" , 0x11800c1000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PEM1_P2P_BAR001_END" , 0x11800c1000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PEM1_P2P_BAR002_END" , 0x11800c1000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PEM1_P2P_BAR003_END" , 0x11800c1000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"PEM0_P2P_BAR000_START" , 0x11800c0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PEM0_P2P_BAR001_START" , 0x11800c0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PEM0_P2P_BAR002_START" , 0x11800c0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PEM0_P2P_BAR003_START" , 0x11800c0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PEM1_P2P_BAR000_START" , 0x11800c1000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PEM1_P2P_BAR001_START" , 0x11800c1000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PEM1_P2P_BAR002_START" , 0x11800c1000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PEM1_P2P_BAR003_START" , 0x11800c1000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PEM0_TLP_CREDITS" , 0x11800c0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PEM1_TLP_CREDITS" , 0x11800c1000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PIP_CLKEN" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PIP_DSA_SRC_GRP" , 0x11800a0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PIP_DSA_VID_GRP" , 0x11800a0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PIP_HG_PRI_QOS" , 0x11800a00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG40" , 0x11800a0000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG41" , 0x11800a0000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG42" , 0x11800a0000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_CFG43" , 0x11800a0000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG40" , 0x11800a0000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG41" , 0x11800a0000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG42" , 0x11800a0000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_PRT_TAG43" , 0x11800a0000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT36" , 0x11800a0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT37" , 0x11800a0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT38" , 0x11800a00013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT0_PRT39" , 0x11800a0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PIP_STAT10_PRT0" , 0x11800a0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT1" , 0x11800a0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT2" , 0x11800a00014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT3" , 0x11800a00014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT32" , 0x11800a0001680ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT33" , 0x11800a0001690ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT34" , 0x11800a00016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT35" , 0x11800a00016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT36" , 0x11800a00016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT37" , 0x11800a00016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT38" , 0x11800a00016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT10_PRT39" , 0x11800a00016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PIP_STAT11_PRT0" , 0x11800a0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT1" , 0x11800a0001498ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT2" , 0x11800a00014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT3" , 0x11800a00014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT32" , 0x11800a0001688ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT33" , 0x11800a0001698ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT34" , 0x11800a00016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT35" , 0x11800a00016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT36" , 0x11800a00016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT37" , 0x11800a00016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT38" , 0x11800a00016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT11_PRT39" , 0x11800a00016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT36" , 0x11800a0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT37" , 0x11800a0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT38" , 0x11800a00013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT1_PRT39" , 0x11800a0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT36" , 0x11800a0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT37" , 0x11800a00013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT38" , 0x11800a00013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT2_PRT39" , 0x11800a0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT36" , 0x11800a0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT37" , 0x11800a00013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT38" , 0x11800a00013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT3_PRT39" , 0x11800a0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT36" , 0x11800a0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT37" , 0x11800a00013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT38" , 0x11800a0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT4_PRT39" , 0x11800a0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT36" , 0x11800a0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT37" , 0x11800a00013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT38" , 0x11800a0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT5_PRT39" , 0x11800a0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT36" , 0x11800a0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT37" , 0x11800a00013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT38" , 0x11800a0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT6_PRT39" , 0x11800a0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT36" , 0x11800a0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT37" , 0x11800a00013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT38" , 0x11800a0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT7_PRT39" , 0x11800a0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT36" , 0x11800a0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT37" , 0x11800a00013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT38" , 0x11800a0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT8_PRT39" , 0x11800a0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT36" , 0x11800a0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT37" , 0x11800a00013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT38" , 0x11800a0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT9_PRT39" , 0x11800a0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS36" , 0x11800a0001e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS37" , 0x11800a0001eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS38" , 0x11800a0001ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS39" , 0x11800a0001ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS40" , 0x11800a0001f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS41" , 0x11800a0001f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS42" , 0x11800a0001f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_ERRS43" , 0x11800a0001f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS36" , 0x11800a0001e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS37" , 0x11800a0001ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS38" , 0x11800a0001ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS39" , 0x11800a0001ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS40" , 0x11800a0001f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS41" , 0x11800a0001f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS42" , 0x11800a0001f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_OCTS43" , 0x11800a0001f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS36" , 0x11800a0001e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS37" , 0x11800a0001ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS38" , 0x11800a0001ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS39" , 0x11800a0001ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS40" , 0x11800a0001f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS41" , 0x11800a0001f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS42" , 0x11800a0001f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_STAT_INB_PKTS43" , 0x11800a0001f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PIP_XSTAT0_PRT40" , 0x11800a0002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PIP_XSTAT0_PRT41" , 0x11800a0002050ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PIP_XSTAT0_PRT42" , 0x11800a00020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PIP_XSTAT0_PRT43" , 0x11800a00020f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PIP_XSTAT10_PRT40" , 0x11800a0001700ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PIP_XSTAT10_PRT41" , 0x11800a0001710ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PIP_XSTAT10_PRT42" , 0x11800a0001720ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PIP_XSTAT10_PRT43" , 0x11800a0001730ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PIP_XSTAT11_PRT40" , 0x11800a0001708ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PIP_XSTAT11_PRT41" , 0x11800a0001718ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PIP_XSTAT11_PRT42" , 0x11800a0001728ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PIP_XSTAT11_PRT43" , 0x11800a0001738ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PIP_XSTAT1_PRT40" , 0x11800a0002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PIP_XSTAT1_PRT41" , 0x11800a0002058ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PIP_XSTAT1_PRT42" , 0x11800a00020a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PIP_XSTAT1_PRT43" , 0x11800a00020f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PIP_XSTAT2_PRT40" , 0x11800a0002010ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"PIP_XSTAT2_PRT41" , 0x11800a0002060ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"PIP_XSTAT2_PRT42" , 0x11800a00020b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"PIP_XSTAT2_PRT43" , 0x11800a0002100ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"PIP_XSTAT3_PRT40" , 0x11800a0002018ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"PIP_XSTAT3_PRT41" , 0x11800a0002068ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"PIP_XSTAT3_PRT42" , 0x11800a00020b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"PIP_XSTAT3_PRT43" , 0x11800a0002108ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"PIP_XSTAT4_PRT40" , 0x11800a0002020ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"PIP_XSTAT4_PRT41" , 0x11800a0002070ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"PIP_XSTAT4_PRT42" , 0x11800a00020c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"PIP_XSTAT4_PRT43" , 0x11800a0002110ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"PIP_XSTAT5_PRT40" , 0x11800a0002028ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"PIP_XSTAT5_PRT41" , 0x11800a0002078ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"PIP_XSTAT5_PRT42" , 0x11800a00020c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"PIP_XSTAT5_PRT43" , 0x11800a0002118ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"PIP_XSTAT6_PRT40" , 0x11800a0002030ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"PIP_XSTAT6_PRT41" , 0x11800a0002080ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"PIP_XSTAT6_PRT42" , 0x11800a00020d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"PIP_XSTAT6_PRT43" , 0x11800a0002120ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"PIP_XSTAT7_PRT40" , 0x11800a0002038ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PIP_XSTAT7_PRT41" , 0x11800a0002088ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PIP_XSTAT7_PRT42" , 0x11800a00020d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PIP_XSTAT7_PRT43" , 0x11800a0002128ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PIP_XSTAT8_PRT40" , 0x11800a0002040ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PIP_XSTAT8_PRT41" , 0x11800a0002090ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PIP_XSTAT8_PRT42" , 0x11800a00020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PIP_XSTAT8_PRT43" , 0x11800a0002130ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PIP_XSTAT9_PRT40" , 0x11800a0002048ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"PIP_XSTAT9_PRT41" , 0x11800a0002098ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"PIP_XSTAT9_PRT42" , 0x11800a00020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"PIP_XSTAT9_PRT43" , 0x11800a0002138ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 812},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 813},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 817},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 819},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 820},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 821},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 822},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 823},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PKO_REG_PREEMPT" , 0x1180050000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PKO_REG_QUEUE_PREEMPT" , 0x1180050000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PKO_REG_TIMESTAMP" , 0x1180050000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 852},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 853},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 854},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 855},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 856},
- {"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 857},
- {"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 858},
- {"POW_IQ_THR0" , 0x16700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 859},
- {"POW_IQ_THR1" , 0x16700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 859},
- {"POW_IQ_THR2" , 0x16700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 859},
- {"POW_IQ_THR3" , 0x16700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 859},
- {"POW_IQ_THR4" , 0x16700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 859},
- {"POW_IQ_THR5" , 0x16700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 859},
- {"POW_IQ_THR6" , 0x16700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 859},
- {"POW_IQ_THR7" , 0x16700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 859},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 860},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 861},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 862},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 863},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 863},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 863},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 863},
- {"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 863},
- {"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 863},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 864},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 865},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 866},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 867},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 868},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 868},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 868},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 868},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 868},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 868},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 868},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 868},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 869},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 870},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 871},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 872},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 873},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 874},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 875},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 876},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 877},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 878},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 879},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 880},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 883},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 884},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 885},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 886},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 887},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 888},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 889},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 890},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 891},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 893},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 894},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 898},
- {"RNM_EER_DBG" , 0x1180040000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 899},
- {"RNM_EER_KEY" , 0x1180040000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 900},
- {"RNM_SERIAL_NUM" , 0x1180040000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 901},
- {"SLI_BIST_STATUS" , 0x11f0000010580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 902},
- {"SLI_CTL_PORT0" , 0x11f0000010050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 903},
- {"SLI_CTL_PORT1" , 0x11f0000010060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 903},
- {"SLI_CTL_STATUS" , 0x11f0000010570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 904},
- {"SLI_DATA_OUT_CNT" , 0x11f00000105f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 905},
- {"SLI_DBG_DATA" , 0x11f0000010310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 906},
- {"SLI_DBG_SELECT" , 0x11f0000010300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 907},
- {"SLI_DMA0_CNT" , 0x11f0000010400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 908},
- {"SLI_DMA1_CNT" , 0x11f0000010410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 908},
- {"SLI_DMA0_INT_LEVEL" , 0x11f00000103e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_DMA1_INT_LEVEL" , 0x11f00000103f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909},
- {"SLI_DMA0_TIM" , 0x11f0000010420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 910},
- {"SLI_DMA1_TIM" , 0x11f0000010430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 910},
- {"SLI_INT_ENB_CIU" , 0x11f0000013cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 911},
- {"SLI_INT_ENB_PORT0" , 0x11f0000010340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 912},
- {"SLI_INT_ENB_PORT1" , 0x11f0000010350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 912},
- {"SLI_INT_SUM" , 0x11f0000010330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 913},
- {"SLI_LAST_WIN_RDATA0" , 0x11f0000010600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 914},
- {"SLI_LAST_WIN_RDATA1" , 0x11f0000010610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 915},
- {"SLI_MAC_CREDIT_CNT" , 0x11f0000013d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 916},
- {"SLI_MAC_NUMBER" , 0x3e00ull, CVMX_CSR_DB_TYPE_PEXP, 64, 917},
- {"SLI_MEM_ACCESS_CTL" , 0x11f00000102f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 918},
- {"SLI_MEM_ACCESS_SUBID12" , 0x11f00000100e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID13" , 0x11f00000100f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID14" , 0x11f0000010100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID15" , 0x11f0000010110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID16" , 0x11f0000010120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID17" , 0x11f0000010130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID18" , 0x11f0000010140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID19" , 0x11f0000010150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID20" , 0x11f0000010160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID21" , 0x11f0000010170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID22" , 0x11f0000010180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID23" , 0x11f0000010190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID24" , 0x11f00000101a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID25" , 0x11f00000101b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID26" , 0x11f00000101c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MEM_ACCESS_SUBID27" , 0x11f00000101d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 919},
- {"SLI_MSI_ENB0" , 0x11f0000013c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 920},
- {"SLI_MSI_ENB1" , 0x11f0000013c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 921},
- {"SLI_MSI_ENB2" , 0x11f0000013c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 922},
- {"SLI_MSI_ENB3" , 0x11f0000013c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 923},
- {"SLI_MSI_RCV0" , 0x11f0000013c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 924},
- {"SLI_MSI_RCV1" , 0x11f0000013c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 925},
- {"SLI_MSI_RCV2" , 0x11f0000013c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 926},
- {"SLI_MSI_RCV3" , 0x11f0000013c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 927},
- {"SLI_MSI_RD_MAP" , 0x11f0000013ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 928},
- {"SLI_MSI_W1C_ENB0" , 0x11f0000013cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 929},
- {"SLI_MSI_W1C_ENB1" , 0x11f0000013d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 930},
- {"SLI_MSI_W1C_ENB2" , 0x11f0000013d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 931},
- {"SLI_MSI_W1C_ENB3" , 0x11f0000013d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932},
- {"SLI_MSI_W1S_ENB0" , 0x11f0000013d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933},
- {"SLI_MSI_W1S_ENB1" , 0x11f0000013d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934},
- {"SLI_MSI_W1S_ENB2" , 0x11f0000013d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935},
- {"SLI_MSI_W1S_ENB3" , 0x11f0000013d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936},
- {"SLI_MSI_WR_MAP" , 0x11f0000013c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937},
- {"SLI_PCIE_MSI_RCV" , 0x11f0000013cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938},
- {"SLI_PCIE_MSI_RCV_B1" , 0x11f0000010650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939},
- {"SLI_PCIE_MSI_RCV_B2" , 0x11f0000010660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940},
- {"SLI_PCIE_MSI_RCV_B3" , 0x11f0000010670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941},
- {"SLI_PKT0_CNTS" , 0x11f0000012400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT1_CNTS" , 0x11f0000012410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT2_CNTS" , 0x11f0000012420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT3_CNTS" , 0x11f0000012430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT4_CNTS" , 0x11f0000012440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT5_CNTS" , 0x11f0000012450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT6_CNTS" , 0x11f0000012460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT7_CNTS" , 0x11f0000012470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT8_CNTS" , 0x11f0000012480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT9_CNTS" , 0x11f0000012490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT10_CNTS" , 0x11f00000124a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT11_CNTS" , 0x11f00000124b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT12_CNTS" , 0x11f00000124c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT13_CNTS" , 0x11f00000124d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT14_CNTS" , 0x11f00000124e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT15_CNTS" , 0x11f00000124f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT16_CNTS" , 0x11f0000012500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT17_CNTS" , 0x11f0000012510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT18_CNTS" , 0x11f0000012520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT19_CNTS" , 0x11f0000012530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT20_CNTS" , 0x11f0000012540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT21_CNTS" , 0x11f0000012550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT22_CNTS" , 0x11f0000012560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT23_CNTS" , 0x11f0000012570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT24_CNTS" , 0x11f0000012580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT25_CNTS" , 0x11f0000012590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT26_CNTS" , 0x11f00000125a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT27_CNTS" , 0x11f00000125b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT28_CNTS" , 0x11f00000125c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT29_CNTS" , 0x11f00000125d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT30_CNTS" , 0x11f00000125e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT31_CNTS" , 0x11f00000125f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942},
- {"SLI_PKT0_IN_BP" , 0x11f0000013800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT1_IN_BP" , 0x11f0000013810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT2_IN_BP" , 0x11f0000013820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT3_IN_BP" , 0x11f0000013830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT4_IN_BP" , 0x11f0000013840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT5_IN_BP" , 0x11f0000013850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT6_IN_BP" , 0x11f0000013860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT7_IN_BP" , 0x11f0000013870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT8_IN_BP" , 0x11f0000013880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT9_IN_BP" , 0x11f0000013890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT10_IN_BP" , 0x11f00000138a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT11_IN_BP" , 0x11f00000138b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT12_IN_BP" , 0x11f00000138c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT13_IN_BP" , 0x11f00000138d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT14_IN_BP" , 0x11f00000138e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT15_IN_BP" , 0x11f00000138f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT16_IN_BP" , 0x11f0000013900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT17_IN_BP" , 0x11f0000013910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT18_IN_BP" , 0x11f0000013920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT19_IN_BP" , 0x11f0000013930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT20_IN_BP" , 0x11f0000013940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT21_IN_BP" , 0x11f0000013950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT22_IN_BP" , 0x11f0000013960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT23_IN_BP" , 0x11f0000013970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT24_IN_BP" , 0x11f0000013980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT25_IN_BP" , 0x11f0000013990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT26_IN_BP" , 0x11f00000139a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT27_IN_BP" , 0x11f00000139b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT28_IN_BP" , 0x11f00000139c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT29_IN_BP" , 0x11f00000139d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT30_IN_BP" , 0x11f00000139e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT31_IN_BP" , 0x11f00000139f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943},
- {"SLI_PKT0_INSTR_BADDR" , 0x11f0000012800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT1_INSTR_BADDR" , 0x11f0000012810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT2_INSTR_BADDR" , 0x11f0000012820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT3_INSTR_BADDR" , 0x11f0000012830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT4_INSTR_BADDR" , 0x11f0000012840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT5_INSTR_BADDR" , 0x11f0000012850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT6_INSTR_BADDR" , 0x11f0000012860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT7_INSTR_BADDR" , 0x11f0000012870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT8_INSTR_BADDR" , 0x11f0000012880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT9_INSTR_BADDR" , 0x11f0000012890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT10_INSTR_BADDR" , 0x11f00000128a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT11_INSTR_BADDR" , 0x11f00000128b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT12_INSTR_BADDR" , 0x11f00000128c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT13_INSTR_BADDR" , 0x11f00000128d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT14_INSTR_BADDR" , 0x11f00000128e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT15_INSTR_BADDR" , 0x11f00000128f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT16_INSTR_BADDR" , 0x11f0000012900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT17_INSTR_BADDR" , 0x11f0000012910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT18_INSTR_BADDR" , 0x11f0000012920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT19_INSTR_BADDR" , 0x11f0000012930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT20_INSTR_BADDR" , 0x11f0000012940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT21_INSTR_BADDR" , 0x11f0000012950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT22_INSTR_BADDR" , 0x11f0000012960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT23_INSTR_BADDR" , 0x11f0000012970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT24_INSTR_BADDR" , 0x11f0000012980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT25_INSTR_BADDR" , 0x11f0000012990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT26_INSTR_BADDR" , 0x11f00000129a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT27_INSTR_BADDR" , 0x11f00000129b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT28_INSTR_BADDR" , 0x11f00000129c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT29_INSTR_BADDR" , 0x11f00000129d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT30_INSTR_BADDR" , 0x11f00000129e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT31_INSTR_BADDR" , 0x11f00000129f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944},
- {"SLI_PKT0_INSTR_BAOFF_DBELL" , 0x11f0000012c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT1_INSTR_BAOFF_DBELL" , 0x11f0000012c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT2_INSTR_BAOFF_DBELL" , 0x11f0000012c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT3_INSTR_BAOFF_DBELL" , 0x11f0000012c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT4_INSTR_BAOFF_DBELL" , 0x11f0000012c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT5_INSTR_BAOFF_DBELL" , 0x11f0000012c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT6_INSTR_BAOFF_DBELL" , 0x11f0000012c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT7_INSTR_BAOFF_DBELL" , 0x11f0000012c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT8_INSTR_BAOFF_DBELL" , 0x11f0000012c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT9_INSTR_BAOFF_DBELL" , 0x11f0000012c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT10_INSTR_BAOFF_DBELL" , 0x11f0000012ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT11_INSTR_BAOFF_DBELL" , 0x11f0000012cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT12_INSTR_BAOFF_DBELL" , 0x11f0000012cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT13_INSTR_BAOFF_DBELL" , 0x11f0000012cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT14_INSTR_BAOFF_DBELL" , 0x11f0000012ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT15_INSTR_BAOFF_DBELL" , 0x11f0000012cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT16_INSTR_BAOFF_DBELL" , 0x11f0000012d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT17_INSTR_BAOFF_DBELL" , 0x11f0000012d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT18_INSTR_BAOFF_DBELL" , 0x11f0000012d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT19_INSTR_BAOFF_DBELL" , 0x11f0000012d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT20_INSTR_BAOFF_DBELL" , 0x11f0000012d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT21_INSTR_BAOFF_DBELL" , 0x11f0000012d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT22_INSTR_BAOFF_DBELL" , 0x11f0000012d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT23_INSTR_BAOFF_DBELL" , 0x11f0000012d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT24_INSTR_BAOFF_DBELL" , 0x11f0000012d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT25_INSTR_BAOFF_DBELL" , 0x11f0000012d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT26_INSTR_BAOFF_DBELL" , 0x11f0000012da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT27_INSTR_BAOFF_DBELL" , 0x11f0000012db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT28_INSTR_BAOFF_DBELL" , 0x11f0000012dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT29_INSTR_BAOFF_DBELL" , 0x11f0000012dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT30_INSTR_BAOFF_DBELL" , 0x11f0000012de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT31_INSTR_BAOFF_DBELL" , 0x11f0000012df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945},
- {"SLI_PKT0_INSTR_FIFO_RSIZE" , 0x11f0000013000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT1_INSTR_FIFO_RSIZE" , 0x11f0000013010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT2_INSTR_FIFO_RSIZE" , 0x11f0000013020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT3_INSTR_FIFO_RSIZE" , 0x11f0000013030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT4_INSTR_FIFO_RSIZE" , 0x11f0000013040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT5_INSTR_FIFO_RSIZE" , 0x11f0000013050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT6_INSTR_FIFO_RSIZE" , 0x11f0000013060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT7_INSTR_FIFO_RSIZE" , 0x11f0000013070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT8_INSTR_FIFO_RSIZE" , 0x11f0000013080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT9_INSTR_FIFO_RSIZE" , 0x11f0000013090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT10_INSTR_FIFO_RSIZE" , 0x11f00000130a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT11_INSTR_FIFO_RSIZE" , 0x11f00000130b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT12_INSTR_FIFO_RSIZE" , 0x11f00000130c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT13_INSTR_FIFO_RSIZE" , 0x11f00000130d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT14_INSTR_FIFO_RSIZE" , 0x11f00000130e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT15_INSTR_FIFO_RSIZE" , 0x11f00000130f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT16_INSTR_FIFO_RSIZE" , 0x11f0000013100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT17_INSTR_FIFO_RSIZE" , 0x11f0000013110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT18_INSTR_FIFO_RSIZE" , 0x11f0000013120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT19_INSTR_FIFO_RSIZE" , 0x11f0000013130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT20_INSTR_FIFO_RSIZE" , 0x11f0000013140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT21_INSTR_FIFO_RSIZE" , 0x11f0000013150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT22_INSTR_FIFO_RSIZE" , 0x11f0000013160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT23_INSTR_FIFO_RSIZE" , 0x11f0000013170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT24_INSTR_FIFO_RSIZE" , 0x11f0000013180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT25_INSTR_FIFO_RSIZE" , 0x11f0000013190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT26_INSTR_FIFO_RSIZE" , 0x11f00000131a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT27_INSTR_FIFO_RSIZE" , 0x11f00000131b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT28_INSTR_FIFO_RSIZE" , 0x11f00000131c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT29_INSTR_FIFO_RSIZE" , 0x11f00000131d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT30_INSTR_FIFO_RSIZE" , 0x11f00000131e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT31_INSTR_FIFO_RSIZE" , 0x11f00000131f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946},
- {"SLI_PKT0_INSTR_HEADER" , 0x11f0000013400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT1_INSTR_HEADER" , 0x11f0000013410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT2_INSTR_HEADER" , 0x11f0000013420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT3_INSTR_HEADER" , 0x11f0000013430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT4_INSTR_HEADER" , 0x11f0000013440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT5_INSTR_HEADER" , 0x11f0000013450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT6_INSTR_HEADER" , 0x11f0000013460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT7_INSTR_HEADER" , 0x11f0000013470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT8_INSTR_HEADER" , 0x11f0000013480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT9_INSTR_HEADER" , 0x11f0000013490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT10_INSTR_HEADER" , 0x11f00000134a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT11_INSTR_HEADER" , 0x11f00000134b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT12_INSTR_HEADER" , 0x11f00000134c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT13_INSTR_HEADER" , 0x11f00000134d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT14_INSTR_HEADER" , 0x11f00000134e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT15_INSTR_HEADER" , 0x11f00000134f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT16_INSTR_HEADER" , 0x11f0000013500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT17_INSTR_HEADER" , 0x11f0000013510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT18_INSTR_HEADER" , 0x11f0000013520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT19_INSTR_HEADER" , 0x11f0000013530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT20_INSTR_HEADER" , 0x11f0000013540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT21_INSTR_HEADER" , 0x11f0000013550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT22_INSTR_HEADER" , 0x11f0000013560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT23_INSTR_HEADER" , 0x11f0000013570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT24_INSTR_HEADER" , 0x11f0000013580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT25_INSTR_HEADER" , 0x11f0000013590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT26_INSTR_HEADER" , 0x11f00000135a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT27_INSTR_HEADER" , 0x11f00000135b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT28_INSTR_HEADER" , 0x11f00000135c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT29_INSTR_HEADER" , 0x11f00000135d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT30_INSTR_HEADER" , 0x11f00000135e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT31_INSTR_HEADER" , 0x11f00000135f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947},
- {"SLI_PKT0_OUT_SIZE" , 0x11f0000010c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT1_OUT_SIZE" , 0x11f0000010c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT2_OUT_SIZE" , 0x11f0000010c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT3_OUT_SIZE" , 0x11f0000010c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT4_OUT_SIZE" , 0x11f0000010c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT5_OUT_SIZE" , 0x11f0000010c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT6_OUT_SIZE" , 0x11f0000010c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT7_OUT_SIZE" , 0x11f0000010c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT8_OUT_SIZE" , 0x11f0000010c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT9_OUT_SIZE" , 0x11f0000010c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT10_OUT_SIZE" , 0x11f0000010ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT11_OUT_SIZE" , 0x11f0000010cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT12_OUT_SIZE" , 0x11f0000010cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT13_OUT_SIZE" , 0x11f0000010cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT14_OUT_SIZE" , 0x11f0000010ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT15_OUT_SIZE" , 0x11f0000010cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT16_OUT_SIZE" , 0x11f0000010d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT17_OUT_SIZE" , 0x11f0000010d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT18_OUT_SIZE" , 0x11f0000010d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT19_OUT_SIZE" , 0x11f0000010d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT20_OUT_SIZE" , 0x11f0000010d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT21_OUT_SIZE" , 0x11f0000010d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT22_OUT_SIZE" , 0x11f0000010d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT23_OUT_SIZE" , 0x11f0000010d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT24_OUT_SIZE" , 0x11f0000010d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT25_OUT_SIZE" , 0x11f0000010d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT26_OUT_SIZE" , 0x11f0000010da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT27_OUT_SIZE" , 0x11f0000010db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT28_OUT_SIZE" , 0x11f0000010dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT29_OUT_SIZE" , 0x11f0000010dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT30_OUT_SIZE" , 0x11f0000010de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT31_OUT_SIZE" , 0x11f0000010df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 948},
- {"SLI_PKT0_SLIST_BADDR" , 0x11f0000011400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT1_SLIST_BADDR" , 0x11f0000011410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT2_SLIST_BADDR" , 0x11f0000011420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT3_SLIST_BADDR" , 0x11f0000011430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT4_SLIST_BADDR" , 0x11f0000011440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT5_SLIST_BADDR" , 0x11f0000011450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT6_SLIST_BADDR" , 0x11f0000011460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT7_SLIST_BADDR" , 0x11f0000011470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT8_SLIST_BADDR" , 0x11f0000011480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT9_SLIST_BADDR" , 0x11f0000011490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT10_SLIST_BADDR" , 0x11f00000114a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT11_SLIST_BADDR" , 0x11f00000114b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT12_SLIST_BADDR" , 0x11f00000114c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT13_SLIST_BADDR" , 0x11f00000114d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT14_SLIST_BADDR" , 0x11f00000114e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT15_SLIST_BADDR" , 0x11f00000114f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT16_SLIST_BADDR" , 0x11f0000011500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT17_SLIST_BADDR" , 0x11f0000011510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT18_SLIST_BADDR" , 0x11f0000011520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT19_SLIST_BADDR" , 0x11f0000011530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT20_SLIST_BADDR" , 0x11f0000011540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT21_SLIST_BADDR" , 0x11f0000011550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT22_SLIST_BADDR" , 0x11f0000011560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT23_SLIST_BADDR" , 0x11f0000011570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT24_SLIST_BADDR" , 0x11f0000011580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT25_SLIST_BADDR" , 0x11f0000011590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT26_SLIST_BADDR" , 0x11f00000115a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT27_SLIST_BADDR" , 0x11f00000115b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT28_SLIST_BADDR" , 0x11f00000115c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT29_SLIST_BADDR" , 0x11f00000115d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT30_SLIST_BADDR" , 0x11f00000115e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT31_SLIST_BADDR" , 0x11f00000115f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 949},
- {"SLI_PKT0_SLIST_BAOFF_DBELL" , 0x11f0000011800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT1_SLIST_BAOFF_DBELL" , 0x11f0000011810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT2_SLIST_BAOFF_DBELL" , 0x11f0000011820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT3_SLIST_BAOFF_DBELL" , 0x11f0000011830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT4_SLIST_BAOFF_DBELL" , 0x11f0000011840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT5_SLIST_BAOFF_DBELL" , 0x11f0000011850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT6_SLIST_BAOFF_DBELL" , 0x11f0000011860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT7_SLIST_BAOFF_DBELL" , 0x11f0000011870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT8_SLIST_BAOFF_DBELL" , 0x11f0000011880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT9_SLIST_BAOFF_DBELL" , 0x11f0000011890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT10_SLIST_BAOFF_DBELL" , 0x11f00000118a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT11_SLIST_BAOFF_DBELL" , 0x11f00000118b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT12_SLIST_BAOFF_DBELL" , 0x11f00000118c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT13_SLIST_BAOFF_DBELL" , 0x11f00000118d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT14_SLIST_BAOFF_DBELL" , 0x11f00000118e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT15_SLIST_BAOFF_DBELL" , 0x11f00000118f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT16_SLIST_BAOFF_DBELL" , 0x11f0000011900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT17_SLIST_BAOFF_DBELL" , 0x11f0000011910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT18_SLIST_BAOFF_DBELL" , 0x11f0000011920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT19_SLIST_BAOFF_DBELL" , 0x11f0000011930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT20_SLIST_BAOFF_DBELL" , 0x11f0000011940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT21_SLIST_BAOFF_DBELL" , 0x11f0000011950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT22_SLIST_BAOFF_DBELL" , 0x11f0000011960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT23_SLIST_BAOFF_DBELL" , 0x11f0000011970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT24_SLIST_BAOFF_DBELL" , 0x11f0000011980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT25_SLIST_BAOFF_DBELL" , 0x11f0000011990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT26_SLIST_BAOFF_DBELL" , 0x11f00000119a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT27_SLIST_BAOFF_DBELL" , 0x11f00000119b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT28_SLIST_BAOFF_DBELL" , 0x11f00000119c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT29_SLIST_BAOFF_DBELL" , 0x11f00000119d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT30_SLIST_BAOFF_DBELL" , 0x11f00000119e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT31_SLIST_BAOFF_DBELL" , 0x11f00000119f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 950},
- {"SLI_PKT0_SLIST_FIFO_RSIZE" , 0x11f0000011c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT1_SLIST_FIFO_RSIZE" , 0x11f0000011c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT2_SLIST_FIFO_RSIZE" , 0x11f0000011c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT3_SLIST_FIFO_RSIZE" , 0x11f0000011c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT4_SLIST_FIFO_RSIZE" , 0x11f0000011c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT5_SLIST_FIFO_RSIZE" , 0x11f0000011c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT6_SLIST_FIFO_RSIZE" , 0x11f0000011c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT7_SLIST_FIFO_RSIZE" , 0x11f0000011c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT8_SLIST_FIFO_RSIZE" , 0x11f0000011c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT9_SLIST_FIFO_RSIZE" , 0x11f0000011c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT10_SLIST_FIFO_RSIZE" , 0x11f0000011ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT11_SLIST_FIFO_RSIZE" , 0x11f0000011cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT12_SLIST_FIFO_RSIZE" , 0x11f0000011cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT13_SLIST_FIFO_RSIZE" , 0x11f0000011cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT14_SLIST_FIFO_RSIZE" , 0x11f0000011ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT15_SLIST_FIFO_RSIZE" , 0x11f0000011cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT16_SLIST_FIFO_RSIZE" , 0x11f0000011d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT17_SLIST_FIFO_RSIZE" , 0x11f0000011d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT18_SLIST_FIFO_RSIZE" , 0x11f0000011d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT19_SLIST_FIFO_RSIZE" , 0x11f0000011d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT20_SLIST_FIFO_RSIZE" , 0x11f0000011d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT21_SLIST_FIFO_RSIZE" , 0x11f0000011d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT22_SLIST_FIFO_RSIZE" , 0x11f0000011d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT23_SLIST_FIFO_RSIZE" , 0x11f0000011d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT24_SLIST_FIFO_RSIZE" , 0x11f0000011d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT25_SLIST_FIFO_RSIZE" , 0x11f0000011d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT26_SLIST_FIFO_RSIZE" , 0x11f0000011da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT27_SLIST_FIFO_RSIZE" , 0x11f0000011db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT28_SLIST_FIFO_RSIZE" , 0x11f0000011dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT29_SLIST_FIFO_RSIZE" , 0x11f0000011dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT30_SLIST_FIFO_RSIZE" , 0x11f0000011de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT31_SLIST_FIFO_RSIZE" , 0x11f0000011df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 951},
- {"SLI_PKT_CNT_INT" , 0x11f0000011130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 952},
- {"SLI_PKT_CNT_INT_ENB" , 0x11f0000011150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 953},
- {"SLI_PKT_CTL" , 0x11f0000011220ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 954},
- {"SLI_PKT_DATA_OUT_ES" , 0x11f00000110b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 955},
- {"SLI_PKT_DATA_OUT_NS" , 0x11f00000110a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 956},
- {"SLI_PKT_DATA_OUT_ROR" , 0x11f0000011090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 957},
- {"SLI_PKT_DPADDR" , 0x11f0000011080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 958},
- {"SLI_PKT_IN_BP" , 0x11f0000011210ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 959},
- {"SLI_PKT_IN_DONE0_CNTS" , 0x11f0000012000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE1_CNTS" , 0x11f0000012010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE2_CNTS" , 0x11f0000012020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE3_CNTS" , 0x11f0000012030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE4_CNTS" , 0x11f0000012040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE5_CNTS" , 0x11f0000012050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE6_CNTS" , 0x11f0000012060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE7_CNTS" , 0x11f0000012070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE8_CNTS" , 0x11f0000012080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE9_CNTS" , 0x11f0000012090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE10_CNTS" , 0x11f00000120a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE11_CNTS" , 0x11f00000120b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE12_CNTS" , 0x11f00000120c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE13_CNTS" , 0x11f00000120d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE14_CNTS" , 0x11f00000120e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE15_CNTS" , 0x11f00000120f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE16_CNTS" , 0x11f0000012100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE17_CNTS" , 0x11f0000012110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE18_CNTS" , 0x11f0000012120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE19_CNTS" , 0x11f0000012130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE20_CNTS" , 0x11f0000012140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE21_CNTS" , 0x11f0000012150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE22_CNTS" , 0x11f0000012160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE23_CNTS" , 0x11f0000012170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE24_CNTS" , 0x11f0000012180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE25_CNTS" , 0x11f0000012190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE26_CNTS" , 0x11f00000121a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE27_CNTS" , 0x11f00000121b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE28_CNTS" , 0x11f00000121c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE29_CNTS" , 0x11f00000121d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE30_CNTS" , 0x11f00000121e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_DONE31_CNTS" , 0x11f00000121f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_PKT_IN_INSTR_COUNTS" , 0x11f0000011200ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 961},
- {"SLI_PKT_IN_PCIE_PORT" , 0x11f00000111b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 962},
- {"SLI_PKT_INPUT_CONTROL" , 0x11f0000011170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 963},
- {"SLI_PKT_INSTR_ENB" , 0x11f0000011000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 964},
- {"SLI_PKT_INSTR_RD_SIZE" , 0x11f00000111a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 965},
- {"SLI_PKT_INSTR_SIZE" , 0x11f0000011020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 966},
- {"SLI_PKT_INT_LEVELS" , 0x11f0000011120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 967},
- {"SLI_PKT_IPTR" , 0x11f0000011070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 968},
- {"SLI_PKT_OUT_BMODE" , 0x11f00000110d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_PKT_OUT_ENB" , 0x11f0000011010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 970},
- {"SLI_PKT_OUTPUT_WMARK" , 0x11f0000011180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 971},
- {"SLI_PKT_PCIE_PORT" , 0x11f00000110e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 972},
- {"SLI_PKT_PORT_IN_RST" , 0x11f00000111f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 973},
- {"SLI_PKT_SLIST_ES" , 0x11f0000011050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 974},
- {"SLI_PKT_SLIST_NS" , 0x11f0000011040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 975},
- {"SLI_PKT_SLIST_ROR" , 0x11f0000011030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 976},
- {"SLI_PKT_TIME_INT" , 0x11f0000011140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_PKT_TIME_INT_ENB" , 0x11f0000011160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 978},
- {"SLI_S2M_PORT0_CTL" , 0x11f0000013d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 979},
- {"SLI_S2M_PORT1_CTL" , 0x11f0000013d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 979},
- {"SLI_SCRATCH_1" , 0x11f00000103c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 980},
- {"SLI_SCRATCH_2" , 0x11f00000103d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 981},
- {"SLI_STATE1" , 0x11f0000010620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 982},
- {"SLI_STATE2" , 0x11f0000010630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 983},
- {"SLI_STATE3" , 0x11f0000010640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 984},
- {"SLI_WIN_RD_ADDR" , 0x10ull, CVMX_CSR_DB_TYPE_PEXP, 64, 985},
- {"SLI_WIN_RD_DATA" , 0x40ull, CVMX_CSR_DB_TYPE_PEXP, 64, 986},
- {"SLI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PEXP, 64, 987},
- {"SLI_WIN_WR_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PEXP, 64, 988},
- {"SLI_WIN_WR_MASK" , 0x30ull, CVMX_CSR_DB_TYPE_PEXP, 64, 989},
- {"SLI_WINDOW_CTL" , 0x11f00000102e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 990},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 991},
- {"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 991},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 992},
- {"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 992},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 993},
- {"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 993},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"SMI_DRV_CTL" , 0x1180000001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 996},
- {"SRIO0_ACC_CTRL" , 0x11800c8000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 997},
- {"SRIO1_ACC_CTRL" , 0x11800c9000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 997},
- {"SRIO0_ASMBLY_ID" , 0x11800c8000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 998},
- {"SRIO1_ASMBLY_ID" , 0x11800c9000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 998},
- {"SRIO0_ASMBLY_INFO" , 0x11800c8000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 999},
- {"SRIO1_ASMBLY_INFO" , 0x11800c9000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 999},
- {"SRIO0_BELL_RESP_CTRL" , 0x11800c8000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1000},
- {"SRIO1_BELL_RESP_CTRL" , 0x11800c9000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1000},
- {"SRIO0_BIST_STATUS" , 0x11800c8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1001},
- {"SRIO1_BIST_STATUS" , 0x11800c9000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1001},
- {"SRIO0_IMSG_CTRL" , 0x11800c8000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1002},
- {"SRIO1_IMSG_CTRL" , 0x11800c9000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1002},
- {"SRIO0_IMSG_INST_HDR000" , 0x11800c8000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1003},
- {"SRIO0_IMSG_INST_HDR001" , 0x11800c8000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1003},
- {"SRIO1_IMSG_INST_HDR000" , 0x11800c9000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1003},
- {"SRIO1_IMSG_INST_HDR001" , 0x11800c9000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1003},
- {"SRIO0_IMSG_QOS_GRP000" , 0x11800c8000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP001" , 0x11800c8000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP002" , 0x11800c8000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP003" , 0x11800c8000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP004" , 0x11800c8000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP005" , 0x11800c8000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP006" , 0x11800c8000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP007" , 0x11800c8000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP008" , 0x11800c8000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP009" , 0x11800c8000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP010" , 0x11800c8000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP011" , 0x11800c8000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP012" , 0x11800c8000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP013" , 0x11800c8000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP014" , 0x11800c8000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP015" , 0x11800c8000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP016" , 0x11800c8000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP017" , 0x11800c8000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP018" , 0x11800c8000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP019" , 0x11800c8000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP020" , 0x11800c80006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP021" , 0x11800c80006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP022" , 0x11800c80006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP023" , 0x11800c80006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP024" , 0x11800c80006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP025" , 0x11800c80006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP026" , 0x11800c80006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP027" , 0x11800c80006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP028" , 0x11800c80006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP029" , 0x11800c80006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP030" , 0x11800c80006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_QOS_GRP031" , 0x11800c80006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP000" , 0x11800c9000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP001" , 0x11800c9000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP002" , 0x11800c9000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP003" , 0x11800c9000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP004" , 0x11800c9000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP005" , 0x11800c9000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP006" , 0x11800c9000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP007" , 0x11800c9000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP008" , 0x11800c9000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP009" , 0x11800c9000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP010" , 0x11800c9000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP011" , 0x11800c9000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP012" , 0x11800c9000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP013" , 0x11800c9000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP014" , 0x11800c9000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP015" , 0x11800c9000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP016" , 0x11800c9000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP017" , 0x11800c9000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP018" , 0x11800c9000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP019" , 0x11800c9000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP020" , 0x11800c90006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP021" , 0x11800c90006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP022" , 0x11800c90006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP023" , 0x11800c90006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP024" , 0x11800c90006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP025" , 0x11800c90006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP026" , 0x11800c90006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP027" , 0x11800c90006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP028" , 0x11800c90006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP029" , 0x11800c90006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP030" , 0x11800c90006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO1_IMSG_QOS_GRP031" , 0x11800c90006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"SRIO0_IMSG_STATUS000" , 0x11800c8000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS001" , 0x11800c8000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS002" , 0x11800c8000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS003" , 0x11800c8000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS004" , 0x11800c8000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS005" , 0x11800c8000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS006" , 0x11800c8000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS007" , 0x11800c8000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS008" , 0x11800c8000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS009" , 0x11800c8000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS010" , 0x11800c8000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS011" , 0x11800c8000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS012" , 0x11800c8000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS013" , 0x11800c8000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS014" , 0x11800c8000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS015" , 0x11800c8000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS016" , 0x11800c8000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS017" , 0x11800c8000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS018" , 0x11800c8000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS019" , 0x11800c8000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS020" , 0x11800c80007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS021" , 0x11800c80007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS022" , 0x11800c80007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_STATUS023" , 0x11800c80007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS000" , 0x11800c9000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS001" , 0x11800c9000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS002" , 0x11800c9000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS003" , 0x11800c9000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS004" , 0x11800c9000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS005" , 0x11800c9000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS006" , 0x11800c9000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS007" , 0x11800c9000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS008" , 0x11800c9000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS009" , 0x11800c9000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS010" , 0x11800c9000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS011" , 0x11800c9000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS012" , 0x11800c9000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS013" , 0x11800c9000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS014" , 0x11800c9000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS015" , 0x11800c9000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS016" , 0x11800c9000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS017" , 0x11800c9000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS018" , 0x11800c9000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS019" , 0x11800c9000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS020" , 0x11800c90007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS021" , 0x11800c90007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS022" , 0x11800c90007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO1_IMSG_STATUS023" , 0x11800c90007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"SRIO0_IMSG_VPORT_THR" , 0x11800c8000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"SRIO1_IMSG_VPORT_THR" , 0x11800c9000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"SRIO0_INT2_ENABLE" , 0x11800c80003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"SRIO1_INT2_ENABLE" , 0x11800c90003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"SRIO0_INT2_REG" , 0x11800c80003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"SRIO1_INT2_REG" , 0x11800c90003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"SRIO0_INT_ENABLE" , 0x11800c8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1009},
- {"SRIO1_INT_ENABLE" , 0x11800c9000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1009},
- {"SRIO0_INT_INFO0" , 0x11800c8000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1010},
- {"SRIO1_INT_INFO0" , 0x11800c9000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1010},
- {"SRIO0_INT_INFO1" , 0x11800c8000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"SRIO1_INT_INFO1" , 0x11800c9000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"SRIO0_INT_INFO2" , 0x11800c8000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"SRIO1_INT_INFO2" , 0x11800c9000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"SRIO0_INT_INFO3" , 0x11800c8000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"SRIO1_INT_INFO3" , 0x11800c9000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"SRIO0_INT_REG" , 0x11800c8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"SRIO1_INT_REG" , 0x11800c9000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"SRIO0_IP_FEATURE" , 0x11800c80003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"SRIO1_IP_FEATURE" , 0x11800c90003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"SRIO0_MAC_BUFFERS" , 0x11800c8000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO1_MAC_BUFFERS" , 0x11800c9000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"SRIO0_MAINT_OP" , 0x11800c8000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"SRIO1_MAINT_OP" , 0x11800c9000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"SRIO0_MAINT_RD_DATA" , 0x11800c8000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"SRIO1_MAINT_RD_DATA" , 0x11800c9000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"SRIO0_MCE_TX_CTL" , 0x11800c8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"SRIO1_MCE_TX_CTL" , 0x11800c9000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"SRIO0_MEM_OP_CTRL" , 0x11800c8000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"SRIO1_MEM_OP_CTRL" , 0x11800c9000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"SRIO0_OMSG_CTRL000" , 0x11800c8000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"SRIO0_OMSG_CTRL001" , 0x11800c80004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"SRIO1_OMSG_CTRL000" , 0x11800c9000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"SRIO1_OMSG_CTRL001" , 0x11800c90004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"SRIO0_OMSG_DONE_COUNTS000" , 0x11800c80004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"SRIO0_OMSG_DONE_COUNTS001" , 0x11800c80004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"SRIO1_OMSG_DONE_COUNTS000" , 0x11800c90004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"SRIO1_OMSG_DONE_COUNTS001" , 0x11800c90004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"SRIO0_OMSG_FMP_MR000" , 0x11800c8000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1023},
- {"SRIO0_OMSG_FMP_MR001" , 0x11800c80004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1023},
- {"SRIO1_OMSG_FMP_MR000" , 0x11800c9000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1023},
- {"SRIO1_OMSG_FMP_MR001" , 0x11800c90004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1023},
- {"SRIO0_OMSG_NMP_MR000" , 0x11800c80004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"SRIO0_OMSG_NMP_MR001" , 0x11800c80004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"SRIO1_OMSG_NMP_MR000" , 0x11800c90004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"SRIO1_OMSG_NMP_MR001" , 0x11800c90004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"SRIO0_OMSG_PORT000" , 0x11800c8000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"SRIO0_OMSG_PORT001" , 0x11800c80004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"SRIO1_OMSG_PORT000" , 0x11800c9000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"SRIO1_OMSG_PORT001" , 0x11800c90004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"SRIO0_OMSG_SILO_THR" , 0x11800c80004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"SRIO1_OMSG_SILO_THR" , 0x11800c90004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"SRIO0_OMSG_SP_MR000" , 0x11800c8000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"SRIO0_OMSG_SP_MR001" , 0x11800c80004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"SRIO1_OMSG_SP_MR000" , 0x11800c9000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"SRIO1_OMSG_SP_MR001" , 0x11800c90004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"SRIO0_PRIO000_IN_USE" , 0x11800c80003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"SRIO0_PRIO001_IN_USE" , 0x11800c80003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"SRIO0_PRIO002_IN_USE" , 0x11800c80003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"SRIO0_PRIO003_IN_USE" , 0x11800c80003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"SRIO1_PRIO000_IN_USE" , 0x11800c90003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"SRIO1_PRIO001_IN_USE" , 0x11800c90003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"SRIO1_PRIO002_IN_USE" , 0x11800c90003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"SRIO1_PRIO003_IN_USE" , 0x11800c90003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"SRIO0_RX_BELL" , 0x11800c8000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1029},
- {"SRIO1_RX_BELL" , 0x11800c9000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1029},
- {"SRIO0_RX_BELL_SEQ" , 0x11800c8000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1030},
- {"SRIO1_RX_BELL_SEQ" , 0x11800c9000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1030},
- {"SRIO0_RX_STATUS" , 0x11800c8000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"SRIO1_RX_STATUS" , 0x11800c9000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"SRIO0_S2M_TYPE000" , 0x11800c8000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE001" , 0x11800c8000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE002" , 0x11800c8000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE003" , 0x11800c8000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE004" , 0x11800c80001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE005" , 0x11800c80001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE006" , 0x11800c80001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE007" , 0x11800c80001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE008" , 0x11800c80001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE009" , 0x11800c80001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE010" , 0x11800c80001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE011" , 0x11800c80001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE012" , 0x11800c80001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE013" , 0x11800c80001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE014" , 0x11800c80001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_S2M_TYPE015" , 0x11800c80001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE000" , 0x11800c9000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE001" , 0x11800c9000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE002" , 0x11800c9000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE003" , 0x11800c9000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE004" , 0x11800c90001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE005" , 0x11800c90001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE006" , 0x11800c90001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE007" , 0x11800c90001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE008" , 0x11800c90001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE009" , 0x11800c90001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE010" , 0x11800c90001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE011" , 0x11800c90001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE012" , 0x11800c90001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE013" , 0x11800c90001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE014" , 0x11800c90001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO1_S2M_TYPE015" , 0x11800c90001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"SRIO0_SEQ" , 0x11800c8000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"SRIO1_SEQ" , 0x11800c9000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"SRIO0_STATUS_REG" , 0x11800c8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"SRIO1_STATUS_REG" , 0x11800c9000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"SRIO0_TAG_CTRL" , 0x11800c8000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"SRIO1_TAG_CTRL" , 0x11800c9000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"SRIO0_TLP_CREDITS" , 0x11800c8000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"SRIO1_TLP_CREDITS" , 0x11800c9000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"SRIO0_TX_BELL" , 0x11800c8000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"SRIO1_TX_BELL" , 0x11800c9000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"SRIO0_TX_BELL_INFO" , 0x11800c8000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"SRIO1_TX_BELL_INFO" , 0x11800c9000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"SRIO0_TX_CTRL" , 0x11800c8000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"SRIO1_TX_CTRL" , 0x11800c9000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"SRIO0_TX_EMPHASIS" , 0x11800c80003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"SRIO1_TX_EMPHASIS" , 0x11800c90003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"SRIO0_TX_STATUS" , 0x11800c8000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"SRIO1_TX_STATUS" , 0x11800c9000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"SRIO0_WR_DONE_COUNTS" , 0x11800c8000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"SRIO1_WR_DONE_COUNTS" , 0x11800c9000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"SRIOMAINT0_ASMBLY_ID" , 0x8ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1043},
- {"SRIOMAINT1_ASMBLY_ID" , 0x8ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1043},
- {"SRIOMAINT0_ASMBLY_INFO" , 0xcull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1044},
- {"SRIOMAINT1_ASMBLY_INFO" , 0xcull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1044},
- {"SRIOMAINT0_BAR1_IDX000" , 0x200010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX001" , 0x200014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX002" , 0x200018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX003" , 0x20001cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX004" , 0x200020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX005" , 0x200024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX006" , 0x200028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX007" , 0x20002cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX008" , 0x200030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX009" , 0x200034ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX010" , 0x200038ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX011" , 0x20003cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX012" , 0x200040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX013" , 0x200044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX014" , 0x200048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BAR1_IDX015" , 0x20004cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX000" , 0x200010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX001" , 0x200014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX002" , 0x200018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX003" , 0x20001cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX004" , 0x200020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX005" , 0x200024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX006" , 0x200028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX007" , 0x20002cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX008" , 0x200030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX009" , 0x200034ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX010" , 0x200038ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX011" , 0x20003cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX012" , 0x200040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX013" , 0x200044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX014" , 0x200048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT1_BAR1_IDX015" , 0x20004cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1045},
- {"SRIOMAINT0_BELL_STATUS" , 0x200080ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1046},
- {"SRIOMAINT1_BELL_STATUS" , 0x200080ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1046},
- {"SRIOMAINT0_COMP_TAG" , 0x6cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1047},
- {"SRIOMAINT1_COMP_TAG" , 0x6cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1047},
- {"SRIOMAINT0_CORE_ENABLES" , 0x200070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1048},
- {"SRIOMAINT1_CORE_ENABLES" , 0x200070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1048},
- {"SRIOMAINT0_DEV_ID" , 0x0ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1049},
- {"SRIOMAINT1_DEV_ID" , 0x0ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1049},
- {"SRIOMAINT0_DEV_REV" , 0x4ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1050},
- {"SRIOMAINT1_DEV_REV" , 0x4ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1050},
- {"SRIOMAINT0_DST_OPS" , 0x1cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1051},
- {"SRIOMAINT1_DST_OPS" , 0x1cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1051},
- {"SRIOMAINT0_ERB_ATTR_CAPT" , 0x2048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1052},
- {"SRIOMAINT1_ERB_ATTR_CAPT" , 0x2048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1052},
- {"SRIOMAINT0_ERB_ERR_DET" , 0x2040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1053},
- {"SRIOMAINT1_ERB_ERR_DET" , 0x2040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1053},
- {"SRIOMAINT0_ERB_ERR_RATE" , 0x2068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1054},
- {"SRIOMAINT1_ERB_ERR_RATE" , 0x2068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1054},
- {"SRIOMAINT0_ERB_ERR_RATE_EN" , 0x2044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1055},
- {"SRIOMAINT1_ERB_ERR_RATE_EN" , 0x2044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1055},
- {"SRIOMAINT0_ERB_ERR_RATE_THR" , 0x206cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1056},
- {"SRIOMAINT1_ERB_ERR_RATE_THR" , 0x206cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1056},
- {"SRIOMAINT0_ERB_HDR" , 0x2000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1057},
- {"SRIOMAINT1_ERB_HDR" , 0x2000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1057},
- {"SRIOMAINT0_ERB_LT_ADDR_CAPT_H", 0x2010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1058},
- {"SRIOMAINT1_ERB_LT_ADDR_CAPT_H", 0x2010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1058},
- {"SRIOMAINT0_ERB_LT_ADDR_CAPT_L", 0x2014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1059},
- {"SRIOMAINT1_ERB_LT_ADDR_CAPT_L", 0x2014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1059},
- {"SRIOMAINT0_ERB_LT_CTRL_CAPT" , 0x201cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1060},
- {"SRIOMAINT1_ERB_LT_CTRL_CAPT" , 0x201cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1060},
- {"SRIOMAINT0_ERB_LT_DEV_ID" , 0x2028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1061},
- {"SRIOMAINT1_ERB_LT_DEV_ID" , 0x2028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1061},
- {"SRIOMAINT0_ERB_LT_DEV_ID_CAPT", 0x2018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1062},
- {"SRIOMAINT1_ERB_LT_DEV_ID_CAPT", 0x2018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1062},
- {"SRIOMAINT0_ERB_LT_ERR_DET" , 0x2008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1063},
- {"SRIOMAINT1_ERB_LT_ERR_DET" , 0x2008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1063},
- {"SRIOMAINT0_ERB_LT_ERR_EN" , 0x200cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1064},
- {"SRIOMAINT1_ERB_LT_ERR_EN" , 0x200cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1064},
- {"SRIOMAINT0_ERB_PACK_CAPT_1" , 0x2050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1065},
- {"SRIOMAINT1_ERB_PACK_CAPT_1" , 0x2050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1065},
- {"SRIOMAINT0_ERB_PACK_CAPT_2" , 0x2054ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1066},
- {"SRIOMAINT1_ERB_PACK_CAPT_2" , 0x2054ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1066},
- {"SRIOMAINT0_ERB_PACK_CAPT_3" , 0x2058ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1067},
- {"SRIOMAINT1_ERB_PACK_CAPT_3" , 0x2058ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1067},
- {"SRIOMAINT0_ERB_PACK_SYM_CAPT", 0x204cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1068},
- {"SRIOMAINT1_ERB_PACK_SYM_CAPT", 0x204cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1068},
- {"SRIOMAINT0_HB_DEV_ID_LOCK" , 0x68ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1069},
- {"SRIOMAINT1_HB_DEV_ID_LOCK" , 0x68ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1069},
- {"SRIOMAINT0_IR_BUFFER_CONFIG" , 0x102000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1070},
- {"SRIOMAINT1_IR_BUFFER_CONFIG" , 0x102000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1070},
- {"SRIOMAINT0_IR_BUFFER_CONFIG2", 0x102004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1071},
- {"SRIOMAINT1_IR_BUFFER_CONFIG2", 0x102004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1071},
- {"SRIOMAINT0_IR_PD_PHY_CTRL" , 0x107028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1072},
- {"SRIOMAINT1_IR_PD_PHY_CTRL" , 0x107028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1072},
- {"SRIOMAINT0_IR_PD_PHY_STAT" , 0x10702cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1073},
- {"SRIOMAINT1_IR_PD_PHY_STAT" , 0x10702cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1073},
- {"SRIOMAINT0_IR_PI_PHY_CTRL" , 0x107020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1074},
- {"SRIOMAINT1_IR_PI_PHY_CTRL" , 0x107020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1074},
- {"SRIOMAINT0_IR_PI_PHY_STAT" , 0x107024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1075},
- {"SRIOMAINT1_IR_PI_PHY_STAT" , 0x107024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1075},
- {"SRIOMAINT0_IR_SP_RX_CTRL" , 0x10700cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1076},
- {"SRIOMAINT1_IR_SP_RX_CTRL" , 0x10700cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1076},
- {"SRIOMAINT0_IR_SP_RX_DATA" , 0x107014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1077},
- {"SRIOMAINT1_IR_SP_RX_DATA" , 0x107014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1077},
- {"SRIOMAINT0_IR_SP_RX_STAT" , 0x107010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1078},
- {"SRIOMAINT1_IR_SP_RX_STAT" , 0x107010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1078},
- {"SRIOMAINT0_IR_SP_TX_CTRL" , 0x107000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1079},
- {"SRIOMAINT1_IR_SP_TX_CTRL" , 0x107000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1079},
- {"SRIOMAINT0_IR_SP_TX_DATA" , 0x107008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1080},
- {"SRIOMAINT1_IR_SP_TX_DATA" , 0x107008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1080},
- {"SRIOMAINT0_IR_SP_TX_STAT" , 0x107004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1081},
- {"SRIOMAINT1_IR_SP_TX_STAT" , 0x107004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1081},
- {"SRIOMAINT0_LANE_000_STATUS_0", 0x1010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1082},
- {"SRIOMAINT0_LANE_001_STATUS_0", 0x1030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1082},
- {"SRIOMAINT0_LANE_002_STATUS_0", 0x1050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1082},
- {"SRIOMAINT0_LANE_003_STATUS_0", 0x1070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1082},
- {"SRIOMAINT1_LANE_000_STATUS_0", 0x1010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1082},
- {"SRIOMAINT1_LANE_001_STATUS_0", 0x1030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1082},
- {"SRIOMAINT1_LANE_002_STATUS_0", 0x1050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1082},
- {"SRIOMAINT1_LANE_003_STATUS_0", 0x1070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1082},
- {"SRIOMAINT0_LCS_BA0" , 0x58ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1083},
- {"SRIOMAINT1_LCS_BA0" , 0x58ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1083},
- {"SRIOMAINT0_LCS_BA1" , 0x5cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1084},
- {"SRIOMAINT1_LCS_BA1" , 0x5cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1084},
- {"SRIOMAINT0_M2S_BAR0_START0" , 0x200000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1085},
- {"SRIOMAINT1_M2S_BAR0_START0" , 0x200000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1085},
- {"SRIOMAINT0_M2S_BAR0_START1" , 0x200004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1086},
- {"SRIOMAINT1_M2S_BAR0_START1" , 0x200004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1086},
- {"SRIOMAINT0_M2S_BAR1_START0" , 0x200008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1087},
- {"SRIOMAINT1_M2S_BAR1_START0" , 0x200008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1087},
- {"SRIOMAINT0_M2S_BAR1_START1" , 0x20000cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1088},
- {"SRIOMAINT1_M2S_BAR1_START1" , 0x20000cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1088},
- {"SRIOMAINT0_M2S_BAR2_START" , 0x200050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1089},
- {"SRIOMAINT1_M2S_BAR2_START" , 0x200050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1089},
- {"SRIOMAINT0_MAC_CTRL" , 0x200068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1090},
- {"SRIOMAINT1_MAC_CTRL" , 0x200068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1090},
- {"SRIOMAINT0_PE_FEAT" , 0x10ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1091},
- {"SRIOMAINT1_PE_FEAT" , 0x10ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1091},
- {"SRIOMAINT0_PE_LLC" , 0x4cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1092},
- {"SRIOMAINT1_PE_LLC" , 0x4cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1092},
- {"SRIOMAINT0_PORT_0_CTL" , 0x15cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1093},
- {"SRIOMAINT1_PORT_0_CTL" , 0x15cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1093},
- {"SRIOMAINT0_PORT_0_CTL2" , 0x154ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1094},
- {"SRIOMAINT1_PORT_0_CTL2" , 0x154ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1094},
- {"SRIOMAINT0_PORT_0_ERR_STAT" , 0x158ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1095},
- {"SRIOMAINT1_PORT_0_ERR_STAT" , 0x158ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1095},
- {"SRIOMAINT0_PORT_0_LINK_REQ" , 0x140ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1096},
- {"SRIOMAINT1_PORT_0_LINK_REQ" , 0x140ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1096},
- {"SRIOMAINT0_PORT_0_LINK_RESP" , 0x144ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1097},
- {"SRIOMAINT1_PORT_0_LINK_RESP" , 0x144ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1097},
- {"SRIOMAINT0_PORT_0_LOCAL_ACKID", 0x148ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1098},
- {"SRIOMAINT1_PORT_0_LOCAL_ACKID", 0x148ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1098},
- {"SRIOMAINT0_PORT_GEN_CTL" , 0x13cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1099},
- {"SRIOMAINT1_PORT_GEN_CTL" , 0x13cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1099},
- {"SRIOMAINT0_PORT_LT_CTL" , 0x120ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1100},
- {"SRIOMAINT1_PORT_LT_CTL" , 0x120ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1100},
- {"SRIOMAINT0_PORT_MBH0" , 0x100ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1101},
- {"SRIOMAINT1_PORT_MBH0" , 0x100ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1101},
- {"SRIOMAINT0_PORT_RT_CTL" , 0x124ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1102},
- {"SRIOMAINT1_PORT_RT_CTL" , 0x124ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1102},
- {"SRIOMAINT0_PORT_TTL_CTL" , 0x12cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1103},
- {"SRIOMAINT1_PORT_TTL_CTL" , 0x12cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1103},
- {"SRIOMAINT0_PRI_DEV_ID" , 0x60ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT1_PRI_DEV_ID" , 0x60ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_SEC_DEV_CTRL" , 0x200064ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1105},
- {"SRIOMAINT1_SEC_DEV_CTRL" , 0x200064ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1105},
- {"SRIOMAINT0_SEC_DEV_ID" , 0x200060ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1106},
- {"SRIOMAINT1_SEC_DEV_ID" , 0x200060ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1106},
- {"SRIOMAINT0_SERIAL_LANE_HDR" , 0x1000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1107},
- {"SRIOMAINT1_SERIAL_LANE_HDR" , 0x1000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1107},
- {"SRIOMAINT0_SRC_OPS" , 0x18ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1108},
- {"SRIOMAINT1_SRC_OPS" , 0x18ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1108},
- {"SRIOMAINT0_TX_DROP" , 0x20006cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1109},
- {"SRIOMAINT1_TX_DROP" , 0x20006cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1109},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1110},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1111},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1112},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1113},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1114},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1115},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1116},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1117},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1118},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1119},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1120},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1121},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1122},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1123},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1124},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1125},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1126},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1127},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1128},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1129},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1130},
- {"TRA0_READ_DAT_HI" , 0x11800a8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1131},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1132},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1133},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1134},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1135},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1136},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1137},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1138},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1139},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1140},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1141},
- {"UAHC0_EHCI_ASYNCLISTADDR" , 0x16f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 1142},
- {"UAHC0_EHCI_CONFIGFLAG" , 0x16f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 1143},
- {"UAHC0_EHCI_CTRLDSSEGMENT" , 0x16f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 1144},
- {"UAHC0_EHCI_FRINDEX" , 0x16f000000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 1145},
- {"UAHC0_EHCI_HCCAPBASE" , 0x16f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 1146},
- {"UAHC0_EHCI_HCCPARAMS" , 0x16f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 1147},
- {"UAHC0_EHCI_HCSPARAMS" , 0x16f0000000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 1148},
- {"UAHC0_EHCI_INSNREG00" , 0x16f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 32, 1149},
- {"UAHC0_EHCI_INSNREG03" , 0x16f000000009cull, CVMX_CSR_DB_TYPE_NCB, 32, 1150},
- {"UAHC0_EHCI_INSNREG04" , 0x16f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 1151},
- {"UAHC0_EHCI_INSNREG06" , 0x16f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 1152},
- {"UAHC0_EHCI_INSNREG07" , 0x16f00000000ecull, CVMX_CSR_DB_TYPE_NCB, 32, 1153},
- {"UAHC0_EHCI_PERIODICLISTBASE" , 0x16f0000000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 1154},
- {"UAHC0_EHCI_PORTSC001" , 0x16f0000000054ull, CVMX_CSR_DB_TYPE_NCB, 32, 1155},
- {"UAHC0_EHCI_PORTSC002" , 0x16f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 32, 1155},
- {"UAHC0_EHCI_USBCMD" , 0x16f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 1156},
- {"UAHC0_EHCI_USBINTR" , 0x16f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 1157},
- {"UAHC0_EHCI_USBSTS" , 0x16f0000000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 1158},
- {"UAHC0_OHCI0_HCBULKCURRENTED" , 0x16f000000042cull, CVMX_CSR_DB_TYPE_NCB, 32, 1159},
- {"UAHC0_OHCI0_HCBULKHEADED" , 0x16f0000000428ull, CVMX_CSR_DB_TYPE_NCB, 32, 1160},
- {"UAHC0_OHCI0_HCCOMMANDSTATUS" , 0x16f0000000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 1161},
- {"UAHC0_OHCI0_HCCONTROL" , 0x16f0000000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 1162},
- {"UAHC0_OHCI0_HCCONTROLCURRENTED", 0x16f0000000424ull, CVMX_CSR_DB_TYPE_NCB, 32, 1163},
- {"UAHC0_OHCI0_HCCONTROLHEADED" , 0x16f0000000420ull, CVMX_CSR_DB_TYPE_NCB, 32, 1164},
- {"UAHC0_OHCI0_HCDONEHEAD" , 0x16f0000000430ull, CVMX_CSR_DB_TYPE_NCB, 32, 1165},
- {"UAHC0_OHCI0_HCFMINTERVAL" , 0x16f0000000434ull, CVMX_CSR_DB_TYPE_NCB, 32, 1166},
- {"UAHC0_OHCI0_HCFMNUMBER" , 0x16f000000043cull, CVMX_CSR_DB_TYPE_NCB, 32, 1167},
- {"UAHC0_OHCI0_HCFMREMAINING" , 0x16f0000000438ull, CVMX_CSR_DB_TYPE_NCB, 32, 1168},
- {"UAHC0_OHCI0_HCHCCA" , 0x16f0000000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 1169},
- {"UAHC0_OHCI0_HCINTERRUPTDISABLE", 0x16f0000000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 1170},
- {"UAHC0_OHCI0_HCINTERRUPTENABLE", 0x16f0000000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 1171},
- {"UAHC0_OHCI0_HCINTERRUPTSTATUS", 0x16f000000040cull, CVMX_CSR_DB_TYPE_NCB, 32, 1172},
- {"UAHC0_OHCI0_HCLSTHRESHOLD" , 0x16f0000000444ull, CVMX_CSR_DB_TYPE_NCB, 32, 1173},
- {"UAHC0_OHCI0_HCPERIODCURRENTED", 0x16f000000041cull, CVMX_CSR_DB_TYPE_NCB, 32, 1174},
- {"UAHC0_OHCI0_HCPERIODICSTART" , 0x16f0000000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 1175},
- {"UAHC0_OHCI0_HCREVISION" , 0x16f0000000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 1176},
- {"UAHC0_OHCI0_HCRHDESCRIPTORA" , 0x16f0000000448ull, CVMX_CSR_DB_TYPE_NCB, 32, 1177},
- {"UAHC0_OHCI0_HCRHDESCRIPTORB" , 0x16f000000044cull, CVMX_CSR_DB_TYPE_NCB, 32, 1178},
- {"UAHC0_OHCI0_HCRHPORTSTATUS001", 0x16f0000000454ull, CVMX_CSR_DB_TYPE_NCB, 32, 1179},
- {"UAHC0_OHCI0_HCRHPORTSTATUS002", 0x16f0000000458ull, CVMX_CSR_DB_TYPE_NCB, 32, 1179},
- {"UAHC0_OHCI0_HCRHSTATUS" , 0x16f0000000450ull, CVMX_CSR_DB_TYPE_NCB, 32, 1180},
- {"UAHC0_OHCI0_INSNREG06" , 0x16f0000000498ull, CVMX_CSR_DB_TYPE_NCB, 32, 1181},
- {"UAHC0_OHCI0_INSNREG07" , 0x16f000000049cull, CVMX_CSR_DB_TYPE_NCB, 32, 1182},
- {"UCTL0_BIST_STATUS" , 0x118006f0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1183},
- {"UCTL0_CLK_RST_CTL" , 0x118006f000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1184},
- {"UCTL0_EHCI_CTL" , 0x118006f000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1185},
- {"UCTL0_EHCI_FLA" , 0x118006f0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1186},
- {"UCTL0_ERTO_CTL" , 0x118006f000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1187},
- {"UCTL0_IF_ENA" , 0x118006f000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1188},
- {"UCTL0_INT_ENA" , 0x118006f000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1189},
- {"UCTL0_INT_REG" , 0x118006f000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1190},
- {"UCTL0_OHCI_CTL" , 0x118006f000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1191},
- {"UCTL0_ORTO_CTL" , 0x118006f000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1192},
- {"UCTL0_PPAF_WM" , 0x118006f000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1193},
- {"UCTL0_UPHY_CTL_STATUS" , 0x118006f000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1194},
- {"UCTL0_UPHY_PORT000_CTL_STATUS", 0x118006f000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1195},
- {"UCTL0_UPHY_PORT001_CTL_STATUS", 0x118006f000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1195},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1196},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1197},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1198},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1199},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1200},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1201},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1202},
- {"ZIP_THROTTLE" , 0x1180038000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1203},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn63xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_21" , 4, 18, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_24_25" , 24, 2, 0, "RAZ", 1, 1, 0, 0},
- {"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRFLW1" , 35, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP1" , 36, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH1" , 37, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 0, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"RX_EN" , 4, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"TX_EN" , 5, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"BURST" , 6, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 2, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 2, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 2, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 2, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 3, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 4, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 9, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 10, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 10, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 10, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 10, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 11, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 12, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 13, "RO", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 7, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"NULL_DIS" , 10, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 13, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 13, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 14, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 14, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 15, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 15, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 16, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 16, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 17, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 18, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 19, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 19, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 20, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 20, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 21, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 21, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 21, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 22, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 22, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 23, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 23, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 27, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 27, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 32, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 32, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 33, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 33, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 34, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 35, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 35, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 36, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 36, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 37, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 37, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 38, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 38, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 39, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 39, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 40, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 41, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 60, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 2, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 61, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 64, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 64, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 64, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 64, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 64, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 64, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 65, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 65, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 65, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 65, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 65, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 65, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 68, "RAZ", 1, 1, 0, 0},
- {"BP" , 4, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 68, "RAZ", 1, 1, 0, 0},
- {"EN" , 8, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 68, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 1, 71, "R/W", 0, 1, 1ull, 0},
- {"CLKRST" , 1, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"ENABLE" , 2, 1, 71, "R/W", 0, 0, 1ull, 1ull},
- {"COMP" , 3, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"DLLRST" , 4, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_SET" , 8, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_14" , 13, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_BYP" , 15, 1, 71, "R/W", 0, 1, 1ull, 0},
- {"CLKRX_SET" , 16, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_22" , 21, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKRX_BYP" , 23, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"CLK_SET" , 24, 5, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_NCTL" , 32, 6, 71, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_38_39" , 38, 2, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_PCTL" , 40, 6, 71, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_46_47" , 46, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_NCTL" , 48, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_54_55" , 54, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_PCTL" , 56, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_BYP" , 63, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"BIST" , 0, 5, 72, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 72, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 73, "RAZ", 1, 1, 0, 0},
- {"SLI" , 3, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 73, "RAZ", 1, 1, 0, 0},
- {"IPD" , 9, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 14, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 73, "RAZ", 1, 1, 0, 0},
- {"L2C" , 16, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 17, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 73, "RAZ", 1, 1, 0, 0},
- {"PIP" , 20, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 73, "RAZ", 1, 1, 0, 0},
- {"ASXPCS0" , 22, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_24" , 23, 2, 73, "RAZ", 1, 1, 0, 0},
- {"PEM0" , 25, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 26, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 73, "RAZ", 1, 1, 0, 0},
- {"AGL" , 28, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_29" , 29, 1, 73, "RAZ", 1, 1, 0, 0},
- {"IOB" , 30, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 73, "RAZ", 1, 1, 0, 0},
- {"SRIO0" , 32, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"SRIO1" , 33, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 73, "RAZ", 1, 1, 0, 0},
- {"DFM" , 40, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 41, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 42, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 73, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 6, 74, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 74, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 6, 75, "RO", 1, 1, 0, 0},
- {"RESERVED_6_63" , 6, 58, 75, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 76, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 77, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 77, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 77, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 77, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 77, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 77, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 77, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 77, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 78, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 78, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 78, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 78, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 79, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 79, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 79, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 79, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 79, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 80, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 80, "R/W", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 80, "R/W", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 80, "R/W", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 80, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 81, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 82, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 82, "R/W1", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 83, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 83, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 83, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 83, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 83, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 83, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 83, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 83, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 83, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 83, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 83, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 84, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 84, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 84, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 84, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 85, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 85, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 85, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 85, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 85, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 86, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 86, "R/W", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 86, "R/W", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 86, "R/W", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 86, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 87, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 6, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 88, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 88, "R/W1", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 89, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 89, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 89, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 89, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 89, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 89, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 89, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 89, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 89, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 89, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 90, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 90, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 90, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 90, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 90, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 90, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 90, "RAZ", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 90, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 90, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 90, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 91, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 91, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 91, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 91, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 91, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 91, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 91, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 91, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 91, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_58" , 57, 2, 91, "RAZ", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 91, "RO", 0, 0, 0ull, 0ull},
- {"PP" , 0, 3, 92, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_7" , 3, 5, 92, "RAZ", 1, 1, 0, 0},
- {"IRQ" , 8, 2, 92, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 92, "RAZ", 1, 1, 0, 0},
- {"SEL" , 16, 3, 92, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_19_63" , 19, 45, 92, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 6, 93, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_17" , 6, 12, 93, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_45" , 37, 9, 93, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"SRIO1" , 51, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 93, "RAZ", 1, 1, 0, 0},
- {"DFM" , 56, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_62" , 57, 6, 93, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 93, "RO", 0, 0, 0ull, 0ull},
- {"BITS" , 0, 32, 94, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 94, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 95, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 95, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 6, 96, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 96, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 97, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 6, 98, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 98, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 99, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 100, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 5, 100, "R/W", 0, 0, 31ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 100, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 101, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 101, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 101, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 101, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 101, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 101, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 101, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 101, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 102, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 102, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 102, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 102, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 102, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 102, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 102, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 102, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 102, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 102, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 102, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 102, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 102, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 103, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 103, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 103, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 103, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 103, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 103, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 103, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 103, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 3, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 104, "RAZ", 1, 1, 0, 0},
- {"MUX_SEL" , 4, 2, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 104, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 104, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 105, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 105, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_39" , 37, 3, 105, "RAZ", 1, 1, 0, 0},
- {"SELECT" , 40, 3, 105, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_60" , 43, 18, 105, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 105, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 105, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 105, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 106, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 106, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 107, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 107, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 108, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 108, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 109, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 109, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 110, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 110, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 111, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 111, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 111, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 111, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 111, "RAZ", 1, 1, 0, 0},
- {"PDB" , 0, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 112, "RAZ", 0, 0, 0ull, 0ull},
- {"RDF" , 4, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 112, "RAZ", 0, 0, 0ull, 0ull},
- {"DTX" , 8, 2, 112, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 112, "RAZ", 0, 0, 0ull, 0ull},
- {"STX" , 16, 2, 112, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_23" , 18, 6, 112, "RAZ", 0, 0, 0ull, 0ull},
- {"GFB" , 24, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 112, "RAZ", 0, 0, 0ull, 0ull},
- {"MWB" , 28, 1, 112, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 112, "RAZ", 0, 0, 0ull, 0ull},
- {"GFU" , 0, 1, 113, "RO", 0, 0, 0ull, 0ull},
- {"GIB" , 1, 1, 113, "RO", 0, 0, 0ull, 0ull},
- {"GIF" , 2, 1, 113, "RO", 0, 0, 0ull, 0ull},
- {"NCD" , 3, 1, 113, "RO", 0, 0, 0ull, 0ull},
- {"GUTP" , 4, 1, 113, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 113, "RAZ", 0, 0, 0ull, 0ull},
- {"GUTV" , 8, 1, 113, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 9, 1, 113, "RO", 0, 0, 0ull, 0ull},
- {"RAM1" , 10, 1, 113, "RO", 0, 0, 0ull, 0ull},
- {"RAM2" , 11, 1, 113, "RO", 0, 0, 0ull, 0ull},
- {"RAM3" , 12, 1, 113, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 113, "RAZ", 0, 0, 0ull, 0ull},
- {"DTECLKDIS" , 0, 1, 114, "R/W", 0, 0, 1ull, 0ull},
- {"CLDTECRIP" , 1, 3, 114, "R/W", 0, 0, 0ull, 0ull},
- {"CLMSKCRIP" , 4, 4, 114, "R/W", 0, 0, 0ull, 0ull},
- {"REPL_ENA" , 8, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 114, "RAZ", 1, 1, 0, 0},
- {"IMODE" , 0, 1, 115, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 1, 1, 115, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 2, 1, 115, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_4" , 3, 2, 115, "RAZ", 1, 1, 0, 0},
- {"SBDLCK" , 5, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"SBDNUM" , 6, 4, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 115, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 20, 116, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 116, "RAZ", 1, 1, 0, 0},
- {"SBD0" , 0, 64, 117, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 118, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 119, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 120, "RO", 1, 1, 0, 0},
- {"SIZE" , 0, 9, 121, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 121, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 121, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_20_63" , 20, 44, 121, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 122, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 35, 122, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 122, "RAZ", 1, 1, 0, 0},
- {"RAM1FADR" , 0, 14, 123, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 123, "RAZ", 1, 1, 0, 0},
- {"RAM2FADR" , 16, 9, 123, "RO", 1, 1, 0, 0},
- {"RESERVED_25_31" , 25, 7, 123, "RAZ", 1, 1, 0, 0},
- {"RAM3FADR" , 32, 12, 123, "RO", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 123, "RAZ", 1, 1, 0, 0},
- {"DBLOVF" , 0, 1, 124, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC0PERR" , 1, 3, 124, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 124, "RAZ", 1, 1, 0, 0},
- {"CNDRD" , 16, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 124, "RAZ", 1, 1, 0, 0},
- {"DBLINA" , 0, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"DC0PENA" , 1, 3, 125, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 125, "RAZ", 1, 1, 0, 0},
- {"HIDAT" , 0, 64, 126, "R/W", 1, 1, 0, 0},
- {"PFCNT0" , 0, 64, 127, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 128, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 128, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 128, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 128, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 128, "RAZ", 1, 1, 0, 0},
- {"PFCNT1" , 0, 64, 129, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 130, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 130, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 130, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 130, "RAZ", 1, 1, 0, 0},
- {"PFCNT2" , 0, 64, 131, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 132, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 132, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 132, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 132, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 132, "RAZ", 1, 1, 0, 0},
- {"PFCNT3" , 0, 64, 133, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 134, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 134, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 134, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 134, "RAZ", 1, 1, 0, 0},
- {"CNT0ENA" , 0, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 1, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 2, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 3, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0WCLR" , 4, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1WCLR" , 5, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2WCLR" , 6, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3WCLR" , 7, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RCLR" , 8, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RCLR" , 9, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RCLR" , 10, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RCLR" , 11, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"SNODE" , 12, 3, 135, "R/W", 0, 0, 0ull, 0ull},
- {"ENODE" , 15, 3, 135, "R/W", 0, 0, 0ull, 0ull},
- {"EDNODE" , 18, 2, 135, "R/W", 0, 0, 0ull, 0ull},
- {"PMODE" , 20, 1, 135, "R/W", 0, 0, 0ull, 0ull},
- {"VGID" , 21, 8, 135, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 135, "RAZ", 1, 1, 0, 0},
- {"PRBS" , 0, 32, 136, "R/W", 1, 1, 0, 0},
- {"PROG" , 32, 8, 136, "R/W", 1, 1, 0, 0},
- {"SEL" , 40, 1, 136, "R/W", 1, 1, 0, 0},
- {"EN" , 41, 1, 136, "R/W", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 136, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 16, 137, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 137, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 16, 138, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 138, "R/W", 1, 1, 0, 0},
- {"CKE_MASK" , 0, 2, 139, "R/W", 1, 1, 0, 0},
- {"CS0_N_MASK" , 2, 2, 139, "R/W", 1, 1, 0, 0},
- {"CS1_N_MASK" , 4, 2, 139, "R/W", 1, 1, 0, 0},
- {"ODT0_MASK" , 6, 2, 139, "R/W", 1, 1, 0, 0},
- {"ODT1_MASK" , 8, 2, 139, "R/W", 1, 1, 0, 0},
- {"RAS_N_MASK" , 10, 1, 139, "R/W", 1, 1, 0, 0},
- {"CAS_N_MASK" , 11, 1, 139, "R/W", 1, 1, 0, 0},
- {"WE_N_MASK" , 12, 1, 139, "R/W", 1, 1, 0, 0},
- {"BA_MASK" , 13, 3, 139, "R/W", 1, 1, 0, 0},
- {"A_MASK" , 16, 16, 139, "R/W", 1, 1, 0, 0},
- {"RESET_N_MASK" , 32, 1, 139, "R/W", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 139, "R/W", 1, 1, 0, 0},
- {"DQX_CTL" , 0, 4, 140, "R/W", 0, 1, 4ull, 0},
- {"CK_CTL" , 4, 4, 140, "R/W", 0, 1, 4ull, 0},
- {"CMD_CTL" , 8, 4, 140, "R/W", 0, 1, 4ull, 0},
- {"RODT_CTL" , 12, 4, 140, "R/W", 0, 1, 0ull, 0},
- {"NTUNE" , 16, 4, 140, "R/W", 0, 1, 0ull, 0},
- {"PTUNE" , 20, 4, 140, "R/W", 0, 1, 0ull, 0},
- {"BYP" , 24, 1, 140, "R/W", 0, 1, 0ull, 0},
- {"M180" , 25, 1, 140, "R/W", 0, 1, 0ull, 0},
- {"DDR__NTUNE" , 26, 4, 140, "RO", 1, 1, 0, 0},
- {"DDR__PTUNE" , 30, 4, 140, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 140, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 141, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"ROW_LSB" , 2, 3, 141, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 141, "R/W", 0, 1, 5ull, 0},
- {"IDLEPOWER" , 9, 3, 141, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 12, 4, 141, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 16, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 141, "R/W", 0, 1, 0ull, 0},
- {"REF_ZQCS_INT" , 18, 19, 141, "R/W", 1, 1, 0, 0},
- {"SEQUENCE" , 37, 3, 141, "R/W", 0, 0, 0ull, 0ull},
- {"EARLY_DQX" , 40, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"SREF_WITH_DLL" , 41, 1, 141, "R/W", 0, 0, 0ull, 0ull},
- {"RANK_ENA" , 42, 1, 141, "R/W", 0, 1, 0ull, 0},
- {"RANKMASK" , 43, 4, 141, "R/W", 0, 1, 0ull, 0},
- {"MIRRMASK" , 47, 4, 141, "R/W", 0, 1, 0ull, 0},
- {"INIT_STATUS" , 51, 4, 141, "R/W1", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R0" , 55, 1, 141, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R1" , 56, 1, 141, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R0" , 57, 1, 141, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R1" , 58, 1, 141, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_59_63" , 59, 5, 141, "RAZ", 1, 1, 0, 0},
- {"RDIMM_ENA" , 0, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"BWCNT" , 1, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 2, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 3, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH2" , 4, 2, 142, "R/W", 0, 0, 0ull, 1ull},
- {"THROTTLE_RD" , 6, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"THROTTLE_WR" , 7, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_RD" , 8, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_WR" , 9, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"ELEV_PRIO_DIS" , 10, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"NXM_WRITE_EN" , 11, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 12, 4, 142, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 16, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"AUTO_FCLKDIS" , 17, 1, 142, "R/W", 0, 0, 0ull, 1ull},
- {"INT_ZQCS_DIS" , 18, 1, 142, "R/W", 0, 0, 1ull, 0ull},
- {"EXT_ZQCS_DIS" , 19, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 20, 2, 142, "R/W", 0, 0, 0ull, 0ull},
- {"WODT_BPRCH" , 22, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_BPRCH" , 23, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 142, "RAZ", 1, 1, 0, 0},
- {"BYP_SETTING" , 0, 8, 143, "R/W", 0, 0, 0ull, 0ull},
- {"BYP_SEL" , 8, 4, 143, "R/W", 0, 0, 0ull, 0ull},
- {"QUAD_DLL_ENA" , 12, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 13, 1, 143, "R/W", 0, 0, 1ull, 0ull},
- {"DLL_BRINGUP" , 14, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 143, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 144, "R/W", 0, 0, 0ull, 0ull},
- {"BYTE_SEL" , 6, 4, 144, "R/W", 0, 0, 0ull, 0ull},
- {"MODE_SEL" , 10, 2, 144, "R/W", 0, 0, 0ull, 0ull},
- {"LOAD_OFFSET" , 12, 1, 144, "WR0", 0, 0, 0ull, 0ull},
- {"OFFSET_ENA" , 13, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYTE_SEL" , 14, 4, 144, "R/W", 0, 0, 1ull, 1ull},
- {"DLL_MODE" , 18, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"FINE_TUNE_MODE" , 19, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_SETTING" , 20, 8, 144, "RO", 1, 1, 0, 0},
- {"DLL_FAST" , 28, 1, 144, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 144, "RAZ", 1, 1, 0, 0},
- {"FCLKCNT" , 0, 64, 145, "RO", 0, 1, 0ull, 0},
- {"MWB" , 0, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"RPB" , 1, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"MFF" , 2, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"MRQ" , 3, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"CAB" , 4, 1, 146, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 146, "RAZ", 1, 1, 0, 0},
- {"DFR_ENA" , 0, 1, 147, "R/W", 0, 0, 0ull, 1ull},
- {"RECC_ENA" , 1, 1, 147, "R/W", 0, 0, 0ull, 1ull},
- {"WECC_ENA" , 2, 1, 147, "R/W", 0, 0, 0ull, 1ull},
- {"SBE_ENA" , 3, 1, 147, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 147, "RAZ", 1, 1, 0, 0},
- {"SBE_INTENA" , 0, 1, 148, "R/W", 0, 0, 0ull, 1ull},
- {"DBE_INTENA" , 1, 1, 148, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 148, "RAZ", 1, 1, 0, 0},
- {"SCLKDIS" , 0, 1, 149, "R/W", 0, 0, 1ull, 0ull},
- {"BIST_START" , 1, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 2, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 149, "RAZ", 1, 1, 0, 0},
- {"SBE_ERR" , 0, 1, 150, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE_ERR" , 1, 1, 150, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 150, "RAZ", 1, 1, 0, 0},
- {"FADR" , 4, 28, 150, "RO", 0, 0, 0ull, 0ull},
- {"FSYN" , 32, 10, 150, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 150, "RAZ", 1, 1, 0, 0},
- {"IFBCNT" , 0, 64, 151, "RO", 0, 1, 1ull, 0},
- {"CWL" , 0, 3, 152, "R/W", 0, 0, 0ull, 0ull},
- {"MPRLOC" , 3, 2, 152, "R/W", 0, 0, 0ull, 0ull},
- {"MPR" , 5, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"DLL" , 6, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"AL" , 7, 2, 152, "R/W", 0, 0, 0ull, 0ull},
- {"WLEV" , 9, 1, 152, "RO", 0, 0, 0ull, 0ull},
- {"TDQS" , 10, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"QOFF" , 11, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"BL" , 12, 2, 152, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 14, 4, 152, "R/W", 0, 0, 2ull, 2ull},
- {"RBT" , 18, 1, 152, "RO", 0, 0, 1ull, 1ull},
- {"TM" , 19, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"DLLR" , 20, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"WRP" , 21, 3, 152, "R/W", 0, 0, 0ull, 0ull},
- {"PPD" , 24, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 152, "RAZ", 1, 1, 0, 0},
- {"PASR_00" , 0, 3, 153, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_00" , 3, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_00" , 4, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_00" , 5, 2, 153, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_00" , 7, 2, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_00" , 9, 3, 153, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_01" , 12, 3, 153, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_01" , 15, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_01" , 16, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_01" , 17, 2, 153, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_01" , 19, 2, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_01" , 21, 3, 153, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_10" , 24, 3, 153, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_10" , 27, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_10" , 28, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_10" , 29, 2, 153, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_10" , 31, 2, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_10" , 33, 3, 153, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_11" , 36, 3, 153, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_11" , 39, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_11" , 40, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_11" , 41, 2, 153, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_11" , 43, 2, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_11" , 45, 3, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 153, "RAZ", 1, 1, 0, 0},
- {"OPSCNT" , 0, 64, 154, "RO", 0, 1, 1ull, 0},
- {"TS_STAGGER" , 0, 1, 155, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK_POS" , 1, 1, 155, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK" , 2, 1, 155, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT0" , 3, 4, 155, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE0" , 7, 1, 155, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT1" , 8, 4, 155, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE1" , 12, 1, 155, "R/W", 0, 1, 0ull, 0},
- {"LV_MODE" , 13, 1, 155, "R/W", 0, 1, 0ull, 0},
- {"RX_ALWAYS_ON" , 14, 1, 155, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 155, "RAZ", 1, 1, 0, 0},
- {"DDR3RST" , 0, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PWARM" , 1, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSOFT" , 2, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSV" , 3, 1, 156, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 156, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 157, "R/W", 0, 1, 0ull, 0},
- {"OFFSET" , 4, 4, 157, "R/W", 0, 0, 2ull, 2ull},
- {"OFFSET_EN" , 8, 1, 157, "R/W", 0, 0, 1ull, 1ull},
- {"OR_DIS" , 9, 1, 157, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 10, 8, 157, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_0" , 18, 1, 157, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_1" , 19, 1, 157, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_2" , 20, 1, 157, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_3" , 21, 1, 157, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 157, "RAZ", 1, 1, 0, 0},
- {"BITMASK" , 0, 64, 158, "RO", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 6, 159, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 6, 6, 159, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_53" , 12, 42, 159, "R/W", 1, 1, 0, 0},
- {"STATUS" , 54, 2, 159, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 159, "RAZ", 1, 1, 0, 0},
- {"RODT_D0_R0" , 0, 8, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D0_R1" , 8, 8, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D1_R0" , 16, 8, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D1_R1" , 24, 8, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R0" , 32, 8, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R1" , 40, 8, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R0" , 48, 8, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R1" , 56, 8, 160, "R/W", 0, 0, 0ull, 0ull},
- {"R2R_INIT" , 0, 6, 161, "R/W", 0, 1, 1ull, 0},
- {"R2W_INIT" , 6, 6, 161, "R/W", 0, 1, 6ull, 0},
- {"W2R_INIT" , 12, 6, 161, "R/W", 0, 1, 9ull, 0},
- {"W2W_INIT" , 18, 6, 161, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_24_63" , 24, 40, 161, "RAZ", 1, 1, 0, 0},
- {"R2R_XRANK_INIT" , 0, 6, 162, "R/W", 0, 1, 3ull, 0},
- {"R2W_XRANK_INIT" , 6, 6, 162, "R/W", 0, 1, 6ull, 0},
- {"W2R_XRANK_INIT" , 12, 6, 162, "R/W", 0, 1, 4ull, 0},
- {"W2W_XRANK_INIT" , 18, 6, 162, "R/W", 0, 1, 5ull, 0},
- {"RESERVED_24_63" , 24, 40, 162, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_9" , 0, 10, 163, "RAZ", 1, 1, 0, 0},
- {"TZQCS" , 10, 4, 163, "R/W", 0, 0, 4ull, 4ull},
- {"TCKE" , 14, 4, 163, "R/W", 0, 0, 3ull, 3ull},
- {"TXPR" , 18, 4, 163, "R/W", 0, 0, 5ull, 5ull},
- {"TMRD" , 22, 4, 163, "R/W", 0, 0, 4ull, 4ull},
- {"TMOD" , 26, 4, 163, "R/W", 0, 0, 12ull, 12ull},
- {"TDLLK" , 30, 4, 163, "R/W", 0, 0, 2ull, 2ull},
- {"TZQINIT" , 34, 4, 163, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 38, 4, 163, "R/W", 0, 0, 6ull, 6ull},
- {"TCKSRE" , 42, 4, 163, "R/W", 0, 0, 5ull, 5ull},
- {"TRP_EXT" , 46, 1, 163, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 163, "RAZ", 1, 1, 0, 0},
- {"TMPRR" , 0, 4, 164, "R/W", 0, 0, 1ull, 1ull},
- {"TRAS" , 4, 5, 164, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 9, 4, 164, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 13, 4, 164, "R/W", 0, 0, 2ull, 2ull},
- {"TRFC" , 17, 5, 164, "R/W", 0, 0, 6ull, 7ull},
- {"TRRD" , 22, 3, 164, "R/W", 0, 0, 2ull, 2ull},
- {"TXP" , 25, 3, 164, "R/W", 0, 0, 3ull, 3ull},
- {"TWLMRD" , 28, 4, 164, "R/W", 0, 0, 10ull, 10ull},
- {"TWLDQSEN" , 32, 4, 164, "R/W", 0, 0, 7ull, 7ull},
- {"TFAW" , 36, 5, 164, "R/W", 0, 0, 0ull, 9ull},
- {"TXPDLL" , 41, 5, 164, "R/W", 0, 0, 0ull, 10ull},
- {"TRAS_EXT" , 46, 1, 164, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 164, "RAZ", 1, 1, 0, 0},
- {"LANEMASK" , 0, 9, 165, "R/W", 0, 1, 0ull, 0},
- {"SSET" , 9, 1, 165, "R/W", 0, 1, 0ull, 0},
- {"OR_DIS" , 10, 1, 165, "R/W", 0, 1, 0ull, 0},
- {"BITMASK" , 11, 8, 165, "R/W", 0, 1, 0ull, 0},
- {"RTT_NOM" , 19, 3, 165, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 165, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 166, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 4, 8, 166, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 166, "RAZ", 1, 1, 0, 0},
- {"BYTE0" , 0, 5, 167, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 5, 5, 167, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_44" , 10, 35, 167, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 45, 2, 167, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_63" , 47, 17, 167, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 168, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D0_R1" , 8, 8, 168, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R0" , 16, 8, 168, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R1" , 24, 8, 168, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R0" , 32, 8, 168, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R1" , 40, 8, 168, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R0" , 48, 8, 168, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R1" , 56, 8, 168, "R/W", 0, 0, 255ull, 255ull},
- {"BIST" , 0, 45, 169, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_63" , 45, 19, 169, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 170, "R/W", 0, 0, 0ull, 1ull},
- {"CLK" , 1, 1, 170, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 170, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 171, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 171, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 171, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 172, "WO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 172, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 173, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 29, 173, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 173, "RAZ", 1, 1, 0, 0},
- {"IDLE" , 40, 1, 173, "RO", 0, 1, 1ull, 0},
- {"RESERVED_41_47" , 41, 7, 173, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 48, 14, 173, "R/W", 0, 1, 64ull, 0},
- {"RESERVED_62_63" , 62, 2, 173, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 174, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 174, "RAZ", 1, 1, 0, 0},
- {"STATE" , 0, 64, 175, "RO", 0, 1, 0ull, 0},
- {"STATE" , 0, 64, 176, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_13" , 0, 14, 177, "RAZ", 1, 1, 0, 0},
- {"O_MODE" , 14, 1, 177, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 177, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 177, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 177, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 177, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 177, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 177, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 177, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 177, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_47" , 34, 14, 177, "RAZ", 1, 1, 0, 0},
- {"DMA_ENB" , 48, 6, 177, "R/W", 0, 0, 0ull, 63ull},
- {"RESERVED_54_55" , 54, 2, 177, "RAZ", 1, 1, 0, 0},
- {"PKT_EN" , 56, 1, 177, "R/W", 0, 1, 0ull, 0},
- {"PKT_HP" , 57, 1, 177, "RO", 0, 0, 0ull, 0ull},
- {"COMMIT_MODE" , 58, 1, 177, "R/W", 0, 0, 0ull, 1ull},
- {"FFP_DIS" , 59, 1, 177, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_EN1" , 60, 1, 177, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_61_63" , 61, 3, 177, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 178, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 178, "RAZ", 1, 1, 0, 0},
- {"BLKS" , 0, 4, 179, "R/W", 0, 1, 2ull, 0},
- {"BASE" , 4, 4, 179, "RO", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 179, "RAZ", 1, 1, 0, 0},
- {"RSL" , 0, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB" , 1, 1, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 180, "RAZ", 1, 1, 0, 0},
- {"FFP" , 4, 4, 180, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 180, "RAZ", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 181, "R/W", 0, 0, 0ull, 0ull},
- {"DMADBO" , 8, 8, 181, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 181, "R/W", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 181, "R/W", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 182, "RAZ", 1, 1, 0, 0},
- {"DMADBO" , 8, 8, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 182, "RAZ", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 182, "RAZ", 1, 1, 0, 0},
- {"SINFO" , 0, 6, 183, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 183, "RAZ", 1, 1, 0, 0},
- {"IINFO" , 8, 6, 183, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 183, "RAZ", 1, 1, 0, 0},
- {"PKTERR" , 0, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 184, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 185, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 185, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 186, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 186, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 187, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 187, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 188, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 188, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 189, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 189, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 2, 190, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 190, "RAZ", 1, 1, 0, 0},
- {"MRRS_LIM" , 3, 1, 190, "R/W", 0, 0, 0ull, 0ull},
- {"MPS" , 4, 1, 190, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 190, "RAZ", 1, 1, 0, 0},
- {"MPS_LIM" , 7, 1, 190, "R/W", 0, 0, 0ull, 0ull},
- {"MOLR" , 8, 6, 190, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_14_15" , 14, 2, 190, "RAZ", 1, 1, 0, 0},
- {"RD_MODE" , 16, 1, 190, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 190, "RAZ", 1, 1, 0, 0},
- {"QLM_CFG" , 20, 1, 190, "RO", 1, 1, 0, 0},
- {"RESERVED_21_23" , 21, 3, 190, "RAZ", 1, 1, 0, 0},
- {"HALT" , 24, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 190, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 191, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 191, "RO", 0, 1, 0ull, 0},
- {"REQQ" , 0, 3, 192, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 192, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 4, 1, 192, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 192, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 8, 1, 192, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 192, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 193, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 193, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 193, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 193, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 193, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 193, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 194, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 194, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OFF" , 18, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"RET_OFF" , 19, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"FREE_EN" , 20, 1, 194, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 194, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 195, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 195, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 195, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 196, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 196, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 197, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 197, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 197, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 198, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 198, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_63" , 44, 20, 199, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 200, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_63" , 44, 20, 200, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 32, 201, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 201, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 29, 202, "R/W", 0, 0, 536870911ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 202, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 203, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 204, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 204, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 205, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 205, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 205, "RO", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 206, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 206, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 206, "RO", 0, 0, 0ull, 7ull},
- {"THRESH" , 0, 32, 207, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 207, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 208, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 208, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 208, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 208, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 208, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 208, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 208, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 209, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 209, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 210, "RAZ", 1, 1, 0, 0},
- {"LOGL_EN" , 0, 16, 211, "R/W", 0, 1, 65535ull, 0},
- {"PHYS_EN" , 16, 1, 211, "R/W", 0, 1, 1ull, 0},
- {"HG2RX_EN" , 17, 1, 211, "R/W", 0, 0, 0ull, 0ull},
- {"HG2TX_EN" , 18, 1, 211, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 211, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 212, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 212, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 212, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 1, 212, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 212, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 4, 212, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 212, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 213, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 213, "RAZ", 1, 1, 0, 0},
- {"RX_EN" , 0, 1, 214, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EN" , 1, 1, 214, "R/W", 0, 0, 0ull, 0ull},
- {"DRP_EN" , 2, 1, 214, "R/W", 0, 0, 0ull, 0ull},
- {"BCK_EN" , 3, 1, 214, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 214, "RAZ", 1, 1, 0, 0},
- {"PHYS_BP" , 16, 16, 214, "R/W", 0, 1, 65535ull, 0},
- {"LOGL_EN" , 32, 16, 214, "R/W", 0, 0, 255ull, 255ull},
- {"PHYS_EN" , 48, 16, 214, "R/W", 0, 0, 255ull, 255ull},
- {"EN" , 0, 1, 215, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 215, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 215, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 215, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 215, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 215, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 215, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 215, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 215, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 215, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 216, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 217, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 218, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 219, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 220, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 221, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 222, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 222, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 223, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 223, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 223, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 223, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 224, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 224, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 225, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 225, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 225, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 225, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 225, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 225, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 225, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 225, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 225, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 226, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 226, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 226, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 226, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 226, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 226, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 226, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 226, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 226, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 226, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 227, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 227, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 228, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 228, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 228, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 228, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 228, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 229, "R/W1C", 0, 1, 0ull, 0},
- {"CAREXT" , 1, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 229, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 229, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 229, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 229, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 229, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 229, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 230, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 230, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 231, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 231, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 232, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 232, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 233, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 233, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 234, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 234, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 235, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 235, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 236, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 236, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 237, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 237, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 238, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 238, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 239, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 239, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 240, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 240, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 241, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 241, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 242, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 242, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 242, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 242, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 243, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 243, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 244, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 244, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 245, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 245, "RAZ", 1, 1, 0, 0},
- {"LGTIM2GO" , 0, 16, 246, "RO", 0, 1, 0ull, 0},
- {"XOF" , 16, 16, 246, "RO", 0, 0, 0ull, 0ull},
- {"PHTIM2GO" , 32, 16, 246, "RO", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 246, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 4, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 247, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 4, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 247, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 248, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 248, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 249, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 249, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 249, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 249, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 249, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 250, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 250, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 251, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 251, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 0, 1, 252, "R/W", 0, 1, 0ull, 0},
- {"START_BIST" , 1, 1, 252, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 252, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 253, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 253, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 254, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 254, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 254, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 254, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 254, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 255, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 255, "RAZ", 1, 1, 0, 0},
- {"XOFF" , 0, 16, 256, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 256, "RAZ", 1, 1, 0, 0},
- {"XON" , 0, 16, 257, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 257, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 258, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 258, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 258, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 259, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 259, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 260, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 260, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 261, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 261, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 262, "RO", 1, 1, 0, 0},
- {"MSG_TIME" , 16, 16, 262, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 262, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 263, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 263, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 264, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 264, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 265, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 265, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 266, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 266, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 267, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 267, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 268, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 268, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 269, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 269, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 270, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 271, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 271, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 272, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 272, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 273, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 273, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 274, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 274, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 275, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 275, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 276, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 276, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 277, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 278, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 278, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 279, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 279, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 280, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 280, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 281, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 281, "RAZ", 1, 1, 0, 0},
- {"TX_XOF" , 0, 16, 282, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 282, "RAZ", 1, 1, 0, 0},
- {"TX_XON" , 0, 16, 283, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 283, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 284, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 284, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 284, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 285, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 285, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 285, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 285, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 285, "R/W", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 285, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 285, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 286, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 286, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 286, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 287, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 287, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 288, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 288, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 289, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 289, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 289, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 289, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 289, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 289, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 290, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 290, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 291, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 291, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 292, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_5_63" , 5, 59, 292, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 293, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 293, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 293, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 293, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 293, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 293, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 294, "R/W", 0, 0, 6ull, 6ull},
- {"EN" , 4, 1, 294, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 294, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 295, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 295, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 295, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 295, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 295, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 295, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 295, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 295, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCE_SEL" , 15, 2, 295, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 295, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 296, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 296, "RAZ", 1, 1, 0, 0},
- {"LANE_SEL" , 0, 2, 297, "R/W", 0, 0, 0ull, 0ull},
- {"DIV" , 2, 1, 297, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 297, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 298, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 298, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 299, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 299, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 300, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 300, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 301, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 301, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IOCFIF" , 18, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RSDFIF" , 19, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"IORFIF" , 20, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"XMCFIF" , 21, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"XMDFIF" , 22, 1, 302, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 302, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 303, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"RR_MODE" , 5, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"XMC_PER" , 6, 4, 303, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 303, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 304, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 304, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 305, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 305, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 305, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 306, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 306, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 306, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 307, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 307, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 307, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 307, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 307, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 308, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 308, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 308, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 308, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 308, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 309, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 310, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 311, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 311, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 311, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 311, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 311, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 311, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 311, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 312, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 312, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 312, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 312, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 312, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 312, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 312, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 313, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 313, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 313, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 314, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 315, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 315, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 315, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 316, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 316, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 316, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 316, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 316, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 317, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 317, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 317, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 317, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 317, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 318, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 319, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 320, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 320, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 320, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 321, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 321, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 321, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 322, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 322, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 322, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 323, "RO", 0, 1, 0ull, 0},
- {"VPORT" , 6, 6, 323, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 323, "RAZ", 1, 1, 0, 0},
- {"NCB_WR" , 0, 3, 324, "R/W", 0, 1, 0ull, 0},
- {"NCB_RD" , 3, 3, 324, "R/W", 0, 1, 0ull, 0},
- {"PKO_RD" , 6, 3, 324, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 324, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 325, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 325, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 326, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 326, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 327, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 327, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 328, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 328, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 44, 329, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_63" , 44, 20, 329, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 330, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 331, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"CLKEN" , 15, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"RST_DONE" , 16, 1, 331, "RO", 0, 0, 1ull, 0ull},
- {"USE_SOP" , 17, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 331, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 332, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 332, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 333, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 334, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 334, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 335, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 335, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 336, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 336, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 337, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 337, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 337, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 338, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 338, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 338, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 339, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 339, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 339, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 340, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 340, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 341, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 341, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 342, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 342, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 343, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 343, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 344, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 345, "R/W", 0, 0, 0ull, 1ull},
- {"RADDR" , 0, 3, 346, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 346, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 346, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 346, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 346, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 346, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 347, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 347, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 347, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 347, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_44_63" , 44, 20, 347, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 348, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 348, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 348, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 348, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 348, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 348, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 349, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 349, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 349, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 349, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 349, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 349, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_61_63" , 61, 3, 349, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 350, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 350, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 351, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 351, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 352, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 352, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 352, "R/W", 0, 0, 0ull, 0ull},
- {"PRT_ENB" , 0, 8, 353, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 353, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 354, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 354, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 354, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 354, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 354, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 355, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 355, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 355, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 356, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_35" , 32, 4, 356, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT2" , 36, 4, 356, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_40_63" , 40, 24, 356, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 357, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 357, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 357, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 358, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 358, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 359, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 359, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 360, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 360, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 361, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 361, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 361, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 362, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 362, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 363, "RAZ", 1, 1, 0, 0},
- {"DISABLE" , 0, 1, 364, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 364, "RAZ", 1, 1, 0, 0},
- {"MAXDRAM" , 4, 4, 364, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_8_63" , 8, 56, 364, "RAZ", 1, 1, 0, 0},
- {"TDFFL" , 0, 1, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_1_3" , 1, 3, 365, "RAZ", 1, 1, 0, 0},
- {"VRTFL" , 4, 1, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_7" , 5, 3, 365, "RAZ", 1, 1, 0, 0},
- {"DUTRESFL" , 8, 1, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_9_11" , 9, 3, 365, "RAZ", 1, 1, 0, 0},
- {"IOCDATFL" , 12, 1, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_13_15" , 13, 3, 365, "RAZ", 1, 1, 0, 0},
- {"IOCCMDFL" , 16, 1, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 365, "RAZ", 1, 1, 0, 0},
- {"DUTFL" , 32, 6, 365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_38_63" , 38, 26, 365, "RAZ", 1, 1, 0, 0},
- {"VBFFL" , 0, 4, 366, "RO", 1, 0, 0, 0ull},
- {"RDFFL" , 4, 1, 366, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_61" , 5, 57, 366, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 62, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 63, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFL" , 0, 8, 367, "RO", 1, 0, 0, 0ull},
- {"FBFFL" , 8, 8, 367, "RO", 1, 0, 0, 0ull},
- {"SBFFL" , 16, 8, 367, "RO", 1, 0, 0, 0ull},
- {"FBFRSPFL" , 24, 8, 367, "RO", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 367, "RAZ", 1, 1, 0, 0},
- {"TAGFL" , 0, 16, 368, "RO", 1, 0, 0, 0ull},
- {"LRUFL" , 16, 1, 368, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 368, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 369, "R/W", 1, 1, 0, 0},
- {"DISIDXALIAS" , 0, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"DISECC" , 1, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"VAB_THRESH" , 2, 4, 370, "R/W", 0, 0, 0ull, 0ull},
- {"EF_CNT" , 6, 7, 370, "R/W", 0, 0, 0ull, 4ull},
- {"EF_ENA" , 13, 1, 370, "R/W", 0, 0, 0ull, 1ull},
- {"XMC_ARB_MODE" , 14, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"RSP_ARB_MODE" , 15, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"MAXLFB" , 16, 4, 370, "R/W", 0, 0, 0ull, 0ull},
- {"MAXVAB" , 20, 4, 370, "R/W", 0, 0, 0ull, 0ull},
- {"DISCCLK" , 24, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFDBE" , 25, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFSBE" , 26, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"DISSTGL2I" , 27, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 370, "RAZ", 1, 1, 0, 0},
- {"VALID" , 0, 1, 371, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_9" , 1, 9, 371, "RAZ", 1, 1, 0, 0},
- {"TAG" , 10, 28, 371, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 371, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 372, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 372, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 4, 17, 372, "RO", 1, 0, 0, 0ull},
- {"RESERVED_21_49" , 21, 29, 372, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 10, 372, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 373, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_6" , 2, 5, 373, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 7, 14, 373, "RO", 1, 0, 0, 0ull},
- {"RESERVED_21_49" , 21, 29, 373, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 6, 373, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_60" , 56, 5, 373, "RAZ", 1, 1, 0, 0},
- {"NOWAY" , 61, 1, 373, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 373, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 373, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 374, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_49" , 2, 48, 374, "RAZ", 1, 1, 0, 0},
- {"VSYN" , 50, 10, 374, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 374, "RO", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 374, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 374, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 38, 375, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_47" , 38, 10, 375, "RAZ", 1, 1, 0, 0},
- {"SID" , 48, 4, 375, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_57" , 52, 6, 375, "RAZ", 1, 1, 0, 0},
- {"CMD" , 58, 6, 375, "RO", 0, 1, 0ull, 0},
- {"HOLERD" , 0, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"HOLEWR" , 1, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"VRTWR" , 2, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"VRTIDRNG" , 3, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"VRTADRNG" , 4, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"VRTPE" , 5, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"BIGWR" , 6, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"BIGRD" , 7, 1, 376, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 376, "RAZ", 1, 1, 0, 0},
- {"HOLERD" , 0, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"HOLEWR" , 1, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTWR" , 2, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTIDRNG" , 3, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTADRNG" , 4, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTPE" , 5, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGWR" , 6, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGRD" , 7, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 377, "RAZ", 1, 1, 0, 0},
- {"TAD0" , 16, 1, 377, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 377, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 378, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 379, "R/W", 0, 1, 0ull, 0},
- {"LVL" , 0, 2, 380, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 380, "RAZ", 1, 1, 0, 0},
- {"DWBLVL" , 4, 2, 380, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 380, "RAZ", 1, 1, 0, 0},
- {"LVL" , 0, 2, 381, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 381, "RAZ", 1, 1, 0, 0},
- {"WGT0" , 0, 8, 382, "R/W", 0, 0, 255ull, 255ull},
- {"WGT1" , 8, 8, 382, "R/W", 0, 0, 255ull, 255ull},
- {"WGT2" , 16, 8, 382, "R/W", 0, 0, 255ull, 255ull},
- {"WGT3" , 24, 8, 382, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 382, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 383, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 384, "R/W", 0, 1, 0ull, 0},
- {"OW0ECC" , 0, 10, 385, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 385, "RAZ", 1, 1, 0, 0},
- {"OW1ECC" , 16, 10, 385, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 385, "RAZ", 1, 1, 0, 0},
- {"OW2ECC" , 32, 10, 385, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 385, "RAZ", 1, 1, 0, 0},
- {"OW3ECC" , 48, 10, 385, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 385, "RAZ", 1, 1, 0, 0},
- {"OW4ECC" , 0, 10, 386, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 386, "RAZ", 1, 1, 0, 0},
- {"OW5ECC" , 16, 10, 386, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 386, "RAZ", 1, 1, 0, 0},
- {"OW6ECC" , 32, 10, 386, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 386, "RAZ", 1, 1, 0, 0},
- {"OW7ECC" , 48, 10, 386, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 386, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 387, "R/W", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"WRDISLMC" , 8, 1, 387, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 387, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 388, "R/W1C", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 388, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 388, "R/W1C", 0, 0, 0ull, 0ull},
- {"WRDISLMC" , 8, 1, 388, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 388, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 389, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 390, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 391, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 392, "R/W", 0, 1, 0ull, 0},
- {"CNT0SEL" , 0, 8, 393, "R/W", 0, 0, 0ull, 1ull},
- {"CNT1SEL" , 8, 8, 393, "R/W", 0, 0, 0ull, 1ull},
- {"CNT2SEL" , 16, 8, 393, "R/W", 0, 0, 0ull, 1ull},
- {"CNT3SEL" , 24, 8, 393, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 393, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 0, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"DIRTY" , 1, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"VALID" , 2, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"USE" , 3, 1, 394, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_16" , 4, 13, 394, "RAZ", 1, 1, 0, 0},
- {"TAG" , 17, 19, 394, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_39" , 36, 4, 394, "RAZ", 1, 1, 0, 0},
- {"ECC" , 40, 6, 394, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_63" , 46, 18, 394, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 395, "R/W1C", 0, 0, 0ull, 0ull},
- {"MASK" , 0, 1, 396, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 396, "RAZ", 1, 1, 0, 0},
- {"DWB" , 0, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"INVL2" , 1, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 397, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 6, 398, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 398, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 399, "RAZ", 1, 1, 0, 0},
- {"DWBID" , 8, 6, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 399, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 400, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 400, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 401, "R/W", 0, 0, 0ull, 1ull},
- {"NUMID" , 1, 3, 401, "R/W", 0, 0, 5ull, 5ull},
- {"MEMSZ" , 4, 3, 401, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_7_7" , 7, 1, 401, "RAZ", 1, 1, 0, 0},
- {"OOBERR" , 8, 1, 401, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 401, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 32, 402, "R/W", 0, 0, 0ull, 0ull},
- {"PARITY" , 32, 4, 402, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 402, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 403, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 403, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 404, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 404, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 405, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 38, 406, "R/W", 1, 1, 0, 0},
- {"RESERVED_38_56" , 38, 19, 406, "RAZ", 1, 1, 0, 0},
- {"CMD" , 57, 6, 406, "R/W", 1, 1, 0, 0},
- {"INUSE" , 63, 1, 406, "RO", 0, 0, 0ull, 0ull},
- {"COUNT" , 0, 64, 407, "R/W", 0, 1, 0ull, 0},
- {"PRBS" , 0, 32, 408, "R/W", 1, 1, 0, 0},
- {"PROG" , 32, 8, 408, "R/W", 1, 1, 0, 0},
- {"SEL" , 40, 1, 408, "R/W", 1, 1, 0, 0},
- {"EN" , 41, 1, 408, "R/W", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 408, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 409, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 410, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 410, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 411, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 412, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 412, "R/W", 1, 1, 0, 0},
- {"CKE_MASK" , 0, 2, 413, "R/W", 1, 1, 0, 0},
- {"CS0_N_MASK" , 2, 2, 413, "R/W", 1, 1, 0, 0},
- {"CS1_N_MASK" , 4, 2, 413, "R/W", 1, 1, 0, 0},
- {"ODT0_MASK" , 6, 2, 413, "R/W", 1, 1, 0, 0},
- {"ODT1_MASK" , 8, 2, 413, "R/W", 1, 1, 0, 0},
- {"RAS_N_MASK" , 10, 1, 413, "R/W", 1, 1, 0, 0},
- {"CAS_N_MASK" , 11, 1, 413, "R/W", 1, 1, 0, 0},
- {"WE_N_MASK" , 12, 1, 413, "R/W", 1, 1, 0, 0},
- {"BA_MASK" , 13, 3, 413, "R/W", 1, 1, 0, 0},
- {"A_MASK" , 16, 16, 413, "R/W", 1, 1, 0, 0},
- {"RESET_N_MASK" , 32, 1, 413, "R/W", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 413, "R/W", 1, 1, 0, 0},
- {"DQX_CTL" , 0, 4, 414, "R/W", 0, 1, 4ull, 0},
- {"CK_CTL" , 4, 4, 414, "R/W", 0, 1, 4ull, 0},
- {"CMD_CTL" , 8, 4, 414, "R/W", 0, 1, 4ull, 0},
- {"RODT_CTL" , 12, 4, 414, "R/W", 0, 1, 0ull, 0},
- {"NTUNE" , 16, 4, 414, "R/W", 0, 1, 0ull, 0},
- {"PTUNE" , 20, 4, 414, "R/W", 0, 1, 0ull, 0},
- {"BYP" , 24, 1, 414, "R/W", 0, 1, 0ull, 0},
- {"M180" , 25, 1, 414, "R/W", 0, 1, 0ull, 0},
- {"DDR__NTUNE" , 26, 4, 414, "RO", 1, 1, 0, 0},
- {"DDR__PTUNE" , 30, 4, 414, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 414, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 415, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 415, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 415, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 415, "R/W", 0, 1, 5ull, 0},
- {"IDLEPOWER" , 9, 3, 415, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 12, 4, 415, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 16, 1, 415, "R/W", 0, 0, 0ull, 1ull},
- {"RESET" , 17, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"REF_ZQCS_INT" , 18, 19, 415, "R/W", 1, 1, 0, 0},
- {"SEQUENCE" , 37, 3, 415, "R/W", 0, 0, 0ull, 0ull},
- {"EARLY_DQX" , 40, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"SREF_WITH_DLL" , 41, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RANK_ENA" , 42, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"RANKMASK" , 43, 4, 415, "R/W", 0, 1, 0ull, 0},
- {"MIRRMASK" , 47, 4, 415, "R/W", 0, 1, 0ull, 0},
- {"INIT_STATUS" , 51, 4, 415, "R/W1", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R0" , 55, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R1" , 56, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R0" , 57, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R1" , 58, 1, 415, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_59_63" , 59, 5, 415, "RAZ", 1, 1, 0, 0},
- {"RDIMM_ENA" , 0, 1, 416, "R/W", 0, 1, 0ull, 0},
- {"BWCNT" , 1, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 2, 1, 416, "R/W", 0, 0, 0ull, 1ull},
- {"POCAS" , 3, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH2" , 4, 2, 416, "R/W", 0, 0, 0ull, 1ull},
- {"THROTTLE_RD" , 6, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"THROTTLE_WR" , 7, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_RD" , 8, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_WR" , 9, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"ELEV_PRIO_DIS" , 10, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"NXM_WRITE_EN" , 11, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 12, 4, 416, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 16, 1, 416, "R/W", 0, 0, 0ull, 1ull},
- {"AUTO_DCLKDIS" , 17, 1, 416, "R/W", 0, 0, 0ull, 1ull},
- {"INT_ZQCS_DIS" , 18, 1, 416, "R/W", 0, 0, 1ull, 0ull},
- {"EXT_ZQCS_DIS" , 19, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 20, 2, 416, "R/W", 0, 0, 0ull, 0ull},
- {"WODT_BPRCH" , 22, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_BPRCH" , 23, 1, 416, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 416, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT" , 0, 64, 417, "RO", 0, 1, 0ull, 0},
- {"CLKF" , 0, 7, 418, "R/W", 0, 1, 48ull, 0},
- {"RESET_N" , 7, 1, 418, "R/W", 0, 0, 0ull, 1ull},
- {"CPB" , 8, 3, 418, "R/W", 0, 0, 0ull, 1ull},
- {"CPS" , 11, 3, 418, "R/W", 0, 0, 0ull, 1ull},
- {"DIFFAMP" , 14, 4, 418, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_PS_EN" , 18, 3, 418, "R/W", 0, 1, 2ull, 0},
- {"DDR_DIV_RESET" , 21, 1, 418, "R/W", 0, 0, 1ull, 0ull},
- {"DFM_PS_EN" , 22, 3, 418, "R/W", 0, 1, 2ull, 0},
- {"DFM_DIV_RESET" , 25, 1, 418, "R/W", 0, 0, 1ull, 0ull},
- {"JTG_TEST_MODE" , 26, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 418, "RAZ", 1, 1, 0, 0},
- {"RC0" , 0, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC1" , 4, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC2" , 8, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC3" , 12, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC4" , 16, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC5" , 20, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC6" , 24, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC7" , 28, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC8" , 32, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC9" , 36, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC10" , 40, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC11" , 44, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC12" , 48, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC13" , 52, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC14" , 56, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"RC15" , 60, 4, 419, "R/W", 0, 0, 0ull, 0ull},
- {"DIMM0_WMASK" , 0, 16, 420, "R/W", 0, 0, 65535ull, 65535ull},
- {"DIMM1_WMASK" , 16, 16, 420, "R/W", 0, 0, 65535ull, 65535ull},
- {"TCWS" , 32, 13, 420, "R/W", 0, 0, 1248ull, 1248ull},
- {"PARITY" , 45, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 420, "RAZ", 1, 1, 0, 0},
- {"BYP_SETTING" , 0, 8, 421, "R/W", 0, 0, 0ull, 0ull},
- {"BYP_SEL" , 8, 4, 421, "R/W", 0, 0, 0ull, 0ull},
- {"QUAD_DLL_ENA" , 12, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 13, 1, 421, "R/W", 0, 0, 1ull, 0ull},
- {"DLL_BRINGUP" , 14, 1, 421, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 421, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 422, "R/W", 0, 0, 0ull, 0ull},
- {"BYTE_SEL" , 6, 4, 422, "R/W", 0, 0, 0ull, 0ull},
- {"MODE_SEL" , 10, 2, 422, "R/W", 0, 0, 0ull, 0ull},
- {"LOAD_OFFSET" , 12, 1, 422, "WR0", 0, 0, 0ull, 0ull},
- {"OFFSET_ENA" , 13, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYTE_SEL" , 14, 4, 422, "R/W", 0, 0, 1ull, 1ull},
- {"DLL_MODE" , 18, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"FINE_TUNE_MODE" , 19, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"DLL90_SETTING" , 20, 8, 422, "RO", 1, 1, 0, 0},
- {"DLL_FAST" , 28, 1, 422, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 422, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 423, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 423, "RAZ", 1, 1, 0, 0},
- {"ROW_LSB" , 16, 3, 423, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_19_63" , 19, 45, 423, "RAZ", 1, 1, 0, 0},
- {"MRDSYN0" , 0, 8, 424, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 424, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 424, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 424, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 424, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 14, 425, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 14, 16, 425, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 30, 3, 425, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 33, 1, 425, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 34, 2, 425, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 425, "RAZ", 1, 1, 0, 0},
- {"IFBCNT" , 0, 64, 426, "RO", 0, 1, 1ull, 0},
- {"NXM_WR_ERR" , 0, 1, 427, "R/W1C", 0, 0, 0ull, 0ull},
- {"SEC_ERR" , 1, 4, 427, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 5, 4, 427, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 427, "RAZ", 1, 1, 0, 0},
- {"INTR_NXM_WR_ENA" , 0, 1, 428, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_SEC_ENA" , 1, 1, 428, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 2, 1, 428, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 428, "RAZ", 1, 1, 0, 0},
- {"CWL" , 0, 3, 429, "R/W", 0, 0, 0ull, 0ull},
- {"MPRLOC" , 3, 2, 429, "R/W", 0, 0, 0ull, 0ull},
- {"MPR" , 5, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"DLL" , 6, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"AL" , 7, 2, 429, "R/W", 0, 0, 0ull, 0ull},
- {"WLEV" , 9, 1, 429, "RO", 0, 0, 0ull, 0ull},
- {"TDQS" , 10, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"QOFF" , 11, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"BL" , 12, 2, 429, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 14, 4, 429, "R/W", 0, 0, 2ull, 2ull},
- {"RBT" , 18, 1, 429, "RO", 0, 0, 1ull, 1ull},
- {"TM" , 19, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"DLLR" , 20, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"WRP" , 21, 3, 429, "R/W", 0, 0, 0ull, 0ull},
- {"PPD" , 24, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 429, "RAZ", 1, 1, 0, 0},
- {"PASR_00" , 0, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_00" , 3, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_00" , 4, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_00" , 5, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_00" , 7, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_00" , 9, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_01" , 12, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_01" , 15, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_01" , 16, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_01" , 17, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_01" , 19, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_01" , 21, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_10" , 24, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_10" , 27, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_10" , 28, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_10" , 29, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_10" , 31, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_10" , 33, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_11" , 36, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_11" , 39, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_11" , 40, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_11" , 41, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_11" , 43, 2, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_11" , 45, 3, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 430, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R0" , 8, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R1" , 12, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R0" , 16, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R1" , 20, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R0" , 24, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R1" , 28, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R0" , 32, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R1" , 36, 4, 431, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 431, "RAZ", 1, 1, 0, 0},
- {"OPSCNT" , 0, 64, 432, "RO", 0, 1, 1ull, 0},
- {"TS_STAGGER" , 0, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK_POS" , 1, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK" , 2, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT0" , 3, 4, 433, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE0" , 7, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT1" , 8, 4, 433, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE1" , 12, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"LV_MODE" , 13, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"RX_ALWAYS_ON" , 14, 1, 433, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 433, "RAZ", 1, 1, 0, 0},
- {"DDR3RST" , 0, 1, 434, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PWARM" , 1, 1, 434, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSOFT" , 2, 1, 434, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSV" , 3, 1, 434, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 434, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 435, "R/W", 0, 1, 0ull, 0},
- {"OFFSET" , 4, 4, 435, "R/W", 0, 0, 2ull, 2ull},
- {"OFFSET_EN" , 8, 1, 435, "R/W", 0, 0, 1ull, 1ull},
- {"OR_DIS" , 9, 1, 435, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 10, 8, 435, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_0" , 18, 1, 435, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_1" , 19, 1, 435, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_2" , 20, 1, 435, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_3" , 21, 1, 435, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 435, "RAZ", 1, 1, 0, 0},
- {"BITMASK" , 0, 64, 436, "RO", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 6, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 12, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 18, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 24, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 30, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 36, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 42, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 48, 6, 437, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 54, 2, 437, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 437, "RAZ", 1, 1, 0, 0},
- {"RODT_D0_R0" , 0, 8, 438, "R/W", 0, 1, 0ull, 0},
- {"RODT_D0_R1" , 8, 8, 438, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R0" , 16, 8, 438, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R1" , 24, 8, 438, "R/W", 0, 1, 0ull, 0},
- {"RODT_D2_R0" , 32, 8, 438, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R1" , 40, 8, 438, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R0" , 48, 8, 438, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R1" , 56, 8, 438, "R/W", 0, 0, 0ull, 0ull},
- {"R2R_INIT" , 0, 6, 439, "R/W", 0, 1, 1ull, 0},
- {"R2W_INIT" , 6, 6, 439, "R/W", 0, 1, 6ull, 0},
- {"W2R_INIT" , 12, 6, 439, "R/W", 0, 1, 9ull, 0},
- {"W2W_INIT" , 18, 6, 439, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_24_63" , 24, 40, 439, "RAZ", 1, 1, 0, 0},
- {"R2R_XRANK_INIT" , 0, 6, 440, "R/W", 0, 1, 3ull, 0},
- {"R2W_XRANK_INIT" , 6, 6, 440, "R/W", 0, 1, 6ull, 0},
- {"W2R_XRANK_INIT" , 12, 6, 440, "R/W", 0, 1, 4ull, 0},
- {"W2W_XRANK_INIT" , 18, 6, 440, "R/W", 0, 1, 5ull, 0},
- {"RESERVED_24_63" , 24, 40, 440, "RAZ", 1, 1, 0, 0},
- {"R2R_XDIMM_INIT" , 0, 6, 441, "R/W", 0, 1, 4ull, 0},
- {"R2W_XDIMM_INIT" , 6, 6, 441, "R/W", 0, 1, 7ull, 0},
- {"W2R_XDIMM_INIT" , 12, 6, 441, "R/W", 0, 1, 4ull, 0},
- {"W2W_XDIMM_INIT" , 18, 6, 441, "R/W", 0, 1, 6ull, 0},
- {"RESERVED_24_63" , 24, 40, 441, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_9" , 0, 10, 442, "RAZ", 1, 1, 0, 0},
- {"TZQCS" , 10, 4, 442, "R/W", 0, 0, 4ull, 4ull},
- {"TCKE" , 14, 4, 442, "R/W", 0, 0, 3ull, 3ull},
- {"TXPR" , 18, 4, 442, "R/W", 0, 0, 5ull, 5ull},
- {"TMRD" , 22, 4, 442, "R/W", 0, 0, 4ull, 4ull},
- {"TMOD" , 26, 4, 442, "R/W", 0, 0, 12ull, 12ull},
- {"TDLLK" , 30, 4, 442, "R/W", 0, 0, 2ull, 2ull},
- {"TZQINIT" , 34, 4, 442, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 38, 4, 442, "R/W", 0, 0, 6ull, 6ull},
- {"TCKSRE" , 42, 4, 442, "R/W", 0, 0, 5ull, 5ull},
- {"TRP_EXT" , 46, 1, 442, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 442, "RAZ", 1, 1, 0, 0},
- {"TMPRR" , 0, 4, 443, "R/W", 0, 0, 1ull, 1ull},
- {"TRAS" , 4, 5, 443, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 9, 4, 443, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 13, 4, 443, "R/W", 0, 0, 2ull, 3ull},
- {"TRFC" , 17, 5, 443, "R/W", 0, 0, 6ull, 7ull},
- {"TRRD" , 22, 3, 443, "R/W", 0, 0, 2ull, 2ull},
- {"TXP" , 25, 3, 443, "R/W", 0, 0, 3ull, 3ull},
- {"TWLMRD" , 28, 4, 443, "R/W", 0, 0, 10ull, 10ull},
- {"TWLDQSEN" , 32, 4, 443, "R/W", 0, 0, 7ull, 7ull},
- {"TFAW" , 36, 5, 443, "R/W", 0, 0, 0ull, 9ull},
- {"TXPDLL" , 41, 5, 443, "R/W", 0, 0, 0ull, 10ull},
- {"TRAS_EXT" , 46, 1, 443, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 443, "RAZ", 1, 1, 0, 0},
- {"TRESET" , 0, 1, 444, "R/W", 0, 1, 1ull, 0},
- {"RCLK_CNT" , 1, 32, 444, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 444, "RAZ", 1, 1, 0, 0},
- {"RING_CNT" , 0, 32, 445, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 445, "RAZ", 1, 1, 0, 0},
- {"LANEMASK" , 0, 9, 446, "R/W", 0, 1, 0ull, 0},
- {"SSET" , 9, 1, 446, "R/W", 0, 1, 0ull, 0},
- {"OR_DIS" , 10, 1, 446, "R/W", 0, 1, 0ull, 0},
- {"BITMASK" , 11, 8, 446, "R/W", 0, 1, 0ull, 0},
- {"RTT_NOM" , 19, 3, 446, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 446, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 447, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 4, 8, 447, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 447, "RAZ", 1, 1, 0, 0},
- {"BYTE0" , 0, 5, 448, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 5, 5, 448, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 10, 5, 448, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 15, 5, 448, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 20, 5, 448, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 25, 5, 448, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 30, 5, 448, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 35, 5, 448, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 40, 5, 448, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 45, 2, 448, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_63" , 47, 17, 448, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 449, "R/W", 0, 1, 255ull, 0},
- {"WODT_D0_R1" , 8, 8, 449, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R0" , 16, 8, 449, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R1" , 24, 8, 449, "R/W", 0, 1, 255ull, 0},
- {"WODT_D2_R0" , 32, 8, 449, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D2_R1" , 40, 8, 449, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R0" , 48, 8, 449, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R1" , 56, 8, 449, "R/W", 0, 0, 255ull, 0ull},
- {"STAT" , 0, 9, 450, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 450, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 451, "R/W", 1, 1, 0, 0},
- {"PCTL" , 6, 6, 451, "R/W", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 451, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 452, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 452, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 452, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 452, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 452, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 452, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 452, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 452, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 452, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 452, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 453, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 453, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 453, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 454, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 454, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 454, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 455, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 455, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 455, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 455, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 455, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 456, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 456, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 456, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 457, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 457, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 457, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 458, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 458, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 458, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 459, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 459, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 459, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 459, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 459, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 460, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 461, "RAZ", 1, 1, 0, 0},
- {"NAND" , 8, 1, 461, "RO", 1, 1, 0, 0},
- {"TERM" , 9, 2, 461, "RO", 1, 1, 0, 0},
- {"DMACK_P0" , 11, 1, 461, "RO", 1, 1, 0, 0},
- {"DMACK_P1" , 12, 1, 461, "RO", 1, 1, 0, 0},
- {"RESERVED_13_13" , 13, 1, 461, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 14, 1, 461, "RO", 1, 1, 0, 0},
- {"ALE" , 15, 1, 461, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 461, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 16, 462, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 462, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 462, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 462, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 462, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 462, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 462, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 462, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 462, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 462, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 462, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 462, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 462, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 463, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 463, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 463, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 463, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 463, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 463, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 463, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 463, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 463, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 463, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 463, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 463, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 463, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 464, "R/W", 0, 0, 25ull, 25ull},
- {"RESERVED_6_7" , 6, 2, 464, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 464, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 464, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 464, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 464, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 465, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 466, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 466, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 467, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 467, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 6, 468, "RO", 1, 1, 0, 0},
- {"RESERVED_6_15" , 6, 10, 468, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 468, "RO", 1, 1, 0, 0},
- {"RESERVED_24_25" , 24, 2, 468, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 468, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 468, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 468, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 468, "RO", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 468, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 468, "RO", 1, 1, 0, 0},
- {"DORM_CRYPTO" , 34, 1, 468, "RO", 1, 1, 0, 0},
- {"RESERVED_35_63" , 35, 29, 468, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 469, "RAZ", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 469, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 469, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 469, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 469, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 469, "RO", 1, 1, 0, 0},
- {"ZIP_INFO" , 29, 2, 469, "RO", 1, 1, 0, 0},
- {"RESERVED_31_31" , 31, 1, 469, "RAZ", 1, 1, 0, 0},
- {"L2C_CRIP" , 32, 3, 469, "RO", 1, 1, 0, 0},
- {"PLL_HALF_DIS" , 35, 1, 469, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_MAN" , 36, 1, 469, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_RSV" , 37, 1, 469, "RO", 1, 1, 0, 0},
- {"EMA" , 38, 2, 469, "RO", 1, 1, 0, 0},
- {"RESERVED_40_40" , 40, 1, 469, "RAZ", 1, 1, 0, 0},
- {"DFA_INFO_CLM" , 41, 4, 469, "RO", 1, 1, 0, 0},
- {"DFA_INFO_DTE" , 45, 3, 469, "RO", 1, 1, 0, 0},
- {"PLL_CTL" , 48, 10, 469, "RO", 1, 1, 0, 0},
- {"RESERVED_58_63" , 58, 6, 469, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 470, "RAZ", 1, 1, 0, 0},
- {"RESERVED_3_3" , 3, 1, 470, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 470, "RAZ", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 470, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 471, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 472, "RAZ", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 472, "RAZ", 0, 1, 0ull, 0},
- {"PNR_COUT_SEL" , 2, 2, 472, "R/W", 0, 1, 0ull, 0},
- {"PNR_COUT_RST" , 4, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_SEL" , 5, 2, 472, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_RST" , 7, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 472, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 473, "R/W", 1, 1, 0, 0},
- {"SOFT" , 1, 1, 473, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 473, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 6, 474, "R/W", 0, 1, 1ull, 0},
- {"SCLK_HI" , 6, 15, 474, "R/W", 0, 1, 5000ull, 0},
- {"SCLK_LO" , 21, 4, 474, "R/W", 0, 1, 1ull, 0},
- {"OUT" , 25, 7, 474, "R/W", 0, 1, 1ull, 0},
- {"PROG_PIN" , 32, 1, 474, "RO", 0, 0, 0ull, 0ull},
- {"FSRC_PIN" , 33, 1, 474, "RO", 0, 0, 0ull, 0ull},
- {"VGATE_PIN" , 34, 1, 474, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 474, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 475, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 475, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 475, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 475, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 475, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 475, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 475, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 10, 476, "R/W", 0, 1, 999ull, 0},
- {"SDH" , 10, 4, 476, "R/W", 0, 1, 0ull, 0},
- {"PRH" , 14, 4, 476, "R/W", 0, 1, 6ull, 0},
- {"FSH" , 18, 4, 476, "R/W", 0, 1, 15ull, 0},
- {"SCH" , 22, 4, 476, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_26_63" , 26, 38, 476, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 18, 477, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 18, 18, 477, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 36, 18, 477, "RO", 0, 0, 0ull, 0ull},
- {"TOO_MANY" , 54, 1, 477, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 477, "RAZ", 1, 1, 0, 0},
- {"REPAIR3" , 0, 18, 478, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR4" , 18, 18, 478, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR5" , 36, 18, 478, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 478, "RAZ", 1, 1, 0, 0},
- {"REPAIR6" , 0, 18, 479, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 479, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 480, "RAZ", 1, 1, 0, 0},
- {"REPAIR1" , 14, 14, 480, "RAZ", 1, 1, 0, 0},
- {"REPAIR2" , 28, 14, 480, "RAZ", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 480, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 481, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 481, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 4, 482, "R/W", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 482, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 483, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 6, 6, 483, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_12_63" , 12, 52, 483, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 484, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 484, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 484, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 485, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 485, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 486, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 486, "RAZ", 1, 1, 0, 0},
- {"PTP_EN" , 0, 1, 487, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EN" , 1, 1, 487, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_IN" , 2, 6, 487, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EN" , 8, 1, 487, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EDGE" , 9, 1, 487, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_IN" , 10, 6, 487, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EN" , 16, 1, 487, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EDGE" , 17, 1, 487, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_IN" , 18, 6, 487, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 487, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 488, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 488, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 489, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 490, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 490, "RAZ", 1, 1, 0, 0},
- {"CNTR" , 0, 64, 491, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 492, "R/W", 0, 0, 0ull, 0ull},
- {"RBOOT_PIN" , 0, 1, 493, "RO", 1, 1, 0, 0},
- {"RBOOT" , 1, 1, 493, "R/W", 1, 1, 0, 0},
- {"LBOOT" , 2, 10, 493, "R/W1C", 1, 1, 0, 0},
- {"QLM0_SPD" , 12, 4, 493, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 16, 4, 493, "RO", 1, 1, 0, 0},
- {"QLM2_SPD" , 20, 4, 493, "RO", 1, 1, 0, 0},
- {"PNR_MUL" , 24, 6, 493, "RO", 1, 1, 0, 0},
- {"C_MUL" , 30, 6, 493, "RO", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 493, "RAZ", 1, 1, 0, 0},
- {"SOFT_CLR_BIST" , 0, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"WARM_CLR_BIST" , 1, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"CNTL_CLR_BIST" , 2, 1, 494, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_5" , 3, 3, 494, "RAZ", 1, 1, 0, 0},
- {"BIST_DELAY" , 6, 58, 494, "RO", 1, 1, 0, 0},
- {"RST_VAL" , 0, 1, 495, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 495, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 495, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 495, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 495, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 495, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 495, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 495, "RO", 1, 1, 0, 0},
- {"PRST_LINK" , 9, 1, 495, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 495, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST_DLY" , 0, 16, 496, "R/W", 0, 1, 2047ull, 0},
- {"WARM_RST_DLY" , 16, 16, 496, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_32_63" , 32, 32, 496, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 497, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 497, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 498, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 498, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 499, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 499, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 499, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 499, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 499, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 499, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 499, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 499, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 499, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 499, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 499, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 499, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 499, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 500, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 500, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 500, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 500, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 500, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 500, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 500, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 500, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 501, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 501, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 501, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 502, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 502, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 502, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 503, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 503, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 504, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 504, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 505, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 505, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 506, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 506, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 506, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 506, "RAZ", 1, 1, 0, 0},
- {"TXTRIG" , 4, 2, 506, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 506, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 506, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 507, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 507, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 508, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 508, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 508, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 508, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 508, "RAZ", 1, 1, 0, 0},
- {"PTIME" , 7, 1, 508, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 508, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 509, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 509, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 509, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 509, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 510, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 510, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 510, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 510, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 510, "RAZ", 1, 1, 0, 0},
- {"BRK" , 6, 1, 510, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 510, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 510, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 511, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 511, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 511, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 511, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 511, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 511, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 511, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 511, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 511, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 512, "RAZ", 1, 1, 0, 0},
- {"DCTS" , 0, 1, 513, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 513, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 513, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 513, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 513, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 513, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 513, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 513, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 513, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 514, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 514, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 515, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 515, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 516, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 516, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 516, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 516, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 517, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 517, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 518, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 518, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 519, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 519, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 520, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 520, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 520, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 520, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 521, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 521, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 522, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 522, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 523, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 524, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 524, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 525, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 525, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 526, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 526, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 527, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 527, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 527, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 527, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 527, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 527, "RAZ", 1, 1, 0, 0},
- {"ORFDAT" , 0, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"IRFDAT" , 1, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"IPFDAT" , 2, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"MRQDAT" , 3, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"MRGDAT" , 4, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"OPFDAT" , 5, 1, 528, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 528, "RAZ", 0, 0, 0ull, 0ull},
- {"MRQ_HWM" , 0, 2, 529, "R/W", 0, 0, 0ull, 1ull},
- {"NBTARB" , 2, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"LENDIAN" , 3, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 4, 1, 529, "R/W", 0, 0, 1ull, 0ull},
- {"EN" , 5, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 6, 1, 529, "RO", 0, 0, 0ull, 0ull},
- {"CRC_STRIP" , 7, 1, 529, "R/W", 0, 0, 0ull, 0ull},
- {"TS_THRESH" , 8, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 529, "RAZ", 1, 1, 0, 0},
- {"OVFENA" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"IVFENA" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"OTHENA" , 2, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"ITHENA" , 3, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_DRPENA" , 4, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"IRUNENA" , 5, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"ORUNENA" , 6, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"TSENA" , 7, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 530, "RAZ", 1, 1, 0, 0},
- {"IRCNT" , 0, 20, 531, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 531, "RAZ", 1, 1, 0, 0},
- {"IRHWM" , 0, 20, 532, "R/W", 0, 0, 0ull, 0ull},
- {"IBPLWM" , 20, 20, 532, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 532, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 533, "RAZ", 1, 1, 0, 0},
- {"IBASE" , 3, 37, 533, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 40, 20, 533, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 533, "RAZ", 1, 1, 0, 0},
- {"IDBELL" , 0, 20, 534, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 534, "RAZ", 1, 1, 0, 0},
- {"ITLPTR" , 32, 20, 534, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 534, "RAZ", 1, 1, 0, 0},
- {"ODBLOVF" , 0, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
- {"IDBLOVF" , 1, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORTHRESH" , 2, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"IRTHRESH" , 3, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"DATA_DRP" , 4, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
- {"IRUN" , 5, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORUN" , 6, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
- {"TS" , 7, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 535, "RAZ", 1, 1, 0, 0},
- {"ORCNT" , 0, 20, 536, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 536, "RAZ", 1, 1, 0, 0},
- {"ORHWM" , 0, 20, 537, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 537, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 538, "RAZ", 1, 1, 0, 0},
- {"OBASE" , 3, 37, 538, "R/W", 0, 1, 0ull, 0},
- {"OSIZE" , 40, 20, 538, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 538, "RAZ", 1, 1, 0, 0},
- {"ODBELL" , 0, 20, 539, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 539, "RAZ", 1, 1, 0, 0},
- {"OTLPTR" , 32, 20, 539, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 539, "RAZ", 1, 1, 0, 0},
- {"OREMCNT" , 0, 20, 540, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 540, "RAZ", 1, 1, 0, 0},
- {"IREMCNT" , 32, 20, 540, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_52_63" , 52, 12, 540, "RAZ", 1, 1, 0, 0},
- {"TSCNT" , 0, 5, 541, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 541, "RAZ", 1, 1, 0, 0},
- {"TSTOT" , 8, 5, 541, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 541, "RAZ", 1, 1, 0, 0},
- {"TSAVL" , 16, 5, 541, "RO", 0, 0, 4ull, 4ull},
- {"RESERVED_21_63" , 21, 43, 541, "RAZ", 1, 1, 0, 0},
- {"TSTAMP" , 0, 64, 542, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 3, 543, "R/W", 0, 1, 0ull, 0},
- {"ADR_CYC" , 3, 4, 543, "R/W", 0, 1, 8ull, 0},
- {"T_MULT" , 7, 4, 543, "R/W", 0, 1, 9ull, 0},
- {"RESERVED_11_63" , 11, 53, 543, "RAZ", 1, 1, 0, 0},
- {"NF_CMD" , 0, 64, 544, "R/W", 0, 1, 0ull, 0},
- {"CNT" , 0, 8, 545, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 545, "RAZ", 1, 1, 0, 0},
- {"ECC_ERR" , 0, 8, 546, "RO", 0, 1, 0ull, 0},
- {"XOR_ECC" , 8, 24, 546, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 546, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 547, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 548, "RAZ", 1, 1, 0, 0},
- {"RST_FF" , 0, 1, 549, "R/W", 0, 0, 0ull, 0ull},
- {"EX_DIS" , 1, 1, 549, "R/W", 0, 0, 0ull, 0ull},
- {"BT_DIS" , 2, 1, 549, "R/W", 0, 0, 0ull, 1ull},
- {"BT_DMA" , 3, 1, 549, "R/W", 0, 1, 0ull, 0},
- {"RD_CMD" , 4, 1, 549, "R/W", 0, 0, 0ull, 0ull},
- {"RD_VAL" , 5, 1, 549, "RO", 0, 1, 0ull, 0},
- {"RD_DONE" , 6, 1, 549, "R/W1C", 0, 0, 0ull, 0ull},
- {"FR_BYT" , 7, 11, 549, "RO", 0, 1, 0ull, 0},
- {"WAIT_CNT" , 18, 6, 549, "R/W", 0, 1, 20ull, 0},
- {"NBR_HWM" , 24, 3, 549, "R/W", 0, 0, 3ull, 3ull},
- {"MB_DIS" , 27, 1, 549, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 549, "RAZ", 1, 1, 0, 0},
- {"MAIN_SM" , 0, 3, 550, "RO", 0, 1, 0ull, 0},
- {"MAIN_BAD" , 3, 1, 550, "RO", 0, 1, 0ull, 0},
- {"RD_FF" , 4, 2, 550, "RO", 0, 1, 0ull, 0},
- {"RD_FF_BAD" , 6, 1, 550, "RO", 0, 1, 0ull, 0},
- {"BT_SM" , 7, 4, 550, "RO", 0, 1, 0ull, 0},
- {"EXE_SM" , 11, 4, 550, "RO", 0, 1, 0ull, 0},
- {"EXE_IDLE" , 15, 1, 550, "RO", 0, 1, 1ull, 0},
- {"RESERVED_16_63" , 16, 48, 550, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 551, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 551, "RO/WRSL", 0, 0, 144ull, 144ull},
- {"ISAE" , 0, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 552, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 552, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 552, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 552, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 552, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 552, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 552, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 552, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 552, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 552, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 552, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 552, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 552, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 552, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 552, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 552, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 552, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 552, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 553, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 553, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 553, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 553, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 554, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 554, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 554, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 554, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 554, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 555, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 555, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 555, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 555, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 555, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 556, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 556, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 557, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 558, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 559, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 559, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 559, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 559, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 560, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 560, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 561, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 562, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 563, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 563, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 563, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 564, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 564, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_8" , 0, 9, 565, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 9, 23, 565, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 566, "WORSL", 0, 0, 511ull, 511ull},
- {"CISP" , 0, 32, 567, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 568, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 568, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 569, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 569, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 570, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 570, "WORSL", 0, 0, 32767ull, 32767ull},
- {"CP" , 0, 8, 571, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 571, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 572, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 572, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 572, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 572, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 573, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 573, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 573, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 573, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 573, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 573, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 573, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 573, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 573, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 573, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 574, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 574, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 574, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 574, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 574, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 574, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 574, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 574, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 574, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 575, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 575, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 575, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 575, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 575, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 575, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 575, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 576, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 576, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 577, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 578, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 579, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 579, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 579, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 579, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 579, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 579, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 579, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 580, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 580, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 580, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 580, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 580, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 580, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 580, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 580, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 580, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 580, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 580, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 581, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 581, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 581, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 581, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 581, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 581, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 581, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 581, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 581, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 582, "RO/WRSL", 1, 1, 0, 0},
- {"MLW" , 4, 6, 582, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"ASLPMS" , 10, 2, 582, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 582, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 582, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 582, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 582, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 582, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 582, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 582, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 582, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 583, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 583, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 583, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 583, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 583, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 583, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 583, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 583, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 583, "RO", 0, 0, 0ull, 8ull},
- {"RESERVED_26_26" , 26, 1, 583, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 583, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 583, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 583, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 583, "RAZ", 1, 1, 0, 0},
- {"ABP" , 0, 1, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 584, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 585, "R/W", 0, 0, 0ull, 0ull},
- {"PIC" , 8, 2, 585, "R/W", 0, 0, 0ull, 0ull},
- {"PCC" , 10, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 585, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 585, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"EMIS" , 23, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 585, "RAZ", 1, 1, 0, 0},
- {"CTRS" , 0, 4, 586, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 586, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 586, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 587, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 587, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 587, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 588, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 588, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 588, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 588, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 589, "R/W", 1, 0, 0, 2ull},
- {"EC" , 4, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 589, "RO", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 589, "RO", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 589, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 589, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 589, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 589, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 589, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 590, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 591, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 592, "RO", 0, 0, 1ull, 0ull},
- {"CV" , 16, 4, 592, "RO", 0, 0, 1ull, 0ull},
- {"NCO" , 20, 12, 592, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 593, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 593, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 593, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 593, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 593, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 593, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 593, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 593, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 593, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 593, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 593, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 593, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 593, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 593, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 594, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 594, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 594, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 594, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 594, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 594, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 594, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 594, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 594, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 594, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 594, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 594, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 594, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 594, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 595, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 595, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 595, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 595, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 595, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 595, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 595, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 595, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 595, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 596, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 596, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 596, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 597, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 597, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 597, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 597, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 598, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 598, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 598, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 598, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 599, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 600, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 601, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 602, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 603, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 603, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 604, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 605, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 605, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 605, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 605, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 605, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 605, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 606, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 606, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 606, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 606, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 606, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 606, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 607, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 607, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 607, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 607, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 607, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 607, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 607, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 607, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 607, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 607, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_22_24" , 22, 3, 607, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 607, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 607, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 608, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 608, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 609, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 609, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 609, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 609, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 609, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 609, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 609, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 609, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 610, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 610, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 610, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 610, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 611, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 611, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 611, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 612, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 613, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 614, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 614, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 614, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 615, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 615, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 615, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 616, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 616, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 616, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 617, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 617, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 617, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 617, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 618, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 618, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 618, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 618, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 619, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 619, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 619, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 619, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 620, "RO/WRSL", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 620, "RO/WRSL", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 620, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 620, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 620, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 620, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 620, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 621, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"HEADER_CREDITS" , 12, 8, 621, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 621, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 621, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 621, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 622, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 622, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 622, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 622, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 622, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 623, "RO/WRSL", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 623, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 623, "RO/WRSL", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 623, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 624, "RO/WRSL", 0, 0, 136ull, 136ull},
- {"RESERVED_14_15" , 14, 2, 624, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 624, "RO/WRSL", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 624, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 625, "RO/WRSL", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 625, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 625, "RO/WRSL", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 625, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 626, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 626, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 626, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 626, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 626, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 626, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 626, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 627, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 628, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 629, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 629, "R/W", 0, 0, 144ull, 144ull},
- {"ISAE" , 0, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 630, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 630, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 630, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 630, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 630, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 630, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 630, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 630, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 630, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 630, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 630, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 630, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 631, "R/W", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 631, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 631, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 631, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 632, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 632, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 632, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 632, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 632, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 633, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 634, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 635, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 635, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 635, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 635, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 636, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 636, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 636, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 636, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 636, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 636, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 636, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 636, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 636, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 636, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 636, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 636, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 636, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 636, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 636, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 637, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 637, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 637, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 637, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 638, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 638, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 638, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 638, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 638, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 638, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 639, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 640, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 641, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 641, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 642, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 642, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 643, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 644, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 644, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 644, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 644, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 644, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 644, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 644, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 644, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 644, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 645, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 645, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 645, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 645, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 645, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 645, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 645, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 646, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 646, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 646, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 646, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 646, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 646, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 646, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 646, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 646, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 646, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 647, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 647, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 647, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 647, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 647, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 647, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 648, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 648, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 649, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 650, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 650, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 651, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 651, "R/W", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 651, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 651, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 651, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 651, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 651, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 652, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 652, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 652, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 652, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 652, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 652, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 652, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 652, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 652, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 652, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 653, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 653, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 653, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 653, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 653, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 653, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 653, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 653, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 653, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 653, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 653, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 653, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 653, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 654, "R/W", 1, 1, 0, 0},
- {"MLW" , 4, 6, 654, "R/W", 0, 0, 4ull, 4ull},
- {"ASLPMS" , 10, 2, 654, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 654, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 654, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 654, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 654, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 654, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 654, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_23" , 22, 2, 654, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 654, "R/W", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 655, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 655, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 655, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 655, "RO", 1, 1, 0, 0},
- {"NLW" , 20, 6, 655, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 655, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 655, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 655, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 655, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 656, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 656, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 656, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 657, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 657, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 657, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 657, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 657, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 657, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 657, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 657, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 657, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 657, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 657, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 657, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 657, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 658, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 658, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 658, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 658, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 659, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 659, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 659, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 660, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 660, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_5_31" , 5, 27, 660, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 661, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 661, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 662, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 662, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 662, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 662, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 663, "R/W", 1, 1, 0, 0},
- {"EC" , 4, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 663, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 663, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 663, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 663, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 664, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 665, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 666, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 666, "RO", 0, 0, 1ull, 1ull},
- {"NCO" , 20, 12, 666, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 667, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 667, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 667, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 668, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 668, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 668, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 668, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 668, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 669, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 669, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 669, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 669, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 669, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 669, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 670, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 670, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 670, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 670, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 671, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 671, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 671, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 671, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 672, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 672, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 672, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 672, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 673, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 674, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 675, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 676, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 677, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 678, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 678, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 678, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 678, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 678, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 678, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 678, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 678, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 678, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 679, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 679, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 680, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 680, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 681, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 682, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 682, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 682, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 682, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 682, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 683, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 683, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 683, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 683, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 683, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_30_31" , 30, 2, 683, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 684, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 684, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 684, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 684, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 684, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 684, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 684, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 684, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 684, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 684, "R/W", 0, 0, 15ull, 7ull},
- {"RESERVED_22_24" , 22, 3, 684, "RAZ", 1, 1, 0, 0},
- {"ECCRC" , 25, 1, 684, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_31" , 26, 6, 684, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 685, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 685, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 685, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 685, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 685, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 686, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 686, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 686, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 686, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 686, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 686, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 686, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 686, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 687, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 687, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 687, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 687, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 688, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 688, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 688, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 689, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 690, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 691, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 691, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 691, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 692, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 692, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 692, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 693, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 693, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 693, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 694, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 695, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 695, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 695, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 695, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 696, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 696, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 696, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 696, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 697, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 697, "R/W", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 697, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 697, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 697, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 697, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 697, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 698, "R/W", 0, 0, 32ull, 32ull},
- {"HEADER_CREDITS" , 12, 8, 698, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 698, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 698, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 698, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 699, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 699, "R/W", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 699, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 699, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 699, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 700, "R/W", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 700, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 700, "R/W", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 700, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 701, "R/W", 0, 0, 136ull, 136ull},
- {"RESERVED_14_15" , 14, 2, 701, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 701, "R/W", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 701, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 702, "R/W", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 702, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 702, "R/W", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 702, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 703, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 703, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 703, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 704, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 705, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 706, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 706, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 706, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 706, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 706, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 706, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 706, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 706, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 707, "RO", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 707, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 707, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 707, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 708, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 708, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 708, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 708, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 708, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 708, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 709, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 709, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 709, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 709, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 709, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 709, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 710, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 12, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 710, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 12, 1, 711, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 711, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 712, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 712, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 713, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 713, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 713, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 714, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 714, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 714, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 715, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 715, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 715, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 715, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 715, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 715, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 715, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 715, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 715, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 715, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 715, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 715, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 715, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 716, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 716, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 716, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 716, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 716, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 716, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 716, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 717, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 717, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 717, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 717, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 717, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 717, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 717, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 718, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 718, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 718, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 719, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 719, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 719, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 719, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 719, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 719, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 719, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 719, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 720, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 720, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 720, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 720, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 720, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 720, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 720, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 721, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 721, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 721, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 721, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 722, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 722, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 722, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 722, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 722, "RAZ", 1, 1, 0, 0},
- {"L0SYNC" , 0, 1, 723, "RO", 0, 0, 0ull, 1ull},
- {"L1SYNC" , 1, 1, 723, "RO", 0, 0, 0ull, 1ull},
- {"L2SYNC" , 2, 1, 723, "RO", 0, 0, 0ull, 1ull},
- {"L3SYNC" , 3, 1, 723, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_4_10" , 4, 7, 723, "RAZ", 1, 1, 0, 0},
- {"PATTST" , 11, 1, 723, "RO", 0, 0, 0ull, 0ull},
- {"ALIGND" , 12, 1, 723, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_63" , 13, 51, 723, "RAZ", 1, 1, 0, 0},
- {"BIST_STATUS" , 0, 1, 724, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 724, "RAZ", 1, 1, 0, 0},
- {"BITLCK0" , 0, 1, 725, "RO", 0, 1, 0ull, 0},
- {"BITLCK1" , 1, 1, 725, "RO", 0, 1, 0ull, 0},
- {"BITLCK2" , 2, 1, 725, "RO", 0, 1, 0ull, 0},
- {"BITLCK3" , 3, 1, 725, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 725, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 726, "RAZ", 1, 1, 0, 0},
- {"SPD" , 2, 4, 726, "RO", 0, 0, 0ull, 0ull},
- {"SPDSEL0" , 6, 1, 726, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_10" , 7, 4, 726, "RAZ", 1, 1, 0, 0},
- {"LO_PWR" , 11, 1, 726, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 726, "RAZ", 1, 1, 0, 0},
- {"SPDSEL1" , 13, 1, 726, "RO", 0, 0, 1ull, 1ull},
- {"LOOPBCK1" , 14, 1, 726, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 726, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 726, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 727, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 727, "RAZ", 1, 1, 0, 0},
- {"TXFLT_EN" , 0, 1, 728, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 1, 1, 728, "R/W", 0, 0, 0ull, 1ull},
- {"RXSYNBAD_EN" , 2, 1, 728, "R/W", 0, 0, 0ull, 1ull},
- {"BITLCKLS_EN" , 3, 1, 728, "R/W", 0, 0, 0ull, 1ull},
- {"SYNLOS_EN" , 4, 1, 728, "R/W", 0, 0, 0ull, 1ull},
- {"ALGNLOS_EN" , 5, 1, 728, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 6, 1, 728, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 728, "RAZ", 1, 1, 0, 0},
- {"TXFLT" , 0, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 1, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXSYNBAD" , 2, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"BITLCKLS" , 3, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNLOS" , 4, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALGNLOS" , 5, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 6, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 729, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 730, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 730, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 730, "R/W1C", 0, 0, 0ull, 0ull},
- {"DROP_LN" , 4, 2, 730, "R/W", 0, 0, 0ull, 0ull},
- {"ENC_MODE" , 6, 1, 730, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 730, "RAZ", 1, 1, 0, 0},
- {"GMXENO" , 0, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"XAUI" , 1, 1, 731, "RO", 1, 1, 0, 0},
- {"RX_SWAP" , 2, 1, 731, "R/W", 0, 1, 0ull, 0},
- {"TX_SWAP" , 3, 1, 731, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 731, "RAZ", 1, 1, 0, 0},
- {"SYNC0ST" , 0, 4, 732, "RO", 0, 1, 0ull, 0},
- {"SYNC1ST" , 4, 4, 732, "RO", 0, 1, 0ull, 0},
- {"SYNC2ST" , 8, 4, 732, "RO", 0, 1, 0ull, 0},
- {"SYNC3ST" , 12, 4, 732, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 732, "RAZ", 1, 1, 0, 0},
- {"TENGB" , 0, 1, 733, "RO", 0, 0, 1ull, 1ull},
- {"TENPASST" , 1, 1, 733, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 733, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 734, "RAZ", 1, 1, 0, 0},
- {"LPABLE" , 1, 1, 734, "RO", 0, 0, 1ull, 1ull},
- {"RCV_LNK" , 2, 1, 734, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_3_6" , 3, 4, 734, "RAZ", 1, 1, 0, 0},
- {"FLT" , 7, 1, 734, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 734, "RAZ", 1, 1, 0, 0},
- {"TENGB_R" , 0, 1, 735, "RO", 0, 0, 0ull, 0ull},
- {"TENGB_X" , 1, 1, 735, "RO", 0, 0, 1ull, 1ull},
- {"TENGB_W" , 2, 1, 735, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_9" , 3, 7, 735, "RAZ", 1, 1, 0, 0},
- {"RCVFLT" , 10, 1, 735, "RC", 0, 0, 0ull, 0ull},
- {"XMTFLT" , 11, 1, 735, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 735, "RAZ", 1, 1, 0, 0},
- {"DEV" , 14, 2, 735, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_16_63" , 16, 48, 735, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 736, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_TXPLRT" , 2, 4, 736, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_RXPLRT" , 6, 4, 736, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 736, "RAZ", 1, 1, 0, 0},
- {"TX_ST" , 0, 3, 737, "RO", 0, 1, 0ull, 0},
- {"RX_ST" , 3, 2, 737, "RO", 0, 1, 0ull, 0},
- {"ALGN_ST" , 5, 3, 737, "RO", 0, 1, 0ull, 0},
- {"RXBAD" , 8, 1, 737, "RO", 0, 0, 0ull, 0ull},
- {"SYN0BAD" , 9, 1, 737, "RO", 0, 0, 0ull, 0ull},
- {"SYN1BAD" , 10, 1, 737, "RO", 0, 0, 0ull, 0ull},
- {"SYN2BAD" , 11, 1, 737, "RO", 0, 0, 0ull, 0ull},
- {"SYN3BAD" , 12, 1, 737, "RO", 0, 0, 0ull, 0ull},
- {"TERM_ERR" , 13, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 737, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 738, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 738, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 738, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 16, 738, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 738, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 739, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 739, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 739, "R/W", 0, 0, 0ull, 1ull},
- {"BAR1_SIZ" , 4, 3, 739, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_7_63" , 7, 57, 739, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 3, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 4, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 5, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 6, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 7, 1, 740, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 740, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 741, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 741, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 741, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 741, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 741, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 741, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 6, 1, 741, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 7, 1, 741, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 8, 1, 741, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 9, 1, 741, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 741, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 742, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 742, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 743, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 743, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 744, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 744, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"FAST_LM" , 2, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 745, "R/W", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 745, "RAZ", 0, 0, 0ull, 0ull},
- {"CFG_RTRY" , 16, 16, 745, "R/W", 0, 0, 0ull, 32ull},
- {"RESERVED_32_33" , 32, 2, 745, "RAZ", 1, 1, 0, 0},
- {"PBUS" , 34, 8, 745, "RO", 1, 1, 0, 0},
- {"DNUM" , 42, 5, 745, "RO", 1, 1, 0, 0},
- {"AUTO_SD" , 47, 1, 745, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 745, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 746, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 746, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 747, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 748, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 748, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 748, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 748, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 748, "RO", 1, 1, 0, 0},
- {"AERI" , 0, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 749, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 749, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 750, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 750, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 751, "RO", 0, 0, 0ull, 0ull},
- {"SE" , 1, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"PMEI" , 2, 1, 751, "RO", 0, 0, 0ull, 0ull},
- {"PMEM" , 3, 1, 751, "RO", 0, 0, 0ull, 0ull},
- {"UP_B1" , 4, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_B2" , 5, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_BX" , 6, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B1" , 7, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B2" , 8, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_BX" , 9, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"EXC" , 10, 1, 751, "RO", 0, 0, 0ull, 0ull},
- {"RDLK" , 11, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_ER" , 12, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_DR" , 13, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 751, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 752, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 752, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 753, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 753, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_40" , 0, 41, 754, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 41, 23, 754, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 755, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 755, "R/W", 0, 1, 4503599627370495ull, 0},
- {"RESERVED_0_11" , 0, 12, 756, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 756, "R/W", 0, 1, 4503599627370495ull, 0},
- {"SLI_P" , 0, 8, 757, "R/W", 0, 0, 128ull, 128ull},
- {"SLI_NP" , 8, 8, 757, "R/W", 0, 0, 16ull, 16ull},
- {"SLI_CPL" , 16, 8, 757, "R/W", 0, 0, 128ull, 128ull},
- {"PEM_P" , 24, 8, 757, "R/W", 0, 0, 128ull, 128ull},
- {"PEM_NP" , 32, 8, 757, "R/W", 0, 0, 16ull, 16ull},
- {"PEM_CPL" , 40, 8, 757, "R/W", 0, 0, 128ull, 128ull},
- {"PEAI_PPF" , 48, 8, 757, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_56_63" , 56, 8, 757, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 758, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 758, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 758, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 758, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 758, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 18, 759, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 759, "RAZ", 1, 1, 0, 0},
- {"CLKEN" , 0, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 760, "RAZ", 0, 1, 0ull, 0},
- {"DPRT" , 0, 16, 761, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 761, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 761, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 761, "RAZ", 1, 1, 0, 0},
- {"MAP0" , 0, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 762, "R/W", 0, 0, 0ull, 0ull},
- {"MAP0" , 0, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MINLEN" , 0, 16, 764, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 764, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 764, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 765, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 765, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 765, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 765, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 765, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 765, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 766, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 766, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 766, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 20, 1, 766, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_23" , 21, 3, 766, "RAZ", 1, 1, 0, 0},
- {"DSA_GRP_SID" , 24, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SCMD" , 25, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_TVID" , 26, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"IHMSK_DIS" , 27, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 766, "RAZ", 1, 1, 0, 0},
- {"PRI" , 0, 6, 767, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 767, "RAZ", 1, 1, 0, 0},
- {"QOS" , 8, 3, 767, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 767, "RAZ", 1, 1, 0, 0},
- {"UP_QOS" , 12, 1, 767, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_13_63" , 13, 51, 767, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 768, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 768, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 769, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 769, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 770, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 770, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 771, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 771, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 771, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_EN" , 10, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"HIGIG_EN" , 11, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"CRC_EN" , 12, 1, 771, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 771, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VSEL" , 19, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 771, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 771, "R/W", 0, 0, 0ull, 0ull},
- {"HG_QOS" , 27, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT" , 28, 4, 771, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 771, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 771, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 771, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 771, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 771, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 771, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 771, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_63" , 53, 11, 771, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 772, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 772, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 772, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 772, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 772, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 772, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 772, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 772, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 773, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 773, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 774, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 774, "RAZ", 1, 1, 0, 0},
- {"QOS1" , 4, 3, 774, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 774, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 775, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 775, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 775, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 775, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 775, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 775, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 775, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 775, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 775, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 776, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 776, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 777, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 777, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 778, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 778, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 779, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 779, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 780, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 780, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 781, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 781, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 782, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 782, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 783, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 783, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 784, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 784, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 785, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 785, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 786, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 786, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 787, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 787, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 788, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 788, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 789, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 789, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 790, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 790, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 791, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 791, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 792, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 792, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 793, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 793, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 794, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 794, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 795, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 795, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 796, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 796, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 796, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 797, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 797, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 797, "RO", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 798, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 798, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 799, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 799, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 800, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 800, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 801, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 801, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 802, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 802, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 803, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 803, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 804, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 804, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 805, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 805, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 806, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 806, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 807, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 807, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 808, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 808, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 809, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 809, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 32, 810, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 810, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 811, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 811, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 812, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 812, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 812, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 812, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 813, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 813, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 813, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 813, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 813, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 814, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 814, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 814, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 814, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 815, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 815, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 815, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 815, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 815, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 815, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 815, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 815, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 816, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 816, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 816, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 816, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 817, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 817, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 817, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 817, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 817, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 818, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 819, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 819, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 819, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 819, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 819, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 820, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 821, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 821, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 821, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 821, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 821, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 821, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 821, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 821, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 821, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 821, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 821, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 821, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 821, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 822, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 822, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 822, "RO", 1, 0, 0, 0ull},
- {"MAJOR_3" , 54, 1, 822, "RO", 1, 0, 0, 0ull},
- {"PTP" , 55, 1, 822, "RO", 1, 0, 0, 0ull},
- {"RESERVED_56_63" , 56, 8, 822, "RAZ", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 823, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 823, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 823, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 823, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 823, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 823, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 823, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 823, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 823, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 823, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 823, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 823, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 823, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 824, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 824, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 824, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 824, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 824, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 824, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 825, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 825, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 825, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 825, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 6, 1, 825, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 825, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 825, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 825, "RO", 1, 0, 0, 0ull},
- {"RESERVED_29_63" , 29, 35, 825, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 826, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 826, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 826, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 826, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 827, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 827, "R/W", 1, 0, 0, 0ull},
- {"BP_PORT" , 10, 6, 827, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_52" , 16, 37, 827, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 827, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 61, 1, 827, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_62_63" , 62, 2, 827, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 828, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 828, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_10_52" , 10, 43, 828, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 828, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 828, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 829, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 829, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 829, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 829, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 829, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 830, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 830, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 830, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 830, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 831, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 831, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 831, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 831, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 831, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 831, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 831, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 831, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 831, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 832, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 832, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 832, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 832, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 832, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 833, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 833, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 833, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 833, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 833, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 833, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 8, 833, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 833, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 833, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 833, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 833, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 3, 833, "RO", 1, 0, 0, 0ull},
- {"OUT_DAT" , 32, 1, 833, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 833, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 833, "RO", 1, 0, 0, 0ull},
- {"RESERVED_35_63" , 35, 29, 833, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 834, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 834, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 834, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 834, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 835, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 836, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 837, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 838, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 839, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE1" , 4, 4, 839, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE2" , 8, 4, 839, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE3" , 12, 4, 839, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE4" , 16, 4, 839, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE5" , 20, 4, 839, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE6" , 24, 4, 839, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE7" , 28, 4, 839, "R/W", 0, 0, 0ull, 0ull},
- {"ENGINE8" , 32, 4, 839, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE9" , 36, 4, 839, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE10" , 40, 4, 839, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE11" , 44, 4, 839, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_48_63" , 48, 16, 839, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 12, 840, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 840, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 841, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 842, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 842, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 843, "R/W", 0, 0, 2ull, 2ull},
- {"MODE1" , 3, 3, 843, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 843, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 844, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 844, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 844, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 844, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 16, 845, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 845, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 846, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 846, "RAZ", 1, 1, 0, 0},
- {"PREEMPTER" , 0, 1, 847, "R/W", 0, 0, 0ull, 0ull},
- {"PREEMPTEE" , 1, 1, 847, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 847, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 848, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 848, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 848, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 849, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 849, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 849, "RAZ", 1, 1, 0, 0},
- {"WQE_WORD" , 0, 4, 850, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_4_63" , 4, 60, 850, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 1, 851, "RO", 0, 0, 0ull, 0ull},
- {"PEND" , 1, 1, 851, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 2, 1, 851, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 3, 1, 851, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 4, 4, 851, "RO", 0, 0, 0ull, 0ull},
- {"NBR" , 8, 3, 851, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 11, 1, 851, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 851, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 6, 851, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 851, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 852, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 852, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 853, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 853, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 853, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 853, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 853, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 853, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 853, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 853, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 853, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 853, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 854, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 854, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 854, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 855, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 855, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 856, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 856, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 857, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 857, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 858, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 858, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 859, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 859, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 11, 860, "RO", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 860, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 861, "R/W", 0, 0, 0ull, 1023ull},
- {"RESERVED_10_63" , 10, 54, 861, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 862, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 862, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 863, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 863, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 863, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 863, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 863, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 863, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 863, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 863, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 863, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 863, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 864, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 864, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 864, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 864, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 864, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 10, 865, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_11" , 10, 2, 865, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 10, 865, "R/W", 0, 1, 1023ull, 0},
- {"RESERVED_22_23" , 22, 2, 865, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 11, 865, "RO", 0, 1, 1011ull, 0},
- {"RESERVED_35_35" , 35, 1, 865, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 36, 11, 865, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_47" , 47, 1, 865, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 48, 11, 865, "RO", 0, 1, 0ull, 0},
- {"RESERVED_59_63" , 59, 5, 865, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 866, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 866, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 867, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 867, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 868, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 868, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 869, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 869, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 869, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 11, 870, "RO", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 870, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 12, 11, 870, "RO", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 870, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 24, 4, 870, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 870, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 871, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 871, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 871, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 871, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 871, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 10, 872, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_11" , 10, 2, 872, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 10, 872, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_23" , 22, 2, 872, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 872, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 872, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 872, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 873, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 873, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 874, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 875, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 876, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 877, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 877, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 877, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 877, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 877, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 878, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 878, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 878, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 878, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 878, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 879, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 879, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 879, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 879, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 880, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 880, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 880, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 880, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 880, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 880, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 880, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 880, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 880, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 880, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 881, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 882, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 882, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 882, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 883, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 883, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 883, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 883, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 883, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 883, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 883, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 884, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 884, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 885, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 886, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 887, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 888, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 888, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 888, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 888, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 888, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 888, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 888, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 888, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 888, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 888, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 888, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 888, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 888, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 888, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 888, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 888, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 888, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 888, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 889, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 889, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 889, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 890, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 890, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 891, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 891, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 891, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 892, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 892, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 892, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 892, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 892, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 892, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 892, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 893, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 894, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 895, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 895, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 896, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 896, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 896, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 897, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 897, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 897, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 898, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 898, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 898, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 898, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 898, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 898, "R/W", 0, 0, 0ull, 0ull},
- {"EER_VAL" , 9, 1, 898, "RO", 0, 0, 0ull, 0ull},
- {"EER_LCK" , 10, 1, 898, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 898, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 899, "RO", 1, 1, 0, 0},
- {"KEY" , 0, 64, 900, "WO", 0, 0, 0ull, 0ull},
- {"DAT" , 0, 64, 901, "RO", 1, 1, 0, 0},
- {"NCB_CMD" , 0, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_0" , 2, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_1" , 3, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_0" , 4, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_1" , 5, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 902, "RAZ", 1, 1, 0, 0},
- {"P2N1_P1" , 9, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_24" , 19, 6, 902, "RAZ", 1, 1, 0, 0},
- {"CPL_P1" , 25, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_O" , 27, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_C" , 28, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_O" , 29, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 902, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_4" , 1, 4, 903, "R/W", 0, 0, 0ull, 0ull},
- {"PTLP_RO" , 5, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 903, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 903, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 903, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 903, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 903, "R/W", 0, 0, 3ull, 3ull},
- {"WAITL_COM" , 16, 1, 903, "R/W", 0, 1, 0ull, 0},
- {"DIS_PORT" , 17, 1, 903, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTA" , 18, 1, 903, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 19, 1, 903, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 20, 1, 903, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 21, 1, 903, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 903, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 904, "RO", 1, 1, 0, 0},
- {"P0_NTAGS" , 8, 6, 904, "R/W", 0, 0, 32ull, 32ull},
- {"P1_NTAGS" , 14, 6, 904, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_63" , 20, 44, 904, "RAZ", 1, 1, 0, 0},
- {"P0_FCNT" , 0, 6, 905, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 905, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 905, "RO", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 905, "RO", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 905, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 906, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 906, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 906, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 32, 907, "R/W", 0, 1, 0ull, 0},
- {"ADBG_SEL" , 32, 1, 907, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 907, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 908, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 908, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 909, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 909, "R/W", 0, 1, 0ull, 0},
- {"TIM" , 0, 32, 910, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 910, "RAZ", 1, 1, 0, 0},
- {"RML_TO" , 0, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 911, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 911, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 911, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 911, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 912, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT1" , 17, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"MAC0_INT" , 18, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"MAC1_INT" , 19, 1, 912, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_31" , 20, 12, 912, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 912, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 912, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 912, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 912, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 912, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 912, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 912, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT" , 4, 1, 913, "RO", 0, 0, 0ull, 0ull},
- {"PTIME" , 5, 1, 913, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_WI" , 9, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_B0" , 10, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_WI" , 11, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_B0" , 12, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_WI" , 13, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_B0" , 14, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_WI" , 15, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO_INT0" , 16, 1, 913, "RO", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 913, "RO", 0, 0, 0ull, 0ull},
- {"MAC0_INT" , 18, 1, 913, "RO", 0, 0, 0ull, 0ull},
- {"MAC1_INT" , 19, 1, 913, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 913, "RAZ", 1, 1, 0, 0},
- {"DMAFI" , 32, 2, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 913, "RO", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 913, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 913, "RAZ", 1, 1, 0, 0},
- {"PIDBOF" , 48, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 913, "RAZ", 1, 1, 0, 0},
- {"ILL_PAD" , 60, 1, 913, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 913, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 914, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 915, "RO", 0, 1, 0ull, 0},
- {"P0_PCNT" , 0, 8, 916, "R/W", 0, 0, 128ull, 128ull},
- {"P0_NCNT" , 8, 8, 916, "R/W", 0, 0, 16ull, 16ull},
- {"P0_CCNT" , 16, 8, 916, "R/W", 0, 0, 128ull, 128ull},
- {"P1_PCNT" , 24, 8, 916, "R/W", 0, 0, 128ull, 128ull},
- {"P1_NCNT" , 32, 8, 916, "R/W", 0, 0, 16ull, 16ull},
- {"P1_CCNT" , 40, 8, 916, "R/W", 0, 0, 128ull, 128ull},
- {"P0_P_D" , 48, 1, 916, "R/W", 0, 0, 1ull, 1ull},
- {"P0_N_D" , 49, 1, 916, "R/W", 0, 0, 1ull, 1ull},
- {"P0_C_D" , 50, 1, 916, "R/W", 0, 0, 1ull, 1ull},
- {"P1_P_D" , 51, 1, 916, "R/W", 0, 0, 1ull, 1ull},
- {"P1_N_D" , 52, 1, 916, "R/W", 0, 0, 1ull, 1ull},
- {"P1_C_D" , 53, 1, 916, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_54_63" , 54, 10, 916, "RAZ", 1, 1, 0, 0},
- {"NUM" , 0, 8, 917, "RO", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 917, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 918, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 918, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 918, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 30, 919, "R/W", 0, 1, 0ull, 0},
- {"RTYPE" , 30, 2, 919, "R/W", 0, 1, 0ull, 0},
- {"WTYPE" , 32, 2, 919, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 919, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 919, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 919, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 3, 919, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 42, 1, 919, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 919, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 920, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 921, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 922, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 923, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 924, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 925, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 926, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 927, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 928, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 928, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 928, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 64, 929, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 930, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 931, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 932, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 933, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 934, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 935, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 936, "R/W", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 937, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 937, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 937, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 938, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 938, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 939, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 939, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 939, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 940, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 940, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 940, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 941, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 941, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 941, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 942, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 32, 22, 942, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 942, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 32, 943, "R/W", 0, 0, 0ull, 0ull},
- {"WMARK" , 32, 32, 943, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_0_2" , 0, 3, 944, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 944, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 945, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 945, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 946, "R/W", 0, 1, 0ull, 0},
- {"FCNT" , 32, 5, 946, "RO", 0, 1, 0ull, 0},
- {"WRP" , 37, 9, 946, "RO", 0, 1, 0ull, 0},
- {"RRP" , 46, 9, 946, "RO", 0, 1, 0ull, 0},
- {"MAX" , 55, 9, 946, "RO", 0, 1, 16ull, 0},
- {"NTAG" , 0, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"NTT" , 1, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"NGRP" , 2, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"NQOS" , 3, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_5" , 4, 2, 947, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 947, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_13" , 13, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 947, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_20" , 16, 5, 947, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"RNTAG" , 22, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"RNTT" , 23, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"RNGRP" , 24, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"RNQOS" , 25, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_27" , 26, 2, 947, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 947, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_35" , 35, 1, 947, "RAZ", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 947, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_42" , 38, 5, 947, "RAZ", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 947, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 947, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 948, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 16, 7, 948, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 948, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 949, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 4, 60, 949, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 950, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 950, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 951, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 951, "RO", 0, 1, 0ull, 0},
- {"PORT" , 0, 32, 952, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 952, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 953, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 953, "RAZ", 1, 1, 0, 0},
- {"PKT_BP" , 0, 4, 954, "R/W", 0, 0, 15ull, 15ull},
- {"RING_EN" , 4, 1, 954, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 954, "RAZ", 1, 1, 0, 0},
- {"ES" , 0, 64, 955, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 956, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 956, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 957, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 957, "RAZ", 1, 1, 0, 0},
- {"DPTR" , 0, 32, 958, "R/W", 0, 0, 0ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 958, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 32, 959, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 959, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 960, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 960, "RO", 0, 1, 0ull, 0},
- {"RD_CNT" , 0, 32, 961, "RO", 0, 1, 0ull, 0},
- {"WR_CNT" , 32, 32, 961, "RO", 0, 1, 0ull, 0},
- {"PP" , 0, 64, 962, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 0, 1, 963, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 963, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 963, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 963, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 963, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 963, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 963, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 963, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 22, 1, 963, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_23_63" , 23, 41, 963, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 964, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 964, "RAZ", 1, 1, 0, 0},
- {"RDSIZE" , 0, 64, 965, "R/W", 0, 1, 0ull, 0},
- {"IS_64B" , 0, 32, 966, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 966, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 967, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 22, 967, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_63" , 54, 10, 967, "RAZ", 1, 1, 0, 0},
- {"IPTR" , 0, 32, 968, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 968, "RAZ", 1, 1, 0, 0},
- {"BMODE" , 0, 32, 969, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 969, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 970, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 970, "RAZ", 1, 1, 0, 0},
- {"WMARK" , 0, 32, 971, "R/W", 0, 0, 0ull, 14ull},
- {"RESERVED_32_63" , 32, 32, 971, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 64, 972, "R/W", 0, 1, 0ull, 0},
- {"OUT_RST" , 0, 32, 973, "RO", 0, 1, 0ull, 0},
- {"IN_RST" , 32, 32, 973, "RO", 0, 1, 0ull, 0},
- {"ES" , 0, 64, 974, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 975, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 975, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 976, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 976, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 977, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 977, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 978, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 978, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 3, 979, "R/W", 0, 0, 2ull, 2ull},
- {"BAR0_D" , 3, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"WIND_D" , 4, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 979, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 980, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 981, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 982, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 982, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 982, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 982, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 983, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 983, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 983, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 983, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 983, "RO", 0, 1, 1ull, 0},
- {"RESERVED_47_47" , 47, 1, 983, "RAZ", 1, 1, 0, 0},
- {"NNP1" , 48, 8, 983, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 983, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 984, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 984, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 984, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 984, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 984, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 985, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 985, "R/W", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 985, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_51_63" , 51, 13, 985, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 986, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 987, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 987, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 987, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 987, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 988, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 989, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 989, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 990, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 990, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 991, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 991, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 991, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 991, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 991, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 991, "R/W", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 991, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 991, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 991, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 991, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 992, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 992, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 992, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 992, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 992, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 992, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 993, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 993, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 994, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 994, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 994, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 994, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 995, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 995, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 995, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 995, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 996, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_6_7" , 6, 2, 996, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 6, 996, "R/W", 0, 0, 19ull, 19ull},
- {"RESERVED_14_63" , 14, 50, 996, "RAZ", 1, 1, 0, 0},
- {"DENY_BAR0" , 0, 1, 997, "R/W", 0, 0, 0ull, 0ull},
- {"DENY_BAR1" , 1, 1, 997, "R/W", 0, 0, 0ull, 0ull},
- {"DENY_BAR2" , 2, 1, 997, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 997, "RAZ", 1, 1, 0, 0},
- {"ASSY_VEN" , 0, 16, 998, "R/W", 0, 0, 140ull, 0ull},
- {"ASSY_ID" , 16, 16, 998, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 998, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 999, "RAZ", 1, 1, 0, 0},
- {"ASSY_REV" , 16, 16, 999, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 999, "RAZ", 1, 1, 0, 0},
- {"RP0_PID" , 0, 2, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_PID" , 2, 1, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"RP0_SID" , 3, 2, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_SID" , 5, 1, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1000, "RAZ", 1, 1, 0, 0},
- {"OMSG" , 0, 7, 1001, "RO", 0, 0, 0ull, 0ull},
- {"IMSG" , 7, 5, 1001, "RO", 0, 0, 0ull, 0ull},
- {"RXBUF" , 12, 2, 1001, "RO", 0, 0, 0ull, 0ull},
- {"TXBUF" , 14, 2, 1001, "RO", 0, 0, 0ull, 0ull},
- {"OSPF" , 16, 1, 1001, "RO", 0, 0, 0ull, 0ull},
- {"ISPF" , 17, 1, 1001, "RO", 0, 0, 0ull, 0ull},
- {"OARB" , 18, 2, 1001, "RO", 0, 0, 0ull, 0ull},
- {"RXBUF2" , 20, 2, 1001, "RO", 0, 0, 0ull, 0ull},
- {"OARB2" , 22, 2, 1001, "RO", 0, 0, 0ull, 0ull},
- {"OPTRS" , 24, 4, 1001, "RO", 0, 0, 0ull, 0ull},
- {"OBULK" , 28, 4, 1001, "RO", 0, 0, 0ull, 0ull},
- {"RTN" , 32, 2, 1001, "RO", 0, 0, 0ull, 0ull},
- {"OFREE" , 34, 1, 1001, "RO", 0, 0, 0ull, 0ull},
- {"ITAG" , 35, 1, 1001, "RO", 0, 0, 0ull, 0ull},
- {"OTAG" , 36, 2, 1001, "RO", 0, 0, 0ull, 0ull},
- {"BELL" , 38, 2, 1001, "RO", 0, 0, 0ull, 0ull},
- {"CRAM" , 40, 2, 1001, "RO", 0, 0, 0ull, 0ull},
- {"MRAM" , 42, 2, 1001, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_44_63" , 44, 20, 1001, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 1002, "R/W", 0, 1, 0ull, 0},
- {"PRIO" , 4, 4, 1002, "R/W", 0, 1, 0ull, 0},
- {"LTTR" , 8, 4, 1002, "R/W", 0, 1, 0ull, 0},
- {"PRT_SEL" , 12, 3, 1002, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 1002, "RAZ", 1, 1, 0, 0},
- {"RP0_PID" , 16, 2, 1002, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_PID" , 18, 1, 1002, "R/W", 0, 0, 0ull, 0ull},
- {"RP0_SID" , 19, 2, 1002, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_SID" , 21, 1, 1002, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1002, "RAZ", 1, 1, 0, 0},
- {"RSP_THR" , 24, 6, 1002, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 1002, "RAZ", 1, 1, 0, 0},
- {"TO_MODE" , 31, 1, 1002, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1002, "RAZ", 1, 1, 0, 0},
- {"TAG" , 0, 32, 1003, "R/W", 0, 1, 0ull, 0},
- {"TT" , 32, 2, 1003, "R/W", 0, 1, 0ull, 0},
- {"RS" , 34, 1, 1003, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_41" , 35, 7, 1003, "RAZ", 1, 1, 0, 0},
- {"NTAG" , 42, 1, 1003, "R/W", 0, 1, 0ull, 0},
- {"NTT" , 43, 1, 1003, "R/W", 0, 1, 0ull, 0},
- {"NGRP" , 44, 1, 1003, "R/W", 0, 1, 0ull, 0},
- {"NQOS" , 45, 1, 1003, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_47" , 46, 2, 1003, "RAZ", 1, 1, 0, 0},
- {"SL" , 48, 7, 1003, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_55_55" , 55, 1, 1003, "RAZ", 1, 1, 0, 0},
- {"PM" , 56, 2, 1003, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_62" , 58, 5, 1003, "RAZ", 1, 1, 0, 0},
- {"R" , 63, 1, 1003, "R/W", 0, 1, 0ull, 0},
- {"GRP0" , 0, 4, 1004, "R/W", 0, 1, 0ull, 0},
- {"QOS0" , 4, 3, 1004, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 1004, "RAZ", 1, 1, 0, 0},
- {"GRP1" , 8, 4, 1004, "R/W", 0, 1, 0ull, 0},
- {"QOS1" , 12, 3, 1004, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 1004, "RAZ", 1, 1, 0, 0},
- {"GRP2" , 16, 4, 1004, "R/W", 0, 1, 0ull, 0},
- {"QOS2" , 20, 3, 1004, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 1004, "RAZ", 1, 1, 0, 0},
- {"GRP3" , 24, 4, 1004, "R/W", 0, 1, 0ull, 0},
- {"QOS3" , 28, 3, 1004, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_31_31" , 31, 1, 1004, "RAZ", 1, 1, 0, 0},
- {"GRP4" , 32, 4, 1004, "R/W", 0, 1, 0ull, 0},
- {"QOS4" , 36, 3, 1004, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_39_39" , 39, 1, 1004, "RAZ", 1, 1, 0, 0},
- {"GRP5" , 40, 4, 1004, "R/W", 0, 1, 0ull, 0},
- {"QOS5" , 44, 3, 1004, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_47_47" , 47, 1, 1004, "RAZ", 1, 1, 0, 0},
- {"GRP6" , 48, 4, 1004, "R/W", 0, 1, 0ull, 0},
- {"QOS6" , 52, 3, 1004, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_55_55" , 55, 1, 1004, "RAZ", 1, 1, 0, 0},
- {"GRP7" , 56, 4, 1004, "R/W", 0, 1, 0ull, 0},
- {"QOS7" , 60, 3, 1004, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_63_63" , 63, 1, 1004, "RAZ", 1, 1, 0, 0},
- {"SID0" , 0, 16, 1005, "RO", 0, 1, 0ull, 0},
- {"LTTR0" , 16, 2, 1005, "RO", 0, 1, 0ull, 0},
- {"MBOX0" , 18, 2, 1005, "RO", 0, 1, 0ull, 0},
- {"SEG0" , 20, 4, 1005, "RO", 0, 1, 0ull, 0},
- {"DIS0" , 24, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"TT0" , 25, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_26" , 26, 1, 1005, "RAZ", 1, 1, 0, 0},
- {"PRT0" , 27, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"TOC0" , 28, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"TOE0" , 29, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"ERR0" , 30, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"VAL0" , 31, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"SID1" , 32, 16, 1005, "RO", 0, 1, 0ull, 0},
- {"LTTR1" , 48, 2, 1005, "RO", 0, 1, 0ull, 0},
- {"MBOX1" , 50, 2, 1005, "RO", 0, 1, 0ull, 0},
- {"SEG1" , 52, 4, 1005, "RO", 0, 1, 0ull, 0},
- {"DIS1" , 56, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"TT1" , 57, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_58" , 58, 1, 1005, "RAZ", 1, 1, 0, 0},
- {"PRT1" , 59, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"TOC1" , 60, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"TOE1" , 61, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"ERR1" , 62, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"VAL1" , 63, 1, 1005, "RO", 0, 1, 0ull, 0},
- {"MAX_P0" , 0, 6, 1006, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_6_7" , 6, 2, 1006, "RAZ", 1, 1, 0, 0},
- {"MAX_P1" , 8, 6, 1006, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_14_15" , 14, 2, 1006, "RAZ", 1, 1, 0, 0},
- {"BUF_THR" , 16, 4, 1006, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_30" , 20, 11, 1006, "RAZ", 1, 1, 0, 0},
- {"SP_VPORT" , 31, 1, 1006, "R/W", 0, 0, 1ull, 1ull},
- {"MAX_S0" , 32, 6, 1006, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_38_39" , 38, 2, 1006, "RAZ", 1, 1, 0, 0},
- {"MAX_S1" , 40, 6, 1006, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_46_47" , 46, 2, 1006, "RAZ", 1, 1, 0, 0},
- {"MAX_TOT" , 48, 6, 1006, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_54_63" , 54, 10, 1006, "RAZ", 1, 1, 0, 0},
- {"PKO_RST" , 0, 1, 1007, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1007, "RAZ", 1, 1, 0, 0},
- {"PKO_RST" , 0, 1, 1008, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_30" , 1, 30, 1008, "RAZ", 1, 1, 0, 0},
- {"INT_SUM" , 31, 1, 1008, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1008, "RAZ", 1, 1, 0, 0},
- {"TXBELL" , 0, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"BELL_ERR" , 1, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"RXBELL" , 2, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"MAINT_OP" , 3, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"BAR_ERR" , 4, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"DENY_WR" , 5, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"SLI_ERR" , 6, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"WR_DONE" , 7, 1, 1009, "R/W", 0, 0, 0ull, 0ull},
- {"MCE_TX" , 8, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"MCE_RX" , 9, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"SOFT_TX" , 10, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"SOFT_RX" , 11, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"LOG_ERB" , 12, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"PHY_ERB" , 13, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"LINK_DWN" , 14, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"LINK_UP" , 15, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"OMSG0" , 16, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"OMSG1" , 17, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"OMSG_ERR" , 18, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"PKO_ERR" , 19, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"RTRY_ERR" , 20, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"F_ERROR" , 21, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"MAC_BUF" , 22, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"DEGRADE" , 23, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"FAIL" , 24, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"TTL_TOUT" , 25, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"ZERO_PKT" , 26, 1, 1009, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_63" , 27, 37, 1009, "RAZ", 1, 1, 0, 0},
- {"BE1" , 0, 8, 1010, "RO", 0, 1, 0ull, 0},
- {"BE0" , 8, 8, 1010, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_28" , 16, 13, 1010, "RO", 1, 1, 0, 0},
- {"STATUS" , 29, 3, 1010, "RO", 0, 1, 0ull, 0},
- {"LENGTH" , 32, 10, 1010, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 1010, "RO", 1, 1, 0, 0},
- {"TAG" , 48, 8, 1010, "RO", 0, 1, 0ull, 0},
- {"TYPE" , 56, 4, 1010, "RO", 0, 1, 0ull, 0},
- {"CMD" , 60, 4, 1010, "RO", 0, 1, 0ull, 0},
- {"INFO1" , 0, 64, 1011, "RO", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 1, 1012, "RO", 0, 1, 0ull, 0},
- {"LNS" , 1, 1, 1012, "RO", 0, 1, 0ull, 0},
- {"RSRVD" , 2, 30, 1012, "RO", 0, 1, 0ull, 0},
- {"LETTER" , 32, 2, 1012, "RO", 0, 1, 0ull, 0},
- {"MBOX" , 34, 2, 1012, "RO", 0, 1, 0ull, 0},
- {"XMBOX" , 36, 4, 1012, "RO", 0, 1, 0ull, 0},
- {"DID" , 40, 16, 1012, "RO", 0, 1, 0ull, 0},
- {"SSIZE" , 56, 4, 1012, "RO", 0, 1, 0ull, 0},
- {"SIS" , 60, 1, 1012, "RO", 0, 1, 0ull, 0},
- {"TT" , 61, 1, 1012, "RO", 0, 1, 0ull, 0},
- {"PRIO" , 62, 2, 1012, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_7" , 0, 8, 1013, "RAZ", 1, 1, 0, 0},
- {"OTHER" , 8, 48, 1013, "RO", 0, 1, 0ull, 0},
- {"TYPE" , 56, 4, 1013, "RO", 0, 1, 0ull, 0},
- {"TT" , 60, 2, 1013, "RO", 0, 1, 0ull, 0},
- {"PRIO" , 62, 2, 1013, "RO", 0, 1, 0ull, 0},
- {"TXBELL" , 0, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"BELL_ERR" , 1, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBELL" , 2, 1, 1014, "RO", 0, 0, 0ull, 0ull},
- {"MAINT_OP" , 3, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR_ERR" , 4, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"DENY_WR" , 5, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI_ERR" , 6, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"WR_DONE" , 7, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCE_TX" , 8, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCE_RX" , 9, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"SOFT_TX" , 10, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"SOFT_RX" , 11, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOG_ERB" , 12, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_ERB" , 13, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"LINK_DWN" , 14, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"LINK_UP" , 15, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"OMSG0" , 16, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"OMSG1" , 17, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"OMSG_ERR" , 18, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO_ERR" , 19, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTRY_ERR" , 20, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"F_ERROR" , 21, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAC_BUF" , 22, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEGRAD" , 23, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"FAIL" , 24, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"TTL_TOUT" , 25, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"ZERO_PKT" , 26, 1, 1014, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_30" , 27, 4, 1014, "RAZ", 1, 1, 0, 0},
- {"INT2_SUM" , 31, 1, 1014, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1014, "RAZ", 1, 1, 0, 0},
- {"RX_POL" , 0, 4, 1015, "R/W", 0, 0, 0ull, 0ull},
- {"TX_POL" , 4, 4, 1015, "R/W", 0, 0, 0ull, 0ull},
- {"PT_WIDTH" , 8, 2, 1015, "R/W", 0, 0, 3ull, 3ull},
- {"TX_FLOW" , 10, 1, 1015, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_11_11" , 11, 1, 1015, "RAZ", 1, 1, 0, 0},
- {"A50" , 12, 1, 1015, "R/W", 0, 0, 1ull, 1ull},
- {"A66" , 13, 1, 1015, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 1015, "RAZ", 1, 1, 0, 0},
- {"OPS" , 32, 32, 1015, "R/W", 0, 0, 64756ull, 64756ull},
- {"RX_STAT" , 0, 8, 1016, "RO", 0, 0, 0ull, 0ull},
- {"RX_INUSE" , 8, 4, 1016, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 1016, "RAZ", 1, 1, 0, 0},
- {"RX_ENB" , 16, 8, 1016, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_24_31" , 24, 8, 1016, "RAZ", 1, 1, 0, 0},
- {"TX_STAT" , 32, 8, 1016, "RO", 0, 0, 0ull, 0ull},
- {"TX_INUSE" , 40, 4, 1016, "RO", 0, 1, 0ull, 0},
- {"RESERVED_44_47" , 44, 4, 1016, "RAZ", 1, 1, 0, 0},
- {"TX_ENB" , 48, 8, 1016, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_56_63" , 56, 8, 1016, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 24, 1017, "R/W", 0, 1, 0ull, 0},
- {"OP" , 24, 1, 1017, "R/W", 0, 1, 0ull, 0},
- {"PENDING" , 25, 1, 1017, "RO", 0, 1, 0ull, 0},
- {"FAIL" , 26, 1, 1017, "RO", 0, 1, 0ull, 0},
- {"RESERVED_27_31" , 27, 5, 1017, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 32, 32, 1017, "R/W", 0, 1, 0ull, 0},
- {"RD_DATA" , 0, 32, 1018, "RO", 0, 1, 0ull, 0},
- {"VALID" , 32, 1, 1018, "RO", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 1018, "RAZ", 1, 1, 0, 0},
- {"MCE" , 0, 1, 1019, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1019, "RAZ", 1, 1, 0, 0},
- {"RP0_PID" , 0, 2, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_PID" , 2, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"RP0_SID" , 3, 2, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_SID" , 5, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 1020, "RAZ", 1, 1, 0, 0},
- {"W_RO" , 8, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"RR_RO" , 9, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1020, "RAZ", 1, 1, 0, 0},
- {"LTTR_MP" , 0, 4, 1021, "R/W", 0, 1, 15ull, 0},
- {"LTTR_SP" , 4, 4, 1021, "R/W", 0, 1, 15ull, 0},
- {"IDM_DID" , 8, 1, 1021, "R/W", 0, 1, 1ull, 0},
- {"IDM_SIS" , 9, 1, 1021, "R/W", 0, 1, 1ull, 0},
- {"IDM_TT" , 10, 1, 1021, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_11_14" , 11, 4, 1021, "RAZ", 1, 1, 0, 0},
- {"RTRY_EN" , 15, 1, 1021, "R/W", 0, 1, 0ull, 0},
- {"RTRY_THR" , 16, 16, 1021, "R/W", 0, 1, 0ull, 0},
- {"SILO_MAX" , 32, 5, 1021, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_37_62" , 37, 26, 1021, "RAZ", 1, 1, 0, 0},
- {"TESTMODE" , 63, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"GOOD" , 0, 16, 1022, "R/W", 0, 1, 0ull, 0},
- {"BAD" , 16, 16, 1022, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1022, "RAZ", 1, 1, 0, 0},
- {"ALL_PSD" , 0, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"ALL_NMP" , 1, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"ALL_FMP" , 2, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"ALL_SP" , 3, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"MBOX_PSD" , 4, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"MBOX_NMP" , 5, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"MBOX_FMP" , 6, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"MBOX_SP" , 7, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"ID_PSD" , 8, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"ID_NMP" , 9, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"ID_FMP" , 10, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"ID_SP" , 11, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"CTLR_NMP" , 12, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"CTLR_FMP" , 13, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"CTLR_SP" , 14, 1, 1023, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 1023, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"ALL_NMP" , 1, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"ALL_FMP" , 2, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"ALL_SP" , 3, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_4" , 4, 1, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX_NMP" , 5, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"MBOX_FMP" , 6, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"MBOX_SP" , 7, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_8" , 8, 1, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"ID_NMP" , 9, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"ID_FMP" , 10, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"ID_SP" , 11, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"CTLR_NMP" , 12, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"CTLR_FMP" , 13, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"CTLR_SP" , 14, 1, 1024, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 1024, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 2, 1025, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_30" , 2, 29, 1025, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 31, 1, 1025, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1025, "RAZ", 1, 1, 0, 0},
- {"TOT_SILO" , 0, 5, 1026, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_5_63" , 5, 59, 1026, "RAZ", 1, 1, 0, 0},
- {"ALL_PSD" , 0, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"ALL_NMP" , 1, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"ALL_FMP" , 2, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"ALL_SP" , 3, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"MBOX_PSD" , 4, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"MBOX_NMP" , 5, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"MBOX_FMP" , 6, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"MBOX_SP" , 7, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"ID_PSD" , 8, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"ID_NMP" , 9, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"ID_FMP" , 10, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"ID_SP" , 11, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"CTLR_NMP" , 12, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"CTLR_FMP" , 13, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"CTLR_SP" , 14, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"XMBOX_SP" , 15, 1, 1027, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1027, "RAZ", 1, 1, 0, 0},
- {"START_CNT" , 0, 16, 1028, "RO", 0, 1, 0ull, 0},
- {"END_CNT" , 16, 16, 1028, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1028, "RAZ", 1, 1, 0, 0},
- {"PRIORITY" , 0, 2, 1029, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1029, "RAZ", 1, 1, 0, 0},
- {"ID16" , 3, 1, 1029, "RO", 0, 0, 0ull, 0ull},
- {"DEST_ID" , 4, 1, 1029, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 1029, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 8, 8, 1029, "RO", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 16, 16, 1029, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 32, 16, 1029, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1029, "RAZ", 1, 1, 0, 0},
- {"SEQ" , 0, 32, 1030, "RO", 0, 1, 0ull, 0},
- {"COUNT" , 32, 8, 1030, "RO", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 1030, "RAZ", 1, 1, 0, 0},
- {"POST" , 0, 8, 1031, "RO", 0, 1, 128ull, 0},
- {"N_POST" , 8, 5, 1031, "RO", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 1031, "RAZ", 1, 1, 0, 0},
- {"COMP" , 16, 8, 1031, "RO", 0, 1, 128ull, 0},
- {"MBOX" , 24, 4, 1031, "RO", 0, 1, 8ull, 0},
- {"RESERVED_28_39" , 28, 12, 1031, "RAZ", 1, 1, 0, 0},
- {"RTN_PR1" , 40, 8, 1031, "RO", 0, 1, 0ull, 0},
- {"RTN_PR2" , 48, 8, 1031, "RO", 0, 1, 0ull, 0},
- {"RTN_PR3" , 56, 8, 1031, "RO", 0, 1, 0ull, 0},
- {"IAOW_SEL" , 0, 2, 1032, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 1032, "RAZ", 1, 1, 0, 0},
- {"ID16" , 4, 1, 1032, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 5, 1, 1032, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 1032, "RAZ", 1, 1, 0, 0},
- {"RD_PRIOR" , 8, 2, 1032, "R/W", 0, 0, 1ull, 1ull},
- {"WR_PRIOR" , 10, 2, 1032, "R/W", 0, 0, 0ull, 0ull},
- {"RD_OP" , 12, 3, 1032, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 1032, "RAZ", 1, 1, 0, 0},
- {"WR_OP" , 16, 3, 1032, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1032, "RAZ", 1, 1, 0, 0},
- {"SEQ" , 0, 32, 1033, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1033, "RAZ", 1, 1, 0, 0},
- {"SRIO" , 0, 1, 1034, "RO", 1, 1, 0, 0},
- {"ACCESS" , 1, 1, 1034, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 1034, "RAZ", 1, 1, 0, 0},
- {"ITAG" , 0, 5, 1035, "RO", 0, 1, 16ull, 0},
- {"RESERVED_5_7" , 5, 3, 1035, "RAZ", 1, 1, 0, 0},
- {"OTAG" , 8, 5, 1035, "RO", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 1035, "RAZ", 1, 1, 0, 0},
- {"O_CLR" , 16, 1, 1035, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1035, "RAZ", 1, 1, 0, 0},
- {"POST" , 0, 8, 1036, "R/W", 0, 0, 128ull, 128ull},
- {"N_POST" , 8, 5, 1036, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_13_15" , 13, 3, 1036, "RAZ", 1, 1, 0, 0},
- {"COMP" , 16, 8, 1036, "R/W", 0, 0, 128ull, 128ull},
- {"MBOX" , 24, 4, 1036, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_28_63" , 28, 36, 1036, "RAZ", 1, 1, 0, 0},
- {"PRIORITY" , 0, 2, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1037, "RAZ", 1, 1, 0, 0},
- {"ID16" , 3, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 4, 1, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 1037, "RAZ", 1, 1, 0, 0},
- {"PENDING" , 8, 1, 1037, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 1037, "RAZ", 1, 1, 0, 0},
- {"DEST_ID" , 16, 16, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"DATA" , 32, 16, 1037, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1037, "RAZ", 1, 1, 0, 0},
- {"PRIORITY" , 0, 2, 1038, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1038, "RAZ", 1, 1, 0, 0},
- {"ID16" , 3, 1, 1038, "RO", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 4, 1, 1038, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 5, 1, 1038, "RO", 0, 0, 0ull, 0ull},
- {"ERROR" , 6, 1, 1038, "RO", 0, 0, 0ull, 0ull},
- {"TIMEOUT" , 7, 1, 1038, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1038, "RAZ", 1, 1, 0, 0},
- {"DEST_ID" , 16, 16, 1038, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 32, 16, 1038, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1038, "RAZ", 1, 1, 0, 0},
- {"TX_TH0" , 0, 4, 1039, "R/W", 0, 0, 6ull, 3ull},
- {"RESERVED_4_7" , 4, 4, 1039, "RAZ", 1, 1, 0, 0},
- {"TX_TH1" , 8, 4, 1039, "R/W", 0, 0, 4ull, 2ull},
- {"RESERVED_12_15" , 12, 4, 1039, "RAZ", 1, 1, 0, 0},
- {"TX_TH2" , 16, 4, 1039, "R/W", 0, 0, 2ull, 1ull},
- {"RESERVED_20_31" , 20, 12, 1039, "RAZ", 1, 1, 0, 0},
- {"TAG_TH0" , 32, 5, 1039, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_37_39" , 37, 3, 1039, "RAZ", 1, 1, 0, 0},
- {"TAG_TH1" , 40, 5, 1039, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_45_47" , 45, 3, 1039, "RAZ", 1, 1, 0, 0},
- {"TAG_TH2" , 48, 5, 1039, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_53_63" , 53, 11, 1039, "RAZ", 1, 1, 0, 0},
- {"EMPH" , 0, 4, 1040, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 1040, "RAZ", 1, 1, 0, 0},
- {"S2M_PR0" , 0, 8, 1041, "RO", 0, 1, 0ull, 0},
- {"S2M_PR1" , 8, 8, 1041, "RO", 0, 1, 0ull, 0},
- {"S2M_PR2" , 16, 8, 1041, "RO", 0, 1, 0ull, 0},
- {"S2M_PR3" , 24, 8, 1041, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1041, "RAZ", 1, 1, 0, 0},
- {"GOOD" , 0, 16, 1042, "R/W", 0, 1, 0ull, 0},
- {"BAD" , 16, 16, 1042, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1042, "RAZ", 1, 1, 0, 0},
- {"ASSY_VEN" , 0, 16, 1043, "RO", 0, 0, 140ull, 0ull},
- {"ASSY_ID" , 16, 16, 1043, "RO", 0, 0, 0ull, 0ull},
- {"EXT_FPTR" , 0, 16, 1044, "RO", 0, 0, 256ull, 256ull},
- {"ASSY_REV" , 16, 16, 1044, "RO", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1045, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_2" , 1, 2, 1045, "RAZ", 1, 1, 0, 0},
- {"NCA" , 3, 1, 1045, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 4, 2, 1045, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 1045, "RAZ", 1, 1, 0, 0},
- {"LA" , 8, 22, 1045, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 1045, "RAZ", 1, 1, 0, 0},
- {"FULL" , 0, 1, 1046, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 1046, "RAZ", 1, 1, 0, 0},
- {"COMP_TAG" , 0, 32, 1047, "R/W", 0, 0, 0ull, 0ull},
- {"MEMORY" , 0, 1, 1048, "R/W", 0, 0, 0ull, 1ull},
- {"DOORBELL" , 1, 1, 1048, "R/W", 0, 0, 0ull, 1ull},
- {"IMSG0" , 2, 1, 1048, "R/W", 0, 0, 0ull, 1ull},
- {"IMSG1" , 3, 1, 1048, "R/W", 0, 0, 0ull, 1ull},
- {"HALT" , 4, 1, 1048, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 1048, "RAZ", 1, 1, 0, 0},
- {"VENDOR" , 0, 16, 1049, "RO", 0, 0, 140ull, 140ull},
- {"DEVICE" , 16, 16, 1049, "RO", 0, 1, 144ull, 0},
- {"REVISION" , 0, 8, 1050, "RO", 1, 1, 0, 0},
- {"RESERVED_8_31" , 8, 24, 1050, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 1051, "RAZ", 1, 1, 0, 0},
- {"PORT_WR" , 2, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SWP" , 3, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_CLR" , 4, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SET" , 5, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_DEC" , 6, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_INC" , 7, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"TESTSWAP" , 8, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"COMPSWAP" , 9, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 10, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"MSG" , 11, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"WRITE_R" , 12, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"SWRITE" , 13, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"WRITE" , 14, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"READ" , 15, 1, 1051, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_21" , 16, 6, 1051, "RAZ", 1, 1, 0, 0},
- {"TLB_INVS" , 22, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"TLB_INV" , 23, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"I_INVALD" , 24, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"IO_READ" , 25, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"D_FLUSH" , 26, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"CASTOUT" , 27, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"D_INVALD" , 28, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"RD_OWN" , 29, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"I_READ" , 30, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"GSM_READ" , 31, 1, 1051, "RO", 0, 0, 0ull, 0ull},
- {"VALID" , 0, 1, 1052, "R/W0C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 1052, "RAZ", 1, 1, 0, 0},
- {"ERR_INFO" , 4, 20, 1052, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_TYPE" , 24, 5, 1052, "R/W", 0, 0, 0ull, 0ull},
- {"INF_TYPE" , 29, 3, 1052, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_TOUT" , 0, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ACK" , 1, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"DEL_ERR" , 2, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"F_TOGGLE" , 3, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"PROTERR" , 4, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_ACK" , 5, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_14" , 6, 9, 1053, "RAZ", 1, 1, 0, 0},
- {"INV_DATA" , 15, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"INV_CHAR" , 16, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 17, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CRC" , 18, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"OUT_ACK" , 19, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"NACK" , 20, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ID" , 21, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"CTL_CRC" , 22, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_30" , 23, 8, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"IMP_ERR" , 31, 1, 1053, "R/W", 0, 0, 0ull, 0ull},
- {"RATE_CNT" , 0, 8, 1054, "R/W", 0, 1, 0ull, 0},
- {"PK_RATE" , 8, 8, 1054, "R/W", 0, 1, 0ull, 0},
- {"RATE_LIM" , 16, 2, 1054, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_23" , 18, 6, 1054, "RAZ", 1, 1, 0, 0},
- {"ERR_BIAS" , 24, 8, 1054, "R/W", 0, 0, 128ull, 128ull},
- {"LNK_TOUT" , 0, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ACK" , 1, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"DEL_ERR" , 2, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"F_TOGGLE" , 3, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"PROTERR" , 4, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_ACK" , 5, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_14" , 6, 9, 1055, "RAZ", 1, 1, 0, 0},
- {"INV_DATA" , 15, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"INV_CHAR" , 16, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 17, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CRC" , 18, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"OUT_ACK" , 19, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"NACK" , 20, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ID" , 21, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"CTL_CRC" , 22, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_30" , 23, 8, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"IMP_ERR" , 31, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_15" , 0, 16, 1056, "RAZ", 1, 1, 0, 0},
- {"DGRAD_TH" , 16, 8, 1056, "R/W", 0, 0, 255ull, 128ull},
- {"FAIL_TH" , 24, 8, 1056, "R/W", 0, 0, 255ull, 255ull},
- {"EF_ID" , 0, 16, 1057, "RO", 0, 0, 7ull, 7ull},
- {"EF_PTR" , 16, 16, 1057, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 32, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"XADDR" , 0, 2, 1059, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1059, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 29, 1059, "R/W", 0, 0, 0ull, 0ull},
- {"CAPT_IDX" , 0, 5, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_5" , 5, 1, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"WDPTR" , 6, 1, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"TT" , 7, 1, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 8, 4, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"STATUS" , 12, 4, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"EXTRA" , 16, 8, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"TTYPE" , 24, 4, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"FTYPE" , 28, 4, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_14" , 0, 15, 1061, "RAZ", 1, 1, 0, 0},
- {"TT" , 15, 1, 1061, "R/W", 0, 0, 0ull, 0ull},
- {"ID8" , 16, 8, 1061, "R/W", 0, 0, 0ull, 0ull},
- {"ID16" , 24, 8, 1061, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID8" , 0, 8, 1062, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID16" , 8, 8, 1062, "R/W", 0, 0, 0ull, 0ull},
- {"DST_ID8" , 16, 8, 1062, "R/W", 0, 0, 0ull, 0ull},
- {"DST_ID16" , 24, 8, 1062, "R/W", 0, 0, 0ull, 0ull},
- {"RESP_SZ" , 0, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_21" , 1, 21, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_TRAN" , 22, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_RESP" , 23, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_TOUT" , 24, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_TOUT" , 25, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TGT" , 26, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TRAN" , 27, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_FMT" , 28, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"GSM_ERR" , 29, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_ERR" , 30, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"IO_ERR" , 31, 1, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"RESP_SZ" , 0, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_21" , 1, 21, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_TRAN" , 22, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_RESP" , 23, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_TOUT" , 24, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_TOUT" , 25, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TGT" , 26, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TRAN" , 27, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_FMT" , 28, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"GSM_ERR" , 29, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_ERR" , 30, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"IO_ERR" , 31, 1, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1066, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1067, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1068, "R/W", 0, 0, 0ull, 0ull},
- {"HOSTID" , 0, 16, 1069, "R/W", 0, 0, 65535ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1069, "RAZ", 1, 1, 0, 0},
- {"RX_SYNC" , 0, 1, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"TX_SYNC" , 1, 1, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"TX_FLOW" , 2, 1, 1070, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_19" , 3, 17, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"TX_WM2" , 20, 4, 1070, "R/W", 0, 1, 2ull, 0},
- {"TX_WM1" , 24, 4, 1070, "R/W", 0, 1, 3ull, 0},
- {"TX_WM0" , 28, 4, 1070, "R/W", 0, 1, 4ull, 0},
- {"RX_WM0" , 0, 4, 1071, "R/W", 0, 0, 4ull, 4ull},
- {"RX_WM1" , 4, 4, 1071, "R/W", 0, 0, 3ull, 3ull},
- {"RX_WM2" , 8, 4, 1071, "R/W", 0, 0, 2ull, 2ull},
- {"RX_WM3" , 12, 4, 1071, "R/W", 0, 0, 1ull, 1ull},
- {"TX_WM0" , 16, 4, 1071, "R/W", 0, 0, 4ull, 4ull},
- {"TX_WM1" , 20, 4, 1071, "R/W", 0, 0, 3ull, 3ull},
- {"TX_WM2" , 24, 4, 1071, "R/W", 0, 0, 2ull, 2ull},
- {"TX_WM3" , 28, 4, 1071, "R/W", 0, 0, 1ull, 1ull},
- {"PD_CTRL" , 0, 32, 1072, "R/W", 0, 0, 0ull, 0ull},
- {"LN0_DIS" , 0, 1, 1073, "RO", 0, 0, 0ull, 0ull},
- {"LN0_RX" , 1, 3, 1073, "RO", 0, 0, 0ull, 0ull},
- {"LN1_DIS" , 4, 1, 1073, "RO", 0, 0, 0ull, 0ull},
- {"LN1_RX" , 5, 3, 1073, "RO", 0, 0, 0ull, 0ull},
- {"LN2_DIS" , 8, 1, 1073, "RO", 0, 0, 0ull, 0ull},
- {"LN2_RX" , 9, 3, 1073, "RO", 0, 0, 0ull, 0ull},
- {"LN3_DIS" , 12, 1, 1073, "RO", 0, 0, 0ull, 0ull},
- {"LN3_RX" , 13, 3, 1073, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1073, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_26" , 0, 27, 1074, "RAZ", 1, 1, 0, 0},
- {"LOOPBACK" , 27, 2, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_29" , 29, 1, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"RX_RESET" , 30, 1, 1074, "R/W", 0, 0, 1ull, 1ull},
- {"TX_RESET" , 31, 1, 1074, "R/W", 0, 0, 1ull, 1ull},
- {"INIT_SM" , 0, 10, 1075, "RO", 0, 0, 0ull, 0ull},
- {"RX_RDY" , 10, 1, 1075, "RO", 0, 0, 0ull, 0ull},
- {"TX_RDY" , 11, 1, 1075, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 1075, "RAZ", 1, 1, 0, 0},
- {"OVERWRT" , 0, 1, 1076, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 1076, "RAZ", 1, 1, 0, 0},
- {"PKT_DATA" , 0, 32, 1077, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_ST" , 0, 4, 1078, "RO", 0, 0, 0ull, 0ull},
- {"FULL" , 4, 1, 1078, "RO", 0, 0, 0ull, 0ull},
- {"DROP_CNT" , 5, 7, 1078, "RO", 0, 1, 0ull, 0},
- {"BUFFERS" , 12, 4, 1078, "RO", 0, 0, 0ull, 0ull},
- {"OCTETS" , 16, 16, 1078, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_15" , 0, 16, 1079, "RAZ", 1, 1, 0, 0},
- {"OCTETS" , 16, 16, 1079, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_DATA" , 0, 32, 1080, "R/W", 0, 0, 0ull, 0ull},
- {"FIFO_ST" , 0, 4, 1081, "RO", 0, 0, 0ull, 0ull},
- {"FULL" , 4, 1, 1081, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_11" , 5, 7, 1081, "RAZ", 1, 1, 0, 0},
- {"BUFFERS" , 12, 4, 1081, "RO", 0, 0, 0ull, 0ull},
- {"OCTETS" , 16, 16, 1081, "RO", 0, 0, 0ull, 0ull},
- {"STATUSN" , 0, 3, 1082, "RO", 0, 0, 0ull, 0ull},
- {"STATUS1" , 3, 1, 1082, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_5" , 4, 2, 1082, "RAZ", 1, 1, 0, 0},
- {"XTRAIN" , 6, 1, 1082, "RO", 0, 0, 0ull, 0ull},
- {"XSYNC" , 7, 1, 1082, "RO", 0, 0, 0ull, 0ull},
- {"DEC_ERR" , 8, 4, 1082, "RO", 0, 0, 0ull, 0ull},
- {"RX_TRAIN" , 12, 1, 1082, "RO", 0, 0, 0ull, 0ull},
- {"RX_SYNC" , 13, 1, 1082, "RO", 0, 0, 0ull, 0ull},
- {"RX_ADAPT" , 14, 1, 1082, "RO", 0, 0, 1ull, 1ull},
- {"RX_INV" , 15, 1, 1082, "RO", 0, 0, 0ull, 0ull},
- {"RX_TYPE" , 16, 2, 1082, "RO", 0, 0, 0ull, 0ull},
- {"TX_MODE" , 18, 1, 1082, "RO", 0, 0, 0ull, 0ull},
- {"TX_TYPE" , 19, 1, 1082, "RO", 0, 0, 0ull, 0ull},
- {"LANE" , 20, 4, 1082, "RO", 0, 0, 0ull, 0ull},
- {"PORT" , 24, 8, 1082, "RO", 0, 0, 0ull, 0ull},
- {"LCSBA" , 0, 31, 1083, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1083, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_20" , 0, 21, 1084, "R/W", 0, 0, 0ull, 0ull},
- {"LCSBA" , 21, 11, 1084, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR48" , 0, 16, 1085, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR64" , 16, 16, 1085, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1086, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR66" , 1, 2, 1086, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_13" , 3, 11, 1086, "RAZ", 1, 1, 0, 0},
- {"ADDR32" , 14, 18, 1086, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR48" , 0, 16, 1087, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR64" , 16, 16, 1087, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR66" , 1, 2, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"BARSIZE" , 3, 4, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_19" , 7, 13, 1088, "RAZ", 1, 1, 0, 0},
- {"ADDR32" , 20, 12, 1088, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR66" , 1, 2, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"CAX" , 3, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"ESX" , 4, 2, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 1089, "RAZ", 1, 1, 0, 0},
- {"ADDR48" , 9, 7, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR64" , 16, 16, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_RTRY" , 0, 16, 1090, "R/W", 0, 1, 0ull, 0},
- {"TYPE_MRG" , 16, 1, 1090, "R/W", 0, 0, 1ull, 1ull},
- {"EOP_MRG" , 17, 1, 1090, "R/W", 0, 0, 1ull, 1ull},
- {"RX_SPF" , 18, 1, 1090, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_ZERO" , 19, 1, 1090, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 1090, "RAZ", 1, 1, 0, 0},
- {"EX_ADDR" , 0, 3, 1091, "RO", 0, 0, 7ull, 7ull},
- {"EX_FEAT" , 3, 1, 1091, "RO", 0, 0, 1ull, 1ull},
- {"LG_TRAN" , 4, 1, 1091, "RO", 0, 0, 1ull, 1ull},
- {"CRF" , 5, 1, 1091, "RO", 0, 0, 0ull, 0ull},
- {"SUPPRESS" , 6, 1, 1091, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 1091, "RAZ", 1, 1, 0, 0},
- {"MULT_PRT" , 27, 1, 1091, "RO", 0, 0, 0ull, 0ull},
- {"SWITCHF" , 28, 1, 1091, "RO", 0, 0, 0ull, 0ull},
- {"PROC" , 29, 1, 1091, "RO", 0, 0, 1ull, 1ull},
- {"MEMORY" , 30, 1, 1091, "RO", 0, 0, 1ull, 1ull},
- {"BRIDGE" , 31, 1, 1091, "RO", 0, 0, 0ull, 0ull},
- {"EX_ADDR" , 0, 3, 1092, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_31" , 3, 29, 1092, "RAZ", 1, 1, 0, 0},
- {"PT_TYPE" , 0, 1, 1093, "RO", 0, 0, 1ull, 1ull},
- {"PRT_LOCK" , 1, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"DROP_PKT" , 2, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"STP_PORT" , 3, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"SUPPRESS" , 4, 8, 1093, "RO", 0, 0, 0ull, 0ull},
- {"EX_STAT" , 12, 2, 1093, "RO", 0, 0, 0ull, 0ull},
- {"EX_WIDTH" , 14, 2, 1093, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 1093, "RAZ", 1, 1, 0, 0},
- {"ENUMB" , 17, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_18" , 18, 1, 1093, "RAZ", 1, 1, 0, 0},
- {"MCAST" , 19, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_ERR" , 20, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"I_ENABLE" , 21, 1, 1093, "R/W", 0, 0, 0ull, 1ull},
- {"O_ENABLE" , 22, 1, 1093, "R/W", 0, 0, 0ull, 1ull},
- {"DISABLE" , 23, 1, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"OV_WIDTH" , 24, 3, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"IT_WIDTH" , 27, 3, 1093, "RO", 0, 1, 0ull, 0},
- {"PT_WIDTH" , 30, 2, 1093, "RO", 0, 0, 3ull, 3ull},
- {"EMPH_EN" , 0, 1, 1094, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EMPH" , 1, 1, 1094, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 1094, "R/W", 0, 0, 0ull, 0ull},
- {"ENB_625G" , 16, 1, 1094, "R/W", 0, 0, 0ull, 0ull},
- {"SUP_625G" , 17, 1, 1094, "RO", 0, 0, 0ull, 0ull},
- {"ENB_500G" , 18, 1, 1094, "R/W", 1, 1, 0, 0},
- {"SUB_500G" , 19, 1, 1094, "RO", 1, 1, 0, 0},
- {"ENB_312G" , 20, 1, 1094, "R/W", 1, 1, 0, 0},
- {"SUP_312G" , 21, 1, 1094, "RO", 1, 1, 0, 0},
- {"ENB_250G" , 22, 1, 1094, "R/W", 1, 1, 0, 0},
- {"SUP_250G" , 23, 1, 1094, "RO", 1, 1, 0, 0},
- {"ENB_125G" , 24, 1, 1094, "R/W", 1, 1, 0, 0},
- {"SUP_125G" , 25, 1, 1094, "RO", 1, 1, 0, 0},
- {"BAUD_ENB" , 26, 1, 1094, "R/W", 0, 0, 0ull, 0ull},
- {"BAUD_SUP" , 27, 1, 1094, "RO", 0, 0, 0ull, 0ull},
- {"SEL_BAUD" , 28, 4, 1094, "RO", 0, 1, 0ull, 0},
- {"PT_UINIT" , 0, 1, 1095, "RO", 0, 0, 1ull, 0ull},
- {"PT_OK" , 1, 1, 1095, "RO", 0, 0, 0ull, 1ull},
- {"PT_ERROR" , 2, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1095, "RAZ", 1, 1, 0, 0},
- {"PT_WRITE" , 4, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 1095, "RAZ", 1, 1, 0, 0},
- {"I_SM_ERR" , 8, 1, 1095, "RO", 0, 0, 0ull, 0ull},
- {"I_ERROR" , 9, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"I_SM_RET" , 10, 1, 1095, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 1095, "RAZ", 1, 1, 0, 0},
- {"O_SM_ERR" , 16, 1, 1095, "RO", 0, 0, 0ull, 0ull},
- {"O_ERROR" , 17, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"O_SM_RET" , 18, 1, 1095, "RO", 0, 0, 0ull, 0ull},
- {"O_RTRIED" , 19, 1, 1095, "RO", 0, 0, 0ull, 0ull},
- {"O_RETRY" , 20, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 1095, "RAZ", 1, 1, 0, 0},
- {"O_DGRAD" , 24, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"O_FAIL" , 25, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKT_DROP" , 26, 1, 1095, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 1095, "RAZ", 1, 1, 0, 0},
- {"CMD" , 0, 3, 1096, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_31" , 3, 29, 1096, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 5, 1097, "RO", 0, 1, 0ull, 0},
- {"ACKID" , 5, 6, 1097, "RO", 0, 1, 0ull, 0},
- {"RESERVED_11_30" , 11, 20, 1097, "RAZ", 1, 1, 0, 0},
- {"VALID" , 31, 1, 1097, "RO", 0, 1, 0ull, 0},
- {"O_ACKID" , 0, 6, 1098, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 1098, "RAZ", 1, 1, 0, 0},
- {"E_ACKID" , 8, 6, 1098, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_23" , 14, 10, 1098, "RAZ", 1, 1, 0, 0},
- {"I_ACKID" , 24, 6, 1098, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 1098, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_28" , 0, 29, 1099, "RAZ", 1, 1, 0, 0},
- {"DISCOVER" , 29, 1, 1099, "R/W", 0, 0, 0ull, 1ull},
- {"MENABLE" , 30, 1, 1099, "R/W", 1, 0, 0, 1ull},
- {"HOST" , 31, 1, 1099, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1100, "RAZ", 1, 1, 0, 0},
- {"TIMEOUT" , 8, 24, 1100, "R/W", 0, 0, 16777215ull, 0ull},
- {"EF_ID" , 0, 16, 1101, "RO", 0, 0, 1ull, 0ull},
- {"EF_PTR" , 16, 16, 1101, "RO", 0, 0, 4096ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1102, "RAZ", 1, 1, 0, 0},
- {"TIMEOUT" , 8, 24, 1102, "R/W", 0, 0, 16777215ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1103, "RAZ", 1, 1, 0, 0},
- {"TIMEOUT" , 8, 24, 1103, "R/W", 0, 1, 0ull, 0},
- {"ID16" , 0, 16, 1104, "R/W", 0, 0, 65535ull, 0ull},
- {"ID8" , 16, 8, 1104, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1104, "RAZ", 1, 1, 0, 0},
- {"ENABLE16" , 0, 1, 1105, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE8" , 1, 1, 1105, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 1105, "RAZ", 1, 1, 0, 0},
- {"ID16" , 0, 16, 1106, "R/W", 0, 0, 65535ull, 0ull},
- {"ID8" , 16, 8, 1106, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1106, "RAZ", 1, 1, 0, 0},
- {"EF_ID" , 0, 16, 1107, "RO", 0, 0, 13ull, 13ull},
- {"EF_PTR" , 16, 16, 1107, "RO", 0, 0, 8192ull, 0ull},
- {"RESERVED_0_1" , 0, 2, 1108, "RAZ", 1, 1, 0, 0},
- {"PORT_WR" , 2, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SWP" , 3, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_CLR" , 4, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SET" , 5, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_DEC" , 6, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_INC" , 7, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"TESTSWAP" , 8, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"COMPSWAP" , 9, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 10, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"MSG" , 11, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"WRITE_R" , 12, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"SWRITE" , 13, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"WRITE" , 14, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"READ" , 15, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_21" , 16, 6, 1108, "RAZ", 1, 1, 0, 0},
- {"TLB_INVS" , 22, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"TLB_INV" , 23, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"I_INVALD" , 24, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"IO_READ" , 25, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"D_FLUSH" , 26, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"CASTOUT" , 27, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"D_INVALD" , 28, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"RD_OWN" , 29, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"I_READ" , 30, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"GSM_READ" , 31, 1, 1108, "RO", 0, 0, 0ull, 0ull},
- {"DROP_CNT" , 0, 16, 1109, "RO", 0, 1, 0ull, 0},
- {"DROP" , 16, 1, 1109, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 1109, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 1110, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 1110, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 1110, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 1110, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 1110, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 1110, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 1111, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 1111, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 1111, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 1112, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1112, "RO", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 1112, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 1112, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 1112, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 1113, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 1113, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 1113, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 1113, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 1114, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 1115, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 1115, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 1115, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 1115, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1116, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 1117, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1117, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1118, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1119, "RAZ", 1, 1, 0, 0},
- {"TDF" , 0, 1, 1120, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1120, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"CLKALWAYS" , 15, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"RDAT_MD" , 16, 1, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1121, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 1122, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 1122, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 1122, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 1123, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 1123, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 1123, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1123, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 1123, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1124, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1124, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1125, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1125, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1126, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1127, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1127, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1127, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1127, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1127, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 8, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1128, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 1129, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 1129, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 1129, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 1129, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1129, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 1130, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 5, 1131, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1131, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1132, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1132, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1133, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1134, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1135, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1135, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1135, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1135, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1135, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 8, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1137, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1137, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1138, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1139, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1140, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1140, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1140, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1140, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1140, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 8, 1141, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1141, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1141, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1141, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1141, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1141, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1141, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 1142, "R/W", 0, 1, 0ull, 0},
- {"LPL" , 5, 27, 1142, "R/W", 0, 1, 0ull, 0},
- {"CF" , 0, 1, 1143, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_31" , 1, 31, 1143, "R/W", 0, 0, 0ull, 0ull},
- {"CTRLDSSEG" , 0, 32, 1144, "R/W", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1145, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_31" , 14, 18, 1145, "RO", 0, 0, 0ull, 0ull},
- {"CAPLENGTH" , 0, 8, 1146, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_15" , 8, 8, 1146, "RO", 0, 0, 0ull, 0ull},
- {"HCIVERSION" , 16, 16, 1146, "RO", 0, 0, 256ull, 256ull},
- {"AC64" , 0, 1, 1147, "RO", 0, 0, 1ull, 1ull},
- {"PFLF" , 1, 1, 1147, "RO", 0, 0, 0ull, 0ull},
- {"ASPC" , 2, 1, 1147, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1147, "RO", 0, 0, 0ull, 0ull},
- {"IST" , 4, 4, 1147, "RO", 0, 0, 2ull, 2ull},
- {"EECP" , 8, 8, 1147, "RO", 0, 0, 160ull, 160ull},
- {"RESERVED_16_31" , 16, 16, 1147, "RO", 0, 0, 0ull, 0ull},
- {"N_PORTS" , 0, 4, 1148, "RO", 0, 0, 2ull, 2ull},
- {"PPC" , 4, 1, 1148, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 1148, "RO", 0, 0, 0ull, 0ull},
- {"PRR" , 7, 1, 1148, "RO", 0, 0, 0ull, 0ull},
- {"N_PCC" , 8, 4, 1148, "RO", 0, 0, 2ull, 2ull},
- {"N_CC" , 12, 4, 1148, "RO", 0, 0, 1ull, 1ull},
- {"P_INDICATOR" , 16, 1, 1148, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 1148, "RO", 0, 0, 0ull, 0ull},
- {"DPN" , 20, 4, 1148, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1148, "RO", 0, 0, 0ull, 0ull},
- {"EN" , 0, 1, 1149, "R/W", 0, 0, 0ull, 0ull},
- {"MFMC" , 1, 13, 1149, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 1149, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_0" , 0, 1, 1150, "R/W", 0, 0, 0ull, 0ull},
- {"TA_OFF" , 1, 8, 1150, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1150, "R/W", 0, 0, 0ull, 0ull},
- {"TXTX_TADAO" , 10, 3, 1150, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 1150, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_RW" , 0, 1, 1151, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_FW" , 1, 1, 1151, "R/W", 0, 0, 0ull, 0ull},
- {"PESD" , 2, 1, 1151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1151, "RAZ", 0, 0, 0ull, 0ull},
- {"NAKRF_DIS" , 4, 1, 1151, "R/W", 0, 0, 0ull, 0ull},
- {"AUTO_DIS" , 5, 1, 1151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 1151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_30" , 0, 31, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1153, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 1154, "R/W", 0, 1, 0ull, 0},
- {"BADDR" , 12, 20, 1154, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1155, "RO", 0, 0, 0ull, 0ull},
- {"CSC" , 1, 1, 1155, "R/W1C", 0, 0, 0ull, 0ull},
- {"PED" , 2, 1, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"PEDC" , 3, 1, 1155, "R/W1C", 0, 0, 0ull, 0ull},
- {"OCA" , 4, 1, 1155, "RO", 0, 0, 0ull, 0ull},
- {"OCC" , 5, 1, 1155, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPR" , 6, 1, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"SPD" , 7, 1, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"PRST" , 8, 1, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1155, "RO", 0, 0, 0ull, 0ull},
- {"LSTS" , 10, 2, 1155, "RO", 0, 1, 0ull, 0},
- {"PP" , 12, 1, 1155, "RO", 0, 0, 1ull, 1ull},
- {"PO" , 13, 1, 1155, "R/W", 0, 0, 1ull, 0ull},
- {"PIC" , 14, 2, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"PTC" , 16, 4, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"WKCNNT_E" , 20, 1, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"WKDSCNNT_E" , 21, 1, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"WKOC_E" , 22, 1, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 1155, "RO", 0, 0, 0ull, 0ull},
- {"RS" , 0, 1, 1156, "R/W", 0, 0, 0ull, 1ull},
- {"HCRESET" , 1, 1, 1156, "R/W", 0, 0, 0ull, 0ull},
- {"FLS" , 2, 2, 1156, "RO", 0, 0, 0ull, 0ull},
- {"PS_EN" , 4, 1, 1156, "R/W", 0, 0, 0ull, 0ull},
- {"AS_EN" , 5, 1, 1156, "R/W", 0, 0, 0ull, 0ull},
- {"IAA_DB" , 6, 1, 1156, "R/W", 0, 0, 0ull, 0ull},
- {"LHCR" , 7, 1, 1156, "R/W", 0, 0, 0ull, 0ull},
- {"ASPMC" , 8, 2, 1156, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1156, "RO", 0, 0, 0ull, 0ull},
- {"ASPM_EN" , 11, 1, 1156, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 1156, "RO", 0, 0, 0ull, 0ull},
- {"ITC" , 16, 8, 1156, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_24_31" , 24, 8, 1156, "RO", 0, 0, 0ull, 0ull},
- {"USBINT_EN" , 0, 1, 1157, "R/W", 0, 1, 0ull, 0},
- {"USBERRINT_EN" , 1, 1, 1157, "R/W", 0, 1, 0ull, 0},
- {"PCI_EN" , 2, 1, 1157, "R/W", 0, 1, 0ull, 0},
- {"FLRO_EN" , 3, 1, 1157, "R/W", 0, 1, 0ull, 0},
- {"HSERR_EN" , 4, 1, 1157, "R/W", 0, 1, 0ull, 0},
- {"IOAA_EN" , 5, 1, 1157, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 1157, "RO", 0, 0, 0ull, 0ull},
- {"USBINT" , 0, 1, 1158, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBERRINT" , 1, 1, 1158, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCD" , 2, 1, 1158, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLRO" , 3, 1, 1158, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSYSERR" , 4, 1, 1158, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOAA" , 5, 1, 1158, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 1158, "RO", 0, 0, 0ull, 0ull},
- {"HCHTD" , 12, 1, 1158, "RO", 0, 0, 1ull, 0ull},
- {"RECLM" , 13, 1, 1158, "RO", 0, 0, 0ull, 0ull},
- {"PSS" , 14, 1, 1158, "RO", 0, 0, 0ull, 0ull},
- {"ASS" , 15, 1, 1158, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1158, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"BCED" , 4, 28, 1159, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1160, "R/W", 0, 0, 0ull, 0ull},
- {"BHED" , 4, 28, 1160, "R/W", 0, 1, 0ull, 0},
- {"HCR" , 0, 1, 1161, "R/W", 0, 0, 0ull, 0ull},
- {"CLF" , 1, 1, 1161, "R/W", 0, 0, 0ull, 0ull},
- {"BLF" , 2, 1, 1161, "R/W", 0, 0, 0ull, 0ull},
- {"OCR" , 3, 1, 1161, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1161, "RO", 0, 0, 0ull, 0ull},
- {"SOC" , 16, 2, 1161, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 1161, "RO", 0, 0, 0ull, 0ull},
- {"CBSR" , 0, 2, 1162, "R/W", 0, 1, 0ull, 0},
- {"PLE" , 2, 1, 1162, "R/W", 0, 0, 0ull, 0ull},
- {"IE" , 3, 1, 1162, "R/W", 0, 0, 0ull, 0ull},
- {"CLE" , 4, 1, 1162, "R/W", 0, 0, 0ull, 0ull},
- {"BLE" , 5, 1, 1162, "R/W", 0, 0, 0ull, 0ull},
- {"HCFS" , 6, 2, 1162, "R/W", 0, 0, 0ull, 0ull},
- {"IR" , 8, 1, 1162, "R/W", 0, 0, 0ull, 0ull},
- {"RWC" , 9, 1, 1162, "R/W", 0, 0, 0ull, 0ull},
- {"RWE" , 10, 1, 1162, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 1162, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1163, "R/W", 0, 0, 0ull, 0ull},
- {"CCED" , 4, 28, 1163, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1164, "R/W", 0, 0, 0ull, 0ull},
- {"CHED" , 4, 28, 1164, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1165, "RO", 0, 0, 0ull, 0ull},
- {"DH" , 4, 28, 1165, "RO", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1166, "R/W", 0, 1, 11999ull, 0},
- {"RESERVED_14_15" , 14, 2, 1166, "R/W", 0, 0, 0ull, 0ull},
- {"FSMPS" , 16, 15, 1166, "R/W", 0, 1, 0ull, 0},
- {"FIT" , 31, 1, 1166, "R/W", 0, 0, 0ull, 0ull},
- {"FN" , 0, 16, 1167, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 1167, "RO", 0, 0, 0ull, 0ull},
- {"FR" , 0, 14, 1168, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_30" , 14, 17, 1168, "RO", 0, 0, 0ull, 0ull},
- {"FRT" , 31, 1, 1168, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"HCCA" , 8, 24, 1169, "R/W", 0, 1, 0ull, 0},
- {"SO" , 0, 1, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1170, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1171, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1171, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1172, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1172, "R/W1C", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1172, "R/W1C", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1172, "R/W1C", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1172, "R/W1C", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1172, "R/W1C", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1172, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1172, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1172, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1172, "RO", 0, 0, 0ull, 0ull},
- {"LST" , 0, 12, 1173, "R/W", 0, 1, 1576ull, 0},
- {"RESERVED_12_31" , 12, 20, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1174, "RO", 0, 0, 0ull, 0ull},
- {"PCED" , 4, 28, 1174, "RO", 0, 1, 0ull, 0},
- {"PS" , 0, 14, 1175, "R/W", 0, 0, 0ull, 15975ull},
- {"RESERVED_14_31" , 14, 18, 1175, "R/W", 0, 0, 0ull, 0ull},
- {"REV" , 0, 8, 1176, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_31" , 8, 24, 1176, "RO", 0, 0, 0ull, 0ull},
- {"NDP" , 0, 8, 1177, "RO", 0, 0, 2ull, 2ull},
- {"NPS" , 8, 1, 1177, "R/W", 0, 0, 0ull, 0ull},
- {"PSM" , 9, 1, 1177, "R/W", 0, 0, 1ull, 1ull},
- {"DT" , 10, 1, 1177, "RO", 0, 0, 0ull, 0ull},
- {"OCPM" , 11, 1, 1177, "R/W", 1, 1, 0, 0},
- {"NOCP" , 12, 1, 1177, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_23" , 13, 11, 1177, "RO", 0, 0, 0ull, 0ull},
- {"POTPGT" , 24, 8, 1177, "R/W", 0, 0, 1ull, 1ull},
- {"DR" , 0, 16, 1178, "R/W", 0, 0, 0ull, 0ull},
- {"PPCM" , 16, 16, 1178, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"PES" , 1, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"PSS" , 2, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"POCI" , 3, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"PRS" , 4, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1179, "R/W", 0, 0, 0ull, 0ull},
- {"PPS" , 8, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"LSDA" , 9, 1, 1179, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_15" , 10, 6, 1179, "R/W", 0, 0, 0ull, 0ull},
- {"CSC" , 16, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"PESC" , 17, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"PSSC" , 18, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"OCIC" , 19, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"PRSC" , 20, 1, 1179, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_31" , 21, 11, 1179, "R/W", 0, 0, 0ull, 0ull},
- {"LPS" , 0, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"OCI" , 1, 1, 1180, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_14" , 2, 13, 1180, "RO", 0, 0, 0ull, 0ull},
- {"DRWE" , 15, 1, 1180, "R/W", 0, 1, 0ull, 0},
- {"LPSC" , 16, 1, 1180, "R/W", 0, 1, 0ull, 0},
- {"CCIC" , 17, 1, 1180, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_18_30" , 18, 13, 1180, "RO", 0, 0, 0ull, 0ull},
- {"CRWE" , 31, 1, 1180, "WO", 1, 1, 0, 0},
- {"RESERVED_0_30" , 0, 31, 1181, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1181, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1182, "RO", 0, 0, 0ull, 0ull},
- {"PPAF_BIS" , 0, 1, 1183, "RO", 0, 0, 0ull, 0ull},
- {"WRBM_BIS" , 1, 1, 1183, "RO", 0, 0, 0ull, 0ull},
- {"ORBM_BIS" , 2, 1, 1183, "RO", 0, 0, 0ull, 0ull},
- {"ERBM_BIS" , 3, 1, 1183, "RO", 0, 0, 0ull, 0ull},
- {"DESC_BIS" , 4, 1, 1183, "RO", 0, 0, 0ull, 0ull},
- {"DATA_BIS" , 5, 1, 1183, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1183, "RO", 1, 1, 0, 0},
- {"HRST" , 0, 1, 1184, "R/W", 0, 0, 0ull, 1ull},
- {"P_PRST" , 1, 1, 1184, "R/W", 0, 0, 0ull, 1ull},
- {"P_POR" , 2, 1, 1184, "R/W", 0, 0, 1ull, 0ull},
- {"P_COM_ON" , 3, 1, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 1184, "R/W", 0, 1, 0ull, 0},
- {"P_REFCLK_DIV" , 5, 2, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"P_REFCLK_SEL" , 7, 2, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"H_DIV" , 9, 4, 1184, "R/W", 0, 0, 6ull, 6ull},
- {"O_CLKDIV_EN" , 13, 1, 1184, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_EN" , 14, 1, 1184, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_RST" , 15, 1, 1184, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_BYP" , 16, 1, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"O_CLKDIV_RST" , 17, 1, 1184, "R/W", 0, 0, 0ull, 1ull},
- {"APP_START_CLK" , 18, 1, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_SUSP_LGCY" , 19, 1, 1184, "R/W", 0, 0, 1ull, 1ull},
- {"OHCI_SM" , 20, 1, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_CLKCKTRST" , 21, 1, 1184, "R/W", 0, 0, 1ull, 1ull},
- {"EHCI_SM" , 22, 1, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 23, 1, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 24, 1, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1184, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1185, "R/W", 0, 1, 0ull, 0},
- {"EHCI_64B_ADDR_EN" , 8, 1, 1185, "R/W", 0, 0, 1ull, 1ull},
- {"INV_REG_A2" , 9, 1, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1185, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1185, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"DESC_RBM" , 19, 1, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1185, "RAZ", 1, 1, 0, 0},
- {"FLA" , 0, 6, 1186, "R/W", 0, 0, 0ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 1186, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 1187, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 5, 27, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1187, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1188, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1188, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1189, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1190, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1191, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_8" , 8, 1, 1191, "RAZ", 1, 1, 0, 0},
- {"INV_REG_A2" , 9, 1, 1191, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1191, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1191, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1191, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1191, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1191, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1191, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1191, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1191, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1192, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 8, 24, 1192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1192, "RAZ", 1, 1, 0, 0},
- {"WM" , 0, 5, 1193, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_5_63" , 5, 59, 1193, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 1194, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_EN" , 1, 1, 1194, "R/W", 0, 0, 0ull, 0ull},
- {"UPHY_BIST" , 2, 1, 1194, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_EN" , 3, 1, 1194, "R/W", 0, 0, 0ull, 0ull},
- {"SIDDQ" , 4, 1, 1194, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 5, 1, 1194, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 6, 1, 1194, "R/W", 0, 0, 0ull, 0ull},
- {"HSBIST" , 7, 1, 1194, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ERR" , 8, 1, 1194, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 9, 1, 1194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1194, "RAZ", 1, 1, 0, 0},
- {"TDATA_IN" , 0, 8, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 8, 4, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 12, 1, 1195, "R/W", 0, 0, 1ull, 0ull},
- {"TCLK" , 13, 1, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_EN" , 14, 1, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"COMPDISTUNE" , 15, 3, 1195, "R/W", 0, 0, 4ull, 4ull},
- {"SQRXTUNE" , 18, 3, 1195, "R/W", 0, 0, 4ull, 4ull},
- {"TXFSLSTUNE" , 21, 4, 1195, "R/W", 0, 0, 3ull, 3ull},
- {"TXPREEMPHASISTUNE" , 25, 1, 1195, "R/W", 0, 0, 0ull, 1ull},
- {"TXRISETUNE" , 26, 1, 1195, "R/W", 0, 0, 0ull, 1ull},
- {"TXVREFTUNE" , 27, 4, 1195, "R/W", 0, 0, 5ull, 15ull},
- {"TXHSVXTUNE" , 31, 2, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 33, 1, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"VBUSVLDEXT" , 34, 1, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"DPPULLDOWN" , 35, 1, 1195, "R/W", 0, 0, 1ull, 1ull},
- {"DMPULLDOWN" , 36, 1, 1195, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFEN" , 37, 1, 1195, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFENH" , 38, 1, 1195, "R/W", 0, 0, 1ull, 1ull},
- {"TDATA_OUT" , 39, 4, 1195, "RO", 1, 1, 0, 0},
- {"RESERVED_43_63" , 43, 21, 1195, "RAZ", 1, 1, 0, 0},
- {"ZIP_CTL" , 0, 4, 1196, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 53, 1196, "RO", 1, 0, 0, 0ull},
- {"RESERVED_57_63" , 57, 7, 1196, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 1197, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 1198, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 1198, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1198, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 1199, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 1199, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 1199, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 1199, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 1199, "RO", 0, 0, 31744ull, 31744ull},
- {"RESERVED_48_63" , 48, 16, 1199, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 17, 1200, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1200, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1201, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1201, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1202, "RAZ", 1, 1, 0, 0},
- {"MAX_INFL" , 0, 4, 1203, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 1203, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn66xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 14, 0},
- {"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 14},
- {"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 13, 16},
- {"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 1, 29},
- {"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 30},
- {"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 31},
- {"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 32},
- {"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 1, 33},
- {"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 1, 34},
- {"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 35},
- {"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 4, 37},
- {"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 41},
- {"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 11, 43},
- {"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 14, 54},
- {"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 68},
- {"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 70},
- {"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 72},
- {"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 21, 74},
- {"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 21, 95},
- {"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 2, 116},
- {"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 38, 2, 118},
- {"cvmx_agl_gmx_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 4, 120},
- {"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 124},
- {"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 126},
- {"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 128},
- {"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 130},
- {"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 132},
- {"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 134},
- {"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 136},
- {"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 138},
- {"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 140},
- {"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 142},
- {"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 4, 144},
- {"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 2, 148},
- {"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 150},
- {"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 2, 152},
- {"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 70, 4, 154},
- {"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 4, 158},
- {"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 2, 162},
- {"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 3, 164},
- {"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 5, 167},
- {"cvmx_agl_gmx_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 2, 172},
- {"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 3, 174},
- {"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 81, 2, 177},
- {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 179},
- {"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 85, 2, 181},
- {"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 87, 2, 183},
- {"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 89, 2, 185},
- {"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 187},
- {"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 93, 2, 189},
- {"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 95, 2, 191},
- {"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 97, 2, 193},
- {"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 2, 195},
- {"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 197},
- {"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 2, 199},
- {"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 2, 201},
- {"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 2, 203},
- {"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 109, 2, 205},
- {"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 111, 2, 207},
- {"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 2, 209},
- {"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 115, 2, 211},
- {"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 117, 2, 213},
- {"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 118, 2, 215},
- {"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 3, 217},
- {"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 120, 12, 220},
- {"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 121, 12, 232},
- {"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 2, 244},
- {"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 123, 2, 246},
- {"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 124, 6, 248},
- {"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 125, 2, 254},
- {"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 126, 2, 256},
- {"cvmx_agl_prt#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 127, 23, 258},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 129, 2, 281},
- {"cvmx_ciu_block_int" , CVMX_CSR_DB_TYPE_NCB, 64, 130, 40, 283},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 131, 2, 323},
- {"cvmx_ciu_en2_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 132, 3, 325},
- {"cvmx_ciu_en2_io#_int_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 134, 3, 328},
- {"cvmx_ciu_en2_io#_int_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 136, 3, 331},
- {"cvmx_ciu_en2_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 138, 3, 334},
- {"cvmx_ciu_en2_pp#_ip2_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 148, 3, 337},
- {"cvmx_ciu_en2_pp#_ip2_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 158, 3, 340},
- {"cvmx_ciu_en2_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 168, 3, 343},
- {"cvmx_ciu_en2_pp#_ip3_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 178, 3, 346},
- {"cvmx_ciu_en2_pp#_ip3_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 188, 3, 349},
- {"cvmx_ciu_en2_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 198, 3, 352},
- {"cvmx_ciu_en2_pp#_ip4_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 208, 3, 355},
- {"cvmx_ciu_en2_pp#_ip4_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 218, 3, 358},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 228, 2, 361},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 229, 2, 363},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 230, 22, 365},
- {"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 252, 22, 387},
- {"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 274, 22, 409},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 296, 37, 431},
- {"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 318, 37, 468},
- {"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 340, 37, 505},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 362, 22, 542},
- {"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 372, 22, 564},
- {"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 382, 22, 586},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 392, 37, 608},
- {"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 402, 37, 645},
- {"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 412, 37, 682},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 422, 22, 719},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 443, 22, 741},
- {"cvmx_ciu_int33_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 453, 22, 763},
- {"cvmx_ciu_int_dbg_sel" , CVMX_CSR_DB_TYPE_NCB, 64, 454, 6, 785},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 455, 37, 791},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 456, 2, 828},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 466, 2, 830},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 476, 2, 832},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 477, 2, 834},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 478, 2, 836},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 479, 1, 838},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 489, 3, 839},
- {"cvmx_ciu_qlm0" , CVMX_CSR_DB_TYPE_NCB, 64, 490, 13, 842},
- {"cvmx_ciu_qlm1" , CVMX_CSR_DB_TYPE_NCB, 64, 491, 13, 855},
- {"cvmx_ciu_qlm2" , CVMX_CSR_DB_TYPE_NCB, 64, 492, 8, 868},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 493, 6, 876},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 494, 8, 882},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 495, 2, 890},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 496, 2, 892},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 497, 2, 894},
- {"cvmx_ciu_soft_prst2" , CVMX_CSR_DB_TYPE_NCB, 64, 498, 2, 896},
- {"cvmx_ciu_soft_prst3" , CVMX_CSR_DB_TYPE_NCB, 64, 499, 2, 898},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 500, 2, 900},
- {"cvmx_ciu_sum1_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 501, 37, 902},
- {"cvmx_ciu_sum1_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 503, 37, 939},
- {"cvmx_ciu_sum1_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 513, 37, 976},
- {"cvmx_ciu_sum1_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 523, 37, 1013},
- {"cvmx_ciu_sum2_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 533, 3, 1050},
- {"cvmx_ciu_sum2_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 535, 3, 1053},
- {"cvmx_ciu_sum2_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 545, 3, 1056},
- {"cvmx_ciu_sum2_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 555, 3, 1059},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 565, 3, 1062},
- {"cvmx_ciu_tim_multi_cast" , CVMX_CSR_DB_TYPE_NCB, 64, 575, 2, 1065},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 576, 7, 1067},
- {"cvmx_dfa_bist0" , CVMX_CSR_DB_TYPE_RSL, 64, 586, 12, 1074},
- {"cvmx_dfa_bist1" , CVMX_CSR_DB_TYPE_RSL, 64, 587, 12, 1086},
- {"cvmx_dfa_config" , CVMX_CSR_DB_TYPE_RSL, 64, 588, 5, 1098},
- {"cvmx_dfa_control" , CVMX_CSR_DB_TYPE_RSL, 64, 589, 7, 1103},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 590, 2, 1110},
- {"cvmx_dfa_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 591, 1, 1112},
- {"cvmx_dfa_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 592, 1, 1113},
- {"cvmx_dfa_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 593, 1, 1114},
- {"cvmx_dfa_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 594, 1, 1115},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 595, 4, 1116},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 596, 3, 1120},
- {"cvmx_dfa_dtcfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 597, 6, 1123},
- {"cvmx_dfa_error" , CVMX_CSR_DB_TYPE_RSL, 64, 598, 5, 1129},
- {"cvmx_dfa_intmsk" , CVMX_CSR_DB_TYPE_RSL, 64, 599, 3, 1134},
- {"cvmx_dfa_memhidat" , CVMX_CSR_DB_TYPE_NCB, 64, 600, 1, 1137},
- {"cvmx_dfa_pfc0_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 601, 1, 1138},
- {"cvmx_dfa_pfc0_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 602, 5, 1139},
- {"cvmx_dfa_pfc1_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 603, 1, 1144},
- {"cvmx_dfa_pfc1_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 604, 5, 1145},
- {"cvmx_dfa_pfc2_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 605, 1, 1150},
- {"cvmx_dfa_pfc2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 606, 5, 1151},
- {"cvmx_dfa_pfc3_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 607, 1, 1156},
- {"cvmx_dfa_pfc3_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 608, 5, 1157},
- {"cvmx_dfa_pfc_gctl" , CVMX_CSR_DB_TYPE_RSL, 64, 609, 18, 1162},
- {"cvmx_dfm_char_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 610, 7, 1180},
- {"cvmx_dfm_char_mask0" , CVMX_CSR_DB_TYPE_RSL, 64, 611, 2, 1187},
- {"cvmx_dfm_char_mask2" , CVMX_CSR_DB_TYPE_RSL, 64, 612, 2, 1189},
- {"cvmx_dfm_char_mask4" , CVMX_CSR_DB_TYPE_RSL, 64, 613, 12, 1191},
- {"cvmx_dfm_comp_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 614, 11, 1203},
- {"cvmx_dfm_config" , CVMX_CSR_DB_TYPE_RSL, 64, 615, 21, 1214},
- {"cvmx_dfm_control" , CVMX_CSR_DB_TYPE_RSL, 64, 616, 20, 1235},
- {"cvmx_dfm_dll_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 617, 6, 1255},
- {"cvmx_dfm_dll_ctl3" , CVMX_CSR_DB_TYPE_RSL, 64, 618, 11, 1261},
- {"cvmx_dfm_fclk_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 619, 1, 1272},
- {"cvmx_dfm_fnt_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 620, 6, 1273},
- {"cvmx_dfm_fnt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 621, 5, 1279},
- {"cvmx_dfm_fnt_iena" , CVMX_CSR_DB_TYPE_RSL, 64, 622, 3, 1284},
- {"cvmx_dfm_fnt_sclk" , CVMX_CSR_DB_TYPE_RSL, 64, 623, 4, 1287},
- {"cvmx_dfm_fnt_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 624, 6, 1291},
- {"cvmx_dfm_ifb_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 625, 1, 1297},
- {"cvmx_dfm_modereg_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 626, 16, 1298},
- {"cvmx_dfm_modereg_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 627, 25, 1314},
- {"cvmx_dfm_ops_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 628, 1, 1339},
- {"cvmx_dfm_phy_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 629, 10, 1340},
- {"cvmx_dfm_reset_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 630, 5, 1350},
- {"cvmx_dfm_rlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 631, 10, 1355},
- {"cvmx_dfm_rlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 632, 1, 1365},
- {"cvmx_dfm_rlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 633, 5, 1366},
- {"cvmx_dfm_rodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 635, 8, 1371},
- {"cvmx_dfm_slot_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 636, 5, 1379},
- {"cvmx_dfm_slot_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 637, 5, 1384},
- {"cvmx_dfm_timing_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 638, 12, 1389},
- {"cvmx_dfm_timing_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 639, 13, 1401},
- {"cvmx_dfm_wlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 640, 6, 1414},
- {"cvmx_dfm_wlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 641, 3, 1420},
- {"cvmx_dfm_wlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 642, 5, 1423},
- {"cvmx_dfm_wodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 644, 8, 1428},
- {"cvmx_dpi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 645, 2, 1436},
- {"cvmx_dpi_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 646, 3, 1438},
- {"cvmx_dpi_dma#_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 647, 3, 1441},
- {"cvmx_dpi_dma#_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 655, 2, 1444},
- {"cvmx_dpi_dma#_err_rsp_status", CVMX_CSR_DB_TYPE_NCB, 64, 663, 2, 1446},
- {"cvmx_dpi_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 671, 7, 1448},
- {"cvmx_dpi_dma#_iflight" , CVMX_CSR_DB_TYPE_NCB, 64, 679, 2, 1455},
- {"cvmx_dpi_dma#_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 687, 2, 1457},
- {"cvmx_dpi_dma#_reqbnk0" , CVMX_CSR_DB_TYPE_NCB, 64, 695, 1, 1459},
- {"cvmx_dpi_dma#_reqbnk1" , CVMX_CSR_DB_TYPE_NCB, 64, 703, 1, 1460},
- {"cvmx_dpi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 711, 19, 1461},
- {"cvmx_dpi_dma_eng#_en" , CVMX_CSR_DB_TYPE_NCB, 64, 712, 2, 1480},
- {"cvmx_dpi_eng#_buf" , CVMX_CSR_DB_TYPE_NCB, 64, 718, 5, 1482},
- {"cvmx_dpi_info_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 724, 5, 1487},
- {"cvmx_dpi_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 725, 17, 1492},
- {"cvmx_dpi_int_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 726, 17, 1509},
- {"cvmx_dpi_ncb#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 727, 2, 1526},
- {"cvmx_dpi_pint_info" , CVMX_CSR_DB_TYPE_NCB, 64, 728, 4, 1528},
- {"cvmx_dpi_pkt_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 729, 2, 1532},
- {"cvmx_dpi_req_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 730, 2, 1534},
- {"cvmx_dpi_req_err_rsp_en" , CVMX_CSR_DB_TYPE_NCB, 64, 731, 2, 1536},
- {"cvmx_dpi_req_err_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 732, 2, 1538},
- {"cvmx_dpi_req_err_rst_en" , CVMX_CSR_DB_TYPE_NCB, 64, 733, 2, 1540},
- {"cvmx_dpi_req_err_skip_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 734, 4, 1542},
- {"cvmx_dpi_req_gbl_en" , CVMX_CSR_DB_TYPE_NCB, 64, 735, 2, 1546},
- {"cvmx_dpi_sli_prt#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 736, 13, 1548},
- {"cvmx_dpi_sli_prt#_err" , CVMX_CSR_DB_TYPE_NCB, 64, 740, 2, 1561},
- {"cvmx_dpi_sli_prt#_err_info" , CVMX_CSR_DB_TYPE_NCB, 64, 744, 6, 1563},
- {"cvmx_fpa_addr_range_error" , CVMX_CSR_DB_TYPE_RSL, 64, 748, 3, 1569},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 749, 6, 1572},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 10, 1578},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 751, 3, 1588},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 2, 1591},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 765, 3, 1593},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 766, 2, 1596},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 767, 47, 1598},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 768, 47, 1645},
- {"cvmx_fpa_packet_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 769, 2, 1692},
- {"cvmx_fpa_pool#_end_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 770, 2, 1694},
- {"cvmx_fpa_pool#_start_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 778, 2, 1696},
- {"cvmx_fpa_pool#_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 786, 2, 1698},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 794, 2, 1700},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 2, 1702},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 3, 1704},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 811, 3, 1707},
- {"cvmx_fpa_wqe_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 2, 1710},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 813, 7, 1712},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 815, 2, 1719},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 817, 2, 1721},
- {"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 819, 5, 1723},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 821, 9, 1728},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 823, 2, 1737},
- {"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 825, 8, 1739},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 827, 10, 1747},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 835, 1, 1757},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 843, 1, 1758},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 851, 1, 1759},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 859, 1, 1760},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 1, 1761},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 1, 1762},
- {"cvmx_gmx#_rx#_adr_cam_all_en", CVMX_CSR_DB_TYPE_RSL, 64, 883, 2, 1763},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 891, 2, 1765},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 899, 4, 1767},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 907, 2, 1771},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 915, 9, 1773},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 13, 1782},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 931, 2, 1795},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 939, 27, 1797},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 947, 27, 1824},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 955, 2, 1851},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 963, 2, 1853},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 971, 2, 1855},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 979, 2, 1857},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 987, 2, 1859},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 995, 2, 1861},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 1003, 2, 1863},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 1011, 2, 1865},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 1019, 2, 1867},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 1869},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 1035, 2, 1871},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 1043, 2, 1873},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 4, 1875},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 2, 1879},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 1067, 2, 1881},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 1075, 2, 1883},
- {"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1083, 4, 1885},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 1085, 4, 1889},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 1087, 2, 1893},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 1089, 5, 1895},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1091, 2, 1900},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 1093, 2, 1902},
- {"cvmx_gmx#_soft_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1101, 3, 1904},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 3, 1907},
- {"cvmx_gmx#_tb_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 2, 1910},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 5, 1912},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 1115, 2, 1917},
- {"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1123, 2, 1919},
- {"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 1125, 2, 1921},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1127, 3, 1923},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 1135, 2, 1926},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 1143, 2, 1928},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 1151, 2, 1930},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 1159, 3, 1932},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 2, 1935},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1175, 2, 1937},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 1183, 2, 1939},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 1191, 2, 1941},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1199, 2, 1943},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1207, 2, 1945},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1215, 2, 1947},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1223, 2, 1949},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 1231, 2, 1951},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 1239, 2, 1953},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 1247, 2, 1955},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 1255, 2, 1957},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 1263, 2, 1959},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 1271, 2, 1961},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1279, 2, 1963},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 1287, 2, 1965},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1295, 2, 1967},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 1297, 2, 1969},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 1299, 2, 1971},
- {"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1301, 2, 1973},
- {"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 1303, 2, 1975},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 1305, 3, 1977},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1307, 10, 1980},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1309, 10, 1990},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 1311, 2, 2000},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1313, 2, 2002},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1315, 6, 2004},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 1317, 2, 2010},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 1319, 2, 2012},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 1321, 2, 2014},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1323, 9, 2016},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 3, 2025},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 1327, 10, 2028},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 1343, 2, 2038},
- {"cvmx_gpio_clk_qlm#" , CVMX_CSR_DB_TYPE_NCB, 64, 1347, 5, 2040},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 1349, 2, 2045},
- {"cvmx_gpio_pin_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 1350, 4, 2047},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 1351, 2, 2051},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 1352, 2, 2053},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 1353, 2, 2055},
- {"cvmx_gpio_xbit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 1354, 10, 2057},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1358, 24, 2067},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1359, 9, 2091},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1360, 3, 2100},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 1361, 3, 2103},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1362, 3, 2106},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1363, 5, 2109},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1364, 5, 2114},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1365, 1, 2119},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1366, 1, 2120},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1367, 7, 2121},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1368, 7, 2128},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1369, 3, 2135},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1370, 3, 2138},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1371, 3, 2141},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1372, 5, 2144},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1373, 5, 2149},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1374, 1, 2154},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1375, 1, 2155},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1376, 3, 2156},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1377, 3, 2159},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1378, 3, 2162},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1379, 3, 2165},
- {"cvmx_iob_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 1380, 4, 2168},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1381, 2, 2172},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 1382, 2, 2174},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 1383, 2, 2176},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1384, 19, 2178},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 1385, 2, 2197},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1386, 1, 2199},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1387, 18, 2200},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1388, 13, 2218},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1389, 13, 2231},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1390, 2, 2244},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1391, 2, 2246},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1392, 2, 2248},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1393, 3, 2250},
- {"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 1405, 3, 2253},
- {"cvmx_ipd_port#_bp_page_cnt3" , CVMX_CSR_DB_TYPE_NCB, 64, 1409, 3, 2256},
- {"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1415, 2, 2259},
- {"cvmx_ipd_port_bp_counters3_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1419, 2, 2261},
- {"cvmx_ipd_port_bp_counters4_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1423, 2, 2263},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1427, 2, 2265},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1439, 2, 2267},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 1615, 1, 2269},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 1619, 1, 2270},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1623, 6, 2271},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1624, 5, 2277},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1625, 6, 2282},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1626, 7, 2288},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 1627, 2, 2295},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1635, 2, 2297},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 1636, 3, 2299},
- {"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 1637, 2, 2302},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 1638, 5, 2304},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 1646, 3, 2309},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 1647, 4, 2312},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1648, 3, 2316},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 1649, 2, 2319},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1650, 2, 2321},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1651, 4, 2323},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1652, 3, 2327},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1653, 5, 2330},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1654, 5, 2335},
- {"cvmx_l2c_big_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1655, 4, 2340},
- {"cvmx_l2c_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 1656, 12, 2344},
- {"cvmx_l2c_bst_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 1657, 5, 2356},
- {"cvmx_l2c_bst_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1658, 5, 2361},
- {"cvmx_l2c_bst_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1659, 3, 2366},
- {"cvmx_l2c_cop0_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 1660, 1, 2369},
- {"cvmx_l2c_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4476, 15, 2370},
- {"cvmx_l2c_dut_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 4477, 4, 2385},
- {"cvmx_l2c_err_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 7037, 9, 2389},
- {"cvmx_l2c_err_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 7038, 9, 2398},
- {"cvmx_l2c_err_vbf#" , CVMX_CSR_DB_TYPE_RSL, 64, 7039, 6, 2407},
- {"cvmx_l2c_err_xmc" , CVMX_CSR_DB_TYPE_RSL, 64, 7040, 5, 2413},
- {"cvmx_l2c_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 7041, 9, 2418},
- {"cvmx_l2c_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7042, 11, 2427},
- {"cvmx_l2c_ioc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 7043, 1, 2438},
- {"cvmx_l2c_ior#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 7044, 1, 2439},
- {"cvmx_l2c_qos_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 7045, 4, 2440},
- {"cvmx_l2c_qos_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 7046, 2, 2444},
- {"cvmx_l2c_qos_wgt" , CVMX_CSR_DB_TYPE_RSL, 64, 7056, 5, 2446},
- {"cvmx_l2c_rsc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 7057, 1, 2451},
- {"cvmx_l2c_rsd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 7058, 1, 2452},
- {"cvmx_l2c_tad#_ecc0" , CVMX_CSR_DB_TYPE_RSL, 64, 7059, 8, 2453},
- {"cvmx_l2c_tad#_ecc1" , CVMX_CSR_DB_TYPE_RSL, 64, 7060, 8, 2461},
- {"cvmx_l2c_tad#_ien" , CVMX_CSR_DB_TYPE_RSL, 64, 7061, 10, 2469},
- {"cvmx_l2c_tad#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 7062, 10, 2479},
- {"cvmx_l2c_tad#_pfc0" , CVMX_CSR_DB_TYPE_RSL, 64, 7063, 1, 2489},
- {"cvmx_l2c_tad#_pfc1" , CVMX_CSR_DB_TYPE_RSL, 64, 7064, 1, 2490},
- {"cvmx_l2c_tad#_pfc2" , CVMX_CSR_DB_TYPE_RSL, 64, 7065, 1, 2491},
- {"cvmx_l2c_tad#_pfc3" , CVMX_CSR_DB_TYPE_RSL, 64, 7066, 1, 2492},
- {"cvmx_l2c_tad#_prf" , CVMX_CSR_DB_TYPE_RSL, 64, 7067, 5, 2493},
- {"cvmx_l2c_tad#_tag" , CVMX_CSR_DB_TYPE_RSL, 64, 7068, 9, 2498},
- {"cvmx_l2c_ver_id" , CVMX_CSR_DB_TYPE_RSL, 64, 7069, 1, 2507},
- {"cvmx_l2c_ver_iob" , CVMX_CSR_DB_TYPE_RSL, 64, 7070, 2, 2508},
- {"cvmx_l2c_ver_msc" , CVMX_CSR_DB_TYPE_RSL, 64, 7071, 3, 2510},
- {"cvmx_l2c_ver_pp" , CVMX_CSR_DB_TYPE_RSL, 64, 7072, 2, 2513},
- {"cvmx_l2c_virtid_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 7073, 4, 2515},
- {"cvmx_l2c_virtid_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 7074, 2, 2519},
- {"cvmx_l2c_vrt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7084, 6, 2521},
- {"cvmx_l2c_vrt_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 7085, 3, 2527},
- {"cvmx_l2c_wpar_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 8109, 2, 2530},
- {"cvmx_l2c_wpar_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 8110, 2, 2532},
- {"cvmx_l2c_xmc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 8120, 1, 2534},
- {"cvmx_l2c_xmc_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 8121, 4, 2535},
- {"cvmx_l2c_xmd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 8122, 1, 2539},
- {"cvmx_lmc#_char_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 8123, 7, 2540},
- {"cvmx_lmc#_char_mask0" , CVMX_CSR_DB_TYPE_RSL, 64, 8124, 1, 2547},
- {"cvmx_lmc#_char_mask1" , CVMX_CSR_DB_TYPE_RSL, 64, 8125, 2, 2548},
- {"cvmx_lmc#_char_mask2" , CVMX_CSR_DB_TYPE_RSL, 64, 8126, 1, 2550},
- {"cvmx_lmc#_char_mask3" , CVMX_CSR_DB_TYPE_RSL, 64, 8127, 2, 2551},
- {"cvmx_lmc#_char_mask4" , CVMX_CSR_DB_TYPE_RSL, 64, 8128, 12, 2553},
- {"cvmx_lmc#_comp_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 8129, 11, 2565},
- {"cvmx_lmc#_config" , CVMX_CSR_DB_TYPE_RSL, 64, 8130, 22, 2576},
- {"cvmx_lmc#_control" , CVMX_CSR_DB_TYPE_RSL, 64, 8131, 21, 2598},
- {"cvmx_lmc#_dclk_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 8132, 1, 2619},
- {"cvmx_lmc#_ddr_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 8133, 11, 2620},
- {"cvmx_lmc#_dimm#_params" , CVMX_CSR_DB_TYPE_RSL, 64, 8134, 16, 2631},
- {"cvmx_lmc#_dimm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 8136, 5, 2647},
- {"cvmx_lmc#_dll_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 8137, 6, 2652},
- {"cvmx_lmc#_dll_ctl3" , CVMX_CSR_DB_TYPE_RSL, 64, 8138, 11, 2658},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 8139, 4, 2669},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 8140, 5, 2673},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 8141, 6, 2678},
- {"cvmx_lmc#_ifb_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 8142, 1, 2684},
- {"cvmx_lmc#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 8143, 4, 2685},
- {"cvmx_lmc#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 8144, 4, 2689},
- {"cvmx_lmc#_modereg_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 8145, 16, 2693},
- {"cvmx_lmc#_modereg_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 8146, 25, 2709},
- {"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 8147, 10, 2734},
- {"cvmx_lmc#_ops_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 8148, 1, 2744},
- {"cvmx_lmc#_phy_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 8149, 10, 2745},
- {"cvmx_lmc#_reset_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 8150, 5, 2755},
- {"cvmx_lmc#_rlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 8151, 10, 2760},
- {"cvmx_lmc#_rlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 8152, 1, 2770},
- {"cvmx_lmc#_rlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 8153, 11, 2771},
- {"cvmx_lmc#_rodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 8157, 8, 2782},
- {"cvmx_lmc#_scramble_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 8158, 1, 2790},
- {"cvmx_lmc#_scramble_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 8159, 1, 2791},
- {"cvmx_lmc#_scrambled_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 8160, 6, 2792},
- {"cvmx_lmc#_slot_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 8161, 5, 2798},
- {"cvmx_lmc#_slot_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 8162, 5, 2803},
- {"cvmx_lmc#_slot_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 8163, 5, 2808},
- {"cvmx_lmc#_timing_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 8164, 12, 2813},
- {"cvmx_lmc#_timing_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 8165, 13, 2825},
- {"cvmx_lmc#_tro_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 8166, 3, 2838},
- {"cvmx_lmc#_tro_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 8167, 2, 2841},
- {"cvmx_lmc#_wlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 8168, 6, 2843},
- {"cvmx_lmc#_wlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 8169, 3, 2849},
- {"cvmx_lmc#_wlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 8170, 11, 2852},
- {"cvmx_lmc#_wodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 8174, 8, 2863},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 8175, 2, 2871},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 8176, 3, 2873},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 8177, 10, 2876},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 8179, 3, 2886},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 8181, 3, 2889},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 8183, 15, 2892},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 8185, 3, 2907},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 8186, 3, 2910},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 8187, 3, 2913},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 8188, 5, 2916},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 8190, 1, 2921},
- {"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 8191, 9, 2922},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 8192, 13, 2931},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 8200, 13, 2944},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 8208, 6, 2957},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 8209, 1, 2963},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 8211, 2, 2964},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 8212, 2, 2966},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 8213, 15, 2968},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 8214, 18, 2983},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 8215, 4, 3001},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 8216, 1, 3005},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 8217, 7, 3006},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 8218, 3, 3013},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 8219, 8, 3016},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 8220, 7, 3024},
- {"cvmx_mio_fus_read_times" , CVMX_CSR_DB_TYPE_RSL, 64, 8221, 6, 3031},
- {"cvmx_mio_fus_repair_res0" , CVMX_CSR_DB_TYPE_RSL, 64, 8222, 5, 3037},
- {"cvmx_mio_fus_repair_res1" , CVMX_CSR_DB_TYPE_RSL, 64, 8223, 4, 3042},
- {"cvmx_mio_fus_repair_res2" , CVMX_CSR_DB_TYPE_RSL, 64, 8224, 2, 3046},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 8225, 4, 3048},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 8226, 2, 3052},
- {"cvmx_mio_fus_tgg" , CVMX_CSR_DB_TYPE_RSL, 64, 8227, 2, 3054},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 8228, 2, 3056},
- {"cvmx_mio_gpio_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 8229, 3, 3058},
- {"cvmx_mio_ndf_dma_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 8230, 10, 3061},
- {"cvmx_mio_ndf_dma_int" , CVMX_CSR_DB_TYPE_RSL, 64, 8231, 2, 3071},
- {"cvmx_mio_ndf_dma_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 8232, 2, 3073},
- {"cvmx_mio_ptp_ckout_hi_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 8233, 2, 3075},
- {"cvmx_mio_ptp_ckout_lo_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 8234, 2, 3077},
- {"cvmx_mio_ptp_ckout_thresh_hi", CVMX_CSR_DB_TYPE_NCB, 64, 8235, 1, 3079},
- {"cvmx_mio_ptp_ckout_thresh_lo", CVMX_CSR_DB_TYPE_NCB, 64, 8236, 2, 3080},
- {"cvmx_mio_ptp_clock_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 8237, 18, 3082},
- {"cvmx_mio_ptp_clock_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 8238, 2, 3100},
- {"cvmx_mio_ptp_clock_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 8239, 1, 3102},
- {"cvmx_mio_ptp_clock_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 8240, 2, 3103},
- {"cvmx_mio_ptp_evt_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 8241, 1, 3105},
- {"cvmx_mio_ptp_pps_hi_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 8242, 2, 3106},
- {"cvmx_mio_ptp_pps_lo_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 8243, 2, 3108},
- {"cvmx_mio_ptp_pps_thresh_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 8244, 1, 3110},
- {"cvmx_mio_ptp_pps_thresh_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 8245, 2, 3111},
- {"cvmx_mio_ptp_timestamp" , CVMX_CSR_DB_TYPE_NCB, 64, 8246, 1, 3113},
- {"cvmx_mio_qlm#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 8247, 4, 3114},
- {"cvmx_mio_rst_boot" , CVMX_CSR_DB_TYPE_RSL, 64, 8250, 16, 3118},
- {"cvmx_mio_rst_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 8251, 5, 3134},
- {"cvmx_mio_rst_ckill" , CVMX_CSR_DB_TYPE_RSL, 64, 8252, 2, 3139},
- {"cvmx_mio_rst_cntl#" , CVMX_CSR_DB_TYPE_RSL, 64, 8253, 10, 3141},
- {"cvmx_mio_rst_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 8257, 10, 3151},
- {"cvmx_mio_rst_delay" , CVMX_CSR_DB_TYPE_RSL, 64, 8259, 3, 3161},
- {"cvmx_mio_rst_int" , CVMX_CSR_DB_TYPE_RSL, 64, 8260, 8, 3164},
- {"cvmx_mio_rst_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 8261, 8, 3172},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 8262, 13, 3180},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 8264, 12, 3193},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 8266, 3, 3205},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 8268, 3, 3208},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 8270, 2, 3211},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 8272, 2, 3213},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 8274, 2, 3215},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 8276, 7, 3217},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 8278, 2, 3224},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 8280, 7, 3226},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 8282, 4, 3233},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 8284, 8, 3237},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 8286, 9, 3245},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 8288, 7, 3254},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 8290, 9, 3261},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 8292, 2, 3270},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 8294, 2, 3272},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 8296, 4, 3274},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 8298, 2, 3278},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 8300, 2, 3280},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 8302, 2, 3282},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 8304, 4, 3284},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 8306, 2, 3288},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 8308, 2, 3290},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 8310, 2, 3292},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 8312, 2, 3294},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 8314, 2, 3296},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 8316, 2, 3298},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 8318, 6, 3300},
- {"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 8320, 7, 3306},
- {"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 8322, 9, 3313},
- {"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 8324, 9, 3322},
- {"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 8326, 2, 3331},
- {"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 8328, 3, 3333},
- {"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 8330, 4, 3336},
- {"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 8332, 4, 3340},
- {"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 8334, 9, 3344},
- {"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 8336, 2, 3353},
- {"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 8338, 2, 3355},
- {"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 8340, 4, 3357},
- {"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 8342, 4, 3361},
- {"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 8344, 4, 3365},
- {"cvmx_mix#_tsctl" , CVMX_CSR_DB_TYPE_NCB, 64, 8346, 6, 3369},
- {"cvmx_mix#_tstamp" , CVMX_CSR_DB_TYPE_NCB, 64, 8348, 1, 3375},
- {"cvmx_mpi_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 8350, 16, 3376},
- {"cvmx_mpi_dat#" , CVMX_CSR_DB_TYPE_NCB, 64, 8351, 2, 3392},
- {"cvmx_mpi_sts" , CVMX_CSR_DB_TYPE_NCB, 64, 8360, 4, 3394},
- {"cvmx_mpi_tx" , CVMX_CSR_DB_TYPE_NCB, 64, 8361, 8, 3398},
- {"cvmx_ndf_bt_pg_info" , CVMX_CSR_DB_TYPE_NCB, 64, 8362, 4, 3406},
- {"cvmx_ndf_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 8363, 1, 3410},
- {"cvmx_ndf_drbell" , CVMX_CSR_DB_TYPE_NCB, 64, 8364, 2, 3411},
- {"cvmx_ndf_ecc_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 8365, 3, 3413},
- {"cvmx_ndf_int" , CVMX_CSR_DB_TYPE_NCB, 64, 8366, 8, 3416},
- {"cvmx_ndf_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 8367, 8, 3424},
- {"cvmx_ndf_misc" , CVMX_CSR_DB_TYPE_NCB, 64, 8368, 12, 3432},
- {"cvmx_ndf_st_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 8369, 8, 3444},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8370, 2, 3452},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8372, 24, 3454},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8374, 4, 3478},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8376, 5, 3482},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8378, 5, 3487},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8380, 2, 3492},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8382, 1, 3494},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8384, 1, 3495},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8386, 5, 3496},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8388, 2, 3501},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8390, 1, 3503},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8392, 1, 3504},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8394, 4, 3505},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8396, 2, 3509},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8398, 2, 3511},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8400, 1, 3513},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8402, 1, 3514},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8404, 2, 3515},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8406, 3, 3517},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8408, 2, 3520},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8410, 2, 3522},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8412, 4, 3524},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8414, 10, 3528},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8416, 12, 3538},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8418, 8, 3550},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8420, 2, 3558},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8422, 1, 3560},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8424, 2, 3561},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8426, 7, 3563},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8428, 12, 3570},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8430, 19, 3582},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8432, 12, 3601},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8434, 20, 3613},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8436, 11, 3633},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8438, 8, 3644},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8440, 4, 3652},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8442, 11, 3656},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8444, 3, 3667},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8446, 16, 3670},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8448, 16, 3686},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8450, 16, 3702},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8452, 9, 3718},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8454, 9, 3727},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8456, 6, 3736},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8458, 1, 3742},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8460, 1, 3743},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8462, 1, 3744},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8464, 1, 3745},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8466, 2, 3746},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8468, 1, 3748},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8470, 6, 3749},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8472, 7, 3755},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8474, 11, 3762},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8476, 5, 3773},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8478, 6, 3778},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8480, 19, 3784},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8482, 5, 3803},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8484, 1, 3808},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8486, 1, 3809},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8488, 3, 3810},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8490, 3, 3813},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8492, 3, 3816},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8494, 4, 3819},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8496, 4, 3823},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8498, 4, 3827},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8500, 7, 3831},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8502, 5, 3838},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8504, 5, 3843},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8506, 4, 3848},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8508, 4, 3852},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8510, 4, 3856},
- {"cvmx_pcieep#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8512, 7, 3860},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8514, 1, 3867},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 8516, 1, 3868},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8518, 2, 3869},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8520, 24, 3871},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8522, 4, 3895},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8524, 5, 3899},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8526, 1, 3904},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8528, 1, 3905},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8530, 4, 3906},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8532, 17, 3910},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8534, 4, 3927},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8536, 6, 3931},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8538, 1, 3937},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8540, 1, 3938},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8542, 2, 3939},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8544, 2, 3941},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8546, 1, 3943},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8548, 15, 3944},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8550, 10, 3959},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8552, 12, 3969},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8554, 7, 3981},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8556, 2, 3988},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8558, 1, 3990},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8560, 2, 3991},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8562, 7, 3993},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8564, 11, 4000},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8566, 19, 4011},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8568, 12, 4030},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8570, 20, 4042},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8572, 12, 4062},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8574, 22, 4074},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8576, 8, 4096},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8578, 4, 4104},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8580, 11, 4108},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8582, 8, 4119},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8584, 4, 4127},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8586, 11, 4131},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8588, 1, 4142},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8590, 1, 4143},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8592, 3, 4144},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8594, 16, 4147},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8596, 16, 4163},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8598, 16, 4179},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8600, 9, 4195},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8602, 9, 4204},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8604, 6, 4213},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8606, 1, 4219},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8608, 1, 4220},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8610, 1, 4221},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8612, 1, 4222},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8614, 4, 4223},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8616, 9, 4227},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8618, 2, 4236},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8620, 2, 4238},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8622, 1, 4240},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8624, 6, 4241},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8626, 7, 4247},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8628, 11, 4254},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8630, 5, 4265},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8632, 6, 4270},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8634, 19, 4276},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8636, 5, 4295},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8638, 1, 4300},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8640, 1, 4301},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8642, 3, 4302},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8644, 3, 4305},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8646, 3, 4308},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8648, 4, 4311},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8650, 4, 4315},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8652, 4, 4319},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8654, 7, 4323},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8656, 5, 4330},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8658, 5, 4335},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8660, 4, 4340},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8662, 4, 4344},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8664, 4, 4348},
- {"cvmx_pcierc#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8666, 7, 4352},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8668, 1, 4359},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 8670, 1, 4360},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8672, 9, 4361},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8680, 6, 4370},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8688, 9, 4376},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8696, 6, 4385},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8704, 14, 4391},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8712, 14, 4405},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 8720, 2, 4419},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8728, 4, 4421},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8736, 8, 4425},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8744, 13, 4433},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8752, 17, 4446},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8760, 7, 4463},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8768, 3, 4470},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8776, 8, 4473},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8784, 7, 4481},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8792, 4, 4488},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 8800, 5, 4492},
- {"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8808, 8, 4497},
- {"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8810, 2, 4505},
- {"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 8812, 5, 4507},
- {"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8814, 10, 4512},
- {"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8816, 2, 4522},
- {"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8818, 8, 4524},
- {"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8820, 8, 4532},
- {"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8822, 6, 4540},
- {"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8824, 5, 4546},
- {"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 8826, 5, 4551},
- {"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8828, 3, 4556},
- {"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8830, 6, 4559},
- {"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8832, 9, 4565},
- {"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 8834, 5, 4574},
- {"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8836, 10, 4579},
- {"cvmx_pem#_bar1_index#" , CVMX_CSR_DB_TYPE_RSL, 64, 8838, 5, 4589},
- {"cvmx_pem#_bar2_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 8870, 3, 4594},
- {"cvmx_pem#_bar_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 8872, 5, 4597},
- {"cvmx_pem#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 8874, 9, 4602},
- {"cvmx_pem#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 8876, 11, 4611},
- {"cvmx_pem#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 8878, 2, 4622},
- {"cvmx_pem#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 8880, 2, 4624},
- {"cvmx_pem#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 8882, 2, 4626},
- {"cvmx_pem#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 8884, 18, 4628},
- {"cvmx_pem#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 8886, 32, 4646},
- {"cvmx_pem#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 8888, 32, 4678},
- {"cvmx_pem#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 8890, 5, 4710},
- {"cvmx_pem#_inb_read_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 8892, 2, 4715},
- {"cvmx_pem#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 8894, 15, 4717},
- {"cvmx_pem#_int_enb_int" , CVMX_CSR_DB_TYPE_RSL, 64, 8896, 15, 4732},
- {"cvmx_pem#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 8898, 15, 4747},
- {"cvmx_pem#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 8900, 2, 4762},
- {"cvmx_pem#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 8902, 2, 4764},
- {"cvmx_pem#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 8904, 2, 4766},
- {"cvmx_pem#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 8906, 2, 4768},
- {"cvmx_pem#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 8914, 2, 4770},
- {"cvmx_pem#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 8922, 8, 4772},
- {"cvmx_pip_alt_skip_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 8924, 12, 4780},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 8928, 5, 4792},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 8929, 2, 4797},
- {"cvmx_pip_clken" , CVMX_CSR_DB_TYPE_RSL, 64, 8930, 2, 4799},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 8931, 4, 4801},
- {"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 8935, 16, 4805},
- {"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 8936, 16, 4821},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 8937, 3, 4837},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 8938, 8, 4840},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 8939, 23, 4848},
- {"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 8940, 6, 4871},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 8941, 14, 4877},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 8942, 14, 4891},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 8943, 2, 4905},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 8944, 28, 4907},
- {"cvmx_pip_prt_cfgb#" , CVMX_CSR_DB_TYPE_RSL, 64, 8966, 4, 4935},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 8990, 25, 4939},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 9012, 2, 4964},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 9076, 4, 4966},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 9084, 9, 4970},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 9092, 2, 4979},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 9093, 2, 4981},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9094, 2, 4983},
- {"cvmx_pip_stat10_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9110, 2, 4985},
- {"cvmx_pip_stat11_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9126, 2, 4987},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9142, 2, 4989},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9158, 2, 4991},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9174, 2, 4993},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9190, 2, 4995},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9206, 2, 4997},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9222, 2, 4999},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9238, 2, 5001},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9254, 2, 5003},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9270, 2, 5005},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 9286, 2, 5007},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 9287, 2, 5009},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 9309, 2, 5011},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 9331, 2, 5013},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 9353, 2, 5015},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 9417, 2, 5017},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 9418, 3, 5019},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 9419, 3, 5022},
- {"cvmx_pip_vlan_etypes#" , CVMX_CSR_DB_TYPE_RSL, 64, 9420, 4, 5025},
- {"cvmx_pip_xstat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9422, 2, 5029},
- {"cvmx_pip_xstat10_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9428, 2, 5031},
- {"cvmx_pip_xstat11_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9434, 2, 5033},
- {"cvmx_pip_xstat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9440, 2, 5035},
- {"cvmx_pip_xstat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9446, 2, 5037},
- {"cvmx_pip_xstat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9452, 2, 5039},
- {"cvmx_pip_xstat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9458, 2, 5041},
- {"cvmx_pip_xstat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9464, 2, 5043},
- {"cvmx_pip_xstat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9470, 2, 5045},
- {"cvmx_pip_xstat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9476, 2, 5047},
- {"cvmx_pip_xstat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9482, 2, 5049},
- {"cvmx_pip_xstat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 9488, 2, 5051},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 9494, 2, 5053},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 9495, 2, 5055},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 9496, 4, 5057},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 9497, 5, 5061},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 9498, 4, 5066},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 9499, 8, 5070},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 9500, 4, 5078},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 9501, 5, 5082},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 9502, 1, 5087},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 9503, 5, 5088},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 9504, 1, 5093},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 9505, 13, 5094},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 9506, 6, 5107},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 9507, 13, 5113},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 9508, 6, 5126},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 9509, 12, 5132},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 9510, 4, 5144},
- {"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 9511, 7, 5148},
- {"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 9512, 5, 5155},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 9513, 5, 5160},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 9514, 4, 5165},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 9515, 9, 5169},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 9516, 5, 5178},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 9517, 16, 5183},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 9518, 4, 5199},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 9519, 1, 5203},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 9520, 1, 5204},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 9521, 1, 5205},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 9522, 1, 5206},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 9523, 15, 5207},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 9524, 2, 5222},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 9525, 4, 5224},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 9526, 8, 5228},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 9527, 3, 5236},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 9528, 4, 5239},
- {"cvmx_pko_reg_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 9529, 2, 5243},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 9530, 2, 5245},
- {"cvmx_pko_reg_queue_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 9531, 3, 5247},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 9532, 3, 5250},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 9533, 3, 5253},
- {"cvmx_pko_reg_timestamp" , CVMX_CSR_DB_TYPE_RSL, 64, 9534, 2, 5256},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 9535, 10, 5258},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 9536, 2, 5268},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 9537, 13, 5270},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 9538, 3, 5283},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 9539, 2, 5286},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 9547, 2, 5288},
- {"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 9548, 2, 5290},
- {"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 9549, 2, 5292},
- {"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 9550, 2, 5294},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 9558, 2, 5296},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 9559, 2, 5298},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 9560, 2, 5300},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 9561, 10, 5302},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 9571, 5, 5312},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 9579, 10, 5317},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 9587, 2, 5327},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 9588, 2, 5329},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 9589, 2, 5331},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 9597, 3, 5333},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 9598, 6, 5336},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 9614, 5, 5342},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 9615, 7, 5347},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 9631, 2, 5354},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 9647, 1, 5356},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 9648, 1, 5357},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 9649, 1, 5358},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 9650, 5, 5359},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 9651, 5, 5364},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 9652, 4, 5369},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 9653, 10, 5373},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 9654, 1, 5383},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 9655, 3, 5384},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 9656, 7, 5387},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 9657, 2, 5394},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 9658, 1, 5396},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 9659, 1, 5397},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 9660, 1, 5398},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 9661, 18, 5399},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 9662, 3, 5417},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 9663, 2, 5420},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 9664, 3, 5422},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 9665, 7, 5425},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 9666, 2, 5432},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 9667, 2, 5434},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 9668, 2, 5436},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 9669, 3, 5438},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 9670, 3, 5441},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 9671, 10, 5444},
- {"cvmx_rnm_eer_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 9672, 1, 5454},
- {"cvmx_rnm_eer_key" , CVMX_CSR_DB_TYPE_RSL, 64, 9673, 1, 5455},
- {"cvmx_rnm_serial_num" , CVMX_CSR_DB_TYPE_RSL, 64, 9674, 1, 5456},
- {"cvmx_sli_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9675, 24, 5457},
- {"cvmx_sli_ctl_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9676, 16, 5481},
- {"cvmx_sli_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9680, 3, 5497},
- {"cvmx_sli_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9681, 5, 5500},
- {"cvmx_sli_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9682, 3, 5505},
- {"cvmx_sli_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9683, 3, 5508},
- {"cvmx_sli_dma#_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9684, 2, 5511},
- {"cvmx_sli_dma#_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9686, 2, 5513},
- {"cvmx_sli_dma#_tim" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9688, 2, 5515},
- {"cvmx_sli_int_enb_ciu" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9690, 45, 5517},
- {"cvmx_sli_int_enb_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9691, 46, 5562},
- {"cvmx_sli_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9693, 46, 5608},
- {"cvmx_sli_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9694, 1, 5654},
- {"cvmx_sli_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9695, 1, 5655},
- {"cvmx_sli_last_win_rdata2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9696, 1, 5656},
- {"cvmx_sli_last_win_rdata3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9697, 1, 5657},
- {"cvmx_sli_mac_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9698, 13, 5658},
- {"cvmx_sli_mac_credit_cnt2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9699, 13, 5671},
- {"cvmx_sli_mac_number" , CVMX_CSR_DB_TYPE_PEXP, 64, 9700, 3, 5684},
- {"cvmx_sli_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9701, 3, 5687},
- {"cvmx_sli_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9702, 9, 5690},
- {"cvmx_sli_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9718, 1, 5699},
- {"cvmx_sli_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9719, 1, 5700},
- {"cvmx_sli_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9720, 1, 5701},
- {"cvmx_sli_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9721, 1, 5702},
- {"cvmx_sli_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9722, 1, 5703},
- {"cvmx_sli_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9723, 1, 5704},
- {"cvmx_sli_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9724, 1, 5705},
- {"cvmx_sli_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9725, 1, 5706},
- {"cvmx_sli_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9726, 3, 5707},
- {"cvmx_sli_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9727, 1, 5710},
- {"cvmx_sli_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9728, 1, 5711},
- {"cvmx_sli_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9729, 1, 5712},
- {"cvmx_sli_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9730, 1, 5713},
- {"cvmx_sli_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9731, 1, 5714},
- {"cvmx_sli_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9732, 1, 5715},
- {"cvmx_sli_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9733, 1, 5716},
- {"cvmx_sli_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9734, 1, 5717},
- {"cvmx_sli_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9735, 3, 5718},
- {"cvmx_sli_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9736, 2, 5721},
- {"cvmx_sli_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9737, 3, 5723},
- {"cvmx_sli_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9738, 3, 5726},
- {"cvmx_sli_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9739, 3, 5729},
- {"cvmx_sli_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9740, 3, 5732},
- {"cvmx_sli_pkt#_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9772, 2, 5735},
- {"cvmx_sli_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9804, 2, 5737},
- {"cvmx_sli_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9836, 2, 5739},
- {"cvmx_sli_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9868, 5, 5741},
- {"cvmx_sli_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9900, 21, 5746},
- {"cvmx_sli_pkt#_out_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9932, 3, 5767},
- {"cvmx_sli_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9964, 2, 5770},
- {"cvmx_sli_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 9996, 2, 5772},
- {"cvmx_sli_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10028, 2, 5774},
- {"cvmx_sli_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10060, 2, 5776},
- {"cvmx_sli_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10061, 2, 5778},
- {"cvmx_sli_pkt_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10062, 3, 5780},
- {"cvmx_sli_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10063, 1, 5783},
- {"cvmx_sli_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10064, 2, 5784},
- {"cvmx_sli_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10065, 2, 5786},
- {"cvmx_sli_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10066, 2, 5788},
- {"cvmx_sli_pkt_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10067, 2, 5790},
- {"cvmx_sli_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10068, 2, 5792},
- {"cvmx_sli_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10100, 2, 5794},
- {"cvmx_sli_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10101, 1, 5796},
- {"cvmx_sli_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10102, 17, 5797},
- {"cvmx_sli_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10103, 2, 5814},
- {"cvmx_sli_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10104, 1, 5816},
- {"cvmx_sli_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10105, 2, 5817},
- {"cvmx_sli_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10106, 3, 5819},
- {"cvmx_sli_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10107, 2, 5822},
- {"cvmx_sli_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10108, 2, 5824},
- {"cvmx_sli_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10109, 2, 5826},
- {"cvmx_sli_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10110, 2, 5828},
- {"cvmx_sli_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10111, 1, 5830},
- {"cvmx_sli_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10112, 2, 5831},
- {"cvmx_sli_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10113, 1, 5833},
- {"cvmx_sli_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10114, 2, 5834},
- {"cvmx_sli_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10115, 2, 5836},
- {"cvmx_sli_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10116, 2, 5838},
- {"cvmx_sli_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10117, 2, 5840},
- {"cvmx_sli_s2m_port#_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10118, 4, 5842},
- {"cvmx_sli_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10122, 1, 5846},
- {"cvmx_sli_scratch_2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10123, 1, 5847},
- {"cvmx_sli_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10124, 4, 5848},
- {"cvmx_sli_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10125, 8, 5852},
- {"cvmx_sli_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10126, 5, 5860},
- {"cvmx_sli_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 10127, 4, 5865},
- {"cvmx_sli_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 10128, 1, 5869},
- {"cvmx_sli_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 10129, 4, 5870},
- {"cvmx_sli_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 10130, 1, 5874},
- {"cvmx_sli_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 10131, 2, 5875},
- {"cvmx_sli_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 10132, 2, 5877},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 10133, 10, 5879},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 10135, 6, 5889},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 10137, 2, 5895},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 10139, 4, 5897},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 10141, 4, 5901},
- {"cvmx_smi_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10143, 4, 5905},
- {"cvmx_srio#_acc_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 10144, 8, 5909},
- {"cvmx_srio#_asmbly_id" , CVMX_CSR_DB_TYPE_RSL, 64, 10147, 3, 5917},
- {"cvmx_srio#_asmbly_info" , CVMX_CSR_DB_TYPE_RSL, 64, 10150, 3, 5920},
- {"cvmx_srio#_bell_resp_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 10153, 5, 5923},
- {"cvmx_srio#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 10156, 20, 5928},
- {"cvmx_srio#_imsg_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 10159, 14, 5948},
- {"cvmx_srio#_imsg_inst_hdr#" , CVMX_CSR_DB_TYPE_RSL, 64, 10162, 14, 5962},
- {"cvmx_srio#_imsg_qos_grp#" , CVMX_CSR_DB_TYPE_RSL, 64, 10168, 24, 5976},
- {"cvmx_srio#_imsg_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 10264, 24, 6000},
- {"cvmx_srio#_imsg_vport_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 10336, 13, 6024},
- {"cvmx_srio#_imsg_vport_thr2" , CVMX_CSR_DB_TYPE_RSL, 64, 10339, 5, 6037},
- {"cvmx_srio#_int2_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 10342, 2, 6042},
- {"cvmx_srio#_int2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 10345, 4, 6044},
- {"cvmx_srio#_int_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 10348, 28, 6048},
- {"cvmx_srio#_int_info0" , CVMX_CSR_DB_TYPE_RSL, 64, 10351, 9, 6076},
- {"cvmx_srio#_int_info1" , CVMX_CSR_DB_TYPE_RSL, 64, 10354, 1, 6085},
- {"cvmx_srio#_int_info2" , CVMX_CSR_DB_TYPE_RSL, 64, 10357, 11, 6086},
- {"cvmx_srio#_int_info3" , CVMX_CSR_DB_TYPE_RSL, 64, 10360, 5, 6097},
- {"cvmx_srio#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 10363, 30, 6102},
- {"cvmx_srio#_ip_feature" , CVMX_CSR_DB_TYPE_RSL, 64, 10366, 10, 6132},
- {"cvmx_srio#_mac_buffers" , CVMX_CSR_DB_TYPE_RSL, 64, 10369, 10, 6142},
- {"cvmx_srio#_maint_op" , CVMX_CSR_DB_TYPE_RSL, 64, 10372, 6, 6152},
- {"cvmx_srio#_maint_rd_data" , CVMX_CSR_DB_TYPE_RSL, 64, 10375, 3, 6158},
- {"cvmx_srio#_mce_tx_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10378, 2, 6161},
- {"cvmx_srio#_mem_op_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 10381, 8, 6163},
- {"cvmx_srio#_omsg_ctrl#" , CVMX_CSR_DB_TYPE_RSL, 64, 10384, 11, 6171},
- {"cvmx_srio#_omsg_done_counts#", CVMX_CSR_DB_TYPE_RSL, 64, 10390, 3, 6182},
- {"cvmx_srio#_omsg_fmp_mr#" , CVMX_CSR_DB_TYPE_RSL, 64, 10396, 16, 6185},
- {"cvmx_srio#_omsg_nmp_mr#" , CVMX_CSR_DB_TYPE_RSL, 64, 10402, 16, 6201},
- {"cvmx_srio#_omsg_port#" , CVMX_CSR_DB_TYPE_RSL, 64, 10408, 4, 6217},
- {"cvmx_srio#_omsg_silo_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 10414, 2, 6221},
- {"cvmx_srio#_omsg_sp_mr#" , CVMX_CSR_DB_TYPE_RSL, 64, 10417, 17, 6223},
- {"cvmx_srio#_prio#_in_use" , CVMX_CSR_DB_TYPE_RSL, 64, 10423, 3, 6240},
- {"cvmx_srio#_rx_bell" , CVMX_CSR_DB_TYPE_RSL, 64, 10435, 9, 6243},
- {"cvmx_srio#_rx_bell_seq" , CVMX_CSR_DB_TYPE_RSL, 64, 10438, 3, 6252},
- {"cvmx_srio#_rx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 10441, 9, 6255},
- {"cvmx_srio#_s2m_type#" , CVMX_CSR_DB_TYPE_RSL, 64, 10444, 11, 6264},
- {"cvmx_srio#_seq" , CVMX_CSR_DB_TYPE_RSL, 64, 10492, 2, 6275},
- {"cvmx_srio#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 10495, 3, 6277},
- {"cvmx_srio#_tag_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 10498, 6, 6280},
- {"cvmx_srio#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 10501, 6, 6286},
- {"cvmx_srio#_tx_bell" , CVMX_CSR_DB_TYPE_RSL, 64, 10504, 10, 6292},
- {"cvmx_srio#_tx_bell_info" , CVMX_CSR_DB_TYPE_RSL, 64, 10507, 11, 6302},
- {"cvmx_srio#_tx_ctrl" , CVMX_CSR_DB_TYPE_RSL, 64, 10510, 12, 6313},
- {"cvmx_srio#_tx_emphasis" , CVMX_CSR_DB_TYPE_RSL, 64, 10513, 2, 6325},
- {"cvmx_srio#_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 10516, 5, 6327},
- {"cvmx_srio#_wr_done_counts" , CVMX_CSR_DB_TYPE_RSL, 64, 10519, 3, 6332},
- {"cvmx_sriomaint#_asmbly_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10522, 2, 6335},
- {"cvmx_sriomaint#_asmbly_info" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10525, 2, 6337},
- {"cvmx_sriomaint#_bar1_idx#" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10528, 7, 6339},
- {"cvmx_sriomaint#_bell_status" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10576, 2, 6346},
- {"cvmx_sriomaint#_comp_tag" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10579, 1, 6348},
- {"cvmx_sriomaint#_core_enables", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10582, 6, 6349},
- {"cvmx_sriomaint#_dev_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10585, 2, 6355},
- {"cvmx_sriomaint#_dev_rev" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10588, 2, 6357},
- {"cvmx_sriomaint#_dst_ops" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10591, 26, 6359},
- {"cvmx_sriomaint#_erb_attr_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10594, 5, 6385},
- {"cvmx_sriomaint#_erb_err_det" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10597, 17, 6390},
- {"cvmx_sriomaint#_erb_err_rate", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10600, 5, 6407},
- {"cvmx_sriomaint#_erb_err_rate_en", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10603, 17, 6412},
- {"cvmx_sriomaint#_erb_err_rate_thr", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10606, 3, 6429},
- {"cvmx_sriomaint#_erb_hdr" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10609, 2, 6432},
- {"cvmx_sriomaint#_erb_lt_addr_capt_h", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10612, 1, 6434},
- {"cvmx_sriomaint#_erb_lt_addr_capt_l", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10615, 3, 6435},
- {"cvmx_sriomaint#_erb_lt_ctrl_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10618, 9, 6438},
- {"cvmx_sriomaint#_erb_lt_dev_id", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10621, 4, 6447},
- {"cvmx_sriomaint#_erb_lt_dev_id_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10624, 4, 6451},
- {"cvmx_sriomaint#_erb_lt_err_det", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10627, 12, 6455},
- {"cvmx_sriomaint#_erb_lt_err_en", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10630, 12, 6467},
- {"cvmx_sriomaint#_erb_pack_capt_1", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10633, 1, 6479},
- {"cvmx_sriomaint#_erb_pack_capt_2", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10636, 1, 6480},
- {"cvmx_sriomaint#_erb_pack_capt_3", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10639, 1, 6481},
- {"cvmx_sriomaint#_erb_pack_sym_capt", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10642, 1, 6482},
- {"cvmx_sriomaint#_hb_dev_id_lock", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10645, 2, 6483},
- {"cvmx_sriomaint#_ir_buffer_config", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10648, 7, 6485},
- {"cvmx_sriomaint#_ir_buffer_config2", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10651, 8, 6492},
- {"cvmx_sriomaint#_ir_pd_phy_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10654, 1, 6500},
- {"cvmx_sriomaint#_ir_pd_phy_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10657, 9, 6501},
- {"cvmx_sriomaint#_ir_pi_phy_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10660, 5, 6510},
- {"cvmx_sriomaint#_ir_pi_phy_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10663, 4, 6515},
- {"cvmx_sriomaint#_ir_sp_rx_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10666, 2, 6519},
- {"cvmx_sriomaint#_ir_sp_rx_data", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10669, 1, 6521},
- {"cvmx_sriomaint#_ir_sp_rx_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10672, 5, 6522},
- {"cvmx_sriomaint#_ir_sp_tx_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10675, 2, 6527},
- {"cvmx_sriomaint#_ir_sp_tx_data", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10678, 1, 6529},
- {"cvmx_sriomaint#_ir_sp_tx_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10681, 5, 6530},
- {"cvmx_sriomaint#_lane_#_status_0", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10684, 15, 6535},
- {"cvmx_sriomaint#_lcs_ba0" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10696, 2, 6550},
- {"cvmx_sriomaint#_lcs_ba1" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10699, 2, 6552},
- {"cvmx_sriomaint#_m2s_bar0_start0", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10702, 2, 6554},
- {"cvmx_sriomaint#_m2s_bar0_start1", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10705, 4, 6556},
- {"cvmx_sriomaint#_m2s_bar1_start0", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10708, 2, 6560},
- {"cvmx_sriomaint#_m2s_bar1_start1", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10711, 5, 6562},
- {"cvmx_sriomaint#_m2s_bar2_start", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10714, 7, 6567},
- {"cvmx_sriomaint#_mac_ctrl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10717, 7, 6574},
- {"cvmx_sriomaint#_pe_feat" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10720, 11, 6581},
- {"cvmx_sriomaint#_pe_llc" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10723, 2, 6592},
- {"cvmx_sriomaint#_port_0_ctl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10726, 18, 6594},
- {"cvmx_sriomaint#_port_0_ctl2" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10729, 16, 6612},
- {"cvmx_sriomaint#_port_0_err_stat", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10732, 20, 6628},
- {"cvmx_sriomaint#_port_0_link_req", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10735, 2, 6648},
- {"cvmx_sriomaint#_port_0_link_resp", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10738, 4, 6650},
- {"cvmx_sriomaint#_port_0_local_ackid", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10741, 6, 6654},
- {"cvmx_sriomaint#_port_gen_ctl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10744, 4, 6660},
- {"cvmx_sriomaint#_port_lt_ctl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10747, 2, 6664},
- {"cvmx_sriomaint#_port_mbh0" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10750, 2, 6666},
- {"cvmx_sriomaint#_port_rt_ctl" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10753, 2, 6668},
- {"cvmx_sriomaint#_port_ttl_ctl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10756, 2, 6670},
- {"cvmx_sriomaint#_pri_dev_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10759, 3, 6672},
- {"cvmx_sriomaint#_sec_dev_ctrl", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10762, 3, 6675},
- {"cvmx_sriomaint#_sec_dev_id" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10765, 3, 6678},
- {"cvmx_sriomaint#_serial_lane_hdr", CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10768, 2, 6681},
- {"cvmx_sriomaint#_src_ops" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10771, 26, 6683},
- {"cvmx_sriomaint#_tx_drop" , CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 10774, 3, 6709},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 10777, 6, 6712},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 10778, 3, 6718},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 10779, 5, 6721},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 10780, 4, 6726},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 10781, 6, 6730},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 10782, 4, 6736},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 10783, 2, 6740},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 10784, 4, 6742},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 10785, 2, 6746},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 10786, 3, 6748},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 10787, 2, 6751},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10788, 14, 6753},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 10789, 3, 6767},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 10790, 5, 6770},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 10791, 2, 6775},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 10792, 2, 6777},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 10793, 57, 6779},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 10794, 20, 6836},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 10795, 7, 6856},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 10796, 5, 6863},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 10797, 1, 6868},
- {"cvmx_tra#_read_dat_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 10798, 2, 6869},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 10799, 2, 6871},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 10800, 2, 6873},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 10801, 57, 6875},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 10802, 20, 6932},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 10803, 7, 6952},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 10804, 2, 6959},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 10805, 2, 6961},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 10806, 57, 6963},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 10807, 20, 7020},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 10808, 7, 7040},
- {"cvmx_uahc#_ehci_asynclistaddr", CVMX_CSR_DB_TYPE_NCB, 32, 10809, 2, 7047},
- {"cvmx_uahc#_ehci_configflag" , CVMX_CSR_DB_TYPE_NCB, 32, 10810, 2, 7049},
- {"cvmx_uahc#_ehci_ctrldssegment", CVMX_CSR_DB_TYPE_NCB, 32, 10811, 1, 7051},
- {"cvmx_uahc#_ehci_frindex" , CVMX_CSR_DB_TYPE_NCB, 32, 10812, 2, 7052},
- {"cvmx_uahc#_ehci_hccapbase" , CVMX_CSR_DB_TYPE_NCB, 32, 10813, 3, 7054},
- {"cvmx_uahc#_ehci_hccparams" , CVMX_CSR_DB_TYPE_NCB, 32, 10814, 7, 7057},
- {"cvmx_uahc#_ehci_hcsparams" , CVMX_CSR_DB_TYPE_NCB, 32, 10815, 10, 7064},
- {"cvmx_uahc#_ehci_insnreg00" , CVMX_CSR_DB_TYPE_NCB, 32, 10816, 3, 7074},
- {"cvmx_uahc#_ehci_insnreg03" , CVMX_CSR_DB_TYPE_NCB, 32, 10817, 5, 7077},
- {"cvmx_uahc#_ehci_insnreg04" , CVMX_CSR_DB_TYPE_NCB, 32, 10818, 7, 7082},
- {"cvmx_uahc#_ehci_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 10819, 2, 7089},
- {"cvmx_uahc#_ehci_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 10820, 1, 7091},
- {"cvmx_uahc#_ehci_periodiclistbase", CVMX_CSR_DB_TYPE_NCB, 32, 10821, 2, 7092},
- {"cvmx_uahc#_ehci_portsc#" , CVMX_CSR_DB_TYPE_NCB, 32, 10822, 19, 7094},
- {"cvmx_uahc#_ehci_usbcmd" , CVMX_CSR_DB_TYPE_NCB, 32, 10824, 13, 7113},
- {"cvmx_uahc#_ehci_usbintr" , CVMX_CSR_DB_TYPE_NCB, 32, 10825, 7, 7126},
- {"cvmx_uahc#_ehci_usbsts" , CVMX_CSR_DB_TYPE_NCB, 32, 10826, 12, 7133},
- {"cvmx_uahc#_ohci0_hcbulkcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 10827, 2, 7145},
- {"cvmx_uahc#_ohci0_hcbulkheaded", CVMX_CSR_DB_TYPE_NCB, 32, 10828, 2, 7147},
- {"cvmx_uahc#_ohci0_hccommandstatus", CVMX_CSR_DB_TYPE_NCB, 32, 10829, 7, 7149},
- {"cvmx_uahc#_ohci0_hccontrol" , CVMX_CSR_DB_TYPE_NCB, 32, 10830, 10, 7156},
- {"cvmx_uahc#_ohci0_hccontrolcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 10831, 2, 7166},
- {"cvmx_uahc#_ohci0_hccontrolheaded", CVMX_CSR_DB_TYPE_NCB, 32, 10832, 2, 7168},
- {"cvmx_uahc#_ohci0_hcdonehead" , CVMX_CSR_DB_TYPE_NCB, 32, 10833, 2, 7170},
- {"cvmx_uahc#_ohci0_hcfminterval", CVMX_CSR_DB_TYPE_NCB, 32, 10834, 4, 7172},
- {"cvmx_uahc#_ohci0_hcfmnumber" , CVMX_CSR_DB_TYPE_NCB, 32, 10835, 2, 7176},
- {"cvmx_uahc#_ohci0_hcfmremaining", CVMX_CSR_DB_TYPE_NCB, 32, 10836, 3, 7178},
- {"cvmx_uahc#_ohci0_hchcca" , CVMX_CSR_DB_TYPE_NCB, 32, 10837, 2, 7181},
- {"cvmx_uahc#_ohci0_hcinterruptdisable", CVMX_CSR_DB_TYPE_NCB, 32, 10838, 10, 7183},
- {"cvmx_uahc#_ohci0_hcinterruptenable", CVMX_CSR_DB_TYPE_NCB, 32, 10839, 10, 7193},
- {"cvmx_uahc#_ohci0_hcinterruptstatus", CVMX_CSR_DB_TYPE_NCB, 32, 10840, 10, 7203},
- {"cvmx_uahc#_ohci0_hclsthreshold", CVMX_CSR_DB_TYPE_NCB, 32, 10841, 2, 7213},
- {"cvmx_uahc#_ohci0_hcperiodcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 10842, 2, 7215},
- {"cvmx_uahc#_ohci0_hcperiodicstart", CVMX_CSR_DB_TYPE_NCB, 32, 10843, 2, 7217},
- {"cvmx_uahc#_ohci0_hcrevision" , CVMX_CSR_DB_TYPE_NCB, 32, 10844, 2, 7219},
- {"cvmx_uahc#_ohci0_hcrhdescriptora", CVMX_CSR_DB_TYPE_NCB, 32, 10845, 8, 7221},
- {"cvmx_uahc#_ohci0_hcrhdescriptorb", CVMX_CSR_DB_TYPE_NCB, 32, 10846, 2, 7229},
- {"cvmx_uahc#_ohci0_hcrhportstatus#", CVMX_CSR_DB_TYPE_NCB, 32, 10847, 15, 7231},
- {"cvmx_uahc#_ohci0_hcrhstatus" , CVMX_CSR_DB_TYPE_NCB, 32, 10849, 8, 7246},
- {"cvmx_uahc#_ohci0_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 10850, 2, 7254},
- {"cvmx_uahc#_ohci0_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 10851, 1, 7256},
- {"cvmx_uctl#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 10852, 7, 7257},
- {"cvmx_uctl#_clk_rst_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10853, 21, 7264},
- {"cvmx_uctl#_ehci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10854, 12, 7285},
- {"cvmx_uctl#_ehci_fla" , CVMX_CSR_DB_TYPE_RSL, 64, 10855, 2, 7297},
- {"cvmx_uctl#_erto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10856, 3, 7299},
- {"cvmx_uctl#_if_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 10857, 2, 7302},
- {"cvmx_uctl#_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 10858, 9, 7304},
- {"cvmx_uctl#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 10859, 9, 7313},
- {"cvmx_uctl#_ohci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10860, 11, 7322},
- {"cvmx_uctl#_orto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10861, 3, 7333},
- {"cvmx_uctl#_ppaf_wm" , CVMX_CSR_DB_TYPE_RSL, 64, 10862, 2, 7336},
- {"cvmx_uctl#_uphy_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 10863, 11, 7338},
- {"cvmx_uctl#_uphy_port#_ctl_status", CVMX_CSR_DB_TYPE_RSL, 64, 10864, 20, 7349},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 10866, 3, 7369},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 10867, 5, 7372},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10868, 3, 7377},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 10869, 8, 7380},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 10870, 2, 7388},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 10871, 2, 7390},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 10872, 2, 7392},
- {"cvmx_zip_throttle" , CVMX_CSR_DB_TYPE_RSL, 64, 10873, 2, 7394},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn66xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"AGL_GMX_BAD_REG" , 0x11800e0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"AGL_GMX_BIST" , 0x11800e0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"AGL_GMX_PRT0_CFG" , 0x11800e0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_PRT1_CFG" , 0x11800e0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_RX0_ADR_CAM0" , 0x11800e0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_RX1_ADR_CAM0" , 0x11800e0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_RX0_ADR_CAM1" , 0x11800e0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX1_ADR_CAM1" , 0x11800e0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX0_ADR_CAM2" , 0x11800e0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX1_ADR_CAM2" , 0x11800e0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX0_ADR_CAM3" , 0x11800e0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX1_ADR_CAM3" , 0x11800e0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX0_ADR_CAM4" , 0x11800e00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX1_ADR_CAM4" , 0x11800e00009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX0_ADR_CAM5" , 0x11800e00001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX1_ADR_CAM5" , 0x11800e00009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800e0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX1_ADR_CAM_EN" , 0x11800e0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX0_ADR_CTL" , 0x11800e0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX1_ADR_CTL" , 0x11800e0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX0_DECISION" , 0x11800e0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX1_DECISION" , 0x11800e0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX0_FRM_CHK" , 0x11800e0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX1_FRM_CHK" , 0x11800e0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX0_FRM_CTL" , 0x11800e0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX1_FRM_CTL" , 0x11800e0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX0_FRM_MAX" , 0x11800e0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX1_FRM_MAX" , 0x11800e0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX0_FRM_MIN" , 0x11800e0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX1_FRM_MIN" , 0x11800e0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX0_IFG" , 0x11800e0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX1_IFG" , 0x11800e0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX0_INT_EN" , 0x11800e0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX1_INT_EN" , 0x11800e0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX0_INT_REG" , 0x11800e0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX1_INT_REG" , 0x11800e0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX0_JABBER" , 0x11800e0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX1_JABBER" , 0x11800e0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800e0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX1_PAUSE_DROP_TIME" , 0x11800e0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX0_RX_INBND" , 0x11800e0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX1_RX_INBND" , 0x11800e0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX0_STATS_CTL" , 0x11800e0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX1_STATS_CTL" , 0x11800e0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX0_STATS_OCTS" , 0x11800e0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX1_STATS_OCTS" , 0x11800e0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800e0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX1_STATS_OCTS_CTL" , 0x11800e0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800e00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX1_STATS_OCTS_DMAC" , 0x11800e00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800e00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX1_STATS_OCTS_DRP" , 0x11800e00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX0_STATS_PKTS" , 0x11800e0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX1_STATS_PKTS" , 0x11800e0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800e00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX1_STATS_PKTS_BAD" , 0x11800e00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800e0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX1_STATS_PKTS_CTL" , 0x11800e0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800e00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX1_STATS_PKTS_DMAC" , 0x11800e00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800e00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX1_STATS_PKTS_DRP" , 0x11800e00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX0_UDD_SKP" , 0x11800e0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX1_UDD_SKP" , 0x11800e0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX_BP_DROP0" , 0x11800e0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_DROP1" , 0x11800e0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_OFF0" , 0x11800e0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_OFF1" , 0x11800e0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_ON0" , 0x11800e0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_BP_ON1" , 0x11800e0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_PRT_INFO" , 0x11800e00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_TX_STATUS" , 0x11800e00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"AGL_GMX_SMAC0" , 0x11800e0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_SMAC1" , 0x11800e0000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_STAT_BP" , 0x11800e0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_TX0_APPEND" , 0x11800e0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX1_APPEND" , 0x11800e0000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX0_CLK" , 0x11800e0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX1_CLK" , 0x11800e0000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX0_CTL" , 0x11800e0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX1_CTL" , 0x11800e0000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX0_MIN_PKT" , 0x11800e0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX1_MIN_PKT" , 0x11800e0000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800e0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX1_PAUSE_PKT_INTERVAL", 0x11800e0000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800e0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX1_PAUSE_PKT_TIME" , 0x11800e0000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800e0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX1_PAUSE_TOGO" , 0x11800e0000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800e0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX1_PAUSE_ZERO" , 0x11800e0000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800e0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX1_SOFT_PAUSE" , 0x11800e0000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX0_STAT0" , 0x11800e0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX1_STAT0" , 0x11800e0000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX0_STAT1" , 0x11800e0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX1_STAT1" , 0x11800e0000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX0_STAT2" , 0x11800e0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX1_STAT2" , 0x11800e0000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX0_STAT3" , 0x11800e0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX1_STAT3" , 0x11800e0000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX0_STAT4" , 0x11800e00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX1_STAT4" , 0x11800e0000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX0_STAT5" , 0x11800e00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX1_STAT5" , 0x11800e0000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX0_STAT6" , 0x11800e00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX1_STAT6" , 0x11800e0000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX0_STAT7" , 0x11800e00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX1_STAT7" , 0x11800e0000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX0_STAT8" , 0x11800e00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX1_STAT8" , 0x11800e0000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX0_STAT9" , 0x11800e00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX1_STAT9" , 0x11800e0000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX0_STATS_CTL" , 0x11800e0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX1_STATS_CTL" , 0x11800e0000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX0_THRESH" , 0x11800e0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX1_THRESH" , 0x11800e0000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX_BP" , 0x11800e00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"AGL_GMX_TX_COL_ATTEMPT" , 0x11800e0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"AGL_GMX_TX_IFG" , 0x11800e0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"AGL_GMX_TX_INT_EN" , 0x11800e0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"AGL_GMX_TX_INT_REG" , 0x11800e0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"AGL_GMX_TX_JAM" , 0x11800e0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"AGL_GMX_TX_LFSR" , 0x11800e00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"AGL_GMX_TX_OVR_BP" , 0x11800e00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800e00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800e00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"AGL_PRT0_CTL" , 0x11800e0002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"AGL_PRT1_CTL" , 0x11800e0002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU_BLOCK_INT" , 0x10700000007c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU_EN2_IO0_INT" , 0x107000000a600ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_EN2_IO1_INT" , 0x107000000a608ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU_EN2_IO0_INT_W1C" , 0x107000000ce00ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_EN2_IO1_INT_W1C" , 0x107000000ce08ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU_EN2_IO0_INT_W1S" , 0x107000000ae00ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_EN2_IO1_INT_W1S" , 0x107000000ae08ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU_EN2_PP0_IP2" , 0x107000000a000ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP1_IP2" , 0x107000000a008ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP2_IP2" , 0x107000000a010ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP3_IP2" , 0x107000000a018ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP4_IP2" , 0x107000000a020ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP5_IP2" , 0x107000000a028ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP6_IP2" , 0x107000000a030ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP7_IP2" , 0x107000000a038ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP8_IP2" , 0x107000000a040ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP9_IP2" , 0x107000000a048ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU_EN2_PP0_IP2_W1C" , 0x107000000c800ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP1_IP2_W1C" , 0x107000000c808ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP2_IP2_W1C" , 0x107000000c810ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP3_IP2_W1C" , 0x107000000c818ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP4_IP2_W1C" , 0x107000000c820ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP5_IP2_W1C" , 0x107000000c828ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP6_IP2_W1C" , 0x107000000c830ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP7_IP2_W1C" , 0x107000000c838ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP8_IP2_W1C" , 0x107000000c840ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP9_IP2_W1C" , 0x107000000c848ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU_EN2_PP0_IP2_W1S" , 0x107000000a800ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP1_IP2_W1S" , 0x107000000a808ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP2_IP2_W1S" , 0x107000000a810ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP3_IP2_W1S" , 0x107000000a818ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP4_IP2_W1S" , 0x107000000a820ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP5_IP2_W1S" , 0x107000000a828ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP6_IP2_W1S" , 0x107000000a830ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP7_IP2_W1S" , 0x107000000a838ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP8_IP2_W1S" , 0x107000000a840ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP9_IP2_W1S" , 0x107000000a848ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU_EN2_PP0_IP3" , 0x107000000a200ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP1_IP3" , 0x107000000a208ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP2_IP3" , 0x107000000a210ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP3_IP3" , 0x107000000a218ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP4_IP3" , 0x107000000a220ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP5_IP3" , 0x107000000a228ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP6_IP3" , 0x107000000a230ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP7_IP3" , 0x107000000a238ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP8_IP3" , 0x107000000a240ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP9_IP3" , 0x107000000a248ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU_EN2_PP0_IP3_W1C" , 0x107000000ca00ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP1_IP3_W1C" , 0x107000000ca08ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP2_IP3_W1C" , 0x107000000ca10ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP3_IP3_W1C" , 0x107000000ca18ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP4_IP3_W1C" , 0x107000000ca20ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP5_IP3_W1C" , 0x107000000ca28ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP6_IP3_W1C" , 0x107000000ca30ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP7_IP3_W1C" , 0x107000000ca38ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP8_IP3_W1C" , 0x107000000ca40ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP9_IP3_W1C" , 0x107000000ca48ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU_EN2_PP0_IP3_W1S" , 0x107000000aa00ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP1_IP3_W1S" , 0x107000000aa08ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP2_IP3_W1S" , 0x107000000aa10ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP3_IP3_W1S" , 0x107000000aa18ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP4_IP3_W1S" , 0x107000000aa20ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP5_IP3_W1S" , 0x107000000aa28ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP6_IP3_W1S" , 0x107000000aa30ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP7_IP3_W1S" , 0x107000000aa38ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP8_IP3_W1S" , 0x107000000aa40ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP9_IP3_W1S" , 0x107000000aa48ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU_EN2_PP0_IP4" , 0x107000000a400ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP1_IP4" , 0x107000000a408ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP2_IP4" , 0x107000000a410ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP3_IP4" , 0x107000000a418ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP4_IP4" , 0x107000000a420ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP5_IP4" , 0x107000000a428ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP6_IP4" , 0x107000000a430ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP7_IP4" , 0x107000000a438ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP8_IP4" , 0x107000000a440ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP9_IP4" , 0x107000000a448ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU_EN2_PP0_IP4_W1C" , 0x107000000cc00ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP1_IP4_W1C" , 0x107000000cc08ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP2_IP4_W1C" , 0x107000000cc10ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP3_IP4_W1C" , 0x107000000cc18ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP4_IP4_W1C" , 0x107000000cc20ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP5_IP4_W1C" , 0x107000000cc28ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP6_IP4_W1C" , 0x107000000cc30ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP7_IP4_W1C" , 0x107000000cc38ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP8_IP4_W1C" , 0x107000000cc40ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP9_IP4_W1C" , 0x107000000cc48ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU_EN2_PP0_IP4_W1S" , 0x107000000ac00ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP1_IP4_W1S" , 0x107000000ac08ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP2_IP4_W1S" , 0x107000000ac10ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP3_IP4_W1S" , 0x107000000ac18ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP4_IP4_W1S" , 0x107000000ac20ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP5_IP4_W1S" , 0x107000000ac28ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP6_IP4_W1S" , 0x107000000ac30ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP7_IP4_W1S" , 0x107000000ac38ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP8_IP4_W1S" , 0x107000000ac40ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_EN2_PP9_IP4_W1S" , 0x107000000ac48ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT10_EN0" , 0x10700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT11_EN0" , 0x10700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT12_EN0" , 0x10700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT13_EN0" , 0x10700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT14_EN0" , 0x10700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT15_EN0" , 0x10700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT33_EN0" , 0x1070000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT8_EN0_W1C" , 0x1070000002280ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT9_EN0_W1C" , 0x1070000002290ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT10_EN0_W1C" , 0x10700000022a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT11_EN0_W1C" , 0x10700000022b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT12_EN0_W1C" , 0x10700000022c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT13_EN0_W1C" , 0x10700000022d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT14_EN0_W1C" , 0x10700000022e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT15_EN0_W1C" , 0x10700000022f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT16_EN0_W1C" , 0x1070000002300ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT17_EN0_W1C" , 0x1070000002310ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT18_EN0_W1C" , 0x1070000002320ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT19_EN0_W1C" , 0x1070000002330ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT33_EN0_W1C" , 0x1070000002410ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT8_EN0_W1S" , 0x1070000006280ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT9_EN0_W1S" , 0x1070000006290ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT10_EN0_W1S" , 0x10700000062a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT11_EN0_W1S" , 0x10700000062b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT12_EN0_W1S" , 0x10700000062c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT13_EN0_W1S" , 0x10700000062d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT14_EN0_W1S" , 0x10700000062e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT15_EN0_W1S" , 0x10700000062f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT16_EN0_W1S" , 0x1070000006300ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT17_EN0_W1S" , 0x1070000006310ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT18_EN0_W1S" , 0x1070000006320ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT19_EN0_W1S" , 0x1070000006330ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT33_EN0_W1S" , 0x1070000006410ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT10_EN1" , 0x10700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT11_EN1" , 0x10700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT12_EN1" , 0x10700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT13_EN1" , 0x10700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT14_EN1" , 0x10700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT15_EN1" , 0x10700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT33_EN1" , 0x1070000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT8_EN1_W1C" , 0x1070000002288ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT9_EN1_W1C" , 0x1070000002298ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT10_EN1_W1C" , 0x10700000022a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT11_EN1_W1C" , 0x10700000022b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT12_EN1_W1C" , 0x10700000022c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT13_EN1_W1C" , 0x10700000022d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT14_EN1_W1C" , 0x10700000022e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT15_EN1_W1C" , 0x10700000022f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT16_EN1_W1C" , 0x1070000002308ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT17_EN1_W1C" , 0x1070000002318ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT18_EN1_W1C" , 0x1070000002328ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT19_EN1_W1C" , 0x1070000002338ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT33_EN1_W1C" , 0x1070000002418ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT8_EN1_W1S" , 0x1070000006288ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT9_EN1_W1S" , 0x1070000006298ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT10_EN1_W1S" , 0x10700000062a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT11_EN1_W1S" , 0x10700000062b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT12_EN1_W1S" , 0x10700000062c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT13_EN1_W1S" , 0x10700000062d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT14_EN1_W1S" , 0x10700000062e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT15_EN1_W1S" , 0x10700000062f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT16_EN1_W1S" , 0x1070000006308ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT17_EN1_W1S" , 0x1070000006318ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT18_EN1_W1S" , 0x1070000006328ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT19_EN1_W1S" , 0x1070000006338ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT33_EN1_W1S" , 0x1070000006418ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT4_EN4_0" , 0x1070000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT5_EN4_0" , 0x1070000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT6_EN4_0" , 0x1070000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT7_EN4_0" , 0x1070000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT8_EN4_0" , 0x1070000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT9_EN4_0" , 0x1070000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU_INT0_EN4_0_W1C" , 0x1070000002c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT1_EN4_0_W1C" , 0x1070000002c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT2_EN4_0_W1C" , 0x1070000002ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT3_EN4_0_W1C" , 0x1070000002cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT4_EN4_0_W1C" , 0x1070000002cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT5_EN4_0_W1C" , 0x1070000002cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT6_EN4_0_W1C" , 0x1070000002ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT7_EN4_0_W1C" , 0x1070000002cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT8_EN4_0_W1C" , 0x1070000002d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT9_EN4_0_W1C" , 0x1070000002d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU_INT0_EN4_0_W1S" , 0x1070000006c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT1_EN4_0_W1S" , 0x1070000006c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT2_EN4_0_W1S" , 0x1070000006ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT3_EN4_0_W1S" , 0x1070000006cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT4_EN4_0_W1S" , 0x1070000006cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT5_EN4_0_W1S" , 0x1070000006cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT6_EN4_0_W1S" , 0x1070000006ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT7_EN4_0_W1S" , 0x1070000006cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT8_EN4_0_W1S" , 0x1070000006d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT9_EN4_0_W1S" , 0x1070000006d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT4_EN4_1" , 0x1070000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT5_EN4_1" , 0x1070000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT6_EN4_1" , 0x1070000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT7_EN4_1" , 0x1070000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT8_EN4_1" , 0x1070000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT9_EN4_1" , 0x1070000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU_INT0_EN4_1_W1C" , 0x1070000002c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT1_EN4_1_W1C" , 0x1070000002c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT2_EN4_1_W1C" , 0x1070000002ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT3_EN4_1_W1C" , 0x1070000002cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT4_EN4_1_W1C" , 0x1070000002cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT5_EN4_1_W1C" , 0x1070000002cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT6_EN4_1_W1C" , 0x1070000002ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT7_EN4_1_W1C" , 0x1070000002cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT8_EN4_1_W1C" , 0x1070000002d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT9_EN4_1_W1C" , 0x1070000002d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU_INT0_EN4_1_W1S" , 0x1070000006c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT1_EN4_1_W1S" , 0x1070000006c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT2_EN4_1_W1S" , 0x1070000006ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT3_EN4_1_W1S" , 0x1070000006cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT4_EN4_1_W1S" , 0x1070000006cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT5_EN4_1_W1S" , 0x1070000006cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT6_EN4_1_W1S" , 0x1070000006ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT7_EN4_1_W1S" , 0x1070000006cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT8_EN4_1_W1S" , 0x1070000006d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT9_EN4_1_W1S" , 0x1070000006d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT4_SUM4" , 0x1070000000c20ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT5_SUM4" , 0x1070000000c28ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT6_SUM4" , 0x1070000000c30ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT7_SUM4" , 0x1070000000c38ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT8_SUM4" , 0x1070000000c40ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT9_SUM4" , 0x1070000000c48ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU_INT33_SUM0" , 0x1070000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU_INT_DBG_SEL" , 0x10700000007d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR4" , 0x10700000006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR5" , 0x10700000006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR6" , 0x10700000006b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR7" , 0x10700000006b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR8" , 0x10700000006c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_CLR9" , 0x10700000006c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE4" , 0x10700000005a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE5" , 0x10700000005a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE6" , 0x10700000005b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE7" , 0x10700000005b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE8" , 0x10700000005c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_POKE9" , 0x10700000005c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU_QLM0" , 0x1070000000780ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU_QLM1" , 0x1070000000788ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU_QLM2" , 0x1070000000790ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU_SOFT_PRST2" , 0x10700000007d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU_SOFT_PRST3" , 0x10700000007e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU_SUM1_IO0_INT" , 0x1070000008600ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU_SUM1_IO1_INT" , 0x1070000008608ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU_SUM1_PP0_IP2" , 0x1070000008000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP1_IP2" , 0x1070000008008ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP2_IP2" , 0x1070000008010ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP3_IP2" , 0x1070000008018ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP4_IP2" , 0x1070000008020ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP5_IP2" , 0x1070000008028ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP6_IP2" , 0x1070000008030ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP7_IP2" , 0x1070000008038ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP8_IP2" , 0x1070000008040ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP9_IP2" , 0x1070000008048ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU_SUM1_PP0_IP3" , 0x1070000008200ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM1_PP1_IP3" , 0x1070000008208ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM1_PP2_IP3" , 0x1070000008210ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM1_PP3_IP3" , 0x1070000008218ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM1_PP4_IP3" , 0x1070000008220ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM1_PP5_IP3" , 0x1070000008228ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM1_PP6_IP3" , 0x1070000008230ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM1_PP7_IP3" , 0x1070000008238ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM1_PP8_IP3" , 0x1070000008240ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM1_PP9_IP3" , 0x1070000008248ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU_SUM1_PP0_IP4" , 0x1070000008400ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM1_PP1_IP4" , 0x1070000008408ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM1_PP2_IP4" , 0x1070000008410ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM1_PP3_IP4" , 0x1070000008418ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM1_PP4_IP4" , 0x1070000008420ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM1_PP5_IP4" , 0x1070000008428ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM1_PP6_IP4" , 0x1070000008430ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM1_PP7_IP4" , 0x1070000008438ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM1_PP8_IP4" , 0x1070000008440ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM1_PP9_IP4" , 0x1070000008448ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU_SUM2_IO0_INT" , 0x1070000008e00ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU_SUM2_IO1_INT" , 0x1070000008e08ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU_SUM2_PP0_IP2" , 0x1070000008800ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP1_IP2" , 0x1070000008808ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP2_IP2" , 0x1070000008810ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP3_IP2" , 0x1070000008818ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP4_IP2" , 0x1070000008820ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP5_IP2" , 0x1070000008828ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP6_IP2" , 0x1070000008830ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP7_IP2" , 0x1070000008838ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP8_IP2" , 0x1070000008840ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP9_IP2" , 0x1070000008848ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU_SUM2_PP0_IP3" , 0x1070000008a00ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_SUM2_PP1_IP3" , 0x1070000008a08ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_SUM2_PP2_IP3" , 0x1070000008a10ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_SUM2_PP3_IP3" , 0x1070000008a18ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_SUM2_PP4_IP3" , 0x1070000008a20ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_SUM2_PP5_IP3" , 0x1070000008a28ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_SUM2_PP6_IP3" , 0x1070000008a30ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_SUM2_PP7_IP3" , 0x1070000008a38ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_SUM2_PP8_IP3" , 0x1070000008a40ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_SUM2_PP9_IP3" , 0x1070000008a48ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU_SUM2_PP0_IP4" , 0x1070000008c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_SUM2_PP1_IP4" , 0x1070000008c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_SUM2_PP2_IP4" , 0x1070000008c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_SUM2_PP3_IP4" , 0x1070000008c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_SUM2_PP4_IP4" , 0x1070000008c20ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_SUM2_PP5_IP4" , 0x1070000008c28ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_SUM2_PP6_IP4" , 0x1070000008c30ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_SUM2_PP7_IP4" , 0x1070000008c38ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_SUM2_PP8_IP4" , 0x1070000008c40ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_SUM2_PP9_IP4" , 0x1070000008c48ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_TIM4" , 0x10700000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_TIM5" , 0x10700000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_TIM6" , 0x10700000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_TIM7" , 0x10700000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_TIM8" , 0x10700000004c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_TIM9" , 0x10700000004c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU_TIM_MULTI_CAST" , 0x107000000c200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"DFA_BIST0" , 0x11800370007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
- {"DFA_BIST1" , 0x11800370007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
- {"DFA_CONFIG" , 0x1180037000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
- {"DFA_CONTROL" , 0x1180037000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"DFA_DEBUG0" , 0x1180037000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
- {"DFA_DEBUG1" , 0x1180037000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
- {"DFA_DEBUG2" , 0x1180037000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
- {"DFA_DEBUG3" , 0x1180037000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"DFA_DTCFADR" , 0x1180037000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
- {"DFA_ERROR" , 0x1180037000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
- {"DFA_INTMSK" , 0x1180037000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
- {"DFA_MEMHIDAT" , 0x1370700000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"DFA_PFC0_CNT" , 0x1180037000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
- {"DFA_PFC0_CTL" , 0x1180037000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
- {"DFA_PFC1_CNT" , 0x11800370000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
- {"DFA_PFC1_CTL" , 0x1180037000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
- {"DFA_PFC2_CNT" , 0x11800370000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
- {"DFA_PFC2_CTL" , 0x11800370000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
- {"DFA_PFC3_CNT" , 0x11800370000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
- {"DFA_PFC3_CTL" , 0x11800370000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
- {"DFA_PFC_GCTL" , 0x1180037000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
- {"DFM_CHAR_CTL" , 0x11800d4000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
- {"DFM_CHAR_MASK0" , 0x11800d4000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
- {"DFM_CHAR_MASK2" , 0x11800d4000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
- {"DFM_CHAR_MASK4" , 0x11800d4000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
- {"DFM_COMP_CTL2" , 0x11800d40001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
- {"DFM_CONFIG" , 0x11800d4000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
- {"DFM_CONTROL" , 0x11800d4000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
- {"DFM_DLL_CTL2" , 0x11800d40001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
- {"DFM_DLL_CTL3" , 0x11800d4000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
- {"DFM_FCLK_CNT" , 0x11800d40001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
- {"DFM_FNT_BIST" , 0x11800d40007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
- {"DFM_FNT_CTL" , 0x11800d4000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
- {"DFM_FNT_IENA" , 0x11800d4000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
- {"DFM_FNT_SCLK" , 0x11800d4000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
- {"DFM_FNT_STAT" , 0x11800d4000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
- {"DFM_IFB_CNT" , 0x11800d40001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
- {"DFM_MODEREG_PARAMS0" , 0x11800d40001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
- {"DFM_MODEREG_PARAMS1" , 0x11800d4000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
- {"DFM_OPS_CNT" , 0x11800d40001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
- {"DFM_PHY_CTL" , 0x11800d4000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
- {"DFM_RESET_CTL" , 0x11800d4000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
- {"DFM_RLEVEL_CTL" , 0x11800d40002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
- {"DFM_RLEVEL_DBG" , 0x11800d40002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
- {"DFM_RLEVEL_RANK0" , 0x11800d4000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"DFM_RLEVEL_RANK1" , 0x11800d4000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
- {"DFM_RODT_MASK" , 0x11800d4000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
- {"DFM_SLOT_CTL0" , 0x11800d40001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
- {"DFM_SLOT_CTL1" , 0x11800d4000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
- {"DFM_TIMING_PARAMS0" , 0x11800d4000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
- {"DFM_TIMING_PARAMS1" , 0x11800d40001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
- {"DFM_WLEVEL_CTL" , 0x11800d4000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
- {"DFM_WLEVEL_DBG" , 0x11800d4000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
- {"DFM_WLEVEL_RANK0" , 0x11800d40002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"DFM_WLEVEL_RANK1" , 0x11800d40002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
- {"DFM_WODT_MASK" , 0x11800d40001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
- {"DPI_BIST_STATUS" , 0x1df0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"DPI_CTL" , 0x1df0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
- {"DPI_DMA0_COUNTS" , 0x1df0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"DPI_DMA1_COUNTS" , 0x1df0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"DPI_DMA2_COUNTS" , 0x1df0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"DPI_DMA3_COUNTS" , 0x1df0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"DPI_DMA4_COUNTS" , 0x1df0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"DPI_DMA5_COUNTS" , 0x1df0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"DPI_DMA6_COUNTS" , 0x1df0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"DPI_DMA7_COUNTS" , 0x1df0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"DPI_DMA0_DBELL" , 0x1df0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"DPI_DMA1_DBELL" , 0x1df0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"DPI_DMA2_DBELL" , 0x1df0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"DPI_DMA3_DBELL" , 0x1df0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"DPI_DMA4_DBELL" , 0x1df0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"DPI_DMA5_DBELL" , 0x1df0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"DPI_DMA6_DBELL" , 0x1df0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"DPI_DMA7_DBELL" , 0x1df0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"DPI_DMA0_ERR_RSP_STATUS" , 0x1df0000000a80ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"DPI_DMA1_ERR_RSP_STATUS" , 0x1df0000000a88ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"DPI_DMA2_ERR_RSP_STATUS" , 0x1df0000000a90ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"DPI_DMA3_ERR_RSP_STATUS" , 0x1df0000000a98ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"DPI_DMA4_ERR_RSP_STATUS" , 0x1df0000000aa0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"DPI_DMA5_ERR_RSP_STATUS" , 0x1df0000000aa8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"DPI_DMA6_ERR_RSP_STATUS" , 0x1df0000000ab0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"DPI_DMA7_ERR_RSP_STATUS" , 0x1df0000000ab8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"DPI_DMA0_IBUFF_SADDR" , 0x1df0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"DPI_DMA1_IBUFF_SADDR" , 0x1df0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"DPI_DMA2_IBUFF_SADDR" , 0x1df0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"DPI_DMA3_IBUFF_SADDR" , 0x1df0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"DPI_DMA4_IBUFF_SADDR" , 0x1df00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"DPI_DMA5_IBUFF_SADDR" , 0x1df00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"DPI_DMA6_IBUFF_SADDR" , 0x1df00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"DPI_DMA7_IBUFF_SADDR" , 0x1df00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"DPI_DMA0_IFLIGHT" , 0x1df0000000a00ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"DPI_DMA1_IFLIGHT" , 0x1df0000000a08ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"DPI_DMA2_IFLIGHT" , 0x1df0000000a10ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"DPI_DMA3_IFLIGHT" , 0x1df0000000a18ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"DPI_DMA4_IFLIGHT" , 0x1df0000000a20ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"DPI_DMA5_IFLIGHT" , 0x1df0000000a28ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"DPI_DMA6_IFLIGHT" , 0x1df0000000a30ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"DPI_DMA7_IFLIGHT" , 0x1df0000000a38ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"DPI_DMA0_NADDR" , 0x1df0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"DPI_DMA1_NADDR" , 0x1df0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"DPI_DMA2_NADDR" , 0x1df0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"DPI_DMA3_NADDR" , 0x1df0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"DPI_DMA4_NADDR" , 0x1df00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"DPI_DMA5_NADDR" , 0x1df00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"DPI_DMA6_NADDR" , 0x1df00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"DPI_DMA7_NADDR" , 0x1df00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"DPI_DMA0_REQBNK0" , 0x1df0000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"DPI_DMA1_REQBNK0" , 0x1df0000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"DPI_DMA2_REQBNK0" , 0x1df0000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"DPI_DMA3_REQBNK0" , 0x1df0000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"DPI_DMA4_REQBNK0" , 0x1df0000000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"DPI_DMA5_REQBNK0" , 0x1df0000000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"DPI_DMA6_REQBNK0" , 0x1df0000000430ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"DPI_DMA7_REQBNK0" , 0x1df0000000438ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"DPI_DMA0_REQBNK1" , 0x1df0000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"DPI_DMA1_REQBNK1" , 0x1df0000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"DPI_DMA2_REQBNK1" , 0x1df0000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"DPI_DMA3_REQBNK1" , 0x1df0000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"DPI_DMA4_REQBNK1" , 0x1df00000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"DPI_DMA5_REQBNK1" , 0x1df00000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"DPI_DMA6_REQBNK1" , 0x1df00000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"DPI_DMA7_REQBNK1" , 0x1df00000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"DPI_DMA_CONTROL" , 0x1df0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"DPI_DMA_ENG0_EN" , 0x1df0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"DPI_DMA_ENG1_EN" , 0x1df0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"DPI_DMA_ENG2_EN" , 0x1df0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"DPI_DMA_ENG3_EN" , 0x1df0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"DPI_DMA_ENG4_EN" , 0x1df00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"DPI_DMA_ENG5_EN" , 0x1df00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"DPI_ENG0_BUF" , 0x1df0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"DPI_ENG1_BUF" , 0x1df0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"DPI_ENG2_BUF" , 0x1df0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"DPI_ENG3_BUF" , 0x1df0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"DPI_ENG4_BUF" , 0x1df00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"DPI_ENG5_BUF" , 0x1df00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"DPI_INFO_REG" , 0x1df0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"DPI_INT_EN" , 0x1df0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"DPI_INT_REG" , 0x1df0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"DPI_NCB0_CFG" , 0x1df0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"DPI_PINT_INFO" , 0x1df0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"DPI_PKT_ERR_RSP" , 0x1df0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"DPI_REQ_ERR_RSP" , 0x1df0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"DPI_REQ_ERR_RSP_EN" , 0x1df0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"DPI_REQ_ERR_RST" , 0x1df0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"DPI_REQ_ERR_RST_EN" , 0x1df0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"DPI_REQ_ERR_SKIP_COMP" , 0x1df0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"DPI_REQ_GBL_EN" , 0x1df0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"DPI_SLI_PRT0_CFG" , 0x1df0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"DPI_SLI_PRT1_CFG" , 0x1df0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"DPI_SLI_PRT2_CFG" , 0x1df0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"DPI_SLI_PRT3_CFG" , 0x1df0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"DPI_SLI_PRT0_ERR" , 0x1df0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"DPI_SLI_PRT1_ERR" , 0x1df0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"DPI_SLI_PRT2_ERR" , 0x1df0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"DPI_SLI_PRT3_ERR" , 0x1df0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"DPI_SLI_PRT0_ERR_INFO" , 0x1df0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"DPI_SLI_PRT1_ERR_INFO" , 0x1df0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"DPI_SLI_PRT2_ERR_INFO" , 0x1df0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"DPI_SLI_PRT3_ERR_INFO" , 0x1df0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"FPA_ADDR_RANGE_ERROR" , 0x1180028000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
- {"FPA_PACKET_THRESHOLD" , 0x1180028000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
- {"FPA_POOL0_END_ADDR" , 0x1180028000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"FPA_POOL1_END_ADDR" , 0x1180028000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"FPA_POOL2_END_ADDR" , 0x1180028000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"FPA_POOL3_END_ADDR" , 0x1180028000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"FPA_POOL4_END_ADDR" , 0x1180028000378ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"FPA_POOL5_END_ADDR" , 0x1180028000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"FPA_POOL6_END_ADDR" , 0x1180028000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"FPA_POOL7_END_ADDR" , 0x1180028000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
- {"FPA_POOL0_START_ADDR" , 0x1180028000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"FPA_POOL1_START_ADDR" , 0x1180028000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"FPA_POOL2_START_ADDR" , 0x1180028000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"FPA_POOL3_START_ADDR" , 0x1180028000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"FPA_POOL4_START_ADDR" , 0x1180028000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"FPA_POOL5_START_ADDR" , 0x1180028000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"FPA_POOL6_START_ADDR" , 0x1180028000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"FPA_POOL7_START_ADDR" , 0x1180028000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
- {"FPA_POOL0_THRESHOLD" , 0x1180028000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"FPA_POOL1_THRESHOLD" , 0x1180028000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"FPA_POOL2_THRESHOLD" , 0x1180028000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"FPA_POOL3_THRESHOLD" , 0x1180028000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"FPA_POOL4_THRESHOLD" , 0x1180028000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"FPA_POOL5_THRESHOLD" , 0x1180028000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"FPA_POOL6_THRESHOLD" , 0x1180028000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"FPA_POOL7_THRESHOLD" , 0x1180028000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
- {"FPA_WQE_THRESHOLD" , 0x1180028000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX1_CLK_EN" , 0x11800100007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
- {"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX1_HG2_CONTROL" , 0x1180010000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX1_INF_MODE" , 0x11800100007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
- {"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"GMX1_PRT000_CBFC_CTL" , 0x1180010000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX1_RX000_ADR_CAM4" , 0x11800100001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX1_RX001_ADR_CAM4" , 0x11800100009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX1_RX002_ADR_CAM4" , 0x11800100011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX1_RX003_ADR_CAM4" , 0x11800100019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX1_RX000_ADR_CAM5" , 0x11800100001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX1_RX001_ADR_CAM5" , 0x11800100009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX1_RX002_ADR_CAM5" , 0x11800100011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX1_RX003_ADR_CAM5" , 0x11800100019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
- {"GMX0_RX000_ADR_CAM_ALL_EN" , 0x1180008000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX0_RX001_ADR_CAM_ALL_EN" , 0x1180008000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX0_RX002_ADR_CAM_ALL_EN" , 0x1180008001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX0_RX003_ADR_CAM_ALL_EN" , 0x1180008001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX1_RX000_ADR_CAM_ALL_EN" , 0x1180010000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX1_RX001_ADR_CAM_ALL_EN" , 0x1180010000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX1_RX002_ADR_CAM_ALL_EN" , 0x1180010001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX1_RX003_ADR_CAM_ALL_EN" , 0x1180010001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180010000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180010000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180010001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180010001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
- {"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"GMX1_RX_HG2_STATUS" , 0x1180010000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"GMX1_RX_PRT_INFO" , 0x11800100004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"GMX1_RX_XAUI_BAD_COL" , 0x1180010000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"GMX1_RX_XAUI_CTL" , 0x1180010000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX1_SMAC001" , 0x1180010000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX1_SMAC003" , 0x1180010001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
- {"GMX0_SOFT_BIST" , 0x11800080007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"GMX1_SOFT_BIST" , 0x11800100007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"GMX0_TB_REG" , 0x11800080007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"GMX1_TB_REG" , 0x11800100007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX1_TX001_APPEND" , 0x1180010000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX1_TX003_APPEND" , 0x1180010001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX1_TX001_BURST" , 0x1180010000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX1_TX003_BURST" , 0x1180010001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"GMX0_TX000_CBFC_XOFF" , 0x11800080005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"GMX1_TX000_CBFC_XOFF" , 0x11800100005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"GMX0_TX000_CBFC_XON" , 0x11800080005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"GMX1_TX000_CBFC_XON" , 0x11800100005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX1_TX001_CTL" , 0x1180010000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX1_TX003_CTL" , 0x1180010001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GMX1_TX001_MIN_PKT" , 0x1180010000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GMX1_TX003_MIN_PKT" , 0x1180010001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"GMX1_TX001_PAUSE_TOGO" , 0x1180010000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"GMX1_TX003_PAUSE_TOGO" , 0x1180010001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"GMX1_TX001_PAUSE_ZERO" , 0x1180010000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"GMX1_TX003_PAUSE_ZERO" , 0x1180010001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"GMX0_TX003_SGMII_CTL" , 0x1180008001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"GMX1_TX000_SGMII_CTL" , 0x1180010000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"GMX1_TX001_SGMII_CTL" , 0x1180010000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"GMX1_TX002_SGMII_CTL" , 0x1180010001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"GMX1_TX003_SGMII_CTL" , 0x1180010001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"GMX1_TX001_SLOT" , 0x1180010000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"GMX1_TX003_SLOT" , 0x1180010001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"GMX1_TX001_SOFT_PAUSE" , 0x1180010000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"GMX1_TX003_SOFT_PAUSE" , 0x1180010001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"GMX1_TX001_STAT0" , 0x1180010000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"GMX1_TX003_STAT0" , 0x1180010001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"GMX1_TX001_STAT1" , 0x1180010000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"GMX1_TX003_STAT1" , 0x1180010001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"GMX1_TX001_STAT2" , 0x1180010000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"GMX1_TX003_STAT2" , 0x1180010001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"GMX1_TX001_STAT3" , 0x1180010000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"GMX1_TX003_STAT3" , 0x1180010001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"GMX1_TX000_STAT4" , 0x11800100002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"GMX1_TX001_STAT4" , 0x1180010000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"GMX1_TX002_STAT4" , 0x11800100012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"GMX1_TX003_STAT4" , 0x1180010001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"GMX1_TX000_STAT5" , 0x11800100002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"GMX1_TX001_STAT5" , 0x1180010000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"GMX1_TX002_STAT5" , 0x11800100012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"GMX1_TX003_STAT5" , 0x1180010001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"GMX1_TX000_STAT6" , 0x11800100002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"GMX1_TX001_STAT6" , 0x1180010000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"GMX1_TX002_STAT6" , 0x11800100012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"GMX1_TX003_STAT6" , 0x1180010001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"GMX1_TX000_STAT7" , 0x11800100002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"GMX1_TX001_STAT7" , 0x1180010000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"GMX1_TX002_STAT7" , 0x11800100012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"GMX1_TX003_STAT7" , 0x1180010001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"GMX1_TX000_STAT8" , 0x11800100002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"GMX1_TX001_STAT8" , 0x1180010000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"GMX1_TX002_STAT8" , 0x11800100012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"GMX1_TX003_STAT8" , 0x1180010001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"GMX1_TX000_STAT9" , 0x11800100002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"GMX1_TX001_STAT9" , 0x1180010000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"GMX1_TX002_STAT9" , 0x11800100012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"GMX1_TX003_STAT9" , 0x1180010001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"GMX1_TX001_STATS_CTL" , 0x1180010000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"GMX1_TX003_STATS_CTL" , 0x1180010001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"GMX1_TX001_THRESH" , 0x1180010000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"GMX1_TX003_THRESH" , 0x1180010001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"GMX1_TX_BP" , 0x11800100004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"GMX1_TX_CORRUPT" , 0x11800100004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"GMX1_TX_HG2_REG1" , 0x1180010000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"GMX1_TX_HG2_REG2" , 0x1180010000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"GMX1_TX_LFSR" , 0x11800100004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"GMX1_TX_OVR_BP" , 0x11800100004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"GMX1_TX_XAUI_CTL" , 0x1180010000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"GMX1_XAUI_EXT_LOOPBACK" , 0x1180010000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"GPIO_CLK_QLM0" , 0x10700000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"GPIO_CLK_QLM1" , 0x10700000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
- {"GPIO_PIN_ENA" , 0x10700000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"GPIO_XBIT_CFG16" , 0x1070000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"GPIO_XBIT_CFG17" , 0x1070000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"GPIO_XBIT_CFG18" , 0x1070000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"GPIO_XBIT_CFG19" , 0x1070000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"IOB_TO_CMB_CREDITS" , 0x11800f00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT16_BP_PAGE_CNT" , 0x14f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT17_BP_PAGE_CNT" , 0x14f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT18_BP_PAGE_CNT" , 0x14f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT19_BP_PAGE_CNT" , 0x14f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
- {"IPD_PORT36_BP_PAGE_CNT2" , 0x14f0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
- {"IPD_PORT37_BP_PAGE_CNT2" , 0x14f0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
- {"IPD_PORT38_BP_PAGE_CNT2" , 0x14f0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
- {"IPD_PORT39_BP_PAGE_CNT2" , 0x14f0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
- {"IPD_PORT40_BP_PAGE_CNT3" , 0x14f00000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"IPD_PORT41_BP_PAGE_CNT3" , 0x14f00000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"IPD_PORT44_BP_PAGE_CNT3" , 0x14f00000003f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"IPD_PORT45_BP_PAGE_CNT3" , 0x14f00000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"IPD_PORT46_BP_PAGE_CNT3" , 0x14f0000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"IPD_PORT47_BP_PAGE_CNT3" , 0x14f0000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
- {"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14f0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
- {"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14f0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
- {"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14f0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
- {"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14f00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
- {"IPD_PORT_BP_COUNTERS3_PAIR40", 0x14f00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"IPD_PORT_BP_COUNTERS3_PAIR41", 0x14f00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"IPD_PORT_BP_COUNTERS3_PAIR42", 0x14f00000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"IPD_PORT_BP_COUNTERS3_PAIR43", 0x14f00000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
- {"IPD_PORT_BP_COUNTERS4_PAIR44", 0x14f0000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"IPD_PORT_BP_COUNTERS4_PAIR45", 0x14f0000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"IPD_PORT_BP_COUNTERS4_PAIR46", 0x14f0000000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"IPD_PORT_BP_COUNTERS4_PAIR47", 0x14f0000000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14f0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14f0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14f0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14f0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_128_CNT" , 0x14f0000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_129_CNT" , 0x14f0000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_130_CNT" , 0x14f0000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_131_CNT" , 0x14f0000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_132_CNT" , 0x14f0000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_133_CNT" , 0x14f0000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_134_CNT" , 0x14f0000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_135_CNT" , 0x14f0000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_136_CNT" , 0x14f0000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_137_CNT" , 0x14f0000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_138_CNT" , 0x14f0000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_139_CNT" , 0x14f0000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_140_CNT" , 0x14f0000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_141_CNT" , 0x14f0000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_142_CNT" , 0x14f0000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_143_CNT" , 0x14f0000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_144_CNT" , 0x14f0000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_145_CNT" , 0x14f0000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_146_CNT" , 0x14f0000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_147_CNT" , 0x14f0000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_148_CNT" , 0x14f0000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_149_CNT" , 0x14f0000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_150_CNT" , 0x14f0000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_151_CNT" , 0x14f0000000d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_152_CNT" , 0x14f0000000d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_153_CNT" , 0x14f0000000d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_154_CNT" , 0x14f0000000d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_155_CNT" , 0x14f0000000d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_156_CNT" , 0x14f0000000d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_157_CNT" , 0x14f0000000d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_158_CNT" , 0x14f0000000d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_159_CNT" , 0x14f0000000d80ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_256_CNT" , 0x14f0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_257_CNT" , 0x14f0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_258_CNT" , 0x14f0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_259_CNT" , 0x14f00000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_260_CNT" , 0x14f00000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_261_CNT" , 0x14f00000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_262_CNT" , 0x14f00000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_263_CNT" , 0x14f00000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_264_CNT" , 0x14f00000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_265_CNT" , 0x14f00000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_266_CNT" , 0x14f00000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_267_CNT" , 0x14f00000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_268_CNT" , 0x14f00000010e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_269_CNT" , 0x14f00000010f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_270_CNT" , 0x14f00000010f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_271_CNT" , 0x14f0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_272_CNT" , 0x14f0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_273_CNT" , 0x14f0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_274_CNT" , 0x14f0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_275_CNT" , 0x14f0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_276_CNT" , 0x14f0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_277_CNT" , 0x14f0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_278_CNT" , 0x14f0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_279_CNT" , 0x14f0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_280_CNT" , 0x14f0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_281_CNT" , 0x14f0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_282_CNT" , 0x14f0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_283_CNT" , 0x14f0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_284_CNT" , 0x14f0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_285_CNT" , 0x14f0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_286_CNT" , 0x14f0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_287_CNT" , 0x14f0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_320_CNT" , 0x14f0000001288ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_321_CNT" , 0x14f0000001290ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_322_CNT" , 0x14f0000001298ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_323_CNT" , 0x14f00000012a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_324_CNT" , 0x14f00000012a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_325_CNT" , 0x14f00000012b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_326_CNT" , 0x14f00000012b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_327_CNT" , 0x14f00000012c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_328_CNT" , 0x14f00000012c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_329_CNT" , 0x14f00000012d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_330_CNT" , 0x14f00000012d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_331_CNT" , 0x14f00000012e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_332_CNT" , 0x14f00000012e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_333_CNT" , 0x14f00000012f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_334_CNT" , 0x14f00000012f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_335_CNT" , 0x14f0000001300ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_352_CNT" , 0x14f0000001388ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_353_CNT" , 0x14f0000001390ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_354_CNT" , 0x14f0000001398ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_355_CNT" , 0x14f00000013a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_356_CNT" , 0x14f00000013a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_357_CNT" , 0x14f00000013b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_358_CNT" , 0x14f00000013b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_359_CNT" , 0x14f00000013c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_360_CNT" , 0x14f00000013c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_361_CNT" , 0x14f00000013d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_362_CNT" , 0x14f00000013d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_363_CNT" , 0x14f00000013e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_364_CNT" , 0x14f00000013e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_365_CNT" , 0x14f00000013f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_366_CNT" , 0x14f00000013f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_367_CNT" , 0x14f0000001400ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_368_CNT" , 0x14f0000001408ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_369_CNT" , 0x14f0000001410ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_370_CNT" , 0x14f0000001418ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_371_CNT" , 0x14f0000001420ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_372_CNT" , 0x14f0000001428ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_373_CNT" , 0x14f0000001430ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_374_CNT" , 0x14f0000001438ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_375_CNT" , 0x14f0000001440ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_376_CNT" , 0x14f0000001448ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_377_CNT" , 0x14f0000001450ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_378_CNT" , 0x14f0000001458ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_379_CNT" , 0x14f0000001460ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_380_CNT" , 0x14f0000001468ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_381_CNT" , 0x14f0000001470ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_382_CNT" , 0x14f0000001478ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_383_CNT" , 0x14f0000001480ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"IPD_PORT_QOS_INT2" , 0x14f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"IPD_PORT_QOS_INT5" , 0x14f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"IPD_PORT_QOS_INT_ENB2" , 0x14f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"IPD_PORT_QOS_INT_ENB5" , 0x14f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
- {"IPD_RED_PORT_ENABLE2" , 0x14f00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"L2C_BIG_CTL" , 0x1180080800030ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"L2C_BST" , 0x11800808007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"L2C_BST_MEM0" , 0x1180080c007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"L2C_BST_TDT0" , 0x1180080a007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"L2C_BST_TTG0" , 0x1180080a007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"L2C_COP0_MAP0" , 0x1180080940000ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1" , 0x1180080940008ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2" , 0x1180080940010ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP3" , 0x1180080940018ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP4" , 0x1180080940020ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP5" , 0x1180080940028ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP6" , 0x1180080940030ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP7" , 0x1180080940038ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP8" , 0x1180080940040ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP9" , 0x1180080940048ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP10" , 0x1180080940050ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP11" , 0x1180080940058ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP12" , 0x1180080940060ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP13" , 0x1180080940068ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP14" , 0x1180080940070ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP15" , 0x1180080940078ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16" , 0x1180080940080ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP17" , 0x1180080940088ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP18" , 0x1180080940090ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP19" , 0x1180080940098ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP20" , 0x11800809400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP21" , 0x11800809400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP22" , 0x11800809400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP23" , 0x11800809400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP24" , 0x11800809400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP25" , 0x11800809400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP26" , 0x11800809400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP27" , 0x11800809400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP28" , 0x11800809400e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP29" , 0x11800809400e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP30" , 0x11800809400f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP31" , 0x11800809400f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP32" , 0x1180080940100ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP33" , 0x1180080940108ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP34" , 0x1180080940110ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP35" , 0x1180080940118ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP36" , 0x1180080940120ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP37" , 0x1180080940128ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP38" , 0x1180080940130ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP39" , 0x1180080940138ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP40" , 0x1180080940140ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP41" , 0x1180080940148ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP42" , 0x1180080940150ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP43" , 0x1180080940158ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP44" , 0x1180080940160ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP45" , 0x1180080940168ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP46" , 0x1180080940170ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP47" , 0x1180080940178ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP48" , 0x1180080940180ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP49" , 0x1180080940188ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP50" , 0x1180080940190ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP51" , 0x1180080940198ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP52" , 0x11800809401a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP53" , 0x11800809401a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP54" , 0x11800809401b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP55" , 0x11800809401b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP56" , 0x11800809401c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP57" , 0x11800809401c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP58" , 0x11800809401d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP59" , 0x11800809401d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP60" , 0x11800809401e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP61" , 0x11800809401e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP62" , 0x11800809401f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP63" , 0x11800809401f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP64" , 0x1180080940200ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP65" , 0x1180080940208ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP66" , 0x1180080940210ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP67" , 0x1180080940218ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP68" , 0x1180080940220ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP69" , 0x1180080940228ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP70" , 0x1180080940230ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP71" , 0x1180080940238ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP72" , 0x1180080940240ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP73" , 0x1180080940248ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP74" , 0x1180080940250ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP75" , 0x1180080940258ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP76" , 0x1180080940260ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP77" , 0x1180080940268ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP78" , 0x1180080940270ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP79" , 0x1180080940278ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP80" , 0x1180080940280ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP81" , 0x1180080940288ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP82" , 0x1180080940290ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP83" , 0x1180080940298ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP84" , 0x11800809402a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP85" , 0x11800809402a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP86" , 0x11800809402b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP87" , 0x11800809402b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP88" , 0x11800809402c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP89" , 0x11800809402c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP90" , 0x11800809402d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP91" , 0x11800809402d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP92" , 0x11800809402e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP93" , 0x11800809402e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP94" , 0x11800809402f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP95" , 0x11800809402f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP96" , 0x1180080940300ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP97" , 0x1180080940308ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP98" , 0x1180080940310ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP99" , 0x1180080940318ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP100" , 0x1180080940320ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP101" , 0x1180080940328ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP102" , 0x1180080940330ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP103" , 0x1180080940338ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP104" , 0x1180080940340ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP105" , 0x1180080940348ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP106" , 0x1180080940350ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP107" , 0x1180080940358ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP108" , 0x1180080940360ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP109" , 0x1180080940368ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP110" , 0x1180080940370ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP111" , 0x1180080940378ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP112" , 0x1180080940380ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP113" , 0x1180080940388ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP114" , 0x1180080940390ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP115" , 0x1180080940398ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP116" , 0x11800809403a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP117" , 0x11800809403a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP118" , 0x11800809403b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP119" , 0x11800809403b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP120" , 0x11800809403c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP121" , 0x11800809403c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP122" , 0x11800809403d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP123" , 0x11800809403d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP124" , 0x11800809403e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP125" , 0x11800809403e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP126" , 0x11800809403f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP127" , 0x11800809403f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP128" , 0x1180080940400ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP129" , 0x1180080940408ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP130" , 0x1180080940410ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP131" , 0x1180080940418ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP132" , 0x1180080940420ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP133" , 0x1180080940428ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP134" , 0x1180080940430ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP135" , 0x1180080940438ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP136" , 0x1180080940440ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP137" , 0x1180080940448ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP138" , 0x1180080940450ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP139" , 0x1180080940458ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP140" , 0x1180080940460ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP141" , 0x1180080940468ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP142" , 0x1180080940470ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP143" , 0x1180080940478ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP144" , 0x1180080940480ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP145" , 0x1180080940488ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP146" , 0x1180080940490ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP147" , 0x1180080940498ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP148" , 0x11800809404a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP149" , 0x11800809404a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP150" , 0x11800809404b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP151" , 0x11800809404b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP152" , 0x11800809404c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP153" , 0x11800809404c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP154" , 0x11800809404d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP155" , 0x11800809404d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP156" , 0x11800809404e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP157" , 0x11800809404e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP158" , 0x11800809404f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP159" , 0x11800809404f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP160" , 0x1180080940500ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP161" , 0x1180080940508ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP162" , 0x1180080940510ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP163" , 0x1180080940518ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP164" , 0x1180080940520ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP165" , 0x1180080940528ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP166" , 0x1180080940530ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP167" , 0x1180080940538ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP168" , 0x1180080940540ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP169" , 0x1180080940548ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP170" , 0x1180080940550ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP171" , 0x1180080940558ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP172" , 0x1180080940560ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP173" , 0x1180080940568ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP174" , 0x1180080940570ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP175" , 0x1180080940578ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP176" , 0x1180080940580ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP177" , 0x1180080940588ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP178" , 0x1180080940590ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP179" , 0x1180080940598ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP180" , 0x11800809405a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP181" , 0x11800809405a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP182" , 0x11800809405b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP183" , 0x11800809405b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP184" , 0x11800809405c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP185" , 0x11800809405c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP186" , 0x11800809405d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP187" , 0x11800809405d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP188" , 0x11800809405e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP189" , 0x11800809405e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP190" , 0x11800809405f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP191" , 0x11800809405f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP192" , 0x1180080940600ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP193" , 0x1180080940608ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP194" , 0x1180080940610ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP195" , 0x1180080940618ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP196" , 0x1180080940620ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP197" , 0x1180080940628ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP198" , 0x1180080940630ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP199" , 0x1180080940638ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP200" , 0x1180080940640ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP201" , 0x1180080940648ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP202" , 0x1180080940650ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP203" , 0x1180080940658ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP204" , 0x1180080940660ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP205" , 0x1180080940668ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP206" , 0x1180080940670ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP207" , 0x1180080940678ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP208" , 0x1180080940680ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP209" , 0x1180080940688ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP210" , 0x1180080940690ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP211" , 0x1180080940698ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP212" , 0x11800809406a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP213" , 0x11800809406a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP214" , 0x11800809406b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP215" , 0x11800809406b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP216" , 0x11800809406c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP217" , 0x11800809406c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP218" , 0x11800809406d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP219" , 0x11800809406d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP220" , 0x11800809406e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP221" , 0x11800809406e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP222" , 0x11800809406f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP223" , 0x11800809406f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP224" , 0x1180080940700ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP225" , 0x1180080940708ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP226" , 0x1180080940710ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP227" , 0x1180080940718ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP228" , 0x1180080940720ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP229" , 0x1180080940728ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP230" , 0x1180080940730ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP231" , 0x1180080940738ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP232" , 0x1180080940740ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP233" , 0x1180080940748ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP234" , 0x1180080940750ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP235" , 0x1180080940758ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP236" , 0x1180080940760ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP237" , 0x1180080940768ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP238" , 0x1180080940770ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP239" , 0x1180080940778ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP240" , 0x1180080940780ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP241" , 0x1180080940788ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP242" , 0x1180080940790ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP243" , 0x1180080940798ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP244" , 0x11800809407a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP245" , 0x11800809407a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP246" , 0x11800809407b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP247" , 0x11800809407b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP248" , 0x11800809407c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP249" , 0x11800809407c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP250" , 0x11800809407d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP251" , 0x11800809407d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP252" , 0x11800809407e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP253" , 0x11800809407e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP254" , 0x11800809407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP255" , 0x11800809407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP256" , 0x1180080940800ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP257" , 0x1180080940808ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP258" , 0x1180080940810ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP259" , 0x1180080940818ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP260" , 0x1180080940820ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP261" , 0x1180080940828ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP262" , 0x1180080940830ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP263" , 0x1180080940838ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP264" , 0x1180080940840ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP265" , 0x1180080940848ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP266" , 0x1180080940850ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP267" , 0x1180080940858ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP268" , 0x1180080940860ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP269" , 0x1180080940868ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP270" , 0x1180080940870ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP271" , 0x1180080940878ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP272" , 0x1180080940880ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP273" , 0x1180080940888ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP274" , 0x1180080940890ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP275" , 0x1180080940898ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP276" , 0x11800809408a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP277" , 0x11800809408a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP278" , 0x11800809408b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP279" , 0x11800809408b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP280" , 0x11800809408c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP281" , 0x11800809408c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP282" , 0x11800809408d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP283" , 0x11800809408d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP284" , 0x11800809408e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP285" , 0x11800809408e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP286" , 0x11800809408f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP287" , 0x11800809408f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP288" , 0x1180080940900ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP289" , 0x1180080940908ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP290" , 0x1180080940910ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP291" , 0x1180080940918ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP292" , 0x1180080940920ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP293" , 0x1180080940928ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP294" , 0x1180080940930ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP295" , 0x1180080940938ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP296" , 0x1180080940940ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP297" , 0x1180080940948ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP298" , 0x1180080940950ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP299" , 0x1180080940958ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP300" , 0x1180080940960ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP301" , 0x1180080940968ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP302" , 0x1180080940970ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP303" , 0x1180080940978ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP304" , 0x1180080940980ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP305" , 0x1180080940988ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP306" , 0x1180080940990ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP307" , 0x1180080940998ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP308" , 0x11800809409a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP309" , 0x11800809409a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP310" , 0x11800809409b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP311" , 0x11800809409b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP312" , 0x11800809409c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP313" , 0x11800809409c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP314" , 0x11800809409d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP315" , 0x11800809409d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP316" , 0x11800809409e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP317" , 0x11800809409e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP318" , 0x11800809409f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP319" , 0x11800809409f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP320" , 0x1180080940a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP321" , 0x1180080940a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP322" , 0x1180080940a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP323" , 0x1180080940a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP324" , 0x1180080940a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP325" , 0x1180080940a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP326" , 0x1180080940a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP327" , 0x1180080940a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP328" , 0x1180080940a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP329" , 0x1180080940a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP330" , 0x1180080940a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP331" , 0x1180080940a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP332" , 0x1180080940a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP333" , 0x1180080940a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP334" , 0x1180080940a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP335" , 0x1180080940a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP336" , 0x1180080940a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP337" , 0x1180080940a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP338" , 0x1180080940a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP339" , 0x1180080940a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP340" , 0x1180080940aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP341" , 0x1180080940aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP342" , 0x1180080940ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP343" , 0x1180080940ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP344" , 0x1180080940ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP345" , 0x1180080940ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP346" , 0x1180080940ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP347" , 0x1180080940ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP348" , 0x1180080940ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP349" , 0x1180080940ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP350" , 0x1180080940af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP351" , 0x1180080940af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP352" , 0x1180080940b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP353" , 0x1180080940b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP354" , 0x1180080940b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP355" , 0x1180080940b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP356" , 0x1180080940b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP357" , 0x1180080940b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP358" , 0x1180080940b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP359" , 0x1180080940b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP360" , 0x1180080940b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP361" , 0x1180080940b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP362" , 0x1180080940b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP363" , 0x1180080940b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP364" , 0x1180080940b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP365" , 0x1180080940b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP366" , 0x1180080940b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP367" , 0x1180080940b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP368" , 0x1180080940b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP369" , 0x1180080940b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP370" , 0x1180080940b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP371" , 0x1180080940b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP372" , 0x1180080940ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP373" , 0x1180080940ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP374" , 0x1180080940bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP375" , 0x1180080940bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP376" , 0x1180080940bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP377" , 0x1180080940bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP378" , 0x1180080940bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP379" , 0x1180080940bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP380" , 0x1180080940be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP381" , 0x1180080940be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP382" , 0x1180080940bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP383" , 0x1180080940bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP384" , 0x1180080940c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP385" , 0x1180080940c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP386" , 0x1180080940c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP387" , 0x1180080940c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP388" , 0x1180080940c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP389" , 0x1180080940c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP390" , 0x1180080940c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP391" , 0x1180080940c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP392" , 0x1180080940c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP393" , 0x1180080940c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP394" , 0x1180080940c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP395" , 0x1180080940c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP396" , 0x1180080940c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP397" , 0x1180080940c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP398" , 0x1180080940c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP399" , 0x1180080940c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP400" , 0x1180080940c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP401" , 0x1180080940c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP402" , 0x1180080940c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP403" , 0x1180080940c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP404" , 0x1180080940ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP405" , 0x1180080940ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP406" , 0x1180080940cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP407" , 0x1180080940cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP408" , 0x1180080940cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP409" , 0x1180080940cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP410" , 0x1180080940cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP411" , 0x1180080940cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP412" , 0x1180080940ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP413" , 0x1180080940ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP414" , 0x1180080940cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP415" , 0x1180080940cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP416" , 0x1180080940d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP417" , 0x1180080940d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP418" , 0x1180080940d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP419" , 0x1180080940d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP420" , 0x1180080940d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP421" , 0x1180080940d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP422" , 0x1180080940d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP423" , 0x1180080940d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP424" , 0x1180080940d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP425" , 0x1180080940d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP426" , 0x1180080940d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP427" , 0x1180080940d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP428" , 0x1180080940d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP429" , 0x1180080940d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP430" , 0x1180080940d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP431" , 0x1180080940d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP432" , 0x1180080940d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP433" , 0x1180080940d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP434" , 0x1180080940d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP435" , 0x1180080940d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP436" , 0x1180080940da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP437" , 0x1180080940da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP438" , 0x1180080940db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP439" , 0x1180080940db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP440" , 0x1180080940dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP441" , 0x1180080940dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP442" , 0x1180080940dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP443" , 0x1180080940dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP444" , 0x1180080940de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP445" , 0x1180080940de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP446" , 0x1180080940df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP447" , 0x1180080940df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP448" , 0x1180080940e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP449" , 0x1180080940e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP450" , 0x1180080940e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP451" , 0x1180080940e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP452" , 0x1180080940e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP453" , 0x1180080940e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP454" , 0x1180080940e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP455" , 0x1180080940e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP456" , 0x1180080940e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP457" , 0x1180080940e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP458" , 0x1180080940e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP459" , 0x1180080940e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP460" , 0x1180080940e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP461" , 0x1180080940e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP462" , 0x1180080940e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP463" , 0x1180080940e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP464" , 0x1180080940e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP465" , 0x1180080940e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP466" , 0x1180080940e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP467" , 0x1180080940e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP468" , 0x1180080940ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP469" , 0x1180080940ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP470" , 0x1180080940eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP471" , 0x1180080940eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP472" , 0x1180080940ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP473" , 0x1180080940ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP474" , 0x1180080940ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP475" , 0x1180080940ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP476" , 0x1180080940ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP477" , 0x1180080940ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP478" , 0x1180080940ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP479" , 0x1180080940ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP480" , 0x1180080940f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP481" , 0x1180080940f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP482" , 0x1180080940f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP483" , 0x1180080940f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP484" , 0x1180080940f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP485" , 0x1180080940f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP486" , 0x1180080940f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP487" , 0x1180080940f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP488" , 0x1180080940f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP489" , 0x1180080940f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP490" , 0x1180080940f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP491" , 0x1180080940f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP492" , 0x1180080940f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP493" , 0x1180080940f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP494" , 0x1180080940f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP495" , 0x1180080940f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP496" , 0x1180080940f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP497" , 0x1180080940f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP498" , 0x1180080940f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP499" , 0x1180080940f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP500" , 0x1180080940fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP501" , 0x1180080940fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP502" , 0x1180080940fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP503" , 0x1180080940fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP504" , 0x1180080940fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP505" , 0x1180080940fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP506" , 0x1180080940fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP507" , 0x1180080940fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP508" , 0x1180080940fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP509" , 0x1180080940fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP510" , 0x1180080940ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP511" , 0x1180080940ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP512" , 0x1180080941000ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP513" , 0x1180080941008ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP514" , 0x1180080941010ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP515" , 0x1180080941018ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP516" , 0x1180080941020ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP517" , 0x1180080941028ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP518" , 0x1180080941030ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP519" , 0x1180080941038ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP520" , 0x1180080941040ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP521" , 0x1180080941048ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP522" , 0x1180080941050ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP523" , 0x1180080941058ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP524" , 0x1180080941060ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP525" , 0x1180080941068ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP526" , 0x1180080941070ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP527" , 0x1180080941078ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP528" , 0x1180080941080ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP529" , 0x1180080941088ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP530" , 0x1180080941090ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP531" , 0x1180080941098ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP532" , 0x11800809410a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP533" , 0x11800809410a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP534" , 0x11800809410b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP535" , 0x11800809410b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP536" , 0x11800809410c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP537" , 0x11800809410c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP538" , 0x11800809410d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP539" , 0x11800809410d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP540" , 0x11800809410e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP541" , 0x11800809410e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP542" , 0x11800809410f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP543" , 0x11800809410f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP544" , 0x1180080941100ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP545" , 0x1180080941108ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP546" , 0x1180080941110ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP547" , 0x1180080941118ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP548" , 0x1180080941120ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP549" , 0x1180080941128ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP550" , 0x1180080941130ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP551" , 0x1180080941138ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP552" , 0x1180080941140ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP553" , 0x1180080941148ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP554" , 0x1180080941150ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP555" , 0x1180080941158ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP556" , 0x1180080941160ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP557" , 0x1180080941168ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP558" , 0x1180080941170ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP559" , 0x1180080941178ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP560" , 0x1180080941180ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP561" , 0x1180080941188ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP562" , 0x1180080941190ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP563" , 0x1180080941198ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP564" , 0x11800809411a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP565" , 0x11800809411a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP566" , 0x11800809411b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP567" , 0x11800809411b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP568" , 0x11800809411c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP569" , 0x11800809411c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP570" , 0x11800809411d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP571" , 0x11800809411d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP572" , 0x11800809411e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP573" , 0x11800809411e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP574" , 0x11800809411f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP575" , 0x11800809411f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP576" , 0x1180080941200ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP577" , 0x1180080941208ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP578" , 0x1180080941210ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP579" , 0x1180080941218ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP580" , 0x1180080941220ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP581" , 0x1180080941228ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP582" , 0x1180080941230ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP583" , 0x1180080941238ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP584" , 0x1180080941240ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP585" , 0x1180080941248ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP586" , 0x1180080941250ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP587" , 0x1180080941258ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP588" , 0x1180080941260ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP589" , 0x1180080941268ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP590" , 0x1180080941270ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP591" , 0x1180080941278ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP592" , 0x1180080941280ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP593" , 0x1180080941288ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP594" , 0x1180080941290ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP595" , 0x1180080941298ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP596" , 0x11800809412a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP597" , 0x11800809412a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP598" , 0x11800809412b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP599" , 0x11800809412b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP600" , 0x11800809412c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP601" , 0x11800809412c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP602" , 0x11800809412d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP603" , 0x11800809412d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP604" , 0x11800809412e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP605" , 0x11800809412e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP606" , 0x11800809412f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP607" , 0x11800809412f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP608" , 0x1180080941300ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP609" , 0x1180080941308ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP610" , 0x1180080941310ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP611" , 0x1180080941318ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP612" , 0x1180080941320ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP613" , 0x1180080941328ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP614" , 0x1180080941330ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP615" , 0x1180080941338ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP616" , 0x1180080941340ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP617" , 0x1180080941348ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP618" , 0x1180080941350ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP619" , 0x1180080941358ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP620" , 0x1180080941360ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP621" , 0x1180080941368ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP622" , 0x1180080941370ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP623" , 0x1180080941378ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP624" , 0x1180080941380ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP625" , 0x1180080941388ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP626" , 0x1180080941390ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP627" , 0x1180080941398ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP628" , 0x11800809413a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP629" , 0x11800809413a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP630" , 0x11800809413b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP631" , 0x11800809413b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP632" , 0x11800809413c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP633" , 0x11800809413c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP634" , 0x11800809413d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP635" , 0x11800809413d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP636" , 0x11800809413e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP637" , 0x11800809413e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP638" , 0x11800809413f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP639" , 0x11800809413f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP640" , 0x1180080941400ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP641" , 0x1180080941408ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP642" , 0x1180080941410ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP643" , 0x1180080941418ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP644" , 0x1180080941420ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP645" , 0x1180080941428ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP646" , 0x1180080941430ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP647" , 0x1180080941438ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP648" , 0x1180080941440ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP649" , 0x1180080941448ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP650" , 0x1180080941450ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP651" , 0x1180080941458ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP652" , 0x1180080941460ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP653" , 0x1180080941468ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP654" , 0x1180080941470ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP655" , 0x1180080941478ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP656" , 0x1180080941480ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP657" , 0x1180080941488ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP658" , 0x1180080941490ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP659" , 0x1180080941498ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP660" , 0x11800809414a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP661" , 0x11800809414a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP662" , 0x11800809414b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP663" , 0x11800809414b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP664" , 0x11800809414c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP665" , 0x11800809414c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP666" , 0x11800809414d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP667" , 0x11800809414d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP668" , 0x11800809414e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP669" , 0x11800809414e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP670" , 0x11800809414f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP671" , 0x11800809414f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP672" , 0x1180080941500ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP673" , 0x1180080941508ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP674" , 0x1180080941510ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP675" , 0x1180080941518ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP676" , 0x1180080941520ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP677" , 0x1180080941528ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP678" , 0x1180080941530ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP679" , 0x1180080941538ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP680" , 0x1180080941540ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP681" , 0x1180080941548ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP682" , 0x1180080941550ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP683" , 0x1180080941558ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP684" , 0x1180080941560ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP685" , 0x1180080941568ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP686" , 0x1180080941570ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP687" , 0x1180080941578ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP688" , 0x1180080941580ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP689" , 0x1180080941588ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP690" , 0x1180080941590ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP691" , 0x1180080941598ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP692" , 0x11800809415a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP693" , 0x11800809415a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP694" , 0x11800809415b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP695" , 0x11800809415b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP696" , 0x11800809415c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP697" , 0x11800809415c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP698" , 0x11800809415d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP699" , 0x11800809415d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP700" , 0x11800809415e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP701" , 0x11800809415e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP702" , 0x11800809415f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP703" , 0x11800809415f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP704" , 0x1180080941600ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP705" , 0x1180080941608ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP706" , 0x1180080941610ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP707" , 0x1180080941618ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP708" , 0x1180080941620ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP709" , 0x1180080941628ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP710" , 0x1180080941630ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP711" , 0x1180080941638ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP712" , 0x1180080941640ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP713" , 0x1180080941648ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP714" , 0x1180080941650ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP715" , 0x1180080941658ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP716" , 0x1180080941660ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP717" , 0x1180080941668ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP718" , 0x1180080941670ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP719" , 0x1180080941678ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP720" , 0x1180080941680ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP721" , 0x1180080941688ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP722" , 0x1180080941690ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP723" , 0x1180080941698ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP724" , 0x11800809416a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP725" , 0x11800809416a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP726" , 0x11800809416b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP727" , 0x11800809416b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP728" , 0x11800809416c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP729" , 0x11800809416c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP730" , 0x11800809416d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP731" , 0x11800809416d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP732" , 0x11800809416e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP733" , 0x11800809416e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP734" , 0x11800809416f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP735" , 0x11800809416f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP736" , 0x1180080941700ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP737" , 0x1180080941708ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP738" , 0x1180080941710ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP739" , 0x1180080941718ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP740" , 0x1180080941720ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP741" , 0x1180080941728ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP742" , 0x1180080941730ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP743" , 0x1180080941738ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP744" , 0x1180080941740ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP745" , 0x1180080941748ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP746" , 0x1180080941750ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP747" , 0x1180080941758ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP748" , 0x1180080941760ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP749" , 0x1180080941768ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP750" , 0x1180080941770ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP751" , 0x1180080941778ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP752" , 0x1180080941780ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP753" , 0x1180080941788ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP754" , 0x1180080941790ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP755" , 0x1180080941798ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP756" , 0x11800809417a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP757" , 0x11800809417a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP758" , 0x11800809417b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP759" , 0x11800809417b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP760" , 0x11800809417c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP761" , 0x11800809417c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP762" , 0x11800809417d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP763" , 0x11800809417d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP764" , 0x11800809417e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP765" , 0x11800809417e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP766" , 0x11800809417f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP767" , 0x11800809417f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP768" , 0x1180080941800ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP769" , 0x1180080941808ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP770" , 0x1180080941810ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP771" , 0x1180080941818ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP772" , 0x1180080941820ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP773" , 0x1180080941828ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP774" , 0x1180080941830ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP775" , 0x1180080941838ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP776" , 0x1180080941840ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP777" , 0x1180080941848ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP778" , 0x1180080941850ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP779" , 0x1180080941858ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP780" , 0x1180080941860ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP781" , 0x1180080941868ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP782" , 0x1180080941870ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP783" , 0x1180080941878ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP784" , 0x1180080941880ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP785" , 0x1180080941888ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP786" , 0x1180080941890ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP787" , 0x1180080941898ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP788" , 0x11800809418a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP789" , 0x11800809418a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP790" , 0x11800809418b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP791" , 0x11800809418b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP792" , 0x11800809418c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP793" , 0x11800809418c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP794" , 0x11800809418d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP795" , 0x11800809418d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP796" , 0x11800809418e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP797" , 0x11800809418e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP798" , 0x11800809418f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP799" , 0x11800809418f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP800" , 0x1180080941900ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP801" , 0x1180080941908ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP802" , 0x1180080941910ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP803" , 0x1180080941918ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP804" , 0x1180080941920ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP805" , 0x1180080941928ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP806" , 0x1180080941930ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP807" , 0x1180080941938ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP808" , 0x1180080941940ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP809" , 0x1180080941948ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP810" , 0x1180080941950ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP811" , 0x1180080941958ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP812" , 0x1180080941960ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP813" , 0x1180080941968ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP814" , 0x1180080941970ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP815" , 0x1180080941978ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP816" , 0x1180080941980ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP817" , 0x1180080941988ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP818" , 0x1180080941990ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP819" , 0x1180080941998ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP820" , 0x11800809419a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP821" , 0x11800809419a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP822" , 0x11800809419b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP823" , 0x11800809419b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP824" , 0x11800809419c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP825" , 0x11800809419c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP826" , 0x11800809419d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP827" , 0x11800809419d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP828" , 0x11800809419e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP829" , 0x11800809419e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP830" , 0x11800809419f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP831" , 0x11800809419f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP832" , 0x1180080941a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP833" , 0x1180080941a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP834" , 0x1180080941a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP835" , 0x1180080941a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP836" , 0x1180080941a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP837" , 0x1180080941a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP838" , 0x1180080941a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP839" , 0x1180080941a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP840" , 0x1180080941a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP841" , 0x1180080941a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP842" , 0x1180080941a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP843" , 0x1180080941a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP844" , 0x1180080941a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP845" , 0x1180080941a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP846" , 0x1180080941a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP847" , 0x1180080941a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP848" , 0x1180080941a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP849" , 0x1180080941a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP850" , 0x1180080941a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP851" , 0x1180080941a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP852" , 0x1180080941aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP853" , 0x1180080941aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP854" , 0x1180080941ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP855" , 0x1180080941ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP856" , 0x1180080941ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP857" , 0x1180080941ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP858" , 0x1180080941ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP859" , 0x1180080941ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP860" , 0x1180080941ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP861" , 0x1180080941ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP862" , 0x1180080941af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP863" , 0x1180080941af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP864" , 0x1180080941b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP865" , 0x1180080941b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP866" , 0x1180080941b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP867" , 0x1180080941b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP868" , 0x1180080941b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP869" , 0x1180080941b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP870" , 0x1180080941b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP871" , 0x1180080941b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP872" , 0x1180080941b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP873" , 0x1180080941b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP874" , 0x1180080941b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP875" , 0x1180080941b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP876" , 0x1180080941b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP877" , 0x1180080941b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP878" , 0x1180080941b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP879" , 0x1180080941b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP880" , 0x1180080941b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP881" , 0x1180080941b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP882" , 0x1180080941b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP883" , 0x1180080941b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP884" , 0x1180080941ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP885" , 0x1180080941ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP886" , 0x1180080941bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP887" , 0x1180080941bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP888" , 0x1180080941bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP889" , 0x1180080941bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP890" , 0x1180080941bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP891" , 0x1180080941bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP892" , 0x1180080941be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP893" , 0x1180080941be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP894" , 0x1180080941bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP895" , 0x1180080941bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP896" , 0x1180080941c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP897" , 0x1180080941c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP898" , 0x1180080941c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP899" , 0x1180080941c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP900" , 0x1180080941c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP901" , 0x1180080941c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP902" , 0x1180080941c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP903" , 0x1180080941c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP904" , 0x1180080941c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP905" , 0x1180080941c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP906" , 0x1180080941c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP907" , 0x1180080941c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP908" , 0x1180080941c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP909" , 0x1180080941c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP910" , 0x1180080941c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP911" , 0x1180080941c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP912" , 0x1180080941c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP913" , 0x1180080941c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP914" , 0x1180080941c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP915" , 0x1180080941c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP916" , 0x1180080941ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP917" , 0x1180080941ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP918" , 0x1180080941cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP919" , 0x1180080941cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP920" , 0x1180080941cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP921" , 0x1180080941cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP922" , 0x1180080941cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP923" , 0x1180080941cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP924" , 0x1180080941ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP925" , 0x1180080941ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP926" , 0x1180080941cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP927" , 0x1180080941cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP928" , 0x1180080941d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP929" , 0x1180080941d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP930" , 0x1180080941d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP931" , 0x1180080941d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP932" , 0x1180080941d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP933" , 0x1180080941d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP934" , 0x1180080941d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP935" , 0x1180080941d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP936" , 0x1180080941d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP937" , 0x1180080941d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP938" , 0x1180080941d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP939" , 0x1180080941d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP940" , 0x1180080941d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP941" , 0x1180080941d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP942" , 0x1180080941d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP943" , 0x1180080941d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP944" , 0x1180080941d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP945" , 0x1180080941d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP946" , 0x1180080941d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP947" , 0x1180080941d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP948" , 0x1180080941da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP949" , 0x1180080941da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP950" , 0x1180080941db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP951" , 0x1180080941db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP952" , 0x1180080941dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP953" , 0x1180080941dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP954" , 0x1180080941dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP955" , 0x1180080941dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP956" , 0x1180080941de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP957" , 0x1180080941de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP958" , 0x1180080941df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP959" , 0x1180080941df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP960" , 0x1180080941e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP961" , 0x1180080941e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP962" , 0x1180080941e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP963" , 0x1180080941e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP964" , 0x1180080941e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP965" , 0x1180080941e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP966" , 0x1180080941e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP967" , 0x1180080941e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP968" , 0x1180080941e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP969" , 0x1180080941e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP970" , 0x1180080941e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP971" , 0x1180080941e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP972" , 0x1180080941e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP973" , 0x1180080941e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP974" , 0x1180080941e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP975" , 0x1180080941e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP976" , 0x1180080941e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP977" , 0x1180080941e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP978" , 0x1180080941e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP979" , 0x1180080941e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP980" , 0x1180080941ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP981" , 0x1180080941ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP982" , 0x1180080941eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP983" , 0x1180080941eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP984" , 0x1180080941ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP985" , 0x1180080941ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP986" , 0x1180080941ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP987" , 0x1180080941ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP988" , 0x1180080941ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP989" , 0x1180080941ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP990" , 0x1180080941ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP991" , 0x1180080941ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP992" , 0x1180080941f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP993" , 0x1180080941f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP994" , 0x1180080941f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP995" , 0x1180080941f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP996" , 0x1180080941f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP997" , 0x1180080941f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP998" , 0x1180080941f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP999" , 0x1180080941f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1000" , 0x1180080941f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1001" , 0x1180080941f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1002" , 0x1180080941f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1003" , 0x1180080941f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1004" , 0x1180080941f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1005" , 0x1180080941f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1006" , 0x1180080941f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1007" , 0x1180080941f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1008" , 0x1180080941f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1009" , 0x1180080941f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1010" , 0x1180080941f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1011" , 0x1180080941f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1012" , 0x1180080941fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1013" , 0x1180080941fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1014" , 0x1180080941fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1015" , 0x1180080941fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1016" , 0x1180080941fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1017" , 0x1180080941fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1018" , 0x1180080941fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1019" , 0x1180080941fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1020" , 0x1180080941fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1021" , 0x1180080941fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1022" , 0x1180080941ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1023" , 0x1180080941ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1024" , 0x1180080942000ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1025" , 0x1180080942008ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1026" , 0x1180080942010ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1027" , 0x1180080942018ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1028" , 0x1180080942020ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1029" , 0x1180080942028ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1030" , 0x1180080942030ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1031" , 0x1180080942038ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1032" , 0x1180080942040ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1033" , 0x1180080942048ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1034" , 0x1180080942050ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1035" , 0x1180080942058ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1036" , 0x1180080942060ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1037" , 0x1180080942068ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1038" , 0x1180080942070ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1039" , 0x1180080942078ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1040" , 0x1180080942080ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1041" , 0x1180080942088ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1042" , 0x1180080942090ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1043" , 0x1180080942098ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1044" , 0x11800809420a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1045" , 0x11800809420a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1046" , 0x11800809420b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1047" , 0x11800809420b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1048" , 0x11800809420c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1049" , 0x11800809420c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1050" , 0x11800809420d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1051" , 0x11800809420d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1052" , 0x11800809420e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1053" , 0x11800809420e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1054" , 0x11800809420f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1055" , 0x11800809420f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1056" , 0x1180080942100ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1057" , 0x1180080942108ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1058" , 0x1180080942110ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1059" , 0x1180080942118ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1060" , 0x1180080942120ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1061" , 0x1180080942128ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1062" , 0x1180080942130ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1063" , 0x1180080942138ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1064" , 0x1180080942140ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1065" , 0x1180080942148ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1066" , 0x1180080942150ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1067" , 0x1180080942158ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1068" , 0x1180080942160ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1069" , 0x1180080942168ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1070" , 0x1180080942170ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1071" , 0x1180080942178ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1072" , 0x1180080942180ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1073" , 0x1180080942188ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1074" , 0x1180080942190ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1075" , 0x1180080942198ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1076" , 0x11800809421a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1077" , 0x11800809421a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1078" , 0x11800809421b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1079" , 0x11800809421b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1080" , 0x11800809421c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1081" , 0x11800809421c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1082" , 0x11800809421d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1083" , 0x11800809421d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1084" , 0x11800809421e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1085" , 0x11800809421e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1086" , 0x11800809421f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1087" , 0x11800809421f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1088" , 0x1180080942200ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1089" , 0x1180080942208ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1090" , 0x1180080942210ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1091" , 0x1180080942218ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1092" , 0x1180080942220ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1093" , 0x1180080942228ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1094" , 0x1180080942230ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1095" , 0x1180080942238ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1096" , 0x1180080942240ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1097" , 0x1180080942248ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1098" , 0x1180080942250ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1099" , 0x1180080942258ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1100" , 0x1180080942260ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1101" , 0x1180080942268ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1102" , 0x1180080942270ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1103" , 0x1180080942278ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1104" , 0x1180080942280ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1105" , 0x1180080942288ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1106" , 0x1180080942290ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1107" , 0x1180080942298ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1108" , 0x11800809422a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1109" , 0x11800809422a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1110" , 0x11800809422b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1111" , 0x11800809422b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1112" , 0x11800809422c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1113" , 0x11800809422c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1114" , 0x11800809422d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1115" , 0x11800809422d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1116" , 0x11800809422e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1117" , 0x11800809422e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1118" , 0x11800809422f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1119" , 0x11800809422f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1120" , 0x1180080942300ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1121" , 0x1180080942308ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1122" , 0x1180080942310ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1123" , 0x1180080942318ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1124" , 0x1180080942320ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1125" , 0x1180080942328ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1126" , 0x1180080942330ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1127" , 0x1180080942338ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1128" , 0x1180080942340ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1129" , 0x1180080942348ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1130" , 0x1180080942350ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1131" , 0x1180080942358ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1132" , 0x1180080942360ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1133" , 0x1180080942368ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1134" , 0x1180080942370ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1135" , 0x1180080942378ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1136" , 0x1180080942380ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1137" , 0x1180080942388ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1138" , 0x1180080942390ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1139" , 0x1180080942398ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1140" , 0x11800809423a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1141" , 0x11800809423a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1142" , 0x11800809423b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1143" , 0x11800809423b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1144" , 0x11800809423c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1145" , 0x11800809423c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1146" , 0x11800809423d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1147" , 0x11800809423d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1148" , 0x11800809423e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1149" , 0x11800809423e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1150" , 0x11800809423f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1151" , 0x11800809423f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1152" , 0x1180080942400ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1153" , 0x1180080942408ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1154" , 0x1180080942410ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1155" , 0x1180080942418ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1156" , 0x1180080942420ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1157" , 0x1180080942428ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1158" , 0x1180080942430ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1159" , 0x1180080942438ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1160" , 0x1180080942440ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1161" , 0x1180080942448ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1162" , 0x1180080942450ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1163" , 0x1180080942458ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1164" , 0x1180080942460ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1165" , 0x1180080942468ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1166" , 0x1180080942470ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1167" , 0x1180080942478ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1168" , 0x1180080942480ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1169" , 0x1180080942488ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1170" , 0x1180080942490ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1171" , 0x1180080942498ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1172" , 0x11800809424a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1173" , 0x11800809424a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1174" , 0x11800809424b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1175" , 0x11800809424b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1176" , 0x11800809424c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1177" , 0x11800809424c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1178" , 0x11800809424d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1179" , 0x11800809424d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1180" , 0x11800809424e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1181" , 0x11800809424e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1182" , 0x11800809424f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1183" , 0x11800809424f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1184" , 0x1180080942500ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1185" , 0x1180080942508ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1186" , 0x1180080942510ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1187" , 0x1180080942518ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1188" , 0x1180080942520ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1189" , 0x1180080942528ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1190" , 0x1180080942530ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1191" , 0x1180080942538ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1192" , 0x1180080942540ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1193" , 0x1180080942548ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1194" , 0x1180080942550ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1195" , 0x1180080942558ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1196" , 0x1180080942560ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1197" , 0x1180080942568ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1198" , 0x1180080942570ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1199" , 0x1180080942578ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1200" , 0x1180080942580ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1201" , 0x1180080942588ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1202" , 0x1180080942590ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1203" , 0x1180080942598ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1204" , 0x11800809425a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1205" , 0x11800809425a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1206" , 0x11800809425b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1207" , 0x11800809425b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1208" , 0x11800809425c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1209" , 0x11800809425c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1210" , 0x11800809425d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1211" , 0x11800809425d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1212" , 0x11800809425e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1213" , 0x11800809425e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1214" , 0x11800809425f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1215" , 0x11800809425f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1216" , 0x1180080942600ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1217" , 0x1180080942608ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1218" , 0x1180080942610ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1219" , 0x1180080942618ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1220" , 0x1180080942620ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1221" , 0x1180080942628ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1222" , 0x1180080942630ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1223" , 0x1180080942638ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1224" , 0x1180080942640ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1225" , 0x1180080942648ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1226" , 0x1180080942650ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1227" , 0x1180080942658ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1228" , 0x1180080942660ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1229" , 0x1180080942668ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1230" , 0x1180080942670ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1231" , 0x1180080942678ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1232" , 0x1180080942680ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1233" , 0x1180080942688ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1234" , 0x1180080942690ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1235" , 0x1180080942698ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1236" , 0x11800809426a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1237" , 0x11800809426a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1238" , 0x11800809426b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1239" , 0x11800809426b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1240" , 0x11800809426c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1241" , 0x11800809426c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1242" , 0x11800809426d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1243" , 0x11800809426d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1244" , 0x11800809426e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1245" , 0x11800809426e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1246" , 0x11800809426f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1247" , 0x11800809426f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1248" , 0x1180080942700ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1249" , 0x1180080942708ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1250" , 0x1180080942710ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1251" , 0x1180080942718ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1252" , 0x1180080942720ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1253" , 0x1180080942728ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1254" , 0x1180080942730ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1255" , 0x1180080942738ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1256" , 0x1180080942740ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1257" , 0x1180080942748ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1258" , 0x1180080942750ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1259" , 0x1180080942758ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1260" , 0x1180080942760ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1261" , 0x1180080942768ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1262" , 0x1180080942770ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1263" , 0x1180080942778ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1264" , 0x1180080942780ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1265" , 0x1180080942788ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1266" , 0x1180080942790ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1267" , 0x1180080942798ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1268" , 0x11800809427a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1269" , 0x11800809427a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1270" , 0x11800809427b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1271" , 0x11800809427b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1272" , 0x11800809427c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1273" , 0x11800809427c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1274" , 0x11800809427d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1275" , 0x11800809427d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1276" , 0x11800809427e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1277" , 0x11800809427e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1278" , 0x11800809427f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1279" , 0x11800809427f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1280" , 0x1180080942800ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1281" , 0x1180080942808ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1282" , 0x1180080942810ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1283" , 0x1180080942818ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1284" , 0x1180080942820ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1285" , 0x1180080942828ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1286" , 0x1180080942830ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1287" , 0x1180080942838ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1288" , 0x1180080942840ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1289" , 0x1180080942848ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1290" , 0x1180080942850ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1291" , 0x1180080942858ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1292" , 0x1180080942860ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1293" , 0x1180080942868ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1294" , 0x1180080942870ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1295" , 0x1180080942878ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1296" , 0x1180080942880ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1297" , 0x1180080942888ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1298" , 0x1180080942890ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1299" , 0x1180080942898ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1300" , 0x11800809428a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1301" , 0x11800809428a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1302" , 0x11800809428b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1303" , 0x11800809428b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1304" , 0x11800809428c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1305" , 0x11800809428c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1306" , 0x11800809428d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1307" , 0x11800809428d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1308" , 0x11800809428e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1309" , 0x11800809428e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1310" , 0x11800809428f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1311" , 0x11800809428f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1312" , 0x1180080942900ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1313" , 0x1180080942908ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1314" , 0x1180080942910ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1315" , 0x1180080942918ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1316" , 0x1180080942920ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1317" , 0x1180080942928ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1318" , 0x1180080942930ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1319" , 0x1180080942938ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1320" , 0x1180080942940ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1321" , 0x1180080942948ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1322" , 0x1180080942950ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1323" , 0x1180080942958ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1324" , 0x1180080942960ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1325" , 0x1180080942968ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1326" , 0x1180080942970ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1327" , 0x1180080942978ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1328" , 0x1180080942980ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1329" , 0x1180080942988ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1330" , 0x1180080942990ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1331" , 0x1180080942998ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1332" , 0x11800809429a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1333" , 0x11800809429a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1334" , 0x11800809429b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1335" , 0x11800809429b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1336" , 0x11800809429c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1337" , 0x11800809429c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1338" , 0x11800809429d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1339" , 0x11800809429d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1340" , 0x11800809429e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1341" , 0x11800809429e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1342" , 0x11800809429f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1343" , 0x11800809429f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1344" , 0x1180080942a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1345" , 0x1180080942a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1346" , 0x1180080942a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1347" , 0x1180080942a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1348" , 0x1180080942a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1349" , 0x1180080942a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1350" , 0x1180080942a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1351" , 0x1180080942a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1352" , 0x1180080942a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1353" , 0x1180080942a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1354" , 0x1180080942a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1355" , 0x1180080942a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1356" , 0x1180080942a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1357" , 0x1180080942a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1358" , 0x1180080942a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1359" , 0x1180080942a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1360" , 0x1180080942a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1361" , 0x1180080942a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1362" , 0x1180080942a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1363" , 0x1180080942a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1364" , 0x1180080942aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1365" , 0x1180080942aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1366" , 0x1180080942ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1367" , 0x1180080942ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1368" , 0x1180080942ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1369" , 0x1180080942ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1370" , 0x1180080942ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1371" , 0x1180080942ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1372" , 0x1180080942ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1373" , 0x1180080942ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1374" , 0x1180080942af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1375" , 0x1180080942af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1376" , 0x1180080942b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1377" , 0x1180080942b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1378" , 0x1180080942b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1379" , 0x1180080942b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1380" , 0x1180080942b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1381" , 0x1180080942b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1382" , 0x1180080942b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1383" , 0x1180080942b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1384" , 0x1180080942b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1385" , 0x1180080942b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1386" , 0x1180080942b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1387" , 0x1180080942b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1388" , 0x1180080942b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1389" , 0x1180080942b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1390" , 0x1180080942b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1391" , 0x1180080942b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1392" , 0x1180080942b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1393" , 0x1180080942b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1394" , 0x1180080942b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1395" , 0x1180080942b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1396" , 0x1180080942ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1397" , 0x1180080942ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1398" , 0x1180080942bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1399" , 0x1180080942bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1400" , 0x1180080942bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1401" , 0x1180080942bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1402" , 0x1180080942bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1403" , 0x1180080942bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1404" , 0x1180080942be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1405" , 0x1180080942be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1406" , 0x1180080942bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1407" , 0x1180080942bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1408" , 0x1180080942c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1409" , 0x1180080942c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1410" , 0x1180080942c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1411" , 0x1180080942c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1412" , 0x1180080942c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1413" , 0x1180080942c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1414" , 0x1180080942c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1415" , 0x1180080942c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1416" , 0x1180080942c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1417" , 0x1180080942c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1418" , 0x1180080942c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1419" , 0x1180080942c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1420" , 0x1180080942c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1421" , 0x1180080942c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1422" , 0x1180080942c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1423" , 0x1180080942c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1424" , 0x1180080942c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1425" , 0x1180080942c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1426" , 0x1180080942c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1427" , 0x1180080942c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1428" , 0x1180080942ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1429" , 0x1180080942ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1430" , 0x1180080942cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1431" , 0x1180080942cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1432" , 0x1180080942cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1433" , 0x1180080942cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1434" , 0x1180080942cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1435" , 0x1180080942cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1436" , 0x1180080942ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1437" , 0x1180080942ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1438" , 0x1180080942cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1439" , 0x1180080942cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1440" , 0x1180080942d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1441" , 0x1180080942d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1442" , 0x1180080942d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1443" , 0x1180080942d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1444" , 0x1180080942d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1445" , 0x1180080942d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1446" , 0x1180080942d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1447" , 0x1180080942d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1448" , 0x1180080942d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1449" , 0x1180080942d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1450" , 0x1180080942d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1451" , 0x1180080942d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1452" , 0x1180080942d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1453" , 0x1180080942d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1454" , 0x1180080942d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1455" , 0x1180080942d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1456" , 0x1180080942d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1457" , 0x1180080942d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1458" , 0x1180080942d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1459" , 0x1180080942d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1460" , 0x1180080942da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1461" , 0x1180080942da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1462" , 0x1180080942db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1463" , 0x1180080942db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1464" , 0x1180080942dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1465" , 0x1180080942dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1466" , 0x1180080942dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1467" , 0x1180080942dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1468" , 0x1180080942de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1469" , 0x1180080942de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1470" , 0x1180080942df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1471" , 0x1180080942df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1472" , 0x1180080942e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1473" , 0x1180080942e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1474" , 0x1180080942e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1475" , 0x1180080942e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1476" , 0x1180080942e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1477" , 0x1180080942e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1478" , 0x1180080942e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1479" , 0x1180080942e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1480" , 0x1180080942e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1481" , 0x1180080942e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1482" , 0x1180080942e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1483" , 0x1180080942e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1484" , 0x1180080942e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1485" , 0x1180080942e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1486" , 0x1180080942e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1487" , 0x1180080942e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1488" , 0x1180080942e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1489" , 0x1180080942e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1490" , 0x1180080942e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1491" , 0x1180080942e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1492" , 0x1180080942ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1493" , 0x1180080942ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1494" , 0x1180080942eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1495" , 0x1180080942eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1496" , 0x1180080942ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1497" , 0x1180080942ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1498" , 0x1180080942ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1499" , 0x1180080942ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1500" , 0x1180080942ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1501" , 0x1180080942ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1502" , 0x1180080942ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1503" , 0x1180080942ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1504" , 0x1180080942f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1505" , 0x1180080942f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1506" , 0x1180080942f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1507" , 0x1180080942f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1508" , 0x1180080942f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1509" , 0x1180080942f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1510" , 0x1180080942f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1511" , 0x1180080942f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1512" , 0x1180080942f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1513" , 0x1180080942f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1514" , 0x1180080942f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1515" , 0x1180080942f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1516" , 0x1180080942f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1517" , 0x1180080942f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1518" , 0x1180080942f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1519" , 0x1180080942f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1520" , 0x1180080942f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1521" , 0x1180080942f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1522" , 0x1180080942f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1523" , 0x1180080942f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1524" , 0x1180080942fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1525" , 0x1180080942fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1526" , 0x1180080942fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1527" , 0x1180080942fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1528" , 0x1180080942fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1529" , 0x1180080942fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1530" , 0x1180080942fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1531" , 0x1180080942fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1532" , 0x1180080942fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1533" , 0x1180080942fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1534" , 0x1180080942ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1535" , 0x1180080942ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1536" , 0x1180080943000ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1537" , 0x1180080943008ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1538" , 0x1180080943010ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1539" , 0x1180080943018ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1540" , 0x1180080943020ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1541" , 0x1180080943028ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1542" , 0x1180080943030ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1543" , 0x1180080943038ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1544" , 0x1180080943040ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1545" , 0x1180080943048ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1546" , 0x1180080943050ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1547" , 0x1180080943058ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1548" , 0x1180080943060ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1549" , 0x1180080943068ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1550" , 0x1180080943070ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1551" , 0x1180080943078ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1552" , 0x1180080943080ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1553" , 0x1180080943088ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1554" , 0x1180080943090ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1555" , 0x1180080943098ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1556" , 0x11800809430a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1557" , 0x11800809430a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1558" , 0x11800809430b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1559" , 0x11800809430b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1560" , 0x11800809430c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1561" , 0x11800809430c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1562" , 0x11800809430d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1563" , 0x11800809430d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1564" , 0x11800809430e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1565" , 0x11800809430e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1566" , 0x11800809430f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1567" , 0x11800809430f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1568" , 0x1180080943100ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1569" , 0x1180080943108ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1570" , 0x1180080943110ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1571" , 0x1180080943118ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1572" , 0x1180080943120ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1573" , 0x1180080943128ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1574" , 0x1180080943130ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1575" , 0x1180080943138ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1576" , 0x1180080943140ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1577" , 0x1180080943148ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1578" , 0x1180080943150ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1579" , 0x1180080943158ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1580" , 0x1180080943160ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1581" , 0x1180080943168ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1582" , 0x1180080943170ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1583" , 0x1180080943178ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1584" , 0x1180080943180ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1585" , 0x1180080943188ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1586" , 0x1180080943190ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1587" , 0x1180080943198ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1588" , 0x11800809431a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1589" , 0x11800809431a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1590" , 0x11800809431b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1591" , 0x11800809431b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1592" , 0x11800809431c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1593" , 0x11800809431c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1594" , 0x11800809431d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1595" , 0x11800809431d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1596" , 0x11800809431e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1597" , 0x11800809431e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1598" , 0x11800809431f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1599" , 0x11800809431f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1600" , 0x1180080943200ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1601" , 0x1180080943208ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1602" , 0x1180080943210ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1603" , 0x1180080943218ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1604" , 0x1180080943220ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1605" , 0x1180080943228ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1606" , 0x1180080943230ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1607" , 0x1180080943238ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1608" , 0x1180080943240ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1609" , 0x1180080943248ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1610" , 0x1180080943250ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1611" , 0x1180080943258ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1612" , 0x1180080943260ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1613" , 0x1180080943268ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1614" , 0x1180080943270ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1615" , 0x1180080943278ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1616" , 0x1180080943280ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1617" , 0x1180080943288ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1618" , 0x1180080943290ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1619" , 0x1180080943298ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1620" , 0x11800809432a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1621" , 0x11800809432a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1622" , 0x11800809432b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1623" , 0x11800809432b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1624" , 0x11800809432c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1625" , 0x11800809432c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1626" , 0x11800809432d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1627" , 0x11800809432d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1628" , 0x11800809432e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1629" , 0x11800809432e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1630" , 0x11800809432f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1631" , 0x11800809432f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1632" , 0x1180080943300ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1633" , 0x1180080943308ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1634" , 0x1180080943310ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1635" , 0x1180080943318ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1636" , 0x1180080943320ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1637" , 0x1180080943328ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1638" , 0x1180080943330ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1639" , 0x1180080943338ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1640" , 0x1180080943340ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1641" , 0x1180080943348ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1642" , 0x1180080943350ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1643" , 0x1180080943358ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1644" , 0x1180080943360ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1645" , 0x1180080943368ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1646" , 0x1180080943370ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1647" , 0x1180080943378ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1648" , 0x1180080943380ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1649" , 0x1180080943388ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1650" , 0x1180080943390ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1651" , 0x1180080943398ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1652" , 0x11800809433a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1653" , 0x11800809433a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1654" , 0x11800809433b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1655" , 0x11800809433b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1656" , 0x11800809433c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1657" , 0x11800809433c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1658" , 0x11800809433d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1659" , 0x11800809433d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1660" , 0x11800809433e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1661" , 0x11800809433e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1662" , 0x11800809433f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1663" , 0x11800809433f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1664" , 0x1180080943400ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1665" , 0x1180080943408ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1666" , 0x1180080943410ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1667" , 0x1180080943418ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1668" , 0x1180080943420ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1669" , 0x1180080943428ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1670" , 0x1180080943430ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1671" , 0x1180080943438ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1672" , 0x1180080943440ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1673" , 0x1180080943448ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1674" , 0x1180080943450ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1675" , 0x1180080943458ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1676" , 0x1180080943460ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1677" , 0x1180080943468ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1678" , 0x1180080943470ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1679" , 0x1180080943478ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1680" , 0x1180080943480ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1681" , 0x1180080943488ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1682" , 0x1180080943490ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1683" , 0x1180080943498ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1684" , 0x11800809434a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1685" , 0x11800809434a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1686" , 0x11800809434b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1687" , 0x11800809434b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1688" , 0x11800809434c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1689" , 0x11800809434c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1690" , 0x11800809434d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1691" , 0x11800809434d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1692" , 0x11800809434e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1693" , 0x11800809434e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1694" , 0x11800809434f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1695" , 0x11800809434f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1696" , 0x1180080943500ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1697" , 0x1180080943508ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1698" , 0x1180080943510ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1699" , 0x1180080943518ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1700" , 0x1180080943520ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1701" , 0x1180080943528ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1702" , 0x1180080943530ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1703" , 0x1180080943538ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1704" , 0x1180080943540ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1705" , 0x1180080943548ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1706" , 0x1180080943550ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1707" , 0x1180080943558ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1708" , 0x1180080943560ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1709" , 0x1180080943568ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1710" , 0x1180080943570ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1711" , 0x1180080943578ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1712" , 0x1180080943580ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1713" , 0x1180080943588ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1714" , 0x1180080943590ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1715" , 0x1180080943598ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1716" , 0x11800809435a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1717" , 0x11800809435a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1718" , 0x11800809435b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1719" , 0x11800809435b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1720" , 0x11800809435c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1721" , 0x11800809435c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1722" , 0x11800809435d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1723" , 0x11800809435d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1724" , 0x11800809435e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1725" , 0x11800809435e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1726" , 0x11800809435f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1727" , 0x11800809435f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1728" , 0x1180080943600ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1729" , 0x1180080943608ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1730" , 0x1180080943610ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1731" , 0x1180080943618ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1732" , 0x1180080943620ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1733" , 0x1180080943628ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1734" , 0x1180080943630ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1735" , 0x1180080943638ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1736" , 0x1180080943640ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1737" , 0x1180080943648ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1738" , 0x1180080943650ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1739" , 0x1180080943658ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1740" , 0x1180080943660ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1741" , 0x1180080943668ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1742" , 0x1180080943670ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1743" , 0x1180080943678ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1744" , 0x1180080943680ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1745" , 0x1180080943688ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1746" , 0x1180080943690ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1747" , 0x1180080943698ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1748" , 0x11800809436a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1749" , 0x11800809436a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1750" , 0x11800809436b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1751" , 0x11800809436b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1752" , 0x11800809436c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1753" , 0x11800809436c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1754" , 0x11800809436d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1755" , 0x11800809436d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1756" , 0x11800809436e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1757" , 0x11800809436e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1758" , 0x11800809436f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1759" , 0x11800809436f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1760" , 0x1180080943700ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1761" , 0x1180080943708ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1762" , 0x1180080943710ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1763" , 0x1180080943718ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1764" , 0x1180080943720ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1765" , 0x1180080943728ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1766" , 0x1180080943730ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1767" , 0x1180080943738ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1768" , 0x1180080943740ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1769" , 0x1180080943748ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1770" , 0x1180080943750ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1771" , 0x1180080943758ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1772" , 0x1180080943760ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1773" , 0x1180080943768ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1774" , 0x1180080943770ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1775" , 0x1180080943778ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1776" , 0x1180080943780ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1777" , 0x1180080943788ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1778" , 0x1180080943790ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1779" , 0x1180080943798ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1780" , 0x11800809437a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1781" , 0x11800809437a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1782" , 0x11800809437b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1783" , 0x11800809437b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1784" , 0x11800809437c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1785" , 0x11800809437c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1786" , 0x11800809437d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1787" , 0x11800809437d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1788" , 0x11800809437e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1789" , 0x11800809437e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1790" , 0x11800809437f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1791" , 0x11800809437f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1792" , 0x1180080943800ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1793" , 0x1180080943808ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1794" , 0x1180080943810ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1795" , 0x1180080943818ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1796" , 0x1180080943820ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1797" , 0x1180080943828ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1798" , 0x1180080943830ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1799" , 0x1180080943838ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1800" , 0x1180080943840ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1801" , 0x1180080943848ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1802" , 0x1180080943850ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1803" , 0x1180080943858ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1804" , 0x1180080943860ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1805" , 0x1180080943868ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1806" , 0x1180080943870ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1807" , 0x1180080943878ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1808" , 0x1180080943880ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1809" , 0x1180080943888ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1810" , 0x1180080943890ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1811" , 0x1180080943898ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1812" , 0x11800809438a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1813" , 0x11800809438a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1814" , 0x11800809438b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1815" , 0x11800809438b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1816" , 0x11800809438c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1817" , 0x11800809438c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1818" , 0x11800809438d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1819" , 0x11800809438d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1820" , 0x11800809438e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1821" , 0x11800809438e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1822" , 0x11800809438f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1823" , 0x11800809438f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1824" , 0x1180080943900ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1825" , 0x1180080943908ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1826" , 0x1180080943910ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1827" , 0x1180080943918ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1828" , 0x1180080943920ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1829" , 0x1180080943928ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1830" , 0x1180080943930ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1831" , 0x1180080943938ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1832" , 0x1180080943940ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1833" , 0x1180080943948ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1834" , 0x1180080943950ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1835" , 0x1180080943958ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1836" , 0x1180080943960ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1837" , 0x1180080943968ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1838" , 0x1180080943970ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1839" , 0x1180080943978ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1840" , 0x1180080943980ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1841" , 0x1180080943988ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1842" , 0x1180080943990ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1843" , 0x1180080943998ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1844" , 0x11800809439a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1845" , 0x11800809439a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1846" , 0x11800809439b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1847" , 0x11800809439b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1848" , 0x11800809439c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1849" , 0x11800809439c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1850" , 0x11800809439d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1851" , 0x11800809439d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1852" , 0x11800809439e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1853" , 0x11800809439e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1854" , 0x11800809439f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1855" , 0x11800809439f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1856" , 0x1180080943a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1857" , 0x1180080943a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1858" , 0x1180080943a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1859" , 0x1180080943a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1860" , 0x1180080943a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1861" , 0x1180080943a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1862" , 0x1180080943a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1863" , 0x1180080943a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1864" , 0x1180080943a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1865" , 0x1180080943a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1866" , 0x1180080943a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1867" , 0x1180080943a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1868" , 0x1180080943a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1869" , 0x1180080943a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1870" , 0x1180080943a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1871" , 0x1180080943a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1872" , 0x1180080943a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1873" , 0x1180080943a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1874" , 0x1180080943a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1875" , 0x1180080943a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1876" , 0x1180080943aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1877" , 0x1180080943aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1878" , 0x1180080943ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1879" , 0x1180080943ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1880" , 0x1180080943ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1881" , 0x1180080943ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1882" , 0x1180080943ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1883" , 0x1180080943ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1884" , 0x1180080943ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1885" , 0x1180080943ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1886" , 0x1180080943af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1887" , 0x1180080943af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1888" , 0x1180080943b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1889" , 0x1180080943b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1890" , 0x1180080943b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1891" , 0x1180080943b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1892" , 0x1180080943b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1893" , 0x1180080943b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1894" , 0x1180080943b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1895" , 0x1180080943b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1896" , 0x1180080943b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1897" , 0x1180080943b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1898" , 0x1180080943b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1899" , 0x1180080943b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1900" , 0x1180080943b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1901" , 0x1180080943b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1902" , 0x1180080943b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1903" , 0x1180080943b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1904" , 0x1180080943b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1905" , 0x1180080943b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1906" , 0x1180080943b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1907" , 0x1180080943b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1908" , 0x1180080943ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1909" , 0x1180080943ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1910" , 0x1180080943bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1911" , 0x1180080943bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1912" , 0x1180080943bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1913" , 0x1180080943bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1914" , 0x1180080943bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1915" , 0x1180080943bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1916" , 0x1180080943be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1917" , 0x1180080943be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1918" , 0x1180080943bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1919" , 0x1180080943bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1920" , 0x1180080943c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1921" , 0x1180080943c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1922" , 0x1180080943c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1923" , 0x1180080943c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1924" , 0x1180080943c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1925" , 0x1180080943c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1926" , 0x1180080943c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1927" , 0x1180080943c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1928" , 0x1180080943c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1929" , 0x1180080943c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1930" , 0x1180080943c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1931" , 0x1180080943c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1932" , 0x1180080943c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1933" , 0x1180080943c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1934" , 0x1180080943c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1935" , 0x1180080943c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1936" , 0x1180080943c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1937" , 0x1180080943c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1938" , 0x1180080943c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1939" , 0x1180080943c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1940" , 0x1180080943ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1941" , 0x1180080943ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1942" , 0x1180080943cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1943" , 0x1180080943cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1944" , 0x1180080943cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1945" , 0x1180080943cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1946" , 0x1180080943cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1947" , 0x1180080943cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1948" , 0x1180080943ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1949" , 0x1180080943ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1950" , 0x1180080943cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1951" , 0x1180080943cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1952" , 0x1180080943d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1953" , 0x1180080943d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1954" , 0x1180080943d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1955" , 0x1180080943d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1956" , 0x1180080943d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1957" , 0x1180080943d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1958" , 0x1180080943d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1959" , 0x1180080943d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1960" , 0x1180080943d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1961" , 0x1180080943d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1962" , 0x1180080943d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1963" , 0x1180080943d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1964" , 0x1180080943d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1965" , 0x1180080943d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1966" , 0x1180080943d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1967" , 0x1180080943d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1968" , 0x1180080943d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1969" , 0x1180080943d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1970" , 0x1180080943d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1971" , 0x1180080943d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1972" , 0x1180080943da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1973" , 0x1180080943da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1974" , 0x1180080943db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1975" , 0x1180080943db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1976" , 0x1180080943dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1977" , 0x1180080943dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1978" , 0x1180080943dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1979" , 0x1180080943dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1980" , 0x1180080943de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1981" , 0x1180080943de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1982" , 0x1180080943df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1983" , 0x1180080943df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1984" , 0x1180080943e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1985" , 0x1180080943e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1986" , 0x1180080943e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1987" , 0x1180080943e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1988" , 0x1180080943e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1989" , 0x1180080943e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1990" , 0x1180080943e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1991" , 0x1180080943e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1992" , 0x1180080943e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1993" , 0x1180080943e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1994" , 0x1180080943e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1995" , 0x1180080943e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1996" , 0x1180080943e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1997" , 0x1180080943e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1998" , 0x1180080943e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP1999" , 0x1180080943e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2000" , 0x1180080943e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2001" , 0x1180080943e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2002" , 0x1180080943e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2003" , 0x1180080943e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2004" , 0x1180080943ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2005" , 0x1180080943ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2006" , 0x1180080943eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2007" , 0x1180080943eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2008" , 0x1180080943ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2009" , 0x1180080943ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2010" , 0x1180080943ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2011" , 0x1180080943ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2012" , 0x1180080943ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2013" , 0x1180080943ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2014" , 0x1180080943ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2015" , 0x1180080943ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2016" , 0x1180080943f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2017" , 0x1180080943f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2018" , 0x1180080943f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2019" , 0x1180080943f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2020" , 0x1180080943f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2021" , 0x1180080943f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2022" , 0x1180080943f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2023" , 0x1180080943f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2024" , 0x1180080943f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2025" , 0x1180080943f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2026" , 0x1180080943f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2027" , 0x1180080943f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2028" , 0x1180080943f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2029" , 0x1180080943f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2030" , 0x1180080943f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2031" , 0x1180080943f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2032" , 0x1180080943f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2033" , 0x1180080943f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2034" , 0x1180080943f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2035" , 0x1180080943f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2036" , 0x1180080943fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2037" , 0x1180080943fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2038" , 0x1180080943fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2039" , 0x1180080943fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2040" , 0x1180080943fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2041" , 0x1180080943fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2042" , 0x1180080943fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2043" , 0x1180080943fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2044" , 0x1180080943fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2045" , 0x1180080943fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2046" , 0x1180080943ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2047" , 0x1180080943ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2048" , 0x1180080944000ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2049" , 0x1180080944008ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2050" , 0x1180080944010ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2051" , 0x1180080944018ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2052" , 0x1180080944020ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2053" , 0x1180080944028ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2054" , 0x1180080944030ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2055" , 0x1180080944038ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2056" , 0x1180080944040ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2057" , 0x1180080944048ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2058" , 0x1180080944050ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2059" , 0x1180080944058ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2060" , 0x1180080944060ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2061" , 0x1180080944068ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2062" , 0x1180080944070ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2063" , 0x1180080944078ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2064" , 0x1180080944080ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2065" , 0x1180080944088ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2066" , 0x1180080944090ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2067" , 0x1180080944098ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2068" , 0x11800809440a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2069" , 0x11800809440a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2070" , 0x11800809440b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2071" , 0x11800809440b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2072" , 0x11800809440c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2073" , 0x11800809440c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2074" , 0x11800809440d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2075" , 0x11800809440d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2076" , 0x11800809440e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2077" , 0x11800809440e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2078" , 0x11800809440f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2079" , 0x11800809440f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2080" , 0x1180080944100ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2081" , 0x1180080944108ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2082" , 0x1180080944110ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2083" , 0x1180080944118ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2084" , 0x1180080944120ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2085" , 0x1180080944128ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2086" , 0x1180080944130ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2087" , 0x1180080944138ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2088" , 0x1180080944140ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2089" , 0x1180080944148ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2090" , 0x1180080944150ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2091" , 0x1180080944158ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2092" , 0x1180080944160ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2093" , 0x1180080944168ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2094" , 0x1180080944170ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2095" , 0x1180080944178ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2096" , 0x1180080944180ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2097" , 0x1180080944188ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2098" , 0x1180080944190ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2099" , 0x1180080944198ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2100" , 0x11800809441a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2101" , 0x11800809441a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2102" , 0x11800809441b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2103" , 0x11800809441b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2104" , 0x11800809441c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2105" , 0x11800809441c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2106" , 0x11800809441d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2107" , 0x11800809441d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2108" , 0x11800809441e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2109" , 0x11800809441e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2110" , 0x11800809441f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2111" , 0x11800809441f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2112" , 0x1180080944200ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2113" , 0x1180080944208ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2114" , 0x1180080944210ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2115" , 0x1180080944218ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2116" , 0x1180080944220ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2117" , 0x1180080944228ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2118" , 0x1180080944230ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2119" , 0x1180080944238ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2120" , 0x1180080944240ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2121" , 0x1180080944248ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2122" , 0x1180080944250ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2123" , 0x1180080944258ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2124" , 0x1180080944260ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2125" , 0x1180080944268ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2126" , 0x1180080944270ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2127" , 0x1180080944278ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2128" , 0x1180080944280ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2129" , 0x1180080944288ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2130" , 0x1180080944290ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2131" , 0x1180080944298ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2132" , 0x11800809442a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2133" , 0x11800809442a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2134" , 0x11800809442b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2135" , 0x11800809442b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2136" , 0x11800809442c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2137" , 0x11800809442c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2138" , 0x11800809442d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2139" , 0x11800809442d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2140" , 0x11800809442e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2141" , 0x11800809442e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2142" , 0x11800809442f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2143" , 0x11800809442f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2144" , 0x1180080944300ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2145" , 0x1180080944308ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2146" , 0x1180080944310ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2147" , 0x1180080944318ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2148" , 0x1180080944320ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2149" , 0x1180080944328ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2150" , 0x1180080944330ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2151" , 0x1180080944338ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2152" , 0x1180080944340ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2153" , 0x1180080944348ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2154" , 0x1180080944350ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2155" , 0x1180080944358ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2156" , 0x1180080944360ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2157" , 0x1180080944368ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2158" , 0x1180080944370ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2159" , 0x1180080944378ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2160" , 0x1180080944380ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2161" , 0x1180080944388ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2162" , 0x1180080944390ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2163" , 0x1180080944398ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2164" , 0x11800809443a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2165" , 0x11800809443a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2166" , 0x11800809443b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2167" , 0x11800809443b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2168" , 0x11800809443c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2169" , 0x11800809443c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2170" , 0x11800809443d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2171" , 0x11800809443d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2172" , 0x11800809443e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2173" , 0x11800809443e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2174" , 0x11800809443f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2175" , 0x11800809443f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2176" , 0x1180080944400ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2177" , 0x1180080944408ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2178" , 0x1180080944410ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2179" , 0x1180080944418ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2180" , 0x1180080944420ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2181" , 0x1180080944428ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2182" , 0x1180080944430ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2183" , 0x1180080944438ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2184" , 0x1180080944440ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2185" , 0x1180080944448ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2186" , 0x1180080944450ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2187" , 0x1180080944458ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2188" , 0x1180080944460ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2189" , 0x1180080944468ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2190" , 0x1180080944470ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2191" , 0x1180080944478ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2192" , 0x1180080944480ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2193" , 0x1180080944488ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2194" , 0x1180080944490ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2195" , 0x1180080944498ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2196" , 0x11800809444a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2197" , 0x11800809444a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2198" , 0x11800809444b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2199" , 0x11800809444b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2200" , 0x11800809444c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2201" , 0x11800809444c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2202" , 0x11800809444d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2203" , 0x11800809444d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2204" , 0x11800809444e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2205" , 0x11800809444e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2206" , 0x11800809444f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2207" , 0x11800809444f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2208" , 0x1180080944500ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2209" , 0x1180080944508ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2210" , 0x1180080944510ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2211" , 0x1180080944518ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2212" , 0x1180080944520ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2213" , 0x1180080944528ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2214" , 0x1180080944530ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2215" , 0x1180080944538ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2216" , 0x1180080944540ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2217" , 0x1180080944548ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2218" , 0x1180080944550ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2219" , 0x1180080944558ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2220" , 0x1180080944560ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2221" , 0x1180080944568ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2222" , 0x1180080944570ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2223" , 0x1180080944578ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2224" , 0x1180080944580ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2225" , 0x1180080944588ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2226" , 0x1180080944590ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2227" , 0x1180080944598ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2228" , 0x11800809445a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2229" , 0x11800809445a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2230" , 0x11800809445b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2231" , 0x11800809445b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2232" , 0x11800809445c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2233" , 0x11800809445c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2234" , 0x11800809445d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2235" , 0x11800809445d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2236" , 0x11800809445e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2237" , 0x11800809445e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2238" , 0x11800809445f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2239" , 0x11800809445f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2240" , 0x1180080944600ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2241" , 0x1180080944608ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2242" , 0x1180080944610ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2243" , 0x1180080944618ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2244" , 0x1180080944620ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2245" , 0x1180080944628ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2246" , 0x1180080944630ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2247" , 0x1180080944638ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2248" , 0x1180080944640ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2249" , 0x1180080944648ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2250" , 0x1180080944650ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2251" , 0x1180080944658ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2252" , 0x1180080944660ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2253" , 0x1180080944668ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2254" , 0x1180080944670ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2255" , 0x1180080944678ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2256" , 0x1180080944680ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2257" , 0x1180080944688ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2258" , 0x1180080944690ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2259" , 0x1180080944698ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2260" , 0x11800809446a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2261" , 0x11800809446a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2262" , 0x11800809446b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2263" , 0x11800809446b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2264" , 0x11800809446c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2265" , 0x11800809446c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2266" , 0x11800809446d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2267" , 0x11800809446d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2268" , 0x11800809446e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2269" , 0x11800809446e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2270" , 0x11800809446f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2271" , 0x11800809446f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2272" , 0x1180080944700ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2273" , 0x1180080944708ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2274" , 0x1180080944710ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2275" , 0x1180080944718ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2276" , 0x1180080944720ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2277" , 0x1180080944728ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2278" , 0x1180080944730ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2279" , 0x1180080944738ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2280" , 0x1180080944740ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2281" , 0x1180080944748ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2282" , 0x1180080944750ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2283" , 0x1180080944758ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2284" , 0x1180080944760ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2285" , 0x1180080944768ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2286" , 0x1180080944770ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2287" , 0x1180080944778ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2288" , 0x1180080944780ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2289" , 0x1180080944788ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2290" , 0x1180080944790ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2291" , 0x1180080944798ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2292" , 0x11800809447a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2293" , 0x11800809447a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2294" , 0x11800809447b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2295" , 0x11800809447b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2296" , 0x11800809447c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2297" , 0x11800809447c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2298" , 0x11800809447d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2299" , 0x11800809447d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2300" , 0x11800809447e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2301" , 0x11800809447e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2302" , 0x11800809447f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2303" , 0x11800809447f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2304" , 0x1180080944800ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2305" , 0x1180080944808ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2306" , 0x1180080944810ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2307" , 0x1180080944818ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2308" , 0x1180080944820ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2309" , 0x1180080944828ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2310" , 0x1180080944830ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2311" , 0x1180080944838ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2312" , 0x1180080944840ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2313" , 0x1180080944848ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2314" , 0x1180080944850ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2315" , 0x1180080944858ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2316" , 0x1180080944860ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2317" , 0x1180080944868ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2318" , 0x1180080944870ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2319" , 0x1180080944878ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2320" , 0x1180080944880ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2321" , 0x1180080944888ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2322" , 0x1180080944890ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2323" , 0x1180080944898ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2324" , 0x11800809448a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2325" , 0x11800809448a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2326" , 0x11800809448b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2327" , 0x11800809448b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2328" , 0x11800809448c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2329" , 0x11800809448c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2330" , 0x11800809448d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2331" , 0x11800809448d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2332" , 0x11800809448e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2333" , 0x11800809448e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2334" , 0x11800809448f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2335" , 0x11800809448f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2336" , 0x1180080944900ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2337" , 0x1180080944908ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2338" , 0x1180080944910ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2339" , 0x1180080944918ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2340" , 0x1180080944920ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2341" , 0x1180080944928ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2342" , 0x1180080944930ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2343" , 0x1180080944938ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2344" , 0x1180080944940ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2345" , 0x1180080944948ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2346" , 0x1180080944950ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2347" , 0x1180080944958ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2348" , 0x1180080944960ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2349" , 0x1180080944968ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2350" , 0x1180080944970ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2351" , 0x1180080944978ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2352" , 0x1180080944980ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2353" , 0x1180080944988ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2354" , 0x1180080944990ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2355" , 0x1180080944998ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2356" , 0x11800809449a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2357" , 0x11800809449a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2358" , 0x11800809449b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2359" , 0x11800809449b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2360" , 0x11800809449c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2361" , 0x11800809449c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2362" , 0x11800809449d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2363" , 0x11800809449d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2364" , 0x11800809449e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2365" , 0x11800809449e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2366" , 0x11800809449f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2367" , 0x11800809449f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2368" , 0x1180080944a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2369" , 0x1180080944a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2370" , 0x1180080944a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2371" , 0x1180080944a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2372" , 0x1180080944a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2373" , 0x1180080944a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2374" , 0x1180080944a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2375" , 0x1180080944a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2376" , 0x1180080944a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2377" , 0x1180080944a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2378" , 0x1180080944a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2379" , 0x1180080944a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2380" , 0x1180080944a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2381" , 0x1180080944a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2382" , 0x1180080944a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2383" , 0x1180080944a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2384" , 0x1180080944a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2385" , 0x1180080944a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2386" , 0x1180080944a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2387" , 0x1180080944a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2388" , 0x1180080944aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2389" , 0x1180080944aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2390" , 0x1180080944ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2391" , 0x1180080944ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2392" , 0x1180080944ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2393" , 0x1180080944ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2394" , 0x1180080944ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2395" , 0x1180080944ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2396" , 0x1180080944ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2397" , 0x1180080944ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2398" , 0x1180080944af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2399" , 0x1180080944af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2400" , 0x1180080944b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2401" , 0x1180080944b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2402" , 0x1180080944b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2403" , 0x1180080944b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2404" , 0x1180080944b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2405" , 0x1180080944b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2406" , 0x1180080944b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2407" , 0x1180080944b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2408" , 0x1180080944b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2409" , 0x1180080944b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2410" , 0x1180080944b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2411" , 0x1180080944b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2412" , 0x1180080944b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2413" , 0x1180080944b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2414" , 0x1180080944b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2415" , 0x1180080944b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2416" , 0x1180080944b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2417" , 0x1180080944b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2418" , 0x1180080944b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2419" , 0x1180080944b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2420" , 0x1180080944ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2421" , 0x1180080944ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2422" , 0x1180080944bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2423" , 0x1180080944bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2424" , 0x1180080944bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2425" , 0x1180080944bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2426" , 0x1180080944bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2427" , 0x1180080944bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2428" , 0x1180080944be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2429" , 0x1180080944be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2430" , 0x1180080944bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2431" , 0x1180080944bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2432" , 0x1180080944c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2433" , 0x1180080944c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2434" , 0x1180080944c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2435" , 0x1180080944c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2436" , 0x1180080944c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2437" , 0x1180080944c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2438" , 0x1180080944c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2439" , 0x1180080944c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2440" , 0x1180080944c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2441" , 0x1180080944c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2442" , 0x1180080944c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2443" , 0x1180080944c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2444" , 0x1180080944c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2445" , 0x1180080944c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2446" , 0x1180080944c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2447" , 0x1180080944c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2448" , 0x1180080944c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2449" , 0x1180080944c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2450" , 0x1180080944c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2451" , 0x1180080944c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2452" , 0x1180080944ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2453" , 0x1180080944ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2454" , 0x1180080944cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2455" , 0x1180080944cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2456" , 0x1180080944cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2457" , 0x1180080944cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2458" , 0x1180080944cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2459" , 0x1180080944cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2460" , 0x1180080944ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2461" , 0x1180080944ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2462" , 0x1180080944cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2463" , 0x1180080944cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2464" , 0x1180080944d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2465" , 0x1180080944d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2466" , 0x1180080944d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2467" , 0x1180080944d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2468" , 0x1180080944d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2469" , 0x1180080944d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2470" , 0x1180080944d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2471" , 0x1180080944d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2472" , 0x1180080944d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2473" , 0x1180080944d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2474" , 0x1180080944d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2475" , 0x1180080944d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2476" , 0x1180080944d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2477" , 0x1180080944d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2478" , 0x1180080944d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2479" , 0x1180080944d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2480" , 0x1180080944d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2481" , 0x1180080944d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2482" , 0x1180080944d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2483" , 0x1180080944d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2484" , 0x1180080944da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2485" , 0x1180080944da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2486" , 0x1180080944db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2487" , 0x1180080944db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2488" , 0x1180080944dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2489" , 0x1180080944dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2490" , 0x1180080944dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2491" , 0x1180080944dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2492" , 0x1180080944de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2493" , 0x1180080944de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2494" , 0x1180080944df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2495" , 0x1180080944df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2496" , 0x1180080944e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2497" , 0x1180080944e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2498" , 0x1180080944e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2499" , 0x1180080944e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2500" , 0x1180080944e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2501" , 0x1180080944e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2502" , 0x1180080944e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2503" , 0x1180080944e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2504" , 0x1180080944e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2505" , 0x1180080944e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2506" , 0x1180080944e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2507" , 0x1180080944e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2508" , 0x1180080944e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2509" , 0x1180080944e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2510" , 0x1180080944e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2511" , 0x1180080944e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2512" , 0x1180080944e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2513" , 0x1180080944e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2514" , 0x1180080944e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2515" , 0x1180080944e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2516" , 0x1180080944ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2517" , 0x1180080944ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2518" , 0x1180080944eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2519" , 0x1180080944eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2520" , 0x1180080944ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2521" , 0x1180080944ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2522" , 0x1180080944ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2523" , 0x1180080944ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2524" , 0x1180080944ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2525" , 0x1180080944ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2526" , 0x1180080944ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2527" , 0x1180080944ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2528" , 0x1180080944f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2529" , 0x1180080944f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2530" , 0x1180080944f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2531" , 0x1180080944f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2532" , 0x1180080944f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2533" , 0x1180080944f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2534" , 0x1180080944f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2535" , 0x1180080944f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2536" , 0x1180080944f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2537" , 0x1180080944f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2538" , 0x1180080944f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2539" , 0x1180080944f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2540" , 0x1180080944f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2541" , 0x1180080944f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2542" , 0x1180080944f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2543" , 0x1180080944f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2544" , 0x1180080944f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2545" , 0x1180080944f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2546" , 0x1180080944f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2547" , 0x1180080944f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2548" , 0x1180080944fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2549" , 0x1180080944fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2550" , 0x1180080944fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2551" , 0x1180080944fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2552" , 0x1180080944fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2553" , 0x1180080944fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2554" , 0x1180080944fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2555" , 0x1180080944fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2556" , 0x1180080944fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2557" , 0x1180080944fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2558" , 0x1180080944ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP2559" , 0x1180080944ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16128" , 0x118008095f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16129" , 0x118008095f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16130" , 0x118008095f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16131" , 0x118008095f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16132" , 0x118008095f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16133" , 0x118008095f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16134" , 0x118008095f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16135" , 0x118008095f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16136" , 0x118008095f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16137" , 0x118008095f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16138" , 0x118008095f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16139" , 0x118008095f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16140" , 0x118008095f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16141" , 0x118008095f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16142" , 0x118008095f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16143" , 0x118008095f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16144" , 0x118008095f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16145" , 0x118008095f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16146" , 0x118008095f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16147" , 0x118008095f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16148" , 0x118008095f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16149" , 0x118008095f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16150" , 0x118008095f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16151" , 0x118008095f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16152" , 0x118008095f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16153" , 0x118008095f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16154" , 0x118008095f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16155" , 0x118008095f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16156" , 0x118008095f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16157" , 0x118008095f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16158" , 0x118008095f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16159" , 0x118008095f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16160" , 0x118008095f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16161" , 0x118008095f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16162" , 0x118008095f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16163" , 0x118008095f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16164" , 0x118008095f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16165" , 0x118008095f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16166" , 0x118008095f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16167" , 0x118008095f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16168" , 0x118008095f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16169" , 0x118008095f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16170" , 0x118008095f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16171" , 0x118008095f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16172" , 0x118008095f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16173" , 0x118008095f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16174" , 0x118008095f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16175" , 0x118008095f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16176" , 0x118008095f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16177" , 0x118008095f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16178" , 0x118008095f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16179" , 0x118008095f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16180" , 0x118008095f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16181" , 0x118008095f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16182" , 0x118008095f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16183" , 0x118008095f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16184" , 0x118008095f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16185" , 0x118008095f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16186" , 0x118008095f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16187" , 0x118008095f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16188" , 0x118008095f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16189" , 0x118008095f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16190" , 0x118008095f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16191" , 0x118008095f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16192" , 0x118008095fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16193" , 0x118008095fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16194" , 0x118008095fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16195" , 0x118008095fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16196" , 0x118008095fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16197" , 0x118008095fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16198" , 0x118008095fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16199" , 0x118008095fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16200" , 0x118008095fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16201" , 0x118008095fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16202" , 0x118008095fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16203" , 0x118008095fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16204" , 0x118008095fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16205" , 0x118008095fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16206" , 0x118008095fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16207" , 0x118008095fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16208" , 0x118008095fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16209" , 0x118008095fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16210" , 0x118008095fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16211" , 0x118008095fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16212" , 0x118008095faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16213" , 0x118008095faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16214" , 0x118008095fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16215" , 0x118008095fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16216" , 0x118008095fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16217" , 0x118008095fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16218" , 0x118008095fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16219" , 0x118008095fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16220" , 0x118008095fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16221" , 0x118008095fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16222" , 0x118008095faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16223" , 0x118008095faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16224" , 0x118008095fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16225" , 0x118008095fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16226" , 0x118008095fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16227" , 0x118008095fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16228" , 0x118008095fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16229" , 0x118008095fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16230" , 0x118008095fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16231" , 0x118008095fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16232" , 0x118008095fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16233" , 0x118008095fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16234" , 0x118008095fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16235" , 0x118008095fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16236" , 0x118008095fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16237" , 0x118008095fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16238" , 0x118008095fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16239" , 0x118008095fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16240" , 0x118008095fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16241" , 0x118008095fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16242" , 0x118008095fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16243" , 0x118008095fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16244" , 0x118008095fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16245" , 0x118008095fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16246" , 0x118008095fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16247" , 0x118008095fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16248" , 0x118008095fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16249" , 0x118008095fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16250" , 0x118008095fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16251" , 0x118008095fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16252" , 0x118008095fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16253" , 0x118008095fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16254" , 0x118008095fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16255" , 0x118008095fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16256" , 0x118008095fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16257" , 0x118008095fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16258" , 0x118008095fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16259" , 0x118008095fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16260" , 0x118008095fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16261" , 0x118008095fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16262" , 0x118008095fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16263" , 0x118008095fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16264" , 0x118008095fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16265" , 0x118008095fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16266" , 0x118008095fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16267" , 0x118008095fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16268" , 0x118008095fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16269" , 0x118008095fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16270" , 0x118008095fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16271" , 0x118008095fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16272" , 0x118008095fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16273" , 0x118008095fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16274" , 0x118008095fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16275" , 0x118008095fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16276" , 0x118008095fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16277" , 0x118008095fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16278" , 0x118008095fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16279" , 0x118008095fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16280" , 0x118008095fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16281" , 0x118008095fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16282" , 0x118008095fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16283" , 0x118008095fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16284" , 0x118008095fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16285" , 0x118008095fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16286" , 0x118008095fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16287" , 0x118008095fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16288" , 0x118008095fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16289" , 0x118008095fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16290" , 0x118008095fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16291" , 0x118008095fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16292" , 0x118008095fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16293" , 0x118008095fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16294" , 0x118008095fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16295" , 0x118008095fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16296" , 0x118008095fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16297" , 0x118008095fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16298" , 0x118008095fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16299" , 0x118008095fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16300" , 0x118008095fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16301" , 0x118008095fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16302" , 0x118008095fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16303" , 0x118008095fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16304" , 0x118008095fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16305" , 0x118008095fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16306" , 0x118008095fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16307" , 0x118008095fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16308" , 0x118008095fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16309" , 0x118008095fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16310" , 0x118008095fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16311" , 0x118008095fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16312" , 0x118008095fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16313" , 0x118008095fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16314" , 0x118008095fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16315" , 0x118008095fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16316" , 0x118008095fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16317" , 0x118008095fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16318" , 0x118008095fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16319" , 0x118008095fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16320" , 0x118008095fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16321" , 0x118008095fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16322" , 0x118008095fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16323" , 0x118008095fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16324" , 0x118008095fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16325" , 0x118008095fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16326" , 0x118008095fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16327" , 0x118008095fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16328" , 0x118008095fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16329" , 0x118008095fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16330" , 0x118008095fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16331" , 0x118008095fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16332" , 0x118008095fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16333" , 0x118008095fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16334" , 0x118008095fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16335" , 0x118008095fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16336" , 0x118008095fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16337" , 0x118008095fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16338" , 0x118008095fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16339" , 0x118008095fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16340" , 0x118008095fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16341" , 0x118008095fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16342" , 0x118008095feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16343" , 0x118008095feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16344" , 0x118008095fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16345" , 0x118008095fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16346" , 0x118008095fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16347" , 0x118008095fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16348" , 0x118008095fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16349" , 0x118008095fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16350" , 0x118008095fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16351" , 0x118008095fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16352" , 0x118008095ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16353" , 0x118008095ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16354" , 0x118008095ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16355" , 0x118008095ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16356" , 0x118008095ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16357" , 0x118008095ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16358" , 0x118008095ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16359" , 0x118008095ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16360" , 0x118008095ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16361" , 0x118008095ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16362" , 0x118008095ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16363" , 0x118008095ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16364" , 0x118008095ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16365" , 0x118008095ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16366" , 0x118008095ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16367" , 0x118008095ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16368" , 0x118008095ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16369" , 0x118008095ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16370" , 0x118008095ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16371" , 0x118008095ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16372" , 0x118008095ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16373" , 0x118008095ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16374" , 0x118008095ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16375" , 0x118008095ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16376" , 0x118008095ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16377" , 0x118008095ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16378" , 0x118008095ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16379" , 0x118008095ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16380" , 0x118008095ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16381" , 0x118008095ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16382" , 0x118008095fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_COP0_MAP16383" , 0x118008095fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"L2C_CTL" , 0x1180080800000ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"L2C_DUT_MAP0" , 0x1180080e00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1" , 0x1180080e00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2" , 0x1180080e00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP3" , 0x1180080e00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP4" , 0x1180080e00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP5" , 0x1180080e00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP6" , 0x1180080e00030ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP7" , 0x1180080e00038ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP8" , 0x1180080e00040ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP9" , 0x1180080e00048ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP10" , 0x1180080e00050ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP11" , 0x1180080e00058ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP12" , 0x1180080e00060ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP13" , 0x1180080e00068ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP14" , 0x1180080e00070ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP15" , 0x1180080e00078ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP16" , 0x1180080e00080ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP17" , 0x1180080e00088ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP18" , 0x1180080e00090ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP19" , 0x1180080e00098ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP20" , 0x1180080e000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP21" , 0x1180080e000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP22" , 0x1180080e000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP23" , 0x1180080e000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP24" , 0x1180080e000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP25" , 0x1180080e000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP26" , 0x1180080e000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP27" , 0x1180080e000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP28" , 0x1180080e000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP29" , 0x1180080e000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP30" , 0x1180080e000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP31" , 0x1180080e000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP32" , 0x1180080e00100ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP33" , 0x1180080e00108ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP34" , 0x1180080e00110ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP35" , 0x1180080e00118ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP36" , 0x1180080e00120ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP37" , 0x1180080e00128ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP38" , 0x1180080e00130ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP39" , 0x1180080e00138ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP40" , 0x1180080e00140ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP41" , 0x1180080e00148ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP42" , 0x1180080e00150ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP43" , 0x1180080e00158ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP44" , 0x1180080e00160ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP45" , 0x1180080e00168ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP46" , 0x1180080e00170ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP47" , 0x1180080e00178ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP48" , 0x1180080e00180ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP49" , 0x1180080e00188ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP50" , 0x1180080e00190ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP51" , 0x1180080e00198ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP52" , 0x1180080e001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP53" , 0x1180080e001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP54" , 0x1180080e001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP55" , 0x1180080e001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP56" , 0x1180080e001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP57" , 0x1180080e001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP58" , 0x1180080e001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP59" , 0x1180080e001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP60" , 0x1180080e001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP61" , 0x1180080e001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP62" , 0x1180080e001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP63" , 0x1180080e001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP64" , 0x1180080e00200ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP65" , 0x1180080e00208ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP66" , 0x1180080e00210ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP67" , 0x1180080e00218ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP68" , 0x1180080e00220ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP69" , 0x1180080e00228ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP70" , 0x1180080e00230ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP71" , 0x1180080e00238ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP72" , 0x1180080e00240ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP73" , 0x1180080e00248ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP74" , 0x1180080e00250ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP75" , 0x1180080e00258ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP76" , 0x1180080e00260ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP77" , 0x1180080e00268ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP78" , 0x1180080e00270ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP79" , 0x1180080e00278ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP80" , 0x1180080e00280ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP81" , 0x1180080e00288ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP82" , 0x1180080e00290ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP83" , 0x1180080e00298ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP84" , 0x1180080e002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP85" , 0x1180080e002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP86" , 0x1180080e002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP87" , 0x1180080e002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP88" , 0x1180080e002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP89" , 0x1180080e002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP90" , 0x1180080e002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP91" , 0x1180080e002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP92" , 0x1180080e002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP93" , 0x1180080e002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP94" , 0x1180080e002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP95" , 0x1180080e002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP96" , 0x1180080e00300ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP97" , 0x1180080e00308ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP98" , 0x1180080e00310ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP99" , 0x1180080e00318ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP100" , 0x1180080e00320ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP101" , 0x1180080e00328ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP102" , 0x1180080e00330ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP103" , 0x1180080e00338ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP104" , 0x1180080e00340ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP105" , 0x1180080e00348ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP106" , 0x1180080e00350ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP107" , 0x1180080e00358ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP108" , 0x1180080e00360ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP109" , 0x1180080e00368ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP110" , 0x1180080e00370ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP111" , 0x1180080e00378ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP112" , 0x1180080e00380ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP113" , 0x1180080e00388ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP114" , 0x1180080e00390ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP115" , 0x1180080e00398ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP116" , 0x1180080e003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP117" , 0x1180080e003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP118" , 0x1180080e003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP119" , 0x1180080e003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP120" , 0x1180080e003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP121" , 0x1180080e003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP122" , 0x1180080e003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP123" , 0x1180080e003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP124" , 0x1180080e003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP125" , 0x1180080e003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP126" , 0x1180080e003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP127" , 0x1180080e003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP128" , 0x1180080e00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP129" , 0x1180080e00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP130" , 0x1180080e00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP131" , 0x1180080e00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP132" , 0x1180080e00420ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP133" , 0x1180080e00428ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP134" , 0x1180080e00430ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP135" , 0x1180080e00438ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP136" , 0x1180080e00440ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP137" , 0x1180080e00448ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP138" , 0x1180080e00450ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP139" , 0x1180080e00458ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP140" , 0x1180080e00460ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP141" , 0x1180080e00468ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP142" , 0x1180080e00470ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP143" , 0x1180080e00478ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP144" , 0x1180080e00480ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP145" , 0x1180080e00488ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP146" , 0x1180080e00490ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP147" , 0x1180080e00498ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP148" , 0x1180080e004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP149" , 0x1180080e004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP150" , 0x1180080e004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP151" , 0x1180080e004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP152" , 0x1180080e004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP153" , 0x1180080e004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP154" , 0x1180080e004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP155" , 0x1180080e004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP156" , 0x1180080e004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP157" , 0x1180080e004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP158" , 0x1180080e004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP159" , 0x1180080e004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP160" , 0x1180080e00500ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP161" , 0x1180080e00508ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP162" , 0x1180080e00510ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP163" , 0x1180080e00518ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP164" , 0x1180080e00520ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP165" , 0x1180080e00528ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP166" , 0x1180080e00530ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP167" , 0x1180080e00538ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP168" , 0x1180080e00540ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP169" , 0x1180080e00548ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP170" , 0x1180080e00550ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP171" , 0x1180080e00558ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP172" , 0x1180080e00560ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP173" , 0x1180080e00568ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP174" , 0x1180080e00570ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP175" , 0x1180080e00578ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP176" , 0x1180080e00580ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP177" , 0x1180080e00588ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP178" , 0x1180080e00590ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP179" , 0x1180080e00598ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP180" , 0x1180080e005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP181" , 0x1180080e005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP182" , 0x1180080e005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP183" , 0x1180080e005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP184" , 0x1180080e005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP185" , 0x1180080e005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP186" , 0x1180080e005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP187" , 0x1180080e005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP188" , 0x1180080e005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP189" , 0x1180080e005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP190" , 0x1180080e005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP191" , 0x1180080e005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP192" , 0x1180080e00600ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP193" , 0x1180080e00608ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP194" , 0x1180080e00610ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP195" , 0x1180080e00618ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP196" , 0x1180080e00620ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP197" , 0x1180080e00628ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP198" , 0x1180080e00630ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP199" , 0x1180080e00638ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP200" , 0x1180080e00640ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP201" , 0x1180080e00648ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP202" , 0x1180080e00650ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP203" , 0x1180080e00658ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP204" , 0x1180080e00660ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP205" , 0x1180080e00668ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP206" , 0x1180080e00670ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP207" , 0x1180080e00678ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP208" , 0x1180080e00680ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP209" , 0x1180080e00688ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP210" , 0x1180080e00690ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP211" , 0x1180080e00698ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP212" , 0x1180080e006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP213" , 0x1180080e006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP214" , 0x1180080e006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP215" , 0x1180080e006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP216" , 0x1180080e006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP217" , 0x1180080e006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP218" , 0x1180080e006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP219" , 0x1180080e006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP220" , 0x1180080e006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP221" , 0x1180080e006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP222" , 0x1180080e006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP223" , 0x1180080e006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP224" , 0x1180080e00700ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP225" , 0x1180080e00708ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP226" , 0x1180080e00710ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP227" , 0x1180080e00718ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP228" , 0x1180080e00720ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP229" , 0x1180080e00728ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP230" , 0x1180080e00730ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP231" , 0x1180080e00738ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP232" , 0x1180080e00740ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP233" , 0x1180080e00748ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP234" , 0x1180080e00750ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP235" , 0x1180080e00758ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP236" , 0x1180080e00760ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP237" , 0x1180080e00768ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP238" , 0x1180080e00770ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP239" , 0x1180080e00778ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP240" , 0x1180080e00780ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP241" , 0x1180080e00788ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP242" , 0x1180080e00790ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP243" , 0x1180080e00798ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP244" , 0x1180080e007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP245" , 0x1180080e007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP246" , 0x1180080e007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP247" , 0x1180080e007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP248" , 0x1180080e007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP249" , 0x1180080e007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP250" , 0x1180080e007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP251" , 0x1180080e007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP252" , 0x1180080e007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP253" , 0x1180080e007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP254" , 0x1180080e007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP255" , 0x1180080e007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP256" , 0x1180080e00800ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP257" , 0x1180080e00808ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP258" , 0x1180080e00810ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP259" , 0x1180080e00818ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP260" , 0x1180080e00820ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP261" , 0x1180080e00828ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP262" , 0x1180080e00830ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP263" , 0x1180080e00838ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP264" , 0x1180080e00840ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP265" , 0x1180080e00848ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP266" , 0x1180080e00850ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP267" , 0x1180080e00858ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP268" , 0x1180080e00860ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP269" , 0x1180080e00868ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP270" , 0x1180080e00870ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP271" , 0x1180080e00878ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP272" , 0x1180080e00880ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP273" , 0x1180080e00888ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP274" , 0x1180080e00890ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP275" , 0x1180080e00898ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP276" , 0x1180080e008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP277" , 0x1180080e008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP278" , 0x1180080e008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP279" , 0x1180080e008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP280" , 0x1180080e008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP281" , 0x1180080e008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP282" , 0x1180080e008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP283" , 0x1180080e008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP284" , 0x1180080e008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP285" , 0x1180080e008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP286" , 0x1180080e008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP287" , 0x1180080e008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP288" , 0x1180080e00900ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP289" , 0x1180080e00908ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP290" , 0x1180080e00910ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP291" , 0x1180080e00918ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP292" , 0x1180080e00920ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP293" , 0x1180080e00928ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP294" , 0x1180080e00930ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP295" , 0x1180080e00938ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP296" , 0x1180080e00940ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP297" , 0x1180080e00948ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP298" , 0x1180080e00950ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP299" , 0x1180080e00958ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP300" , 0x1180080e00960ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP301" , 0x1180080e00968ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP302" , 0x1180080e00970ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP303" , 0x1180080e00978ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP304" , 0x1180080e00980ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP305" , 0x1180080e00988ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP306" , 0x1180080e00990ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP307" , 0x1180080e00998ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP308" , 0x1180080e009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP309" , 0x1180080e009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP310" , 0x1180080e009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP311" , 0x1180080e009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP312" , 0x1180080e009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP313" , 0x1180080e009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP314" , 0x1180080e009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP315" , 0x1180080e009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP316" , 0x1180080e009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP317" , 0x1180080e009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP318" , 0x1180080e009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP319" , 0x1180080e009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP320" , 0x1180080e00a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP321" , 0x1180080e00a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP322" , 0x1180080e00a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP323" , 0x1180080e00a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP324" , 0x1180080e00a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP325" , 0x1180080e00a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP326" , 0x1180080e00a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP327" , 0x1180080e00a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP328" , 0x1180080e00a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP329" , 0x1180080e00a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP330" , 0x1180080e00a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP331" , 0x1180080e00a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP332" , 0x1180080e00a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP333" , 0x1180080e00a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP334" , 0x1180080e00a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP335" , 0x1180080e00a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP336" , 0x1180080e00a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP337" , 0x1180080e00a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP338" , 0x1180080e00a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP339" , 0x1180080e00a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP340" , 0x1180080e00aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP341" , 0x1180080e00aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP342" , 0x1180080e00ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP343" , 0x1180080e00ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP344" , 0x1180080e00ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP345" , 0x1180080e00ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP346" , 0x1180080e00ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP347" , 0x1180080e00ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP348" , 0x1180080e00ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP349" , 0x1180080e00ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP350" , 0x1180080e00af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP351" , 0x1180080e00af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP352" , 0x1180080e00b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP353" , 0x1180080e00b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP354" , 0x1180080e00b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP355" , 0x1180080e00b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP356" , 0x1180080e00b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP357" , 0x1180080e00b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP358" , 0x1180080e00b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP359" , 0x1180080e00b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP360" , 0x1180080e00b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP361" , 0x1180080e00b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP362" , 0x1180080e00b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP363" , 0x1180080e00b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP364" , 0x1180080e00b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP365" , 0x1180080e00b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP366" , 0x1180080e00b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP367" , 0x1180080e00b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP368" , 0x1180080e00b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP369" , 0x1180080e00b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP370" , 0x1180080e00b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP371" , 0x1180080e00b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP372" , 0x1180080e00ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP373" , 0x1180080e00ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP374" , 0x1180080e00bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP375" , 0x1180080e00bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP376" , 0x1180080e00bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP377" , 0x1180080e00bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP378" , 0x1180080e00bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP379" , 0x1180080e00bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP380" , 0x1180080e00be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP381" , 0x1180080e00be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP382" , 0x1180080e00bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP383" , 0x1180080e00bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP384" , 0x1180080e00c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP385" , 0x1180080e00c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP386" , 0x1180080e00c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP387" , 0x1180080e00c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP388" , 0x1180080e00c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP389" , 0x1180080e00c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP390" , 0x1180080e00c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP391" , 0x1180080e00c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP392" , 0x1180080e00c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP393" , 0x1180080e00c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP394" , 0x1180080e00c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP395" , 0x1180080e00c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP396" , 0x1180080e00c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP397" , 0x1180080e00c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP398" , 0x1180080e00c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP399" , 0x1180080e00c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP400" , 0x1180080e00c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP401" , 0x1180080e00c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP402" , 0x1180080e00c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP403" , 0x1180080e00c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP404" , 0x1180080e00ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP405" , 0x1180080e00ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP406" , 0x1180080e00cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP407" , 0x1180080e00cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP408" , 0x1180080e00cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP409" , 0x1180080e00cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP410" , 0x1180080e00cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP411" , 0x1180080e00cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP412" , 0x1180080e00ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP413" , 0x1180080e00ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP414" , 0x1180080e00cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP415" , 0x1180080e00cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP416" , 0x1180080e00d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP417" , 0x1180080e00d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP418" , 0x1180080e00d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP419" , 0x1180080e00d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP420" , 0x1180080e00d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP421" , 0x1180080e00d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP422" , 0x1180080e00d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP423" , 0x1180080e00d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP424" , 0x1180080e00d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP425" , 0x1180080e00d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP426" , 0x1180080e00d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP427" , 0x1180080e00d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP428" , 0x1180080e00d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP429" , 0x1180080e00d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP430" , 0x1180080e00d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP431" , 0x1180080e00d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP432" , 0x1180080e00d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP433" , 0x1180080e00d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP434" , 0x1180080e00d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP435" , 0x1180080e00d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP436" , 0x1180080e00da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP437" , 0x1180080e00da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP438" , 0x1180080e00db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP439" , 0x1180080e00db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP440" , 0x1180080e00dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP441" , 0x1180080e00dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP442" , 0x1180080e00dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP443" , 0x1180080e00dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP444" , 0x1180080e00de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP445" , 0x1180080e00de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP446" , 0x1180080e00df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP447" , 0x1180080e00df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP448" , 0x1180080e00e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP449" , 0x1180080e00e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP450" , 0x1180080e00e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP451" , 0x1180080e00e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP452" , 0x1180080e00e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP453" , 0x1180080e00e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP454" , 0x1180080e00e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP455" , 0x1180080e00e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP456" , 0x1180080e00e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP457" , 0x1180080e00e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP458" , 0x1180080e00e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP459" , 0x1180080e00e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP460" , 0x1180080e00e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP461" , 0x1180080e00e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP462" , 0x1180080e00e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP463" , 0x1180080e00e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP464" , 0x1180080e00e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP465" , 0x1180080e00e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP466" , 0x1180080e00e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP467" , 0x1180080e00e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP468" , 0x1180080e00ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP469" , 0x1180080e00ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP470" , 0x1180080e00eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP471" , 0x1180080e00eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP472" , 0x1180080e00ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP473" , 0x1180080e00ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP474" , 0x1180080e00ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP475" , 0x1180080e00ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP476" , 0x1180080e00ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP477" , 0x1180080e00ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP478" , 0x1180080e00ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP479" , 0x1180080e00ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP480" , 0x1180080e00f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP481" , 0x1180080e00f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP482" , 0x1180080e00f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP483" , 0x1180080e00f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP484" , 0x1180080e00f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP485" , 0x1180080e00f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP486" , 0x1180080e00f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP487" , 0x1180080e00f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP488" , 0x1180080e00f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP489" , 0x1180080e00f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP490" , 0x1180080e00f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP491" , 0x1180080e00f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP492" , 0x1180080e00f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP493" , 0x1180080e00f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP494" , 0x1180080e00f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP495" , 0x1180080e00f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP496" , 0x1180080e00f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP497" , 0x1180080e00f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP498" , 0x1180080e00f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP499" , 0x1180080e00f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP500" , 0x1180080e00fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP501" , 0x1180080e00fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP502" , 0x1180080e00fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP503" , 0x1180080e00fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP504" , 0x1180080e00fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP505" , 0x1180080e00fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP506" , 0x1180080e00fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP507" , 0x1180080e00fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP508" , 0x1180080e00fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP509" , 0x1180080e00fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP510" , 0x1180080e00ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP511" , 0x1180080e00ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP512" , 0x1180080e01000ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP513" , 0x1180080e01008ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP514" , 0x1180080e01010ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP515" , 0x1180080e01018ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP516" , 0x1180080e01020ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP517" , 0x1180080e01028ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP518" , 0x1180080e01030ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP519" , 0x1180080e01038ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP520" , 0x1180080e01040ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP521" , 0x1180080e01048ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP522" , 0x1180080e01050ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP523" , 0x1180080e01058ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP524" , 0x1180080e01060ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP525" , 0x1180080e01068ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP526" , 0x1180080e01070ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP527" , 0x1180080e01078ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP528" , 0x1180080e01080ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP529" , 0x1180080e01088ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP530" , 0x1180080e01090ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP531" , 0x1180080e01098ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP532" , 0x1180080e010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP533" , 0x1180080e010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP534" , 0x1180080e010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP535" , 0x1180080e010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP536" , 0x1180080e010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP537" , 0x1180080e010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP538" , 0x1180080e010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP539" , 0x1180080e010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP540" , 0x1180080e010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP541" , 0x1180080e010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP542" , 0x1180080e010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP543" , 0x1180080e010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP544" , 0x1180080e01100ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP545" , 0x1180080e01108ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP546" , 0x1180080e01110ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP547" , 0x1180080e01118ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP548" , 0x1180080e01120ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP549" , 0x1180080e01128ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP550" , 0x1180080e01130ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP551" , 0x1180080e01138ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP552" , 0x1180080e01140ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP553" , 0x1180080e01148ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP554" , 0x1180080e01150ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP555" , 0x1180080e01158ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP556" , 0x1180080e01160ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP557" , 0x1180080e01168ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP558" , 0x1180080e01170ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP559" , 0x1180080e01178ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP560" , 0x1180080e01180ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP561" , 0x1180080e01188ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP562" , 0x1180080e01190ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP563" , 0x1180080e01198ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP564" , 0x1180080e011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP565" , 0x1180080e011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP566" , 0x1180080e011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP567" , 0x1180080e011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP568" , 0x1180080e011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP569" , 0x1180080e011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP570" , 0x1180080e011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP571" , 0x1180080e011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP572" , 0x1180080e011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP573" , 0x1180080e011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP574" , 0x1180080e011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP575" , 0x1180080e011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP576" , 0x1180080e01200ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP577" , 0x1180080e01208ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP578" , 0x1180080e01210ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP579" , 0x1180080e01218ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP580" , 0x1180080e01220ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP581" , 0x1180080e01228ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP582" , 0x1180080e01230ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP583" , 0x1180080e01238ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP584" , 0x1180080e01240ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP585" , 0x1180080e01248ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP586" , 0x1180080e01250ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP587" , 0x1180080e01258ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP588" , 0x1180080e01260ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP589" , 0x1180080e01268ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP590" , 0x1180080e01270ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP591" , 0x1180080e01278ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP592" , 0x1180080e01280ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP593" , 0x1180080e01288ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP594" , 0x1180080e01290ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP595" , 0x1180080e01298ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP596" , 0x1180080e012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP597" , 0x1180080e012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP598" , 0x1180080e012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP599" , 0x1180080e012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP600" , 0x1180080e012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP601" , 0x1180080e012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP602" , 0x1180080e012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP603" , 0x1180080e012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP604" , 0x1180080e012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP605" , 0x1180080e012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP606" , 0x1180080e012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP607" , 0x1180080e012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP608" , 0x1180080e01300ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP609" , 0x1180080e01308ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP610" , 0x1180080e01310ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP611" , 0x1180080e01318ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP612" , 0x1180080e01320ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP613" , 0x1180080e01328ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP614" , 0x1180080e01330ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP615" , 0x1180080e01338ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP616" , 0x1180080e01340ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP617" , 0x1180080e01348ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP618" , 0x1180080e01350ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP619" , 0x1180080e01358ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP620" , 0x1180080e01360ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP621" , 0x1180080e01368ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP622" , 0x1180080e01370ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP623" , 0x1180080e01378ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP624" , 0x1180080e01380ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP625" , 0x1180080e01388ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP626" , 0x1180080e01390ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP627" , 0x1180080e01398ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP628" , 0x1180080e013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP629" , 0x1180080e013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP630" , 0x1180080e013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP631" , 0x1180080e013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP632" , 0x1180080e013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP633" , 0x1180080e013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP634" , 0x1180080e013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP635" , 0x1180080e013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP636" , 0x1180080e013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP637" , 0x1180080e013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP638" , 0x1180080e013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP639" , 0x1180080e013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP640" , 0x1180080e01400ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP641" , 0x1180080e01408ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP642" , 0x1180080e01410ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP643" , 0x1180080e01418ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP644" , 0x1180080e01420ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP645" , 0x1180080e01428ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP646" , 0x1180080e01430ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP647" , 0x1180080e01438ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP648" , 0x1180080e01440ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP649" , 0x1180080e01448ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP650" , 0x1180080e01450ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP651" , 0x1180080e01458ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP652" , 0x1180080e01460ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP653" , 0x1180080e01468ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP654" , 0x1180080e01470ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP655" , 0x1180080e01478ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP656" , 0x1180080e01480ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP657" , 0x1180080e01488ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP658" , 0x1180080e01490ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP659" , 0x1180080e01498ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP660" , 0x1180080e014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP661" , 0x1180080e014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP662" , 0x1180080e014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP663" , 0x1180080e014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP664" , 0x1180080e014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP665" , 0x1180080e014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP666" , 0x1180080e014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP667" , 0x1180080e014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP668" , 0x1180080e014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP669" , 0x1180080e014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP670" , 0x1180080e014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP671" , 0x1180080e014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP672" , 0x1180080e01500ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP673" , 0x1180080e01508ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP674" , 0x1180080e01510ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP675" , 0x1180080e01518ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP676" , 0x1180080e01520ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP677" , 0x1180080e01528ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP678" , 0x1180080e01530ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP679" , 0x1180080e01538ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP680" , 0x1180080e01540ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP681" , 0x1180080e01548ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP682" , 0x1180080e01550ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP683" , 0x1180080e01558ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP684" , 0x1180080e01560ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP685" , 0x1180080e01568ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP686" , 0x1180080e01570ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP687" , 0x1180080e01578ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP688" , 0x1180080e01580ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP689" , 0x1180080e01588ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP690" , 0x1180080e01590ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP691" , 0x1180080e01598ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP692" , 0x1180080e015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP693" , 0x1180080e015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP694" , 0x1180080e015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP695" , 0x1180080e015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP696" , 0x1180080e015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP697" , 0x1180080e015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP698" , 0x1180080e015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP699" , 0x1180080e015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP700" , 0x1180080e015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP701" , 0x1180080e015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP702" , 0x1180080e015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP703" , 0x1180080e015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP704" , 0x1180080e01600ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP705" , 0x1180080e01608ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP706" , 0x1180080e01610ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP707" , 0x1180080e01618ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP708" , 0x1180080e01620ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP709" , 0x1180080e01628ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP710" , 0x1180080e01630ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP711" , 0x1180080e01638ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP712" , 0x1180080e01640ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP713" , 0x1180080e01648ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP714" , 0x1180080e01650ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP715" , 0x1180080e01658ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP716" , 0x1180080e01660ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP717" , 0x1180080e01668ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP718" , 0x1180080e01670ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP719" , 0x1180080e01678ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP720" , 0x1180080e01680ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP721" , 0x1180080e01688ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP722" , 0x1180080e01690ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP723" , 0x1180080e01698ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP724" , 0x1180080e016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP725" , 0x1180080e016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP726" , 0x1180080e016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP727" , 0x1180080e016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP728" , 0x1180080e016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP729" , 0x1180080e016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP730" , 0x1180080e016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP731" , 0x1180080e016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP732" , 0x1180080e016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP733" , 0x1180080e016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP734" , 0x1180080e016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP735" , 0x1180080e016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP736" , 0x1180080e01700ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP737" , 0x1180080e01708ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP738" , 0x1180080e01710ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP739" , 0x1180080e01718ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP740" , 0x1180080e01720ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP741" , 0x1180080e01728ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP742" , 0x1180080e01730ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP743" , 0x1180080e01738ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP744" , 0x1180080e01740ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP745" , 0x1180080e01748ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP746" , 0x1180080e01750ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP747" , 0x1180080e01758ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP748" , 0x1180080e01760ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP749" , 0x1180080e01768ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP750" , 0x1180080e01770ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP751" , 0x1180080e01778ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP752" , 0x1180080e01780ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP753" , 0x1180080e01788ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP754" , 0x1180080e01790ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP755" , 0x1180080e01798ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP756" , 0x1180080e017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP757" , 0x1180080e017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP758" , 0x1180080e017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP759" , 0x1180080e017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP760" , 0x1180080e017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP761" , 0x1180080e017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP762" , 0x1180080e017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP763" , 0x1180080e017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP764" , 0x1180080e017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP765" , 0x1180080e017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP766" , 0x1180080e017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP767" , 0x1180080e017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP768" , 0x1180080e01800ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP769" , 0x1180080e01808ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP770" , 0x1180080e01810ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP771" , 0x1180080e01818ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP772" , 0x1180080e01820ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP773" , 0x1180080e01828ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP774" , 0x1180080e01830ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP775" , 0x1180080e01838ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP776" , 0x1180080e01840ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP777" , 0x1180080e01848ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP778" , 0x1180080e01850ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP779" , 0x1180080e01858ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP780" , 0x1180080e01860ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP781" , 0x1180080e01868ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP782" , 0x1180080e01870ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP783" , 0x1180080e01878ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP784" , 0x1180080e01880ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP785" , 0x1180080e01888ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP786" , 0x1180080e01890ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP787" , 0x1180080e01898ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP788" , 0x1180080e018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP789" , 0x1180080e018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP790" , 0x1180080e018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP791" , 0x1180080e018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP792" , 0x1180080e018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP793" , 0x1180080e018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP794" , 0x1180080e018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP795" , 0x1180080e018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP796" , 0x1180080e018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP797" , 0x1180080e018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP798" , 0x1180080e018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP799" , 0x1180080e018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP800" , 0x1180080e01900ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP801" , 0x1180080e01908ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP802" , 0x1180080e01910ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP803" , 0x1180080e01918ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP804" , 0x1180080e01920ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP805" , 0x1180080e01928ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP806" , 0x1180080e01930ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP807" , 0x1180080e01938ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP808" , 0x1180080e01940ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP809" , 0x1180080e01948ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP810" , 0x1180080e01950ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP811" , 0x1180080e01958ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP812" , 0x1180080e01960ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP813" , 0x1180080e01968ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP814" , 0x1180080e01970ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP815" , 0x1180080e01978ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP816" , 0x1180080e01980ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP817" , 0x1180080e01988ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP818" , 0x1180080e01990ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP819" , 0x1180080e01998ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP820" , 0x1180080e019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP821" , 0x1180080e019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP822" , 0x1180080e019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP823" , 0x1180080e019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP824" , 0x1180080e019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP825" , 0x1180080e019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP826" , 0x1180080e019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP827" , 0x1180080e019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP828" , 0x1180080e019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP829" , 0x1180080e019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP830" , 0x1180080e019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP831" , 0x1180080e019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP832" , 0x1180080e01a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP833" , 0x1180080e01a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP834" , 0x1180080e01a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP835" , 0x1180080e01a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP836" , 0x1180080e01a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP837" , 0x1180080e01a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP838" , 0x1180080e01a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP839" , 0x1180080e01a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP840" , 0x1180080e01a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP841" , 0x1180080e01a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP842" , 0x1180080e01a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP843" , 0x1180080e01a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP844" , 0x1180080e01a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP845" , 0x1180080e01a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP846" , 0x1180080e01a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP847" , 0x1180080e01a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP848" , 0x1180080e01a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP849" , 0x1180080e01a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP850" , 0x1180080e01a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP851" , 0x1180080e01a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP852" , 0x1180080e01aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP853" , 0x1180080e01aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP854" , 0x1180080e01ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP855" , 0x1180080e01ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP856" , 0x1180080e01ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP857" , 0x1180080e01ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP858" , 0x1180080e01ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP859" , 0x1180080e01ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP860" , 0x1180080e01ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP861" , 0x1180080e01ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP862" , 0x1180080e01af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP863" , 0x1180080e01af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP864" , 0x1180080e01b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP865" , 0x1180080e01b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP866" , 0x1180080e01b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP867" , 0x1180080e01b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP868" , 0x1180080e01b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP869" , 0x1180080e01b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP870" , 0x1180080e01b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP871" , 0x1180080e01b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP872" , 0x1180080e01b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP873" , 0x1180080e01b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP874" , 0x1180080e01b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP875" , 0x1180080e01b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP876" , 0x1180080e01b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP877" , 0x1180080e01b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP878" , 0x1180080e01b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP879" , 0x1180080e01b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP880" , 0x1180080e01b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP881" , 0x1180080e01b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP882" , 0x1180080e01b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP883" , 0x1180080e01b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP884" , 0x1180080e01ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP885" , 0x1180080e01ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP886" , 0x1180080e01bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP887" , 0x1180080e01bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP888" , 0x1180080e01bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP889" , 0x1180080e01bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP890" , 0x1180080e01bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP891" , 0x1180080e01bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP892" , 0x1180080e01be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP893" , 0x1180080e01be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP894" , 0x1180080e01bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP895" , 0x1180080e01bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP896" , 0x1180080e01c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP897" , 0x1180080e01c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP898" , 0x1180080e01c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP899" , 0x1180080e01c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP900" , 0x1180080e01c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP901" , 0x1180080e01c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP902" , 0x1180080e01c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP903" , 0x1180080e01c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP904" , 0x1180080e01c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP905" , 0x1180080e01c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP906" , 0x1180080e01c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP907" , 0x1180080e01c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP908" , 0x1180080e01c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP909" , 0x1180080e01c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP910" , 0x1180080e01c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP911" , 0x1180080e01c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP912" , 0x1180080e01c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP913" , 0x1180080e01c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP914" , 0x1180080e01c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP915" , 0x1180080e01c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP916" , 0x1180080e01ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP917" , 0x1180080e01ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP918" , 0x1180080e01cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP919" , 0x1180080e01cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP920" , 0x1180080e01cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP921" , 0x1180080e01cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP922" , 0x1180080e01cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP923" , 0x1180080e01cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP924" , 0x1180080e01ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP925" , 0x1180080e01ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP926" , 0x1180080e01cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP927" , 0x1180080e01cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP928" , 0x1180080e01d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP929" , 0x1180080e01d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP930" , 0x1180080e01d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP931" , 0x1180080e01d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP932" , 0x1180080e01d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP933" , 0x1180080e01d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP934" , 0x1180080e01d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP935" , 0x1180080e01d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP936" , 0x1180080e01d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP937" , 0x1180080e01d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP938" , 0x1180080e01d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP939" , 0x1180080e01d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP940" , 0x1180080e01d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP941" , 0x1180080e01d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP942" , 0x1180080e01d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP943" , 0x1180080e01d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP944" , 0x1180080e01d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP945" , 0x1180080e01d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP946" , 0x1180080e01d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP947" , 0x1180080e01d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP948" , 0x1180080e01da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP949" , 0x1180080e01da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP950" , 0x1180080e01db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP951" , 0x1180080e01db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP952" , 0x1180080e01dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP953" , 0x1180080e01dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP954" , 0x1180080e01dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP955" , 0x1180080e01dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP956" , 0x1180080e01de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP957" , 0x1180080e01de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP958" , 0x1180080e01df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP959" , 0x1180080e01df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP960" , 0x1180080e01e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP961" , 0x1180080e01e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP962" , 0x1180080e01e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP963" , 0x1180080e01e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP964" , 0x1180080e01e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP965" , 0x1180080e01e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP966" , 0x1180080e01e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP967" , 0x1180080e01e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP968" , 0x1180080e01e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP969" , 0x1180080e01e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP970" , 0x1180080e01e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP971" , 0x1180080e01e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP972" , 0x1180080e01e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP973" , 0x1180080e01e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP974" , 0x1180080e01e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP975" , 0x1180080e01e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP976" , 0x1180080e01e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP977" , 0x1180080e01e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP978" , 0x1180080e01e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP979" , 0x1180080e01e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP980" , 0x1180080e01ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP981" , 0x1180080e01ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP982" , 0x1180080e01eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP983" , 0x1180080e01eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP984" , 0x1180080e01ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP985" , 0x1180080e01ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP986" , 0x1180080e01ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP987" , 0x1180080e01ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP988" , 0x1180080e01ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP989" , 0x1180080e01ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP990" , 0x1180080e01ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP991" , 0x1180080e01ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP992" , 0x1180080e01f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP993" , 0x1180080e01f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP994" , 0x1180080e01f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP995" , 0x1180080e01f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP996" , 0x1180080e01f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP997" , 0x1180080e01f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP998" , 0x1180080e01f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP999" , 0x1180080e01f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1000" , 0x1180080e01f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1001" , 0x1180080e01f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1002" , 0x1180080e01f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1003" , 0x1180080e01f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1004" , 0x1180080e01f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1005" , 0x1180080e01f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1006" , 0x1180080e01f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1007" , 0x1180080e01f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1008" , 0x1180080e01f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1009" , 0x1180080e01f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1010" , 0x1180080e01f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1011" , 0x1180080e01f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1012" , 0x1180080e01fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1013" , 0x1180080e01fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1014" , 0x1180080e01fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1015" , 0x1180080e01fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1016" , 0x1180080e01fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1017" , 0x1180080e01fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1018" , 0x1180080e01fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1019" , 0x1180080e01fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1020" , 0x1180080e01fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1021" , 0x1180080e01fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1022" , 0x1180080e01ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1023" , 0x1180080e01ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1024" , 0x1180080e02000ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1025" , 0x1180080e02008ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1026" , 0x1180080e02010ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1027" , 0x1180080e02018ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1028" , 0x1180080e02020ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1029" , 0x1180080e02028ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1030" , 0x1180080e02030ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1031" , 0x1180080e02038ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1032" , 0x1180080e02040ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1033" , 0x1180080e02048ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1034" , 0x1180080e02050ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1035" , 0x1180080e02058ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1036" , 0x1180080e02060ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1037" , 0x1180080e02068ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1038" , 0x1180080e02070ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1039" , 0x1180080e02078ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1040" , 0x1180080e02080ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1041" , 0x1180080e02088ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1042" , 0x1180080e02090ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1043" , 0x1180080e02098ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1044" , 0x1180080e020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1045" , 0x1180080e020a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1046" , 0x1180080e020b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1047" , 0x1180080e020b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1048" , 0x1180080e020c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1049" , 0x1180080e020c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1050" , 0x1180080e020d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1051" , 0x1180080e020d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1052" , 0x1180080e020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1053" , 0x1180080e020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1054" , 0x1180080e020f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1055" , 0x1180080e020f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1056" , 0x1180080e02100ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1057" , 0x1180080e02108ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1058" , 0x1180080e02110ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1059" , 0x1180080e02118ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1060" , 0x1180080e02120ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1061" , 0x1180080e02128ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1062" , 0x1180080e02130ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1063" , 0x1180080e02138ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1064" , 0x1180080e02140ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1065" , 0x1180080e02148ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1066" , 0x1180080e02150ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1067" , 0x1180080e02158ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1068" , 0x1180080e02160ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1069" , 0x1180080e02168ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1070" , 0x1180080e02170ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1071" , 0x1180080e02178ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1072" , 0x1180080e02180ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1073" , 0x1180080e02188ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1074" , 0x1180080e02190ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1075" , 0x1180080e02198ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1076" , 0x1180080e021a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1077" , 0x1180080e021a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1078" , 0x1180080e021b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1079" , 0x1180080e021b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1080" , 0x1180080e021c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1081" , 0x1180080e021c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1082" , 0x1180080e021d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1083" , 0x1180080e021d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1084" , 0x1180080e021e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1085" , 0x1180080e021e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1086" , 0x1180080e021f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1087" , 0x1180080e021f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1088" , 0x1180080e02200ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1089" , 0x1180080e02208ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1090" , 0x1180080e02210ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1091" , 0x1180080e02218ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1092" , 0x1180080e02220ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1093" , 0x1180080e02228ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1094" , 0x1180080e02230ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1095" , 0x1180080e02238ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1096" , 0x1180080e02240ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1097" , 0x1180080e02248ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1098" , 0x1180080e02250ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1099" , 0x1180080e02258ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1100" , 0x1180080e02260ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1101" , 0x1180080e02268ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1102" , 0x1180080e02270ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1103" , 0x1180080e02278ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1104" , 0x1180080e02280ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1105" , 0x1180080e02288ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1106" , 0x1180080e02290ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1107" , 0x1180080e02298ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1108" , 0x1180080e022a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1109" , 0x1180080e022a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1110" , 0x1180080e022b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1111" , 0x1180080e022b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1112" , 0x1180080e022c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1113" , 0x1180080e022c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1114" , 0x1180080e022d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1115" , 0x1180080e022d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1116" , 0x1180080e022e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1117" , 0x1180080e022e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1118" , 0x1180080e022f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1119" , 0x1180080e022f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1120" , 0x1180080e02300ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1121" , 0x1180080e02308ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1122" , 0x1180080e02310ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1123" , 0x1180080e02318ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1124" , 0x1180080e02320ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1125" , 0x1180080e02328ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1126" , 0x1180080e02330ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1127" , 0x1180080e02338ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1128" , 0x1180080e02340ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1129" , 0x1180080e02348ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1130" , 0x1180080e02350ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1131" , 0x1180080e02358ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1132" , 0x1180080e02360ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1133" , 0x1180080e02368ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1134" , 0x1180080e02370ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1135" , 0x1180080e02378ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1136" , 0x1180080e02380ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1137" , 0x1180080e02388ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1138" , 0x1180080e02390ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1139" , 0x1180080e02398ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1140" , 0x1180080e023a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1141" , 0x1180080e023a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1142" , 0x1180080e023b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1143" , 0x1180080e023b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1144" , 0x1180080e023c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1145" , 0x1180080e023c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1146" , 0x1180080e023d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1147" , 0x1180080e023d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1148" , 0x1180080e023e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1149" , 0x1180080e023e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1150" , 0x1180080e023f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1151" , 0x1180080e023f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1152" , 0x1180080e02400ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1153" , 0x1180080e02408ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1154" , 0x1180080e02410ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1155" , 0x1180080e02418ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1156" , 0x1180080e02420ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1157" , 0x1180080e02428ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1158" , 0x1180080e02430ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1159" , 0x1180080e02438ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1160" , 0x1180080e02440ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1161" , 0x1180080e02448ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1162" , 0x1180080e02450ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1163" , 0x1180080e02458ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1164" , 0x1180080e02460ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1165" , 0x1180080e02468ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1166" , 0x1180080e02470ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1167" , 0x1180080e02478ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1168" , 0x1180080e02480ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1169" , 0x1180080e02488ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1170" , 0x1180080e02490ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1171" , 0x1180080e02498ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1172" , 0x1180080e024a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1173" , 0x1180080e024a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1174" , 0x1180080e024b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1175" , 0x1180080e024b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1176" , 0x1180080e024c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1177" , 0x1180080e024c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1178" , 0x1180080e024d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1179" , 0x1180080e024d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1180" , 0x1180080e024e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1181" , 0x1180080e024e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1182" , 0x1180080e024f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1183" , 0x1180080e024f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1184" , 0x1180080e02500ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1185" , 0x1180080e02508ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1186" , 0x1180080e02510ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1187" , 0x1180080e02518ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1188" , 0x1180080e02520ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1189" , 0x1180080e02528ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1190" , 0x1180080e02530ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1191" , 0x1180080e02538ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1192" , 0x1180080e02540ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1193" , 0x1180080e02548ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1194" , 0x1180080e02550ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1195" , 0x1180080e02558ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1196" , 0x1180080e02560ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1197" , 0x1180080e02568ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1198" , 0x1180080e02570ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1199" , 0x1180080e02578ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1200" , 0x1180080e02580ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1201" , 0x1180080e02588ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1202" , 0x1180080e02590ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1203" , 0x1180080e02598ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1204" , 0x1180080e025a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1205" , 0x1180080e025a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1206" , 0x1180080e025b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1207" , 0x1180080e025b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1208" , 0x1180080e025c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1209" , 0x1180080e025c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1210" , 0x1180080e025d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1211" , 0x1180080e025d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1212" , 0x1180080e025e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1213" , 0x1180080e025e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1214" , 0x1180080e025f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1215" , 0x1180080e025f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1216" , 0x1180080e02600ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1217" , 0x1180080e02608ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1218" , 0x1180080e02610ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1219" , 0x1180080e02618ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1220" , 0x1180080e02620ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1221" , 0x1180080e02628ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1222" , 0x1180080e02630ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1223" , 0x1180080e02638ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1224" , 0x1180080e02640ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1225" , 0x1180080e02648ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1226" , 0x1180080e02650ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1227" , 0x1180080e02658ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1228" , 0x1180080e02660ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1229" , 0x1180080e02668ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1230" , 0x1180080e02670ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1231" , 0x1180080e02678ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1232" , 0x1180080e02680ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1233" , 0x1180080e02688ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1234" , 0x1180080e02690ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1235" , 0x1180080e02698ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1236" , 0x1180080e026a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1237" , 0x1180080e026a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1238" , 0x1180080e026b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1239" , 0x1180080e026b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1240" , 0x1180080e026c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1241" , 0x1180080e026c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1242" , 0x1180080e026d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1243" , 0x1180080e026d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1244" , 0x1180080e026e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1245" , 0x1180080e026e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1246" , 0x1180080e026f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1247" , 0x1180080e026f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1248" , 0x1180080e02700ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1249" , 0x1180080e02708ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1250" , 0x1180080e02710ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1251" , 0x1180080e02718ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1252" , 0x1180080e02720ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1253" , 0x1180080e02728ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1254" , 0x1180080e02730ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1255" , 0x1180080e02738ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1256" , 0x1180080e02740ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1257" , 0x1180080e02748ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1258" , 0x1180080e02750ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1259" , 0x1180080e02758ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1260" , 0x1180080e02760ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1261" , 0x1180080e02768ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1262" , 0x1180080e02770ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1263" , 0x1180080e02778ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1264" , 0x1180080e02780ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1265" , 0x1180080e02788ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1266" , 0x1180080e02790ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1267" , 0x1180080e02798ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1268" , 0x1180080e027a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1269" , 0x1180080e027a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1270" , 0x1180080e027b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1271" , 0x1180080e027b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1272" , 0x1180080e027c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1273" , 0x1180080e027c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1274" , 0x1180080e027d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1275" , 0x1180080e027d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1276" , 0x1180080e027e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1277" , 0x1180080e027e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1278" , 0x1180080e027f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1279" , 0x1180080e027f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1280" , 0x1180080e02800ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1281" , 0x1180080e02808ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1282" , 0x1180080e02810ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1283" , 0x1180080e02818ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1284" , 0x1180080e02820ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1285" , 0x1180080e02828ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1286" , 0x1180080e02830ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1287" , 0x1180080e02838ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1288" , 0x1180080e02840ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1289" , 0x1180080e02848ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1290" , 0x1180080e02850ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1291" , 0x1180080e02858ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1292" , 0x1180080e02860ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1293" , 0x1180080e02868ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1294" , 0x1180080e02870ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1295" , 0x1180080e02878ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1296" , 0x1180080e02880ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1297" , 0x1180080e02888ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1298" , 0x1180080e02890ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1299" , 0x1180080e02898ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1300" , 0x1180080e028a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1301" , 0x1180080e028a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1302" , 0x1180080e028b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1303" , 0x1180080e028b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1304" , 0x1180080e028c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1305" , 0x1180080e028c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1306" , 0x1180080e028d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1307" , 0x1180080e028d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1308" , 0x1180080e028e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1309" , 0x1180080e028e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1310" , 0x1180080e028f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1311" , 0x1180080e028f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1312" , 0x1180080e02900ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1313" , 0x1180080e02908ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1314" , 0x1180080e02910ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1315" , 0x1180080e02918ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1316" , 0x1180080e02920ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1317" , 0x1180080e02928ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1318" , 0x1180080e02930ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1319" , 0x1180080e02938ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1320" , 0x1180080e02940ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1321" , 0x1180080e02948ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1322" , 0x1180080e02950ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1323" , 0x1180080e02958ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1324" , 0x1180080e02960ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1325" , 0x1180080e02968ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1326" , 0x1180080e02970ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1327" , 0x1180080e02978ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1328" , 0x1180080e02980ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1329" , 0x1180080e02988ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1330" , 0x1180080e02990ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1331" , 0x1180080e02998ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1332" , 0x1180080e029a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1333" , 0x1180080e029a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1334" , 0x1180080e029b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1335" , 0x1180080e029b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1336" , 0x1180080e029c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1337" , 0x1180080e029c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1338" , 0x1180080e029d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1339" , 0x1180080e029d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1340" , 0x1180080e029e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1341" , 0x1180080e029e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1342" , 0x1180080e029f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1343" , 0x1180080e029f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1344" , 0x1180080e02a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1345" , 0x1180080e02a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1346" , 0x1180080e02a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1347" , 0x1180080e02a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1348" , 0x1180080e02a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1349" , 0x1180080e02a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1350" , 0x1180080e02a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1351" , 0x1180080e02a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1352" , 0x1180080e02a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1353" , 0x1180080e02a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1354" , 0x1180080e02a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1355" , 0x1180080e02a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1356" , 0x1180080e02a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1357" , 0x1180080e02a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1358" , 0x1180080e02a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1359" , 0x1180080e02a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1360" , 0x1180080e02a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1361" , 0x1180080e02a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1362" , 0x1180080e02a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1363" , 0x1180080e02a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1364" , 0x1180080e02aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1365" , 0x1180080e02aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1366" , 0x1180080e02ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1367" , 0x1180080e02ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1368" , 0x1180080e02ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1369" , 0x1180080e02ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1370" , 0x1180080e02ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1371" , 0x1180080e02ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1372" , 0x1180080e02ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1373" , 0x1180080e02ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1374" , 0x1180080e02af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1375" , 0x1180080e02af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1376" , 0x1180080e02b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1377" , 0x1180080e02b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1378" , 0x1180080e02b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1379" , 0x1180080e02b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1380" , 0x1180080e02b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1381" , 0x1180080e02b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1382" , 0x1180080e02b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1383" , 0x1180080e02b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1384" , 0x1180080e02b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1385" , 0x1180080e02b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1386" , 0x1180080e02b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1387" , 0x1180080e02b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1388" , 0x1180080e02b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1389" , 0x1180080e02b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1390" , 0x1180080e02b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1391" , 0x1180080e02b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1392" , 0x1180080e02b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1393" , 0x1180080e02b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1394" , 0x1180080e02b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1395" , 0x1180080e02b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1396" , 0x1180080e02ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1397" , 0x1180080e02ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1398" , 0x1180080e02bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1399" , 0x1180080e02bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1400" , 0x1180080e02bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1401" , 0x1180080e02bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1402" , 0x1180080e02bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1403" , 0x1180080e02bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1404" , 0x1180080e02be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1405" , 0x1180080e02be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1406" , 0x1180080e02bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1407" , 0x1180080e02bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1408" , 0x1180080e02c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1409" , 0x1180080e02c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1410" , 0x1180080e02c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1411" , 0x1180080e02c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1412" , 0x1180080e02c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1413" , 0x1180080e02c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1414" , 0x1180080e02c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1415" , 0x1180080e02c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1416" , 0x1180080e02c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1417" , 0x1180080e02c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1418" , 0x1180080e02c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1419" , 0x1180080e02c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1420" , 0x1180080e02c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1421" , 0x1180080e02c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1422" , 0x1180080e02c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1423" , 0x1180080e02c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1424" , 0x1180080e02c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1425" , 0x1180080e02c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1426" , 0x1180080e02c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1427" , 0x1180080e02c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1428" , 0x1180080e02ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1429" , 0x1180080e02ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1430" , 0x1180080e02cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1431" , 0x1180080e02cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1432" , 0x1180080e02cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1433" , 0x1180080e02cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1434" , 0x1180080e02cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1435" , 0x1180080e02cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1436" , 0x1180080e02ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1437" , 0x1180080e02ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1438" , 0x1180080e02cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1439" , 0x1180080e02cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1440" , 0x1180080e02d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1441" , 0x1180080e02d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1442" , 0x1180080e02d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1443" , 0x1180080e02d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1444" , 0x1180080e02d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1445" , 0x1180080e02d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1446" , 0x1180080e02d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1447" , 0x1180080e02d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1448" , 0x1180080e02d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1449" , 0x1180080e02d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1450" , 0x1180080e02d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1451" , 0x1180080e02d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1452" , 0x1180080e02d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1453" , 0x1180080e02d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1454" , 0x1180080e02d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1455" , 0x1180080e02d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1456" , 0x1180080e02d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1457" , 0x1180080e02d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1458" , 0x1180080e02d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1459" , 0x1180080e02d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1460" , 0x1180080e02da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1461" , 0x1180080e02da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1462" , 0x1180080e02db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1463" , 0x1180080e02db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1464" , 0x1180080e02dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1465" , 0x1180080e02dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1466" , 0x1180080e02dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1467" , 0x1180080e02dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1468" , 0x1180080e02de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1469" , 0x1180080e02de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1470" , 0x1180080e02df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1471" , 0x1180080e02df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1472" , 0x1180080e02e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1473" , 0x1180080e02e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1474" , 0x1180080e02e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1475" , 0x1180080e02e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1476" , 0x1180080e02e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1477" , 0x1180080e02e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1478" , 0x1180080e02e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1479" , 0x1180080e02e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1480" , 0x1180080e02e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1481" , 0x1180080e02e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1482" , 0x1180080e02e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1483" , 0x1180080e02e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1484" , 0x1180080e02e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1485" , 0x1180080e02e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1486" , 0x1180080e02e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1487" , 0x1180080e02e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1488" , 0x1180080e02e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1489" , 0x1180080e02e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1490" , 0x1180080e02e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1491" , 0x1180080e02e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1492" , 0x1180080e02ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1493" , 0x1180080e02ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1494" , 0x1180080e02eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1495" , 0x1180080e02eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1496" , 0x1180080e02ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1497" , 0x1180080e02ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1498" , 0x1180080e02ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1499" , 0x1180080e02ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1500" , 0x1180080e02ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1501" , 0x1180080e02ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1502" , 0x1180080e02ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1503" , 0x1180080e02ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1504" , 0x1180080e02f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1505" , 0x1180080e02f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1506" , 0x1180080e02f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1507" , 0x1180080e02f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1508" , 0x1180080e02f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1509" , 0x1180080e02f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1510" , 0x1180080e02f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1511" , 0x1180080e02f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1512" , 0x1180080e02f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1513" , 0x1180080e02f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1514" , 0x1180080e02f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1515" , 0x1180080e02f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1516" , 0x1180080e02f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1517" , 0x1180080e02f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1518" , 0x1180080e02f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1519" , 0x1180080e02f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1520" , 0x1180080e02f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1521" , 0x1180080e02f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1522" , 0x1180080e02f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1523" , 0x1180080e02f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1524" , 0x1180080e02fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1525" , 0x1180080e02fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1526" , 0x1180080e02fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1527" , 0x1180080e02fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1528" , 0x1180080e02fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1529" , 0x1180080e02fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1530" , 0x1180080e02fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1531" , 0x1180080e02fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1532" , 0x1180080e02fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1533" , 0x1180080e02fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1534" , 0x1180080e02ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1535" , 0x1180080e02ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1536" , 0x1180080e03000ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1537" , 0x1180080e03008ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1538" , 0x1180080e03010ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1539" , 0x1180080e03018ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1540" , 0x1180080e03020ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1541" , 0x1180080e03028ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1542" , 0x1180080e03030ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1543" , 0x1180080e03038ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1544" , 0x1180080e03040ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1545" , 0x1180080e03048ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1546" , 0x1180080e03050ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1547" , 0x1180080e03058ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1548" , 0x1180080e03060ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1549" , 0x1180080e03068ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1550" , 0x1180080e03070ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1551" , 0x1180080e03078ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1552" , 0x1180080e03080ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1553" , 0x1180080e03088ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1554" , 0x1180080e03090ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1555" , 0x1180080e03098ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1556" , 0x1180080e030a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1557" , 0x1180080e030a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1558" , 0x1180080e030b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1559" , 0x1180080e030b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1560" , 0x1180080e030c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1561" , 0x1180080e030c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1562" , 0x1180080e030d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1563" , 0x1180080e030d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1564" , 0x1180080e030e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1565" , 0x1180080e030e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1566" , 0x1180080e030f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1567" , 0x1180080e030f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1568" , 0x1180080e03100ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1569" , 0x1180080e03108ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1570" , 0x1180080e03110ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1571" , 0x1180080e03118ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1572" , 0x1180080e03120ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1573" , 0x1180080e03128ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1574" , 0x1180080e03130ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1575" , 0x1180080e03138ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1576" , 0x1180080e03140ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1577" , 0x1180080e03148ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1578" , 0x1180080e03150ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1579" , 0x1180080e03158ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1580" , 0x1180080e03160ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1581" , 0x1180080e03168ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1582" , 0x1180080e03170ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1583" , 0x1180080e03178ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1584" , 0x1180080e03180ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1585" , 0x1180080e03188ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1586" , 0x1180080e03190ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1587" , 0x1180080e03198ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1588" , 0x1180080e031a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1589" , 0x1180080e031a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1590" , 0x1180080e031b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1591" , 0x1180080e031b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1592" , 0x1180080e031c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1593" , 0x1180080e031c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1594" , 0x1180080e031d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1595" , 0x1180080e031d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1596" , 0x1180080e031e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1597" , 0x1180080e031e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1598" , 0x1180080e031f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1599" , 0x1180080e031f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1600" , 0x1180080e03200ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1601" , 0x1180080e03208ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1602" , 0x1180080e03210ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1603" , 0x1180080e03218ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1604" , 0x1180080e03220ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1605" , 0x1180080e03228ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1606" , 0x1180080e03230ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1607" , 0x1180080e03238ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1608" , 0x1180080e03240ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1609" , 0x1180080e03248ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1610" , 0x1180080e03250ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1611" , 0x1180080e03258ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1612" , 0x1180080e03260ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1613" , 0x1180080e03268ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1614" , 0x1180080e03270ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1615" , 0x1180080e03278ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1616" , 0x1180080e03280ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1617" , 0x1180080e03288ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1618" , 0x1180080e03290ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1619" , 0x1180080e03298ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1620" , 0x1180080e032a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1621" , 0x1180080e032a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1622" , 0x1180080e032b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1623" , 0x1180080e032b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1624" , 0x1180080e032c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1625" , 0x1180080e032c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1626" , 0x1180080e032d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1627" , 0x1180080e032d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1628" , 0x1180080e032e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1629" , 0x1180080e032e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1630" , 0x1180080e032f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1631" , 0x1180080e032f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1632" , 0x1180080e03300ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1633" , 0x1180080e03308ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1634" , 0x1180080e03310ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1635" , 0x1180080e03318ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1636" , 0x1180080e03320ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1637" , 0x1180080e03328ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1638" , 0x1180080e03330ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1639" , 0x1180080e03338ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1640" , 0x1180080e03340ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1641" , 0x1180080e03348ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1642" , 0x1180080e03350ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1643" , 0x1180080e03358ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1644" , 0x1180080e03360ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1645" , 0x1180080e03368ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1646" , 0x1180080e03370ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1647" , 0x1180080e03378ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1648" , 0x1180080e03380ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1649" , 0x1180080e03388ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1650" , 0x1180080e03390ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1651" , 0x1180080e03398ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1652" , 0x1180080e033a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1653" , 0x1180080e033a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1654" , 0x1180080e033b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1655" , 0x1180080e033b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1656" , 0x1180080e033c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1657" , 0x1180080e033c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1658" , 0x1180080e033d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1659" , 0x1180080e033d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1660" , 0x1180080e033e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1661" , 0x1180080e033e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1662" , 0x1180080e033f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1663" , 0x1180080e033f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1664" , 0x1180080e03400ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1665" , 0x1180080e03408ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1666" , 0x1180080e03410ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1667" , 0x1180080e03418ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1668" , 0x1180080e03420ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1669" , 0x1180080e03428ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1670" , 0x1180080e03430ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1671" , 0x1180080e03438ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1672" , 0x1180080e03440ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1673" , 0x1180080e03448ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1674" , 0x1180080e03450ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1675" , 0x1180080e03458ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1676" , 0x1180080e03460ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1677" , 0x1180080e03468ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1678" , 0x1180080e03470ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1679" , 0x1180080e03478ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1680" , 0x1180080e03480ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1681" , 0x1180080e03488ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1682" , 0x1180080e03490ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1683" , 0x1180080e03498ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1684" , 0x1180080e034a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1685" , 0x1180080e034a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1686" , 0x1180080e034b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1687" , 0x1180080e034b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1688" , 0x1180080e034c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1689" , 0x1180080e034c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1690" , 0x1180080e034d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1691" , 0x1180080e034d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1692" , 0x1180080e034e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1693" , 0x1180080e034e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1694" , 0x1180080e034f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1695" , 0x1180080e034f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1696" , 0x1180080e03500ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1697" , 0x1180080e03508ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1698" , 0x1180080e03510ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1699" , 0x1180080e03518ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1700" , 0x1180080e03520ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1701" , 0x1180080e03528ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1702" , 0x1180080e03530ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1703" , 0x1180080e03538ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1704" , 0x1180080e03540ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1705" , 0x1180080e03548ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1706" , 0x1180080e03550ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1707" , 0x1180080e03558ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1708" , 0x1180080e03560ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1709" , 0x1180080e03568ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1710" , 0x1180080e03570ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1711" , 0x1180080e03578ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1712" , 0x1180080e03580ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1713" , 0x1180080e03588ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1714" , 0x1180080e03590ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1715" , 0x1180080e03598ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1716" , 0x1180080e035a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1717" , 0x1180080e035a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1718" , 0x1180080e035b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1719" , 0x1180080e035b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1720" , 0x1180080e035c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1721" , 0x1180080e035c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1722" , 0x1180080e035d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1723" , 0x1180080e035d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1724" , 0x1180080e035e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1725" , 0x1180080e035e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1726" , 0x1180080e035f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1727" , 0x1180080e035f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1728" , 0x1180080e03600ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1729" , 0x1180080e03608ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1730" , 0x1180080e03610ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1731" , 0x1180080e03618ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1732" , 0x1180080e03620ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1733" , 0x1180080e03628ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1734" , 0x1180080e03630ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1735" , 0x1180080e03638ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1736" , 0x1180080e03640ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1737" , 0x1180080e03648ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1738" , 0x1180080e03650ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1739" , 0x1180080e03658ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1740" , 0x1180080e03660ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1741" , 0x1180080e03668ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1742" , 0x1180080e03670ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1743" , 0x1180080e03678ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1744" , 0x1180080e03680ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1745" , 0x1180080e03688ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1746" , 0x1180080e03690ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1747" , 0x1180080e03698ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1748" , 0x1180080e036a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1749" , 0x1180080e036a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1750" , 0x1180080e036b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1751" , 0x1180080e036b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1752" , 0x1180080e036c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1753" , 0x1180080e036c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1754" , 0x1180080e036d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1755" , 0x1180080e036d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1756" , 0x1180080e036e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1757" , 0x1180080e036e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1758" , 0x1180080e036f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1759" , 0x1180080e036f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1760" , 0x1180080e03700ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1761" , 0x1180080e03708ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1762" , 0x1180080e03710ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1763" , 0x1180080e03718ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1764" , 0x1180080e03720ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1765" , 0x1180080e03728ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1766" , 0x1180080e03730ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1767" , 0x1180080e03738ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1768" , 0x1180080e03740ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1769" , 0x1180080e03748ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1770" , 0x1180080e03750ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1771" , 0x1180080e03758ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1772" , 0x1180080e03760ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1773" , 0x1180080e03768ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1774" , 0x1180080e03770ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1775" , 0x1180080e03778ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1776" , 0x1180080e03780ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1777" , 0x1180080e03788ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1778" , 0x1180080e03790ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1779" , 0x1180080e03798ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1780" , 0x1180080e037a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1781" , 0x1180080e037a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1782" , 0x1180080e037b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1783" , 0x1180080e037b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1784" , 0x1180080e037c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1785" , 0x1180080e037c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1786" , 0x1180080e037d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1787" , 0x1180080e037d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1788" , 0x1180080e037e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1789" , 0x1180080e037e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1790" , 0x1180080e037f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1791" , 0x1180080e037f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1792" , 0x1180080e03800ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1793" , 0x1180080e03808ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1794" , 0x1180080e03810ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1795" , 0x1180080e03818ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1796" , 0x1180080e03820ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1797" , 0x1180080e03828ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1798" , 0x1180080e03830ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1799" , 0x1180080e03838ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1800" , 0x1180080e03840ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1801" , 0x1180080e03848ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1802" , 0x1180080e03850ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1803" , 0x1180080e03858ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1804" , 0x1180080e03860ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1805" , 0x1180080e03868ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1806" , 0x1180080e03870ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1807" , 0x1180080e03878ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1808" , 0x1180080e03880ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1809" , 0x1180080e03888ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1810" , 0x1180080e03890ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1811" , 0x1180080e03898ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1812" , 0x1180080e038a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1813" , 0x1180080e038a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1814" , 0x1180080e038b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1815" , 0x1180080e038b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1816" , 0x1180080e038c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1817" , 0x1180080e038c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1818" , 0x1180080e038d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1819" , 0x1180080e038d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1820" , 0x1180080e038e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1821" , 0x1180080e038e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1822" , 0x1180080e038f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1823" , 0x1180080e038f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1824" , 0x1180080e03900ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1825" , 0x1180080e03908ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1826" , 0x1180080e03910ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1827" , 0x1180080e03918ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1828" , 0x1180080e03920ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1829" , 0x1180080e03928ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1830" , 0x1180080e03930ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1831" , 0x1180080e03938ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1832" , 0x1180080e03940ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1833" , 0x1180080e03948ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1834" , 0x1180080e03950ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1835" , 0x1180080e03958ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1836" , 0x1180080e03960ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1837" , 0x1180080e03968ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1838" , 0x1180080e03970ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1839" , 0x1180080e03978ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1840" , 0x1180080e03980ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1841" , 0x1180080e03988ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1842" , 0x1180080e03990ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1843" , 0x1180080e03998ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1844" , 0x1180080e039a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1845" , 0x1180080e039a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1846" , 0x1180080e039b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1847" , 0x1180080e039b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1848" , 0x1180080e039c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1849" , 0x1180080e039c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1850" , 0x1180080e039d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1851" , 0x1180080e039d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1852" , 0x1180080e039e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1853" , 0x1180080e039e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1854" , 0x1180080e039f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1855" , 0x1180080e039f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1856" , 0x1180080e03a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1857" , 0x1180080e03a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1858" , 0x1180080e03a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1859" , 0x1180080e03a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1860" , 0x1180080e03a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1861" , 0x1180080e03a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1862" , 0x1180080e03a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1863" , 0x1180080e03a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1864" , 0x1180080e03a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1865" , 0x1180080e03a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1866" , 0x1180080e03a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1867" , 0x1180080e03a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1868" , 0x1180080e03a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1869" , 0x1180080e03a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1870" , 0x1180080e03a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1871" , 0x1180080e03a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1872" , 0x1180080e03a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1873" , 0x1180080e03a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1874" , 0x1180080e03a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1875" , 0x1180080e03a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1876" , 0x1180080e03aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1877" , 0x1180080e03aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1878" , 0x1180080e03ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1879" , 0x1180080e03ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1880" , 0x1180080e03ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1881" , 0x1180080e03ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1882" , 0x1180080e03ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1883" , 0x1180080e03ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1884" , 0x1180080e03ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1885" , 0x1180080e03ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1886" , 0x1180080e03af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1887" , 0x1180080e03af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1888" , 0x1180080e03b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1889" , 0x1180080e03b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1890" , 0x1180080e03b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1891" , 0x1180080e03b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1892" , 0x1180080e03b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1893" , 0x1180080e03b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1894" , 0x1180080e03b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1895" , 0x1180080e03b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1896" , 0x1180080e03b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1897" , 0x1180080e03b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1898" , 0x1180080e03b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1899" , 0x1180080e03b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1900" , 0x1180080e03b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1901" , 0x1180080e03b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1902" , 0x1180080e03b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1903" , 0x1180080e03b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1904" , 0x1180080e03b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1905" , 0x1180080e03b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1906" , 0x1180080e03b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1907" , 0x1180080e03b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1908" , 0x1180080e03ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1909" , 0x1180080e03ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1910" , 0x1180080e03bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1911" , 0x1180080e03bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1912" , 0x1180080e03bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1913" , 0x1180080e03bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1914" , 0x1180080e03bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1915" , 0x1180080e03bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1916" , 0x1180080e03be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1917" , 0x1180080e03be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1918" , 0x1180080e03bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1919" , 0x1180080e03bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1920" , 0x1180080e03c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1921" , 0x1180080e03c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1922" , 0x1180080e03c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1923" , 0x1180080e03c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1924" , 0x1180080e03c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1925" , 0x1180080e03c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1926" , 0x1180080e03c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1927" , 0x1180080e03c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1928" , 0x1180080e03c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1929" , 0x1180080e03c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1930" , 0x1180080e03c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1931" , 0x1180080e03c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1932" , 0x1180080e03c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1933" , 0x1180080e03c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1934" , 0x1180080e03c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1935" , 0x1180080e03c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1936" , 0x1180080e03c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1937" , 0x1180080e03c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1938" , 0x1180080e03c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1939" , 0x1180080e03c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1940" , 0x1180080e03ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1941" , 0x1180080e03ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1942" , 0x1180080e03cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1943" , 0x1180080e03cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1944" , 0x1180080e03cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1945" , 0x1180080e03cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1946" , 0x1180080e03cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1947" , 0x1180080e03cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1948" , 0x1180080e03ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1949" , 0x1180080e03ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1950" , 0x1180080e03cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1951" , 0x1180080e03cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1952" , 0x1180080e03d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1953" , 0x1180080e03d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1954" , 0x1180080e03d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1955" , 0x1180080e03d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1956" , 0x1180080e03d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1957" , 0x1180080e03d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1958" , 0x1180080e03d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1959" , 0x1180080e03d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1960" , 0x1180080e03d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1961" , 0x1180080e03d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1962" , 0x1180080e03d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1963" , 0x1180080e03d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1964" , 0x1180080e03d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1965" , 0x1180080e03d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1966" , 0x1180080e03d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1967" , 0x1180080e03d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1968" , 0x1180080e03d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1969" , 0x1180080e03d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1970" , 0x1180080e03d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1971" , 0x1180080e03d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1972" , 0x1180080e03da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1973" , 0x1180080e03da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1974" , 0x1180080e03db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1975" , 0x1180080e03db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1976" , 0x1180080e03dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1977" , 0x1180080e03dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1978" , 0x1180080e03dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1979" , 0x1180080e03dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1980" , 0x1180080e03de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1981" , 0x1180080e03de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1982" , 0x1180080e03df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1983" , 0x1180080e03df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1984" , 0x1180080e03e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1985" , 0x1180080e03e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1986" , 0x1180080e03e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1987" , 0x1180080e03e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1988" , 0x1180080e03e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1989" , 0x1180080e03e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1990" , 0x1180080e03e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1991" , 0x1180080e03e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1992" , 0x1180080e03e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1993" , 0x1180080e03e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1994" , 0x1180080e03e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1995" , 0x1180080e03e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1996" , 0x1180080e03e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1997" , 0x1180080e03e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1998" , 0x1180080e03e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP1999" , 0x1180080e03e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2000" , 0x1180080e03e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2001" , 0x1180080e03e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2002" , 0x1180080e03e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2003" , 0x1180080e03e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2004" , 0x1180080e03ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2005" , 0x1180080e03ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2006" , 0x1180080e03eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2007" , 0x1180080e03eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2008" , 0x1180080e03ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2009" , 0x1180080e03ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2010" , 0x1180080e03ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2011" , 0x1180080e03ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2012" , 0x1180080e03ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2013" , 0x1180080e03ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2014" , 0x1180080e03ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2015" , 0x1180080e03ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2016" , 0x1180080e03f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2017" , 0x1180080e03f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2018" , 0x1180080e03f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2019" , 0x1180080e03f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2020" , 0x1180080e03f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2021" , 0x1180080e03f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2022" , 0x1180080e03f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2023" , 0x1180080e03f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2024" , 0x1180080e03f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2025" , 0x1180080e03f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2026" , 0x1180080e03f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2027" , 0x1180080e03f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2028" , 0x1180080e03f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2029" , 0x1180080e03f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2030" , 0x1180080e03f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2031" , 0x1180080e03f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2032" , 0x1180080e03f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2033" , 0x1180080e03f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2034" , 0x1180080e03f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2035" , 0x1180080e03f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2036" , 0x1180080e03fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2037" , 0x1180080e03fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2038" , 0x1180080e03fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2039" , 0x1180080e03fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2040" , 0x1180080e03fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2041" , 0x1180080e03fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2042" , 0x1180080e03fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2043" , 0x1180080e03fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2044" , 0x1180080e03fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2045" , 0x1180080e03fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2046" , 0x1180080e03ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2047" , 0x1180080e03ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2048" , 0x1180080e04000ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2049" , 0x1180080e04008ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2050" , 0x1180080e04010ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2051" , 0x1180080e04018ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2052" , 0x1180080e04020ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2053" , 0x1180080e04028ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2054" , 0x1180080e04030ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2055" , 0x1180080e04038ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2056" , 0x1180080e04040ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2057" , 0x1180080e04048ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2058" , 0x1180080e04050ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2059" , 0x1180080e04058ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2060" , 0x1180080e04060ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2061" , 0x1180080e04068ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2062" , 0x1180080e04070ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2063" , 0x1180080e04078ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2064" , 0x1180080e04080ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2065" , 0x1180080e04088ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2066" , 0x1180080e04090ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2067" , 0x1180080e04098ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2068" , 0x1180080e040a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2069" , 0x1180080e040a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2070" , 0x1180080e040b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2071" , 0x1180080e040b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2072" , 0x1180080e040c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2073" , 0x1180080e040c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2074" , 0x1180080e040d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2075" , 0x1180080e040d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2076" , 0x1180080e040e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2077" , 0x1180080e040e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2078" , 0x1180080e040f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2079" , 0x1180080e040f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2080" , 0x1180080e04100ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2081" , 0x1180080e04108ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2082" , 0x1180080e04110ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2083" , 0x1180080e04118ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2084" , 0x1180080e04120ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2085" , 0x1180080e04128ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2086" , 0x1180080e04130ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2087" , 0x1180080e04138ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2088" , 0x1180080e04140ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2089" , 0x1180080e04148ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2090" , 0x1180080e04150ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2091" , 0x1180080e04158ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2092" , 0x1180080e04160ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2093" , 0x1180080e04168ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2094" , 0x1180080e04170ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2095" , 0x1180080e04178ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2096" , 0x1180080e04180ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2097" , 0x1180080e04188ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2098" , 0x1180080e04190ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2099" , 0x1180080e04198ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2100" , 0x1180080e041a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2101" , 0x1180080e041a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2102" , 0x1180080e041b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2103" , 0x1180080e041b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2104" , 0x1180080e041c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2105" , 0x1180080e041c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2106" , 0x1180080e041d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2107" , 0x1180080e041d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2108" , 0x1180080e041e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2109" , 0x1180080e041e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2110" , 0x1180080e041f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2111" , 0x1180080e041f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2112" , 0x1180080e04200ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2113" , 0x1180080e04208ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2114" , 0x1180080e04210ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2115" , 0x1180080e04218ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2116" , 0x1180080e04220ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2117" , 0x1180080e04228ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2118" , 0x1180080e04230ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2119" , 0x1180080e04238ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2120" , 0x1180080e04240ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2121" , 0x1180080e04248ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2122" , 0x1180080e04250ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2123" , 0x1180080e04258ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2124" , 0x1180080e04260ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2125" , 0x1180080e04268ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2126" , 0x1180080e04270ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2127" , 0x1180080e04278ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2128" , 0x1180080e04280ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2129" , 0x1180080e04288ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2130" , 0x1180080e04290ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2131" , 0x1180080e04298ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2132" , 0x1180080e042a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2133" , 0x1180080e042a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2134" , 0x1180080e042b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2135" , 0x1180080e042b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2136" , 0x1180080e042c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2137" , 0x1180080e042c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2138" , 0x1180080e042d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2139" , 0x1180080e042d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2140" , 0x1180080e042e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2141" , 0x1180080e042e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2142" , 0x1180080e042f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2143" , 0x1180080e042f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2144" , 0x1180080e04300ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2145" , 0x1180080e04308ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2146" , 0x1180080e04310ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2147" , 0x1180080e04318ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2148" , 0x1180080e04320ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2149" , 0x1180080e04328ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2150" , 0x1180080e04330ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2151" , 0x1180080e04338ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2152" , 0x1180080e04340ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2153" , 0x1180080e04348ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2154" , 0x1180080e04350ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2155" , 0x1180080e04358ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2156" , 0x1180080e04360ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2157" , 0x1180080e04368ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2158" , 0x1180080e04370ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2159" , 0x1180080e04378ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2160" , 0x1180080e04380ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2161" , 0x1180080e04388ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2162" , 0x1180080e04390ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2163" , 0x1180080e04398ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2164" , 0x1180080e043a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2165" , 0x1180080e043a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2166" , 0x1180080e043b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2167" , 0x1180080e043b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2168" , 0x1180080e043c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2169" , 0x1180080e043c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2170" , 0x1180080e043d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2171" , 0x1180080e043d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2172" , 0x1180080e043e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2173" , 0x1180080e043e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2174" , 0x1180080e043f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2175" , 0x1180080e043f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2176" , 0x1180080e04400ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2177" , 0x1180080e04408ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2178" , 0x1180080e04410ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2179" , 0x1180080e04418ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2180" , 0x1180080e04420ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2181" , 0x1180080e04428ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2182" , 0x1180080e04430ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2183" , 0x1180080e04438ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2184" , 0x1180080e04440ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2185" , 0x1180080e04448ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2186" , 0x1180080e04450ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2187" , 0x1180080e04458ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2188" , 0x1180080e04460ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2189" , 0x1180080e04468ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2190" , 0x1180080e04470ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2191" , 0x1180080e04478ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2192" , 0x1180080e04480ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2193" , 0x1180080e04488ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2194" , 0x1180080e04490ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2195" , 0x1180080e04498ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2196" , 0x1180080e044a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2197" , 0x1180080e044a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2198" , 0x1180080e044b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2199" , 0x1180080e044b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2200" , 0x1180080e044c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2201" , 0x1180080e044c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2202" , 0x1180080e044d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2203" , 0x1180080e044d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2204" , 0x1180080e044e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2205" , 0x1180080e044e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2206" , 0x1180080e044f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2207" , 0x1180080e044f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2208" , 0x1180080e04500ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2209" , 0x1180080e04508ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2210" , 0x1180080e04510ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2211" , 0x1180080e04518ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2212" , 0x1180080e04520ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2213" , 0x1180080e04528ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2214" , 0x1180080e04530ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2215" , 0x1180080e04538ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2216" , 0x1180080e04540ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2217" , 0x1180080e04548ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2218" , 0x1180080e04550ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2219" , 0x1180080e04558ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2220" , 0x1180080e04560ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2221" , 0x1180080e04568ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2222" , 0x1180080e04570ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2223" , 0x1180080e04578ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2224" , 0x1180080e04580ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2225" , 0x1180080e04588ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2226" , 0x1180080e04590ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2227" , 0x1180080e04598ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2228" , 0x1180080e045a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2229" , 0x1180080e045a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2230" , 0x1180080e045b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2231" , 0x1180080e045b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2232" , 0x1180080e045c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2233" , 0x1180080e045c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2234" , 0x1180080e045d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2235" , 0x1180080e045d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2236" , 0x1180080e045e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2237" , 0x1180080e045e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2238" , 0x1180080e045f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2239" , 0x1180080e045f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2240" , 0x1180080e04600ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2241" , 0x1180080e04608ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2242" , 0x1180080e04610ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2243" , 0x1180080e04618ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2244" , 0x1180080e04620ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2245" , 0x1180080e04628ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2246" , 0x1180080e04630ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2247" , 0x1180080e04638ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2248" , 0x1180080e04640ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2249" , 0x1180080e04648ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2250" , 0x1180080e04650ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2251" , 0x1180080e04658ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2252" , 0x1180080e04660ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2253" , 0x1180080e04668ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2254" , 0x1180080e04670ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2255" , 0x1180080e04678ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2256" , 0x1180080e04680ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2257" , 0x1180080e04688ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2258" , 0x1180080e04690ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2259" , 0x1180080e04698ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2260" , 0x1180080e046a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2261" , 0x1180080e046a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2262" , 0x1180080e046b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2263" , 0x1180080e046b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2264" , 0x1180080e046c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2265" , 0x1180080e046c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2266" , 0x1180080e046d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2267" , 0x1180080e046d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2268" , 0x1180080e046e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2269" , 0x1180080e046e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2270" , 0x1180080e046f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2271" , 0x1180080e046f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2272" , 0x1180080e04700ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2273" , 0x1180080e04708ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2274" , 0x1180080e04710ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2275" , 0x1180080e04718ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2276" , 0x1180080e04720ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2277" , 0x1180080e04728ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2278" , 0x1180080e04730ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2279" , 0x1180080e04738ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2280" , 0x1180080e04740ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2281" , 0x1180080e04748ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2282" , 0x1180080e04750ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2283" , 0x1180080e04758ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2284" , 0x1180080e04760ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2285" , 0x1180080e04768ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2286" , 0x1180080e04770ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2287" , 0x1180080e04778ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2288" , 0x1180080e04780ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2289" , 0x1180080e04788ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2290" , 0x1180080e04790ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2291" , 0x1180080e04798ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2292" , 0x1180080e047a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2293" , 0x1180080e047a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2294" , 0x1180080e047b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2295" , 0x1180080e047b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2296" , 0x1180080e047c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2297" , 0x1180080e047c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2298" , 0x1180080e047d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2299" , 0x1180080e047d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2300" , 0x1180080e047e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2301" , 0x1180080e047e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2302" , 0x1180080e047f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2303" , 0x1180080e047f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2304" , 0x1180080e04800ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2305" , 0x1180080e04808ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2306" , 0x1180080e04810ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2307" , 0x1180080e04818ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2308" , 0x1180080e04820ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2309" , 0x1180080e04828ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2310" , 0x1180080e04830ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2311" , 0x1180080e04838ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2312" , 0x1180080e04840ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2313" , 0x1180080e04848ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2314" , 0x1180080e04850ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2315" , 0x1180080e04858ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2316" , 0x1180080e04860ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2317" , 0x1180080e04868ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2318" , 0x1180080e04870ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2319" , 0x1180080e04878ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2320" , 0x1180080e04880ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2321" , 0x1180080e04888ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2322" , 0x1180080e04890ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2323" , 0x1180080e04898ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2324" , 0x1180080e048a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2325" , 0x1180080e048a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2326" , 0x1180080e048b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2327" , 0x1180080e048b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2328" , 0x1180080e048c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2329" , 0x1180080e048c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2330" , 0x1180080e048d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2331" , 0x1180080e048d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2332" , 0x1180080e048e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2333" , 0x1180080e048e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2334" , 0x1180080e048f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2335" , 0x1180080e048f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2336" , 0x1180080e04900ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2337" , 0x1180080e04908ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2338" , 0x1180080e04910ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2339" , 0x1180080e04918ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2340" , 0x1180080e04920ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2341" , 0x1180080e04928ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2342" , 0x1180080e04930ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2343" , 0x1180080e04938ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2344" , 0x1180080e04940ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2345" , 0x1180080e04948ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2346" , 0x1180080e04950ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2347" , 0x1180080e04958ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2348" , 0x1180080e04960ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2349" , 0x1180080e04968ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2350" , 0x1180080e04970ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2351" , 0x1180080e04978ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2352" , 0x1180080e04980ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2353" , 0x1180080e04988ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2354" , 0x1180080e04990ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2355" , 0x1180080e04998ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2356" , 0x1180080e049a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2357" , 0x1180080e049a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2358" , 0x1180080e049b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2359" , 0x1180080e049b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2360" , 0x1180080e049c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2361" , 0x1180080e049c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2362" , 0x1180080e049d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2363" , 0x1180080e049d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2364" , 0x1180080e049e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2365" , 0x1180080e049e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2366" , 0x1180080e049f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2367" , 0x1180080e049f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2368" , 0x1180080e04a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2369" , 0x1180080e04a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2370" , 0x1180080e04a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2371" , 0x1180080e04a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2372" , 0x1180080e04a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2373" , 0x1180080e04a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2374" , 0x1180080e04a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2375" , 0x1180080e04a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2376" , 0x1180080e04a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2377" , 0x1180080e04a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2378" , 0x1180080e04a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2379" , 0x1180080e04a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2380" , 0x1180080e04a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2381" , 0x1180080e04a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2382" , 0x1180080e04a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2383" , 0x1180080e04a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2384" , 0x1180080e04a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2385" , 0x1180080e04a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2386" , 0x1180080e04a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2387" , 0x1180080e04a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2388" , 0x1180080e04aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2389" , 0x1180080e04aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2390" , 0x1180080e04ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2391" , 0x1180080e04ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2392" , 0x1180080e04ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2393" , 0x1180080e04ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2394" , 0x1180080e04ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2395" , 0x1180080e04ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2396" , 0x1180080e04ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2397" , 0x1180080e04ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2398" , 0x1180080e04af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2399" , 0x1180080e04af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2400" , 0x1180080e04b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2401" , 0x1180080e04b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2402" , 0x1180080e04b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2403" , 0x1180080e04b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2404" , 0x1180080e04b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2405" , 0x1180080e04b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2406" , 0x1180080e04b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2407" , 0x1180080e04b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2408" , 0x1180080e04b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2409" , 0x1180080e04b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2410" , 0x1180080e04b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2411" , 0x1180080e04b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2412" , 0x1180080e04b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2413" , 0x1180080e04b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2414" , 0x1180080e04b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2415" , 0x1180080e04b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2416" , 0x1180080e04b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2417" , 0x1180080e04b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2418" , 0x1180080e04b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2419" , 0x1180080e04b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2420" , 0x1180080e04ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2421" , 0x1180080e04ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2422" , 0x1180080e04bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2423" , 0x1180080e04bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2424" , 0x1180080e04bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2425" , 0x1180080e04bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2426" , 0x1180080e04bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2427" , 0x1180080e04bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2428" , 0x1180080e04be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2429" , 0x1180080e04be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2430" , 0x1180080e04bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2431" , 0x1180080e04bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2432" , 0x1180080e04c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2433" , 0x1180080e04c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2434" , 0x1180080e04c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2435" , 0x1180080e04c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2436" , 0x1180080e04c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2437" , 0x1180080e04c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2438" , 0x1180080e04c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2439" , 0x1180080e04c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2440" , 0x1180080e04c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2441" , 0x1180080e04c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2442" , 0x1180080e04c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2443" , 0x1180080e04c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2444" , 0x1180080e04c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2445" , 0x1180080e04c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2446" , 0x1180080e04c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2447" , 0x1180080e04c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2448" , 0x1180080e04c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2449" , 0x1180080e04c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2450" , 0x1180080e04c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2451" , 0x1180080e04c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2452" , 0x1180080e04ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2453" , 0x1180080e04ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2454" , 0x1180080e04cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2455" , 0x1180080e04cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2456" , 0x1180080e04cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2457" , 0x1180080e04cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2458" , 0x1180080e04cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2459" , 0x1180080e04cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2460" , 0x1180080e04ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2461" , 0x1180080e04ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2462" , 0x1180080e04cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2463" , 0x1180080e04cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2464" , 0x1180080e04d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2465" , 0x1180080e04d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2466" , 0x1180080e04d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2467" , 0x1180080e04d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2468" , 0x1180080e04d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2469" , 0x1180080e04d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2470" , 0x1180080e04d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2471" , 0x1180080e04d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2472" , 0x1180080e04d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2473" , 0x1180080e04d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2474" , 0x1180080e04d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2475" , 0x1180080e04d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2476" , 0x1180080e04d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2477" , 0x1180080e04d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2478" , 0x1180080e04d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2479" , 0x1180080e04d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2480" , 0x1180080e04d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2481" , 0x1180080e04d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2482" , 0x1180080e04d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2483" , 0x1180080e04d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2484" , 0x1180080e04da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2485" , 0x1180080e04da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2486" , 0x1180080e04db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2487" , 0x1180080e04db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2488" , 0x1180080e04dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2489" , 0x1180080e04dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2490" , 0x1180080e04dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2491" , 0x1180080e04dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2492" , 0x1180080e04de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2493" , 0x1180080e04de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2494" , 0x1180080e04df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2495" , 0x1180080e04df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2496" , 0x1180080e04e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2497" , 0x1180080e04e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2498" , 0x1180080e04e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2499" , 0x1180080e04e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2500" , 0x1180080e04e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2501" , 0x1180080e04e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2502" , 0x1180080e04e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2503" , 0x1180080e04e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2504" , 0x1180080e04e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2505" , 0x1180080e04e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2506" , 0x1180080e04e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2507" , 0x1180080e04e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2508" , 0x1180080e04e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2509" , 0x1180080e04e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2510" , 0x1180080e04e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2511" , 0x1180080e04e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2512" , 0x1180080e04e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2513" , 0x1180080e04e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2514" , 0x1180080e04e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2515" , 0x1180080e04e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2516" , 0x1180080e04ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2517" , 0x1180080e04ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2518" , 0x1180080e04eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2519" , 0x1180080e04eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2520" , 0x1180080e04ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2521" , 0x1180080e04ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2522" , 0x1180080e04ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2523" , 0x1180080e04ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2524" , 0x1180080e04ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2525" , 0x1180080e04ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2526" , 0x1180080e04ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2527" , 0x1180080e04ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2528" , 0x1180080e04f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2529" , 0x1180080e04f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2530" , 0x1180080e04f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2531" , 0x1180080e04f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2532" , 0x1180080e04f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2533" , 0x1180080e04f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2534" , 0x1180080e04f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2535" , 0x1180080e04f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2536" , 0x1180080e04f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2537" , 0x1180080e04f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2538" , 0x1180080e04f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2539" , 0x1180080e04f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2540" , 0x1180080e04f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2541" , 0x1180080e04f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2542" , 0x1180080e04f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2543" , 0x1180080e04f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2544" , 0x1180080e04f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2545" , 0x1180080e04f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2546" , 0x1180080e04f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2547" , 0x1180080e04f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2548" , 0x1180080e04fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2549" , 0x1180080e04fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2550" , 0x1180080e04fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2551" , 0x1180080e04fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2552" , 0x1180080e04fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2553" , 0x1180080e04fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2554" , 0x1180080e04fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2555" , 0x1180080e04fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2556" , 0x1180080e04fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2557" , 0x1180080e04fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2558" , 0x1180080e04ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_DUT_MAP2559" , 0x1180080e04ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"L2C_ERR_TDT0" , 0x1180080a007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"L2C_ERR_TTG0" , 0x1180080a007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"L2C_ERR_VBF0" , 0x1180080c007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"L2C_ERR_XMC" , 0x11800808007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"L2C_INT_ENA" , 0x1180080800020ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"L2C_INT_REG" , 0x1180080800018ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"L2C_IOC0_PFC" , 0x1180080800420ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"L2C_IOR0_PFC" , 0x1180080800428ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"L2C_QOS_IOB0" , 0x1180080880200ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"L2C_QOS_PP0" , 0x1180080880000ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"L2C_QOS_PP1" , 0x1180080880008ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"L2C_QOS_PP2" , 0x1180080880010ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"L2C_QOS_PP3" , 0x1180080880018ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"L2C_QOS_PP4" , 0x1180080880020ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"L2C_QOS_PP5" , 0x1180080880028ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"L2C_QOS_PP6" , 0x1180080880030ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"L2C_QOS_PP7" , 0x1180080880038ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"L2C_QOS_PP8" , 0x1180080880040ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"L2C_QOS_PP9" , 0x1180080880048ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"L2C_QOS_WGT" , 0x1180080800008ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"L2C_RSC0_PFC" , 0x1180080800410ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"L2C_RSD0_PFC" , 0x1180080800418ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"L2C_TAD0_ECC0" , 0x1180080a00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"L2C_TAD0_ECC1" , 0x1180080a00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"L2C_TAD0_IEN" , 0x1180080a00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"L2C_TAD0_INT" , 0x1180080a00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"L2C_TAD0_PFC0" , 0x1180080a00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"L2C_TAD0_PFC1" , 0x1180080a00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"L2C_TAD0_PFC2" , 0x1180080a00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"L2C_TAD0_PFC3" , 0x1180080a00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"L2C_TAD0_PRF" , 0x1180080a00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"L2C_TAD0_TAG" , 0x1180080a00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"L2C_VER_ID" , 0x11800808007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"L2C_VER_IOB" , 0x11800808007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"L2C_VER_MSC" , 0x11800808007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"L2C_VER_PP" , 0x11800808007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"L2C_VIRTID_IOB0" , 0x11800808c0200ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"L2C_VIRTID_PP0" , 0x11800808c0000ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"L2C_VIRTID_PP1" , 0x11800808c0008ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"L2C_VIRTID_PP2" , 0x11800808c0010ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"L2C_VIRTID_PP3" , 0x11800808c0018ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"L2C_VIRTID_PP4" , 0x11800808c0020ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"L2C_VIRTID_PP5" , 0x11800808c0028ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"L2C_VIRTID_PP6" , 0x11800808c0030ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"L2C_VIRTID_PP7" , 0x11800808c0038ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"L2C_VIRTID_PP8" , 0x11800808c0040ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"L2C_VIRTID_PP9" , 0x11800808c0048ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"L2C_VRT_CTL" , 0x1180080800010ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"L2C_VRT_MEM0" , 0x1180080900000ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1" , 0x1180080900008ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM2" , 0x1180080900010ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM3" , 0x1180080900018ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM4" , 0x1180080900020ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM5" , 0x1180080900028ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM6" , 0x1180080900030ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM7" , 0x1180080900038ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM8" , 0x1180080900040ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM9" , 0x1180080900048ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM10" , 0x1180080900050ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM11" , 0x1180080900058ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM12" , 0x1180080900060ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM13" , 0x1180080900068ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM14" , 0x1180080900070ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM15" , 0x1180080900078ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM16" , 0x1180080900080ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM17" , 0x1180080900088ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM18" , 0x1180080900090ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM19" , 0x1180080900098ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM20" , 0x11800809000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM21" , 0x11800809000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM22" , 0x11800809000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM23" , 0x11800809000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM24" , 0x11800809000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM25" , 0x11800809000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM26" , 0x11800809000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM27" , 0x11800809000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM28" , 0x11800809000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM29" , 0x11800809000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM30" , 0x11800809000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM31" , 0x11800809000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM32" , 0x1180080900100ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM33" , 0x1180080900108ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM34" , 0x1180080900110ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM35" , 0x1180080900118ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM36" , 0x1180080900120ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM37" , 0x1180080900128ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM38" , 0x1180080900130ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM39" , 0x1180080900138ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM40" , 0x1180080900140ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM41" , 0x1180080900148ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM42" , 0x1180080900150ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM43" , 0x1180080900158ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM44" , 0x1180080900160ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM45" , 0x1180080900168ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM46" , 0x1180080900170ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM47" , 0x1180080900178ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM48" , 0x1180080900180ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM49" , 0x1180080900188ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM50" , 0x1180080900190ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM51" , 0x1180080900198ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM52" , 0x11800809001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM53" , 0x11800809001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM54" , 0x11800809001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM55" , 0x11800809001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM56" , 0x11800809001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM57" , 0x11800809001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM58" , 0x11800809001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM59" , 0x11800809001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM60" , 0x11800809001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM61" , 0x11800809001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM62" , 0x11800809001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM63" , 0x11800809001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM64" , 0x1180080900200ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM65" , 0x1180080900208ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM66" , 0x1180080900210ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM67" , 0x1180080900218ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM68" , 0x1180080900220ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM69" , 0x1180080900228ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM70" , 0x1180080900230ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM71" , 0x1180080900238ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM72" , 0x1180080900240ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM73" , 0x1180080900248ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM74" , 0x1180080900250ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM75" , 0x1180080900258ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM76" , 0x1180080900260ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM77" , 0x1180080900268ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM78" , 0x1180080900270ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM79" , 0x1180080900278ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM80" , 0x1180080900280ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM81" , 0x1180080900288ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM82" , 0x1180080900290ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM83" , 0x1180080900298ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM84" , 0x11800809002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM85" , 0x11800809002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM86" , 0x11800809002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM87" , 0x11800809002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM88" , 0x11800809002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM89" , 0x11800809002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM90" , 0x11800809002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM91" , 0x11800809002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM92" , 0x11800809002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM93" , 0x11800809002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM94" , 0x11800809002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM95" , 0x11800809002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM96" , 0x1180080900300ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM97" , 0x1180080900308ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM98" , 0x1180080900310ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM99" , 0x1180080900318ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM100" , 0x1180080900320ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM101" , 0x1180080900328ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM102" , 0x1180080900330ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM103" , 0x1180080900338ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM104" , 0x1180080900340ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM105" , 0x1180080900348ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM106" , 0x1180080900350ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM107" , 0x1180080900358ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM108" , 0x1180080900360ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM109" , 0x1180080900368ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM110" , 0x1180080900370ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM111" , 0x1180080900378ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM112" , 0x1180080900380ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM113" , 0x1180080900388ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM114" , 0x1180080900390ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM115" , 0x1180080900398ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM116" , 0x11800809003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM117" , 0x11800809003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM118" , 0x11800809003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM119" , 0x11800809003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM120" , 0x11800809003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM121" , 0x11800809003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM122" , 0x11800809003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM123" , 0x11800809003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM124" , 0x11800809003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM125" , 0x11800809003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM126" , 0x11800809003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM127" , 0x11800809003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM128" , 0x1180080900400ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM129" , 0x1180080900408ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM130" , 0x1180080900410ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM131" , 0x1180080900418ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM132" , 0x1180080900420ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM133" , 0x1180080900428ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM134" , 0x1180080900430ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM135" , 0x1180080900438ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM136" , 0x1180080900440ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM137" , 0x1180080900448ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM138" , 0x1180080900450ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM139" , 0x1180080900458ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM140" , 0x1180080900460ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM141" , 0x1180080900468ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM142" , 0x1180080900470ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM143" , 0x1180080900478ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM144" , 0x1180080900480ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM145" , 0x1180080900488ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM146" , 0x1180080900490ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM147" , 0x1180080900498ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM148" , 0x11800809004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM149" , 0x11800809004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM150" , 0x11800809004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM151" , 0x11800809004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM152" , 0x11800809004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM153" , 0x11800809004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM154" , 0x11800809004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM155" , 0x11800809004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM156" , 0x11800809004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM157" , 0x11800809004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM158" , 0x11800809004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM159" , 0x11800809004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM160" , 0x1180080900500ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM161" , 0x1180080900508ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM162" , 0x1180080900510ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM163" , 0x1180080900518ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM164" , 0x1180080900520ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM165" , 0x1180080900528ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM166" , 0x1180080900530ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM167" , 0x1180080900538ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM168" , 0x1180080900540ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM169" , 0x1180080900548ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM170" , 0x1180080900550ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM171" , 0x1180080900558ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM172" , 0x1180080900560ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM173" , 0x1180080900568ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM174" , 0x1180080900570ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM175" , 0x1180080900578ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM176" , 0x1180080900580ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM177" , 0x1180080900588ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM178" , 0x1180080900590ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM179" , 0x1180080900598ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM180" , 0x11800809005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM181" , 0x11800809005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM182" , 0x11800809005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM183" , 0x11800809005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM184" , 0x11800809005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM185" , 0x11800809005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM186" , 0x11800809005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM187" , 0x11800809005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM188" , 0x11800809005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM189" , 0x11800809005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM190" , 0x11800809005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM191" , 0x11800809005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM192" , 0x1180080900600ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM193" , 0x1180080900608ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM194" , 0x1180080900610ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM195" , 0x1180080900618ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM196" , 0x1180080900620ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM197" , 0x1180080900628ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM198" , 0x1180080900630ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM199" , 0x1180080900638ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM200" , 0x1180080900640ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM201" , 0x1180080900648ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM202" , 0x1180080900650ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM203" , 0x1180080900658ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM204" , 0x1180080900660ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM205" , 0x1180080900668ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM206" , 0x1180080900670ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM207" , 0x1180080900678ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM208" , 0x1180080900680ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM209" , 0x1180080900688ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM210" , 0x1180080900690ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM211" , 0x1180080900698ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM212" , 0x11800809006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM213" , 0x11800809006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM214" , 0x11800809006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM215" , 0x11800809006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM216" , 0x11800809006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM217" , 0x11800809006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM218" , 0x11800809006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM219" , 0x11800809006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM220" , 0x11800809006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM221" , 0x11800809006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM222" , 0x11800809006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM223" , 0x11800809006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM224" , 0x1180080900700ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM225" , 0x1180080900708ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM226" , 0x1180080900710ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM227" , 0x1180080900718ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM228" , 0x1180080900720ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM229" , 0x1180080900728ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM230" , 0x1180080900730ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM231" , 0x1180080900738ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM232" , 0x1180080900740ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM233" , 0x1180080900748ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM234" , 0x1180080900750ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM235" , 0x1180080900758ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM236" , 0x1180080900760ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM237" , 0x1180080900768ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM238" , 0x1180080900770ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM239" , 0x1180080900778ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM240" , 0x1180080900780ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM241" , 0x1180080900788ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM242" , 0x1180080900790ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM243" , 0x1180080900798ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM244" , 0x11800809007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM245" , 0x11800809007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM246" , 0x11800809007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM247" , 0x11800809007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM248" , 0x11800809007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM249" , 0x11800809007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM250" , 0x11800809007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM251" , 0x11800809007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM252" , 0x11800809007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM253" , 0x11800809007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM254" , 0x11800809007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM255" , 0x11800809007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM256" , 0x1180080900800ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM257" , 0x1180080900808ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM258" , 0x1180080900810ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM259" , 0x1180080900818ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM260" , 0x1180080900820ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM261" , 0x1180080900828ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM262" , 0x1180080900830ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM263" , 0x1180080900838ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM264" , 0x1180080900840ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM265" , 0x1180080900848ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM266" , 0x1180080900850ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM267" , 0x1180080900858ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM268" , 0x1180080900860ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM269" , 0x1180080900868ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM270" , 0x1180080900870ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM271" , 0x1180080900878ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM272" , 0x1180080900880ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM273" , 0x1180080900888ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM274" , 0x1180080900890ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM275" , 0x1180080900898ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM276" , 0x11800809008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM277" , 0x11800809008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM278" , 0x11800809008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM279" , 0x11800809008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM280" , 0x11800809008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM281" , 0x11800809008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM282" , 0x11800809008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM283" , 0x11800809008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM284" , 0x11800809008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM285" , 0x11800809008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM286" , 0x11800809008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM287" , 0x11800809008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM288" , 0x1180080900900ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM289" , 0x1180080900908ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM290" , 0x1180080900910ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM291" , 0x1180080900918ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM292" , 0x1180080900920ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM293" , 0x1180080900928ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM294" , 0x1180080900930ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM295" , 0x1180080900938ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM296" , 0x1180080900940ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM297" , 0x1180080900948ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM298" , 0x1180080900950ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM299" , 0x1180080900958ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM300" , 0x1180080900960ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM301" , 0x1180080900968ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM302" , 0x1180080900970ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM303" , 0x1180080900978ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM304" , 0x1180080900980ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM305" , 0x1180080900988ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM306" , 0x1180080900990ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM307" , 0x1180080900998ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM308" , 0x11800809009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM309" , 0x11800809009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM310" , 0x11800809009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM311" , 0x11800809009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM312" , 0x11800809009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM313" , 0x11800809009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM314" , 0x11800809009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM315" , 0x11800809009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM316" , 0x11800809009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM317" , 0x11800809009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM318" , 0x11800809009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM319" , 0x11800809009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM320" , 0x1180080900a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM321" , 0x1180080900a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM322" , 0x1180080900a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM323" , 0x1180080900a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM324" , 0x1180080900a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM325" , 0x1180080900a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM326" , 0x1180080900a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM327" , 0x1180080900a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM328" , 0x1180080900a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM329" , 0x1180080900a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM330" , 0x1180080900a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM331" , 0x1180080900a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM332" , 0x1180080900a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM333" , 0x1180080900a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM334" , 0x1180080900a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM335" , 0x1180080900a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM336" , 0x1180080900a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM337" , 0x1180080900a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM338" , 0x1180080900a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM339" , 0x1180080900a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM340" , 0x1180080900aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM341" , 0x1180080900aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM342" , 0x1180080900ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM343" , 0x1180080900ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM344" , 0x1180080900ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM345" , 0x1180080900ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM346" , 0x1180080900ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM347" , 0x1180080900ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM348" , 0x1180080900ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM349" , 0x1180080900ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM350" , 0x1180080900af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM351" , 0x1180080900af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM352" , 0x1180080900b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM353" , 0x1180080900b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM354" , 0x1180080900b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM355" , 0x1180080900b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM356" , 0x1180080900b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM357" , 0x1180080900b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM358" , 0x1180080900b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM359" , 0x1180080900b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM360" , 0x1180080900b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM361" , 0x1180080900b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM362" , 0x1180080900b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM363" , 0x1180080900b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM364" , 0x1180080900b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM365" , 0x1180080900b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM366" , 0x1180080900b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM367" , 0x1180080900b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM368" , 0x1180080900b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM369" , 0x1180080900b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM370" , 0x1180080900b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM371" , 0x1180080900b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM372" , 0x1180080900ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM373" , 0x1180080900ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM374" , 0x1180080900bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM375" , 0x1180080900bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM376" , 0x1180080900bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM377" , 0x1180080900bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM378" , 0x1180080900bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM379" , 0x1180080900bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM380" , 0x1180080900be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM381" , 0x1180080900be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM382" , 0x1180080900bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM383" , 0x1180080900bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM384" , 0x1180080900c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM385" , 0x1180080900c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM386" , 0x1180080900c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM387" , 0x1180080900c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM388" , 0x1180080900c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM389" , 0x1180080900c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM390" , 0x1180080900c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM391" , 0x1180080900c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM392" , 0x1180080900c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM393" , 0x1180080900c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM394" , 0x1180080900c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM395" , 0x1180080900c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM396" , 0x1180080900c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM397" , 0x1180080900c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM398" , 0x1180080900c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM399" , 0x1180080900c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM400" , 0x1180080900c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM401" , 0x1180080900c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM402" , 0x1180080900c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM403" , 0x1180080900c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM404" , 0x1180080900ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM405" , 0x1180080900ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM406" , 0x1180080900cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM407" , 0x1180080900cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM408" , 0x1180080900cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM409" , 0x1180080900cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM410" , 0x1180080900cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM411" , 0x1180080900cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM412" , 0x1180080900ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM413" , 0x1180080900ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM414" , 0x1180080900cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM415" , 0x1180080900cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM416" , 0x1180080900d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM417" , 0x1180080900d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM418" , 0x1180080900d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM419" , 0x1180080900d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM420" , 0x1180080900d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM421" , 0x1180080900d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM422" , 0x1180080900d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM423" , 0x1180080900d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM424" , 0x1180080900d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM425" , 0x1180080900d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM426" , 0x1180080900d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM427" , 0x1180080900d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM428" , 0x1180080900d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM429" , 0x1180080900d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM430" , 0x1180080900d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM431" , 0x1180080900d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM432" , 0x1180080900d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM433" , 0x1180080900d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM434" , 0x1180080900d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM435" , 0x1180080900d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM436" , 0x1180080900da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM437" , 0x1180080900da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM438" , 0x1180080900db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM439" , 0x1180080900db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM440" , 0x1180080900dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM441" , 0x1180080900dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM442" , 0x1180080900dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM443" , 0x1180080900dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM444" , 0x1180080900de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM445" , 0x1180080900de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM446" , 0x1180080900df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM447" , 0x1180080900df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM448" , 0x1180080900e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM449" , 0x1180080900e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM450" , 0x1180080900e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM451" , 0x1180080900e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM452" , 0x1180080900e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM453" , 0x1180080900e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM454" , 0x1180080900e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM455" , 0x1180080900e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM456" , 0x1180080900e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM457" , 0x1180080900e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM458" , 0x1180080900e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM459" , 0x1180080900e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM460" , 0x1180080900e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM461" , 0x1180080900e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM462" , 0x1180080900e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM463" , 0x1180080900e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM464" , 0x1180080900e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM465" , 0x1180080900e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM466" , 0x1180080900e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM467" , 0x1180080900e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM468" , 0x1180080900ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM469" , 0x1180080900ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM470" , 0x1180080900eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM471" , 0x1180080900eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM472" , 0x1180080900ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM473" , 0x1180080900ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM474" , 0x1180080900ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM475" , 0x1180080900ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM476" , 0x1180080900ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM477" , 0x1180080900ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM478" , 0x1180080900ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM479" , 0x1180080900ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM480" , 0x1180080900f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM481" , 0x1180080900f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM482" , 0x1180080900f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM483" , 0x1180080900f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM484" , 0x1180080900f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM485" , 0x1180080900f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM486" , 0x1180080900f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM487" , 0x1180080900f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM488" , 0x1180080900f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM489" , 0x1180080900f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM490" , 0x1180080900f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM491" , 0x1180080900f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM492" , 0x1180080900f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM493" , 0x1180080900f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM494" , 0x1180080900f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM495" , 0x1180080900f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM496" , 0x1180080900f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM497" , 0x1180080900f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM498" , 0x1180080900f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM499" , 0x1180080900f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM500" , 0x1180080900fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM501" , 0x1180080900fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM502" , 0x1180080900fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM503" , 0x1180080900fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM504" , 0x1180080900fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM505" , 0x1180080900fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM506" , 0x1180080900fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM507" , 0x1180080900fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM508" , 0x1180080900fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM509" , 0x1180080900fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM510" , 0x1180080900ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM511" , 0x1180080900ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM512" , 0x1180080901000ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM513" , 0x1180080901008ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM514" , 0x1180080901010ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM515" , 0x1180080901018ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM516" , 0x1180080901020ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM517" , 0x1180080901028ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM518" , 0x1180080901030ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM519" , 0x1180080901038ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM520" , 0x1180080901040ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM521" , 0x1180080901048ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM522" , 0x1180080901050ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM523" , 0x1180080901058ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM524" , 0x1180080901060ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM525" , 0x1180080901068ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM526" , 0x1180080901070ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM527" , 0x1180080901078ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM528" , 0x1180080901080ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM529" , 0x1180080901088ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM530" , 0x1180080901090ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM531" , 0x1180080901098ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM532" , 0x11800809010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM533" , 0x11800809010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM534" , 0x11800809010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM535" , 0x11800809010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM536" , 0x11800809010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM537" , 0x11800809010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM538" , 0x11800809010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM539" , 0x11800809010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM540" , 0x11800809010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM541" , 0x11800809010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM542" , 0x11800809010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM543" , 0x11800809010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM544" , 0x1180080901100ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM545" , 0x1180080901108ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM546" , 0x1180080901110ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM547" , 0x1180080901118ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM548" , 0x1180080901120ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM549" , 0x1180080901128ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM550" , 0x1180080901130ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM551" , 0x1180080901138ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM552" , 0x1180080901140ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM553" , 0x1180080901148ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM554" , 0x1180080901150ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM555" , 0x1180080901158ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM556" , 0x1180080901160ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM557" , 0x1180080901168ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM558" , 0x1180080901170ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM559" , 0x1180080901178ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM560" , 0x1180080901180ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM561" , 0x1180080901188ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM562" , 0x1180080901190ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM563" , 0x1180080901198ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM564" , 0x11800809011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM565" , 0x11800809011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM566" , 0x11800809011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM567" , 0x11800809011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM568" , 0x11800809011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM569" , 0x11800809011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM570" , 0x11800809011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM571" , 0x11800809011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM572" , 0x11800809011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM573" , 0x11800809011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM574" , 0x11800809011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM575" , 0x11800809011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM576" , 0x1180080901200ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM577" , 0x1180080901208ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM578" , 0x1180080901210ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM579" , 0x1180080901218ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM580" , 0x1180080901220ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM581" , 0x1180080901228ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM582" , 0x1180080901230ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM583" , 0x1180080901238ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM584" , 0x1180080901240ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM585" , 0x1180080901248ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM586" , 0x1180080901250ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM587" , 0x1180080901258ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM588" , 0x1180080901260ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM589" , 0x1180080901268ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM590" , 0x1180080901270ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM591" , 0x1180080901278ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM592" , 0x1180080901280ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM593" , 0x1180080901288ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM594" , 0x1180080901290ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM595" , 0x1180080901298ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM596" , 0x11800809012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM597" , 0x11800809012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM598" , 0x11800809012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM599" , 0x11800809012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM600" , 0x11800809012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM601" , 0x11800809012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM602" , 0x11800809012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM603" , 0x11800809012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM604" , 0x11800809012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM605" , 0x11800809012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM606" , 0x11800809012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM607" , 0x11800809012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM608" , 0x1180080901300ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM609" , 0x1180080901308ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM610" , 0x1180080901310ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM611" , 0x1180080901318ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM612" , 0x1180080901320ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM613" , 0x1180080901328ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM614" , 0x1180080901330ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM615" , 0x1180080901338ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM616" , 0x1180080901340ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM617" , 0x1180080901348ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM618" , 0x1180080901350ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM619" , 0x1180080901358ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM620" , 0x1180080901360ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM621" , 0x1180080901368ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM622" , 0x1180080901370ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM623" , 0x1180080901378ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM624" , 0x1180080901380ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM625" , 0x1180080901388ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM626" , 0x1180080901390ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM627" , 0x1180080901398ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM628" , 0x11800809013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM629" , 0x11800809013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM630" , 0x11800809013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM631" , 0x11800809013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM632" , 0x11800809013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM633" , 0x11800809013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM634" , 0x11800809013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM635" , 0x11800809013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM636" , 0x11800809013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM637" , 0x11800809013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM638" , 0x11800809013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM639" , 0x11800809013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM640" , 0x1180080901400ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM641" , 0x1180080901408ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM642" , 0x1180080901410ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM643" , 0x1180080901418ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM644" , 0x1180080901420ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM645" , 0x1180080901428ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM646" , 0x1180080901430ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM647" , 0x1180080901438ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM648" , 0x1180080901440ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM649" , 0x1180080901448ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM650" , 0x1180080901450ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM651" , 0x1180080901458ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM652" , 0x1180080901460ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM653" , 0x1180080901468ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM654" , 0x1180080901470ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM655" , 0x1180080901478ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM656" , 0x1180080901480ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM657" , 0x1180080901488ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM658" , 0x1180080901490ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM659" , 0x1180080901498ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM660" , 0x11800809014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM661" , 0x11800809014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM662" , 0x11800809014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM663" , 0x11800809014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM664" , 0x11800809014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM665" , 0x11800809014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM666" , 0x11800809014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM667" , 0x11800809014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM668" , 0x11800809014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM669" , 0x11800809014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM670" , 0x11800809014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM671" , 0x11800809014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM672" , 0x1180080901500ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM673" , 0x1180080901508ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM674" , 0x1180080901510ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM675" , 0x1180080901518ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM676" , 0x1180080901520ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM677" , 0x1180080901528ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM678" , 0x1180080901530ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM679" , 0x1180080901538ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM680" , 0x1180080901540ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM681" , 0x1180080901548ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM682" , 0x1180080901550ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM683" , 0x1180080901558ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM684" , 0x1180080901560ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM685" , 0x1180080901568ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM686" , 0x1180080901570ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM687" , 0x1180080901578ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM688" , 0x1180080901580ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM689" , 0x1180080901588ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM690" , 0x1180080901590ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM691" , 0x1180080901598ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM692" , 0x11800809015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM693" , 0x11800809015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM694" , 0x11800809015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM695" , 0x11800809015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM696" , 0x11800809015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM697" , 0x11800809015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM698" , 0x11800809015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM699" , 0x11800809015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM700" , 0x11800809015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM701" , 0x11800809015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM702" , 0x11800809015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM703" , 0x11800809015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM704" , 0x1180080901600ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM705" , 0x1180080901608ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM706" , 0x1180080901610ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM707" , 0x1180080901618ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM708" , 0x1180080901620ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM709" , 0x1180080901628ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM710" , 0x1180080901630ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM711" , 0x1180080901638ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM712" , 0x1180080901640ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM713" , 0x1180080901648ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM714" , 0x1180080901650ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM715" , 0x1180080901658ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM716" , 0x1180080901660ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM717" , 0x1180080901668ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM718" , 0x1180080901670ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM719" , 0x1180080901678ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM720" , 0x1180080901680ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM721" , 0x1180080901688ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM722" , 0x1180080901690ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM723" , 0x1180080901698ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM724" , 0x11800809016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM725" , 0x11800809016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM726" , 0x11800809016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM727" , 0x11800809016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM728" , 0x11800809016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM729" , 0x11800809016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM730" , 0x11800809016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM731" , 0x11800809016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM732" , 0x11800809016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM733" , 0x11800809016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM734" , 0x11800809016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM735" , 0x11800809016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM736" , 0x1180080901700ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM737" , 0x1180080901708ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM738" , 0x1180080901710ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM739" , 0x1180080901718ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM740" , 0x1180080901720ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM741" , 0x1180080901728ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM742" , 0x1180080901730ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM743" , 0x1180080901738ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM744" , 0x1180080901740ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM745" , 0x1180080901748ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM746" , 0x1180080901750ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM747" , 0x1180080901758ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM748" , 0x1180080901760ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM749" , 0x1180080901768ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM750" , 0x1180080901770ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM751" , 0x1180080901778ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM752" , 0x1180080901780ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM753" , 0x1180080901788ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM754" , 0x1180080901790ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM755" , 0x1180080901798ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM756" , 0x11800809017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM757" , 0x11800809017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM758" , 0x11800809017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM759" , 0x11800809017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM760" , 0x11800809017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM761" , 0x11800809017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM762" , 0x11800809017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM763" , 0x11800809017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM764" , 0x11800809017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM765" , 0x11800809017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM766" , 0x11800809017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM767" , 0x11800809017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM768" , 0x1180080901800ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM769" , 0x1180080901808ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM770" , 0x1180080901810ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM771" , 0x1180080901818ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM772" , 0x1180080901820ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM773" , 0x1180080901828ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM774" , 0x1180080901830ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM775" , 0x1180080901838ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM776" , 0x1180080901840ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM777" , 0x1180080901848ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM778" , 0x1180080901850ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM779" , 0x1180080901858ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM780" , 0x1180080901860ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM781" , 0x1180080901868ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM782" , 0x1180080901870ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM783" , 0x1180080901878ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM784" , 0x1180080901880ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM785" , 0x1180080901888ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM786" , 0x1180080901890ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM787" , 0x1180080901898ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM788" , 0x11800809018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM789" , 0x11800809018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM790" , 0x11800809018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM791" , 0x11800809018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM792" , 0x11800809018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM793" , 0x11800809018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM794" , 0x11800809018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM795" , 0x11800809018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM796" , 0x11800809018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM797" , 0x11800809018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM798" , 0x11800809018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM799" , 0x11800809018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM800" , 0x1180080901900ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM801" , 0x1180080901908ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM802" , 0x1180080901910ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM803" , 0x1180080901918ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM804" , 0x1180080901920ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM805" , 0x1180080901928ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM806" , 0x1180080901930ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM807" , 0x1180080901938ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM808" , 0x1180080901940ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM809" , 0x1180080901948ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM810" , 0x1180080901950ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM811" , 0x1180080901958ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM812" , 0x1180080901960ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM813" , 0x1180080901968ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM814" , 0x1180080901970ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM815" , 0x1180080901978ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM816" , 0x1180080901980ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM817" , 0x1180080901988ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM818" , 0x1180080901990ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM819" , 0x1180080901998ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM820" , 0x11800809019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM821" , 0x11800809019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM822" , 0x11800809019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM823" , 0x11800809019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM824" , 0x11800809019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM825" , 0x11800809019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM826" , 0x11800809019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM827" , 0x11800809019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM828" , 0x11800809019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM829" , 0x11800809019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM830" , 0x11800809019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM831" , 0x11800809019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM832" , 0x1180080901a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM833" , 0x1180080901a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM834" , 0x1180080901a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM835" , 0x1180080901a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM836" , 0x1180080901a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM837" , 0x1180080901a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM838" , 0x1180080901a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM839" , 0x1180080901a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM840" , 0x1180080901a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM841" , 0x1180080901a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM842" , 0x1180080901a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM843" , 0x1180080901a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM844" , 0x1180080901a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM845" , 0x1180080901a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM846" , 0x1180080901a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM847" , 0x1180080901a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM848" , 0x1180080901a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM849" , 0x1180080901a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM850" , 0x1180080901a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM851" , 0x1180080901a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM852" , 0x1180080901aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM853" , 0x1180080901aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM854" , 0x1180080901ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM855" , 0x1180080901ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM856" , 0x1180080901ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM857" , 0x1180080901ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM858" , 0x1180080901ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM859" , 0x1180080901ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM860" , 0x1180080901ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM861" , 0x1180080901ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM862" , 0x1180080901af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM863" , 0x1180080901af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM864" , 0x1180080901b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM865" , 0x1180080901b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM866" , 0x1180080901b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM867" , 0x1180080901b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM868" , 0x1180080901b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM869" , 0x1180080901b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM870" , 0x1180080901b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM871" , 0x1180080901b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM872" , 0x1180080901b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM873" , 0x1180080901b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM874" , 0x1180080901b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM875" , 0x1180080901b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM876" , 0x1180080901b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM877" , 0x1180080901b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM878" , 0x1180080901b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM879" , 0x1180080901b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM880" , 0x1180080901b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM881" , 0x1180080901b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM882" , 0x1180080901b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM883" , 0x1180080901b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM884" , 0x1180080901ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM885" , 0x1180080901ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM886" , 0x1180080901bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM887" , 0x1180080901bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM888" , 0x1180080901bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM889" , 0x1180080901bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM890" , 0x1180080901bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM891" , 0x1180080901bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM892" , 0x1180080901be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM893" , 0x1180080901be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM894" , 0x1180080901bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM895" , 0x1180080901bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM896" , 0x1180080901c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM897" , 0x1180080901c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM898" , 0x1180080901c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM899" , 0x1180080901c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM900" , 0x1180080901c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM901" , 0x1180080901c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM902" , 0x1180080901c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM903" , 0x1180080901c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM904" , 0x1180080901c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM905" , 0x1180080901c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM906" , 0x1180080901c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM907" , 0x1180080901c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM908" , 0x1180080901c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM909" , 0x1180080901c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM910" , 0x1180080901c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM911" , 0x1180080901c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM912" , 0x1180080901c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM913" , 0x1180080901c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM914" , 0x1180080901c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM915" , 0x1180080901c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM916" , 0x1180080901ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM917" , 0x1180080901ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM918" , 0x1180080901cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM919" , 0x1180080901cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM920" , 0x1180080901cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM921" , 0x1180080901cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM922" , 0x1180080901cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM923" , 0x1180080901cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM924" , 0x1180080901ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM925" , 0x1180080901ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM926" , 0x1180080901cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM927" , 0x1180080901cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM928" , 0x1180080901d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM929" , 0x1180080901d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM930" , 0x1180080901d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM931" , 0x1180080901d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM932" , 0x1180080901d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM933" , 0x1180080901d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM934" , 0x1180080901d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM935" , 0x1180080901d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM936" , 0x1180080901d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM937" , 0x1180080901d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM938" , 0x1180080901d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM939" , 0x1180080901d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM940" , 0x1180080901d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM941" , 0x1180080901d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM942" , 0x1180080901d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM943" , 0x1180080901d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM944" , 0x1180080901d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM945" , 0x1180080901d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM946" , 0x1180080901d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM947" , 0x1180080901d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM948" , 0x1180080901da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM949" , 0x1180080901da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM950" , 0x1180080901db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM951" , 0x1180080901db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM952" , 0x1180080901dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM953" , 0x1180080901dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM954" , 0x1180080901dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM955" , 0x1180080901dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM956" , 0x1180080901de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM957" , 0x1180080901de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM958" , 0x1180080901df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM959" , 0x1180080901df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM960" , 0x1180080901e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM961" , 0x1180080901e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM962" , 0x1180080901e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM963" , 0x1180080901e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM964" , 0x1180080901e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM965" , 0x1180080901e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM966" , 0x1180080901e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM967" , 0x1180080901e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM968" , 0x1180080901e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM969" , 0x1180080901e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM970" , 0x1180080901e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM971" , 0x1180080901e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM972" , 0x1180080901e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM973" , 0x1180080901e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM974" , 0x1180080901e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM975" , 0x1180080901e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM976" , 0x1180080901e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM977" , 0x1180080901e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM978" , 0x1180080901e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM979" , 0x1180080901e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM980" , 0x1180080901ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM981" , 0x1180080901ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM982" , 0x1180080901eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM983" , 0x1180080901eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM984" , 0x1180080901ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM985" , 0x1180080901ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM986" , 0x1180080901ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM987" , 0x1180080901ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM988" , 0x1180080901ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM989" , 0x1180080901ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM990" , 0x1180080901ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM991" , 0x1180080901ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM992" , 0x1180080901f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM993" , 0x1180080901f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM994" , 0x1180080901f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM995" , 0x1180080901f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM996" , 0x1180080901f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM997" , 0x1180080901f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM998" , 0x1180080901f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM999" , 0x1180080901f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1000" , 0x1180080901f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1001" , 0x1180080901f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1002" , 0x1180080901f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1003" , 0x1180080901f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1004" , 0x1180080901f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1005" , 0x1180080901f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1006" , 0x1180080901f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1007" , 0x1180080901f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1008" , 0x1180080901f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1009" , 0x1180080901f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1010" , 0x1180080901f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1011" , 0x1180080901f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1012" , 0x1180080901fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1013" , 0x1180080901fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1014" , 0x1180080901fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1015" , 0x1180080901fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1016" , 0x1180080901fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1017" , 0x1180080901fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1018" , 0x1180080901fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1019" , 0x1180080901fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1020" , 0x1180080901fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1021" , 0x1180080901fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1022" , 0x1180080901ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_VRT_MEM1023" , 0x1180080901ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"L2C_WPAR_IOB0" , 0x1180080840200ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"L2C_WPAR_PP0" , 0x1180080840000ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"L2C_WPAR_PP1" , 0x1180080840008ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"L2C_WPAR_PP2" , 0x1180080840010ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"L2C_WPAR_PP3" , 0x1180080840018ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"L2C_WPAR_PP4" , 0x1180080840020ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"L2C_WPAR_PP5" , 0x1180080840028ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"L2C_WPAR_PP6" , 0x1180080840030ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"L2C_WPAR_PP7" , 0x1180080840038ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"L2C_WPAR_PP8" , 0x1180080840040ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"L2C_WPAR_PP9" , 0x1180080840048ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"L2C_XMC0_PFC" , 0x1180080800400ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"L2C_XMC_CMD" , 0x1180080800028ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"L2C_XMD0_PFC" , 0x1180080800408ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"LMC0_CHAR_CTL" , 0x1180088000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"LMC0_CHAR_MASK0" , 0x1180088000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"LMC0_CHAR_MASK1" , 0x1180088000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"LMC0_CHAR_MASK2" , 0x1180088000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"LMC0_CHAR_MASK3" , 0x1180088000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"LMC0_CHAR_MASK4" , 0x1180088000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"LMC0_COMP_CTL2" , 0x11800880001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"LMC0_CONFIG" , 0x1180088000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"LMC0_CONTROL" , 0x1180088000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"LMC0_DCLK_CNT" , 0x11800880001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"LMC0_DDR_PLL_CTL" , 0x1180088000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"LMC0_DIMM000_PARAMS" , 0x1180088000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"LMC0_DIMM001_PARAMS" , 0x1180088000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"LMC0_DIMM_CTL" , 0x1180088000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"LMC0_DLL_CTL2" , 0x11800880001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"LMC0_DLL_CTL3" , 0x1180088000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"LMC0_IFB_CNT" , 0x11800880001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
- {"LMC0_INT" , 0x11800880001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
- {"LMC0_INT_EN" , 0x11800880001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
- {"LMC0_MODEREG_PARAMS0" , 0x11800880001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
- {"LMC0_MODEREG_PARAMS1" , 0x1180088000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"LMC0_NXM" , 0x11800880000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"LMC0_OPS_CNT" , 0x11800880001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"LMC0_PHY_CTL" , 0x1180088000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"LMC0_RESET_CTL" , 0x1180088000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"LMC0_RLEVEL_CTL" , 0x11800880002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"LMC0_RLEVEL_DBG" , 0x11800880002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"LMC0_RLEVEL_RANK000" , 0x1180088000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"LMC0_RLEVEL_RANK001" , 0x1180088000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"LMC0_RLEVEL_RANK002" , 0x1180088000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"LMC0_RLEVEL_RANK003" , 0x1180088000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"LMC0_RODT_MASK" , 0x1180088000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"LMC0_SCRAMBLE_CFG0" , 0x1180088000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"LMC0_SCRAMBLE_CFG1" , 0x1180088000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"LMC0_SCRAMBLED_FADR" , 0x1180088000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"LMC0_SLOT_CTL0" , 0x11800880001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"LMC0_SLOT_CTL1" , 0x1180088000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"LMC0_SLOT_CTL2" , 0x1180088000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"LMC0_TIMING_PARAMS0" , 0x1180088000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"LMC0_TIMING_PARAMS1" , 0x11800880001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"LMC0_TRO_CTL" , 0x1180088000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"LMC0_TRO_STAT" , 0x1180088000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"LMC0_WLEVEL_CTL" , 0x1180088000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"LMC0_WLEVEL_DBG" , 0x1180088000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"LMC0_WLEVEL_RANK000" , 0x11800880002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"LMC0_WLEVEL_RANK001" , 0x11800880002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"LMC0_WLEVEL_RANK002" , 0x11800880002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"LMC0_WLEVEL_RANK003" , 0x11800880002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"LMC0_WODT_MASK" , 0x11800880001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"MIO_BOOT_PIN_DEFS" , 0x11800000000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"MIO_FUS_READ_TIMES" , 0x1180000001570ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"MIO_FUS_REPAIR_RES0" , 0x1180000001558ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"MIO_FUS_REPAIR_RES1" , 0x1180000001560ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"MIO_FUS_REPAIR_RES2" , 0x1180000001568ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"MIO_FUS_TGG" , 0x1180000001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"MIO_GPIO_COMP" , 0x11800000000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"MIO_NDF_DMA_CFG" , 0x1180000000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"MIO_NDF_DMA_INT" , 0x1180000000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"MIO_NDF_DMA_INT_EN" , 0x1180000000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"MIO_PTP_CKOUT_HI_INCR" , 0x1070000000f40ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
- {"MIO_PTP_CKOUT_LO_INCR" , 0x1070000000f48ull, CVMX_CSR_DB_TYPE_NCB, 64, 527},
- {"MIO_PTP_CKOUT_THRESH_HI" , 0x1070000000f38ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
- {"MIO_PTP_CKOUT_THRESH_LO" , 0x1070000000f30ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
- {"MIO_PTP_CLOCK_CFG" , 0x1070000000f00ull, CVMX_CSR_DB_TYPE_NCB, 64, 530},
- {"MIO_PTP_CLOCK_COMP" , 0x1070000000f18ull, CVMX_CSR_DB_TYPE_NCB, 64, 531},
- {"MIO_PTP_CLOCK_HI" , 0x1070000000f10ull, CVMX_CSR_DB_TYPE_NCB, 64, 532},
- {"MIO_PTP_CLOCK_LO" , 0x1070000000f08ull, CVMX_CSR_DB_TYPE_NCB, 64, 533},
- {"MIO_PTP_EVT_CNT" , 0x1070000000f28ull, CVMX_CSR_DB_TYPE_NCB, 64, 534},
- {"MIO_PTP_PPS_HI_INCR" , 0x1070000000f60ull, CVMX_CSR_DB_TYPE_NCB, 64, 535},
- {"MIO_PTP_PPS_LO_INCR" , 0x1070000000f68ull, CVMX_CSR_DB_TYPE_NCB, 64, 536},
- {"MIO_PTP_PPS_THRESH_HI" , 0x1070000000f58ull, CVMX_CSR_DB_TYPE_NCB, 64, 537},
- {"MIO_PTP_PPS_THRESH_LO" , 0x1070000000f50ull, CVMX_CSR_DB_TYPE_NCB, 64, 538},
- {"MIO_PTP_TIMESTAMP" , 0x1070000000f20ull, CVMX_CSR_DB_TYPE_NCB, 64, 539},
- {"MIO_QLM0_CFG" , 0x1180000001590ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"MIO_QLM1_CFG" , 0x1180000001598ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"MIO_QLM2_CFG" , 0x11800000015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"MIO_RST_BOOT" , 0x1180000001600ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"MIO_RST_CFG" , 0x1180000001610ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"MIO_RST_CKILL" , 0x1180000001638ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"MIO_RST_CNTL0" , 0x1180000001648ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"MIO_RST_CNTL1" , 0x1180000001650ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"MIO_RST_CNTL2" , 0x1180000001658ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"MIO_RST_CNTL3" , 0x1180000001660ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"MIO_RST_CTL0" , 0x1180000001618ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"MIO_RST_CTL1" , 0x1180000001620ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"MIO_RST_DELAY" , 0x1180000001608ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"MIO_RST_INT" , 0x1180000001628ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"MIO_RST_INT_EN" , 0x1180000001630ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 577},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 577},
- {"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 578},
- {"MIX1_BIST" , 0x1070000100878ull, CVMX_CSR_DB_TYPE_NCB, 64, 578},
- {"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 579},
- {"MIX1_CTL" , 0x1070000100820ull, CVMX_CSR_DB_TYPE_NCB, 64, 579},
- {"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 580},
- {"MIX1_INTENA" , 0x1070000100850ull, CVMX_CSR_DB_TYPE_NCB, 64, 580},
- {"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 581},
- {"MIX1_IRCNT" , 0x1070000100830ull, CVMX_CSR_DB_TYPE_NCB, 64, 581},
- {"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 582},
- {"MIX1_IRHWM" , 0x1070000100828ull, CVMX_CSR_DB_TYPE_NCB, 64, 582},
- {"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"MIX1_IRING1" , 0x1070000100810ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"MIX1_IRING2" , 0x1070000100818ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"MIX1_ISR" , 0x1070000100848ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 586},
- {"MIX1_ORCNT" , 0x1070000100840ull, CVMX_CSR_DB_TYPE_NCB, 64, 586},
- {"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 587},
- {"MIX1_ORHWM" , 0x1070000100838ull, CVMX_CSR_DB_TYPE_NCB, 64, 587},
- {"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"MIX1_ORING1" , 0x1070000100800ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"MIX1_ORING2" , 0x1070000100808ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"MIX1_REMCNT" , 0x1070000100858ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"MIX0_TSCTL" , 0x1070000100068ull, CVMX_CSR_DB_TYPE_NCB, 64, 591},
- {"MIX1_TSCTL" , 0x1070000100868ull, CVMX_CSR_DB_TYPE_NCB, 64, 591},
- {"MIX0_TSTAMP" , 0x1070000100060ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"MIX1_TSTAMP" , 0x1070000100860ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"MPI_CFG" , 0x1070000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"MPI_DAT0" , 0x1070000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"MPI_DAT1" , 0x1070000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"MPI_DAT2" , 0x1070000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"MPI_DAT3" , 0x1070000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"MPI_DAT4" , 0x10700000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"MPI_DAT5" , 0x10700000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"MPI_DAT6" , 0x10700000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"MPI_DAT7" , 0x10700000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"MPI_DAT8" , 0x10700000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"MPI_STS" , 0x1070000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 595},
- {"MPI_TX" , 0x1070000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 596},
- {"NDF_BT_PG_INFO" , 0x1070001000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
- {"NDF_CMD" , 0x1070001000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 598},
- {"NDF_DRBELL" , 0x1070001000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 599},
- {"NDF_ECC_CNT" , 0x1070001000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 600},
- {"NDF_INT" , 0x1070001000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 601},
- {"NDF_INT_EN" , 0x1070001000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 602},
- {"NDF_MISC" , 0x1070001000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 603},
- {"NDF_ST_REG" , 0x1070001000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 604},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 605},
- {"PCIEEP1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 605},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 606},
- {"PCIEEP1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 606},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 607},
- {"PCIEEP1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 607},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 608},
- {"PCIEEP1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 608},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 609},
- {"PCIEEP1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 609},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 610},
- {"PCIEEP1_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 610},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 611},
- {"PCIEEP1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 611},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 612},
- {"PCIEEP1_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 612},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 613},
- {"PCIEEP1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 613},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 614},
- {"PCIEEP1_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 614},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 615},
- {"PCIEEP1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 615},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 616},
- {"PCIEEP1_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 616},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 617},
- {"PCIEEP1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 617},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 618},
- {"PCIEEP1_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 618},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 619},
- {"PCIEEP1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 619},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 620},
- {"PCIEEP1_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 620},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 621},
- {"PCIEEP1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 621},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 622},
- {"PCIEEP1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 622},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 623},
- {"PCIEEP1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 623},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 624},
- {"PCIEEP1_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 624},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 625},
- {"PCIEEP1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 625},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 626},
- {"PCIEEP1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 626},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 627},
- {"PCIEEP1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 627},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 628},
- {"PCIEEP1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 628},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 629},
- {"PCIEEP1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 629},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 630},
- {"PCIEEP1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 630},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 631},
- {"PCIEEP1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 631},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 632},
- {"PCIEEP1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 632},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 633},
- {"PCIEEP1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 633},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 634},
- {"PCIEEP1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 634},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 635},
- {"PCIEEP1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 635},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 636},
- {"PCIEEP1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 636},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 637},
- {"PCIEEP1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 637},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 638},
- {"PCIEEP1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 638},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 639},
- {"PCIEEP1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 639},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 640},
- {"PCIEEP1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 640},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 641},
- {"PCIEEP1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 641},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 642},
- {"PCIEEP1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 642},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 643},
- {"PCIEEP1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 643},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 644},
- {"PCIEEP1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 644},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 645},
- {"PCIEEP1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 645},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 646},
- {"PCIEEP1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 646},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 647},
- {"PCIEEP1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 647},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 648},
- {"PCIEEP1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 648},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 649},
- {"PCIEEP1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 649},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 650},
- {"PCIEEP1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 650},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 651},
- {"PCIEEP1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 651},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 652},
- {"PCIEEP1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 652},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 653},
- {"PCIEEP1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 653},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 654},
- {"PCIEEP1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 654},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 655},
- {"PCIEEP1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 655},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 656},
- {"PCIEEP1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 656},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 657},
- {"PCIEEP1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 657},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 658},
- {"PCIEEP1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 658},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 659},
- {"PCIEEP1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 659},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 660},
- {"PCIEEP1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 660},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 661},
- {"PCIEEP1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 661},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 662},
- {"PCIEEP1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 662},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 663},
- {"PCIEEP1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 663},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 664},
- {"PCIEEP1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 664},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 665},
- {"PCIEEP1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 665},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 666},
- {"PCIEEP1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 666},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 667},
- {"PCIEEP1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 667},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 668},
- {"PCIEEP1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 668},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 669},
- {"PCIEEP1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 669},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 670},
- {"PCIEEP1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 670},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 671},
- {"PCIEEP1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 671},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 672},
- {"PCIEEP1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 672},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 673},
- {"PCIEEP1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 673},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 674},
- {"PCIEEP1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 674},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 675},
- {"PCIEEP1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 675},
- {"PCIEEP0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 676},
- {"PCIEEP1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 676},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 677},
- {"PCIEEP1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 677},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 678},
- {"PCIEEP1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 678},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 694},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 694},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 695},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 695},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 696},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 696},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 697},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 697},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 698},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 698},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 699},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 699},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 700},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 700},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 701},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 701},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 702},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 702},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 703},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 703},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 704},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 704},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 705},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 705},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 706},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 706},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 707},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 707},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 708},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 708},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 709},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 709},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 710},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 710},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 711},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 711},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 712},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 712},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 713},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 713},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 714},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 714},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 715},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 715},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 716},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 716},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 717},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 717},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 718},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 718},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 719},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 719},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 720},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 720},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 721},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 721},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 722},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 722},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 723},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 723},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 724},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 724},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 725},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 725},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 726},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 726},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 727},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 727},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 728},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 728},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 729},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 729},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 730},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 730},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 731},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 731},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 732},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 732},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 733},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 733},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 734},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 734},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 735},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 735},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 736},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 736},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 737},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 737},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 738},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 738},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 739},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 739},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 740},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 740},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 741},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 741},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 742},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 742},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 743},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 743},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 744},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 744},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 745},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 745},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 746},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 746},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 747},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 747},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 748},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 748},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 749},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 749},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 750},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 750},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 751},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 751},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 752},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 752},
- {"PCIERC0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 753},
- {"PCIERC1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 753},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 754},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 754},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 755},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 755},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PCS0_AN002_ADV_REG" , 0x11800b0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PCS0_AN003_ADV_REG" , 0x11800b0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PCS1_AN000_ADV_REG" , 0x11800b8001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PCS1_AN001_ADV_REG" , 0x11800b8001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PCS1_AN002_ADV_REG" , 0x11800b8001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PCS1_AN003_ADV_REG" , 0x11800b8001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PCS0_AN002_EXT_ST_REG" , 0x11800b0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PCS0_AN003_EXT_ST_REG" , 0x11800b0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PCS1_AN000_EXT_ST_REG" , 0x11800b8001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PCS1_AN001_EXT_ST_REG" , 0x11800b8001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PCS1_AN002_EXT_ST_REG" , 0x11800b8001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PCS1_AN003_EXT_ST_REG" , 0x11800b8001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PCS0_AN002_LP_ABIL_REG" , 0x11800b0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PCS0_AN003_LP_ABIL_REG" , 0x11800b0001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PCS1_AN000_LP_ABIL_REG" , 0x11800b8001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PCS1_AN001_LP_ABIL_REG" , 0x11800b8001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PCS1_AN002_LP_ABIL_REG" , 0x11800b8001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PCS1_AN003_LP_ABIL_REG" , 0x11800b8001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS0_AN002_RESULTS_REG" , 0x11800b0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS0_AN003_RESULTS_REG" , 0x11800b0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS1_AN000_RESULTS_REG" , 0x11800b8001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS1_AN001_RESULTS_REG" , 0x11800b8001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS1_AN002_RESULTS_REG" , 0x11800b8001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS1_AN003_RESULTS_REG" , 0x11800b8001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS0_INT002_EN_REG" , 0x11800b0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS0_INT003_EN_REG" , 0x11800b0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS1_INT000_EN_REG" , 0x11800b8001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS1_INT001_EN_REG" , 0x11800b8001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS1_INT002_EN_REG" , 0x11800b8001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS1_INT003_EN_REG" , 0x11800b8001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS0_INT002_REG" , 0x11800b0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS0_INT003_REG" , 0x11800b0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS1_INT000_REG" , 0x11800b8001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS1_INT001_REG" , 0x11800b8001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS1_INT002_REG" , 0x11800b8001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS1_INT003_REG" , 0x11800b8001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS0_LINK002_TIMER_COUNT_REG", 0x11800b0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS0_LINK003_TIMER_COUNT_REG", 0x11800b0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS1_LINK000_TIMER_COUNT_REG", 0x11800b8001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS1_LINK001_TIMER_COUNT_REG", 0x11800b8001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS1_LINK002_TIMER_COUNT_REG", 0x11800b8001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS1_LINK003_TIMER_COUNT_REG", 0x11800b8001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS0_LOG_ANL002_REG" , 0x11800b0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS0_LOG_ANL003_REG" , 0x11800b0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS1_LOG_ANL000_REG" , 0x11800b8001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS1_LOG_ANL001_REG" , 0x11800b8001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS1_LOG_ANL002_REG" , 0x11800b8001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS1_LOG_ANL003_REG" , 0x11800b8001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS0_MISC002_CTL_REG" , 0x11800b0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS0_MISC003_CTL_REG" , 0x11800b0001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS1_MISC000_CTL_REG" , 0x11800b8001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS1_MISC001_CTL_REG" , 0x11800b8001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS1_MISC002_CTL_REG" , 0x11800b8001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS1_MISC003_CTL_REG" , 0x11800b8001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS0_MR002_CONTROL_REG" , 0x11800b0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS0_MR003_CONTROL_REG" , 0x11800b0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS1_MR000_CONTROL_REG" , 0x11800b8001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS1_MR001_CONTROL_REG" , 0x11800b8001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS1_MR002_CONTROL_REG" , 0x11800b8001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS1_MR003_CONTROL_REG" , 0x11800b8001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS0_MR002_STATUS_REG" , 0x11800b0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS0_MR003_STATUS_REG" , 0x11800b0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS1_MR000_STATUS_REG" , 0x11800b8001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS1_MR001_STATUS_REG" , 0x11800b8001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS1_MR002_STATUS_REG" , 0x11800b8001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS1_MR003_STATUS_REG" , 0x11800b8001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS0_RX002_STATES_REG" , 0x11800b0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS0_RX003_STATES_REG" , 0x11800b0001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS1_RX000_STATES_REG" , 0x11800b8001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS1_RX001_STATES_REG" , 0x11800b8001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS1_RX002_STATES_REG" , 0x11800b8001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS1_RX003_STATES_REG" , 0x11800b8001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS0_RX002_SYNC_REG" , 0x11800b0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS0_RX003_SYNC_REG" , 0x11800b0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS1_RX000_SYNC_REG" , 0x11800b8001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS1_RX001_SYNC_REG" , 0x11800b8001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS1_RX002_SYNC_REG" , 0x11800b8001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS1_RX003_SYNC_REG" , 0x11800b8001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS0_SGM002_AN_ADV_REG" , 0x11800b0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS0_SGM003_AN_ADV_REG" , 0x11800b0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS1_SGM000_AN_ADV_REG" , 0x11800b8001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS1_SGM001_AN_ADV_REG" , 0x11800b8001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS1_SGM002_AN_ADV_REG" , 0x11800b8001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS1_SGM003_AN_ADV_REG" , 0x11800b8001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS0_SGM002_LP_ADV_REG" , 0x11800b0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS0_SGM003_LP_ADV_REG" , 0x11800b0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS1_SGM000_LP_ADV_REG" , 0x11800b8001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS1_SGM001_LP_ADV_REG" , 0x11800b8001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS1_SGM002_LP_ADV_REG" , 0x11800b8001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS1_SGM003_LP_ADV_REG" , 0x11800b8001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS0_TX002_STATES_REG" , 0x11800b0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS0_TX003_STATES_REG" , 0x11800b0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS1_TX000_STATES_REG" , 0x11800b8001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS1_TX001_STATES_REG" , 0x11800b8001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS1_TX002_STATES_REG" , 0x11800b8001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS1_TX003_STATES_REG" , 0x11800b8001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS0_TX_RX002_POLARITY_REG" , 0x11800b0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS0_TX_RX003_POLARITY_REG" , 0x11800b0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS1_TX_RX000_POLARITY_REG" , 0x11800b8001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS1_TX_RX001_POLARITY_REG" , 0x11800b8001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS1_TX_RX002_POLARITY_REG" , 0x11800b8001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCS1_TX_RX003_POLARITY_REG" , 0x11800b8001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"PCSX0_10GBX_STATUS_REG" , 0x11800b0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PCSX1_10GBX_STATUS_REG" , 0x11800b8000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"PCSX0_BIST_STATUS_REG" , 0x11800b0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PCSX1_BIST_STATUS_REG" , 0x11800b8000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800b0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PCSX1_BIT_LOCK_STATUS_REG" , 0x11800b8000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"PCSX0_CONTROL1_REG" , 0x11800b0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PCSX1_CONTROL1_REG" , 0x11800b8000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"PCSX0_CONTROL2_REG" , 0x11800b0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PCSX1_CONTROL2_REG" , 0x11800b8000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"PCSX0_INT_EN_REG" , 0x11800b0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PCSX1_INT_EN_REG" , 0x11800b8000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"PCSX0_INT_REG" , 0x11800b0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PCSX1_INT_REG" , 0x11800b8000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"PCSX0_LOG_ANL_REG" , 0x11800b0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PCSX1_LOG_ANL_REG" , 0x11800b8000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
- {"PCSX0_MISC_CTL_REG" , 0x11800b0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PCSX1_MISC_CTL_REG" , 0x11800b8000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
- {"PCSX0_RX_SYNC_STATES_REG" , 0x11800b0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PCSX1_RX_SYNC_STATES_REG" , 0x11800b8000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
- {"PCSX0_SPD_ABIL_REG" , 0x11800b0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PCSX1_SPD_ABIL_REG" , 0x11800b8000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
- {"PCSX0_STATUS1_REG" , 0x11800b0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PCSX1_STATUS1_REG" , 0x11800b8000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
- {"PCSX0_STATUS2_REG" , 0x11800b0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PCSX1_STATUS2_REG" , 0x11800b8000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
- {"PCSX0_TX_RX_POLARITY_REG" , 0x11800b0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PCSX1_TX_RX_POLARITY_REG" , 0x11800b8000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
- {"PCSX0_TX_RX_STATES_REG" , 0x11800b0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PCSX1_TX_RX_STATES_REG" , 0x11800b8000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
- {"PEM0_BAR1_INDEX000" , 0x11800c00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX001" , 0x11800c00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX002" , 0x11800c00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX003" , 0x11800c00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX004" , 0x11800c00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX005" , 0x11800c00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX006" , 0x11800c00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX007" , 0x11800c00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX008" , 0x11800c00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX009" , 0x11800c00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX010" , 0x11800c00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX011" , 0x11800c0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX012" , 0x11800c0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX013" , 0x11800c0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX014" , 0x11800c0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR1_INDEX015" , 0x11800c0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX000" , 0x11800c10000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX001" , 0x11800c10000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX002" , 0x11800c10000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX003" , 0x11800c10000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX004" , 0x11800c10000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX005" , 0x11800c10000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX006" , 0x11800c10000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX007" , 0x11800c10000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX008" , 0x11800c10000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX009" , 0x11800c10000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX010" , 0x11800c10000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX011" , 0x11800c1000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX012" , 0x11800c1000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX013" , 0x11800c1000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX014" , 0x11800c1000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM1_BAR1_INDEX015" , 0x11800c1000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
- {"PEM0_BAR2_MASK" , 0x11800c0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PEM1_BAR2_MASK" , 0x11800c1000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
- {"PEM0_BAR_CTL" , 0x11800c0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PEM1_BAR_CTL" , 0x11800c1000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
- {"PEM0_BIST_STATUS" , 0x11800c0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM1_BIST_STATUS" , 0x11800c1000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
- {"PEM0_BIST_STATUS2" , 0x11800c0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PEM1_BIST_STATUS2" , 0x11800c1000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
- {"PEM0_CFG_RD" , 0x11800c0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PEM1_CFG_RD" , 0x11800c1000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
- {"PEM0_CFG_WR" , 0x11800c0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PEM1_CFG_WR" , 0x11800c1000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
- {"PEM0_CPL_LUT_VALID" , 0x11800c0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PEM1_CPL_LUT_VALID" , 0x11800c1000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
- {"PEM0_CTL_STATUS" , 0x11800c0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PEM1_CTL_STATUS" , 0x11800c1000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
- {"PEM0_DBG_INFO" , 0x11800c0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PEM1_DBG_INFO" , 0x11800c1000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
- {"PEM0_DBG_INFO_EN" , 0x11800c00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PEM1_DBG_INFO_EN" , 0x11800c10000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
- {"PEM0_DIAG_STATUS" , 0x11800c0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PEM1_DIAG_STATUS" , 0x11800c1000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
- {"PEM0_INB_READ_CREDITS" , 0x11800c0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PEM1_INB_READ_CREDITS" , 0x11800c1000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
- {"PEM0_INT_ENB" , 0x11800c0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PEM1_INT_ENB" , 0x11800c1000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
- {"PEM0_INT_ENB_INT" , 0x11800c0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"PEM1_INT_ENB_INT" , 0x11800c1000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
- {"PEM0_INT_SUM" , 0x11800c0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"PEM1_INT_SUM" , 0x11800c1000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
- {"PEM0_P2N_BAR0_START" , 0x11800c0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"PEM1_P2N_BAR0_START" , 0x11800c1000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
- {"PEM0_P2N_BAR1_START" , 0x11800c0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"PEM1_P2N_BAR1_START" , 0x11800c1000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
- {"PEM0_P2N_BAR2_START" , 0x11800c0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"PEM1_P2N_BAR2_START" , 0x11800c1000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
- {"PEM0_P2P_BAR000_END" , 0x11800c0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PEM0_P2P_BAR001_END" , 0x11800c0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PEM0_P2P_BAR002_END" , 0x11800c0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PEM0_P2P_BAR003_END" , 0x11800c0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PEM1_P2P_BAR000_END" , 0x11800c1000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PEM1_P2P_BAR001_END" , 0x11800c1000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PEM1_P2P_BAR002_END" , 0x11800c1000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PEM1_P2P_BAR003_END" , 0x11800c1000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
- {"PEM0_P2P_BAR000_START" , 0x11800c0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PEM0_P2P_BAR001_START" , 0x11800c0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PEM0_P2P_BAR002_START" , 0x11800c0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PEM0_P2P_BAR003_START" , 0x11800c0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PEM1_P2P_BAR000_START" , 0x11800c1000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PEM1_P2P_BAR001_START" , 0x11800c1000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PEM1_P2P_BAR002_START" , 0x11800c1000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PEM1_P2P_BAR003_START" , 0x11800c1000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
- {"PEM0_TLP_CREDITS" , 0x11800c0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"PEM1_TLP_CREDITS" , 0x11800c1000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
- {"PIP_ALT_SKIP_CFG0" , 0x11800a0002a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"PIP_ALT_SKIP_CFG1" , 0x11800a0002a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"PIP_ALT_SKIP_CFG2" , 0x11800a0002a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"PIP_ALT_SKIP_CFG3" , 0x11800a0002a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 812},
- {"PIP_CLKEN" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 813},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
- {"PIP_DSA_SRC_GRP" , 0x11800a0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
- {"PIP_DSA_VID_GRP" , 0x11800a0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 817},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 819},
- {"PIP_HG_PRI_QOS" , 0x11800a00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 820},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 821},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 822},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 823},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG16" , 0x11800a0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG17" , 0x11800a0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG18" , 0x11800a0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG19" , 0x11800a0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG40" , 0x11800a0000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG41" , 0x11800a0000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG44" , 0x11800a0000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG45" , 0x11800a0000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG46" , 0x11800a0000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFG47" , 0x11800a0000378ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
- {"PIP_PRT_CFGB0" , 0x11800a0008000ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB1" , 0x11800a0008008ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB2" , 0x11800a0008010ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB3" , 0x11800a0008018ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB16" , 0x11800a0008080ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB17" , 0x11800a0008088ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB18" , 0x11800a0008090ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB19" , 0x11800a0008098ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB32" , 0x11800a0008100ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB33" , 0x11800a0008108ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB34" , 0x11800a0008110ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB35" , 0x11800a0008118ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB36" , 0x11800a0008120ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB37" , 0x11800a0008128ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB38" , 0x11800a0008130ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB39" , 0x11800a0008138ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB40" , 0x11800a0008140ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB41" , 0x11800a0008148ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB42" , 0x11800a0008150ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB43" , 0x11800a0008158ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB44" , 0x11800a0008160ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB45" , 0x11800a0008168ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB46" , 0x11800a0008170ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_CFGB47" , 0x11800a0008178ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG16" , 0x11800a0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG17" , 0x11800a0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG18" , 0x11800a0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG19" , 0x11800a0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG40" , 0x11800a0000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG41" , 0x11800a0000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG44" , 0x11800a0000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG45" , 0x11800a0000568ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG46" , 0x11800a0000570ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_PRT_TAG47" , 0x11800a0000578ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT2" , 0x11800a00008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT3" , 0x11800a00008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT16" , 0x11800a0000d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT17" , 0x11800a0000d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT18" , 0x11800a0000da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT19" , 0x11800a0000df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT36" , 0x11800a0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT37" , 0x11800a0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT38" , 0x11800a00013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT0_PRT39" , 0x11800a0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
- {"PIP_STAT10_PRT0" , 0x11800a0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT1" , 0x11800a0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT2" , 0x11800a00014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT3" , 0x11800a00014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT16" , 0x11800a0001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT17" , 0x11800a0001590ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT18" , 0x11800a00015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT19" , 0x11800a00015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT32" , 0x11800a0001680ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT33" , 0x11800a0001690ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT34" , 0x11800a00016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT35" , 0x11800a00016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT36" , 0x11800a00016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT37" , 0x11800a00016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT38" , 0x11800a00016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT10_PRT39" , 0x11800a00016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
- {"PIP_STAT11_PRT0" , 0x11800a0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT1" , 0x11800a0001498ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT2" , 0x11800a00014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT3" , 0x11800a00014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT16" , 0x11800a0001588ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT17" , 0x11800a0001598ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT18" , 0x11800a00015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT19" , 0x11800a00015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT32" , 0x11800a0001688ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT33" , 0x11800a0001698ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT34" , 0x11800a00016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT35" , 0x11800a00016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT36" , 0x11800a00016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT37" , 0x11800a00016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT38" , 0x11800a00016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT11_PRT39" , 0x11800a00016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT2" , 0x11800a00008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT3" , 0x11800a00008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT16" , 0x11800a0000d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT17" , 0x11800a0000d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT18" , 0x11800a0000da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT19" , 0x11800a0000df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT36" , 0x11800a0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT37" , 0x11800a0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT38" , 0x11800a00013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT1_PRT39" , 0x11800a0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT2" , 0x11800a00008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT3" , 0x11800a0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT16" , 0x11800a0000d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT17" , 0x11800a0000d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT18" , 0x11800a0000db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT19" , 0x11800a0000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT36" , 0x11800a0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT37" , 0x11800a00013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT38" , 0x11800a00013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT2_PRT39" , 0x11800a0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT2" , 0x11800a00008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT3" , 0x11800a0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT16" , 0x11800a0000d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT17" , 0x11800a0000d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT18" , 0x11800a0000db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT19" , 0x11800a0000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT36" , 0x11800a0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT37" , 0x11800a00013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT38" , 0x11800a00013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT3_PRT39" , 0x11800a0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT2" , 0x11800a00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT3" , 0x11800a0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT16" , 0x11800a0000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT17" , 0x11800a0000d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT18" , 0x11800a0000dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT19" , 0x11800a0000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT36" , 0x11800a0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT37" , 0x11800a00013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT38" , 0x11800a0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT4_PRT39" , 0x11800a0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT2" , 0x11800a00008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT3" , 0x11800a0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT16" , 0x11800a0000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT17" , 0x11800a0000d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT18" , 0x11800a0000dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT19" , 0x11800a0000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT36" , 0x11800a0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT37" , 0x11800a00013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT38" , 0x11800a0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT5_PRT39" , 0x11800a0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT2" , 0x11800a00008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT3" , 0x11800a0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT16" , 0x11800a0000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT17" , 0x11800a0000d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT18" , 0x11800a0000dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT19" , 0x11800a0000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT36" , 0x11800a0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT37" , 0x11800a00013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT38" , 0x11800a0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT6_PRT39" , 0x11800a0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT2" , 0x11800a00008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT3" , 0x11800a0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT16" , 0x11800a0000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT17" , 0x11800a0000d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT18" , 0x11800a0000dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT19" , 0x11800a0000e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT36" , 0x11800a0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT37" , 0x11800a00013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT38" , 0x11800a0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT7_PRT39" , 0x11800a0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT2" , 0x11800a00008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT3" , 0x11800a0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT16" , 0x11800a0000d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT17" , 0x11800a0000d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT18" , 0x11800a0000de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT19" , 0x11800a0000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT36" , 0x11800a0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT37" , 0x11800a00013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT38" , 0x11800a0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT8_PRT39" , 0x11800a0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT2" , 0x11800a00008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT3" , 0x11800a0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT16" , 0x11800a0000d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT17" , 0x11800a0000d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT18" , 0x11800a0000de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT19" , 0x11800a0000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT36" , 0x11800a0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT37" , 0x11800a00013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT38" , 0x11800a0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT9_PRT39" , 0x11800a0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS2" , 0x11800a0001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS3" , 0x11800a0001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS16" , 0x11800a0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS17" , 0x11800a0001c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS18" , 0x11800a0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS19" , 0x11800a0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS36" , 0x11800a0001e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS37" , 0x11800a0001eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS38" , 0x11800a0001ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS39" , 0x11800a0001ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS40" , 0x11800a0001f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS41" , 0x11800a0001f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS44" , 0x11800a0001f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS45" , 0x11800a0001fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS46" , 0x11800a0001fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_ERRS47" , 0x11800a0001ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS2" , 0x11800a0001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS3" , 0x11800a0001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS16" , 0x11800a0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS17" , 0x11800a0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS18" , 0x11800a0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS19" , 0x11800a0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS36" , 0x11800a0001e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS37" , 0x11800a0001ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS38" , 0x11800a0001ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS39" , 0x11800a0001ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS40" , 0x11800a0001f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS41" , 0x11800a0001f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS44" , 0x11800a0001f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS45" , 0x11800a0001fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS46" , 0x11800a0001fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_OCTS47" , 0x11800a0001fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS2" , 0x11800a0001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS3" , 0x11800a0001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS16" , 0x11800a0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS17" , 0x11800a0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS18" , 0x11800a0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS19" , 0x11800a0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS36" , 0x11800a0001e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS37" , 0x11800a0001ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS38" , 0x11800a0001ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS39" , 0x11800a0001ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS40" , 0x11800a0001f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS41" , 0x11800a0001f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS44" , 0x11800a0001f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS45" , 0x11800a0001fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS46" , 0x11800a0001fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_STAT_INB_PKTS47" , 0x11800a0001fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
- {"PIP_VLAN_ETYPES0" , 0x11800a00001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_VLAN_ETYPES1" , 0x11800a00001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
- {"PIP_XSTAT0_PRT40" , 0x11800a0002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
- {"PIP_XSTAT0_PRT41" , 0x11800a0002050ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
- {"PIP_XSTAT0_PRT44" , 0x11800a0002140ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
- {"PIP_XSTAT0_PRT45" , 0x11800a0002190ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
- {"PIP_XSTAT0_PRT46" , 0x11800a00021e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
- {"PIP_XSTAT0_PRT47" , 0x11800a0002230ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
- {"PIP_XSTAT10_PRT40" , 0x11800a0001700ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
- {"PIP_XSTAT10_PRT41" , 0x11800a0001710ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
- {"PIP_XSTAT10_PRT44" , 0x11800a0001740ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
- {"PIP_XSTAT10_PRT45" , 0x11800a0001750ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
- {"PIP_XSTAT10_PRT46" , 0x11800a0001760ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
- {"PIP_XSTAT10_PRT47" , 0x11800a0001770ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
- {"PIP_XSTAT11_PRT40" , 0x11800a0001708ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"PIP_XSTAT11_PRT41" , 0x11800a0001718ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"PIP_XSTAT11_PRT44" , 0x11800a0001748ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"PIP_XSTAT11_PRT45" , 0x11800a0001758ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"PIP_XSTAT11_PRT46" , 0x11800a0001768ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"PIP_XSTAT11_PRT47" , 0x11800a0001778ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"PIP_XSTAT1_PRT40" , 0x11800a0002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"PIP_XSTAT1_PRT41" , 0x11800a0002058ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"PIP_XSTAT1_PRT44" , 0x11800a0002148ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"PIP_XSTAT1_PRT45" , 0x11800a0002198ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"PIP_XSTAT1_PRT46" , 0x11800a00021e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"PIP_XSTAT1_PRT47" , 0x11800a0002238ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"PIP_XSTAT2_PRT40" , 0x11800a0002010ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"PIP_XSTAT2_PRT41" , 0x11800a0002060ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"PIP_XSTAT2_PRT44" , 0x11800a0002150ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"PIP_XSTAT2_PRT45" , 0x11800a00021a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"PIP_XSTAT2_PRT46" , 0x11800a00021f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"PIP_XSTAT2_PRT47" , 0x11800a0002240ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"PIP_XSTAT3_PRT40" , 0x11800a0002018ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"PIP_XSTAT3_PRT41" , 0x11800a0002068ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"PIP_XSTAT3_PRT44" , 0x11800a0002158ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"PIP_XSTAT3_PRT45" , 0x11800a00021a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"PIP_XSTAT3_PRT46" , 0x11800a00021f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"PIP_XSTAT3_PRT47" , 0x11800a0002248ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"PIP_XSTAT4_PRT40" , 0x11800a0002020ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"PIP_XSTAT4_PRT41" , 0x11800a0002070ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"PIP_XSTAT4_PRT44" , 0x11800a0002160ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"PIP_XSTAT4_PRT45" , 0x11800a00021b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"PIP_XSTAT4_PRT46" , 0x11800a0002200ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"PIP_XSTAT4_PRT47" , 0x11800a0002250ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"PIP_XSTAT5_PRT40" , 0x11800a0002028ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"PIP_XSTAT5_PRT41" , 0x11800a0002078ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"PIP_XSTAT5_PRT44" , 0x11800a0002168ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"PIP_XSTAT5_PRT45" , 0x11800a00021b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"PIP_XSTAT5_PRT46" , 0x11800a0002208ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"PIP_XSTAT5_PRT47" , 0x11800a0002258ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"PIP_XSTAT6_PRT40" , 0x11800a0002030ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"PIP_XSTAT6_PRT41" , 0x11800a0002080ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"PIP_XSTAT6_PRT44" , 0x11800a0002170ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"PIP_XSTAT6_PRT45" , 0x11800a00021c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"PIP_XSTAT6_PRT46" , 0x11800a0002210ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"PIP_XSTAT6_PRT47" , 0x11800a0002260ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"PIP_XSTAT7_PRT40" , 0x11800a0002038ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"PIP_XSTAT7_PRT41" , 0x11800a0002088ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"PIP_XSTAT7_PRT44" , 0x11800a0002178ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"PIP_XSTAT7_PRT45" , 0x11800a00021c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"PIP_XSTAT7_PRT46" , 0x11800a0002218ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"PIP_XSTAT7_PRT47" , 0x11800a0002268ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"PIP_XSTAT8_PRT40" , 0x11800a0002040ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"PIP_XSTAT8_PRT41" , 0x11800a0002090ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"PIP_XSTAT8_PRT44" , 0x11800a0002180ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"PIP_XSTAT8_PRT45" , 0x11800a00021d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"PIP_XSTAT8_PRT46" , 0x11800a0002220ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"PIP_XSTAT8_PRT47" , 0x11800a0002270ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"PIP_XSTAT9_PRT40" , 0x11800a0002048ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"PIP_XSTAT9_PRT41" , 0x11800a0002098ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"PIP_XSTAT9_PRT44" , 0x11800a0002188ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"PIP_XSTAT9_PRT45" , 0x11800a00021d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"PIP_XSTAT9_PRT46" , 0x11800a0002228ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"PIP_XSTAT9_PRT47" , 0x11800a0002278ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 865},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 869},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 870},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 871},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 874},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 875},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 876},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 877},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 878},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 879},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 880},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
- {"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
- {"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 883},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 884},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 885},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 886},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 887},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 888},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 889},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 890},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 891},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 893},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 894},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 898},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 899},
- {"PKO_REG_PREEMPT" , 0x1180050000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 900},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 901},
- {"PKO_REG_QUEUE_PREEMPT" , 0x1180050000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 902},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 903},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 904},
- {"PKO_REG_TIMESTAMP" , 0x1180050000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 905},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 906},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 907},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 908},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 909},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 910},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 911},
- {"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 912},
- {"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 913},
- {"POW_IQ_THR0" , 0x16700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 914},
- {"POW_IQ_THR1" , 0x16700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 914},
- {"POW_IQ_THR2" , 0x16700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 914},
- {"POW_IQ_THR3" , 0x16700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 914},
- {"POW_IQ_THR4" , 0x16700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 914},
- {"POW_IQ_THR5" , 0x16700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 914},
- {"POW_IQ_THR6" , 0x16700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 914},
- {"POW_IQ_THR7" , 0x16700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 914},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 915},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 916},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 917},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 918},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 919},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 920},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 921},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 922},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 923},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 923},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 923},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 923},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 923},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 923},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 923},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 923},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 924},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 925},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 926},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 927},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 928},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 929},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 934},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 935},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 936},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 937},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 938},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"RNM_EER_DBG" , 0x1180040000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"RNM_EER_KEY" , 0x1180040000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"RNM_SERIAL_NUM" , 0x1180040000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"SLI_BIST_STATUS" , 0x11f0000010580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 957},
- {"SLI_CTL_PORT0" , 0x11f0000010050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 958},
- {"SLI_CTL_PORT1" , 0x11f0000010060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 958},
- {"SLI_CTL_PORT2" , 0x11f0000010070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 958},
- {"SLI_CTL_PORT3" , 0x11f0000010080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 958},
- {"SLI_CTL_STATUS" , 0x11f0000010570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 959},
- {"SLI_DATA_OUT_CNT" , 0x11f00000105f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 960},
- {"SLI_DBG_DATA" , 0x11f0000010310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 961},
- {"SLI_DBG_SELECT" , 0x11f0000010300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 962},
- {"SLI_DMA0_CNT" , 0x11f0000010400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 963},
- {"SLI_DMA1_CNT" , 0x11f0000010410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 963},
- {"SLI_DMA0_INT_LEVEL" , 0x11f00000103e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 964},
- {"SLI_DMA1_INT_LEVEL" , 0x11f00000103f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 964},
- {"SLI_DMA0_TIM" , 0x11f0000010420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 965},
- {"SLI_DMA1_TIM" , 0x11f0000010430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 965},
- {"SLI_INT_ENB_CIU" , 0x11f0000013cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 966},
- {"SLI_INT_ENB_PORT0" , 0x11f0000010340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 967},
- {"SLI_INT_ENB_PORT1" , 0x11f0000010350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 967},
- {"SLI_INT_SUM" , 0x11f0000010330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 968},
- {"SLI_LAST_WIN_RDATA0" , 0x11f0000010600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969},
- {"SLI_LAST_WIN_RDATA1" , 0x11f0000010610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 970},
- {"SLI_LAST_WIN_RDATA2" , 0x11f00000106c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 971},
- {"SLI_LAST_WIN_RDATA3" , 0x11f00000106d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 972},
- {"SLI_MAC_CREDIT_CNT" , 0x11f0000013d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 973},
- {"SLI_MAC_CREDIT_CNT2" , 0x11f0000013e10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 974},
- {"SLI_MAC_NUMBER" , 0x3e00ull, CVMX_CSR_DB_TYPE_PEXP, 64, 975},
- {"SLI_MEM_ACCESS_CTL" , 0x11f00000102f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 976},
- {"SLI_MEM_ACCESS_SUBID12" , 0x11f00000100e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID13" , 0x11f00000100f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID14" , 0x11f0000010100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID15" , 0x11f0000010110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID16" , 0x11f0000010120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID17" , 0x11f0000010130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID18" , 0x11f0000010140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID19" , 0x11f0000010150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID20" , 0x11f0000010160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID21" , 0x11f0000010170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID22" , 0x11f0000010180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID23" , 0x11f0000010190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID24" , 0x11f00000101a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID25" , 0x11f00000101b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID26" , 0x11f00000101c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MEM_ACCESS_SUBID27" , 0x11f00000101d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977},
- {"SLI_MSI_ENB0" , 0x11f0000013c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 978},
- {"SLI_MSI_ENB1" , 0x11f0000013c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 979},
- {"SLI_MSI_ENB2" , 0x11f0000013c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 980},
- {"SLI_MSI_ENB3" , 0x11f0000013c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 981},
- {"SLI_MSI_RCV0" , 0x11f0000013c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 982},
- {"SLI_MSI_RCV1" , 0x11f0000013c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 983},
- {"SLI_MSI_RCV2" , 0x11f0000013c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 984},
- {"SLI_MSI_RCV3" , 0x11f0000013c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 985},
- {"SLI_MSI_RD_MAP" , 0x11f0000013ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 986},
- {"SLI_MSI_W1C_ENB0" , 0x11f0000013cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 987},
- {"SLI_MSI_W1C_ENB1" , 0x11f0000013d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 988},
- {"SLI_MSI_W1C_ENB2" , 0x11f0000013d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 989},
- {"SLI_MSI_W1C_ENB3" , 0x11f0000013d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 990},
- {"SLI_MSI_W1S_ENB0" , 0x11f0000013d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 991},
- {"SLI_MSI_W1S_ENB1" , 0x11f0000013d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 992},
- {"SLI_MSI_W1S_ENB2" , 0x11f0000013d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 993},
- {"SLI_MSI_W1S_ENB3" , 0x11f0000013d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 994},
- {"SLI_MSI_WR_MAP" , 0x11f0000013c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 995},
- {"SLI_PCIE_MSI_RCV" , 0x11f0000013cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 996},
- {"SLI_PCIE_MSI_RCV_B1" , 0x11f0000010650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 997},
- {"SLI_PCIE_MSI_RCV_B2" , 0x11f0000010660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 998},
- {"SLI_PCIE_MSI_RCV_B3" , 0x11f0000010670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 999},
- {"SLI_PKT0_CNTS" , 0x11f0000012400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT1_CNTS" , 0x11f0000012410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT2_CNTS" , 0x11f0000012420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT3_CNTS" , 0x11f0000012430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT4_CNTS" , 0x11f0000012440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT5_CNTS" , 0x11f0000012450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT6_CNTS" , 0x11f0000012460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT7_CNTS" , 0x11f0000012470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT8_CNTS" , 0x11f0000012480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT9_CNTS" , 0x11f0000012490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT10_CNTS" , 0x11f00000124a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT11_CNTS" , 0x11f00000124b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT12_CNTS" , 0x11f00000124c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT13_CNTS" , 0x11f00000124d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT14_CNTS" , 0x11f00000124e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT15_CNTS" , 0x11f00000124f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT16_CNTS" , 0x11f0000012500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT17_CNTS" , 0x11f0000012510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT18_CNTS" , 0x11f0000012520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT19_CNTS" , 0x11f0000012530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT20_CNTS" , 0x11f0000012540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT21_CNTS" , 0x11f0000012550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT22_CNTS" , 0x11f0000012560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT23_CNTS" , 0x11f0000012570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT24_CNTS" , 0x11f0000012580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT25_CNTS" , 0x11f0000012590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT26_CNTS" , 0x11f00000125a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT27_CNTS" , 0x11f00000125b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT28_CNTS" , 0x11f00000125c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT29_CNTS" , 0x11f00000125d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT30_CNTS" , 0x11f00000125e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT31_CNTS" , 0x11f00000125f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1000},
- {"SLI_PKT0_IN_BP" , 0x11f0000013800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT1_IN_BP" , 0x11f0000013810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT2_IN_BP" , 0x11f0000013820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT3_IN_BP" , 0x11f0000013830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT4_IN_BP" , 0x11f0000013840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT5_IN_BP" , 0x11f0000013850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT6_IN_BP" , 0x11f0000013860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT7_IN_BP" , 0x11f0000013870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT8_IN_BP" , 0x11f0000013880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT9_IN_BP" , 0x11f0000013890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT10_IN_BP" , 0x11f00000138a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT11_IN_BP" , 0x11f00000138b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT12_IN_BP" , 0x11f00000138c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT13_IN_BP" , 0x11f00000138d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT14_IN_BP" , 0x11f00000138e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT15_IN_BP" , 0x11f00000138f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT16_IN_BP" , 0x11f0000013900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT17_IN_BP" , 0x11f0000013910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT18_IN_BP" , 0x11f0000013920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT19_IN_BP" , 0x11f0000013930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT20_IN_BP" , 0x11f0000013940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT21_IN_BP" , 0x11f0000013950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT22_IN_BP" , 0x11f0000013960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT23_IN_BP" , 0x11f0000013970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT24_IN_BP" , 0x11f0000013980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT25_IN_BP" , 0x11f0000013990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT26_IN_BP" , 0x11f00000139a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT27_IN_BP" , 0x11f00000139b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT28_IN_BP" , 0x11f00000139c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT29_IN_BP" , 0x11f00000139d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT30_IN_BP" , 0x11f00000139e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT31_IN_BP" , 0x11f00000139f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1001},
- {"SLI_PKT0_INSTR_BADDR" , 0x11f0000012800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT1_INSTR_BADDR" , 0x11f0000012810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT2_INSTR_BADDR" , 0x11f0000012820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT3_INSTR_BADDR" , 0x11f0000012830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT4_INSTR_BADDR" , 0x11f0000012840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT5_INSTR_BADDR" , 0x11f0000012850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT6_INSTR_BADDR" , 0x11f0000012860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT7_INSTR_BADDR" , 0x11f0000012870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT8_INSTR_BADDR" , 0x11f0000012880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT9_INSTR_BADDR" , 0x11f0000012890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT10_INSTR_BADDR" , 0x11f00000128a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT11_INSTR_BADDR" , 0x11f00000128b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT12_INSTR_BADDR" , 0x11f00000128c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT13_INSTR_BADDR" , 0x11f00000128d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT14_INSTR_BADDR" , 0x11f00000128e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT15_INSTR_BADDR" , 0x11f00000128f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT16_INSTR_BADDR" , 0x11f0000012900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT17_INSTR_BADDR" , 0x11f0000012910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT18_INSTR_BADDR" , 0x11f0000012920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT19_INSTR_BADDR" , 0x11f0000012930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT20_INSTR_BADDR" , 0x11f0000012940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT21_INSTR_BADDR" , 0x11f0000012950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT22_INSTR_BADDR" , 0x11f0000012960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT23_INSTR_BADDR" , 0x11f0000012970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT24_INSTR_BADDR" , 0x11f0000012980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT25_INSTR_BADDR" , 0x11f0000012990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT26_INSTR_BADDR" , 0x11f00000129a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT27_INSTR_BADDR" , 0x11f00000129b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT28_INSTR_BADDR" , 0x11f00000129c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT29_INSTR_BADDR" , 0x11f00000129d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT30_INSTR_BADDR" , 0x11f00000129e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT31_INSTR_BADDR" , 0x11f00000129f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1002},
- {"SLI_PKT0_INSTR_BAOFF_DBELL" , 0x11f0000012c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT1_INSTR_BAOFF_DBELL" , 0x11f0000012c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT2_INSTR_BAOFF_DBELL" , 0x11f0000012c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT3_INSTR_BAOFF_DBELL" , 0x11f0000012c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT4_INSTR_BAOFF_DBELL" , 0x11f0000012c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT5_INSTR_BAOFF_DBELL" , 0x11f0000012c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT6_INSTR_BAOFF_DBELL" , 0x11f0000012c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT7_INSTR_BAOFF_DBELL" , 0x11f0000012c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT8_INSTR_BAOFF_DBELL" , 0x11f0000012c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT9_INSTR_BAOFF_DBELL" , 0x11f0000012c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT10_INSTR_BAOFF_DBELL" , 0x11f0000012ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT11_INSTR_BAOFF_DBELL" , 0x11f0000012cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT12_INSTR_BAOFF_DBELL" , 0x11f0000012cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT13_INSTR_BAOFF_DBELL" , 0x11f0000012cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT14_INSTR_BAOFF_DBELL" , 0x11f0000012ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT15_INSTR_BAOFF_DBELL" , 0x11f0000012cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT16_INSTR_BAOFF_DBELL" , 0x11f0000012d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT17_INSTR_BAOFF_DBELL" , 0x11f0000012d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT18_INSTR_BAOFF_DBELL" , 0x11f0000012d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT19_INSTR_BAOFF_DBELL" , 0x11f0000012d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT20_INSTR_BAOFF_DBELL" , 0x11f0000012d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT21_INSTR_BAOFF_DBELL" , 0x11f0000012d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT22_INSTR_BAOFF_DBELL" , 0x11f0000012d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT23_INSTR_BAOFF_DBELL" , 0x11f0000012d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT24_INSTR_BAOFF_DBELL" , 0x11f0000012d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT25_INSTR_BAOFF_DBELL" , 0x11f0000012d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT26_INSTR_BAOFF_DBELL" , 0x11f0000012da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT27_INSTR_BAOFF_DBELL" , 0x11f0000012db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT28_INSTR_BAOFF_DBELL" , 0x11f0000012dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT29_INSTR_BAOFF_DBELL" , 0x11f0000012dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT30_INSTR_BAOFF_DBELL" , 0x11f0000012de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT31_INSTR_BAOFF_DBELL" , 0x11f0000012df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1003},
- {"SLI_PKT0_INSTR_FIFO_RSIZE" , 0x11f0000013000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT1_INSTR_FIFO_RSIZE" , 0x11f0000013010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT2_INSTR_FIFO_RSIZE" , 0x11f0000013020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT3_INSTR_FIFO_RSIZE" , 0x11f0000013030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT4_INSTR_FIFO_RSIZE" , 0x11f0000013040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT5_INSTR_FIFO_RSIZE" , 0x11f0000013050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT6_INSTR_FIFO_RSIZE" , 0x11f0000013060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT7_INSTR_FIFO_RSIZE" , 0x11f0000013070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT8_INSTR_FIFO_RSIZE" , 0x11f0000013080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT9_INSTR_FIFO_RSIZE" , 0x11f0000013090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT10_INSTR_FIFO_RSIZE" , 0x11f00000130a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT11_INSTR_FIFO_RSIZE" , 0x11f00000130b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT12_INSTR_FIFO_RSIZE" , 0x11f00000130c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT13_INSTR_FIFO_RSIZE" , 0x11f00000130d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT14_INSTR_FIFO_RSIZE" , 0x11f00000130e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT15_INSTR_FIFO_RSIZE" , 0x11f00000130f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT16_INSTR_FIFO_RSIZE" , 0x11f0000013100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT17_INSTR_FIFO_RSIZE" , 0x11f0000013110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT18_INSTR_FIFO_RSIZE" , 0x11f0000013120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT19_INSTR_FIFO_RSIZE" , 0x11f0000013130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT20_INSTR_FIFO_RSIZE" , 0x11f0000013140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT21_INSTR_FIFO_RSIZE" , 0x11f0000013150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT22_INSTR_FIFO_RSIZE" , 0x11f0000013160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT23_INSTR_FIFO_RSIZE" , 0x11f0000013170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT24_INSTR_FIFO_RSIZE" , 0x11f0000013180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT25_INSTR_FIFO_RSIZE" , 0x11f0000013190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT26_INSTR_FIFO_RSIZE" , 0x11f00000131a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT27_INSTR_FIFO_RSIZE" , 0x11f00000131b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT28_INSTR_FIFO_RSIZE" , 0x11f00000131c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT29_INSTR_FIFO_RSIZE" , 0x11f00000131d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT30_INSTR_FIFO_RSIZE" , 0x11f00000131e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT31_INSTR_FIFO_RSIZE" , 0x11f00000131f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1004},
- {"SLI_PKT0_INSTR_HEADER" , 0x11f0000013400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT1_INSTR_HEADER" , 0x11f0000013410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT2_INSTR_HEADER" , 0x11f0000013420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT3_INSTR_HEADER" , 0x11f0000013430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT4_INSTR_HEADER" , 0x11f0000013440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT5_INSTR_HEADER" , 0x11f0000013450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT6_INSTR_HEADER" , 0x11f0000013460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT7_INSTR_HEADER" , 0x11f0000013470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT8_INSTR_HEADER" , 0x11f0000013480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT9_INSTR_HEADER" , 0x11f0000013490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT10_INSTR_HEADER" , 0x11f00000134a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT11_INSTR_HEADER" , 0x11f00000134b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT12_INSTR_HEADER" , 0x11f00000134c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT13_INSTR_HEADER" , 0x11f00000134d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT14_INSTR_HEADER" , 0x11f00000134e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT15_INSTR_HEADER" , 0x11f00000134f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT16_INSTR_HEADER" , 0x11f0000013500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT17_INSTR_HEADER" , 0x11f0000013510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT18_INSTR_HEADER" , 0x11f0000013520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT19_INSTR_HEADER" , 0x11f0000013530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT20_INSTR_HEADER" , 0x11f0000013540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT21_INSTR_HEADER" , 0x11f0000013550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT22_INSTR_HEADER" , 0x11f0000013560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT23_INSTR_HEADER" , 0x11f0000013570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT24_INSTR_HEADER" , 0x11f0000013580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT25_INSTR_HEADER" , 0x11f0000013590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT26_INSTR_HEADER" , 0x11f00000135a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT27_INSTR_HEADER" , 0x11f00000135b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT28_INSTR_HEADER" , 0x11f00000135c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT29_INSTR_HEADER" , 0x11f00000135d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT30_INSTR_HEADER" , 0x11f00000135e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT31_INSTR_HEADER" , 0x11f00000135f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1005},
- {"SLI_PKT0_OUT_SIZE" , 0x11f0000010c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT1_OUT_SIZE" , 0x11f0000010c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT2_OUT_SIZE" , 0x11f0000010c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT3_OUT_SIZE" , 0x11f0000010c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT4_OUT_SIZE" , 0x11f0000010c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT5_OUT_SIZE" , 0x11f0000010c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT6_OUT_SIZE" , 0x11f0000010c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT7_OUT_SIZE" , 0x11f0000010c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT8_OUT_SIZE" , 0x11f0000010c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT9_OUT_SIZE" , 0x11f0000010c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT10_OUT_SIZE" , 0x11f0000010ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT11_OUT_SIZE" , 0x11f0000010cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT12_OUT_SIZE" , 0x11f0000010cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT13_OUT_SIZE" , 0x11f0000010cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT14_OUT_SIZE" , 0x11f0000010ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT15_OUT_SIZE" , 0x11f0000010cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT16_OUT_SIZE" , 0x11f0000010d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT17_OUT_SIZE" , 0x11f0000010d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT18_OUT_SIZE" , 0x11f0000010d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT19_OUT_SIZE" , 0x11f0000010d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT20_OUT_SIZE" , 0x11f0000010d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT21_OUT_SIZE" , 0x11f0000010d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT22_OUT_SIZE" , 0x11f0000010d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT23_OUT_SIZE" , 0x11f0000010d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT24_OUT_SIZE" , 0x11f0000010d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT25_OUT_SIZE" , 0x11f0000010d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT26_OUT_SIZE" , 0x11f0000010da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT27_OUT_SIZE" , 0x11f0000010db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT28_OUT_SIZE" , 0x11f0000010dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT29_OUT_SIZE" , 0x11f0000010dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT30_OUT_SIZE" , 0x11f0000010de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT31_OUT_SIZE" , 0x11f0000010df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1006},
- {"SLI_PKT0_SLIST_BADDR" , 0x11f0000011400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT1_SLIST_BADDR" , 0x11f0000011410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT2_SLIST_BADDR" , 0x11f0000011420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT3_SLIST_BADDR" , 0x11f0000011430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT4_SLIST_BADDR" , 0x11f0000011440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT5_SLIST_BADDR" , 0x11f0000011450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT6_SLIST_BADDR" , 0x11f0000011460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT7_SLIST_BADDR" , 0x11f0000011470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT8_SLIST_BADDR" , 0x11f0000011480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT9_SLIST_BADDR" , 0x11f0000011490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT10_SLIST_BADDR" , 0x11f00000114a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT11_SLIST_BADDR" , 0x11f00000114b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT12_SLIST_BADDR" , 0x11f00000114c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT13_SLIST_BADDR" , 0x11f00000114d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT14_SLIST_BADDR" , 0x11f00000114e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT15_SLIST_BADDR" , 0x11f00000114f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT16_SLIST_BADDR" , 0x11f0000011500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT17_SLIST_BADDR" , 0x11f0000011510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT18_SLIST_BADDR" , 0x11f0000011520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT19_SLIST_BADDR" , 0x11f0000011530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT20_SLIST_BADDR" , 0x11f0000011540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT21_SLIST_BADDR" , 0x11f0000011550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT22_SLIST_BADDR" , 0x11f0000011560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT23_SLIST_BADDR" , 0x11f0000011570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT24_SLIST_BADDR" , 0x11f0000011580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT25_SLIST_BADDR" , 0x11f0000011590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT26_SLIST_BADDR" , 0x11f00000115a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT27_SLIST_BADDR" , 0x11f00000115b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT28_SLIST_BADDR" , 0x11f00000115c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT29_SLIST_BADDR" , 0x11f00000115d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT30_SLIST_BADDR" , 0x11f00000115e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT31_SLIST_BADDR" , 0x11f00000115f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1007},
- {"SLI_PKT0_SLIST_BAOFF_DBELL" , 0x11f0000011800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT1_SLIST_BAOFF_DBELL" , 0x11f0000011810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT2_SLIST_BAOFF_DBELL" , 0x11f0000011820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT3_SLIST_BAOFF_DBELL" , 0x11f0000011830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT4_SLIST_BAOFF_DBELL" , 0x11f0000011840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT5_SLIST_BAOFF_DBELL" , 0x11f0000011850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT6_SLIST_BAOFF_DBELL" , 0x11f0000011860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT7_SLIST_BAOFF_DBELL" , 0x11f0000011870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT8_SLIST_BAOFF_DBELL" , 0x11f0000011880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT9_SLIST_BAOFF_DBELL" , 0x11f0000011890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT10_SLIST_BAOFF_DBELL" , 0x11f00000118a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT11_SLIST_BAOFF_DBELL" , 0x11f00000118b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT12_SLIST_BAOFF_DBELL" , 0x11f00000118c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT13_SLIST_BAOFF_DBELL" , 0x11f00000118d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT14_SLIST_BAOFF_DBELL" , 0x11f00000118e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT15_SLIST_BAOFF_DBELL" , 0x11f00000118f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT16_SLIST_BAOFF_DBELL" , 0x11f0000011900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT17_SLIST_BAOFF_DBELL" , 0x11f0000011910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT18_SLIST_BAOFF_DBELL" , 0x11f0000011920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT19_SLIST_BAOFF_DBELL" , 0x11f0000011930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT20_SLIST_BAOFF_DBELL" , 0x11f0000011940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT21_SLIST_BAOFF_DBELL" , 0x11f0000011950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT22_SLIST_BAOFF_DBELL" , 0x11f0000011960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT23_SLIST_BAOFF_DBELL" , 0x11f0000011970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT24_SLIST_BAOFF_DBELL" , 0x11f0000011980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT25_SLIST_BAOFF_DBELL" , 0x11f0000011990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT26_SLIST_BAOFF_DBELL" , 0x11f00000119a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT27_SLIST_BAOFF_DBELL" , 0x11f00000119b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT28_SLIST_BAOFF_DBELL" , 0x11f00000119c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT29_SLIST_BAOFF_DBELL" , 0x11f00000119d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT30_SLIST_BAOFF_DBELL" , 0x11f00000119e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT31_SLIST_BAOFF_DBELL" , 0x11f00000119f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1008},
- {"SLI_PKT0_SLIST_FIFO_RSIZE" , 0x11f0000011c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT1_SLIST_FIFO_RSIZE" , 0x11f0000011c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT2_SLIST_FIFO_RSIZE" , 0x11f0000011c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT3_SLIST_FIFO_RSIZE" , 0x11f0000011c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT4_SLIST_FIFO_RSIZE" , 0x11f0000011c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT5_SLIST_FIFO_RSIZE" , 0x11f0000011c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT6_SLIST_FIFO_RSIZE" , 0x11f0000011c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT7_SLIST_FIFO_RSIZE" , 0x11f0000011c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT8_SLIST_FIFO_RSIZE" , 0x11f0000011c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT9_SLIST_FIFO_RSIZE" , 0x11f0000011c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT10_SLIST_FIFO_RSIZE" , 0x11f0000011ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT11_SLIST_FIFO_RSIZE" , 0x11f0000011cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT12_SLIST_FIFO_RSIZE" , 0x11f0000011cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT13_SLIST_FIFO_RSIZE" , 0x11f0000011cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT14_SLIST_FIFO_RSIZE" , 0x11f0000011ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT15_SLIST_FIFO_RSIZE" , 0x11f0000011cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT16_SLIST_FIFO_RSIZE" , 0x11f0000011d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT17_SLIST_FIFO_RSIZE" , 0x11f0000011d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT18_SLIST_FIFO_RSIZE" , 0x11f0000011d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT19_SLIST_FIFO_RSIZE" , 0x11f0000011d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT20_SLIST_FIFO_RSIZE" , 0x11f0000011d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT21_SLIST_FIFO_RSIZE" , 0x11f0000011d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT22_SLIST_FIFO_RSIZE" , 0x11f0000011d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT23_SLIST_FIFO_RSIZE" , 0x11f0000011d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT24_SLIST_FIFO_RSIZE" , 0x11f0000011d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT25_SLIST_FIFO_RSIZE" , 0x11f0000011d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT26_SLIST_FIFO_RSIZE" , 0x11f0000011da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT27_SLIST_FIFO_RSIZE" , 0x11f0000011db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT28_SLIST_FIFO_RSIZE" , 0x11f0000011dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT29_SLIST_FIFO_RSIZE" , 0x11f0000011dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT30_SLIST_FIFO_RSIZE" , 0x11f0000011de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT31_SLIST_FIFO_RSIZE" , 0x11f0000011df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1009},
- {"SLI_PKT_CNT_INT" , 0x11f0000011130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1010},
- {"SLI_PKT_CNT_INT_ENB" , 0x11f0000011150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1011},
- {"SLI_PKT_CTL" , 0x11f0000011220ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1012},
- {"SLI_PKT_DATA_OUT_ES" , 0x11f00000110b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1013},
- {"SLI_PKT_DATA_OUT_NS" , 0x11f00000110a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1014},
- {"SLI_PKT_DATA_OUT_ROR" , 0x11f0000011090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1015},
- {"SLI_PKT_DPADDR" , 0x11f0000011080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1016},
- {"SLI_PKT_IN_BP" , 0x11f0000011210ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1017},
- {"SLI_PKT_IN_DONE0_CNTS" , 0x11f0000012000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE1_CNTS" , 0x11f0000012010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE2_CNTS" , 0x11f0000012020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE3_CNTS" , 0x11f0000012030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE4_CNTS" , 0x11f0000012040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE5_CNTS" , 0x11f0000012050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE6_CNTS" , 0x11f0000012060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE7_CNTS" , 0x11f0000012070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE8_CNTS" , 0x11f0000012080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE9_CNTS" , 0x11f0000012090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE10_CNTS" , 0x11f00000120a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE11_CNTS" , 0x11f00000120b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE12_CNTS" , 0x11f00000120c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE13_CNTS" , 0x11f00000120d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE14_CNTS" , 0x11f00000120e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE15_CNTS" , 0x11f00000120f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE16_CNTS" , 0x11f0000012100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE17_CNTS" , 0x11f0000012110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE18_CNTS" , 0x11f0000012120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE19_CNTS" , 0x11f0000012130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE20_CNTS" , 0x11f0000012140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE21_CNTS" , 0x11f0000012150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE22_CNTS" , 0x11f0000012160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE23_CNTS" , 0x11f0000012170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE24_CNTS" , 0x11f0000012180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE25_CNTS" , 0x11f0000012190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE26_CNTS" , 0x11f00000121a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE27_CNTS" , 0x11f00000121b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE28_CNTS" , 0x11f00000121c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE29_CNTS" , 0x11f00000121d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE30_CNTS" , 0x11f00000121e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_DONE31_CNTS" , 0x11f00000121f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018},
- {"SLI_PKT_IN_INSTR_COUNTS" , 0x11f0000011200ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1019},
- {"SLI_PKT_IN_PCIE_PORT" , 0x11f00000111b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1020},
- {"SLI_PKT_INPUT_CONTROL" , 0x11f0000011170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1021},
- {"SLI_PKT_INSTR_ENB" , 0x11f0000011000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1022},
- {"SLI_PKT_INSTR_RD_SIZE" , 0x11f00000111a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1023},
- {"SLI_PKT_INSTR_SIZE" , 0x11f0000011020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1024},
- {"SLI_PKT_INT_LEVELS" , 0x11f0000011120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1025},
- {"SLI_PKT_IPTR" , 0x11f0000011070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1026},
- {"SLI_PKT_OUT_BMODE" , 0x11f00000110d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1027},
- {"SLI_PKT_OUT_ENB" , 0x11f0000011010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1028},
- {"SLI_PKT_OUTPUT_WMARK" , 0x11f0000011180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1029},
- {"SLI_PKT_PCIE_PORT" , 0x11f00000110e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1030},
- {"SLI_PKT_PORT_IN_RST" , 0x11f00000111f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1031},
- {"SLI_PKT_SLIST_ES" , 0x11f0000011050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1032},
- {"SLI_PKT_SLIST_NS" , 0x11f0000011040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1033},
- {"SLI_PKT_SLIST_ROR" , 0x11f0000011030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1034},
- {"SLI_PKT_TIME_INT" , 0x11f0000011140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1035},
- {"SLI_PKT_TIME_INT_ENB" , 0x11f0000011160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1036},
- {"SLI_S2M_PORT0_CTL" , 0x11f0000013d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1037},
- {"SLI_S2M_PORT1_CTL" , 0x11f0000013d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1037},
- {"SLI_S2M_PORT2_CTL" , 0x11f0000013da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1037},
- {"SLI_S2M_PORT3_CTL" , 0x11f0000013db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1037},
- {"SLI_SCRATCH_1" , 0x11f00000103c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1038},
- {"SLI_SCRATCH_2" , 0x11f00000103d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1039},
- {"SLI_STATE1" , 0x11f0000010620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1040},
- {"SLI_STATE2" , 0x11f0000010630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1041},
- {"SLI_STATE3" , 0x11f0000010640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1042},
- {"SLI_WIN_RD_ADDR" , 0x10ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1043},
- {"SLI_WIN_RD_DATA" , 0x40ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1044},
- {"SLI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1045},
- {"SLI_WIN_WR_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1046},
- {"SLI_WIN_WR_MASK" , 0x30ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1047},
- {"SLI_WINDOW_CTL" , 0x11f00000102e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1048},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1049},
- {"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1049},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1050},
- {"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1050},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1051},
- {"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1051},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1052},
- {"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1052},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1053},
- {"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1053},
- {"SMI_DRV_CTL" , 0x1180000001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1054},
- {"SRIO0_ACC_CTRL" , 0x11800c8000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1055},
- {"SRIO2_ACC_CTRL" , 0x11800ca000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1055},
- {"SRIO3_ACC_CTRL" , 0x11800cb000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1055},
- {"SRIO0_ASMBLY_ID" , 0x11800c8000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1056},
- {"SRIO2_ASMBLY_ID" , 0x11800ca000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1056},
- {"SRIO3_ASMBLY_ID" , 0x11800cb000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1056},
- {"SRIO0_ASMBLY_INFO" , 0x11800c8000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1057},
- {"SRIO2_ASMBLY_INFO" , 0x11800ca000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1057},
- {"SRIO3_ASMBLY_INFO" , 0x11800cb000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1057},
- {"SRIO0_BELL_RESP_CTRL" , 0x11800c8000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1058},
- {"SRIO2_BELL_RESP_CTRL" , 0x11800ca000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1058},
- {"SRIO3_BELL_RESP_CTRL" , 0x11800cb000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1058},
- {"SRIO0_BIST_STATUS" , 0x11800c8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1059},
- {"SRIO2_BIST_STATUS" , 0x11800ca000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1059},
- {"SRIO3_BIST_STATUS" , 0x11800cb000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1059},
- {"SRIO0_IMSG_CTRL" , 0x11800c8000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1060},
- {"SRIO2_IMSG_CTRL" , 0x11800ca000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1060},
- {"SRIO3_IMSG_CTRL" , 0x11800cb000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1060},
- {"SRIO0_IMSG_INST_HDR000" , 0x11800c8000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1061},
- {"SRIO0_IMSG_INST_HDR001" , 0x11800c8000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1061},
- {"SRIO2_IMSG_INST_HDR000" , 0x11800ca000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1061},
- {"SRIO2_IMSG_INST_HDR001" , 0x11800ca000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1061},
- {"SRIO3_IMSG_INST_HDR000" , 0x11800cb000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1061},
- {"SRIO3_IMSG_INST_HDR001" , 0x11800cb000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1061},
- {"SRIO0_IMSG_QOS_GRP000" , 0x11800c8000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP001" , 0x11800c8000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP002" , 0x11800c8000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP003" , 0x11800c8000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP004" , 0x11800c8000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP005" , 0x11800c8000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP006" , 0x11800c8000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP007" , 0x11800c8000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP008" , 0x11800c8000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP009" , 0x11800c8000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP010" , 0x11800c8000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP011" , 0x11800c8000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP012" , 0x11800c8000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP013" , 0x11800c8000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP014" , 0x11800c8000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP015" , 0x11800c8000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP016" , 0x11800c8000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP017" , 0x11800c8000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP018" , 0x11800c8000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP019" , 0x11800c8000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP020" , 0x11800c80006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP021" , 0x11800c80006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP022" , 0x11800c80006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP023" , 0x11800c80006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP024" , 0x11800c80006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP025" , 0x11800c80006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP026" , 0x11800c80006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP027" , 0x11800c80006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP028" , 0x11800c80006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP029" , 0x11800c80006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP030" , 0x11800c80006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_QOS_GRP031" , 0x11800c80006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP000" , 0x11800ca000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP001" , 0x11800ca000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP002" , 0x11800ca000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP003" , 0x11800ca000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP004" , 0x11800ca000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP005" , 0x11800ca000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP006" , 0x11800ca000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP007" , 0x11800ca000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP008" , 0x11800ca000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP009" , 0x11800ca000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP010" , 0x11800ca000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP011" , 0x11800ca000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP012" , 0x11800ca000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP013" , 0x11800ca000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP014" , 0x11800ca000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP015" , 0x11800ca000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP016" , 0x11800ca000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP017" , 0x11800ca000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP018" , 0x11800ca000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP019" , 0x11800ca000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP020" , 0x11800ca0006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP021" , 0x11800ca0006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP022" , 0x11800ca0006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP023" , 0x11800ca0006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP024" , 0x11800ca0006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP025" , 0x11800ca0006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP026" , 0x11800ca0006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP027" , 0x11800ca0006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP028" , 0x11800ca0006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP029" , 0x11800ca0006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP030" , 0x11800ca0006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO2_IMSG_QOS_GRP031" , 0x11800ca0006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP000" , 0x11800cb000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP001" , 0x11800cb000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP002" , 0x11800cb000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP003" , 0x11800cb000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP004" , 0x11800cb000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP005" , 0x11800cb000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP006" , 0x11800cb000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP007" , 0x11800cb000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP008" , 0x11800cb000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP009" , 0x11800cb000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP010" , 0x11800cb000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP011" , 0x11800cb000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP012" , 0x11800cb000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP013" , 0x11800cb000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP014" , 0x11800cb000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP015" , 0x11800cb000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP016" , 0x11800cb000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP017" , 0x11800cb000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP018" , 0x11800cb000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP019" , 0x11800cb000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP020" , 0x11800cb0006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP021" , 0x11800cb0006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP022" , 0x11800cb0006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP023" , 0x11800cb0006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP024" , 0x11800cb0006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP025" , 0x11800cb0006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP026" , 0x11800cb0006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP027" , 0x11800cb0006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP028" , 0x11800cb0006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP029" , 0x11800cb0006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP030" , 0x11800cb0006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO3_IMSG_QOS_GRP031" , 0x11800cb0006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"SRIO0_IMSG_STATUS000" , 0x11800c8000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS001" , 0x11800c8000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS002" , 0x11800c8000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS003" , 0x11800c8000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS004" , 0x11800c8000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS005" , 0x11800c8000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS006" , 0x11800c8000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS007" , 0x11800c8000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS008" , 0x11800c8000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS009" , 0x11800c8000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS010" , 0x11800c8000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS011" , 0x11800c8000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS012" , 0x11800c8000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS013" , 0x11800c8000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS014" , 0x11800c8000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS015" , 0x11800c8000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS016" , 0x11800c8000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS017" , 0x11800c8000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS018" , 0x11800c8000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS019" , 0x11800c8000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS020" , 0x11800c80007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS021" , 0x11800c80007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS022" , 0x11800c80007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_STATUS023" , 0x11800c80007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS000" , 0x11800ca000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS001" , 0x11800ca000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS002" , 0x11800ca000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS003" , 0x11800ca000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS004" , 0x11800ca000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS005" , 0x11800ca000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS006" , 0x11800ca000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS007" , 0x11800ca000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS008" , 0x11800ca000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS009" , 0x11800ca000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS010" , 0x11800ca000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS011" , 0x11800ca000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS012" , 0x11800ca000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS013" , 0x11800ca000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS014" , 0x11800ca000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS015" , 0x11800ca000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS016" , 0x11800ca000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS017" , 0x11800ca000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS018" , 0x11800ca000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS019" , 0x11800ca000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS020" , 0x11800ca0007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS021" , 0x11800ca0007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS022" , 0x11800ca0007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO2_IMSG_STATUS023" , 0x11800ca0007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS000" , 0x11800cb000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS001" , 0x11800cb000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS002" , 0x11800cb000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS003" , 0x11800cb000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS004" , 0x11800cb000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS005" , 0x11800cb000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS006" , 0x11800cb000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS007" , 0x11800cb000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS008" , 0x11800cb000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS009" , 0x11800cb000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS010" , 0x11800cb000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS011" , 0x11800cb000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS012" , 0x11800cb000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS013" , 0x11800cb000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS014" , 0x11800cb000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS015" , 0x11800cb000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS016" , 0x11800cb000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS017" , 0x11800cb000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS018" , 0x11800cb000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS019" , 0x11800cb000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS020" , 0x11800cb0007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS021" , 0x11800cb0007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS022" , 0x11800cb0007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO3_IMSG_STATUS023" , 0x11800cb0007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"SRIO0_IMSG_VPORT_THR" , 0x11800c8000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1064},
- {"SRIO2_IMSG_VPORT_THR" , 0x11800ca000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1064},
- {"SRIO3_IMSG_VPORT_THR" , 0x11800cb000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1064},
- {"SRIO0_IMSG_VPORT_THR2" , 0x11800c8000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1065},
- {"SRIO2_IMSG_VPORT_THR2" , 0x11800ca000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1065},
- {"SRIO3_IMSG_VPORT_THR2" , 0x11800cb000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1065},
- {"SRIO0_INT2_ENABLE" , 0x11800c80003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1066},
- {"SRIO2_INT2_ENABLE" , 0x11800ca0003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1066},
- {"SRIO3_INT2_ENABLE" , 0x11800cb0003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1066},
- {"SRIO0_INT2_REG" , 0x11800c80003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1067},
- {"SRIO2_INT2_REG" , 0x11800ca0003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1067},
- {"SRIO3_INT2_REG" , 0x11800cb0003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1067},
- {"SRIO0_INT_ENABLE" , 0x11800c8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1068},
- {"SRIO2_INT_ENABLE" , 0x11800ca000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1068},
- {"SRIO3_INT_ENABLE" , 0x11800cb000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1068},
- {"SRIO0_INT_INFO0" , 0x11800c8000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1069},
- {"SRIO2_INT_INFO0" , 0x11800ca000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1069},
- {"SRIO3_INT_INFO0" , 0x11800cb000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1069},
- {"SRIO0_INT_INFO1" , 0x11800c8000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1070},
- {"SRIO2_INT_INFO1" , 0x11800ca000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1070},
- {"SRIO3_INT_INFO1" , 0x11800cb000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1070},
- {"SRIO0_INT_INFO2" , 0x11800c8000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1071},
- {"SRIO2_INT_INFO2" , 0x11800ca000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1071},
- {"SRIO3_INT_INFO2" , 0x11800cb000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1071},
- {"SRIO0_INT_INFO3" , 0x11800c8000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1072},
- {"SRIO2_INT_INFO3" , 0x11800ca000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1072},
- {"SRIO3_INT_INFO3" , 0x11800cb000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1072},
- {"SRIO0_INT_REG" , 0x11800c8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1073},
- {"SRIO2_INT_REG" , 0x11800ca000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1073},
- {"SRIO3_INT_REG" , 0x11800cb000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1073},
- {"SRIO0_IP_FEATURE" , 0x11800c80003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1074},
- {"SRIO2_IP_FEATURE" , 0x11800ca0003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1074},
- {"SRIO3_IP_FEATURE" , 0x11800cb0003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1074},
- {"SRIO0_MAC_BUFFERS" , 0x11800c8000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1075},
- {"SRIO2_MAC_BUFFERS" , 0x11800ca000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1075},
- {"SRIO3_MAC_BUFFERS" , 0x11800cb000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1075},
- {"SRIO0_MAINT_OP" , 0x11800c8000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1076},
- {"SRIO2_MAINT_OP" , 0x11800ca000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1076},
- {"SRIO3_MAINT_OP" , 0x11800cb000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1076},
- {"SRIO0_MAINT_RD_DATA" , 0x11800c8000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1077},
- {"SRIO2_MAINT_RD_DATA" , 0x11800ca000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1077},
- {"SRIO3_MAINT_RD_DATA" , 0x11800cb000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1077},
- {"SRIO0_MCE_TX_CTL" , 0x11800c8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1078},
- {"SRIO2_MCE_TX_CTL" , 0x11800ca000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1078},
- {"SRIO3_MCE_TX_CTL" , 0x11800cb000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1078},
- {"SRIO0_MEM_OP_CTRL" , 0x11800c8000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1079},
- {"SRIO2_MEM_OP_CTRL" , 0x11800ca000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1079},
- {"SRIO3_MEM_OP_CTRL" , 0x11800cb000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1079},
- {"SRIO0_OMSG_CTRL000" , 0x11800c8000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1080},
- {"SRIO0_OMSG_CTRL001" , 0x11800c80004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1080},
- {"SRIO2_OMSG_CTRL000" , 0x11800ca000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1080},
- {"SRIO2_OMSG_CTRL001" , 0x11800ca0004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1080},
- {"SRIO3_OMSG_CTRL000" , 0x11800cb000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1080},
- {"SRIO3_OMSG_CTRL001" , 0x11800cb0004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1080},
- {"SRIO0_OMSG_DONE_COUNTS000" , 0x11800c80004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1081},
- {"SRIO0_OMSG_DONE_COUNTS001" , 0x11800c80004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1081},
- {"SRIO2_OMSG_DONE_COUNTS000" , 0x11800ca0004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1081},
- {"SRIO2_OMSG_DONE_COUNTS001" , 0x11800ca0004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1081},
- {"SRIO3_OMSG_DONE_COUNTS000" , 0x11800cb0004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1081},
- {"SRIO3_OMSG_DONE_COUNTS001" , 0x11800cb0004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1081},
- {"SRIO0_OMSG_FMP_MR000" , 0x11800c8000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1082},
- {"SRIO0_OMSG_FMP_MR001" , 0x11800c80004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1082},
- {"SRIO2_OMSG_FMP_MR000" , 0x11800ca000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1082},
- {"SRIO2_OMSG_FMP_MR001" , 0x11800ca0004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1082},
- {"SRIO3_OMSG_FMP_MR000" , 0x11800cb000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1082},
- {"SRIO3_OMSG_FMP_MR001" , 0x11800cb0004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1082},
- {"SRIO0_OMSG_NMP_MR000" , 0x11800c80004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1083},
- {"SRIO0_OMSG_NMP_MR001" , 0x11800c80004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1083},
- {"SRIO2_OMSG_NMP_MR000" , 0x11800ca0004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1083},
- {"SRIO2_OMSG_NMP_MR001" , 0x11800ca0004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1083},
- {"SRIO3_OMSG_NMP_MR000" , 0x11800cb0004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1083},
- {"SRIO3_OMSG_NMP_MR001" , 0x11800cb0004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1083},
- {"SRIO0_OMSG_PORT000" , 0x11800c8000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1084},
- {"SRIO0_OMSG_PORT001" , 0x11800c80004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1084},
- {"SRIO2_OMSG_PORT000" , 0x11800ca000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1084},
- {"SRIO2_OMSG_PORT001" , 0x11800ca0004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1084},
- {"SRIO3_OMSG_PORT000" , 0x11800cb000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1084},
- {"SRIO3_OMSG_PORT001" , 0x11800cb0004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1084},
- {"SRIO0_OMSG_SILO_THR" , 0x11800c80004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1085},
- {"SRIO2_OMSG_SILO_THR" , 0x11800ca0004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1085},
- {"SRIO3_OMSG_SILO_THR" , 0x11800cb0004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1085},
- {"SRIO0_OMSG_SP_MR000" , 0x11800c8000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1086},
- {"SRIO0_OMSG_SP_MR001" , 0x11800c80004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1086},
- {"SRIO2_OMSG_SP_MR000" , 0x11800ca000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1086},
- {"SRIO2_OMSG_SP_MR001" , 0x11800ca0004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1086},
- {"SRIO3_OMSG_SP_MR000" , 0x11800cb000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1086},
- {"SRIO3_OMSG_SP_MR001" , 0x11800cb0004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1086},
- {"SRIO0_PRIO000_IN_USE" , 0x11800c80003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO0_PRIO001_IN_USE" , 0x11800c80003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO0_PRIO002_IN_USE" , 0x11800c80003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO0_PRIO003_IN_USE" , 0x11800c80003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO2_PRIO000_IN_USE" , 0x11800ca0003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO2_PRIO001_IN_USE" , 0x11800ca0003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO2_PRIO002_IN_USE" , 0x11800ca0003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO2_PRIO003_IN_USE" , 0x11800ca0003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO3_PRIO000_IN_USE" , 0x11800cb0003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO3_PRIO001_IN_USE" , 0x11800cb0003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO3_PRIO002_IN_USE" , 0x11800cb0003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO3_PRIO003_IN_USE" , 0x11800cb0003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"SRIO0_RX_BELL" , 0x11800c8000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1088},
- {"SRIO2_RX_BELL" , 0x11800ca000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1088},
- {"SRIO3_RX_BELL" , 0x11800cb000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1088},
- {"SRIO0_RX_BELL_SEQ" , 0x11800c8000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1089},
- {"SRIO2_RX_BELL_SEQ" , 0x11800ca000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1089},
- {"SRIO3_RX_BELL_SEQ" , 0x11800cb000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1089},
- {"SRIO0_RX_STATUS" , 0x11800c8000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1090},
- {"SRIO2_RX_STATUS" , 0x11800ca000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1090},
- {"SRIO3_RX_STATUS" , 0x11800cb000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1090},
- {"SRIO0_S2M_TYPE000" , 0x11800c8000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE001" , 0x11800c8000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE002" , 0x11800c8000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE003" , 0x11800c8000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE004" , 0x11800c80001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE005" , 0x11800c80001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE006" , 0x11800c80001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE007" , 0x11800c80001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE008" , 0x11800c80001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE009" , 0x11800c80001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE010" , 0x11800c80001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE011" , 0x11800c80001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE012" , 0x11800c80001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE013" , 0x11800c80001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE014" , 0x11800c80001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_S2M_TYPE015" , 0x11800c80001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE000" , 0x11800ca000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE001" , 0x11800ca000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE002" , 0x11800ca000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE003" , 0x11800ca000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE004" , 0x11800ca0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE005" , 0x11800ca0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE006" , 0x11800ca0001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE007" , 0x11800ca0001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE008" , 0x11800ca0001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE009" , 0x11800ca0001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE010" , 0x11800ca0001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE011" , 0x11800ca0001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE012" , 0x11800ca0001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE013" , 0x11800ca0001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE014" , 0x11800ca0001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO2_S2M_TYPE015" , 0x11800ca0001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE000" , 0x11800cb000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE001" , 0x11800cb000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE002" , 0x11800cb000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE003" , 0x11800cb000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE004" , 0x11800cb0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE005" , 0x11800cb0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE006" , 0x11800cb0001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE007" , 0x11800cb0001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE008" , 0x11800cb0001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE009" , 0x11800cb0001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE010" , 0x11800cb0001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE011" , 0x11800cb0001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE012" , 0x11800cb0001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE013" , 0x11800cb0001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE014" , 0x11800cb0001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO3_S2M_TYPE015" , 0x11800cb0001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"SRIO0_SEQ" , 0x11800c8000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1092},
- {"SRIO2_SEQ" , 0x11800ca000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1092},
- {"SRIO3_SEQ" , 0x11800cb000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1092},
- {"SRIO0_STATUS_REG" , 0x11800c8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1093},
- {"SRIO2_STATUS_REG" , 0x11800ca000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1093},
- {"SRIO3_STATUS_REG" , 0x11800cb000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1093},
- {"SRIO0_TAG_CTRL" , 0x11800c8000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1094},
- {"SRIO2_TAG_CTRL" , 0x11800ca000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1094},
- {"SRIO3_TAG_CTRL" , 0x11800cb000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1094},
- {"SRIO0_TLP_CREDITS" , 0x11800c8000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1095},
- {"SRIO2_TLP_CREDITS" , 0x11800ca000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1095},
- {"SRIO3_TLP_CREDITS" , 0x11800cb000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1095},
- {"SRIO0_TX_BELL" , 0x11800c8000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1096},
- {"SRIO2_TX_BELL" , 0x11800ca000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1096},
- {"SRIO3_TX_BELL" , 0x11800cb000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1096},
- {"SRIO0_TX_BELL_INFO" , 0x11800c8000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1097},
- {"SRIO2_TX_BELL_INFO" , 0x11800ca000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1097},
- {"SRIO3_TX_BELL_INFO" , 0x11800cb000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1097},
- {"SRIO0_TX_CTRL" , 0x11800c8000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1098},
- {"SRIO2_TX_CTRL" , 0x11800ca000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1098},
- {"SRIO3_TX_CTRL" , 0x11800cb000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1098},
- {"SRIO0_TX_EMPHASIS" , 0x11800c80003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1099},
- {"SRIO2_TX_EMPHASIS" , 0x11800ca0003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1099},
- {"SRIO3_TX_EMPHASIS" , 0x11800cb0003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1099},
- {"SRIO0_TX_STATUS" , 0x11800c8000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1100},
- {"SRIO2_TX_STATUS" , 0x11800ca000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1100},
- {"SRIO3_TX_STATUS" , 0x11800cb000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1100},
- {"SRIO0_WR_DONE_COUNTS" , 0x11800c8000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1101},
- {"SRIO2_WR_DONE_COUNTS" , 0x11800ca000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1101},
- {"SRIO3_WR_DONE_COUNTS" , 0x11800cb000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1101},
- {"SRIOMAINT0_ASMBLY_ID" , 0x8ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1102},
- {"SRIOMAINT2_ASMBLY_ID" , 0x8ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1102},
- {"SRIOMAINT3_ASMBLY_ID" , 0x8ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1102},
- {"SRIOMAINT0_ASMBLY_INFO" , 0xcull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1103},
- {"SRIOMAINT2_ASMBLY_INFO" , 0xcull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1103},
- {"SRIOMAINT3_ASMBLY_INFO" , 0xcull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1103},
- {"SRIOMAINT0_BAR1_IDX000" , 0x200010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX001" , 0x200014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX002" , 0x200018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX003" , 0x20001cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX004" , 0x200020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX005" , 0x200024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX006" , 0x200028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX007" , 0x20002cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX008" , 0x200030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX009" , 0x200034ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX010" , 0x200038ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX011" , 0x20003cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX012" , 0x200040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX013" , 0x200044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX014" , 0x200048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BAR1_IDX015" , 0x20004cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX000" , 0x200010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX001" , 0x200014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX002" , 0x200018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX003" , 0x20001cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX004" , 0x200020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX005" , 0x200024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX006" , 0x200028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX007" , 0x20002cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX008" , 0x200030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX009" , 0x200034ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX010" , 0x200038ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX011" , 0x20003cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX012" , 0x200040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX013" , 0x200044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX014" , 0x200048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT2_BAR1_IDX015" , 0x20004cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX000" , 0x200010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX001" , 0x200014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX002" , 0x200018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX003" , 0x20001cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX004" , 0x200020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX005" , 0x200024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX006" , 0x200028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX007" , 0x20002cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX008" , 0x200030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX009" , 0x200034ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX010" , 0x200038ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX011" , 0x20003cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX012" , 0x200040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX013" , 0x200044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX014" , 0x200048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT3_BAR1_IDX015" , 0x20004cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1104},
- {"SRIOMAINT0_BELL_STATUS" , 0x200080ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1105},
- {"SRIOMAINT2_BELL_STATUS" , 0x200080ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1105},
- {"SRIOMAINT3_BELL_STATUS" , 0x200080ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1105},
- {"SRIOMAINT0_COMP_TAG" , 0x6cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1106},
- {"SRIOMAINT2_COMP_TAG" , 0x6cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1106},
- {"SRIOMAINT3_COMP_TAG" , 0x6cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1106},
- {"SRIOMAINT0_CORE_ENABLES" , 0x200070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1107},
- {"SRIOMAINT2_CORE_ENABLES" , 0x200070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1107},
- {"SRIOMAINT3_CORE_ENABLES" , 0x200070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1107},
- {"SRIOMAINT0_DEV_ID" , 0x0ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1108},
- {"SRIOMAINT2_DEV_ID" , 0x0ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1108},
- {"SRIOMAINT3_DEV_ID" , 0x0ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1108},
- {"SRIOMAINT0_DEV_REV" , 0x4ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1109},
- {"SRIOMAINT2_DEV_REV" , 0x4ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1109},
- {"SRIOMAINT3_DEV_REV" , 0x4ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1109},
- {"SRIOMAINT0_DST_OPS" , 0x1cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1110},
- {"SRIOMAINT2_DST_OPS" , 0x1cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1110},
- {"SRIOMAINT3_DST_OPS" , 0x1cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1110},
- {"SRIOMAINT0_ERB_ATTR_CAPT" , 0x2048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1111},
- {"SRIOMAINT2_ERB_ATTR_CAPT" , 0x2048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1111},
- {"SRIOMAINT3_ERB_ATTR_CAPT" , 0x2048ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1111},
- {"SRIOMAINT0_ERB_ERR_DET" , 0x2040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1112},
- {"SRIOMAINT2_ERB_ERR_DET" , 0x2040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1112},
- {"SRIOMAINT3_ERB_ERR_DET" , 0x2040ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1112},
- {"SRIOMAINT0_ERB_ERR_RATE" , 0x2068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1113},
- {"SRIOMAINT2_ERB_ERR_RATE" , 0x2068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1113},
- {"SRIOMAINT3_ERB_ERR_RATE" , 0x2068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1113},
- {"SRIOMAINT0_ERB_ERR_RATE_EN" , 0x2044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1114},
- {"SRIOMAINT2_ERB_ERR_RATE_EN" , 0x2044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1114},
- {"SRIOMAINT3_ERB_ERR_RATE_EN" , 0x2044ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1114},
- {"SRIOMAINT0_ERB_ERR_RATE_THR" , 0x206cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1115},
- {"SRIOMAINT2_ERB_ERR_RATE_THR" , 0x206cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1115},
- {"SRIOMAINT3_ERB_ERR_RATE_THR" , 0x206cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1115},
- {"SRIOMAINT0_ERB_HDR" , 0x2000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1116},
- {"SRIOMAINT2_ERB_HDR" , 0x2000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1116},
- {"SRIOMAINT3_ERB_HDR" , 0x2000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1116},
- {"SRIOMAINT0_ERB_LT_ADDR_CAPT_H", 0x2010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1117},
- {"SRIOMAINT2_ERB_LT_ADDR_CAPT_H", 0x2010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1117},
- {"SRIOMAINT3_ERB_LT_ADDR_CAPT_H", 0x2010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1117},
- {"SRIOMAINT0_ERB_LT_ADDR_CAPT_L", 0x2014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1118},
- {"SRIOMAINT2_ERB_LT_ADDR_CAPT_L", 0x2014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1118},
- {"SRIOMAINT3_ERB_LT_ADDR_CAPT_L", 0x2014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1118},
- {"SRIOMAINT0_ERB_LT_CTRL_CAPT" , 0x201cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1119},
- {"SRIOMAINT2_ERB_LT_CTRL_CAPT" , 0x201cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1119},
- {"SRIOMAINT3_ERB_LT_CTRL_CAPT" , 0x201cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1119},
- {"SRIOMAINT0_ERB_LT_DEV_ID" , 0x2028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1120},
- {"SRIOMAINT2_ERB_LT_DEV_ID" , 0x2028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1120},
- {"SRIOMAINT3_ERB_LT_DEV_ID" , 0x2028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1120},
- {"SRIOMAINT0_ERB_LT_DEV_ID_CAPT", 0x2018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1121},
- {"SRIOMAINT2_ERB_LT_DEV_ID_CAPT", 0x2018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1121},
- {"SRIOMAINT3_ERB_LT_DEV_ID_CAPT", 0x2018ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1121},
- {"SRIOMAINT0_ERB_LT_ERR_DET" , 0x2008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1122},
- {"SRIOMAINT2_ERB_LT_ERR_DET" , 0x2008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1122},
- {"SRIOMAINT3_ERB_LT_ERR_DET" , 0x2008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1122},
- {"SRIOMAINT0_ERB_LT_ERR_EN" , 0x200cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1123},
- {"SRIOMAINT2_ERB_LT_ERR_EN" , 0x200cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1123},
- {"SRIOMAINT3_ERB_LT_ERR_EN" , 0x200cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1123},
- {"SRIOMAINT0_ERB_PACK_CAPT_1" , 0x2050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1124},
- {"SRIOMAINT2_ERB_PACK_CAPT_1" , 0x2050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1124},
- {"SRIOMAINT3_ERB_PACK_CAPT_1" , 0x2050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1124},
- {"SRIOMAINT0_ERB_PACK_CAPT_2" , 0x2054ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1125},
- {"SRIOMAINT2_ERB_PACK_CAPT_2" , 0x2054ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1125},
- {"SRIOMAINT3_ERB_PACK_CAPT_2" , 0x2054ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1125},
- {"SRIOMAINT0_ERB_PACK_CAPT_3" , 0x2058ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1126},
- {"SRIOMAINT2_ERB_PACK_CAPT_3" , 0x2058ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1126},
- {"SRIOMAINT3_ERB_PACK_CAPT_3" , 0x2058ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1126},
- {"SRIOMAINT0_ERB_PACK_SYM_CAPT", 0x204cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1127},
- {"SRIOMAINT2_ERB_PACK_SYM_CAPT", 0x204cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1127},
- {"SRIOMAINT3_ERB_PACK_SYM_CAPT", 0x204cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1127},
- {"SRIOMAINT0_HB_DEV_ID_LOCK" , 0x68ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1128},
- {"SRIOMAINT2_HB_DEV_ID_LOCK" , 0x68ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1128},
- {"SRIOMAINT3_HB_DEV_ID_LOCK" , 0x68ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1128},
- {"SRIOMAINT0_IR_BUFFER_CONFIG" , 0x102000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1129},
- {"SRIOMAINT2_IR_BUFFER_CONFIG" , 0x102000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1129},
- {"SRIOMAINT3_IR_BUFFER_CONFIG" , 0x102000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1129},
- {"SRIOMAINT0_IR_BUFFER_CONFIG2", 0x102004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1130},
- {"SRIOMAINT2_IR_BUFFER_CONFIG2", 0x102004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1130},
- {"SRIOMAINT3_IR_BUFFER_CONFIG2", 0x102004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1130},
- {"SRIOMAINT0_IR_PD_PHY_CTRL" , 0x107028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1131},
- {"SRIOMAINT2_IR_PD_PHY_CTRL" , 0x107028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1131},
- {"SRIOMAINT3_IR_PD_PHY_CTRL" , 0x107028ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1131},
- {"SRIOMAINT0_IR_PD_PHY_STAT" , 0x10702cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1132},
- {"SRIOMAINT2_IR_PD_PHY_STAT" , 0x10702cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1132},
- {"SRIOMAINT3_IR_PD_PHY_STAT" , 0x10702cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1132},
- {"SRIOMAINT0_IR_PI_PHY_CTRL" , 0x107020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1133},
- {"SRIOMAINT2_IR_PI_PHY_CTRL" , 0x107020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1133},
- {"SRIOMAINT3_IR_PI_PHY_CTRL" , 0x107020ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1133},
- {"SRIOMAINT0_IR_PI_PHY_STAT" , 0x107024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1134},
- {"SRIOMAINT2_IR_PI_PHY_STAT" , 0x107024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1134},
- {"SRIOMAINT3_IR_PI_PHY_STAT" , 0x107024ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1134},
- {"SRIOMAINT0_IR_SP_RX_CTRL" , 0x10700cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1135},
- {"SRIOMAINT2_IR_SP_RX_CTRL" , 0x10700cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1135},
- {"SRIOMAINT3_IR_SP_RX_CTRL" , 0x10700cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1135},
- {"SRIOMAINT0_IR_SP_RX_DATA" , 0x107014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1136},
- {"SRIOMAINT2_IR_SP_RX_DATA" , 0x107014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1136},
- {"SRIOMAINT3_IR_SP_RX_DATA" , 0x107014ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1136},
- {"SRIOMAINT0_IR_SP_RX_STAT" , 0x107010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1137},
- {"SRIOMAINT2_IR_SP_RX_STAT" , 0x107010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1137},
- {"SRIOMAINT3_IR_SP_RX_STAT" , 0x107010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1137},
- {"SRIOMAINT0_IR_SP_TX_CTRL" , 0x107000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1138},
- {"SRIOMAINT2_IR_SP_TX_CTRL" , 0x107000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1138},
- {"SRIOMAINT3_IR_SP_TX_CTRL" , 0x107000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1138},
- {"SRIOMAINT0_IR_SP_TX_DATA" , 0x107008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1139},
- {"SRIOMAINT2_IR_SP_TX_DATA" , 0x107008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1139},
- {"SRIOMAINT3_IR_SP_TX_DATA" , 0x107008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1139},
- {"SRIOMAINT0_IR_SP_TX_STAT" , 0x107004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1140},
- {"SRIOMAINT2_IR_SP_TX_STAT" , 0x107004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1140},
- {"SRIOMAINT3_IR_SP_TX_STAT" , 0x107004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1140},
- {"SRIOMAINT0_LANE_000_STATUS_0", 0x1010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT0_LANE_001_STATUS_0", 0x1030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT0_LANE_002_STATUS_0", 0x1050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT0_LANE_003_STATUS_0", 0x1070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT2_LANE_000_STATUS_0", 0x1010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT2_LANE_001_STATUS_0", 0x1030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT2_LANE_002_STATUS_0", 0x1050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT2_LANE_003_STATUS_0", 0x1070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT3_LANE_000_STATUS_0", 0x1010ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT3_LANE_001_STATUS_0", 0x1030ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT3_LANE_002_STATUS_0", 0x1050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT3_LANE_003_STATUS_0", 0x1070ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1141},
- {"SRIOMAINT0_LCS_BA0" , 0x58ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1142},
- {"SRIOMAINT2_LCS_BA0" , 0x58ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1142},
- {"SRIOMAINT3_LCS_BA0" , 0x58ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1142},
- {"SRIOMAINT0_LCS_BA1" , 0x5cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1143},
- {"SRIOMAINT2_LCS_BA1" , 0x5cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1143},
- {"SRIOMAINT3_LCS_BA1" , 0x5cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1143},
- {"SRIOMAINT0_M2S_BAR0_START0" , 0x200000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1144},
- {"SRIOMAINT2_M2S_BAR0_START0" , 0x200000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1144},
- {"SRIOMAINT3_M2S_BAR0_START0" , 0x200000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1144},
- {"SRIOMAINT0_M2S_BAR0_START1" , 0x200004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1145},
- {"SRIOMAINT2_M2S_BAR0_START1" , 0x200004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1145},
- {"SRIOMAINT3_M2S_BAR0_START1" , 0x200004ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1145},
- {"SRIOMAINT0_M2S_BAR1_START0" , 0x200008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1146},
- {"SRIOMAINT2_M2S_BAR1_START0" , 0x200008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1146},
- {"SRIOMAINT3_M2S_BAR1_START0" , 0x200008ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1146},
- {"SRIOMAINT0_M2S_BAR1_START1" , 0x20000cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1147},
- {"SRIOMAINT2_M2S_BAR1_START1" , 0x20000cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1147},
- {"SRIOMAINT3_M2S_BAR1_START1" , 0x20000cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1147},
- {"SRIOMAINT0_M2S_BAR2_START" , 0x200050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1148},
- {"SRIOMAINT2_M2S_BAR2_START" , 0x200050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1148},
- {"SRIOMAINT3_M2S_BAR2_START" , 0x200050ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1148},
- {"SRIOMAINT0_MAC_CTRL" , 0x200068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1149},
- {"SRIOMAINT2_MAC_CTRL" , 0x200068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1149},
- {"SRIOMAINT3_MAC_CTRL" , 0x200068ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1149},
- {"SRIOMAINT0_PE_FEAT" , 0x10ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1150},
- {"SRIOMAINT2_PE_FEAT" , 0x10ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1150},
- {"SRIOMAINT3_PE_FEAT" , 0x10ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1150},
- {"SRIOMAINT0_PE_LLC" , 0x4cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1151},
- {"SRIOMAINT2_PE_LLC" , 0x4cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1151},
- {"SRIOMAINT3_PE_LLC" , 0x4cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1151},
- {"SRIOMAINT0_PORT_0_CTL" , 0x15cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1152},
- {"SRIOMAINT2_PORT_0_CTL" , 0x15cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1152},
- {"SRIOMAINT3_PORT_0_CTL" , 0x15cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1152},
- {"SRIOMAINT0_PORT_0_CTL2" , 0x154ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1153},
- {"SRIOMAINT2_PORT_0_CTL2" , 0x154ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1153},
- {"SRIOMAINT3_PORT_0_CTL2" , 0x154ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1153},
- {"SRIOMAINT0_PORT_0_ERR_STAT" , 0x158ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1154},
- {"SRIOMAINT2_PORT_0_ERR_STAT" , 0x158ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1154},
- {"SRIOMAINT3_PORT_0_ERR_STAT" , 0x158ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1154},
- {"SRIOMAINT0_PORT_0_LINK_REQ" , 0x140ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1155},
- {"SRIOMAINT2_PORT_0_LINK_REQ" , 0x140ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1155},
- {"SRIOMAINT3_PORT_0_LINK_REQ" , 0x140ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1155},
- {"SRIOMAINT0_PORT_0_LINK_RESP" , 0x144ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1156},
- {"SRIOMAINT2_PORT_0_LINK_RESP" , 0x144ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1156},
- {"SRIOMAINT3_PORT_0_LINK_RESP" , 0x144ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1156},
- {"SRIOMAINT0_PORT_0_LOCAL_ACKID", 0x148ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1157},
- {"SRIOMAINT2_PORT_0_LOCAL_ACKID", 0x148ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1157},
- {"SRIOMAINT3_PORT_0_LOCAL_ACKID", 0x148ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1157},
- {"SRIOMAINT0_PORT_GEN_CTL" , 0x13cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1158},
- {"SRIOMAINT2_PORT_GEN_CTL" , 0x13cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1158},
- {"SRIOMAINT3_PORT_GEN_CTL" , 0x13cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1158},
- {"SRIOMAINT0_PORT_LT_CTL" , 0x120ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1159},
- {"SRIOMAINT2_PORT_LT_CTL" , 0x120ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1159},
- {"SRIOMAINT3_PORT_LT_CTL" , 0x120ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1159},
- {"SRIOMAINT0_PORT_MBH0" , 0x100ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1160},
- {"SRIOMAINT2_PORT_MBH0" , 0x100ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1160},
- {"SRIOMAINT3_PORT_MBH0" , 0x100ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1160},
- {"SRIOMAINT0_PORT_RT_CTL" , 0x124ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1161},
- {"SRIOMAINT2_PORT_RT_CTL" , 0x124ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1161},
- {"SRIOMAINT3_PORT_RT_CTL" , 0x124ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1161},
- {"SRIOMAINT0_PORT_TTL_CTL" , 0x12cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1162},
- {"SRIOMAINT2_PORT_TTL_CTL" , 0x12cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1162},
- {"SRIOMAINT3_PORT_TTL_CTL" , 0x12cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1162},
- {"SRIOMAINT0_PRI_DEV_ID" , 0x60ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1163},
- {"SRIOMAINT2_PRI_DEV_ID" , 0x60ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1163},
- {"SRIOMAINT3_PRI_DEV_ID" , 0x60ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1163},
- {"SRIOMAINT0_SEC_DEV_CTRL" , 0x200064ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1164},
- {"SRIOMAINT2_SEC_DEV_CTRL" , 0x200064ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1164},
- {"SRIOMAINT3_SEC_DEV_CTRL" , 0x200064ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1164},
- {"SRIOMAINT0_SEC_DEV_ID" , 0x200060ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1165},
- {"SRIOMAINT2_SEC_DEV_ID" , 0x200060ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1165},
- {"SRIOMAINT3_SEC_DEV_ID" , 0x200060ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1165},
- {"SRIOMAINT0_SERIAL_LANE_HDR" , 0x1000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1166},
- {"SRIOMAINT2_SERIAL_LANE_HDR" , 0x1000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1166},
- {"SRIOMAINT3_SERIAL_LANE_HDR" , 0x1000ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1166},
- {"SRIOMAINT0_SRC_OPS" , 0x18ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1167},
- {"SRIOMAINT2_SRC_OPS" , 0x18ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1167},
- {"SRIOMAINT3_SRC_OPS" , 0x18ull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1167},
- {"SRIOMAINT0_TX_DROP" , 0x20006cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1168},
- {"SRIOMAINT2_TX_DROP" , 0x20006cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1168},
- {"SRIOMAINT3_TX_DROP" , 0x20006cull, CVMX_CSR_DB_TYPE_SRIOMAINT, 32, 1168},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1169},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1170},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1171},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1172},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1173},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1174},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1175},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1176},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1177},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1178},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1179},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1180},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1181},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1182},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1183},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1184},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1185},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1186},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1187},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1188},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1189},
- {"TRA0_READ_DAT_HI" , 0x11800a8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1190},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1191},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1192},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1193},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1194},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1195},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1196},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1197},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1198},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1199},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1200},
- {"UAHC0_EHCI_ASYNCLISTADDR" , 0x16f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 1201},
- {"UAHC0_EHCI_CONFIGFLAG" , 0x16f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 1202},
- {"UAHC0_EHCI_CTRLDSSEGMENT" , 0x16f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 1203},
- {"UAHC0_EHCI_FRINDEX" , 0x16f000000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 1204},
- {"UAHC0_EHCI_HCCAPBASE" , 0x16f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 1205},
- {"UAHC0_EHCI_HCCPARAMS" , 0x16f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 1206},
- {"UAHC0_EHCI_HCSPARAMS" , 0x16f0000000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 1207},
- {"UAHC0_EHCI_INSNREG00" , 0x16f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 32, 1208},
- {"UAHC0_EHCI_INSNREG03" , 0x16f000000009cull, CVMX_CSR_DB_TYPE_NCB, 32, 1209},
- {"UAHC0_EHCI_INSNREG04" , 0x16f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 1210},
- {"UAHC0_EHCI_INSNREG06" , 0x16f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 1211},
- {"UAHC0_EHCI_INSNREG07" , 0x16f00000000ecull, CVMX_CSR_DB_TYPE_NCB, 32, 1212},
- {"UAHC0_EHCI_PERIODICLISTBASE" , 0x16f0000000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 1213},
- {"UAHC0_EHCI_PORTSC001" , 0x16f0000000054ull, CVMX_CSR_DB_TYPE_NCB, 32, 1214},
- {"UAHC0_EHCI_PORTSC002" , 0x16f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 32, 1214},
- {"UAHC0_EHCI_USBCMD" , 0x16f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 1215},
- {"UAHC0_EHCI_USBINTR" , 0x16f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 1216},
- {"UAHC0_EHCI_USBSTS" , 0x16f0000000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 1217},
- {"UAHC0_OHCI0_HCBULKCURRENTED" , 0x16f000000042cull, CVMX_CSR_DB_TYPE_NCB, 32, 1218},
- {"UAHC0_OHCI0_HCBULKHEADED" , 0x16f0000000428ull, CVMX_CSR_DB_TYPE_NCB, 32, 1219},
- {"UAHC0_OHCI0_HCCOMMANDSTATUS" , 0x16f0000000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 1220},
- {"UAHC0_OHCI0_HCCONTROL" , 0x16f0000000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 1221},
- {"UAHC0_OHCI0_HCCONTROLCURRENTED", 0x16f0000000424ull, CVMX_CSR_DB_TYPE_NCB, 32, 1222},
- {"UAHC0_OHCI0_HCCONTROLHEADED" , 0x16f0000000420ull, CVMX_CSR_DB_TYPE_NCB, 32, 1223},
- {"UAHC0_OHCI0_HCDONEHEAD" , 0x16f0000000430ull, CVMX_CSR_DB_TYPE_NCB, 32, 1224},
- {"UAHC0_OHCI0_HCFMINTERVAL" , 0x16f0000000434ull, CVMX_CSR_DB_TYPE_NCB, 32, 1225},
- {"UAHC0_OHCI0_HCFMNUMBER" , 0x16f000000043cull, CVMX_CSR_DB_TYPE_NCB, 32, 1226},
- {"UAHC0_OHCI0_HCFMREMAINING" , 0x16f0000000438ull, CVMX_CSR_DB_TYPE_NCB, 32, 1227},
- {"UAHC0_OHCI0_HCHCCA" , 0x16f0000000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 1228},
- {"UAHC0_OHCI0_HCINTERRUPTDISABLE", 0x16f0000000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 1229},
- {"UAHC0_OHCI0_HCINTERRUPTENABLE", 0x16f0000000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 1230},
- {"UAHC0_OHCI0_HCINTERRUPTSTATUS", 0x16f000000040cull, CVMX_CSR_DB_TYPE_NCB, 32, 1231},
- {"UAHC0_OHCI0_HCLSTHRESHOLD" , 0x16f0000000444ull, CVMX_CSR_DB_TYPE_NCB, 32, 1232},
- {"UAHC0_OHCI0_HCPERIODCURRENTED", 0x16f000000041cull, CVMX_CSR_DB_TYPE_NCB, 32, 1233},
- {"UAHC0_OHCI0_HCPERIODICSTART" , 0x16f0000000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 1234},
- {"UAHC0_OHCI0_HCREVISION" , 0x16f0000000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 1235},
- {"UAHC0_OHCI0_HCRHDESCRIPTORA" , 0x16f0000000448ull, CVMX_CSR_DB_TYPE_NCB, 32, 1236},
- {"UAHC0_OHCI0_HCRHDESCRIPTORB" , 0x16f000000044cull, CVMX_CSR_DB_TYPE_NCB, 32, 1237},
- {"UAHC0_OHCI0_HCRHPORTSTATUS001", 0x16f0000000454ull, CVMX_CSR_DB_TYPE_NCB, 32, 1238},
- {"UAHC0_OHCI0_HCRHPORTSTATUS002", 0x16f0000000458ull, CVMX_CSR_DB_TYPE_NCB, 32, 1238},
- {"UAHC0_OHCI0_HCRHSTATUS" , 0x16f0000000450ull, CVMX_CSR_DB_TYPE_NCB, 32, 1239},
- {"UAHC0_OHCI0_INSNREG06" , 0x16f0000000498ull, CVMX_CSR_DB_TYPE_NCB, 32, 1240},
- {"UAHC0_OHCI0_INSNREG07" , 0x16f000000049cull, CVMX_CSR_DB_TYPE_NCB, 32, 1241},
- {"UCTL0_BIST_STATUS" , 0x118006f0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1242},
- {"UCTL0_CLK_RST_CTL" , 0x118006f000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1243},
- {"UCTL0_EHCI_CTL" , 0x118006f000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1244},
- {"UCTL0_EHCI_FLA" , 0x118006f0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1245},
- {"UCTL0_ERTO_CTL" , 0x118006f000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1246},
- {"UCTL0_IF_ENA" , 0x118006f000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1247},
- {"UCTL0_INT_ENA" , 0x118006f000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1248},
- {"UCTL0_INT_REG" , 0x118006f000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1249},
- {"UCTL0_OHCI_CTL" , 0x118006f000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1250},
- {"UCTL0_ORTO_CTL" , 0x118006f000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1251},
- {"UCTL0_PPAF_WM" , 0x118006f000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1252},
- {"UCTL0_UPHY_CTL_STATUS" , 0x118006f000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1253},
- {"UCTL0_UPHY_PORT000_CTL_STATUS", 0x118006f000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1254},
- {"UCTL0_UPHY_PORT001_CTL_STATUS", 0x118006f000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1254},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1255},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1256},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"ZIP_THROTTLE" , 0x1180038000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1262},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn66xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_21" , 4, 18, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_24_25" , 24, 2, 0, "RAZ", 1, 1, 0, 0},
- {"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRFLW1" , 35, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP1" , 36, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH1" , 37, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 0, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"RX_EN" , 4, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"TX_EN" , 5, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"BURST" , 6, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 2, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 2, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 2, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 2, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 3, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 4, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 9, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 10, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 10, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 10, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 10, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 11, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 12, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 13, "RO", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 7, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"NULL_DIS" , 10, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 13, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 13, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 14, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 14, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 15, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 15, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 16, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 16, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 17, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 18, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 19, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 19, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 20, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 20, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 21, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 21, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 21, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 22, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 22, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 23, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 23, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 27, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 27, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 32, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 32, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 33, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 33, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 34, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 35, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 35, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 36, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 36, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 37, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 37, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 38, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 38, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 39, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 39, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 40, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 41, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 60, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 2, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 61, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 64, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 64, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 64, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 64, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 64, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 64, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 65, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 65, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 65, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 65, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 65, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 65, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 68, "RAZ", 1, 1, 0, 0},
- {"BP" , 4, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 68, "RAZ", 1, 1, 0, 0},
- {"EN" , 8, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 68, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 1, 71, "R/W", 0, 1, 1ull, 0},
- {"CLKRST" , 1, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"ENABLE" , 2, 1, 71, "R/W", 0, 0, 1ull, 1ull},
- {"COMP" , 3, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"DLLRST" , 4, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_SET" , 8, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_14" , 13, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_BYP" , 15, 1, 71, "R/W", 0, 1, 1ull, 0},
- {"CLKRX_SET" , 16, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_22" , 21, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKRX_BYP" , 23, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"CLK_SET" , 24, 5, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_NCTL" , 32, 6, 71, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_38_39" , 38, 2, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_PCTL" , 40, 6, 71, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_46_47" , 46, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_NCTL" , 48, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_54_55" , 54, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_PCTL" , 56, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_BYP" , 63, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"BIST" , 0, 6, 72, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 72, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"GMX1" , 2, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 3, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 6, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 7, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_8" , 8, 1, 73, "RAZ", 1, 1, 0, 0},
- {"IPD" , 9, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 14, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 73, "RAZ", 1, 1, 0, 0},
- {"L2C" , 16, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 17, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 73, "RAZ", 1, 1, 0, 0},
- {"PIP" , 20, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 73, "RAZ", 1, 1, 0, 0},
- {"ASXPCS0" , 22, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"ASXPCS1" , 23, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_24" , 24, 1, 73, "RAZ", 1, 1, 0, 0},
- {"PEM0" , 25, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 26, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 73, "RAZ", 1, 1, 0, 0},
- {"AGL" , 28, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_29" , 29, 1, 73, "RAZ", 1, 1, 0, 0},
- {"IOB" , 30, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 73, "RAZ", 1, 1, 0, 0},
- {"SRIO0" , 32, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 73, "RAZ", 1, 1, 0, 0},
- {"DFM" , 40, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 41, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 42, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_43_59" , 43, 17, 73, "RAZ", 1, 1, 0, 0},
- {"SRIO2" , 60, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 73, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 10, 74, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 74, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 75, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 75, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 75, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 76, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 76, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 76, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 77, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 77, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 77, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 78, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 78, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 78, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 79, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 79, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 79, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 80, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 80, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 80, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 81, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 81, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 81, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 82, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 82, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 82, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 83, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 83, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 83, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 84, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 84, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 84, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 85, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 85, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 85, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 86, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 86, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 86, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 10, 87, "RO", 1, 1, 0, 0},
- {"RESERVED_10_63" , 10, 54, 87, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 88, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 89, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 89, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 89, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 89, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 89, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 89, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 89, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 89, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 89, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 89, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_57" , 57, 1, 89, "RAZ", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 89, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 90, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 90, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_57" , 57, 1, 90, "RAZ", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 90, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 91, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 91, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_57" , 57, 1, 91, "RAZ", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 91, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 10, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 92, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 92, "R/W", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 92, "R/W", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 92, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO2" , 60, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 10, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 93, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO2" , 60, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 93, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 10, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 94, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO2" , 60, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 94, "R/W1", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 95, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 95, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 95, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 95, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 95, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 95, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 95, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 95, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 95, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 95, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_57" , 57, 1, 95, "RAZ", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 95, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 96, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 96, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_57" , 57, 1, 96, "RAZ", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 96, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 97, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 97, "RAZ", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_57" , 57, 1, 97, "RAZ", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 97, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 10, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 98, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 98, "R/W", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 98, "R/W", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 98, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO2" , 60, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 10, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 99, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO2" , 60, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 99, "R/W1", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 99, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 10, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 100, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"AGL" , 46, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"LMC0" , 52, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"DFM" , 56, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO2" , 60, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"RST" , 63, 1, 100, "R/W1", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 101, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 101, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 101, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 101, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 101, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 101, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"SUM2" , 51, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_57" , 57, 1, 101, "RAZ", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 101, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 102, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 102, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 102, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 102, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 102, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 102, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 102, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 102, "R/W1C", 0, 0, 0ull, 0ull},
- {"SUM2" , 51, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 102, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_57" , 57, 1, 102, "RAZ", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 102, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 102, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 103, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 103, "RO", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 103, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 103, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 103, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 103, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 2, 103, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 50, 1, 103, "R/W1C", 0, 0, 0ull, 0ull},
- {"SUM2" , 51, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 103, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_57" , 57, 1, 103, "RAZ", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 103, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"MII" , 62, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 63, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"PP" , 0, 4, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_7" , 4, 4, 104, "RAZ", 1, 1, 0, 0},
- {"IRQ" , 8, 2, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 104, "RAZ", 1, 1, 0, 0},
- {"SEL" , 16, 3, 104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_19_63" , 19, 45, 104, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 10, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 105, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 105, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 105, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 105, "RAZ", 1, 1, 0, 0},
- {"DFM" , 56, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 105, "RAZ", 1, 1, 0, 0},
- {"SRIO2" , 60, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 105, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 105, "RO", 0, 0, 0ull, 0ull},
- {"BITS" , 0, 32, 106, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 106, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 107, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 10, 108, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 108, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 109, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 109, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 10, 110, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 110, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 111, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 112, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 9, 112, "R/W", 0, 0, 511ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 112, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 113, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 113, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 113, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 113, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 113, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 113, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 113, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 113, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 114, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 114, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 114, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 114, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 114, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 114, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 114, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 114, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 114, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 115, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 115, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 115, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 115, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 115, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 115, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 115, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 115, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 3, 116, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 116, "RAZ", 1, 1, 0, 0},
- {"MUX_SEL" , 4, 2, 116, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 116, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 116, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 116, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 117, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 117, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_39" , 37, 3, 117, "RAZ", 1, 1, 0, 0},
- {"SELECT" , 40, 3, 117, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_60" , 43, 18, 117, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 117, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 117, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 117, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 118, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 118, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 119, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 119, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 120, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 120, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 121, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 121, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 122, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 122, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 123, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 123, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 10, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 124, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 124, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 124, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 124, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 124, "RAZ", 1, 1, 0, 0},
- {"DFM" , 56, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 124, "RAZ", 1, 1, 0, 0},
- {"SRIO2" , 60, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 124, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 124, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 10, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 125, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 125, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 125, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 125, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 125, "RAZ", 1, 1, 0, 0},
- {"DFM" , 56, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 125, "RAZ", 1, 1, 0, 0},
- {"SRIO2" , 60, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 125, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 125, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 10, 126, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 126, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 126, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 126, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 126, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 126, "RAZ", 1, 1, 0, 0},
- {"DFM" , 56, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 126, "RAZ", 1, 1, 0, 0},
- {"SRIO2" , 60, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 126, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 126, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 10, 127, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_17" , 10, 8, 127, "RAZ", 1, 1, 0, 0},
- {"MII1" , 18, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"NAND" , 19, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"ZIP" , 28, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 29, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"DFA" , 32, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 33, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"AGX1" , 37, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_45" , 38, 8, 127, "RAZ", 1, 1, 0, 0},
- {"AGL" , 46, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 47, 1, 127, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"SRIO0" , 50, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 127, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_55" , 53, 3, 127, "RAZ", 1, 1, 0, 0},
- {"DFM" , 56, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_57_59" , 57, 3, 127, "RAZ", 1, 1, 0, 0},
- {"SRIO2" , 60, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"SRIO3" , 61, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 127, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 127, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 128, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 128, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 129, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 129, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 129, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 130, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 130, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 130, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 131, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 131, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 132, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 132, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 132, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 133, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 134, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 134, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 134, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 134, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 134, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 134, "RAZ", 1, 1, 0, 0},
- {"PDB" , 0, 1, 135, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 135, "RAZ", 0, 0, 0ull, 0ull},
- {"RDF" , 4, 1, 135, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 135, "RAZ", 0, 0, 0ull, 0ull},
- {"DTX" , 8, 2, 135, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 135, "RAZ", 0, 0, 0ull, 0ull},
- {"STX" , 16, 2, 135, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_23" , 18, 6, 135, "RAZ", 0, 0, 0ull, 0ull},
- {"GFB" , 24, 1, 135, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 135, "RAZ", 0, 0, 0ull, 0ull},
- {"MWB" , 28, 1, 135, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 135, "RAZ", 0, 0, 0ull, 0ull},
- {"GFU" , 0, 1, 136, "RO", 0, 0, 0ull, 0ull},
- {"GIB" , 1, 1, 136, "RO", 0, 0, 0ull, 0ull},
- {"GIF" , 2, 1, 136, "RO", 0, 0, 0ull, 0ull},
- {"NCD" , 3, 1, 136, "RO", 0, 0, 0ull, 0ull},
- {"GUTP" , 4, 1, 136, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 136, "RAZ", 0, 0, 0ull, 0ull},
- {"GUTV" , 8, 1, 136, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 9, 1, 136, "RO", 0, 0, 0ull, 0ull},
- {"RAM1" , 10, 1, 136, "RO", 0, 0, 0ull, 0ull},
- {"RAM2" , 11, 1, 136, "RO", 0, 0, 0ull, 0ull},
- {"RAM3" , 12, 1, 136, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 136, "RAZ", 0, 0, 0ull, 0ull},
- {"DTECLKDIS" , 0, 1, 137, "R/W", 0, 0, 1ull, 0ull},
- {"CLDTECRIP" , 1, 3, 137, "R/W", 0, 0, 0ull, 0ull},
- {"CLMSKCRIP" , 4, 4, 137, "R/W", 0, 0, 0ull, 0ull},
- {"REPL_ENA" , 8, 1, 137, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 137, "RAZ", 1, 1, 0, 0},
- {"IMODE" , 0, 1, 138, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 1, 1, 138, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 2, 1, 138, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_4" , 3, 2, 138, "RAZ", 1, 1, 0, 0},
- {"SBDLCK" , 5, 1, 138, "R/W", 0, 0, 0ull, 0ull},
- {"SBDNUM" , 6, 4, 138, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 138, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 20, 139, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 139, "RAZ", 1, 1, 0, 0},
- {"SBD0" , 0, 64, 140, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 141, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 142, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 143, "RO", 1, 1, 0, 0},
- {"SIZE" , 0, 9, 144, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 144, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 144, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_20_63" , 20, 44, 144, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 145, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 35, 145, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 145, "RAZ", 1, 1, 0, 0},
- {"RAM1FADR" , 0, 14, 146, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 146, "RAZ", 1, 1, 0, 0},
- {"RAM2FADR" , 16, 9, 146, "RO", 1, 1, 0, 0},
- {"RESERVED_25_31" , 25, 7, 146, "RAZ", 1, 1, 0, 0},
- {"RAM3FADR" , 32, 12, 146, "RO", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 146, "RAZ", 1, 1, 0, 0},
- {"DBLOVF" , 0, 1, 147, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC0PERR" , 1, 3, 147, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 147, "RAZ", 1, 1, 0, 0},
- {"CNDRD" , 16, 1, 147, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 147, "RAZ", 1, 1, 0, 0},
- {"DBLINA" , 0, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"DC0PENA" , 1, 3, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 148, "RAZ", 1, 1, 0, 0},
- {"HIDAT" , 0, 64, 149, "R/W", 1, 1, 0, 0},
- {"PFCNT0" , 0, 64, 150, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 151, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 151, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 151, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 151, "RAZ", 1, 1, 0, 0},
- {"PFCNT1" , 0, 64, 152, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 153, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 153, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 153, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 153, "RAZ", 1, 1, 0, 0},
- {"PFCNT2" , 0, 64, 154, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 155, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 155, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 155, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 155, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 155, "RAZ", 1, 1, 0, 0},
- {"PFCNT3" , 0, 64, 156, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 157, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 157, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 157, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 157, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 157, "RAZ", 1, 1, 0, 0},
- {"CNT0ENA" , 0, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 1, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 2, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 3, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0WCLR" , 4, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1WCLR" , 5, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2WCLR" , 6, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3WCLR" , 7, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RCLR" , 8, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RCLR" , 9, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RCLR" , 10, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RCLR" , 11, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"SNODE" , 12, 3, 158, "R/W", 0, 0, 0ull, 0ull},
- {"ENODE" , 15, 3, 158, "R/W", 0, 0, 0ull, 0ull},
- {"EDNODE" , 18, 2, 158, "R/W", 0, 0, 0ull, 0ull},
- {"PMODE" , 20, 1, 158, "R/W", 0, 0, 0ull, 0ull},
- {"VGID" , 21, 8, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 158, "RAZ", 1, 1, 0, 0},
- {"PRBS" , 0, 32, 159, "R/W", 1, 1, 0, 0},
- {"PROG" , 32, 8, 159, "R/W", 1, 1, 0, 0},
- {"SEL" , 40, 1, 159, "R/W", 1, 1, 0, 0},
- {"EN" , 41, 1, 159, "R/W", 1, 1, 0, 0},
- {"SKEW_ON" , 42, 1, 159, "R/W", 1, 1, 0, 0},
- {"DR" , 43, 1, 159, "R/W", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 159, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 16, 160, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 160, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 16, 161, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 161, "R/W", 1, 1, 0, 0},
- {"CKE_MASK" , 0, 2, 162, "R/W", 1, 1, 0, 0},
- {"CS0_N_MASK" , 2, 2, 162, "R/W", 1, 1, 0, 0},
- {"CS1_N_MASK" , 4, 2, 162, "R/W", 1, 1, 0, 0},
- {"ODT0_MASK" , 6, 2, 162, "R/W", 1, 1, 0, 0},
- {"ODT1_MASK" , 8, 2, 162, "R/W", 1, 1, 0, 0},
- {"RAS_N_MASK" , 10, 1, 162, "R/W", 1, 1, 0, 0},
- {"CAS_N_MASK" , 11, 1, 162, "R/W", 1, 1, 0, 0},
- {"WE_N_MASK" , 12, 1, 162, "R/W", 1, 1, 0, 0},
- {"BA_MASK" , 13, 3, 162, "R/W", 1, 1, 0, 0},
- {"A_MASK" , 16, 16, 162, "R/W", 1, 1, 0, 0},
- {"RESET_N_MASK" , 32, 1, 162, "R/W", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 162, "R/W", 1, 1, 0, 0},
- {"DQX_CTL" , 0, 4, 163, "R/W", 0, 1, 4ull, 0},
- {"CK_CTL" , 4, 4, 163, "R/W", 0, 1, 4ull, 0},
- {"CMD_CTL" , 8, 4, 163, "R/W", 0, 1, 4ull, 0},
- {"RODT_CTL" , 12, 4, 163, "R/W", 0, 1, 0ull, 0},
- {"NTUNE" , 16, 4, 163, "R/W", 0, 1, 0ull, 0},
- {"PTUNE" , 20, 4, 163, "R/W", 0, 1, 0ull, 0},
- {"BYP" , 24, 1, 163, "R/W", 0, 1, 0ull, 0},
- {"M180" , 25, 1, 163, "R/W", 0, 1, 0ull, 0},
- {"DDR__NTUNE" , 26, 4, 163, "RO", 1, 1, 0, 0},
- {"DDR__PTUNE" , 30, 4, 163, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 163, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 164, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 164, "R/W", 0, 0, 0ull, 0ull},
- {"ROW_LSB" , 2, 3, 164, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 164, "R/W", 0, 1, 5ull, 0},
- {"IDLEPOWER" , 9, 3, 164, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 12, 4, 164, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 16, 1, 164, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 164, "R/W", 0, 1, 0ull, 0},
- {"REF_ZQCS_INT" , 18, 19, 164, "R/W", 1, 1, 0, 0},
- {"SEQUENCE" , 37, 3, 164, "R/W", 0, 0, 0ull, 0ull},
- {"EARLY_DQX" , 40, 1, 164, "R/W", 0, 0, 0ull, 0ull},
- {"SREF_WITH_DLL" , 41, 1, 164, "R/W", 0, 0, 0ull, 0ull},
- {"RANK_ENA" , 42, 1, 164, "R/W", 0, 1, 0ull, 0},
- {"RANKMASK" , 43, 4, 164, "R/W", 0, 1, 0ull, 0},
- {"MIRRMASK" , 47, 4, 164, "R/W", 0, 1, 0ull, 0},
- {"INIT_STATUS" , 51, 4, 164, "R/W1", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R0" , 55, 1, 164, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R1" , 56, 1, 164, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R0" , 57, 1, 164, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R1" , 58, 1, 164, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_59_63" , 59, 5, 164, "RAZ", 1, 1, 0, 0},
- {"RDIMM_ENA" , 0, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"BWCNT" , 1, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 2, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"POCAS" , 3, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH2" , 4, 2, 165, "R/W", 0, 0, 0ull, 1ull},
- {"THROTTLE_RD" , 6, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"THROTTLE_WR" , 7, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_RD" , 8, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_WR" , 9, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"ELEV_PRIO_DIS" , 10, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"NXM_WRITE_EN" , 11, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 12, 4, 165, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 16, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"AUTO_FCLKDIS" , 17, 1, 165, "R/W", 0, 0, 0ull, 1ull},
- {"INT_ZQCS_DIS" , 18, 1, 165, "R/W", 0, 0, 1ull, 0ull},
- {"EXT_ZQCS_DIS" , 19, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 20, 2, 165, "R/W", 0, 0, 0ull, 0ull},
- {"WODT_BPRCH" , 22, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_BPRCH" , 23, 1, 165, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 165, "RAZ", 1, 1, 0, 0},
- {"BYP_SETTING" , 0, 8, 166, "R/W", 0, 0, 0ull, 0ull},
- {"BYP_SEL" , 8, 4, 166, "R/W", 0, 0, 0ull, 0ull},
- {"QUAD_DLL_ENA" , 12, 1, 166, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 13, 1, 166, "R/W", 0, 0, 1ull, 0ull},
- {"DLL_BRINGUP" , 14, 1, 166, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 166, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 167, "R/W", 0, 0, 0ull, 0ull},
- {"BYTE_SEL" , 6, 4, 167, "R/W", 0, 0, 0ull, 0ull},
- {"MODE_SEL" , 10, 2, 167, "R/W", 0, 0, 0ull, 0ull},
- {"LOAD_OFFSET" , 12, 1, 167, "WR0", 0, 0, 0ull, 0ull},
- {"OFFSET_ENA" , 13, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYTE_SEL" , 14, 4, 167, "R/W", 0, 0, 1ull, 1ull},
- {"DLL_MODE" , 18, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"FINE_TUNE_MODE" , 19, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_SETTING" , 20, 8, 167, "RO", 1, 1, 0, 0},
- {"DLL_FAST" , 28, 1, 167, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 167, "RAZ", 1, 1, 0, 0},
- {"FCLKCNT" , 0, 64, 168, "RO", 0, 1, 0ull, 0},
- {"MWB" , 0, 1, 169, "RO", 0, 0, 0ull, 0ull},
- {"RPB" , 1, 1, 169, "RO", 0, 0, 0ull, 0ull},
- {"MFF" , 2, 1, 169, "RO", 0, 0, 0ull, 0ull},
- {"MRQ" , 3, 1, 169, "RO", 0, 0, 0ull, 0ull},
- {"CAB" , 4, 1, 169, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 169, "RAZ", 1, 1, 0, 0},
- {"DFR_ENA" , 0, 1, 170, "R/W", 0, 0, 0ull, 1ull},
- {"RECC_ENA" , 1, 1, 170, "R/W", 0, 0, 0ull, 1ull},
- {"WECC_ENA" , 2, 1, 170, "R/W", 0, 0, 0ull, 1ull},
- {"SBE_ENA" , 3, 1, 170, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 170, "RAZ", 1, 1, 0, 0},
- {"SBE_INTENA" , 0, 1, 171, "R/W", 0, 0, 0ull, 1ull},
- {"DBE_INTENA" , 1, 1, 171, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 171, "RAZ", 1, 1, 0, 0},
- {"SCLKDIS" , 0, 1, 172, "R/W", 0, 0, 1ull, 0ull},
- {"BIST_START" , 1, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 2, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 172, "RAZ", 1, 1, 0, 0},
- {"SBE_ERR" , 0, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE_ERR" , 1, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 173, "RAZ", 1, 1, 0, 0},
- {"FADR" , 4, 28, 173, "RO", 0, 0, 0ull, 0ull},
- {"FSYN" , 32, 10, 173, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_42_63" , 42, 22, 173, "RAZ", 1, 1, 0, 0},
- {"IFBCNT" , 0, 64, 174, "RO", 0, 1, 1ull, 0},
- {"CWL" , 0, 3, 175, "R/W", 0, 0, 0ull, 0ull},
- {"MPRLOC" , 3, 2, 175, "R/W", 0, 0, 0ull, 0ull},
- {"MPR" , 5, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"DLL" , 6, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"AL" , 7, 2, 175, "R/W", 0, 0, 0ull, 0ull},
- {"WLEV" , 9, 1, 175, "RO", 0, 0, 0ull, 0ull},
- {"TDQS" , 10, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"QOFF" , 11, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"BL" , 12, 2, 175, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 14, 4, 175, "R/W", 0, 0, 2ull, 2ull},
- {"RBT" , 18, 1, 175, "RO", 0, 0, 1ull, 1ull},
- {"TM" , 19, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"DLLR" , 20, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"WRP" , 21, 3, 175, "R/W", 0, 0, 0ull, 0ull},
- {"PPD" , 24, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 175, "RAZ", 1, 1, 0, 0},
- {"PASR_00" , 0, 3, 176, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_00" , 3, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_00" , 4, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_00" , 5, 2, 176, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_00" , 7, 2, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_00" , 9, 3, 176, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_01" , 12, 3, 176, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_01" , 15, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_01" , 16, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_01" , 17, 2, 176, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_01" , 19, 2, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_01" , 21, 3, 176, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_10" , 24, 3, 176, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_10" , 27, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_10" , 28, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_10" , 29, 2, 176, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_10" , 31, 2, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_10" , 33, 3, 176, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_11" , 36, 3, 176, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_11" , 39, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_11" , 40, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_11" , 41, 2, 176, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_11" , 43, 2, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_11" , 45, 3, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 176, "RAZ", 1, 1, 0, 0},
- {"OPSCNT" , 0, 64, 177, "RO", 0, 1, 1ull, 0},
- {"TS_STAGGER" , 0, 1, 178, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK_POS" , 1, 1, 178, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK" , 2, 1, 178, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT0" , 3, 4, 178, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE0" , 7, 1, 178, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT1" , 8, 4, 178, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE1" , 12, 1, 178, "R/W", 0, 1, 0ull, 0},
- {"LV_MODE" , 13, 1, 178, "R/W", 0, 1, 0ull, 0},
- {"RX_ALWAYS_ON" , 14, 1, 178, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 178, "RAZ", 1, 1, 0, 0},
- {"DDR3RST" , 0, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PWARM" , 1, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSOFT" , 2, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSV" , 3, 1, 179, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 179, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 180, "R/W", 0, 1, 0ull, 0},
- {"OFFSET" , 4, 4, 180, "R/W", 0, 0, 2ull, 2ull},
- {"OFFSET_EN" , 8, 1, 180, "R/W", 0, 0, 1ull, 1ull},
- {"OR_DIS" , 9, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 10, 8, 180, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_0" , 18, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_1" , 19, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_2" , 20, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_3" , 21, 1, 180, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 180, "RAZ", 1, 1, 0, 0},
- {"BITMASK" , 0, 64, 181, "RO", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 6, 182, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 6, 6, 182, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_53" , 12, 42, 182, "R/W", 1, 1, 0, 0},
- {"STATUS" , 54, 2, 182, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 182, "RAZ", 1, 1, 0, 0},
- {"RODT_D0_R0" , 0, 8, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D0_R1" , 8, 8, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D1_R0" , 16, 8, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D1_R1" , 24, 8, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R0" , 32, 8, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R1" , 40, 8, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R0" , 48, 8, 183, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R1" , 56, 8, 183, "R/W", 0, 0, 0ull, 0ull},
- {"R2R_INIT" , 0, 6, 184, "R/W", 0, 1, 1ull, 0},
- {"R2W_INIT" , 6, 6, 184, "R/W", 0, 1, 6ull, 0},
- {"W2R_INIT" , 12, 6, 184, "R/W", 0, 1, 9ull, 0},
- {"W2W_INIT" , 18, 6, 184, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_24_63" , 24, 40, 184, "RAZ", 1, 1, 0, 0},
- {"R2R_XRANK_INIT" , 0, 6, 185, "R/W", 0, 1, 3ull, 0},
- {"R2W_XRANK_INIT" , 6, 6, 185, "R/W", 0, 1, 6ull, 0},
- {"W2R_XRANK_INIT" , 12, 6, 185, "R/W", 0, 1, 4ull, 0},
- {"W2W_XRANK_INIT" , 18, 6, 185, "R/W", 0, 1, 5ull, 0},
- {"RESERVED_24_63" , 24, 40, 185, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_9" , 0, 10, 186, "RAZ", 1, 1, 0, 0},
- {"TZQCS" , 10, 4, 186, "R/W", 0, 0, 4ull, 4ull},
- {"TCKE" , 14, 4, 186, "R/W", 0, 0, 3ull, 3ull},
- {"TXPR" , 18, 4, 186, "R/W", 0, 0, 5ull, 5ull},
- {"TMRD" , 22, 4, 186, "R/W", 0, 0, 4ull, 4ull},
- {"TMOD" , 26, 4, 186, "R/W", 0, 0, 12ull, 12ull},
- {"TDLLK" , 30, 4, 186, "R/W", 0, 0, 2ull, 2ull},
- {"TZQINIT" , 34, 4, 186, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 38, 4, 186, "R/W", 0, 0, 6ull, 6ull},
- {"TCKSRE" , 42, 4, 186, "R/W", 0, 0, 5ull, 5ull},
- {"TRP_EXT" , 46, 1, 186, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 186, "RAZ", 1, 1, 0, 0},
- {"TMPRR" , 0, 4, 187, "R/W", 0, 0, 1ull, 1ull},
- {"TRAS" , 4, 5, 187, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 9, 4, 187, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 13, 4, 187, "R/W", 0, 0, 2ull, 2ull},
- {"TRFC" , 17, 5, 187, "R/W", 0, 0, 6ull, 7ull},
- {"TRRD" , 22, 3, 187, "R/W", 0, 0, 2ull, 2ull},
- {"TXP" , 25, 3, 187, "R/W", 0, 0, 3ull, 3ull},
- {"TWLMRD" , 28, 4, 187, "R/W", 0, 0, 10ull, 10ull},
- {"TWLDQSEN" , 32, 4, 187, "R/W", 0, 0, 7ull, 7ull},
- {"TFAW" , 36, 5, 187, "R/W", 0, 0, 0ull, 9ull},
- {"TXPDLL" , 41, 5, 187, "R/W", 0, 0, 0ull, 10ull},
- {"TRAS_EXT" , 46, 1, 187, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 187, "RAZ", 1, 1, 0, 0},
- {"LANEMASK" , 0, 9, 188, "R/W", 0, 1, 0ull, 0},
- {"SSET" , 9, 1, 188, "R/W", 0, 1, 0ull, 0},
- {"OR_DIS" , 10, 1, 188, "R/W", 0, 1, 0ull, 0},
- {"BITMASK" , 11, 8, 188, "R/W", 0, 1, 0ull, 0},
- {"RTT_NOM" , 19, 3, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 188, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 189, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 4, 8, 189, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 189, "RAZ", 1, 1, 0, 0},
- {"BYTE0" , 0, 5, 190, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 5, 5, 190, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_44" , 10, 35, 190, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 45, 2, 190, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_63" , 47, 17, 190, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 191, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D0_R1" , 8, 8, 191, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R0" , 16, 8, 191, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D1_R1" , 24, 8, 191, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R0" , 32, 8, 191, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D2_R1" , 40, 8, 191, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R0" , 48, 8, 191, "R/W", 0, 0, 255ull, 255ull},
- {"WODT_D3_R1" , 56, 8, 191, "R/W", 0, 0, 255ull, 255ull},
- {"BIST" , 0, 47, 192, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 192, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 193, "R/W", 0, 0, 0ull, 1ull},
- {"CLK" , 1, 1, 193, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 193, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 194, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 194, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 195, "WO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 195, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 196, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 197, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 29, 197, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 197, "RAZ", 1, 1, 0, 0},
- {"IDLE" , 40, 1, 197, "RO", 0, 1, 1ull, 0},
- {"RESERVED_41_47" , 41, 7, 197, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 48, 14, 197, "R/W", 0, 1, 64ull, 0},
- {"RESERVED_62_63" , 62, 2, 197, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 3, 198, "R/W", 0, 0, 6ull, 6ull},
- {"RESERVED_3_63" , 3, 61, 198, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 199, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 199, "RAZ", 1, 1, 0, 0},
- {"STATE" , 0, 64, 200, "RO", 0, 1, 0ull, 0},
- {"STATE" , 0, 64, 201, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_13" , 0, 14, 202, "RAZ", 1, 1, 0, 0},
- {"O_MODE" , 14, 1, 202, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 202, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 202, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 202, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 202, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 202, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 202, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 202, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_47" , 34, 14, 202, "RAZ", 1, 1, 0, 0},
- {"DMA_ENB" , 48, 6, 202, "R/W", 0, 0, 0ull, 63ull},
- {"RESERVED_54_55" , 54, 2, 202, "RAZ", 1, 1, 0, 0},
- {"PKT_EN" , 56, 1, 202, "R/W", 0, 1, 0ull, 0},
- {"PKT_HP" , 57, 1, 202, "RO", 0, 0, 0ull, 0ull},
- {"COMMIT_MODE" , 58, 1, 202, "R/W", 0, 0, 0ull, 1ull},
- {"FFP_DIS" , 59, 1, 202, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_EN1" , 60, 1, 202, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_61_63" , 61, 3, 202, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 203, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 203, "RAZ", 1, 1, 0, 0},
- {"BLKS" , 0, 4, 204, "R/W", 0, 1, 2ull, 0},
- {"BASE" , 4, 5, 204, "RO", 1, 1, 0, 0},
- {"RESERVED_9_31" , 9, 23, 204, "RAZ", 1, 1, 0, 0},
- {"COMPBLKS" , 32, 5, 204, "RO", 1, 1, 0, 0},
- {"RESERVED_37_63" , 37, 27, 204, "RAZ", 1, 1, 0, 0},
- {"RSL" , 0, 1, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB" , 1, 1, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 205, "RAZ", 1, 1, 0, 0},
- {"FFP" , 4, 4, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 205, "RAZ", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 206, "R/W", 0, 0, 0ull, 0ull},
- {"DMADBO" , 8, 8, 206, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 206, "R/W", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT2_RST" , 26, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT3_RST" , 27, 1, 206, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 206, "RAZ", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 207, "RAZ", 1, 1, 0, 0},
- {"DMADBO" , 8, 8, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 207, "RAZ", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT2_RST" , 26, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT3_RST" , 27, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 207, "RAZ", 1, 1, 0, 0},
- {"MOLR" , 0, 6, 208, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 208, "RAZ", 1, 1, 0, 0},
- {"SINFO" , 0, 6, 209, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 209, "RAZ", 1, 1, 0, 0},
- {"IINFO" , 8, 6, 209, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 209, "RAZ", 1, 1, 0, 0},
- {"PKTERR" , 0, 1, 210, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 210, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 211, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 211, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 212, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 212, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 213, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 213, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 214, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 214, "RAZ", 1, 1, 0, 0},
- {"EN_RSP" , 0, 8, 215, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 215, "RAZ", 1, 1, 0, 0},
- {"EN_RST" , 16, 8, 215, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 215, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 216, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 216, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 2, 217, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 217, "RAZ", 1, 1, 0, 0},
- {"MRRS_LIM" , 3, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"MPS" , 4, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 217, "RAZ", 1, 1, 0, 0},
- {"MPS_LIM" , 7, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"MOLR" , 8, 6, 217, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 217, "RAZ", 1, 1, 0, 0},
- {"RD_MODE" , 16, 1, 217, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 217, "RAZ", 1, 1, 0, 0},
- {"QLM_CFG" , 20, 4, 217, "RO", 1, 1, 0, 0},
- {"HALT" , 24, 1, 217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 217, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 218, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 218, "RO", 0, 1, 0ull, 0},
- {"REQQ" , 0, 3, 219, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 219, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 4, 1, 219, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 219, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 8, 1, 219, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 219, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 220, "RO", 0, 1, 0ull, 0},
- {"POOL" , 33, 5, 220, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 220, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 221, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 222, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 222, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OFF" , 18, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"RET_OFF" , 19, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"FREE_EN" , 20, 1, 222, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 222, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 223, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 223, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 223, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 224, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 224, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 225, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 225, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 225, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 226, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 226, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"RES_44" , 44, 5, 227, "R/W", 0, 0, 0ull, 0ull},
- {"PADDR_E" , 49, 1, 227, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_63" , 50, 14, 227, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_48" , 44, 5, 228, "RAZ", 1, 1, 0, 0},
- {"PADDR_E" , 49, 1, 228, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_50_63" , 50, 14, 228, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 32, 229, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 229, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 230, "R/W", 0, 1, 8589934591ull, 0},
- {"RESERVED_33_63" , 33, 31, 230, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 231, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 231, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 29, 232, "R/W", 0, 0, 536870911ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 232, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 233, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 233, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 234, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 234, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 235, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 235, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 235, "RO", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 236, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 236, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 236, "RO", 0, 0, 0ull, 7ull},
- {"THRESH" , 0, 32, 237, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 237, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 238, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 238, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 238, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 238, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 238, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 238, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 238, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 239, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 240, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 240, "RAZ", 1, 1, 0, 0},
- {"LOGL_EN" , 0, 16, 241, "R/W", 0, 1, 65535ull, 0},
- {"PHYS_EN" , 16, 1, 241, "R/W", 0, 1, 1ull, 0},
- {"HG2RX_EN" , 17, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"HG2TX_EN" , 18, 1, 241, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 241, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 242, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 242, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 242, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 1, 242, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 242, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 4, 242, "RO", 1, 1, 0, 0},
- {"RESERVED_12_15" , 12, 4, 242, "RAZ", 1, 1, 0, 0},
- {"RATE" , 16, 4, 242, "R/W", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 242, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 243, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 243, "RAZ", 1, 1, 0, 0},
- {"RX_EN" , 0, 1, 244, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EN" , 1, 1, 244, "R/W", 0, 0, 0ull, 0ull},
- {"DRP_EN" , 2, 1, 244, "R/W", 0, 0, 0ull, 0ull},
- {"BCK_EN" , 3, 1, 244, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 244, "RAZ", 1, 1, 0, 0},
- {"PHYS_BP" , 16, 16, 244, "R/W", 0, 1, 65535ull, 0},
- {"LOGL_EN" , 32, 16, 244, "R/W", 0, 0, 255ull, 255ull},
- {"PHYS_EN" , 48, 16, 244, "R/W", 0, 0, 255ull, 255ull},
- {"EN" , 0, 1, 245, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 245, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 245, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 245, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 245, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 245, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 245, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 245, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 245, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 245, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 246, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 247, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 248, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 249, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 250, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 251, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 32, 252, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 252, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 253, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 253, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 254, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 254, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 254, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 254, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 255, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 255, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 256, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 256, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 256, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 256, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 256, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 256, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 256, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 256, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 256, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 257, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 257, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 257, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 257, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 257, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 257, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 257, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 257, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 257, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 257, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 257, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 257, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 257, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 258, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 258, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 259, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 259, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 259, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 259, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 259, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 259, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 260, "R/W1C", 0, 1, 0ull, 0},
- {"CAREXT" , 1, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 260, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 260, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 260, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 260, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 260, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 260, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 261, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 261, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 262, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 262, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 263, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 263, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 264, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 264, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 265, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 265, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 266, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 266, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 267, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 267, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 268, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 268, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 269, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 269, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 270, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 271, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 271, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 272, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 272, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 273, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 273, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 273, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 273, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 274, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 274, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 275, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 275, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 276, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 276, "RAZ", 1, 1, 0, 0},
- {"LGTIM2GO" , 0, 16, 277, "RO", 0, 1, 0ull, 0},
- {"XOF" , 16, 16, 277, "RO", 0, 0, 0ull, 0ull},
- {"PHTIM2GO" , 32, 16, 277, "RO", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 277, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 4, 278, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 278, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 4, 278, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 278, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 279, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 279, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 280, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 280, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 280, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 280, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 280, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 281, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 281, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 282, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 0, 1, 283, "R/W", 0, 1, 0ull, 0},
- {"START_BIST" , 1, 1, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 283, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 284, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 284, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 284, "RAZ", 1, 1, 0, 0},
- {"WR_MAGIC" , 0, 1, 285, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 285, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 286, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 286, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 286, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 286, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 286, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 287, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 287, "RAZ", 1, 1, 0, 0},
- {"XOFF" , 0, 16, 288, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 288, "RAZ", 1, 1, 0, 0},
- {"XON" , 0, 16, 289, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 289, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 290, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 290, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 290, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 291, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 291, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 292, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 292, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 293, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 293, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 294, "RO", 1, 1, 0, 0},
- {"MSG_TIME" , 16, 16, 294, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 294, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 295, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 295, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 296, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 296, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 297, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 297, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 298, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 298, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 299, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 299, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 300, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 300, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 301, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 301, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 302, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 302, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 303, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 303, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 304, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 304, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 305, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 305, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 306, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 306, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 307, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 307, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 308, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 308, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 309, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 309, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 310, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 310, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 311, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 311, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 312, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 312, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 313, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 313, "RAZ", 1, 1, 0, 0},
- {"TX_XOF" , 0, 16, 314, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 314, "RAZ", 1, 1, 0, 0},
- {"TX_XON" , 0, 16, 315, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 315, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 316, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 316, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 316, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 317, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 317, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 317, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 317, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 317, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 317, "R/W", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 317, "R/W", 0, 0, 0ull, 0ull},
- {"XCHANGE" , 24, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 317, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 318, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 318, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 318, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 318, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 318, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 318, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 318, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 318, "R/W1C", 0, 0, 0ull, 0ull},
- {"XCHANGE" , 24, 1, 318, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 318, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 319, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 319, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 320, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 320, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 321, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 321, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 321, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 321, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 321, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 321, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 322, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 322, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 323, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 323, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 324, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_5_63" , 5, 59, 324, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 325, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 325, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 325, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 325, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 325, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 325, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 325, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 325, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 326, "R/W", 0, 0, 6ull, 6ull},
- {"EN" , 4, 1, 326, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 326, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 327, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 327, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 327, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 327, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCE_SEL" , 15, 2, 327, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 327, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 328, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 328, "RAZ", 1, 1, 0, 0},
- {"LANE_SEL" , 0, 2, 329, "R/W", 0, 0, 0ull, 0ull},
- {"DIV" , 2, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 329, "RAZ", 1, 1, 0, 0},
- {"QLM_SEL" , 8, 2, 329, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 329, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 330, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_17" , 0, 18, 331, "RAZ", 1, 1, 0, 0},
- {"ENA18" , 18, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"ENA19" , 19, 1, 331, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 331, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 20, 332, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 332, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 20, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 333, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 20, 334, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 334, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 335, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 335, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 335, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCE_SEL" , 15, 2, 335, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 335, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"IOCFIF" , 18, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"RSDFIF" , 19, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"IORFIF" , 20, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"XMCFIF" , 21, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"XMDFIF" , 22, 1, 336, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 336, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 337, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 337, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 337, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 337, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 337, "R/W1C", 0, 0, 0ull, 0ull},
- {"RR_MODE" , 5, 1, 337, "R/W", 0, 0, 0ull, 0ull},
- {"XMC_PER" , 6, 4, 337, "R/W", 0, 0, 0ull, 0ull},
- {"FIF_DLY" , 10, 1, 337, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 337, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 338, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 338, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 338, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 339, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 339, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 339, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 340, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 340, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 340, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 341, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 341, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 341, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 341, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 341, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 342, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 342, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 342, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 342, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 342, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 343, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 344, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 345, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 345, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 345, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 345, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 345, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 345, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 345, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 346, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 347, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 347, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 347, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 348, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 348, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 348, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 349, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 349, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 349, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 350, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 350, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 350, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 350, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 350, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 351, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 351, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 351, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 351, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 351, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 352, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 353, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 354, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 354, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 354, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 355, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 355, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 355, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 356, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 356, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 356, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 357, "RO", 0, 1, 0ull, 0},
- {"VPORT" , 6, 6, 357, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 357, "RAZ", 1, 1, 0, 0},
- {"NCB_WR" , 0, 3, 358, "R/W", 0, 1, 0ull, 0},
- {"NCB_RD" , 3, 3, 358, "R/W", 0, 1, 0ull, 0},
- {"PKO_RD" , 6, 3, 358, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 358, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 359, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 359, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 360, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 360, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 361, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 361, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 362, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 362, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 48, 363, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 363, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 364, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 365, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 365, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"CLKEN" , 15, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"RST_DONE" , 16, 1, 365, "RO", 0, 0, 1ull, 0ull},
- {"USE_SOP" , 17, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 365, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 366, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 366, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 367, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 367, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 368, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 368, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 369, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 369, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 370, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 370, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 371, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 371, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 371, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 372, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 372, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 372, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 373, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 373, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 373, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 374, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 374, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 375, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 375, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 376, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 376, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 377, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 377, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 378, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 378, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 379, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 380, "R/W", 0, 0, 0ull, 1ull},
- {"RADDR" , 0, 3, 381, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 381, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 381, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 381, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 381, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 381, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 382, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 382, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 382, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 382, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_44_63" , 44, 20, 382, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 383, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 383, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 383, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 383, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 383, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 383, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 384, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 384, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 384, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 384, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 384, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 384, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_61_63" , 61, 3, 384, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 385, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 385, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 386, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 386, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 387, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 387, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 387, "R/W", 0, 0, 0ull, 0ull},
- {"PRT_ENB" , 0, 12, 388, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 388, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 389, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 389, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 389, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 389, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 390, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 390, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 390, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 391, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_35" , 32, 4, 391, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT2" , 36, 4, 391, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_40_63" , 40, 24, 391, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 392, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 392, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 392, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 393, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 393, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 394, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 394, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 395, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 395, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 395, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 395, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 396, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 396, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 396, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 397, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 397, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 398, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 398, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 398, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 398, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 398, "RAZ", 1, 1, 0, 0},
- {"DISABLE" , 0, 1, 399, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 399, "RAZ", 1, 1, 0, 0},
- {"MAXDRAM" , 4, 4, 399, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_8_63" , 8, 56, 399, "RAZ", 1, 1, 0, 0},
- {"TDFFL" , 0, 1, 400, "RO", 1, 0, 0, 0ull},
- {"RESERVED_1_3" , 1, 3, 400, "RAZ", 1, 1, 0, 0},
- {"VRTFL" , 4, 1, 400, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_7" , 5, 3, 400, "RAZ", 1, 1, 0, 0},
- {"DUTRESFL" , 8, 1, 400, "RO", 1, 0, 0, 0ull},
- {"RESERVED_9_11" , 9, 3, 400, "RAZ", 1, 1, 0, 0},
- {"IOCDATFL" , 12, 1, 400, "RO", 1, 0, 0, 0ull},
- {"RESERVED_13_15" , 13, 3, 400, "RAZ", 1, 1, 0, 0},
- {"IOCCMDFL" , 16, 1, 400, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 400, "RAZ", 1, 1, 0, 0},
- {"DUTFL" , 32, 10, 400, "RO", 1, 0, 0, 0ull},
- {"RESERVED_42_63" , 42, 22, 400, "RAZ", 1, 1, 0, 0},
- {"VBFFL" , 0, 4, 401, "RO", 1, 0, 0, 0ull},
- {"RDFFL" , 4, 1, 401, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_61" , 5, 57, 401, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 62, 1, 401, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 63, 1, 401, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFL" , 0, 8, 402, "RO", 1, 0, 0, 0ull},
- {"FBFFL" , 8, 8, 402, "RO", 1, 0, 0, 0ull},
- {"SBFFL" , 16, 8, 402, "RO", 1, 0, 0, 0ull},
- {"FBFRSPFL" , 24, 8, 402, "RO", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 402, "RAZ", 1, 1, 0, 0},
- {"TAGFL" , 0, 16, 403, "RO", 1, 0, 0, 0ull},
- {"LRUFL" , 16, 1, 403, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 403, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 404, "R/W", 1, 1, 0, 0},
- {"DISIDXALIAS" , 0, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"DISECC" , 1, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"VAB_THRESH" , 2, 4, 405, "R/W", 0, 0, 0ull, 0ull},
- {"EF_CNT" , 6, 7, 405, "R/W", 0, 0, 0ull, 4ull},
- {"EF_ENA" , 13, 1, 405, "R/W", 0, 0, 0ull, 1ull},
- {"XMC_ARB_MODE" , 14, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"RSP_ARB_MODE" , 15, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"MAXLFB" , 16, 4, 405, "R/W", 0, 0, 0ull, 0ull},
- {"MAXVAB" , 20, 4, 405, "R/W", 0, 0, 0ull, 0ull},
- {"DISCCLK" , 24, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFDBE" , 25, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFSBE" , 26, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"DISSTGL2I" , 27, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"RDF_FAST" , 28, 1, 405, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_29_63" , 29, 35, 405, "RAZ", 1, 1, 0, 0},
- {"VALID" , 0, 1, 406, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_9" , 1, 9, 406, "RAZ", 1, 1, 0, 0},
- {"TAG" , 10, 28, 406, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 406, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 407, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 407, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 4, 17, 407, "RO", 1, 0, 0, 0ull},
- {"RESERVED_21_49" , 21, 29, 407, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 10, 407, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 408, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_6" , 2, 5, 408, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 7, 14, 408, "RO", 1, 0, 0, 0ull},
- {"RESERVED_21_49" , 21, 29, 408, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 6, 408, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_60" , 56, 5, 408, "RAZ", 1, 1, 0, 0},
- {"NOWAY" , 61, 1, 408, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 408, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 408, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 409, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_49" , 2, 48, 409, "RAZ", 1, 1, 0, 0},
- {"VSYN" , 50, 10, 409, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 409, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 409, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 38, 410, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_47" , 38, 10, 410, "RAZ", 1, 1, 0, 0},
- {"SID" , 48, 5, 410, "RO", 0, 1, 0ull, 0},
- {"RESERVED_53_57" , 53, 5, 410, "RAZ", 1, 1, 0, 0},
- {"CMD" , 58, 6, 410, "RO", 0, 1, 0ull, 0},
- {"HOLERD" , 0, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"HOLEWR" , 1, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"VRTWR" , 2, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"VRTIDRNG" , 3, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"VRTADRNG" , 4, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"VRTPE" , 5, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"BIGWR" , 6, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"BIGRD" , 7, 1, 411, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 411, "RAZ", 1, 1, 0, 0},
- {"HOLERD" , 0, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"HOLEWR" , 1, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTWR" , 2, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTIDRNG" , 3, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTADRNG" , 4, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTPE" , 5, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGWR" , 6, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGRD" , 7, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 412, "RAZ", 1, 1, 0, 0},
- {"TAD0" , 16, 1, 412, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 412, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 413, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 414, "R/W", 0, 1, 0ull, 0},
- {"LVL" , 0, 2, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 415, "RAZ", 1, 1, 0, 0},
- {"DWBLVL" , 4, 2, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 415, "RAZ", 1, 1, 0, 0},
- {"LVL" , 0, 2, 416, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 416, "RAZ", 1, 1, 0, 0},
- {"WGT0" , 0, 8, 417, "R/W", 0, 0, 255ull, 255ull},
- {"WGT1" , 8, 8, 417, "R/W", 0, 0, 255ull, 255ull},
- {"WGT2" , 16, 8, 417, "R/W", 0, 0, 255ull, 255ull},
- {"WGT3" , 24, 8, 417, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 417, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 418, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 419, "R/W", 0, 1, 0ull, 0},
- {"OW0ECC" , 0, 10, 420, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 420, "RAZ", 1, 1, 0, 0},
- {"OW1ECC" , 16, 10, 420, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 420, "RAZ", 1, 1, 0, 0},
- {"OW2ECC" , 32, 10, 420, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 420, "RAZ", 1, 1, 0, 0},
- {"OW3ECC" , 48, 10, 420, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 420, "RAZ", 1, 1, 0, 0},
- {"OW4ECC" , 0, 10, 421, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 421, "RAZ", 1, 1, 0, 0},
- {"OW5ECC" , 16, 10, 421, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 421, "RAZ", 1, 1, 0, 0},
- {"OW6ECC" , 32, 10, 421, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 421, "RAZ", 1, 1, 0, 0},
- {"OW7ECC" , 48, 10, 421, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 421, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"WRDISLMC" , 8, 1, 422, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 422, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 423, "R/W1C", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 423, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 423, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 423, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 423, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 423, "R/W1C", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"WRDISLMC" , 8, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 423, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 424, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 425, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 426, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 427, "R/W", 0, 1, 0ull, 0},
- {"CNT0SEL" , 0, 8, 428, "R/W", 0, 0, 0ull, 1ull},
- {"CNT1SEL" , 8, 8, 428, "R/W", 0, 0, 0ull, 1ull},
- {"CNT2SEL" , 16, 8, 428, "R/W", 0, 0, 0ull, 1ull},
- {"CNT3SEL" , 24, 8, 428, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 428, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 0, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"DIRTY" , 1, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"VALID" , 2, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"USE" , 3, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_16" , 4, 13, 429, "RAZ", 1, 1, 0, 0},
- {"TAG" , 17, 19, 429, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_39" , 36, 4, 429, "RAZ", 1, 1, 0, 0},
- {"ECC" , 40, 6, 429, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_63" , 46, 18, 429, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 430, "R/W1C", 0, 0, 0ull, 0ull},
- {"MASK" , 0, 1, 431, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 431, "RAZ", 1, 1, 0, 0},
- {"DWB" , 0, 1, 432, "R/W1C", 0, 0, 0ull, 0ull},
- {"INVL2" , 1, 1, 432, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 432, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 10, 433, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 433, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 434, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 434, "RAZ", 1, 1, 0, 0},
- {"DWBID" , 8, 6, 434, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 434, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 435, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 435, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 436, "R/W", 0, 0, 0ull, 1ull},
- {"NUMID" , 1, 3, 436, "R/W", 0, 0, 5ull, 5ull},
- {"MEMSZ" , 4, 3, 436, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_7_7" , 7, 1, 436, "RAZ", 1, 1, 0, 0},
- {"OOBERR" , 8, 1, 436, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 436, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 32, 437, "R/W", 0, 0, 0ull, 0ull},
- {"PARITY" , 32, 4, 437, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 437, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 438, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 438, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 439, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 439, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 440, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 38, 441, "R/W", 1, 1, 0, 0},
- {"RESERVED_38_56" , 38, 19, 441, "RAZ", 1, 1, 0, 0},
- {"CMD" , 57, 6, 441, "R/W", 1, 1, 0, 0},
- {"INUSE" , 63, 1, 441, "RO", 0, 0, 0ull, 0ull},
- {"COUNT" , 0, 64, 442, "R/W", 0, 1, 0ull, 0},
- {"PRBS" , 0, 32, 443, "R/W", 1, 1, 0, 0},
- {"PROG" , 32, 8, 443, "R/W", 1, 1, 0, 0},
- {"SEL" , 40, 1, 443, "R/W", 1, 1, 0, 0},
- {"EN" , 41, 1, 443, "R/W", 1, 1, 0, 0},
- {"SKEW_ON" , 42, 1, 443, "R/W", 1, 1, 0, 0},
- {"DR" , 43, 1, 443, "R/W", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 443, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 444, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 445, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 445, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 446, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 447, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 447, "R/W", 1, 1, 0, 0},
- {"CKE_MASK" , 0, 2, 448, "R/W", 1, 1, 0, 0},
- {"CS0_N_MASK" , 2, 2, 448, "R/W", 1, 1, 0, 0},
- {"CS1_N_MASK" , 4, 2, 448, "R/W", 1, 1, 0, 0},
- {"ODT0_MASK" , 6, 2, 448, "R/W", 1, 1, 0, 0},
- {"ODT1_MASK" , 8, 2, 448, "R/W", 1, 1, 0, 0},
- {"RAS_N_MASK" , 10, 1, 448, "R/W", 1, 1, 0, 0},
- {"CAS_N_MASK" , 11, 1, 448, "R/W", 1, 1, 0, 0},
- {"WE_N_MASK" , 12, 1, 448, "R/W", 1, 1, 0, 0},
- {"BA_MASK" , 13, 3, 448, "R/W", 1, 1, 0, 0},
- {"A_MASK" , 16, 16, 448, "R/W", 1, 1, 0, 0},
- {"RESET_N_MASK" , 32, 1, 448, "R/W", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 448, "R/W", 1, 1, 0, 0},
- {"DQX_CTL" , 0, 4, 449, "R/W", 0, 1, 4ull, 0},
- {"CK_CTL" , 4, 4, 449, "R/W", 0, 1, 4ull, 0},
- {"CMD_CTL" , 8, 4, 449, "R/W", 0, 1, 4ull, 0},
- {"RODT_CTL" , 12, 4, 449, "R/W", 0, 1, 0ull, 0},
- {"NTUNE" , 16, 4, 449, "R/W", 0, 1, 0ull, 0},
- {"PTUNE" , 20, 4, 449, "R/W", 0, 1, 0ull, 0},
- {"BYP" , 24, 1, 449, "R/W", 0, 1, 0ull, 0},
- {"M180" , 25, 1, 449, "R/W", 0, 1, 0ull, 0},
- {"DDR__NTUNE" , 26, 4, 449, "RO", 1, 1, 0, 0},
- {"DDR__PTUNE" , 30, 4, 449, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 449, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 450, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 450, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 450, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 450, "R/W", 0, 1, 5ull, 0},
- {"IDLEPOWER" , 9, 3, 450, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 12, 4, 450, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 16, 1, 450, "R/W", 0, 0, 0ull, 1ull},
- {"RESET" , 17, 1, 450, "R/W", 0, 1, 0ull, 0},
- {"REF_ZQCS_INT" , 18, 19, 450, "R/W", 1, 1, 0, 0},
- {"SEQUENCE" , 37, 3, 450, "R/W", 0, 0, 0ull, 0ull},
- {"EARLY_DQX" , 40, 1, 450, "R/W", 0, 0, 0ull, 0ull},
- {"SREF_WITH_DLL" , 41, 1, 450, "R/W", 0, 0, 0ull, 0ull},
- {"RANK_ENA" , 42, 1, 450, "R/W", 0, 1, 0ull, 0},
- {"RANKMASK" , 43, 4, 450, "R/W", 0, 1, 0ull, 0},
- {"MIRRMASK" , 47, 4, 450, "R/W", 0, 1, 0ull, 0},
- {"INIT_STATUS" , 51, 4, 450, "R/W1", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R0" , 55, 1, 450, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R1" , 56, 1, 450, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R0" , 57, 1, 450, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R1" , 58, 1, 450, "R/W", 0, 1, 0ull, 0},
- {"SCRZ" , 59, 1, 450, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 450, "RAZ", 1, 1, 0, 0},
- {"RDIMM_ENA" , 0, 1, 451, "R/W", 0, 1, 0ull, 0},
- {"BWCNT" , 1, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 2, 1, 451, "R/W", 0, 0, 0ull, 1ull},
- {"POCAS" , 3, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH2" , 4, 2, 451, "R/W", 0, 0, 0ull, 1ull},
- {"THROTTLE_RD" , 6, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"THROTTLE_WR" , 7, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_RD" , 8, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_WR" , 9, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"ELEV_PRIO_DIS" , 10, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"NXM_WRITE_EN" , 11, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 12, 4, 451, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 16, 1, 451, "R/W", 0, 0, 0ull, 1ull},
- {"AUTO_DCLKDIS" , 17, 1, 451, "R/W", 0, 0, 0ull, 1ull},
- {"INT_ZQCS_DIS" , 18, 1, 451, "R/W", 0, 0, 1ull, 0ull},
- {"EXT_ZQCS_DIS" , 19, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 20, 2, 451, "R/W", 0, 0, 0ull, 0ull},
- {"WODT_BPRCH" , 22, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_BPRCH" , 23, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_62" , 24, 39, 451, "RAZ", 1, 1, 0, 0},
- {"SCRAMBLE_ENA" , 63, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"DCLKCNT" , 0, 64, 452, "RO", 0, 1, 0ull, 0},
- {"CLKF" , 0, 7, 453, "R/W", 0, 1, 48ull, 0},
- {"RESET_N" , 7, 1, 453, "R/W", 0, 0, 0ull, 1ull},
- {"CPB" , 8, 3, 453, "R/W", 0, 0, 0ull, 1ull},
- {"CPS" , 11, 3, 453, "R/W", 0, 0, 0ull, 1ull},
- {"DIFFAMP" , 14, 4, 453, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_PS_EN" , 18, 3, 453, "R/W", 0, 1, 2ull, 0},
- {"DDR_DIV_RESET" , 21, 1, 453, "R/W", 0, 0, 1ull, 0ull},
- {"DFM_PS_EN" , 22, 3, 453, "R/W", 0, 1, 2ull, 0},
- {"DFM_DIV_RESET" , 25, 1, 453, "R/W", 0, 0, 1ull, 0ull},
- {"JTG_TEST_MODE" , 26, 1, 453, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 453, "RAZ", 1, 1, 0, 0},
- {"RC0" , 0, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC1" , 4, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC2" , 8, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC3" , 12, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC4" , 16, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC5" , 20, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC6" , 24, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC7" , 28, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC8" , 32, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC9" , 36, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC10" , 40, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC11" , 44, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC12" , 48, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC13" , 52, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC14" , 56, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"RC15" , 60, 4, 454, "R/W", 0, 0, 0ull, 0ull},
- {"DIMM0_WMASK" , 0, 16, 455, "R/W", 0, 0, 65535ull, 65535ull},
- {"DIMM1_WMASK" , 16, 16, 455, "R/W", 0, 0, 65535ull, 65535ull},
- {"TCWS" , 32, 13, 455, "R/W", 0, 0, 1248ull, 1248ull},
- {"PARITY" , 45, 1, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 455, "RAZ", 1, 1, 0, 0},
- {"BYP_SETTING" , 0, 8, 456, "R/W", 0, 0, 0ull, 0ull},
- {"BYP_SEL" , 8, 4, 456, "R/W", 0, 0, 0ull, 0ull},
- {"QUAD_DLL_ENA" , 12, 1, 456, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 13, 1, 456, "R/W", 0, 0, 1ull, 0ull},
- {"DLL_BRINGUP" , 14, 1, 456, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 456, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 457, "R/W", 0, 0, 0ull, 0ull},
- {"BYTE_SEL" , 6, 4, 457, "R/W", 0, 0, 0ull, 0ull},
- {"MODE_SEL" , 10, 2, 457, "R/W", 0, 0, 0ull, 0ull},
- {"LOAD_OFFSET" , 12, 1, 457, "WR0", 0, 0, 0ull, 0ull},
- {"OFFSET_ENA" , 13, 1, 457, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYTE_SEL" , 14, 4, 457, "R/W", 0, 0, 1ull, 1ull},
- {"DLL_MODE" , 18, 1, 457, "R/W", 0, 0, 0ull, 0ull},
- {"FINE_TUNE_MODE" , 19, 1, 457, "R/W", 0, 0, 0ull, 1ull},
- {"DLL90_SETTING" , 20, 8, 457, "RO", 1, 1, 0, 0},
- {"DLL_FAST" , 28, 1, 457, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 457, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 458, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 458, "RAZ", 1, 1, 0, 0},
- {"ROW_LSB" , 16, 3, 458, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_19_63" , 19, 45, 458, "RAZ", 1, 1, 0, 0},
- {"MRDSYN0" , 0, 8, 459, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 459, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 459, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 459, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 459, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 14, 460, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 14, 16, 460, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 30, 3, 460, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 33, 1, 460, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 34, 2, 460, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 460, "RAZ", 1, 1, 0, 0},
- {"IFBCNT" , 0, 64, 461, "RO", 0, 1, 1ull, 0},
- {"NXM_WR_ERR" , 0, 1, 462, "R/W1C", 0, 0, 0ull, 0ull},
- {"SEC_ERR" , 1, 4, 462, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 5, 4, 462, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 462, "RAZ", 1, 1, 0, 0},
- {"INTR_NXM_WR_ENA" , 0, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_SEC_ENA" , 1, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 2, 1, 463, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 463, "RAZ", 1, 1, 0, 0},
- {"CWL" , 0, 3, 464, "R/W", 0, 0, 0ull, 0ull},
- {"MPRLOC" , 3, 2, 464, "R/W", 0, 0, 0ull, 0ull},
- {"MPR" , 5, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"DLL" , 6, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"AL" , 7, 2, 464, "R/W", 0, 0, 0ull, 0ull},
- {"WLEV" , 9, 1, 464, "RO", 0, 0, 0ull, 0ull},
- {"TDQS" , 10, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"QOFF" , 11, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"BL" , 12, 2, 464, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 14, 4, 464, "R/W", 0, 0, 2ull, 2ull},
- {"RBT" , 18, 1, 464, "RO", 0, 0, 1ull, 1ull},
- {"TM" , 19, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"DLLR" , 20, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"WRP" , 21, 3, 464, "R/W", 0, 0, 0ull, 0ull},
- {"PPD" , 24, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 464, "RAZ", 1, 1, 0, 0},
- {"PASR_00" , 0, 3, 465, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_00" , 3, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_00" , 4, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_00" , 5, 2, 465, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_00" , 7, 2, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_00" , 9, 3, 465, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_01" , 12, 3, 465, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_01" , 15, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_01" , 16, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_01" , 17, 2, 465, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_01" , 19, 2, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_01" , 21, 3, 465, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_10" , 24, 3, 465, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_10" , 27, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_10" , 28, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_10" , 29, 2, 465, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_10" , 31, 2, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_10" , 33, 3, 465, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_11" , 36, 3, 465, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_11" , 39, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_11" , 40, 1, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_11" , 41, 2, 465, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_11" , 43, 2, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_11" , 45, 3, 465, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 465, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 466, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R0" , 8, 4, 466, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R1" , 12, 4, 466, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R0" , 16, 4, 466, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R1" , 20, 4, 466, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R0" , 24, 4, 466, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R1" , 28, 4, 466, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R0" , 32, 4, 466, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R1" , 36, 4, 466, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 466, "RAZ", 1, 1, 0, 0},
- {"OPSCNT" , 0, 64, 467, "RO", 0, 1, 1ull, 0},
- {"TS_STAGGER" , 0, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK_POS" , 1, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK" , 2, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT0" , 3, 4, 468, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE0" , 7, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT1" , 8, 4, 468, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE1" , 12, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"LV_MODE" , 13, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"RX_ALWAYS_ON" , 14, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 468, "RAZ", 1, 1, 0, 0},
- {"DDR3RST" , 0, 1, 469, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PWARM" , 1, 1, 469, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSOFT" , 2, 1, 469, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSV" , 3, 1, 469, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 469, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 470, "R/W", 0, 1, 0ull, 0},
- {"OFFSET" , 4, 4, 470, "R/W", 0, 0, 2ull, 2ull},
- {"OFFSET_EN" , 8, 1, 470, "R/W", 0, 0, 1ull, 1ull},
- {"OR_DIS" , 9, 1, 470, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 10, 8, 470, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_0" , 18, 1, 470, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_1" , 19, 1, 470, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_2" , 20, 1, 470, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_3" , 21, 1, 470, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 470, "RAZ", 1, 1, 0, 0},
- {"BITMASK" , 0, 64, 471, "RO", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 6, 472, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 6, 6, 472, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 12, 6, 472, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 18, 6, 472, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 24, 6, 472, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 30, 6, 472, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 36, 6, 472, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 42, 6, 472, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 48, 6, 472, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 54, 2, 472, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 472, "RAZ", 1, 1, 0, 0},
- {"RODT_D0_R0" , 0, 8, 473, "R/W", 0, 1, 0ull, 0},
- {"RODT_D0_R1" , 8, 8, 473, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R0" , 16, 8, 473, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R1" , 24, 8, 473, "R/W", 0, 1, 0ull, 0},
- {"RODT_D2_R0" , 32, 8, 473, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R1" , 40, 8, 473, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R0" , 48, 8, 473, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R1" , 56, 8, 473, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 0, 64, 474, "R/W", 0, 1, 0ull, 0},
- {"KEY" , 0, 64, 475, "R/W", 0, 1, 0ull, 0},
- {"FCOL" , 0, 14, 476, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 14, 16, 476, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 30, 3, 476, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 33, 1, 476, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 34, 2, 476, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 476, "RAZ", 1, 1, 0, 0},
- {"R2R_INIT" , 0, 6, 477, "R/W", 0, 1, 1ull, 0},
- {"R2W_INIT" , 6, 6, 477, "R/W", 0, 1, 6ull, 0},
- {"W2R_INIT" , 12, 6, 477, "R/W", 0, 1, 9ull, 0},
- {"W2W_INIT" , 18, 6, 477, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_24_63" , 24, 40, 477, "RAZ", 1, 1, 0, 0},
- {"R2R_XRANK_INIT" , 0, 6, 478, "R/W", 0, 1, 3ull, 0},
- {"R2W_XRANK_INIT" , 6, 6, 478, "R/W", 0, 1, 6ull, 0},
- {"W2R_XRANK_INIT" , 12, 6, 478, "R/W", 0, 1, 4ull, 0},
- {"W2W_XRANK_INIT" , 18, 6, 478, "R/W", 0, 1, 5ull, 0},
- {"RESERVED_24_63" , 24, 40, 478, "RAZ", 1, 1, 0, 0},
- {"R2R_XDIMM_INIT" , 0, 6, 479, "R/W", 0, 1, 4ull, 0},
- {"R2W_XDIMM_INIT" , 6, 6, 479, "R/W", 0, 1, 7ull, 0},
- {"W2R_XDIMM_INIT" , 12, 6, 479, "R/W", 0, 1, 4ull, 0},
- {"W2W_XDIMM_INIT" , 18, 6, 479, "R/W", 0, 1, 6ull, 0},
- {"RESERVED_24_63" , 24, 40, 479, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_9" , 0, 10, 480, "RAZ", 1, 1, 0, 0},
- {"TZQCS" , 10, 4, 480, "R/W", 0, 0, 4ull, 4ull},
- {"TCKE" , 14, 4, 480, "R/W", 0, 0, 3ull, 3ull},
- {"TXPR" , 18, 4, 480, "R/W", 0, 0, 5ull, 5ull},
- {"TMRD" , 22, 4, 480, "R/W", 0, 0, 4ull, 4ull},
- {"TMOD" , 26, 4, 480, "R/W", 0, 0, 12ull, 12ull},
- {"TDLLK" , 30, 4, 480, "R/W", 0, 0, 2ull, 2ull},
- {"TZQINIT" , 34, 4, 480, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 38, 4, 480, "R/W", 0, 0, 6ull, 6ull},
- {"TCKSRE" , 42, 4, 480, "R/W", 0, 0, 5ull, 5ull},
- {"TRP_EXT" , 46, 1, 480, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 480, "RAZ", 1, 1, 0, 0},
- {"TMPRR" , 0, 4, 481, "R/W", 0, 0, 1ull, 1ull},
- {"TRAS" , 4, 5, 481, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 9, 4, 481, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 13, 4, 481, "R/W", 0, 0, 2ull, 3ull},
- {"TRFC" , 17, 5, 481, "R/W", 0, 0, 6ull, 7ull},
- {"TRRD" , 22, 3, 481, "R/W", 0, 0, 2ull, 2ull},
- {"TXP" , 25, 3, 481, "R/W", 0, 0, 3ull, 3ull},
- {"TWLMRD" , 28, 4, 481, "R/W", 0, 0, 10ull, 10ull},
- {"TWLDQSEN" , 32, 4, 481, "R/W", 0, 0, 7ull, 7ull},
- {"TFAW" , 36, 5, 481, "R/W", 0, 0, 0ull, 9ull},
- {"TXPDLL" , 41, 5, 481, "R/W", 0, 0, 0ull, 10ull},
- {"TRAS_EXT" , 46, 1, 481, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 481, "RAZ", 1, 1, 0, 0},
- {"TRESET" , 0, 1, 482, "R/W", 0, 1, 1ull, 0},
- {"RCLK_CNT" , 1, 32, 482, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 482, "RAZ", 1, 1, 0, 0},
- {"RING_CNT" , 0, 32, 483, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 483, "RAZ", 1, 1, 0, 0},
- {"LANEMASK" , 0, 9, 484, "R/W", 0, 1, 0ull, 0},
- {"SSET" , 9, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"OR_DIS" , 10, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"BITMASK" , 11, 8, 484, "R/W", 0, 1, 0ull, 0},
- {"RTT_NOM" , 19, 3, 484, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 484, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 485, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 4, 8, 485, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 485, "RAZ", 1, 1, 0, 0},
- {"BYTE0" , 0, 5, 486, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 5, 5, 486, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 10, 5, 486, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 15, 5, 486, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 20, 5, 486, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 25, 5, 486, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 30, 5, 486, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 35, 5, 486, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 40, 5, 486, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 45, 2, 486, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_63" , 47, 17, 486, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 487, "R/W", 0, 1, 255ull, 0},
- {"WODT_D0_R1" , 8, 8, 487, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R0" , 16, 8, 487, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R1" , 24, 8, 487, "R/W", 0, 1, 255ull, 0},
- {"WODT_D2_R0" , 32, 8, 487, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D2_R1" , 40, 8, 487, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R0" , 48, 8, 487, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R1" , 56, 8, 487, "R/W", 0, 0, 255ull, 0ull},
- {"STAT" , 0, 10, 488, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 488, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 489, "R/W", 1, 1, 0, 0},
- {"PCTL" , 6, 6, 489, "R/W", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 489, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 490, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 490, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 490, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 490, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 491, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 491, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 491, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 492, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 492, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 493, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 493, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 493, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 493, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 493, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 493, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 493, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 493, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 493, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 493, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 493, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 493, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 493, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 493, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 493, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 494, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 494, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 494, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 495, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 495, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 495, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 496, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 496, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 496, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 497, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 497, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 497, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 497, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 497, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 498, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 499, "RAZ", 1, 1, 0, 0},
- {"NAND" , 8, 1, 499, "RO", 1, 1, 0, 0},
- {"TERM" , 9, 2, 499, "RO", 1, 1, 0, 0},
- {"DMACK_P0" , 11, 1, 499, "RO", 1, 1, 0, 0},
- {"DMACK_P1" , 12, 1, 499, "RO", 1, 1, 0, 0},
- {"RESERVED_13_13" , 13, 1, 499, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 14, 1, 499, "RO", 1, 1, 0, 0},
- {"ALE" , 15, 1, 499, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 499, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 16, 500, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 500, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 500, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 500, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 500, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 500, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 500, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 500, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 500, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 501, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 501, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 501, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 501, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 501, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 501, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 501, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 501, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 501, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 501, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 501, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 501, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 501, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 502, "R/W", 0, 0, 25ull, 25ull},
- {"RESERVED_6_7" , 6, 2, 502, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 502, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 502, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 502, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 502, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 503, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 504, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 504, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 505, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 505, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 10, 506, "RO", 1, 1, 0, 0},
- {"RESERVED_10_15" , 10, 6, 506, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 506, "RO", 1, 1, 0, 0},
- {"RESERVED_24_25" , 24, 2, 506, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 506, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 506, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 506, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 506, "RO", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 506, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 506, "RO", 1, 1, 0, 0},
- {"DORM_CRYPTO" , 34, 1, 506, "RO", 1, 1, 0, 0},
- {"POWER_LIMIT" , 35, 2, 506, "RO", 1, 1, 0, 0},
- {"ROM_INFO" , 37, 10, 506, "RO", 1, 1, 0, 0},
- {"FUS118" , 47, 1, 506, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 506, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 507, "RAZ", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 507, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 507, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 507, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 507, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 507, "RO", 1, 1, 0, 0},
- {"ZIP_INFO" , 29, 2, 507, "RO", 1, 1, 0, 0},
- {"RESERVED_31_31" , 31, 1, 507, "RAZ", 1, 1, 0, 0},
- {"L2C_CRIP" , 32, 3, 507, "RO", 1, 1, 0, 0},
- {"PLL_HALF_DIS" , 35, 1, 507, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_MAN" , 36, 1, 507, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_RSV" , 37, 1, 507, "RO", 1, 1, 0, 0},
- {"EMA" , 38, 2, 507, "RO", 1, 1, 0, 0},
- {"RESERVED_40_40" , 40, 1, 507, "RAZ", 1, 1, 0, 0},
- {"DFA_INFO_CLM" , 41, 4, 507, "RO", 1, 1, 0, 0},
- {"DFA_INFO_DTE" , 45, 3, 507, "RO", 1, 1, 0, 0},
- {"PLL_CTL" , 48, 10, 507, "RO", 1, 1, 0, 0},
- {"RESERVED_58_63" , 58, 6, 507, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 508, "RAZ", 1, 1, 0, 0},
- {"RESERVED_3_3" , 3, 1, 508, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 508, "RAZ", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 508, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 509, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 510, "RAZ", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 510, "RAZ", 0, 1, 0ull, 0},
- {"PNR_COUT_SEL" , 2, 2, 510, "R/W", 0, 1, 0ull, 0},
- {"PNR_COUT_RST" , 4, 1, 510, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_SEL" , 5, 2, 510, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_RST" , 7, 1, 510, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 510, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 511, "R/W", 1, 1, 0, 0},
- {"SOFT" , 1, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 511, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 6, 512, "R/W", 0, 1, 1ull, 0},
- {"SCLK_HI" , 6, 15, 512, "R/W", 0, 1, 5000ull, 0},
- {"SCLK_LO" , 21, 4, 512, "R/W", 0, 1, 1ull, 0},
- {"OUT" , 25, 7, 512, "R/W", 0, 1, 1ull, 0},
- {"PROG_PIN" , 32, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"FSRC_PIN" , 33, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"VGATE_PIN" , 34, 1, 512, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 512, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 513, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 513, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 513, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 513, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 513, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 513, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 10, 514, "R/W", 0, 1, 999ull, 0},
- {"SDH" , 10, 4, 514, "R/W", 0, 1, 0ull, 0},
- {"PRH" , 14, 4, 514, "R/W", 0, 1, 6ull, 0},
- {"FSH" , 18, 4, 514, "R/W", 0, 1, 15ull, 0},
- {"SCH" , 22, 4, 514, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_26_63" , 26, 38, 514, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 18, 515, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 18, 18, 515, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 36, 18, 515, "RO", 0, 0, 0ull, 0ull},
- {"TOO_MANY" , 54, 1, 515, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 515, "RAZ", 1, 1, 0, 0},
- {"REPAIR3" , 0, 18, 516, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR4" , 18, 18, 516, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR5" , 36, 18, 516, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 516, "RAZ", 1, 1, 0, 0},
- {"REPAIR6" , 0, 18, 517, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 517, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 518, "RAZ", 1, 1, 0, 0},
- {"REPAIR1" , 14, 14, 518, "RAZ", 1, 1, 0, 0},
- {"REPAIR2" , 28, 14, 518, "RAZ", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 518, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 519, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 519, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 63, 520, "RO", 1, 1, 0, 0},
- {"VAL" , 63, 1, 520, "R/W", 1, 1, 0, 0},
- {"ADDR" , 0, 4, 521, "R/W", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 521, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 522, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 6, 6, 522, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_12_63" , 12, 52, 522, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 523, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 523, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 523, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 523, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 523, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 523, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 523, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 523, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 523, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 524, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 524, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 525, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 525, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 526, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 526, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 527, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 527, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 528, "R/W", 0, 0, 18446744073709551615ull, 0ull},
- {"FRNANOSEC" , 0, 32, 529, "R/W", 0, 0, 4294967295ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 529, "RAZ", 1, 1, 0, 0},
- {"PTP_EN" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EN" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_IN" , 2, 6, 530, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EN" , 8, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EDGE" , 9, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_IN" , 10, 6, 530, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EN" , 16, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EDGE" , 17, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_IN" , 18, 6, 530, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_EN" , 24, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_INV" , 25, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_OUT" , 26, 4, 530, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_EN" , 30, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_INV" , 31, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_OUT" , 32, 5, 530, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_OUT4" , 37, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EDGE" , 38, 2, 530, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 530, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 531, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 531, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 532, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 533, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 533, "RAZ", 1, 1, 0, 0},
- {"CNTR" , 0, 64, 534, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 535, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 535, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 536, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 536, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 537, "R/W", 0, 0, 18446744073709551615ull, 0ull},
- {"FRNANOSEC" , 0, 32, 538, "R/W", 0, 0, 4294967295ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 538, "RAZ", 1, 1, 0, 0},
- {"NANOSEC" , 0, 64, 539, "R/W", 0, 0, 0ull, 0ull},
- {"QLM_CFG" , 0, 4, 540, "RO", 1, 1, 0, 0},
- {"RESERVED_4_7" , 4, 4, 540, "RAZ", 1, 1, 0, 0},
- {"QLM_SPD" , 8, 4, 540, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 540, "RAZ", 1, 1, 0, 0},
- {"RBOOT_PIN" , 0, 1, 541, "RO", 1, 1, 0, 0},
- {"RBOOT" , 1, 1, 541, "R/W", 1, 1, 0, 0},
- {"LBOOT" , 2, 10, 541, "R/W1C", 1, 1, 0, 0},
- {"QLM0_SPD" , 12, 4, 541, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 16, 4, 541, "RO", 1, 1, 0, 0},
- {"QLM2_SPD" , 20, 4, 541, "RO", 1, 1, 0, 0},
- {"PNR_MUL" , 24, 6, 541, "RO", 1, 1, 0, 0},
- {"C_MUL" , 30, 6, 541, "RO", 1, 1, 0, 0},
- {"RESERVED_36_47" , 36, 12, 541, "RAZ", 1, 1, 0, 0},
- {"LBOOT_EXT" , 48, 2, 541, "R/W1C", 1, 1, 0, 0},
- {"RESERVED_50_58" , 50, 9, 541, "RAZ", 1, 1, 0, 0},
- {"CKILL_PPDIS" , 59, 1, 541, "R/W", 0, 1, 1ull, 0},
- {"ROMEN" , 60, 1, 541, "R/W", 1, 1, 0, 0},
- {"EJTAGDIS" , 61, 1, 541, "R/W", 1, 1, 0, 0},
- {"JTCSRDIS" , 62, 1, 541, "R/W", 1, 1, 0, 0},
- {"CHIPKILL" , 63, 1, 541, "R/W1", 0, 0, 0ull, 0ull},
- {"SOFT_CLR_BIST" , 0, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"WARM_CLR_BIST" , 1, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"CNTL_CLR_BIST" , 2, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_5" , 3, 3, 542, "RAZ", 1, 1, 0, 0},
- {"BIST_DELAY" , 6, 58, 542, "RO", 1, 1, 0, 0},
- {"TIMER" , 0, 47, 543, "R/W", 0, 1, 17179869183ull, 0},
- {"RESERVED_47_63" , 47, 17, 543, "RAZ", 0, 0, 0ull, 0ull},
- {"RST_VAL" , 0, 1, 544, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 544, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 544, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 544, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 544, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 544, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 544, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 544, "RO", 1, 1, 0, 0},
- {"PRST_LINK" , 9, 1, 544, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 544, "RAZ", 1, 1, 0, 0},
- {"RST_VAL" , 0, 1, 545, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 545, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 545, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 545, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 545, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 545, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 545, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 545, "RO", 1, 1, 0, 0},
- {"PRST_LINK" , 9, 1, 545, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 545, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST_DLY" , 0, 16, 546, "R/W", 0, 1, 2047ull, 0},
- {"WARM_RST_DLY" , 16, 16, 546, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_32_63" , 32, 32, 546, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"RST_LINK2" , 2, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"RST_LINK3" , 3, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_4_7" , 4, 4, 547, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 547, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 547, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"RST_LINK2" , 2, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"RST_LINK3" , 3, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_7" , 4, 4, 548, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 548, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 549, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 549, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 549, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 549, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 549, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 549, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 549, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 549, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 549, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 549, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 549, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 549, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 549, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 550, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 550, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 550, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 550, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 550, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 550, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 550, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 550, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 550, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 550, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 550, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 550, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 551, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 551, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 551, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 552, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 552, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 552, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 553, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 553, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 554, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 554, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 555, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 555, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 556, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 556, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 556, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 556, "RAZ", 1, 1, 0, 0},
- {"TXTRIG" , 4, 2, 556, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 556, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 556, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 557, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 557, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 558, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 558, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 558, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 558, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 558, "RAZ", 1, 1, 0, 0},
- {"PTIME" , 7, 1, 558, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 558, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 559, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 559, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 559, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 559, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 560, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 560, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 560, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 560, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 560, "RAZ", 1, 1, 0, 0},
- {"BRK" , 6, 1, 560, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 560, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 560, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 561, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 561, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 561, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 561, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 561, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 561, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 561, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 561, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 561, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 562, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 562, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 562, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 562, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 562, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 562, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 562, "RAZ", 1, 1, 0, 0},
- {"DCTS" , 0, 1, 563, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 563, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 563, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 563, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 563, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 563, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 563, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 563, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 563, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 564, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 564, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 565, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 565, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 566, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 566, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 566, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 566, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 567, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 567, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 568, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 568, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 569, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 569, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 570, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 570, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 570, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 570, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 571, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 571, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 572, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 572, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 573, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 573, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 574, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 574, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 575, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 575, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 576, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 576, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 577, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 577, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 577, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 577, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 577, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 577, "RAZ", 1, 1, 0, 0},
- {"ORFDAT" , 0, 1, 578, "RO", 0, 0, 0ull, 0ull},
- {"IRFDAT" , 1, 1, 578, "RO", 0, 0, 0ull, 0ull},
- {"IPFDAT" , 2, 1, 578, "RO", 0, 0, 0ull, 0ull},
- {"MRQDAT" , 3, 1, 578, "RO", 0, 0, 0ull, 0ull},
- {"MRGDAT" , 4, 1, 578, "RO", 0, 0, 0ull, 0ull},
- {"OPFDAT" , 5, 1, 578, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 578, "RAZ", 0, 0, 0ull, 0ull},
- {"MRQ_HWM" , 0, 2, 579, "R/W", 0, 0, 0ull, 1ull},
- {"NBTARB" , 2, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"LENDIAN" , 3, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 4, 1, 579, "R/W", 0, 0, 1ull, 0ull},
- {"EN" , 5, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 6, 1, 579, "RO", 0, 0, 0ull, 0ull},
- {"CRC_STRIP" , 7, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"TS_THRESH" , 8, 4, 579, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 579, "RAZ", 1, 1, 0, 0},
- {"OVFENA" , 0, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"IVFENA" , 1, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"OTHENA" , 2, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"ITHENA" , 3, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_DRPENA" , 4, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"IRUNENA" , 5, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"ORUNENA" , 6, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"TSENA" , 7, 1, 580, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 580, "RAZ", 1, 1, 0, 0},
- {"IRCNT" , 0, 20, 581, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 581, "RAZ", 1, 1, 0, 0},
- {"IRHWM" , 0, 20, 582, "R/W", 0, 0, 0ull, 0ull},
- {"IBPLWM" , 20, 20, 582, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 582, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 583, "RAZ", 1, 1, 0, 0},
- {"IBASE" , 3, 37, 583, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 40, 20, 583, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 583, "RAZ", 1, 1, 0, 0},
- {"IDBELL" , 0, 20, 584, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 584, "RAZ", 1, 1, 0, 0},
- {"ITLPTR" , 32, 20, 584, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 584, "RAZ", 1, 1, 0, 0},
- {"ODBLOVF" , 0, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"IDBLOVF" , 1, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORTHRESH" , 2, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"IRTHRESH" , 3, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"DATA_DRP" , 4, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"IRUN" , 5, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORUN" , 6, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
- {"TS" , 7, 1, 585, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 585, "RAZ", 1, 1, 0, 0},
- {"ORCNT" , 0, 20, 586, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 586, "RAZ", 1, 1, 0, 0},
- {"ORHWM" , 0, 20, 587, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 587, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 588, "RAZ", 1, 1, 0, 0},
- {"OBASE" , 3, 37, 588, "R/W", 0, 1, 0ull, 0},
- {"OSIZE" , 40, 20, 588, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 588, "RAZ", 1, 1, 0, 0},
- {"ODBELL" , 0, 20, 589, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 589, "RAZ", 1, 1, 0, 0},
- {"OTLPTR" , 32, 20, 589, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 589, "RAZ", 1, 1, 0, 0},
- {"OREMCNT" , 0, 20, 590, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 590, "RAZ", 1, 1, 0, 0},
- {"IREMCNT" , 32, 20, 590, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_52_63" , 52, 12, 590, "RAZ", 1, 1, 0, 0},
- {"TSCNT" , 0, 5, 591, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 591, "RAZ", 1, 1, 0, 0},
- {"TSTOT" , 8, 5, 591, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 591, "RAZ", 1, 1, 0, 0},
- {"TSAVL" , 16, 5, 591, "RO", 0, 0, 4ull, 4ull},
- {"RESERVED_21_63" , 21, 43, 591, "RAZ", 1, 1, 0, 0},
- {"TSTAMP" , 0, 64, 592, "RO", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"IDLELO" , 1, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_CONT" , 2, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"WIREOR" , 3, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 4, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"INT_ENA" , 5, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 593, "RAZ", 1, 1, 0, 0},
- {"CSHI" , 7, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"IDLECLKS" , 8, 2, 593, "R/W", 0, 0, 0ull, 0ull},
- {"TRITX" , 10, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"CSLATE" , 11, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 593, "RAZ", 1, 1, 0, 0},
- {"CSENA2" , 14, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"CSENA3" , 15, 1, 593, "R/W", 0, 0, 0ull, 0ull},
- {"CLKDIV" , 16, 13, 593, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 593, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 8, 594, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 594, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 595, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 595, "RAZ", 1, 1, 0, 0},
- {"RXNUM" , 8, 5, 595, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 595, "RAZ", 1, 1, 0, 0},
- {"TOTNUM" , 0, 5, 596, "WO", 1, 0, 0, 2ull},
- {"RESERVED_5_7" , 5, 3, 596, "RAZ", 1, 1, 0, 0},
- {"TXNUM" , 8, 5, 596, "WO", 1, 0, 0, 1ull},
- {"RESERVED_13_15" , 13, 3, 596, "RAZ", 1, 1, 0, 0},
- {"LEAVECS" , 16, 1, 596, "WO", 1, 0, 0, 0ull},
- {"RESERVED_17_19" , 17, 3, 596, "RAZ", 1, 1, 0, 0},
- {"CSID" , 20, 2, 596, "WO", 1, 0, 0, 0ull},
- {"RESERVED_22_63" , 22, 42, 596, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 3, 597, "R/W", 0, 1, 0ull, 0},
- {"ADR_CYC" , 3, 4, 597, "R/W", 0, 1, 8ull, 0},
- {"T_MULT" , 7, 4, 597, "R/W", 0, 1, 9ull, 0},
- {"RESERVED_11_63" , 11, 53, 597, "RAZ", 1, 1, 0, 0},
- {"NF_CMD" , 0, 64, 598, "R/W", 0, 1, 0ull, 0},
- {"CNT" , 0, 8, 599, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 599, "RAZ", 1, 1, 0, 0},
- {"ECC_ERR" , 0, 8, 600, "RO", 0, 1, 0ull, 0},
- {"XOR_ECC" , 8, 24, 600, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 600, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 601, "R/W1C", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 601, "R/W1C", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 601, "R/W1C", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 601, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 601, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 601, "R/W1C", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 601, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 601, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 602, "R/W", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 602, "R/W", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 602, "R/W", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 602, "R/W", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 602, "R/W", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 602, "R/W", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 602, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 602, "RAZ", 1, 1, 0, 0},
- {"RST_FF" , 0, 1, 603, "R/W", 0, 0, 0ull, 0ull},
- {"EX_DIS" , 1, 1, 603, "R/W", 0, 0, 0ull, 0ull},
- {"BT_DIS" , 2, 1, 603, "R/W", 0, 0, 0ull, 1ull},
- {"BT_DMA" , 3, 1, 603, "R/W", 0, 1, 0ull, 0},
- {"RD_CMD" , 4, 1, 603, "R/W", 0, 0, 0ull, 0ull},
- {"RD_VAL" , 5, 1, 603, "RO", 0, 1, 0ull, 0},
- {"RD_DONE" , 6, 1, 603, "R/W1C", 0, 0, 0ull, 0ull},
- {"FR_BYT" , 7, 11, 603, "RO", 0, 1, 0ull, 0},
- {"WAIT_CNT" , 18, 6, 603, "R/W", 0, 1, 20ull, 0},
- {"NBR_HWM" , 24, 3, 603, "R/W", 0, 0, 3ull, 3ull},
- {"MB_DIS" , 27, 1, 603, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 603, "RAZ", 1, 1, 0, 0},
- {"MAIN_SM" , 0, 3, 604, "RO", 0, 1, 0ull, 0},
- {"MAIN_BAD" , 3, 1, 604, "RO", 0, 1, 0ull, 0},
- {"RD_FF" , 4, 2, 604, "RO", 0, 1, 0ull, 0},
- {"RD_FF_BAD" , 6, 1, 604, "RO", 0, 1, 0ull, 0},
- {"BT_SM" , 7, 4, 604, "RO", 0, 1, 0ull, 0},
- {"EXE_SM" , 11, 4, 604, "RO", 0, 1, 0ull, 0},
- {"EXE_IDLE" , 15, 1, 604, "RO", 0, 1, 1ull, 0},
- {"RESERVED_16_63" , 16, 48, 604, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 605, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 605, "RO/WRSL", 0, 0, 146ull, 146ull},
- {"ISAE" , 0, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 606, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 606, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 606, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 606, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 606, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 606, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 606, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 606, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 606, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 606, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 606, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 606, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 606, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 606, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 606, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 606, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 606, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 606, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 607, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 607, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 607, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 607, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 608, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 608, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 608, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 608, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 608, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 609, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 609, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 609, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 609, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 609, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 610, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 610, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 611, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 612, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 613, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 613, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 613, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 613, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 613, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 614, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 614, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 615, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 616, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 617, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 617, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 617, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 617, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 618, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 618, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_8" , 0, 9, 619, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 9, 23, 619, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 620, "WORSL", 0, 0, 511ull, 511ull},
- {"CISP" , 0, 32, 621, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 622, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 622, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 623, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 623, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 623, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 624, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 624, "WORSL", 0, 0, 32767ull, 32767ull},
- {"CP" , 0, 8, 625, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 625, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 626, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 626, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 626, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 626, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 627, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 627, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 627, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 627, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 627, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 627, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 627, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 627, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 627, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 627, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 628, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 628, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 628, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 628, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 628, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 628, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 628, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 628, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 628, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 628, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 628, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 629, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 629, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 629, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 629, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 629, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PVM" , 24, 1, 629, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 629, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 630, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 630, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 631, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 632, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 632, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 633, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 633, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 633, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 633, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 633, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 633, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 633, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 634, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 634, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 634, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 634, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 634, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 634, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 634, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 634, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 634, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 634, "RO", 0, 0, 0ull, 0ull},
- {"FLR" , 28, 1, 634, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 634, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 635, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 635, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 635, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 635, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 635, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 635, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 635, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 635, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 635, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 635, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 635, "R/W", 0, 0, 2ull, 2ull},
- {"I_FLR" , 15, 1, 635, "RO", 0, 0, 0ull, 0ull},
- {"CE_D" , 16, 1, 635, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 635, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 635, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 635, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 635, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 635, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 635, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 636, "RO/WRSL", 1, 1, 0, 0},
- {"MLW" , 4, 6, 636, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"ASLPMS" , 10, 2, 636, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 636, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 636, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 636, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 636, "RO", 0, 0, 0ull, 0ull},
- {"ASPM" , 22, 1, 636, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 636, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 636, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 637, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 637, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 637, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 637, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 637, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 637, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 637, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 637, "RO", 0, 0, 0ull, 8ull},
- {"RESERVED_26_26" , 26, 1, 637, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 637, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"LBM" , 30, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 637, "RO", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 638, "RO", 0, 0, 15ull, 15ull},
- {"CTDS" , 4, 1, 638, "RO", 0, 0, 1ull, 1ull},
- {"ARI" , 5, 1, 638, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OPS" , 6, 1, 638, "RO", 0, 0, 0ull, 0ull},
- {"ATOM32S" , 7, 1, 638, "RO", 0, 0, 0ull, 0ull},
- {"ATOM64S" , 8, 1, 638, "RO", 0, 0, 0ull, 0ull},
- {"ATOM128S" , 9, 1, 638, "RO", 0, 0, 0ull, 0ull},
- {"NOROPRPR" , 10, 1, 638, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 638, "RAZ", 1, 1, 0, 0},
- {"TPH" , 12, 2, 638, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 638, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 639, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 639, "R/W", 0, 0, 0ull, 0ull},
- {"ARI" , 5, 1, 639, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP" , 6, 1, 639, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP_EB" , 7, 1, 639, "RO", 0, 0, 0ull, 0ull},
- {"ID0_RQ" , 8, 1, 639, "RO", 0, 0, 0ull, 0ull},
- {"ID0_CP" , 9, 1, 639, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 639, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 640, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 640, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 640, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 640, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 641, "R/W", 1, 0, 0, 2ull},
- {"EC" , 4, 1, 641, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 641, "RO", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 641, "RO", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 641, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 641, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 641, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 641, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 641, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 641, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 641, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 642, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 642, "RO", 0, 0, 2ull, 2ull},
- {"NCO" , 20, 12, 642, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 643, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 643, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 643, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 643, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 643, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 643, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 643, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 643, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 643, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 643, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 643, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 643, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 643, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 643, "RAZ", 1, 1, 0, 0},
- {"UATOMBS" , 24, 1, 643, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 643, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 644, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 644, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 644, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 644, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 644, "RAZ", 1, 1, 0, 0},
- {"UATOMBM" , 24, 1, 644, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 644, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 645, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 645, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 645, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 645, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 645, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 645, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 645, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 645, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 645, "RO", 0, 0, 2ull, 2ull},
- {"UATOMBS" , 24, 1, 645, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 645, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 646, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 646, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 646, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 647, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 647, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 647, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 647, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 647, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 648, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 648, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 648, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 648, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 648, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 649, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 650, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 651, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 652, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 653, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 653, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 654, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 655, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 655, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 655, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 655, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 655, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 656, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 656, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 656, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 656, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 656, "R/W", 0, 0, 3ull, 3ull},
- {"EASPML1" , 30, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 656, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 657, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 657, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 657, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 657, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 657, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_22_31" , 22, 10, 657, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 658, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 658, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"MFUNCN" , 0, 8, 659, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_13" , 8, 6, 659, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 659, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 659, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 659, "R/W", 0, 0, 0ull, 0ull},
- {"CX_NFUNC" , 29, 3, 659, "R/W", 0, 0, 0ull, 0ull},
- {"SKPIV" , 0, 11, 660, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 660, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 660, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_DABORT_4UCPL" , 2, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"M_HANDLE_FLUSH" , 3, 1, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 661, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 662, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 663, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 664, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 664, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 664, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 665, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 665, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 665, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 666, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 666, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 666, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 667, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 668, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 668, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 668, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 668, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 669, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 669, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 669, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 669, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 670, "RO/WRSL", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 670, "RO/WRSL", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 670, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 670, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 670, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 670, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 670, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 671, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"HEADER_CREDITS" , 12, 8, 671, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 671, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 671, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 671, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 672, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 672, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 672, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 672, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 672, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 673, "RO/WRSL", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 673, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 673, "RO/WRSL", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 673, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 674, "RO/WRSL", 0, 0, 136ull, 136ull},
- {"RESERVED_14_15" , 14, 2, 674, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 674, "RO/WRSL", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 674, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 675, "RO/WRSL", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 675, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 675, "RO/WRSL", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 675, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 676, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 676, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 676, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 677, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 678, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 679, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 679, "R/W", 0, 0, 146ull, 146ull},
- {"ISAE" , 0, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 680, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 680, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 680, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 680, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 680, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 680, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 681, "R/W", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 681, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 681, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 681, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 682, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 682, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 682, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 682, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 682, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 683, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 684, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 685, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 685, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 685, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 685, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 686, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 686, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 686, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 686, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 686, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 686, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 686, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 686, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 686, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 686, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 686, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 686, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 686, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 686, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 686, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 686, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 686, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 687, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 687, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 687, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 687, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 688, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 688, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 688, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 688, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 688, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 688, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 689, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 690, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 691, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 691, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 692, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 692, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 693, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 694, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 694, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 694, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 694, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 694, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 695, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 695, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 695, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 695, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 695, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 695, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 695, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 695, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 696, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 696, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 696, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 696, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 696, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 696, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 696, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 696, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 696, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 696, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 696, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 696, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 697, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 697, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 697, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 697, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 697, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 697, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 697, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 698, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 698, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 699, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 700, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 700, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 701, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 701, "R/W", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 701, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 701, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 701, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 701, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 701, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 702, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 702, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 702, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 702, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 702, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 702, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 702, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 702, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 702, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 702, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 702, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 703, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 703, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 703, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 703, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 703, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 703, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 703, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 703, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 703, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 704, "R/W", 1, 1, 0, 0},
- {"MLW" , 4, 6, 704, "R/W", 0, 0, 4ull, 4ull},
- {"ASLPMS" , 10, 2, 704, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 704, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 704, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 704, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 704, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 704, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ASPM" , 22, 1, 704, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 704, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 704, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 705, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 705, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 705, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 705, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 705, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 705, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 705, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 705, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 705, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 705, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 705, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 705, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 705, "RO", 1, 1, 0, 0},
- {"NLW" , 20, 6, 705, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 705, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 705, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 705, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 705, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 705, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 705, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 706, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 706, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 706, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 707, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 707, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 707, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 707, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 707, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 707, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 707, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 707, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 707, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 707, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 707, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 707, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 708, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 708, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 708, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 708, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 708, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 708, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 709, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 709, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 709, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 709, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 710, "RO", 0, 0, 15ull, 15ull},
- {"CTDS" , 4, 1, 710, "RO", 0, 0, 1ull, 1ull},
- {"ARI" , 5, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OPS" , 6, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"ATOM32S" , 7, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"ATOM64S" , 8, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"ATOM128S" , 9, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"NOROPRPR" , 10, 1, 710, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_11_11" , 11, 1, 710, "RAZ", 1, 1, 0, 0},
- {"TPH" , 12, 2, 710, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 710, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 711, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 711, "R/W", 0, 0, 0ull, 0ull},
- {"ARI" , 5, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP" , 6, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP_EB" , 7, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"ID0_RQ" , 8, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"ID0_CP" , 9, 1, 711, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 711, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 712, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 712, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 712, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 713, "R/W", 1, 1, 0, 0},
- {"EC" , 4, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 713, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 713, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 713, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 713, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 714, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 715, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 716, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 716, "RO", 0, 0, 2ull, 2ull},
- {"NCO" , 20, 12, 716, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 717, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 717, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 717, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 717, "RAZ", 1, 1, 0, 0},
- {"UATOMBS" , 24, 1, 717, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 717, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 718, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 718, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 718, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 718, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 718, "RAZ", 1, 1, 0, 0},
- {"UATOMBM" , 24, 1, 718, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 718, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 719, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 719, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 719, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 719, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 719, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 719, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 719, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 719, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 719, "RO", 0, 0, 2ull, 2ull},
- {"UATOMBS" , 24, 1, 719, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 719, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 720, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 720, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 720, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 720, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 720, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 720, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 720, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 720, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 720, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 721, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 721, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 721, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 721, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 721, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 721, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 721, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 721, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 721, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 722, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 722, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 722, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 722, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 722, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 722, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 723, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 724, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 725, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 726, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 727, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 727, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 727, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 727, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 728, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 728, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 728, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 728, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 728, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 728, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 728, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 728, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 728, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 729, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 729, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 730, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 730, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 731, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 732, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 732, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 732, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 732, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 732, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 732, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 733, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 733, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 733, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 733, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 733, "R/W", 0, 0, 3ull, 3ull},
- {"EASPML1" , 30, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 733, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 734, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 734, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 734, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 734, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 734, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 734, "R/W", 0, 0, 15ull, 7ull},
- {"RESERVED_22_31" , 22, 10, 734, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 735, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 735, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 735, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 735, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 735, "R/W", 0, 0, 0ull, 0ull},
- {"MFUNCN" , 0, 8, 736, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_13" , 8, 6, 736, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 736, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 736, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 736, "R/W", 0, 0, 0ull, 0ull},
- {"CX_NFUNC" , 29, 3, 736, "R/W", 0, 0, 0ull, 0ull},
- {"SKPIV" , 0, 11, 737, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 737, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 737, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 737, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 738, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 738, "R/W", 0, 0, 0ull, 0ull},
- {"M_DABORT_4UCPL" , 2, 1, 738, "R/W", 0, 0, 0ull, 0ull},
- {"M_HANDLE_FLUSH" , 3, 1, 738, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 738, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 739, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 740, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 741, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 741, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 741, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 742, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 742, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 742, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 743, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 743, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 743, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 744, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 744, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 744, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 744, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 745, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 745, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 745, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 745, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 746, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 746, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 746, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 746, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 747, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 747, "R/W", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 747, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 747, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 747, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 747, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 747, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 748, "R/W", 0, 0, 32ull, 32ull},
- {"HEADER_CREDITS" , 12, 8, 748, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 748, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 748, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 748, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 749, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 749, "R/W", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 749, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 749, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 749, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 750, "R/W", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 750, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 750, "R/W", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 750, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 751, "R/W", 0, 0, 136ull, 136ull},
- {"RESERVED_14_15" , 14, 2, 751, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 751, "R/W", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 751, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 752, "R/W", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 752, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 752, "R/W", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 752, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 753, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 753, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 753, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 753, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 754, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 755, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 756, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 756, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 756, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 756, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 756, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 756, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 756, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 756, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 756, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 757, "RO", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 757, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 757, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 757, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 757, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 757, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 758, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 758, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 758, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 758, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 758, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 758, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 758, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 758, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 758, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 759, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 759, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 759, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 759, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 759, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 759, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 760, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 12, 1, 760, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 760, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 12, 1, 761, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 761, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 762, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 762, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 763, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 763, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 763, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 764, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 764, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 764, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 765, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 765, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 765, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 765, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 765, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 765, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 766, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 766, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 766, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 766, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 766, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 766, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 766, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 767, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 767, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 767, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 767, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 767, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 767, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 767, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 768, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 768, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 768, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 769, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 769, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 769, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 769, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 769, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 769, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 769, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 769, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 770, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 770, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 770, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 770, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 770, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 770, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 770, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 771, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 771, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 771, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 771, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 772, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 772, "RAZ", 1, 1, 0, 0},
- {"L0SYNC" , 0, 1, 773, "RO", 0, 0, 0ull, 1ull},
- {"L1SYNC" , 1, 1, 773, "RO", 0, 0, 0ull, 1ull},
- {"L2SYNC" , 2, 1, 773, "RO", 0, 0, 0ull, 1ull},
- {"L3SYNC" , 3, 1, 773, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_4_10" , 4, 7, 773, "RAZ", 1, 1, 0, 0},
- {"PATTST" , 11, 1, 773, "RO", 0, 0, 0ull, 0ull},
- {"ALIGND" , 12, 1, 773, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_63" , 13, 51, 773, "RAZ", 1, 1, 0, 0},
- {"BIST_STATUS" , 0, 1, 774, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 774, "RAZ", 1, 1, 0, 0},
- {"BITLCK0" , 0, 1, 775, "RO", 0, 1, 0ull, 0},
- {"BITLCK1" , 1, 1, 775, "RO", 0, 1, 0ull, 0},
- {"BITLCK2" , 2, 1, 775, "RO", 0, 1, 0ull, 0},
- {"BITLCK3" , 3, 1, 775, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 775, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 776, "RAZ", 1, 1, 0, 0},
- {"SPD" , 2, 4, 776, "RO", 0, 0, 0ull, 0ull},
- {"SPDSEL0" , 6, 1, 776, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_10" , 7, 4, 776, "RAZ", 1, 1, 0, 0},
- {"LO_PWR" , 11, 1, 776, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 776, "RAZ", 1, 1, 0, 0},
- {"SPDSEL1" , 13, 1, 776, "RO", 0, 0, 1ull, 1ull},
- {"LOOPBCK1" , 14, 1, 776, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 776, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 776, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 777, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 777, "RAZ", 1, 1, 0, 0},
- {"TXFLT_EN" , 0, 1, 778, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 1, 1, 778, "R/W", 0, 0, 0ull, 1ull},
- {"RXSYNBAD_EN" , 2, 1, 778, "R/W", 0, 0, 0ull, 1ull},
- {"BITLCKLS_EN" , 3, 1, 778, "R/W", 0, 0, 0ull, 1ull},
- {"SYNLOS_EN" , 4, 1, 778, "R/W", 0, 0, 0ull, 1ull},
- {"ALGNLOS_EN" , 5, 1, 778, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 6, 1, 778, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 778, "RAZ", 1, 1, 0, 0},
- {"TXFLT" , 0, 1, 779, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 1, 1, 779, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXSYNBAD" , 2, 1, 779, "R/W1C", 0, 0, 0ull, 0ull},
- {"BITLCKLS" , 3, 1, 779, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNLOS" , 4, 1, 779, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALGNLOS" , 5, 1, 779, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 6, 1, 779, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 779, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 780, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 780, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 780, "R/W1C", 0, 0, 0ull, 0ull},
- {"DROP_LN" , 4, 2, 780, "R/W", 0, 0, 0ull, 0ull},
- {"ENC_MODE" , 6, 1, 780, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 780, "RAZ", 1, 1, 0, 0},
- {"GMXENO" , 0, 1, 781, "R/W", 0, 0, 0ull, 0ull},
- {"XAUI" , 1, 1, 781, "RO", 1, 1, 0, 0},
- {"RX_SWAP" , 2, 1, 781, "R/W", 0, 1, 0ull, 0},
- {"TX_SWAP" , 3, 1, 781, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 781, "RAZ", 1, 1, 0, 0},
- {"SYNC0ST" , 0, 4, 782, "RO", 0, 1, 0ull, 0},
- {"SYNC1ST" , 4, 4, 782, "RO", 0, 1, 0ull, 0},
- {"SYNC2ST" , 8, 4, 782, "RO", 0, 1, 0ull, 0},
- {"SYNC3ST" , 12, 4, 782, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 782, "RAZ", 1, 1, 0, 0},
- {"TENGB" , 0, 1, 783, "RO", 0, 0, 1ull, 1ull},
- {"TENPASST" , 1, 1, 783, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 783, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 784, "RAZ", 1, 1, 0, 0},
- {"LPABLE" , 1, 1, 784, "RO", 0, 0, 1ull, 1ull},
- {"RCV_LNK" , 2, 1, 784, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_3_6" , 3, 4, 784, "RAZ", 1, 1, 0, 0},
- {"FLT" , 7, 1, 784, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 784, "RAZ", 1, 1, 0, 0},
- {"TENGB_R" , 0, 1, 785, "RO", 0, 0, 0ull, 0ull},
- {"TENGB_X" , 1, 1, 785, "RO", 0, 0, 1ull, 1ull},
- {"TENGB_W" , 2, 1, 785, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_9" , 3, 7, 785, "RAZ", 1, 1, 0, 0},
- {"RCVFLT" , 10, 1, 785, "RC", 0, 0, 0ull, 0ull},
- {"XMTFLT" , 11, 1, 785, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 785, "RAZ", 1, 1, 0, 0},
- {"DEV" , 14, 2, 785, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_16_63" , 16, 48, 785, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 786, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 786, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_TXPLRT" , 2, 4, 786, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_RXPLRT" , 6, 4, 786, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 786, "RAZ", 1, 1, 0, 0},
- {"TX_ST" , 0, 3, 787, "RO", 0, 1, 0ull, 0},
- {"RX_ST" , 3, 2, 787, "RO", 0, 1, 0ull, 0},
- {"ALGN_ST" , 5, 3, 787, "RO", 0, 1, 0ull, 0},
- {"RXBAD" , 8, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"SYN0BAD" , 9, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"SYN1BAD" , 10, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"SYN2BAD" , 11, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"SYN3BAD" , 12, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"TERM_ERR" , 13, 1, 787, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 787, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 788, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 788, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 788, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 16, 788, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 788, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 789, "RAZ", 1, 1, 0, 0},
- {"MASK" , 3, 35, 789, "R/W", 0, 0, 34359738367ull, 34359738367ull},
- {"RESERVED_38_63" , 38, 26, 789, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 790, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 790, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 790, "R/W", 0, 0, 0ull, 1ull},
- {"BAR1_SIZ" , 4, 3, 790, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_7_63" , 7, 57, 790, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 791, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 791, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 791, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 3, 1, 791, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 4, 1, 791, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 5, 1, 791, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 6, 1, 791, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 7, 1, 791, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 791, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 792, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 792, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 792, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 792, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 792, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 792, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 6, 1, 792, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 7, 1, 792, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 8, 1, 792, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 9, 1, 792, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 792, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 793, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 793, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 794, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 794, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 795, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 795, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"FAST_LM" , 2, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 796, "R/W", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 796, "RAZ", 0, 0, 0ull, 0ull},
- {"CFG_RTRY" , 16, 16, 796, "R/W", 0, 0, 0ull, 32ull},
- {"RESERVED_32_33" , 32, 2, 796, "RAZ", 1, 1, 0, 0},
- {"PBUS" , 34, 8, 796, "RO", 1, 1, 0, 0},
- {"DNUM" , 42, 5, 796, "RO", 1, 1, 0, 0},
- {"AUTO_SD" , 47, 1, 796, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 796, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 797, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 798, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 798, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 799, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 799, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 799, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 799, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 799, "RO", 1, 1, 0, 0},
- {"NUM" , 0, 6, 800, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 800, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 801, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 802, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 802, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 803, "RO", 0, 0, 0ull, 0ull},
- {"SE" , 1, 1, 803, "R/W1C", 0, 0, 0ull, 0ull},
- {"PMEI" , 2, 1, 803, "RO", 0, 0, 0ull, 0ull},
- {"PMEM" , 3, 1, 803, "RO", 0, 0, 0ull, 0ull},
- {"UP_B1" , 4, 1, 803, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_B2" , 5, 1, 803, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_BX" , 6, 1, 803, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B1" , 7, 1, 803, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B2" , 8, 1, 803, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_BX" , 9, 1, 803, "R/W1C", 0, 0, 0ull, 0ull},
- {"EXC" , 10, 1, 803, "RO", 0, 0, 0ull, 0ull},
- {"RDLK" , 11, 1, 803, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_ER" , 12, 1, 803, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_DR" , 13, 1, 803, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 803, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 804, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 804, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 805, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 805, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_40" , 0, 41, 806, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 41, 23, 806, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 807, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 807, "R/W", 0, 1, 4503599627370495ull, 0},
- {"RESERVED_0_11" , 0, 12, 808, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 808, "R/W", 0, 1, 4503599627370495ull, 0},
- {"SLI_P" , 0, 8, 809, "R/W", 0, 0, 128ull, 128ull},
- {"SLI_NP" , 8, 8, 809, "R/W", 0, 0, 16ull, 16ull},
- {"SLI_CPL" , 16, 8, 809, "R/W", 0, 0, 128ull, 128ull},
- {"PEM_P" , 24, 8, 809, "R/W", 0, 0, 128ull, 128ull},
- {"PEM_NP" , 32, 8, 809, "R/W", 0, 0, 16ull, 16ull},
- {"PEM_CPL" , 40, 8, 809, "R/W", 0, 0, 128ull, 128ull},
- {"PEAI_PPF" , 48, 8, 809, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_56_63" , 56, 8, 809, "RAZ", 1, 1, 0, 0},
- {"SKIP1" , 0, 7, 810, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 810, "RAZ", 1, 1, 0, 0},
- {"SKIP2" , 8, 7, 810, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 810, "RAZ", 1, 1, 0, 0},
- {"SKIP3" , 16, 7, 810, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_31" , 23, 9, 810, "RAZ", 1, 1, 0, 0},
- {"BIT0" , 32, 6, 810, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_39" , 38, 2, 810, "RAZ", 1, 1, 0, 0},
- {"BIT1" , 40, 6, 810, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_55" , 46, 10, 810, "RAZ", 1, 1, 0, 0},
- {"LEN" , 56, 1, 810, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_57_63" , 57, 7, 810, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 811, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 811, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 811, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 811, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 811, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 20, 812, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 812, "RAZ", 1, 1, 0, 0},
- {"CLKEN" , 0, 1, 813, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 813, "RAZ", 0, 1, 0ull, 0},
- {"DPRT" , 0, 16, 814, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 814, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 814, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 814, "RAZ", 1, 1, 0, 0},
- {"MAP0" , 0, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 815, "R/W", 0, 0, 0ull, 0ull},
- {"MAP0" , 0, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 816, "R/W", 0, 0, 0ull, 0ull},
- {"MINLEN" , 0, 16, 817, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 817, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 817, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 818, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 818, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 818, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 818, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 818, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 818, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 819, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 819, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 819, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 819, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 819, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 819, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 819, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 819, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 819, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 819, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 819, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 819, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 819, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 20, 1, 819, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_23" , 21, 3, 819, "RAZ", 1, 1, 0, 0},
- {"DSA_GRP_SID" , 24, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SCMD" , 25, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_TVID" , 26, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"IHMSK_DIS" , 27, 1, 819, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 819, "RAZ", 1, 1, 0, 0},
- {"PRI" , 0, 6, 820, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 820, "RAZ", 1, 1, 0, 0},
- {"QOS" , 8, 3, 820, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 820, "RAZ", 1, 1, 0, 0},
- {"UP_QOS" , 12, 1, 820, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_13_63" , 13, 51, 820, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 821, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 822, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 822, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 823, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 823, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 824, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 824, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 824, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_EN" , 10, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"HIGIG_EN" , 11, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"CRC_EN" , 12, 1, 824, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 824, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VSEL" , 19, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 824, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 824, "R/W", 0, 0, 0ull, 0ull},
- {"HG_QOS" , 27, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT" , 28, 4, 824, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 824, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 824, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 824, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 824, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 824, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 824, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 824, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_63" , 53, 11, 824, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_35" , 0, 36, 825, "RAZ", 1, 1, 0, 0},
- {"ALT_SKP_EN" , 36, 1, 825, "R/W", 0, 1, 0ull, 0},
- {"ALT_SKP_SEL" , 37, 2, 825, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_39_63" , 39, 25, 825, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 826, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 826, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 826, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 826, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 826, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 826, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 826, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 826, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 827, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 827, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 828, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 828, "RAZ", 1, 1, 0, 0},
- {"QOS1" , 4, 3, 828, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 828, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 829, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 829, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 829, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 829, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 829, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 829, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 829, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 829, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 829, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 830, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 830, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 831, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 831, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 832, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 832, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 833, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 833, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 834, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 834, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 835, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 835, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 836, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 836, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 837, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 837, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 838, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 838, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 839, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 839, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 840, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 840, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 841, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 841, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 842, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 842, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 843, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 843, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 844, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 844, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 845, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 845, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 846, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 846, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 847, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 847, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 848, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 848, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 849, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 849, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 850, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 850, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 850, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 851, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 851, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 851, "RO", 1, 1, 0, 0},
- {"TYPE0" , 0, 16, 852, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE1" , 16, 16, 852, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE2" , 32, 16, 852, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE3" , 48, 16, 852, "R/W", 0, 0, 33024ull, 33024ull},
- {"DRP_OCTS" , 0, 32, 853, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 853, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 854, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 854, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 855, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 855, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 856, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 856, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 857, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 857, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 858, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 858, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 859, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 859, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 860, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 860, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 861, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 861, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 862, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 862, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 863, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 863, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 864, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 864, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 32, 865, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 865, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 866, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 866, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 867, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 867, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 867, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 867, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 868, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 868, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 868, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 868, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 868, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 869, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 869, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 869, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 869, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 870, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 870, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 870, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 870, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 870, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 870, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 870, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 870, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 871, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 871, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 871, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 871, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 872, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 872, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 872, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 872, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 872, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 873, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 874, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 874, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 874, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 874, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 874, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 875, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 876, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 876, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 876, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 876, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 876, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 876, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 876, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 876, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 876, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 876, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 876, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 876, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 876, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 877, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 877, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 877, "RO", 1, 0, 0, 0ull},
- {"MAJOR_3" , 54, 1, 877, "RO", 1, 0, 0, 0ull},
- {"PTP" , 55, 1, 877, "RO", 1, 0, 0, 0ull},
- {"RESERVED_56_63" , 56, 8, 877, "RAZ", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 878, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 878, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 878, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 878, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 878, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 878, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 878, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 878, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 878, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 878, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 878, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 878, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 878, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 879, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 879, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 879, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 879, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 879, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 879, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 880, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 880, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 880, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 880, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 6, 1, 880, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 880, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 880, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 880, "RO", 1, 0, 0, 0ull},
- {"QID_IDX" , 29, 4, 880, "RO", 1, 1, 0, 0},
- {"RESERVED_33_33" , 33, 1, 880, "RAZ", 1, 1, 0, 0},
- {"QID_QQOS" , 34, 8, 880, "RO", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 880, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 881, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 881, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 881, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 881, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 882, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 882, "R/W", 1, 0, 0, 0ull},
- {"BP_PORT" , 10, 6, 882, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_52" , 16, 37, 882, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 882, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 61, 1, 882, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_62_63" , 62, 2, 882, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 883, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 883, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_10_52" , 10, 43, 883, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 883, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 883, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 884, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 884, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 884, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 884, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 884, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 885, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 885, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 885, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 885, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 886, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 886, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 886, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 886, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 886, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 886, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 886, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 886, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 886, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 887, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 887, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 887, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 887, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 887, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 888, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 888, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 888, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 888, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 888, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 888, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 8, 888, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 888, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 888, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 888, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 888, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 3, 888, "RO", 1, 0, 0, 0ull},
- {"OUT_DAT" , 32, 1, 888, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 888, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 888, "RO", 1, 0, 0, 0ull},
- {"RESERVED_35_63" , 35, 29, 888, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 889, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 889, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 889, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 889, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 890, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 891, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 892, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 893, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE1" , 4, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE2" , 8, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE3" , 12, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE4" , 16, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE5" , 20, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE6" , 24, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE7" , 28, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE8" , 32, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE9" , 36, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE10" , 40, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE11" , 44, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE12" , 48, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE13" , 52, 4, 894, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_56_63" , 56, 8, 894, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 14, 895, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 895, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 896, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 896, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 896, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 896, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 897, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 897, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 897, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 897, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_6" , 4, 3, 897, "RAZ", 1, 1, 0, 0},
- {"DIS_PERF2" , 7, 1, 897, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_PERF3" , 8, 1, 897, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 897, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 898, "R/W", 0, 0, 0ull, 0ull},
- {"MODE1" , 3, 3, 898, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 898, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 899, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 899, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 899, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 899, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 16, 900, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 900, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 901, "RAZ", 1, 1, 0, 0},
- {"PREEMPTER" , 0, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"PREEMPTEE" , 1, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 902, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 903, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 904, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 904, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 904, "RAZ", 1, 1, 0, 0},
- {"WQE_WORD" , 0, 4, 905, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_4_63" , 4, 60, 905, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 1, 906, "RO", 0, 0, 0ull, 0ull},
- {"PEND" , 1, 1, 906, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 2, 1, 906, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 3, 1, 906, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 4, 4, 906, "RO", 0, 0, 0ull, 0ull},
- {"NBR" , 8, 3, 906, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 11, 1, 906, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 906, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 10, 906, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 906, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 907, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 907, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 908, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 908, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 908, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 908, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 908, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 908, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 908, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 908, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 908, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 908, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 908, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 908, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 908, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 909, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 909, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 910, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 910, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 911, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 911, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 912, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 912, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 913, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 913, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 914, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 914, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 11, 915, "RO", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 915, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 916, "R/W", 0, 0, 0ull, 1023ull},
- {"RESERVED_10_63" , 10, 54, 916, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 917, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 917, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 918, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 918, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 918, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 918, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 918, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 918, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 918, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 918, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 918, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 918, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 919, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 919, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 919, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 919, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 919, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 10, 920, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_11" , 10, 2, 920, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 10, 920, "R/W", 0, 1, 1023ull, 0},
- {"RESERVED_22_23" , 22, 2, 920, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 11, 920, "RO", 0, 1, 1003ull, 0},
- {"RESERVED_35_35" , 35, 1, 920, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 36, 11, 920, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_47" , 47, 1, 920, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 48, 11, 920, "RO", 0, 1, 0ull, 0},
- {"RESERVED_59_63" , 59, 5, 920, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 921, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 921, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 922, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 922, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 923, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 923, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 924, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 924, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 924, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 11, 925, "RO", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 925, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 12, 11, 925, "RO", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 925, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 24, 4, 925, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 925, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 926, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 926, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 926, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 926, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 926, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 10, 927, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_11" , 10, 2, 927, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 10, 927, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_23" , 22, 2, 927, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 927, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 927, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 927, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 928, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 928, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 929, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 930, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 931, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 932, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 932, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 932, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 932, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 932, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 933, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 933, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 933, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 933, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 933, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 934, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 934, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 934, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 934, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 935, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 935, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 935, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 935, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 935, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 935, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 935, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 935, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 935, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 935, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 936, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 937, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 937, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 937, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 938, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 938, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 938, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 938, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 938, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 938, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 938, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 939, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 939, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 940, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 941, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 942, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 943, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 943, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 943, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 943, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 943, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 943, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 943, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 943, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 943, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 943, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 943, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 943, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 943, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 943, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 943, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 943, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 943, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 943, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 944, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 944, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 944, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 945, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 945, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 946, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 946, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 946, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 947, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 947, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 947, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 947, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 947, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 947, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 947, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 948, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 948, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 949, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 949, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 950, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 950, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 951, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 951, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 951, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 952, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 952, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 952, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 953, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 953, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 953, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 953, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 953, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 953, "R/W", 0, 0, 0ull, 0ull},
- {"EER_VAL" , 9, 1, 953, "RO", 0, 0, 0ull, 0ull},
- {"EER_LCK" , 10, 1, 953, "RO", 0, 0, 0ull, 0ull},
- {"DIS_MAK" , 11, 1, 953, "R/W1", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 953, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 954, "RO", 1, 1, 0, 0},
- {"KEY" , 0, 64, 955, "WO", 0, 0, 0ull, 0ull},
- {"DAT" , 0, 64, 956, "RO", 1, 1, 0, 0},
- {"NCB_CMD" , 0, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_0" , 2, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_1" , 3, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_0" , 4, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_1" , 5, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 957, "RAZ", 1, 1, 0, 0},
- {"P2N1_P1" , 9, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_24" , 19, 6, 957, "RAZ", 1, 1, 0, 0},
- {"CPL_P1" , 25, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_28" , 27, 2, 957, "RAZ", 1, 1, 0, 0},
- {"N2P0_O" , 29, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 957, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_4" , 1, 4, 958, "R/W", 0, 0, 0ull, 0ull},
- {"PTLP_RO" , 5, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 958, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 958, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 958, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 958, "R/W", 0, 0, 3ull, 3ull},
- {"WAITL_COM" , 16, 1, 958, "R/W", 0, 1, 0ull, 0},
- {"DIS_PORT" , 17, 1, 958, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTA" , 18, 1, 958, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 19, 1, 958, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 20, 1, 958, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 21, 1, 958, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 958, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 959, "RO", 1, 1, 0, 0},
- {"P0_NTAGS" , 8, 6, 959, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_14_63" , 14, 50, 959, "R/W", 0, 0, 32ull, 32ull},
- {"P0_FCNT" , 0, 6, 960, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 960, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 960, "RAZ", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 960, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 960, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 961, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 961, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 961, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 32, 962, "R/W", 0, 1, 0ull, 0},
- {"ADBG_SEL" , 32, 1, 962, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 962, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 963, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 963, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 964, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 964, "R/W", 0, 1, 0ull, 0},
- {"TIM" , 0, 32, 965, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 965, "RAZ", 1, 1, 0, 0},
- {"RML_TO" , 0, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 966, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 966, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UP_B0" , 20, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M2_UP_WI" , 21, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M2_UN_B0" , 22, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M2_UN_WI" , 23, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M3_UP_B0" , 24, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M3_UP_WI" , 25, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M3_UN_B0" , 26, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"M3_UN_WI" , 27, 1, 966, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_28_31" , 28, 4, 966, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 966, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 966, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 966, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 966, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT2_ERR" , 58, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT3_ERR" , 59, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 966, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 966, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 967, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT1" , 17, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"MAC0_INT" , 18, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"MAC1_INT" , 19, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M2_UP_B0" , 20, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M2_UP_WI" , 21, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M2_UN_B0" , 22, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M2_UN_WI" , 23, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M3_UP_B0" , 24, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M3_UP_WI" , 25, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M3_UN_B0" , 26, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"M3_UN_WI" , 27, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_28_31" , 28, 4, 967, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 967, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 967, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 967, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 967, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT2_ERR" , 58, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT3_ERR" , 59, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 967, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 967, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT" , 4, 1, 968, "RO", 0, 0, 0ull, 0ull},
- {"PTIME" , 5, 1, 968, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_WI" , 9, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_B0" , 10, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_WI" , 11, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_B0" , 12, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_WI" , 13, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_B0" , 14, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_WI" , 15, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO_INT0" , 16, 1, 968, "RO", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 968, "RO", 0, 0, 0ull, 0ull},
- {"MAC0_INT" , 18, 1, 968, "RO", 0, 0, 0ull, 0ull},
- {"MAC1_INT" , 19, 1, 968, "RO", 0, 0, 0ull, 0ull},
- {"M2_UP_B0" , 20, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M2_UP_WI" , 21, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M2_UN_B0" , 22, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M2_UN_WI" , 23, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UP_B0" , 24, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UP_WI" , 25, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UN_B0" , 26, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UN_WI" , 27, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 968, "RAZ", 1, 1, 0, 0},
- {"DMAFI" , 32, 2, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 968, "RO", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 968, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 968, "RAZ", 1, 1, 0, 0},
- {"PIDBOF" , 48, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT2_ERR" , 58, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT3_ERR" , 59, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 968, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 968, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 969, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 970, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 971, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 972, "RO", 0, 1, 0ull, 0},
- {"P0_PCNT" , 0, 8, 973, "R/W", 0, 0, 128ull, 128ull},
- {"P0_NCNT" , 8, 8, 973, "R/W", 0, 0, 16ull, 16ull},
- {"P0_CCNT" , 16, 8, 973, "R/W", 0, 0, 128ull, 128ull},
- {"P1_PCNT" , 24, 8, 973, "R/W", 0, 0, 128ull, 128ull},
- {"P1_NCNT" , 32, 8, 973, "R/W", 0, 0, 16ull, 16ull},
- {"P1_CCNT" , 40, 8, 973, "R/W", 0, 0, 128ull, 128ull},
- {"P0_P_D" , 48, 1, 973, "R/W", 0, 0, 1ull, 1ull},
- {"P0_N_D" , 49, 1, 973, "R/W", 0, 0, 1ull, 1ull},
- {"P0_C_D" , 50, 1, 973, "R/W", 0, 0, 1ull, 1ull},
- {"P1_P_D" , 51, 1, 973, "R/W", 0, 0, 1ull, 1ull},
- {"P1_N_D" , 52, 1, 973, "R/W", 0, 0, 1ull, 1ull},
- {"P1_C_D" , 53, 1, 973, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_54_63" , 54, 10, 973, "RAZ", 1, 1, 0, 0},
- {"P2_PCNT" , 0, 8, 974, "R/W", 0, 0, 128ull, 128ull},
- {"P2_NCNT" , 8, 8, 974, "R/W", 0, 0, 16ull, 16ull},
- {"P2_CCNT" , 16, 8, 974, "R/W", 0, 0, 128ull, 128ull},
- {"P3_PCNT" , 24, 8, 974, "R/W", 0, 0, 128ull, 128ull},
- {"P3_NCNT" , 32, 8, 974, "R/W", 0, 0, 16ull, 16ull},
- {"P3_CCNT" , 40, 8, 974, "R/W", 0, 0, 128ull, 128ull},
- {"P2_P_D" , 48, 1, 974, "R/W", 0, 0, 1ull, 1ull},
- {"P2_N_D" , 49, 1, 974, "R/W", 0, 0, 1ull, 1ull},
- {"P2_C_D" , 50, 1, 974, "R/W", 0, 0, 1ull, 1ull},
- {"P3_P_D" , 51, 1, 974, "R/W", 0, 0, 1ull, 1ull},
- {"P3_N_D" , 52, 1, 974, "R/W", 0, 0, 1ull, 1ull},
- {"P3_C_D" , 53, 1, 974, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_54_63" , 54, 10, 974, "RAZ", 1, 1, 0, 0},
- {"NUM" , 0, 8, 975, "RO", 1, 1, 0, 0},
- {"A_MODE" , 8, 1, 975, "RO", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 975, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 976, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 976, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 976, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 30, 977, "R/W", 0, 1, 0ull, 0},
- {"RTYPE" , 30, 2, 977, "R/W", 0, 1, 0ull, 0},
- {"WTYPE" , 32, 2, 977, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 977, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 977, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 977, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 3, 977, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 42, 1, 977, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 977, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 978, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 979, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 980, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 981, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 982, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 983, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 984, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 986, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 986, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 986, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 64, 987, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 988, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 989, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 990, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 991, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 992, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 993, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 994, "R/W", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 995, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 995, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 995, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 996, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 996, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 997, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 997, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 997, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 998, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 998, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 998, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 999, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 999, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 999, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 32, 22, 1000, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 1000, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"WMARK" , 32, 32, 1001, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_0_2" , 0, 3, 1002, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 1002, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 1003, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 1003, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 1004, "R/W", 0, 1, 0ull, 0},
- {"FCNT" , 32, 5, 1004, "RO", 0, 1, 0ull, 0},
- {"WRP" , 37, 9, 1004, "RO", 0, 1, 0ull, 0},
- {"RRP" , 46, 9, 1004, "RO", 0, 1, 0ull, 0},
- {"MAX" , 55, 9, 1004, "RO", 0, 1, 16ull, 0},
- {"NTAG" , 0, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"NTT" , 1, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"NGRP" , 2, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"NQOS" , 3, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_5" , 4, 2, 1005, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 1005, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_13" , 13, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 1005, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_20" , 16, 5, 1005, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"RNTAG" , 22, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"RNTT" , 23, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"RNGRP" , 24, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"RNQOS" , 25, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_27" , 26, 2, 1005, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 1005, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_35" , 35, 1, 1005, "RAZ", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 1005, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_42" , 38, 5, 1005, "RAZ", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 1005, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 1005, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 1006, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 16, 7, 1006, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 1006, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1007, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 4, 60, 1007, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 1008, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 1008, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 1009, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1009, "RO", 0, 1, 0ull, 0},
- {"PORT" , 0, 32, 1010, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1010, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1011, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1011, "RAZ", 1, 1, 0, 0},
- {"PKT_BP" , 0, 4, 1012, "R/W", 0, 0, 15ull, 15ull},
- {"RING_EN" , 4, 1, 1012, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1012, "RAZ", 1, 1, 0, 0},
- {"ES" , 0, 64, 1013, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 1014, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1014, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 1015, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1015, "RAZ", 1, 1, 0, 0},
- {"DPTR" , 0, 32, 1016, "R/W", 0, 0, 0ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 1016, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 32, 1017, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1017, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1018, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1018, "RO", 0, 1, 0ull, 0},
- {"RD_CNT" , 0, 32, 1019, "RO", 0, 1, 0ull, 0},
- {"WR_CNT" , 32, 32, 1019, "RO", 0, 1, 0ull, 0},
- {"PP" , 0, 64, 1020, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 0, 1, 1021, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 1021, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 1021, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 1021, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 1021, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 1021, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 1021, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 22, 1, 1021, "R/W", 0, 0, 0ull, 1ull},
- {"PIN_RST" , 23, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_39" , 24, 16, 1021, "RAZ", 1, 1, 0, 0},
- {"PRC_IDLE" , 40, 1, 1021, "RO", 0, 1, 0ull, 0},
- {"RESERVED_41_47" , 41, 7, 1021, "RAZ", 1, 1, 0, 0},
- {"GII_RDS" , 48, 7, 1021, "RO", 0, 1, 0ull, 0},
- {"GII_ERST" , 55, 1, 1021, "RO", 0, 1, 0ull, 0},
- {"PRD_RDS" , 56, 7, 1021, "RO", 0, 1, 0ull, 0},
- {"PRD_ERST" , 63, 1, 1021, "RO", 0, 1, 0ull, 0},
- {"ENB" , 0, 32, 1022, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1022, "RAZ", 1, 1, 0, 0},
- {"RDSIZE" , 0, 64, 1023, "R/W", 0, 1, 0ull, 0},
- {"IS_64B" , 0, 32, 1024, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1024, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1025, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 22, 1025, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_63" , 54, 10, 1025, "RAZ", 1, 1, 0, 0},
- {"IPTR" , 0, 32, 1026, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1026, "RAZ", 1, 1, 0, 0},
- {"BMODE" , 0, 32, 1027, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1027, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 1028, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1028, "RAZ", 1, 1, 0, 0},
- {"WMARK" , 0, 32, 1029, "R/W", 0, 0, 0ull, 14ull},
- {"RESERVED_32_63" , 32, 32, 1029, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 64, 1030, "R/W", 0, 1, 0ull, 0},
- {"OUT_RST" , 0, 32, 1031, "RO", 0, 1, 0ull, 0},
- {"IN_RST" , 32, 32, 1031, "RO", 0, 1, 0ull, 0},
- {"ES" , 0, 64, 1032, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 1033, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1033, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 1034, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1034, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1035, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1035, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1036, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1036, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 3, 1037, "R/W", 0, 0, 2ull, 2ull},
- {"BAR0_D" , 3, 1, 1037, "R/W", 1, 1, 0, 0},
- {"WIND_D" , 4, 1, 1037, "R/W", 1, 1, 0, 0},
- {"RESERVED_5_63" , 5, 59, 1037, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 1038, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 1039, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 1040, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 1040, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 1040, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 1040, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 1041, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 1041, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 1041, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 1041, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 1041, "RO", 0, 1, 1ull, 0},
- {"RESERVED_47_47" , 47, 1, 1041, "RAZ", 1, 1, 0, 0},
- {"NNP1" , 48, 8, 1041, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 1041, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 1042, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 1042, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 1042, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 1042, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 1042, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 1043, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 1043, "R/W", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 1043, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_51_63" , 51, 13, 1043, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 1044, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 1045, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 1045, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 1045, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 1045, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 1046, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 1047, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1047, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 1048, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 1048, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 1049, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 1049, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 1049, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 1049, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 1049, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 1049, "R/W", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 1049, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 1049, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 1049, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1049, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 1050, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1050, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 1050, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 1050, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 1050, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1050, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1051, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1051, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 1052, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 1052, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 1052, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1052, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 1053, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 1053, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 1053, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1053, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 1054, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_6_7" , 6, 2, 1054, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 6, 1054, "R/W", 0, 0, 19ull, 19ull},
- {"RESERVED_14_63" , 14, 50, 1054, "RAZ", 1, 1, 0, 0},
- {"DENY_BAR0" , 0, 1, 1055, "R/W", 1, 1, 0, 0},
- {"DENY_BAR1" , 1, 1, 1055, "R/W", 1, 1, 0, 0},
- {"DENY_BAR2" , 2, 1, 1055, "R/W", 1, 1, 0, 0},
- {"RESERVED_3_3" , 3, 1, 1055, "RAZ", 1, 1, 0, 0},
- {"DENY_ADR0" , 4, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"DENY_ADR1" , 5, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"DENY_ADR2" , 6, 1, 1055, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 1055, "RAZ", 1, 1, 0, 0},
- {"ASSY_VEN" , 0, 16, 1056, "R/W", 0, 0, 140ull, 0ull},
- {"ASSY_ID" , 16, 16, 1056, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1056, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 1057, "RAZ", 1, 1, 0, 0},
- {"ASSY_REV" , 16, 16, 1057, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1057, "RAZ", 1, 1, 0, 0},
- {"RP0_PID" , 0, 2, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_PID" , 2, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"RP0_SID" , 3, 2, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_SID" , 5, 1, 1058, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1058, "RAZ", 1, 1, 0, 0},
- {"OMSG" , 0, 7, 1059, "RO", 0, 0, 0ull, 0ull},
- {"IMSG" , 7, 5, 1059, "RO", 0, 0, 0ull, 0ull},
- {"RXBUF" , 12, 2, 1059, "RO", 0, 0, 0ull, 0ull},
- {"TXBUF" , 14, 2, 1059, "RO", 0, 0, 0ull, 0ull},
- {"OSPF" , 16, 1, 1059, "RO", 0, 0, 0ull, 0ull},
- {"ISPF" , 17, 1, 1059, "RO", 0, 0, 0ull, 0ull},
- {"OARB" , 18, 2, 1059, "RO", 0, 0, 0ull, 0ull},
- {"RXBUF2" , 20, 2, 1059, "RO", 0, 0, 0ull, 0ull},
- {"OARB2" , 22, 2, 1059, "RO", 0, 0, 0ull, 0ull},
- {"OPTRS" , 24, 4, 1059, "RO", 0, 0, 0ull, 0ull},
- {"OBULK" , 28, 4, 1059, "RO", 0, 0, 0ull, 0ull},
- {"RTN" , 32, 2, 1059, "RO", 0, 0, 0ull, 0ull},
- {"OFREE" , 34, 1, 1059, "RO", 0, 0, 0ull, 0ull},
- {"ITAG" , 35, 1, 1059, "RO", 0, 0, 0ull, 0ull},
- {"OTAG" , 36, 2, 1059, "RO", 0, 0, 0ull, 0ull},
- {"BELL" , 38, 2, 1059, "RO", 0, 0, 0ull, 0ull},
- {"CRAM" , 40, 2, 1059, "RO", 0, 0, 0ull, 0ull},
- {"MRAM" , 42, 2, 1059, "RO", 0, 0, 0ull, 0ull},
- {"LRAM" , 44, 1, 1059, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_63" , 45, 19, 1059, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 1060, "R/W", 0, 1, 0ull, 0},
- {"PRIO" , 4, 4, 1060, "R/W", 0, 1, 0ull, 0},
- {"LTTR" , 8, 4, 1060, "R/W", 0, 1, 0ull, 0},
- {"PRT_SEL" , 12, 3, 1060, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 1060, "RAZ", 1, 1, 0, 0},
- {"RP0_PID" , 16, 2, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_PID" , 18, 1, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"RP0_SID" , 19, 2, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_SID" , 21, 1, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1060, "RAZ", 1, 1, 0, 0},
- {"RSP_THR" , 24, 6, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_30" , 30, 1, 1060, "RAZ", 1, 1, 0, 0},
- {"TO_MODE" , 31, 1, 1060, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1060, "RAZ", 1, 1, 0, 0},
- {"TAG" , 0, 32, 1061, "R/W", 0, 1, 0ull, 0},
- {"TT" , 32, 2, 1061, "R/W", 0, 1, 0ull, 0},
- {"RS" , 34, 1, 1061, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_41" , 35, 7, 1061, "RAZ", 1, 1, 0, 0},
- {"NTAG" , 42, 1, 1061, "R/W", 0, 1, 0ull, 0},
- {"NTT" , 43, 1, 1061, "R/W", 0, 1, 0ull, 0},
- {"NGRP" , 44, 1, 1061, "R/W", 0, 1, 0ull, 0},
- {"NQOS" , 45, 1, 1061, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_47" , 46, 2, 1061, "RAZ", 1, 1, 0, 0},
- {"SL" , 48, 7, 1061, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_55_55" , 55, 1, 1061, "RAZ", 1, 1, 0, 0},
- {"PM" , 56, 2, 1061, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_62" , 58, 5, 1061, "RAZ", 1, 1, 0, 0},
- {"R" , 63, 1, 1061, "R/W", 0, 1, 0ull, 0},
- {"GRP0" , 0, 4, 1062, "R/W", 0, 1, 0ull, 0},
- {"QOS0" , 4, 3, 1062, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 1062, "RAZ", 1, 1, 0, 0},
- {"GRP1" , 8, 4, 1062, "R/W", 0, 1, 0ull, 0},
- {"QOS1" , 12, 3, 1062, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 1062, "RAZ", 1, 1, 0, 0},
- {"GRP2" , 16, 4, 1062, "R/W", 0, 1, 0ull, 0},
- {"QOS2" , 20, 3, 1062, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_23" , 23, 1, 1062, "RAZ", 1, 1, 0, 0},
- {"GRP3" , 24, 4, 1062, "R/W", 0, 1, 0ull, 0},
- {"QOS3" , 28, 3, 1062, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_31_31" , 31, 1, 1062, "RAZ", 1, 1, 0, 0},
- {"GRP4" , 32, 4, 1062, "R/W", 0, 1, 0ull, 0},
- {"QOS4" , 36, 3, 1062, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_39_39" , 39, 1, 1062, "RAZ", 1, 1, 0, 0},
- {"GRP5" , 40, 4, 1062, "R/W", 0, 1, 0ull, 0},
- {"QOS5" , 44, 3, 1062, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_47_47" , 47, 1, 1062, "RAZ", 1, 1, 0, 0},
- {"GRP6" , 48, 4, 1062, "R/W", 0, 1, 0ull, 0},
- {"QOS6" , 52, 3, 1062, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_55_55" , 55, 1, 1062, "RAZ", 1, 1, 0, 0},
- {"GRP7" , 56, 4, 1062, "R/W", 0, 1, 0ull, 0},
- {"QOS7" , 60, 3, 1062, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_63_63" , 63, 1, 1062, "RAZ", 1, 1, 0, 0},
- {"SID0" , 0, 16, 1063, "RO", 0, 1, 0ull, 0},
- {"LTTR0" , 16, 2, 1063, "RO", 0, 1, 0ull, 0},
- {"MBOX0" , 18, 2, 1063, "RO", 0, 1, 0ull, 0},
- {"SEG0" , 20, 4, 1063, "RO", 0, 1, 0ull, 0},
- {"DIS0" , 24, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"TT0" , 25, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_26" , 26, 1, 1063, "RAZ", 1, 1, 0, 0},
- {"PRT0" , 27, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"TOC0" , 28, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"TOE0" , 29, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"ERR0" , 30, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"VAL0" , 31, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"SID1" , 32, 16, 1063, "RO", 0, 1, 0ull, 0},
- {"LTTR1" , 48, 2, 1063, "RO", 0, 1, 0ull, 0},
- {"MBOX1" , 50, 2, 1063, "RO", 0, 1, 0ull, 0},
- {"SEG1" , 52, 4, 1063, "RO", 0, 1, 0ull, 0},
- {"DIS1" , 56, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"TT1" , 57, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_58" , 58, 1, 1063, "RAZ", 1, 1, 0, 0},
- {"PRT1" , 59, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"TOC1" , 60, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"TOE1" , 61, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"ERR1" , 62, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"VAL1" , 63, 1, 1063, "RO", 0, 1, 0ull, 0},
- {"MAX_P0" , 0, 6, 1064, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_6_7" , 6, 2, 1064, "RAZ", 1, 1, 0, 0},
- {"MAX_P1" , 8, 6, 1064, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_14_15" , 14, 2, 1064, "RAZ", 1, 1, 0, 0},
- {"BUF_THR" , 16, 4, 1064, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_30" , 20, 11, 1064, "RAZ", 1, 1, 0, 0},
- {"SP_VPORT" , 31, 1, 1064, "R/W", 0, 0, 1ull, 1ull},
- {"MAX_S0" , 32, 6, 1064, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_38_39" , 38, 2, 1064, "RAZ", 1, 1, 0, 0},
- {"MAX_S1" , 40, 6, 1064, "R/W", 0, 0, 48ull, 48ull},
- {"RESERVED_46_47" , 46, 2, 1064, "RAZ", 1, 1, 0, 0},
- {"MAX_TOT" , 48, 6, 1064, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_54_63" , 54, 10, 1064, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 1065, "RAZ", 1, 1, 0, 0},
- {"MAX_S2" , 32, 6, 1065, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_38_39" , 38, 2, 1065, "RAZ", 1, 1, 0, 0},
- {"MAX_S3" , 40, 6, 1065, "R/W", 0, 1, 48ull, 0},
- {"RESERVED_46_63" , 46, 18, 1065, "RAZ", 1, 1, 0, 0},
- {"PKO_RST" , 0, 1, 1066, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1066, "RAZ", 1, 1, 0, 0},
- {"PKO_RST" , 0, 1, 1067, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_30" , 1, 30, 1067, "RAZ", 1, 1, 0, 0},
- {"INT_SUM" , 31, 1, 1067, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1067, "RAZ", 1, 1, 0, 0},
- {"TXBELL" , 0, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"BELL_ERR" , 1, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"RXBELL" , 2, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"MAINT_OP" , 3, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"BAR_ERR" , 4, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"DENY_WR" , 5, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"SLI_ERR" , 6, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"WR_DONE" , 7, 1, 1068, "R/W", 0, 0, 0ull, 0ull},
- {"MCE_TX" , 8, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"MCE_RX" , 9, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"SOFT_TX" , 10, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"SOFT_RX" , 11, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"LOG_ERB" , 12, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"PHY_ERB" , 13, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"LINK_DWN" , 14, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"LINK_UP" , 15, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"OMSG0" , 16, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"OMSG1" , 17, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"OMSG_ERR" , 18, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"PKO_ERR" , 19, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"RTRY_ERR" , 20, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"F_ERROR" , 21, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"MAC_BUF" , 22, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"DEGRADE" , 23, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"FAIL" , 24, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"TTL_TOUT" , 25, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"ZERO_PKT" , 26, 1, 1068, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_63" , 27, 37, 1068, "RAZ", 1, 1, 0, 0},
- {"BE1" , 0, 8, 1069, "RO", 0, 1, 0ull, 0},
- {"BE0" , 8, 8, 1069, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_28" , 16, 13, 1069, "RO", 1, 1, 0, 0},
- {"STATUS" , 29, 3, 1069, "RO", 0, 1, 0ull, 0},
- {"LENGTH" , 32, 10, 1069, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 1069, "RO", 1, 1, 0, 0},
- {"TAG" , 48, 8, 1069, "RO", 0, 1, 0ull, 0},
- {"TYPE" , 56, 4, 1069, "RO", 0, 1, 0ull, 0},
- {"CMD" , 60, 4, 1069, "RO", 0, 1, 0ull, 0},
- {"INFO1" , 0, 64, 1070, "RO", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 1, 1071, "RO", 0, 1, 0ull, 0},
- {"LNS" , 1, 1, 1071, "RO", 0, 1, 0ull, 0},
- {"RSRVD" , 2, 30, 1071, "RO", 0, 1, 0ull, 0},
- {"LETTER" , 32, 2, 1071, "RO", 0, 1, 0ull, 0},
- {"MBOX" , 34, 2, 1071, "RO", 0, 1, 0ull, 0},
- {"XMBOX" , 36, 4, 1071, "RO", 0, 1, 0ull, 0},
- {"DID" , 40, 16, 1071, "RO", 0, 1, 0ull, 0},
- {"SSIZE" , 56, 4, 1071, "RO", 0, 1, 0ull, 0},
- {"SIS" , 60, 1, 1071, "RO", 0, 1, 0ull, 0},
- {"TT" , 61, 1, 1071, "RO", 0, 1, 0ull, 0},
- {"PRIO" , 62, 2, 1071, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_7" , 0, 8, 1072, "RAZ", 1, 1, 0, 0},
- {"OTHER" , 8, 48, 1072, "RO", 0, 1, 0ull, 0},
- {"TYPE" , 56, 4, 1072, "RO", 0, 1, 0ull, 0},
- {"TT" , 60, 2, 1072, "RO", 0, 1, 0ull, 0},
- {"PRIO" , 62, 2, 1072, "RO", 0, 1, 0ull, 0},
- {"TXBELL" , 0, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"BELL_ERR" , 1, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBELL" , 2, 1, 1073, "RO", 0, 0, 0ull, 0ull},
- {"MAINT_OP" , 3, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR_ERR" , 4, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"DENY_WR" , 5, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI_ERR" , 6, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"WR_DONE" , 7, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCE_TX" , 8, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCE_RX" , 9, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"SOFT_TX" , 10, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"SOFT_RX" , 11, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOG_ERB" , 12, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_ERB" , 13, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"LINK_DWN" , 14, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"LINK_UP" , 15, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"OMSG0" , 16, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"OMSG1" , 17, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"OMSG_ERR" , 18, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO_ERR" , 19, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTRY_ERR" , 20, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"F_ERROR" , 21, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAC_BUF" , 22, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEGRAD" , 23, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"FAIL" , 24, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"TTL_TOUT" , 25, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"ZERO_PKT" , 26, 1, 1073, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_30" , 27, 4, 1073, "RAZ", 1, 1, 0, 0},
- {"INT2_SUM" , 31, 1, 1073, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1073, "RAZ", 1, 1, 0, 0},
- {"RX_POL" , 0, 4, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"TX_POL" , 4, 4, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"PT_WIDTH" , 8, 2, 1074, "R/W", 0, 0, 3ull, 3ull},
- {"TX_FLOW" , 10, 1, 1074, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_11_11" , 11, 1, 1074, "RAZ", 1, 1, 0, 0},
- {"A50" , 12, 1, 1074, "R/W", 0, 0, 1ull, 1ull},
- {"A66" , 13, 1, 1074, "R/W", 0, 0, 1ull, 1ull},
- {"NO_VMIN" , 14, 1, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_31" , 15, 17, 1074, "RAZ", 1, 1, 0, 0},
- {"OPS" , 32, 32, 1074, "R/W", 0, 0, 64756ull, 64756ull},
- {"RX_STAT" , 0, 8, 1075, "RO", 0, 0, 0ull, 0ull},
- {"RX_INUSE" , 8, 4, 1075, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 1075, "RAZ", 1, 1, 0, 0},
- {"RX_ENB" , 16, 8, 1075, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_24_31" , 24, 8, 1075, "RAZ", 1, 1, 0, 0},
- {"TX_STAT" , 32, 8, 1075, "RO", 0, 0, 0ull, 0ull},
- {"TX_INUSE" , 40, 4, 1075, "RO", 0, 1, 0ull, 0},
- {"RESERVED_44_47" , 44, 4, 1075, "RAZ", 1, 1, 0, 0},
- {"TX_ENB" , 48, 8, 1075, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_56_63" , 56, 8, 1075, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 24, 1076, "R/W", 0, 1, 0ull, 0},
- {"OP" , 24, 1, 1076, "R/W", 0, 1, 0ull, 0},
- {"PENDING" , 25, 1, 1076, "RO", 0, 1, 0ull, 0},
- {"FAIL" , 26, 1, 1076, "RO", 0, 1, 0ull, 0},
- {"RESERVED_27_31" , 27, 5, 1076, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 32, 32, 1076, "R/W", 0, 1, 0ull, 0},
- {"RD_DATA" , 0, 32, 1077, "RO", 0, 1, 0ull, 0},
- {"VALID" , 32, 1, 1077, "RO", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 1077, "RAZ", 1, 1, 0, 0},
- {"MCE" , 0, 1, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1078, "RAZ", 1, 1, 0, 0},
- {"RP0_PID" , 0, 2, 1079, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_PID" , 2, 1, 1079, "R/W", 0, 0, 0ull, 0ull},
- {"RP0_SID" , 3, 2, 1079, "R/W", 0, 0, 0ull, 0ull},
- {"RP1_SID" , 5, 1, 1079, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 1079, "RAZ", 1, 1, 0, 0},
- {"W_RO" , 8, 1, 1079, "R/W", 0, 0, 0ull, 0ull},
- {"RR_RO" , 9, 1, 1079, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1079, "RAZ", 1, 1, 0, 0},
- {"LTTR_MP" , 0, 4, 1080, "R/W", 0, 1, 15ull, 0},
- {"LTTR_SP" , 4, 4, 1080, "R/W", 0, 1, 15ull, 0},
- {"IDM_DID" , 8, 1, 1080, "R/W", 0, 1, 1ull, 0},
- {"IDM_SIS" , 9, 1, 1080, "R/W", 0, 1, 1ull, 0},
- {"IDM_TT" , 10, 1, 1080, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_11_14" , 11, 4, 1080, "RAZ", 1, 1, 0, 0},
- {"RTRY_EN" , 15, 1, 1080, "R/W", 0, 1, 0ull, 0},
- {"RTRY_THR" , 16, 16, 1080, "R/W", 0, 1, 0ull, 0},
- {"SILO_MAX" , 32, 5, 1080, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_37_62" , 37, 26, 1080, "RAZ", 1, 1, 0, 0},
- {"TESTMODE" , 63, 1, 1080, "R/W", 0, 0, 0ull, 0ull},
- {"GOOD" , 0, 16, 1081, "R/W", 0, 1, 0ull, 0},
- {"BAD" , 16, 16, 1081, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1081, "RAZ", 1, 1, 0, 0},
- {"ALL_PSD" , 0, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"ALL_NMP" , 1, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"ALL_FMP" , 2, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"ALL_SP" , 3, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"MBOX_PSD" , 4, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"MBOX_NMP" , 5, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"MBOX_FMP" , 6, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"MBOX_SP" , 7, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"ID_PSD" , 8, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"ID_NMP" , 9, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"ID_FMP" , 10, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"ID_SP" , 11, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"CTLR_NMP" , 12, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"CTLR_FMP" , 13, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"CTLR_SP" , 14, 1, 1082, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 1082, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 1083, "R/W", 0, 0, 0ull, 0ull},
- {"ALL_NMP" , 1, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"ALL_FMP" , 2, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"ALL_SP" , 3, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_4" , 4, 1, 1083, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX_NMP" , 5, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"MBOX_FMP" , 6, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"MBOX_SP" , 7, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_8" , 8, 1, 1083, "R/W", 0, 0, 0ull, 0ull},
- {"ID_NMP" , 9, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"ID_FMP" , 10, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"ID_SP" , 11, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"CTLR_NMP" , 12, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"CTLR_FMP" , 13, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"CTLR_SP" , 14, 1, 1083, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 1083, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 3, 1084, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_30" , 3, 28, 1084, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 31, 1, 1084, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1084, "RAZ", 1, 1, 0, 0},
- {"TOT_SILO" , 0, 5, 1085, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_5_63" , 5, 59, 1085, "RAZ", 1, 1, 0, 0},
- {"ALL_PSD" , 0, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"ALL_NMP" , 1, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"ALL_FMP" , 2, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"ALL_SP" , 3, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"MBOX_PSD" , 4, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"MBOX_NMP" , 5, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"MBOX_FMP" , 6, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"MBOX_SP" , 7, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"ID_PSD" , 8, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"ID_NMP" , 9, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"ID_FMP" , 10, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"ID_SP" , 11, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"CTLR_NMP" , 12, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"CTLR_FMP" , 13, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"CTLR_SP" , 14, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"XMBOX_SP" , 15, 1, 1086, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1086, "RAZ", 1, 1, 0, 0},
- {"START_CNT" , 0, 16, 1087, "RO", 0, 1, 0ull, 0},
- {"END_CNT" , 16, 16, 1087, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1087, "RAZ", 1, 1, 0, 0},
- {"PRIORITY" , 0, 2, 1088, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1088, "RAZ", 1, 1, 0, 0},
- {"ID16" , 3, 1, 1088, "RO", 0, 0, 0ull, 0ull},
- {"DEST_ID" , 4, 1, 1088, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 1088, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 8, 8, 1088, "RO", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 16, 16, 1088, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 32, 16, 1088, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1088, "RAZ", 1, 1, 0, 0},
- {"SEQ" , 0, 32, 1089, "RO", 0, 1, 0ull, 0},
- {"COUNT" , 32, 8, 1089, "RO", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 1089, "RAZ", 1, 1, 0, 0},
- {"POST" , 0, 8, 1090, "RO", 0, 1, 128ull, 0},
- {"N_POST" , 8, 5, 1090, "RO", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 1090, "RAZ", 1, 1, 0, 0},
- {"COMP" , 16, 8, 1090, "RO", 0, 1, 128ull, 0},
- {"MBOX" , 24, 4, 1090, "RO", 0, 1, 8ull, 0},
- {"RESERVED_28_39" , 28, 12, 1090, "RAZ", 1, 1, 0, 0},
- {"RTN_PR1" , 40, 8, 1090, "RO", 0, 1, 0ull, 0},
- {"RTN_PR2" , 48, 8, 1090, "RO", 0, 1, 0ull, 0},
- {"RTN_PR3" , 56, 8, 1090, "RO", 0, 1, 0ull, 0},
- {"IAOW_SEL" , 0, 2, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 1091, "RAZ", 1, 1, 0, 0},
- {"ID16" , 4, 1, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 5, 1, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 1091, "RAZ", 1, 1, 0, 0},
- {"RD_PRIOR" , 8, 2, 1091, "R/W", 0, 0, 1ull, 1ull},
- {"WR_PRIOR" , 10, 2, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RD_OP" , 12, 3, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 1091, "RAZ", 1, 1, 0, 0},
- {"WR_OP" , 16, 3, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1091, "RAZ", 1, 1, 0, 0},
- {"SEQ" , 0, 32, 1092, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1092, "RAZ", 1, 1, 0, 0},
- {"SRIO" , 0, 1, 1093, "RO", 1, 1, 0, 0},
- {"ACCESS" , 1, 1, 1093, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 1093, "RAZ", 1, 1, 0, 0},
- {"ITAG" , 0, 5, 1094, "RO", 0, 1, 16ull, 0},
- {"RESERVED_5_7" , 5, 3, 1094, "RAZ", 1, 1, 0, 0},
- {"OTAG" , 8, 5, 1094, "RO", 0, 1, 16ull, 0},
- {"RESERVED_13_15" , 13, 3, 1094, "RAZ", 1, 1, 0, 0},
- {"O_CLR" , 16, 1, 1094, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1094, "RAZ", 1, 1, 0, 0},
- {"POST" , 0, 8, 1095, "R/W", 1, 1, 0, 0},
- {"N_POST" , 8, 5, 1095, "R/W", 1, 1, 0, 0},
- {"RESERVED_13_15" , 13, 3, 1095, "RAZ", 1, 1, 0, 0},
- {"COMP" , 16, 8, 1095, "R/W", 1, 1, 0, 0},
- {"MBOX" , 24, 4, 1095, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_28_63" , 28, 36, 1095, "RAZ", 1, 1, 0, 0},
- {"PRIORITY" , 0, 2, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1096, "RAZ", 1, 1, 0, 0},
- {"ID16" , 3, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 4, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 1096, "RAZ", 1, 1, 0, 0},
- {"PENDING" , 8, 1, 1096, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 1096, "RAZ", 1, 1, 0, 0},
- {"DEST_ID" , 16, 16, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"DATA" , 32, 16, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1096, "RAZ", 1, 1, 0, 0},
- {"PRIORITY" , 0, 2, 1097, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1097, "RAZ", 1, 1, 0, 0},
- {"ID16" , 3, 1, 1097, "RO", 0, 0, 0ull, 0ull},
- {"SRC_ID" , 4, 1, 1097, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 5, 1, 1097, "RO", 0, 0, 0ull, 0ull},
- {"ERROR" , 6, 1, 1097, "RO", 0, 0, 0ull, 0ull},
- {"TIMEOUT" , 7, 1, 1097, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1097, "RAZ", 1, 1, 0, 0},
- {"DEST_ID" , 16, 16, 1097, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 32, 16, 1097, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1097, "RAZ", 1, 1, 0, 0},
- {"TX_TH0" , 0, 4, 1098, "R/W", 0, 0, 6ull, 3ull},
- {"RESERVED_4_7" , 4, 4, 1098, "RAZ", 1, 1, 0, 0},
- {"TX_TH1" , 8, 4, 1098, "R/W", 0, 0, 4ull, 2ull},
- {"RESERVED_12_15" , 12, 4, 1098, "RAZ", 1, 1, 0, 0},
- {"TX_TH2" , 16, 4, 1098, "R/W", 0, 0, 2ull, 1ull},
- {"RESERVED_20_31" , 20, 12, 1098, "RAZ", 1, 1, 0, 0},
- {"TAG_TH0" , 32, 5, 1098, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_37_39" , 37, 3, 1098, "RAZ", 1, 1, 0, 0},
- {"TAG_TH1" , 40, 5, 1098, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_45_47" , 45, 3, 1098, "RAZ", 1, 1, 0, 0},
- {"TAG_TH2" , 48, 5, 1098, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_53_63" , 53, 11, 1098, "RAZ", 1, 1, 0, 0},
- {"EMPH" , 0, 4, 1099, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 1099, "RAZ", 1, 1, 0, 0},
- {"S2M_PR0" , 0, 8, 1100, "RO", 0, 1, 0ull, 0},
- {"S2M_PR1" , 8, 8, 1100, "RO", 0, 1, 0ull, 0},
- {"S2M_PR2" , 16, 8, 1100, "RO", 0, 1, 0ull, 0},
- {"S2M_PR3" , 24, 8, 1100, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1100, "RAZ", 1, 1, 0, 0},
- {"GOOD" , 0, 16, 1101, "R/W", 0, 1, 0ull, 0},
- {"BAD" , 16, 16, 1101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1101, "RAZ", 1, 1, 0, 0},
- {"ASSY_VEN" , 0, 16, 1102, "RO", 0, 0, 140ull, 0ull},
- {"ASSY_ID" , 16, 16, 1102, "RO", 0, 0, 0ull, 0ull},
- {"EXT_FPTR" , 0, 16, 1103, "RO", 0, 0, 256ull, 256ull},
- {"ASSY_REV" , 16, 16, 1103, "RO", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_2" , 1, 2, 1104, "RAZ", 1, 1, 0, 0},
- {"NCA" , 3, 1, 1104, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 4, 2, 1104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 1104, "RAZ", 1, 1, 0, 0},
- {"LA" , 8, 22, 1104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 1104, "RAZ", 1, 1, 0, 0},
- {"FULL" , 0, 1, 1105, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 1105, "RAZ", 1, 1, 0, 0},
- {"COMP_TAG" , 0, 32, 1106, "R/W", 0, 0, 0ull, 0ull},
- {"MEMORY" , 0, 1, 1107, "R/W", 0, 0, 0ull, 1ull},
- {"DOORBELL" , 1, 1, 1107, "R/W", 0, 0, 0ull, 1ull},
- {"IMSG0" , 2, 1, 1107, "R/W", 0, 0, 0ull, 1ull},
- {"IMSG1" , 3, 1, 1107, "R/W", 0, 0, 0ull, 1ull},
- {"HALT" , 4, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_31" , 5, 27, 1107, "RAZ", 1, 1, 0, 0},
- {"VENDOR" , 0, 16, 1108, "RO", 0, 0, 140ull, 140ull},
- {"DEVICE" , 16, 16, 1108, "RO", 0, 1, 146ull, 0},
- {"REVISION" , 0, 8, 1109, "RO", 1, 1, 0, 0},
- {"RESERVED_8_31" , 8, 24, 1109, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 1110, "RAZ", 1, 1, 0, 0},
- {"PORT_WR" , 2, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SWP" , 3, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_CLR" , 4, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SET" , 5, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_DEC" , 6, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_INC" , 7, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"TESTSWAP" , 8, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"COMPSWAP" , 9, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 10, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"MSG" , 11, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"WRITE_R" , 12, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"SWRITE" , 13, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"WRITE" , 14, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"READ" , 15, 1, 1110, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_21" , 16, 6, 1110, "RAZ", 1, 1, 0, 0},
- {"TLB_INVS" , 22, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"TLB_INV" , 23, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"I_INVALD" , 24, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"IO_READ" , 25, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"D_FLUSH" , 26, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"CASTOUT" , 27, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"D_INVALD" , 28, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"RD_OWN" , 29, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"I_READ" , 30, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"GSM_READ" , 31, 1, 1110, "RO", 0, 0, 0ull, 0ull},
- {"VALID" , 0, 1, 1111, "R/W0C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 1111, "RAZ", 1, 1, 0, 0},
- {"ERR_INFO" , 4, 20, 1111, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_TYPE" , 24, 5, 1111, "R/W", 0, 0, 0ull, 0ull},
- {"INF_TYPE" , 29, 3, 1111, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_TOUT" , 0, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ACK" , 1, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"DEL_ERR" , 2, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"F_TOGGLE" , 3, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"PROTERR" , 4, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_ACK" , 5, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_14" , 6, 9, 1112, "RAZ", 1, 1, 0, 0},
- {"INV_DATA" , 15, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"INV_CHAR" , 16, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 17, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CRC" , 18, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"OUT_ACK" , 19, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"NACK" , 20, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ID" , 21, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"CTL_CRC" , 22, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_30" , 23, 8, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"IMP_ERR" , 31, 1, 1112, "R/W", 0, 0, 0ull, 0ull},
- {"RATE_CNT" , 0, 8, 1113, "R/W", 0, 1, 0ull, 0},
- {"PK_RATE" , 8, 8, 1113, "R/W", 0, 1, 0ull, 0},
- {"RATE_LIM" , 16, 2, 1113, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_23" , 18, 6, 1113, "RAZ", 1, 1, 0, 0},
- {"ERR_BIAS" , 24, 8, 1113, "R/W", 0, 0, 128ull, 128ull},
- {"LNK_TOUT" , 0, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ACK" , 1, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"DEL_ERR" , 2, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"F_TOGGLE" , 3, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"PROTERR" , 4, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_ACK" , 5, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_14" , 6, 9, 1114, "RAZ", 1, 1, 0, 0},
- {"INV_DATA" , 15, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"INV_CHAR" , 16, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 17, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_CRC" , 18, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"OUT_ACK" , 19, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"NACK" , 20, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_ID" , 21, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"CTL_CRC" , 22, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_30" , 23, 8, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"IMP_ERR" , 31, 1, 1114, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_15" , 0, 16, 1115, "RAZ", 1, 1, 0, 0},
- {"DGRAD_TH" , 16, 8, 1115, "R/W", 0, 0, 255ull, 128ull},
- {"FAIL_TH" , 24, 8, 1115, "R/W", 0, 0, 255ull, 255ull},
- {"EF_ID" , 0, 16, 1116, "RO", 0, 0, 7ull, 7ull},
- {"EF_PTR" , 16, 16, 1116, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 32, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"XADDR" , 0, 2, 1118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1118, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 29, 1118, "R/W", 0, 0, 0ull, 0ull},
- {"CAPT_IDX" , 0, 5, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_5" , 5, 1, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"WDPTR" , 6, 1, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"TT" , 7, 1, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 8, 4, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"STATUS" , 12, 4, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"EXTRA" , 16, 8, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"TTYPE" , 24, 4, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"FTYPE" , 28, 4, 1119, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_14" , 0, 15, 1120, "RAZ", 1, 1, 0, 0},
- {"TT" , 15, 1, 1120, "R/W", 0, 0, 0ull, 0ull},
- {"ID8" , 16, 8, 1120, "R/W", 0, 0, 0ull, 0ull},
- {"ID16" , 24, 8, 1120, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID8" , 0, 8, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"SRC_ID16" , 8, 8, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"DST_ID8" , 16, 8, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"DST_ID16" , 24, 8, 1121, "R/W", 0, 0, 0ull, 0ull},
- {"RESP_SZ" , 0, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_21" , 1, 21, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_TRAN" , 22, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_RESP" , 23, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_TOUT" , 24, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_TOUT" , 25, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TGT" , 26, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TRAN" , 27, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_FMT" , 28, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"GSM_ERR" , 29, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_ERR" , 30, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"IO_ERR" , 31, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"RESP_SZ" , 0, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_21" , 1, 21, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_TRAN" , 22, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"UNS_RESP" , 23, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_TOUT" , 24, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_TOUT" , 25, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TGT" , 26, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_TRAN" , 27, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_FMT" , 28, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"GSM_ERR" , 29, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_ERR" , 30, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"IO_ERR" , 31, 1, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1125, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1126, "R/W", 0, 0, 0ull, 0ull},
- {"CAPTURE" , 0, 32, 1127, "R/W", 0, 0, 0ull, 0ull},
- {"HOSTID" , 0, 16, 1128, "R/W", 0, 0, 65535ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1128, "RAZ", 1, 1, 0, 0},
- {"RX_SYNC" , 0, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"TX_SYNC" , 1, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"TX_FLOW" , 2, 1, 1129, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_19" , 3, 17, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"TX_WM2" , 20, 4, 1129, "R/W", 0, 1, 2ull, 0},
- {"TX_WM1" , 24, 4, 1129, "R/W", 0, 1, 3ull, 0},
- {"TX_WM0" , 28, 4, 1129, "R/W", 0, 1, 4ull, 0},
- {"RX_WM0" , 0, 4, 1130, "R/W", 0, 0, 4ull, 4ull},
- {"RX_WM1" , 4, 4, 1130, "R/W", 0, 0, 3ull, 3ull},
- {"RX_WM2" , 8, 4, 1130, "R/W", 0, 0, 2ull, 2ull},
- {"RX_WM3" , 12, 4, 1130, "R/W", 0, 0, 1ull, 1ull},
- {"TX_WM0" , 16, 4, 1130, "R/W", 0, 0, 4ull, 4ull},
- {"TX_WM1" , 20, 4, 1130, "R/W", 0, 0, 3ull, 3ull},
- {"TX_WM2" , 24, 4, 1130, "R/W", 0, 0, 2ull, 2ull},
- {"TX_WM3" , 28, 4, 1130, "R/W", 0, 0, 1ull, 1ull},
- {"PD_CTRL" , 0, 32, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"LN0_DIS" , 0, 1, 1132, "RO", 0, 0, 0ull, 0ull},
- {"LN0_RX" , 1, 3, 1132, "RO", 0, 0, 0ull, 0ull},
- {"LN1_DIS" , 4, 1, 1132, "RO", 0, 0, 0ull, 0ull},
- {"LN1_RX" , 5, 3, 1132, "RO", 0, 0, 0ull, 0ull},
- {"LN2_DIS" , 8, 1, 1132, "RO", 0, 0, 0ull, 0ull},
- {"LN2_RX" , 9, 3, 1132, "RO", 0, 0, 0ull, 0ull},
- {"LN3_DIS" , 12, 1, 1132, "RO", 0, 0, 0ull, 0ull},
- {"LN3_RX" , 13, 3, 1132, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1132, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_26" , 0, 27, 1133, "RAZ", 1, 1, 0, 0},
- {"LOOPBACK" , 27, 2, 1133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_29" , 29, 1, 1133, "R/W", 0, 0, 0ull, 0ull},
- {"RX_RESET" , 30, 1, 1133, "R/W", 0, 0, 1ull, 1ull},
- {"TX_RESET" , 31, 1, 1133, "R/W", 0, 0, 1ull, 1ull},
- {"INIT_SM" , 0, 10, 1134, "RO", 0, 0, 0ull, 0ull},
- {"RX_RDY" , 10, 1, 1134, "RO", 0, 0, 0ull, 0ull},
- {"TX_RDY" , 11, 1, 1134, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 1134, "RAZ", 1, 1, 0, 0},
- {"OVERWRT" , 0, 1, 1135, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 1135, "RAZ", 1, 1, 0, 0},
- {"PKT_DATA" , 0, 32, 1136, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_ST" , 0, 4, 1137, "RO", 0, 0, 0ull, 0ull},
- {"FULL" , 4, 1, 1137, "RO", 0, 0, 0ull, 0ull},
- {"DROP_CNT" , 5, 7, 1137, "RO", 0, 1, 0ull, 0},
- {"BUFFERS" , 12, 4, 1137, "RO", 0, 0, 0ull, 0ull},
- {"OCTETS" , 16, 16, 1137, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_15" , 0, 16, 1138, "RAZ", 1, 1, 0, 0},
- {"OCTETS" , 16, 16, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_DATA" , 0, 32, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"FIFO_ST" , 0, 4, 1140, "RO", 0, 0, 0ull, 0ull},
- {"FULL" , 4, 1, 1140, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_11" , 5, 7, 1140, "RAZ", 1, 1, 0, 0},
- {"BUFFERS" , 12, 4, 1140, "RO", 0, 0, 0ull, 0ull},
- {"OCTETS" , 16, 16, 1140, "RO", 0, 0, 0ull, 0ull},
- {"STATUSN" , 0, 3, 1141, "RO", 0, 0, 0ull, 0ull},
- {"STATUS1" , 3, 1, 1141, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_5" , 4, 2, 1141, "RAZ", 1, 1, 0, 0},
- {"XTRAIN" , 6, 1, 1141, "RO", 0, 0, 0ull, 0ull},
- {"XSYNC" , 7, 1, 1141, "RO", 0, 0, 0ull, 0ull},
- {"DEC_ERR" , 8, 4, 1141, "RO", 0, 0, 0ull, 0ull},
- {"RX_TRAIN" , 12, 1, 1141, "RO", 0, 0, 0ull, 0ull},
- {"RX_SYNC" , 13, 1, 1141, "RO", 0, 0, 0ull, 0ull},
- {"RX_ADAPT" , 14, 1, 1141, "RO", 0, 0, 1ull, 1ull},
- {"RX_INV" , 15, 1, 1141, "RO", 0, 0, 0ull, 0ull},
- {"RX_TYPE" , 16, 2, 1141, "RO", 0, 0, 0ull, 0ull},
- {"TX_MODE" , 18, 1, 1141, "RO", 0, 0, 0ull, 0ull},
- {"TX_TYPE" , 19, 1, 1141, "RO", 0, 0, 0ull, 0ull},
- {"LANE" , 20, 4, 1141, "RO", 0, 0, 0ull, 0ull},
- {"PORT" , 24, 8, 1141, "RO", 0, 0, 0ull, 0ull},
- {"LCSBA" , 0, 31, 1142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1142, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_20" , 0, 21, 1143, "R/W", 0, 0, 0ull, 0ull},
- {"LCSBA" , 21, 11, 1143, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR48" , 0, 16, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR64" , 16, 16, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR66" , 1, 2, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_13" , 3, 11, 1145, "RAZ", 1, 1, 0, 0},
- {"ADDR32" , 14, 18, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR48" , 0, 16, 1146, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR64" , 16, 16, 1146, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1147, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR66" , 1, 2, 1147, "R/W", 0, 0, 0ull, 0ull},
- {"BARSIZE" , 3, 4, 1147, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_19" , 7, 13, 1147, "RAZ", 1, 1, 0, 0},
- {"ADDR32" , 20, 12, 1147, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 1148, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR66" , 1, 2, 1148, "R/W", 0, 0, 0ull, 0ull},
- {"CAX" , 3, 1, 1148, "R/W", 0, 0, 0ull, 0ull},
- {"ESX" , 4, 2, 1148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 1148, "RAZ", 1, 1, 0, 0},
- {"ADDR48" , 9, 7, 1148, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR64" , 16, 16, 1148, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_RTRY" , 0, 16, 1149, "R/W", 0, 1, 0ull, 0},
- {"TYPE_MRG" , 16, 1, 1149, "R/W", 0, 0, 1ull, 1ull},
- {"EOP_MRG" , 17, 1, 1149, "R/W", 0, 0, 1ull, 1ull},
- {"RX_SPF" , 18, 1, 1149, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_ZERO" , 19, 1, 1149, "R/W", 0, 0, 0ull, 0ull},
- {"SEC_SPF" , 20, 1, 1149, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 1149, "RAZ", 1, 1, 0, 0},
- {"EX_ADDR" , 0, 3, 1150, "RO", 0, 0, 7ull, 7ull},
- {"EX_FEAT" , 3, 1, 1150, "RO", 0, 0, 1ull, 1ull},
- {"LG_TRAN" , 4, 1, 1150, "RO", 0, 0, 1ull, 1ull},
- {"CRF" , 5, 1, 1150, "RO", 0, 0, 0ull, 0ull},
- {"SUPPRESS" , 6, 1, 1150, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 1150, "RAZ", 1, 1, 0, 0},
- {"MULT_PRT" , 27, 1, 1150, "RO", 0, 0, 0ull, 0ull},
- {"SWITCHF" , 28, 1, 1150, "RO", 0, 0, 0ull, 0ull},
- {"PROC" , 29, 1, 1150, "RO", 0, 0, 1ull, 1ull},
- {"MEMORY" , 30, 1, 1150, "RO", 0, 0, 1ull, 1ull},
- {"BRIDGE" , 31, 1, 1150, "RO", 0, 0, 0ull, 0ull},
- {"EX_ADDR" , 0, 3, 1151, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_31" , 3, 29, 1151, "RAZ", 1, 1, 0, 0},
- {"PT_TYPE" , 0, 1, 1152, "RO", 0, 0, 1ull, 1ull},
- {"PRT_LOCK" , 1, 1, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"DROP_PKT" , 2, 1, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"STP_PORT" , 3, 1, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"SUPPRESS" , 4, 8, 1152, "RO", 0, 0, 0ull, 0ull},
- {"EX_STAT" , 12, 2, 1152, "RO", 0, 0, 0ull, 0ull},
- {"EX_WIDTH" , 14, 2, 1152, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_16" , 16, 1, 1152, "RAZ", 1, 1, 0, 0},
- {"ENUMB" , 17, 1, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_18" , 18, 1, 1152, "RAZ", 1, 1, 0, 0},
- {"MCAST" , 19, 1, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_ERR" , 20, 1, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"I_ENABLE" , 21, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"O_ENABLE" , 22, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"DISABLE" , 23, 1, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"OV_WIDTH" , 24, 3, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"IT_WIDTH" , 27, 3, 1152, "RO", 0, 1, 0ull, 0},
- {"PT_WIDTH" , 30, 2, 1152, "RO", 0, 0, 3ull, 3ull},
- {"EMPH_EN" , 0, 1, 1153, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EMPH" , 1, 1, 1153, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 1153, "R/W", 0, 0, 0ull, 0ull},
- {"ENB_625G" , 16, 1, 1153, "R/W", 0, 0, 0ull, 0ull},
- {"SUP_625G" , 17, 1, 1153, "RO", 0, 0, 0ull, 0ull},
- {"ENB_500G" , 18, 1, 1153, "R/W", 1, 1, 0, 0},
- {"SUB_500G" , 19, 1, 1153, "RO", 1, 1, 0, 0},
- {"ENB_312G" , 20, 1, 1153, "R/W", 1, 1, 0, 0},
- {"SUP_312G" , 21, 1, 1153, "RO", 1, 1, 0, 0},
- {"ENB_250G" , 22, 1, 1153, "R/W", 1, 1, 0, 0},
- {"SUP_250G" , 23, 1, 1153, "RO", 1, 1, 0, 0},
- {"ENB_125G" , 24, 1, 1153, "R/W", 1, 1, 0, 0},
- {"SUP_125G" , 25, 1, 1153, "RO", 1, 1, 0, 0},
- {"BAUD_ENB" , 26, 1, 1153, "R/W", 0, 0, 0ull, 0ull},
- {"BAUD_SUP" , 27, 1, 1153, "RO", 0, 0, 0ull, 0ull},
- {"SEL_BAUD" , 28, 4, 1153, "RO", 0, 1, 0ull, 0},
- {"PT_UINIT" , 0, 1, 1154, "RO", 0, 0, 1ull, 0ull},
- {"PT_OK" , 1, 1, 1154, "RO", 0, 0, 0ull, 1ull},
- {"PT_ERROR" , 2, 1, 1154, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1154, "RAZ", 1, 1, 0, 0},
- {"PT_WRITE" , 4, 1, 1154, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 1154, "RAZ", 1, 1, 0, 0},
- {"I_SM_ERR" , 8, 1, 1154, "RO", 0, 0, 0ull, 0ull},
- {"I_ERROR" , 9, 1, 1154, "R/W1C", 0, 0, 0ull, 0ull},
- {"I_SM_RET" , 10, 1, 1154, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 1154, "RAZ", 1, 1, 0, 0},
- {"O_SM_ERR" , 16, 1, 1154, "RO", 0, 0, 0ull, 0ull},
- {"O_ERROR" , 17, 1, 1154, "R/W1C", 0, 0, 0ull, 0ull},
- {"O_SM_RET" , 18, 1, 1154, "RO", 0, 0, 0ull, 0ull},
- {"O_RTRIED" , 19, 1, 1154, "RO", 0, 0, 0ull, 0ull},
- {"O_RETRY" , 20, 1, 1154, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 1154, "RAZ", 1, 1, 0, 0},
- {"O_DGRAD" , 24, 1, 1154, "R/W1C", 0, 0, 0ull, 0ull},
- {"O_FAIL" , 25, 1, 1154, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKT_DROP" , 26, 1, 1154, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 1154, "RAZ", 1, 1, 0, 0},
- {"CMD" , 0, 3, 1155, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_31" , 3, 29, 1155, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 5, 1156, "RO", 0, 1, 0ull, 0},
- {"ACKID" , 5, 6, 1156, "RO", 0, 1, 0ull, 0},
- {"RESERVED_11_30" , 11, 20, 1156, "RAZ", 1, 1, 0, 0},
- {"VALID" , 31, 1, 1156, "RO", 0, 1, 0ull, 0},
- {"O_ACKID" , 0, 6, 1157, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 1157, "RAZ", 1, 1, 0, 0},
- {"E_ACKID" , 8, 6, 1157, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_23" , 14, 10, 1157, "RAZ", 1, 1, 0, 0},
- {"I_ACKID" , 24, 6, 1157, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_30_31" , 30, 2, 1157, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_28" , 0, 29, 1158, "RAZ", 1, 1, 0, 0},
- {"DISCOVER" , 29, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"MENABLE" , 30, 1, 1158, "R/W", 1, 0, 0, 1ull},
- {"HOST" , 31, 1, 1158, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1159, "RAZ", 1, 1, 0, 0},
- {"TIMEOUT" , 8, 24, 1159, "R/W", 0, 0, 16777215ull, 0ull},
- {"EF_ID" , 0, 16, 1160, "RO", 0, 0, 1ull, 0ull},
- {"EF_PTR" , 16, 16, 1160, "RO", 0, 0, 4096ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1161, "RAZ", 1, 1, 0, 0},
- {"TIMEOUT" , 8, 24, 1161, "R/W", 0, 0, 16777215ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1162, "RAZ", 1, 1, 0, 0},
- {"TIMEOUT" , 8, 24, 1162, "R/W", 0, 1, 0ull, 0},
- {"ID16" , 0, 16, 1163, "R/W", 0, 0, 65535ull, 0ull},
- {"ID8" , 16, 8, 1163, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1163, "RAZ", 1, 1, 0, 0},
- {"ENABLE16" , 0, 1, 1164, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE8" , 1, 1, 1164, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 1164, "RAZ", 1, 1, 0, 0},
- {"ID16" , 0, 16, 1165, "R/W", 0, 0, 65535ull, 0ull},
- {"ID8" , 16, 8, 1165, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1165, "RAZ", 1, 1, 0, 0},
- {"EF_ID" , 0, 16, 1166, "RO", 0, 0, 13ull, 13ull},
- {"EF_PTR" , 16, 16, 1166, "RO", 0, 0, 8192ull, 0ull},
- {"RESERVED_0_1" , 0, 2, 1167, "RAZ", 1, 1, 0, 0},
- {"PORT_WR" , 2, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SWP" , 3, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_CLR" , 4, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_SET" , 5, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_DEC" , 6, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"ATOM_INC" , 7, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"TESTSWAP" , 8, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"COMPSWAP" , 9, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 10, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"MSG" , 11, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"WRITE_R" , 12, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"SWRITE" , 13, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"WRITE" , 14, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"READ" , 15, 1, 1167, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_21" , 16, 6, 1167, "RAZ", 1, 1, 0, 0},
- {"TLB_INVS" , 22, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"TLB_INV" , 23, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"I_INVALD" , 24, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"IO_READ" , 25, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"D_FLUSH" , 26, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"CASTOUT" , 27, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"D_INVALD" , 28, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"RD_OWN" , 29, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"I_READ" , 30, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"GSM_READ" , 31, 1, 1167, "RO", 0, 0, 0ull, 0ull},
- {"DROP_CNT" , 0, 16, 1168, "RO", 0, 1, 0ull, 0},
- {"DROP" , 16, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 1168, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 1169, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 1169, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 1169, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 1169, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 1169, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 1169, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 1170, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 1170, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 1170, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 1171, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1171, "RO", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 1171, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 1171, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 1171, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 1172, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 1172, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 1172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 1172, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 1173, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 1174, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 1174, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 1174, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 1174, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1175, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1175, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 1176, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 1176, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 1176, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1176, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1177, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1177, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1178, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 1178, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1178, "RAZ", 1, 1, 0, 0},
- {"TDF" , 0, 1, 1179, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1179, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"CLKALWAYS" , 15, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"RDAT_MD" , 16, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1180, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 1181, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 1181, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 1181, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 1182, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 1182, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 1182, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1182, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 1182, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1183, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1183, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1184, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1185, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1185, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1186, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1186, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1186, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1186, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1186, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 10, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 1188, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 1188, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 1188, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 1188, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1188, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 1189, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 5, 1190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1190, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1191, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1191, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1192, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1193, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1193, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1193, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1193, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1193, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1193, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1194, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1194, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1194, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1194, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1194, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 10, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1196, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1196, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1197, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1198, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1198, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1198, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1198, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1198, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1198, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1199, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1199, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1199, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1199, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 10, 1200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 1200, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1200, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1200, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1200, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 1201, "R/W", 0, 1, 0ull, 0},
- {"LPL" , 5, 27, 1201, "R/W", 0, 1, 0ull, 0},
- {"CF" , 0, 1, 1202, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_31" , 1, 31, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"CTRLDSSEG" , 0, 32, 1203, "R/W", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1204, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_31" , 14, 18, 1204, "RO", 0, 0, 0ull, 0ull},
- {"CAPLENGTH" , 0, 8, 1205, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_15" , 8, 8, 1205, "RO", 0, 0, 0ull, 0ull},
- {"HCIVERSION" , 16, 16, 1205, "RO", 0, 0, 256ull, 256ull},
- {"AC64" , 0, 1, 1206, "RO", 0, 0, 1ull, 1ull},
- {"PFLF" , 1, 1, 1206, "RO", 0, 0, 0ull, 0ull},
- {"ASPC" , 2, 1, 1206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1206, "RO", 0, 0, 0ull, 0ull},
- {"IST" , 4, 4, 1206, "RO", 0, 0, 2ull, 2ull},
- {"EECP" , 8, 8, 1206, "RO", 0, 0, 160ull, 160ull},
- {"RESERVED_16_31" , 16, 16, 1206, "RO", 0, 0, 0ull, 0ull},
- {"N_PORTS" , 0, 4, 1207, "RO", 0, 0, 2ull, 2ull},
- {"PPC" , 4, 1, 1207, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 1207, "RO", 0, 0, 0ull, 0ull},
- {"PRR" , 7, 1, 1207, "RO", 0, 0, 0ull, 0ull},
- {"N_PCC" , 8, 4, 1207, "RO", 0, 0, 2ull, 2ull},
- {"N_CC" , 12, 4, 1207, "RO", 0, 0, 1ull, 1ull},
- {"P_INDICATOR" , 16, 1, 1207, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 1207, "RO", 0, 0, 0ull, 0ull},
- {"DPN" , 20, 4, 1207, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1207, "RO", 0, 0, 0ull, 0ull},
- {"EN" , 0, 1, 1208, "R/W", 0, 0, 0ull, 0ull},
- {"MFMC" , 1, 13, 1208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 1208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_0" , 0, 1, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"TA_OFF" , 1, 8, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"TXTX_TADAO" , 10, 3, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_RW" , 0, 1, 1210, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_FW" , 1, 1, 1210, "R/W", 0, 0, 0ull, 0ull},
- {"PESD" , 2, 1, 1210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1210, "RAZ", 0, 0, 0ull, 0ull},
- {"NAKRF_DIS" , 4, 1, 1210, "R/W", 0, 0, 0ull, 0ull},
- {"AUTO_DIS" , 5, 1, 1210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 1210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_30" , 0, 31, 1211, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1211, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 1213, "R/W", 0, 1, 0ull, 0},
- {"BADDR" , 12, 20, 1213, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1214, "RO", 0, 0, 0ull, 0ull},
- {"CSC" , 1, 1, 1214, "R/W1C", 0, 0, 0ull, 0ull},
- {"PED" , 2, 1, 1214, "R/W", 0, 0, 0ull, 0ull},
- {"PEDC" , 3, 1, 1214, "R/W1C", 0, 0, 0ull, 0ull},
- {"OCA" , 4, 1, 1214, "RO", 0, 0, 0ull, 0ull},
- {"OCC" , 5, 1, 1214, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPR" , 6, 1, 1214, "R/W", 0, 0, 0ull, 0ull},
- {"SPD" , 7, 1, 1214, "R/W", 0, 0, 0ull, 0ull},
- {"PRST" , 8, 1, 1214, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1214, "RO", 0, 0, 0ull, 0ull},
- {"LSTS" , 10, 2, 1214, "RO", 0, 1, 0ull, 0},
- {"PP" , 12, 1, 1214, "RO", 0, 0, 1ull, 1ull},
- {"PO" , 13, 1, 1214, "R/W", 0, 0, 1ull, 0ull},
- {"PIC" , 14, 2, 1214, "R/W", 0, 0, 0ull, 0ull},
- {"PTC" , 16, 4, 1214, "R/W", 0, 0, 0ull, 0ull},
- {"WKCNNT_E" , 20, 1, 1214, "R/W", 0, 0, 0ull, 0ull},
- {"WKDSCNNT_E" , 21, 1, 1214, "R/W", 0, 0, 0ull, 0ull},
- {"WKOC_E" , 22, 1, 1214, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 1214, "RO", 0, 0, 0ull, 0ull},
- {"RS" , 0, 1, 1215, "R/W", 0, 0, 0ull, 1ull},
- {"HCRESET" , 1, 1, 1215, "R/W", 0, 0, 0ull, 0ull},
- {"FLS" , 2, 2, 1215, "RO", 0, 0, 0ull, 0ull},
- {"PS_EN" , 4, 1, 1215, "R/W", 0, 0, 0ull, 0ull},
- {"AS_EN" , 5, 1, 1215, "R/W", 0, 0, 0ull, 0ull},
- {"IAA_DB" , 6, 1, 1215, "R/W", 0, 0, 0ull, 0ull},
- {"LHCR" , 7, 1, 1215, "R/W", 0, 0, 0ull, 0ull},
- {"ASPMC" , 8, 2, 1215, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1215, "RO", 0, 0, 0ull, 0ull},
- {"ASPM_EN" , 11, 1, 1215, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 1215, "RO", 0, 0, 0ull, 0ull},
- {"ITC" , 16, 8, 1215, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_24_31" , 24, 8, 1215, "RO", 0, 0, 0ull, 0ull},
- {"USBINT_EN" , 0, 1, 1216, "R/W", 0, 1, 0ull, 0},
- {"USBERRINT_EN" , 1, 1, 1216, "R/W", 0, 1, 0ull, 0},
- {"PCI_EN" , 2, 1, 1216, "R/W", 0, 1, 0ull, 0},
- {"FLRO_EN" , 3, 1, 1216, "R/W", 0, 1, 0ull, 0},
- {"HSERR_EN" , 4, 1, 1216, "R/W", 0, 1, 0ull, 0},
- {"IOAA_EN" , 5, 1, 1216, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 1216, "RO", 0, 0, 0ull, 0ull},
- {"USBINT" , 0, 1, 1217, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBERRINT" , 1, 1, 1217, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCD" , 2, 1, 1217, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLRO" , 3, 1, 1217, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSYSERR" , 4, 1, 1217, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOAA" , 5, 1, 1217, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 1217, "RO", 0, 0, 0ull, 0ull},
- {"HCHTD" , 12, 1, 1217, "RO", 0, 0, 1ull, 0ull},
- {"RECLM" , 13, 1, 1217, "RO", 0, 0, 0ull, 0ull},
- {"PSS" , 14, 1, 1217, "RO", 0, 0, 0ull, 0ull},
- {"ASS" , 15, 1, 1217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1218, "R/W", 0, 0, 0ull, 0ull},
- {"BCED" , 4, 28, 1218, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1219, "R/W", 0, 0, 0ull, 0ull},
- {"BHED" , 4, 28, 1219, "R/W", 0, 1, 0ull, 0},
- {"HCR" , 0, 1, 1220, "R/W", 0, 0, 0ull, 0ull},
- {"CLF" , 1, 1, 1220, "R/W", 0, 0, 0ull, 0ull},
- {"BLF" , 2, 1, 1220, "R/W", 0, 0, 0ull, 0ull},
- {"OCR" , 3, 1, 1220, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1220, "RO", 0, 0, 0ull, 0ull},
- {"SOC" , 16, 2, 1220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 1220, "RO", 0, 0, 0ull, 0ull},
- {"CBSR" , 0, 2, 1221, "R/W", 0, 1, 0ull, 0},
- {"PLE" , 2, 1, 1221, "R/W", 0, 0, 0ull, 0ull},
- {"IE" , 3, 1, 1221, "R/W", 0, 0, 0ull, 0ull},
- {"CLE" , 4, 1, 1221, "R/W", 0, 0, 0ull, 0ull},
- {"BLE" , 5, 1, 1221, "R/W", 0, 0, 0ull, 0ull},
- {"HCFS" , 6, 2, 1221, "R/W", 0, 0, 0ull, 0ull},
- {"IR" , 8, 1, 1221, "R/W", 0, 0, 0ull, 0ull},
- {"RWC" , 9, 1, 1221, "R/W", 0, 0, 0ull, 0ull},
- {"RWE" , 10, 1, 1221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 1221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1222, "R/W", 0, 0, 0ull, 0ull},
- {"CCED" , 4, 28, 1222, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1223, "R/W", 0, 0, 0ull, 0ull},
- {"CHED" , 4, 28, 1223, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1224, "RO", 0, 0, 0ull, 0ull},
- {"DH" , 4, 28, 1224, "RO", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1225, "R/W", 0, 1, 11999ull, 0},
- {"RESERVED_14_15" , 14, 2, 1225, "R/W", 0, 0, 0ull, 0ull},
- {"FSMPS" , 16, 15, 1225, "R/W", 0, 1, 0ull, 0},
- {"FIT" , 31, 1, 1225, "R/W", 0, 0, 0ull, 0ull},
- {"FN" , 0, 16, 1226, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 1226, "RO", 0, 0, 0ull, 0ull},
- {"FR" , 0, 14, 1227, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_30" , 14, 17, 1227, "RO", 0, 0, 0ull, 0ull},
- {"FRT" , 31, 1, 1227, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1228, "R/W", 0, 0, 0ull, 0ull},
- {"HCCA" , 8, 24, 1228, "R/W", 0, 1, 0ull, 0},
- {"SO" , 0, 1, 1229, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1229, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1229, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1229, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1229, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1229, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1229, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1229, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1229, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1229, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1230, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1230, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1230, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1230, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1230, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1230, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1230, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1230, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1230, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1230, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1231, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1231, "R/W1C", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1231, "R/W1C", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1231, "R/W1C", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1231, "R/W1C", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1231, "R/W1C", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1231, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1231, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1231, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1231, "RO", 0, 0, 0ull, 0ull},
- {"LST" , 0, 12, 1232, "R/W", 0, 1, 1576ull, 0},
- {"RESERVED_12_31" , 12, 20, 1232, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1233, "RO", 0, 0, 0ull, 0ull},
- {"PCED" , 4, 28, 1233, "RO", 0, 1, 0ull, 0},
- {"PS" , 0, 14, 1234, "R/W", 0, 0, 0ull, 15975ull},
- {"RESERVED_14_31" , 14, 18, 1234, "R/W", 0, 0, 0ull, 0ull},
- {"REV" , 0, 8, 1235, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_31" , 8, 24, 1235, "RO", 0, 0, 0ull, 0ull},
- {"NDP" , 0, 8, 1236, "RO", 0, 0, 2ull, 2ull},
- {"NPS" , 8, 1, 1236, "R/W", 0, 0, 0ull, 0ull},
- {"PSM" , 9, 1, 1236, "R/W", 0, 0, 1ull, 1ull},
- {"DT" , 10, 1, 1236, "RO", 0, 0, 0ull, 0ull},
- {"OCPM" , 11, 1, 1236, "R/W", 1, 1, 0, 0},
- {"NOCP" , 12, 1, 1236, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_23" , 13, 11, 1236, "RO", 0, 0, 0ull, 0ull},
- {"POTPGT" , 24, 8, 1236, "R/W", 0, 0, 1ull, 1ull},
- {"DR" , 0, 16, 1237, "R/W", 0, 0, 0ull, 0ull},
- {"PPCM" , 16, 16, 1237, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"PES" , 1, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"PSS" , 2, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"POCI" , 3, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"PRS" , 4, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1238, "R/W", 0, 0, 0ull, 0ull},
- {"PPS" , 8, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"LSDA" , 9, 1, 1238, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_15" , 10, 6, 1238, "R/W", 0, 0, 0ull, 0ull},
- {"CSC" , 16, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"PESC" , 17, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"PSSC" , 18, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"OCIC" , 19, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"PRSC" , 20, 1, 1238, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_31" , 21, 11, 1238, "R/W", 0, 0, 0ull, 0ull},
- {"LPS" , 0, 1, 1239, "R/W", 0, 0, 0ull, 0ull},
- {"OCI" , 1, 1, 1239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_14" , 2, 13, 1239, "RO", 0, 0, 0ull, 0ull},
- {"DRWE" , 15, 1, 1239, "R/W", 0, 1, 0ull, 0},
- {"LPSC" , 16, 1, 1239, "R/W", 0, 1, 0ull, 0},
- {"CCIC" , 17, 1, 1239, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_18_30" , 18, 13, 1239, "RO", 0, 0, 0ull, 0ull},
- {"CRWE" , 31, 1, 1239, "WO", 1, 1, 0, 0},
- {"RESERVED_0_30" , 0, 31, 1240, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1240, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1241, "RO", 0, 0, 0ull, 0ull},
- {"PPAF_BIS" , 0, 1, 1242, "RO", 0, 0, 0ull, 0ull},
- {"WRBM_BIS" , 1, 1, 1242, "RO", 0, 0, 0ull, 0ull},
- {"ORBM_BIS" , 2, 1, 1242, "RO", 0, 0, 0ull, 0ull},
- {"ERBM_BIS" , 3, 1, 1242, "RO", 0, 0, 0ull, 0ull},
- {"DESC_BIS" , 4, 1, 1242, "RO", 0, 0, 0ull, 0ull},
- {"DATA_BIS" , 5, 1, 1242, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1242, "RO", 1, 1, 0, 0},
- {"HRST" , 0, 1, 1243, "R/W", 0, 0, 0ull, 1ull},
- {"P_PRST" , 1, 1, 1243, "R/W", 0, 0, 0ull, 1ull},
- {"P_POR" , 2, 1, 1243, "R/W", 0, 0, 1ull, 0ull},
- {"P_COM_ON" , 3, 1, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 1243, "R/W", 0, 1, 0ull, 0},
- {"P_REFCLK_DIV" , 5, 2, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"P_REFCLK_SEL" , 7, 2, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"H_DIV" , 9, 4, 1243, "R/W", 0, 0, 6ull, 6ull},
- {"O_CLKDIV_EN" , 13, 1, 1243, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_EN" , 14, 1, 1243, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_RST" , 15, 1, 1243, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_BYP" , 16, 1, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"O_CLKDIV_RST" , 17, 1, 1243, "R/W", 0, 0, 0ull, 1ull},
- {"APP_START_CLK" , 18, 1, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_SUSP_LGCY" , 19, 1, 1243, "R/W", 0, 0, 1ull, 1ull},
- {"OHCI_SM" , 20, 1, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_CLKCKTRST" , 21, 1, 1243, "R/W", 0, 0, 1ull, 1ull},
- {"EHCI_SM" , 22, 1, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 23, 1, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 24, 1, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1243, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1244, "R/W", 0, 1, 0ull, 0},
- {"EHCI_64B_ADDR_EN" , 8, 1, 1244, "R/W", 0, 0, 1ull, 1ull},
- {"INV_REG_A2" , 9, 1, 1244, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1244, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1244, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1244, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1244, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1244, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1244, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1244, "R/W", 0, 0, 0ull, 0ull},
- {"DESC_RBM" , 19, 1, 1244, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1244, "RAZ", 1, 1, 0, 0},
- {"FLA" , 0, 6, 1245, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 1245, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 1246, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 5, 27, 1246, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1246, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1247, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1247, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1248, "R/W", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1248, "R/W", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1248, "R/W", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1248, "R/W", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1248, "R/W", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1248, "R/W", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1248, "R/W", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1248, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1248, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1249, "R/W1C", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1249, "R/W1C", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1249, "R/W1C", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1249, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1249, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1249, "R/W1C", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1249, "R/W1C", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1249, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1249, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1250, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_8" , 8, 1, 1250, "RAZ", 1, 1, 0, 0},
- {"INV_REG_A2" , 9, 1, 1250, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1250, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1250, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1250, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1250, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1250, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1250, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1250, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1250, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1251, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 8, 24, 1251, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1251, "RAZ", 1, 1, 0, 0},
- {"WM" , 0, 5, 1252, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_5_63" , 5, 59, 1252, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 1253, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_EN" , 1, 1, 1253, "R/W", 0, 0, 0ull, 0ull},
- {"UPHY_BIST" , 2, 1, 1253, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_EN" , 3, 1, 1253, "R/W", 0, 0, 0ull, 0ull},
- {"SIDDQ" , 4, 1, 1253, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 5, 1, 1253, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 6, 1, 1253, "R/W", 0, 0, 0ull, 0ull},
- {"HSBIST" , 7, 1, 1253, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ERR" , 8, 1, 1253, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 9, 1, 1253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1253, "RAZ", 1, 1, 0, 0},
- {"TDATA_IN" , 0, 8, 1254, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 8, 4, 1254, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 12, 1, 1254, "R/W", 0, 0, 1ull, 0ull},
- {"TCLK" , 13, 1, 1254, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_EN" , 14, 1, 1254, "R/W", 0, 0, 0ull, 0ull},
- {"COMPDISTUNE" , 15, 3, 1254, "R/W", 0, 0, 4ull, 4ull},
- {"SQRXTUNE" , 18, 3, 1254, "R/W", 0, 0, 4ull, 4ull},
- {"TXFSLSTUNE" , 21, 4, 1254, "R/W", 0, 0, 3ull, 3ull},
- {"TXPREEMPHASISTUNE" , 25, 1, 1254, "R/W", 0, 0, 0ull, 1ull},
- {"TXRISETUNE" , 26, 1, 1254, "R/W", 0, 0, 0ull, 1ull},
- {"TXVREFTUNE" , 27, 4, 1254, "R/W", 0, 0, 5ull, 15ull},
- {"TXHSVXTUNE" , 31, 2, 1254, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 33, 1, 1254, "R/W", 0, 0, 0ull, 0ull},
- {"VBUSVLDEXT" , 34, 1, 1254, "R/W", 0, 0, 0ull, 0ull},
- {"DPPULLDOWN" , 35, 1, 1254, "R/W", 0, 0, 1ull, 1ull},
- {"DMPULLDOWN" , 36, 1, 1254, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFEN" , 37, 1, 1254, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFENH" , 38, 1, 1254, "R/W", 0, 0, 1ull, 1ull},
- {"TDATA_OUT" , 39, 4, 1254, "RO", 1, 1, 0, 0},
- {"RESERVED_43_63" , 43, 21, 1254, "RAZ", 1, 1, 0, 0},
- {"ZIP_CTL" , 0, 4, 1255, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 53, 1255, "RO", 1, 0, 0, 0ull},
- {"RESERVED_57_63" , 57, 7, 1255, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1256, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 1256, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 1256, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 1256, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 1256, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 1257, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 1257, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1257, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 1258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 1258, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 1258, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 1258, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 1258, "RO", 0, 0, 31744ull, 31744ull},
- {"SYNCFLUSH_CAPABLE" , 48, 1, 1258, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_49_55" , 49, 7, 1258, "RAZ", 1, 1, 0, 0},
- {"NEXEC" , 56, 8, 1258, "RO", 0, 0, 1ull, 1ull},
- {"ASSERTS" , 0, 17, 1259, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1259, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1260, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1260, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1261, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1261, "RAZ", 1, 1, 0, 0},
- {"MAX_INFL" , 0, 4, 1262, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 1262, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn68xxp1[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 14, 0},
- {"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 14},
- {"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 13, 16},
- {"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 1, 29},
- {"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 1, 30},
- {"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 1, 31},
- {"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 32},
- {"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 7, 1, 33},
- {"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 34},
- {"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 2, 35},
- {"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 4, 37},
- {"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 11, 2, 41},
- {"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 11, 43},
- {"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 14, 54},
- {"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 68},
- {"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 15, 2, 70},
- {"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 72},
- {"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 17, 21, 74},
- {"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 21, 95},
- {"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 19, 2, 116},
- {"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 118},
- {"cvmx_agl_gmx_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 21, 4, 120},
- {"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 124},
- {"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 23, 2, 126},
- {"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 128},
- {"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 25, 2, 130},
- {"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 132},
- {"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 27, 2, 134},
- {"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 136},
- {"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 29, 2, 138},
- {"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 140},
- {"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 31, 2, 142},
- {"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 4, 144},
- {"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 33, 2, 148},
- {"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 150},
- {"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 35, 2, 152},
- {"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 4, 154},
- {"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 37, 4, 158},
- {"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 2, 162},
- {"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 39, 3, 164},
- {"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 5, 167},
- {"cvmx_agl_gmx_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 41, 2, 172},
- {"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 3, 174},
- {"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 43, 2, 177},
- {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 179},
- {"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 45, 2, 181},
- {"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 183},
- {"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 47, 2, 185},
- {"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 187},
- {"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 49, 2, 189},
- {"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 191},
- {"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 51, 2, 193},
- {"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 195},
- {"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 53, 2, 197},
- {"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 199},
- {"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 55, 2, 201},
- {"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 203},
- {"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 57, 2, 205},
- {"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 207},
- {"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 59, 2, 209},
- {"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 211},
- {"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 61, 2, 213},
- {"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 215},
- {"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 63, 3, 217},
- {"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 12, 220},
- {"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 12, 232},
- {"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 244},
- {"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 2, 246},
- {"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 6, 248},
- {"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 69, 2, 254},
- {"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 70, 2, 256},
- {"cvmx_agl_prt#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 23, 258},
- {"cvmx_ciu2_ack_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 72, 2, 281},
- {"cvmx_ciu2_ack_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 74, 2, 283},
- {"cvmx_ciu2_ack_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 106, 2, 285},
- {"cvmx_ciu2_ack_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 138, 2, 287},
- {"cvmx_ciu2_en_io#_int_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 170, 2, 289},
- {"cvmx_ciu2_en_io#_int_gpio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 172, 2, 291},
- {"cvmx_ciu2_en_io#_int_gpio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 174, 2, 293},
- {"cvmx_ciu2_en_io#_int_io" , CVMX_CSR_DB_TYPE_NCB, 64, 176, 9, 295},
- {"cvmx_ciu2_en_io#_int_io_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 178, 9, 304},
- {"cvmx_ciu2_en_io#_int_io_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 180, 9, 313},
- {"cvmx_ciu2_en_io#_int_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 182, 2, 322},
- {"cvmx_ciu2_en_io#_int_mbox_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 184, 2, 324},
- {"cvmx_ciu2_en_io#_int_mbox_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 186, 2, 326},
- {"cvmx_ciu2_en_io#_int_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 188, 2, 328},
- {"cvmx_ciu2_en_io#_int_mem_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 190, 2, 330},
- {"cvmx_ciu2_en_io#_int_mem_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 192, 2, 332},
- {"cvmx_ciu2_en_io#_int_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 194, 21, 334},
- {"cvmx_ciu2_en_io#_int_mio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 196, 21, 355},
- {"cvmx_ciu2_en_io#_int_mio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 198, 21, 376},
- {"cvmx_ciu2_en_io#_int_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 200, 10, 397},
- {"cvmx_ciu2_en_io#_int_pkt_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 202, 10, 407},
- {"cvmx_ciu2_en_io#_int_pkt_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 204, 10, 417},
- {"cvmx_ciu2_en_io#_int_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 206, 24, 427},
- {"cvmx_ciu2_en_io#_int_rml_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 208, 24, 451},
- {"cvmx_ciu2_en_io#_int_rml_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 210, 24, 475},
- {"cvmx_ciu2_en_io#_int_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 212, 2, 499},
- {"cvmx_ciu2_en_io#_int_wdog_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 214, 2, 501},
- {"cvmx_ciu2_en_io#_int_wdog_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 216, 2, 503},
- {"cvmx_ciu2_en_io#_int_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 218, 1, 505},
- {"cvmx_ciu2_en_io#_int_wrkq_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 220, 1, 506},
- {"cvmx_ciu2_en_io#_int_wrkq_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 222, 1, 507},
- {"cvmx_ciu2_en_pp#_ip2_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 2, 508},
- {"cvmx_ciu2_en_pp#_ip2_gpio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 256, 2, 510},
- {"cvmx_ciu2_en_pp#_ip2_gpio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 288, 2, 512},
- {"cvmx_ciu2_en_pp#_ip2_io" , CVMX_CSR_DB_TYPE_NCB, 64, 320, 9, 514},
- {"cvmx_ciu2_en_pp#_ip2_io_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 352, 9, 523},
- {"cvmx_ciu2_en_pp#_ip2_io_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 384, 9, 532},
- {"cvmx_ciu2_en_pp#_ip2_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 416, 2, 541},
- {"cvmx_ciu2_en_pp#_ip2_mbox_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 448, 2, 543},
- {"cvmx_ciu2_en_pp#_ip2_mbox_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 480, 2, 545},
- {"cvmx_ciu2_en_pp#_ip2_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 512, 2, 547},
- {"cvmx_ciu2_en_pp#_ip2_mem_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 544, 2, 549},
- {"cvmx_ciu2_en_pp#_ip2_mem_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 576, 2, 551},
- {"cvmx_ciu2_en_pp#_ip2_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 608, 21, 553},
- {"cvmx_ciu2_en_pp#_ip2_mio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 640, 21, 574},
- {"cvmx_ciu2_en_pp#_ip2_mio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 672, 21, 595},
- {"cvmx_ciu2_en_pp#_ip2_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 704, 10, 616},
- {"cvmx_ciu2_en_pp#_ip2_pkt_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 736, 10, 626},
- {"cvmx_ciu2_en_pp#_ip2_pkt_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 768, 10, 636},
- {"cvmx_ciu2_en_pp#_ip2_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 800, 24, 646},
- {"cvmx_ciu2_en_pp#_ip2_rml_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 832, 24, 670},
- {"cvmx_ciu2_en_pp#_ip2_rml_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 864, 24, 694},
- {"cvmx_ciu2_en_pp#_ip2_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 896, 2, 718},
- {"cvmx_ciu2_en_pp#_ip2_wdog_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 928, 2, 720},
- {"cvmx_ciu2_en_pp#_ip2_wdog_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 960, 2, 722},
- {"cvmx_ciu2_en_pp#_ip2_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 992, 1, 724},
- {"cvmx_ciu2_en_pp#_ip2_wrkq_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1024, 1, 725},
- {"cvmx_ciu2_en_pp#_ip2_wrkq_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1056, 1, 726},
- {"cvmx_ciu2_en_pp#_ip3_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 1088, 2, 727},
- {"cvmx_ciu2_en_pp#_ip3_gpio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1120, 2, 729},
- {"cvmx_ciu2_en_pp#_ip3_gpio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1152, 2, 731},
- {"cvmx_ciu2_en_pp#_ip3_io" , CVMX_CSR_DB_TYPE_NCB, 64, 1184, 9, 733},
- {"cvmx_ciu2_en_pp#_ip3_io_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 1216, 9, 742},
- {"cvmx_ciu2_en_pp#_ip3_io_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 1248, 9, 751},
- {"cvmx_ciu2_en_pp#_ip3_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 1280, 2, 760},
- {"cvmx_ciu2_en_pp#_ip3_mbox_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1312, 2, 762},
- {"cvmx_ciu2_en_pp#_ip3_mbox_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1344, 2, 764},
- {"cvmx_ciu2_en_pp#_ip3_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 1376, 2, 766},
- {"cvmx_ciu2_en_pp#_ip3_mem_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1408, 2, 768},
- {"cvmx_ciu2_en_pp#_ip3_mem_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1440, 2, 770},
- {"cvmx_ciu2_en_pp#_ip3_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 1472, 21, 772},
- {"cvmx_ciu2_en_pp#_ip3_mio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1504, 21, 793},
- {"cvmx_ciu2_en_pp#_ip3_mio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1536, 21, 814},
- {"cvmx_ciu2_en_pp#_ip3_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 1568, 10, 835},
- {"cvmx_ciu2_en_pp#_ip3_pkt_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1600, 10, 845},
- {"cvmx_ciu2_en_pp#_ip3_pkt_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1632, 10, 855},
- {"cvmx_ciu2_en_pp#_ip3_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 1664, 24, 865},
- {"cvmx_ciu2_en_pp#_ip3_rml_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1696, 24, 889},
- {"cvmx_ciu2_en_pp#_ip3_rml_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1728, 24, 913},
- {"cvmx_ciu2_en_pp#_ip3_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 1760, 2, 937},
- {"cvmx_ciu2_en_pp#_ip3_wdog_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1792, 2, 939},
- {"cvmx_ciu2_en_pp#_ip3_wdog_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1824, 2, 941},
- {"cvmx_ciu2_en_pp#_ip3_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 1856, 1, 943},
- {"cvmx_ciu2_en_pp#_ip3_wrkq_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1888, 1, 944},
- {"cvmx_ciu2_en_pp#_ip3_wrkq_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1920, 1, 945},
- {"cvmx_ciu2_en_pp#_ip4_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 1952, 2, 946},
- {"cvmx_ciu2_en_pp#_ip4_gpio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1984, 2, 948},
- {"cvmx_ciu2_en_pp#_ip4_gpio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2016, 2, 950},
- {"cvmx_ciu2_en_pp#_ip4_io" , CVMX_CSR_DB_TYPE_NCB, 64, 2048, 9, 952},
- {"cvmx_ciu2_en_pp#_ip4_io_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 2080, 9, 961},
- {"cvmx_ciu2_en_pp#_ip4_io_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 2112, 9, 970},
- {"cvmx_ciu2_en_pp#_ip4_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 2144, 2, 979},
- {"cvmx_ciu2_en_pp#_ip4_mbox_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2176, 2, 981},
- {"cvmx_ciu2_en_pp#_ip4_mbox_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2208, 2, 983},
- {"cvmx_ciu2_en_pp#_ip4_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 2240, 2, 985},
- {"cvmx_ciu2_en_pp#_ip4_mem_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2272, 2, 987},
- {"cvmx_ciu2_en_pp#_ip4_mem_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2304, 2, 989},
- {"cvmx_ciu2_en_pp#_ip4_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 2336, 21, 991},
- {"cvmx_ciu2_en_pp#_ip4_mio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2368, 21, 1012},
- {"cvmx_ciu2_en_pp#_ip4_mio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2400, 21, 1033},
- {"cvmx_ciu2_en_pp#_ip4_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 2432, 10, 1054},
- {"cvmx_ciu2_en_pp#_ip4_pkt_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2464, 10, 1064},
- {"cvmx_ciu2_en_pp#_ip4_pkt_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2496, 10, 1074},
- {"cvmx_ciu2_en_pp#_ip4_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 2528, 24, 1084},
- {"cvmx_ciu2_en_pp#_ip4_rml_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2560, 24, 1108},
- {"cvmx_ciu2_en_pp#_ip4_rml_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2592, 24, 1132},
- {"cvmx_ciu2_en_pp#_ip4_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 2624, 2, 1156},
- {"cvmx_ciu2_en_pp#_ip4_wdog_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2656, 2, 1158},
- {"cvmx_ciu2_en_pp#_ip4_wdog_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2688, 2, 1160},
- {"cvmx_ciu2_en_pp#_ip4_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 2720, 1, 1162},
- {"cvmx_ciu2_en_pp#_ip4_wrkq_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2752, 1, 1163},
- {"cvmx_ciu2_en_pp#_ip4_wrkq_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2784, 1, 1164},
- {"cvmx_ciu2_intr_ciu_ready" , CVMX_CSR_DB_TYPE_NCB, 64, 2816, 2, 1165},
- {"cvmx_ciu2_intr_ram_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2817, 3, 1167},
- {"cvmx_ciu2_intr_ram_ecc_st" , CVMX_CSR_DB_TYPE_NCB, 64, 2818, 7, 1170},
- {"cvmx_ciu2_intr_slowdown" , CVMX_CSR_DB_TYPE_NCB, 64, 2819, 2, 1177},
- {"cvmx_ciu2_msi_rcv#" , CVMX_CSR_DB_TYPE_NCB, 64, 2820, 2, 1179},
- {"cvmx_ciu2_msi_sel#" , CVMX_CSR_DB_TYPE_NCB, 64, 3076, 6, 1181},
- {"cvmx_ciu2_msired_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 3332, 6, 1187},
- {"cvmx_ciu2_msired_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 3364, 6, 1193},
- {"cvmx_ciu2_msired_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 3396, 6, 1199},
- {"cvmx_ciu2_raw_io#_int_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 3428, 2, 1205},
- {"cvmx_ciu2_raw_io#_int_io" , CVMX_CSR_DB_TYPE_NCB, 64, 3430, 9, 1207},
- {"cvmx_ciu2_raw_io#_int_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 3432, 2, 1216},
- {"cvmx_ciu2_raw_io#_int_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 3434, 21, 1218},
- {"cvmx_ciu2_raw_io#_int_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 3436, 10, 1239},
- {"cvmx_ciu2_raw_io#_int_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 3438, 24, 1249},
- {"cvmx_ciu2_raw_io#_int_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 3440, 2, 1273},
- {"cvmx_ciu2_raw_io#_int_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 3442, 1, 1275},
- {"cvmx_ciu2_raw_pp#_ip2_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 3444, 2, 1276},
- {"cvmx_ciu2_raw_pp#_ip2_io" , CVMX_CSR_DB_TYPE_NCB, 64, 3476, 9, 1278},
- {"cvmx_ciu2_raw_pp#_ip2_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 3508, 2, 1287},
- {"cvmx_ciu2_raw_pp#_ip2_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 3540, 21, 1289},
- {"cvmx_ciu2_raw_pp#_ip2_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 3572, 10, 1310},
- {"cvmx_ciu2_raw_pp#_ip2_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 3604, 24, 1320},
- {"cvmx_ciu2_raw_pp#_ip2_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 3636, 2, 1344},
- {"cvmx_ciu2_raw_pp#_ip2_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 3668, 1, 1346},
- {"cvmx_ciu2_raw_pp#_ip3_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 3700, 2, 1347},
- {"cvmx_ciu2_raw_pp#_ip3_io" , CVMX_CSR_DB_TYPE_NCB, 64, 3732, 9, 1349},
- {"cvmx_ciu2_raw_pp#_ip3_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 3764, 2, 1358},
- {"cvmx_ciu2_raw_pp#_ip3_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 3796, 21, 1360},
- {"cvmx_ciu2_raw_pp#_ip3_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 3828, 10, 1381},
- {"cvmx_ciu2_raw_pp#_ip3_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 3860, 24, 1391},
- {"cvmx_ciu2_raw_pp#_ip3_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 3892, 2, 1415},
- {"cvmx_ciu2_raw_pp#_ip3_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 3924, 1, 1417},
- {"cvmx_ciu2_raw_pp#_ip4_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 3956, 2, 1418},
- {"cvmx_ciu2_raw_pp#_ip4_io" , CVMX_CSR_DB_TYPE_NCB, 64, 3988, 9, 1420},
- {"cvmx_ciu2_raw_pp#_ip4_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 4020, 2, 1429},
- {"cvmx_ciu2_raw_pp#_ip4_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 4052, 21, 1431},
- {"cvmx_ciu2_raw_pp#_ip4_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 4084, 10, 1452},
- {"cvmx_ciu2_raw_pp#_ip4_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 4116, 24, 1462},
- {"cvmx_ciu2_raw_pp#_ip4_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 4148, 2, 1486},
- {"cvmx_ciu2_raw_pp#_ip4_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 4180, 1, 1488},
- {"cvmx_ciu2_src_io#_int_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 4212, 2, 1489},
- {"cvmx_ciu2_src_io#_int_io" , CVMX_CSR_DB_TYPE_NCB, 64, 4214, 9, 1491},
- {"cvmx_ciu2_src_io#_int_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 4216, 2, 1500},
- {"cvmx_ciu2_src_io#_int_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 4218, 2, 1502},
- {"cvmx_ciu2_src_io#_int_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 4220, 21, 1504},
- {"cvmx_ciu2_src_io#_int_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 4222, 10, 1525},
- {"cvmx_ciu2_src_io#_int_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 4224, 24, 1535},
- {"cvmx_ciu2_src_io#_int_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 4226, 2, 1559},
- {"cvmx_ciu2_src_io#_int_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 4228, 1, 1561},
- {"cvmx_ciu2_src_pp#_ip2_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 4230, 2, 1562},
- {"cvmx_ciu2_src_pp#_ip2_io" , CVMX_CSR_DB_TYPE_NCB, 64, 4262, 9, 1564},
- {"cvmx_ciu2_src_pp#_ip2_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 4294, 2, 1573},
- {"cvmx_ciu2_src_pp#_ip2_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 4326, 2, 1575},
- {"cvmx_ciu2_src_pp#_ip2_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 4358, 21, 1577},
- {"cvmx_ciu2_src_pp#_ip2_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 4390, 10, 1598},
- {"cvmx_ciu2_src_pp#_ip2_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 4422, 24, 1608},
- {"cvmx_ciu2_src_pp#_ip2_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 4454, 2, 1632},
- {"cvmx_ciu2_src_pp#_ip2_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 4486, 1, 1634},
- {"cvmx_ciu2_src_pp#_ip3_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 4518, 2, 1635},
- {"cvmx_ciu2_src_pp#_ip3_io" , CVMX_CSR_DB_TYPE_NCB, 64, 4550, 9, 1637},
- {"cvmx_ciu2_src_pp#_ip3_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 4582, 2, 1646},
- {"cvmx_ciu2_src_pp#_ip3_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 4614, 2, 1648},
- {"cvmx_ciu2_src_pp#_ip3_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 4646, 21, 1650},
- {"cvmx_ciu2_src_pp#_ip3_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 4678, 10, 1671},
- {"cvmx_ciu2_src_pp#_ip3_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 4710, 24, 1681},
- {"cvmx_ciu2_src_pp#_ip3_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 4742, 2, 1705},
- {"cvmx_ciu2_src_pp#_ip3_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 4774, 1, 1707},
- {"cvmx_ciu2_src_pp#_ip4_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 4806, 2, 1708},
- {"cvmx_ciu2_src_pp#_ip4_io" , CVMX_CSR_DB_TYPE_NCB, 64, 4838, 9, 1710},
- {"cvmx_ciu2_src_pp#_ip4_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 4870, 2, 1719},
- {"cvmx_ciu2_src_pp#_ip4_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 4902, 2, 1721},
- {"cvmx_ciu2_src_pp#_ip4_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 4934, 21, 1723},
- {"cvmx_ciu2_src_pp#_ip4_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 4966, 10, 1744},
- {"cvmx_ciu2_src_pp#_ip4_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 4998, 24, 1754},
- {"cvmx_ciu2_src_pp#_ip4_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 5030, 2, 1778},
- {"cvmx_ciu2_src_pp#_ip4_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 5062, 1, 1780},
- {"cvmx_ciu2_sum_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 5094, 10, 1781},
- {"cvmx_ciu2_sum_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 5096, 10, 1791},
- {"cvmx_ciu2_sum_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 5128, 10, 1801},
- {"cvmx_ciu2_sum_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 5160, 10, 1811},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 5192, 2, 1821},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 5193, 2, 1823},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 5194, 2, 1825},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 5195, 2, 1827},
- {"cvmx_ciu_int_dbg_sel" , CVMX_CSR_DB_TYPE_NCB, 64, 5196, 6, 1829},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 5197, 2, 1835},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 5229, 2, 1837},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 5261, 2, 1839},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 5262, 2, 1841},
- {"cvmx_ciu_pp_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 5263, 2, 1843},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 5264, 2, 1845},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 5265, 1, 1847},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 5297, 3, 1848},
- {"cvmx_ciu_qlm0" , CVMX_CSR_DB_TYPE_NCB, 64, 5298, 8, 1851},
- {"cvmx_ciu_qlm1" , CVMX_CSR_DB_TYPE_NCB, 64, 5299, 13, 1859},
- {"cvmx_ciu_qlm2" , CVMX_CSR_DB_TYPE_NCB, 64, 5300, 13, 1872},
- {"cvmx_ciu_qlm3" , CVMX_CSR_DB_TYPE_NCB, 64, 5301, 13, 1885},
- {"cvmx_ciu_qlm4" , CVMX_CSR_DB_TYPE_NCB, 64, 5302, 13, 1898},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 5303, 7, 1911},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 5304, 8, 1918},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 5305, 2, 1926},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 5306, 2, 1928},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 5307, 2, 1930},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 5308, 2, 1932},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 5309, 3, 1934},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 5313, 7, 1937},
- {"cvmx_dfa_bist0" , CVMX_CSR_DB_TYPE_RSL, 64, 5345, 16, 1944},
- {"cvmx_dfa_bist1" , CVMX_CSR_DB_TYPE_RSL, 64, 5346, 20, 1960},
- {"cvmx_dfa_config" , CVMX_CSR_DB_TYPE_RSL, 64, 5347, 7, 1980},
- {"cvmx_dfa_control" , CVMX_CSR_DB_TYPE_RSL, 64, 5348, 7, 1987},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 5349, 2, 1994},
- {"cvmx_dfa_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 5350, 1, 1996},
- {"cvmx_dfa_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 5351, 1, 1997},
- {"cvmx_dfa_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 5352, 1, 1998},
- {"cvmx_dfa_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 5353, 1, 1999},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 5354, 5, 2000},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 5355, 3, 2005},
- {"cvmx_dfa_dtcfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 5356, 6, 2008},
- {"cvmx_dfa_error" , CVMX_CSR_DB_TYPE_RSL, 64, 5357, 12, 2014},
- {"cvmx_dfa_intmsk" , CVMX_CSR_DB_TYPE_RSL, 64, 5358, 11, 2026},
- {"cvmx_dfa_memhidat" , CVMX_CSR_DB_TYPE_NCB, 64, 5359, 1, 2037},
- {"cvmx_dfa_pfc0_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5360, 1, 2038},
- {"cvmx_dfa_pfc0_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5361, 5, 2039},
- {"cvmx_dfa_pfc1_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5362, 1, 2044},
- {"cvmx_dfa_pfc1_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5363, 5, 2045},
- {"cvmx_dfa_pfc2_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5364, 1, 2050},
- {"cvmx_dfa_pfc2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5365, 5, 2051},
- {"cvmx_dfa_pfc3_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5366, 1, 2056},
- {"cvmx_dfa_pfc3_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5367, 5, 2057},
- {"cvmx_dfa_pfc_gctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5368, 18, 2062},
- {"cvmx_dpi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 5369, 2, 2080},
- {"cvmx_dpi_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 5370, 3, 2082},
- {"cvmx_dpi_dma#_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 5371, 3, 2085},
- {"cvmx_dpi_dma#_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 5379, 2, 2088},
- {"cvmx_dpi_dma#_err_rsp_status", CVMX_CSR_DB_TYPE_NCB, 64, 5387, 2, 2090},
- {"cvmx_dpi_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 5395, 6, 2092},
- {"cvmx_dpi_dma#_iflight" , CVMX_CSR_DB_TYPE_NCB, 64, 5403, 2, 2098},
- {"cvmx_dpi_dma#_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 5411, 2, 2100},
- {"cvmx_dpi_dma#_reqbnk0" , CVMX_CSR_DB_TYPE_NCB, 64, 5419, 1, 2102},
- {"cvmx_dpi_dma#_reqbnk1" , CVMX_CSR_DB_TYPE_NCB, 64, 5427, 1, 2103},
- {"cvmx_dpi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 5435, 19, 2104},
- {"cvmx_dpi_dma_eng#_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5436, 2, 2123},
- {"cvmx_dpi_eng#_buf" , CVMX_CSR_DB_TYPE_NCB, 64, 5442, 5, 2125},
- {"cvmx_dpi_info_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 5448, 5, 2130},
- {"cvmx_dpi_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5449, 15, 2135},
- {"cvmx_dpi_int_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 5450, 15, 2150},
- {"cvmx_dpi_pint_info" , CVMX_CSR_DB_TYPE_NCB, 64, 5451, 4, 2165},
- {"cvmx_dpi_pkt_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 5452, 2, 2169},
- {"cvmx_dpi_req_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 5453, 2, 2171},
- {"cvmx_dpi_req_err_rsp_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5454, 2, 2173},
- {"cvmx_dpi_req_err_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 5455, 2, 2175},
- {"cvmx_dpi_req_err_rst_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5456, 2, 2177},
- {"cvmx_dpi_req_err_skip_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 5457, 4, 2179},
- {"cvmx_dpi_req_gbl_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5458, 2, 2183},
- {"cvmx_dpi_sli_prt#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5459, 14, 2185},
- {"cvmx_dpi_sli_prt#_err" , CVMX_CSR_DB_TYPE_NCB, 64, 5461, 2, 2199},
- {"cvmx_dpi_sli_prt#_err_info" , CVMX_CSR_DB_TYPE_NCB, 64, 5463, 6, 2201},
- {"cvmx_fpa_addr_range_error" , CVMX_CSR_DB_TYPE_RSL, 64, 5465, 3, 2207},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5466, 6, 2210},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5467, 10, 2216},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 5468, 3, 2226},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 5475, 2, 2229},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 5482, 3, 2231},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 5483, 2, 2234},
- {"cvmx_fpa_fpf8_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 5484, 3, 2236},
- {"cvmx_fpa_fpf8_size" , CVMX_CSR_DB_TYPE_RSL, 64, 5485, 2, 2239},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 5486, 51, 2241},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 5487, 51, 2292},
- {"cvmx_fpa_packet_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 5488, 2, 2343},
- {"cvmx_fpa_pool#_end_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 5489, 2, 2345},
- {"cvmx_fpa_pool#_start_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 5498, 2, 2347},
- {"cvmx_fpa_pool#_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 5507, 2, 2349},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 5516, 2, 2351},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 5525, 2, 2353},
- {"cvmx_fpa_que8_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 5533, 2, 2355},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 5534, 3, 2357},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 5535, 3, 2360},
- {"cvmx_fpa_wqe_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 5536, 2, 2363},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5537, 7, 2365},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 5542, 2, 2372},
- {"cvmx_gmx#_bpid_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 5547, 6, 2374},
- {"cvmx_gmx#_bpid_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 5627, 4, 2380},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5632, 2, 2384},
- {"cvmx_gmx#_ebp_dis" , CVMX_CSR_DB_TYPE_RSL, 64, 5637, 2, 2386},
- {"cvmx_gmx#_ebp_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 5642, 2, 2388},
- {"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 5647, 5, 2390},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 5652, 7, 2395},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 5657, 4, 2402},
- {"cvmx_gmx#_pipe_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5662, 6, 2406},
- {"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5667, 8, 2412},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 5672, 12, 2420},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 5692, 1, 2432},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 5712, 1, 2433},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 5732, 1, 2434},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 5752, 1, 2435},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 5772, 1, 2436},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 5792, 1, 2437},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5812, 2, 2438},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5832, 4, 2440},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 5852, 2, 2444},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 5872, 9, 2446},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5892, 13, 2455},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 5912, 2, 2468},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5932, 27, 2470},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5952, 27, 2497},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 5972, 2, 2524},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 5992, 2, 2526},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6012, 2, 2528},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 6032, 2, 2530},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 6052, 2, 2532},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 6072, 2, 2534},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 6092, 2, 2536},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 6112, 2, 2538},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 6132, 2, 2540},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 6152, 2, 2542},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 6172, 2, 2544},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 6192, 2, 2546},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 6212, 4, 2548},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 6232, 2, 2552},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 6252, 2, 2554},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 6272, 2, 2556},
- {"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6292, 4, 2558},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 6297, 4, 2562},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 6302, 2, 2566},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 6307, 5, 2568},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6312, 2, 2573},
- {"cvmx_gmx#_rxaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6317, 2, 2575},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 6322, 2, 2577},
- {"cvmx_gmx#_soft_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 6342, 3, 2579},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 6347, 3, 2582},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 6352, 5, 2585},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 6372, 2, 2590},
- {"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 6392, 2, 2592},
- {"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 6397, 2, 2594},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6402, 3, 2596},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 6422, 2, 2599},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 6442, 2, 2601},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 6462, 2, 2603},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 6482, 3, 2605},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 6502, 2, 2608},
- {"cvmx_gmx#_tx#_pipe" , CVMX_CSR_DB_TYPE_RSL, 64, 6522, 6, 2610},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6542, 2, 2616},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 6562, 2, 2618},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 6582, 2, 2620},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 6602, 2, 2622},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 6622, 2, 2624},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 6642, 2, 2626},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 6662, 2, 2628},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 6682, 2, 2630},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 6702, 2, 2632},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 6722, 2, 2634},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 6742, 2, 2636},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 6762, 2, 2638},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 6782, 2, 2640},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6802, 2, 2642},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 6822, 2, 2644},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 6842, 2, 2646},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 6847, 2, 2648},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 6852, 2, 2650},
- {"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 6857, 2, 2652},
- {"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 6862, 2, 2654},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 6867, 3, 2656},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 6872, 10, 2659},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6877, 10, 2669},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 6882, 2, 2679},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 6887, 2, 2681},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 6892, 6, 2683},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 6897, 2, 2689},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 6902, 2, 2691},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 6907, 2, 2693},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6912, 9, 2695},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 6917, 3, 2704},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 6922, 10, 2707},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 6938, 2, 2717},
- {"cvmx_gpio_clk_qlm#" , CVMX_CSR_DB_TYPE_NCB, 64, 6942, 5, 2719},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 6944, 2, 2724},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 6945, 2, 2726},
- {"cvmx_gpio_tim_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 6946, 2, 2728},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 6947, 2, 2730},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 6948, 2, 2732},
- {"cvmx_ilk_bist_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 6949, 42, 2734},
- {"cvmx_ilk_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 6950, 3, 2776},
- {"cvmx_ilk_gbl_int" , CVMX_CSR_DB_TYPE_RSL, 64, 6951, 6, 2779},
- {"cvmx_ilk_gbl_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 6952, 6, 2785},
- {"cvmx_ilk_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 6953, 14, 2791},
- {"cvmx_ilk_lne_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 6954, 11, 2805},
- {"cvmx_ilk_lne_sts_msg" , CVMX_CSR_DB_TYPE_RSL, 64, 6955, 8, 2816},
- {"cvmx_ilk_rx#_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 6956, 16, 2824},
- {"cvmx_ilk_rx#_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 6958, 14, 2840},
- {"cvmx_ilk_rx#_flow_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 6960, 1, 2854},
- {"cvmx_ilk_rx#_flow_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 6962, 1, 2855},
- {"cvmx_ilk_rx#_idx_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 6964, 4, 2856},
- {"cvmx_ilk_rx#_idx_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 6966, 6, 2860},
- {"cvmx_ilk_rx#_idx_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 6968, 6, 2866},
- {"cvmx_ilk_rx#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 6970, 9, 2872},
- {"cvmx_ilk_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 6972, 9, 2881},
- {"cvmx_ilk_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 6974, 2, 2890},
- {"cvmx_ilk_rx#_mem_cal0" , CVMX_CSR_DB_TYPE_RSL, 64, 6976, 9, 2892},
- {"cvmx_ilk_rx#_mem_cal1" , CVMX_CSR_DB_TYPE_RSL, 64, 6978, 9, 2901},
- {"cvmx_ilk_rx#_mem_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 6980, 2, 2910},
- {"cvmx_ilk_rx#_mem_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 6982, 2, 2912},
- {"cvmx_ilk_rx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 6984, 2, 2914},
- {"cvmx_ilk_rx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 6986, 2, 2916},
- {"cvmx_ilk_rx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 6988, 4, 2918},
- {"cvmx_ilk_rx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 6990, 2, 2922},
- {"cvmx_ilk_rx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 6992, 2, 2924},
- {"cvmx_ilk_rx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 6994, 2, 2926},
- {"cvmx_ilk_rx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 6996, 2, 2928},
- {"cvmx_ilk_rx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 6998, 2, 2930},
- {"cvmx_ilk_rx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 7000, 3, 2932},
- {"cvmx_ilk_rx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 7002, 1, 2935},
- {"cvmx_ilk_rx_lne#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 7004, 6, 2936},
- {"cvmx_ilk_rx_lne#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 7012, 10, 2942},
- {"cvmx_ilk_rx_lne#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 7020, 10, 2952},
- {"cvmx_ilk_rx_lne#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 7028, 2, 2962},
- {"cvmx_ilk_rx_lne#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 7036, 2, 2964},
- {"cvmx_ilk_rx_lne#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 7044, 4, 2966},
- {"cvmx_ilk_rx_lne#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 7052, 2, 2970},
- {"cvmx_ilk_rx_lne#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 7060, 4, 2972},
- {"cvmx_ilk_rx_lne#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 7068, 2, 2976},
- {"cvmx_ilk_rx_lne#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 7076, 2, 2978},
- {"cvmx_ilk_rx_lne#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 7084, 2, 2980},
- {"cvmx_ilk_rx_lne#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 7092, 2, 2982},
- {"cvmx_ilk_rx_lne#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 7100, 4, 2984},
- {"cvmx_ilk_rxf_idx_pmap" , CVMX_CSR_DB_TYPE_RSL, 64, 7108, 4, 2988},
- {"cvmx_ilk_rxf_mem_pmap" , CVMX_CSR_DB_TYPE_RSL, 64, 7109, 2, 2992},
- {"cvmx_ilk_ser_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 7110, 12, 2994},
- {"cvmx_ilk_tx#_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 7111, 17, 3006},
- {"cvmx_ilk_tx#_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 7113, 15, 3023},
- {"cvmx_ilk_tx#_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 7115, 4, 3038},
- {"cvmx_ilk_tx#_flow_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 7117, 1, 3042},
- {"cvmx_ilk_tx#_flow_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 7119, 1, 3043},
- {"cvmx_ilk_tx#_idx_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 7121, 4, 3044},
- {"cvmx_ilk_tx#_idx_pmap" , CVMX_CSR_DB_TYPE_RSL, 64, 7123, 4, 3048},
- {"cvmx_ilk_tx#_idx_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 7125, 6, 3052},
- {"cvmx_ilk_tx#_idx_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 7127, 6, 3058},
- {"cvmx_ilk_tx#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 7129, 5, 3064},
- {"cvmx_ilk_tx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 7131, 5, 3069},
- {"cvmx_ilk_tx#_mem_cal0" , CVMX_CSR_DB_TYPE_RSL, 64, 7133, 13, 3074},
- {"cvmx_ilk_tx#_mem_cal1" , CVMX_CSR_DB_TYPE_RSL, 64, 7135, 13, 3087},
- {"cvmx_ilk_tx#_mem_pmap" , CVMX_CSR_DB_TYPE_RSL, 64, 7137, 2, 3100},
- {"cvmx_ilk_tx#_mem_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 7139, 2, 3102},
- {"cvmx_ilk_tx#_mem_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 7141, 2, 3104},
- {"cvmx_ilk_tx#_pipe" , CVMX_CSR_DB_TYPE_RSL, 64, 7143, 4, 3106},
- {"cvmx_ilk_tx#_rmatch" , CVMX_CSR_DB_TYPE_RSL, 64, 7145, 5, 3110},
- {"cvmx_iob1_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7147, 9, 3115},
- {"cvmx_iob1_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7148, 4, 3124},
- {"cvmx_iob1_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 7149, 4, 3128},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7150, 19, 3132},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7151, 9, 3151},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 7152, 3, 3160},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 7153, 5, 3163},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 7154, 5, 3168},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 7155, 1, 3173},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 7156, 1, 3174},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 7157, 1, 3175},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 7158, 1, 3176},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 7159, 3, 3177},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 7160, 5, 3180},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 7161, 5, 3185},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 7162, 1, 3190},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 7163, 1, 3191},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 7164, 3, 3192},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 7165, 3, 3195},
- {"cvmx_iob_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 7166, 4, 3198},
- {"cvmx_iob_to_ncb_did_00_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7167, 2, 3202},
- {"cvmx_iob_to_ncb_did_111_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7168, 2, 3204},
- {"cvmx_iob_to_ncb_did_223_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7169, 2, 3206},
- {"cvmx_iob_to_ncb_did_24_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7170, 2, 3208},
- {"cvmx_iob_to_ncb_did_32_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7171, 2, 3210},
- {"cvmx_iob_to_ncb_did_40_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7172, 2, 3212},
- {"cvmx_iob_to_ncb_did_55_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7173, 2, 3214},
- {"cvmx_iob_to_ncb_did_64_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7174, 2, 3216},
- {"cvmx_iob_to_ncb_did_79_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7175, 2, 3218},
- {"cvmx_iob_to_ncb_did_96_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7176, 2, 3220},
- {"cvmx_iob_to_ncb_did_98_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7177, 2, 3222},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 7178, 2, 3224},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 7179, 2, 3226},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 7180, 2, 3228},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 7181, 24, 3230},
- {"cvmx_ipd_bpid#_mbuf_th" , CVMX_CSR_DB_TYPE_NCB, 64, 7182, 3, 3254},
- {"cvmx_ipd_bpid_bp_counter#" , CVMX_CSR_DB_TYPE_NCB, 64, 7246, 2, 3257},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 7310, 1, 3259},
- {"cvmx_ipd_credits" , CVMX_CSR_DB_TYPE_NCB, 64, 7311, 3, 3260},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 7312, 18, 3263},
- {"cvmx_ipd_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 7313, 5, 3281},
- {"cvmx_ipd_free_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 7314, 6, 3286},
- {"cvmx_ipd_free_ptr_value" , CVMX_CSR_DB_TYPE_NCB, 64, 7315, 2, 3292},
- {"cvmx_ipd_hold_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 7316, 6, 3294},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 7317, 24, 3300},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 7318, 24, 3324},
- {"cvmx_ipd_next_pkt_ptr" , CVMX_CSR_DB_TYPE_NCB, 64, 7319, 2, 3348},
- {"cvmx_ipd_next_wqe_ptr" , CVMX_CSR_DB_TYPE_NCB, 64, 7320, 2, 3350},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 7321, 2, 3352},
- {"cvmx_ipd_on_bp_drop_pkt#" , CVMX_CSR_DB_TYPE_NCB, 64, 7322, 1, 3354},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 7323, 2, 3355},
- {"cvmx_ipd_pkt_err" , CVMX_CSR_DB_TYPE_NCB, 64, 7324, 2, 3357},
- {"cvmx_ipd_port_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 7325, 5, 3359},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 7326, 2, 3364},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 7838, 1, 3366},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 7846, 1, 3367},
- {"cvmx_ipd_port_sop#" , CVMX_CSR_DB_TYPE_NCB, 64, 7854, 1, 3368},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 7855, 6, 3369},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 7856, 2, 3375},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 7864, 2, 3377},
- {"cvmx_ipd_red_bpid_enable#" , CVMX_CSR_DB_TYPE_NCB, 64, 7865, 1, 3379},
- {"cvmx_ipd_red_delay" , CVMX_CSR_DB_TYPE_NCB, 64, 7866, 3, 3380},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 7867, 5, 3383},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 7875, 3, 3388},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 7876, 3, 3391},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 7877, 2, 3394},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7878, 4, 3396},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7879, 3, 3400},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 7880, 5, 3403},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 7881, 5, 3408},
- {"cvmx_l2c_big_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7882, 4, 3413},
- {"cvmx_l2c_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 7883, 9, 3417},
- {"cvmx_l2c_bst_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 7884, 5, 3426},
- {"cvmx_l2c_bst_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 7888, 5, 3431},
- {"cvmx_l2c_bst_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 7892, 3, 3436},
- {"cvmx_l2c_cop0_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 7896, 1, 3439},
- {"cvmx_l2c_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 16344, 14, 3440},
- {"cvmx_l2c_dut_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 16345, 4, 3454},
- {"cvmx_l2c_err_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 24537, 9, 3458},
- {"cvmx_l2c_err_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 24541, 9, 3467},
- {"cvmx_l2c_err_vbf#" , CVMX_CSR_DB_TYPE_RSL, 64, 24545, 6, 3476},
- {"cvmx_l2c_err_xmc" , CVMX_CSR_DB_TYPE_RSL, 64, 24549, 5, 3482},
- {"cvmx_l2c_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 24550, 9, 3487},
- {"cvmx_l2c_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 24551, 14, 3496},
- {"cvmx_l2c_ioc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 24552, 1, 3510},
- {"cvmx_l2c_ior#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 24553, 1, 3511},
- {"cvmx_l2c_qos_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 24554, 4, 3512},
- {"cvmx_l2c_qos_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 24556, 2, 3516},
- {"cvmx_l2c_qos_wgt" , CVMX_CSR_DB_TYPE_RSL, 64, 24588, 8, 3518},
- {"cvmx_l2c_rsc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 24589, 1, 3526},
- {"cvmx_l2c_rsd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 24593, 1, 3527},
- {"cvmx_l2c_tad#_ecc0" , CVMX_CSR_DB_TYPE_RSL, 64, 24597, 8, 3528},
- {"cvmx_l2c_tad#_ecc1" , CVMX_CSR_DB_TYPE_RSL, 64, 24601, 8, 3536},
- {"cvmx_l2c_tad#_ien" , CVMX_CSR_DB_TYPE_RSL, 64, 24605, 10, 3544},
- {"cvmx_l2c_tad#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 24609, 10, 3554},
- {"cvmx_l2c_tad#_pfc0" , CVMX_CSR_DB_TYPE_RSL, 64, 24613, 1, 3564},
- {"cvmx_l2c_tad#_pfc1" , CVMX_CSR_DB_TYPE_RSL, 64, 24617, 1, 3565},
- {"cvmx_l2c_tad#_pfc2" , CVMX_CSR_DB_TYPE_RSL, 64, 24621, 1, 3566},
- {"cvmx_l2c_tad#_pfc3" , CVMX_CSR_DB_TYPE_RSL, 64, 24625, 1, 3567},
- {"cvmx_l2c_tad#_prf" , CVMX_CSR_DB_TYPE_RSL, 64, 24629, 5, 3568},
- {"cvmx_l2c_tad#_tag" , CVMX_CSR_DB_TYPE_RSL, 64, 24633, 9, 3573},
- {"cvmx_l2c_ver_id" , CVMX_CSR_DB_TYPE_RSL, 64, 24637, 1, 3582},
- {"cvmx_l2c_ver_iob" , CVMX_CSR_DB_TYPE_RSL, 64, 24638, 2, 3583},
- {"cvmx_l2c_ver_msc" , CVMX_CSR_DB_TYPE_RSL, 64, 24639, 3, 3585},
- {"cvmx_l2c_ver_pp" , CVMX_CSR_DB_TYPE_RSL, 64, 24640, 2, 3588},
- {"cvmx_l2c_virtid_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 24641, 4, 3590},
- {"cvmx_l2c_virtid_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 24643, 2, 3594},
- {"cvmx_l2c_vrt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 24675, 6, 3596},
- {"cvmx_l2c_vrt_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 24676, 3, 3602},
- {"cvmx_l2c_wpar_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 25700, 2, 3605},
- {"cvmx_l2c_wpar_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 25702, 2, 3607},
- {"cvmx_l2c_xmc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 25734, 1, 3609},
- {"cvmx_l2c_xmc_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 25738, 4, 3610},
- {"cvmx_l2c_xmd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 25739, 1, 3614},
- {"cvmx_lmc#_char_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25743, 5, 3615},
- {"cvmx_lmc#_char_mask0" , CVMX_CSR_DB_TYPE_RSL, 64, 25747, 1, 3620},
- {"cvmx_lmc#_char_mask1" , CVMX_CSR_DB_TYPE_RSL, 64, 25751, 2, 3621},
- {"cvmx_lmc#_char_mask2" , CVMX_CSR_DB_TYPE_RSL, 64, 25755, 1, 3623},
- {"cvmx_lmc#_char_mask3" , CVMX_CSR_DB_TYPE_RSL, 64, 25759, 2, 3624},
- {"cvmx_lmc#_char_mask4" , CVMX_CSR_DB_TYPE_RSL, 64, 25763, 12, 3626},
- {"cvmx_lmc#_comp_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 25767, 11, 3638},
- {"cvmx_lmc#_config" , CVMX_CSR_DB_TYPE_RSL, 64, 25771, 21, 3649},
- {"cvmx_lmc#_control" , CVMX_CSR_DB_TYPE_RSL, 64, 25775, 26, 3670},
- {"cvmx_lmc#_dclk_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 25779, 1, 3696},
- {"cvmx_lmc#_ddr_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25783, 11, 3697},
- {"cvmx_lmc#_dimm#_params" , CVMX_CSR_DB_TYPE_RSL, 64, 25787, 16, 3708},
- {"cvmx_lmc#_dimm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25795, 5, 3724},
- {"cvmx_lmc#_dll_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 25799, 7, 3729},
- {"cvmx_lmc#_dll_ctl3" , CVMX_CSR_DB_TYPE_RSL, 64, 25803, 16, 3736},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 25807, 4, 3752},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 25811, 5, 3756},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 25815, 6, 3761},
- {"cvmx_lmc#_ifb_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 25819, 1, 3767},
- {"cvmx_lmc#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 25823, 4, 3768},
- {"cvmx_lmc#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 25827, 4, 3772},
- {"cvmx_lmc#_modereg_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 25831, 16, 3776},
- {"cvmx_lmc#_modereg_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 25835, 25, 3792},
- {"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 25839, 10, 3817},
- {"cvmx_lmc#_ops_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 25843, 1, 3827},
- {"cvmx_lmc#_phy_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25847, 10, 3828},
- {"cvmx_lmc#_reset_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25851, 5, 3838},
- {"cvmx_lmc#_rlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25855, 10, 3843},
- {"cvmx_lmc#_rlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 25859, 1, 3853},
- {"cvmx_lmc#_rlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 25863, 11, 3854},
- {"cvmx_lmc#_rodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 25879, 8, 3865},
- {"cvmx_lmc#_slot_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 25883, 5, 3873},
- {"cvmx_lmc#_slot_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 25887, 5, 3878},
- {"cvmx_lmc#_slot_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 25891, 5, 3883},
- {"cvmx_lmc#_timing_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 25895, 12, 3888},
- {"cvmx_lmc#_timing_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 25899, 13, 3900},
- {"cvmx_lmc#_tro_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25903, 3, 3913},
- {"cvmx_lmc#_tro_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 25907, 2, 3916},
- {"cvmx_lmc#_wlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25911, 6, 3918},
- {"cvmx_lmc#_wlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 25915, 3, 3924},
- {"cvmx_lmc#_wlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 25919, 11, 3927},
- {"cvmx_lmc#_wodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 25935, 8, 3938},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 25939, 2, 3946},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 25940, 3, 3948},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 25941, 10, 3951},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 25943, 3, 3961},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 25945, 3, 3964},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 25947, 15, 3967},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 25949, 3, 3982},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 25950, 3, 3985},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 25951, 3, 3988},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 25952, 5, 3991},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 25954, 1, 3996},
- {"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 25955, 9, 3997},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 25956, 13, 4006},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 25964, 13, 4019},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 25972, 6, 4032},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 25973, 1, 4038},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 25975, 2, 4039},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 25976, 2, 4041},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 25977, 12, 4043},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 25978, 18, 4055},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 25979, 4, 4073},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 25980, 1, 4077},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 25981, 10, 4078},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 25982, 3, 4088},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 25983, 8, 4091},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 25984, 7, 4099},
- {"cvmx_mio_fus_read_times" , CVMX_CSR_DB_TYPE_RSL, 64, 25985, 6, 4106},
- {"cvmx_mio_fus_repair_res0" , CVMX_CSR_DB_TYPE_RSL, 64, 25986, 5, 4112},
- {"cvmx_mio_fus_repair_res1" , CVMX_CSR_DB_TYPE_RSL, 64, 25987, 4, 4117},
- {"cvmx_mio_fus_repair_res2" , CVMX_CSR_DB_TYPE_RSL, 64, 25988, 2, 4121},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 25989, 4, 4123},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 25990, 2, 4127},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 25991, 2, 4129},
- {"cvmx_mio_gpio_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 25992, 3, 4131},
- {"cvmx_mio_ndf_dma_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 25993, 10, 4134},
- {"cvmx_mio_ndf_dma_int" , CVMX_CSR_DB_TYPE_RSL, 64, 25994, 2, 4144},
- {"cvmx_mio_ndf_dma_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 25995, 2, 4146},
- {"cvmx_mio_ptp_clock_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 25996, 10, 4148},
- {"cvmx_mio_ptp_clock_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 25997, 2, 4158},
- {"cvmx_mio_ptp_clock_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 25998, 1, 4160},
- {"cvmx_mio_ptp_clock_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 25999, 2, 4161},
- {"cvmx_mio_ptp_evt_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 26000, 1, 4163},
- {"cvmx_mio_ptp_timestamp" , CVMX_CSR_DB_TYPE_NCB, 64, 26001, 1, 4164},
- {"cvmx_mio_qlm#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 26002, 4, 4165},
- {"cvmx_mio_rst_boot" , CVMX_CSR_DB_TYPE_RSL, 64, 26007, 11, 4169},
- {"cvmx_mio_rst_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 26008, 5, 4180},
- {"cvmx_mio_rst_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 26009, 10, 4185},
- {"cvmx_mio_rst_delay" , CVMX_CSR_DB_TYPE_RSL, 64, 26011, 3, 4195},
- {"cvmx_mio_rst_int" , CVMX_CSR_DB_TYPE_RSL, 64, 26012, 6, 4198},
- {"cvmx_mio_rst_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 26013, 6, 4204},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 26014, 13, 4210},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 26016, 12, 4223},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 26018, 3, 4235},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 26020, 3, 4238},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 26022, 2, 4241},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 26024, 2, 4243},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 26026, 2, 4245},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 26028, 7, 4247},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 26030, 2, 4254},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 26032, 7, 4256},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 26034, 4, 4263},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 26036, 8, 4267},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 26038, 9, 4275},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 26040, 7, 4284},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 26042, 9, 4291},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 26044, 2, 4300},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 26046, 2, 4302},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 26048, 4, 4304},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 26050, 2, 4308},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 26052, 2, 4310},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 26054, 2, 4312},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 26056, 4, 4314},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 26058, 2, 4318},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 26060, 2, 4320},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 26062, 2, 4322},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 26064, 2, 4324},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 26066, 2, 4326},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 26068, 2, 4328},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 26070, 6, 4330},
- {"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 26072, 7, 4336},
- {"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 26073, 9, 4343},
- {"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 26074, 9, 4352},
- {"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 26075, 2, 4361},
- {"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 26076, 3, 4363},
- {"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 26077, 4, 4366},
- {"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 26078, 4, 4370},
- {"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 26079, 9, 4374},
- {"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 26080, 2, 4383},
- {"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 26081, 2, 4385},
- {"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 26082, 4, 4387},
- {"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 26083, 4, 4391},
- {"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 26084, 4, 4395},
- {"cvmx_mix#_tsctl" , CVMX_CSR_DB_TYPE_NCB, 64, 26085, 6, 4399},
- {"cvmx_mix#_tstamp" , CVMX_CSR_DB_TYPE_NCB, 64, 26086, 1, 4405},
- {"cvmx_ndf_bt_pg_info" , CVMX_CSR_DB_TYPE_NCB, 64, 26087, 4, 4406},
- {"cvmx_ndf_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 26088, 1, 4410},
- {"cvmx_ndf_drbell" , CVMX_CSR_DB_TYPE_NCB, 64, 26089, 2, 4411},
- {"cvmx_ndf_ecc_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 26090, 3, 4413},
- {"cvmx_ndf_int" , CVMX_CSR_DB_TYPE_NCB, 64, 26091, 8, 4416},
- {"cvmx_ndf_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 26092, 8, 4424},
- {"cvmx_ndf_misc" , CVMX_CSR_DB_TYPE_NCB, 64, 26093, 12, 4432},
- {"cvmx_ndf_st_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 26094, 8, 4444},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26095, 2, 4452},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26097, 24, 4454},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26099, 4, 4478},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26101, 5, 4482},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26103, 5, 4487},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26105, 2, 4492},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26107, 1, 4494},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26109, 1, 4495},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26111, 5, 4496},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26113, 2, 4501},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26115, 1, 4503},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26117, 1, 4504},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26119, 4, 4505},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26121, 2, 4509},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26123, 2, 4511},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26125, 1, 4513},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26127, 1, 4514},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26129, 2, 4515},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26131, 3, 4517},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26133, 2, 4520},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26135, 2, 4522},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26137, 4, 4524},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26139, 10, 4528},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26141, 12, 4538},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26143, 8, 4550},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26145, 2, 4558},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26147, 1, 4560},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26149, 2, 4561},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26151, 7, 4563},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26153, 12, 4570},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26155, 19, 4582},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26157, 11, 4601},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26159, 19, 4612},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26161, 11, 4631},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26163, 8, 4642},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26165, 4, 4650},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26167, 11, 4654},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26169, 3, 4665},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26171, 14, 4668},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26173, 14, 4682},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26175, 14, 4696},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26177, 9, 4710},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26179, 9, 4719},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26181, 6, 4728},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26183, 1, 4734},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26185, 1, 4735},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26187, 1, 4736},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26189, 1, 4737},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26191, 2, 4738},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26193, 1, 4740},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26195, 6, 4741},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26197, 7, 4747},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26199, 11, 4754},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26201, 5, 4765},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26203, 8, 4770},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26205, 19, 4778},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26207, 3, 4797},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26209, 1, 4800},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26211, 1, 4801},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26213, 3, 4802},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26215, 3, 4805},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26217, 3, 4808},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26219, 4, 4811},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26221, 4, 4815},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26223, 4, 4819},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26225, 7, 4823},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26227, 5, 4830},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26229, 5, 4835},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26231, 4, 4840},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26233, 4, 4844},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26235, 4, 4848},
- {"cvmx_pcieep#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26237, 7, 4852},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26239, 1, 4859},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26241, 1, 4860},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26243, 2, 4861},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26245, 24, 4863},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26247, 4, 4887},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26249, 5, 4891},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26251, 1, 4896},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26253, 1, 4897},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26255, 4, 4898},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26257, 17, 4902},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26259, 4, 4919},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26261, 6, 4923},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26263, 1, 4929},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26265, 1, 4930},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26267, 2, 4931},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26269, 2, 4933},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26271, 1, 4935},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26273, 15, 4936},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26275, 10, 4951},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26277, 12, 4961},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26279, 7, 4973},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26281, 2, 4980},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26283, 1, 4982},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26285, 2, 4983},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26287, 7, 4985},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26289, 11, 4992},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26291, 19, 5003},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26293, 11, 5022},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26295, 20, 5033},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26297, 12, 5053},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26299, 22, 5065},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26301, 8, 5087},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26303, 4, 5095},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26305, 11, 5099},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26307, 8, 5110},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26309, 4, 5118},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26311, 11, 5122},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26313, 1, 5133},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26315, 1, 5134},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26317, 3, 5135},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26319, 14, 5138},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26321, 14, 5152},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26323, 14, 5166},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26325, 9, 5180},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26327, 9, 5189},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26329, 6, 5198},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26331, 1, 5204},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26333, 1, 5205},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26335, 1, 5206},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26337, 1, 5207},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26339, 4, 5208},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26341, 9, 5212},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26343, 2, 5221},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26345, 2, 5223},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26347, 1, 5225},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26349, 6, 5226},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26351, 7, 5232},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26353, 11, 5239},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26355, 5, 5250},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26357, 8, 5255},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26359, 19, 5263},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26361, 3, 5282},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26363, 1, 5285},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26365, 1, 5286},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26367, 3, 5287},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26369, 3, 5290},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26371, 3, 5293},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26373, 4, 5296},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26375, 4, 5300},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26377, 4, 5304},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26379, 7, 5308},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26381, 5, 5315},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26383, 5, 5320},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26385, 4, 5325},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26387, 4, 5329},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26389, 4, 5333},
- {"cvmx_pcierc#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26391, 7, 5337},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26393, 1, 5344},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26395, 1, 5345},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26397, 9, 5346},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26417, 6, 5355},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26437, 9, 5361},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26457, 6, 5370},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26477, 14, 5376},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26497, 14, 5390},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 26517, 2, 5404},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26537, 4, 5406},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26557, 8, 5410},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26577, 13, 5418},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26597, 17, 5431},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26617, 7, 5448},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26637, 3, 5455},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26657, 8, 5458},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26677, 7, 5466},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26697, 4, 5473},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 26717, 5, 5477},
- {"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26737, 8, 5482},
- {"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26742, 2, 5490},
- {"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 26747, 5, 5492},
- {"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26752, 10, 5497},
- {"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26757, 2, 5507},
- {"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26762, 8, 5509},
- {"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26767, 8, 5517},
- {"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26772, 6, 5525},
- {"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26777, 5, 5531},
- {"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 26782, 5, 5536},
- {"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26787, 3, 5541},
- {"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26792, 6, 5544},
- {"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26797, 9, 5550},
- {"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 26802, 5, 5559},
- {"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26807, 10, 5564},
- {"cvmx_pem#_bar1_index#" , CVMX_CSR_DB_TYPE_RSL, 64, 26812, 5, 5574},
- {"cvmx_pem#_bar2_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 26844, 3, 5579},
- {"cvmx_pem#_bar_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 26846, 5, 5582},
- {"cvmx_pem#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 26848, 9, 5587},
- {"cvmx_pem#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 26850, 11, 5596},
- {"cvmx_pem#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 26852, 2, 5607},
- {"cvmx_pem#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 26854, 2, 5609},
- {"cvmx_pem#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 26856, 2, 5611},
- {"cvmx_pem#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 26858, 18, 5613},
- {"cvmx_pem#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 26860, 32, 5631},
- {"cvmx_pem#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 26862, 32, 5663},
- {"cvmx_pem#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 26864, 5, 5695},
- {"cvmx_pem#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 26866, 15, 5700},
- {"cvmx_pem#_int_enb_int" , CVMX_CSR_DB_TYPE_RSL, 64, 26868, 15, 5715},
- {"cvmx_pem#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 26870, 15, 5730},
- {"cvmx_pem#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 26872, 2, 5745},
- {"cvmx_pem#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 26874, 2, 5747},
- {"cvmx_pem#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 26876, 2, 5749},
- {"cvmx_pem#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 26878, 2, 5751},
- {"cvmx_pem#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 26886, 2, 5753},
- {"cvmx_pem#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 26894, 8, 5755},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 26896, 5, 5763},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 26897, 2, 5768},
- {"cvmx_pip_clken" , CVMX_CSR_DB_TYPE_RSL, 64, 26898, 2, 5770},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 26899, 4, 5772},
- {"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 26903, 16, 5776},
- {"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 26904, 16, 5792},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 26905, 3, 5808},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 26907, 8, 5811},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 26908, 21, 5819},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 26909, 14, 5840},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26910, 14, 5854},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 26911, 2, 5868},
- {"cvmx_pip_pri_tbl#" , CVMX_CSR_DB_TYPE_RSL, 64, 26912, 15, 5870},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 27168, 30, 5885},
- {"cvmx_pip_prt_cfgb#" , CVMX_CSR_DB_TYPE_RSL, 64, 27232, 4, 5915},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 27296, 33, 5919},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 27360, 9, 5952},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 27368, 2, 5961},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 27369, 2, 5963},
- {"cvmx_pip_stat0_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27370, 2, 5965},
- {"cvmx_pip_stat10_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27434, 2, 5967},
- {"cvmx_pip_stat11_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27498, 2, 5969},
- {"cvmx_pip_stat1_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27562, 2, 5971},
- {"cvmx_pip_stat2_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27626, 2, 5973},
- {"cvmx_pip_stat3_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27690, 2, 5975},
- {"cvmx_pip_stat4_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27754, 2, 5977},
- {"cvmx_pip_stat5_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27818, 2, 5979},
- {"cvmx_pip_stat6_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27882, 2, 5981},
- {"cvmx_pip_stat7_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27946, 2, 5983},
- {"cvmx_pip_stat8_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28010, 2, 5985},
- {"cvmx_pip_stat9_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28074, 2, 5987},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 28138, 4, 5989},
- {"cvmx_pip_stat_inb_errs_pknd#", CVMX_CSR_DB_TYPE_RSL, 64, 28139, 2, 5993},
- {"cvmx_pip_stat_inb_octs_pknd#", CVMX_CSR_DB_TYPE_RSL, 64, 28203, 2, 5995},
- {"cvmx_pip_stat_inb_pkts_pknd#", CVMX_CSR_DB_TYPE_RSL, 64, 28267, 2, 5997},
- {"cvmx_pip_sub_pkind_fcs#" , CVMX_CSR_DB_TYPE_RSL, 64, 28331, 1, 5999},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 28332, 2, 6000},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 28396, 2, 6002},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 28397, 3, 6004},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 28398, 3, 6007},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 28399, 2, 6010},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 28400, 2, 6012},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 28401, 4, 6014},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 28402, 5, 6018},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 28403, 4, 6023},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 28404, 8, 6027},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 28405, 1, 6035},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 28406, 1, 6036},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 28407, 5, 6037},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 28408, 1, 6042},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 28409, 13, 6043},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 28410, 7, 6056},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 28411, 13, 6063},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 28412, 6, 6076},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 28413, 9, 6082},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 28414, 4, 6091},
- {"cvmx_pko_mem_iport_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 28415, 13, 6095},
- {"cvmx_pko_mem_iport_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 28416, 6, 6108},
- {"cvmx_pko_mem_iqueue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 28417, 10, 6114},
- {"cvmx_pko_mem_iqueue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 28418, 5, 6124},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 28419, 5, 6129},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 28420, 4, 6134},
- {"cvmx_pko_mem_throttle_int" , CVMX_CSR_DB_TYPE_RSL, 64, 28421, 6, 6138},
- {"cvmx_pko_mem_throttle_pipe" , CVMX_CSR_DB_TYPE_RSL, 64, 28422, 6, 6144},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 28423, 19, 6150},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 28424, 4, 6169},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 28425, 1, 6173},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 28426, 1, 6174},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 28427, 1, 6175},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 28428, 1, 6176},
- {"cvmx_pko_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 28429, 1, 6177},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 28430, 16, 6178},
- {"cvmx_pko_reg_engine_inflight1", CVMX_CSR_DB_TYPE_RSL, 64, 28431, 5, 6194},
- {"cvmx_pko_reg_engine_storage#", CVMX_CSR_DB_TYPE_RSL, 64, 28432, 16, 6199},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 28434, 2, 6215},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 28435, 5, 6217},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 28436, 8, 6222},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 28437, 5, 6230},
- {"cvmx_pko_reg_loopback_bpid" , CVMX_CSR_DB_TYPE_RSL, 64, 28438, 17, 6235},
- {"cvmx_pko_reg_loopback_pkind" , CVMX_CSR_DB_TYPE_RSL, 64, 28439, 17, 6252},
- {"cvmx_pko_reg_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 28440, 8, 6269},
- {"cvmx_pko_reg_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 28441, 2, 6277},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 28442, 2, 6279},
- {"cvmx_pko_reg_queue_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 28443, 3, 6281},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 28444, 3, 6284},
- {"cvmx_pko_reg_throttle" , CVMX_CSR_DB_TYPE_RSL, 64, 28445, 2, 6287},
- {"cvmx_pko_reg_timestamp" , CVMX_CSR_DB_TYPE_RSL, 64, 28446, 2, 6289},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 28447, 1, 6291},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 28448, 1, 6292},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 28449, 1, 6293},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 28450, 5, 6294},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 28451, 5, 6299},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 28452, 4, 6304},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 28453, 10, 6308},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 28454, 1, 6318},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 28455, 3, 6319},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 28456, 7, 6322},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 28457, 2, 6329},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 28458, 1, 6331},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 28459, 1, 6332},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 28460, 1, 6333},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 28461, 18, 6334},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 28462, 3, 6352},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 28463, 2, 6355},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 28464, 3, 6357},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 28465, 7, 6360},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 28466, 2, 6367},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 28467, 2, 6369},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 28468, 2, 6371},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 28469, 3, 6373},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 28470, 3, 6376},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 28471, 9, 6379},
- {"cvmx_rnm_eer_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 28472, 1, 6388},
- {"cvmx_rnm_eer_key" , CVMX_CSR_DB_TYPE_RSL, 64, 28473, 1, 6389},
- {"cvmx_rnm_serial_num" , CVMX_CSR_DB_TYPE_RSL, 64, 28474, 1, 6390},
- {"cvmx_sli_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28475, 26, 6391},
- {"cvmx_sli_ctl_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28476, 16, 6417},
- {"cvmx_sli_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28478, 4, 6433},
- {"cvmx_sli_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28479, 5, 6437},
- {"cvmx_sli_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28480, 3, 6442},
- {"cvmx_sli_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28481, 3, 6445},
- {"cvmx_sli_dma#_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28482, 2, 6448},
- {"cvmx_sli_dma#_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28484, 2, 6450},
- {"cvmx_sli_dma#_tim" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28486, 2, 6452},
- {"cvmx_sli_int_enb_ciu" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28488, 36, 6454},
- {"cvmx_sli_int_enb_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28489, 38, 6490},
- {"cvmx_sli_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28491, 38, 6528},
- {"cvmx_sli_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28492, 1, 6566},
- {"cvmx_sli_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28493, 1, 6567},
- {"cvmx_sli_mac_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28494, 13, 6568},
- {"cvmx_sli_mac_number" , CVMX_CSR_DB_TYPE_PEXP, 64, 28495, 2, 6581},
- {"cvmx_sli_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28496, 3, 6583},
- {"cvmx_sli_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28497, 10, 6586},
- {"cvmx_sli_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28513, 1, 6596},
- {"cvmx_sli_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28514, 1, 6597},
- {"cvmx_sli_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28515, 1, 6598},
- {"cvmx_sli_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28516, 1, 6599},
- {"cvmx_sli_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28517, 1, 6600},
- {"cvmx_sli_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28518, 1, 6601},
- {"cvmx_sli_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28519, 1, 6602},
- {"cvmx_sli_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28520, 1, 6603},
- {"cvmx_sli_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28521, 3, 6604},
- {"cvmx_sli_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28522, 1, 6607},
- {"cvmx_sli_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28523, 1, 6608},
- {"cvmx_sli_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28524, 1, 6609},
- {"cvmx_sli_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28525, 1, 6610},
- {"cvmx_sli_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28526, 1, 6611},
- {"cvmx_sli_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28527, 1, 6612},
- {"cvmx_sli_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28528, 1, 6613},
- {"cvmx_sli_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28529, 1, 6614},
- {"cvmx_sli_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28530, 3, 6615},
- {"cvmx_sli_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28531, 2, 6618},
- {"cvmx_sli_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28532, 3, 6620},
- {"cvmx_sli_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28533, 3, 6623},
- {"cvmx_sli_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28534, 3, 6626},
- {"cvmx_sli_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28535, 3, 6629},
- {"cvmx_sli_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28567, 2, 6632},
- {"cvmx_sli_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28599, 2, 6634},
- {"cvmx_sli_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28631, 5, 6636},
- {"cvmx_sli_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28663, 21, 6641},
- {"cvmx_sli_pkt#_out_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28695, 3, 6662},
- {"cvmx_sli_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28727, 2, 6665},
- {"cvmx_sli_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28759, 2, 6667},
- {"cvmx_sli_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28791, 2, 6669},
- {"cvmx_sli_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28823, 2, 6671},
- {"cvmx_sli_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28824, 2, 6673},
- {"cvmx_sli_pkt_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28825, 3, 6675},
- {"cvmx_sli_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28826, 1, 6678},
- {"cvmx_sli_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28827, 2, 6679},
- {"cvmx_sli_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28828, 2, 6681},
- {"cvmx_sli_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28829, 2, 6683},
- {"cvmx_sli_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28830, 2, 6685},
- {"cvmx_sli_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28862, 2, 6687},
- {"cvmx_sli_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28863, 1, 6689},
- {"cvmx_sli_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28864, 17, 6690},
- {"cvmx_sli_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28865, 2, 6707},
- {"cvmx_sli_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28866, 1, 6709},
- {"cvmx_sli_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28867, 2, 6710},
- {"cvmx_sli_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28868, 3, 6712},
- {"cvmx_sli_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28869, 2, 6715},
- {"cvmx_sli_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28870, 2, 6717},
- {"cvmx_sli_pkt_out_bp_en" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28871, 2, 6719},
- {"cvmx_sli_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28872, 2, 6721},
- {"cvmx_sli_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28873, 2, 6723},
- {"cvmx_sli_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28874, 1, 6725},
- {"cvmx_sli_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28875, 2, 6726},
- {"cvmx_sli_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28876, 1, 6728},
- {"cvmx_sli_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28877, 2, 6729},
- {"cvmx_sli_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28878, 2, 6731},
- {"cvmx_sli_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28879, 2, 6733},
- {"cvmx_sli_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28880, 2, 6735},
- {"cvmx_sli_port#_pkind" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28881, 4, 6737},
- {"cvmx_sli_s2m_port#_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28913, 4, 6741},
- {"cvmx_sli_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28915, 1, 6745},
- {"cvmx_sli_scratch_2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28916, 1, 6746},
- {"cvmx_sli_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28917, 4, 6747},
- {"cvmx_sli_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28918, 8, 6751},
- {"cvmx_sli_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28919, 5, 6759},
- {"cvmx_sli_tx_pipe" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28920, 4, 6764},
- {"cvmx_sli_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 28921, 4, 6768},
- {"cvmx_sli_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 28922, 1, 6772},
- {"cvmx_sli_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 28923, 4, 6773},
- {"cvmx_sli_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 28924, 1, 6777},
- {"cvmx_sli_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 28925, 2, 6778},
- {"cvmx_sli_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 28926, 2, 6780},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 28927, 10, 6782},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 28931, 6, 6792},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 28935, 2, 6798},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 28939, 4, 6800},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 28943, 4, 6804},
- {"cvmx_smi_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 28947, 4, 6808},
- {"cvmx_sso_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 28948, 19, 6812},
- {"cvmx_sso_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 28949, 9, 6831},
- {"cvmx_sso_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 28950, 1, 6840},
- {"cvmx_sso_err" , CVMX_CSR_DB_TYPE_NCB, 64, 28951, 19, 6841},
- {"cvmx_sso_err_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 28952, 19, 6860},
- {"cvmx_sso_fidx_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 28953, 3, 6879},
- {"cvmx_sso_fidx_ecc_st" , CVMX_CSR_DB_TYPE_NCB, 64, 28954, 5, 6882},
- {"cvmx_sso_fpage_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 28955, 2, 6887},
- {"cvmx_sso_gwe_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 28956, 5, 6889},
- {"cvmx_sso_idx_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 28957, 3, 6894},
- {"cvmx_sso_idx_ecc_st" , CVMX_CSR_DB_TYPE_NCB, 64, 28958, 5, 6897},
- {"cvmx_sso_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 28959, 2, 6902},
- {"cvmx_sso_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 28967, 2, 6904},
- {"cvmx_sso_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 28968, 2, 6906},
- {"cvmx_sso_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 28969, 2, 6908},
- {"cvmx_sso_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 28970, 2, 6910},
- {"cvmx_sso_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 28978, 2, 6912},
- {"cvmx_sso_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 28979, 2, 6914},
- {"cvmx_sso_oth_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 28980, 5, 6916},
- {"cvmx_sso_oth_ecc_st" , CVMX_CSR_DB_TYPE_NCB, 64, 28981, 9, 6921},
- {"cvmx_sso_pnd_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 28982, 5, 6930},
- {"cvmx_sso_pnd_ecc_st" , CVMX_CSR_DB_TYPE_NCB, 64, 28983, 9, 6935},
- {"cvmx_sso_pp#_grp_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 28984, 1, 6944},
- {"cvmx_sso_pp#_qos_pri" , CVMX_CSR_DB_TYPE_NCB, 64, 29016, 16, 6945},
- {"cvmx_sso_pp_strict" , CVMX_CSR_DB_TYPE_NCB, 64, 29048, 2, 6961},
- {"cvmx_sso_qos#_rnd" , CVMX_CSR_DB_TYPE_NCB, 64, 29049, 2, 6963},
- {"cvmx_sso_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 29057, 6, 6965},
- {"cvmx_sso_qos_we" , CVMX_CSR_DB_TYPE_NCB, 64, 29065, 4, 6971},
- {"cvmx_sso_rwq_head_ptr#" , CVMX_CSR_DB_TYPE_NCB, 64, 29066, 4, 6975},
- {"cvmx_sso_rwq_pop_fptr" , CVMX_CSR_DB_TYPE_NCB, 64, 29074, 4, 6979},
- {"cvmx_sso_rwq_psh_fptr" , CVMX_CSR_DB_TYPE_NCB, 64, 29075, 4, 6983},
- {"cvmx_sso_rwq_tail_ptr#" , CVMX_CSR_DB_TYPE_NCB, 64, 29076, 4, 6987},
- {"cvmx_sso_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 29084, 1, 6991},
- {"cvmx_sso_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 29085, 1, 6992},
- {"cvmx_sso_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 29086, 1, 6993},
- {"cvmx_sso_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 29094, 1, 6994},
- {"cvmx_sso_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 29095, 6, 6995},
- {"cvmx_sso_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 29159, 5, 7001},
- {"cvmx_sso_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 29160, 7, 7006},
- {"cvmx_sso_wq_iq_dis" , CVMX_CSR_DB_TYPE_NCB, 64, 29224, 1, 7013},
- {"cvmx_sso_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 29225, 1, 7014},
- {"cvmx_tim_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 29289, 4, 7015},
- {"cvmx_tim_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 29290, 11, 7019},
- {"cvmx_tim_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 29291, 1, 7030},
- {"cvmx_tim_ecc_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 29292, 3, 7031},
- {"cvmx_tim_fr_rn_tt" , CVMX_CSR_DB_TYPE_RSL, 64, 29293, 2, 7034},
- {"cvmx_tim_int0" , CVMX_CSR_DB_TYPE_RSL, 64, 29294, 1, 7036},
- {"cvmx_tim_int0_en" , CVMX_CSR_DB_TYPE_RSL, 64, 29295, 1, 7037},
- {"cvmx_tim_int0_event" , CVMX_CSR_DB_TYPE_RSL, 64, 29296, 2, 7038},
- {"cvmx_tim_int_eccerr" , CVMX_CSR_DB_TYPE_RSL, 64, 29297, 3, 7040},
- {"cvmx_tim_int_eccerr_en" , CVMX_CSR_DB_TYPE_RSL, 64, 29298, 3, 7043},
- {"cvmx_tim_int_eccerr_event0" , CVMX_CSR_DB_TYPE_RSL, 64, 29299, 3, 7046},
- {"cvmx_tim_int_eccerr_event1" , CVMX_CSR_DB_TYPE_RSL, 64, 29300, 3, 7049},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 29301, 7, 7052},
- {"cvmx_tim_ring#_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 29302, 5, 7059},
- {"cvmx_tim_ring#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 29366, 4, 7064},
- {"cvmx_tim_ring#_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 29430, 4, 7068},
- {"cvmx_tim_ring#_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 29494, 3, 7072},
- {"cvmx_tim_ring#_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 29558, 2, 7075},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 29622, 2, 7077},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 29626, 14, 7079},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 29630, 3, 7093},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 29634, 5, 7096},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 29638, 2, 7101},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 29642, 2, 7103},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 29646, 57, 7105},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 29650, 20, 7162},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 29654, 7, 7182},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 29658, 5, 7189},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 29662, 1, 7194},
- {"cvmx_tra#_read_dat_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 29666, 2, 7195},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 29670, 2, 7197},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 29674, 2, 7199},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 29678, 57, 7201},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 29682, 20, 7258},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 29686, 7, 7278},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 29690, 2, 7285},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 29694, 2, 7287},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 29698, 57, 7289},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 29702, 20, 7346},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 29706, 7, 7366},
- {"cvmx_uahc#_ehci_asynclistaddr", CVMX_CSR_DB_TYPE_NCB, 32, 29710, 2, 7373},
- {"cvmx_uahc#_ehci_configflag" , CVMX_CSR_DB_TYPE_NCB, 32, 29711, 2, 7375},
- {"cvmx_uahc#_ehci_ctrldssegment", CVMX_CSR_DB_TYPE_NCB, 32, 29712, 1, 7377},
- {"cvmx_uahc#_ehci_frindex" , CVMX_CSR_DB_TYPE_NCB, 32, 29713, 2, 7378},
- {"cvmx_uahc#_ehci_hccapbase" , CVMX_CSR_DB_TYPE_NCB, 32, 29714, 3, 7380},
- {"cvmx_uahc#_ehci_hccparams" , CVMX_CSR_DB_TYPE_NCB, 32, 29715, 7, 7383},
- {"cvmx_uahc#_ehci_hcsparams" , CVMX_CSR_DB_TYPE_NCB, 32, 29716, 10, 7390},
- {"cvmx_uahc#_ehci_insnreg00" , CVMX_CSR_DB_TYPE_NCB, 32, 29717, 3, 7400},
- {"cvmx_uahc#_ehci_insnreg03" , CVMX_CSR_DB_TYPE_NCB, 32, 29718, 5, 7403},
- {"cvmx_uahc#_ehci_insnreg04" , CVMX_CSR_DB_TYPE_NCB, 32, 29719, 7, 7408},
- {"cvmx_uahc#_ehci_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 29720, 2, 7415},
- {"cvmx_uahc#_ehci_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 29721, 1, 7417},
- {"cvmx_uahc#_ehci_periodiclistbase", CVMX_CSR_DB_TYPE_NCB, 32, 29722, 2, 7418},
- {"cvmx_uahc#_ehci_portsc#" , CVMX_CSR_DB_TYPE_NCB, 32, 29723, 19, 7420},
- {"cvmx_uahc#_ehci_usbcmd" , CVMX_CSR_DB_TYPE_NCB, 32, 29725, 13, 7439},
- {"cvmx_uahc#_ehci_usbintr" , CVMX_CSR_DB_TYPE_NCB, 32, 29726, 7, 7452},
- {"cvmx_uahc#_ehci_usbsts" , CVMX_CSR_DB_TYPE_NCB, 32, 29727, 12, 7459},
- {"cvmx_uahc#_ohci0_hcbulkcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 29728, 2, 7471},
- {"cvmx_uahc#_ohci0_hcbulkheaded", CVMX_CSR_DB_TYPE_NCB, 32, 29729, 2, 7473},
- {"cvmx_uahc#_ohci0_hccommandstatus", CVMX_CSR_DB_TYPE_NCB, 32, 29730, 7, 7475},
- {"cvmx_uahc#_ohci0_hccontrol" , CVMX_CSR_DB_TYPE_NCB, 32, 29731, 10, 7482},
- {"cvmx_uahc#_ohci0_hccontrolcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 29732, 2, 7492},
- {"cvmx_uahc#_ohci0_hccontrolheaded", CVMX_CSR_DB_TYPE_NCB, 32, 29733, 2, 7494},
- {"cvmx_uahc#_ohci0_hcdonehead" , CVMX_CSR_DB_TYPE_NCB, 32, 29734, 2, 7496},
- {"cvmx_uahc#_ohci0_hcfminterval", CVMX_CSR_DB_TYPE_NCB, 32, 29735, 4, 7498},
- {"cvmx_uahc#_ohci0_hcfmnumber" , CVMX_CSR_DB_TYPE_NCB, 32, 29736, 2, 7502},
- {"cvmx_uahc#_ohci0_hcfmremaining", CVMX_CSR_DB_TYPE_NCB, 32, 29737, 3, 7504},
- {"cvmx_uahc#_ohci0_hchcca" , CVMX_CSR_DB_TYPE_NCB, 32, 29738, 2, 7507},
- {"cvmx_uahc#_ohci0_hcinterruptdisable", CVMX_CSR_DB_TYPE_NCB, 32, 29739, 10, 7509},
- {"cvmx_uahc#_ohci0_hcinterruptenable", CVMX_CSR_DB_TYPE_NCB, 32, 29740, 10, 7519},
- {"cvmx_uahc#_ohci0_hcinterruptstatus", CVMX_CSR_DB_TYPE_NCB, 32, 29741, 10, 7529},
- {"cvmx_uahc#_ohci0_hclsthreshold", CVMX_CSR_DB_TYPE_NCB, 32, 29742, 2, 7539},
- {"cvmx_uahc#_ohci0_hcperiodcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 29743, 2, 7541},
- {"cvmx_uahc#_ohci0_hcperiodicstart", CVMX_CSR_DB_TYPE_NCB, 32, 29744, 2, 7543},
- {"cvmx_uahc#_ohci0_hcrevision" , CVMX_CSR_DB_TYPE_NCB, 32, 29745, 2, 7545},
- {"cvmx_uahc#_ohci0_hcrhdescriptora", CVMX_CSR_DB_TYPE_NCB, 32, 29746, 8, 7547},
- {"cvmx_uahc#_ohci0_hcrhdescriptorb", CVMX_CSR_DB_TYPE_NCB, 32, 29747, 2, 7555},
- {"cvmx_uahc#_ohci0_hcrhportstatus#", CVMX_CSR_DB_TYPE_NCB, 32, 29748, 15, 7557},
- {"cvmx_uahc#_ohci0_hcrhstatus" , CVMX_CSR_DB_TYPE_NCB, 32, 29750, 8, 7572},
- {"cvmx_uahc#_ohci0_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 29751, 2, 7580},
- {"cvmx_uahc#_ohci0_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 29752, 1, 7582},
- {"cvmx_uctl#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 29753, 7, 7583},
- {"cvmx_uctl#_clk_rst_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 29754, 21, 7590},
- {"cvmx_uctl#_ehci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 29755, 12, 7611},
- {"cvmx_uctl#_ehci_fla" , CVMX_CSR_DB_TYPE_RSL, 64, 29756, 2, 7623},
- {"cvmx_uctl#_erto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 29757, 3, 7625},
- {"cvmx_uctl#_if_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 29758, 2, 7628},
- {"cvmx_uctl#_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 29759, 9, 7630},
- {"cvmx_uctl#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 29760, 9, 7639},
- {"cvmx_uctl#_ohci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 29761, 11, 7648},
- {"cvmx_uctl#_orto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 29762, 3, 7659},
- {"cvmx_uctl#_uphy_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 29763, 11, 7662},
- {"cvmx_uctl#_uphy_port#_ctl_status", CVMX_CSR_DB_TYPE_RSL, 64, 29764, 20, 7673},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 29766, 3, 7693},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 29767, 5, 7696},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 29768, 3, 7701},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 29769, 6, 7704},
- {"cvmx_zip_core#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 29770, 2, 7710},
- {"cvmx_zip_ctl_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 29772, 2, 7712},
- {"cvmx_zip_ctl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 29773, 15, 7714},
- {"cvmx_zip_dbg_core#_inst" , CVMX_CSR_DB_TYPE_RSL, 64, 29774, 4, 7729},
- {"cvmx_zip_dbg_core#_sta" , CVMX_CSR_DB_TYPE_RSL, 64, 29776, 4, 7733},
- {"cvmx_zip_dbg_que#_sta" , CVMX_CSR_DB_TYPE_RSL, 64, 29778, 4, 7737},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 29780, 2, 7741},
- {"cvmx_zip_ecc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 29781, 4, 7743},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 29782, 2, 7747},
- {"cvmx_zip_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 29783, 7, 7749},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 29784, 2, 7756},
- {"cvmx_zip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 29785, 7, 7758},
- {"cvmx_zip_que#_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 29786, 5, 7765},
- {"cvmx_zip_que#_ecc_err_sta" , CVMX_CSR_DB_TYPE_RSL, 64, 29788, 3, 7770},
- {"cvmx_zip_que#_map" , CVMX_CSR_DB_TYPE_RSL, 64, 29790, 2, 7773},
- {"cvmx_zip_que_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 29792, 2, 7775},
- {"cvmx_zip_que_pri" , CVMX_CSR_DB_TYPE_RSL, 64, 29793, 2, 7777},
- {"cvmx_zip_throttle" , CVMX_CSR_DB_TYPE_RSL, 64, 29794, 2, 7779},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn68xxp1[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"AGL_GMX_BAD_REG" , 0x11800e0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"AGL_GMX_BIST" , 0x11800e0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"AGL_GMX_PRT0_CFG" , 0x11800e0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_RX0_ADR_CAM0" , 0x11800e0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_RX0_ADR_CAM1" , 0x11800e0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX0_ADR_CAM2" , 0x11800e0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX0_ADR_CAM3" , 0x11800e0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX0_ADR_CAM4" , 0x11800e00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX0_ADR_CAM5" , 0x11800e00001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800e0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX0_ADR_CTL" , 0x11800e0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX0_DECISION" , 0x11800e0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX0_FRM_CHK" , 0x11800e0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX0_FRM_CTL" , 0x11800e0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX0_FRM_MAX" , 0x11800e0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX0_FRM_MIN" , 0x11800e0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX0_IFG" , 0x11800e0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX0_INT_EN" , 0x11800e0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX0_INT_REG" , 0x11800e0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX0_JABBER" , 0x11800e0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800e0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX0_RX_INBND" , 0x11800e0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX0_STATS_CTL" , 0x11800e0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX0_STATS_OCTS" , 0x11800e0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800e0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800e00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800e00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX0_STATS_PKTS" , 0x11800e0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800e00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800e0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800e00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800e00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX0_UDD_SKP" , 0x11800e0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX_BP_DROP0" , 0x11800e0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_OFF0" , 0x11800e0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_ON0" , 0x11800e0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_PRT_INFO" , 0x11800e00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_TX_STATUS" , 0x11800e00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"AGL_GMX_SMAC0" , 0x11800e0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_STAT_BP" , 0x11800e0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_TX0_APPEND" , 0x11800e0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX0_CLK" , 0x11800e0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX0_CTL" , 0x11800e0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX0_MIN_PKT" , 0x11800e0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800e0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800e0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800e0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800e0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800e0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX0_STAT0" , 0x11800e0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX0_STAT1" , 0x11800e0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX0_STAT2" , 0x11800e0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX0_STAT3" , 0x11800e0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX0_STAT4" , 0x11800e00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX0_STAT5" , 0x11800e00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX0_STAT6" , 0x11800e00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX0_STAT7" , 0x11800e00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX0_STAT8" , 0x11800e00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX0_STAT9" , 0x11800e00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX0_STATS_CTL" , 0x11800e0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX0_THRESH" , 0x11800e0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX_BP" , 0x11800e00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"AGL_GMX_TX_COL_ATTEMPT" , 0x11800e0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"AGL_GMX_TX_IFG" , 0x11800e0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"AGL_GMX_TX_INT_EN" , 0x11800e0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"AGL_GMX_TX_INT_REG" , 0x11800e0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"AGL_GMX_TX_JAM" , 0x11800e0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"AGL_GMX_TX_LFSR" , 0x11800e00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"AGL_GMX_TX_OVR_BP" , 0x11800e00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800e00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800e00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"AGL_PRT0_CTL" , 0x11800e0002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"CIU2_ACK_IO0_INT" , 0x10701080c0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU2_ACK_IO1_INT" , 0x10701082c0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU2_ACK_PP0_IP2" , 0x10701000c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP1_IP2" , 0x10701002c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP2_IP2" , 0x10701004c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP3_IP2" , 0x10701006c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP4_IP2" , 0x10701008c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP5_IP2" , 0x1070100ac0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP6_IP2" , 0x1070100cc0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP7_IP2" , 0x1070100ec0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP8_IP2" , 0x10701010c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP9_IP2" , 0x10701012c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP10_IP2" , 0x10701014c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP11_IP2" , 0x10701016c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP12_IP2" , 0x10701018c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP13_IP2" , 0x1070101ac0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP14_IP2" , 0x1070101cc0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP15_IP2" , 0x1070101ec0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP16_IP2" , 0x10701020c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP17_IP2" , 0x10701022c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP18_IP2" , 0x10701024c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP19_IP2" , 0x10701026c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP20_IP2" , 0x10701028c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP21_IP2" , 0x1070102ac0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP22_IP2" , 0x1070102cc0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP23_IP2" , 0x1070102ec0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP24_IP2" , 0x10701030c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP25_IP2" , 0x10701032c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP26_IP2" , 0x10701034c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP27_IP2" , 0x10701036c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP28_IP2" , 0x10701038c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP29_IP2" , 0x1070103ac0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP30_IP2" , 0x1070103cc0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP31_IP2" , 0x1070103ec0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP0_IP3" , 0x10701000c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP1_IP3" , 0x10701002c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP2_IP3" , 0x10701004c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP3_IP3" , 0x10701006c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP4_IP3" , 0x10701008c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP5_IP3" , 0x1070100ac0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP6_IP3" , 0x1070100cc0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP7_IP3" , 0x1070100ec0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP8_IP3" , 0x10701010c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP9_IP3" , 0x10701012c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP10_IP3" , 0x10701014c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP11_IP3" , 0x10701016c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP12_IP3" , 0x10701018c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP13_IP3" , 0x1070101ac0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP14_IP3" , 0x1070101cc0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP15_IP3" , 0x1070101ec0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP16_IP3" , 0x10701020c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP17_IP3" , 0x10701022c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP18_IP3" , 0x10701024c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP19_IP3" , 0x10701026c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP20_IP3" , 0x10701028c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP21_IP3" , 0x1070102ac0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP22_IP3" , 0x1070102cc0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP23_IP3" , 0x1070102ec0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP24_IP3" , 0x10701030c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP25_IP3" , 0x10701032c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP26_IP3" , 0x10701034c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP27_IP3" , 0x10701036c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP28_IP3" , 0x10701038c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP29_IP3" , 0x1070103ac0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP30_IP3" , 0x1070103cc0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP31_IP3" , 0x1070103ec0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP0_IP4" , 0x10701000c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP1_IP4" , 0x10701002c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP2_IP4" , 0x10701004c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP3_IP4" , 0x10701006c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP4_IP4" , 0x10701008c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP5_IP4" , 0x1070100ac0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP6_IP4" , 0x1070100cc0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP7_IP4" , 0x1070100ec0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP8_IP4" , 0x10701010c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP9_IP4" , 0x10701012c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP10_IP4" , 0x10701014c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP11_IP4" , 0x10701016c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP12_IP4" , 0x10701018c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP13_IP4" , 0x1070101ac0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP14_IP4" , 0x1070101cc0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP15_IP4" , 0x1070101ec0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP16_IP4" , 0x10701020c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP17_IP4" , 0x10701022c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP18_IP4" , 0x10701024c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP19_IP4" , 0x10701026c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP20_IP4" , 0x10701028c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP21_IP4" , 0x1070102ac0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP22_IP4" , 0x1070102cc0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP23_IP4" , 0x1070102ec0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP24_IP4" , 0x10701030c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP25_IP4" , 0x10701032c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP26_IP4" , 0x10701034c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP27_IP4" , 0x10701036c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP28_IP4" , 0x10701038c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP29_IP4" , 0x1070103ac0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP30_IP4" , 0x1070103cc0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP31_IP4" , 0x1070103ec0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_EN_IO0_INT_GPIO" , 0x1070108097800ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU2_EN_IO1_INT_GPIO" , 0x1070108297800ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU2_EN_IO0_INT_GPIO_W1C" , 0x10701080b7800ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU2_EN_IO1_INT_GPIO_W1C" , 0x10701082b7800ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU2_EN_IO0_INT_GPIO_W1S" , 0x10701080a7800ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU2_EN_IO1_INT_GPIO_W1S" , 0x10701082a7800ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU2_EN_IO0_INT_IO" , 0x1070108094800ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU2_EN_IO1_INT_IO" , 0x1070108294800ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU2_EN_IO0_INT_IO_W1C" , 0x10701080b4800ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU2_EN_IO1_INT_IO_W1C" , 0x10701082b4800ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU2_EN_IO0_INT_IO_W1S" , 0x10701080a4800ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU2_EN_IO1_INT_IO_W1S" , 0x10701082a4800ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU2_EN_IO0_INT_MBOX" , 0x1070108098800ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU2_EN_IO1_INT_MBOX" , 0x1070108298800ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU2_EN_IO0_INT_MBOX_W1C" , 0x10701080b8800ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU2_EN_IO1_INT_MBOX_W1C" , 0x10701082b8800ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU2_EN_IO0_INT_MBOX_W1S" , 0x10701080a8800ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU2_EN_IO1_INT_MBOX_W1S" , 0x10701082a8800ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU2_EN_IO0_INT_MEM" , 0x1070108095800ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU2_EN_IO1_INT_MEM" , 0x1070108295800ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU2_EN_IO0_INT_MEM_W1C" , 0x10701080b5800ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU2_EN_IO1_INT_MEM_W1C" , 0x10701082b5800ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU2_EN_IO0_INT_MEM_W1S" , 0x10701080a5800ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU2_EN_IO1_INT_MEM_W1S" , 0x10701082a5800ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU2_EN_IO0_INT_MIO" , 0x1070108093800ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU2_EN_IO1_INT_MIO" , 0x1070108293800ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU2_EN_IO0_INT_MIO_W1C" , 0x10701080b3800ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU2_EN_IO1_INT_MIO_W1C" , 0x10701082b3800ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU2_EN_IO0_INT_MIO_W1S" , 0x10701080a3800ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU2_EN_IO1_INT_MIO_W1S" , 0x10701082a3800ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU2_EN_IO0_INT_PKT" , 0x1070108096800ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU2_EN_IO1_INT_PKT" , 0x1070108296800ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU2_EN_IO0_INT_PKT_W1C" , 0x10701080b6800ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU2_EN_IO1_INT_PKT_W1C" , 0x10701082b6800ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU2_EN_IO0_INT_PKT_W1S" , 0x10701080a6800ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU2_EN_IO1_INT_PKT_W1S" , 0x10701082a6800ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU2_EN_IO0_INT_RML" , 0x1070108092800ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU2_EN_IO1_INT_RML" , 0x1070108292800ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU2_EN_IO0_INT_RML_W1C" , 0x10701080b2800ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU2_EN_IO1_INT_RML_W1C" , 0x10701082b2800ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU2_EN_IO0_INT_RML_W1S" , 0x10701080a2800ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU2_EN_IO1_INT_RML_W1S" , 0x10701082a2800ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU2_EN_IO0_INT_WDOG" , 0x1070108091800ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU2_EN_IO1_INT_WDOG" , 0x1070108291800ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU2_EN_IO0_INT_WDOG_W1C" , 0x10701080b1800ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU2_EN_IO1_INT_WDOG_W1C" , 0x10701082b1800ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU2_EN_IO0_INT_WDOG_W1S" , 0x10701080a1800ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU2_EN_IO1_INT_WDOG_W1S" , 0x10701082a1800ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU2_EN_IO0_INT_WRKQ" , 0x1070108090800ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU2_EN_IO1_INT_WRKQ" , 0x1070108290800ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU2_EN_IO0_INT_WRKQ_W1C" , 0x10701080b0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU2_EN_IO1_INT_WRKQ_W1C" , 0x10701082b0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU2_EN_IO0_INT_WRKQ_W1S" , 0x10701080a0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU2_EN_IO1_INT_WRKQ_W1S" , 0x10701082a0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU2_EN_PP0_IP2_GPIO" , 0x1070100097000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP1_IP2_GPIO" , 0x1070100297000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP2_IP2_GPIO" , 0x1070100497000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP3_IP2_GPIO" , 0x1070100697000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP4_IP2_GPIO" , 0x1070100897000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP5_IP2_GPIO" , 0x1070100a97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP6_IP2_GPIO" , 0x1070100c97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP7_IP2_GPIO" , 0x1070100e97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP8_IP2_GPIO" , 0x1070101097000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP9_IP2_GPIO" , 0x1070101297000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP10_IP2_GPIO" , 0x1070101497000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP11_IP2_GPIO" , 0x1070101697000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP12_IP2_GPIO" , 0x1070101897000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP13_IP2_GPIO" , 0x1070101a97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP14_IP2_GPIO" , 0x1070101c97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP15_IP2_GPIO" , 0x1070101e97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP16_IP2_GPIO" , 0x1070102097000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP17_IP2_GPIO" , 0x1070102297000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP18_IP2_GPIO" , 0x1070102497000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP19_IP2_GPIO" , 0x1070102697000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP20_IP2_GPIO" , 0x1070102897000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP21_IP2_GPIO" , 0x1070102a97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP22_IP2_GPIO" , 0x1070102c97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP23_IP2_GPIO" , 0x1070102e97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP24_IP2_GPIO" , 0x1070103097000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP25_IP2_GPIO" , 0x1070103297000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP26_IP2_GPIO" , 0x1070103497000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP27_IP2_GPIO" , 0x1070103697000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP28_IP2_GPIO" , 0x1070103897000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP29_IP2_GPIO" , 0x1070103a97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP30_IP2_GPIO" , 0x1070103c97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP31_IP2_GPIO" , 0x1070103e97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP0_IP2_GPIO_W1C" , 0x10701000b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP1_IP2_GPIO_W1C" , 0x10701002b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP2_IP2_GPIO_W1C" , 0x10701004b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP3_IP2_GPIO_W1C" , 0x10701006b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP4_IP2_GPIO_W1C" , 0x10701008b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP5_IP2_GPIO_W1C" , 0x1070100ab7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP6_IP2_GPIO_W1C" , 0x1070100cb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP7_IP2_GPIO_W1C" , 0x1070100eb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP8_IP2_GPIO_W1C" , 0x10701010b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP9_IP2_GPIO_W1C" , 0x10701012b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP10_IP2_GPIO_W1C" , 0x10701014b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP11_IP2_GPIO_W1C" , 0x10701016b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP12_IP2_GPIO_W1C" , 0x10701018b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP13_IP2_GPIO_W1C" , 0x1070101ab7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP14_IP2_GPIO_W1C" , 0x1070101cb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP15_IP2_GPIO_W1C" , 0x1070101eb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP16_IP2_GPIO_W1C" , 0x10701020b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP17_IP2_GPIO_W1C" , 0x10701022b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP18_IP2_GPIO_W1C" , 0x10701024b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP19_IP2_GPIO_W1C" , 0x10701026b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP20_IP2_GPIO_W1C" , 0x10701028b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP21_IP2_GPIO_W1C" , 0x1070102ab7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP22_IP2_GPIO_W1C" , 0x1070102cb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP23_IP2_GPIO_W1C" , 0x1070102eb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP24_IP2_GPIO_W1C" , 0x10701030b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP25_IP2_GPIO_W1C" , 0x10701032b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP26_IP2_GPIO_W1C" , 0x10701034b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP27_IP2_GPIO_W1C" , 0x10701036b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP28_IP2_GPIO_W1C" , 0x10701038b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP29_IP2_GPIO_W1C" , 0x1070103ab7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP30_IP2_GPIO_W1C" , 0x1070103cb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP31_IP2_GPIO_W1C" , 0x1070103eb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP0_IP2_GPIO_W1S" , 0x10701000a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP1_IP2_GPIO_W1S" , 0x10701002a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP2_IP2_GPIO_W1S" , 0x10701004a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP3_IP2_GPIO_W1S" , 0x10701006a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP4_IP2_GPIO_W1S" , 0x10701008a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP5_IP2_GPIO_W1S" , 0x1070100aa7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP6_IP2_GPIO_W1S" , 0x1070100ca7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP7_IP2_GPIO_W1S" , 0x1070100ea7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP8_IP2_GPIO_W1S" , 0x10701010a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP9_IP2_GPIO_W1S" , 0x10701012a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP10_IP2_GPIO_W1S" , 0x10701014a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP11_IP2_GPIO_W1S" , 0x10701016a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP12_IP2_GPIO_W1S" , 0x10701018a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP13_IP2_GPIO_W1S" , 0x1070101aa7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP14_IP2_GPIO_W1S" , 0x1070101ca7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP15_IP2_GPIO_W1S" , 0x1070101ea7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP16_IP2_GPIO_W1S" , 0x10701020a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP17_IP2_GPIO_W1S" , 0x10701022a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP18_IP2_GPIO_W1S" , 0x10701024a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP19_IP2_GPIO_W1S" , 0x10701026a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP20_IP2_GPIO_W1S" , 0x10701028a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP21_IP2_GPIO_W1S" , 0x1070102aa7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP22_IP2_GPIO_W1S" , 0x1070102ca7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP23_IP2_GPIO_W1S" , 0x1070102ea7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP24_IP2_GPIO_W1S" , 0x10701030a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP25_IP2_GPIO_W1S" , 0x10701032a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP26_IP2_GPIO_W1S" , 0x10701034a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP27_IP2_GPIO_W1S" , 0x10701036a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP28_IP2_GPIO_W1S" , 0x10701038a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP29_IP2_GPIO_W1S" , 0x1070103aa7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP30_IP2_GPIO_W1S" , 0x1070103ca7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP31_IP2_GPIO_W1S" , 0x1070103ea7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP0_IP2_IO" , 0x1070100094000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP1_IP2_IO" , 0x1070100294000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP2_IP2_IO" , 0x1070100494000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP3_IP2_IO" , 0x1070100694000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP4_IP2_IO" , 0x1070100894000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP5_IP2_IO" , 0x1070100a94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP6_IP2_IO" , 0x1070100c94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP7_IP2_IO" , 0x1070100e94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP8_IP2_IO" , 0x1070101094000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP9_IP2_IO" , 0x1070101294000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP10_IP2_IO" , 0x1070101494000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP11_IP2_IO" , 0x1070101694000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP12_IP2_IO" , 0x1070101894000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP13_IP2_IO" , 0x1070101a94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP14_IP2_IO" , 0x1070101c94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP15_IP2_IO" , 0x1070101e94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP16_IP2_IO" , 0x1070102094000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP17_IP2_IO" , 0x1070102294000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP18_IP2_IO" , 0x1070102494000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP19_IP2_IO" , 0x1070102694000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP20_IP2_IO" , 0x1070102894000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP21_IP2_IO" , 0x1070102a94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP22_IP2_IO" , 0x1070102c94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP23_IP2_IO" , 0x1070102e94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP24_IP2_IO" , 0x1070103094000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP25_IP2_IO" , 0x1070103294000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP26_IP2_IO" , 0x1070103494000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP27_IP2_IO" , 0x1070103694000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP28_IP2_IO" , 0x1070103894000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP29_IP2_IO" , 0x1070103a94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP30_IP2_IO" , 0x1070103c94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP31_IP2_IO" , 0x1070103e94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP0_IP2_IO_W1C" , 0x10701000b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP1_IP2_IO_W1C" , 0x10701002b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP2_IP2_IO_W1C" , 0x10701004b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP3_IP2_IO_W1C" , 0x10701006b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP4_IP2_IO_W1C" , 0x10701008b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP5_IP2_IO_W1C" , 0x1070100ab4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP6_IP2_IO_W1C" , 0x1070100cb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP7_IP2_IO_W1C" , 0x1070100eb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP8_IP2_IO_W1C" , 0x10701010b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP9_IP2_IO_W1C" , 0x10701012b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP10_IP2_IO_W1C" , 0x10701014b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP11_IP2_IO_W1C" , 0x10701016b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP12_IP2_IO_W1C" , 0x10701018b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP13_IP2_IO_W1C" , 0x1070101ab4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP14_IP2_IO_W1C" , 0x1070101cb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP15_IP2_IO_W1C" , 0x1070101eb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP16_IP2_IO_W1C" , 0x10701020b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP17_IP2_IO_W1C" , 0x10701022b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP18_IP2_IO_W1C" , 0x10701024b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP19_IP2_IO_W1C" , 0x10701026b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP20_IP2_IO_W1C" , 0x10701028b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP21_IP2_IO_W1C" , 0x1070102ab4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP22_IP2_IO_W1C" , 0x1070102cb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP23_IP2_IO_W1C" , 0x1070102eb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP24_IP2_IO_W1C" , 0x10701030b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP25_IP2_IO_W1C" , 0x10701032b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP26_IP2_IO_W1C" , 0x10701034b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP27_IP2_IO_W1C" , 0x10701036b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP28_IP2_IO_W1C" , 0x10701038b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP29_IP2_IO_W1C" , 0x1070103ab4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP30_IP2_IO_W1C" , 0x1070103cb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP31_IP2_IO_W1C" , 0x1070103eb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP0_IP2_IO_W1S" , 0x10701000a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP1_IP2_IO_W1S" , 0x10701002a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP2_IP2_IO_W1S" , 0x10701004a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP3_IP2_IO_W1S" , 0x10701006a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP4_IP2_IO_W1S" , 0x10701008a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP5_IP2_IO_W1S" , 0x1070100aa4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP6_IP2_IO_W1S" , 0x1070100ca4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP7_IP2_IO_W1S" , 0x1070100ea4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP8_IP2_IO_W1S" , 0x10701010a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP9_IP2_IO_W1S" , 0x10701012a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP10_IP2_IO_W1S" , 0x10701014a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP11_IP2_IO_W1S" , 0x10701016a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP12_IP2_IO_W1S" , 0x10701018a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP13_IP2_IO_W1S" , 0x1070101aa4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP14_IP2_IO_W1S" , 0x1070101ca4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP15_IP2_IO_W1S" , 0x1070101ea4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP16_IP2_IO_W1S" , 0x10701020a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP17_IP2_IO_W1S" , 0x10701022a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP18_IP2_IO_W1S" , 0x10701024a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP19_IP2_IO_W1S" , 0x10701026a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP20_IP2_IO_W1S" , 0x10701028a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP21_IP2_IO_W1S" , 0x1070102aa4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP22_IP2_IO_W1S" , 0x1070102ca4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP23_IP2_IO_W1S" , 0x1070102ea4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP24_IP2_IO_W1S" , 0x10701030a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP25_IP2_IO_W1S" , 0x10701032a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP26_IP2_IO_W1S" , 0x10701034a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP27_IP2_IO_W1S" , 0x10701036a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP28_IP2_IO_W1S" , 0x10701038a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP29_IP2_IO_W1S" , 0x1070103aa4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP30_IP2_IO_W1S" , 0x1070103ca4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP31_IP2_IO_W1S" , 0x1070103ea4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP0_IP2_MBOX" , 0x1070100098000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP1_IP2_MBOX" , 0x1070100298000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP2_IP2_MBOX" , 0x1070100498000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP3_IP2_MBOX" , 0x1070100698000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP4_IP2_MBOX" , 0x1070100898000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP5_IP2_MBOX" , 0x1070100a98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP6_IP2_MBOX" , 0x1070100c98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP7_IP2_MBOX" , 0x1070100e98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP8_IP2_MBOX" , 0x1070101098000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP9_IP2_MBOX" , 0x1070101298000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP10_IP2_MBOX" , 0x1070101498000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP11_IP2_MBOX" , 0x1070101698000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP12_IP2_MBOX" , 0x1070101898000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP13_IP2_MBOX" , 0x1070101a98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP14_IP2_MBOX" , 0x1070101c98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP15_IP2_MBOX" , 0x1070101e98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP16_IP2_MBOX" , 0x1070102098000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP17_IP2_MBOX" , 0x1070102298000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP18_IP2_MBOX" , 0x1070102498000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP19_IP2_MBOX" , 0x1070102698000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP20_IP2_MBOX" , 0x1070102898000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP21_IP2_MBOX" , 0x1070102a98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP22_IP2_MBOX" , 0x1070102c98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP23_IP2_MBOX" , 0x1070102e98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP24_IP2_MBOX" , 0x1070103098000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP25_IP2_MBOX" , 0x1070103298000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP26_IP2_MBOX" , 0x1070103498000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP27_IP2_MBOX" , 0x1070103698000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP28_IP2_MBOX" , 0x1070103898000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP29_IP2_MBOX" , 0x1070103a98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP30_IP2_MBOX" , 0x1070103c98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP31_IP2_MBOX" , 0x1070103e98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP0_IP2_MBOX_W1C" , 0x10701000b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP1_IP2_MBOX_W1C" , 0x10701002b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP2_IP2_MBOX_W1C" , 0x10701004b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP3_IP2_MBOX_W1C" , 0x10701006b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP4_IP2_MBOX_W1C" , 0x10701008b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP5_IP2_MBOX_W1C" , 0x1070100ab8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP6_IP2_MBOX_W1C" , 0x1070100cb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP7_IP2_MBOX_W1C" , 0x1070100eb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP8_IP2_MBOX_W1C" , 0x10701010b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP9_IP2_MBOX_W1C" , 0x10701012b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP10_IP2_MBOX_W1C" , 0x10701014b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP11_IP2_MBOX_W1C" , 0x10701016b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP12_IP2_MBOX_W1C" , 0x10701018b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP13_IP2_MBOX_W1C" , 0x1070101ab8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP14_IP2_MBOX_W1C" , 0x1070101cb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP15_IP2_MBOX_W1C" , 0x1070101eb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP16_IP2_MBOX_W1C" , 0x10701020b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP17_IP2_MBOX_W1C" , 0x10701022b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP18_IP2_MBOX_W1C" , 0x10701024b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP19_IP2_MBOX_W1C" , 0x10701026b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP20_IP2_MBOX_W1C" , 0x10701028b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP21_IP2_MBOX_W1C" , 0x1070102ab8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP22_IP2_MBOX_W1C" , 0x1070102cb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP23_IP2_MBOX_W1C" , 0x1070102eb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP24_IP2_MBOX_W1C" , 0x10701030b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP25_IP2_MBOX_W1C" , 0x10701032b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP26_IP2_MBOX_W1C" , 0x10701034b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP27_IP2_MBOX_W1C" , 0x10701036b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP28_IP2_MBOX_W1C" , 0x10701038b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP29_IP2_MBOX_W1C" , 0x1070103ab8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP30_IP2_MBOX_W1C" , 0x1070103cb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP31_IP2_MBOX_W1C" , 0x1070103eb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP0_IP2_MBOX_W1S" , 0x10701000a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP1_IP2_MBOX_W1S" , 0x10701002a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP2_IP2_MBOX_W1S" , 0x10701004a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP3_IP2_MBOX_W1S" , 0x10701006a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP4_IP2_MBOX_W1S" , 0x10701008a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP5_IP2_MBOX_W1S" , 0x1070100aa8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP6_IP2_MBOX_W1S" , 0x1070100ca8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP7_IP2_MBOX_W1S" , 0x1070100ea8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP8_IP2_MBOX_W1S" , 0x10701010a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP9_IP2_MBOX_W1S" , 0x10701012a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP10_IP2_MBOX_W1S" , 0x10701014a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP11_IP2_MBOX_W1S" , 0x10701016a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP12_IP2_MBOX_W1S" , 0x10701018a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP13_IP2_MBOX_W1S" , 0x1070101aa8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP14_IP2_MBOX_W1S" , 0x1070101ca8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP15_IP2_MBOX_W1S" , 0x1070101ea8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP16_IP2_MBOX_W1S" , 0x10701020a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP17_IP2_MBOX_W1S" , 0x10701022a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP18_IP2_MBOX_W1S" , 0x10701024a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP19_IP2_MBOX_W1S" , 0x10701026a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP20_IP2_MBOX_W1S" , 0x10701028a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP21_IP2_MBOX_W1S" , 0x1070102aa8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP22_IP2_MBOX_W1S" , 0x1070102ca8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP23_IP2_MBOX_W1S" , 0x1070102ea8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP24_IP2_MBOX_W1S" , 0x10701030a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP25_IP2_MBOX_W1S" , 0x10701032a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP26_IP2_MBOX_W1S" , 0x10701034a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP27_IP2_MBOX_W1S" , 0x10701036a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP28_IP2_MBOX_W1S" , 0x10701038a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP29_IP2_MBOX_W1S" , 0x1070103aa8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP30_IP2_MBOX_W1S" , 0x1070103ca8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP31_IP2_MBOX_W1S" , 0x1070103ea8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP0_IP2_MEM" , 0x1070100095000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP1_IP2_MEM" , 0x1070100295000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP2_IP2_MEM" , 0x1070100495000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP3_IP2_MEM" , 0x1070100695000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP4_IP2_MEM" , 0x1070100895000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP5_IP2_MEM" , 0x1070100a95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP6_IP2_MEM" , 0x1070100c95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP7_IP2_MEM" , 0x1070100e95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP8_IP2_MEM" , 0x1070101095000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP9_IP2_MEM" , 0x1070101295000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP10_IP2_MEM" , 0x1070101495000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP11_IP2_MEM" , 0x1070101695000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP12_IP2_MEM" , 0x1070101895000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP13_IP2_MEM" , 0x1070101a95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP14_IP2_MEM" , 0x1070101c95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP15_IP2_MEM" , 0x1070101e95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP16_IP2_MEM" , 0x1070102095000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP17_IP2_MEM" , 0x1070102295000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP18_IP2_MEM" , 0x1070102495000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP19_IP2_MEM" , 0x1070102695000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP20_IP2_MEM" , 0x1070102895000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP21_IP2_MEM" , 0x1070102a95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP22_IP2_MEM" , 0x1070102c95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP23_IP2_MEM" , 0x1070102e95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP24_IP2_MEM" , 0x1070103095000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP25_IP2_MEM" , 0x1070103295000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP26_IP2_MEM" , 0x1070103495000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP27_IP2_MEM" , 0x1070103695000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP28_IP2_MEM" , 0x1070103895000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP29_IP2_MEM" , 0x1070103a95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP30_IP2_MEM" , 0x1070103c95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP31_IP2_MEM" , 0x1070103e95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP0_IP2_MEM_W1C" , 0x10701000b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP1_IP2_MEM_W1C" , 0x10701002b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP2_IP2_MEM_W1C" , 0x10701004b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP3_IP2_MEM_W1C" , 0x10701006b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP4_IP2_MEM_W1C" , 0x10701008b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP5_IP2_MEM_W1C" , 0x1070100ab5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP6_IP2_MEM_W1C" , 0x1070100cb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP7_IP2_MEM_W1C" , 0x1070100eb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP8_IP2_MEM_W1C" , 0x10701010b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP9_IP2_MEM_W1C" , 0x10701012b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP10_IP2_MEM_W1C" , 0x10701014b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP11_IP2_MEM_W1C" , 0x10701016b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP12_IP2_MEM_W1C" , 0x10701018b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP13_IP2_MEM_W1C" , 0x1070101ab5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP14_IP2_MEM_W1C" , 0x1070101cb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP15_IP2_MEM_W1C" , 0x1070101eb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP16_IP2_MEM_W1C" , 0x10701020b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP17_IP2_MEM_W1C" , 0x10701022b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP18_IP2_MEM_W1C" , 0x10701024b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP19_IP2_MEM_W1C" , 0x10701026b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP20_IP2_MEM_W1C" , 0x10701028b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP21_IP2_MEM_W1C" , 0x1070102ab5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP22_IP2_MEM_W1C" , 0x1070102cb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP23_IP2_MEM_W1C" , 0x1070102eb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP24_IP2_MEM_W1C" , 0x10701030b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP25_IP2_MEM_W1C" , 0x10701032b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP26_IP2_MEM_W1C" , 0x10701034b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP27_IP2_MEM_W1C" , 0x10701036b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP28_IP2_MEM_W1C" , 0x10701038b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP29_IP2_MEM_W1C" , 0x1070103ab5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP30_IP2_MEM_W1C" , 0x1070103cb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP31_IP2_MEM_W1C" , 0x1070103eb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP0_IP2_MEM_W1S" , 0x10701000a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP1_IP2_MEM_W1S" , 0x10701002a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP2_IP2_MEM_W1S" , 0x10701004a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP3_IP2_MEM_W1S" , 0x10701006a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP4_IP2_MEM_W1S" , 0x10701008a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP5_IP2_MEM_W1S" , 0x1070100aa5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP6_IP2_MEM_W1S" , 0x1070100ca5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP7_IP2_MEM_W1S" , 0x1070100ea5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP8_IP2_MEM_W1S" , 0x10701010a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP9_IP2_MEM_W1S" , 0x10701012a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP10_IP2_MEM_W1S" , 0x10701014a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP11_IP2_MEM_W1S" , 0x10701016a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP12_IP2_MEM_W1S" , 0x10701018a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP13_IP2_MEM_W1S" , 0x1070101aa5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP14_IP2_MEM_W1S" , 0x1070101ca5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP15_IP2_MEM_W1S" , 0x1070101ea5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP16_IP2_MEM_W1S" , 0x10701020a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP17_IP2_MEM_W1S" , 0x10701022a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP18_IP2_MEM_W1S" , 0x10701024a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP19_IP2_MEM_W1S" , 0x10701026a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP20_IP2_MEM_W1S" , 0x10701028a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP21_IP2_MEM_W1S" , 0x1070102aa5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP22_IP2_MEM_W1S" , 0x1070102ca5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP23_IP2_MEM_W1S" , 0x1070102ea5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP24_IP2_MEM_W1S" , 0x10701030a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP25_IP2_MEM_W1S" , 0x10701032a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP26_IP2_MEM_W1S" , 0x10701034a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP27_IP2_MEM_W1S" , 0x10701036a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP28_IP2_MEM_W1S" , 0x10701038a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP29_IP2_MEM_W1S" , 0x1070103aa5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP30_IP2_MEM_W1S" , 0x1070103ca5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP31_IP2_MEM_W1S" , 0x1070103ea5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP0_IP2_MIO" , 0x1070100093000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP1_IP2_MIO" , 0x1070100293000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP2_IP2_MIO" , 0x1070100493000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP3_IP2_MIO" , 0x1070100693000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP4_IP2_MIO" , 0x1070100893000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP5_IP2_MIO" , 0x1070100a93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP6_IP2_MIO" , 0x1070100c93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP7_IP2_MIO" , 0x1070100e93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP8_IP2_MIO" , 0x1070101093000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP9_IP2_MIO" , 0x1070101293000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP10_IP2_MIO" , 0x1070101493000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP11_IP2_MIO" , 0x1070101693000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP12_IP2_MIO" , 0x1070101893000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP13_IP2_MIO" , 0x1070101a93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP14_IP2_MIO" , 0x1070101c93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP15_IP2_MIO" , 0x1070101e93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP16_IP2_MIO" , 0x1070102093000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP17_IP2_MIO" , 0x1070102293000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP18_IP2_MIO" , 0x1070102493000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP19_IP2_MIO" , 0x1070102693000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP20_IP2_MIO" , 0x1070102893000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP21_IP2_MIO" , 0x1070102a93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP22_IP2_MIO" , 0x1070102c93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP23_IP2_MIO" , 0x1070102e93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP24_IP2_MIO" , 0x1070103093000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP25_IP2_MIO" , 0x1070103293000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP26_IP2_MIO" , 0x1070103493000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP27_IP2_MIO" , 0x1070103693000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP28_IP2_MIO" , 0x1070103893000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP29_IP2_MIO" , 0x1070103a93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP30_IP2_MIO" , 0x1070103c93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP31_IP2_MIO" , 0x1070103e93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP0_IP2_MIO_W1C" , 0x10701000b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP1_IP2_MIO_W1C" , 0x10701002b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP2_IP2_MIO_W1C" , 0x10701004b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP3_IP2_MIO_W1C" , 0x10701006b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP4_IP2_MIO_W1C" , 0x10701008b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP5_IP2_MIO_W1C" , 0x1070100ab3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP6_IP2_MIO_W1C" , 0x1070100cb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP7_IP2_MIO_W1C" , 0x1070100eb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP8_IP2_MIO_W1C" , 0x10701010b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP9_IP2_MIO_W1C" , 0x10701012b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP10_IP2_MIO_W1C" , 0x10701014b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP11_IP2_MIO_W1C" , 0x10701016b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP12_IP2_MIO_W1C" , 0x10701018b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP13_IP2_MIO_W1C" , 0x1070101ab3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP14_IP2_MIO_W1C" , 0x1070101cb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP15_IP2_MIO_W1C" , 0x1070101eb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP16_IP2_MIO_W1C" , 0x10701020b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP17_IP2_MIO_W1C" , 0x10701022b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP18_IP2_MIO_W1C" , 0x10701024b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP19_IP2_MIO_W1C" , 0x10701026b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP20_IP2_MIO_W1C" , 0x10701028b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP21_IP2_MIO_W1C" , 0x1070102ab3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP22_IP2_MIO_W1C" , 0x1070102cb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP23_IP2_MIO_W1C" , 0x1070102eb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP24_IP2_MIO_W1C" , 0x10701030b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP25_IP2_MIO_W1C" , 0x10701032b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP26_IP2_MIO_W1C" , 0x10701034b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP27_IP2_MIO_W1C" , 0x10701036b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP28_IP2_MIO_W1C" , 0x10701038b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP29_IP2_MIO_W1C" , 0x1070103ab3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP30_IP2_MIO_W1C" , 0x1070103cb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP31_IP2_MIO_W1C" , 0x1070103eb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP0_IP2_MIO_W1S" , 0x10701000a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP1_IP2_MIO_W1S" , 0x10701002a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP2_IP2_MIO_W1S" , 0x10701004a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP3_IP2_MIO_W1S" , 0x10701006a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP4_IP2_MIO_W1S" , 0x10701008a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP5_IP2_MIO_W1S" , 0x1070100aa3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP6_IP2_MIO_W1S" , 0x1070100ca3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP7_IP2_MIO_W1S" , 0x1070100ea3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP8_IP2_MIO_W1S" , 0x10701010a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP9_IP2_MIO_W1S" , 0x10701012a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP10_IP2_MIO_W1S" , 0x10701014a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP11_IP2_MIO_W1S" , 0x10701016a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP12_IP2_MIO_W1S" , 0x10701018a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP13_IP2_MIO_W1S" , 0x1070101aa3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP14_IP2_MIO_W1S" , 0x1070101ca3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP15_IP2_MIO_W1S" , 0x1070101ea3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP16_IP2_MIO_W1S" , 0x10701020a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP17_IP2_MIO_W1S" , 0x10701022a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP18_IP2_MIO_W1S" , 0x10701024a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP19_IP2_MIO_W1S" , 0x10701026a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP20_IP2_MIO_W1S" , 0x10701028a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP21_IP2_MIO_W1S" , 0x1070102aa3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP22_IP2_MIO_W1S" , 0x1070102ca3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP23_IP2_MIO_W1S" , 0x1070102ea3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP24_IP2_MIO_W1S" , 0x10701030a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP25_IP2_MIO_W1S" , 0x10701032a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP26_IP2_MIO_W1S" , 0x10701034a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP27_IP2_MIO_W1S" , 0x10701036a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP28_IP2_MIO_W1S" , 0x10701038a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP29_IP2_MIO_W1S" , 0x1070103aa3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP30_IP2_MIO_W1S" , 0x1070103ca3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP31_IP2_MIO_W1S" , 0x1070103ea3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP0_IP2_PKT" , 0x1070100096000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP1_IP2_PKT" , 0x1070100296000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP2_IP2_PKT" , 0x1070100496000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP3_IP2_PKT" , 0x1070100696000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP4_IP2_PKT" , 0x1070100896000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP5_IP2_PKT" , 0x1070100a96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP6_IP2_PKT" , 0x1070100c96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP7_IP2_PKT" , 0x1070100e96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP8_IP2_PKT" , 0x1070101096000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP9_IP2_PKT" , 0x1070101296000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP10_IP2_PKT" , 0x1070101496000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP11_IP2_PKT" , 0x1070101696000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP12_IP2_PKT" , 0x1070101896000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP13_IP2_PKT" , 0x1070101a96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP14_IP2_PKT" , 0x1070101c96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP15_IP2_PKT" , 0x1070101e96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP16_IP2_PKT" , 0x1070102096000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP17_IP2_PKT" , 0x1070102296000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP18_IP2_PKT" , 0x1070102496000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP19_IP2_PKT" , 0x1070102696000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP20_IP2_PKT" , 0x1070102896000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP21_IP2_PKT" , 0x1070102a96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP22_IP2_PKT" , 0x1070102c96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP23_IP2_PKT" , 0x1070102e96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP24_IP2_PKT" , 0x1070103096000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP25_IP2_PKT" , 0x1070103296000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP26_IP2_PKT" , 0x1070103496000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP27_IP2_PKT" , 0x1070103696000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP28_IP2_PKT" , 0x1070103896000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP29_IP2_PKT" , 0x1070103a96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP30_IP2_PKT" , 0x1070103c96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP31_IP2_PKT" , 0x1070103e96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP0_IP2_PKT_W1C" , 0x10701000b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP1_IP2_PKT_W1C" , 0x10701002b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP2_IP2_PKT_W1C" , 0x10701004b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP3_IP2_PKT_W1C" , 0x10701006b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP4_IP2_PKT_W1C" , 0x10701008b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP5_IP2_PKT_W1C" , 0x1070100ab6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP6_IP2_PKT_W1C" , 0x1070100cb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP7_IP2_PKT_W1C" , 0x1070100eb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP8_IP2_PKT_W1C" , 0x10701010b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP9_IP2_PKT_W1C" , 0x10701012b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP10_IP2_PKT_W1C" , 0x10701014b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP11_IP2_PKT_W1C" , 0x10701016b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP12_IP2_PKT_W1C" , 0x10701018b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP13_IP2_PKT_W1C" , 0x1070101ab6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP14_IP2_PKT_W1C" , 0x1070101cb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP15_IP2_PKT_W1C" , 0x1070101eb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP16_IP2_PKT_W1C" , 0x10701020b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP17_IP2_PKT_W1C" , 0x10701022b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP18_IP2_PKT_W1C" , 0x10701024b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP19_IP2_PKT_W1C" , 0x10701026b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP20_IP2_PKT_W1C" , 0x10701028b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP21_IP2_PKT_W1C" , 0x1070102ab6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP22_IP2_PKT_W1C" , 0x1070102cb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP23_IP2_PKT_W1C" , 0x1070102eb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP24_IP2_PKT_W1C" , 0x10701030b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP25_IP2_PKT_W1C" , 0x10701032b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP26_IP2_PKT_W1C" , 0x10701034b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP27_IP2_PKT_W1C" , 0x10701036b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP28_IP2_PKT_W1C" , 0x10701038b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP29_IP2_PKT_W1C" , 0x1070103ab6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP30_IP2_PKT_W1C" , 0x1070103cb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP31_IP2_PKT_W1C" , 0x1070103eb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP0_IP2_PKT_W1S" , 0x10701000a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP1_IP2_PKT_W1S" , 0x10701002a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP2_IP2_PKT_W1S" , 0x10701004a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP3_IP2_PKT_W1S" , 0x10701006a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP4_IP2_PKT_W1S" , 0x10701008a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP5_IP2_PKT_W1S" , 0x1070100aa6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP6_IP2_PKT_W1S" , 0x1070100ca6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP7_IP2_PKT_W1S" , 0x1070100ea6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP8_IP2_PKT_W1S" , 0x10701010a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP9_IP2_PKT_W1S" , 0x10701012a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP10_IP2_PKT_W1S" , 0x10701014a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP11_IP2_PKT_W1S" , 0x10701016a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP12_IP2_PKT_W1S" , 0x10701018a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP13_IP2_PKT_W1S" , 0x1070101aa6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP14_IP2_PKT_W1S" , 0x1070101ca6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP15_IP2_PKT_W1S" , 0x1070101ea6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP16_IP2_PKT_W1S" , 0x10701020a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP17_IP2_PKT_W1S" , 0x10701022a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP18_IP2_PKT_W1S" , 0x10701024a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP19_IP2_PKT_W1S" , 0x10701026a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP20_IP2_PKT_W1S" , 0x10701028a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP21_IP2_PKT_W1S" , 0x1070102aa6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP22_IP2_PKT_W1S" , 0x1070102ca6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP23_IP2_PKT_W1S" , 0x1070102ea6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP24_IP2_PKT_W1S" , 0x10701030a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP25_IP2_PKT_W1S" , 0x10701032a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP26_IP2_PKT_W1S" , 0x10701034a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP27_IP2_PKT_W1S" , 0x10701036a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP28_IP2_PKT_W1S" , 0x10701038a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP29_IP2_PKT_W1S" , 0x1070103aa6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP30_IP2_PKT_W1S" , 0x1070103ca6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP31_IP2_PKT_W1S" , 0x1070103ea6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP0_IP2_RML" , 0x1070100092000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP1_IP2_RML" , 0x1070100292000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP2_IP2_RML" , 0x1070100492000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP3_IP2_RML" , 0x1070100692000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP4_IP2_RML" , 0x1070100892000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP5_IP2_RML" , 0x1070100a92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP6_IP2_RML" , 0x1070100c92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP7_IP2_RML" , 0x1070100e92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP8_IP2_RML" , 0x1070101092000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP9_IP2_RML" , 0x1070101292000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP10_IP2_RML" , 0x1070101492000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP11_IP2_RML" , 0x1070101692000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP12_IP2_RML" , 0x1070101892000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP13_IP2_RML" , 0x1070101a92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP14_IP2_RML" , 0x1070101c92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP15_IP2_RML" , 0x1070101e92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP16_IP2_RML" , 0x1070102092000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP17_IP2_RML" , 0x1070102292000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP18_IP2_RML" , 0x1070102492000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP19_IP2_RML" , 0x1070102692000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP20_IP2_RML" , 0x1070102892000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP21_IP2_RML" , 0x1070102a92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP22_IP2_RML" , 0x1070102c92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP23_IP2_RML" , 0x1070102e92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP24_IP2_RML" , 0x1070103092000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP25_IP2_RML" , 0x1070103292000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP26_IP2_RML" , 0x1070103492000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP27_IP2_RML" , 0x1070103692000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP28_IP2_RML" , 0x1070103892000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP29_IP2_RML" , 0x1070103a92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP30_IP2_RML" , 0x1070103c92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP31_IP2_RML" , 0x1070103e92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP0_IP2_RML_W1C" , 0x10701000b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP1_IP2_RML_W1C" , 0x10701002b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP2_IP2_RML_W1C" , 0x10701004b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP3_IP2_RML_W1C" , 0x10701006b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP4_IP2_RML_W1C" , 0x10701008b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP5_IP2_RML_W1C" , 0x1070100ab2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP6_IP2_RML_W1C" , 0x1070100cb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP7_IP2_RML_W1C" , 0x1070100eb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP8_IP2_RML_W1C" , 0x10701010b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP9_IP2_RML_W1C" , 0x10701012b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP10_IP2_RML_W1C" , 0x10701014b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP11_IP2_RML_W1C" , 0x10701016b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP12_IP2_RML_W1C" , 0x10701018b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP13_IP2_RML_W1C" , 0x1070101ab2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP14_IP2_RML_W1C" , 0x1070101cb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP15_IP2_RML_W1C" , 0x1070101eb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP16_IP2_RML_W1C" , 0x10701020b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP17_IP2_RML_W1C" , 0x10701022b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP18_IP2_RML_W1C" , 0x10701024b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP19_IP2_RML_W1C" , 0x10701026b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP20_IP2_RML_W1C" , 0x10701028b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP21_IP2_RML_W1C" , 0x1070102ab2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP22_IP2_RML_W1C" , 0x1070102cb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP23_IP2_RML_W1C" , 0x1070102eb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP24_IP2_RML_W1C" , 0x10701030b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP25_IP2_RML_W1C" , 0x10701032b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP26_IP2_RML_W1C" , 0x10701034b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP27_IP2_RML_W1C" , 0x10701036b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP28_IP2_RML_W1C" , 0x10701038b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP29_IP2_RML_W1C" , 0x1070103ab2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP30_IP2_RML_W1C" , 0x1070103cb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP31_IP2_RML_W1C" , 0x1070103eb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP0_IP2_RML_W1S" , 0x10701000a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP1_IP2_RML_W1S" , 0x10701002a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP2_IP2_RML_W1S" , 0x10701004a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP3_IP2_RML_W1S" , 0x10701006a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP4_IP2_RML_W1S" , 0x10701008a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP5_IP2_RML_W1S" , 0x1070100aa2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP6_IP2_RML_W1S" , 0x1070100ca2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP7_IP2_RML_W1S" , 0x1070100ea2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP8_IP2_RML_W1S" , 0x10701010a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP9_IP2_RML_W1S" , 0x10701012a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP10_IP2_RML_W1S" , 0x10701014a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP11_IP2_RML_W1S" , 0x10701016a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP12_IP2_RML_W1S" , 0x10701018a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP13_IP2_RML_W1S" , 0x1070101aa2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP14_IP2_RML_W1S" , 0x1070101ca2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP15_IP2_RML_W1S" , 0x1070101ea2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP16_IP2_RML_W1S" , 0x10701020a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP17_IP2_RML_W1S" , 0x10701022a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP18_IP2_RML_W1S" , 0x10701024a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP19_IP2_RML_W1S" , 0x10701026a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP20_IP2_RML_W1S" , 0x10701028a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP21_IP2_RML_W1S" , 0x1070102aa2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP22_IP2_RML_W1S" , 0x1070102ca2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP23_IP2_RML_W1S" , 0x1070102ea2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP24_IP2_RML_W1S" , 0x10701030a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP25_IP2_RML_W1S" , 0x10701032a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP26_IP2_RML_W1S" , 0x10701034a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP27_IP2_RML_W1S" , 0x10701036a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP28_IP2_RML_W1S" , 0x10701038a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP29_IP2_RML_W1S" , 0x1070103aa2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP30_IP2_RML_W1S" , 0x1070103ca2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP31_IP2_RML_W1S" , 0x1070103ea2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP0_IP2_WDOG" , 0x1070100091000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP1_IP2_WDOG" , 0x1070100291000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP2_IP2_WDOG" , 0x1070100491000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP3_IP2_WDOG" , 0x1070100691000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP4_IP2_WDOG" , 0x1070100891000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP5_IP2_WDOG" , 0x1070100a91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP6_IP2_WDOG" , 0x1070100c91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP7_IP2_WDOG" , 0x1070100e91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP8_IP2_WDOG" , 0x1070101091000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP9_IP2_WDOG" , 0x1070101291000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP10_IP2_WDOG" , 0x1070101491000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP11_IP2_WDOG" , 0x1070101691000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP12_IP2_WDOG" , 0x1070101891000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP13_IP2_WDOG" , 0x1070101a91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP14_IP2_WDOG" , 0x1070101c91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP15_IP2_WDOG" , 0x1070101e91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP16_IP2_WDOG" , 0x1070102091000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP17_IP2_WDOG" , 0x1070102291000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP18_IP2_WDOG" , 0x1070102491000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP19_IP2_WDOG" , 0x1070102691000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP20_IP2_WDOG" , 0x1070102891000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP21_IP2_WDOG" , 0x1070102a91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP22_IP2_WDOG" , 0x1070102c91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP23_IP2_WDOG" , 0x1070102e91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP24_IP2_WDOG" , 0x1070103091000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP25_IP2_WDOG" , 0x1070103291000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP26_IP2_WDOG" , 0x1070103491000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP27_IP2_WDOG" , 0x1070103691000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP28_IP2_WDOG" , 0x1070103891000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP29_IP2_WDOG" , 0x1070103a91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP30_IP2_WDOG" , 0x1070103c91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP31_IP2_WDOG" , 0x1070103e91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP0_IP2_WDOG_W1C" , 0x10701000b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP1_IP2_WDOG_W1C" , 0x10701002b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP2_IP2_WDOG_W1C" , 0x10701004b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP3_IP2_WDOG_W1C" , 0x10701006b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP4_IP2_WDOG_W1C" , 0x10701008b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP5_IP2_WDOG_W1C" , 0x1070100ab1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP6_IP2_WDOG_W1C" , 0x1070100cb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP7_IP2_WDOG_W1C" , 0x1070100eb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP8_IP2_WDOG_W1C" , 0x10701010b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP9_IP2_WDOG_W1C" , 0x10701012b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP10_IP2_WDOG_W1C" , 0x10701014b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP11_IP2_WDOG_W1C" , 0x10701016b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP12_IP2_WDOG_W1C" , 0x10701018b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP13_IP2_WDOG_W1C" , 0x1070101ab1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP14_IP2_WDOG_W1C" , 0x1070101cb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP15_IP2_WDOG_W1C" , 0x1070101eb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP16_IP2_WDOG_W1C" , 0x10701020b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP17_IP2_WDOG_W1C" , 0x10701022b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP18_IP2_WDOG_W1C" , 0x10701024b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP19_IP2_WDOG_W1C" , 0x10701026b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP20_IP2_WDOG_W1C" , 0x10701028b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP21_IP2_WDOG_W1C" , 0x1070102ab1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP22_IP2_WDOG_W1C" , 0x1070102cb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP23_IP2_WDOG_W1C" , 0x1070102eb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP24_IP2_WDOG_W1C" , 0x10701030b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP25_IP2_WDOG_W1C" , 0x10701032b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP26_IP2_WDOG_W1C" , 0x10701034b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP27_IP2_WDOG_W1C" , 0x10701036b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP28_IP2_WDOG_W1C" , 0x10701038b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP29_IP2_WDOG_W1C" , 0x1070103ab1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP30_IP2_WDOG_W1C" , 0x1070103cb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP31_IP2_WDOG_W1C" , 0x1070103eb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP0_IP2_WDOG_W1S" , 0x10701000a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP1_IP2_WDOG_W1S" , 0x10701002a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP2_IP2_WDOG_W1S" , 0x10701004a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP3_IP2_WDOG_W1S" , 0x10701006a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP4_IP2_WDOG_W1S" , 0x10701008a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP5_IP2_WDOG_W1S" , 0x1070100aa1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP6_IP2_WDOG_W1S" , 0x1070100ca1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP7_IP2_WDOG_W1S" , 0x1070100ea1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP8_IP2_WDOG_W1S" , 0x10701010a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP9_IP2_WDOG_W1S" , 0x10701012a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP10_IP2_WDOG_W1S" , 0x10701014a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP11_IP2_WDOG_W1S" , 0x10701016a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP12_IP2_WDOG_W1S" , 0x10701018a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP13_IP2_WDOG_W1S" , 0x1070101aa1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP14_IP2_WDOG_W1S" , 0x1070101ca1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP15_IP2_WDOG_W1S" , 0x1070101ea1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP16_IP2_WDOG_W1S" , 0x10701020a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP17_IP2_WDOG_W1S" , 0x10701022a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP18_IP2_WDOG_W1S" , 0x10701024a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP19_IP2_WDOG_W1S" , 0x10701026a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP20_IP2_WDOG_W1S" , 0x10701028a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP21_IP2_WDOG_W1S" , 0x1070102aa1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP22_IP2_WDOG_W1S" , 0x1070102ca1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP23_IP2_WDOG_W1S" , 0x1070102ea1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP24_IP2_WDOG_W1S" , 0x10701030a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP25_IP2_WDOG_W1S" , 0x10701032a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP26_IP2_WDOG_W1S" , 0x10701034a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP27_IP2_WDOG_W1S" , 0x10701036a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP28_IP2_WDOG_W1S" , 0x10701038a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP29_IP2_WDOG_W1S" , 0x1070103aa1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP30_IP2_WDOG_W1S" , 0x1070103ca1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP31_IP2_WDOG_W1S" , 0x1070103ea1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP0_IP2_WRKQ" , 0x1070100090000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP1_IP2_WRKQ" , 0x1070100290000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP2_IP2_WRKQ" , 0x1070100490000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP3_IP2_WRKQ" , 0x1070100690000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP4_IP2_WRKQ" , 0x1070100890000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP5_IP2_WRKQ" , 0x1070100a90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP6_IP2_WRKQ" , 0x1070100c90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP7_IP2_WRKQ" , 0x1070100e90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP8_IP2_WRKQ" , 0x1070101090000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP9_IP2_WRKQ" , 0x1070101290000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP10_IP2_WRKQ" , 0x1070101490000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP11_IP2_WRKQ" , 0x1070101690000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP12_IP2_WRKQ" , 0x1070101890000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP13_IP2_WRKQ" , 0x1070101a90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP14_IP2_WRKQ" , 0x1070101c90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP15_IP2_WRKQ" , 0x1070101e90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP16_IP2_WRKQ" , 0x1070102090000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP17_IP2_WRKQ" , 0x1070102290000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP18_IP2_WRKQ" , 0x1070102490000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP19_IP2_WRKQ" , 0x1070102690000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP20_IP2_WRKQ" , 0x1070102890000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP21_IP2_WRKQ" , 0x1070102a90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP22_IP2_WRKQ" , 0x1070102c90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP23_IP2_WRKQ" , 0x1070102e90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP24_IP2_WRKQ" , 0x1070103090000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP25_IP2_WRKQ" , 0x1070103290000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP26_IP2_WRKQ" , 0x1070103490000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP27_IP2_WRKQ" , 0x1070103690000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP28_IP2_WRKQ" , 0x1070103890000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP29_IP2_WRKQ" , 0x1070103a90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP30_IP2_WRKQ" , 0x1070103c90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP31_IP2_WRKQ" , 0x1070103e90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP0_IP2_WRKQ_W1C" , 0x10701000b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP1_IP2_WRKQ_W1C" , 0x10701002b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP2_IP2_WRKQ_W1C" , 0x10701004b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP3_IP2_WRKQ_W1C" , 0x10701006b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP4_IP2_WRKQ_W1C" , 0x10701008b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP5_IP2_WRKQ_W1C" , 0x1070100ab0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP6_IP2_WRKQ_W1C" , 0x1070100cb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP7_IP2_WRKQ_W1C" , 0x1070100eb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP8_IP2_WRKQ_W1C" , 0x10701010b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP9_IP2_WRKQ_W1C" , 0x10701012b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP10_IP2_WRKQ_W1C" , 0x10701014b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP11_IP2_WRKQ_W1C" , 0x10701016b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP12_IP2_WRKQ_W1C" , 0x10701018b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP13_IP2_WRKQ_W1C" , 0x1070101ab0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP14_IP2_WRKQ_W1C" , 0x1070101cb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP15_IP2_WRKQ_W1C" , 0x1070101eb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP16_IP2_WRKQ_W1C" , 0x10701020b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP17_IP2_WRKQ_W1C" , 0x10701022b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP18_IP2_WRKQ_W1C" , 0x10701024b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP19_IP2_WRKQ_W1C" , 0x10701026b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP20_IP2_WRKQ_W1C" , 0x10701028b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP21_IP2_WRKQ_W1C" , 0x1070102ab0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP22_IP2_WRKQ_W1C" , 0x1070102cb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP23_IP2_WRKQ_W1C" , 0x1070102eb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP24_IP2_WRKQ_W1C" , 0x10701030b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP25_IP2_WRKQ_W1C" , 0x10701032b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP26_IP2_WRKQ_W1C" , 0x10701034b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP27_IP2_WRKQ_W1C" , 0x10701036b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP28_IP2_WRKQ_W1C" , 0x10701038b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP29_IP2_WRKQ_W1C" , 0x1070103ab0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP30_IP2_WRKQ_W1C" , 0x1070103cb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP31_IP2_WRKQ_W1C" , 0x1070103eb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP0_IP2_WRKQ_W1S" , 0x10701000a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP1_IP2_WRKQ_W1S" , 0x10701002a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP2_IP2_WRKQ_W1S" , 0x10701004a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP3_IP2_WRKQ_W1S" , 0x10701006a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP4_IP2_WRKQ_W1S" , 0x10701008a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP5_IP2_WRKQ_W1S" , 0x1070100aa0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP6_IP2_WRKQ_W1S" , 0x1070100ca0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP7_IP2_WRKQ_W1S" , 0x1070100ea0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP8_IP2_WRKQ_W1S" , 0x10701010a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP9_IP2_WRKQ_W1S" , 0x10701012a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP10_IP2_WRKQ_W1S" , 0x10701014a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP11_IP2_WRKQ_W1S" , 0x10701016a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP12_IP2_WRKQ_W1S" , 0x10701018a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP13_IP2_WRKQ_W1S" , 0x1070101aa0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP14_IP2_WRKQ_W1S" , 0x1070101ca0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP15_IP2_WRKQ_W1S" , 0x1070101ea0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP16_IP2_WRKQ_W1S" , 0x10701020a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP17_IP2_WRKQ_W1S" , 0x10701022a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP18_IP2_WRKQ_W1S" , 0x10701024a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP19_IP2_WRKQ_W1S" , 0x10701026a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP20_IP2_WRKQ_W1S" , 0x10701028a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP21_IP2_WRKQ_W1S" , 0x1070102aa0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP22_IP2_WRKQ_W1S" , 0x1070102ca0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP23_IP2_WRKQ_W1S" , 0x1070102ea0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP24_IP2_WRKQ_W1S" , 0x10701030a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP25_IP2_WRKQ_W1S" , 0x10701032a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP26_IP2_WRKQ_W1S" , 0x10701034a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP27_IP2_WRKQ_W1S" , 0x10701036a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP28_IP2_WRKQ_W1S" , 0x10701038a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP29_IP2_WRKQ_W1S" , 0x1070103aa0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP30_IP2_WRKQ_W1S" , 0x1070103ca0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP31_IP2_WRKQ_W1S" , 0x1070103ea0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP0_IP3_GPIO" , 0x1070100097200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP1_IP3_GPIO" , 0x1070100297200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP2_IP3_GPIO" , 0x1070100497200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP3_IP3_GPIO" , 0x1070100697200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP4_IP3_GPIO" , 0x1070100897200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP5_IP3_GPIO" , 0x1070100a97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP6_IP3_GPIO" , 0x1070100c97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP7_IP3_GPIO" , 0x1070100e97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP8_IP3_GPIO" , 0x1070101097200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP9_IP3_GPIO" , 0x1070101297200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP10_IP3_GPIO" , 0x1070101497200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP11_IP3_GPIO" , 0x1070101697200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP12_IP3_GPIO" , 0x1070101897200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP13_IP3_GPIO" , 0x1070101a97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP14_IP3_GPIO" , 0x1070101c97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP15_IP3_GPIO" , 0x1070101e97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP16_IP3_GPIO" , 0x1070102097200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP17_IP3_GPIO" , 0x1070102297200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP18_IP3_GPIO" , 0x1070102497200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP19_IP3_GPIO" , 0x1070102697200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP20_IP3_GPIO" , 0x1070102897200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP21_IP3_GPIO" , 0x1070102a97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP22_IP3_GPIO" , 0x1070102c97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP23_IP3_GPIO" , 0x1070102e97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP24_IP3_GPIO" , 0x1070103097200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP25_IP3_GPIO" , 0x1070103297200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP26_IP3_GPIO" , 0x1070103497200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP27_IP3_GPIO" , 0x1070103697200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP28_IP3_GPIO" , 0x1070103897200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP29_IP3_GPIO" , 0x1070103a97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP30_IP3_GPIO" , 0x1070103c97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP31_IP3_GPIO" , 0x1070103e97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP0_IP3_GPIO_W1C" , 0x10701000b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP1_IP3_GPIO_W1C" , 0x10701002b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP2_IP3_GPIO_W1C" , 0x10701004b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP3_IP3_GPIO_W1C" , 0x10701006b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP4_IP3_GPIO_W1C" , 0x10701008b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP5_IP3_GPIO_W1C" , 0x1070100ab7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP6_IP3_GPIO_W1C" , 0x1070100cb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP7_IP3_GPIO_W1C" , 0x1070100eb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP8_IP3_GPIO_W1C" , 0x10701010b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP9_IP3_GPIO_W1C" , 0x10701012b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP10_IP3_GPIO_W1C" , 0x10701014b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP11_IP3_GPIO_W1C" , 0x10701016b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP12_IP3_GPIO_W1C" , 0x10701018b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP13_IP3_GPIO_W1C" , 0x1070101ab7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP14_IP3_GPIO_W1C" , 0x1070101cb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP15_IP3_GPIO_W1C" , 0x1070101eb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP16_IP3_GPIO_W1C" , 0x10701020b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP17_IP3_GPIO_W1C" , 0x10701022b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP18_IP3_GPIO_W1C" , 0x10701024b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP19_IP3_GPIO_W1C" , 0x10701026b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP20_IP3_GPIO_W1C" , 0x10701028b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP21_IP3_GPIO_W1C" , 0x1070102ab7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP22_IP3_GPIO_W1C" , 0x1070102cb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP23_IP3_GPIO_W1C" , 0x1070102eb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP24_IP3_GPIO_W1C" , 0x10701030b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP25_IP3_GPIO_W1C" , 0x10701032b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP26_IP3_GPIO_W1C" , 0x10701034b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP27_IP3_GPIO_W1C" , 0x10701036b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP28_IP3_GPIO_W1C" , 0x10701038b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP29_IP3_GPIO_W1C" , 0x1070103ab7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP30_IP3_GPIO_W1C" , 0x1070103cb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP31_IP3_GPIO_W1C" , 0x1070103eb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP0_IP3_GPIO_W1S" , 0x10701000a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP1_IP3_GPIO_W1S" , 0x10701002a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP2_IP3_GPIO_W1S" , 0x10701004a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP3_IP3_GPIO_W1S" , 0x10701006a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP4_IP3_GPIO_W1S" , 0x10701008a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP5_IP3_GPIO_W1S" , 0x1070100aa7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP6_IP3_GPIO_W1S" , 0x1070100ca7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP7_IP3_GPIO_W1S" , 0x1070100ea7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP8_IP3_GPIO_W1S" , 0x10701010a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP9_IP3_GPIO_W1S" , 0x10701012a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP10_IP3_GPIO_W1S" , 0x10701014a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP11_IP3_GPIO_W1S" , 0x10701016a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP12_IP3_GPIO_W1S" , 0x10701018a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP13_IP3_GPIO_W1S" , 0x1070101aa7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP14_IP3_GPIO_W1S" , 0x1070101ca7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP15_IP3_GPIO_W1S" , 0x1070101ea7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP16_IP3_GPIO_W1S" , 0x10701020a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP17_IP3_GPIO_W1S" , 0x10701022a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP18_IP3_GPIO_W1S" , 0x10701024a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP19_IP3_GPIO_W1S" , 0x10701026a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP20_IP3_GPIO_W1S" , 0x10701028a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP21_IP3_GPIO_W1S" , 0x1070102aa7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP22_IP3_GPIO_W1S" , 0x1070102ca7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP23_IP3_GPIO_W1S" , 0x1070102ea7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP24_IP3_GPIO_W1S" , 0x10701030a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP25_IP3_GPIO_W1S" , 0x10701032a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP26_IP3_GPIO_W1S" , 0x10701034a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP27_IP3_GPIO_W1S" , 0x10701036a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP28_IP3_GPIO_W1S" , 0x10701038a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP29_IP3_GPIO_W1S" , 0x1070103aa7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP30_IP3_GPIO_W1S" , 0x1070103ca7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP31_IP3_GPIO_W1S" , 0x1070103ea7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP0_IP3_IO" , 0x1070100094200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP1_IP3_IO" , 0x1070100294200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP2_IP3_IO" , 0x1070100494200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP3_IP3_IO" , 0x1070100694200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP4_IP3_IO" , 0x1070100894200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP5_IP3_IO" , 0x1070100a94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP6_IP3_IO" , 0x1070100c94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP7_IP3_IO" , 0x1070100e94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP8_IP3_IO" , 0x1070101094200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP9_IP3_IO" , 0x1070101294200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP10_IP3_IO" , 0x1070101494200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP11_IP3_IO" , 0x1070101694200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP12_IP3_IO" , 0x1070101894200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP13_IP3_IO" , 0x1070101a94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP14_IP3_IO" , 0x1070101c94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP15_IP3_IO" , 0x1070101e94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP16_IP3_IO" , 0x1070102094200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP17_IP3_IO" , 0x1070102294200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP18_IP3_IO" , 0x1070102494200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP19_IP3_IO" , 0x1070102694200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP20_IP3_IO" , 0x1070102894200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP21_IP3_IO" , 0x1070102a94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP22_IP3_IO" , 0x1070102c94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP23_IP3_IO" , 0x1070102e94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP24_IP3_IO" , 0x1070103094200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP25_IP3_IO" , 0x1070103294200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP26_IP3_IO" , 0x1070103494200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP27_IP3_IO" , 0x1070103694200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP28_IP3_IO" , 0x1070103894200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP29_IP3_IO" , 0x1070103a94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP30_IP3_IO" , 0x1070103c94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP31_IP3_IO" , 0x1070103e94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP0_IP3_IO_W1C" , 0x10701000b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP1_IP3_IO_W1C" , 0x10701002b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP2_IP3_IO_W1C" , 0x10701004b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP3_IP3_IO_W1C" , 0x10701006b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP4_IP3_IO_W1C" , 0x10701008b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP5_IP3_IO_W1C" , 0x1070100ab4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP6_IP3_IO_W1C" , 0x1070100cb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP7_IP3_IO_W1C" , 0x1070100eb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP8_IP3_IO_W1C" , 0x10701010b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP9_IP3_IO_W1C" , 0x10701012b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP10_IP3_IO_W1C" , 0x10701014b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP11_IP3_IO_W1C" , 0x10701016b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP12_IP3_IO_W1C" , 0x10701018b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP13_IP3_IO_W1C" , 0x1070101ab4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP14_IP3_IO_W1C" , 0x1070101cb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP15_IP3_IO_W1C" , 0x1070101eb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP16_IP3_IO_W1C" , 0x10701020b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP17_IP3_IO_W1C" , 0x10701022b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP18_IP3_IO_W1C" , 0x10701024b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP19_IP3_IO_W1C" , 0x10701026b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP20_IP3_IO_W1C" , 0x10701028b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP21_IP3_IO_W1C" , 0x1070102ab4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP22_IP3_IO_W1C" , 0x1070102cb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP23_IP3_IO_W1C" , 0x1070102eb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP24_IP3_IO_W1C" , 0x10701030b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP25_IP3_IO_W1C" , 0x10701032b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP26_IP3_IO_W1C" , 0x10701034b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP27_IP3_IO_W1C" , 0x10701036b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP28_IP3_IO_W1C" , 0x10701038b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP29_IP3_IO_W1C" , 0x1070103ab4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP30_IP3_IO_W1C" , 0x1070103cb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP31_IP3_IO_W1C" , 0x1070103eb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP0_IP3_IO_W1S" , 0x10701000a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP1_IP3_IO_W1S" , 0x10701002a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP2_IP3_IO_W1S" , 0x10701004a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP3_IP3_IO_W1S" , 0x10701006a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP4_IP3_IO_W1S" , 0x10701008a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP5_IP3_IO_W1S" , 0x1070100aa4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP6_IP3_IO_W1S" , 0x1070100ca4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP7_IP3_IO_W1S" , 0x1070100ea4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP8_IP3_IO_W1S" , 0x10701010a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP9_IP3_IO_W1S" , 0x10701012a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP10_IP3_IO_W1S" , 0x10701014a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP11_IP3_IO_W1S" , 0x10701016a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP12_IP3_IO_W1S" , 0x10701018a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP13_IP3_IO_W1S" , 0x1070101aa4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP14_IP3_IO_W1S" , 0x1070101ca4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP15_IP3_IO_W1S" , 0x1070101ea4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP16_IP3_IO_W1S" , 0x10701020a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP17_IP3_IO_W1S" , 0x10701022a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP18_IP3_IO_W1S" , 0x10701024a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP19_IP3_IO_W1S" , 0x10701026a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP20_IP3_IO_W1S" , 0x10701028a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP21_IP3_IO_W1S" , 0x1070102aa4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP22_IP3_IO_W1S" , 0x1070102ca4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP23_IP3_IO_W1S" , 0x1070102ea4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP24_IP3_IO_W1S" , 0x10701030a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP25_IP3_IO_W1S" , 0x10701032a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP26_IP3_IO_W1S" , 0x10701034a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP27_IP3_IO_W1S" , 0x10701036a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP28_IP3_IO_W1S" , 0x10701038a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP29_IP3_IO_W1S" , 0x1070103aa4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP30_IP3_IO_W1S" , 0x1070103ca4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP31_IP3_IO_W1S" , 0x1070103ea4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP0_IP3_MBOX" , 0x1070100098200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP1_IP3_MBOX" , 0x1070100298200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP2_IP3_MBOX" , 0x1070100498200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP3_IP3_MBOX" , 0x1070100698200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP4_IP3_MBOX" , 0x1070100898200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP5_IP3_MBOX" , 0x1070100a98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP6_IP3_MBOX" , 0x1070100c98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP7_IP3_MBOX" , 0x1070100e98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP8_IP3_MBOX" , 0x1070101098200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP9_IP3_MBOX" , 0x1070101298200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP10_IP3_MBOX" , 0x1070101498200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP11_IP3_MBOX" , 0x1070101698200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP12_IP3_MBOX" , 0x1070101898200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP13_IP3_MBOX" , 0x1070101a98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP14_IP3_MBOX" , 0x1070101c98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP15_IP3_MBOX" , 0x1070101e98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP16_IP3_MBOX" , 0x1070102098200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP17_IP3_MBOX" , 0x1070102298200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP18_IP3_MBOX" , 0x1070102498200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP19_IP3_MBOX" , 0x1070102698200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP20_IP3_MBOX" , 0x1070102898200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP21_IP3_MBOX" , 0x1070102a98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP22_IP3_MBOX" , 0x1070102c98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP23_IP3_MBOX" , 0x1070102e98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP24_IP3_MBOX" , 0x1070103098200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP25_IP3_MBOX" , 0x1070103298200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP26_IP3_MBOX" , 0x1070103498200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP27_IP3_MBOX" , 0x1070103698200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP28_IP3_MBOX" , 0x1070103898200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP29_IP3_MBOX" , 0x1070103a98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP30_IP3_MBOX" , 0x1070103c98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP31_IP3_MBOX" , 0x1070103e98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP0_IP3_MBOX_W1C" , 0x10701000b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP1_IP3_MBOX_W1C" , 0x10701002b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP2_IP3_MBOX_W1C" , 0x10701004b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP3_IP3_MBOX_W1C" , 0x10701006b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP4_IP3_MBOX_W1C" , 0x10701008b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP5_IP3_MBOX_W1C" , 0x1070100ab8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP6_IP3_MBOX_W1C" , 0x1070100cb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP7_IP3_MBOX_W1C" , 0x1070100eb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP8_IP3_MBOX_W1C" , 0x10701010b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP9_IP3_MBOX_W1C" , 0x10701012b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP10_IP3_MBOX_W1C" , 0x10701014b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP11_IP3_MBOX_W1C" , 0x10701016b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP12_IP3_MBOX_W1C" , 0x10701018b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP13_IP3_MBOX_W1C" , 0x1070101ab8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP14_IP3_MBOX_W1C" , 0x1070101cb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP15_IP3_MBOX_W1C" , 0x1070101eb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP16_IP3_MBOX_W1C" , 0x10701020b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP17_IP3_MBOX_W1C" , 0x10701022b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP18_IP3_MBOX_W1C" , 0x10701024b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP19_IP3_MBOX_W1C" , 0x10701026b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP20_IP3_MBOX_W1C" , 0x10701028b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP21_IP3_MBOX_W1C" , 0x1070102ab8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP22_IP3_MBOX_W1C" , 0x1070102cb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP23_IP3_MBOX_W1C" , 0x1070102eb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP24_IP3_MBOX_W1C" , 0x10701030b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP25_IP3_MBOX_W1C" , 0x10701032b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP26_IP3_MBOX_W1C" , 0x10701034b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP27_IP3_MBOX_W1C" , 0x10701036b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP28_IP3_MBOX_W1C" , 0x10701038b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP29_IP3_MBOX_W1C" , 0x1070103ab8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP30_IP3_MBOX_W1C" , 0x1070103cb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP31_IP3_MBOX_W1C" , 0x1070103eb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP0_IP3_MBOX_W1S" , 0x10701000a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP1_IP3_MBOX_W1S" , 0x10701002a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP2_IP3_MBOX_W1S" , 0x10701004a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP3_IP3_MBOX_W1S" , 0x10701006a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP4_IP3_MBOX_W1S" , 0x10701008a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP5_IP3_MBOX_W1S" , 0x1070100aa8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP6_IP3_MBOX_W1S" , 0x1070100ca8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP7_IP3_MBOX_W1S" , 0x1070100ea8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP8_IP3_MBOX_W1S" , 0x10701010a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP9_IP3_MBOX_W1S" , 0x10701012a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP10_IP3_MBOX_W1S" , 0x10701014a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP11_IP3_MBOX_W1S" , 0x10701016a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP12_IP3_MBOX_W1S" , 0x10701018a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP13_IP3_MBOX_W1S" , 0x1070101aa8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP14_IP3_MBOX_W1S" , 0x1070101ca8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP15_IP3_MBOX_W1S" , 0x1070101ea8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP16_IP3_MBOX_W1S" , 0x10701020a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP17_IP3_MBOX_W1S" , 0x10701022a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP18_IP3_MBOX_W1S" , 0x10701024a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP19_IP3_MBOX_W1S" , 0x10701026a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP20_IP3_MBOX_W1S" , 0x10701028a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP21_IP3_MBOX_W1S" , 0x1070102aa8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP22_IP3_MBOX_W1S" , 0x1070102ca8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP23_IP3_MBOX_W1S" , 0x1070102ea8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP24_IP3_MBOX_W1S" , 0x10701030a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP25_IP3_MBOX_W1S" , 0x10701032a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP26_IP3_MBOX_W1S" , 0x10701034a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP27_IP3_MBOX_W1S" , 0x10701036a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP28_IP3_MBOX_W1S" , 0x10701038a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP29_IP3_MBOX_W1S" , 0x1070103aa8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP30_IP3_MBOX_W1S" , 0x1070103ca8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP31_IP3_MBOX_W1S" , 0x1070103ea8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP0_IP3_MEM" , 0x1070100095200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP1_IP3_MEM" , 0x1070100295200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP2_IP3_MEM" , 0x1070100495200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP3_IP3_MEM" , 0x1070100695200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP4_IP3_MEM" , 0x1070100895200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP5_IP3_MEM" , 0x1070100a95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP6_IP3_MEM" , 0x1070100c95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP7_IP3_MEM" , 0x1070100e95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP8_IP3_MEM" , 0x1070101095200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP9_IP3_MEM" , 0x1070101295200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP10_IP3_MEM" , 0x1070101495200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP11_IP3_MEM" , 0x1070101695200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP12_IP3_MEM" , 0x1070101895200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP13_IP3_MEM" , 0x1070101a95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP14_IP3_MEM" , 0x1070101c95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP15_IP3_MEM" , 0x1070101e95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP16_IP3_MEM" , 0x1070102095200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP17_IP3_MEM" , 0x1070102295200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP18_IP3_MEM" , 0x1070102495200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP19_IP3_MEM" , 0x1070102695200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP20_IP3_MEM" , 0x1070102895200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP21_IP3_MEM" , 0x1070102a95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP22_IP3_MEM" , 0x1070102c95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP23_IP3_MEM" , 0x1070102e95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP24_IP3_MEM" , 0x1070103095200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP25_IP3_MEM" , 0x1070103295200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP26_IP3_MEM" , 0x1070103495200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP27_IP3_MEM" , 0x1070103695200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP28_IP3_MEM" , 0x1070103895200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP29_IP3_MEM" , 0x1070103a95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP30_IP3_MEM" , 0x1070103c95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP31_IP3_MEM" , 0x1070103e95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP0_IP3_MEM_W1C" , 0x10701000b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP1_IP3_MEM_W1C" , 0x10701002b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP2_IP3_MEM_W1C" , 0x10701004b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP3_IP3_MEM_W1C" , 0x10701006b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP4_IP3_MEM_W1C" , 0x10701008b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP5_IP3_MEM_W1C" , 0x1070100ab5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP6_IP3_MEM_W1C" , 0x1070100cb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP7_IP3_MEM_W1C" , 0x1070100eb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP8_IP3_MEM_W1C" , 0x10701010b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP9_IP3_MEM_W1C" , 0x10701012b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP10_IP3_MEM_W1C" , 0x10701014b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP11_IP3_MEM_W1C" , 0x10701016b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP12_IP3_MEM_W1C" , 0x10701018b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP13_IP3_MEM_W1C" , 0x1070101ab5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP14_IP3_MEM_W1C" , 0x1070101cb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP15_IP3_MEM_W1C" , 0x1070101eb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP16_IP3_MEM_W1C" , 0x10701020b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP17_IP3_MEM_W1C" , 0x10701022b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP18_IP3_MEM_W1C" , 0x10701024b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP19_IP3_MEM_W1C" , 0x10701026b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP20_IP3_MEM_W1C" , 0x10701028b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP21_IP3_MEM_W1C" , 0x1070102ab5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP22_IP3_MEM_W1C" , 0x1070102cb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP23_IP3_MEM_W1C" , 0x1070102eb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP24_IP3_MEM_W1C" , 0x10701030b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP25_IP3_MEM_W1C" , 0x10701032b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP26_IP3_MEM_W1C" , 0x10701034b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP27_IP3_MEM_W1C" , 0x10701036b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP28_IP3_MEM_W1C" , 0x10701038b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP29_IP3_MEM_W1C" , 0x1070103ab5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP30_IP3_MEM_W1C" , 0x1070103cb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP31_IP3_MEM_W1C" , 0x1070103eb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP0_IP3_MEM_W1S" , 0x10701000a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP1_IP3_MEM_W1S" , 0x10701002a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP2_IP3_MEM_W1S" , 0x10701004a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP3_IP3_MEM_W1S" , 0x10701006a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP4_IP3_MEM_W1S" , 0x10701008a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP5_IP3_MEM_W1S" , 0x1070100aa5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP6_IP3_MEM_W1S" , 0x1070100ca5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP7_IP3_MEM_W1S" , 0x1070100ea5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP8_IP3_MEM_W1S" , 0x10701010a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP9_IP3_MEM_W1S" , 0x10701012a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP10_IP3_MEM_W1S" , 0x10701014a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP11_IP3_MEM_W1S" , 0x10701016a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP12_IP3_MEM_W1S" , 0x10701018a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP13_IP3_MEM_W1S" , 0x1070101aa5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP14_IP3_MEM_W1S" , 0x1070101ca5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP15_IP3_MEM_W1S" , 0x1070101ea5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP16_IP3_MEM_W1S" , 0x10701020a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP17_IP3_MEM_W1S" , 0x10701022a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP18_IP3_MEM_W1S" , 0x10701024a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP19_IP3_MEM_W1S" , 0x10701026a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP20_IP3_MEM_W1S" , 0x10701028a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP21_IP3_MEM_W1S" , 0x1070102aa5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP22_IP3_MEM_W1S" , 0x1070102ca5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP23_IP3_MEM_W1S" , 0x1070102ea5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP24_IP3_MEM_W1S" , 0x10701030a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP25_IP3_MEM_W1S" , 0x10701032a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP26_IP3_MEM_W1S" , 0x10701034a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP27_IP3_MEM_W1S" , 0x10701036a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP28_IP3_MEM_W1S" , 0x10701038a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP29_IP3_MEM_W1S" , 0x1070103aa5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP30_IP3_MEM_W1S" , 0x1070103ca5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP31_IP3_MEM_W1S" , 0x1070103ea5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP0_IP3_MIO" , 0x1070100093200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP1_IP3_MIO" , 0x1070100293200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP2_IP3_MIO" , 0x1070100493200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP3_IP3_MIO" , 0x1070100693200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP4_IP3_MIO" , 0x1070100893200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP5_IP3_MIO" , 0x1070100a93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP6_IP3_MIO" , 0x1070100c93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP7_IP3_MIO" , 0x1070100e93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP8_IP3_MIO" , 0x1070101093200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP9_IP3_MIO" , 0x1070101293200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP10_IP3_MIO" , 0x1070101493200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP11_IP3_MIO" , 0x1070101693200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP12_IP3_MIO" , 0x1070101893200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP13_IP3_MIO" , 0x1070101a93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP14_IP3_MIO" , 0x1070101c93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP15_IP3_MIO" , 0x1070101e93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP16_IP3_MIO" , 0x1070102093200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP17_IP3_MIO" , 0x1070102293200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP18_IP3_MIO" , 0x1070102493200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP19_IP3_MIO" , 0x1070102693200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP20_IP3_MIO" , 0x1070102893200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP21_IP3_MIO" , 0x1070102a93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP22_IP3_MIO" , 0x1070102c93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP23_IP3_MIO" , 0x1070102e93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP24_IP3_MIO" , 0x1070103093200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP25_IP3_MIO" , 0x1070103293200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP26_IP3_MIO" , 0x1070103493200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP27_IP3_MIO" , 0x1070103693200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP28_IP3_MIO" , 0x1070103893200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP29_IP3_MIO" , 0x1070103a93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP30_IP3_MIO" , 0x1070103c93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP31_IP3_MIO" , 0x1070103e93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP0_IP3_MIO_W1C" , 0x10701000b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP1_IP3_MIO_W1C" , 0x10701002b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP2_IP3_MIO_W1C" , 0x10701004b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP3_IP3_MIO_W1C" , 0x10701006b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP4_IP3_MIO_W1C" , 0x10701008b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP5_IP3_MIO_W1C" , 0x1070100ab3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP6_IP3_MIO_W1C" , 0x1070100cb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP7_IP3_MIO_W1C" , 0x1070100eb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP8_IP3_MIO_W1C" , 0x10701010b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP9_IP3_MIO_W1C" , 0x10701012b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP10_IP3_MIO_W1C" , 0x10701014b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP11_IP3_MIO_W1C" , 0x10701016b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP12_IP3_MIO_W1C" , 0x10701018b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP13_IP3_MIO_W1C" , 0x1070101ab3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP14_IP3_MIO_W1C" , 0x1070101cb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP15_IP3_MIO_W1C" , 0x1070101eb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP16_IP3_MIO_W1C" , 0x10701020b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP17_IP3_MIO_W1C" , 0x10701022b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP18_IP3_MIO_W1C" , 0x10701024b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP19_IP3_MIO_W1C" , 0x10701026b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP20_IP3_MIO_W1C" , 0x10701028b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP21_IP3_MIO_W1C" , 0x1070102ab3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP22_IP3_MIO_W1C" , 0x1070102cb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP23_IP3_MIO_W1C" , 0x1070102eb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP24_IP3_MIO_W1C" , 0x10701030b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP25_IP3_MIO_W1C" , 0x10701032b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP26_IP3_MIO_W1C" , 0x10701034b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP27_IP3_MIO_W1C" , 0x10701036b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP28_IP3_MIO_W1C" , 0x10701038b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP29_IP3_MIO_W1C" , 0x1070103ab3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP30_IP3_MIO_W1C" , 0x1070103cb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP31_IP3_MIO_W1C" , 0x1070103eb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP0_IP3_MIO_W1S" , 0x10701000a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP1_IP3_MIO_W1S" , 0x10701002a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP2_IP3_MIO_W1S" , 0x10701004a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP3_IP3_MIO_W1S" , 0x10701006a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP4_IP3_MIO_W1S" , 0x10701008a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP5_IP3_MIO_W1S" , 0x1070100aa3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP6_IP3_MIO_W1S" , 0x1070100ca3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP7_IP3_MIO_W1S" , 0x1070100ea3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP8_IP3_MIO_W1S" , 0x10701010a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP9_IP3_MIO_W1S" , 0x10701012a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP10_IP3_MIO_W1S" , 0x10701014a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP11_IP3_MIO_W1S" , 0x10701016a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP12_IP3_MIO_W1S" , 0x10701018a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP13_IP3_MIO_W1S" , 0x1070101aa3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP14_IP3_MIO_W1S" , 0x1070101ca3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP15_IP3_MIO_W1S" , 0x1070101ea3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP16_IP3_MIO_W1S" , 0x10701020a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP17_IP3_MIO_W1S" , 0x10701022a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP18_IP3_MIO_W1S" , 0x10701024a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP19_IP3_MIO_W1S" , 0x10701026a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP20_IP3_MIO_W1S" , 0x10701028a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP21_IP3_MIO_W1S" , 0x1070102aa3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP22_IP3_MIO_W1S" , 0x1070102ca3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP23_IP3_MIO_W1S" , 0x1070102ea3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP24_IP3_MIO_W1S" , 0x10701030a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP25_IP3_MIO_W1S" , 0x10701032a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP26_IP3_MIO_W1S" , 0x10701034a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP27_IP3_MIO_W1S" , 0x10701036a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP28_IP3_MIO_W1S" , 0x10701038a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP29_IP3_MIO_W1S" , 0x1070103aa3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP30_IP3_MIO_W1S" , 0x1070103ca3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP31_IP3_MIO_W1S" , 0x1070103ea3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP0_IP3_PKT" , 0x1070100096200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP1_IP3_PKT" , 0x1070100296200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP2_IP3_PKT" , 0x1070100496200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP3_IP3_PKT" , 0x1070100696200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP4_IP3_PKT" , 0x1070100896200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP5_IP3_PKT" , 0x1070100a96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP6_IP3_PKT" , 0x1070100c96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP7_IP3_PKT" , 0x1070100e96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP8_IP3_PKT" , 0x1070101096200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP9_IP3_PKT" , 0x1070101296200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP10_IP3_PKT" , 0x1070101496200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP11_IP3_PKT" , 0x1070101696200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP12_IP3_PKT" , 0x1070101896200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP13_IP3_PKT" , 0x1070101a96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP14_IP3_PKT" , 0x1070101c96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP15_IP3_PKT" , 0x1070101e96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP16_IP3_PKT" , 0x1070102096200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP17_IP3_PKT" , 0x1070102296200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP18_IP3_PKT" , 0x1070102496200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP19_IP3_PKT" , 0x1070102696200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP20_IP3_PKT" , 0x1070102896200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP21_IP3_PKT" , 0x1070102a96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP22_IP3_PKT" , 0x1070102c96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP23_IP3_PKT" , 0x1070102e96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP24_IP3_PKT" , 0x1070103096200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP25_IP3_PKT" , 0x1070103296200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP26_IP3_PKT" , 0x1070103496200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP27_IP3_PKT" , 0x1070103696200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP28_IP3_PKT" , 0x1070103896200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP29_IP3_PKT" , 0x1070103a96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP30_IP3_PKT" , 0x1070103c96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP31_IP3_PKT" , 0x1070103e96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP0_IP3_PKT_W1C" , 0x10701000b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP1_IP3_PKT_W1C" , 0x10701002b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP2_IP3_PKT_W1C" , 0x10701004b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP3_IP3_PKT_W1C" , 0x10701006b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP4_IP3_PKT_W1C" , 0x10701008b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP5_IP3_PKT_W1C" , 0x1070100ab6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP6_IP3_PKT_W1C" , 0x1070100cb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP7_IP3_PKT_W1C" , 0x1070100eb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP8_IP3_PKT_W1C" , 0x10701010b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP9_IP3_PKT_W1C" , 0x10701012b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP10_IP3_PKT_W1C" , 0x10701014b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP11_IP3_PKT_W1C" , 0x10701016b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP12_IP3_PKT_W1C" , 0x10701018b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP13_IP3_PKT_W1C" , 0x1070101ab6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP14_IP3_PKT_W1C" , 0x1070101cb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP15_IP3_PKT_W1C" , 0x1070101eb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP16_IP3_PKT_W1C" , 0x10701020b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP17_IP3_PKT_W1C" , 0x10701022b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP18_IP3_PKT_W1C" , 0x10701024b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP19_IP3_PKT_W1C" , 0x10701026b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP20_IP3_PKT_W1C" , 0x10701028b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP21_IP3_PKT_W1C" , 0x1070102ab6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP22_IP3_PKT_W1C" , 0x1070102cb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP23_IP3_PKT_W1C" , 0x1070102eb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP24_IP3_PKT_W1C" , 0x10701030b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP25_IP3_PKT_W1C" , 0x10701032b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP26_IP3_PKT_W1C" , 0x10701034b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP27_IP3_PKT_W1C" , 0x10701036b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP28_IP3_PKT_W1C" , 0x10701038b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP29_IP3_PKT_W1C" , 0x1070103ab6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP30_IP3_PKT_W1C" , 0x1070103cb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP31_IP3_PKT_W1C" , 0x1070103eb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP0_IP3_PKT_W1S" , 0x10701000a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP1_IP3_PKT_W1S" , 0x10701002a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP2_IP3_PKT_W1S" , 0x10701004a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP3_IP3_PKT_W1S" , 0x10701006a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP4_IP3_PKT_W1S" , 0x10701008a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP5_IP3_PKT_W1S" , 0x1070100aa6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP6_IP3_PKT_W1S" , 0x1070100ca6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP7_IP3_PKT_W1S" , 0x1070100ea6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP8_IP3_PKT_W1S" , 0x10701010a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP9_IP3_PKT_W1S" , 0x10701012a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP10_IP3_PKT_W1S" , 0x10701014a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP11_IP3_PKT_W1S" , 0x10701016a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP12_IP3_PKT_W1S" , 0x10701018a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP13_IP3_PKT_W1S" , 0x1070101aa6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP14_IP3_PKT_W1S" , 0x1070101ca6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP15_IP3_PKT_W1S" , 0x1070101ea6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP16_IP3_PKT_W1S" , 0x10701020a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP17_IP3_PKT_W1S" , 0x10701022a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP18_IP3_PKT_W1S" , 0x10701024a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP19_IP3_PKT_W1S" , 0x10701026a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP20_IP3_PKT_W1S" , 0x10701028a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP21_IP3_PKT_W1S" , 0x1070102aa6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP22_IP3_PKT_W1S" , 0x1070102ca6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP23_IP3_PKT_W1S" , 0x1070102ea6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP24_IP3_PKT_W1S" , 0x10701030a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP25_IP3_PKT_W1S" , 0x10701032a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP26_IP3_PKT_W1S" , 0x10701034a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP27_IP3_PKT_W1S" , 0x10701036a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP28_IP3_PKT_W1S" , 0x10701038a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP29_IP3_PKT_W1S" , 0x1070103aa6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP30_IP3_PKT_W1S" , 0x1070103ca6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP31_IP3_PKT_W1S" , 0x1070103ea6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP0_IP3_RML" , 0x1070100092200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP1_IP3_RML" , 0x1070100292200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP2_IP3_RML" , 0x1070100492200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP3_IP3_RML" , 0x1070100692200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP4_IP3_RML" , 0x1070100892200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP5_IP3_RML" , 0x1070100a92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP6_IP3_RML" , 0x1070100c92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP7_IP3_RML" , 0x1070100e92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP8_IP3_RML" , 0x1070101092200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP9_IP3_RML" , 0x1070101292200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP10_IP3_RML" , 0x1070101492200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP11_IP3_RML" , 0x1070101692200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP12_IP3_RML" , 0x1070101892200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP13_IP3_RML" , 0x1070101a92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP14_IP3_RML" , 0x1070101c92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP15_IP3_RML" , 0x1070101e92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP16_IP3_RML" , 0x1070102092200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP17_IP3_RML" , 0x1070102292200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP18_IP3_RML" , 0x1070102492200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP19_IP3_RML" , 0x1070102692200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP20_IP3_RML" , 0x1070102892200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP21_IP3_RML" , 0x1070102a92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP22_IP3_RML" , 0x1070102c92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP23_IP3_RML" , 0x1070102e92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP24_IP3_RML" , 0x1070103092200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP25_IP3_RML" , 0x1070103292200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP26_IP3_RML" , 0x1070103492200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP27_IP3_RML" , 0x1070103692200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP28_IP3_RML" , 0x1070103892200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP29_IP3_RML" , 0x1070103a92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP30_IP3_RML" , 0x1070103c92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP31_IP3_RML" , 0x1070103e92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP0_IP3_RML_W1C" , 0x10701000b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP1_IP3_RML_W1C" , 0x10701002b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP2_IP3_RML_W1C" , 0x10701004b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP3_IP3_RML_W1C" , 0x10701006b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP4_IP3_RML_W1C" , 0x10701008b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP5_IP3_RML_W1C" , 0x1070100ab2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP6_IP3_RML_W1C" , 0x1070100cb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP7_IP3_RML_W1C" , 0x1070100eb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP8_IP3_RML_W1C" , 0x10701010b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP9_IP3_RML_W1C" , 0x10701012b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP10_IP3_RML_W1C" , 0x10701014b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP11_IP3_RML_W1C" , 0x10701016b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP12_IP3_RML_W1C" , 0x10701018b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP13_IP3_RML_W1C" , 0x1070101ab2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP14_IP3_RML_W1C" , 0x1070101cb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP15_IP3_RML_W1C" , 0x1070101eb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP16_IP3_RML_W1C" , 0x10701020b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP17_IP3_RML_W1C" , 0x10701022b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP18_IP3_RML_W1C" , 0x10701024b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP19_IP3_RML_W1C" , 0x10701026b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP20_IP3_RML_W1C" , 0x10701028b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP21_IP3_RML_W1C" , 0x1070102ab2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP22_IP3_RML_W1C" , 0x1070102cb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP23_IP3_RML_W1C" , 0x1070102eb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP24_IP3_RML_W1C" , 0x10701030b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP25_IP3_RML_W1C" , 0x10701032b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP26_IP3_RML_W1C" , 0x10701034b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP27_IP3_RML_W1C" , 0x10701036b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP28_IP3_RML_W1C" , 0x10701038b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP29_IP3_RML_W1C" , 0x1070103ab2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP30_IP3_RML_W1C" , 0x1070103cb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP31_IP3_RML_W1C" , 0x1070103eb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP0_IP3_RML_W1S" , 0x10701000a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP1_IP3_RML_W1S" , 0x10701002a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP2_IP3_RML_W1S" , 0x10701004a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP3_IP3_RML_W1S" , 0x10701006a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP4_IP3_RML_W1S" , 0x10701008a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP5_IP3_RML_W1S" , 0x1070100aa2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP6_IP3_RML_W1S" , 0x1070100ca2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP7_IP3_RML_W1S" , 0x1070100ea2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP8_IP3_RML_W1S" , 0x10701010a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP9_IP3_RML_W1S" , 0x10701012a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP10_IP3_RML_W1S" , 0x10701014a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP11_IP3_RML_W1S" , 0x10701016a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP12_IP3_RML_W1S" , 0x10701018a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP13_IP3_RML_W1S" , 0x1070101aa2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP14_IP3_RML_W1S" , 0x1070101ca2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP15_IP3_RML_W1S" , 0x1070101ea2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP16_IP3_RML_W1S" , 0x10701020a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP17_IP3_RML_W1S" , 0x10701022a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP18_IP3_RML_W1S" , 0x10701024a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP19_IP3_RML_W1S" , 0x10701026a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP20_IP3_RML_W1S" , 0x10701028a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP21_IP3_RML_W1S" , 0x1070102aa2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP22_IP3_RML_W1S" , 0x1070102ca2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP23_IP3_RML_W1S" , 0x1070102ea2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP24_IP3_RML_W1S" , 0x10701030a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP25_IP3_RML_W1S" , 0x10701032a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP26_IP3_RML_W1S" , 0x10701034a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP27_IP3_RML_W1S" , 0x10701036a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP28_IP3_RML_W1S" , 0x10701038a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP29_IP3_RML_W1S" , 0x1070103aa2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP30_IP3_RML_W1S" , 0x1070103ca2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP31_IP3_RML_W1S" , 0x1070103ea2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP0_IP3_WDOG" , 0x1070100091200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP1_IP3_WDOG" , 0x1070100291200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP2_IP3_WDOG" , 0x1070100491200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP3_IP3_WDOG" , 0x1070100691200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP4_IP3_WDOG" , 0x1070100891200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP5_IP3_WDOG" , 0x1070100a91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP6_IP3_WDOG" , 0x1070100c91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP7_IP3_WDOG" , 0x1070100e91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP8_IP3_WDOG" , 0x1070101091200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP9_IP3_WDOG" , 0x1070101291200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP10_IP3_WDOG" , 0x1070101491200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP11_IP3_WDOG" , 0x1070101691200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP12_IP3_WDOG" , 0x1070101891200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP13_IP3_WDOG" , 0x1070101a91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP14_IP3_WDOG" , 0x1070101c91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP15_IP3_WDOG" , 0x1070101e91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP16_IP3_WDOG" , 0x1070102091200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP17_IP3_WDOG" , 0x1070102291200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP18_IP3_WDOG" , 0x1070102491200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP19_IP3_WDOG" , 0x1070102691200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP20_IP3_WDOG" , 0x1070102891200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP21_IP3_WDOG" , 0x1070102a91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP22_IP3_WDOG" , 0x1070102c91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP23_IP3_WDOG" , 0x1070102e91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP24_IP3_WDOG" , 0x1070103091200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP25_IP3_WDOG" , 0x1070103291200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP26_IP3_WDOG" , 0x1070103491200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP27_IP3_WDOG" , 0x1070103691200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP28_IP3_WDOG" , 0x1070103891200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP29_IP3_WDOG" , 0x1070103a91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP30_IP3_WDOG" , 0x1070103c91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP31_IP3_WDOG" , 0x1070103e91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP0_IP3_WDOG_W1C" , 0x10701000b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP1_IP3_WDOG_W1C" , 0x10701002b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP2_IP3_WDOG_W1C" , 0x10701004b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP3_IP3_WDOG_W1C" , 0x10701006b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP4_IP3_WDOG_W1C" , 0x10701008b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP5_IP3_WDOG_W1C" , 0x1070100ab1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP6_IP3_WDOG_W1C" , 0x1070100cb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP7_IP3_WDOG_W1C" , 0x1070100eb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP8_IP3_WDOG_W1C" , 0x10701010b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP9_IP3_WDOG_W1C" , 0x10701012b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP10_IP3_WDOG_W1C" , 0x10701014b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP11_IP3_WDOG_W1C" , 0x10701016b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP12_IP3_WDOG_W1C" , 0x10701018b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP13_IP3_WDOG_W1C" , 0x1070101ab1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP14_IP3_WDOG_W1C" , 0x1070101cb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP15_IP3_WDOG_W1C" , 0x1070101eb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP16_IP3_WDOG_W1C" , 0x10701020b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP17_IP3_WDOG_W1C" , 0x10701022b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP18_IP3_WDOG_W1C" , 0x10701024b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP19_IP3_WDOG_W1C" , 0x10701026b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP20_IP3_WDOG_W1C" , 0x10701028b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP21_IP3_WDOG_W1C" , 0x1070102ab1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP22_IP3_WDOG_W1C" , 0x1070102cb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP23_IP3_WDOG_W1C" , 0x1070102eb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP24_IP3_WDOG_W1C" , 0x10701030b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP25_IP3_WDOG_W1C" , 0x10701032b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP26_IP3_WDOG_W1C" , 0x10701034b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP27_IP3_WDOG_W1C" , 0x10701036b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP28_IP3_WDOG_W1C" , 0x10701038b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP29_IP3_WDOG_W1C" , 0x1070103ab1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP30_IP3_WDOG_W1C" , 0x1070103cb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP31_IP3_WDOG_W1C" , 0x1070103eb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP0_IP3_WDOG_W1S" , 0x10701000a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP1_IP3_WDOG_W1S" , 0x10701002a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP2_IP3_WDOG_W1S" , 0x10701004a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP3_IP3_WDOG_W1S" , 0x10701006a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP4_IP3_WDOG_W1S" , 0x10701008a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP5_IP3_WDOG_W1S" , 0x1070100aa1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP6_IP3_WDOG_W1S" , 0x1070100ca1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP7_IP3_WDOG_W1S" , 0x1070100ea1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP8_IP3_WDOG_W1S" , 0x10701010a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP9_IP3_WDOG_W1S" , 0x10701012a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP10_IP3_WDOG_W1S" , 0x10701014a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP11_IP3_WDOG_W1S" , 0x10701016a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP12_IP3_WDOG_W1S" , 0x10701018a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP13_IP3_WDOG_W1S" , 0x1070101aa1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP14_IP3_WDOG_W1S" , 0x1070101ca1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP15_IP3_WDOG_W1S" , 0x1070101ea1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP16_IP3_WDOG_W1S" , 0x10701020a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP17_IP3_WDOG_W1S" , 0x10701022a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP18_IP3_WDOG_W1S" , 0x10701024a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP19_IP3_WDOG_W1S" , 0x10701026a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP20_IP3_WDOG_W1S" , 0x10701028a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP21_IP3_WDOG_W1S" , 0x1070102aa1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP22_IP3_WDOG_W1S" , 0x1070102ca1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP23_IP3_WDOG_W1S" , 0x1070102ea1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP24_IP3_WDOG_W1S" , 0x10701030a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP25_IP3_WDOG_W1S" , 0x10701032a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP26_IP3_WDOG_W1S" , 0x10701034a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP27_IP3_WDOG_W1S" , 0x10701036a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP28_IP3_WDOG_W1S" , 0x10701038a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP29_IP3_WDOG_W1S" , 0x1070103aa1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP30_IP3_WDOG_W1S" , 0x1070103ca1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP31_IP3_WDOG_W1S" , 0x1070103ea1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP0_IP3_WRKQ" , 0x1070100090200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP1_IP3_WRKQ" , 0x1070100290200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP2_IP3_WRKQ" , 0x1070100490200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP3_IP3_WRKQ" , 0x1070100690200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP4_IP3_WRKQ" , 0x1070100890200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP5_IP3_WRKQ" , 0x1070100a90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP6_IP3_WRKQ" , 0x1070100c90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP7_IP3_WRKQ" , 0x1070100e90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP8_IP3_WRKQ" , 0x1070101090200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP9_IP3_WRKQ" , 0x1070101290200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP10_IP3_WRKQ" , 0x1070101490200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP11_IP3_WRKQ" , 0x1070101690200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP12_IP3_WRKQ" , 0x1070101890200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP13_IP3_WRKQ" , 0x1070101a90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP14_IP3_WRKQ" , 0x1070101c90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP15_IP3_WRKQ" , 0x1070101e90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP16_IP3_WRKQ" , 0x1070102090200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP17_IP3_WRKQ" , 0x1070102290200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP18_IP3_WRKQ" , 0x1070102490200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP19_IP3_WRKQ" , 0x1070102690200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP20_IP3_WRKQ" , 0x1070102890200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP21_IP3_WRKQ" , 0x1070102a90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP22_IP3_WRKQ" , 0x1070102c90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP23_IP3_WRKQ" , 0x1070102e90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP24_IP3_WRKQ" , 0x1070103090200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP25_IP3_WRKQ" , 0x1070103290200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP26_IP3_WRKQ" , 0x1070103490200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP27_IP3_WRKQ" , 0x1070103690200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP28_IP3_WRKQ" , 0x1070103890200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP29_IP3_WRKQ" , 0x1070103a90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP30_IP3_WRKQ" , 0x1070103c90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP31_IP3_WRKQ" , 0x1070103e90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP0_IP3_WRKQ_W1C" , 0x10701000b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP1_IP3_WRKQ_W1C" , 0x10701002b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP2_IP3_WRKQ_W1C" , 0x10701004b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP3_IP3_WRKQ_W1C" , 0x10701006b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP4_IP3_WRKQ_W1C" , 0x10701008b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP5_IP3_WRKQ_W1C" , 0x1070100ab0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP6_IP3_WRKQ_W1C" , 0x1070100cb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP7_IP3_WRKQ_W1C" , 0x1070100eb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP8_IP3_WRKQ_W1C" , 0x10701010b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP9_IP3_WRKQ_W1C" , 0x10701012b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP10_IP3_WRKQ_W1C" , 0x10701014b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP11_IP3_WRKQ_W1C" , 0x10701016b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP12_IP3_WRKQ_W1C" , 0x10701018b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP13_IP3_WRKQ_W1C" , 0x1070101ab0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP14_IP3_WRKQ_W1C" , 0x1070101cb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP15_IP3_WRKQ_W1C" , 0x1070101eb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP16_IP3_WRKQ_W1C" , 0x10701020b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP17_IP3_WRKQ_W1C" , 0x10701022b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP18_IP3_WRKQ_W1C" , 0x10701024b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP19_IP3_WRKQ_W1C" , 0x10701026b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP20_IP3_WRKQ_W1C" , 0x10701028b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP21_IP3_WRKQ_W1C" , 0x1070102ab0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP22_IP3_WRKQ_W1C" , 0x1070102cb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP23_IP3_WRKQ_W1C" , 0x1070102eb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP24_IP3_WRKQ_W1C" , 0x10701030b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP25_IP3_WRKQ_W1C" , 0x10701032b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP26_IP3_WRKQ_W1C" , 0x10701034b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP27_IP3_WRKQ_W1C" , 0x10701036b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP28_IP3_WRKQ_W1C" , 0x10701038b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP29_IP3_WRKQ_W1C" , 0x1070103ab0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP30_IP3_WRKQ_W1C" , 0x1070103cb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP31_IP3_WRKQ_W1C" , 0x1070103eb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP0_IP3_WRKQ_W1S" , 0x10701000a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP1_IP3_WRKQ_W1S" , 0x10701002a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP2_IP3_WRKQ_W1S" , 0x10701004a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP3_IP3_WRKQ_W1S" , 0x10701006a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP4_IP3_WRKQ_W1S" , 0x10701008a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP5_IP3_WRKQ_W1S" , 0x1070100aa0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP6_IP3_WRKQ_W1S" , 0x1070100ca0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP7_IP3_WRKQ_W1S" , 0x1070100ea0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP8_IP3_WRKQ_W1S" , 0x10701010a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP9_IP3_WRKQ_W1S" , 0x10701012a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP10_IP3_WRKQ_W1S" , 0x10701014a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP11_IP3_WRKQ_W1S" , 0x10701016a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP12_IP3_WRKQ_W1S" , 0x10701018a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP13_IP3_WRKQ_W1S" , 0x1070101aa0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP14_IP3_WRKQ_W1S" , 0x1070101ca0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP15_IP3_WRKQ_W1S" , 0x1070101ea0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP16_IP3_WRKQ_W1S" , 0x10701020a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP17_IP3_WRKQ_W1S" , 0x10701022a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP18_IP3_WRKQ_W1S" , 0x10701024a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP19_IP3_WRKQ_W1S" , 0x10701026a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP20_IP3_WRKQ_W1S" , 0x10701028a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP21_IP3_WRKQ_W1S" , 0x1070102aa0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP22_IP3_WRKQ_W1S" , 0x1070102ca0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP23_IP3_WRKQ_W1S" , 0x1070102ea0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP24_IP3_WRKQ_W1S" , 0x10701030a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP25_IP3_WRKQ_W1S" , 0x10701032a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP26_IP3_WRKQ_W1S" , 0x10701034a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP27_IP3_WRKQ_W1S" , 0x10701036a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP28_IP3_WRKQ_W1S" , 0x10701038a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP29_IP3_WRKQ_W1S" , 0x1070103aa0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP30_IP3_WRKQ_W1S" , 0x1070103ca0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP31_IP3_WRKQ_W1S" , 0x1070103ea0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP0_IP4_GPIO" , 0x1070100097400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP1_IP4_GPIO" , 0x1070100297400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP2_IP4_GPIO" , 0x1070100497400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP3_IP4_GPIO" , 0x1070100697400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP4_IP4_GPIO" , 0x1070100897400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP5_IP4_GPIO" , 0x1070100a97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP6_IP4_GPIO" , 0x1070100c97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP7_IP4_GPIO" , 0x1070100e97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP8_IP4_GPIO" , 0x1070101097400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP9_IP4_GPIO" , 0x1070101297400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP10_IP4_GPIO" , 0x1070101497400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP11_IP4_GPIO" , 0x1070101697400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP12_IP4_GPIO" , 0x1070101897400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP13_IP4_GPIO" , 0x1070101a97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP14_IP4_GPIO" , 0x1070101c97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP15_IP4_GPIO" , 0x1070101e97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP16_IP4_GPIO" , 0x1070102097400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP17_IP4_GPIO" , 0x1070102297400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP18_IP4_GPIO" , 0x1070102497400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP19_IP4_GPIO" , 0x1070102697400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP20_IP4_GPIO" , 0x1070102897400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP21_IP4_GPIO" , 0x1070102a97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP22_IP4_GPIO" , 0x1070102c97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP23_IP4_GPIO" , 0x1070102e97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP24_IP4_GPIO" , 0x1070103097400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP25_IP4_GPIO" , 0x1070103297400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP26_IP4_GPIO" , 0x1070103497400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP27_IP4_GPIO" , 0x1070103697400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP28_IP4_GPIO" , 0x1070103897400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP29_IP4_GPIO" , 0x1070103a97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP30_IP4_GPIO" , 0x1070103c97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP31_IP4_GPIO" , 0x1070103e97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP0_IP4_GPIO_W1C" , 0x10701000b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP1_IP4_GPIO_W1C" , 0x10701002b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP2_IP4_GPIO_W1C" , 0x10701004b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP3_IP4_GPIO_W1C" , 0x10701006b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP4_IP4_GPIO_W1C" , 0x10701008b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP5_IP4_GPIO_W1C" , 0x1070100ab7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP6_IP4_GPIO_W1C" , 0x1070100cb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP7_IP4_GPIO_W1C" , 0x1070100eb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP8_IP4_GPIO_W1C" , 0x10701010b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP9_IP4_GPIO_W1C" , 0x10701012b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP10_IP4_GPIO_W1C" , 0x10701014b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP11_IP4_GPIO_W1C" , 0x10701016b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP12_IP4_GPIO_W1C" , 0x10701018b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP13_IP4_GPIO_W1C" , 0x1070101ab7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP14_IP4_GPIO_W1C" , 0x1070101cb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP15_IP4_GPIO_W1C" , 0x1070101eb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP16_IP4_GPIO_W1C" , 0x10701020b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP17_IP4_GPIO_W1C" , 0x10701022b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP18_IP4_GPIO_W1C" , 0x10701024b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP19_IP4_GPIO_W1C" , 0x10701026b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP20_IP4_GPIO_W1C" , 0x10701028b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP21_IP4_GPIO_W1C" , 0x1070102ab7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP22_IP4_GPIO_W1C" , 0x1070102cb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP23_IP4_GPIO_W1C" , 0x1070102eb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP24_IP4_GPIO_W1C" , 0x10701030b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP25_IP4_GPIO_W1C" , 0x10701032b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP26_IP4_GPIO_W1C" , 0x10701034b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP27_IP4_GPIO_W1C" , 0x10701036b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP28_IP4_GPIO_W1C" , 0x10701038b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP29_IP4_GPIO_W1C" , 0x1070103ab7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP30_IP4_GPIO_W1C" , 0x1070103cb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP31_IP4_GPIO_W1C" , 0x1070103eb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP0_IP4_GPIO_W1S" , 0x10701000a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP1_IP4_GPIO_W1S" , 0x10701002a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP2_IP4_GPIO_W1S" , 0x10701004a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP3_IP4_GPIO_W1S" , 0x10701006a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP4_IP4_GPIO_W1S" , 0x10701008a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP5_IP4_GPIO_W1S" , 0x1070100aa7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP6_IP4_GPIO_W1S" , 0x1070100ca7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP7_IP4_GPIO_W1S" , 0x1070100ea7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP8_IP4_GPIO_W1S" , 0x10701010a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP9_IP4_GPIO_W1S" , 0x10701012a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP10_IP4_GPIO_W1S" , 0x10701014a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP11_IP4_GPIO_W1S" , 0x10701016a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP12_IP4_GPIO_W1S" , 0x10701018a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP13_IP4_GPIO_W1S" , 0x1070101aa7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP14_IP4_GPIO_W1S" , 0x1070101ca7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP15_IP4_GPIO_W1S" , 0x1070101ea7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP16_IP4_GPIO_W1S" , 0x10701020a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP17_IP4_GPIO_W1S" , 0x10701022a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP18_IP4_GPIO_W1S" , 0x10701024a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP19_IP4_GPIO_W1S" , 0x10701026a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP20_IP4_GPIO_W1S" , 0x10701028a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP21_IP4_GPIO_W1S" , 0x1070102aa7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP22_IP4_GPIO_W1S" , 0x1070102ca7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP23_IP4_GPIO_W1S" , 0x1070102ea7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP24_IP4_GPIO_W1S" , 0x10701030a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP25_IP4_GPIO_W1S" , 0x10701032a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP26_IP4_GPIO_W1S" , 0x10701034a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP27_IP4_GPIO_W1S" , 0x10701036a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP28_IP4_GPIO_W1S" , 0x10701038a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP29_IP4_GPIO_W1S" , 0x1070103aa7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP30_IP4_GPIO_W1S" , 0x1070103ca7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP31_IP4_GPIO_W1S" , 0x1070103ea7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP0_IP4_IO" , 0x1070100094400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP1_IP4_IO" , 0x1070100294400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP2_IP4_IO" , 0x1070100494400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP3_IP4_IO" , 0x1070100694400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP4_IP4_IO" , 0x1070100894400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP5_IP4_IO" , 0x1070100a94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP6_IP4_IO" , 0x1070100c94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP7_IP4_IO" , 0x1070100e94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP8_IP4_IO" , 0x1070101094400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP9_IP4_IO" , 0x1070101294400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP10_IP4_IO" , 0x1070101494400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP11_IP4_IO" , 0x1070101694400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP12_IP4_IO" , 0x1070101894400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP13_IP4_IO" , 0x1070101a94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP14_IP4_IO" , 0x1070101c94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP15_IP4_IO" , 0x1070101e94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP16_IP4_IO" , 0x1070102094400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP17_IP4_IO" , 0x1070102294400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP18_IP4_IO" , 0x1070102494400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP19_IP4_IO" , 0x1070102694400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP20_IP4_IO" , 0x1070102894400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP21_IP4_IO" , 0x1070102a94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP22_IP4_IO" , 0x1070102c94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP23_IP4_IO" , 0x1070102e94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP24_IP4_IO" , 0x1070103094400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP25_IP4_IO" , 0x1070103294400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP26_IP4_IO" , 0x1070103494400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP27_IP4_IO" , 0x1070103694400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP28_IP4_IO" , 0x1070103894400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP29_IP4_IO" , 0x1070103a94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP30_IP4_IO" , 0x1070103c94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP31_IP4_IO" , 0x1070103e94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP0_IP4_IO_W1C" , 0x10701000b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP1_IP4_IO_W1C" , 0x10701002b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP2_IP4_IO_W1C" , 0x10701004b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP3_IP4_IO_W1C" , 0x10701006b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP4_IP4_IO_W1C" , 0x10701008b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP5_IP4_IO_W1C" , 0x1070100ab4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP6_IP4_IO_W1C" , 0x1070100cb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP7_IP4_IO_W1C" , 0x1070100eb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP8_IP4_IO_W1C" , 0x10701010b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP9_IP4_IO_W1C" , 0x10701012b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP10_IP4_IO_W1C" , 0x10701014b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP11_IP4_IO_W1C" , 0x10701016b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP12_IP4_IO_W1C" , 0x10701018b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP13_IP4_IO_W1C" , 0x1070101ab4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP14_IP4_IO_W1C" , 0x1070101cb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP15_IP4_IO_W1C" , 0x1070101eb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP16_IP4_IO_W1C" , 0x10701020b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP17_IP4_IO_W1C" , 0x10701022b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP18_IP4_IO_W1C" , 0x10701024b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP19_IP4_IO_W1C" , 0x10701026b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP20_IP4_IO_W1C" , 0x10701028b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP21_IP4_IO_W1C" , 0x1070102ab4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP22_IP4_IO_W1C" , 0x1070102cb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP23_IP4_IO_W1C" , 0x1070102eb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP24_IP4_IO_W1C" , 0x10701030b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP25_IP4_IO_W1C" , 0x10701032b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP26_IP4_IO_W1C" , 0x10701034b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP27_IP4_IO_W1C" , 0x10701036b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP28_IP4_IO_W1C" , 0x10701038b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP29_IP4_IO_W1C" , 0x1070103ab4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP30_IP4_IO_W1C" , 0x1070103cb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP31_IP4_IO_W1C" , 0x1070103eb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP0_IP4_IO_W1S" , 0x10701000a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP1_IP4_IO_W1S" , 0x10701002a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP2_IP4_IO_W1S" , 0x10701004a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP3_IP4_IO_W1S" , 0x10701006a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP4_IP4_IO_W1S" , 0x10701008a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP5_IP4_IO_W1S" , 0x1070100aa4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP6_IP4_IO_W1S" , 0x1070100ca4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP7_IP4_IO_W1S" , 0x1070100ea4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP8_IP4_IO_W1S" , 0x10701010a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP9_IP4_IO_W1S" , 0x10701012a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP10_IP4_IO_W1S" , 0x10701014a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP11_IP4_IO_W1S" , 0x10701016a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP12_IP4_IO_W1S" , 0x10701018a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP13_IP4_IO_W1S" , 0x1070101aa4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP14_IP4_IO_W1S" , 0x1070101ca4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP15_IP4_IO_W1S" , 0x1070101ea4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP16_IP4_IO_W1S" , 0x10701020a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP17_IP4_IO_W1S" , 0x10701022a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP18_IP4_IO_W1S" , 0x10701024a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP19_IP4_IO_W1S" , 0x10701026a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP20_IP4_IO_W1S" , 0x10701028a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP21_IP4_IO_W1S" , 0x1070102aa4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP22_IP4_IO_W1S" , 0x1070102ca4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP23_IP4_IO_W1S" , 0x1070102ea4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP24_IP4_IO_W1S" , 0x10701030a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP25_IP4_IO_W1S" , 0x10701032a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP26_IP4_IO_W1S" , 0x10701034a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP27_IP4_IO_W1S" , 0x10701036a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP28_IP4_IO_W1S" , 0x10701038a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP29_IP4_IO_W1S" , 0x1070103aa4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP30_IP4_IO_W1S" , 0x1070103ca4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP31_IP4_IO_W1S" , 0x1070103ea4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP0_IP4_MBOX" , 0x1070100098400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP1_IP4_MBOX" , 0x1070100298400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP2_IP4_MBOX" , 0x1070100498400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP3_IP4_MBOX" , 0x1070100698400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP4_IP4_MBOX" , 0x1070100898400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP5_IP4_MBOX" , 0x1070100a98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP6_IP4_MBOX" , 0x1070100c98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP7_IP4_MBOX" , 0x1070100e98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP8_IP4_MBOX" , 0x1070101098400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP9_IP4_MBOX" , 0x1070101298400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP10_IP4_MBOX" , 0x1070101498400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP11_IP4_MBOX" , 0x1070101698400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP12_IP4_MBOX" , 0x1070101898400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP13_IP4_MBOX" , 0x1070101a98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP14_IP4_MBOX" , 0x1070101c98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP15_IP4_MBOX" , 0x1070101e98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP16_IP4_MBOX" , 0x1070102098400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP17_IP4_MBOX" , 0x1070102298400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP18_IP4_MBOX" , 0x1070102498400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP19_IP4_MBOX" , 0x1070102698400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP20_IP4_MBOX" , 0x1070102898400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP21_IP4_MBOX" , 0x1070102a98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP22_IP4_MBOX" , 0x1070102c98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP23_IP4_MBOX" , 0x1070102e98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP24_IP4_MBOX" , 0x1070103098400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP25_IP4_MBOX" , 0x1070103298400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP26_IP4_MBOX" , 0x1070103498400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP27_IP4_MBOX" , 0x1070103698400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP28_IP4_MBOX" , 0x1070103898400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP29_IP4_MBOX" , 0x1070103a98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP30_IP4_MBOX" , 0x1070103c98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP31_IP4_MBOX" , 0x1070103e98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP0_IP4_MBOX_W1C" , 0x10701000b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP1_IP4_MBOX_W1C" , 0x10701002b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP2_IP4_MBOX_W1C" , 0x10701004b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP3_IP4_MBOX_W1C" , 0x10701006b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP4_IP4_MBOX_W1C" , 0x10701008b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP5_IP4_MBOX_W1C" , 0x1070100ab8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP6_IP4_MBOX_W1C" , 0x1070100cb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP7_IP4_MBOX_W1C" , 0x1070100eb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP8_IP4_MBOX_W1C" , 0x10701010b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP9_IP4_MBOX_W1C" , 0x10701012b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP10_IP4_MBOX_W1C" , 0x10701014b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP11_IP4_MBOX_W1C" , 0x10701016b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP12_IP4_MBOX_W1C" , 0x10701018b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP13_IP4_MBOX_W1C" , 0x1070101ab8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP14_IP4_MBOX_W1C" , 0x1070101cb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP15_IP4_MBOX_W1C" , 0x1070101eb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP16_IP4_MBOX_W1C" , 0x10701020b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP17_IP4_MBOX_W1C" , 0x10701022b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP18_IP4_MBOX_W1C" , 0x10701024b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP19_IP4_MBOX_W1C" , 0x10701026b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP20_IP4_MBOX_W1C" , 0x10701028b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP21_IP4_MBOX_W1C" , 0x1070102ab8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP22_IP4_MBOX_W1C" , 0x1070102cb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP23_IP4_MBOX_W1C" , 0x1070102eb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP24_IP4_MBOX_W1C" , 0x10701030b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP25_IP4_MBOX_W1C" , 0x10701032b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP26_IP4_MBOX_W1C" , 0x10701034b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP27_IP4_MBOX_W1C" , 0x10701036b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP28_IP4_MBOX_W1C" , 0x10701038b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP29_IP4_MBOX_W1C" , 0x1070103ab8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP30_IP4_MBOX_W1C" , 0x1070103cb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP31_IP4_MBOX_W1C" , 0x1070103eb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP0_IP4_MBOX_W1S" , 0x10701000a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP1_IP4_MBOX_W1S" , 0x10701002a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP2_IP4_MBOX_W1S" , 0x10701004a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP3_IP4_MBOX_W1S" , 0x10701006a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP4_IP4_MBOX_W1S" , 0x10701008a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP5_IP4_MBOX_W1S" , 0x1070100aa8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP6_IP4_MBOX_W1S" , 0x1070100ca8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP7_IP4_MBOX_W1S" , 0x1070100ea8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP8_IP4_MBOX_W1S" , 0x10701010a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP9_IP4_MBOX_W1S" , 0x10701012a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP10_IP4_MBOX_W1S" , 0x10701014a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP11_IP4_MBOX_W1S" , 0x10701016a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP12_IP4_MBOX_W1S" , 0x10701018a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP13_IP4_MBOX_W1S" , 0x1070101aa8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP14_IP4_MBOX_W1S" , 0x1070101ca8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP15_IP4_MBOX_W1S" , 0x1070101ea8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP16_IP4_MBOX_W1S" , 0x10701020a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP17_IP4_MBOX_W1S" , 0x10701022a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP18_IP4_MBOX_W1S" , 0x10701024a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP19_IP4_MBOX_W1S" , 0x10701026a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP20_IP4_MBOX_W1S" , 0x10701028a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP21_IP4_MBOX_W1S" , 0x1070102aa8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP22_IP4_MBOX_W1S" , 0x1070102ca8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP23_IP4_MBOX_W1S" , 0x1070102ea8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP24_IP4_MBOX_W1S" , 0x10701030a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP25_IP4_MBOX_W1S" , 0x10701032a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP26_IP4_MBOX_W1S" , 0x10701034a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP27_IP4_MBOX_W1S" , 0x10701036a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP28_IP4_MBOX_W1S" , 0x10701038a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP29_IP4_MBOX_W1S" , 0x1070103aa8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP30_IP4_MBOX_W1S" , 0x1070103ca8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP31_IP4_MBOX_W1S" , 0x1070103ea8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP0_IP4_MEM" , 0x1070100095400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP1_IP4_MEM" , 0x1070100295400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP2_IP4_MEM" , 0x1070100495400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP3_IP4_MEM" , 0x1070100695400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP4_IP4_MEM" , 0x1070100895400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP5_IP4_MEM" , 0x1070100a95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP6_IP4_MEM" , 0x1070100c95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP7_IP4_MEM" , 0x1070100e95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP8_IP4_MEM" , 0x1070101095400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP9_IP4_MEM" , 0x1070101295400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP10_IP4_MEM" , 0x1070101495400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP11_IP4_MEM" , 0x1070101695400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP12_IP4_MEM" , 0x1070101895400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP13_IP4_MEM" , 0x1070101a95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP14_IP4_MEM" , 0x1070101c95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP15_IP4_MEM" , 0x1070101e95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP16_IP4_MEM" , 0x1070102095400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP17_IP4_MEM" , 0x1070102295400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP18_IP4_MEM" , 0x1070102495400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP19_IP4_MEM" , 0x1070102695400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP20_IP4_MEM" , 0x1070102895400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP21_IP4_MEM" , 0x1070102a95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP22_IP4_MEM" , 0x1070102c95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP23_IP4_MEM" , 0x1070102e95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP24_IP4_MEM" , 0x1070103095400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP25_IP4_MEM" , 0x1070103295400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP26_IP4_MEM" , 0x1070103495400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP27_IP4_MEM" , 0x1070103695400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP28_IP4_MEM" , 0x1070103895400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP29_IP4_MEM" , 0x1070103a95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP30_IP4_MEM" , 0x1070103c95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP31_IP4_MEM" , 0x1070103e95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP0_IP4_MEM_W1C" , 0x10701000b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP1_IP4_MEM_W1C" , 0x10701002b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP2_IP4_MEM_W1C" , 0x10701004b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP3_IP4_MEM_W1C" , 0x10701006b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP4_IP4_MEM_W1C" , 0x10701008b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP5_IP4_MEM_W1C" , 0x1070100ab5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP6_IP4_MEM_W1C" , 0x1070100cb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP7_IP4_MEM_W1C" , 0x1070100eb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP8_IP4_MEM_W1C" , 0x10701010b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP9_IP4_MEM_W1C" , 0x10701012b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP10_IP4_MEM_W1C" , 0x10701014b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP11_IP4_MEM_W1C" , 0x10701016b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP12_IP4_MEM_W1C" , 0x10701018b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP13_IP4_MEM_W1C" , 0x1070101ab5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP14_IP4_MEM_W1C" , 0x1070101cb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP15_IP4_MEM_W1C" , 0x1070101eb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP16_IP4_MEM_W1C" , 0x10701020b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP17_IP4_MEM_W1C" , 0x10701022b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP18_IP4_MEM_W1C" , 0x10701024b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP19_IP4_MEM_W1C" , 0x10701026b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP20_IP4_MEM_W1C" , 0x10701028b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP21_IP4_MEM_W1C" , 0x1070102ab5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP22_IP4_MEM_W1C" , 0x1070102cb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP23_IP4_MEM_W1C" , 0x1070102eb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP24_IP4_MEM_W1C" , 0x10701030b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP25_IP4_MEM_W1C" , 0x10701032b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP26_IP4_MEM_W1C" , 0x10701034b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP27_IP4_MEM_W1C" , 0x10701036b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP28_IP4_MEM_W1C" , 0x10701038b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP29_IP4_MEM_W1C" , 0x1070103ab5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP30_IP4_MEM_W1C" , 0x1070103cb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP31_IP4_MEM_W1C" , 0x1070103eb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP0_IP4_MEM_W1S" , 0x10701000a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP1_IP4_MEM_W1S" , 0x10701002a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP2_IP4_MEM_W1S" , 0x10701004a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP3_IP4_MEM_W1S" , 0x10701006a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP4_IP4_MEM_W1S" , 0x10701008a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP5_IP4_MEM_W1S" , 0x1070100aa5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP6_IP4_MEM_W1S" , 0x1070100ca5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP7_IP4_MEM_W1S" , 0x1070100ea5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP8_IP4_MEM_W1S" , 0x10701010a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP9_IP4_MEM_W1S" , 0x10701012a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP10_IP4_MEM_W1S" , 0x10701014a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP11_IP4_MEM_W1S" , 0x10701016a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP12_IP4_MEM_W1S" , 0x10701018a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP13_IP4_MEM_W1S" , 0x1070101aa5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP14_IP4_MEM_W1S" , 0x1070101ca5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP15_IP4_MEM_W1S" , 0x1070101ea5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP16_IP4_MEM_W1S" , 0x10701020a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP17_IP4_MEM_W1S" , 0x10701022a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP18_IP4_MEM_W1S" , 0x10701024a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP19_IP4_MEM_W1S" , 0x10701026a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP20_IP4_MEM_W1S" , 0x10701028a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP21_IP4_MEM_W1S" , 0x1070102aa5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP22_IP4_MEM_W1S" , 0x1070102ca5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP23_IP4_MEM_W1S" , 0x1070102ea5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP24_IP4_MEM_W1S" , 0x10701030a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP25_IP4_MEM_W1S" , 0x10701032a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP26_IP4_MEM_W1S" , 0x10701034a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP27_IP4_MEM_W1S" , 0x10701036a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP28_IP4_MEM_W1S" , 0x10701038a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP29_IP4_MEM_W1S" , 0x1070103aa5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP30_IP4_MEM_W1S" , 0x1070103ca5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP31_IP4_MEM_W1S" , 0x1070103ea5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP0_IP4_MIO" , 0x1070100093400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP1_IP4_MIO" , 0x1070100293400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP2_IP4_MIO" , 0x1070100493400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP3_IP4_MIO" , 0x1070100693400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP4_IP4_MIO" , 0x1070100893400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP5_IP4_MIO" , 0x1070100a93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP6_IP4_MIO" , 0x1070100c93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP7_IP4_MIO" , 0x1070100e93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP8_IP4_MIO" , 0x1070101093400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP9_IP4_MIO" , 0x1070101293400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP10_IP4_MIO" , 0x1070101493400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP11_IP4_MIO" , 0x1070101693400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP12_IP4_MIO" , 0x1070101893400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP13_IP4_MIO" , 0x1070101a93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP14_IP4_MIO" , 0x1070101c93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP15_IP4_MIO" , 0x1070101e93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP16_IP4_MIO" , 0x1070102093400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP17_IP4_MIO" , 0x1070102293400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP18_IP4_MIO" , 0x1070102493400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP19_IP4_MIO" , 0x1070102693400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP20_IP4_MIO" , 0x1070102893400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP21_IP4_MIO" , 0x1070102a93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP22_IP4_MIO" , 0x1070102c93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP23_IP4_MIO" , 0x1070102e93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP24_IP4_MIO" , 0x1070103093400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP25_IP4_MIO" , 0x1070103293400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP26_IP4_MIO" , 0x1070103493400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP27_IP4_MIO" , 0x1070103693400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP28_IP4_MIO" , 0x1070103893400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP29_IP4_MIO" , 0x1070103a93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP30_IP4_MIO" , 0x1070103c93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP31_IP4_MIO" , 0x1070103e93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP0_IP4_MIO_W1C" , 0x10701000b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP1_IP4_MIO_W1C" , 0x10701002b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP2_IP4_MIO_W1C" , 0x10701004b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP3_IP4_MIO_W1C" , 0x10701006b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP4_IP4_MIO_W1C" , 0x10701008b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP5_IP4_MIO_W1C" , 0x1070100ab3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP6_IP4_MIO_W1C" , 0x1070100cb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP7_IP4_MIO_W1C" , 0x1070100eb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP8_IP4_MIO_W1C" , 0x10701010b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP9_IP4_MIO_W1C" , 0x10701012b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP10_IP4_MIO_W1C" , 0x10701014b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP11_IP4_MIO_W1C" , 0x10701016b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP12_IP4_MIO_W1C" , 0x10701018b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP13_IP4_MIO_W1C" , 0x1070101ab3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP14_IP4_MIO_W1C" , 0x1070101cb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP15_IP4_MIO_W1C" , 0x1070101eb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP16_IP4_MIO_W1C" , 0x10701020b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP17_IP4_MIO_W1C" , 0x10701022b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP18_IP4_MIO_W1C" , 0x10701024b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP19_IP4_MIO_W1C" , 0x10701026b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP20_IP4_MIO_W1C" , 0x10701028b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP21_IP4_MIO_W1C" , 0x1070102ab3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP22_IP4_MIO_W1C" , 0x1070102cb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP23_IP4_MIO_W1C" , 0x1070102eb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP24_IP4_MIO_W1C" , 0x10701030b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP25_IP4_MIO_W1C" , 0x10701032b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP26_IP4_MIO_W1C" , 0x10701034b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP27_IP4_MIO_W1C" , 0x10701036b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP28_IP4_MIO_W1C" , 0x10701038b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP29_IP4_MIO_W1C" , 0x1070103ab3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP30_IP4_MIO_W1C" , 0x1070103cb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP31_IP4_MIO_W1C" , 0x1070103eb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP0_IP4_MIO_W1S" , 0x10701000a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP1_IP4_MIO_W1S" , 0x10701002a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP2_IP4_MIO_W1S" , 0x10701004a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP3_IP4_MIO_W1S" , 0x10701006a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP4_IP4_MIO_W1S" , 0x10701008a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP5_IP4_MIO_W1S" , 0x1070100aa3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP6_IP4_MIO_W1S" , 0x1070100ca3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP7_IP4_MIO_W1S" , 0x1070100ea3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP8_IP4_MIO_W1S" , 0x10701010a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP9_IP4_MIO_W1S" , 0x10701012a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP10_IP4_MIO_W1S" , 0x10701014a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP11_IP4_MIO_W1S" , 0x10701016a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP12_IP4_MIO_W1S" , 0x10701018a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP13_IP4_MIO_W1S" , 0x1070101aa3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP14_IP4_MIO_W1S" , 0x1070101ca3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP15_IP4_MIO_W1S" , 0x1070101ea3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP16_IP4_MIO_W1S" , 0x10701020a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP17_IP4_MIO_W1S" , 0x10701022a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP18_IP4_MIO_W1S" , 0x10701024a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP19_IP4_MIO_W1S" , 0x10701026a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP20_IP4_MIO_W1S" , 0x10701028a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP21_IP4_MIO_W1S" , 0x1070102aa3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP22_IP4_MIO_W1S" , 0x1070102ca3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP23_IP4_MIO_W1S" , 0x1070102ea3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP24_IP4_MIO_W1S" , 0x10701030a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP25_IP4_MIO_W1S" , 0x10701032a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP26_IP4_MIO_W1S" , 0x10701034a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP27_IP4_MIO_W1S" , 0x10701036a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP28_IP4_MIO_W1S" , 0x10701038a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP29_IP4_MIO_W1S" , 0x1070103aa3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP30_IP4_MIO_W1S" , 0x1070103ca3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP31_IP4_MIO_W1S" , 0x1070103ea3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP0_IP4_PKT" , 0x1070100096400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP1_IP4_PKT" , 0x1070100296400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP2_IP4_PKT" , 0x1070100496400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP3_IP4_PKT" , 0x1070100696400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP4_IP4_PKT" , 0x1070100896400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP5_IP4_PKT" , 0x1070100a96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP6_IP4_PKT" , 0x1070100c96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP7_IP4_PKT" , 0x1070100e96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP8_IP4_PKT" , 0x1070101096400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP9_IP4_PKT" , 0x1070101296400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP10_IP4_PKT" , 0x1070101496400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP11_IP4_PKT" , 0x1070101696400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP12_IP4_PKT" , 0x1070101896400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP13_IP4_PKT" , 0x1070101a96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP14_IP4_PKT" , 0x1070101c96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP15_IP4_PKT" , 0x1070101e96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP16_IP4_PKT" , 0x1070102096400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP17_IP4_PKT" , 0x1070102296400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP18_IP4_PKT" , 0x1070102496400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP19_IP4_PKT" , 0x1070102696400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP20_IP4_PKT" , 0x1070102896400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP21_IP4_PKT" , 0x1070102a96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP22_IP4_PKT" , 0x1070102c96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP23_IP4_PKT" , 0x1070102e96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP24_IP4_PKT" , 0x1070103096400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP25_IP4_PKT" , 0x1070103296400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP26_IP4_PKT" , 0x1070103496400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP27_IP4_PKT" , 0x1070103696400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP28_IP4_PKT" , 0x1070103896400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP29_IP4_PKT" , 0x1070103a96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP30_IP4_PKT" , 0x1070103c96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP31_IP4_PKT" , 0x1070103e96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP0_IP4_PKT_W1C" , 0x10701000b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP1_IP4_PKT_W1C" , 0x10701002b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP2_IP4_PKT_W1C" , 0x10701004b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP3_IP4_PKT_W1C" , 0x10701006b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP4_IP4_PKT_W1C" , 0x10701008b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP5_IP4_PKT_W1C" , 0x1070100ab6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP6_IP4_PKT_W1C" , 0x1070100cb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP7_IP4_PKT_W1C" , 0x1070100eb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP8_IP4_PKT_W1C" , 0x10701010b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP9_IP4_PKT_W1C" , 0x10701012b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP10_IP4_PKT_W1C" , 0x10701014b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP11_IP4_PKT_W1C" , 0x10701016b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP12_IP4_PKT_W1C" , 0x10701018b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP13_IP4_PKT_W1C" , 0x1070101ab6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP14_IP4_PKT_W1C" , 0x1070101cb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP15_IP4_PKT_W1C" , 0x1070101eb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP16_IP4_PKT_W1C" , 0x10701020b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP17_IP4_PKT_W1C" , 0x10701022b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP18_IP4_PKT_W1C" , 0x10701024b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP19_IP4_PKT_W1C" , 0x10701026b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP20_IP4_PKT_W1C" , 0x10701028b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP21_IP4_PKT_W1C" , 0x1070102ab6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP22_IP4_PKT_W1C" , 0x1070102cb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP23_IP4_PKT_W1C" , 0x1070102eb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP24_IP4_PKT_W1C" , 0x10701030b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP25_IP4_PKT_W1C" , 0x10701032b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP26_IP4_PKT_W1C" , 0x10701034b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP27_IP4_PKT_W1C" , 0x10701036b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP28_IP4_PKT_W1C" , 0x10701038b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP29_IP4_PKT_W1C" , 0x1070103ab6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP30_IP4_PKT_W1C" , 0x1070103cb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP31_IP4_PKT_W1C" , 0x1070103eb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP0_IP4_PKT_W1S" , 0x10701000a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP1_IP4_PKT_W1S" , 0x10701002a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP2_IP4_PKT_W1S" , 0x10701004a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP3_IP4_PKT_W1S" , 0x10701006a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP4_IP4_PKT_W1S" , 0x10701008a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP5_IP4_PKT_W1S" , 0x1070100aa6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP6_IP4_PKT_W1S" , 0x1070100ca6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP7_IP4_PKT_W1S" , 0x1070100ea6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP8_IP4_PKT_W1S" , 0x10701010a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP9_IP4_PKT_W1S" , 0x10701012a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP10_IP4_PKT_W1S" , 0x10701014a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP11_IP4_PKT_W1S" , 0x10701016a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP12_IP4_PKT_W1S" , 0x10701018a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP13_IP4_PKT_W1S" , 0x1070101aa6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP14_IP4_PKT_W1S" , 0x1070101ca6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP15_IP4_PKT_W1S" , 0x1070101ea6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP16_IP4_PKT_W1S" , 0x10701020a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP17_IP4_PKT_W1S" , 0x10701022a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP18_IP4_PKT_W1S" , 0x10701024a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP19_IP4_PKT_W1S" , 0x10701026a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP20_IP4_PKT_W1S" , 0x10701028a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP21_IP4_PKT_W1S" , 0x1070102aa6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP22_IP4_PKT_W1S" , 0x1070102ca6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP23_IP4_PKT_W1S" , 0x1070102ea6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP24_IP4_PKT_W1S" , 0x10701030a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP25_IP4_PKT_W1S" , 0x10701032a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP26_IP4_PKT_W1S" , 0x10701034a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP27_IP4_PKT_W1S" , 0x10701036a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP28_IP4_PKT_W1S" , 0x10701038a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP29_IP4_PKT_W1S" , 0x1070103aa6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP30_IP4_PKT_W1S" , 0x1070103ca6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP31_IP4_PKT_W1S" , 0x1070103ea6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP0_IP4_RML" , 0x1070100092400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP1_IP4_RML" , 0x1070100292400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP2_IP4_RML" , 0x1070100492400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP3_IP4_RML" , 0x1070100692400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP4_IP4_RML" , 0x1070100892400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP5_IP4_RML" , 0x1070100a92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP6_IP4_RML" , 0x1070100c92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP7_IP4_RML" , 0x1070100e92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP8_IP4_RML" , 0x1070101092400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP9_IP4_RML" , 0x1070101292400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP10_IP4_RML" , 0x1070101492400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP11_IP4_RML" , 0x1070101692400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP12_IP4_RML" , 0x1070101892400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP13_IP4_RML" , 0x1070101a92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP14_IP4_RML" , 0x1070101c92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP15_IP4_RML" , 0x1070101e92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP16_IP4_RML" , 0x1070102092400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP17_IP4_RML" , 0x1070102292400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP18_IP4_RML" , 0x1070102492400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP19_IP4_RML" , 0x1070102692400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP20_IP4_RML" , 0x1070102892400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP21_IP4_RML" , 0x1070102a92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP22_IP4_RML" , 0x1070102c92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP23_IP4_RML" , 0x1070102e92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP24_IP4_RML" , 0x1070103092400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP25_IP4_RML" , 0x1070103292400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP26_IP4_RML" , 0x1070103492400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP27_IP4_RML" , 0x1070103692400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP28_IP4_RML" , 0x1070103892400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP29_IP4_RML" , 0x1070103a92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP30_IP4_RML" , 0x1070103c92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP31_IP4_RML" , 0x1070103e92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP0_IP4_RML_W1C" , 0x10701000b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP1_IP4_RML_W1C" , 0x10701002b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP2_IP4_RML_W1C" , 0x10701004b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP3_IP4_RML_W1C" , 0x10701006b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP4_IP4_RML_W1C" , 0x10701008b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP5_IP4_RML_W1C" , 0x1070100ab2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP6_IP4_RML_W1C" , 0x1070100cb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP7_IP4_RML_W1C" , 0x1070100eb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP8_IP4_RML_W1C" , 0x10701010b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP9_IP4_RML_W1C" , 0x10701012b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP10_IP4_RML_W1C" , 0x10701014b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP11_IP4_RML_W1C" , 0x10701016b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP12_IP4_RML_W1C" , 0x10701018b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP13_IP4_RML_W1C" , 0x1070101ab2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP14_IP4_RML_W1C" , 0x1070101cb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP15_IP4_RML_W1C" , 0x1070101eb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP16_IP4_RML_W1C" , 0x10701020b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP17_IP4_RML_W1C" , 0x10701022b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP18_IP4_RML_W1C" , 0x10701024b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP19_IP4_RML_W1C" , 0x10701026b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP20_IP4_RML_W1C" , 0x10701028b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP21_IP4_RML_W1C" , 0x1070102ab2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP22_IP4_RML_W1C" , 0x1070102cb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP23_IP4_RML_W1C" , 0x1070102eb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP24_IP4_RML_W1C" , 0x10701030b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP25_IP4_RML_W1C" , 0x10701032b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP26_IP4_RML_W1C" , 0x10701034b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP27_IP4_RML_W1C" , 0x10701036b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP28_IP4_RML_W1C" , 0x10701038b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP29_IP4_RML_W1C" , 0x1070103ab2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP30_IP4_RML_W1C" , 0x1070103cb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP31_IP4_RML_W1C" , 0x1070103eb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP0_IP4_RML_W1S" , 0x10701000a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP1_IP4_RML_W1S" , 0x10701002a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP2_IP4_RML_W1S" , 0x10701004a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP3_IP4_RML_W1S" , 0x10701006a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP4_IP4_RML_W1S" , 0x10701008a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP5_IP4_RML_W1S" , 0x1070100aa2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP6_IP4_RML_W1S" , 0x1070100ca2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP7_IP4_RML_W1S" , 0x1070100ea2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP8_IP4_RML_W1S" , 0x10701010a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP9_IP4_RML_W1S" , 0x10701012a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP10_IP4_RML_W1S" , 0x10701014a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP11_IP4_RML_W1S" , 0x10701016a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP12_IP4_RML_W1S" , 0x10701018a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP13_IP4_RML_W1S" , 0x1070101aa2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP14_IP4_RML_W1S" , 0x1070101ca2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP15_IP4_RML_W1S" , 0x1070101ea2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP16_IP4_RML_W1S" , 0x10701020a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP17_IP4_RML_W1S" , 0x10701022a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP18_IP4_RML_W1S" , 0x10701024a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP19_IP4_RML_W1S" , 0x10701026a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP20_IP4_RML_W1S" , 0x10701028a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP21_IP4_RML_W1S" , 0x1070102aa2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP22_IP4_RML_W1S" , 0x1070102ca2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP23_IP4_RML_W1S" , 0x1070102ea2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP24_IP4_RML_W1S" , 0x10701030a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP25_IP4_RML_W1S" , 0x10701032a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP26_IP4_RML_W1S" , 0x10701034a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP27_IP4_RML_W1S" , 0x10701036a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP28_IP4_RML_W1S" , 0x10701038a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP29_IP4_RML_W1S" , 0x1070103aa2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP30_IP4_RML_W1S" , 0x1070103ca2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP31_IP4_RML_W1S" , 0x1070103ea2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP0_IP4_WDOG" , 0x1070100091400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP1_IP4_WDOG" , 0x1070100291400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP2_IP4_WDOG" , 0x1070100491400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP3_IP4_WDOG" , 0x1070100691400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP4_IP4_WDOG" , 0x1070100891400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP5_IP4_WDOG" , 0x1070100a91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP6_IP4_WDOG" , 0x1070100c91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP7_IP4_WDOG" , 0x1070100e91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP8_IP4_WDOG" , 0x1070101091400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP9_IP4_WDOG" , 0x1070101291400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP10_IP4_WDOG" , 0x1070101491400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP11_IP4_WDOG" , 0x1070101691400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP12_IP4_WDOG" , 0x1070101891400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP13_IP4_WDOG" , 0x1070101a91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP14_IP4_WDOG" , 0x1070101c91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP15_IP4_WDOG" , 0x1070101e91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP16_IP4_WDOG" , 0x1070102091400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP17_IP4_WDOG" , 0x1070102291400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP18_IP4_WDOG" , 0x1070102491400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP19_IP4_WDOG" , 0x1070102691400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP20_IP4_WDOG" , 0x1070102891400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP21_IP4_WDOG" , 0x1070102a91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP22_IP4_WDOG" , 0x1070102c91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP23_IP4_WDOG" , 0x1070102e91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP24_IP4_WDOG" , 0x1070103091400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP25_IP4_WDOG" , 0x1070103291400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP26_IP4_WDOG" , 0x1070103491400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP27_IP4_WDOG" , 0x1070103691400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP28_IP4_WDOG" , 0x1070103891400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP29_IP4_WDOG" , 0x1070103a91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP30_IP4_WDOG" , 0x1070103c91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP31_IP4_WDOG" , 0x1070103e91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP0_IP4_WDOG_W1C" , 0x10701000b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP1_IP4_WDOG_W1C" , 0x10701002b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP2_IP4_WDOG_W1C" , 0x10701004b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP3_IP4_WDOG_W1C" , 0x10701006b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP4_IP4_WDOG_W1C" , 0x10701008b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP5_IP4_WDOG_W1C" , 0x1070100ab1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP6_IP4_WDOG_W1C" , 0x1070100cb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP7_IP4_WDOG_W1C" , 0x1070100eb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP8_IP4_WDOG_W1C" , 0x10701010b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP9_IP4_WDOG_W1C" , 0x10701012b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP10_IP4_WDOG_W1C" , 0x10701014b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP11_IP4_WDOG_W1C" , 0x10701016b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP12_IP4_WDOG_W1C" , 0x10701018b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP13_IP4_WDOG_W1C" , 0x1070101ab1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP14_IP4_WDOG_W1C" , 0x1070101cb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP15_IP4_WDOG_W1C" , 0x1070101eb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP16_IP4_WDOG_W1C" , 0x10701020b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP17_IP4_WDOG_W1C" , 0x10701022b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP18_IP4_WDOG_W1C" , 0x10701024b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP19_IP4_WDOG_W1C" , 0x10701026b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP20_IP4_WDOG_W1C" , 0x10701028b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP21_IP4_WDOG_W1C" , 0x1070102ab1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP22_IP4_WDOG_W1C" , 0x1070102cb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP23_IP4_WDOG_W1C" , 0x1070102eb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP24_IP4_WDOG_W1C" , 0x10701030b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP25_IP4_WDOG_W1C" , 0x10701032b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP26_IP4_WDOG_W1C" , 0x10701034b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP27_IP4_WDOG_W1C" , 0x10701036b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP28_IP4_WDOG_W1C" , 0x10701038b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP29_IP4_WDOG_W1C" , 0x1070103ab1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP30_IP4_WDOG_W1C" , 0x1070103cb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP31_IP4_WDOG_W1C" , 0x1070103eb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP0_IP4_WDOG_W1S" , 0x10701000a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP1_IP4_WDOG_W1S" , 0x10701002a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP2_IP4_WDOG_W1S" , 0x10701004a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP3_IP4_WDOG_W1S" , 0x10701006a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP4_IP4_WDOG_W1S" , 0x10701008a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP5_IP4_WDOG_W1S" , 0x1070100aa1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP6_IP4_WDOG_W1S" , 0x1070100ca1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP7_IP4_WDOG_W1S" , 0x1070100ea1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP8_IP4_WDOG_W1S" , 0x10701010a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP9_IP4_WDOG_W1S" , 0x10701012a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP10_IP4_WDOG_W1S" , 0x10701014a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP11_IP4_WDOG_W1S" , 0x10701016a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP12_IP4_WDOG_W1S" , 0x10701018a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP13_IP4_WDOG_W1S" , 0x1070101aa1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP14_IP4_WDOG_W1S" , 0x1070101ca1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP15_IP4_WDOG_W1S" , 0x1070101ea1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP16_IP4_WDOG_W1S" , 0x10701020a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP17_IP4_WDOG_W1S" , 0x10701022a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP18_IP4_WDOG_W1S" , 0x10701024a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP19_IP4_WDOG_W1S" , 0x10701026a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP20_IP4_WDOG_W1S" , 0x10701028a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP21_IP4_WDOG_W1S" , 0x1070102aa1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP22_IP4_WDOG_W1S" , 0x1070102ca1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP23_IP4_WDOG_W1S" , 0x1070102ea1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP24_IP4_WDOG_W1S" , 0x10701030a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP25_IP4_WDOG_W1S" , 0x10701032a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP26_IP4_WDOG_W1S" , 0x10701034a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP27_IP4_WDOG_W1S" , 0x10701036a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP28_IP4_WDOG_W1S" , 0x10701038a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP29_IP4_WDOG_W1S" , 0x1070103aa1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP30_IP4_WDOG_W1S" , 0x1070103ca1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP31_IP4_WDOG_W1S" , 0x1070103ea1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP0_IP4_WRKQ" , 0x1070100090400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP1_IP4_WRKQ" , 0x1070100290400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP2_IP4_WRKQ" , 0x1070100490400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP3_IP4_WRKQ" , 0x1070100690400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP4_IP4_WRKQ" , 0x1070100890400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP5_IP4_WRKQ" , 0x1070100a90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP6_IP4_WRKQ" , 0x1070100c90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP7_IP4_WRKQ" , 0x1070100e90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP8_IP4_WRKQ" , 0x1070101090400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP9_IP4_WRKQ" , 0x1070101290400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP10_IP4_WRKQ" , 0x1070101490400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP11_IP4_WRKQ" , 0x1070101690400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP12_IP4_WRKQ" , 0x1070101890400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP13_IP4_WRKQ" , 0x1070101a90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP14_IP4_WRKQ" , 0x1070101c90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP15_IP4_WRKQ" , 0x1070101e90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP16_IP4_WRKQ" , 0x1070102090400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP17_IP4_WRKQ" , 0x1070102290400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP18_IP4_WRKQ" , 0x1070102490400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP19_IP4_WRKQ" , 0x1070102690400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP20_IP4_WRKQ" , 0x1070102890400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP21_IP4_WRKQ" , 0x1070102a90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP22_IP4_WRKQ" , 0x1070102c90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP23_IP4_WRKQ" , 0x1070102e90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP24_IP4_WRKQ" , 0x1070103090400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP25_IP4_WRKQ" , 0x1070103290400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP26_IP4_WRKQ" , 0x1070103490400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP27_IP4_WRKQ" , 0x1070103690400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP28_IP4_WRKQ" , 0x1070103890400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP29_IP4_WRKQ" , 0x1070103a90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP30_IP4_WRKQ" , 0x1070103c90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP31_IP4_WRKQ" , 0x1070103e90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP0_IP4_WRKQ_W1C" , 0x10701000b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP1_IP4_WRKQ_W1C" , 0x10701002b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP2_IP4_WRKQ_W1C" , 0x10701004b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP3_IP4_WRKQ_W1C" , 0x10701006b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP4_IP4_WRKQ_W1C" , 0x10701008b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP5_IP4_WRKQ_W1C" , 0x1070100ab0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP6_IP4_WRKQ_W1C" , 0x1070100cb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP7_IP4_WRKQ_W1C" , 0x1070100eb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP8_IP4_WRKQ_W1C" , 0x10701010b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP9_IP4_WRKQ_W1C" , 0x10701012b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP10_IP4_WRKQ_W1C" , 0x10701014b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP11_IP4_WRKQ_W1C" , 0x10701016b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP12_IP4_WRKQ_W1C" , 0x10701018b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP13_IP4_WRKQ_W1C" , 0x1070101ab0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP14_IP4_WRKQ_W1C" , 0x1070101cb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP15_IP4_WRKQ_W1C" , 0x1070101eb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP16_IP4_WRKQ_W1C" , 0x10701020b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP17_IP4_WRKQ_W1C" , 0x10701022b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP18_IP4_WRKQ_W1C" , 0x10701024b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP19_IP4_WRKQ_W1C" , 0x10701026b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP20_IP4_WRKQ_W1C" , 0x10701028b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP21_IP4_WRKQ_W1C" , 0x1070102ab0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP22_IP4_WRKQ_W1C" , 0x1070102cb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP23_IP4_WRKQ_W1C" , 0x1070102eb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP24_IP4_WRKQ_W1C" , 0x10701030b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP25_IP4_WRKQ_W1C" , 0x10701032b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP26_IP4_WRKQ_W1C" , 0x10701034b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP27_IP4_WRKQ_W1C" , 0x10701036b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP28_IP4_WRKQ_W1C" , 0x10701038b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP29_IP4_WRKQ_W1C" , 0x1070103ab0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP30_IP4_WRKQ_W1C" , 0x1070103cb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP31_IP4_WRKQ_W1C" , 0x1070103eb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP0_IP4_WRKQ_W1S" , 0x10701000a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP1_IP4_WRKQ_W1S" , 0x10701002a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP2_IP4_WRKQ_W1S" , 0x10701004a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP3_IP4_WRKQ_W1S" , 0x10701006a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP4_IP4_WRKQ_W1S" , 0x10701008a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP5_IP4_WRKQ_W1S" , 0x1070100aa0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP6_IP4_WRKQ_W1S" , 0x1070100ca0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP7_IP4_WRKQ_W1S" , 0x1070100ea0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP8_IP4_WRKQ_W1S" , 0x10701010a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP9_IP4_WRKQ_W1S" , 0x10701012a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP10_IP4_WRKQ_W1S" , 0x10701014a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP11_IP4_WRKQ_W1S" , 0x10701016a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP12_IP4_WRKQ_W1S" , 0x10701018a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP13_IP4_WRKQ_W1S" , 0x1070101aa0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP14_IP4_WRKQ_W1S" , 0x1070101ca0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP15_IP4_WRKQ_W1S" , 0x1070101ea0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP16_IP4_WRKQ_W1S" , 0x10701020a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP17_IP4_WRKQ_W1S" , 0x10701022a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP18_IP4_WRKQ_W1S" , 0x10701024a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP19_IP4_WRKQ_W1S" , 0x10701026a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP20_IP4_WRKQ_W1S" , 0x10701028a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP21_IP4_WRKQ_W1S" , 0x1070102aa0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP22_IP4_WRKQ_W1S" , 0x1070102ca0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP23_IP4_WRKQ_W1S" , 0x1070102ea0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP24_IP4_WRKQ_W1S" , 0x10701030a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP25_IP4_WRKQ_W1S" , 0x10701032a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP26_IP4_WRKQ_W1S" , 0x10701034a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP27_IP4_WRKQ_W1S" , 0x10701036a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP28_IP4_WRKQ_W1S" , 0x10701038a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP29_IP4_WRKQ_W1S" , 0x1070103aa0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP30_IP4_WRKQ_W1S" , 0x1070103ca0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP31_IP4_WRKQ_W1S" , 0x1070103ea0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_INTR_CIU_READY" , 0x1070100102008ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"CIU2_INTR_RAM_ECC_CTL" , 0x1070100102010ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
- {"CIU2_INTR_RAM_ECC_ST" , 0x1070100102018ull, CVMX_CSR_DB_TYPE_NCB, 64, 186},
- {"CIU2_INTR_SLOWDOWN" , 0x1070100102000ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
- {"CIU2_MSI_RCV0" , 0x10701000c2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV1" , 0x10701000c2008ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV2" , 0x10701000c2010ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV3" , 0x10701000c2018ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV4" , 0x10701000c2020ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV5" , 0x10701000c2028ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV6" , 0x10701000c2030ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV7" , 0x10701000c2038ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV8" , 0x10701000c2040ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV9" , 0x10701000c2048ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV10" , 0x10701000c2050ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV11" , 0x10701000c2058ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV12" , 0x10701000c2060ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV13" , 0x10701000c2068ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV14" , 0x10701000c2070ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV15" , 0x10701000c2078ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV16" , 0x10701000c2080ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV17" , 0x10701000c2088ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV18" , 0x10701000c2090ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV19" , 0x10701000c2098ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV20" , 0x10701000c20a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV21" , 0x10701000c20a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV22" , 0x10701000c20b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV23" , 0x10701000c20b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV24" , 0x10701000c20c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV25" , 0x10701000c20c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV26" , 0x10701000c20d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV27" , 0x10701000c20d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV28" , 0x10701000c20e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV29" , 0x10701000c20e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV30" , 0x10701000c20f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV31" , 0x10701000c20f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV32" , 0x10701000c2100ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV33" , 0x10701000c2108ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV34" , 0x10701000c2110ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV35" , 0x10701000c2118ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV36" , 0x10701000c2120ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV37" , 0x10701000c2128ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV38" , 0x10701000c2130ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV39" , 0x10701000c2138ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV40" , 0x10701000c2140ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV41" , 0x10701000c2148ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV42" , 0x10701000c2150ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV43" , 0x10701000c2158ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV44" , 0x10701000c2160ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV45" , 0x10701000c2168ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV46" , 0x10701000c2170ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV47" , 0x10701000c2178ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV48" , 0x10701000c2180ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV49" , 0x10701000c2188ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV50" , 0x10701000c2190ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV51" , 0x10701000c2198ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV52" , 0x10701000c21a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV53" , 0x10701000c21a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV54" , 0x10701000c21b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV55" , 0x10701000c21b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV56" , 0x10701000c21c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV57" , 0x10701000c21c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV58" , 0x10701000c21d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV59" , 0x10701000c21d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV60" , 0x10701000c21e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV61" , 0x10701000c21e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV62" , 0x10701000c21f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV63" , 0x10701000c21f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV64" , 0x10701000c2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV65" , 0x10701000c2208ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV66" , 0x10701000c2210ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV67" , 0x10701000c2218ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV68" , 0x10701000c2220ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV69" , 0x10701000c2228ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV70" , 0x10701000c2230ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV71" , 0x10701000c2238ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV72" , 0x10701000c2240ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV73" , 0x10701000c2248ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV74" , 0x10701000c2250ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV75" , 0x10701000c2258ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV76" , 0x10701000c2260ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV77" , 0x10701000c2268ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV78" , 0x10701000c2270ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV79" , 0x10701000c2278ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV80" , 0x10701000c2280ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV81" , 0x10701000c2288ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV82" , 0x10701000c2290ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV83" , 0x10701000c2298ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV84" , 0x10701000c22a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV85" , 0x10701000c22a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV86" , 0x10701000c22b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV87" , 0x10701000c22b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV88" , 0x10701000c22c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV89" , 0x10701000c22c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV90" , 0x10701000c22d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV91" , 0x10701000c22d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV92" , 0x10701000c22e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV93" , 0x10701000c22e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV94" , 0x10701000c22f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV95" , 0x10701000c22f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV96" , 0x10701000c2300ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV97" , 0x10701000c2308ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV98" , 0x10701000c2310ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV99" , 0x10701000c2318ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV100" , 0x10701000c2320ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV101" , 0x10701000c2328ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV102" , 0x10701000c2330ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV103" , 0x10701000c2338ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV104" , 0x10701000c2340ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV105" , 0x10701000c2348ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV106" , 0x10701000c2350ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV107" , 0x10701000c2358ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV108" , 0x10701000c2360ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV109" , 0x10701000c2368ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV110" , 0x10701000c2370ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV111" , 0x10701000c2378ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV112" , 0x10701000c2380ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV113" , 0x10701000c2388ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV114" , 0x10701000c2390ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV115" , 0x10701000c2398ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV116" , 0x10701000c23a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV117" , 0x10701000c23a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV118" , 0x10701000c23b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV119" , 0x10701000c23b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV120" , 0x10701000c23c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV121" , 0x10701000c23c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV122" , 0x10701000c23d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV123" , 0x10701000c23d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV124" , 0x10701000c23e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV125" , 0x10701000c23e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV126" , 0x10701000c23f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV127" , 0x10701000c23f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV128" , 0x10701000c2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV129" , 0x10701000c2408ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV130" , 0x10701000c2410ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV131" , 0x10701000c2418ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV132" , 0x10701000c2420ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV133" , 0x10701000c2428ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV134" , 0x10701000c2430ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV135" , 0x10701000c2438ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV136" , 0x10701000c2440ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV137" , 0x10701000c2448ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV138" , 0x10701000c2450ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV139" , 0x10701000c2458ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV140" , 0x10701000c2460ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV141" , 0x10701000c2468ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV142" , 0x10701000c2470ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV143" , 0x10701000c2478ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV144" , 0x10701000c2480ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV145" , 0x10701000c2488ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV146" , 0x10701000c2490ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV147" , 0x10701000c2498ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV148" , 0x10701000c24a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV149" , 0x10701000c24a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV150" , 0x10701000c24b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV151" , 0x10701000c24b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV152" , 0x10701000c24c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV153" , 0x10701000c24c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV154" , 0x10701000c24d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV155" , 0x10701000c24d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV156" , 0x10701000c24e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV157" , 0x10701000c24e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV158" , 0x10701000c24f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV159" , 0x10701000c24f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV160" , 0x10701000c2500ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV161" , 0x10701000c2508ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV162" , 0x10701000c2510ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV163" , 0x10701000c2518ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV164" , 0x10701000c2520ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV165" , 0x10701000c2528ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV166" , 0x10701000c2530ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV167" , 0x10701000c2538ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV168" , 0x10701000c2540ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV169" , 0x10701000c2548ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV170" , 0x10701000c2550ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV171" , 0x10701000c2558ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV172" , 0x10701000c2560ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV173" , 0x10701000c2568ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV174" , 0x10701000c2570ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV175" , 0x10701000c2578ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV176" , 0x10701000c2580ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV177" , 0x10701000c2588ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV178" , 0x10701000c2590ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV179" , 0x10701000c2598ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV180" , 0x10701000c25a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV181" , 0x10701000c25a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV182" , 0x10701000c25b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV183" , 0x10701000c25b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV184" , 0x10701000c25c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV185" , 0x10701000c25c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV186" , 0x10701000c25d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV187" , 0x10701000c25d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV188" , 0x10701000c25e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV189" , 0x10701000c25e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV190" , 0x10701000c25f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV191" , 0x10701000c25f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV192" , 0x10701000c2600ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV193" , 0x10701000c2608ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV194" , 0x10701000c2610ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV195" , 0x10701000c2618ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV196" , 0x10701000c2620ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV197" , 0x10701000c2628ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV198" , 0x10701000c2630ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV199" , 0x10701000c2638ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV200" , 0x10701000c2640ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV201" , 0x10701000c2648ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV202" , 0x10701000c2650ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV203" , 0x10701000c2658ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV204" , 0x10701000c2660ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV205" , 0x10701000c2668ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV206" , 0x10701000c2670ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV207" , 0x10701000c2678ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV208" , 0x10701000c2680ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV209" , 0x10701000c2688ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV210" , 0x10701000c2690ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV211" , 0x10701000c2698ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV212" , 0x10701000c26a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV213" , 0x10701000c26a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV214" , 0x10701000c26b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV215" , 0x10701000c26b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV216" , 0x10701000c26c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV217" , 0x10701000c26c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV218" , 0x10701000c26d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV219" , 0x10701000c26d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV220" , 0x10701000c26e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV221" , 0x10701000c26e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV222" , 0x10701000c26f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV223" , 0x10701000c26f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV224" , 0x10701000c2700ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV225" , 0x10701000c2708ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV226" , 0x10701000c2710ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV227" , 0x10701000c2718ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV228" , 0x10701000c2720ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV229" , 0x10701000c2728ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV230" , 0x10701000c2730ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV231" , 0x10701000c2738ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV232" , 0x10701000c2740ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV233" , 0x10701000c2748ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV234" , 0x10701000c2750ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV235" , 0x10701000c2758ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV236" , 0x10701000c2760ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV237" , 0x10701000c2768ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV238" , 0x10701000c2770ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV239" , 0x10701000c2778ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV240" , 0x10701000c2780ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV241" , 0x10701000c2788ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV242" , 0x10701000c2790ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV243" , 0x10701000c2798ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV244" , 0x10701000c27a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV245" , 0x10701000c27a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV246" , 0x10701000c27b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV247" , 0x10701000c27b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV248" , 0x10701000c27c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV249" , 0x10701000c27c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV250" , 0x10701000c27d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV251" , 0x10701000c27d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV252" , 0x10701000c27e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV253" , 0x10701000c27e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV254" , 0x10701000c27f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV255" , 0x10701000c27f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_SEL0" , 0x10701000c3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL1" , 0x10701000c3008ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL2" , 0x10701000c3010ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL3" , 0x10701000c3018ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL4" , 0x10701000c3020ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL5" , 0x10701000c3028ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL6" , 0x10701000c3030ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL7" , 0x10701000c3038ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL8" , 0x10701000c3040ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL9" , 0x10701000c3048ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL10" , 0x10701000c3050ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL11" , 0x10701000c3058ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL12" , 0x10701000c3060ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL13" , 0x10701000c3068ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL14" , 0x10701000c3070ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL15" , 0x10701000c3078ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL16" , 0x10701000c3080ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL17" , 0x10701000c3088ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL18" , 0x10701000c3090ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL19" , 0x10701000c3098ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL20" , 0x10701000c30a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL21" , 0x10701000c30a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL22" , 0x10701000c30b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL23" , 0x10701000c30b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL24" , 0x10701000c30c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL25" , 0x10701000c30c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL26" , 0x10701000c30d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL27" , 0x10701000c30d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL28" , 0x10701000c30e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL29" , 0x10701000c30e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL30" , 0x10701000c30f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL31" , 0x10701000c30f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL32" , 0x10701000c3100ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL33" , 0x10701000c3108ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL34" , 0x10701000c3110ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL35" , 0x10701000c3118ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL36" , 0x10701000c3120ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL37" , 0x10701000c3128ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL38" , 0x10701000c3130ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL39" , 0x10701000c3138ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL40" , 0x10701000c3140ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL41" , 0x10701000c3148ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL42" , 0x10701000c3150ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL43" , 0x10701000c3158ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL44" , 0x10701000c3160ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL45" , 0x10701000c3168ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL46" , 0x10701000c3170ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL47" , 0x10701000c3178ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL48" , 0x10701000c3180ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL49" , 0x10701000c3188ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL50" , 0x10701000c3190ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL51" , 0x10701000c3198ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL52" , 0x10701000c31a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL53" , 0x10701000c31a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL54" , 0x10701000c31b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL55" , 0x10701000c31b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL56" , 0x10701000c31c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL57" , 0x10701000c31c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL58" , 0x10701000c31d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL59" , 0x10701000c31d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL60" , 0x10701000c31e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL61" , 0x10701000c31e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL62" , 0x10701000c31f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL63" , 0x10701000c31f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL64" , 0x10701000c3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL65" , 0x10701000c3208ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL66" , 0x10701000c3210ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL67" , 0x10701000c3218ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL68" , 0x10701000c3220ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL69" , 0x10701000c3228ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL70" , 0x10701000c3230ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL71" , 0x10701000c3238ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL72" , 0x10701000c3240ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL73" , 0x10701000c3248ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL74" , 0x10701000c3250ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL75" , 0x10701000c3258ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL76" , 0x10701000c3260ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL77" , 0x10701000c3268ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL78" , 0x10701000c3270ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL79" , 0x10701000c3278ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL80" , 0x10701000c3280ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL81" , 0x10701000c3288ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL82" , 0x10701000c3290ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL83" , 0x10701000c3298ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL84" , 0x10701000c32a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL85" , 0x10701000c32a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL86" , 0x10701000c32b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL87" , 0x10701000c32b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL88" , 0x10701000c32c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL89" , 0x10701000c32c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL90" , 0x10701000c32d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL91" , 0x10701000c32d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL92" , 0x10701000c32e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL93" , 0x10701000c32e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL94" , 0x10701000c32f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL95" , 0x10701000c32f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL96" , 0x10701000c3300ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL97" , 0x10701000c3308ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL98" , 0x10701000c3310ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL99" , 0x10701000c3318ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL100" , 0x10701000c3320ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL101" , 0x10701000c3328ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL102" , 0x10701000c3330ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL103" , 0x10701000c3338ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL104" , 0x10701000c3340ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL105" , 0x10701000c3348ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL106" , 0x10701000c3350ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL107" , 0x10701000c3358ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL108" , 0x10701000c3360ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL109" , 0x10701000c3368ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL110" , 0x10701000c3370ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL111" , 0x10701000c3378ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL112" , 0x10701000c3380ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL113" , 0x10701000c3388ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL114" , 0x10701000c3390ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL115" , 0x10701000c3398ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL116" , 0x10701000c33a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL117" , 0x10701000c33a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL118" , 0x10701000c33b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL119" , 0x10701000c33b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL120" , 0x10701000c33c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL121" , 0x10701000c33c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL122" , 0x10701000c33d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL123" , 0x10701000c33d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL124" , 0x10701000c33e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL125" , 0x10701000c33e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL126" , 0x10701000c33f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL127" , 0x10701000c33f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL128" , 0x10701000c3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL129" , 0x10701000c3408ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL130" , 0x10701000c3410ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL131" , 0x10701000c3418ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL132" , 0x10701000c3420ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL133" , 0x10701000c3428ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL134" , 0x10701000c3430ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL135" , 0x10701000c3438ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL136" , 0x10701000c3440ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL137" , 0x10701000c3448ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL138" , 0x10701000c3450ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL139" , 0x10701000c3458ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL140" , 0x10701000c3460ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL141" , 0x10701000c3468ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL142" , 0x10701000c3470ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL143" , 0x10701000c3478ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL144" , 0x10701000c3480ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL145" , 0x10701000c3488ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL146" , 0x10701000c3490ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL147" , 0x10701000c3498ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL148" , 0x10701000c34a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL149" , 0x10701000c34a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL150" , 0x10701000c34b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL151" , 0x10701000c34b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL152" , 0x10701000c34c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL153" , 0x10701000c34c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL154" , 0x10701000c34d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL155" , 0x10701000c34d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL156" , 0x10701000c34e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL157" , 0x10701000c34e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL158" , 0x10701000c34f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL159" , 0x10701000c34f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL160" , 0x10701000c3500ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL161" , 0x10701000c3508ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL162" , 0x10701000c3510ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL163" , 0x10701000c3518ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL164" , 0x10701000c3520ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL165" , 0x10701000c3528ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL166" , 0x10701000c3530ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL167" , 0x10701000c3538ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL168" , 0x10701000c3540ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL169" , 0x10701000c3548ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL170" , 0x10701000c3550ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL171" , 0x10701000c3558ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL172" , 0x10701000c3560ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL173" , 0x10701000c3568ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL174" , 0x10701000c3570ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL175" , 0x10701000c3578ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL176" , 0x10701000c3580ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL177" , 0x10701000c3588ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL178" , 0x10701000c3590ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL179" , 0x10701000c3598ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL180" , 0x10701000c35a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL181" , 0x10701000c35a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL182" , 0x10701000c35b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL183" , 0x10701000c35b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL184" , 0x10701000c35c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL185" , 0x10701000c35c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL186" , 0x10701000c35d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL187" , 0x10701000c35d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL188" , 0x10701000c35e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL189" , 0x10701000c35e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL190" , 0x10701000c35f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL191" , 0x10701000c35f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL192" , 0x10701000c3600ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL193" , 0x10701000c3608ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL194" , 0x10701000c3610ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL195" , 0x10701000c3618ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL196" , 0x10701000c3620ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL197" , 0x10701000c3628ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL198" , 0x10701000c3630ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL199" , 0x10701000c3638ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL200" , 0x10701000c3640ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL201" , 0x10701000c3648ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL202" , 0x10701000c3650ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL203" , 0x10701000c3658ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL204" , 0x10701000c3660ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL205" , 0x10701000c3668ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL206" , 0x10701000c3670ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL207" , 0x10701000c3678ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL208" , 0x10701000c3680ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL209" , 0x10701000c3688ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL210" , 0x10701000c3690ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL211" , 0x10701000c3698ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL212" , 0x10701000c36a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL213" , 0x10701000c36a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL214" , 0x10701000c36b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL215" , 0x10701000c36b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL216" , 0x10701000c36c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL217" , 0x10701000c36c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL218" , 0x10701000c36d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL219" , 0x10701000c36d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL220" , 0x10701000c36e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL221" , 0x10701000c36e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL222" , 0x10701000c36f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL223" , 0x10701000c36f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL224" , 0x10701000c3700ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL225" , 0x10701000c3708ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL226" , 0x10701000c3710ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL227" , 0x10701000c3718ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL228" , 0x10701000c3720ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL229" , 0x10701000c3728ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL230" , 0x10701000c3730ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL231" , 0x10701000c3738ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL232" , 0x10701000c3740ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL233" , 0x10701000c3748ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL234" , 0x10701000c3750ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL235" , 0x10701000c3758ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL236" , 0x10701000c3760ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL237" , 0x10701000c3768ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL238" , 0x10701000c3770ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL239" , 0x10701000c3778ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL240" , 0x10701000c3780ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL241" , 0x10701000c3788ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL242" , 0x10701000c3790ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL243" , 0x10701000c3798ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL244" , 0x10701000c37a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL245" , 0x10701000c37a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL246" , 0x10701000c37b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL247" , 0x10701000c37b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL248" , 0x10701000c37c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL249" , 0x10701000c37c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL250" , 0x10701000c37d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL251" , 0x10701000c37d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL252" , 0x10701000c37e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL253" , 0x10701000c37e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL254" , 0x10701000c37f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL255" , 0x10701000c37f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSIRED_PP0_IP2" , 0x10701000c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP1_IP2" , 0x10701002c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP2_IP2" , 0x10701004c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP3_IP2" , 0x10701006c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP4_IP2" , 0x10701008c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP5_IP2" , 0x1070100ac1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP6_IP2" , 0x1070100cc1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP7_IP2" , 0x1070100ec1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP8_IP2" , 0x10701010c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP9_IP2" , 0x10701012c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP10_IP2" , 0x10701014c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP11_IP2" , 0x10701016c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP12_IP2" , 0x10701018c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP13_IP2" , 0x1070101ac1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP14_IP2" , 0x1070101cc1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP15_IP2" , 0x1070101ec1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP16_IP2" , 0x10701020c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP17_IP2" , 0x10701022c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP18_IP2" , 0x10701024c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP19_IP2" , 0x10701026c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP20_IP2" , 0x10701028c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP21_IP2" , 0x1070102ac1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP22_IP2" , 0x1070102cc1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP23_IP2" , 0x1070102ec1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP24_IP2" , 0x10701030c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP25_IP2" , 0x10701032c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP26_IP2" , 0x10701034c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP27_IP2" , 0x10701036c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP28_IP2" , 0x10701038c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP29_IP2" , 0x1070103ac1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP30_IP2" , 0x1070103cc1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP31_IP2" , 0x1070103ec1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP0_IP3" , 0x10701000c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP1_IP3" , 0x10701002c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP2_IP3" , 0x10701004c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP3_IP3" , 0x10701006c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP4_IP3" , 0x10701008c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP5_IP3" , 0x1070100ac1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP6_IP3" , 0x1070100cc1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP7_IP3" , 0x1070100ec1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP8_IP3" , 0x10701010c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP9_IP3" , 0x10701012c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP10_IP3" , 0x10701014c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP11_IP3" , 0x10701016c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP12_IP3" , 0x10701018c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP13_IP3" , 0x1070101ac1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP14_IP3" , 0x1070101cc1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP15_IP3" , 0x1070101ec1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP16_IP3" , 0x10701020c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP17_IP3" , 0x10701022c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP18_IP3" , 0x10701024c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP19_IP3" , 0x10701026c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP20_IP3" , 0x10701028c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP21_IP3" , 0x1070102ac1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP22_IP3" , 0x1070102cc1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP23_IP3" , 0x1070102ec1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP24_IP3" , 0x10701030c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP25_IP3" , 0x10701032c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP26_IP3" , 0x10701034c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP27_IP3" , 0x10701036c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP28_IP3" , 0x10701038c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP29_IP3" , 0x1070103ac1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP30_IP3" , 0x1070103cc1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP31_IP3" , 0x1070103ec1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP0_IP4" , 0x10701000c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP1_IP4" , 0x10701002c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP2_IP4" , 0x10701004c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP3_IP4" , 0x10701006c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP4_IP4" , 0x10701008c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP5_IP4" , 0x1070100ac1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP6_IP4" , 0x1070100cc1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP7_IP4" , 0x1070100ec1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP8_IP4" , 0x10701010c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP9_IP4" , 0x10701012c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP10_IP4" , 0x10701014c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP11_IP4" , 0x10701016c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP12_IP4" , 0x10701018c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP13_IP4" , 0x1070101ac1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP14_IP4" , 0x1070101cc1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP15_IP4" , 0x1070101ec1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP16_IP4" , 0x10701020c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP17_IP4" , 0x10701022c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP18_IP4" , 0x10701024c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP19_IP4" , 0x10701026c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP20_IP4" , 0x10701028c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP21_IP4" , 0x1070102ac1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP22_IP4" , 0x1070102cc1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP23_IP4" , 0x1070102ec1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP24_IP4" , 0x10701030c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP25_IP4" , 0x10701032c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP26_IP4" , 0x10701034c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP27_IP4" , 0x10701036c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP28_IP4" , 0x10701038c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP29_IP4" , 0x1070103ac1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP30_IP4" , 0x1070103cc1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP31_IP4" , 0x1070103ec1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_RAW_IO0_INT_GPIO" , 0x1070108047800ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
- {"CIU2_RAW_IO1_INT_GPIO" , 0x1070108247800ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
- {"CIU2_RAW_IO0_INT_IO" , 0x1070108044800ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"CIU2_RAW_IO1_INT_IO" , 0x1070108244800ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"CIU2_RAW_IO0_INT_MEM" , 0x1070108045800ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"CIU2_RAW_IO1_INT_MEM" , 0x1070108245800ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"CIU2_RAW_IO0_INT_MIO" , 0x1070108043800ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"CIU2_RAW_IO1_INT_MIO" , 0x1070108243800ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"CIU2_RAW_IO0_INT_PKT" , 0x1070108046800ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"CIU2_RAW_IO1_INT_PKT" , 0x1070108246800ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"CIU2_RAW_IO0_INT_RML" , 0x1070108042800ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"CIU2_RAW_IO1_INT_RML" , 0x1070108242800ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"CIU2_RAW_IO0_INT_WDOG" , 0x1070108041800ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"CIU2_RAW_IO1_INT_WDOG" , 0x1070108241800ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"CIU2_RAW_IO0_INT_WRKQ" , 0x1070108040800ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"CIU2_RAW_IO1_INT_WRKQ" , 0x1070108240800ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"CIU2_RAW_PP0_IP2_GPIO" , 0x1070100047000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP1_IP2_GPIO" , 0x1070100247000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP2_IP2_GPIO" , 0x1070100447000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP3_IP2_GPIO" , 0x1070100647000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP4_IP2_GPIO" , 0x1070100847000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP5_IP2_GPIO" , 0x1070100a47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP6_IP2_GPIO" , 0x1070100c47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP7_IP2_GPIO" , 0x1070100e47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP8_IP2_GPIO" , 0x1070101047000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP9_IP2_GPIO" , 0x1070101247000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP10_IP2_GPIO" , 0x1070101447000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP11_IP2_GPIO" , 0x1070101647000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP12_IP2_GPIO" , 0x1070101847000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP13_IP2_GPIO" , 0x1070101a47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP14_IP2_GPIO" , 0x1070101c47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP15_IP2_GPIO" , 0x1070101e47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP16_IP2_GPIO" , 0x1070102047000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP17_IP2_GPIO" , 0x1070102247000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP18_IP2_GPIO" , 0x1070102447000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP19_IP2_GPIO" , 0x1070102647000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP20_IP2_GPIO" , 0x1070102847000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP21_IP2_GPIO" , 0x1070102a47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP22_IP2_GPIO" , 0x1070102c47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP23_IP2_GPIO" , 0x1070102e47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP24_IP2_GPIO" , 0x1070103047000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP25_IP2_GPIO" , 0x1070103247000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP26_IP2_GPIO" , 0x1070103447000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP27_IP2_GPIO" , 0x1070103647000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP28_IP2_GPIO" , 0x1070103847000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP29_IP2_GPIO" , 0x1070103a47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP30_IP2_GPIO" , 0x1070103c47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP31_IP2_GPIO" , 0x1070103e47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP0_IP2_IO" , 0x1070100044000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP1_IP2_IO" , 0x1070100244000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP2_IP2_IO" , 0x1070100444000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP3_IP2_IO" , 0x1070100644000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP4_IP2_IO" , 0x1070100844000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP5_IP2_IO" , 0x1070100a44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP6_IP2_IO" , 0x1070100c44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP7_IP2_IO" , 0x1070100e44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP8_IP2_IO" , 0x1070101044000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP9_IP2_IO" , 0x1070101244000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP10_IP2_IO" , 0x1070101444000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP11_IP2_IO" , 0x1070101644000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP12_IP2_IO" , 0x1070101844000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP13_IP2_IO" , 0x1070101a44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP14_IP2_IO" , 0x1070101c44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP15_IP2_IO" , 0x1070101e44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP16_IP2_IO" , 0x1070102044000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP17_IP2_IO" , 0x1070102244000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP18_IP2_IO" , 0x1070102444000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP19_IP2_IO" , 0x1070102644000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP20_IP2_IO" , 0x1070102844000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP21_IP2_IO" , 0x1070102a44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP22_IP2_IO" , 0x1070102c44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP23_IP2_IO" , 0x1070102e44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP24_IP2_IO" , 0x1070103044000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP25_IP2_IO" , 0x1070103244000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP26_IP2_IO" , 0x1070103444000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP27_IP2_IO" , 0x1070103644000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP28_IP2_IO" , 0x1070103844000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP29_IP2_IO" , 0x1070103a44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP30_IP2_IO" , 0x1070103c44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP31_IP2_IO" , 0x1070103e44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP0_IP2_MEM" , 0x1070100045000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP1_IP2_MEM" , 0x1070100245000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP2_IP2_MEM" , 0x1070100445000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP3_IP2_MEM" , 0x1070100645000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP4_IP2_MEM" , 0x1070100845000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP5_IP2_MEM" , 0x1070100a45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP6_IP2_MEM" , 0x1070100c45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP7_IP2_MEM" , 0x1070100e45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP8_IP2_MEM" , 0x1070101045000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP9_IP2_MEM" , 0x1070101245000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP10_IP2_MEM" , 0x1070101445000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP11_IP2_MEM" , 0x1070101645000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP12_IP2_MEM" , 0x1070101845000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP13_IP2_MEM" , 0x1070101a45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP14_IP2_MEM" , 0x1070101c45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP15_IP2_MEM" , 0x1070101e45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP16_IP2_MEM" , 0x1070102045000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP17_IP2_MEM" , 0x1070102245000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP18_IP2_MEM" , 0x1070102445000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP19_IP2_MEM" , 0x1070102645000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP20_IP2_MEM" , 0x1070102845000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP21_IP2_MEM" , 0x1070102a45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP22_IP2_MEM" , 0x1070102c45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP23_IP2_MEM" , 0x1070102e45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP24_IP2_MEM" , 0x1070103045000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP25_IP2_MEM" , 0x1070103245000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP26_IP2_MEM" , 0x1070103445000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP27_IP2_MEM" , 0x1070103645000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP28_IP2_MEM" , 0x1070103845000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP29_IP2_MEM" , 0x1070103a45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP30_IP2_MEM" , 0x1070103c45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP31_IP2_MEM" , 0x1070103e45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP0_IP2_MIO" , 0x1070100043000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP1_IP2_MIO" , 0x1070100243000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP2_IP2_MIO" , 0x1070100443000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP3_IP2_MIO" , 0x1070100643000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP4_IP2_MIO" , 0x1070100843000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP5_IP2_MIO" , 0x1070100a43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP6_IP2_MIO" , 0x1070100c43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP7_IP2_MIO" , 0x1070100e43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP8_IP2_MIO" , 0x1070101043000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP9_IP2_MIO" , 0x1070101243000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP10_IP2_MIO" , 0x1070101443000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP11_IP2_MIO" , 0x1070101643000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP12_IP2_MIO" , 0x1070101843000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP13_IP2_MIO" , 0x1070101a43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP14_IP2_MIO" , 0x1070101c43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP15_IP2_MIO" , 0x1070101e43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP16_IP2_MIO" , 0x1070102043000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP17_IP2_MIO" , 0x1070102243000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP18_IP2_MIO" , 0x1070102443000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP19_IP2_MIO" , 0x1070102643000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP20_IP2_MIO" , 0x1070102843000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP21_IP2_MIO" , 0x1070102a43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP22_IP2_MIO" , 0x1070102c43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP23_IP2_MIO" , 0x1070102e43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP24_IP2_MIO" , 0x1070103043000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP25_IP2_MIO" , 0x1070103243000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP26_IP2_MIO" , 0x1070103443000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP27_IP2_MIO" , 0x1070103643000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP28_IP2_MIO" , 0x1070103843000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP29_IP2_MIO" , 0x1070103a43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP30_IP2_MIO" , 0x1070103c43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP31_IP2_MIO" , 0x1070103e43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP0_IP2_PKT" , 0x1070100046000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP1_IP2_PKT" , 0x1070100246000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP2_IP2_PKT" , 0x1070100446000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP3_IP2_PKT" , 0x1070100646000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP4_IP2_PKT" , 0x1070100846000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP5_IP2_PKT" , 0x1070100a46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP6_IP2_PKT" , 0x1070100c46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP7_IP2_PKT" , 0x1070100e46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP8_IP2_PKT" , 0x1070101046000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP9_IP2_PKT" , 0x1070101246000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP10_IP2_PKT" , 0x1070101446000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP11_IP2_PKT" , 0x1070101646000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP12_IP2_PKT" , 0x1070101846000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP13_IP2_PKT" , 0x1070101a46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP14_IP2_PKT" , 0x1070101c46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP15_IP2_PKT" , 0x1070101e46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP16_IP2_PKT" , 0x1070102046000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP17_IP2_PKT" , 0x1070102246000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP18_IP2_PKT" , 0x1070102446000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP19_IP2_PKT" , 0x1070102646000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP20_IP2_PKT" , 0x1070102846000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP21_IP2_PKT" , 0x1070102a46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP22_IP2_PKT" , 0x1070102c46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP23_IP2_PKT" , 0x1070102e46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP24_IP2_PKT" , 0x1070103046000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP25_IP2_PKT" , 0x1070103246000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP26_IP2_PKT" , 0x1070103446000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP27_IP2_PKT" , 0x1070103646000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP28_IP2_PKT" , 0x1070103846000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP29_IP2_PKT" , 0x1070103a46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP30_IP2_PKT" , 0x1070103c46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP31_IP2_PKT" , 0x1070103e46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP0_IP2_RML" , 0x1070100042000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP1_IP2_RML" , 0x1070100242000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP2_IP2_RML" , 0x1070100442000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP3_IP2_RML" , 0x1070100642000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP4_IP2_RML" , 0x1070100842000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP5_IP2_RML" , 0x1070100a42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP6_IP2_RML" , 0x1070100c42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP7_IP2_RML" , 0x1070100e42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP8_IP2_RML" , 0x1070101042000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP9_IP2_RML" , 0x1070101242000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP10_IP2_RML" , 0x1070101442000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP11_IP2_RML" , 0x1070101642000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP12_IP2_RML" , 0x1070101842000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP13_IP2_RML" , 0x1070101a42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP14_IP2_RML" , 0x1070101c42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP15_IP2_RML" , 0x1070101e42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP16_IP2_RML" , 0x1070102042000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP17_IP2_RML" , 0x1070102242000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP18_IP2_RML" , 0x1070102442000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP19_IP2_RML" , 0x1070102642000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP20_IP2_RML" , 0x1070102842000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP21_IP2_RML" , 0x1070102a42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP22_IP2_RML" , 0x1070102c42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP23_IP2_RML" , 0x1070102e42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP24_IP2_RML" , 0x1070103042000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP25_IP2_RML" , 0x1070103242000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP26_IP2_RML" , 0x1070103442000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP27_IP2_RML" , 0x1070103642000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP28_IP2_RML" , 0x1070103842000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP29_IP2_RML" , 0x1070103a42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP30_IP2_RML" , 0x1070103c42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP31_IP2_RML" , 0x1070103e42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP0_IP2_WDOG" , 0x1070100041000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP1_IP2_WDOG" , 0x1070100241000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP2_IP2_WDOG" , 0x1070100441000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP3_IP2_WDOG" , 0x1070100641000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP4_IP2_WDOG" , 0x1070100841000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP5_IP2_WDOG" , 0x1070100a41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP6_IP2_WDOG" , 0x1070100c41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP7_IP2_WDOG" , 0x1070100e41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP8_IP2_WDOG" , 0x1070101041000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP9_IP2_WDOG" , 0x1070101241000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP10_IP2_WDOG" , 0x1070101441000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP11_IP2_WDOG" , 0x1070101641000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP12_IP2_WDOG" , 0x1070101841000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP13_IP2_WDOG" , 0x1070101a41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP14_IP2_WDOG" , 0x1070101c41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP15_IP2_WDOG" , 0x1070101e41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP16_IP2_WDOG" , 0x1070102041000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP17_IP2_WDOG" , 0x1070102241000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP18_IP2_WDOG" , 0x1070102441000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP19_IP2_WDOG" , 0x1070102641000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP20_IP2_WDOG" , 0x1070102841000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP21_IP2_WDOG" , 0x1070102a41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP22_IP2_WDOG" , 0x1070102c41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP23_IP2_WDOG" , 0x1070102e41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP24_IP2_WDOG" , 0x1070103041000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP25_IP2_WDOG" , 0x1070103241000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP26_IP2_WDOG" , 0x1070103441000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP27_IP2_WDOG" , 0x1070103641000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP28_IP2_WDOG" , 0x1070103841000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP29_IP2_WDOG" , 0x1070103a41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP30_IP2_WDOG" , 0x1070103c41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP31_IP2_WDOG" , 0x1070103e41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP0_IP2_WRKQ" , 0x1070100040000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP1_IP2_WRKQ" , 0x1070100240000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP2_IP2_WRKQ" , 0x1070100440000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP3_IP2_WRKQ" , 0x1070100640000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP4_IP2_WRKQ" , 0x1070100840000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP5_IP2_WRKQ" , 0x1070100a40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP6_IP2_WRKQ" , 0x1070100c40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP7_IP2_WRKQ" , 0x1070100e40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP8_IP2_WRKQ" , 0x1070101040000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP9_IP2_WRKQ" , 0x1070101240000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP10_IP2_WRKQ" , 0x1070101440000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP11_IP2_WRKQ" , 0x1070101640000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP12_IP2_WRKQ" , 0x1070101840000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP13_IP2_WRKQ" , 0x1070101a40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP14_IP2_WRKQ" , 0x1070101c40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP15_IP2_WRKQ" , 0x1070101e40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP16_IP2_WRKQ" , 0x1070102040000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP17_IP2_WRKQ" , 0x1070102240000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP18_IP2_WRKQ" , 0x1070102440000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP19_IP2_WRKQ" , 0x1070102640000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP20_IP2_WRKQ" , 0x1070102840000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP21_IP2_WRKQ" , 0x1070102a40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP22_IP2_WRKQ" , 0x1070102c40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP23_IP2_WRKQ" , 0x1070102e40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP24_IP2_WRKQ" , 0x1070103040000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP25_IP2_WRKQ" , 0x1070103240000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP26_IP2_WRKQ" , 0x1070103440000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP27_IP2_WRKQ" , 0x1070103640000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP28_IP2_WRKQ" , 0x1070103840000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP29_IP2_WRKQ" , 0x1070103a40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP30_IP2_WRKQ" , 0x1070103c40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP31_IP2_WRKQ" , 0x1070103e40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP0_IP3_GPIO" , 0x1070100047200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP1_IP3_GPIO" , 0x1070100247200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP2_IP3_GPIO" , 0x1070100447200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP3_IP3_GPIO" , 0x1070100647200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP4_IP3_GPIO" , 0x1070100847200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP5_IP3_GPIO" , 0x1070100a47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP6_IP3_GPIO" , 0x1070100c47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP7_IP3_GPIO" , 0x1070100e47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP8_IP3_GPIO" , 0x1070101047200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP9_IP3_GPIO" , 0x1070101247200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP10_IP3_GPIO" , 0x1070101447200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP11_IP3_GPIO" , 0x1070101647200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP12_IP3_GPIO" , 0x1070101847200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP13_IP3_GPIO" , 0x1070101a47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP14_IP3_GPIO" , 0x1070101c47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP15_IP3_GPIO" , 0x1070101e47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP16_IP3_GPIO" , 0x1070102047200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP17_IP3_GPIO" , 0x1070102247200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP18_IP3_GPIO" , 0x1070102447200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP19_IP3_GPIO" , 0x1070102647200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP20_IP3_GPIO" , 0x1070102847200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP21_IP3_GPIO" , 0x1070102a47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP22_IP3_GPIO" , 0x1070102c47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP23_IP3_GPIO" , 0x1070102e47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP24_IP3_GPIO" , 0x1070103047200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP25_IP3_GPIO" , 0x1070103247200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP26_IP3_GPIO" , 0x1070103447200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP27_IP3_GPIO" , 0x1070103647200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP28_IP3_GPIO" , 0x1070103847200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP29_IP3_GPIO" , 0x1070103a47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP30_IP3_GPIO" , 0x1070103c47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP31_IP3_GPIO" , 0x1070103e47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP0_IP3_IO" , 0x1070100044200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP1_IP3_IO" , 0x1070100244200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP2_IP3_IO" , 0x1070100444200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP3_IP3_IO" , 0x1070100644200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP4_IP3_IO" , 0x1070100844200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP5_IP3_IO" , 0x1070100a44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP6_IP3_IO" , 0x1070100c44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP7_IP3_IO" , 0x1070100e44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP8_IP3_IO" , 0x1070101044200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP9_IP3_IO" , 0x1070101244200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP10_IP3_IO" , 0x1070101444200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP11_IP3_IO" , 0x1070101644200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP12_IP3_IO" , 0x1070101844200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP13_IP3_IO" , 0x1070101a44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP14_IP3_IO" , 0x1070101c44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP15_IP3_IO" , 0x1070101e44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP16_IP3_IO" , 0x1070102044200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP17_IP3_IO" , 0x1070102244200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP18_IP3_IO" , 0x1070102444200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP19_IP3_IO" , 0x1070102644200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP20_IP3_IO" , 0x1070102844200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP21_IP3_IO" , 0x1070102a44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP22_IP3_IO" , 0x1070102c44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP23_IP3_IO" , 0x1070102e44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP24_IP3_IO" , 0x1070103044200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP25_IP3_IO" , 0x1070103244200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP26_IP3_IO" , 0x1070103444200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP27_IP3_IO" , 0x1070103644200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP28_IP3_IO" , 0x1070103844200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP29_IP3_IO" , 0x1070103a44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP30_IP3_IO" , 0x1070103c44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP31_IP3_IO" , 0x1070103e44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP0_IP3_MEM" , 0x1070100045200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP1_IP3_MEM" , 0x1070100245200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP2_IP3_MEM" , 0x1070100445200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP3_IP3_MEM" , 0x1070100645200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP4_IP3_MEM" , 0x1070100845200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP5_IP3_MEM" , 0x1070100a45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP6_IP3_MEM" , 0x1070100c45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP7_IP3_MEM" , 0x1070100e45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP8_IP3_MEM" , 0x1070101045200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP9_IP3_MEM" , 0x1070101245200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP10_IP3_MEM" , 0x1070101445200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP11_IP3_MEM" , 0x1070101645200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP12_IP3_MEM" , 0x1070101845200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP13_IP3_MEM" , 0x1070101a45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP14_IP3_MEM" , 0x1070101c45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP15_IP3_MEM" , 0x1070101e45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP16_IP3_MEM" , 0x1070102045200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP17_IP3_MEM" , 0x1070102245200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP18_IP3_MEM" , 0x1070102445200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP19_IP3_MEM" , 0x1070102645200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP20_IP3_MEM" , 0x1070102845200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP21_IP3_MEM" , 0x1070102a45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP22_IP3_MEM" , 0x1070102c45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP23_IP3_MEM" , 0x1070102e45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP24_IP3_MEM" , 0x1070103045200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP25_IP3_MEM" , 0x1070103245200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP26_IP3_MEM" , 0x1070103445200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP27_IP3_MEM" , 0x1070103645200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP28_IP3_MEM" , 0x1070103845200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP29_IP3_MEM" , 0x1070103a45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP30_IP3_MEM" , 0x1070103c45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP31_IP3_MEM" , 0x1070103e45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP0_IP3_MIO" , 0x1070100043200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP1_IP3_MIO" , 0x1070100243200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP2_IP3_MIO" , 0x1070100443200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP3_IP3_MIO" , 0x1070100643200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP4_IP3_MIO" , 0x1070100843200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP5_IP3_MIO" , 0x1070100a43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP6_IP3_MIO" , 0x1070100c43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP7_IP3_MIO" , 0x1070100e43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP8_IP3_MIO" , 0x1070101043200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP9_IP3_MIO" , 0x1070101243200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP10_IP3_MIO" , 0x1070101443200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP11_IP3_MIO" , 0x1070101643200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP12_IP3_MIO" , 0x1070101843200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP13_IP3_MIO" , 0x1070101a43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP14_IP3_MIO" , 0x1070101c43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP15_IP3_MIO" , 0x1070101e43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP16_IP3_MIO" , 0x1070102043200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP17_IP3_MIO" , 0x1070102243200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP18_IP3_MIO" , 0x1070102443200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP19_IP3_MIO" , 0x1070102643200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP20_IP3_MIO" , 0x1070102843200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP21_IP3_MIO" , 0x1070102a43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP22_IP3_MIO" , 0x1070102c43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP23_IP3_MIO" , 0x1070102e43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP24_IP3_MIO" , 0x1070103043200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP25_IP3_MIO" , 0x1070103243200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP26_IP3_MIO" , 0x1070103443200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP27_IP3_MIO" , 0x1070103643200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP28_IP3_MIO" , 0x1070103843200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP29_IP3_MIO" , 0x1070103a43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP30_IP3_MIO" , 0x1070103c43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP31_IP3_MIO" , 0x1070103e43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP0_IP3_PKT" , 0x1070100046200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP1_IP3_PKT" , 0x1070100246200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP2_IP3_PKT" , 0x1070100446200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP3_IP3_PKT" , 0x1070100646200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP4_IP3_PKT" , 0x1070100846200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP5_IP3_PKT" , 0x1070100a46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP6_IP3_PKT" , 0x1070100c46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP7_IP3_PKT" , 0x1070100e46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP8_IP3_PKT" , 0x1070101046200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP9_IP3_PKT" , 0x1070101246200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP10_IP3_PKT" , 0x1070101446200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP11_IP3_PKT" , 0x1070101646200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP12_IP3_PKT" , 0x1070101846200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP13_IP3_PKT" , 0x1070101a46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP14_IP3_PKT" , 0x1070101c46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP15_IP3_PKT" , 0x1070101e46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP16_IP3_PKT" , 0x1070102046200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP17_IP3_PKT" , 0x1070102246200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP18_IP3_PKT" , 0x1070102446200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP19_IP3_PKT" , 0x1070102646200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP20_IP3_PKT" , 0x1070102846200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP21_IP3_PKT" , 0x1070102a46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP22_IP3_PKT" , 0x1070102c46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP23_IP3_PKT" , 0x1070102e46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP24_IP3_PKT" , 0x1070103046200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP25_IP3_PKT" , 0x1070103246200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP26_IP3_PKT" , 0x1070103446200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP27_IP3_PKT" , 0x1070103646200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP28_IP3_PKT" , 0x1070103846200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP29_IP3_PKT" , 0x1070103a46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP30_IP3_PKT" , 0x1070103c46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP31_IP3_PKT" , 0x1070103e46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP0_IP3_RML" , 0x1070100042200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP1_IP3_RML" , 0x1070100242200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP2_IP3_RML" , 0x1070100442200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP3_IP3_RML" , 0x1070100642200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP4_IP3_RML" , 0x1070100842200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP5_IP3_RML" , 0x1070100a42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP6_IP3_RML" , 0x1070100c42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP7_IP3_RML" , 0x1070100e42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP8_IP3_RML" , 0x1070101042200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP9_IP3_RML" , 0x1070101242200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP10_IP3_RML" , 0x1070101442200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP11_IP3_RML" , 0x1070101642200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP12_IP3_RML" , 0x1070101842200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP13_IP3_RML" , 0x1070101a42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP14_IP3_RML" , 0x1070101c42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP15_IP3_RML" , 0x1070101e42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP16_IP3_RML" , 0x1070102042200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP17_IP3_RML" , 0x1070102242200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP18_IP3_RML" , 0x1070102442200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP19_IP3_RML" , 0x1070102642200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP20_IP3_RML" , 0x1070102842200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP21_IP3_RML" , 0x1070102a42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP22_IP3_RML" , 0x1070102c42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP23_IP3_RML" , 0x1070102e42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP24_IP3_RML" , 0x1070103042200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP25_IP3_RML" , 0x1070103242200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP26_IP3_RML" , 0x1070103442200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP27_IP3_RML" , 0x1070103642200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP28_IP3_RML" , 0x1070103842200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP29_IP3_RML" , 0x1070103a42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP30_IP3_RML" , 0x1070103c42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP31_IP3_RML" , 0x1070103e42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP0_IP3_WDOG" , 0x1070100041200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP1_IP3_WDOG" , 0x1070100241200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP2_IP3_WDOG" , 0x1070100441200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP3_IP3_WDOG" , 0x1070100641200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP4_IP3_WDOG" , 0x1070100841200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP5_IP3_WDOG" , 0x1070100a41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP6_IP3_WDOG" , 0x1070100c41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP7_IP3_WDOG" , 0x1070100e41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP8_IP3_WDOG" , 0x1070101041200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP9_IP3_WDOG" , 0x1070101241200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP10_IP3_WDOG" , 0x1070101441200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP11_IP3_WDOG" , 0x1070101641200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP12_IP3_WDOG" , 0x1070101841200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP13_IP3_WDOG" , 0x1070101a41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP14_IP3_WDOG" , 0x1070101c41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP15_IP3_WDOG" , 0x1070101e41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP16_IP3_WDOG" , 0x1070102041200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP17_IP3_WDOG" , 0x1070102241200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP18_IP3_WDOG" , 0x1070102441200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP19_IP3_WDOG" , 0x1070102641200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP20_IP3_WDOG" , 0x1070102841200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP21_IP3_WDOG" , 0x1070102a41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP22_IP3_WDOG" , 0x1070102c41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP23_IP3_WDOG" , 0x1070102e41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP24_IP3_WDOG" , 0x1070103041200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP25_IP3_WDOG" , 0x1070103241200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP26_IP3_WDOG" , 0x1070103441200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP27_IP3_WDOG" , 0x1070103641200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP28_IP3_WDOG" , 0x1070103841200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP29_IP3_WDOG" , 0x1070103a41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP30_IP3_WDOG" , 0x1070103c41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP31_IP3_WDOG" , 0x1070103e41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP0_IP3_WRKQ" , 0x1070100040200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP1_IP3_WRKQ" , 0x1070100240200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP2_IP3_WRKQ" , 0x1070100440200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP3_IP3_WRKQ" , 0x1070100640200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP4_IP3_WRKQ" , 0x1070100840200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP5_IP3_WRKQ" , 0x1070100a40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP6_IP3_WRKQ" , 0x1070100c40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP7_IP3_WRKQ" , 0x1070100e40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP8_IP3_WRKQ" , 0x1070101040200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP9_IP3_WRKQ" , 0x1070101240200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP10_IP3_WRKQ" , 0x1070101440200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP11_IP3_WRKQ" , 0x1070101640200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP12_IP3_WRKQ" , 0x1070101840200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP13_IP3_WRKQ" , 0x1070101a40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP14_IP3_WRKQ" , 0x1070101c40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP15_IP3_WRKQ" , 0x1070101e40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP16_IP3_WRKQ" , 0x1070102040200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP17_IP3_WRKQ" , 0x1070102240200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP18_IP3_WRKQ" , 0x1070102440200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP19_IP3_WRKQ" , 0x1070102640200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP20_IP3_WRKQ" , 0x1070102840200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP21_IP3_WRKQ" , 0x1070102a40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP22_IP3_WRKQ" , 0x1070102c40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP23_IP3_WRKQ" , 0x1070102e40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP24_IP3_WRKQ" , 0x1070103040200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP25_IP3_WRKQ" , 0x1070103240200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP26_IP3_WRKQ" , 0x1070103440200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP27_IP3_WRKQ" , 0x1070103640200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP28_IP3_WRKQ" , 0x1070103840200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP29_IP3_WRKQ" , 0x1070103a40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP30_IP3_WRKQ" , 0x1070103c40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP31_IP3_WRKQ" , 0x1070103e40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP0_IP4_GPIO" , 0x1070100047400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP1_IP4_GPIO" , 0x1070100247400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP2_IP4_GPIO" , 0x1070100447400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP3_IP4_GPIO" , 0x1070100647400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP4_IP4_GPIO" , 0x1070100847400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP5_IP4_GPIO" , 0x1070100a47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP6_IP4_GPIO" , 0x1070100c47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP7_IP4_GPIO" , 0x1070100e47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP8_IP4_GPIO" , 0x1070101047400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP9_IP4_GPIO" , 0x1070101247400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP10_IP4_GPIO" , 0x1070101447400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP11_IP4_GPIO" , 0x1070101647400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP12_IP4_GPIO" , 0x1070101847400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP13_IP4_GPIO" , 0x1070101a47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP14_IP4_GPIO" , 0x1070101c47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP15_IP4_GPIO" , 0x1070101e47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP16_IP4_GPIO" , 0x1070102047400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP17_IP4_GPIO" , 0x1070102247400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP18_IP4_GPIO" , 0x1070102447400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP19_IP4_GPIO" , 0x1070102647400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP20_IP4_GPIO" , 0x1070102847400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP21_IP4_GPIO" , 0x1070102a47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP22_IP4_GPIO" , 0x1070102c47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP23_IP4_GPIO" , 0x1070102e47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP24_IP4_GPIO" , 0x1070103047400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP25_IP4_GPIO" , 0x1070103247400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP26_IP4_GPIO" , 0x1070103447400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP27_IP4_GPIO" , 0x1070103647400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP28_IP4_GPIO" , 0x1070103847400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP29_IP4_GPIO" , 0x1070103a47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP30_IP4_GPIO" , 0x1070103c47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP31_IP4_GPIO" , 0x1070103e47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP0_IP4_IO" , 0x1070100044400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP1_IP4_IO" , 0x1070100244400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP2_IP4_IO" , 0x1070100444400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP3_IP4_IO" , 0x1070100644400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP4_IP4_IO" , 0x1070100844400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP5_IP4_IO" , 0x1070100a44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP6_IP4_IO" , 0x1070100c44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP7_IP4_IO" , 0x1070100e44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP8_IP4_IO" , 0x1070101044400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP9_IP4_IO" , 0x1070101244400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP10_IP4_IO" , 0x1070101444400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP11_IP4_IO" , 0x1070101644400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP12_IP4_IO" , 0x1070101844400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP13_IP4_IO" , 0x1070101a44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP14_IP4_IO" , 0x1070101c44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP15_IP4_IO" , 0x1070101e44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP16_IP4_IO" , 0x1070102044400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP17_IP4_IO" , 0x1070102244400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP18_IP4_IO" , 0x1070102444400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP19_IP4_IO" , 0x1070102644400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP20_IP4_IO" , 0x1070102844400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP21_IP4_IO" , 0x1070102a44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP22_IP4_IO" , 0x1070102c44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP23_IP4_IO" , 0x1070102e44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP24_IP4_IO" , 0x1070103044400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP25_IP4_IO" , 0x1070103244400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP26_IP4_IO" , 0x1070103444400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP27_IP4_IO" , 0x1070103644400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP28_IP4_IO" , 0x1070103844400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP29_IP4_IO" , 0x1070103a44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP30_IP4_IO" , 0x1070103c44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP31_IP4_IO" , 0x1070103e44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP0_IP4_MEM" , 0x1070100045400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP1_IP4_MEM" , 0x1070100245400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP2_IP4_MEM" , 0x1070100445400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP3_IP4_MEM" , 0x1070100645400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP4_IP4_MEM" , 0x1070100845400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP5_IP4_MEM" , 0x1070100a45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP6_IP4_MEM" , 0x1070100c45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP7_IP4_MEM" , 0x1070100e45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP8_IP4_MEM" , 0x1070101045400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP9_IP4_MEM" , 0x1070101245400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP10_IP4_MEM" , 0x1070101445400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP11_IP4_MEM" , 0x1070101645400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP12_IP4_MEM" , 0x1070101845400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP13_IP4_MEM" , 0x1070101a45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP14_IP4_MEM" , 0x1070101c45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP15_IP4_MEM" , 0x1070101e45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP16_IP4_MEM" , 0x1070102045400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP17_IP4_MEM" , 0x1070102245400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP18_IP4_MEM" , 0x1070102445400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP19_IP4_MEM" , 0x1070102645400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP20_IP4_MEM" , 0x1070102845400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP21_IP4_MEM" , 0x1070102a45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP22_IP4_MEM" , 0x1070102c45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP23_IP4_MEM" , 0x1070102e45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP24_IP4_MEM" , 0x1070103045400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP25_IP4_MEM" , 0x1070103245400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP26_IP4_MEM" , 0x1070103445400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP27_IP4_MEM" , 0x1070103645400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP28_IP4_MEM" , 0x1070103845400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP29_IP4_MEM" , 0x1070103a45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP30_IP4_MEM" , 0x1070103c45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP31_IP4_MEM" , 0x1070103e45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP0_IP4_MIO" , 0x1070100043400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP1_IP4_MIO" , 0x1070100243400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP2_IP4_MIO" , 0x1070100443400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP3_IP4_MIO" , 0x1070100643400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP4_IP4_MIO" , 0x1070100843400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP5_IP4_MIO" , 0x1070100a43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP6_IP4_MIO" , 0x1070100c43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP7_IP4_MIO" , 0x1070100e43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP8_IP4_MIO" , 0x1070101043400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP9_IP4_MIO" , 0x1070101243400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP10_IP4_MIO" , 0x1070101443400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP11_IP4_MIO" , 0x1070101643400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP12_IP4_MIO" , 0x1070101843400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP13_IP4_MIO" , 0x1070101a43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP14_IP4_MIO" , 0x1070101c43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP15_IP4_MIO" , 0x1070101e43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP16_IP4_MIO" , 0x1070102043400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP17_IP4_MIO" , 0x1070102243400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP18_IP4_MIO" , 0x1070102443400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP19_IP4_MIO" , 0x1070102643400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP20_IP4_MIO" , 0x1070102843400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP21_IP4_MIO" , 0x1070102a43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP22_IP4_MIO" , 0x1070102c43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP23_IP4_MIO" , 0x1070102e43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP24_IP4_MIO" , 0x1070103043400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP25_IP4_MIO" , 0x1070103243400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP26_IP4_MIO" , 0x1070103443400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP27_IP4_MIO" , 0x1070103643400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP28_IP4_MIO" , 0x1070103843400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP29_IP4_MIO" , 0x1070103a43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP30_IP4_MIO" , 0x1070103c43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP31_IP4_MIO" , 0x1070103e43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP0_IP4_PKT" , 0x1070100046400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP1_IP4_PKT" , 0x1070100246400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP2_IP4_PKT" , 0x1070100446400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP3_IP4_PKT" , 0x1070100646400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP4_IP4_PKT" , 0x1070100846400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP5_IP4_PKT" , 0x1070100a46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP6_IP4_PKT" , 0x1070100c46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP7_IP4_PKT" , 0x1070100e46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP8_IP4_PKT" , 0x1070101046400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP9_IP4_PKT" , 0x1070101246400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP10_IP4_PKT" , 0x1070101446400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP11_IP4_PKT" , 0x1070101646400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP12_IP4_PKT" , 0x1070101846400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP13_IP4_PKT" , 0x1070101a46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP14_IP4_PKT" , 0x1070101c46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP15_IP4_PKT" , 0x1070101e46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP16_IP4_PKT" , 0x1070102046400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP17_IP4_PKT" , 0x1070102246400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP18_IP4_PKT" , 0x1070102446400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP19_IP4_PKT" , 0x1070102646400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP20_IP4_PKT" , 0x1070102846400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP21_IP4_PKT" , 0x1070102a46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP22_IP4_PKT" , 0x1070102c46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP23_IP4_PKT" , 0x1070102e46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP24_IP4_PKT" , 0x1070103046400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP25_IP4_PKT" , 0x1070103246400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP26_IP4_PKT" , 0x1070103446400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP27_IP4_PKT" , 0x1070103646400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP28_IP4_PKT" , 0x1070103846400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP29_IP4_PKT" , 0x1070103a46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP30_IP4_PKT" , 0x1070103c46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP31_IP4_PKT" , 0x1070103e46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP0_IP4_RML" , 0x1070100042400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP1_IP4_RML" , 0x1070100242400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP2_IP4_RML" , 0x1070100442400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP3_IP4_RML" , 0x1070100642400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP4_IP4_RML" , 0x1070100842400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP5_IP4_RML" , 0x1070100a42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP6_IP4_RML" , 0x1070100c42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP7_IP4_RML" , 0x1070100e42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP8_IP4_RML" , 0x1070101042400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP9_IP4_RML" , 0x1070101242400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP10_IP4_RML" , 0x1070101442400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP11_IP4_RML" , 0x1070101642400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP12_IP4_RML" , 0x1070101842400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP13_IP4_RML" , 0x1070101a42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP14_IP4_RML" , 0x1070101c42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP15_IP4_RML" , 0x1070101e42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP16_IP4_RML" , 0x1070102042400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP17_IP4_RML" , 0x1070102242400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP18_IP4_RML" , 0x1070102442400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP19_IP4_RML" , 0x1070102642400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP20_IP4_RML" , 0x1070102842400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP21_IP4_RML" , 0x1070102a42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP22_IP4_RML" , 0x1070102c42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP23_IP4_RML" , 0x1070102e42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP24_IP4_RML" , 0x1070103042400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP25_IP4_RML" , 0x1070103242400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP26_IP4_RML" , 0x1070103442400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP27_IP4_RML" , 0x1070103642400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP28_IP4_RML" , 0x1070103842400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP29_IP4_RML" , 0x1070103a42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP30_IP4_RML" , 0x1070103c42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP31_IP4_RML" , 0x1070103e42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP0_IP4_WDOG" , 0x1070100041400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP1_IP4_WDOG" , 0x1070100241400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP2_IP4_WDOG" , 0x1070100441400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP3_IP4_WDOG" , 0x1070100641400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP4_IP4_WDOG" , 0x1070100841400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP5_IP4_WDOG" , 0x1070100a41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP6_IP4_WDOG" , 0x1070100c41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP7_IP4_WDOG" , 0x1070100e41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP8_IP4_WDOG" , 0x1070101041400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP9_IP4_WDOG" , 0x1070101241400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP10_IP4_WDOG" , 0x1070101441400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP11_IP4_WDOG" , 0x1070101641400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP12_IP4_WDOG" , 0x1070101841400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP13_IP4_WDOG" , 0x1070101a41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP14_IP4_WDOG" , 0x1070101c41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP15_IP4_WDOG" , 0x1070101e41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP16_IP4_WDOG" , 0x1070102041400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP17_IP4_WDOG" , 0x1070102241400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP18_IP4_WDOG" , 0x1070102441400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP19_IP4_WDOG" , 0x1070102641400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP20_IP4_WDOG" , 0x1070102841400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP21_IP4_WDOG" , 0x1070102a41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP22_IP4_WDOG" , 0x1070102c41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP23_IP4_WDOG" , 0x1070102e41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP24_IP4_WDOG" , 0x1070103041400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP25_IP4_WDOG" , 0x1070103241400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP26_IP4_WDOG" , 0x1070103441400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP27_IP4_WDOG" , 0x1070103641400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP28_IP4_WDOG" , 0x1070103841400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP29_IP4_WDOG" , 0x1070103a41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP30_IP4_WDOG" , 0x1070103c41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP31_IP4_WDOG" , 0x1070103e41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP0_IP4_WRKQ" , 0x1070100040400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP1_IP4_WRKQ" , 0x1070100240400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP2_IP4_WRKQ" , 0x1070100440400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP3_IP4_WRKQ" , 0x1070100640400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP4_IP4_WRKQ" , 0x1070100840400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP5_IP4_WRKQ" , 0x1070100a40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP6_IP4_WRKQ" , 0x1070100c40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP7_IP4_WRKQ" , 0x1070100e40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP8_IP4_WRKQ" , 0x1070101040400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP9_IP4_WRKQ" , 0x1070101240400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP10_IP4_WRKQ" , 0x1070101440400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP11_IP4_WRKQ" , 0x1070101640400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP12_IP4_WRKQ" , 0x1070101840400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP13_IP4_WRKQ" , 0x1070101a40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP14_IP4_WRKQ" , 0x1070101c40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP15_IP4_WRKQ" , 0x1070101e40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP16_IP4_WRKQ" , 0x1070102040400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP17_IP4_WRKQ" , 0x1070102240400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP18_IP4_WRKQ" , 0x1070102440400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP19_IP4_WRKQ" , 0x1070102640400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP20_IP4_WRKQ" , 0x1070102840400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP21_IP4_WRKQ" , 0x1070102a40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP22_IP4_WRKQ" , 0x1070102c40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP23_IP4_WRKQ" , 0x1070102e40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP24_IP4_WRKQ" , 0x1070103040400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP25_IP4_WRKQ" , 0x1070103240400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP26_IP4_WRKQ" , 0x1070103440400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP27_IP4_WRKQ" , 0x1070103640400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP28_IP4_WRKQ" , 0x1070103840400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP29_IP4_WRKQ" , 0x1070103a40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP30_IP4_WRKQ" , 0x1070103c40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP31_IP4_WRKQ" , 0x1070103e40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_SRC_IO0_INT_GPIO" , 0x1070108087800ull, CVMX_CSR_DB_TYPE_NCB, 64, 225},
- {"CIU2_SRC_IO1_INT_GPIO" , 0x1070108287800ull, CVMX_CSR_DB_TYPE_NCB, 64, 225},
- {"CIU2_SRC_IO0_INT_IO" , 0x1070108084800ull, CVMX_CSR_DB_TYPE_NCB, 64, 226},
- {"CIU2_SRC_IO1_INT_IO" , 0x1070108284800ull, CVMX_CSR_DB_TYPE_NCB, 64, 226},
- {"CIU2_SRC_IO0_INT_MBOX" , 0x1070108088800ull, CVMX_CSR_DB_TYPE_NCB, 64, 227},
- {"CIU2_SRC_IO1_INT_MBOX" , 0x1070108288800ull, CVMX_CSR_DB_TYPE_NCB, 64, 227},
- {"CIU2_SRC_IO0_INT_MEM" , 0x1070108085800ull, CVMX_CSR_DB_TYPE_NCB, 64, 228},
- {"CIU2_SRC_IO1_INT_MEM" , 0x1070108285800ull, CVMX_CSR_DB_TYPE_NCB, 64, 228},
- {"CIU2_SRC_IO0_INT_MIO" , 0x1070108083800ull, CVMX_CSR_DB_TYPE_NCB, 64, 229},
- {"CIU2_SRC_IO1_INT_MIO" , 0x1070108283800ull, CVMX_CSR_DB_TYPE_NCB, 64, 229},
- {"CIU2_SRC_IO0_INT_PKT" , 0x1070108086800ull, CVMX_CSR_DB_TYPE_NCB, 64, 230},
- {"CIU2_SRC_IO1_INT_PKT" , 0x1070108286800ull, CVMX_CSR_DB_TYPE_NCB, 64, 230},
- {"CIU2_SRC_IO0_INT_RML" , 0x1070108082800ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"CIU2_SRC_IO1_INT_RML" , 0x1070108282800ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"CIU2_SRC_IO0_INT_WDOG" , 0x1070108081800ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"CIU2_SRC_IO1_INT_WDOG" , 0x1070108281800ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"CIU2_SRC_IO0_INT_WRKQ" , 0x1070108080800ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"CIU2_SRC_IO1_INT_WRKQ" , 0x1070108280800ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"CIU2_SRC_PP0_IP2_GPIO" , 0x1070100087000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP1_IP2_GPIO" , 0x1070100287000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP2_IP2_GPIO" , 0x1070100487000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP3_IP2_GPIO" , 0x1070100687000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP4_IP2_GPIO" , 0x1070100887000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP5_IP2_GPIO" , 0x1070100a87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP6_IP2_GPIO" , 0x1070100c87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP7_IP2_GPIO" , 0x1070100e87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP8_IP2_GPIO" , 0x1070101087000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP9_IP2_GPIO" , 0x1070101287000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP10_IP2_GPIO" , 0x1070101487000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP11_IP2_GPIO" , 0x1070101687000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP12_IP2_GPIO" , 0x1070101887000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP13_IP2_GPIO" , 0x1070101a87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP14_IP2_GPIO" , 0x1070101c87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP15_IP2_GPIO" , 0x1070101e87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP16_IP2_GPIO" , 0x1070102087000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP17_IP2_GPIO" , 0x1070102287000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP18_IP2_GPIO" , 0x1070102487000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP19_IP2_GPIO" , 0x1070102687000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP20_IP2_GPIO" , 0x1070102887000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP21_IP2_GPIO" , 0x1070102a87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP22_IP2_GPIO" , 0x1070102c87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP23_IP2_GPIO" , 0x1070102e87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP24_IP2_GPIO" , 0x1070103087000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP25_IP2_GPIO" , 0x1070103287000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP26_IP2_GPIO" , 0x1070103487000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP27_IP2_GPIO" , 0x1070103687000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP28_IP2_GPIO" , 0x1070103887000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP29_IP2_GPIO" , 0x1070103a87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP30_IP2_GPIO" , 0x1070103c87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP31_IP2_GPIO" , 0x1070103e87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP0_IP2_IO" , 0x1070100084000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP1_IP2_IO" , 0x1070100284000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP2_IP2_IO" , 0x1070100484000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP3_IP2_IO" , 0x1070100684000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP4_IP2_IO" , 0x1070100884000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP5_IP2_IO" , 0x1070100a84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP6_IP2_IO" , 0x1070100c84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP7_IP2_IO" , 0x1070100e84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP8_IP2_IO" , 0x1070101084000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP9_IP2_IO" , 0x1070101284000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP10_IP2_IO" , 0x1070101484000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP11_IP2_IO" , 0x1070101684000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP12_IP2_IO" , 0x1070101884000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP13_IP2_IO" , 0x1070101a84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP14_IP2_IO" , 0x1070101c84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP15_IP2_IO" , 0x1070101e84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP16_IP2_IO" , 0x1070102084000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP17_IP2_IO" , 0x1070102284000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP18_IP2_IO" , 0x1070102484000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP19_IP2_IO" , 0x1070102684000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP20_IP2_IO" , 0x1070102884000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP21_IP2_IO" , 0x1070102a84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP22_IP2_IO" , 0x1070102c84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP23_IP2_IO" , 0x1070102e84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP24_IP2_IO" , 0x1070103084000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP25_IP2_IO" , 0x1070103284000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP26_IP2_IO" , 0x1070103484000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP27_IP2_IO" , 0x1070103684000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP28_IP2_IO" , 0x1070103884000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP29_IP2_IO" , 0x1070103a84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP30_IP2_IO" , 0x1070103c84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP31_IP2_IO" , 0x1070103e84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP0_IP2_MBOX" , 0x1070100088000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP1_IP2_MBOX" , 0x1070100288000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP2_IP2_MBOX" , 0x1070100488000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP3_IP2_MBOX" , 0x1070100688000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP4_IP2_MBOX" , 0x1070100888000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP5_IP2_MBOX" , 0x1070100a88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP6_IP2_MBOX" , 0x1070100c88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP7_IP2_MBOX" , 0x1070100e88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP8_IP2_MBOX" , 0x1070101088000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP9_IP2_MBOX" , 0x1070101288000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP10_IP2_MBOX" , 0x1070101488000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP11_IP2_MBOX" , 0x1070101688000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP12_IP2_MBOX" , 0x1070101888000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP13_IP2_MBOX" , 0x1070101a88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP14_IP2_MBOX" , 0x1070101c88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP15_IP2_MBOX" , 0x1070101e88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP16_IP2_MBOX" , 0x1070102088000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP17_IP2_MBOX" , 0x1070102288000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP18_IP2_MBOX" , 0x1070102488000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP19_IP2_MBOX" , 0x1070102688000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP20_IP2_MBOX" , 0x1070102888000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP21_IP2_MBOX" , 0x1070102a88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP22_IP2_MBOX" , 0x1070102c88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP23_IP2_MBOX" , 0x1070102e88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP24_IP2_MBOX" , 0x1070103088000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP25_IP2_MBOX" , 0x1070103288000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP26_IP2_MBOX" , 0x1070103488000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP27_IP2_MBOX" , 0x1070103688000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP28_IP2_MBOX" , 0x1070103888000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP29_IP2_MBOX" , 0x1070103a88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP30_IP2_MBOX" , 0x1070103c88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP31_IP2_MBOX" , 0x1070103e88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP0_IP2_MEM" , 0x1070100085000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP1_IP2_MEM" , 0x1070100285000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP2_IP2_MEM" , 0x1070100485000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP3_IP2_MEM" , 0x1070100685000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP4_IP2_MEM" , 0x1070100885000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP5_IP2_MEM" , 0x1070100a85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP6_IP2_MEM" , 0x1070100c85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP7_IP2_MEM" , 0x1070100e85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP8_IP2_MEM" , 0x1070101085000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP9_IP2_MEM" , 0x1070101285000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP10_IP2_MEM" , 0x1070101485000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP11_IP2_MEM" , 0x1070101685000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP12_IP2_MEM" , 0x1070101885000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP13_IP2_MEM" , 0x1070101a85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP14_IP2_MEM" , 0x1070101c85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP15_IP2_MEM" , 0x1070101e85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP16_IP2_MEM" , 0x1070102085000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP17_IP2_MEM" , 0x1070102285000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP18_IP2_MEM" , 0x1070102485000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP19_IP2_MEM" , 0x1070102685000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP20_IP2_MEM" , 0x1070102885000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP21_IP2_MEM" , 0x1070102a85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP22_IP2_MEM" , 0x1070102c85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP23_IP2_MEM" , 0x1070102e85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP24_IP2_MEM" , 0x1070103085000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP25_IP2_MEM" , 0x1070103285000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP26_IP2_MEM" , 0x1070103485000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP27_IP2_MEM" , 0x1070103685000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP28_IP2_MEM" , 0x1070103885000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP29_IP2_MEM" , 0x1070103a85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP30_IP2_MEM" , 0x1070103c85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP31_IP2_MEM" , 0x1070103e85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP0_IP2_MIO" , 0x1070100083000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP1_IP2_MIO" , 0x1070100283000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP2_IP2_MIO" , 0x1070100483000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP3_IP2_MIO" , 0x1070100683000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP4_IP2_MIO" , 0x1070100883000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP5_IP2_MIO" , 0x1070100a83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP6_IP2_MIO" , 0x1070100c83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP7_IP2_MIO" , 0x1070100e83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP8_IP2_MIO" , 0x1070101083000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP9_IP2_MIO" , 0x1070101283000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP10_IP2_MIO" , 0x1070101483000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP11_IP2_MIO" , 0x1070101683000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP12_IP2_MIO" , 0x1070101883000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP13_IP2_MIO" , 0x1070101a83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP14_IP2_MIO" , 0x1070101c83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP15_IP2_MIO" , 0x1070101e83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP16_IP2_MIO" , 0x1070102083000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP17_IP2_MIO" , 0x1070102283000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP18_IP2_MIO" , 0x1070102483000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP19_IP2_MIO" , 0x1070102683000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP20_IP2_MIO" , 0x1070102883000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP21_IP2_MIO" , 0x1070102a83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP22_IP2_MIO" , 0x1070102c83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP23_IP2_MIO" , 0x1070102e83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP24_IP2_MIO" , 0x1070103083000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP25_IP2_MIO" , 0x1070103283000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP26_IP2_MIO" , 0x1070103483000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP27_IP2_MIO" , 0x1070103683000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP28_IP2_MIO" , 0x1070103883000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP29_IP2_MIO" , 0x1070103a83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP30_IP2_MIO" , 0x1070103c83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP31_IP2_MIO" , 0x1070103e83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP0_IP2_PKT" , 0x1070100086000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP1_IP2_PKT" , 0x1070100286000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP2_IP2_PKT" , 0x1070100486000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP3_IP2_PKT" , 0x1070100686000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP4_IP2_PKT" , 0x1070100886000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP5_IP2_PKT" , 0x1070100a86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP6_IP2_PKT" , 0x1070100c86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP7_IP2_PKT" , 0x1070100e86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP8_IP2_PKT" , 0x1070101086000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP9_IP2_PKT" , 0x1070101286000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP10_IP2_PKT" , 0x1070101486000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP11_IP2_PKT" , 0x1070101686000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP12_IP2_PKT" , 0x1070101886000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP13_IP2_PKT" , 0x1070101a86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP14_IP2_PKT" , 0x1070101c86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP15_IP2_PKT" , 0x1070101e86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP16_IP2_PKT" , 0x1070102086000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP17_IP2_PKT" , 0x1070102286000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP18_IP2_PKT" , 0x1070102486000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP19_IP2_PKT" , 0x1070102686000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP20_IP2_PKT" , 0x1070102886000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP21_IP2_PKT" , 0x1070102a86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP22_IP2_PKT" , 0x1070102c86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP23_IP2_PKT" , 0x1070102e86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP24_IP2_PKT" , 0x1070103086000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP25_IP2_PKT" , 0x1070103286000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP26_IP2_PKT" , 0x1070103486000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP27_IP2_PKT" , 0x1070103686000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP28_IP2_PKT" , 0x1070103886000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP29_IP2_PKT" , 0x1070103a86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP30_IP2_PKT" , 0x1070103c86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP31_IP2_PKT" , 0x1070103e86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP0_IP2_RML" , 0x1070100082000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP1_IP2_RML" , 0x1070100282000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP2_IP2_RML" , 0x1070100482000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP3_IP2_RML" , 0x1070100682000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP4_IP2_RML" , 0x1070100882000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP5_IP2_RML" , 0x1070100a82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP6_IP2_RML" , 0x1070100c82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP7_IP2_RML" , 0x1070100e82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP8_IP2_RML" , 0x1070101082000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP9_IP2_RML" , 0x1070101282000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP10_IP2_RML" , 0x1070101482000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP11_IP2_RML" , 0x1070101682000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP12_IP2_RML" , 0x1070101882000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP13_IP2_RML" , 0x1070101a82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP14_IP2_RML" , 0x1070101c82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP15_IP2_RML" , 0x1070101e82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP16_IP2_RML" , 0x1070102082000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP17_IP2_RML" , 0x1070102282000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP18_IP2_RML" , 0x1070102482000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP19_IP2_RML" , 0x1070102682000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP20_IP2_RML" , 0x1070102882000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP21_IP2_RML" , 0x1070102a82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP22_IP2_RML" , 0x1070102c82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP23_IP2_RML" , 0x1070102e82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP24_IP2_RML" , 0x1070103082000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP25_IP2_RML" , 0x1070103282000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP26_IP2_RML" , 0x1070103482000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP27_IP2_RML" , 0x1070103682000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP28_IP2_RML" , 0x1070103882000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP29_IP2_RML" , 0x1070103a82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP30_IP2_RML" , 0x1070103c82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP31_IP2_RML" , 0x1070103e82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP0_IP2_WDOG" , 0x1070100081000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP1_IP2_WDOG" , 0x1070100281000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP2_IP2_WDOG" , 0x1070100481000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP3_IP2_WDOG" , 0x1070100681000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP4_IP2_WDOG" , 0x1070100881000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP5_IP2_WDOG" , 0x1070100a81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP6_IP2_WDOG" , 0x1070100c81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP7_IP2_WDOG" , 0x1070100e81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP8_IP2_WDOG" , 0x1070101081000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP9_IP2_WDOG" , 0x1070101281000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP10_IP2_WDOG" , 0x1070101481000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP11_IP2_WDOG" , 0x1070101681000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP12_IP2_WDOG" , 0x1070101881000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP13_IP2_WDOG" , 0x1070101a81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP14_IP2_WDOG" , 0x1070101c81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP15_IP2_WDOG" , 0x1070101e81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP16_IP2_WDOG" , 0x1070102081000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP17_IP2_WDOG" , 0x1070102281000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP18_IP2_WDOG" , 0x1070102481000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP19_IP2_WDOG" , 0x1070102681000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP20_IP2_WDOG" , 0x1070102881000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP21_IP2_WDOG" , 0x1070102a81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP22_IP2_WDOG" , 0x1070102c81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP23_IP2_WDOG" , 0x1070102e81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP24_IP2_WDOG" , 0x1070103081000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP25_IP2_WDOG" , 0x1070103281000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP26_IP2_WDOG" , 0x1070103481000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP27_IP2_WDOG" , 0x1070103681000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP28_IP2_WDOG" , 0x1070103881000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP29_IP2_WDOG" , 0x1070103a81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP30_IP2_WDOG" , 0x1070103c81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP31_IP2_WDOG" , 0x1070103e81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP0_IP2_WRKQ" , 0x1070100080000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP1_IP2_WRKQ" , 0x1070100280000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP2_IP2_WRKQ" , 0x1070100480000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP3_IP2_WRKQ" , 0x1070100680000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP4_IP2_WRKQ" , 0x1070100880000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP5_IP2_WRKQ" , 0x1070100a80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP6_IP2_WRKQ" , 0x1070100c80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP7_IP2_WRKQ" , 0x1070100e80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP8_IP2_WRKQ" , 0x1070101080000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP9_IP2_WRKQ" , 0x1070101280000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP10_IP2_WRKQ" , 0x1070101480000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP11_IP2_WRKQ" , 0x1070101680000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP12_IP2_WRKQ" , 0x1070101880000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP13_IP2_WRKQ" , 0x1070101a80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP14_IP2_WRKQ" , 0x1070101c80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP15_IP2_WRKQ" , 0x1070101e80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP16_IP2_WRKQ" , 0x1070102080000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP17_IP2_WRKQ" , 0x1070102280000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP18_IP2_WRKQ" , 0x1070102480000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP19_IP2_WRKQ" , 0x1070102680000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP20_IP2_WRKQ" , 0x1070102880000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP21_IP2_WRKQ" , 0x1070102a80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP22_IP2_WRKQ" , 0x1070102c80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP23_IP2_WRKQ" , 0x1070102e80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP24_IP2_WRKQ" , 0x1070103080000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP25_IP2_WRKQ" , 0x1070103280000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP26_IP2_WRKQ" , 0x1070103480000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP27_IP2_WRKQ" , 0x1070103680000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP28_IP2_WRKQ" , 0x1070103880000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP29_IP2_WRKQ" , 0x1070103a80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP30_IP2_WRKQ" , 0x1070103c80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP31_IP2_WRKQ" , 0x1070103e80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP0_IP3_GPIO" , 0x1070100087200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP1_IP3_GPIO" , 0x1070100287200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP2_IP3_GPIO" , 0x1070100487200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP3_IP3_GPIO" , 0x1070100687200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP4_IP3_GPIO" , 0x1070100887200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP5_IP3_GPIO" , 0x1070100a87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP6_IP3_GPIO" , 0x1070100c87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP7_IP3_GPIO" , 0x1070100e87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP8_IP3_GPIO" , 0x1070101087200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP9_IP3_GPIO" , 0x1070101287200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP10_IP3_GPIO" , 0x1070101487200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP11_IP3_GPIO" , 0x1070101687200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP12_IP3_GPIO" , 0x1070101887200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP13_IP3_GPIO" , 0x1070101a87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP14_IP3_GPIO" , 0x1070101c87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP15_IP3_GPIO" , 0x1070101e87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP16_IP3_GPIO" , 0x1070102087200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP17_IP3_GPIO" , 0x1070102287200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP18_IP3_GPIO" , 0x1070102487200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP19_IP3_GPIO" , 0x1070102687200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP20_IP3_GPIO" , 0x1070102887200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP21_IP3_GPIO" , 0x1070102a87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP22_IP3_GPIO" , 0x1070102c87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP23_IP3_GPIO" , 0x1070102e87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP24_IP3_GPIO" , 0x1070103087200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP25_IP3_GPIO" , 0x1070103287200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP26_IP3_GPIO" , 0x1070103487200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP27_IP3_GPIO" , 0x1070103687200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP28_IP3_GPIO" , 0x1070103887200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP29_IP3_GPIO" , 0x1070103a87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP30_IP3_GPIO" , 0x1070103c87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP31_IP3_GPIO" , 0x1070103e87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP0_IP3_IO" , 0x1070100084200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP1_IP3_IO" , 0x1070100284200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP2_IP3_IO" , 0x1070100484200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP3_IP3_IO" , 0x1070100684200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP4_IP3_IO" , 0x1070100884200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP5_IP3_IO" , 0x1070100a84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP6_IP3_IO" , 0x1070100c84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP7_IP3_IO" , 0x1070100e84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP8_IP3_IO" , 0x1070101084200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP9_IP3_IO" , 0x1070101284200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP10_IP3_IO" , 0x1070101484200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP11_IP3_IO" , 0x1070101684200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP12_IP3_IO" , 0x1070101884200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP13_IP3_IO" , 0x1070101a84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP14_IP3_IO" , 0x1070101c84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP15_IP3_IO" , 0x1070101e84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP16_IP3_IO" , 0x1070102084200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP17_IP3_IO" , 0x1070102284200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP18_IP3_IO" , 0x1070102484200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP19_IP3_IO" , 0x1070102684200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP20_IP3_IO" , 0x1070102884200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP21_IP3_IO" , 0x1070102a84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP22_IP3_IO" , 0x1070102c84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP23_IP3_IO" , 0x1070102e84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP24_IP3_IO" , 0x1070103084200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP25_IP3_IO" , 0x1070103284200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP26_IP3_IO" , 0x1070103484200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP27_IP3_IO" , 0x1070103684200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP28_IP3_IO" , 0x1070103884200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP29_IP3_IO" , 0x1070103a84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP30_IP3_IO" , 0x1070103c84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP31_IP3_IO" , 0x1070103e84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP0_IP3_MBOX" , 0x1070100088200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP1_IP3_MBOX" , 0x1070100288200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP2_IP3_MBOX" , 0x1070100488200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP3_IP3_MBOX" , 0x1070100688200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP4_IP3_MBOX" , 0x1070100888200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP5_IP3_MBOX" , 0x1070100a88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP6_IP3_MBOX" , 0x1070100c88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP7_IP3_MBOX" , 0x1070100e88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP8_IP3_MBOX" , 0x1070101088200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP9_IP3_MBOX" , 0x1070101288200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP10_IP3_MBOX" , 0x1070101488200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP11_IP3_MBOX" , 0x1070101688200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP12_IP3_MBOX" , 0x1070101888200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP13_IP3_MBOX" , 0x1070101a88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP14_IP3_MBOX" , 0x1070101c88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP15_IP3_MBOX" , 0x1070101e88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP16_IP3_MBOX" , 0x1070102088200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP17_IP3_MBOX" , 0x1070102288200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP18_IP3_MBOX" , 0x1070102488200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP19_IP3_MBOX" , 0x1070102688200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP20_IP3_MBOX" , 0x1070102888200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP21_IP3_MBOX" , 0x1070102a88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP22_IP3_MBOX" , 0x1070102c88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP23_IP3_MBOX" , 0x1070102e88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP24_IP3_MBOX" , 0x1070103088200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP25_IP3_MBOX" , 0x1070103288200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP26_IP3_MBOX" , 0x1070103488200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP27_IP3_MBOX" , 0x1070103688200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP28_IP3_MBOX" , 0x1070103888200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP29_IP3_MBOX" , 0x1070103a88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP30_IP3_MBOX" , 0x1070103c88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP31_IP3_MBOX" , 0x1070103e88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP0_IP3_MEM" , 0x1070100085200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP1_IP3_MEM" , 0x1070100285200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP2_IP3_MEM" , 0x1070100485200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP3_IP3_MEM" , 0x1070100685200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP4_IP3_MEM" , 0x1070100885200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP5_IP3_MEM" , 0x1070100a85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP6_IP3_MEM" , 0x1070100c85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP7_IP3_MEM" , 0x1070100e85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP8_IP3_MEM" , 0x1070101085200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP9_IP3_MEM" , 0x1070101285200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP10_IP3_MEM" , 0x1070101485200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP11_IP3_MEM" , 0x1070101685200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP12_IP3_MEM" , 0x1070101885200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP13_IP3_MEM" , 0x1070101a85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP14_IP3_MEM" , 0x1070101c85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP15_IP3_MEM" , 0x1070101e85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP16_IP3_MEM" , 0x1070102085200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP17_IP3_MEM" , 0x1070102285200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP18_IP3_MEM" , 0x1070102485200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP19_IP3_MEM" , 0x1070102685200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP20_IP3_MEM" , 0x1070102885200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP21_IP3_MEM" , 0x1070102a85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP22_IP3_MEM" , 0x1070102c85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP23_IP3_MEM" , 0x1070102e85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP24_IP3_MEM" , 0x1070103085200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP25_IP3_MEM" , 0x1070103285200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP26_IP3_MEM" , 0x1070103485200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP27_IP3_MEM" , 0x1070103685200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP28_IP3_MEM" , 0x1070103885200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP29_IP3_MEM" , 0x1070103a85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP30_IP3_MEM" , 0x1070103c85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP31_IP3_MEM" , 0x1070103e85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP0_IP3_MIO" , 0x1070100083200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP1_IP3_MIO" , 0x1070100283200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP2_IP3_MIO" , 0x1070100483200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP3_IP3_MIO" , 0x1070100683200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP4_IP3_MIO" , 0x1070100883200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP5_IP3_MIO" , 0x1070100a83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP6_IP3_MIO" , 0x1070100c83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP7_IP3_MIO" , 0x1070100e83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP8_IP3_MIO" , 0x1070101083200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP9_IP3_MIO" , 0x1070101283200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP10_IP3_MIO" , 0x1070101483200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP11_IP3_MIO" , 0x1070101683200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP12_IP3_MIO" , 0x1070101883200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP13_IP3_MIO" , 0x1070101a83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP14_IP3_MIO" , 0x1070101c83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP15_IP3_MIO" , 0x1070101e83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP16_IP3_MIO" , 0x1070102083200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP17_IP3_MIO" , 0x1070102283200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP18_IP3_MIO" , 0x1070102483200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP19_IP3_MIO" , 0x1070102683200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP20_IP3_MIO" , 0x1070102883200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP21_IP3_MIO" , 0x1070102a83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP22_IP3_MIO" , 0x1070102c83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP23_IP3_MIO" , 0x1070102e83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP24_IP3_MIO" , 0x1070103083200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP25_IP3_MIO" , 0x1070103283200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP26_IP3_MIO" , 0x1070103483200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP27_IP3_MIO" , 0x1070103683200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP28_IP3_MIO" , 0x1070103883200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP29_IP3_MIO" , 0x1070103a83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP30_IP3_MIO" , 0x1070103c83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP31_IP3_MIO" , 0x1070103e83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP0_IP3_PKT" , 0x1070100086200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP1_IP3_PKT" , 0x1070100286200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP2_IP3_PKT" , 0x1070100486200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP3_IP3_PKT" , 0x1070100686200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP4_IP3_PKT" , 0x1070100886200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP5_IP3_PKT" , 0x1070100a86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP6_IP3_PKT" , 0x1070100c86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP7_IP3_PKT" , 0x1070100e86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP8_IP3_PKT" , 0x1070101086200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP9_IP3_PKT" , 0x1070101286200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP10_IP3_PKT" , 0x1070101486200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP11_IP3_PKT" , 0x1070101686200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP12_IP3_PKT" , 0x1070101886200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP13_IP3_PKT" , 0x1070101a86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP14_IP3_PKT" , 0x1070101c86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP15_IP3_PKT" , 0x1070101e86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP16_IP3_PKT" , 0x1070102086200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP17_IP3_PKT" , 0x1070102286200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP18_IP3_PKT" , 0x1070102486200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP19_IP3_PKT" , 0x1070102686200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP20_IP3_PKT" , 0x1070102886200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP21_IP3_PKT" , 0x1070102a86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP22_IP3_PKT" , 0x1070102c86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP23_IP3_PKT" , 0x1070102e86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP24_IP3_PKT" , 0x1070103086200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP25_IP3_PKT" , 0x1070103286200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP26_IP3_PKT" , 0x1070103486200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP27_IP3_PKT" , 0x1070103686200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP28_IP3_PKT" , 0x1070103886200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP29_IP3_PKT" , 0x1070103a86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP30_IP3_PKT" , 0x1070103c86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP31_IP3_PKT" , 0x1070103e86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP0_IP3_RML" , 0x1070100082200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP1_IP3_RML" , 0x1070100282200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP2_IP3_RML" , 0x1070100482200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP3_IP3_RML" , 0x1070100682200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP4_IP3_RML" , 0x1070100882200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP5_IP3_RML" , 0x1070100a82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP6_IP3_RML" , 0x1070100c82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP7_IP3_RML" , 0x1070100e82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP8_IP3_RML" , 0x1070101082200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP9_IP3_RML" , 0x1070101282200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP10_IP3_RML" , 0x1070101482200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP11_IP3_RML" , 0x1070101682200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP12_IP3_RML" , 0x1070101882200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP13_IP3_RML" , 0x1070101a82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP14_IP3_RML" , 0x1070101c82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP15_IP3_RML" , 0x1070101e82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP16_IP3_RML" , 0x1070102082200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP17_IP3_RML" , 0x1070102282200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP18_IP3_RML" , 0x1070102482200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP19_IP3_RML" , 0x1070102682200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP20_IP3_RML" , 0x1070102882200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP21_IP3_RML" , 0x1070102a82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP22_IP3_RML" , 0x1070102c82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP23_IP3_RML" , 0x1070102e82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP24_IP3_RML" , 0x1070103082200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP25_IP3_RML" , 0x1070103282200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP26_IP3_RML" , 0x1070103482200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP27_IP3_RML" , 0x1070103682200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP28_IP3_RML" , 0x1070103882200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP29_IP3_RML" , 0x1070103a82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP30_IP3_RML" , 0x1070103c82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP31_IP3_RML" , 0x1070103e82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP0_IP3_WDOG" , 0x1070100081200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP1_IP3_WDOG" , 0x1070100281200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP2_IP3_WDOG" , 0x1070100481200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP3_IP3_WDOG" , 0x1070100681200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP4_IP3_WDOG" , 0x1070100881200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP5_IP3_WDOG" , 0x1070100a81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP6_IP3_WDOG" , 0x1070100c81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP7_IP3_WDOG" , 0x1070100e81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP8_IP3_WDOG" , 0x1070101081200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP9_IP3_WDOG" , 0x1070101281200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP10_IP3_WDOG" , 0x1070101481200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP11_IP3_WDOG" , 0x1070101681200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP12_IP3_WDOG" , 0x1070101881200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP13_IP3_WDOG" , 0x1070101a81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP14_IP3_WDOG" , 0x1070101c81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP15_IP3_WDOG" , 0x1070101e81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP16_IP3_WDOG" , 0x1070102081200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP17_IP3_WDOG" , 0x1070102281200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP18_IP3_WDOG" , 0x1070102481200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP19_IP3_WDOG" , 0x1070102681200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP20_IP3_WDOG" , 0x1070102881200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP21_IP3_WDOG" , 0x1070102a81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP22_IP3_WDOG" , 0x1070102c81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP23_IP3_WDOG" , 0x1070102e81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP24_IP3_WDOG" , 0x1070103081200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP25_IP3_WDOG" , 0x1070103281200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP26_IP3_WDOG" , 0x1070103481200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP27_IP3_WDOG" , 0x1070103681200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP28_IP3_WDOG" , 0x1070103881200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP29_IP3_WDOG" , 0x1070103a81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP30_IP3_WDOG" , 0x1070103c81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP31_IP3_WDOG" , 0x1070103e81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP0_IP3_WRKQ" , 0x1070100080200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP1_IP3_WRKQ" , 0x1070100280200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP2_IP3_WRKQ" , 0x1070100480200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP3_IP3_WRKQ" , 0x1070100680200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP4_IP3_WRKQ" , 0x1070100880200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP5_IP3_WRKQ" , 0x1070100a80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP6_IP3_WRKQ" , 0x1070100c80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP7_IP3_WRKQ" , 0x1070100e80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP8_IP3_WRKQ" , 0x1070101080200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP9_IP3_WRKQ" , 0x1070101280200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP10_IP3_WRKQ" , 0x1070101480200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP11_IP3_WRKQ" , 0x1070101680200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP12_IP3_WRKQ" , 0x1070101880200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP13_IP3_WRKQ" , 0x1070101a80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP14_IP3_WRKQ" , 0x1070101c80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP15_IP3_WRKQ" , 0x1070101e80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP16_IP3_WRKQ" , 0x1070102080200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP17_IP3_WRKQ" , 0x1070102280200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP18_IP3_WRKQ" , 0x1070102480200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP19_IP3_WRKQ" , 0x1070102680200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP20_IP3_WRKQ" , 0x1070102880200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP21_IP3_WRKQ" , 0x1070102a80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP22_IP3_WRKQ" , 0x1070102c80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP23_IP3_WRKQ" , 0x1070102e80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP24_IP3_WRKQ" , 0x1070103080200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP25_IP3_WRKQ" , 0x1070103280200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP26_IP3_WRKQ" , 0x1070103480200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP27_IP3_WRKQ" , 0x1070103680200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP28_IP3_WRKQ" , 0x1070103880200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP29_IP3_WRKQ" , 0x1070103a80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP30_IP3_WRKQ" , 0x1070103c80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP31_IP3_WRKQ" , 0x1070103e80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP0_IP4_GPIO" , 0x1070100087400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP1_IP4_GPIO" , 0x1070100287400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP2_IP4_GPIO" , 0x1070100487400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP3_IP4_GPIO" , 0x1070100687400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP4_IP4_GPIO" , 0x1070100887400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP5_IP4_GPIO" , 0x1070100a87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP6_IP4_GPIO" , 0x1070100c87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP7_IP4_GPIO" , 0x1070100e87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP8_IP4_GPIO" , 0x1070101087400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP9_IP4_GPIO" , 0x1070101287400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP10_IP4_GPIO" , 0x1070101487400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP11_IP4_GPIO" , 0x1070101687400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP12_IP4_GPIO" , 0x1070101887400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP13_IP4_GPIO" , 0x1070101a87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP14_IP4_GPIO" , 0x1070101c87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP15_IP4_GPIO" , 0x1070101e87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP16_IP4_GPIO" , 0x1070102087400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP17_IP4_GPIO" , 0x1070102287400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP18_IP4_GPIO" , 0x1070102487400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP19_IP4_GPIO" , 0x1070102687400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP20_IP4_GPIO" , 0x1070102887400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP21_IP4_GPIO" , 0x1070102a87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP22_IP4_GPIO" , 0x1070102c87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP23_IP4_GPIO" , 0x1070102e87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP24_IP4_GPIO" , 0x1070103087400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP25_IP4_GPIO" , 0x1070103287400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP26_IP4_GPIO" , 0x1070103487400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP27_IP4_GPIO" , 0x1070103687400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP28_IP4_GPIO" , 0x1070103887400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP29_IP4_GPIO" , 0x1070103a87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP30_IP4_GPIO" , 0x1070103c87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP31_IP4_GPIO" , 0x1070103e87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP0_IP4_IO" , 0x1070100084400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP1_IP4_IO" , 0x1070100284400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP2_IP4_IO" , 0x1070100484400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP3_IP4_IO" , 0x1070100684400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP4_IP4_IO" , 0x1070100884400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP5_IP4_IO" , 0x1070100a84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP6_IP4_IO" , 0x1070100c84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP7_IP4_IO" , 0x1070100e84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP8_IP4_IO" , 0x1070101084400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP9_IP4_IO" , 0x1070101284400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP10_IP4_IO" , 0x1070101484400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP11_IP4_IO" , 0x1070101684400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP12_IP4_IO" , 0x1070101884400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP13_IP4_IO" , 0x1070101a84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP14_IP4_IO" , 0x1070101c84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP15_IP4_IO" , 0x1070101e84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP16_IP4_IO" , 0x1070102084400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP17_IP4_IO" , 0x1070102284400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP18_IP4_IO" , 0x1070102484400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP19_IP4_IO" , 0x1070102684400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP20_IP4_IO" , 0x1070102884400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP21_IP4_IO" , 0x1070102a84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP22_IP4_IO" , 0x1070102c84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP23_IP4_IO" , 0x1070102e84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP24_IP4_IO" , 0x1070103084400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP25_IP4_IO" , 0x1070103284400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP26_IP4_IO" , 0x1070103484400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP27_IP4_IO" , 0x1070103684400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP28_IP4_IO" , 0x1070103884400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP29_IP4_IO" , 0x1070103a84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP30_IP4_IO" , 0x1070103c84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP31_IP4_IO" , 0x1070103e84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP0_IP4_MBOX" , 0x1070100088400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP1_IP4_MBOX" , 0x1070100288400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP2_IP4_MBOX" , 0x1070100488400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP3_IP4_MBOX" , 0x1070100688400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP4_IP4_MBOX" , 0x1070100888400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP5_IP4_MBOX" , 0x1070100a88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP6_IP4_MBOX" , 0x1070100c88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP7_IP4_MBOX" , 0x1070100e88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP8_IP4_MBOX" , 0x1070101088400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP9_IP4_MBOX" , 0x1070101288400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP10_IP4_MBOX" , 0x1070101488400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP11_IP4_MBOX" , 0x1070101688400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP12_IP4_MBOX" , 0x1070101888400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP13_IP4_MBOX" , 0x1070101a88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP14_IP4_MBOX" , 0x1070101c88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP15_IP4_MBOX" , 0x1070101e88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP16_IP4_MBOX" , 0x1070102088400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP17_IP4_MBOX" , 0x1070102288400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP18_IP4_MBOX" , 0x1070102488400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP19_IP4_MBOX" , 0x1070102688400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP20_IP4_MBOX" , 0x1070102888400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP21_IP4_MBOX" , 0x1070102a88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP22_IP4_MBOX" , 0x1070102c88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP23_IP4_MBOX" , 0x1070102e88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP24_IP4_MBOX" , 0x1070103088400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP25_IP4_MBOX" , 0x1070103288400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP26_IP4_MBOX" , 0x1070103488400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP27_IP4_MBOX" , 0x1070103688400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP28_IP4_MBOX" , 0x1070103888400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP29_IP4_MBOX" , 0x1070103a88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP30_IP4_MBOX" , 0x1070103c88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP31_IP4_MBOX" , 0x1070103e88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP0_IP4_MEM" , 0x1070100085400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP1_IP4_MEM" , 0x1070100285400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP2_IP4_MEM" , 0x1070100485400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP3_IP4_MEM" , 0x1070100685400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP4_IP4_MEM" , 0x1070100885400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP5_IP4_MEM" , 0x1070100a85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP6_IP4_MEM" , 0x1070100c85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP7_IP4_MEM" , 0x1070100e85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP8_IP4_MEM" , 0x1070101085400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP9_IP4_MEM" , 0x1070101285400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP10_IP4_MEM" , 0x1070101485400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP11_IP4_MEM" , 0x1070101685400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP12_IP4_MEM" , 0x1070101885400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP13_IP4_MEM" , 0x1070101a85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP14_IP4_MEM" , 0x1070101c85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP15_IP4_MEM" , 0x1070101e85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP16_IP4_MEM" , 0x1070102085400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP17_IP4_MEM" , 0x1070102285400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP18_IP4_MEM" , 0x1070102485400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP19_IP4_MEM" , 0x1070102685400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP20_IP4_MEM" , 0x1070102885400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP21_IP4_MEM" , 0x1070102a85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP22_IP4_MEM" , 0x1070102c85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP23_IP4_MEM" , 0x1070102e85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP24_IP4_MEM" , 0x1070103085400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP25_IP4_MEM" , 0x1070103285400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP26_IP4_MEM" , 0x1070103485400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP27_IP4_MEM" , 0x1070103685400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP28_IP4_MEM" , 0x1070103885400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP29_IP4_MEM" , 0x1070103a85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP30_IP4_MEM" , 0x1070103c85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP31_IP4_MEM" , 0x1070103e85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP0_IP4_MIO" , 0x1070100083400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP1_IP4_MIO" , 0x1070100283400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP2_IP4_MIO" , 0x1070100483400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP3_IP4_MIO" , 0x1070100683400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP4_IP4_MIO" , 0x1070100883400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP5_IP4_MIO" , 0x1070100a83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP6_IP4_MIO" , 0x1070100c83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP7_IP4_MIO" , 0x1070100e83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP8_IP4_MIO" , 0x1070101083400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP9_IP4_MIO" , 0x1070101283400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP10_IP4_MIO" , 0x1070101483400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP11_IP4_MIO" , 0x1070101683400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP12_IP4_MIO" , 0x1070101883400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP13_IP4_MIO" , 0x1070101a83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP14_IP4_MIO" , 0x1070101c83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP15_IP4_MIO" , 0x1070101e83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP16_IP4_MIO" , 0x1070102083400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP17_IP4_MIO" , 0x1070102283400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP18_IP4_MIO" , 0x1070102483400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP19_IP4_MIO" , 0x1070102683400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP20_IP4_MIO" , 0x1070102883400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP21_IP4_MIO" , 0x1070102a83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP22_IP4_MIO" , 0x1070102c83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP23_IP4_MIO" , 0x1070102e83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP24_IP4_MIO" , 0x1070103083400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP25_IP4_MIO" , 0x1070103283400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP26_IP4_MIO" , 0x1070103483400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP27_IP4_MIO" , 0x1070103683400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP28_IP4_MIO" , 0x1070103883400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP29_IP4_MIO" , 0x1070103a83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP30_IP4_MIO" , 0x1070103c83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP31_IP4_MIO" , 0x1070103e83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP0_IP4_PKT" , 0x1070100086400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP1_IP4_PKT" , 0x1070100286400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP2_IP4_PKT" , 0x1070100486400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP3_IP4_PKT" , 0x1070100686400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP4_IP4_PKT" , 0x1070100886400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP5_IP4_PKT" , 0x1070100a86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP6_IP4_PKT" , 0x1070100c86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP7_IP4_PKT" , 0x1070100e86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP8_IP4_PKT" , 0x1070101086400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP9_IP4_PKT" , 0x1070101286400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP10_IP4_PKT" , 0x1070101486400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP11_IP4_PKT" , 0x1070101686400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP12_IP4_PKT" , 0x1070101886400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP13_IP4_PKT" , 0x1070101a86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP14_IP4_PKT" , 0x1070101c86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP15_IP4_PKT" , 0x1070101e86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP16_IP4_PKT" , 0x1070102086400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP17_IP4_PKT" , 0x1070102286400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP18_IP4_PKT" , 0x1070102486400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP19_IP4_PKT" , 0x1070102686400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP20_IP4_PKT" , 0x1070102886400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP21_IP4_PKT" , 0x1070102a86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP22_IP4_PKT" , 0x1070102c86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP23_IP4_PKT" , 0x1070102e86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP24_IP4_PKT" , 0x1070103086400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP25_IP4_PKT" , 0x1070103286400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP26_IP4_PKT" , 0x1070103486400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP27_IP4_PKT" , 0x1070103686400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP28_IP4_PKT" , 0x1070103886400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP29_IP4_PKT" , 0x1070103a86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP30_IP4_PKT" , 0x1070103c86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP31_IP4_PKT" , 0x1070103e86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP0_IP4_RML" , 0x1070100082400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP1_IP4_RML" , 0x1070100282400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP2_IP4_RML" , 0x1070100482400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP3_IP4_RML" , 0x1070100682400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP4_IP4_RML" , 0x1070100882400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP5_IP4_RML" , 0x1070100a82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP6_IP4_RML" , 0x1070100c82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP7_IP4_RML" , 0x1070100e82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP8_IP4_RML" , 0x1070101082400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP9_IP4_RML" , 0x1070101282400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP10_IP4_RML" , 0x1070101482400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP11_IP4_RML" , 0x1070101682400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP12_IP4_RML" , 0x1070101882400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP13_IP4_RML" , 0x1070101a82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP14_IP4_RML" , 0x1070101c82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP15_IP4_RML" , 0x1070101e82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP16_IP4_RML" , 0x1070102082400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP17_IP4_RML" , 0x1070102282400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP18_IP4_RML" , 0x1070102482400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP19_IP4_RML" , 0x1070102682400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP20_IP4_RML" , 0x1070102882400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP21_IP4_RML" , 0x1070102a82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP22_IP4_RML" , 0x1070102c82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP23_IP4_RML" , 0x1070102e82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP24_IP4_RML" , 0x1070103082400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP25_IP4_RML" , 0x1070103282400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP26_IP4_RML" , 0x1070103482400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP27_IP4_RML" , 0x1070103682400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP28_IP4_RML" , 0x1070103882400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP29_IP4_RML" , 0x1070103a82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP30_IP4_RML" , 0x1070103c82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP31_IP4_RML" , 0x1070103e82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP0_IP4_WDOG" , 0x1070100081400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP1_IP4_WDOG" , 0x1070100281400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP2_IP4_WDOG" , 0x1070100481400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP3_IP4_WDOG" , 0x1070100681400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP4_IP4_WDOG" , 0x1070100881400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP5_IP4_WDOG" , 0x1070100a81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP6_IP4_WDOG" , 0x1070100c81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP7_IP4_WDOG" , 0x1070100e81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP8_IP4_WDOG" , 0x1070101081400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP9_IP4_WDOG" , 0x1070101281400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP10_IP4_WDOG" , 0x1070101481400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP11_IP4_WDOG" , 0x1070101681400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP12_IP4_WDOG" , 0x1070101881400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP13_IP4_WDOG" , 0x1070101a81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP14_IP4_WDOG" , 0x1070101c81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP15_IP4_WDOG" , 0x1070101e81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP16_IP4_WDOG" , 0x1070102081400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP17_IP4_WDOG" , 0x1070102281400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP18_IP4_WDOG" , 0x1070102481400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP19_IP4_WDOG" , 0x1070102681400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP20_IP4_WDOG" , 0x1070102881400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP21_IP4_WDOG" , 0x1070102a81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP22_IP4_WDOG" , 0x1070102c81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP23_IP4_WDOG" , 0x1070102e81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP24_IP4_WDOG" , 0x1070103081400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP25_IP4_WDOG" , 0x1070103281400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP26_IP4_WDOG" , 0x1070103481400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP27_IP4_WDOG" , 0x1070103681400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP28_IP4_WDOG" , 0x1070103881400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP29_IP4_WDOG" , 0x1070103a81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP30_IP4_WDOG" , 0x1070103c81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP31_IP4_WDOG" , 0x1070103e81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP0_IP4_WRKQ" , 0x1070100080400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP1_IP4_WRKQ" , 0x1070100280400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP2_IP4_WRKQ" , 0x1070100480400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP3_IP4_WRKQ" , 0x1070100680400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP4_IP4_WRKQ" , 0x1070100880400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP5_IP4_WRKQ" , 0x1070100a80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP6_IP4_WRKQ" , 0x1070100c80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP7_IP4_WRKQ" , 0x1070100e80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP8_IP4_WRKQ" , 0x1070101080400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP9_IP4_WRKQ" , 0x1070101280400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP10_IP4_WRKQ" , 0x1070101480400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP11_IP4_WRKQ" , 0x1070101680400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP12_IP4_WRKQ" , 0x1070101880400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP13_IP4_WRKQ" , 0x1070101a80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP14_IP4_WRKQ" , 0x1070101c80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP15_IP4_WRKQ" , 0x1070101e80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP16_IP4_WRKQ" , 0x1070102080400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP17_IP4_WRKQ" , 0x1070102280400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP18_IP4_WRKQ" , 0x1070102480400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP19_IP4_WRKQ" , 0x1070102680400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP20_IP4_WRKQ" , 0x1070102880400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP21_IP4_WRKQ" , 0x1070102a80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP22_IP4_WRKQ" , 0x1070102c80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP23_IP4_WRKQ" , 0x1070102e80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP24_IP4_WRKQ" , 0x1070103080400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP25_IP4_WRKQ" , 0x1070103280400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP26_IP4_WRKQ" , 0x1070103480400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP27_IP4_WRKQ" , 0x1070103680400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP28_IP4_WRKQ" , 0x1070103880400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP29_IP4_WRKQ" , 0x1070103a80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP30_IP4_WRKQ" , 0x1070103c80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP31_IP4_WRKQ" , 0x1070103e80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SUM_IO0_INT" , 0x1070100000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"CIU2_SUM_IO1_INT" , 0x1070100000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"CIU2_SUM_PP0_IP2" , 0x1070100000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP1_IP2" , 0x1070100000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP2_IP2" , 0x1070100000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP3_IP2" , 0x1070100000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP4_IP2" , 0x1070100000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP5_IP2" , 0x1070100000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP6_IP2" , 0x1070100000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP7_IP2" , 0x1070100000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP8_IP2" , 0x1070100000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP9_IP2" , 0x1070100000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP10_IP2" , 0x1070100000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP11_IP2" , 0x1070100000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP12_IP2" , 0x1070100000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP13_IP2" , 0x1070100000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP14_IP2" , 0x1070100000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP15_IP2" , 0x1070100000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP16_IP2" , 0x1070100000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP17_IP2" , 0x1070100000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP18_IP2" , 0x1070100000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP19_IP2" , 0x1070100000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP20_IP2" , 0x10701000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP21_IP2" , 0x10701000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP22_IP2" , 0x10701000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP23_IP2" , 0x10701000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP24_IP2" , 0x10701000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP25_IP2" , 0x10701000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP26_IP2" , 0x10701000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP27_IP2" , 0x10701000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP28_IP2" , 0x10701000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP29_IP2" , 0x10701000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP30_IP2" , 0x10701000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP31_IP2" , 0x10701000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP0_IP3" , 0x1070100000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP1_IP3" , 0x1070100000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP2_IP3" , 0x1070100000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP3_IP3" , 0x1070100000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP4_IP3" , 0x1070100000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP5_IP3" , 0x1070100000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP6_IP3" , 0x1070100000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP7_IP3" , 0x1070100000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP8_IP3" , 0x1070100000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP9_IP3" , 0x1070100000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP10_IP3" , 0x1070100000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP11_IP3" , 0x1070100000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP12_IP3" , 0x1070100000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP13_IP3" , 0x1070100000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP14_IP3" , 0x1070100000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP15_IP3" , 0x1070100000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP16_IP3" , 0x1070100000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP17_IP3" , 0x1070100000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP18_IP3" , 0x1070100000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP19_IP3" , 0x1070100000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP20_IP3" , 0x10701000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP21_IP3" , 0x10701000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP22_IP3" , 0x10701000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP23_IP3" , 0x10701000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP24_IP3" , 0x10701000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP25_IP3" , 0x10701000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP26_IP3" , 0x10701000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP27_IP3" , 0x10701000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP28_IP3" , 0x10701000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP29_IP3" , 0x10701000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP30_IP3" , 0x10701000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP31_IP3" , 0x10701000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP0_IP4" , 0x1070100000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP1_IP4" , 0x1070100000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP2_IP4" , 0x1070100000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP3_IP4" , 0x1070100000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP4_IP4" , 0x1070100000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP5_IP4" , 0x1070100000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP6_IP4" , 0x1070100000430ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP7_IP4" , 0x1070100000438ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP8_IP4" , 0x1070100000440ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP9_IP4" , 0x1070100000448ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP10_IP4" , 0x1070100000450ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP11_IP4" , 0x1070100000458ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP12_IP4" , 0x1070100000460ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP13_IP4" , 0x1070100000468ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP14_IP4" , 0x1070100000470ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP15_IP4" , 0x1070100000478ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP16_IP4" , 0x1070100000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP17_IP4" , 0x1070100000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP18_IP4" , 0x1070100000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP19_IP4" , 0x1070100000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP20_IP4" , 0x10701000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP21_IP4" , 0x10701000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP22_IP4" , 0x10701000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP23_IP4" , 0x10701000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP24_IP4" , 0x10701000004c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP25_IP4" , 0x10701000004c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP26_IP4" , 0x10701000004d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP27_IP4" , 0x10701000004d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP28_IP4" , 0x10701000004e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP29_IP4" , 0x10701000004e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP30_IP4" , 0x10701000004f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP31_IP4" , 0x10701000004f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 265},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 266},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 267},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"CIU_INT_DBG_SEL" , 0x10700000007d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 269},
- {"CIU_MBOX_CLR0" , 0x1070100100600ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR1" , 0x1070100100608ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR2" , 0x1070100100610ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR3" , 0x1070100100618ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR4" , 0x1070100100620ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR5" , 0x1070100100628ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR6" , 0x1070100100630ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR7" , 0x1070100100638ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR8" , 0x1070100100640ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR9" , 0x1070100100648ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR10" , 0x1070100100650ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR11" , 0x1070100100658ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR12" , 0x1070100100660ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR13" , 0x1070100100668ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR14" , 0x1070100100670ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR15" , 0x1070100100678ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR16" , 0x1070100100680ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR17" , 0x1070100100688ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR18" , 0x1070100100690ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR19" , 0x1070100100698ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR20" , 0x10701001006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR21" , 0x10701001006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR22" , 0x10701001006b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR23" , 0x10701001006b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR24" , 0x10701001006c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR25" , 0x10701001006c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR26" , 0x10701001006d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR27" , 0x10701001006d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR28" , 0x10701001006e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR29" , 0x10701001006e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR30" , 0x10701001006f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR31" , 0x10701001006f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_SET0" , 0x1070100100400ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET1" , 0x1070100100408ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET2" , 0x1070100100410ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET3" , 0x1070100100418ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET4" , 0x1070100100420ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET5" , 0x1070100100428ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET6" , 0x1070100100430ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET7" , 0x1070100100438ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET8" , 0x1070100100440ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET9" , 0x1070100100448ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET10" , 0x1070100100450ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET11" , 0x1070100100458ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET12" , 0x1070100100460ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET13" , 0x1070100100468ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET14" , 0x1070100100470ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET15" , 0x1070100100478ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET16" , 0x1070100100480ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET17" , 0x1070100100488ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET18" , 0x1070100100490ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET19" , 0x1070100100498ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET20" , 0x10701001004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET21" , 0x10701001004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET22" , 0x10701001004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET23" , 0x10701001004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET24" , 0x10701001004c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET25" , 0x10701001004c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET26" , 0x10701001004d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET27" , 0x10701001004d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET28" , 0x10701001004e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET29" , 0x10701001004e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET30" , 0x10701001004f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET31" , 0x10701001004f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 272},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 273},
- {"CIU_PP_BIST_STAT" , 0x10700000007e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 274},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 275},
- {"CIU_PP_POKE0" , 0x1070100100200ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE1" , 0x1070100100208ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE2" , 0x1070100100210ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE3" , 0x1070100100218ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE4" , 0x1070100100220ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE5" , 0x1070100100228ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE6" , 0x1070100100230ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE7" , 0x1070100100238ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE8" , 0x1070100100240ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE9" , 0x1070100100248ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE10" , 0x1070100100250ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE11" , 0x1070100100258ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE12" , 0x1070100100260ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE13" , 0x1070100100268ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE14" , 0x1070100100270ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE15" , 0x1070100100278ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE16" , 0x1070100100280ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE17" , 0x1070100100288ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE18" , 0x1070100100290ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE19" , 0x1070100100298ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE20" , 0x10701001002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE21" , 0x10701001002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE22" , 0x10701001002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE23" , 0x10701001002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE24" , 0x10701001002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE25" , 0x10701001002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE26" , 0x10701001002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE27" , 0x10701001002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE28" , 0x10701001002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE29" , 0x10701001002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE30" , 0x10701001002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE31" , 0x10701001002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"CIU_QLM0" , 0x1070000000780ull, CVMX_CSR_DB_TYPE_NCB, 64, 278},
- {"CIU_QLM1" , 0x1070000000788ull, CVMX_CSR_DB_TYPE_NCB, 64, 279},
- {"CIU_QLM2" , 0x1070000000790ull, CVMX_CSR_DB_TYPE_NCB, 64, 280},
- {"CIU_QLM3" , 0x1070000000798ull, CVMX_CSR_DB_TYPE_NCB, 64, 281},
- {"CIU_QLM4" , 0x10700000007a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 282},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 283},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 284},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 285},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 287},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 288},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"CIU_WDOG0" , 0x1070100100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG1" , 0x1070100100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG2" , 0x1070100100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG3" , 0x1070100100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG4" , 0x1070100100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG5" , 0x1070100100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG6" , 0x1070100100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG7" , 0x1070100100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG8" , 0x1070100100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG9" , 0x1070100100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG10" , 0x1070100100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG11" , 0x1070100100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG12" , 0x1070100100060ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG13" , 0x1070100100068ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG14" , 0x1070100100070ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG15" , 0x1070100100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG16" , 0x1070100100080ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG17" , 0x1070100100088ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG18" , 0x1070100100090ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG19" , 0x1070100100098ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG20" , 0x10701001000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG21" , 0x10701001000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG22" , 0x10701001000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG23" , 0x10701001000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG24" , 0x10701001000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG25" , 0x10701001000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG26" , 0x10701001000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG27" , 0x10701001000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG28" , 0x10701001000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG29" , 0x10701001000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG30" , 0x10701001000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG31" , 0x10701001000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"DFA_BIST0" , 0x11800370007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"DFA_BIST1" , 0x11800370007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"DFA_CONFIG" , 0x1180037000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"DFA_CONTROL" , 0x1180037000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"DFA_DEBUG0" , 0x1180037000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"DFA_DEBUG1" , 0x1180037000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"DFA_DEBUG2" , 0x1180037000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"DFA_DEBUG3" , 0x1180037000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
- {"DFA_DTCFADR" , 0x1180037000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"DFA_ERROR" , 0x1180037000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"DFA_INTMSK" , 0x1180037000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"DFA_MEMHIDAT" , 0x1370700000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 305},
- {"DFA_PFC0_CNT" , 0x1180037000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"DFA_PFC0_CTL" , 0x1180037000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"DFA_PFC1_CNT" , 0x11800370000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"DFA_PFC1_CTL" , 0x1180037000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"DFA_PFC2_CNT" , 0x11800370000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"DFA_PFC2_CTL" , 0x11800370000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"DFA_PFC3_CNT" , 0x11800370000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"DFA_PFC3_CTL" , 0x11800370000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"DFA_PFC_GCTL" , 0x1180037000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"DPI_BIST_STATUS" , 0x1df0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 315},
- {"DPI_CTL" , 0x1df0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
- {"DPI_DMA0_COUNTS" , 0x1df0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA1_COUNTS" , 0x1df0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA2_COUNTS" , 0x1df0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA3_COUNTS" , 0x1df0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA4_COUNTS" , 0x1df0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA5_COUNTS" , 0x1df0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA6_COUNTS" , 0x1df0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA7_COUNTS" , 0x1df0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA0_DBELL" , 0x1df0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA1_DBELL" , 0x1df0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA2_DBELL" , 0x1df0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA3_DBELL" , 0x1df0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA4_DBELL" , 0x1df0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA5_DBELL" , 0x1df0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA6_DBELL" , 0x1df0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA7_DBELL" , 0x1df0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA0_ERR_RSP_STATUS" , 0x1df0000000a80ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA1_ERR_RSP_STATUS" , 0x1df0000000a88ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA2_ERR_RSP_STATUS" , 0x1df0000000a90ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA3_ERR_RSP_STATUS" , 0x1df0000000a98ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA4_ERR_RSP_STATUS" , 0x1df0000000aa0ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA5_ERR_RSP_STATUS" , 0x1df0000000aa8ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA6_ERR_RSP_STATUS" , 0x1df0000000ab0ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA7_ERR_RSP_STATUS" , 0x1df0000000ab8ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA0_IBUFF_SADDR" , 0x1df0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA1_IBUFF_SADDR" , 0x1df0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA2_IBUFF_SADDR" , 0x1df0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA3_IBUFF_SADDR" , 0x1df0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA4_IBUFF_SADDR" , 0x1df00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA5_IBUFF_SADDR" , 0x1df00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA6_IBUFF_SADDR" , 0x1df00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA7_IBUFF_SADDR" , 0x1df00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA0_IFLIGHT" , 0x1df0000000a00ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA1_IFLIGHT" , 0x1df0000000a08ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA2_IFLIGHT" , 0x1df0000000a10ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA3_IFLIGHT" , 0x1df0000000a18ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA4_IFLIGHT" , 0x1df0000000a20ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA5_IFLIGHT" , 0x1df0000000a28ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA6_IFLIGHT" , 0x1df0000000a30ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA7_IFLIGHT" , 0x1df0000000a38ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA0_NADDR" , 0x1df0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA1_NADDR" , 0x1df0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA2_NADDR" , 0x1df0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA3_NADDR" , 0x1df0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA4_NADDR" , 0x1df00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA5_NADDR" , 0x1df00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA6_NADDR" , 0x1df00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA7_NADDR" , 0x1df00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA0_REQBNK0" , 0x1df0000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA1_REQBNK0" , 0x1df0000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA2_REQBNK0" , 0x1df0000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA3_REQBNK0" , 0x1df0000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA4_REQBNK0" , 0x1df0000000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA5_REQBNK0" , 0x1df0000000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA6_REQBNK0" , 0x1df0000000430ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA7_REQBNK0" , 0x1df0000000438ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA0_REQBNK1" , 0x1df0000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA1_REQBNK1" , 0x1df0000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA2_REQBNK1" , 0x1df0000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA3_REQBNK1" , 0x1df0000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA4_REQBNK1" , 0x1df00000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA5_REQBNK1" , 0x1df00000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA6_REQBNK1" , 0x1df00000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA7_REQBNK1" , 0x1df00000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA_CONTROL" , 0x1df0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 325},
- {"DPI_DMA_ENG0_EN" , 0x1df0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_ENG1_EN" , 0x1df0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_ENG2_EN" , 0x1df0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_ENG3_EN" , 0x1df0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_ENG4_EN" , 0x1df00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_ENG5_EN" , 0x1df00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_ENG0_BUF" , 0x1df0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_ENG1_BUF" , 0x1df0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_ENG2_BUF" , 0x1df0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_ENG3_BUF" , 0x1df0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_ENG4_BUF" , 0x1df00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_ENG5_BUF" , 0x1df00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_INFO_REG" , 0x1df0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"DPI_INT_EN" , 0x1df0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"DPI_INT_REG" , 0x1df0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
- {"DPI_PINT_INFO" , 0x1df0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
- {"DPI_PKT_ERR_RSP" , 0x1df0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"DPI_REQ_ERR_RSP" , 0x1df0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"DPI_REQ_ERR_RSP_EN" , 0x1df0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"DPI_REQ_ERR_RST" , 0x1df0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"DPI_REQ_ERR_RST_EN" , 0x1df0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"DPI_REQ_ERR_SKIP_COMP" , 0x1df0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"DPI_REQ_GBL_EN" , 0x1df0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"DPI_SLI_PRT0_CFG" , 0x1df0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"DPI_SLI_PRT1_CFG" , 0x1df0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"DPI_SLI_PRT0_ERR" , 0x1df0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"DPI_SLI_PRT1_ERR" , 0x1df0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"DPI_SLI_PRT0_ERR_INFO" , 0x1df0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"DPI_SLI_PRT1_ERR_INFO" , 0x1df0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"FPA_ADDR_RANGE_ERROR" , 0x1180028000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"FPA_FPF8_MARKS" , 0x1180028000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"FPA_FPF8_SIZE" , 0x1180028000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"FPA_PACKET_THRESHOLD" , 0x1180028000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
- {"FPA_POOL0_END_ADDR" , 0x1180028000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"FPA_POOL1_END_ADDR" , 0x1180028000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"FPA_POOL2_END_ADDR" , 0x1180028000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"FPA_POOL3_END_ADDR" , 0x1180028000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"FPA_POOL4_END_ADDR" , 0x1180028000378ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"FPA_POOL5_END_ADDR" , 0x1180028000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"FPA_POOL6_END_ADDR" , 0x1180028000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"FPA_POOL7_END_ADDR" , 0x1180028000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"FPA_POOL8_END_ADDR" , 0x1180028000398ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"FPA_POOL0_START_ADDR" , 0x1180028000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"FPA_POOL1_START_ADDR" , 0x1180028000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"FPA_POOL2_START_ADDR" , 0x1180028000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"FPA_POOL3_START_ADDR" , 0x1180028000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"FPA_POOL4_START_ADDR" , 0x1180028000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"FPA_POOL5_START_ADDR" , 0x1180028000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"FPA_POOL6_START_ADDR" , 0x1180028000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"FPA_POOL7_START_ADDR" , 0x1180028000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"FPA_POOL8_START_ADDR" , 0x1180028000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"FPA_POOL0_THRESHOLD" , 0x1180028000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL1_THRESHOLD" , 0x1180028000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL2_THRESHOLD" , 0x1180028000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL3_THRESHOLD" , 0x1180028000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL4_THRESHOLD" , 0x1180028000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL5_THRESHOLD" , 0x1180028000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL6_THRESHOLD" , 0x1180028000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL7_THRESHOLD" , 0x1180028000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL8_THRESHOLD" , 0x1180028000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_QUE8_AVAILABLE" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_QUE8_PAGE_INDEX" , 0x1180028000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"FPA_WQE_THRESHOLD" , 0x1180028000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"GMX1_BAD_REG" , 0x1180009000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"GMX2_BAD_REG" , 0x118000a000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"GMX3_BAD_REG" , 0x118000b000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"GMX4_BAD_REG" , 0x118000c000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"GMX1_BIST" , 0x1180009000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"GMX2_BIST" , 0x118000a000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"GMX3_BIST" , 0x118000b000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"GMX4_BIST" , 0x118000c000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"GMX0_BPID_MAP000" , 0x1180008000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP001" , 0x1180008000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP002" , 0x1180008000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP003" , 0x1180008000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP004" , 0x11800080006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP005" , 0x11800080006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP006" , 0x11800080006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP007" , 0x11800080006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP008" , 0x11800080006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP009" , 0x11800080006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP010" , 0x11800080006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP011" , 0x11800080006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP012" , 0x11800080006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP013" , 0x11800080006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP014" , 0x11800080006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MAP015" , 0x11800080006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP000" , 0x1180009000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP001" , 0x1180009000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP002" , 0x1180009000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP003" , 0x1180009000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP004" , 0x11800090006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP005" , 0x11800090006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP006" , 0x11800090006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP007" , 0x11800090006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP008" , 0x11800090006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP009" , 0x11800090006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP010" , 0x11800090006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP011" , 0x11800090006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP012" , 0x11800090006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP013" , 0x11800090006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP014" , 0x11800090006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BPID_MAP015" , 0x11800090006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP000" , 0x118000a000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP001" , 0x118000a000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP002" , 0x118000a000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP003" , 0x118000a000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP004" , 0x118000a0006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP005" , 0x118000a0006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP006" , 0x118000a0006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP007" , 0x118000a0006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP008" , 0x118000a0006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP009" , 0x118000a0006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP010" , 0x118000a0006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP011" , 0x118000a0006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP012" , 0x118000a0006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP013" , 0x118000a0006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP014" , 0x118000a0006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BPID_MAP015" , 0x118000a0006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP000" , 0x118000b000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP001" , 0x118000b000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP002" , 0x118000b000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP003" , 0x118000b000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP004" , 0x118000b0006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP005" , 0x118000b0006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP006" , 0x118000b0006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP007" , 0x118000b0006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP008" , 0x118000b0006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP009" , 0x118000b0006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP010" , 0x118000b0006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP011" , 0x118000b0006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP012" , 0x118000b0006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP013" , 0x118000b0006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP014" , 0x118000b0006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BPID_MAP015" , 0x118000b0006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP000" , 0x118000c000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP001" , 0x118000c000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP002" , 0x118000c000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP003" , 0x118000c000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP004" , 0x118000c0006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP005" , 0x118000c0006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP006" , 0x118000c0006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP007" , 0x118000c0006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP008" , 0x118000c0006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP009" , 0x118000c0006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP010" , 0x118000c0006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP011" , 0x118000c0006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP012" , 0x118000c0006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP013" , 0x118000c0006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP014" , 0x118000c0006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BPID_MAP015" , 0x118000c0006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BPID_MSK" , 0x1180008000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX1_BPID_MSK" , 0x1180009000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX2_BPID_MSK" , 0x118000a000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX3_BPID_MSK" , 0x118000b000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX4_BPID_MSK" , 0x118000c000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_CLK_EN" , 0x11800090007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_CLK_EN" , 0x118000a0007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_CLK_EN" , 0x118000b0007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_CLK_EN" , 0x118000c0007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_EBP_DIS" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX1_EBP_DIS" , 0x1180009000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX2_EBP_DIS" , 0x118000a000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX3_EBP_DIS" , 0x118000b000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX4_EBP_DIS" , 0x118000c000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX0_EBP_MSK" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX1_EBP_MSK" , 0x1180009000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX2_EBP_MSK" , 0x118000a000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX3_EBP_MSK" , 0x118000b000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX4_EBP_MSK" , 0x118000c000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX1_HG2_CONTROL" , 0x1180009000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX2_HG2_CONTROL" , 0x118000a000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX3_HG2_CONTROL" , 0x118000b000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX4_HG2_CONTROL" , 0x118000c000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX1_INF_MODE" , 0x11800090007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX2_INF_MODE" , 0x118000a0007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX3_INF_MODE" , 0x118000b0007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX4_INF_MODE" , 0x118000c0007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX1_NXA_ADR" , 0x1180009000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX2_NXA_ADR" , 0x118000a000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX3_NXA_ADR" , 0x118000b000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX4_NXA_ADR" , 0x118000c000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX0_PIPE_STATUS" , 0x1180008000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX1_PIPE_STATUS" , 0x1180009000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX2_PIPE_STATUS" , 0x118000a000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX3_PIPE_STATUS" , 0x118000b000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX4_PIPE_STATUS" , 0x118000c000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX1_PRT000_CBFC_CTL" , 0x1180009000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX2_PRT000_CBFC_CTL" , 0x118000a000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX3_PRT000_CBFC_CTL" , 0x118000b000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX4_PRT000_CBFC_CTL" , 0x118000c000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX1_PRT000_CFG" , 0x1180009000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX1_PRT001_CFG" , 0x1180009000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX1_PRT002_CFG" , 0x1180009001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX1_PRT003_CFG" , 0x1180009001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX2_PRT000_CFG" , 0x118000a000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX2_PRT001_CFG" , 0x118000a000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX2_PRT002_CFG" , 0x118000a001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX2_PRT003_CFG" , 0x118000a001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX3_PRT000_CFG" , 0x118000b000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX3_PRT001_CFG" , 0x118000b000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX3_PRT002_CFG" , 0x118000b001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX3_PRT003_CFG" , 0x118000b001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX4_PRT000_CFG" , 0x118000c000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX4_PRT001_CFG" , 0x118000c000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX4_PRT002_CFG" , 0x118000c001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX4_PRT003_CFG" , 0x118000c001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX1_RX000_ADR_CAM0" , 0x1180009000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX1_RX001_ADR_CAM0" , 0x1180009000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX1_RX002_ADR_CAM0" , 0x1180009001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX1_RX003_ADR_CAM0" , 0x1180009001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX2_RX000_ADR_CAM0" , 0x118000a000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX2_RX001_ADR_CAM0" , 0x118000a000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX2_RX002_ADR_CAM0" , 0x118000a001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX2_RX003_ADR_CAM0" , 0x118000a001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX3_RX000_ADR_CAM0" , 0x118000b000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX3_RX001_ADR_CAM0" , 0x118000b000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX3_RX002_ADR_CAM0" , 0x118000b001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX3_RX003_ADR_CAM0" , 0x118000b001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX4_RX000_ADR_CAM0" , 0x118000c000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX4_RX001_ADR_CAM0" , 0x118000c000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX4_RX002_ADR_CAM0" , 0x118000c001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX4_RX003_ADR_CAM0" , 0x118000c001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX1_RX000_ADR_CAM1" , 0x1180009000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX1_RX001_ADR_CAM1" , 0x1180009000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX1_RX002_ADR_CAM1" , 0x1180009001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX1_RX003_ADR_CAM1" , 0x1180009001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX2_RX000_ADR_CAM1" , 0x118000a000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX2_RX001_ADR_CAM1" , 0x118000a000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX2_RX002_ADR_CAM1" , 0x118000a001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX2_RX003_ADR_CAM1" , 0x118000a001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX3_RX000_ADR_CAM1" , 0x118000b000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX3_RX001_ADR_CAM1" , 0x118000b000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX3_RX002_ADR_CAM1" , 0x118000b001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX3_RX003_ADR_CAM1" , 0x118000b001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX4_RX000_ADR_CAM1" , 0x118000c000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX4_RX001_ADR_CAM1" , 0x118000c000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX4_RX002_ADR_CAM1" , 0x118000c001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX4_RX003_ADR_CAM1" , 0x118000c001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX1_RX000_ADR_CAM2" , 0x1180009000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX1_RX001_ADR_CAM2" , 0x1180009000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX1_RX002_ADR_CAM2" , 0x1180009001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX1_RX003_ADR_CAM2" , 0x1180009001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX2_RX000_ADR_CAM2" , 0x118000a000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX2_RX001_ADR_CAM2" , 0x118000a000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX2_RX002_ADR_CAM2" , 0x118000a001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX2_RX003_ADR_CAM2" , 0x118000a001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX3_RX000_ADR_CAM2" , 0x118000b000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX3_RX001_ADR_CAM2" , 0x118000b000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX3_RX002_ADR_CAM2" , 0x118000b001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX3_RX003_ADR_CAM2" , 0x118000b001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX4_RX000_ADR_CAM2" , 0x118000c000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX4_RX001_ADR_CAM2" , 0x118000c000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX4_RX002_ADR_CAM2" , 0x118000c001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX4_RX003_ADR_CAM2" , 0x118000c001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX1_RX000_ADR_CAM3" , 0x1180009000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX1_RX001_ADR_CAM3" , 0x1180009000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX1_RX002_ADR_CAM3" , 0x1180009001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX1_RX003_ADR_CAM3" , 0x1180009001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX2_RX000_ADR_CAM3" , 0x118000a000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX2_RX001_ADR_CAM3" , 0x118000a000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX2_RX002_ADR_CAM3" , 0x118000a001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX2_RX003_ADR_CAM3" , 0x118000a001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX3_RX000_ADR_CAM3" , 0x118000b000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX3_RX001_ADR_CAM3" , 0x118000b000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX3_RX002_ADR_CAM3" , 0x118000b001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX3_RX003_ADR_CAM3" , 0x118000b001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX4_RX000_ADR_CAM3" , 0x118000c000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX4_RX001_ADR_CAM3" , 0x118000c000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX4_RX002_ADR_CAM3" , 0x118000c001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX4_RX003_ADR_CAM3" , 0x118000c001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX1_RX000_ADR_CAM4" , 0x11800090001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX1_RX001_ADR_CAM4" , 0x11800090009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX1_RX002_ADR_CAM4" , 0x11800090011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX1_RX003_ADR_CAM4" , 0x11800090019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX2_RX000_ADR_CAM4" , 0x118000a0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX2_RX001_ADR_CAM4" , 0x118000a0009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX2_RX002_ADR_CAM4" , 0x118000a0011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX2_RX003_ADR_CAM4" , 0x118000a0019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX3_RX000_ADR_CAM4" , 0x118000b0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX3_RX001_ADR_CAM4" , 0x118000b0009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX3_RX002_ADR_CAM4" , 0x118000b0011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX3_RX003_ADR_CAM4" , 0x118000b0019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX4_RX000_ADR_CAM4" , 0x118000c0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX4_RX001_ADR_CAM4" , 0x118000c0009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX4_RX002_ADR_CAM4" , 0x118000c0011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX4_RX003_ADR_CAM4" , 0x118000c0019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX1_RX000_ADR_CAM5" , 0x11800090001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX1_RX001_ADR_CAM5" , 0x11800090009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX1_RX002_ADR_CAM5" , 0x11800090011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX1_RX003_ADR_CAM5" , 0x11800090019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX2_RX000_ADR_CAM5" , 0x118000a0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX2_RX001_ADR_CAM5" , 0x118000a0009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX2_RX002_ADR_CAM5" , 0x118000a0011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX2_RX003_ADR_CAM5" , 0x118000a0019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX3_RX000_ADR_CAM5" , 0x118000b0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX3_RX001_ADR_CAM5" , 0x118000b0009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX3_RX002_ADR_CAM5" , 0x118000b0011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX3_RX003_ADR_CAM5" , 0x118000b0019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX4_RX000_ADR_CAM5" , 0x118000c0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX4_RX001_ADR_CAM5" , 0x118000c0009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX4_RX002_ADR_CAM5" , 0x118000c0011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX4_RX003_ADR_CAM5" , 0x118000c0019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX1_RX000_ADR_CAM_EN" , 0x1180009000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX1_RX001_ADR_CAM_EN" , 0x1180009000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX1_RX002_ADR_CAM_EN" , 0x1180009001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX1_RX003_ADR_CAM_EN" , 0x1180009001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX2_RX000_ADR_CAM_EN" , 0x118000a000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX2_RX001_ADR_CAM_EN" , 0x118000a000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX2_RX002_ADR_CAM_EN" , 0x118000a001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX2_RX003_ADR_CAM_EN" , 0x118000a001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX3_RX000_ADR_CAM_EN" , 0x118000b000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX3_RX001_ADR_CAM_EN" , 0x118000b000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX3_RX002_ADR_CAM_EN" , 0x118000b001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX3_RX003_ADR_CAM_EN" , 0x118000b001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX4_RX000_ADR_CAM_EN" , 0x118000c000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX4_RX001_ADR_CAM_EN" , 0x118000c000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX4_RX002_ADR_CAM_EN" , 0x118000c001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX4_RX003_ADR_CAM_EN" , 0x118000c001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX1_RX000_ADR_CTL" , 0x1180009000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX1_RX001_ADR_CTL" , 0x1180009000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX1_RX002_ADR_CTL" , 0x1180009001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX1_RX003_ADR_CTL" , 0x1180009001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX2_RX000_ADR_CTL" , 0x118000a000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX2_RX001_ADR_CTL" , 0x118000a000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX2_RX002_ADR_CTL" , 0x118000a001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX2_RX003_ADR_CTL" , 0x118000a001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX3_RX000_ADR_CTL" , 0x118000b000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX3_RX001_ADR_CTL" , 0x118000b000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX3_RX002_ADR_CTL" , 0x118000b001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX3_RX003_ADR_CTL" , 0x118000b001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX4_RX000_ADR_CTL" , 0x118000c000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX4_RX001_ADR_CTL" , 0x118000c000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX4_RX002_ADR_CTL" , 0x118000c001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX4_RX003_ADR_CTL" , 0x118000c001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX1_RX000_DECISION" , 0x1180009000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX1_RX001_DECISION" , 0x1180009000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX1_RX002_DECISION" , 0x1180009001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX1_RX003_DECISION" , 0x1180009001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX2_RX000_DECISION" , 0x118000a000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX2_RX001_DECISION" , 0x118000a000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX2_RX002_DECISION" , 0x118000a001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX2_RX003_DECISION" , 0x118000a001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX3_RX000_DECISION" , 0x118000b000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX3_RX001_DECISION" , 0x118000b000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX3_RX002_DECISION" , 0x118000b001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX3_RX003_DECISION" , 0x118000b001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX4_RX000_DECISION" , 0x118000c000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX4_RX001_DECISION" , 0x118000c000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX4_RX002_DECISION" , 0x118000c001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX4_RX003_DECISION" , 0x118000c001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX1_RX000_FRM_CHK" , 0x1180009000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX1_RX001_FRM_CHK" , 0x1180009000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX1_RX002_FRM_CHK" , 0x1180009001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX1_RX003_FRM_CHK" , 0x1180009001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX2_RX000_FRM_CHK" , 0x118000a000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX2_RX001_FRM_CHK" , 0x118000a000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX2_RX002_FRM_CHK" , 0x118000a001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX2_RX003_FRM_CHK" , 0x118000a001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX3_RX000_FRM_CHK" , 0x118000b000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX3_RX001_FRM_CHK" , 0x118000b000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX3_RX002_FRM_CHK" , 0x118000b001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX3_RX003_FRM_CHK" , 0x118000b001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX4_RX000_FRM_CHK" , 0x118000c000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX4_RX001_FRM_CHK" , 0x118000c000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX4_RX002_FRM_CHK" , 0x118000c001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX4_RX003_FRM_CHK" , 0x118000c001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX1_RX000_FRM_CTL" , 0x1180009000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX1_RX001_FRM_CTL" , 0x1180009000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX1_RX002_FRM_CTL" , 0x1180009001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX1_RX003_FRM_CTL" , 0x1180009001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX2_RX000_FRM_CTL" , 0x118000a000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX2_RX001_FRM_CTL" , 0x118000a000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX2_RX002_FRM_CTL" , 0x118000a001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX2_RX003_FRM_CTL" , 0x118000a001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX3_RX000_FRM_CTL" , 0x118000b000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX3_RX001_FRM_CTL" , 0x118000b000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX3_RX002_FRM_CTL" , 0x118000b001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX3_RX003_FRM_CTL" , 0x118000b001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX4_RX000_FRM_CTL" , 0x118000c000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX4_RX001_FRM_CTL" , 0x118000c000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX4_RX002_FRM_CTL" , 0x118000c001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX4_RX003_FRM_CTL" , 0x118000c001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX1_RX000_IFG" , 0x1180009000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX1_RX001_IFG" , 0x1180009000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX1_RX002_IFG" , 0x1180009001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX1_RX003_IFG" , 0x1180009001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX2_RX000_IFG" , 0x118000a000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX2_RX001_IFG" , 0x118000a000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX2_RX002_IFG" , 0x118000a001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX2_RX003_IFG" , 0x118000a001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX3_RX000_IFG" , 0x118000b000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX3_RX001_IFG" , 0x118000b000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX3_RX002_IFG" , 0x118000b001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX3_RX003_IFG" , 0x118000b001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX4_RX000_IFG" , 0x118000c000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX4_RX001_IFG" , 0x118000c000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX4_RX002_IFG" , 0x118000c001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX4_RX003_IFG" , 0x118000c001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX1_RX000_INT_EN" , 0x1180009000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX1_RX001_INT_EN" , 0x1180009000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX1_RX002_INT_EN" , 0x1180009001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX1_RX003_INT_EN" , 0x1180009001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX2_RX000_INT_EN" , 0x118000a000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX2_RX001_INT_EN" , 0x118000a000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX2_RX002_INT_EN" , 0x118000a001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX2_RX003_INT_EN" , 0x118000a001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX3_RX000_INT_EN" , 0x118000b000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX3_RX001_INT_EN" , 0x118000b000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX3_RX002_INT_EN" , 0x118000b001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX3_RX003_INT_EN" , 0x118000b001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX4_RX000_INT_EN" , 0x118000c000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX4_RX001_INT_EN" , 0x118000c000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX4_RX002_INT_EN" , 0x118000c001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX4_RX003_INT_EN" , 0x118000c001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX1_RX000_INT_REG" , 0x1180009000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX1_RX001_INT_REG" , 0x1180009000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX1_RX002_INT_REG" , 0x1180009001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX1_RX003_INT_REG" , 0x1180009001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX2_RX000_INT_REG" , 0x118000a000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX2_RX001_INT_REG" , 0x118000a000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX2_RX002_INT_REG" , 0x118000a001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX2_RX003_INT_REG" , 0x118000a001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX3_RX000_INT_REG" , 0x118000b000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX3_RX001_INT_REG" , 0x118000b000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX3_RX002_INT_REG" , 0x118000b001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX3_RX003_INT_REG" , 0x118000b001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX4_RX000_INT_REG" , 0x118000c000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX4_RX001_INT_REG" , 0x118000c000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX4_RX002_INT_REG" , 0x118000c001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX4_RX003_INT_REG" , 0x118000c001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX1_RX000_JABBER" , 0x1180009000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX1_RX001_JABBER" , 0x1180009000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX1_RX002_JABBER" , 0x1180009001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX1_RX003_JABBER" , 0x1180009001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX2_RX000_JABBER" , 0x118000a000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX2_RX001_JABBER" , 0x118000a000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX2_RX002_JABBER" , 0x118000a001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX2_RX003_JABBER" , 0x118000a001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX3_RX000_JABBER" , 0x118000b000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX3_RX001_JABBER" , 0x118000b000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX3_RX002_JABBER" , 0x118000b001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX3_RX003_JABBER" , 0x118000b001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX4_RX000_JABBER" , 0x118000c000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX4_RX001_JABBER" , 0x118000c000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX4_RX002_JABBER" , 0x118000c001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX4_RX003_JABBER" , 0x118000c001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180009000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180009000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180009001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180009001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX2_RX000_PAUSE_DROP_TIME" , 0x118000a000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX2_RX001_PAUSE_DROP_TIME" , 0x118000a000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX2_RX002_PAUSE_DROP_TIME" , 0x118000a001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX2_RX003_PAUSE_DROP_TIME" , 0x118000a001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX3_RX000_PAUSE_DROP_TIME" , 0x118000b000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX3_RX001_PAUSE_DROP_TIME" , 0x118000b000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX3_RX002_PAUSE_DROP_TIME" , 0x118000b001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX3_RX003_PAUSE_DROP_TIME" , 0x118000b001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX4_RX000_PAUSE_DROP_TIME" , 0x118000c000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX4_RX001_PAUSE_DROP_TIME" , 0x118000c000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX4_RX002_PAUSE_DROP_TIME" , 0x118000c001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX4_RX003_PAUSE_DROP_TIME" , 0x118000c001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX1_RX000_STATS_CTL" , 0x1180009000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX1_RX001_STATS_CTL" , 0x1180009000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX1_RX002_STATS_CTL" , 0x1180009001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX1_RX003_STATS_CTL" , 0x1180009001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX2_RX000_STATS_CTL" , 0x118000a000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX2_RX001_STATS_CTL" , 0x118000a000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX2_RX002_STATS_CTL" , 0x118000a001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX2_RX003_STATS_CTL" , 0x118000a001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX3_RX000_STATS_CTL" , 0x118000b000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX3_RX001_STATS_CTL" , 0x118000b000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX3_RX002_STATS_CTL" , 0x118000b001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX3_RX003_STATS_CTL" , 0x118000b001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX4_RX000_STATS_CTL" , 0x118000c000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX4_RX001_STATS_CTL" , 0x118000c000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX4_RX002_STATS_CTL" , 0x118000c001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX4_RX003_STATS_CTL" , 0x118000c001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX1_RX000_STATS_OCTS" , 0x1180009000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX1_RX001_STATS_OCTS" , 0x1180009000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX1_RX002_STATS_OCTS" , 0x1180009001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX1_RX003_STATS_OCTS" , 0x1180009001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX2_RX000_STATS_OCTS" , 0x118000a000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX2_RX001_STATS_OCTS" , 0x118000a000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX2_RX002_STATS_OCTS" , 0x118000a001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX2_RX003_STATS_OCTS" , 0x118000a001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX3_RX000_STATS_OCTS" , 0x118000b000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX3_RX001_STATS_OCTS" , 0x118000b000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX3_RX002_STATS_OCTS" , 0x118000b001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX3_RX003_STATS_OCTS" , 0x118000b001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX4_RX000_STATS_OCTS" , 0x118000c000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX4_RX001_STATS_OCTS" , 0x118000c000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX4_RX002_STATS_OCTS" , 0x118000c001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX4_RX003_STATS_OCTS" , 0x118000c001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180009000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180009000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180009001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180009001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX2_RX000_STATS_OCTS_CTL" , 0x118000a000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX2_RX001_STATS_OCTS_CTL" , 0x118000a000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX2_RX002_STATS_OCTS_CTL" , 0x118000a001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX2_RX003_STATS_OCTS_CTL" , 0x118000a001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX3_RX000_STATS_OCTS_CTL" , 0x118000b000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX3_RX001_STATS_OCTS_CTL" , 0x118000b000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX3_RX002_STATS_OCTS_CTL" , 0x118000b001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX3_RX003_STATS_OCTS_CTL" , 0x118000b001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX4_RX000_STATS_OCTS_CTL" , 0x118000c000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX4_RX001_STATS_OCTS_CTL" , 0x118000c000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX4_RX002_STATS_OCTS_CTL" , 0x118000c001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX4_RX003_STATS_OCTS_CTL" , 0x118000c001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800090000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800090008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800090010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800090018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX2_RX000_STATS_OCTS_DMAC" , 0x118000a0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX2_RX001_STATS_OCTS_DMAC" , 0x118000a0008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX2_RX002_STATS_OCTS_DMAC" , 0x118000a0010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX2_RX003_STATS_OCTS_DMAC" , 0x118000a0018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX3_RX000_STATS_OCTS_DMAC" , 0x118000b0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX3_RX001_STATS_OCTS_DMAC" , 0x118000b0008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX3_RX002_STATS_OCTS_DMAC" , 0x118000b0010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX3_RX003_STATS_OCTS_DMAC" , 0x118000b0018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX4_RX000_STATS_OCTS_DMAC" , 0x118000c0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX4_RX001_STATS_OCTS_DMAC" , 0x118000c0008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX4_RX002_STATS_OCTS_DMAC" , 0x118000c0010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX4_RX003_STATS_OCTS_DMAC" , 0x118000c0018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800090000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800090008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800090010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800090018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX2_RX000_STATS_OCTS_DRP" , 0x118000a0000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX2_RX001_STATS_OCTS_DRP" , 0x118000a0008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX2_RX002_STATS_OCTS_DRP" , 0x118000a0010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX2_RX003_STATS_OCTS_DRP" , 0x118000a0018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX3_RX000_STATS_OCTS_DRP" , 0x118000b0000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX3_RX001_STATS_OCTS_DRP" , 0x118000b0008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX3_RX002_STATS_OCTS_DRP" , 0x118000b0010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX3_RX003_STATS_OCTS_DRP" , 0x118000b0018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX4_RX000_STATS_OCTS_DRP" , 0x118000c0000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX4_RX001_STATS_OCTS_DRP" , 0x118000c0008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX4_RX002_STATS_OCTS_DRP" , 0x118000c0010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX4_RX003_STATS_OCTS_DRP" , 0x118000c0018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX1_RX000_STATS_PKTS" , 0x1180009000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX1_RX001_STATS_PKTS" , 0x1180009000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX1_RX002_STATS_PKTS" , 0x1180009001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX1_RX003_STATS_PKTS" , 0x1180009001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX2_RX000_STATS_PKTS" , 0x118000a000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX2_RX001_STATS_PKTS" , 0x118000a000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX2_RX002_STATS_PKTS" , 0x118000a001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX2_RX003_STATS_PKTS" , 0x118000a001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX3_RX000_STATS_PKTS" , 0x118000b000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX3_RX001_STATS_PKTS" , 0x118000b000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX3_RX002_STATS_PKTS" , 0x118000b001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX3_RX003_STATS_PKTS" , 0x118000b001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX4_RX000_STATS_PKTS" , 0x118000c000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX4_RX001_STATS_PKTS" , 0x118000c000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX4_RX002_STATS_PKTS" , 0x118000c001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX4_RX003_STATS_PKTS" , 0x118000c001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800090000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800090008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800090010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800090018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX2_RX000_STATS_PKTS_BAD" , 0x118000a0000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX2_RX001_STATS_PKTS_BAD" , 0x118000a0008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX2_RX002_STATS_PKTS_BAD" , 0x118000a0010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX2_RX003_STATS_PKTS_BAD" , 0x118000a0018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX3_RX000_STATS_PKTS_BAD" , 0x118000b0000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX3_RX001_STATS_PKTS_BAD" , 0x118000b0008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX3_RX002_STATS_PKTS_BAD" , 0x118000b0010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX3_RX003_STATS_PKTS_BAD" , 0x118000b0018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX4_RX000_STATS_PKTS_BAD" , 0x118000c0000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX4_RX001_STATS_PKTS_BAD" , 0x118000c0008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX4_RX002_STATS_PKTS_BAD" , 0x118000c0010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX4_RX003_STATS_PKTS_BAD" , 0x118000c0018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180009000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180009000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180009001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180009001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX2_RX000_STATS_PKTS_CTL" , 0x118000a000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX2_RX001_STATS_PKTS_CTL" , 0x118000a000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX2_RX002_STATS_PKTS_CTL" , 0x118000a001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX2_RX003_STATS_PKTS_CTL" , 0x118000a001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX3_RX000_STATS_PKTS_CTL" , 0x118000b000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX3_RX001_STATS_PKTS_CTL" , 0x118000b000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX3_RX002_STATS_PKTS_CTL" , 0x118000b001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX3_RX003_STATS_PKTS_CTL" , 0x118000b001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX4_RX000_STATS_PKTS_CTL" , 0x118000c000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX4_RX001_STATS_PKTS_CTL" , 0x118000c000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX4_RX002_STATS_PKTS_CTL" , 0x118000c001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX4_RX003_STATS_PKTS_CTL" , 0x118000c001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800090000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800090008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800090010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800090018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX2_RX000_STATS_PKTS_DMAC" , 0x118000a0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX2_RX001_STATS_PKTS_DMAC" , 0x118000a0008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX2_RX002_STATS_PKTS_DMAC" , 0x118000a0010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX2_RX003_STATS_PKTS_DMAC" , 0x118000a0018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX3_RX000_STATS_PKTS_DMAC" , 0x118000b0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX3_RX001_STATS_PKTS_DMAC" , 0x118000b0008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX3_RX002_STATS_PKTS_DMAC" , 0x118000b0010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX3_RX003_STATS_PKTS_DMAC" , 0x118000b0018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX4_RX000_STATS_PKTS_DMAC" , 0x118000c0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX4_RX001_STATS_PKTS_DMAC" , 0x118000c0008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX4_RX002_STATS_PKTS_DMAC" , 0x118000c0010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX4_RX003_STATS_PKTS_DMAC" , 0x118000c0018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800090000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800090008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800090010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800090018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX2_RX000_STATS_PKTS_DRP" , 0x118000a0000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX2_RX001_STATS_PKTS_DRP" , 0x118000a0008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX2_RX002_STATS_PKTS_DRP" , 0x118000a0010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX2_RX003_STATS_PKTS_DRP" , 0x118000a0018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX3_RX000_STATS_PKTS_DRP" , 0x118000b0000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX3_RX001_STATS_PKTS_DRP" , 0x118000b0008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX3_RX002_STATS_PKTS_DRP" , 0x118000b0010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX3_RX003_STATS_PKTS_DRP" , 0x118000b0018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX4_RX000_STATS_PKTS_DRP" , 0x118000c0000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX4_RX001_STATS_PKTS_DRP" , 0x118000c0008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX4_RX002_STATS_PKTS_DRP" , 0x118000c0010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX4_RX003_STATS_PKTS_DRP" , 0x118000c0018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX1_RX000_UDD_SKP" , 0x1180009000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX1_RX001_UDD_SKP" , 0x1180009000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX1_RX002_UDD_SKP" , 0x1180009001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX1_RX003_UDD_SKP" , 0x1180009001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX2_RX000_UDD_SKP" , 0x118000a000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX2_RX001_UDD_SKP" , 0x118000a000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX2_RX002_UDD_SKP" , 0x118000a001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX2_RX003_UDD_SKP" , 0x118000a001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX3_RX000_UDD_SKP" , 0x118000b000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX3_RX001_UDD_SKP" , 0x118000b000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX3_RX002_UDD_SKP" , 0x118000b001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX3_RX003_UDD_SKP" , 0x118000b001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX4_RX000_UDD_SKP" , 0x118000c000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX4_RX001_UDD_SKP" , 0x118000c000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX4_RX002_UDD_SKP" , 0x118000c001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX4_RX003_UDD_SKP" , 0x118000c001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX1_RX_BP_DROP000" , 0x1180009000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX1_RX_BP_DROP001" , 0x1180009000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX1_RX_BP_DROP002" , 0x1180009000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX1_RX_BP_DROP003" , 0x1180009000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX2_RX_BP_DROP000" , 0x118000a000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX2_RX_BP_DROP001" , 0x118000a000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX2_RX_BP_DROP002" , 0x118000a000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX2_RX_BP_DROP003" , 0x118000a000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX3_RX_BP_DROP000" , 0x118000b000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX3_RX_BP_DROP001" , 0x118000b000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX3_RX_BP_DROP002" , 0x118000b000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX3_RX_BP_DROP003" , 0x118000b000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX4_RX_BP_DROP000" , 0x118000c000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX4_RX_BP_DROP001" , 0x118000c000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX4_RX_BP_DROP002" , 0x118000c000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX4_RX_BP_DROP003" , 0x118000c000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX1_RX_BP_OFF000" , 0x1180009000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX1_RX_BP_OFF001" , 0x1180009000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX1_RX_BP_OFF002" , 0x1180009000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX1_RX_BP_OFF003" , 0x1180009000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX2_RX_BP_OFF000" , 0x118000a000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX2_RX_BP_OFF001" , 0x118000a000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX2_RX_BP_OFF002" , 0x118000a000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX2_RX_BP_OFF003" , 0x118000a000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX3_RX_BP_OFF000" , 0x118000b000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX3_RX_BP_OFF001" , 0x118000b000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX3_RX_BP_OFF002" , 0x118000b000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX3_RX_BP_OFF003" , 0x118000b000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX4_RX_BP_OFF000" , 0x118000c000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX4_RX_BP_OFF001" , 0x118000c000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX4_RX_BP_OFF002" , 0x118000c000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX4_RX_BP_OFF003" , 0x118000c000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX1_RX_BP_ON000" , 0x1180009000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX1_RX_BP_ON001" , 0x1180009000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX1_RX_BP_ON002" , 0x1180009000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX1_RX_BP_ON003" , 0x1180009000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX2_RX_BP_ON000" , 0x118000a000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX2_RX_BP_ON001" , 0x118000a000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX2_RX_BP_ON002" , 0x118000a000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX2_RX_BP_ON003" , 0x118000a000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX3_RX_BP_ON000" , 0x118000b000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX3_RX_BP_ON001" , 0x118000b000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX3_RX_BP_ON002" , 0x118000b000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX3_RX_BP_ON003" , 0x118000b000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX4_RX_BP_ON000" , 0x118000c000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX4_RX_BP_ON001" , 0x118000c000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX4_RX_BP_ON002" , 0x118000c000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX4_RX_BP_ON003" , 0x118000c000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX1_RX_HG2_STATUS" , 0x1180009000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX2_RX_HG2_STATUS" , 0x118000a000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX3_RX_HG2_STATUS" , 0x118000b000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX4_RX_HG2_STATUS" , 0x118000c000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX1_RX_PRT_INFO" , 0x11800090004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX2_RX_PRT_INFO" , 0x118000a0004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX3_RX_PRT_INFO" , 0x118000b0004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX4_RX_PRT_INFO" , 0x118000c0004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX1_RX_PRTS" , 0x1180009000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX2_RX_PRTS" , 0x118000a000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX3_RX_PRTS" , 0x118000b000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX4_RX_PRTS" , 0x118000c000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"GMX1_RX_XAUI_BAD_COL" , 0x1180009000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"GMX2_RX_XAUI_BAD_COL" , 0x118000a000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"GMX3_RX_XAUI_BAD_COL" , 0x118000b000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"GMX4_RX_XAUI_BAD_COL" , 0x118000c000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"GMX1_RX_XAUI_CTL" , 0x1180009000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"GMX2_RX_XAUI_CTL" , 0x118000a000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"GMX3_RX_XAUI_CTL" , 0x118000b000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"GMX4_RX_XAUI_CTL" , 0x118000c000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"GMX0_RXAUI_CTL" , 0x1180008000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"GMX1_RXAUI_CTL" , 0x1180009000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"GMX2_RXAUI_CTL" , 0x118000a000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"GMX3_RXAUI_CTL" , 0x118000b000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"GMX4_RXAUI_CTL" , 0x118000c000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX1_SMAC000" , 0x1180009000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX1_SMAC001" , 0x1180009000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX1_SMAC002" , 0x1180009001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX1_SMAC003" , 0x1180009001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX2_SMAC000" , 0x118000a000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX2_SMAC001" , 0x118000a000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX2_SMAC002" , 0x118000a001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX2_SMAC003" , 0x118000a001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX3_SMAC000" , 0x118000b000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX3_SMAC001" , 0x118000b000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX3_SMAC002" , 0x118000b001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX3_SMAC003" , 0x118000b001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX4_SMAC000" , 0x118000c000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX4_SMAC001" , 0x118000c000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX4_SMAC002" , 0x118000c001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX4_SMAC003" , 0x118000c001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX0_SOFT_BIST" , 0x11800080007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"GMX1_SOFT_BIST" , 0x11800090007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"GMX2_SOFT_BIST" , 0x118000a0007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"GMX3_SOFT_BIST" , 0x118000b0007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"GMX4_SOFT_BIST" , 0x118000c0007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"GMX1_STAT_BP" , 0x1180009000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"GMX2_STAT_BP" , 0x118000a000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"GMX3_STAT_BP" , 0x118000b000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"GMX4_STAT_BP" , 0x118000c000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX1_TX000_APPEND" , 0x1180009000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX1_TX001_APPEND" , 0x1180009000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX1_TX002_APPEND" , 0x1180009001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX1_TX003_APPEND" , 0x1180009001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX2_TX000_APPEND" , 0x118000a000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX2_TX001_APPEND" , 0x118000a000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX2_TX002_APPEND" , 0x118000a001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX2_TX003_APPEND" , 0x118000a001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX3_TX000_APPEND" , 0x118000b000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX3_TX001_APPEND" , 0x118000b000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX3_TX002_APPEND" , 0x118000b001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX3_TX003_APPEND" , 0x118000b001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX4_TX000_APPEND" , 0x118000c000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX4_TX001_APPEND" , 0x118000c000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX4_TX002_APPEND" , 0x118000c001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX4_TX003_APPEND" , 0x118000c001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX1_TX000_BURST" , 0x1180009000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX1_TX001_BURST" , 0x1180009000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX1_TX002_BURST" , 0x1180009001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX1_TX003_BURST" , 0x1180009001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX2_TX000_BURST" , 0x118000a000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX2_TX001_BURST" , 0x118000a000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX2_TX002_BURST" , 0x118000a001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX2_TX003_BURST" , 0x118000a001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX3_TX000_BURST" , 0x118000b000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX3_TX001_BURST" , 0x118000b000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX3_TX002_BURST" , 0x118000b001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX3_TX003_BURST" , 0x118000b001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX4_TX000_BURST" , 0x118000c000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX4_TX001_BURST" , 0x118000c000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX4_TX002_BURST" , 0x118000c001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX4_TX003_BURST" , 0x118000c001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX0_TX000_CBFC_XOFF" , 0x11800080005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"GMX1_TX000_CBFC_XOFF" , 0x11800090005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"GMX2_TX000_CBFC_XOFF" , 0x118000a0005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"GMX3_TX000_CBFC_XOFF" , 0x118000b0005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"GMX4_TX000_CBFC_XOFF" , 0x118000c0005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"GMX0_TX000_CBFC_XON" , 0x11800080005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"GMX1_TX000_CBFC_XON" , 0x11800090005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"GMX2_TX000_CBFC_XON" , 0x118000a0005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"GMX3_TX000_CBFC_XON" , 0x118000b0005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"GMX4_TX000_CBFC_XON" , 0x118000c0005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX1_TX000_CTL" , 0x1180009000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX1_TX001_CTL" , 0x1180009000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX1_TX002_CTL" , 0x1180009001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX1_TX003_CTL" , 0x1180009001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX2_TX000_CTL" , 0x118000a000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX2_TX001_CTL" , 0x118000a000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX2_TX002_CTL" , 0x118000a001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX2_TX003_CTL" , 0x118000a001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX3_TX000_CTL" , 0x118000b000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX3_TX001_CTL" , 0x118000b000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX3_TX002_CTL" , 0x118000b001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX3_TX003_CTL" , 0x118000b001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX4_TX000_CTL" , 0x118000c000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX4_TX001_CTL" , 0x118000c000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX4_TX002_CTL" , 0x118000c001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX4_TX003_CTL" , 0x118000c001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX1_TX000_MIN_PKT" , 0x1180009000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX1_TX001_MIN_PKT" , 0x1180009000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX1_TX002_MIN_PKT" , 0x1180009001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX1_TX003_MIN_PKT" , 0x1180009001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX2_TX000_MIN_PKT" , 0x118000a000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX2_TX001_MIN_PKT" , 0x118000a000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX2_TX002_MIN_PKT" , 0x118000a001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX2_TX003_MIN_PKT" , 0x118000a001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX3_TX000_MIN_PKT" , 0x118000b000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX3_TX001_MIN_PKT" , 0x118000b000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX3_TX002_MIN_PKT" , 0x118000b001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX3_TX003_MIN_PKT" , 0x118000b001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX4_TX000_MIN_PKT" , 0x118000c000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX4_TX001_MIN_PKT" , 0x118000c000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX4_TX002_MIN_PKT" , 0x118000c001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX4_TX003_MIN_PKT" , 0x118000c001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180009000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180009000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180009001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180009001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX2_TX000_PAUSE_PKT_INTERVAL", 0x118000a000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX2_TX001_PAUSE_PKT_INTERVAL", 0x118000a000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX2_TX002_PAUSE_PKT_INTERVAL", 0x118000a001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX2_TX003_PAUSE_PKT_INTERVAL", 0x118000a001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX3_TX000_PAUSE_PKT_INTERVAL", 0x118000b000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX3_TX001_PAUSE_PKT_INTERVAL", 0x118000b000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX3_TX002_PAUSE_PKT_INTERVAL", 0x118000b001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX3_TX003_PAUSE_PKT_INTERVAL", 0x118000b001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX4_TX000_PAUSE_PKT_INTERVAL", 0x118000c000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX4_TX001_PAUSE_PKT_INTERVAL", 0x118000c000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX4_TX002_PAUSE_PKT_INTERVAL", 0x118000c001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX4_TX003_PAUSE_PKT_INTERVAL", 0x118000c001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180009000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180009000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180009001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180009001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX2_TX000_PAUSE_PKT_TIME" , 0x118000a000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX2_TX001_PAUSE_PKT_TIME" , 0x118000a000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX2_TX002_PAUSE_PKT_TIME" , 0x118000a001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX2_TX003_PAUSE_PKT_TIME" , 0x118000a001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX3_TX000_PAUSE_PKT_TIME" , 0x118000b000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX3_TX001_PAUSE_PKT_TIME" , 0x118000b000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX3_TX002_PAUSE_PKT_TIME" , 0x118000b001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX3_TX003_PAUSE_PKT_TIME" , 0x118000b001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX4_TX000_PAUSE_PKT_TIME" , 0x118000c000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX4_TX001_PAUSE_PKT_TIME" , 0x118000c000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX4_TX002_PAUSE_PKT_TIME" , 0x118000c001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX4_TX003_PAUSE_PKT_TIME" , 0x118000c001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX1_TX000_PAUSE_TOGO" , 0x1180009000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX1_TX001_PAUSE_TOGO" , 0x1180009000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX1_TX002_PAUSE_TOGO" , 0x1180009001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX1_TX003_PAUSE_TOGO" , 0x1180009001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX2_TX000_PAUSE_TOGO" , 0x118000a000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX2_TX001_PAUSE_TOGO" , 0x118000a000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX2_TX002_PAUSE_TOGO" , 0x118000a001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX2_TX003_PAUSE_TOGO" , 0x118000a001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX3_TX000_PAUSE_TOGO" , 0x118000b000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX3_TX001_PAUSE_TOGO" , 0x118000b000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX3_TX002_PAUSE_TOGO" , 0x118000b001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX3_TX003_PAUSE_TOGO" , 0x118000b001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX4_TX000_PAUSE_TOGO" , 0x118000c000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX4_TX001_PAUSE_TOGO" , 0x118000c000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX4_TX002_PAUSE_TOGO" , 0x118000c001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX4_TX003_PAUSE_TOGO" , 0x118000c001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX1_TX000_PAUSE_ZERO" , 0x1180009000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX1_TX001_PAUSE_ZERO" , 0x1180009000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX1_TX002_PAUSE_ZERO" , 0x1180009001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX1_TX003_PAUSE_ZERO" , 0x1180009001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX2_TX000_PAUSE_ZERO" , 0x118000a000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX2_TX001_PAUSE_ZERO" , 0x118000a000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX2_TX002_PAUSE_ZERO" , 0x118000a001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX2_TX003_PAUSE_ZERO" , 0x118000a001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX3_TX000_PAUSE_ZERO" , 0x118000b000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX3_TX001_PAUSE_ZERO" , 0x118000b000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX3_TX002_PAUSE_ZERO" , 0x118000b001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX3_TX003_PAUSE_ZERO" , 0x118000b001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX4_TX000_PAUSE_ZERO" , 0x118000c000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX4_TX001_PAUSE_ZERO" , 0x118000c000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX4_TX002_PAUSE_ZERO" , 0x118000c001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX4_TX003_PAUSE_ZERO" , 0x118000c001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX0_TX000_PIPE" , 0x1180008000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX0_TX001_PIPE" , 0x1180008000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX0_TX002_PIPE" , 0x1180008001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX0_TX003_PIPE" , 0x1180008001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX1_TX000_PIPE" , 0x1180009000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX1_TX001_PIPE" , 0x1180009000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX1_TX002_PIPE" , 0x1180009001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX1_TX003_PIPE" , 0x1180009001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX2_TX000_PIPE" , 0x118000a000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX2_TX001_PIPE" , 0x118000a000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX2_TX002_PIPE" , 0x118000a001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX2_TX003_PIPE" , 0x118000a001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX3_TX000_PIPE" , 0x118000b000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX3_TX001_PIPE" , 0x118000b000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX3_TX002_PIPE" , 0x118000b001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX3_TX003_PIPE" , 0x118000b001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX4_TX000_PIPE" , 0x118000c000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX4_TX001_PIPE" , 0x118000c000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX4_TX002_PIPE" , 0x118000c001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX4_TX003_PIPE" , 0x118000c001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX0_TX003_SGMII_CTL" , 0x1180008001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX1_TX000_SGMII_CTL" , 0x1180009000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX1_TX001_SGMII_CTL" , 0x1180009000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX1_TX002_SGMII_CTL" , 0x1180009001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX1_TX003_SGMII_CTL" , 0x1180009001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX2_TX000_SGMII_CTL" , 0x118000a000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX2_TX001_SGMII_CTL" , 0x118000a000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX2_TX002_SGMII_CTL" , 0x118000a001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX2_TX003_SGMII_CTL" , 0x118000a001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX3_TX000_SGMII_CTL" , 0x118000b000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX3_TX001_SGMII_CTL" , 0x118000b000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX3_TX002_SGMII_CTL" , 0x118000b001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX3_TX003_SGMII_CTL" , 0x118000b001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX4_TX000_SGMII_CTL" , 0x118000c000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX4_TX001_SGMII_CTL" , 0x118000c000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX4_TX002_SGMII_CTL" , 0x118000c001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX4_TX003_SGMII_CTL" , 0x118000c001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX1_TX000_SLOT" , 0x1180009000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX1_TX001_SLOT" , 0x1180009000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX1_TX002_SLOT" , 0x1180009001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX1_TX003_SLOT" , 0x1180009001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX2_TX000_SLOT" , 0x118000a000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX2_TX001_SLOT" , 0x118000a000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX2_TX002_SLOT" , 0x118000a001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX2_TX003_SLOT" , 0x118000a001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX3_TX000_SLOT" , 0x118000b000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX3_TX001_SLOT" , 0x118000b000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX3_TX002_SLOT" , 0x118000b001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX3_TX003_SLOT" , 0x118000b001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX4_TX000_SLOT" , 0x118000c000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX4_TX001_SLOT" , 0x118000c000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX4_TX002_SLOT" , 0x118000c001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX4_TX003_SLOT" , 0x118000c001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX1_TX000_SOFT_PAUSE" , 0x1180009000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX1_TX001_SOFT_PAUSE" , 0x1180009000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX1_TX002_SOFT_PAUSE" , 0x1180009001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX1_TX003_SOFT_PAUSE" , 0x1180009001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX2_TX000_SOFT_PAUSE" , 0x118000a000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX2_TX001_SOFT_PAUSE" , 0x118000a000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX2_TX002_SOFT_PAUSE" , 0x118000a001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX2_TX003_SOFT_PAUSE" , 0x118000a001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX3_TX000_SOFT_PAUSE" , 0x118000b000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX3_TX001_SOFT_PAUSE" , 0x118000b000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX3_TX002_SOFT_PAUSE" , 0x118000b001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX3_TX003_SOFT_PAUSE" , 0x118000b001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX4_TX000_SOFT_PAUSE" , 0x118000c000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX4_TX001_SOFT_PAUSE" , 0x118000c000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX4_TX002_SOFT_PAUSE" , 0x118000c001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX4_TX003_SOFT_PAUSE" , 0x118000c001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX1_TX000_STAT0" , 0x1180009000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX1_TX001_STAT0" , 0x1180009000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX1_TX002_STAT0" , 0x1180009001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX1_TX003_STAT0" , 0x1180009001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX2_TX000_STAT0" , 0x118000a000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX2_TX001_STAT0" , 0x118000a000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX2_TX002_STAT0" , 0x118000a001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX2_TX003_STAT0" , 0x118000a001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX3_TX000_STAT0" , 0x118000b000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX3_TX001_STAT0" , 0x118000b000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX3_TX002_STAT0" , 0x118000b001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX3_TX003_STAT0" , 0x118000b001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX4_TX000_STAT0" , 0x118000c000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX4_TX001_STAT0" , 0x118000c000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX4_TX002_STAT0" , 0x118000c001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX4_TX003_STAT0" , 0x118000c001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX1_TX000_STAT1" , 0x1180009000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX1_TX001_STAT1" , 0x1180009000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX1_TX002_STAT1" , 0x1180009001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX1_TX003_STAT1" , 0x1180009001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX2_TX000_STAT1" , 0x118000a000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX2_TX001_STAT1" , 0x118000a000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX2_TX002_STAT1" , 0x118000a001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX2_TX003_STAT1" , 0x118000a001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX3_TX000_STAT1" , 0x118000b000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX3_TX001_STAT1" , 0x118000b000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX3_TX002_STAT1" , 0x118000b001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX3_TX003_STAT1" , 0x118000b001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX4_TX000_STAT1" , 0x118000c000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX4_TX001_STAT1" , 0x118000c000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX4_TX002_STAT1" , 0x118000c001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX4_TX003_STAT1" , 0x118000c001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX1_TX000_STAT2" , 0x1180009000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX1_TX001_STAT2" , 0x1180009000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX1_TX002_STAT2" , 0x1180009001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX1_TX003_STAT2" , 0x1180009001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX2_TX000_STAT2" , 0x118000a000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX2_TX001_STAT2" , 0x118000a000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX2_TX002_STAT2" , 0x118000a001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX2_TX003_STAT2" , 0x118000a001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX3_TX000_STAT2" , 0x118000b000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX3_TX001_STAT2" , 0x118000b000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX3_TX002_STAT2" , 0x118000b001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX3_TX003_STAT2" , 0x118000b001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX4_TX000_STAT2" , 0x118000c000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX4_TX001_STAT2" , 0x118000c000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX4_TX002_STAT2" , 0x118000c001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX4_TX003_STAT2" , 0x118000c001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX1_TX000_STAT3" , 0x1180009000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX1_TX001_STAT3" , 0x1180009000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX1_TX002_STAT3" , 0x1180009001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX1_TX003_STAT3" , 0x1180009001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX2_TX000_STAT3" , 0x118000a000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX2_TX001_STAT3" , 0x118000a000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX2_TX002_STAT3" , 0x118000a001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX2_TX003_STAT3" , 0x118000a001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX3_TX000_STAT3" , 0x118000b000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX3_TX001_STAT3" , 0x118000b000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX3_TX002_STAT3" , 0x118000b001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX3_TX003_STAT3" , 0x118000b001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX4_TX000_STAT3" , 0x118000c000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX4_TX001_STAT3" , 0x118000c000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX4_TX002_STAT3" , 0x118000c001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX4_TX003_STAT3" , 0x118000c001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX1_TX000_STAT4" , 0x11800090002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX1_TX001_STAT4" , 0x1180009000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX1_TX002_STAT4" , 0x11800090012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX1_TX003_STAT4" , 0x1180009001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX2_TX000_STAT4" , 0x118000a0002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX2_TX001_STAT4" , 0x118000a000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX2_TX002_STAT4" , 0x118000a0012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX2_TX003_STAT4" , 0x118000a001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX3_TX000_STAT4" , 0x118000b0002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX3_TX001_STAT4" , 0x118000b000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX3_TX002_STAT4" , 0x118000b0012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX3_TX003_STAT4" , 0x118000b001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX4_TX000_STAT4" , 0x118000c0002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX4_TX001_STAT4" , 0x118000c000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX4_TX002_STAT4" , 0x118000c0012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX4_TX003_STAT4" , 0x118000c001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX1_TX000_STAT5" , 0x11800090002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX1_TX001_STAT5" , 0x1180009000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX1_TX002_STAT5" , 0x11800090012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX1_TX003_STAT5" , 0x1180009001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX2_TX000_STAT5" , 0x118000a0002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX2_TX001_STAT5" , 0x118000a000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX2_TX002_STAT5" , 0x118000a0012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX2_TX003_STAT5" , 0x118000a001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX3_TX000_STAT5" , 0x118000b0002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX3_TX001_STAT5" , 0x118000b000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX3_TX002_STAT5" , 0x118000b0012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX3_TX003_STAT5" , 0x118000b001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX4_TX000_STAT5" , 0x118000c0002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX4_TX001_STAT5" , 0x118000c000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX4_TX002_STAT5" , 0x118000c0012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX4_TX003_STAT5" , 0x118000c001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX1_TX000_STAT6" , 0x11800090002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX1_TX001_STAT6" , 0x1180009000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX1_TX002_STAT6" , 0x11800090012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX1_TX003_STAT6" , 0x1180009001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX2_TX000_STAT6" , 0x118000a0002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX2_TX001_STAT6" , 0x118000a000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX2_TX002_STAT6" , 0x118000a0012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX2_TX003_STAT6" , 0x118000a001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX3_TX000_STAT6" , 0x118000b0002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX3_TX001_STAT6" , 0x118000b000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX3_TX002_STAT6" , 0x118000b0012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX3_TX003_STAT6" , 0x118000b001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX4_TX000_STAT6" , 0x118000c0002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX4_TX001_STAT6" , 0x118000c000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX4_TX002_STAT6" , 0x118000c0012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX4_TX003_STAT6" , 0x118000c001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX1_TX000_STAT7" , 0x11800090002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX1_TX001_STAT7" , 0x1180009000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX1_TX002_STAT7" , 0x11800090012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX1_TX003_STAT7" , 0x1180009001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX2_TX000_STAT7" , 0x118000a0002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX2_TX001_STAT7" , 0x118000a000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX2_TX002_STAT7" , 0x118000a0012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX2_TX003_STAT7" , 0x118000a001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX3_TX000_STAT7" , 0x118000b0002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX3_TX001_STAT7" , 0x118000b000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX3_TX002_STAT7" , 0x118000b0012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX3_TX003_STAT7" , 0x118000b001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX4_TX000_STAT7" , 0x118000c0002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX4_TX001_STAT7" , 0x118000c000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX4_TX002_STAT7" , 0x118000c0012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX4_TX003_STAT7" , 0x118000c001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX1_TX000_STAT8" , 0x11800090002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX1_TX001_STAT8" , 0x1180009000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX1_TX002_STAT8" , 0x11800090012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX1_TX003_STAT8" , 0x1180009001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX2_TX000_STAT8" , 0x118000a0002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX2_TX001_STAT8" , 0x118000a000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX2_TX002_STAT8" , 0x118000a0012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX2_TX003_STAT8" , 0x118000a001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX3_TX000_STAT8" , 0x118000b0002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX3_TX001_STAT8" , 0x118000b000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX3_TX002_STAT8" , 0x118000b0012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX3_TX003_STAT8" , 0x118000b001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX4_TX000_STAT8" , 0x118000c0002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX4_TX001_STAT8" , 0x118000c000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX4_TX002_STAT8" , 0x118000c0012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX4_TX003_STAT8" , 0x118000c001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX1_TX000_STAT9" , 0x11800090002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX1_TX001_STAT9" , 0x1180009000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX1_TX002_STAT9" , 0x11800090012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX1_TX003_STAT9" , 0x1180009001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX2_TX000_STAT9" , 0x118000a0002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX2_TX001_STAT9" , 0x118000a000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX2_TX002_STAT9" , 0x118000a0012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX2_TX003_STAT9" , 0x118000a001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX3_TX000_STAT9" , 0x118000b0002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX3_TX001_STAT9" , 0x118000b000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX3_TX002_STAT9" , 0x118000b0012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX3_TX003_STAT9" , 0x118000b001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX4_TX000_STAT9" , 0x118000c0002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX4_TX001_STAT9" , 0x118000c000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX4_TX002_STAT9" , 0x118000c0012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX4_TX003_STAT9" , 0x118000c001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX1_TX000_STATS_CTL" , 0x1180009000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX1_TX001_STATS_CTL" , 0x1180009000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX1_TX002_STATS_CTL" , 0x1180009001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX1_TX003_STATS_CTL" , 0x1180009001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX2_TX000_STATS_CTL" , 0x118000a000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX2_TX001_STATS_CTL" , 0x118000a000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX2_TX002_STATS_CTL" , 0x118000a001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX2_TX003_STATS_CTL" , 0x118000a001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX3_TX000_STATS_CTL" , 0x118000b000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX3_TX001_STATS_CTL" , 0x118000b000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX3_TX002_STATS_CTL" , 0x118000b001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX3_TX003_STATS_CTL" , 0x118000b001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX4_TX000_STATS_CTL" , 0x118000c000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX4_TX001_STATS_CTL" , 0x118000c000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX4_TX002_STATS_CTL" , 0x118000c001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX4_TX003_STATS_CTL" , 0x118000c001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX1_TX000_THRESH" , 0x1180009000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX1_TX001_THRESH" , 0x1180009000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX1_TX002_THRESH" , 0x1180009001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX1_TX003_THRESH" , 0x1180009001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX2_TX000_THRESH" , 0x118000a000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX2_TX001_THRESH" , 0x118000a000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX2_TX002_THRESH" , 0x118000a001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX2_TX003_THRESH" , 0x118000a001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX3_TX000_THRESH" , 0x118000b000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX3_TX001_THRESH" , 0x118000b000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX3_TX002_THRESH" , 0x118000b001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX3_TX003_THRESH" , 0x118000b001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX4_TX000_THRESH" , 0x118000c000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX4_TX001_THRESH" , 0x118000c000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX4_TX002_THRESH" , 0x118000c001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX4_TX003_THRESH" , 0x118000c001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX1_TX_BP" , 0x11800090004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX2_TX_BP" , 0x118000a0004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX3_TX_BP" , 0x118000b0004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX4_TX_BP" , 0x118000c0004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX1_TX_COL_ATTEMPT" , 0x1180009000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX2_TX_COL_ATTEMPT" , 0x118000a000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX3_TX_COL_ATTEMPT" , 0x118000b000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX4_TX_COL_ATTEMPT" , 0x118000c000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX1_TX_CORRUPT" , 0x11800090004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX2_TX_CORRUPT" , 0x118000a0004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX3_TX_CORRUPT" , 0x118000b0004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX4_TX_CORRUPT" , 0x118000c0004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX1_TX_HG2_REG1" , 0x1180009000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX2_TX_HG2_REG1" , 0x118000a000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX3_TX_HG2_REG1" , 0x118000b000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX4_TX_HG2_REG1" , 0x118000c000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"GMX1_TX_HG2_REG2" , 0x1180009000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"GMX2_TX_HG2_REG2" , 0x118000a000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"GMX3_TX_HG2_REG2" , 0x118000b000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"GMX4_TX_HG2_REG2" , 0x118000c000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"GMX1_TX_IFG" , 0x1180009000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"GMX2_TX_IFG" , 0x118000a000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"GMX3_TX_IFG" , 0x118000b000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"GMX4_TX_IFG" , 0x118000c000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"GMX1_TX_INT_EN" , 0x1180009000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"GMX2_TX_INT_EN" , 0x118000a000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"GMX3_TX_INT_EN" , 0x118000b000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"GMX4_TX_INT_EN" , 0x118000c000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"GMX1_TX_INT_REG" , 0x1180009000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"GMX2_TX_INT_REG" , 0x118000a000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"GMX3_TX_INT_REG" , 0x118000b000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"GMX4_TX_INT_REG" , 0x118000c000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"GMX1_TX_JAM" , 0x1180009000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"GMX2_TX_JAM" , 0x118000a000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"GMX3_TX_JAM" , 0x118000b000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"GMX4_TX_JAM" , 0x118000c000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"GMX1_TX_LFSR" , 0x11800090004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"GMX2_TX_LFSR" , 0x118000a0004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"GMX3_TX_LFSR" , 0x118000b0004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"GMX4_TX_LFSR" , 0x118000c0004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"GMX1_TX_OVR_BP" , 0x11800090004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"GMX2_TX_OVR_BP" , 0x118000a0004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"GMX3_TX_OVR_BP" , 0x118000b0004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"GMX4_TX_OVR_BP" , 0x118000c0004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800090004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"GMX2_TX_PAUSE_PKT_DMAC" , 0x118000a0004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"GMX3_TX_PAUSE_PKT_DMAC" , 0x118000b0004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"GMX4_TX_PAUSE_PKT_DMAC" , 0x118000c0004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800090004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"GMX2_TX_PAUSE_PKT_TYPE" , 0x118000a0004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"GMX3_TX_PAUSE_PKT_TYPE" , 0x118000b0004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"GMX4_TX_PAUSE_PKT_TYPE" , 0x118000c0004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"GMX1_TX_PRTS" , 0x1180009000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"GMX2_TX_PRTS" , 0x118000a000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"GMX3_TX_PRTS" , 0x118000b000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"GMX4_TX_PRTS" , 0x118000c000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"GMX1_TX_XAUI_CTL" , 0x1180009000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"GMX2_TX_XAUI_CTL" , 0x118000a000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"GMX3_TX_XAUI_CTL" , 0x118000b000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"GMX4_TX_XAUI_CTL" , 0x118000c000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"GMX1_XAUI_EXT_LOOPBACK" , 0x1180009000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"GMX2_XAUI_EXT_LOOPBACK" , 0x118000a000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"GMX3_XAUI_EXT_LOOPBACK" , 0x118000b000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"GMX4_XAUI_EXT_LOOPBACK" , 0x118000c000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 458},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 458},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 458},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 458},
- {"GPIO_CLK_QLM0" , 0x10700000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 459},
- {"GPIO_CLK_QLM1" , 0x10700000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 459},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_TIM_CTL" , 0x10700000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 463},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"ILK_BIST_SUM" , 0x1180014000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
- {"ILK_GBL_CFG" , 0x1180014000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
- {"ILK_GBL_INT" , 0x1180014000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
- {"ILK_GBL_INT_EN" , 0x1180014000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
- {"ILK_INT_SUM" , 0x1180014000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"ILK_LNE_DBG" , 0x1180014030008ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"ILK_LNE_STS_MSG" , 0x1180014030000ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"ILK_RX0_CFG0" , 0x1180014020000ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"ILK_RX1_CFG0" , 0x1180014024000ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"ILK_RX0_CFG1" , 0x1180014020008ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"ILK_RX1_CFG1" , 0x1180014024008ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"ILK_RX0_FLOW_CTL0" , 0x1180014020090ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"ILK_RX1_FLOW_CTL0" , 0x1180014024090ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"ILK_RX0_FLOW_CTL1" , 0x1180014020098ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"ILK_RX1_FLOW_CTL1" , 0x1180014024098ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"ILK_RX0_IDX_CAL" , 0x11800140200a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"ILK_RX1_IDX_CAL" , 0x11800140240a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"ILK_RX0_IDX_STAT0" , 0x1180014020070ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"ILK_RX1_IDX_STAT0" , 0x1180014024070ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"ILK_RX0_IDX_STAT1" , 0x1180014020078ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"ILK_RX1_IDX_STAT1" , 0x1180014024078ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"ILK_RX0_INT" , 0x1180014020010ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"ILK_RX1_INT" , 0x1180014024010ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"ILK_RX0_INT_EN" , 0x1180014020018ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"ILK_RX1_INT_EN" , 0x1180014024018ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"ILK_RX0_JABBER" , 0x11800140200b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"ILK_RX1_JABBER" , 0x11800140240b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"ILK_RX0_MEM_CAL0" , 0x11800140200a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"ILK_RX1_MEM_CAL0" , 0x11800140240a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"ILK_RX0_MEM_CAL1" , 0x11800140200b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"ILK_RX1_MEM_CAL1" , 0x11800140240b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"ILK_RX0_MEM_STAT0" , 0x1180014020080ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"ILK_RX1_MEM_STAT0" , 0x1180014024080ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"ILK_RX0_MEM_STAT1" , 0x1180014020088ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"ILK_RX1_MEM_STAT1" , 0x1180014024088ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"ILK_RX0_STAT0" , 0x1180014020020ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"ILK_RX1_STAT0" , 0x1180014024020ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"ILK_RX0_STAT1" , 0x1180014020028ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"ILK_RX1_STAT1" , 0x1180014024028ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"ILK_RX0_STAT2" , 0x1180014020030ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"ILK_RX1_STAT2" , 0x1180014024030ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"ILK_RX0_STAT3" , 0x1180014020038ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"ILK_RX1_STAT3" , 0x1180014024038ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"ILK_RX0_STAT4" , 0x1180014020040ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"ILK_RX1_STAT4" , 0x1180014024040ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"ILK_RX0_STAT5" , 0x1180014020048ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"ILK_RX1_STAT5" , 0x1180014024048ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"ILK_RX0_STAT6" , 0x1180014020050ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"ILK_RX1_STAT6" , 0x1180014024050ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"ILK_RX0_STAT7" , 0x1180014020058ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"ILK_RX1_STAT7" , 0x1180014024058ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"ILK_RX0_STAT8" , 0x1180014020060ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"ILK_RX1_STAT8" , 0x1180014024060ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"ILK_RX0_STAT9" , 0x1180014020068ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"ILK_RX1_STAT9" , 0x1180014024068ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"ILK_RX_LNE0_CFG" , 0x1180014038000ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"ILK_RX_LNE1_CFG" , 0x1180014038400ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"ILK_RX_LNE2_CFG" , 0x1180014038800ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"ILK_RX_LNE3_CFG" , 0x1180014038c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"ILK_RX_LNE4_CFG" , 0x1180014039000ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"ILK_RX_LNE5_CFG" , 0x1180014039400ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"ILK_RX_LNE6_CFG" , 0x1180014039800ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"ILK_RX_LNE7_CFG" , 0x1180014039c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"ILK_RX_LNE0_INT" , 0x1180014038008ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"ILK_RX_LNE1_INT" , 0x1180014038408ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"ILK_RX_LNE2_INT" , 0x1180014038808ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"ILK_RX_LNE3_INT" , 0x1180014038c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"ILK_RX_LNE4_INT" , 0x1180014039008ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"ILK_RX_LNE5_INT" , 0x1180014039408ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"ILK_RX_LNE6_INT" , 0x1180014039808ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"ILK_RX_LNE7_INT" , 0x1180014039c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"ILK_RX_LNE0_INT_EN" , 0x1180014038010ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"ILK_RX_LNE1_INT_EN" , 0x1180014038410ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"ILK_RX_LNE2_INT_EN" , 0x1180014038810ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"ILK_RX_LNE3_INT_EN" , 0x1180014038c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"ILK_RX_LNE4_INT_EN" , 0x1180014039010ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"ILK_RX_LNE5_INT_EN" , 0x1180014039410ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"ILK_RX_LNE6_INT_EN" , 0x1180014039810ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"ILK_RX_LNE7_INT_EN" , 0x1180014039c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"ILK_RX_LNE0_STAT0" , 0x1180014038018ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"ILK_RX_LNE1_STAT0" , 0x1180014038418ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"ILK_RX_LNE2_STAT0" , 0x1180014038818ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"ILK_RX_LNE3_STAT0" , 0x1180014038c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"ILK_RX_LNE4_STAT0" , 0x1180014039018ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"ILK_RX_LNE5_STAT0" , 0x1180014039418ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"ILK_RX_LNE6_STAT0" , 0x1180014039818ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"ILK_RX_LNE7_STAT0" , 0x1180014039c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"ILK_RX_LNE0_STAT1" , 0x1180014038020ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"ILK_RX_LNE1_STAT1" , 0x1180014038420ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"ILK_RX_LNE2_STAT1" , 0x1180014038820ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"ILK_RX_LNE3_STAT1" , 0x1180014038c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"ILK_RX_LNE4_STAT1" , 0x1180014039020ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"ILK_RX_LNE5_STAT1" , 0x1180014039420ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"ILK_RX_LNE6_STAT1" , 0x1180014039820ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"ILK_RX_LNE7_STAT1" , 0x1180014039c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"ILK_RX_LNE0_STAT2" , 0x1180014038028ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE1_STAT2" , 0x1180014038428ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE2_STAT2" , 0x1180014038828ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE3_STAT2" , 0x1180014038c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE4_STAT2" , 0x1180014039028ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE5_STAT2" , 0x1180014039428ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE6_STAT2" , 0x1180014039828ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE7_STAT2" , 0x1180014039c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE0_STAT3" , 0x1180014038030ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE1_STAT3" , 0x1180014038430ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE2_STAT3" , 0x1180014038830ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE3_STAT3" , 0x1180014038c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE4_STAT3" , 0x1180014039030ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE5_STAT3" , 0x1180014039430ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE6_STAT3" , 0x1180014039830ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE7_STAT3" , 0x1180014039c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE0_STAT4" , 0x1180014038038ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE1_STAT4" , 0x1180014038438ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE2_STAT4" , 0x1180014038838ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE3_STAT4" , 0x1180014038c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE4_STAT4" , 0x1180014039038ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE5_STAT4" , 0x1180014039438ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE6_STAT4" , 0x1180014039838ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE7_STAT4" , 0x1180014039c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE0_STAT5" , 0x1180014038040ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE1_STAT5" , 0x1180014038440ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE2_STAT5" , 0x1180014038840ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE3_STAT5" , 0x1180014038c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE4_STAT5" , 0x1180014039040ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE5_STAT5" , 0x1180014039440ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE6_STAT5" , 0x1180014039840ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE7_STAT5" , 0x1180014039c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE0_STAT6" , 0x1180014038048ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE1_STAT6" , 0x1180014038448ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE2_STAT6" , 0x1180014038848ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE3_STAT6" , 0x1180014038c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE4_STAT6" , 0x1180014039048ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE5_STAT6" , 0x1180014039448ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE6_STAT6" , 0x1180014039848ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE7_STAT6" , 0x1180014039c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE0_STAT7" , 0x1180014038050ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE1_STAT7" , 0x1180014038450ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE2_STAT7" , 0x1180014038850ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE3_STAT7" , 0x1180014038c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE4_STAT7" , 0x1180014039050ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE5_STAT7" , 0x1180014039450ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE6_STAT7" , 0x1180014039850ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE7_STAT7" , 0x1180014039c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE0_STAT8" , 0x1180014038058ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE1_STAT8" , 0x1180014038458ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE2_STAT8" , 0x1180014038858ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE3_STAT8" , 0x1180014038c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE4_STAT8" , 0x1180014039058ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE5_STAT8" , 0x1180014039458ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE6_STAT8" , 0x1180014039858ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE7_STAT8" , 0x1180014039c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE0_STAT9" , 0x1180014038060ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE1_STAT9" , 0x1180014038460ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE2_STAT9" , 0x1180014038860ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE3_STAT9" , 0x1180014038c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE4_STAT9" , 0x1180014039060ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE5_STAT9" , 0x1180014039460ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE6_STAT9" , 0x1180014039860ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE7_STAT9" , 0x1180014039c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RXF_IDX_PMAP" , 0x1180014000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"ILK_RXF_MEM_PMAP" , 0x1180014000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"ILK_SER_CFG" , 0x1180014000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"ILK_TX0_CFG0" , 0x1180014010000ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"ILK_TX1_CFG0" , 0x1180014014000ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"ILK_TX0_CFG1" , 0x1180014010008ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"ILK_TX1_CFG1" , 0x1180014014008ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"ILK_TX0_DBG" , 0x1180014010070ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"ILK_TX1_DBG" , 0x1180014014070ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"ILK_TX0_FLOW_CTL0" , 0x1180014010048ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"ILK_TX1_FLOW_CTL0" , 0x1180014014048ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"ILK_TX0_FLOW_CTL1" , 0x1180014010050ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"ILK_TX1_FLOW_CTL1" , 0x1180014014050ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"ILK_TX0_IDX_CAL" , 0x1180014010058ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"ILK_TX1_IDX_CAL" , 0x1180014014058ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"ILK_TX0_IDX_PMAP" , 0x1180014010010ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"ILK_TX1_IDX_PMAP" , 0x1180014014010ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"ILK_TX0_IDX_STAT0" , 0x1180014010020ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"ILK_TX1_IDX_STAT0" , 0x1180014014020ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"ILK_TX0_IDX_STAT1" , 0x1180014010028ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"ILK_TX1_IDX_STAT1" , 0x1180014014028ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"ILK_TX0_INT" , 0x1180014010078ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"ILK_TX1_INT" , 0x1180014014078ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"ILK_TX0_INT_EN" , 0x1180014010080ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"ILK_TX1_INT_EN" , 0x1180014014080ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"ILK_TX0_MEM_CAL0" , 0x1180014010060ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"ILK_TX1_MEM_CAL0" , 0x1180014014060ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"ILK_TX0_MEM_CAL1" , 0x1180014010068ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"ILK_TX1_MEM_CAL1" , 0x1180014014068ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"ILK_TX0_MEM_PMAP" , 0x1180014010018ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"ILK_TX1_MEM_PMAP" , 0x1180014014018ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"ILK_TX0_MEM_STAT0" , 0x1180014010030ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"ILK_TX1_MEM_STAT0" , 0x1180014014030ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"ILK_TX0_MEM_STAT1" , 0x1180014010038ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"ILK_TX1_MEM_STAT1" , 0x1180014014038ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"ILK_TX0_PIPE" , 0x1180014010088ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"ILK_TX1_PIPE" , 0x1180014014088ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"ILK_TX0_RMATCH" , 0x1180014010040ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"ILK_TX1_RMATCH" , 0x1180014014040ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"IOB1_BIST_STATUS" , 0x11800f00107f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"IOB1_CTL_STATUS" , 0x11800f0010050ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"IOB1_TO_CMB_CREDITS" , 0x11800f00100b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"IOB_TO_CMB_CREDITS" , 0x11800f00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"IOB_TO_NCB_DID_00_CREDITS" , 0x11800f0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"IOB_TO_NCB_DID_111_CREDITS" , 0x11800f0000b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"IOB_TO_NCB_DID_223_CREDITS" , 0x11800f0000ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"IOB_TO_NCB_DID_24_CREDITS" , 0x11800f00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"IOB_TO_NCB_DID_32_CREDITS" , 0x11800f0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"IOB_TO_NCB_DID_40_CREDITS" , 0x11800f0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"IOB_TO_NCB_DID_55_CREDITS" , 0x11800f00009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"IOB_TO_NCB_DID_64_CREDITS" , 0x11800f0000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"IOB_TO_NCB_DID_79_CREDITS" , 0x11800f0000a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"IOB_TO_NCB_DID_96_CREDITS" , 0x11800f0000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"IOB_TO_NCB_DID_98_CREDITS" , 0x11800f0000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 561},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 562},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 563},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 564},
- {"IPD_BPID0_MBUF_TH" , 0x14f0000002000ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID1_MBUF_TH" , 0x14f0000002008ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID2_MBUF_TH" , 0x14f0000002010ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID3_MBUF_TH" , 0x14f0000002018ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID4_MBUF_TH" , 0x14f0000002020ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID5_MBUF_TH" , 0x14f0000002028ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID6_MBUF_TH" , 0x14f0000002030ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID7_MBUF_TH" , 0x14f0000002038ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID8_MBUF_TH" , 0x14f0000002040ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID9_MBUF_TH" , 0x14f0000002048ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID10_MBUF_TH" , 0x14f0000002050ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID11_MBUF_TH" , 0x14f0000002058ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID12_MBUF_TH" , 0x14f0000002060ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID13_MBUF_TH" , 0x14f0000002068ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID14_MBUF_TH" , 0x14f0000002070ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID15_MBUF_TH" , 0x14f0000002078ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID16_MBUF_TH" , 0x14f0000002080ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID17_MBUF_TH" , 0x14f0000002088ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID18_MBUF_TH" , 0x14f0000002090ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID19_MBUF_TH" , 0x14f0000002098ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID20_MBUF_TH" , 0x14f00000020a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID21_MBUF_TH" , 0x14f00000020a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID22_MBUF_TH" , 0x14f00000020b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID23_MBUF_TH" , 0x14f00000020b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID24_MBUF_TH" , 0x14f00000020c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID25_MBUF_TH" , 0x14f00000020c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID26_MBUF_TH" , 0x14f00000020d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID27_MBUF_TH" , 0x14f00000020d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID28_MBUF_TH" , 0x14f00000020e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID29_MBUF_TH" , 0x14f00000020e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID30_MBUF_TH" , 0x14f00000020f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID31_MBUF_TH" , 0x14f00000020f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID32_MBUF_TH" , 0x14f0000002100ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID33_MBUF_TH" , 0x14f0000002108ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID34_MBUF_TH" , 0x14f0000002110ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID35_MBUF_TH" , 0x14f0000002118ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID36_MBUF_TH" , 0x14f0000002120ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID37_MBUF_TH" , 0x14f0000002128ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID38_MBUF_TH" , 0x14f0000002130ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID39_MBUF_TH" , 0x14f0000002138ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID40_MBUF_TH" , 0x14f0000002140ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID41_MBUF_TH" , 0x14f0000002148ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID42_MBUF_TH" , 0x14f0000002150ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID43_MBUF_TH" , 0x14f0000002158ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID44_MBUF_TH" , 0x14f0000002160ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID45_MBUF_TH" , 0x14f0000002168ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID46_MBUF_TH" , 0x14f0000002170ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID47_MBUF_TH" , 0x14f0000002178ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID48_MBUF_TH" , 0x14f0000002180ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID49_MBUF_TH" , 0x14f0000002188ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID50_MBUF_TH" , 0x14f0000002190ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID51_MBUF_TH" , 0x14f0000002198ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID52_MBUF_TH" , 0x14f00000021a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID53_MBUF_TH" , 0x14f00000021a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID54_MBUF_TH" , 0x14f00000021b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID55_MBUF_TH" , 0x14f00000021b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID56_MBUF_TH" , 0x14f00000021c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID57_MBUF_TH" , 0x14f00000021c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID58_MBUF_TH" , 0x14f00000021d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID59_MBUF_TH" , 0x14f00000021d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID60_MBUF_TH" , 0x14f00000021e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID61_MBUF_TH" , 0x14f00000021e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID62_MBUF_TH" , 0x14f00000021f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID63_MBUF_TH" , 0x14f00000021f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
- {"IPD_BPID_BP_COUNTER0" , 0x14f0000003000ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER1" , 0x14f0000003008ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER2" , 0x14f0000003010ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER3" , 0x14f0000003018ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER4" , 0x14f0000003020ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER5" , 0x14f0000003028ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER6" , 0x14f0000003030ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER7" , 0x14f0000003038ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER8" , 0x14f0000003040ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER9" , 0x14f0000003048ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER10" , 0x14f0000003050ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER11" , 0x14f0000003058ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER12" , 0x14f0000003060ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER13" , 0x14f0000003068ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER14" , 0x14f0000003070ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER15" , 0x14f0000003078ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER16" , 0x14f0000003080ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER17" , 0x14f0000003088ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER18" , 0x14f0000003090ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER19" , 0x14f0000003098ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER20" , 0x14f00000030a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER21" , 0x14f00000030a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER22" , 0x14f00000030b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER23" , 0x14f00000030b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER24" , 0x14f00000030c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER25" , 0x14f00000030c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER26" , 0x14f00000030d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER27" , 0x14f00000030d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER28" , 0x14f00000030e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER29" , 0x14f00000030e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER30" , 0x14f00000030f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER31" , 0x14f00000030f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER32" , 0x14f0000003100ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER33" , 0x14f0000003108ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER34" , 0x14f0000003110ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER35" , 0x14f0000003118ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER36" , 0x14f0000003120ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER37" , 0x14f0000003128ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER38" , 0x14f0000003130ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER39" , 0x14f0000003138ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER40" , 0x14f0000003140ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER41" , 0x14f0000003148ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER42" , 0x14f0000003150ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER43" , 0x14f0000003158ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER44" , 0x14f0000003160ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER45" , 0x14f0000003168ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER46" , 0x14f0000003170ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER47" , 0x14f0000003178ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER48" , 0x14f0000003180ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER49" , 0x14f0000003188ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER50" , 0x14f0000003190ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER51" , 0x14f0000003198ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER52" , 0x14f00000031a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER53" , 0x14f00000031a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER54" , 0x14f00000031b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER55" , 0x14f00000031b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER56" , 0x14f00000031c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER57" , 0x14f00000031c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER58" , 0x14f00000031d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER59" , 0x14f00000031d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER60" , 0x14f00000031e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER61" , 0x14f00000031e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER62" , 0x14f00000031f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_BPID_BP_COUNTER63" , 0x14f00000031f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 567},
- {"IPD_CREDITS" , 0x14f0000004410ull, CVMX_CSR_DB_TYPE_NCB, 64, 568},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 569},
- {"IPD_ECC_CTL" , 0x14f0000004408ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_FREE_PTR_FIFO_CTL" , 0x14f0000000780ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_FREE_PTR_VALUE" , 0x14f0000000788ull, CVMX_CSR_DB_TYPE_NCB, 64, 572},
- {"IPD_HOLD_PTR_FIFO_CTL" , 0x14f0000000790ull, CVMX_CSR_DB_TYPE_NCB, 64, 573},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 574},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"IPD_NEXT_PKT_PTR" , 0x14f00000007a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 576},
- {"IPD_NEXT_WQE_PTR" , 0x14f00000007a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 577},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 578},
- {"IPD_ON_BP_DROP_PKT0" , 0x14f0000004100ull, CVMX_CSR_DB_TYPE_NCB, 64, 579},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 580},
- {"IPD_PKT_ERR" , 0x14f00000003f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 581},
- {"IPD_PORT_PTR_FIFO_CTL" , 0x14f0000000798ull, CVMX_CSR_DB_TYPE_NCB, 64, 582},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_32_CNT" , 0x14f0000000988ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_33_CNT" , 0x14f0000000990ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_34_CNT" , 0x14f0000000998ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_35_CNT" , 0x14f00000009a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_36_CNT" , 0x14f00000009a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_37_CNT" , 0x14f00000009b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_38_CNT" , 0x14f00000009b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_39_CNT" , 0x14f00000009c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_40_CNT" , 0x14f00000009c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_41_CNT" , 0x14f00000009d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_42_CNT" , 0x14f00000009d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_43_CNT" , 0x14f00000009e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_44_CNT" , 0x14f00000009e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_45_CNT" , 0x14f00000009f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_46_CNT" , 0x14f00000009f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_47_CNT" , 0x14f0000000a00ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_48_CNT" , 0x14f0000000a08ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_49_CNT" , 0x14f0000000a10ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_50_CNT" , 0x14f0000000a18ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_51_CNT" , 0x14f0000000a20ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_52_CNT" , 0x14f0000000a28ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_53_CNT" , 0x14f0000000a30ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_54_CNT" , 0x14f0000000a38ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_55_CNT" , 0x14f0000000a40ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_56_CNT" , 0x14f0000000a48ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_57_CNT" , 0x14f0000000a50ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_58_CNT" , 0x14f0000000a58ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_59_CNT" , 0x14f0000000a60ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_60_CNT" , 0x14f0000000a68ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_61_CNT" , 0x14f0000000a70ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_62_CNT" , 0x14f0000000a78ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_63_CNT" , 0x14f0000000a80ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_64_CNT" , 0x14f0000000a88ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_65_CNT" , 0x14f0000000a90ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_66_CNT" , 0x14f0000000a98ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_67_CNT" , 0x14f0000000aa0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_68_CNT" , 0x14f0000000aa8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_69_CNT" , 0x14f0000000ab0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_70_CNT" , 0x14f0000000ab8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_71_CNT" , 0x14f0000000ac0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_72_CNT" , 0x14f0000000ac8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_73_CNT" , 0x14f0000000ad0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_74_CNT" , 0x14f0000000ad8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_75_CNT" , 0x14f0000000ae0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_76_CNT" , 0x14f0000000ae8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_77_CNT" , 0x14f0000000af0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_78_CNT" , 0x14f0000000af8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_79_CNT" , 0x14f0000000b00ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_80_CNT" , 0x14f0000000b08ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_81_CNT" , 0x14f0000000b10ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_82_CNT" , 0x14f0000000b18ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_83_CNT" , 0x14f0000000b20ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_84_CNT" , 0x14f0000000b28ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_85_CNT" , 0x14f0000000b30ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_86_CNT" , 0x14f0000000b38ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_87_CNT" , 0x14f0000000b40ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_88_CNT" , 0x14f0000000b48ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_89_CNT" , 0x14f0000000b50ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_90_CNT" , 0x14f0000000b58ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_91_CNT" , 0x14f0000000b60ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_92_CNT" , 0x14f0000000b68ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_93_CNT" , 0x14f0000000b70ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_94_CNT" , 0x14f0000000b78ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_95_CNT" , 0x14f0000000b80ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_96_CNT" , 0x14f0000000b88ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_97_CNT" , 0x14f0000000b90ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_98_CNT" , 0x14f0000000b98ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_99_CNT" , 0x14f0000000ba0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_100_CNT" , 0x14f0000000ba8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_101_CNT" , 0x14f0000000bb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_102_CNT" , 0x14f0000000bb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_103_CNT" , 0x14f0000000bc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_104_CNT" , 0x14f0000000bc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_105_CNT" , 0x14f0000000bd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_106_CNT" , 0x14f0000000bd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_107_CNT" , 0x14f0000000be0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_108_CNT" , 0x14f0000000be8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_109_CNT" , 0x14f0000000bf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_110_CNT" , 0x14f0000000bf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_111_CNT" , 0x14f0000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_112_CNT" , 0x14f0000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_113_CNT" , 0x14f0000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_114_CNT" , 0x14f0000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_115_CNT" , 0x14f0000000c20ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_116_CNT" , 0x14f0000000c28ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_117_CNT" , 0x14f0000000c30ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_118_CNT" , 0x14f0000000c38ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_119_CNT" , 0x14f0000000c40ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_120_CNT" , 0x14f0000000c48ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_121_CNT" , 0x14f0000000c50ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_122_CNT" , 0x14f0000000c58ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_123_CNT" , 0x14f0000000c60ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_124_CNT" , 0x14f0000000c68ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_125_CNT" , 0x14f0000000c70ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_126_CNT" , 0x14f0000000c78ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_127_CNT" , 0x14f0000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_128_CNT" , 0x14f0000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_129_CNT" , 0x14f0000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_130_CNT" , 0x14f0000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_131_CNT" , 0x14f0000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_132_CNT" , 0x14f0000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_133_CNT" , 0x14f0000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_134_CNT" , 0x14f0000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_135_CNT" , 0x14f0000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_136_CNT" , 0x14f0000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_137_CNT" , 0x14f0000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_138_CNT" , 0x14f0000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_139_CNT" , 0x14f0000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_140_CNT" , 0x14f0000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_141_CNT" , 0x14f0000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_142_CNT" , 0x14f0000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_143_CNT" , 0x14f0000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_144_CNT" , 0x14f0000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_145_CNT" , 0x14f0000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_146_CNT" , 0x14f0000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_147_CNT" , 0x14f0000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_148_CNT" , 0x14f0000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_149_CNT" , 0x14f0000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_150_CNT" , 0x14f0000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_151_CNT" , 0x14f0000000d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_152_CNT" , 0x14f0000000d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_153_CNT" , 0x14f0000000d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_154_CNT" , 0x14f0000000d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_155_CNT" , 0x14f0000000d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_156_CNT" , 0x14f0000000d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_157_CNT" , 0x14f0000000d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_158_CNT" , 0x14f0000000d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_159_CNT" , 0x14f0000000d80ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_160_CNT" , 0x14f0000000d88ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_161_CNT" , 0x14f0000000d90ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_162_CNT" , 0x14f0000000d98ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_163_CNT" , 0x14f0000000da0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_164_CNT" , 0x14f0000000da8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_165_CNT" , 0x14f0000000db0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_166_CNT" , 0x14f0000000db8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_167_CNT" , 0x14f0000000dc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_168_CNT" , 0x14f0000000dc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_169_CNT" , 0x14f0000000dd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_170_CNT" , 0x14f0000000dd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_171_CNT" , 0x14f0000000de0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_172_CNT" , 0x14f0000000de8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_173_CNT" , 0x14f0000000df0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_174_CNT" , 0x14f0000000df8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_175_CNT" , 0x14f0000000e00ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_176_CNT" , 0x14f0000000e08ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_177_CNT" , 0x14f0000000e10ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_178_CNT" , 0x14f0000000e18ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_179_CNT" , 0x14f0000000e20ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_180_CNT" , 0x14f0000000e28ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_181_CNT" , 0x14f0000000e30ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_182_CNT" , 0x14f0000000e38ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_183_CNT" , 0x14f0000000e40ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_184_CNT" , 0x14f0000000e48ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_185_CNT" , 0x14f0000000e50ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_186_CNT" , 0x14f0000000e58ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_187_CNT" , 0x14f0000000e60ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_188_CNT" , 0x14f0000000e68ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_189_CNT" , 0x14f0000000e70ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_190_CNT" , 0x14f0000000e78ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_191_CNT" , 0x14f0000000e80ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_192_CNT" , 0x14f0000000e88ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_193_CNT" , 0x14f0000000e90ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_194_CNT" , 0x14f0000000e98ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_195_CNT" , 0x14f0000000ea0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_196_CNT" , 0x14f0000000ea8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_197_CNT" , 0x14f0000000eb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_198_CNT" , 0x14f0000000eb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_199_CNT" , 0x14f0000000ec0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_200_CNT" , 0x14f0000000ec8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_201_CNT" , 0x14f0000000ed0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_202_CNT" , 0x14f0000000ed8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_203_CNT" , 0x14f0000000ee0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_204_CNT" , 0x14f0000000ee8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_205_CNT" , 0x14f0000000ef0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_206_CNT" , 0x14f0000000ef8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_207_CNT" , 0x14f0000000f00ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_208_CNT" , 0x14f0000000f08ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_209_CNT" , 0x14f0000000f10ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_210_CNT" , 0x14f0000000f18ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_211_CNT" , 0x14f0000000f20ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_212_CNT" , 0x14f0000000f28ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_213_CNT" , 0x14f0000000f30ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_214_CNT" , 0x14f0000000f38ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_215_CNT" , 0x14f0000000f40ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_216_CNT" , 0x14f0000000f48ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_217_CNT" , 0x14f0000000f50ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_218_CNT" , 0x14f0000000f58ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_219_CNT" , 0x14f0000000f60ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_220_CNT" , 0x14f0000000f68ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_221_CNT" , 0x14f0000000f70ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_222_CNT" , 0x14f0000000f78ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_223_CNT" , 0x14f0000000f80ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_224_CNT" , 0x14f0000000f88ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_225_CNT" , 0x14f0000000f90ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_226_CNT" , 0x14f0000000f98ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_227_CNT" , 0x14f0000000fa0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_228_CNT" , 0x14f0000000fa8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_229_CNT" , 0x14f0000000fb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_230_CNT" , 0x14f0000000fb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_231_CNT" , 0x14f0000000fc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_232_CNT" , 0x14f0000000fc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_233_CNT" , 0x14f0000000fd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_234_CNT" , 0x14f0000000fd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_235_CNT" , 0x14f0000000fe0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_236_CNT" , 0x14f0000000fe8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_237_CNT" , 0x14f0000000ff0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_238_CNT" , 0x14f0000000ff8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_239_CNT" , 0x14f0000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_240_CNT" , 0x14f0000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_241_CNT" , 0x14f0000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_242_CNT" , 0x14f0000001018ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_243_CNT" , 0x14f0000001020ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_244_CNT" , 0x14f0000001028ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_245_CNT" , 0x14f0000001030ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_246_CNT" , 0x14f0000001038ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_247_CNT" , 0x14f0000001040ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_248_CNT" , 0x14f0000001048ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_249_CNT" , 0x14f0000001050ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_250_CNT" , 0x14f0000001058ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_251_CNT" , 0x14f0000001060ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_252_CNT" , 0x14f0000001068ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_253_CNT" , 0x14f0000001070ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_254_CNT" , 0x14f0000001078ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_255_CNT" , 0x14f0000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_256_CNT" , 0x14f0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_257_CNT" , 0x14f0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_258_CNT" , 0x14f0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_259_CNT" , 0x14f00000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_260_CNT" , 0x14f00000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_261_CNT" , 0x14f00000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_262_CNT" , 0x14f00000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_263_CNT" , 0x14f00000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_264_CNT" , 0x14f00000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_265_CNT" , 0x14f00000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_266_CNT" , 0x14f00000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_267_CNT" , 0x14f00000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_268_CNT" , 0x14f00000010e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_269_CNT" , 0x14f00000010f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_270_CNT" , 0x14f00000010f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_271_CNT" , 0x14f0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_272_CNT" , 0x14f0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_273_CNT" , 0x14f0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_274_CNT" , 0x14f0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_275_CNT" , 0x14f0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_276_CNT" , 0x14f0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_277_CNT" , 0x14f0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_278_CNT" , 0x14f0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_279_CNT" , 0x14f0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_280_CNT" , 0x14f0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_281_CNT" , 0x14f0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_282_CNT" , 0x14f0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_283_CNT" , 0x14f0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_284_CNT" , 0x14f0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_285_CNT" , 0x14f0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_286_CNT" , 0x14f0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_287_CNT" , 0x14f0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_320_CNT" , 0x14f0000001288ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_321_CNT" , 0x14f0000001290ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_322_CNT" , 0x14f0000001298ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_323_CNT" , 0x14f00000012a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_324_CNT" , 0x14f00000012a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_325_CNT" , 0x14f00000012b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_326_CNT" , 0x14f00000012b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_327_CNT" , 0x14f00000012c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_328_CNT" , 0x14f00000012c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_329_CNT" , 0x14f00000012d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_330_CNT" , 0x14f00000012d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_331_CNT" , 0x14f00000012e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_332_CNT" , 0x14f00000012e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_333_CNT" , 0x14f00000012f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_334_CNT" , 0x14f00000012f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_335_CNT" , 0x14f0000001300ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_336_CNT" , 0x14f0000001308ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_337_CNT" , 0x14f0000001310ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_338_CNT" , 0x14f0000001318ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_339_CNT" , 0x14f0000001320ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_340_CNT" , 0x14f0000001328ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_341_CNT" , 0x14f0000001330ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_342_CNT" , 0x14f0000001338ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_343_CNT" , 0x14f0000001340ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_344_CNT" , 0x14f0000001348ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_345_CNT" , 0x14f0000001350ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_346_CNT" , 0x14f0000001358ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_347_CNT" , 0x14f0000001360ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_348_CNT" , 0x14f0000001368ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_349_CNT" , 0x14f0000001370ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_350_CNT" , 0x14f0000001378ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_351_CNT" , 0x14f0000001380ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_352_CNT" , 0x14f0000001388ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_353_CNT" , 0x14f0000001390ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_354_CNT" , 0x14f0000001398ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_355_CNT" , 0x14f00000013a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_356_CNT" , 0x14f00000013a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_357_CNT" , 0x14f00000013b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_358_CNT" , 0x14f00000013b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_359_CNT" , 0x14f00000013c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_360_CNT" , 0x14f00000013c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_361_CNT" , 0x14f00000013d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_362_CNT" , 0x14f00000013d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_363_CNT" , 0x14f00000013e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_364_CNT" , 0x14f00000013e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_365_CNT" , 0x14f00000013f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_366_CNT" , 0x14f00000013f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_367_CNT" , 0x14f0000001400ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_368_CNT" , 0x14f0000001408ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_369_CNT" , 0x14f0000001410ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_370_CNT" , 0x14f0000001418ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_371_CNT" , 0x14f0000001420ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_372_CNT" , 0x14f0000001428ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_373_CNT" , 0x14f0000001430ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_374_CNT" , 0x14f0000001438ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_375_CNT" , 0x14f0000001440ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_376_CNT" , 0x14f0000001448ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_377_CNT" , 0x14f0000001450ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_378_CNT" , 0x14f0000001458ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_379_CNT" , 0x14f0000001460ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_380_CNT" , 0x14f0000001468ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_381_CNT" , 0x14f0000001470ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_382_CNT" , 0x14f0000001478ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_383_CNT" , 0x14f0000001480ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_384_CNT" , 0x14f0000001488ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_385_CNT" , 0x14f0000001490ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_386_CNT" , 0x14f0000001498ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_387_CNT" , 0x14f00000014a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_388_CNT" , 0x14f00000014a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_389_CNT" , 0x14f00000014b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_390_CNT" , 0x14f00000014b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_391_CNT" , 0x14f00000014c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_392_CNT" , 0x14f00000014c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_393_CNT" , 0x14f00000014d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_394_CNT" , 0x14f00000014d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_395_CNT" , 0x14f00000014e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_396_CNT" , 0x14f00000014e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_397_CNT" , 0x14f00000014f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_398_CNT" , 0x14f00000014f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_399_CNT" , 0x14f0000001500ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_400_CNT" , 0x14f0000001508ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_401_CNT" , 0x14f0000001510ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_402_CNT" , 0x14f0000001518ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_403_CNT" , 0x14f0000001520ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_404_CNT" , 0x14f0000001528ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_405_CNT" , 0x14f0000001530ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_406_CNT" , 0x14f0000001538ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_407_CNT" , 0x14f0000001540ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_408_CNT" , 0x14f0000001548ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_409_CNT" , 0x14f0000001550ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_410_CNT" , 0x14f0000001558ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_411_CNT" , 0x14f0000001560ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_412_CNT" , 0x14f0000001568ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_413_CNT" , 0x14f0000001570ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_414_CNT" , 0x14f0000001578ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_415_CNT" , 0x14f0000001580ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_416_CNT" , 0x14f0000001588ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_417_CNT" , 0x14f0000001590ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_418_CNT" , 0x14f0000001598ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_419_CNT" , 0x14f00000015a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_420_CNT" , 0x14f00000015a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_421_CNT" , 0x14f00000015b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_422_CNT" , 0x14f00000015b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_423_CNT" , 0x14f00000015c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_424_CNT" , 0x14f00000015c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_425_CNT" , 0x14f00000015d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_426_CNT" , 0x14f00000015d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_427_CNT" , 0x14f00000015e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_428_CNT" , 0x14f00000015e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_429_CNT" , 0x14f00000015f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_430_CNT" , 0x14f00000015f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_431_CNT" , 0x14f0000001600ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_432_CNT" , 0x14f0000001608ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_433_CNT" , 0x14f0000001610ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_434_CNT" , 0x14f0000001618ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_435_CNT" , 0x14f0000001620ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_436_CNT" , 0x14f0000001628ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_437_CNT" , 0x14f0000001630ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_438_CNT" , 0x14f0000001638ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_439_CNT" , 0x14f0000001640ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_440_CNT" , 0x14f0000001648ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_441_CNT" , 0x14f0000001650ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_442_CNT" , 0x14f0000001658ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_443_CNT" , 0x14f0000001660ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_444_CNT" , 0x14f0000001668ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_445_CNT" , 0x14f0000001670ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_446_CNT" , 0x14f0000001678ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_447_CNT" , 0x14f0000001680ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_448_CNT" , 0x14f0000001688ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_449_CNT" , 0x14f0000001690ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_450_CNT" , 0x14f0000001698ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_451_CNT" , 0x14f00000016a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_452_CNT" , 0x14f00000016a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_453_CNT" , 0x14f00000016b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_454_CNT" , 0x14f00000016b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_455_CNT" , 0x14f00000016c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_456_CNT" , 0x14f00000016c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_457_CNT" , 0x14f00000016d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_458_CNT" , 0x14f00000016d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_459_CNT" , 0x14f00000016e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_460_CNT" , 0x14f00000016e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_461_CNT" , 0x14f00000016f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_462_CNT" , 0x14f00000016f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_463_CNT" , 0x14f0000001700ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_464_CNT" , 0x14f0000001708ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_465_CNT" , 0x14f0000001710ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_466_CNT" , 0x14f0000001718ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_467_CNT" , 0x14f0000001720ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_468_CNT" , 0x14f0000001728ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_469_CNT" , 0x14f0000001730ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_470_CNT" , 0x14f0000001738ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_471_CNT" , 0x14f0000001740ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_472_CNT" , 0x14f0000001748ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_473_CNT" , 0x14f0000001750ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_474_CNT" , 0x14f0000001758ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_475_CNT" , 0x14f0000001760ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_476_CNT" , 0x14f0000001768ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_477_CNT" , 0x14f0000001770ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_478_CNT" , 0x14f0000001778ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_479_CNT" , 0x14f0000001780ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_480_CNT" , 0x14f0000001788ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_481_CNT" , 0x14f0000001790ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_482_CNT" , 0x14f0000001798ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_483_CNT" , 0x14f00000017a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_484_CNT" , 0x14f00000017a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_485_CNT" , 0x14f00000017b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_486_CNT" , 0x14f00000017b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_487_CNT" , 0x14f00000017c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_488_CNT" , 0x14f00000017c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_489_CNT" , 0x14f00000017d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_490_CNT" , 0x14f00000017d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_491_CNT" , 0x14f00000017e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_492_CNT" , 0x14f00000017e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_493_CNT" , 0x14f00000017f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_494_CNT" , 0x14f00000017f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_495_CNT" , 0x14f0000001800ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_496_CNT" , 0x14f0000001808ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_497_CNT" , 0x14f0000001810ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_498_CNT" , 0x14f0000001818ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_499_CNT" , 0x14f0000001820ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_500_CNT" , 0x14f0000001828ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_501_CNT" , 0x14f0000001830ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_502_CNT" , 0x14f0000001838ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_503_CNT" , 0x14f0000001840ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_504_CNT" , 0x14f0000001848ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_505_CNT" , 0x14f0000001850ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_506_CNT" , 0x14f0000001858ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_507_CNT" , 0x14f0000001860ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_508_CNT" , 0x14f0000001868ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_509_CNT" , 0x14f0000001870ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_510_CNT" , 0x14f0000001878ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_511_CNT" , 0x14f0000001880ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"IPD_PORT_QOS_INT1" , 0x14f0000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"IPD_PORT_QOS_INT2" , 0x14f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"IPD_PORT_QOS_INT3" , 0x14f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"IPD_PORT_QOS_INT5" , 0x14f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"IPD_PORT_QOS_INT6" , 0x14f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"IPD_PORT_QOS_INT7" , 0x14f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"IPD_PORT_QOS_INT_ENB1" , 0x14f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"IPD_PORT_QOS_INT_ENB2" , 0x14f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"IPD_PORT_QOS_INT_ENB3" , 0x14f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"IPD_PORT_QOS_INT_ENB5" , 0x14f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"IPD_PORT_QOS_INT_ENB6" , 0x14f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"IPD_PORT_QOS_INT_ENB7" , 0x14f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"IPD_PORT_SOP0" , 0x14f0000004400ull, CVMX_CSR_DB_TYPE_NCB, 64, 586},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 587},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"IPD_RED_BPID_ENABLE0" , 0x14f0000004200ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"IPD_RED_DELAY" , 0x14f0000004300ull, CVMX_CSR_DB_TYPE_NCB, 64, 591},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 595},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 596},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 597},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 598},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 599},
- {"L2C_BIG_CTL" , 0x1180080800030ull, CVMX_CSR_DB_TYPE_RSL, 64, 600},
- {"L2C_BST" , 0x11800808007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 601},
- {"L2C_BST_MEM0" , 0x1180080c007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
- {"L2C_BST_MEM1" , 0x1180080c407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
- {"L2C_BST_MEM2" , 0x1180080c807f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
- {"L2C_BST_MEM3" , 0x1180080cc07f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
- {"L2C_BST_TDT0" , 0x1180080a007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
- {"L2C_BST_TDT1" , 0x1180080a407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
- {"L2C_BST_TDT2" , 0x1180080a807f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
- {"L2C_BST_TDT3" , 0x1180080ac07f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
- {"L2C_BST_TTG0" , 0x1180080a007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
- {"L2C_BST_TTG1" , 0x1180080a407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
- {"L2C_BST_TTG2" , 0x1180080a807f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
- {"L2C_BST_TTG3" , 0x1180080ac07f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
- {"L2C_COP0_MAP0" , 0x1180080940000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1" , 0x1180080940008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2" , 0x1180080940010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3" , 0x1180080940018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4" , 0x1180080940020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5" , 0x1180080940028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6" , 0x1180080940030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7" , 0x1180080940038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8" , 0x1180080940040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP9" , 0x1180080940048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP10" , 0x1180080940050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP11" , 0x1180080940058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP12" , 0x1180080940060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP13" , 0x1180080940068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP14" , 0x1180080940070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP15" , 0x1180080940078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16" , 0x1180080940080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP17" , 0x1180080940088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP18" , 0x1180080940090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP19" , 0x1180080940098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP20" , 0x11800809400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP21" , 0x11800809400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP22" , 0x11800809400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP23" , 0x11800809400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP24" , 0x11800809400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP25" , 0x11800809400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP26" , 0x11800809400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP27" , 0x11800809400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP28" , 0x11800809400e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP29" , 0x11800809400e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP30" , 0x11800809400f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP31" , 0x11800809400f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP32" , 0x1180080940100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP33" , 0x1180080940108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP34" , 0x1180080940110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP35" , 0x1180080940118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP36" , 0x1180080940120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP37" , 0x1180080940128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP38" , 0x1180080940130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP39" , 0x1180080940138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP40" , 0x1180080940140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP41" , 0x1180080940148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP42" , 0x1180080940150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP43" , 0x1180080940158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP44" , 0x1180080940160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP45" , 0x1180080940168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP46" , 0x1180080940170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP47" , 0x1180080940178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP48" , 0x1180080940180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP49" , 0x1180080940188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP50" , 0x1180080940190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP51" , 0x1180080940198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP52" , 0x11800809401a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP53" , 0x11800809401a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP54" , 0x11800809401b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP55" , 0x11800809401b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP56" , 0x11800809401c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP57" , 0x11800809401c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP58" , 0x11800809401d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP59" , 0x11800809401d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP60" , 0x11800809401e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP61" , 0x11800809401e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP62" , 0x11800809401f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP63" , 0x11800809401f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP64" , 0x1180080940200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP65" , 0x1180080940208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP66" , 0x1180080940210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP67" , 0x1180080940218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP68" , 0x1180080940220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP69" , 0x1180080940228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP70" , 0x1180080940230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP71" , 0x1180080940238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP72" , 0x1180080940240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP73" , 0x1180080940248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP74" , 0x1180080940250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP75" , 0x1180080940258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP76" , 0x1180080940260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP77" , 0x1180080940268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP78" , 0x1180080940270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP79" , 0x1180080940278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP80" , 0x1180080940280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP81" , 0x1180080940288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP82" , 0x1180080940290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP83" , 0x1180080940298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP84" , 0x11800809402a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP85" , 0x11800809402a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP86" , 0x11800809402b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP87" , 0x11800809402b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP88" , 0x11800809402c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP89" , 0x11800809402c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP90" , 0x11800809402d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP91" , 0x11800809402d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP92" , 0x11800809402e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP93" , 0x11800809402e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP94" , 0x11800809402f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP95" , 0x11800809402f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP96" , 0x1180080940300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP97" , 0x1180080940308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP98" , 0x1180080940310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP99" , 0x1180080940318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP100" , 0x1180080940320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP101" , 0x1180080940328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP102" , 0x1180080940330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP103" , 0x1180080940338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP104" , 0x1180080940340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP105" , 0x1180080940348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP106" , 0x1180080940350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP107" , 0x1180080940358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP108" , 0x1180080940360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP109" , 0x1180080940368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP110" , 0x1180080940370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP111" , 0x1180080940378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP112" , 0x1180080940380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP113" , 0x1180080940388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP114" , 0x1180080940390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP115" , 0x1180080940398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP116" , 0x11800809403a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP117" , 0x11800809403a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP118" , 0x11800809403b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP119" , 0x11800809403b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP120" , 0x11800809403c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP121" , 0x11800809403c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP122" , 0x11800809403d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP123" , 0x11800809403d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP124" , 0x11800809403e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP125" , 0x11800809403e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP126" , 0x11800809403f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP127" , 0x11800809403f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP128" , 0x1180080940400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP129" , 0x1180080940408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP130" , 0x1180080940410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP131" , 0x1180080940418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP132" , 0x1180080940420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP133" , 0x1180080940428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP134" , 0x1180080940430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP135" , 0x1180080940438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP136" , 0x1180080940440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP137" , 0x1180080940448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP138" , 0x1180080940450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP139" , 0x1180080940458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP140" , 0x1180080940460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP141" , 0x1180080940468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP142" , 0x1180080940470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP143" , 0x1180080940478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP144" , 0x1180080940480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP145" , 0x1180080940488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP146" , 0x1180080940490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP147" , 0x1180080940498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP148" , 0x11800809404a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP149" , 0x11800809404a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP150" , 0x11800809404b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP151" , 0x11800809404b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP152" , 0x11800809404c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP153" , 0x11800809404c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP154" , 0x11800809404d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP155" , 0x11800809404d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP156" , 0x11800809404e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP157" , 0x11800809404e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP158" , 0x11800809404f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP159" , 0x11800809404f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP160" , 0x1180080940500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP161" , 0x1180080940508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP162" , 0x1180080940510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP163" , 0x1180080940518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP164" , 0x1180080940520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP165" , 0x1180080940528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP166" , 0x1180080940530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP167" , 0x1180080940538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP168" , 0x1180080940540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP169" , 0x1180080940548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP170" , 0x1180080940550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP171" , 0x1180080940558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP172" , 0x1180080940560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP173" , 0x1180080940568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP174" , 0x1180080940570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP175" , 0x1180080940578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP176" , 0x1180080940580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP177" , 0x1180080940588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP178" , 0x1180080940590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP179" , 0x1180080940598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP180" , 0x11800809405a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP181" , 0x11800809405a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP182" , 0x11800809405b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP183" , 0x11800809405b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP184" , 0x11800809405c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP185" , 0x11800809405c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP186" , 0x11800809405d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP187" , 0x11800809405d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP188" , 0x11800809405e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP189" , 0x11800809405e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP190" , 0x11800809405f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP191" , 0x11800809405f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP192" , 0x1180080940600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP193" , 0x1180080940608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP194" , 0x1180080940610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP195" , 0x1180080940618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP196" , 0x1180080940620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP197" , 0x1180080940628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP198" , 0x1180080940630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP199" , 0x1180080940638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP200" , 0x1180080940640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP201" , 0x1180080940648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP202" , 0x1180080940650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP203" , 0x1180080940658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP204" , 0x1180080940660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP205" , 0x1180080940668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP206" , 0x1180080940670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP207" , 0x1180080940678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP208" , 0x1180080940680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP209" , 0x1180080940688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP210" , 0x1180080940690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP211" , 0x1180080940698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP212" , 0x11800809406a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP213" , 0x11800809406a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP214" , 0x11800809406b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP215" , 0x11800809406b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP216" , 0x11800809406c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP217" , 0x11800809406c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP218" , 0x11800809406d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP219" , 0x11800809406d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP220" , 0x11800809406e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP221" , 0x11800809406e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP222" , 0x11800809406f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP223" , 0x11800809406f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP224" , 0x1180080940700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP225" , 0x1180080940708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP226" , 0x1180080940710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP227" , 0x1180080940718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP228" , 0x1180080940720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP229" , 0x1180080940728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP230" , 0x1180080940730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP231" , 0x1180080940738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP232" , 0x1180080940740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP233" , 0x1180080940748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP234" , 0x1180080940750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP235" , 0x1180080940758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP236" , 0x1180080940760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP237" , 0x1180080940768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP238" , 0x1180080940770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP239" , 0x1180080940778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP240" , 0x1180080940780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP241" , 0x1180080940788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP242" , 0x1180080940790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP243" , 0x1180080940798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP244" , 0x11800809407a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP245" , 0x11800809407a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP246" , 0x11800809407b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP247" , 0x11800809407b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP248" , 0x11800809407c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP249" , 0x11800809407c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP250" , 0x11800809407d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP251" , 0x11800809407d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP252" , 0x11800809407e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP253" , 0x11800809407e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP254" , 0x11800809407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP255" , 0x11800809407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP256" , 0x1180080940800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP257" , 0x1180080940808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP258" , 0x1180080940810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP259" , 0x1180080940818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP260" , 0x1180080940820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP261" , 0x1180080940828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP262" , 0x1180080940830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP263" , 0x1180080940838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP264" , 0x1180080940840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP265" , 0x1180080940848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP266" , 0x1180080940850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP267" , 0x1180080940858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP268" , 0x1180080940860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP269" , 0x1180080940868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP270" , 0x1180080940870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP271" , 0x1180080940878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP272" , 0x1180080940880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP273" , 0x1180080940888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP274" , 0x1180080940890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP275" , 0x1180080940898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP276" , 0x11800809408a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP277" , 0x11800809408a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP278" , 0x11800809408b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP279" , 0x11800809408b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP280" , 0x11800809408c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP281" , 0x11800809408c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP282" , 0x11800809408d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP283" , 0x11800809408d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP284" , 0x11800809408e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP285" , 0x11800809408e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP286" , 0x11800809408f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP287" , 0x11800809408f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP288" , 0x1180080940900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP289" , 0x1180080940908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP290" , 0x1180080940910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP291" , 0x1180080940918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP292" , 0x1180080940920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP293" , 0x1180080940928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP294" , 0x1180080940930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP295" , 0x1180080940938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP296" , 0x1180080940940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP297" , 0x1180080940948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP298" , 0x1180080940950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP299" , 0x1180080940958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP300" , 0x1180080940960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP301" , 0x1180080940968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP302" , 0x1180080940970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP303" , 0x1180080940978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP304" , 0x1180080940980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP305" , 0x1180080940988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP306" , 0x1180080940990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP307" , 0x1180080940998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP308" , 0x11800809409a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP309" , 0x11800809409a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP310" , 0x11800809409b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP311" , 0x11800809409b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP312" , 0x11800809409c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP313" , 0x11800809409c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP314" , 0x11800809409d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP315" , 0x11800809409d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP316" , 0x11800809409e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP317" , 0x11800809409e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP318" , 0x11800809409f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP319" , 0x11800809409f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP320" , 0x1180080940a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP321" , 0x1180080940a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP322" , 0x1180080940a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP323" , 0x1180080940a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP324" , 0x1180080940a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP325" , 0x1180080940a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP326" , 0x1180080940a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP327" , 0x1180080940a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP328" , 0x1180080940a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP329" , 0x1180080940a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP330" , 0x1180080940a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP331" , 0x1180080940a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP332" , 0x1180080940a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP333" , 0x1180080940a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP334" , 0x1180080940a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP335" , 0x1180080940a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP336" , 0x1180080940a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP337" , 0x1180080940a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP338" , 0x1180080940a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP339" , 0x1180080940a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP340" , 0x1180080940aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP341" , 0x1180080940aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP342" , 0x1180080940ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP343" , 0x1180080940ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP344" , 0x1180080940ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP345" , 0x1180080940ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP346" , 0x1180080940ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP347" , 0x1180080940ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP348" , 0x1180080940ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP349" , 0x1180080940ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP350" , 0x1180080940af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP351" , 0x1180080940af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP352" , 0x1180080940b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP353" , 0x1180080940b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP354" , 0x1180080940b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP355" , 0x1180080940b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP356" , 0x1180080940b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP357" , 0x1180080940b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP358" , 0x1180080940b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP359" , 0x1180080940b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP360" , 0x1180080940b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP361" , 0x1180080940b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP362" , 0x1180080940b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP363" , 0x1180080940b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP364" , 0x1180080940b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP365" , 0x1180080940b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP366" , 0x1180080940b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP367" , 0x1180080940b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP368" , 0x1180080940b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP369" , 0x1180080940b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP370" , 0x1180080940b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP371" , 0x1180080940b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP372" , 0x1180080940ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP373" , 0x1180080940ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP374" , 0x1180080940bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP375" , 0x1180080940bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP376" , 0x1180080940bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP377" , 0x1180080940bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP378" , 0x1180080940bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP379" , 0x1180080940bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP380" , 0x1180080940be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP381" , 0x1180080940be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP382" , 0x1180080940bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP383" , 0x1180080940bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP384" , 0x1180080940c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP385" , 0x1180080940c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP386" , 0x1180080940c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP387" , 0x1180080940c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP388" , 0x1180080940c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP389" , 0x1180080940c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP390" , 0x1180080940c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP391" , 0x1180080940c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP392" , 0x1180080940c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP393" , 0x1180080940c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP394" , 0x1180080940c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP395" , 0x1180080940c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP396" , 0x1180080940c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP397" , 0x1180080940c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP398" , 0x1180080940c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP399" , 0x1180080940c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP400" , 0x1180080940c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP401" , 0x1180080940c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP402" , 0x1180080940c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP403" , 0x1180080940c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP404" , 0x1180080940ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP405" , 0x1180080940ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP406" , 0x1180080940cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP407" , 0x1180080940cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP408" , 0x1180080940cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP409" , 0x1180080940cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP410" , 0x1180080940cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP411" , 0x1180080940cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP412" , 0x1180080940ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP413" , 0x1180080940ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP414" , 0x1180080940cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP415" , 0x1180080940cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP416" , 0x1180080940d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP417" , 0x1180080940d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP418" , 0x1180080940d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP419" , 0x1180080940d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP420" , 0x1180080940d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP421" , 0x1180080940d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP422" , 0x1180080940d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP423" , 0x1180080940d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP424" , 0x1180080940d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP425" , 0x1180080940d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP426" , 0x1180080940d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP427" , 0x1180080940d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP428" , 0x1180080940d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP429" , 0x1180080940d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP430" , 0x1180080940d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP431" , 0x1180080940d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP432" , 0x1180080940d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP433" , 0x1180080940d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP434" , 0x1180080940d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP435" , 0x1180080940d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP436" , 0x1180080940da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP437" , 0x1180080940da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP438" , 0x1180080940db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP439" , 0x1180080940db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP440" , 0x1180080940dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP441" , 0x1180080940dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP442" , 0x1180080940dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP443" , 0x1180080940dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP444" , 0x1180080940de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP445" , 0x1180080940de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP446" , 0x1180080940df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP447" , 0x1180080940df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP448" , 0x1180080940e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP449" , 0x1180080940e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP450" , 0x1180080940e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP451" , 0x1180080940e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP452" , 0x1180080940e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP453" , 0x1180080940e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP454" , 0x1180080940e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP455" , 0x1180080940e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP456" , 0x1180080940e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP457" , 0x1180080940e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP458" , 0x1180080940e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP459" , 0x1180080940e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP460" , 0x1180080940e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP461" , 0x1180080940e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP462" , 0x1180080940e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP463" , 0x1180080940e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP464" , 0x1180080940e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP465" , 0x1180080940e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP466" , 0x1180080940e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP467" , 0x1180080940e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP468" , 0x1180080940ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP469" , 0x1180080940ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP470" , 0x1180080940eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP471" , 0x1180080940eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP472" , 0x1180080940ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP473" , 0x1180080940ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP474" , 0x1180080940ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP475" , 0x1180080940ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP476" , 0x1180080940ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP477" , 0x1180080940ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP478" , 0x1180080940ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP479" , 0x1180080940ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP480" , 0x1180080940f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP481" , 0x1180080940f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP482" , 0x1180080940f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP483" , 0x1180080940f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP484" , 0x1180080940f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP485" , 0x1180080940f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP486" , 0x1180080940f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP487" , 0x1180080940f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP488" , 0x1180080940f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP489" , 0x1180080940f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP490" , 0x1180080940f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP491" , 0x1180080940f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP492" , 0x1180080940f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP493" , 0x1180080940f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP494" , 0x1180080940f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP495" , 0x1180080940f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP496" , 0x1180080940f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP497" , 0x1180080940f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP498" , 0x1180080940f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP499" , 0x1180080940f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP500" , 0x1180080940fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP501" , 0x1180080940fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP502" , 0x1180080940fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP503" , 0x1180080940fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP504" , 0x1180080940fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP505" , 0x1180080940fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP506" , 0x1180080940fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP507" , 0x1180080940fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP508" , 0x1180080940fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP509" , 0x1180080940fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP510" , 0x1180080940ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP511" , 0x1180080940ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP512" , 0x1180080941000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP513" , 0x1180080941008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP514" , 0x1180080941010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP515" , 0x1180080941018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP516" , 0x1180080941020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP517" , 0x1180080941028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP518" , 0x1180080941030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP519" , 0x1180080941038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP520" , 0x1180080941040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP521" , 0x1180080941048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP522" , 0x1180080941050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP523" , 0x1180080941058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP524" , 0x1180080941060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP525" , 0x1180080941068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP526" , 0x1180080941070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP527" , 0x1180080941078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP528" , 0x1180080941080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP529" , 0x1180080941088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP530" , 0x1180080941090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP531" , 0x1180080941098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP532" , 0x11800809410a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP533" , 0x11800809410a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP534" , 0x11800809410b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP535" , 0x11800809410b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP536" , 0x11800809410c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP537" , 0x11800809410c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP538" , 0x11800809410d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP539" , 0x11800809410d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP540" , 0x11800809410e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP541" , 0x11800809410e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP542" , 0x11800809410f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP543" , 0x11800809410f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP544" , 0x1180080941100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP545" , 0x1180080941108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP546" , 0x1180080941110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP547" , 0x1180080941118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP548" , 0x1180080941120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP549" , 0x1180080941128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP550" , 0x1180080941130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP551" , 0x1180080941138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP552" , 0x1180080941140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP553" , 0x1180080941148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP554" , 0x1180080941150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP555" , 0x1180080941158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP556" , 0x1180080941160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP557" , 0x1180080941168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP558" , 0x1180080941170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP559" , 0x1180080941178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP560" , 0x1180080941180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP561" , 0x1180080941188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP562" , 0x1180080941190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP563" , 0x1180080941198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP564" , 0x11800809411a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP565" , 0x11800809411a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP566" , 0x11800809411b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP567" , 0x11800809411b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP568" , 0x11800809411c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP569" , 0x11800809411c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP570" , 0x11800809411d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP571" , 0x11800809411d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP572" , 0x11800809411e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP573" , 0x11800809411e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP574" , 0x11800809411f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP575" , 0x11800809411f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP576" , 0x1180080941200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP577" , 0x1180080941208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP578" , 0x1180080941210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP579" , 0x1180080941218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP580" , 0x1180080941220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP581" , 0x1180080941228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP582" , 0x1180080941230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP583" , 0x1180080941238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP584" , 0x1180080941240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP585" , 0x1180080941248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP586" , 0x1180080941250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP587" , 0x1180080941258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP588" , 0x1180080941260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP589" , 0x1180080941268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP590" , 0x1180080941270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP591" , 0x1180080941278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP592" , 0x1180080941280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP593" , 0x1180080941288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP594" , 0x1180080941290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP595" , 0x1180080941298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP596" , 0x11800809412a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP597" , 0x11800809412a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP598" , 0x11800809412b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP599" , 0x11800809412b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP600" , 0x11800809412c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP601" , 0x11800809412c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP602" , 0x11800809412d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP603" , 0x11800809412d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP604" , 0x11800809412e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP605" , 0x11800809412e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP606" , 0x11800809412f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP607" , 0x11800809412f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP608" , 0x1180080941300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP609" , 0x1180080941308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP610" , 0x1180080941310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP611" , 0x1180080941318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP612" , 0x1180080941320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP613" , 0x1180080941328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP614" , 0x1180080941330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP615" , 0x1180080941338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP616" , 0x1180080941340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP617" , 0x1180080941348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP618" , 0x1180080941350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP619" , 0x1180080941358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP620" , 0x1180080941360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP621" , 0x1180080941368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP622" , 0x1180080941370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP623" , 0x1180080941378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP624" , 0x1180080941380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP625" , 0x1180080941388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP626" , 0x1180080941390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP627" , 0x1180080941398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP628" , 0x11800809413a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP629" , 0x11800809413a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP630" , 0x11800809413b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP631" , 0x11800809413b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP632" , 0x11800809413c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP633" , 0x11800809413c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP634" , 0x11800809413d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP635" , 0x11800809413d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP636" , 0x11800809413e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP637" , 0x11800809413e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP638" , 0x11800809413f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP639" , 0x11800809413f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP640" , 0x1180080941400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP641" , 0x1180080941408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP642" , 0x1180080941410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP643" , 0x1180080941418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP644" , 0x1180080941420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP645" , 0x1180080941428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP646" , 0x1180080941430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP647" , 0x1180080941438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP648" , 0x1180080941440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP649" , 0x1180080941448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP650" , 0x1180080941450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP651" , 0x1180080941458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP652" , 0x1180080941460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP653" , 0x1180080941468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP654" , 0x1180080941470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP655" , 0x1180080941478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP656" , 0x1180080941480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP657" , 0x1180080941488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP658" , 0x1180080941490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP659" , 0x1180080941498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP660" , 0x11800809414a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP661" , 0x11800809414a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP662" , 0x11800809414b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP663" , 0x11800809414b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP664" , 0x11800809414c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP665" , 0x11800809414c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP666" , 0x11800809414d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP667" , 0x11800809414d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP668" , 0x11800809414e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP669" , 0x11800809414e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP670" , 0x11800809414f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP671" , 0x11800809414f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP672" , 0x1180080941500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP673" , 0x1180080941508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP674" , 0x1180080941510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP675" , 0x1180080941518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP676" , 0x1180080941520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP677" , 0x1180080941528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP678" , 0x1180080941530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP679" , 0x1180080941538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP680" , 0x1180080941540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP681" , 0x1180080941548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP682" , 0x1180080941550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP683" , 0x1180080941558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP684" , 0x1180080941560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP685" , 0x1180080941568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP686" , 0x1180080941570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP687" , 0x1180080941578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP688" , 0x1180080941580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP689" , 0x1180080941588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP690" , 0x1180080941590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP691" , 0x1180080941598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP692" , 0x11800809415a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP693" , 0x11800809415a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP694" , 0x11800809415b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP695" , 0x11800809415b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP696" , 0x11800809415c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP697" , 0x11800809415c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP698" , 0x11800809415d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP699" , 0x11800809415d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP700" , 0x11800809415e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP701" , 0x11800809415e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP702" , 0x11800809415f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP703" , 0x11800809415f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP704" , 0x1180080941600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP705" , 0x1180080941608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP706" , 0x1180080941610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP707" , 0x1180080941618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP708" , 0x1180080941620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP709" , 0x1180080941628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP710" , 0x1180080941630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP711" , 0x1180080941638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP712" , 0x1180080941640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP713" , 0x1180080941648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP714" , 0x1180080941650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP715" , 0x1180080941658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP716" , 0x1180080941660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP717" , 0x1180080941668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP718" , 0x1180080941670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP719" , 0x1180080941678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP720" , 0x1180080941680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP721" , 0x1180080941688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP722" , 0x1180080941690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP723" , 0x1180080941698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP724" , 0x11800809416a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP725" , 0x11800809416a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP726" , 0x11800809416b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP727" , 0x11800809416b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP728" , 0x11800809416c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP729" , 0x11800809416c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP730" , 0x11800809416d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP731" , 0x11800809416d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP732" , 0x11800809416e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP733" , 0x11800809416e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP734" , 0x11800809416f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP735" , 0x11800809416f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP736" , 0x1180080941700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP737" , 0x1180080941708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP738" , 0x1180080941710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP739" , 0x1180080941718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP740" , 0x1180080941720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP741" , 0x1180080941728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP742" , 0x1180080941730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP743" , 0x1180080941738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP744" , 0x1180080941740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP745" , 0x1180080941748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP746" , 0x1180080941750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP747" , 0x1180080941758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP748" , 0x1180080941760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP749" , 0x1180080941768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP750" , 0x1180080941770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP751" , 0x1180080941778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP752" , 0x1180080941780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP753" , 0x1180080941788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP754" , 0x1180080941790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP755" , 0x1180080941798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP756" , 0x11800809417a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP757" , 0x11800809417a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP758" , 0x11800809417b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP759" , 0x11800809417b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP760" , 0x11800809417c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP761" , 0x11800809417c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP762" , 0x11800809417d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP763" , 0x11800809417d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP764" , 0x11800809417e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP765" , 0x11800809417e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP766" , 0x11800809417f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP767" , 0x11800809417f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP768" , 0x1180080941800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP769" , 0x1180080941808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP770" , 0x1180080941810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP771" , 0x1180080941818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP772" , 0x1180080941820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP773" , 0x1180080941828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP774" , 0x1180080941830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP775" , 0x1180080941838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP776" , 0x1180080941840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP777" , 0x1180080941848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP778" , 0x1180080941850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP779" , 0x1180080941858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP780" , 0x1180080941860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP781" , 0x1180080941868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP782" , 0x1180080941870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP783" , 0x1180080941878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP784" , 0x1180080941880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP785" , 0x1180080941888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP786" , 0x1180080941890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP787" , 0x1180080941898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP788" , 0x11800809418a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP789" , 0x11800809418a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP790" , 0x11800809418b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP791" , 0x11800809418b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP792" , 0x11800809418c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP793" , 0x11800809418c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP794" , 0x11800809418d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP795" , 0x11800809418d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP796" , 0x11800809418e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP797" , 0x11800809418e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP798" , 0x11800809418f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP799" , 0x11800809418f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP800" , 0x1180080941900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP801" , 0x1180080941908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP802" , 0x1180080941910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP803" , 0x1180080941918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP804" , 0x1180080941920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP805" , 0x1180080941928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP806" , 0x1180080941930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP807" , 0x1180080941938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP808" , 0x1180080941940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP809" , 0x1180080941948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP810" , 0x1180080941950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP811" , 0x1180080941958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP812" , 0x1180080941960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP813" , 0x1180080941968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP814" , 0x1180080941970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP815" , 0x1180080941978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP816" , 0x1180080941980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP817" , 0x1180080941988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP818" , 0x1180080941990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP819" , 0x1180080941998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP820" , 0x11800809419a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP821" , 0x11800809419a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP822" , 0x11800809419b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP823" , 0x11800809419b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP824" , 0x11800809419c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP825" , 0x11800809419c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP826" , 0x11800809419d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP827" , 0x11800809419d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP828" , 0x11800809419e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP829" , 0x11800809419e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP830" , 0x11800809419f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP831" , 0x11800809419f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP832" , 0x1180080941a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP833" , 0x1180080941a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP834" , 0x1180080941a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP835" , 0x1180080941a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP836" , 0x1180080941a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP837" , 0x1180080941a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP838" , 0x1180080941a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP839" , 0x1180080941a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP840" , 0x1180080941a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP841" , 0x1180080941a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP842" , 0x1180080941a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP843" , 0x1180080941a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP844" , 0x1180080941a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP845" , 0x1180080941a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP846" , 0x1180080941a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP847" , 0x1180080941a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP848" , 0x1180080941a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP849" , 0x1180080941a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP850" , 0x1180080941a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP851" , 0x1180080941a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP852" , 0x1180080941aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP853" , 0x1180080941aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP854" , 0x1180080941ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP855" , 0x1180080941ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP856" , 0x1180080941ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP857" , 0x1180080941ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP858" , 0x1180080941ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP859" , 0x1180080941ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP860" , 0x1180080941ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP861" , 0x1180080941ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP862" , 0x1180080941af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP863" , 0x1180080941af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP864" , 0x1180080941b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP865" , 0x1180080941b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP866" , 0x1180080941b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP867" , 0x1180080941b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP868" , 0x1180080941b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP869" , 0x1180080941b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP870" , 0x1180080941b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP871" , 0x1180080941b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP872" , 0x1180080941b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP873" , 0x1180080941b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP874" , 0x1180080941b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP875" , 0x1180080941b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP876" , 0x1180080941b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP877" , 0x1180080941b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP878" , 0x1180080941b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP879" , 0x1180080941b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP880" , 0x1180080941b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP881" , 0x1180080941b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP882" , 0x1180080941b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP883" , 0x1180080941b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP884" , 0x1180080941ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP885" , 0x1180080941ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP886" , 0x1180080941bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP887" , 0x1180080941bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP888" , 0x1180080941bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP889" , 0x1180080941bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP890" , 0x1180080941bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP891" , 0x1180080941bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP892" , 0x1180080941be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP893" , 0x1180080941be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP894" , 0x1180080941bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP895" , 0x1180080941bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP896" , 0x1180080941c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP897" , 0x1180080941c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP898" , 0x1180080941c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP899" , 0x1180080941c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP900" , 0x1180080941c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP901" , 0x1180080941c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP902" , 0x1180080941c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP903" , 0x1180080941c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP904" , 0x1180080941c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP905" , 0x1180080941c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP906" , 0x1180080941c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP907" , 0x1180080941c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP908" , 0x1180080941c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP909" , 0x1180080941c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP910" , 0x1180080941c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP911" , 0x1180080941c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP912" , 0x1180080941c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP913" , 0x1180080941c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP914" , 0x1180080941c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP915" , 0x1180080941c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP916" , 0x1180080941ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP917" , 0x1180080941ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP918" , 0x1180080941cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP919" , 0x1180080941cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP920" , 0x1180080941cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP921" , 0x1180080941cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP922" , 0x1180080941cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP923" , 0x1180080941cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP924" , 0x1180080941ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP925" , 0x1180080941ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP926" , 0x1180080941cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP927" , 0x1180080941cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP928" , 0x1180080941d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP929" , 0x1180080941d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP930" , 0x1180080941d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP931" , 0x1180080941d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP932" , 0x1180080941d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP933" , 0x1180080941d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP934" , 0x1180080941d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP935" , 0x1180080941d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP936" , 0x1180080941d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP937" , 0x1180080941d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP938" , 0x1180080941d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP939" , 0x1180080941d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP940" , 0x1180080941d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP941" , 0x1180080941d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP942" , 0x1180080941d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP943" , 0x1180080941d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP944" , 0x1180080941d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP945" , 0x1180080941d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP946" , 0x1180080941d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP947" , 0x1180080941d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP948" , 0x1180080941da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP949" , 0x1180080941da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP950" , 0x1180080941db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP951" , 0x1180080941db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP952" , 0x1180080941dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP953" , 0x1180080941dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP954" , 0x1180080941dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP955" , 0x1180080941dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP956" , 0x1180080941de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP957" , 0x1180080941de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP958" , 0x1180080941df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP959" , 0x1180080941df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP960" , 0x1180080941e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP961" , 0x1180080941e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP962" , 0x1180080941e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP963" , 0x1180080941e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP964" , 0x1180080941e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP965" , 0x1180080941e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP966" , 0x1180080941e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP967" , 0x1180080941e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP968" , 0x1180080941e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP969" , 0x1180080941e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP970" , 0x1180080941e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP971" , 0x1180080941e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP972" , 0x1180080941e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP973" , 0x1180080941e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP974" , 0x1180080941e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP975" , 0x1180080941e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP976" , 0x1180080941e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP977" , 0x1180080941e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP978" , 0x1180080941e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP979" , 0x1180080941e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP980" , 0x1180080941ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP981" , 0x1180080941ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP982" , 0x1180080941eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP983" , 0x1180080941eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP984" , 0x1180080941ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP985" , 0x1180080941ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP986" , 0x1180080941ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP987" , 0x1180080941ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP988" , 0x1180080941ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP989" , 0x1180080941ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP990" , 0x1180080941ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP991" , 0x1180080941ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP992" , 0x1180080941f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP993" , 0x1180080941f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP994" , 0x1180080941f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP995" , 0x1180080941f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP996" , 0x1180080941f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP997" , 0x1180080941f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP998" , 0x1180080941f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP999" , 0x1180080941f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1000" , 0x1180080941f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1001" , 0x1180080941f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1002" , 0x1180080941f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1003" , 0x1180080941f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1004" , 0x1180080941f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1005" , 0x1180080941f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1006" , 0x1180080941f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1007" , 0x1180080941f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1008" , 0x1180080941f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1009" , 0x1180080941f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1010" , 0x1180080941f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1011" , 0x1180080941f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1012" , 0x1180080941fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1013" , 0x1180080941fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1014" , 0x1180080941fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1015" , 0x1180080941fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1016" , 0x1180080941fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1017" , 0x1180080941fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1018" , 0x1180080941fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1019" , 0x1180080941fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1020" , 0x1180080941fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1021" , 0x1180080941fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1022" , 0x1180080941ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1023" , 0x1180080941ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1024" , 0x1180080942000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1025" , 0x1180080942008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1026" , 0x1180080942010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1027" , 0x1180080942018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1028" , 0x1180080942020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1029" , 0x1180080942028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1030" , 0x1180080942030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1031" , 0x1180080942038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1032" , 0x1180080942040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1033" , 0x1180080942048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1034" , 0x1180080942050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1035" , 0x1180080942058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1036" , 0x1180080942060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1037" , 0x1180080942068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1038" , 0x1180080942070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1039" , 0x1180080942078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1040" , 0x1180080942080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1041" , 0x1180080942088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1042" , 0x1180080942090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1043" , 0x1180080942098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1044" , 0x11800809420a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1045" , 0x11800809420a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1046" , 0x11800809420b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1047" , 0x11800809420b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1048" , 0x11800809420c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1049" , 0x11800809420c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1050" , 0x11800809420d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1051" , 0x11800809420d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1052" , 0x11800809420e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1053" , 0x11800809420e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1054" , 0x11800809420f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1055" , 0x11800809420f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1056" , 0x1180080942100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1057" , 0x1180080942108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1058" , 0x1180080942110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1059" , 0x1180080942118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1060" , 0x1180080942120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1061" , 0x1180080942128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1062" , 0x1180080942130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1063" , 0x1180080942138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1064" , 0x1180080942140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1065" , 0x1180080942148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1066" , 0x1180080942150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1067" , 0x1180080942158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1068" , 0x1180080942160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1069" , 0x1180080942168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1070" , 0x1180080942170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1071" , 0x1180080942178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1072" , 0x1180080942180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1073" , 0x1180080942188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1074" , 0x1180080942190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1075" , 0x1180080942198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1076" , 0x11800809421a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1077" , 0x11800809421a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1078" , 0x11800809421b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1079" , 0x11800809421b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1080" , 0x11800809421c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1081" , 0x11800809421c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1082" , 0x11800809421d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1083" , 0x11800809421d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1084" , 0x11800809421e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1085" , 0x11800809421e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1086" , 0x11800809421f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1087" , 0x11800809421f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1088" , 0x1180080942200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1089" , 0x1180080942208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1090" , 0x1180080942210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1091" , 0x1180080942218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1092" , 0x1180080942220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1093" , 0x1180080942228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1094" , 0x1180080942230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1095" , 0x1180080942238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1096" , 0x1180080942240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1097" , 0x1180080942248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1098" , 0x1180080942250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1099" , 0x1180080942258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1100" , 0x1180080942260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1101" , 0x1180080942268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1102" , 0x1180080942270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1103" , 0x1180080942278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1104" , 0x1180080942280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1105" , 0x1180080942288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1106" , 0x1180080942290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1107" , 0x1180080942298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1108" , 0x11800809422a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1109" , 0x11800809422a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1110" , 0x11800809422b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1111" , 0x11800809422b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1112" , 0x11800809422c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1113" , 0x11800809422c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1114" , 0x11800809422d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1115" , 0x11800809422d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1116" , 0x11800809422e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1117" , 0x11800809422e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1118" , 0x11800809422f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1119" , 0x11800809422f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1120" , 0x1180080942300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1121" , 0x1180080942308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1122" , 0x1180080942310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1123" , 0x1180080942318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1124" , 0x1180080942320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1125" , 0x1180080942328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1126" , 0x1180080942330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1127" , 0x1180080942338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1128" , 0x1180080942340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1129" , 0x1180080942348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1130" , 0x1180080942350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1131" , 0x1180080942358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1132" , 0x1180080942360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1133" , 0x1180080942368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1134" , 0x1180080942370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1135" , 0x1180080942378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1136" , 0x1180080942380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1137" , 0x1180080942388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1138" , 0x1180080942390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1139" , 0x1180080942398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1140" , 0x11800809423a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1141" , 0x11800809423a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1142" , 0x11800809423b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1143" , 0x11800809423b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1144" , 0x11800809423c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1145" , 0x11800809423c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1146" , 0x11800809423d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1147" , 0x11800809423d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1148" , 0x11800809423e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1149" , 0x11800809423e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1150" , 0x11800809423f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1151" , 0x11800809423f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1152" , 0x1180080942400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1153" , 0x1180080942408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1154" , 0x1180080942410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1155" , 0x1180080942418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1156" , 0x1180080942420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1157" , 0x1180080942428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1158" , 0x1180080942430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1159" , 0x1180080942438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1160" , 0x1180080942440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1161" , 0x1180080942448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1162" , 0x1180080942450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1163" , 0x1180080942458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1164" , 0x1180080942460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1165" , 0x1180080942468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1166" , 0x1180080942470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1167" , 0x1180080942478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1168" , 0x1180080942480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1169" , 0x1180080942488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1170" , 0x1180080942490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1171" , 0x1180080942498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1172" , 0x11800809424a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1173" , 0x11800809424a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1174" , 0x11800809424b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1175" , 0x11800809424b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1176" , 0x11800809424c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1177" , 0x11800809424c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1178" , 0x11800809424d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1179" , 0x11800809424d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1180" , 0x11800809424e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1181" , 0x11800809424e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1182" , 0x11800809424f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1183" , 0x11800809424f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1184" , 0x1180080942500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1185" , 0x1180080942508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1186" , 0x1180080942510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1187" , 0x1180080942518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1188" , 0x1180080942520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1189" , 0x1180080942528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1190" , 0x1180080942530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1191" , 0x1180080942538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1192" , 0x1180080942540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1193" , 0x1180080942548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1194" , 0x1180080942550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1195" , 0x1180080942558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1196" , 0x1180080942560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1197" , 0x1180080942568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1198" , 0x1180080942570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1199" , 0x1180080942578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1200" , 0x1180080942580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1201" , 0x1180080942588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1202" , 0x1180080942590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1203" , 0x1180080942598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1204" , 0x11800809425a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1205" , 0x11800809425a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1206" , 0x11800809425b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1207" , 0x11800809425b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1208" , 0x11800809425c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1209" , 0x11800809425c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1210" , 0x11800809425d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1211" , 0x11800809425d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1212" , 0x11800809425e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1213" , 0x11800809425e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1214" , 0x11800809425f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1215" , 0x11800809425f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1216" , 0x1180080942600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1217" , 0x1180080942608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1218" , 0x1180080942610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1219" , 0x1180080942618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1220" , 0x1180080942620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1221" , 0x1180080942628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1222" , 0x1180080942630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1223" , 0x1180080942638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1224" , 0x1180080942640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1225" , 0x1180080942648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1226" , 0x1180080942650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1227" , 0x1180080942658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1228" , 0x1180080942660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1229" , 0x1180080942668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1230" , 0x1180080942670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1231" , 0x1180080942678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1232" , 0x1180080942680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1233" , 0x1180080942688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1234" , 0x1180080942690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1235" , 0x1180080942698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1236" , 0x11800809426a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1237" , 0x11800809426a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1238" , 0x11800809426b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1239" , 0x11800809426b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1240" , 0x11800809426c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1241" , 0x11800809426c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1242" , 0x11800809426d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1243" , 0x11800809426d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1244" , 0x11800809426e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1245" , 0x11800809426e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1246" , 0x11800809426f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1247" , 0x11800809426f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1248" , 0x1180080942700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1249" , 0x1180080942708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1250" , 0x1180080942710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1251" , 0x1180080942718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1252" , 0x1180080942720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1253" , 0x1180080942728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1254" , 0x1180080942730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1255" , 0x1180080942738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1256" , 0x1180080942740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1257" , 0x1180080942748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1258" , 0x1180080942750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1259" , 0x1180080942758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1260" , 0x1180080942760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1261" , 0x1180080942768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1262" , 0x1180080942770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1263" , 0x1180080942778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1264" , 0x1180080942780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1265" , 0x1180080942788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1266" , 0x1180080942790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1267" , 0x1180080942798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1268" , 0x11800809427a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1269" , 0x11800809427a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1270" , 0x11800809427b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1271" , 0x11800809427b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1272" , 0x11800809427c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1273" , 0x11800809427c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1274" , 0x11800809427d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1275" , 0x11800809427d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1276" , 0x11800809427e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1277" , 0x11800809427e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1278" , 0x11800809427f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1279" , 0x11800809427f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1280" , 0x1180080942800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1281" , 0x1180080942808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1282" , 0x1180080942810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1283" , 0x1180080942818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1284" , 0x1180080942820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1285" , 0x1180080942828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1286" , 0x1180080942830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1287" , 0x1180080942838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1288" , 0x1180080942840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1289" , 0x1180080942848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1290" , 0x1180080942850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1291" , 0x1180080942858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1292" , 0x1180080942860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1293" , 0x1180080942868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1294" , 0x1180080942870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1295" , 0x1180080942878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1296" , 0x1180080942880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1297" , 0x1180080942888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1298" , 0x1180080942890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1299" , 0x1180080942898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1300" , 0x11800809428a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1301" , 0x11800809428a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1302" , 0x11800809428b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1303" , 0x11800809428b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1304" , 0x11800809428c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1305" , 0x11800809428c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1306" , 0x11800809428d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1307" , 0x11800809428d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1308" , 0x11800809428e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1309" , 0x11800809428e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1310" , 0x11800809428f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1311" , 0x11800809428f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1312" , 0x1180080942900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1313" , 0x1180080942908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1314" , 0x1180080942910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1315" , 0x1180080942918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1316" , 0x1180080942920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1317" , 0x1180080942928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1318" , 0x1180080942930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1319" , 0x1180080942938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1320" , 0x1180080942940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1321" , 0x1180080942948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1322" , 0x1180080942950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1323" , 0x1180080942958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1324" , 0x1180080942960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1325" , 0x1180080942968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1326" , 0x1180080942970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1327" , 0x1180080942978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1328" , 0x1180080942980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1329" , 0x1180080942988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1330" , 0x1180080942990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1331" , 0x1180080942998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1332" , 0x11800809429a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1333" , 0x11800809429a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1334" , 0x11800809429b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1335" , 0x11800809429b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1336" , 0x11800809429c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1337" , 0x11800809429c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1338" , 0x11800809429d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1339" , 0x11800809429d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1340" , 0x11800809429e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1341" , 0x11800809429e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1342" , 0x11800809429f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1343" , 0x11800809429f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1344" , 0x1180080942a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1345" , 0x1180080942a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1346" , 0x1180080942a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1347" , 0x1180080942a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1348" , 0x1180080942a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1349" , 0x1180080942a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1350" , 0x1180080942a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1351" , 0x1180080942a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1352" , 0x1180080942a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1353" , 0x1180080942a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1354" , 0x1180080942a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1355" , 0x1180080942a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1356" , 0x1180080942a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1357" , 0x1180080942a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1358" , 0x1180080942a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1359" , 0x1180080942a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1360" , 0x1180080942a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1361" , 0x1180080942a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1362" , 0x1180080942a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1363" , 0x1180080942a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1364" , 0x1180080942aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1365" , 0x1180080942aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1366" , 0x1180080942ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1367" , 0x1180080942ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1368" , 0x1180080942ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1369" , 0x1180080942ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1370" , 0x1180080942ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1371" , 0x1180080942ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1372" , 0x1180080942ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1373" , 0x1180080942ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1374" , 0x1180080942af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1375" , 0x1180080942af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1376" , 0x1180080942b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1377" , 0x1180080942b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1378" , 0x1180080942b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1379" , 0x1180080942b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1380" , 0x1180080942b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1381" , 0x1180080942b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1382" , 0x1180080942b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1383" , 0x1180080942b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1384" , 0x1180080942b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1385" , 0x1180080942b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1386" , 0x1180080942b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1387" , 0x1180080942b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1388" , 0x1180080942b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1389" , 0x1180080942b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1390" , 0x1180080942b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1391" , 0x1180080942b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1392" , 0x1180080942b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1393" , 0x1180080942b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1394" , 0x1180080942b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1395" , 0x1180080942b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1396" , 0x1180080942ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1397" , 0x1180080942ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1398" , 0x1180080942bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1399" , 0x1180080942bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1400" , 0x1180080942bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1401" , 0x1180080942bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1402" , 0x1180080942bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1403" , 0x1180080942bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1404" , 0x1180080942be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1405" , 0x1180080942be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1406" , 0x1180080942bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1407" , 0x1180080942bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1408" , 0x1180080942c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1409" , 0x1180080942c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1410" , 0x1180080942c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1411" , 0x1180080942c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1412" , 0x1180080942c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1413" , 0x1180080942c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1414" , 0x1180080942c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1415" , 0x1180080942c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1416" , 0x1180080942c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1417" , 0x1180080942c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1418" , 0x1180080942c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1419" , 0x1180080942c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1420" , 0x1180080942c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1421" , 0x1180080942c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1422" , 0x1180080942c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1423" , 0x1180080942c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1424" , 0x1180080942c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1425" , 0x1180080942c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1426" , 0x1180080942c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1427" , 0x1180080942c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1428" , 0x1180080942ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1429" , 0x1180080942ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1430" , 0x1180080942cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1431" , 0x1180080942cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1432" , 0x1180080942cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1433" , 0x1180080942cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1434" , 0x1180080942cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1435" , 0x1180080942cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1436" , 0x1180080942ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1437" , 0x1180080942ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1438" , 0x1180080942cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1439" , 0x1180080942cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1440" , 0x1180080942d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1441" , 0x1180080942d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1442" , 0x1180080942d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1443" , 0x1180080942d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1444" , 0x1180080942d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1445" , 0x1180080942d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1446" , 0x1180080942d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1447" , 0x1180080942d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1448" , 0x1180080942d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1449" , 0x1180080942d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1450" , 0x1180080942d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1451" , 0x1180080942d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1452" , 0x1180080942d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1453" , 0x1180080942d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1454" , 0x1180080942d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1455" , 0x1180080942d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1456" , 0x1180080942d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1457" , 0x1180080942d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1458" , 0x1180080942d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1459" , 0x1180080942d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1460" , 0x1180080942da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1461" , 0x1180080942da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1462" , 0x1180080942db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1463" , 0x1180080942db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1464" , 0x1180080942dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1465" , 0x1180080942dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1466" , 0x1180080942dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1467" , 0x1180080942dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1468" , 0x1180080942de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1469" , 0x1180080942de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1470" , 0x1180080942df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1471" , 0x1180080942df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1472" , 0x1180080942e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1473" , 0x1180080942e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1474" , 0x1180080942e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1475" , 0x1180080942e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1476" , 0x1180080942e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1477" , 0x1180080942e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1478" , 0x1180080942e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1479" , 0x1180080942e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1480" , 0x1180080942e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1481" , 0x1180080942e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1482" , 0x1180080942e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1483" , 0x1180080942e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1484" , 0x1180080942e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1485" , 0x1180080942e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1486" , 0x1180080942e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1487" , 0x1180080942e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1488" , 0x1180080942e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1489" , 0x1180080942e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1490" , 0x1180080942e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1491" , 0x1180080942e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1492" , 0x1180080942ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1493" , 0x1180080942ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1494" , 0x1180080942eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1495" , 0x1180080942eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1496" , 0x1180080942ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1497" , 0x1180080942ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1498" , 0x1180080942ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1499" , 0x1180080942ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1500" , 0x1180080942ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1501" , 0x1180080942ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1502" , 0x1180080942ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1503" , 0x1180080942ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1504" , 0x1180080942f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1505" , 0x1180080942f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1506" , 0x1180080942f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1507" , 0x1180080942f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1508" , 0x1180080942f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1509" , 0x1180080942f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1510" , 0x1180080942f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1511" , 0x1180080942f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1512" , 0x1180080942f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1513" , 0x1180080942f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1514" , 0x1180080942f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1515" , 0x1180080942f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1516" , 0x1180080942f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1517" , 0x1180080942f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1518" , 0x1180080942f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1519" , 0x1180080942f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1520" , 0x1180080942f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1521" , 0x1180080942f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1522" , 0x1180080942f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1523" , 0x1180080942f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1524" , 0x1180080942fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1525" , 0x1180080942fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1526" , 0x1180080942fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1527" , 0x1180080942fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1528" , 0x1180080942fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1529" , 0x1180080942fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1530" , 0x1180080942fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1531" , 0x1180080942fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1532" , 0x1180080942fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1533" , 0x1180080942fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1534" , 0x1180080942ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1535" , 0x1180080942ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1536" , 0x1180080943000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1537" , 0x1180080943008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1538" , 0x1180080943010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1539" , 0x1180080943018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1540" , 0x1180080943020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1541" , 0x1180080943028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1542" , 0x1180080943030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1543" , 0x1180080943038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1544" , 0x1180080943040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1545" , 0x1180080943048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1546" , 0x1180080943050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1547" , 0x1180080943058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1548" , 0x1180080943060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1549" , 0x1180080943068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1550" , 0x1180080943070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1551" , 0x1180080943078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1552" , 0x1180080943080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1553" , 0x1180080943088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1554" , 0x1180080943090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1555" , 0x1180080943098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1556" , 0x11800809430a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1557" , 0x11800809430a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1558" , 0x11800809430b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1559" , 0x11800809430b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1560" , 0x11800809430c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1561" , 0x11800809430c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1562" , 0x11800809430d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1563" , 0x11800809430d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1564" , 0x11800809430e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1565" , 0x11800809430e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1566" , 0x11800809430f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1567" , 0x11800809430f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1568" , 0x1180080943100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1569" , 0x1180080943108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1570" , 0x1180080943110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1571" , 0x1180080943118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1572" , 0x1180080943120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1573" , 0x1180080943128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1574" , 0x1180080943130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1575" , 0x1180080943138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1576" , 0x1180080943140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1577" , 0x1180080943148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1578" , 0x1180080943150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1579" , 0x1180080943158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1580" , 0x1180080943160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1581" , 0x1180080943168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1582" , 0x1180080943170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1583" , 0x1180080943178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1584" , 0x1180080943180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1585" , 0x1180080943188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1586" , 0x1180080943190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1587" , 0x1180080943198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1588" , 0x11800809431a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1589" , 0x11800809431a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1590" , 0x11800809431b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1591" , 0x11800809431b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1592" , 0x11800809431c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1593" , 0x11800809431c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1594" , 0x11800809431d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1595" , 0x11800809431d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1596" , 0x11800809431e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1597" , 0x11800809431e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1598" , 0x11800809431f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1599" , 0x11800809431f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1600" , 0x1180080943200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1601" , 0x1180080943208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1602" , 0x1180080943210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1603" , 0x1180080943218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1604" , 0x1180080943220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1605" , 0x1180080943228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1606" , 0x1180080943230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1607" , 0x1180080943238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1608" , 0x1180080943240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1609" , 0x1180080943248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1610" , 0x1180080943250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1611" , 0x1180080943258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1612" , 0x1180080943260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1613" , 0x1180080943268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1614" , 0x1180080943270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1615" , 0x1180080943278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1616" , 0x1180080943280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1617" , 0x1180080943288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1618" , 0x1180080943290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1619" , 0x1180080943298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1620" , 0x11800809432a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1621" , 0x11800809432a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1622" , 0x11800809432b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1623" , 0x11800809432b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1624" , 0x11800809432c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1625" , 0x11800809432c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1626" , 0x11800809432d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1627" , 0x11800809432d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1628" , 0x11800809432e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1629" , 0x11800809432e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1630" , 0x11800809432f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1631" , 0x11800809432f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1632" , 0x1180080943300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1633" , 0x1180080943308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1634" , 0x1180080943310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1635" , 0x1180080943318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1636" , 0x1180080943320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1637" , 0x1180080943328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1638" , 0x1180080943330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1639" , 0x1180080943338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1640" , 0x1180080943340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1641" , 0x1180080943348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1642" , 0x1180080943350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1643" , 0x1180080943358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1644" , 0x1180080943360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1645" , 0x1180080943368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1646" , 0x1180080943370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1647" , 0x1180080943378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1648" , 0x1180080943380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1649" , 0x1180080943388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1650" , 0x1180080943390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1651" , 0x1180080943398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1652" , 0x11800809433a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1653" , 0x11800809433a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1654" , 0x11800809433b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1655" , 0x11800809433b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1656" , 0x11800809433c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1657" , 0x11800809433c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1658" , 0x11800809433d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1659" , 0x11800809433d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1660" , 0x11800809433e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1661" , 0x11800809433e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1662" , 0x11800809433f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1663" , 0x11800809433f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1664" , 0x1180080943400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1665" , 0x1180080943408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1666" , 0x1180080943410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1667" , 0x1180080943418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1668" , 0x1180080943420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1669" , 0x1180080943428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1670" , 0x1180080943430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1671" , 0x1180080943438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1672" , 0x1180080943440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1673" , 0x1180080943448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1674" , 0x1180080943450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1675" , 0x1180080943458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1676" , 0x1180080943460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1677" , 0x1180080943468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1678" , 0x1180080943470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1679" , 0x1180080943478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1680" , 0x1180080943480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1681" , 0x1180080943488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1682" , 0x1180080943490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1683" , 0x1180080943498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1684" , 0x11800809434a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1685" , 0x11800809434a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1686" , 0x11800809434b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1687" , 0x11800809434b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1688" , 0x11800809434c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1689" , 0x11800809434c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1690" , 0x11800809434d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1691" , 0x11800809434d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1692" , 0x11800809434e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1693" , 0x11800809434e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1694" , 0x11800809434f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1695" , 0x11800809434f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1696" , 0x1180080943500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1697" , 0x1180080943508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1698" , 0x1180080943510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1699" , 0x1180080943518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1700" , 0x1180080943520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1701" , 0x1180080943528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1702" , 0x1180080943530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1703" , 0x1180080943538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1704" , 0x1180080943540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1705" , 0x1180080943548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1706" , 0x1180080943550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1707" , 0x1180080943558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1708" , 0x1180080943560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1709" , 0x1180080943568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1710" , 0x1180080943570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1711" , 0x1180080943578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1712" , 0x1180080943580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1713" , 0x1180080943588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1714" , 0x1180080943590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1715" , 0x1180080943598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1716" , 0x11800809435a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1717" , 0x11800809435a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1718" , 0x11800809435b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1719" , 0x11800809435b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1720" , 0x11800809435c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1721" , 0x11800809435c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1722" , 0x11800809435d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1723" , 0x11800809435d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1724" , 0x11800809435e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1725" , 0x11800809435e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1726" , 0x11800809435f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1727" , 0x11800809435f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1728" , 0x1180080943600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1729" , 0x1180080943608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1730" , 0x1180080943610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1731" , 0x1180080943618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1732" , 0x1180080943620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1733" , 0x1180080943628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1734" , 0x1180080943630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1735" , 0x1180080943638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1736" , 0x1180080943640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1737" , 0x1180080943648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1738" , 0x1180080943650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1739" , 0x1180080943658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1740" , 0x1180080943660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1741" , 0x1180080943668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1742" , 0x1180080943670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1743" , 0x1180080943678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1744" , 0x1180080943680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1745" , 0x1180080943688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1746" , 0x1180080943690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1747" , 0x1180080943698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1748" , 0x11800809436a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1749" , 0x11800809436a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1750" , 0x11800809436b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1751" , 0x11800809436b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1752" , 0x11800809436c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1753" , 0x11800809436c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1754" , 0x11800809436d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1755" , 0x11800809436d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1756" , 0x11800809436e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1757" , 0x11800809436e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1758" , 0x11800809436f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1759" , 0x11800809436f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1760" , 0x1180080943700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1761" , 0x1180080943708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1762" , 0x1180080943710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1763" , 0x1180080943718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1764" , 0x1180080943720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1765" , 0x1180080943728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1766" , 0x1180080943730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1767" , 0x1180080943738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1768" , 0x1180080943740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1769" , 0x1180080943748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1770" , 0x1180080943750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1771" , 0x1180080943758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1772" , 0x1180080943760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1773" , 0x1180080943768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1774" , 0x1180080943770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1775" , 0x1180080943778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1776" , 0x1180080943780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1777" , 0x1180080943788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1778" , 0x1180080943790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1779" , 0x1180080943798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1780" , 0x11800809437a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1781" , 0x11800809437a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1782" , 0x11800809437b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1783" , 0x11800809437b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1784" , 0x11800809437c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1785" , 0x11800809437c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1786" , 0x11800809437d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1787" , 0x11800809437d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1788" , 0x11800809437e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1789" , 0x11800809437e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1790" , 0x11800809437f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1791" , 0x11800809437f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1792" , 0x1180080943800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1793" , 0x1180080943808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1794" , 0x1180080943810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1795" , 0x1180080943818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1796" , 0x1180080943820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1797" , 0x1180080943828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1798" , 0x1180080943830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1799" , 0x1180080943838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1800" , 0x1180080943840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1801" , 0x1180080943848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1802" , 0x1180080943850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1803" , 0x1180080943858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1804" , 0x1180080943860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1805" , 0x1180080943868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1806" , 0x1180080943870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1807" , 0x1180080943878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1808" , 0x1180080943880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1809" , 0x1180080943888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1810" , 0x1180080943890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1811" , 0x1180080943898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1812" , 0x11800809438a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1813" , 0x11800809438a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1814" , 0x11800809438b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1815" , 0x11800809438b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1816" , 0x11800809438c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1817" , 0x11800809438c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1818" , 0x11800809438d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1819" , 0x11800809438d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1820" , 0x11800809438e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1821" , 0x11800809438e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1822" , 0x11800809438f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1823" , 0x11800809438f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1824" , 0x1180080943900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1825" , 0x1180080943908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1826" , 0x1180080943910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1827" , 0x1180080943918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1828" , 0x1180080943920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1829" , 0x1180080943928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1830" , 0x1180080943930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1831" , 0x1180080943938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1832" , 0x1180080943940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1833" , 0x1180080943948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1834" , 0x1180080943950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1835" , 0x1180080943958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1836" , 0x1180080943960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1837" , 0x1180080943968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1838" , 0x1180080943970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1839" , 0x1180080943978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1840" , 0x1180080943980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1841" , 0x1180080943988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1842" , 0x1180080943990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1843" , 0x1180080943998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1844" , 0x11800809439a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1845" , 0x11800809439a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1846" , 0x11800809439b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1847" , 0x11800809439b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1848" , 0x11800809439c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1849" , 0x11800809439c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1850" , 0x11800809439d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1851" , 0x11800809439d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1852" , 0x11800809439e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1853" , 0x11800809439e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1854" , 0x11800809439f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1855" , 0x11800809439f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1856" , 0x1180080943a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1857" , 0x1180080943a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1858" , 0x1180080943a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1859" , 0x1180080943a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1860" , 0x1180080943a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1861" , 0x1180080943a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1862" , 0x1180080943a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1863" , 0x1180080943a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1864" , 0x1180080943a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1865" , 0x1180080943a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1866" , 0x1180080943a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1867" , 0x1180080943a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1868" , 0x1180080943a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1869" , 0x1180080943a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1870" , 0x1180080943a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1871" , 0x1180080943a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1872" , 0x1180080943a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1873" , 0x1180080943a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1874" , 0x1180080943a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1875" , 0x1180080943a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1876" , 0x1180080943aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1877" , 0x1180080943aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1878" , 0x1180080943ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1879" , 0x1180080943ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1880" , 0x1180080943ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1881" , 0x1180080943ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1882" , 0x1180080943ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1883" , 0x1180080943ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1884" , 0x1180080943ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1885" , 0x1180080943ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1886" , 0x1180080943af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1887" , 0x1180080943af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1888" , 0x1180080943b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1889" , 0x1180080943b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1890" , 0x1180080943b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1891" , 0x1180080943b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1892" , 0x1180080943b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1893" , 0x1180080943b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1894" , 0x1180080943b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1895" , 0x1180080943b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1896" , 0x1180080943b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1897" , 0x1180080943b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1898" , 0x1180080943b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1899" , 0x1180080943b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1900" , 0x1180080943b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1901" , 0x1180080943b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1902" , 0x1180080943b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1903" , 0x1180080943b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1904" , 0x1180080943b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1905" , 0x1180080943b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1906" , 0x1180080943b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1907" , 0x1180080943b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1908" , 0x1180080943ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1909" , 0x1180080943ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1910" , 0x1180080943bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1911" , 0x1180080943bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1912" , 0x1180080943bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1913" , 0x1180080943bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1914" , 0x1180080943bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1915" , 0x1180080943bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1916" , 0x1180080943be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1917" , 0x1180080943be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1918" , 0x1180080943bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1919" , 0x1180080943bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1920" , 0x1180080943c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1921" , 0x1180080943c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1922" , 0x1180080943c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1923" , 0x1180080943c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1924" , 0x1180080943c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1925" , 0x1180080943c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1926" , 0x1180080943c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1927" , 0x1180080943c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1928" , 0x1180080943c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1929" , 0x1180080943c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1930" , 0x1180080943c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1931" , 0x1180080943c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1932" , 0x1180080943c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1933" , 0x1180080943c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1934" , 0x1180080943c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1935" , 0x1180080943c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1936" , 0x1180080943c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1937" , 0x1180080943c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1938" , 0x1180080943c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1939" , 0x1180080943c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1940" , 0x1180080943ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1941" , 0x1180080943ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1942" , 0x1180080943cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1943" , 0x1180080943cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1944" , 0x1180080943cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1945" , 0x1180080943cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1946" , 0x1180080943cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1947" , 0x1180080943cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1948" , 0x1180080943ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1949" , 0x1180080943ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1950" , 0x1180080943cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1951" , 0x1180080943cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1952" , 0x1180080943d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1953" , 0x1180080943d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1954" , 0x1180080943d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1955" , 0x1180080943d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1956" , 0x1180080943d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1957" , 0x1180080943d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1958" , 0x1180080943d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1959" , 0x1180080943d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1960" , 0x1180080943d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1961" , 0x1180080943d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1962" , 0x1180080943d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1963" , 0x1180080943d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1964" , 0x1180080943d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1965" , 0x1180080943d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1966" , 0x1180080943d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1967" , 0x1180080943d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1968" , 0x1180080943d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1969" , 0x1180080943d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1970" , 0x1180080943d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1971" , 0x1180080943d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1972" , 0x1180080943da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1973" , 0x1180080943da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1974" , 0x1180080943db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1975" , 0x1180080943db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1976" , 0x1180080943dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1977" , 0x1180080943dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1978" , 0x1180080943dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1979" , 0x1180080943dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1980" , 0x1180080943de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1981" , 0x1180080943de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1982" , 0x1180080943df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1983" , 0x1180080943df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1984" , 0x1180080943e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1985" , 0x1180080943e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1986" , 0x1180080943e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1987" , 0x1180080943e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1988" , 0x1180080943e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1989" , 0x1180080943e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1990" , 0x1180080943e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1991" , 0x1180080943e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1992" , 0x1180080943e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1993" , 0x1180080943e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1994" , 0x1180080943e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1995" , 0x1180080943e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1996" , 0x1180080943e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1997" , 0x1180080943e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1998" , 0x1180080943e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP1999" , 0x1180080943e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2000" , 0x1180080943e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2001" , 0x1180080943e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2002" , 0x1180080943e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2003" , 0x1180080943e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2004" , 0x1180080943ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2005" , 0x1180080943ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2006" , 0x1180080943eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2007" , 0x1180080943eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2008" , 0x1180080943ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2009" , 0x1180080943ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2010" , 0x1180080943ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2011" , 0x1180080943ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2012" , 0x1180080943ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2013" , 0x1180080943ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2014" , 0x1180080943ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2015" , 0x1180080943ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2016" , 0x1180080943f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2017" , 0x1180080943f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2018" , 0x1180080943f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2019" , 0x1180080943f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2020" , 0x1180080943f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2021" , 0x1180080943f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2022" , 0x1180080943f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2023" , 0x1180080943f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2024" , 0x1180080943f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2025" , 0x1180080943f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2026" , 0x1180080943f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2027" , 0x1180080943f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2028" , 0x1180080943f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2029" , 0x1180080943f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2030" , 0x1180080943f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2031" , 0x1180080943f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2032" , 0x1180080943f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2033" , 0x1180080943f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2034" , 0x1180080943f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2035" , 0x1180080943f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2036" , 0x1180080943fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2037" , 0x1180080943fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2038" , 0x1180080943fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2039" , 0x1180080943fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2040" , 0x1180080943fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2041" , 0x1180080943fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2042" , 0x1180080943fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2043" , 0x1180080943fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2044" , 0x1180080943fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2045" , 0x1180080943fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2046" , 0x1180080943ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2047" , 0x1180080943ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2048" , 0x1180080944000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2049" , 0x1180080944008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2050" , 0x1180080944010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2051" , 0x1180080944018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2052" , 0x1180080944020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2053" , 0x1180080944028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2054" , 0x1180080944030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2055" , 0x1180080944038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2056" , 0x1180080944040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2057" , 0x1180080944048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2058" , 0x1180080944050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2059" , 0x1180080944058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2060" , 0x1180080944060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2061" , 0x1180080944068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2062" , 0x1180080944070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2063" , 0x1180080944078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2064" , 0x1180080944080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2065" , 0x1180080944088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2066" , 0x1180080944090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2067" , 0x1180080944098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2068" , 0x11800809440a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2069" , 0x11800809440a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2070" , 0x11800809440b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2071" , 0x11800809440b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2072" , 0x11800809440c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2073" , 0x11800809440c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2074" , 0x11800809440d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2075" , 0x11800809440d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2076" , 0x11800809440e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2077" , 0x11800809440e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2078" , 0x11800809440f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2079" , 0x11800809440f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2080" , 0x1180080944100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2081" , 0x1180080944108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2082" , 0x1180080944110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2083" , 0x1180080944118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2084" , 0x1180080944120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2085" , 0x1180080944128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2086" , 0x1180080944130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2087" , 0x1180080944138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2088" , 0x1180080944140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2089" , 0x1180080944148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2090" , 0x1180080944150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2091" , 0x1180080944158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2092" , 0x1180080944160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2093" , 0x1180080944168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2094" , 0x1180080944170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2095" , 0x1180080944178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2096" , 0x1180080944180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2097" , 0x1180080944188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2098" , 0x1180080944190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2099" , 0x1180080944198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2100" , 0x11800809441a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2101" , 0x11800809441a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2102" , 0x11800809441b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2103" , 0x11800809441b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2104" , 0x11800809441c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2105" , 0x11800809441c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2106" , 0x11800809441d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2107" , 0x11800809441d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2108" , 0x11800809441e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2109" , 0x11800809441e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2110" , 0x11800809441f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2111" , 0x11800809441f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2112" , 0x1180080944200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2113" , 0x1180080944208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2114" , 0x1180080944210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2115" , 0x1180080944218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2116" , 0x1180080944220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2117" , 0x1180080944228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2118" , 0x1180080944230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2119" , 0x1180080944238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2120" , 0x1180080944240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2121" , 0x1180080944248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2122" , 0x1180080944250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2123" , 0x1180080944258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2124" , 0x1180080944260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2125" , 0x1180080944268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2126" , 0x1180080944270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2127" , 0x1180080944278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2128" , 0x1180080944280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2129" , 0x1180080944288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2130" , 0x1180080944290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2131" , 0x1180080944298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2132" , 0x11800809442a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2133" , 0x11800809442a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2134" , 0x11800809442b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2135" , 0x11800809442b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2136" , 0x11800809442c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2137" , 0x11800809442c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2138" , 0x11800809442d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2139" , 0x11800809442d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2140" , 0x11800809442e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2141" , 0x11800809442e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2142" , 0x11800809442f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2143" , 0x11800809442f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2144" , 0x1180080944300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2145" , 0x1180080944308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2146" , 0x1180080944310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2147" , 0x1180080944318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2148" , 0x1180080944320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2149" , 0x1180080944328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2150" , 0x1180080944330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2151" , 0x1180080944338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2152" , 0x1180080944340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2153" , 0x1180080944348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2154" , 0x1180080944350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2155" , 0x1180080944358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2156" , 0x1180080944360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2157" , 0x1180080944368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2158" , 0x1180080944370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2159" , 0x1180080944378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2160" , 0x1180080944380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2161" , 0x1180080944388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2162" , 0x1180080944390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2163" , 0x1180080944398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2164" , 0x11800809443a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2165" , 0x11800809443a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2166" , 0x11800809443b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2167" , 0x11800809443b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2168" , 0x11800809443c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2169" , 0x11800809443c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2170" , 0x11800809443d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2171" , 0x11800809443d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2172" , 0x11800809443e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2173" , 0x11800809443e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2174" , 0x11800809443f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2175" , 0x11800809443f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2176" , 0x1180080944400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2177" , 0x1180080944408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2178" , 0x1180080944410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2179" , 0x1180080944418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2180" , 0x1180080944420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2181" , 0x1180080944428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2182" , 0x1180080944430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2183" , 0x1180080944438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2184" , 0x1180080944440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2185" , 0x1180080944448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2186" , 0x1180080944450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2187" , 0x1180080944458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2188" , 0x1180080944460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2189" , 0x1180080944468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2190" , 0x1180080944470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2191" , 0x1180080944478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2192" , 0x1180080944480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2193" , 0x1180080944488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2194" , 0x1180080944490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2195" , 0x1180080944498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2196" , 0x11800809444a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2197" , 0x11800809444a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2198" , 0x11800809444b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2199" , 0x11800809444b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2200" , 0x11800809444c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2201" , 0x11800809444c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2202" , 0x11800809444d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2203" , 0x11800809444d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2204" , 0x11800809444e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2205" , 0x11800809444e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2206" , 0x11800809444f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2207" , 0x11800809444f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2208" , 0x1180080944500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2209" , 0x1180080944508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2210" , 0x1180080944510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2211" , 0x1180080944518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2212" , 0x1180080944520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2213" , 0x1180080944528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2214" , 0x1180080944530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2215" , 0x1180080944538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2216" , 0x1180080944540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2217" , 0x1180080944548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2218" , 0x1180080944550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2219" , 0x1180080944558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2220" , 0x1180080944560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2221" , 0x1180080944568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2222" , 0x1180080944570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2223" , 0x1180080944578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2224" , 0x1180080944580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2225" , 0x1180080944588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2226" , 0x1180080944590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2227" , 0x1180080944598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2228" , 0x11800809445a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2229" , 0x11800809445a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2230" , 0x11800809445b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2231" , 0x11800809445b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2232" , 0x11800809445c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2233" , 0x11800809445c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2234" , 0x11800809445d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2235" , 0x11800809445d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2236" , 0x11800809445e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2237" , 0x11800809445e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2238" , 0x11800809445f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2239" , 0x11800809445f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2240" , 0x1180080944600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2241" , 0x1180080944608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2242" , 0x1180080944610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2243" , 0x1180080944618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2244" , 0x1180080944620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2245" , 0x1180080944628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2246" , 0x1180080944630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2247" , 0x1180080944638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2248" , 0x1180080944640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2249" , 0x1180080944648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2250" , 0x1180080944650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2251" , 0x1180080944658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2252" , 0x1180080944660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2253" , 0x1180080944668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2254" , 0x1180080944670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2255" , 0x1180080944678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2256" , 0x1180080944680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2257" , 0x1180080944688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2258" , 0x1180080944690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2259" , 0x1180080944698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2260" , 0x11800809446a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2261" , 0x11800809446a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2262" , 0x11800809446b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2263" , 0x11800809446b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2264" , 0x11800809446c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2265" , 0x11800809446c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2266" , 0x11800809446d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2267" , 0x11800809446d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2268" , 0x11800809446e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2269" , 0x11800809446e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2270" , 0x11800809446f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2271" , 0x11800809446f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2272" , 0x1180080944700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2273" , 0x1180080944708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2274" , 0x1180080944710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2275" , 0x1180080944718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2276" , 0x1180080944720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2277" , 0x1180080944728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2278" , 0x1180080944730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2279" , 0x1180080944738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2280" , 0x1180080944740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2281" , 0x1180080944748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2282" , 0x1180080944750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2283" , 0x1180080944758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2284" , 0x1180080944760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2285" , 0x1180080944768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2286" , 0x1180080944770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2287" , 0x1180080944778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2288" , 0x1180080944780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2289" , 0x1180080944788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2290" , 0x1180080944790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2291" , 0x1180080944798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2292" , 0x11800809447a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2293" , 0x11800809447a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2294" , 0x11800809447b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2295" , 0x11800809447b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2296" , 0x11800809447c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2297" , 0x11800809447c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2298" , 0x11800809447d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2299" , 0x11800809447d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2300" , 0x11800809447e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2301" , 0x11800809447e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2302" , 0x11800809447f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2303" , 0x11800809447f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2304" , 0x1180080944800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2305" , 0x1180080944808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2306" , 0x1180080944810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2307" , 0x1180080944818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2308" , 0x1180080944820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2309" , 0x1180080944828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2310" , 0x1180080944830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2311" , 0x1180080944838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2312" , 0x1180080944840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2313" , 0x1180080944848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2314" , 0x1180080944850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2315" , 0x1180080944858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2316" , 0x1180080944860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2317" , 0x1180080944868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2318" , 0x1180080944870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2319" , 0x1180080944878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2320" , 0x1180080944880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2321" , 0x1180080944888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2322" , 0x1180080944890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2323" , 0x1180080944898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2324" , 0x11800809448a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2325" , 0x11800809448a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2326" , 0x11800809448b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2327" , 0x11800809448b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2328" , 0x11800809448c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2329" , 0x11800809448c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2330" , 0x11800809448d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2331" , 0x11800809448d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2332" , 0x11800809448e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2333" , 0x11800809448e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2334" , 0x11800809448f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2335" , 0x11800809448f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2336" , 0x1180080944900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2337" , 0x1180080944908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2338" , 0x1180080944910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2339" , 0x1180080944918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2340" , 0x1180080944920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2341" , 0x1180080944928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2342" , 0x1180080944930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2343" , 0x1180080944938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2344" , 0x1180080944940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2345" , 0x1180080944948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2346" , 0x1180080944950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2347" , 0x1180080944958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2348" , 0x1180080944960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2349" , 0x1180080944968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2350" , 0x1180080944970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2351" , 0x1180080944978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2352" , 0x1180080944980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2353" , 0x1180080944988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2354" , 0x1180080944990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2355" , 0x1180080944998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2356" , 0x11800809449a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2357" , 0x11800809449a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2358" , 0x11800809449b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2359" , 0x11800809449b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2360" , 0x11800809449c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2361" , 0x11800809449c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2362" , 0x11800809449d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2363" , 0x11800809449d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2364" , 0x11800809449e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2365" , 0x11800809449e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2366" , 0x11800809449f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2367" , 0x11800809449f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2368" , 0x1180080944a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2369" , 0x1180080944a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2370" , 0x1180080944a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2371" , 0x1180080944a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2372" , 0x1180080944a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2373" , 0x1180080944a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2374" , 0x1180080944a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2375" , 0x1180080944a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2376" , 0x1180080944a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2377" , 0x1180080944a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2378" , 0x1180080944a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2379" , 0x1180080944a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2380" , 0x1180080944a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2381" , 0x1180080944a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2382" , 0x1180080944a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2383" , 0x1180080944a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2384" , 0x1180080944a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2385" , 0x1180080944a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2386" , 0x1180080944a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2387" , 0x1180080944a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2388" , 0x1180080944aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2389" , 0x1180080944aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2390" , 0x1180080944ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2391" , 0x1180080944ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2392" , 0x1180080944ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2393" , 0x1180080944ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2394" , 0x1180080944ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2395" , 0x1180080944ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2396" , 0x1180080944ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2397" , 0x1180080944ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2398" , 0x1180080944af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2399" , 0x1180080944af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2400" , 0x1180080944b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2401" , 0x1180080944b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2402" , 0x1180080944b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2403" , 0x1180080944b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2404" , 0x1180080944b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2405" , 0x1180080944b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2406" , 0x1180080944b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2407" , 0x1180080944b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2408" , 0x1180080944b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2409" , 0x1180080944b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2410" , 0x1180080944b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2411" , 0x1180080944b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2412" , 0x1180080944b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2413" , 0x1180080944b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2414" , 0x1180080944b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2415" , 0x1180080944b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2416" , 0x1180080944b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2417" , 0x1180080944b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2418" , 0x1180080944b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2419" , 0x1180080944b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2420" , 0x1180080944ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2421" , 0x1180080944ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2422" , 0x1180080944bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2423" , 0x1180080944bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2424" , 0x1180080944bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2425" , 0x1180080944bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2426" , 0x1180080944bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2427" , 0x1180080944bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2428" , 0x1180080944be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2429" , 0x1180080944be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2430" , 0x1180080944bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2431" , 0x1180080944bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2432" , 0x1180080944c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2433" , 0x1180080944c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2434" , 0x1180080944c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2435" , 0x1180080944c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2436" , 0x1180080944c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2437" , 0x1180080944c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2438" , 0x1180080944c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2439" , 0x1180080944c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2440" , 0x1180080944c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2441" , 0x1180080944c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2442" , 0x1180080944c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2443" , 0x1180080944c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2444" , 0x1180080944c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2445" , 0x1180080944c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2446" , 0x1180080944c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2447" , 0x1180080944c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2448" , 0x1180080944c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2449" , 0x1180080944c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2450" , 0x1180080944c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2451" , 0x1180080944c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2452" , 0x1180080944ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2453" , 0x1180080944ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2454" , 0x1180080944cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2455" , 0x1180080944cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2456" , 0x1180080944cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2457" , 0x1180080944cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2458" , 0x1180080944cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2459" , 0x1180080944cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2460" , 0x1180080944ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2461" , 0x1180080944ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2462" , 0x1180080944cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2463" , 0x1180080944cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2464" , 0x1180080944d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2465" , 0x1180080944d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2466" , 0x1180080944d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2467" , 0x1180080944d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2468" , 0x1180080944d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2469" , 0x1180080944d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2470" , 0x1180080944d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2471" , 0x1180080944d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2472" , 0x1180080944d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2473" , 0x1180080944d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2474" , 0x1180080944d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2475" , 0x1180080944d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2476" , 0x1180080944d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2477" , 0x1180080944d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2478" , 0x1180080944d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2479" , 0x1180080944d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2480" , 0x1180080944d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2481" , 0x1180080944d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2482" , 0x1180080944d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2483" , 0x1180080944d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2484" , 0x1180080944da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2485" , 0x1180080944da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2486" , 0x1180080944db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2487" , 0x1180080944db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2488" , 0x1180080944dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2489" , 0x1180080944dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2490" , 0x1180080944dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2491" , 0x1180080944dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2492" , 0x1180080944de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2493" , 0x1180080944de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2494" , 0x1180080944df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2495" , 0x1180080944df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2496" , 0x1180080944e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2497" , 0x1180080944e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2498" , 0x1180080944e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2499" , 0x1180080944e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2500" , 0x1180080944e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2501" , 0x1180080944e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2502" , 0x1180080944e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2503" , 0x1180080944e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2504" , 0x1180080944e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2505" , 0x1180080944e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2506" , 0x1180080944e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2507" , 0x1180080944e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2508" , 0x1180080944e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2509" , 0x1180080944e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2510" , 0x1180080944e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2511" , 0x1180080944e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2512" , 0x1180080944e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2513" , 0x1180080944e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2514" , 0x1180080944e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2515" , 0x1180080944e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2516" , 0x1180080944ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2517" , 0x1180080944ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2518" , 0x1180080944eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2519" , 0x1180080944eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2520" , 0x1180080944ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2521" , 0x1180080944ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2522" , 0x1180080944ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2523" , 0x1180080944ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2524" , 0x1180080944ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2525" , 0x1180080944ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2526" , 0x1180080944ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2527" , 0x1180080944ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2528" , 0x1180080944f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2529" , 0x1180080944f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2530" , 0x1180080944f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2531" , 0x1180080944f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2532" , 0x1180080944f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2533" , 0x1180080944f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2534" , 0x1180080944f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2535" , 0x1180080944f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2536" , 0x1180080944f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2537" , 0x1180080944f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2538" , 0x1180080944f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2539" , 0x1180080944f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2540" , 0x1180080944f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2541" , 0x1180080944f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2542" , 0x1180080944f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2543" , 0x1180080944f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2544" , 0x1180080944f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2545" , 0x1180080944f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2546" , 0x1180080944f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2547" , 0x1180080944f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2548" , 0x1180080944fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2549" , 0x1180080944fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2550" , 0x1180080944fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2551" , 0x1180080944fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2552" , 0x1180080944fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2553" , 0x1180080944fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2554" , 0x1180080944fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2555" , 0x1180080944fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2556" , 0x1180080944fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2557" , 0x1180080944fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2558" , 0x1180080944ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2559" , 0x1180080944ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2560" , 0x1180080945000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2561" , 0x1180080945008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2562" , 0x1180080945010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2563" , 0x1180080945018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2564" , 0x1180080945020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2565" , 0x1180080945028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2566" , 0x1180080945030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2567" , 0x1180080945038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2568" , 0x1180080945040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2569" , 0x1180080945048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2570" , 0x1180080945050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2571" , 0x1180080945058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2572" , 0x1180080945060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2573" , 0x1180080945068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2574" , 0x1180080945070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2575" , 0x1180080945078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2576" , 0x1180080945080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2577" , 0x1180080945088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2578" , 0x1180080945090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2579" , 0x1180080945098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2580" , 0x11800809450a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2581" , 0x11800809450a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2582" , 0x11800809450b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2583" , 0x11800809450b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2584" , 0x11800809450c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2585" , 0x11800809450c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2586" , 0x11800809450d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2587" , 0x11800809450d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2588" , 0x11800809450e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2589" , 0x11800809450e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2590" , 0x11800809450f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2591" , 0x11800809450f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2592" , 0x1180080945100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2593" , 0x1180080945108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2594" , 0x1180080945110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2595" , 0x1180080945118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2596" , 0x1180080945120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2597" , 0x1180080945128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2598" , 0x1180080945130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2599" , 0x1180080945138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2600" , 0x1180080945140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2601" , 0x1180080945148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2602" , 0x1180080945150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2603" , 0x1180080945158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2604" , 0x1180080945160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2605" , 0x1180080945168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2606" , 0x1180080945170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2607" , 0x1180080945178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2608" , 0x1180080945180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2609" , 0x1180080945188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2610" , 0x1180080945190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2611" , 0x1180080945198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2612" , 0x11800809451a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2613" , 0x11800809451a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2614" , 0x11800809451b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2615" , 0x11800809451b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2616" , 0x11800809451c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2617" , 0x11800809451c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2618" , 0x11800809451d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2619" , 0x11800809451d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2620" , 0x11800809451e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2621" , 0x11800809451e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2622" , 0x11800809451f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2623" , 0x11800809451f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2624" , 0x1180080945200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2625" , 0x1180080945208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2626" , 0x1180080945210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2627" , 0x1180080945218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2628" , 0x1180080945220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2629" , 0x1180080945228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2630" , 0x1180080945230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2631" , 0x1180080945238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2632" , 0x1180080945240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2633" , 0x1180080945248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2634" , 0x1180080945250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2635" , 0x1180080945258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2636" , 0x1180080945260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2637" , 0x1180080945268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2638" , 0x1180080945270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2639" , 0x1180080945278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2640" , 0x1180080945280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2641" , 0x1180080945288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2642" , 0x1180080945290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2643" , 0x1180080945298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2644" , 0x11800809452a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2645" , 0x11800809452a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2646" , 0x11800809452b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2647" , 0x11800809452b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2648" , 0x11800809452c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2649" , 0x11800809452c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2650" , 0x11800809452d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2651" , 0x11800809452d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2652" , 0x11800809452e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2653" , 0x11800809452e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2654" , 0x11800809452f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2655" , 0x11800809452f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2656" , 0x1180080945300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2657" , 0x1180080945308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2658" , 0x1180080945310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2659" , 0x1180080945318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2660" , 0x1180080945320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2661" , 0x1180080945328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2662" , 0x1180080945330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2663" , 0x1180080945338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2664" , 0x1180080945340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2665" , 0x1180080945348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2666" , 0x1180080945350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2667" , 0x1180080945358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2668" , 0x1180080945360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2669" , 0x1180080945368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2670" , 0x1180080945370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2671" , 0x1180080945378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2672" , 0x1180080945380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2673" , 0x1180080945388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2674" , 0x1180080945390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2675" , 0x1180080945398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2676" , 0x11800809453a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2677" , 0x11800809453a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2678" , 0x11800809453b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2679" , 0x11800809453b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2680" , 0x11800809453c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2681" , 0x11800809453c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2682" , 0x11800809453d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2683" , 0x11800809453d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2684" , 0x11800809453e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2685" , 0x11800809453e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2686" , 0x11800809453f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2687" , 0x11800809453f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2688" , 0x1180080945400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2689" , 0x1180080945408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2690" , 0x1180080945410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2691" , 0x1180080945418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2692" , 0x1180080945420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2693" , 0x1180080945428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2694" , 0x1180080945430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2695" , 0x1180080945438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2696" , 0x1180080945440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2697" , 0x1180080945448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2698" , 0x1180080945450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2699" , 0x1180080945458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2700" , 0x1180080945460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2701" , 0x1180080945468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2702" , 0x1180080945470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2703" , 0x1180080945478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2704" , 0x1180080945480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2705" , 0x1180080945488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2706" , 0x1180080945490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2707" , 0x1180080945498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2708" , 0x11800809454a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2709" , 0x11800809454a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2710" , 0x11800809454b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2711" , 0x11800809454b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2712" , 0x11800809454c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2713" , 0x11800809454c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2714" , 0x11800809454d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2715" , 0x11800809454d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2716" , 0x11800809454e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2717" , 0x11800809454e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2718" , 0x11800809454f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2719" , 0x11800809454f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2720" , 0x1180080945500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2721" , 0x1180080945508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2722" , 0x1180080945510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2723" , 0x1180080945518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2724" , 0x1180080945520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2725" , 0x1180080945528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2726" , 0x1180080945530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2727" , 0x1180080945538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2728" , 0x1180080945540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2729" , 0x1180080945548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2730" , 0x1180080945550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2731" , 0x1180080945558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2732" , 0x1180080945560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2733" , 0x1180080945568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2734" , 0x1180080945570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2735" , 0x1180080945578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2736" , 0x1180080945580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2737" , 0x1180080945588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2738" , 0x1180080945590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2739" , 0x1180080945598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2740" , 0x11800809455a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2741" , 0x11800809455a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2742" , 0x11800809455b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2743" , 0x11800809455b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2744" , 0x11800809455c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2745" , 0x11800809455c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2746" , 0x11800809455d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2747" , 0x11800809455d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2748" , 0x11800809455e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2749" , 0x11800809455e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2750" , 0x11800809455f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2751" , 0x11800809455f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2752" , 0x1180080945600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2753" , 0x1180080945608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2754" , 0x1180080945610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2755" , 0x1180080945618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2756" , 0x1180080945620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2757" , 0x1180080945628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2758" , 0x1180080945630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2759" , 0x1180080945638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2760" , 0x1180080945640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2761" , 0x1180080945648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2762" , 0x1180080945650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2763" , 0x1180080945658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2764" , 0x1180080945660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2765" , 0x1180080945668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2766" , 0x1180080945670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2767" , 0x1180080945678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2768" , 0x1180080945680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2769" , 0x1180080945688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2770" , 0x1180080945690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2771" , 0x1180080945698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2772" , 0x11800809456a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2773" , 0x11800809456a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2774" , 0x11800809456b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2775" , 0x11800809456b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2776" , 0x11800809456c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2777" , 0x11800809456c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2778" , 0x11800809456d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2779" , 0x11800809456d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2780" , 0x11800809456e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2781" , 0x11800809456e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2782" , 0x11800809456f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2783" , 0x11800809456f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2784" , 0x1180080945700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2785" , 0x1180080945708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2786" , 0x1180080945710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2787" , 0x1180080945718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2788" , 0x1180080945720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2789" , 0x1180080945728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2790" , 0x1180080945730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2791" , 0x1180080945738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2792" , 0x1180080945740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2793" , 0x1180080945748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2794" , 0x1180080945750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2795" , 0x1180080945758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2796" , 0x1180080945760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2797" , 0x1180080945768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2798" , 0x1180080945770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2799" , 0x1180080945778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2800" , 0x1180080945780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2801" , 0x1180080945788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2802" , 0x1180080945790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2803" , 0x1180080945798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2804" , 0x11800809457a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2805" , 0x11800809457a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2806" , 0x11800809457b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2807" , 0x11800809457b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2808" , 0x11800809457c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2809" , 0x11800809457c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2810" , 0x11800809457d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2811" , 0x11800809457d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2812" , 0x11800809457e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2813" , 0x11800809457e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2814" , 0x11800809457f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2815" , 0x11800809457f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2816" , 0x1180080945800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2817" , 0x1180080945808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2818" , 0x1180080945810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2819" , 0x1180080945818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2820" , 0x1180080945820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2821" , 0x1180080945828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2822" , 0x1180080945830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2823" , 0x1180080945838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2824" , 0x1180080945840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2825" , 0x1180080945848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2826" , 0x1180080945850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2827" , 0x1180080945858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2828" , 0x1180080945860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2829" , 0x1180080945868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2830" , 0x1180080945870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2831" , 0x1180080945878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2832" , 0x1180080945880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2833" , 0x1180080945888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2834" , 0x1180080945890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2835" , 0x1180080945898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2836" , 0x11800809458a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2837" , 0x11800809458a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2838" , 0x11800809458b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2839" , 0x11800809458b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2840" , 0x11800809458c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2841" , 0x11800809458c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2842" , 0x11800809458d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2843" , 0x11800809458d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2844" , 0x11800809458e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2845" , 0x11800809458e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2846" , 0x11800809458f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2847" , 0x11800809458f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2848" , 0x1180080945900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2849" , 0x1180080945908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2850" , 0x1180080945910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2851" , 0x1180080945918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2852" , 0x1180080945920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2853" , 0x1180080945928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2854" , 0x1180080945930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2855" , 0x1180080945938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2856" , 0x1180080945940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2857" , 0x1180080945948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2858" , 0x1180080945950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2859" , 0x1180080945958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2860" , 0x1180080945960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2861" , 0x1180080945968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2862" , 0x1180080945970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2863" , 0x1180080945978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2864" , 0x1180080945980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2865" , 0x1180080945988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2866" , 0x1180080945990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2867" , 0x1180080945998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2868" , 0x11800809459a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2869" , 0x11800809459a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2870" , 0x11800809459b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2871" , 0x11800809459b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2872" , 0x11800809459c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2873" , 0x11800809459c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2874" , 0x11800809459d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2875" , 0x11800809459d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2876" , 0x11800809459e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2877" , 0x11800809459e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2878" , 0x11800809459f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2879" , 0x11800809459f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2880" , 0x1180080945a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2881" , 0x1180080945a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2882" , 0x1180080945a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2883" , 0x1180080945a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2884" , 0x1180080945a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2885" , 0x1180080945a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2886" , 0x1180080945a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2887" , 0x1180080945a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2888" , 0x1180080945a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2889" , 0x1180080945a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2890" , 0x1180080945a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2891" , 0x1180080945a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2892" , 0x1180080945a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2893" , 0x1180080945a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2894" , 0x1180080945a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2895" , 0x1180080945a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2896" , 0x1180080945a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2897" , 0x1180080945a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2898" , 0x1180080945a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2899" , 0x1180080945a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2900" , 0x1180080945aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2901" , 0x1180080945aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2902" , 0x1180080945ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2903" , 0x1180080945ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2904" , 0x1180080945ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2905" , 0x1180080945ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2906" , 0x1180080945ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2907" , 0x1180080945ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2908" , 0x1180080945ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2909" , 0x1180080945ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2910" , 0x1180080945af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2911" , 0x1180080945af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2912" , 0x1180080945b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2913" , 0x1180080945b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2914" , 0x1180080945b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2915" , 0x1180080945b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2916" , 0x1180080945b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2917" , 0x1180080945b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2918" , 0x1180080945b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2919" , 0x1180080945b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2920" , 0x1180080945b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2921" , 0x1180080945b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2922" , 0x1180080945b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2923" , 0x1180080945b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2924" , 0x1180080945b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2925" , 0x1180080945b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2926" , 0x1180080945b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2927" , 0x1180080945b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2928" , 0x1180080945b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2929" , 0x1180080945b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2930" , 0x1180080945b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2931" , 0x1180080945b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2932" , 0x1180080945ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2933" , 0x1180080945ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2934" , 0x1180080945bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2935" , 0x1180080945bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2936" , 0x1180080945bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2937" , 0x1180080945bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2938" , 0x1180080945bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2939" , 0x1180080945bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2940" , 0x1180080945be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2941" , 0x1180080945be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2942" , 0x1180080945bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2943" , 0x1180080945bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2944" , 0x1180080945c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2945" , 0x1180080945c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2946" , 0x1180080945c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2947" , 0x1180080945c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2948" , 0x1180080945c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2949" , 0x1180080945c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2950" , 0x1180080945c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2951" , 0x1180080945c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2952" , 0x1180080945c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2953" , 0x1180080945c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2954" , 0x1180080945c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2955" , 0x1180080945c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2956" , 0x1180080945c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2957" , 0x1180080945c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2958" , 0x1180080945c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2959" , 0x1180080945c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2960" , 0x1180080945c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2961" , 0x1180080945c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2962" , 0x1180080945c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2963" , 0x1180080945c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2964" , 0x1180080945ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2965" , 0x1180080945ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2966" , 0x1180080945cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2967" , 0x1180080945cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2968" , 0x1180080945cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2969" , 0x1180080945cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2970" , 0x1180080945cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2971" , 0x1180080945cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2972" , 0x1180080945ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2973" , 0x1180080945ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2974" , 0x1180080945cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2975" , 0x1180080945cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2976" , 0x1180080945d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2977" , 0x1180080945d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2978" , 0x1180080945d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2979" , 0x1180080945d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2980" , 0x1180080945d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2981" , 0x1180080945d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2982" , 0x1180080945d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2983" , 0x1180080945d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2984" , 0x1180080945d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2985" , 0x1180080945d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2986" , 0x1180080945d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2987" , 0x1180080945d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2988" , 0x1180080945d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2989" , 0x1180080945d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2990" , 0x1180080945d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2991" , 0x1180080945d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2992" , 0x1180080945d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2993" , 0x1180080945d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2994" , 0x1180080945d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2995" , 0x1180080945d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2996" , 0x1180080945da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2997" , 0x1180080945da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2998" , 0x1180080945db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP2999" , 0x1180080945db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3000" , 0x1180080945dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3001" , 0x1180080945dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3002" , 0x1180080945dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3003" , 0x1180080945dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3004" , 0x1180080945de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3005" , 0x1180080945de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3006" , 0x1180080945df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3007" , 0x1180080945df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3008" , 0x1180080945e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3009" , 0x1180080945e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3010" , 0x1180080945e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3011" , 0x1180080945e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3012" , 0x1180080945e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3013" , 0x1180080945e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3014" , 0x1180080945e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3015" , 0x1180080945e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3016" , 0x1180080945e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3017" , 0x1180080945e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3018" , 0x1180080945e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3019" , 0x1180080945e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3020" , 0x1180080945e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3021" , 0x1180080945e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3022" , 0x1180080945e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3023" , 0x1180080945e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3024" , 0x1180080945e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3025" , 0x1180080945e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3026" , 0x1180080945e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3027" , 0x1180080945e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3028" , 0x1180080945ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3029" , 0x1180080945ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3030" , 0x1180080945eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3031" , 0x1180080945eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3032" , 0x1180080945ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3033" , 0x1180080945ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3034" , 0x1180080945ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3035" , 0x1180080945ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3036" , 0x1180080945ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3037" , 0x1180080945ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3038" , 0x1180080945ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3039" , 0x1180080945ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3040" , 0x1180080945f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3041" , 0x1180080945f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3042" , 0x1180080945f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3043" , 0x1180080945f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3044" , 0x1180080945f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3045" , 0x1180080945f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3046" , 0x1180080945f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3047" , 0x1180080945f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3048" , 0x1180080945f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3049" , 0x1180080945f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3050" , 0x1180080945f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3051" , 0x1180080945f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3052" , 0x1180080945f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3053" , 0x1180080945f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3054" , 0x1180080945f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3055" , 0x1180080945f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3056" , 0x1180080945f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3057" , 0x1180080945f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3058" , 0x1180080945f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3059" , 0x1180080945f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3060" , 0x1180080945fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3061" , 0x1180080945fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3062" , 0x1180080945fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3063" , 0x1180080945fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3064" , 0x1180080945fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3065" , 0x1180080945fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3066" , 0x1180080945fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3067" , 0x1180080945fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3068" , 0x1180080945fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3069" , 0x1180080945fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3070" , 0x1180080945ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3071" , 0x1180080945ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3072" , 0x1180080946000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3073" , 0x1180080946008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3074" , 0x1180080946010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3075" , 0x1180080946018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3076" , 0x1180080946020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3077" , 0x1180080946028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3078" , 0x1180080946030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3079" , 0x1180080946038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3080" , 0x1180080946040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3081" , 0x1180080946048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3082" , 0x1180080946050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3083" , 0x1180080946058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3084" , 0x1180080946060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3085" , 0x1180080946068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3086" , 0x1180080946070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3087" , 0x1180080946078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3088" , 0x1180080946080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3089" , 0x1180080946088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3090" , 0x1180080946090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3091" , 0x1180080946098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3092" , 0x11800809460a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3093" , 0x11800809460a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3094" , 0x11800809460b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3095" , 0x11800809460b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3096" , 0x11800809460c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3097" , 0x11800809460c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3098" , 0x11800809460d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3099" , 0x11800809460d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3100" , 0x11800809460e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3101" , 0x11800809460e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3102" , 0x11800809460f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3103" , 0x11800809460f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3104" , 0x1180080946100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3105" , 0x1180080946108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3106" , 0x1180080946110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3107" , 0x1180080946118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3108" , 0x1180080946120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3109" , 0x1180080946128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3110" , 0x1180080946130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3111" , 0x1180080946138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3112" , 0x1180080946140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3113" , 0x1180080946148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3114" , 0x1180080946150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3115" , 0x1180080946158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3116" , 0x1180080946160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3117" , 0x1180080946168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3118" , 0x1180080946170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3119" , 0x1180080946178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3120" , 0x1180080946180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3121" , 0x1180080946188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3122" , 0x1180080946190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3123" , 0x1180080946198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3124" , 0x11800809461a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3125" , 0x11800809461a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3126" , 0x11800809461b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3127" , 0x11800809461b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3128" , 0x11800809461c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3129" , 0x11800809461c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3130" , 0x11800809461d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3131" , 0x11800809461d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3132" , 0x11800809461e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3133" , 0x11800809461e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3134" , 0x11800809461f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3135" , 0x11800809461f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3136" , 0x1180080946200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3137" , 0x1180080946208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3138" , 0x1180080946210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3139" , 0x1180080946218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3140" , 0x1180080946220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3141" , 0x1180080946228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3142" , 0x1180080946230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3143" , 0x1180080946238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3144" , 0x1180080946240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3145" , 0x1180080946248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3146" , 0x1180080946250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3147" , 0x1180080946258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3148" , 0x1180080946260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3149" , 0x1180080946268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3150" , 0x1180080946270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3151" , 0x1180080946278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3152" , 0x1180080946280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3153" , 0x1180080946288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3154" , 0x1180080946290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3155" , 0x1180080946298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3156" , 0x11800809462a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3157" , 0x11800809462a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3158" , 0x11800809462b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3159" , 0x11800809462b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3160" , 0x11800809462c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3161" , 0x11800809462c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3162" , 0x11800809462d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3163" , 0x11800809462d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3164" , 0x11800809462e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3165" , 0x11800809462e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3166" , 0x11800809462f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3167" , 0x11800809462f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3168" , 0x1180080946300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3169" , 0x1180080946308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3170" , 0x1180080946310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3171" , 0x1180080946318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3172" , 0x1180080946320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3173" , 0x1180080946328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3174" , 0x1180080946330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3175" , 0x1180080946338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3176" , 0x1180080946340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3177" , 0x1180080946348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3178" , 0x1180080946350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3179" , 0x1180080946358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3180" , 0x1180080946360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3181" , 0x1180080946368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3182" , 0x1180080946370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3183" , 0x1180080946378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3184" , 0x1180080946380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3185" , 0x1180080946388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3186" , 0x1180080946390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3187" , 0x1180080946398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3188" , 0x11800809463a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3189" , 0x11800809463a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3190" , 0x11800809463b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3191" , 0x11800809463b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3192" , 0x11800809463c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3193" , 0x11800809463c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3194" , 0x11800809463d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3195" , 0x11800809463d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3196" , 0x11800809463e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3197" , 0x11800809463e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3198" , 0x11800809463f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3199" , 0x11800809463f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3200" , 0x1180080946400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3201" , 0x1180080946408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3202" , 0x1180080946410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3203" , 0x1180080946418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3204" , 0x1180080946420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3205" , 0x1180080946428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3206" , 0x1180080946430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3207" , 0x1180080946438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3208" , 0x1180080946440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3209" , 0x1180080946448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3210" , 0x1180080946450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3211" , 0x1180080946458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3212" , 0x1180080946460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3213" , 0x1180080946468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3214" , 0x1180080946470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3215" , 0x1180080946478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3216" , 0x1180080946480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3217" , 0x1180080946488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3218" , 0x1180080946490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3219" , 0x1180080946498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3220" , 0x11800809464a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3221" , 0x11800809464a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3222" , 0x11800809464b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3223" , 0x11800809464b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3224" , 0x11800809464c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3225" , 0x11800809464c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3226" , 0x11800809464d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3227" , 0x11800809464d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3228" , 0x11800809464e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3229" , 0x11800809464e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3230" , 0x11800809464f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3231" , 0x11800809464f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3232" , 0x1180080946500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3233" , 0x1180080946508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3234" , 0x1180080946510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3235" , 0x1180080946518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3236" , 0x1180080946520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3237" , 0x1180080946528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3238" , 0x1180080946530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3239" , 0x1180080946538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3240" , 0x1180080946540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3241" , 0x1180080946548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3242" , 0x1180080946550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3243" , 0x1180080946558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3244" , 0x1180080946560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3245" , 0x1180080946568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3246" , 0x1180080946570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3247" , 0x1180080946578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3248" , 0x1180080946580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3249" , 0x1180080946588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3250" , 0x1180080946590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3251" , 0x1180080946598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3252" , 0x11800809465a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3253" , 0x11800809465a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3254" , 0x11800809465b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3255" , 0x11800809465b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3256" , 0x11800809465c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3257" , 0x11800809465c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3258" , 0x11800809465d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3259" , 0x11800809465d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3260" , 0x11800809465e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3261" , 0x11800809465e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3262" , 0x11800809465f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3263" , 0x11800809465f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3264" , 0x1180080946600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3265" , 0x1180080946608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3266" , 0x1180080946610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3267" , 0x1180080946618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3268" , 0x1180080946620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3269" , 0x1180080946628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3270" , 0x1180080946630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3271" , 0x1180080946638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3272" , 0x1180080946640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3273" , 0x1180080946648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3274" , 0x1180080946650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3275" , 0x1180080946658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3276" , 0x1180080946660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3277" , 0x1180080946668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3278" , 0x1180080946670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3279" , 0x1180080946678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3280" , 0x1180080946680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3281" , 0x1180080946688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3282" , 0x1180080946690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3283" , 0x1180080946698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3284" , 0x11800809466a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3285" , 0x11800809466a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3286" , 0x11800809466b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3287" , 0x11800809466b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3288" , 0x11800809466c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3289" , 0x11800809466c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3290" , 0x11800809466d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3291" , 0x11800809466d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3292" , 0x11800809466e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3293" , 0x11800809466e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3294" , 0x11800809466f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3295" , 0x11800809466f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3296" , 0x1180080946700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3297" , 0x1180080946708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3298" , 0x1180080946710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3299" , 0x1180080946718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3300" , 0x1180080946720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3301" , 0x1180080946728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3302" , 0x1180080946730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3303" , 0x1180080946738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3304" , 0x1180080946740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3305" , 0x1180080946748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3306" , 0x1180080946750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3307" , 0x1180080946758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3308" , 0x1180080946760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3309" , 0x1180080946768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3310" , 0x1180080946770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3311" , 0x1180080946778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3312" , 0x1180080946780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3313" , 0x1180080946788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3314" , 0x1180080946790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3315" , 0x1180080946798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3316" , 0x11800809467a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3317" , 0x11800809467a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3318" , 0x11800809467b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3319" , 0x11800809467b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3320" , 0x11800809467c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3321" , 0x11800809467c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3322" , 0x11800809467d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3323" , 0x11800809467d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3324" , 0x11800809467e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3325" , 0x11800809467e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3326" , 0x11800809467f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3327" , 0x11800809467f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3328" , 0x1180080946800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3329" , 0x1180080946808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3330" , 0x1180080946810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3331" , 0x1180080946818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3332" , 0x1180080946820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3333" , 0x1180080946828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3334" , 0x1180080946830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3335" , 0x1180080946838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3336" , 0x1180080946840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3337" , 0x1180080946848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3338" , 0x1180080946850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3339" , 0x1180080946858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3340" , 0x1180080946860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3341" , 0x1180080946868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3342" , 0x1180080946870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3343" , 0x1180080946878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3344" , 0x1180080946880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3345" , 0x1180080946888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3346" , 0x1180080946890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3347" , 0x1180080946898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3348" , 0x11800809468a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3349" , 0x11800809468a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3350" , 0x11800809468b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3351" , 0x11800809468b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3352" , 0x11800809468c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3353" , 0x11800809468c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3354" , 0x11800809468d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3355" , 0x11800809468d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3356" , 0x11800809468e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3357" , 0x11800809468e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3358" , 0x11800809468f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3359" , 0x11800809468f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3360" , 0x1180080946900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3361" , 0x1180080946908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3362" , 0x1180080946910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3363" , 0x1180080946918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3364" , 0x1180080946920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3365" , 0x1180080946928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3366" , 0x1180080946930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3367" , 0x1180080946938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3368" , 0x1180080946940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3369" , 0x1180080946948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3370" , 0x1180080946950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3371" , 0x1180080946958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3372" , 0x1180080946960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3373" , 0x1180080946968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3374" , 0x1180080946970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3375" , 0x1180080946978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3376" , 0x1180080946980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3377" , 0x1180080946988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3378" , 0x1180080946990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3379" , 0x1180080946998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3380" , 0x11800809469a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3381" , 0x11800809469a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3382" , 0x11800809469b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3383" , 0x11800809469b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3384" , 0x11800809469c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3385" , 0x11800809469c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3386" , 0x11800809469d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3387" , 0x11800809469d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3388" , 0x11800809469e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3389" , 0x11800809469e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3390" , 0x11800809469f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3391" , 0x11800809469f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3392" , 0x1180080946a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3393" , 0x1180080946a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3394" , 0x1180080946a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3395" , 0x1180080946a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3396" , 0x1180080946a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3397" , 0x1180080946a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3398" , 0x1180080946a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3399" , 0x1180080946a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3400" , 0x1180080946a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3401" , 0x1180080946a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3402" , 0x1180080946a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3403" , 0x1180080946a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3404" , 0x1180080946a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3405" , 0x1180080946a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3406" , 0x1180080946a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3407" , 0x1180080946a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3408" , 0x1180080946a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3409" , 0x1180080946a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3410" , 0x1180080946a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3411" , 0x1180080946a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3412" , 0x1180080946aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3413" , 0x1180080946aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3414" , 0x1180080946ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3415" , 0x1180080946ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3416" , 0x1180080946ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3417" , 0x1180080946ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3418" , 0x1180080946ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3419" , 0x1180080946ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3420" , 0x1180080946ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3421" , 0x1180080946ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3422" , 0x1180080946af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3423" , 0x1180080946af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3424" , 0x1180080946b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3425" , 0x1180080946b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3426" , 0x1180080946b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3427" , 0x1180080946b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3428" , 0x1180080946b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3429" , 0x1180080946b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3430" , 0x1180080946b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3431" , 0x1180080946b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3432" , 0x1180080946b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3433" , 0x1180080946b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3434" , 0x1180080946b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3435" , 0x1180080946b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3436" , 0x1180080946b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3437" , 0x1180080946b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3438" , 0x1180080946b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3439" , 0x1180080946b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3440" , 0x1180080946b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3441" , 0x1180080946b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3442" , 0x1180080946b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3443" , 0x1180080946b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3444" , 0x1180080946ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3445" , 0x1180080946ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3446" , 0x1180080946bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3447" , 0x1180080946bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3448" , 0x1180080946bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3449" , 0x1180080946bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3450" , 0x1180080946bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3451" , 0x1180080946bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3452" , 0x1180080946be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3453" , 0x1180080946be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3454" , 0x1180080946bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3455" , 0x1180080946bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3456" , 0x1180080946c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3457" , 0x1180080946c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3458" , 0x1180080946c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3459" , 0x1180080946c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3460" , 0x1180080946c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3461" , 0x1180080946c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3462" , 0x1180080946c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3463" , 0x1180080946c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3464" , 0x1180080946c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3465" , 0x1180080946c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3466" , 0x1180080946c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3467" , 0x1180080946c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3468" , 0x1180080946c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3469" , 0x1180080946c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3470" , 0x1180080946c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3471" , 0x1180080946c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3472" , 0x1180080946c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3473" , 0x1180080946c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3474" , 0x1180080946c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3475" , 0x1180080946c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3476" , 0x1180080946ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3477" , 0x1180080946ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3478" , 0x1180080946cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3479" , 0x1180080946cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3480" , 0x1180080946cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3481" , 0x1180080946cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3482" , 0x1180080946cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3483" , 0x1180080946cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3484" , 0x1180080946ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3485" , 0x1180080946ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3486" , 0x1180080946cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3487" , 0x1180080946cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3488" , 0x1180080946d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3489" , 0x1180080946d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3490" , 0x1180080946d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3491" , 0x1180080946d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3492" , 0x1180080946d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3493" , 0x1180080946d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3494" , 0x1180080946d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3495" , 0x1180080946d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3496" , 0x1180080946d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3497" , 0x1180080946d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3498" , 0x1180080946d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3499" , 0x1180080946d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3500" , 0x1180080946d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3501" , 0x1180080946d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3502" , 0x1180080946d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3503" , 0x1180080946d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3504" , 0x1180080946d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3505" , 0x1180080946d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3506" , 0x1180080946d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3507" , 0x1180080946d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3508" , 0x1180080946da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3509" , 0x1180080946da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3510" , 0x1180080946db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3511" , 0x1180080946db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3512" , 0x1180080946dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3513" , 0x1180080946dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3514" , 0x1180080946dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3515" , 0x1180080946dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3516" , 0x1180080946de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3517" , 0x1180080946de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3518" , 0x1180080946df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3519" , 0x1180080946df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3520" , 0x1180080946e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3521" , 0x1180080946e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3522" , 0x1180080946e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3523" , 0x1180080946e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3524" , 0x1180080946e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3525" , 0x1180080946e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3526" , 0x1180080946e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3527" , 0x1180080946e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3528" , 0x1180080946e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3529" , 0x1180080946e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3530" , 0x1180080946e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3531" , 0x1180080946e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3532" , 0x1180080946e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3533" , 0x1180080946e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3534" , 0x1180080946e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3535" , 0x1180080946e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3536" , 0x1180080946e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3537" , 0x1180080946e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3538" , 0x1180080946e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3539" , 0x1180080946e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3540" , 0x1180080946ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3541" , 0x1180080946ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3542" , 0x1180080946eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3543" , 0x1180080946eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3544" , 0x1180080946ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3545" , 0x1180080946ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3546" , 0x1180080946ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3547" , 0x1180080946ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3548" , 0x1180080946ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3549" , 0x1180080946ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3550" , 0x1180080946ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3551" , 0x1180080946ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3552" , 0x1180080946f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3553" , 0x1180080946f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3554" , 0x1180080946f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3555" , 0x1180080946f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3556" , 0x1180080946f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3557" , 0x1180080946f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3558" , 0x1180080946f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3559" , 0x1180080946f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3560" , 0x1180080946f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3561" , 0x1180080946f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3562" , 0x1180080946f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3563" , 0x1180080946f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3564" , 0x1180080946f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3565" , 0x1180080946f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3566" , 0x1180080946f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3567" , 0x1180080946f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3568" , 0x1180080946f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3569" , 0x1180080946f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3570" , 0x1180080946f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3571" , 0x1180080946f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3572" , 0x1180080946fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3573" , 0x1180080946fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3574" , 0x1180080946fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3575" , 0x1180080946fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3576" , 0x1180080946fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3577" , 0x1180080946fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3578" , 0x1180080946fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3579" , 0x1180080946fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3580" , 0x1180080946fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3581" , 0x1180080946fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3582" , 0x1180080946ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3583" , 0x1180080946ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3584" , 0x1180080947000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3585" , 0x1180080947008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3586" , 0x1180080947010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3587" , 0x1180080947018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3588" , 0x1180080947020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3589" , 0x1180080947028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3590" , 0x1180080947030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3591" , 0x1180080947038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3592" , 0x1180080947040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3593" , 0x1180080947048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3594" , 0x1180080947050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3595" , 0x1180080947058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3596" , 0x1180080947060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3597" , 0x1180080947068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3598" , 0x1180080947070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3599" , 0x1180080947078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3600" , 0x1180080947080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3601" , 0x1180080947088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3602" , 0x1180080947090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3603" , 0x1180080947098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3604" , 0x11800809470a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3605" , 0x11800809470a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3606" , 0x11800809470b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3607" , 0x11800809470b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3608" , 0x11800809470c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3609" , 0x11800809470c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3610" , 0x11800809470d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3611" , 0x11800809470d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3612" , 0x11800809470e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3613" , 0x11800809470e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3614" , 0x11800809470f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3615" , 0x11800809470f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3616" , 0x1180080947100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3617" , 0x1180080947108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3618" , 0x1180080947110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3619" , 0x1180080947118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3620" , 0x1180080947120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3621" , 0x1180080947128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3622" , 0x1180080947130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3623" , 0x1180080947138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3624" , 0x1180080947140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3625" , 0x1180080947148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3626" , 0x1180080947150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3627" , 0x1180080947158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3628" , 0x1180080947160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3629" , 0x1180080947168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3630" , 0x1180080947170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3631" , 0x1180080947178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3632" , 0x1180080947180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3633" , 0x1180080947188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3634" , 0x1180080947190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3635" , 0x1180080947198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3636" , 0x11800809471a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3637" , 0x11800809471a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3638" , 0x11800809471b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3639" , 0x11800809471b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3640" , 0x11800809471c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3641" , 0x11800809471c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3642" , 0x11800809471d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3643" , 0x11800809471d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3644" , 0x11800809471e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3645" , 0x11800809471e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3646" , 0x11800809471f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3647" , 0x11800809471f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3648" , 0x1180080947200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3649" , 0x1180080947208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3650" , 0x1180080947210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3651" , 0x1180080947218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3652" , 0x1180080947220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3653" , 0x1180080947228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3654" , 0x1180080947230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3655" , 0x1180080947238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3656" , 0x1180080947240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3657" , 0x1180080947248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3658" , 0x1180080947250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3659" , 0x1180080947258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3660" , 0x1180080947260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3661" , 0x1180080947268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3662" , 0x1180080947270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3663" , 0x1180080947278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3664" , 0x1180080947280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3665" , 0x1180080947288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3666" , 0x1180080947290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3667" , 0x1180080947298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3668" , 0x11800809472a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3669" , 0x11800809472a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3670" , 0x11800809472b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3671" , 0x11800809472b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3672" , 0x11800809472c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3673" , 0x11800809472c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3674" , 0x11800809472d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3675" , 0x11800809472d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3676" , 0x11800809472e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3677" , 0x11800809472e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3678" , 0x11800809472f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3679" , 0x11800809472f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3680" , 0x1180080947300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3681" , 0x1180080947308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3682" , 0x1180080947310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3683" , 0x1180080947318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3684" , 0x1180080947320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3685" , 0x1180080947328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3686" , 0x1180080947330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3687" , 0x1180080947338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3688" , 0x1180080947340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3689" , 0x1180080947348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3690" , 0x1180080947350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3691" , 0x1180080947358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3692" , 0x1180080947360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3693" , 0x1180080947368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3694" , 0x1180080947370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3695" , 0x1180080947378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3696" , 0x1180080947380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3697" , 0x1180080947388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3698" , 0x1180080947390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3699" , 0x1180080947398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3700" , 0x11800809473a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3701" , 0x11800809473a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3702" , 0x11800809473b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3703" , 0x11800809473b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3704" , 0x11800809473c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3705" , 0x11800809473c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3706" , 0x11800809473d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3707" , 0x11800809473d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3708" , 0x11800809473e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3709" , 0x11800809473e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3710" , 0x11800809473f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3711" , 0x11800809473f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3712" , 0x1180080947400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3713" , 0x1180080947408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3714" , 0x1180080947410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3715" , 0x1180080947418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3716" , 0x1180080947420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3717" , 0x1180080947428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3718" , 0x1180080947430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3719" , 0x1180080947438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3720" , 0x1180080947440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3721" , 0x1180080947448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3722" , 0x1180080947450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3723" , 0x1180080947458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3724" , 0x1180080947460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3725" , 0x1180080947468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3726" , 0x1180080947470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3727" , 0x1180080947478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3728" , 0x1180080947480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3729" , 0x1180080947488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3730" , 0x1180080947490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3731" , 0x1180080947498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3732" , 0x11800809474a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3733" , 0x11800809474a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3734" , 0x11800809474b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3735" , 0x11800809474b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3736" , 0x11800809474c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3737" , 0x11800809474c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3738" , 0x11800809474d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3739" , 0x11800809474d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3740" , 0x11800809474e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3741" , 0x11800809474e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3742" , 0x11800809474f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3743" , 0x11800809474f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3744" , 0x1180080947500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3745" , 0x1180080947508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3746" , 0x1180080947510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3747" , 0x1180080947518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3748" , 0x1180080947520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3749" , 0x1180080947528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3750" , 0x1180080947530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3751" , 0x1180080947538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3752" , 0x1180080947540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3753" , 0x1180080947548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3754" , 0x1180080947550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3755" , 0x1180080947558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3756" , 0x1180080947560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3757" , 0x1180080947568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3758" , 0x1180080947570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3759" , 0x1180080947578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3760" , 0x1180080947580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3761" , 0x1180080947588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3762" , 0x1180080947590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3763" , 0x1180080947598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3764" , 0x11800809475a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3765" , 0x11800809475a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3766" , 0x11800809475b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3767" , 0x11800809475b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3768" , 0x11800809475c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3769" , 0x11800809475c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3770" , 0x11800809475d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3771" , 0x11800809475d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3772" , 0x11800809475e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3773" , 0x11800809475e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3774" , 0x11800809475f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3775" , 0x11800809475f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3776" , 0x1180080947600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3777" , 0x1180080947608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3778" , 0x1180080947610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3779" , 0x1180080947618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3780" , 0x1180080947620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3781" , 0x1180080947628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3782" , 0x1180080947630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3783" , 0x1180080947638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3784" , 0x1180080947640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3785" , 0x1180080947648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3786" , 0x1180080947650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3787" , 0x1180080947658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3788" , 0x1180080947660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3789" , 0x1180080947668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3790" , 0x1180080947670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3791" , 0x1180080947678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3792" , 0x1180080947680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3793" , 0x1180080947688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3794" , 0x1180080947690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3795" , 0x1180080947698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3796" , 0x11800809476a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3797" , 0x11800809476a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3798" , 0x11800809476b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3799" , 0x11800809476b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3800" , 0x11800809476c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3801" , 0x11800809476c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3802" , 0x11800809476d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3803" , 0x11800809476d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3804" , 0x11800809476e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3805" , 0x11800809476e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3806" , 0x11800809476f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3807" , 0x11800809476f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3808" , 0x1180080947700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3809" , 0x1180080947708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3810" , 0x1180080947710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3811" , 0x1180080947718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3812" , 0x1180080947720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3813" , 0x1180080947728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3814" , 0x1180080947730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3815" , 0x1180080947738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3816" , 0x1180080947740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3817" , 0x1180080947748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3818" , 0x1180080947750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3819" , 0x1180080947758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3820" , 0x1180080947760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3821" , 0x1180080947768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3822" , 0x1180080947770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3823" , 0x1180080947778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3824" , 0x1180080947780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3825" , 0x1180080947788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3826" , 0x1180080947790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3827" , 0x1180080947798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3828" , 0x11800809477a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3829" , 0x11800809477a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3830" , 0x11800809477b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3831" , 0x11800809477b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3832" , 0x11800809477c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3833" , 0x11800809477c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3834" , 0x11800809477d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3835" , 0x11800809477d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3836" , 0x11800809477e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3837" , 0x11800809477e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3838" , 0x11800809477f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3839" , 0x11800809477f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3840" , 0x1180080947800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3841" , 0x1180080947808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3842" , 0x1180080947810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3843" , 0x1180080947818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3844" , 0x1180080947820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3845" , 0x1180080947828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3846" , 0x1180080947830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3847" , 0x1180080947838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3848" , 0x1180080947840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3849" , 0x1180080947848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3850" , 0x1180080947850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3851" , 0x1180080947858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3852" , 0x1180080947860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3853" , 0x1180080947868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3854" , 0x1180080947870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3855" , 0x1180080947878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3856" , 0x1180080947880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3857" , 0x1180080947888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3858" , 0x1180080947890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3859" , 0x1180080947898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3860" , 0x11800809478a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3861" , 0x11800809478a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3862" , 0x11800809478b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3863" , 0x11800809478b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3864" , 0x11800809478c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3865" , 0x11800809478c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3866" , 0x11800809478d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3867" , 0x11800809478d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3868" , 0x11800809478e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3869" , 0x11800809478e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3870" , 0x11800809478f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3871" , 0x11800809478f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3872" , 0x1180080947900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3873" , 0x1180080947908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3874" , 0x1180080947910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3875" , 0x1180080947918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3876" , 0x1180080947920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3877" , 0x1180080947928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3878" , 0x1180080947930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3879" , 0x1180080947938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3880" , 0x1180080947940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3881" , 0x1180080947948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3882" , 0x1180080947950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3883" , 0x1180080947958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3884" , 0x1180080947960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3885" , 0x1180080947968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3886" , 0x1180080947970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3887" , 0x1180080947978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3888" , 0x1180080947980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3889" , 0x1180080947988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3890" , 0x1180080947990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3891" , 0x1180080947998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3892" , 0x11800809479a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3893" , 0x11800809479a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3894" , 0x11800809479b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3895" , 0x11800809479b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3896" , 0x11800809479c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3897" , 0x11800809479c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3898" , 0x11800809479d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3899" , 0x11800809479d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3900" , 0x11800809479e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3901" , 0x11800809479e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3902" , 0x11800809479f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3903" , 0x11800809479f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3904" , 0x1180080947a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3905" , 0x1180080947a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3906" , 0x1180080947a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3907" , 0x1180080947a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3908" , 0x1180080947a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3909" , 0x1180080947a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3910" , 0x1180080947a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3911" , 0x1180080947a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3912" , 0x1180080947a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3913" , 0x1180080947a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3914" , 0x1180080947a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3915" , 0x1180080947a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3916" , 0x1180080947a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3917" , 0x1180080947a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3918" , 0x1180080947a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3919" , 0x1180080947a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3920" , 0x1180080947a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3921" , 0x1180080947a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3922" , 0x1180080947a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3923" , 0x1180080947a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3924" , 0x1180080947aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3925" , 0x1180080947aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3926" , 0x1180080947ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3927" , 0x1180080947ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3928" , 0x1180080947ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3929" , 0x1180080947ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3930" , 0x1180080947ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3931" , 0x1180080947ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3932" , 0x1180080947ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3933" , 0x1180080947ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3934" , 0x1180080947af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3935" , 0x1180080947af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3936" , 0x1180080947b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3937" , 0x1180080947b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3938" , 0x1180080947b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3939" , 0x1180080947b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3940" , 0x1180080947b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3941" , 0x1180080947b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3942" , 0x1180080947b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3943" , 0x1180080947b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3944" , 0x1180080947b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3945" , 0x1180080947b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3946" , 0x1180080947b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3947" , 0x1180080947b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3948" , 0x1180080947b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3949" , 0x1180080947b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3950" , 0x1180080947b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3951" , 0x1180080947b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3952" , 0x1180080947b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3953" , 0x1180080947b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3954" , 0x1180080947b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3955" , 0x1180080947b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3956" , 0x1180080947ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3957" , 0x1180080947ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3958" , 0x1180080947bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3959" , 0x1180080947bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3960" , 0x1180080947bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3961" , 0x1180080947bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3962" , 0x1180080947bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3963" , 0x1180080947bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3964" , 0x1180080947be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3965" , 0x1180080947be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3966" , 0x1180080947bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3967" , 0x1180080947bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3968" , 0x1180080947c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3969" , 0x1180080947c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3970" , 0x1180080947c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3971" , 0x1180080947c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3972" , 0x1180080947c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3973" , 0x1180080947c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3974" , 0x1180080947c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3975" , 0x1180080947c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3976" , 0x1180080947c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3977" , 0x1180080947c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3978" , 0x1180080947c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3979" , 0x1180080947c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3980" , 0x1180080947c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3981" , 0x1180080947c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3982" , 0x1180080947c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3983" , 0x1180080947c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3984" , 0x1180080947c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3985" , 0x1180080947c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3986" , 0x1180080947c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3987" , 0x1180080947c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3988" , 0x1180080947ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3989" , 0x1180080947ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3990" , 0x1180080947cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3991" , 0x1180080947cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3992" , 0x1180080947cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3993" , 0x1180080947cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3994" , 0x1180080947cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3995" , 0x1180080947cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3996" , 0x1180080947ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3997" , 0x1180080947ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3998" , 0x1180080947cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP3999" , 0x1180080947cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4000" , 0x1180080947d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4001" , 0x1180080947d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4002" , 0x1180080947d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4003" , 0x1180080947d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4004" , 0x1180080947d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4005" , 0x1180080947d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4006" , 0x1180080947d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4007" , 0x1180080947d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4008" , 0x1180080947d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4009" , 0x1180080947d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4010" , 0x1180080947d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4011" , 0x1180080947d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4012" , 0x1180080947d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4013" , 0x1180080947d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4014" , 0x1180080947d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4015" , 0x1180080947d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4016" , 0x1180080947d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4017" , 0x1180080947d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4018" , 0x1180080947d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4019" , 0x1180080947d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4020" , 0x1180080947da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4021" , 0x1180080947da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4022" , 0x1180080947db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4023" , 0x1180080947db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4024" , 0x1180080947dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4025" , 0x1180080947dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4026" , 0x1180080947dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4027" , 0x1180080947dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4028" , 0x1180080947de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4029" , 0x1180080947de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4030" , 0x1180080947df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4031" , 0x1180080947df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4032" , 0x1180080947e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4033" , 0x1180080947e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4034" , 0x1180080947e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4035" , 0x1180080947e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4036" , 0x1180080947e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4037" , 0x1180080947e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4038" , 0x1180080947e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4039" , 0x1180080947e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4040" , 0x1180080947e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4041" , 0x1180080947e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4042" , 0x1180080947e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4043" , 0x1180080947e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4044" , 0x1180080947e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4045" , 0x1180080947e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4046" , 0x1180080947e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4047" , 0x1180080947e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4048" , 0x1180080947e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4049" , 0x1180080947e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4050" , 0x1180080947e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4051" , 0x1180080947e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4052" , 0x1180080947ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4053" , 0x1180080947ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4054" , 0x1180080947eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4055" , 0x1180080947eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4056" , 0x1180080947ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4057" , 0x1180080947ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4058" , 0x1180080947ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4059" , 0x1180080947ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4060" , 0x1180080947ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4061" , 0x1180080947ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4062" , 0x1180080947ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4063" , 0x1180080947ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4064" , 0x1180080947f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4065" , 0x1180080947f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4066" , 0x1180080947f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4067" , 0x1180080947f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4068" , 0x1180080947f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4069" , 0x1180080947f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4070" , 0x1180080947f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4071" , 0x1180080947f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4072" , 0x1180080947f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4073" , 0x1180080947f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4074" , 0x1180080947f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4075" , 0x1180080947f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4076" , 0x1180080947f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4077" , 0x1180080947f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4078" , 0x1180080947f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4079" , 0x1180080947f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4080" , 0x1180080947f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4081" , 0x1180080947f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4082" , 0x1180080947f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4083" , 0x1180080947f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4084" , 0x1180080947fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4085" , 0x1180080947fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4086" , 0x1180080947fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4087" , 0x1180080947fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4088" , 0x1180080947fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4089" , 0x1180080947fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4090" , 0x1180080947fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4091" , 0x1180080947fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4092" , 0x1180080947fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4093" , 0x1180080947fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4094" , 0x1180080947ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4095" , 0x1180080947ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4096" , 0x1180080948000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4097" , 0x1180080948008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4098" , 0x1180080948010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4099" , 0x1180080948018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4100" , 0x1180080948020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4101" , 0x1180080948028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4102" , 0x1180080948030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4103" , 0x1180080948038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4104" , 0x1180080948040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4105" , 0x1180080948048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4106" , 0x1180080948050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4107" , 0x1180080948058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4108" , 0x1180080948060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4109" , 0x1180080948068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4110" , 0x1180080948070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4111" , 0x1180080948078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4112" , 0x1180080948080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4113" , 0x1180080948088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4114" , 0x1180080948090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4115" , 0x1180080948098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4116" , 0x11800809480a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4117" , 0x11800809480a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4118" , 0x11800809480b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4119" , 0x11800809480b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4120" , 0x11800809480c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4121" , 0x11800809480c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4122" , 0x11800809480d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4123" , 0x11800809480d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4124" , 0x11800809480e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4125" , 0x11800809480e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4126" , 0x11800809480f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4127" , 0x11800809480f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4128" , 0x1180080948100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4129" , 0x1180080948108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4130" , 0x1180080948110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4131" , 0x1180080948118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4132" , 0x1180080948120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4133" , 0x1180080948128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4134" , 0x1180080948130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4135" , 0x1180080948138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4136" , 0x1180080948140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4137" , 0x1180080948148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4138" , 0x1180080948150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4139" , 0x1180080948158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4140" , 0x1180080948160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4141" , 0x1180080948168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4142" , 0x1180080948170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4143" , 0x1180080948178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4144" , 0x1180080948180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4145" , 0x1180080948188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4146" , 0x1180080948190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4147" , 0x1180080948198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4148" , 0x11800809481a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4149" , 0x11800809481a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4150" , 0x11800809481b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4151" , 0x11800809481b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4152" , 0x11800809481c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4153" , 0x11800809481c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4154" , 0x11800809481d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4155" , 0x11800809481d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4156" , 0x11800809481e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4157" , 0x11800809481e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4158" , 0x11800809481f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4159" , 0x11800809481f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4160" , 0x1180080948200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4161" , 0x1180080948208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4162" , 0x1180080948210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4163" , 0x1180080948218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4164" , 0x1180080948220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4165" , 0x1180080948228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4166" , 0x1180080948230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4167" , 0x1180080948238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4168" , 0x1180080948240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4169" , 0x1180080948248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4170" , 0x1180080948250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4171" , 0x1180080948258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4172" , 0x1180080948260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4173" , 0x1180080948268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4174" , 0x1180080948270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4175" , 0x1180080948278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4176" , 0x1180080948280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4177" , 0x1180080948288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4178" , 0x1180080948290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4179" , 0x1180080948298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4180" , 0x11800809482a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4181" , 0x11800809482a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4182" , 0x11800809482b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4183" , 0x11800809482b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4184" , 0x11800809482c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4185" , 0x11800809482c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4186" , 0x11800809482d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4187" , 0x11800809482d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4188" , 0x11800809482e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4189" , 0x11800809482e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4190" , 0x11800809482f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4191" , 0x11800809482f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4192" , 0x1180080948300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4193" , 0x1180080948308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4194" , 0x1180080948310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4195" , 0x1180080948318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4196" , 0x1180080948320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4197" , 0x1180080948328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4198" , 0x1180080948330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4199" , 0x1180080948338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4200" , 0x1180080948340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4201" , 0x1180080948348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4202" , 0x1180080948350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4203" , 0x1180080948358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4204" , 0x1180080948360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4205" , 0x1180080948368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4206" , 0x1180080948370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4207" , 0x1180080948378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4208" , 0x1180080948380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4209" , 0x1180080948388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4210" , 0x1180080948390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4211" , 0x1180080948398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4212" , 0x11800809483a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4213" , 0x11800809483a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4214" , 0x11800809483b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4215" , 0x11800809483b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4216" , 0x11800809483c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4217" , 0x11800809483c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4218" , 0x11800809483d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4219" , 0x11800809483d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4220" , 0x11800809483e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4221" , 0x11800809483e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4222" , 0x11800809483f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4223" , 0x11800809483f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4224" , 0x1180080948400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4225" , 0x1180080948408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4226" , 0x1180080948410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4227" , 0x1180080948418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4228" , 0x1180080948420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4229" , 0x1180080948428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4230" , 0x1180080948430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4231" , 0x1180080948438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4232" , 0x1180080948440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4233" , 0x1180080948448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4234" , 0x1180080948450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4235" , 0x1180080948458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4236" , 0x1180080948460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4237" , 0x1180080948468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4238" , 0x1180080948470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4239" , 0x1180080948478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4240" , 0x1180080948480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4241" , 0x1180080948488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4242" , 0x1180080948490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4243" , 0x1180080948498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4244" , 0x11800809484a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4245" , 0x11800809484a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4246" , 0x11800809484b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4247" , 0x11800809484b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4248" , 0x11800809484c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4249" , 0x11800809484c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4250" , 0x11800809484d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4251" , 0x11800809484d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4252" , 0x11800809484e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4253" , 0x11800809484e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4254" , 0x11800809484f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4255" , 0x11800809484f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4256" , 0x1180080948500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4257" , 0x1180080948508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4258" , 0x1180080948510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4259" , 0x1180080948518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4260" , 0x1180080948520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4261" , 0x1180080948528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4262" , 0x1180080948530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4263" , 0x1180080948538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4264" , 0x1180080948540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4265" , 0x1180080948548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4266" , 0x1180080948550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4267" , 0x1180080948558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4268" , 0x1180080948560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4269" , 0x1180080948568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4270" , 0x1180080948570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4271" , 0x1180080948578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4272" , 0x1180080948580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4273" , 0x1180080948588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4274" , 0x1180080948590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4275" , 0x1180080948598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4276" , 0x11800809485a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4277" , 0x11800809485a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4278" , 0x11800809485b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4279" , 0x11800809485b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4280" , 0x11800809485c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4281" , 0x11800809485c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4282" , 0x11800809485d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4283" , 0x11800809485d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4284" , 0x11800809485e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4285" , 0x11800809485e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4286" , 0x11800809485f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4287" , 0x11800809485f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4288" , 0x1180080948600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4289" , 0x1180080948608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4290" , 0x1180080948610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4291" , 0x1180080948618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4292" , 0x1180080948620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4293" , 0x1180080948628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4294" , 0x1180080948630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4295" , 0x1180080948638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4296" , 0x1180080948640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4297" , 0x1180080948648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4298" , 0x1180080948650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4299" , 0x1180080948658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4300" , 0x1180080948660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4301" , 0x1180080948668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4302" , 0x1180080948670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4303" , 0x1180080948678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4304" , 0x1180080948680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4305" , 0x1180080948688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4306" , 0x1180080948690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4307" , 0x1180080948698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4308" , 0x11800809486a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4309" , 0x11800809486a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4310" , 0x11800809486b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4311" , 0x11800809486b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4312" , 0x11800809486c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4313" , 0x11800809486c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4314" , 0x11800809486d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4315" , 0x11800809486d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4316" , 0x11800809486e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4317" , 0x11800809486e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4318" , 0x11800809486f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4319" , 0x11800809486f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4320" , 0x1180080948700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4321" , 0x1180080948708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4322" , 0x1180080948710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4323" , 0x1180080948718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4324" , 0x1180080948720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4325" , 0x1180080948728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4326" , 0x1180080948730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4327" , 0x1180080948738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4328" , 0x1180080948740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4329" , 0x1180080948748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4330" , 0x1180080948750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4331" , 0x1180080948758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4332" , 0x1180080948760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4333" , 0x1180080948768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4334" , 0x1180080948770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4335" , 0x1180080948778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4336" , 0x1180080948780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4337" , 0x1180080948788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4338" , 0x1180080948790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4339" , 0x1180080948798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4340" , 0x11800809487a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4341" , 0x11800809487a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4342" , 0x11800809487b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4343" , 0x11800809487b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4344" , 0x11800809487c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4345" , 0x11800809487c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4346" , 0x11800809487d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4347" , 0x11800809487d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4348" , 0x11800809487e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4349" , 0x11800809487e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4350" , 0x11800809487f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4351" , 0x11800809487f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4352" , 0x1180080948800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4353" , 0x1180080948808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4354" , 0x1180080948810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4355" , 0x1180080948818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4356" , 0x1180080948820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4357" , 0x1180080948828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4358" , 0x1180080948830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4359" , 0x1180080948838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4360" , 0x1180080948840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4361" , 0x1180080948848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4362" , 0x1180080948850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4363" , 0x1180080948858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4364" , 0x1180080948860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4365" , 0x1180080948868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4366" , 0x1180080948870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4367" , 0x1180080948878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4368" , 0x1180080948880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4369" , 0x1180080948888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4370" , 0x1180080948890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4371" , 0x1180080948898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4372" , 0x11800809488a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4373" , 0x11800809488a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4374" , 0x11800809488b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4375" , 0x11800809488b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4376" , 0x11800809488c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4377" , 0x11800809488c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4378" , 0x11800809488d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4379" , 0x11800809488d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4380" , 0x11800809488e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4381" , 0x11800809488e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4382" , 0x11800809488f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4383" , 0x11800809488f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4384" , 0x1180080948900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4385" , 0x1180080948908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4386" , 0x1180080948910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4387" , 0x1180080948918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4388" , 0x1180080948920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4389" , 0x1180080948928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4390" , 0x1180080948930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4391" , 0x1180080948938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4392" , 0x1180080948940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4393" , 0x1180080948948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4394" , 0x1180080948950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4395" , 0x1180080948958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4396" , 0x1180080948960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4397" , 0x1180080948968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4398" , 0x1180080948970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4399" , 0x1180080948978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4400" , 0x1180080948980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4401" , 0x1180080948988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4402" , 0x1180080948990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4403" , 0x1180080948998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4404" , 0x11800809489a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4405" , 0x11800809489a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4406" , 0x11800809489b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4407" , 0x11800809489b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4408" , 0x11800809489c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4409" , 0x11800809489c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4410" , 0x11800809489d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4411" , 0x11800809489d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4412" , 0x11800809489e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4413" , 0x11800809489e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4414" , 0x11800809489f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4415" , 0x11800809489f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4416" , 0x1180080948a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4417" , 0x1180080948a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4418" , 0x1180080948a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4419" , 0x1180080948a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4420" , 0x1180080948a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4421" , 0x1180080948a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4422" , 0x1180080948a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4423" , 0x1180080948a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4424" , 0x1180080948a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4425" , 0x1180080948a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4426" , 0x1180080948a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4427" , 0x1180080948a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4428" , 0x1180080948a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4429" , 0x1180080948a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4430" , 0x1180080948a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4431" , 0x1180080948a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4432" , 0x1180080948a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4433" , 0x1180080948a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4434" , 0x1180080948a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4435" , 0x1180080948a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4436" , 0x1180080948aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4437" , 0x1180080948aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4438" , 0x1180080948ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4439" , 0x1180080948ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4440" , 0x1180080948ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4441" , 0x1180080948ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4442" , 0x1180080948ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4443" , 0x1180080948ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4444" , 0x1180080948ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4445" , 0x1180080948ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4446" , 0x1180080948af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4447" , 0x1180080948af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4448" , 0x1180080948b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4449" , 0x1180080948b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4450" , 0x1180080948b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4451" , 0x1180080948b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4452" , 0x1180080948b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4453" , 0x1180080948b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4454" , 0x1180080948b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4455" , 0x1180080948b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4456" , 0x1180080948b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4457" , 0x1180080948b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4458" , 0x1180080948b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4459" , 0x1180080948b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4460" , 0x1180080948b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4461" , 0x1180080948b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4462" , 0x1180080948b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4463" , 0x1180080948b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4464" , 0x1180080948b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4465" , 0x1180080948b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4466" , 0x1180080948b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4467" , 0x1180080948b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4468" , 0x1180080948ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4469" , 0x1180080948ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4470" , 0x1180080948bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4471" , 0x1180080948bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4472" , 0x1180080948bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4473" , 0x1180080948bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4474" , 0x1180080948bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4475" , 0x1180080948bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4476" , 0x1180080948be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4477" , 0x1180080948be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4478" , 0x1180080948bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4479" , 0x1180080948bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4480" , 0x1180080948c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4481" , 0x1180080948c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4482" , 0x1180080948c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4483" , 0x1180080948c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4484" , 0x1180080948c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4485" , 0x1180080948c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4486" , 0x1180080948c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4487" , 0x1180080948c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4488" , 0x1180080948c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4489" , 0x1180080948c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4490" , 0x1180080948c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4491" , 0x1180080948c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4492" , 0x1180080948c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4493" , 0x1180080948c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4494" , 0x1180080948c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4495" , 0x1180080948c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4496" , 0x1180080948c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4497" , 0x1180080948c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4498" , 0x1180080948c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4499" , 0x1180080948c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4500" , 0x1180080948ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4501" , 0x1180080948ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4502" , 0x1180080948cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4503" , 0x1180080948cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4504" , 0x1180080948cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4505" , 0x1180080948cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4506" , 0x1180080948cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4507" , 0x1180080948cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4508" , 0x1180080948ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4509" , 0x1180080948ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4510" , 0x1180080948cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4511" , 0x1180080948cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4512" , 0x1180080948d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4513" , 0x1180080948d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4514" , 0x1180080948d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4515" , 0x1180080948d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4516" , 0x1180080948d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4517" , 0x1180080948d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4518" , 0x1180080948d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4519" , 0x1180080948d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4520" , 0x1180080948d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4521" , 0x1180080948d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4522" , 0x1180080948d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4523" , 0x1180080948d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4524" , 0x1180080948d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4525" , 0x1180080948d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4526" , 0x1180080948d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4527" , 0x1180080948d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4528" , 0x1180080948d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4529" , 0x1180080948d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4530" , 0x1180080948d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4531" , 0x1180080948d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4532" , 0x1180080948da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4533" , 0x1180080948da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4534" , 0x1180080948db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4535" , 0x1180080948db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4536" , 0x1180080948dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4537" , 0x1180080948dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4538" , 0x1180080948dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4539" , 0x1180080948dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4540" , 0x1180080948de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4541" , 0x1180080948de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4542" , 0x1180080948df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4543" , 0x1180080948df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4544" , 0x1180080948e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4545" , 0x1180080948e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4546" , 0x1180080948e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4547" , 0x1180080948e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4548" , 0x1180080948e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4549" , 0x1180080948e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4550" , 0x1180080948e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4551" , 0x1180080948e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4552" , 0x1180080948e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4553" , 0x1180080948e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4554" , 0x1180080948e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4555" , 0x1180080948e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4556" , 0x1180080948e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4557" , 0x1180080948e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4558" , 0x1180080948e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4559" , 0x1180080948e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4560" , 0x1180080948e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4561" , 0x1180080948e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4562" , 0x1180080948e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4563" , 0x1180080948e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4564" , 0x1180080948ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4565" , 0x1180080948ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4566" , 0x1180080948eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4567" , 0x1180080948eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4568" , 0x1180080948ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4569" , 0x1180080948ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4570" , 0x1180080948ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4571" , 0x1180080948ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4572" , 0x1180080948ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4573" , 0x1180080948ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4574" , 0x1180080948ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4575" , 0x1180080948ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4576" , 0x1180080948f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4577" , 0x1180080948f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4578" , 0x1180080948f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4579" , 0x1180080948f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4580" , 0x1180080948f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4581" , 0x1180080948f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4582" , 0x1180080948f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4583" , 0x1180080948f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4584" , 0x1180080948f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4585" , 0x1180080948f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4586" , 0x1180080948f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4587" , 0x1180080948f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4588" , 0x1180080948f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4589" , 0x1180080948f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4590" , 0x1180080948f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4591" , 0x1180080948f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4592" , 0x1180080948f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4593" , 0x1180080948f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4594" , 0x1180080948f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4595" , 0x1180080948f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4596" , 0x1180080948fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4597" , 0x1180080948fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4598" , 0x1180080948fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4599" , 0x1180080948fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4600" , 0x1180080948fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4601" , 0x1180080948fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4602" , 0x1180080948fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4603" , 0x1180080948fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4604" , 0x1180080948fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4605" , 0x1180080948fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4606" , 0x1180080948ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4607" , 0x1180080948ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4608" , 0x1180080949000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4609" , 0x1180080949008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4610" , 0x1180080949010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4611" , 0x1180080949018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4612" , 0x1180080949020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4613" , 0x1180080949028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4614" , 0x1180080949030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4615" , 0x1180080949038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4616" , 0x1180080949040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4617" , 0x1180080949048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4618" , 0x1180080949050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4619" , 0x1180080949058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4620" , 0x1180080949060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4621" , 0x1180080949068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4622" , 0x1180080949070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4623" , 0x1180080949078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4624" , 0x1180080949080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4625" , 0x1180080949088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4626" , 0x1180080949090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4627" , 0x1180080949098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4628" , 0x11800809490a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4629" , 0x11800809490a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4630" , 0x11800809490b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4631" , 0x11800809490b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4632" , 0x11800809490c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4633" , 0x11800809490c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4634" , 0x11800809490d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4635" , 0x11800809490d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4636" , 0x11800809490e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4637" , 0x11800809490e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4638" , 0x11800809490f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4639" , 0x11800809490f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4640" , 0x1180080949100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4641" , 0x1180080949108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4642" , 0x1180080949110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4643" , 0x1180080949118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4644" , 0x1180080949120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4645" , 0x1180080949128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4646" , 0x1180080949130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4647" , 0x1180080949138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4648" , 0x1180080949140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4649" , 0x1180080949148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4650" , 0x1180080949150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4651" , 0x1180080949158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4652" , 0x1180080949160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4653" , 0x1180080949168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4654" , 0x1180080949170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4655" , 0x1180080949178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4656" , 0x1180080949180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4657" , 0x1180080949188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4658" , 0x1180080949190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4659" , 0x1180080949198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4660" , 0x11800809491a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4661" , 0x11800809491a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4662" , 0x11800809491b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4663" , 0x11800809491b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4664" , 0x11800809491c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4665" , 0x11800809491c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4666" , 0x11800809491d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4667" , 0x11800809491d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4668" , 0x11800809491e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4669" , 0x11800809491e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4670" , 0x11800809491f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4671" , 0x11800809491f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4672" , 0x1180080949200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4673" , 0x1180080949208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4674" , 0x1180080949210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4675" , 0x1180080949218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4676" , 0x1180080949220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4677" , 0x1180080949228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4678" , 0x1180080949230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4679" , 0x1180080949238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4680" , 0x1180080949240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4681" , 0x1180080949248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4682" , 0x1180080949250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4683" , 0x1180080949258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4684" , 0x1180080949260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4685" , 0x1180080949268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4686" , 0x1180080949270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4687" , 0x1180080949278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4688" , 0x1180080949280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4689" , 0x1180080949288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4690" , 0x1180080949290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4691" , 0x1180080949298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4692" , 0x11800809492a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4693" , 0x11800809492a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4694" , 0x11800809492b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4695" , 0x11800809492b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4696" , 0x11800809492c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4697" , 0x11800809492c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4698" , 0x11800809492d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4699" , 0x11800809492d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4700" , 0x11800809492e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4701" , 0x11800809492e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4702" , 0x11800809492f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4703" , 0x11800809492f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4704" , 0x1180080949300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4705" , 0x1180080949308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4706" , 0x1180080949310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4707" , 0x1180080949318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4708" , 0x1180080949320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4709" , 0x1180080949328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4710" , 0x1180080949330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4711" , 0x1180080949338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4712" , 0x1180080949340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4713" , 0x1180080949348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4714" , 0x1180080949350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4715" , 0x1180080949358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4716" , 0x1180080949360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4717" , 0x1180080949368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4718" , 0x1180080949370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4719" , 0x1180080949378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4720" , 0x1180080949380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4721" , 0x1180080949388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4722" , 0x1180080949390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4723" , 0x1180080949398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4724" , 0x11800809493a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4725" , 0x11800809493a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4726" , 0x11800809493b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4727" , 0x11800809493b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4728" , 0x11800809493c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4729" , 0x11800809493c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4730" , 0x11800809493d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4731" , 0x11800809493d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4732" , 0x11800809493e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4733" , 0x11800809493e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4734" , 0x11800809493f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4735" , 0x11800809493f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4736" , 0x1180080949400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4737" , 0x1180080949408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4738" , 0x1180080949410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4739" , 0x1180080949418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4740" , 0x1180080949420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4741" , 0x1180080949428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4742" , 0x1180080949430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4743" , 0x1180080949438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4744" , 0x1180080949440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4745" , 0x1180080949448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4746" , 0x1180080949450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4747" , 0x1180080949458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4748" , 0x1180080949460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4749" , 0x1180080949468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4750" , 0x1180080949470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4751" , 0x1180080949478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4752" , 0x1180080949480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4753" , 0x1180080949488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4754" , 0x1180080949490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4755" , 0x1180080949498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4756" , 0x11800809494a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4757" , 0x11800809494a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4758" , 0x11800809494b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4759" , 0x11800809494b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4760" , 0x11800809494c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4761" , 0x11800809494c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4762" , 0x11800809494d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4763" , 0x11800809494d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4764" , 0x11800809494e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4765" , 0x11800809494e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4766" , 0x11800809494f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4767" , 0x11800809494f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4768" , 0x1180080949500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4769" , 0x1180080949508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4770" , 0x1180080949510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4771" , 0x1180080949518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4772" , 0x1180080949520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4773" , 0x1180080949528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4774" , 0x1180080949530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4775" , 0x1180080949538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4776" , 0x1180080949540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4777" , 0x1180080949548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4778" , 0x1180080949550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4779" , 0x1180080949558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4780" , 0x1180080949560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4781" , 0x1180080949568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4782" , 0x1180080949570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4783" , 0x1180080949578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4784" , 0x1180080949580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4785" , 0x1180080949588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4786" , 0x1180080949590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4787" , 0x1180080949598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4788" , 0x11800809495a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4789" , 0x11800809495a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4790" , 0x11800809495b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4791" , 0x11800809495b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4792" , 0x11800809495c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4793" , 0x11800809495c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4794" , 0x11800809495d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4795" , 0x11800809495d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4796" , 0x11800809495e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4797" , 0x11800809495e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4798" , 0x11800809495f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4799" , 0x11800809495f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4800" , 0x1180080949600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4801" , 0x1180080949608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4802" , 0x1180080949610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4803" , 0x1180080949618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4804" , 0x1180080949620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4805" , 0x1180080949628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4806" , 0x1180080949630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4807" , 0x1180080949638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4808" , 0x1180080949640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4809" , 0x1180080949648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4810" , 0x1180080949650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4811" , 0x1180080949658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4812" , 0x1180080949660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4813" , 0x1180080949668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4814" , 0x1180080949670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4815" , 0x1180080949678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4816" , 0x1180080949680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4817" , 0x1180080949688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4818" , 0x1180080949690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4819" , 0x1180080949698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4820" , 0x11800809496a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4821" , 0x11800809496a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4822" , 0x11800809496b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4823" , 0x11800809496b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4824" , 0x11800809496c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4825" , 0x11800809496c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4826" , 0x11800809496d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4827" , 0x11800809496d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4828" , 0x11800809496e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4829" , 0x11800809496e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4830" , 0x11800809496f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4831" , 0x11800809496f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4832" , 0x1180080949700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4833" , 0x1180080949708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4834" , 0x1180080949710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4835" , 0x1180080949718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4836" , 0x1180080949720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4837" , 0x1180080949728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4838" , 0x1180080949730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4839" , 0x1180080949738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4840" , 0x1180080949740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4841" , 0x1180080949748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4842" , 0x1180080949750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4843" , 0x1180080949758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4844" , 0x1180080949760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4845" , 0x1180080949768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4846" , 0x1180080949770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4847" , 0x1180080949778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4848" , 0x1180080949780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4849" , 0x1180080949788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4850" , 0x1180080949790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4851" , 0x1180080949798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4852" , 0x11800809497a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4853" , 0x11800809497a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4854" , 0x11800809497b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4855" , 0x11800809497b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4856" , 0x11800809497c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4857" , 0x11800809497c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4858" , 0x11800809497d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4859" , 0x11800809497d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4860" , 0x11800809497e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4861" , 0x11800809497e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4862" , 0x11800809497f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4863" , 0x11800809497f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4864" , 0x1180080949800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4865" , 0x1180080949808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4866" , 0x1180080949810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4867" , 0x1180080949818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4868" , 0x1180080949820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4869" , 0x1180080949828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4870" , 0x1180080949830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4871" , 0x1180080949838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4872" , 0x1180080949840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4873" , 0x1180080949848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4874" , 0x1180080949850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4875" , 0x1180080949858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4876" , 0x1180080949860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4877" , 0x1180080949868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4878" , 0x1180080949870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4879" , 0x1180080949878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4880" , 0x1180080949880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4881" , 0x1180080949888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4882" , 0x1180080949890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4883" , 0x1180080949898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4884" , 0x11800809498a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4885" , 0x11800809498a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4886" , 0x11800809498b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4887" , 0x11800809498b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4888" , 0x11800809498c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4889" , 0x11800809498c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4890" , 0x11800809498d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4891" , 0x11800809498d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4892" , 0x11800809498e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4893" , 0x11800809498e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4894" , 0x11800809498f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4895" , 0x11800809498f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4896" , 0x1180080949900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4897" , 0x1180080949908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4898" , 0x1180080949910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4899" , 0x1180080949918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4900" , 0x1180080949920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4901" , 0x1180080949928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4902" , 0x1180080949930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4903" , 0x1180080949938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4904" , 0x1180080949940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4905" , 0x1180080949948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4906" , 0x1180080949950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4907" , 0x1180080949958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4908" , 0x1180080949960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4909" , 0x1180080949968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4910" , 0x1180080949970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4911" , 0x1180080949978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4912" , 0x1180080949980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4913" , 0x1180080949988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4914" , 0x1180080949990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4915" , 0x1180080949998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4916" , 0x11800809499a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4917" , 0x11800809499a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4918" , 0x11800809499b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4919" , 0x11800809499b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4920" , 0x11800809499c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4921" , 0x11800809499c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4922" , 0x11800809499d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4923" , 0x11800809499d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4924" , 0x11800809499e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4925" , 0x11800809499e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4926" , 0x11800809499f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4927" , 0x11800809499f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4928" , 0x1180080949a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4929" , 0x1180080949a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4930" , 0x1180080949a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4931" , 0x1180080949a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4932" , 0x1180080949a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4933" , 0x1180080949a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4934" , 0x1180080949a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4935" , 0x1180080949a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4936" , 0x1180080949a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4937" , 0x1180080949a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4938" , 0x1180080949a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4939" , 0x1180080949a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4940" , 0x1180080949a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4941" , 0x1180080949a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4942" , 0x1180080949a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4943" , 0x1180080949a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4944" , 0x1180080949a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4945" , 0x1180080949a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4946" , 0x1180080949a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4947" , 0x1180080949a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4948" , 0x1180080949aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4949" , 0x1180080949aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4950" , 0x1180080949ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4951" , 0x1180080949ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4952" , 0x1180080949ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4953" , 0x1180080949ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4954" , 0x1180080949ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4955" , 0x1180080949ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4956" , 0x1180080949ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4957" , 0x1180080949ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4958" , 0x1180080949af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4959" , 0x1180080949af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4960" , 0x1180080949b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4961" , 0x1180080949b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4962" , 0x1180080949b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4963" , 0x1180080949b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4964" , 0x1180080949b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4965" , 0x1180080949b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4966" , 0x1180080949b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4967" , 0x1180080949b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4968" , 0x1180080949b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4969" , 0x1180080949b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4970" , 0x1180080949b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4971" , 0x1180080949b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4972" , 0x1180080949b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4973" , 0x1180080949b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4974" , 0x1180080949b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4975" , 0x1180080949b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4976" , 0x1180080949b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4977" , 0x1180080949b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4978" , 0x1180080949b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4979" , 0x1180080949b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4980" , 0x1180080949ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4981" , 0x1180080949ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4982" , 0x1180080949bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4983" , 0x1180080949bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4984" , 0x1180080949bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4985" , 0x1180080949bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4986" , 0x1180080949bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4987" , 0x1180080949bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4988" , 0x1180080949be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4989" , 0x1180080949be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4990" , 0x1180080949bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4991" , 0x1180080949bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4992" , 0x1180080949c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4993" , 0x1180080949c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4994" , 0x1180080949c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4995" , 0x1180080949c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4996" , 0x1180080949c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4997" , 0x1180080949c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4998" , 0x1180080949c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP4999" , 0x1180080949c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5000" , 0x1180080949c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5001" , 0x1180080949c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5002" , 0x1180080949c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5003" , 0x1180080949c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5004" , 0x1180080949c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5005" , 0x1180080949c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5006" , 0x1180080949c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5007" , 0x1180080949c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5008" , 0x1180080949c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5009" , 0x1180080949c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5010" , 0x1180080949c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5011" , 0x1180080949c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5012" , 0x1180080949ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5013" , 0x1180080949ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5014" , 0x1180080949cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5015" , 0x1180080949cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5016" , 0x1180080949cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5017" , 0x1180080949cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5018" , 0x1180080949cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5019" , 0x1180080949cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5020" , 0x1180080949ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5021" , 0x1180080949ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5022" , 0x1180080949cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5023" , 0x1180080949cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5024" , 0x1180080949d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5025" , 0x1180080949d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5026" , 0x1180080949d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5027" , 0x1180080949d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5028" , 0x1180080949d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5029" , 0x1180080949d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5030" , 0x1180080949d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5031" , 0x1180080949d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5032" , 0x1180080949d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5033" , 0x1180080949d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5034" , 0x1180080949d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5035" , 0x1180080949d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5036" , 0x1180080949d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5037" , 0x1180080949d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5038" , 0x1180080949d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5039" , 0x1180080949d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5040" , 0x1180080949d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5041" , 0x1180080949d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5042" , 0x1180080949d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5043" , 0x1180080949d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5044" , 0x1180080949da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5045" , 0x1180080949da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5046" , 0x1180080949db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5047" , 0x1180080949db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5048" , 0x1180080949dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5049" , 0x1180080949dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5050" , 0x1180080949dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5051" , 0x1180080949dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5052" , 0x1180080949de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5053" , 0x1180080949de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5054" , 0x1180080949df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5055" , 0x1180080949df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5056" , 0x1180080949e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5057" , 0x1180080949e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5058" , 0x1180080949e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5059" , 0x1180080949e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5060" , 0x1180080949e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5061" , 0x1180080949e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5062" , 0x1180080949e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5063" , 0x1180080949e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5064" , 0x1180080949e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5065" , 0x1180080949e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5066" , 0x1180080949e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5067" , 0x1180080949e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5068" , 0x1180080949e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5069" , 0x1180080949e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5070" , 0x1180080949e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5071" , 0x1180080949e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5072" , 0x1180080949e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5073" , 0x1180080949e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5074" , 0x1180080949e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5075" , 0x1180080949e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5076" , 0x1180080949ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5077" , 0x1180080949ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5078" , 0x1180080949eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5079" , 0x1180080949eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5080" , 0x1180080949ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5081" , 0x1180080949ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5082" , 0x1180080949ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5083" , 0x1180080949ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5084" , 0x1180080949ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5085" , 0x1180080949ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5086" , 0x1180080949ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5087" , 0x1180080949ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5088" , 0x1180080949f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5089" , 0x1180080949f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5090" , 0x1180080949f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5091" , 0x1180080949f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5092" , 0x1180080949f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5093" , 0x1180080949f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5094" , 0x1180080949f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5095" , 0x1180080949f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5096" , 0x1180080949f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5097" , 0x1180080949f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5098" , 0x1180080949f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5099" , 0x1180080949f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5100" , 0x1180080949f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5101" , 0x1180080949f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5102" , 0x1180080949f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5103" , 0x1180080949f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5104" , 0x1180080949f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5105" , 0x1180080949f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5106" , 0x1180080949f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5107" , 0x1180080949f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5108" , 0x1180080949fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5109" , 0x1180080949fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5110" , 0x1180080949fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5111" , 0x1180080949fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5112" , 0x1180080949fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5113" , 0x1180080949fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5114" , 0x1180080949fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5115" , 0x1180080949fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5116" , 0x1180080949fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5117" , 0x1180080949fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5118" , 0x1180080949ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5119" , 0x1180080949ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5120" , 0x118008094a000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5121" , 0x118008094a008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5122" , 0x118008094a010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5123" , 0x118008094a018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5124" , 0x118008094a020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5125" , 0x118008094a028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5126" , 0x118008094a030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5127" , 0x118008094a038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5128" , 0x118008094a040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5129" , 0x118008094a048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5130" , 0x118008094a050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5131" , 0x118008094a058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5132" , 0x118008094a060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5133" , 0x118008094a068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5134" , 0x118008094a070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5135" , 0x118008094a078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5136" , 0x118008094a080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5137" , 0x118008094a088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5138" , 0x118008094a090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5139" , 0x118008094a098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5140" , 0x118008094a0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5141" , 0x118008094a0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5142" , 0x118008094a0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5143" , 0x118008094a0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5144" , 0x118008094a0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5145" , 0x118008094a0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5146" , 0x118008094a0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5147" , 0x118008094a0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5148" , 0x118008094a0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5149" , 0x118008094a0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5150" , 0x118008094a0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5151" , 0x118008094a0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5152" , 0x118008094a100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5153" , 0x118008094a108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5154" , 0x118008094a110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5155" , 0x118008094a118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5156" , 0x118008094a120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5157" , 0x118008094a128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5158" , 0x118008094a130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5159" , 0x118008094a138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5160" , 0x118008094a140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5161" , 0x118008094a148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5162" , 0x118008094a150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5163" , 0x118008094a158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5164" , 0x118008094a160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5165" , 0x118008094a168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5166" , 0x118008094a170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5167" , 0x118008094a178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5168" , 0x118008094a180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5169" , 0x118008094a188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5170" , 0x118008094a190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5171" , 0x118008094a198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5172" , 0x118008094a1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5173" , 0x118008094a1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5174" , 0x118008094a1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5175" , 0x118008094a1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5176" , 0x118008094a1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5177" , 0x118008094a1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5178" , 0x118008094a1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5179" , 0x118008094a1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5180" , 0x118008094a1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5181" , 0x118008094a1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5182" , 0x118008094a1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5183" , 0x118008094a1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5184" , 0x118008094a200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5185" , 0x118008094a208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5186" , 0x118008094a210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5187" , 0x118008094a218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5188" , 0x118008094a220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5189" , 0x118008094a228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5190" , 0x118008094a230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5191" , 0x118008094a238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5192" , 0x118008094a240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5193" , 0x118008094a248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5194" , 0x118008094a250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5195" , 0x118008094a258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5196" , 0x118008094a260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5197" , 0x118008094a268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5198" , 0x118008094a270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5199" , 0x118008094a278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5200" , 0x118008094a280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5201" , 0x118008094a288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5202" , 0x118008094a290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5203" , 0x118008094a298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5204" , 0x118008094a2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5205" , 0x118008094a2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5206" , 0x118008094a2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5207" , 0x118008094a2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5208" , 0x118008094a2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5209" , 0x118008094a2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5210" , 0x118008094a2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5211" , 0x118008094a2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5212" , 0x118008094a2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5213" , 0x118008094a2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5214" , 0x118008094a2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5215" , 0x118008094a2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5216" , 0x118008094a300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5217" , 0x118008094a308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5218" , 0x118008094a310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5219" , 0x118008094a318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5220" , 0x118008094a320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5221" , 0x118008094a328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5222" , 0x118008094a330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5223" , 0x118008094a338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5224" , 0x118008094a340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5225" , 0x118008094a348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5226" , 0x118008094a350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5227" , 0x118008094a358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5228" , 0x118008094a360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5229" , 0x118008094a368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5230" , 0x118008094a370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5231" , 0x118008094a378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5232" , 0x118008094a380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5233" , 0x118008094a388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5234" , 0x118008094a390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5235" , 0x118008094a398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5236" , 0x118008094a3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5237" , 0x118008094a3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5238" , 0x118008094a3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5239" , 0x118008094a3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5240" , 0x118008094a3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5241" , 0x118008094a3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5242" , 0x118008094a3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5243" , 0x118008094a3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5244" , 0x118008094a3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5245" , 0x118008094a3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5246" , 0x118008094a3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5247" , 0x118008094a3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5248" , 0x118008094a400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5249" , 0x118008094a408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5250" , 0x118008094a410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5251" , 0x118008094a418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5252" , 0x118008094a420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5253" , 0x118008094a428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5254" , 0x118008094a430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5255" , 0x118008094a438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5256" , 0x118008094a440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5257" , 0x118008094a448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5258" , 0x118008094a450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5259" , 0x118008094a458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5260" , 0x118008094a460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5261" , 0x118008094a468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5262" , 0x118008094a470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5263" , 0x118008094a478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5264" , 0x118008094a480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5265" , 0x118008094a488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5266" , 0x118008094a490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5267" , 0x118008094a498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5268" , 0x118008094a4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5269" , 0x118008094a4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5270" , 0x118008094a4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5271" , 0x118008094a4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5272" , 0x118008094a4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5273" , 0x118008094a4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5274" , 0x118008094a4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5275" , 0x118008094a4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5276" , 0x118008094a4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5277" , 0x118008094a4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5278" , 0x118008094a4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5279" , 0x118008094a4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5280" , 0x118008094a500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5281" , 0x118008094a508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5282" , 0x118008094a510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5283" , 0x118008094a518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5284" , 0x118008094a520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5285" , 0x118008094a528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5286" , 0x118008094a530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5287" , 0x118008094a538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5288" , 0x118008094a540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5289" , 0x118008094a548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5290" , 0x118008094a550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5291" , 0x118008094a558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5292" , 0x118008094a560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5293" , 0x118008094a568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5294" , 0x118008094a570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5295" , 0x118008094a578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5296" , 0x118008094a580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5297" , 0x118008094a588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5298" , 0x118008094a590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5299" , 0x118008094a598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5300" , 0x118008094a5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5301" , 0x118008094a5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5302" , 0x118008094a5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5303" , 0x118008094a5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5304" , 0x118008094a5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5305" , 0x118008094a5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5306" , 0x118008094a5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5307" , 0x118008094a5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5308" , 0x118008094a5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5309" , 0x118008094a5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5310" , 0x118008094a5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5311" , 0x118008094a5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5312" , 0x118008094a600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5313" , 0x118008094a608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5314" , 0x118008094a610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5315" , 0x118008094a618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5316" , 0x118008094a620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5317" , 0x118008094a628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5318" , 0x118008094a630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5319" , 0x118008094a638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5320" , 0x118008094a640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5321" , 0x118008094a648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5322" , 0x118008094a650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5323" , 0x118008094a658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5324" , 0x118008094a660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5325" , 0x118008094a668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5326" , 0x118008094a670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5327" , 0x118008094a678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5328" , 0x118008094a680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5329" , 0x118008094a688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5330" , 0x118008094a690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5331" , 0x118008094a698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5332" , 0x118008094a6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5333" , 0x118008094a6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5334" , 0x118008094a6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5335" , 0x118008094a6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5336" , 0x118008094a6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5337" , 0x118008094a6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5338" , 0x118008094a6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5339" , 0x118008094a6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5340" , 0x118008094a6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5341" , 0x118008094a6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5342" , 0x118008094a6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5343" , 0x118008094a6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5344" , 0x118008094a700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5345" , 0x118008094a708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5346" , 0x118008094a710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5347" , 0x118008094a718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5348" , 0x118008094a720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5349" , 0x118008094a728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5350" , 0x118008094a730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5351" , 0x118008094a738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5352" , 0x118008094a740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5353" , 0x118008094a748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5354" , 0x118008094a750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5355" , 0x118008094a758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5356" , 0x118008094a760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5357" , 0x118008094a768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5358" , 0x118008094a770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5359" , 0x118008094a778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5360" , 0x118008094a780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5361" , 0x118008094a788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5362" , 0x118008094a790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5363" , 0x118008094a798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5364" , 0x118008094a7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5365" , 0x118008094a7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5366" , 0x118008094a7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5367" , 0x118008094a7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5368" , 0x118008094a7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5369" , 0x118008094a7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5370" , 0x118008094a7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5371" , 0x118008094a7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5372" , 0x118008094a7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5373" , 0x118008094a7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5374" , 0x118008094a7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5375" , 0x118008094a7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5376" , 0x118008094a800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5377" , 0x118008094a808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5378" , 0x118008094a810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5379" , 0x118008094a818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5380" , 0x118008094a820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5381" , 0x118008094a828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5382" , 0x118008094a830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5383" , 0x118008094a838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5384" , 0x118008094a840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5385" , 0x118008094a848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5386" , 0x118008094a850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5387" , 0x118008094a858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5388" , 0x118008094a860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5389" , 0x118008094a868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5390" , 0x118008094a870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5391" , 0x118008094a878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5392" , 0x118008094a880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5393" , 0x118008094a888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5394" , 0x118008094a890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5395" , 0x118008094a898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5396" , 0x118008094a8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5397" , 0x118008094a8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5398" , 0x118008094a8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5399" , 0x118008094a8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5400" , 0x118008094a8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5401" , 0x118008094a8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5402" , 0x118008094a8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5403" , 0x118008094a8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5404" , 0x118008094a8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5405" , 0x118008094a8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5406" , 0x118008094a8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5407" , 0x118008094a8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5408" , 0x118008094a900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5409" , 0x118008094a908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5410" , 0x118008094a910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5411" , 0x118008094a918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5412" , 0x118008094a920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5413" , 0x118008094a928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5414" , 0x118008094a930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5415" , 0x118008094a938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5416" , 0x118008094a940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5417" , 0x118008094a948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5418" , 0x118008094a950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5419" , 0x118008094a958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5420" , 0x118008094a960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5421" , 0x118008094a968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5422" , 0x118008094a970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5423" , 0x118008094a978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5424" , 0x118008094a980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5425" , 0x118008094a988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5426" , 0x118008094a990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5427" , 0x118008094a998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5428" , 0x118008094a9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5429" , 0x118008094a9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5430" , 0x118008094a9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5431" , 0x118008094a9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5432" , 0x118008094a9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5433" , 0x118008094a9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5434" , 0x118008094a9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5435" , 0x118008094a9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5436" , 0x118008094a9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5437" , 0x118008094a9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5438" , 0x118008094a9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5439" , 0x118008094a9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5440" , 0x118008094aa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5441" , 0x118008094aa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5442" , 0x118008094aa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5443" , 0x118008094aa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5444" , 0x118008094aa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5445" , 0x118008094aa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5446" , 0x118008094aa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5447" , 0x118008094aa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5448" , 0x118008094aa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5449" , 0x118008094aa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5450" , 0x118008094aa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5451" , 0x118008094aa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5452" , 0x118008094aa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5453" , 0x118008094aa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5454" , 0x118008094aa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5455" , 0x118008094aa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5456" , 0x118008094aa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5457" , 0x118008094aa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5458" , 0x118008094aa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5459" , 0x118008094aa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5460" , 0x118008094aaa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5461" , 0x118008094aaa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5462" , 0x118008094aab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5463" , 0x118008094aab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5464" , 0x118008094aac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5465" , 0x118008094aac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5466" , 0x118008094aad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5467" , 0x118008094aad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5468" , 0x118008094aae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5469" , 0x118008094aae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5470" , 0x118008094aaf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5471" , 0x118008094aaf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5472" , 0x118008094ab00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5473" , 0x118008094ab08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5474" , 0x118008094ab10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5475" , 0x118008094ab18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5476" , 0x118008094ab20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5477" , 0x118008094ab28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5478" , 0x118008094ab30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5479" , 0x118008094ab38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5480" , 0x118008094ab40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5481" , 0x118008094ab48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5482" , 0x118008094ab50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5483" , 0x118008094ab58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5484" , 0x118008094ab60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5485" , 0x118008094ab68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5486" , 0x118008094ab70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5487" , 0x118008094ab78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5488" , 0x118008094ab80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5489" , 0x118008094ab88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5490" , 0x118008094ab90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5491" , 0x118008094ab98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5492" , 0x118008094aba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5493" , 0x118008094aba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5494" , 0x118008094abb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5495" , 0x118008094abb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5496" , 0x118008094abc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5497" , 0x118008094abc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5498" , 0x118008094abd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5499" , 0x118008094abd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5500" , 0x118008094abe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5501" , 0x118008094abe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5502" , 0x118008094abf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5503" , 0x118008094abf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5504" , 0x118008094ac00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5505" , 0x118008094ac08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5506" , 0x118008094ac10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5507" , 0x118008094ac18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5508" , 0x118008094ac20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5509" , 0x118008094ac28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5510" , 0x118008094ac30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5511" , 0x118008094ac38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5512" , 0x118008094ac40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5513" , 0x118008094ac48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5514" , 0x118008094ac50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5515" , 0x118008094ac58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5516" , 0x118008094ac60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5517" , 0x118008094ac68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5518" , 0x118008094ac70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5519" , 0x118008094ac78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5520" , 0x118008094ac80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5521" , 0x118008094ac88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5522" , 0x118008094ac90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5523" , 0x118008094ac98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5524" , 0x118008094aca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5525" , 0x118008094aca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5526" , 0x118008094acb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5527" , 0x118008094acb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5528" , 0x118008094acc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5529" , 0x118008094acc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5530" , 0x118008094acd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5531" , 0x118008094acd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5532" , 0x118008094ace0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5533" , 0x118008094ace8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5534" , 0x118008094acf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5535" , 0x118008094acf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5536" , 0x118008094ad00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5537" , 0x118008094ad08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5538" , 0x118008094ad10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5539" , 0x118008094ad18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5540" , 0x118008094ad20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5541" , 0x118008094ad28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5542" , 0x118008094ad30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5543" , 0x118008094ad38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5544" , 0x118008094ad40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5545" , 0x118008094ad48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5546" , 0x118008094ad50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5547" , 0x118008094ad58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5548" , 0x118008094ad60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5549" , 0x118008094ad68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5550" , 0x118008094ad70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5551" , 0x118008094ad78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5552" , 0x118008094ad80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5553" , 0x118008094ad88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5554" , 0x118008094ad90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5555" , 0x118008094ad98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5556" , 0x118008094ada0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5557" , 0x118008094ada8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5558" , 0x118008094adb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5559" , 0x118008094adb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5560" , 0x118008094adc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5561" , 0x118008094adc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5562" , 0x118008094add0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5563" , 0x118008094add8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5564" , 0x118008094ade0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5565" , 0x118008094ade8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5566" , 0x118008094adf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5567" , 0x118008094adf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5568" , 0x118008094ae00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5569" , 0x118008094ae08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5570" , 0x118008094ae10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5571" , 0x118008094ae18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5572" , 0x118008094ae20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5573" , 0x118008094ae28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5574" , 0x118008094ae30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5575" , 0x118008094ae38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5576" , 0x118008094ae40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5577" , 0x118008094ae48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5578" , 0x118008094ae50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5579" , 0x118008094ae58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5580" , 0x118008094ae60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5581" , 0x118008094ae68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5582" , 0x118008094ae70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5583" , 0x118008094ae78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5584" , 0x118008094ae80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5585" , 0x118008094ae88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5586" , 0x118008094ae90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5587" , 0x118008094ae98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5588" , 0x118008094aea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5589" , 0x118008094aea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5590" , 0x118008094aeb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5591" , 0x118008094aeb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5592" , 0x118008094aec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5593" , 0x118008094aec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5594" , 0x118008094aed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5595" , 0x118008094aed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5596" , 0x118008094aee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5597" , 0x118008094aee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5598" , 0x118008094aef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5599" , 0x118008094aef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5600" , 0x118008094af00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5601" , 0x118008094af08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5602" , 0x118008094af10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5603" , 0x118008094af18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5604" , 0x118008094af20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5605" , 0x118008094af28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5606" , 0x118008094af30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5607" , 0x118008094af38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5608" , 0x118008094af40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5609" , 0x118008094af48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5610" , 0x118008094af50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5611" , 0x118008094af58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5612" , 0x118008094af60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5613" , 0x118008094af68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5614" , 0x118008094af70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5615" , 0x118008094af78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5616" , 0x118008094af80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5617" , 0x118008094af88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5618" , 0x118008094af90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5619" , 0x118008094af98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5620" , 0x118008094afa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5621" , 0x118008094afa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5622" , 0x118008094afb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5623" , 0x118008094afb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5624" , 0x118008094afc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5625" , 0x118008094afc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5626" , 0x118008094afd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5627" , 0x118008094afd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5628" , 0x118008094afe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5629" , 0x118008094afe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5630" , 0x118008094aff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5631" , 0x118008094aff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5632" , 0x118008094b000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5633" , 0x118008094b008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5634" , 0x118008094b010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5635" , 0x118008094b018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5636" , 0x118008094b020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5637" , 0x118008094b028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5638" , 0x118008094b030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5639" , 0x118008094b038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5640" , 0x118008094b040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5641" , 0x118008094b048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5642" , 0x118008094b050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5643" , 0x118008094b058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5644" , 0x118008094b060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5645" , 0x118008094b068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5646" , 0x118008094b070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5647" , 0x118008094b078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5648" , 0x118008094b080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5649" , 0x118008094b088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5650" , 0x118008094b090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5651" , 0x118008094b098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5652" , 0x118008094b0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5653" , 0x118008094b0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5654" , 0x118008094b0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5655" , 0x118008094b0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5656" , 0x118008094b0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5657" , 0x118008094b0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5658" , 0x118008094b0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5659" , 0x118008094b0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5660" , 0x118008094b0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5661" , 0x118008094b0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5662" , 0x118008094b0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5663" , 0x118008094b0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5664" , 0x118008094b100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5665" , 0x118008094b108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5666" , 0x118008094b110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5667" , 0x118008094b118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5668" , 0x118008094b120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5669" , 0x118008094b128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5670" , 0x118008094b130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5671" , 0x118008094b138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5672" , 0x118008094b140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5673" , 0x118008094b148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5674" , 0x118008094b150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5675" , 0x118008094b158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5676" , 0x118008094b160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5677" , 0x118008094b168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5678" , 0x118008094b170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5679" , 0x118008094b178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5680" , 0x118008094b180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5681" , 0x118008094b188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5682" , 0x118008094b190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5683" , 0x118008094b198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5684" , 0x118008094b1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5685" , 0x118008094b1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5686" , 0x118008094b1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5687" , 0x118008094b1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5688" , 0x118008094b1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5689" , 0x118008094b1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5690" , 0x118008094b1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5691" , 0x118008094b1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5692" , 0x118008094b1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5693" , 0x118008094b1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5694" , 0x118008094b1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5695" , 0x118008094b1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5696" , 0x118008094b200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5697" , 0x118008094b208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5698" , 0x118008094b210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5699" , 0x118008094b218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5700" , 0x118008094b220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5701" , 0x118008094b228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5702" , 0x118008094b230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5703" , 0x118008094b238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5704" , 0x118008094b240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5705" , 0x118008094b248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5706" , 0x118008094b250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5707" , 0x118008094b258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5708" , 0x118008094b260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5709" , 0x118008094b268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5710" , 0x118008094b270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5711" , 0x118008094b278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5712" , 0x118008094b280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5713" , 0x118008094b288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5714" , 0x118008094b290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5715" , 0x118008094b298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5716" , 0x118008094b2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5717" , 0x118008094b2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5718" , 0x118008094b2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5719" , 0x118008094b2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5720" , 0x118008094b2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5721" , 0x118008094b2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5722" , 0x118008094b2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5723" , 0x118008094b2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5724" , 0x118008094b2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5725" , 0x118008094b2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5726" , 0x118008094b2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5727" , 0x118008094b2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5728" , 0x118008094b300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5729" , 0x118008094b308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5730" , 0x118008094b310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5731" , 0x118008094b318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5732" , 0x118008094b320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5733" , 0x118008094b328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5734" , 0x118008094b330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5735" , 0x118008094b338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5736" , 0x118008094b340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5737" , 0x118008094b348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5738" , 0x118008094b350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5739" , 0x118008094b358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5740" , 0x118008094b360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5741" , 0x118008094b368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5742" , 0x118008094b370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5743" , 0x118008094b378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5744" , 0x118008094b380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5745" , 0x118008094b388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5746" , 0x118008094b390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5747" , 0x118008094b398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5748" , 0x118008094b3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5749" , 0x118008094b3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5750" , 0x118008094b3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5751" , 0x118008094b3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5752" , 0x118008094b3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5753" , 0x118008094b3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5754" , 0x118008094b3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5755" , 0x118008094b3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5756" , 0x118008094b3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5757" , 0x118008094b3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5758" , 0x118008094b3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5759" , 0x118008094b3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5760" , 0x118008094b400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5761" , 0x118008094b408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5762" , 0x118008094b410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5763" , 0x118008094b418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5764" , 0x118008094b420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5765" , 0x118008094b428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5766" , 0x118008094b430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5767" , 0x118008094b438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5768" , 0x118008094b440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5769" , 0x118008094b448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5770" , 0x118008094b450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5771" , 0x118008094b458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5772" , 0x118008094b460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5773" , 0x118008094b468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5774" , 0x118008094b470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5775" , 0x118008094b478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5776" , 0x118008094b480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5777" , 0x118008094b488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5778" , 0x118008094b490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5779" , 0x118008094b498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5780" , 0x118008094b4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5781" , 0x118008094b4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5782" , 0x118008094b4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5783" , 0x118008094b4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5784" , 0x118008094b4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5785" , 0x118008094b4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5786" , 0x118008094b4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5787" , 0x118008094b4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5788" , 0x118008094b4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5789" , 0x118008094b4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5790" , 0x118008094b4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5791" , 0x118008094b4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5792" , 0x118008094b500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5793" , 0x118008094b508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5794" , 0x118008094b510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5795" , 0x118008094b518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5796" , 0x118008094b520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5797" , 0x118008094b528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5798" , 0x118008094b530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5799" , 0x118008094b538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5800" , 0x118008094b540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5801" , 0x118008094b548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5802" , 0x118008094b550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5803" , 0x118008094b558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5804" , 0x118008094b560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5805" , 0x118008094b568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5806" , 0x118008094b570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5807" , 0x118008094b578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5808" , 0x118008094b580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5809" , 0x118008094b588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5810" , 0x118008094b590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5811" , 0x118008094b598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5812" , 0x118008094b5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5813" , 0x118008094b5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5814" , 0x118008094b5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5815" , 0x118008094b5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5816" , 0x118008094b5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5817" , 0x118008094b5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5818" , 0x118008094b5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5819" , 0x118008094b5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5820" , 0x118008094b5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5821" , 0x118008094b5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5822" , 0x118008094b5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5823" , 0x118008094b5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5824" , 0x118008094b600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5825" , 0x118008094b608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5826" , 0x118008094b610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5827" , 0x118008094b618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5828" , 0x118008094b620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5829" , 0x118008094b628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5830" , 0x118008094b630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5831" , 0x118008094b638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5832" , 0x118008094b640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5833" , 0x118008094b648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5834" , 0x118008094b650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5835" , 0x118008094b658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5836" , 0x118008094b660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5837" , 0x118008094b668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5838" , 0x118008094b670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5839" , 0x118008094b678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5840" , 0x118008094b680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5841" , 0x118008094b688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5842" , 0x118008094b690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5843" , 0x118008094b698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5844" , 0x118008094b6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5845" , 0x118008094b6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5846" , 0x118008094b6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5847" , 0x118008094b6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5848" , 0x118008094b6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5849" , 0x118008094b6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5850" , 0x118008094b6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5851" , 0x118008094b6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5852" , 0x118008094b6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5853" , 0x118008094b6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5854" , 0x118008094b6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5855" , 0x118008094b6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5856" , 0x118008094b700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5857" , 0x118008094b708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5858" , 0x118008094b710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5859" , 0x118008094b718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5860" , 0x118008094b720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5861" , 0x118008094b728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5862" , 0x118008094b730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5863" , 0x118008094b738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5864" , 0x118008094b740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5865" , 0x118008094b748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5866" , 0x118008094b750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5867" , 0x118008094b758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5868" , 0x118008094b760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5869" , 0x118008094b768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5870" , 0x118008094b770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5871" , 0x118008094b778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5872" , 0x118008094b780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5873" , 0x118008094b788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5874" , 0x118008094b790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5875" , 0x118008094b798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5876" , 0x118008094b7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5877" , 0x118008094b7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5878" , 0x118008094b7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5879" , 0x118008094b7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5880" , 0x118008094b7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5881" , 0x118008094b7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5882" , 0x118008094b7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5883" , 0x118008094b7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5884" , 0x118008094b7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5885" , 0x118008094b7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5886" , 0x118008094b7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5887" , 0x118008094b7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5888" , 0x118008094b800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5889" , 0x118008094b808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5890" , 0x118008094b810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5891" , 0x118008094b818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5892" , 0x118008094b820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5893" , 0x118008094b828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5894" , 0x118008094b830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5895" , 0x118008094b838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5896" , 0x118008094b840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5897" , 0x118008094b848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5898" , 0x118008094b850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5899" , 0x118008094b858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5900" , 0x118008094b860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5901" , 0x118008094b868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5902" , 0x118008094b870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5903" , 0x118008094b878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5904" , 0x118008094b880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5905" , 0x118008094b888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5906" , 0x118008094b890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5907" , 0x118008094b898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5908" , 0x118008094b8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5909" , 0x118008094b8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5910" , 0x118008094b8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5911" , 0x118008094b8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5912" , 0x118008094b8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5913" , 0x118008094b8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5914" , 0x118008094b8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5915" , 0x118008094b8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5916" , 0x118008094b8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5917" , 0x118008094b8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5918" , 0x118008094b8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5919" , 0x118008094b8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5920" , 0x118008094b900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5921" , 0x118008094b908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5922" , 0x118008094b910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5923" , 0x118008094b918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5924" , 0x118008094b920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5925" , 0x118008094b928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5926" , 0x118008094b930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5927" , 0x118008094b938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5928" , 0x118008094b940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5929" , 0x118008094b948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5930" , 0x118008094b950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5931" , 0x118008094b958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5932" , 0x118008094b960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5933" , 0x118008094b968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5934" , 0x118008094b970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5935" , 0x118008094b978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5936" , 0x118008094b980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5937" , 0x118008094b988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5938" , 0x118008094b990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5939" , 0x118008094b998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5940" , 0x118008094b9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5941" , 0x118008094b9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5942" , 0x118008094b9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5943" , 0x118008094b9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5944" , 0x118008094b9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5945" , 0x118008094b9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5946" , 0x118008094b9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5947" , 0x118008094b9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5948" , 0x118008094b9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5949" , 0x118008094b9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5950" , 0x118008094b9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5951" , 0x118008094b9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5952" , 0x118008094ba00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5953" , 0x118008094ba08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5954" , 0x118008094ba10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5955" , 0x118008094ba18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5956" , 0x118008094ba20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5957" , 0x118008094ba28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5958" , 0x118008094ba30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5959" , 0x118008094ba38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5960" , 0x118008094ba40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5961" , 0x118008094ba48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5962" , 0x118008094ba50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5963" , 0x118008094ba58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5964" , 0x118008094ba60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5965" , 0x118008094ba68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5966" , 0x118008094ba70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5967" , 0x118008094ba78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5968" , 0x118008094ba80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5969" , 0x118008094ba88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5970" , 0x118008094ba90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5971" , 0x118008094ba98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5972" , 0x118008094baa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5973" , 0x118008094baa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5974" , 0x118008094bab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5975" , 0x118008094bab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5976" , 0x118008094bac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5977" , 0x118008094bac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5978" , 0x118008094bad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5979" , 0x118008094bad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5980" , 0x118008094bae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5981" , 0x118008094bae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5982" , 0x118008094baf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5983" , 0x118008094baf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5984" , 0x118008094bb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5985" , 0x118008094bb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5986" , 0x118008094bb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5987" , 0x118008094bb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5988" , 0x118008094bb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5989" , 0x118008094bb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5990" , 0x118008094bb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5991" , 0x118008094bb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5992" , 0x118008094bb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5993" , 0x118008094bb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5994" , 0x118008094bb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5995" , 0x118008094bb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5996" , 0x118008094bb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5997" , 0x118008094bb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5998" , 0x118008094bb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP5999" , 0x118008094bb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6000" , 0x118008094bb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6001" , 0x118008094bb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6002" , 0x118008094bb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6003" , 0x118008094bb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6004" , 0x118008094bba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6005" , 0x118008094bba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6006" , 0x118008094bbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6007" , 0x118008094bbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6008" , 0x118008094bbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6009" , 0x118008094bbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6010" , 0x118008094bbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6011" , 0x118008094bbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6012" , 0x118008094bbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6013" , 0x118008094bbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6014" , 0x118008094bbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6015" , 0x118008094bbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6016" , 0x118008094bc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6017" , 0x118008094bc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6018" , 0x118008094bc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6019" , 0x118008094bc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6020" , 0x118008094bc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6021" , 0x118008094bc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6022" , 0x118008094bc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6023" , 0x118008094bc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6024" , 0x118008094bc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6025" , 0x118008094bc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6026" , 0x118008094bc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6027" , 0x118008094bc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6028" , 0x118008094bc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6029" , 0x118008094bc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6030" , 0x118008094bc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6031" , 0x118008094bc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6032" , 0x118008094bc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6033" , 0x118008094bc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6034" , 0x118008094bc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6035" , 0x118008094bc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6036" , 0x118008094bca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6037" , 0x118008094bca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6038" , 0x118008094bcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6039" , 0x118008094bcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6040" , 0x118008094bcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6041" , 0x118008094bcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6042" , 0x118008094bcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6043" , 0x118008094bcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6044" , 0x118008094bce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6045" , 0x118008094bce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6046" , 0x118008094bcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6047" , 0x118008094bcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6048" , 0x118008094bd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6049" , 0x118008094bd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6050" , 0x118008094bd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6051" , 0x118008094bd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6052" , 0x118008094bd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6053" , 0x118008094bd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6054" , 0x118008094bd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6055" , 0x118008094bd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6056" , 0x118008094bd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6057" , 0x118008094bd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6058" , 0x118008094bd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6059" , 0x118008094bd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6060" , 0x118008094bd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6061" , 0x118008094bd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6062" , 0x118008094bd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6063" , 0x118008094bd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6064" , 0x118008094bd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6065" , 0x118008094bd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6066" , 0x118008094bd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6067" , 0x118008094bd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6068" , 0x118008094bda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6069" , 0x118008094bda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6070" , 0x118008094bdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6071" , 0x118008094bdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6072" , 0x118008094bdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6073" , 0x118008094bdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6074" , 0x118008094bdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6075" , 0x118008094bdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6076" , 0x118008094bde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6077" , 0x118008094bde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6078" , 0x118008094bdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6079" , 0x118008094bdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6080" , 0x118008094be00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6081" , 0x118008094be08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6082" , 0x118008094be10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6083" , 0x118008094be18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6084" , 0x118008094be20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6085" , 0x118008094be28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6086" , 0x118008094be30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6087" , 0x118008094be38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6088" , 0x118008094be40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6089" , 0x118008094be48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6090" , 0x118008094be50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6091" , 0x118008094be58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6092" , 0x118008094be60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6093" , 0x118008094be68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6094" , 0x118008094be70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6095" , 0x118008094be78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6096" , 0x118008094be80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6097" , 0x118008094be88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6098" , 0x118008094be90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6099" , 0x118008094be98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6100" , 0x118008094bea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6101" , 0x118008094bea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6102" , 0x118008094beb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6103" , 0x118008094beb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6104" , 0x118008094bec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6105" , 0x118008094bec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6106" , 0x118008094bed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6107" , 0x118008094bed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6108" , 0x118008094bee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6109" , 0x118008094bee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6110" , 0x118008094bef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6111" , 0x118008094bef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6112" , 0x118008094bf00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6113" , 0x118008094bf08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6114" , 0x118008094bf10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6115" , 0x118008094bf18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6116" , 0x118008094bf20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6117" , 0x118008094bf28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6118" , 0x118008094bf30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6119" , 0x118008094bf38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6120" , 0x118008094bf40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6121" , 0x118008094bf48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6122" , 0x118008094bf50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6123" , 0x118008094bf58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6124" , 0x118008094bf60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6125" , 0x118008094bf68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6126" , 0x118008094bf70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6127" , 0x118008094bf78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6128" , 0x118008094bf80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6129" , 0x118008094bf88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6130" , 0x118008094bf90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6131" , 0x118008094bf98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6132" , 0x118008094bfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6133" , 0x118008094bfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6134" , 0x118008094bfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6135" , 0x118008094bfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6136" , 0x118008094bfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6137" , 0x118008094bfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6138" , 0x118008094bfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6139" , 0x118008094bfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6140" , 0x118008094bfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6141" , 0x118008094bfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6142" , 0x118008094bff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6143" , 0x118008094bff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6144" , 0x118008094c000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6145" , 0x118008094c008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6146" , 0x118008094c010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6147" , 0x118008094c018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6148" , 0x118008094c020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6149" , 0x118008094c028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6150" , 0x118008094c030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6151" , 0x118008094c038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6152" , 0x118008094c040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6153" , 0x118008094c048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6154" , 0x118008094c050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6155" , 0x118008094c058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6156" , 0x118008094c060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6157" , 0x118008094c068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6158" , 0x118008094c070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6159" , 0x118008094c078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6160" , 0x118008094c080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6161" , 0x118008094c088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6162" , 0x118008094c090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6163" , 0x118008094c098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6164" , 0x118008094c0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6165" , 0x118008094c0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6166" , 0x118008094c0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6167" , 0x118008094c0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6168" , 0x118008094c0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6169" , 0x118008094c0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6170" , 0x118008094c0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6171" , 0x118008094c0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6172" , 0x118008094c0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6173" , 0x118008094c0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6174" , 0x118008094c0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6175" , 0x118008094c0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6176" , 0x118008094c100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6177" , 0x118008094c108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6178" , 0x118008094c110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6179" , 0x118008094c118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6180" , 0x118008094c120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6181" , 0x118008094c128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6182" , 0x118008094c130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6183" , 0x118008094c138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6184" , 0x118008094c140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6185" , 0x118008094c148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6186" , 0x118008094c150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6187" , 0x118008094c158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6188" , 0x118008094c160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6189" , 0x118008094c168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6190" , 0x118008094c170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6191" , 0x118008094c178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6192" , 0x118008094c180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6193" , 0x118008094c188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6194" , 0x118008094c190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6195" , 0x118008094c198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6196" , 0x118008094c1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6197" , 0x118008094c1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6198" , 0x118008094c1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6199" , 0x118008094c1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6200" , 0x118008094c1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6201" , 0x118008094c1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6202" , 0x118008094c1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6203" , 0x118008094c1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6204" , 0x118008094c1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6205" , 0x118008094c1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6206" , 0x118008094c1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6207" , 0x118008094c1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6208" , 0x118008094c200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6209" , 0x118008094c208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6210" , 0x118008094c210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6211" , 0x118008094c218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6212" , 0x118008094c220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6213" , 0x118008094c228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6214" , 0x118008094c230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6215" , 0x118008094c238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6216" , 0x118008094c240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6217" , 0x118008094c248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6218" , 0x118008094c250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6219" , 0x118008094c258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6220" , 0x118008094c260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6221" , 0x118008094c268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6222" , 0x118008094c270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6223" , 0x118008094c278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6224" , 0x118008094c280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6225" , 0x118008094c288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6226" , 0x118008094c290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6227" , 0x118008094c298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6228" , 0x118008094c2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6229" , 0x118008094c2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6230" , 0x118008094c2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6231" , 0x118008094c2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6232" , 0x118008094c2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6233" , 0x118008094c2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6234" , 0x118008094c2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6235" , 0x118008094c2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6236" , 0x118008094c2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6237" , 0x118008094c2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6238" , 0x118008094c2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6239" , 0x118008094c2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6240" , 0x118008094c300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6241" , 0x118008094c308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6242" , 0x118008094c310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6243" , 0x118008094c318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6244" , 0x118008094c320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6245" , 0x118008094c328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6246" , 0x118008094c330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6247" , 0x118008094c338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6248" , 0x118008094c340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6249" , 0x118008094c348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6250" , 0x118008094c350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6251" , 0x118008094c358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6252" , 0x118008094c360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6253" , 0x118008094c368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6254" , 0x118008094c370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6255" , 0x118008094c378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6256" , 0x118008094c380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6257" , 0x118008094c388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6258" , 0x118008094c390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6259" , 0x118008094c398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6260" , 0x118008094c3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6261" , 0x118008094c3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6262" , 0x118008094c3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6263" , 0x118008094c3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6264" , 0x118008094c3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6265" , 0x118008094c3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6266" , 0x118008094c3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6267" , 0x118008094c3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6268" , 0x118008094c3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6269" , 0x118008094c3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6270" , 0x118008094c3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6271" , 0x118008094c3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6272" , 0x118008094c400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6273" , 0x118008094c408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6274" , 0x118008094c410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6275" , 0x118008094c418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6276" , 0x118008094c420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6277" , 0x118008094c428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6278" , 0x118008094c430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6279" , 0x118008094c438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6280" , 0x118008094c440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6281" , 0x118008094c448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6282" , 0x118008094c450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6283" , 0x118008094c458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6284" , 0x118008094c460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6285" , 0x118008094c468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6286" , 0x118008094c470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6287" , 0x118008094c478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6288" , 0x118008094c480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6289" , 0x118008094c488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6290" , 0x118008094c490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6291" , 0x118008094c498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6292" , 0x118008094c4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6293" , 0x118008094c4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6294" , 0x118008094c4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6295" , 0x118008094c4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6296" , 0x118008094c4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6297" , 0x118008094c4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6298" , 0x118008094c4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6299" , 0x118008094c4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6300" , 0x118008094c4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6301" , 0x118008094c4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6302" , 0x118008094c4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6303" , 0x118008094c4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6304" , 0x118008094c500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6305" , 0x118008094c508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6306" , 0x118008094c510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6307" , 0x118008094c518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6308" , 0x118008094c520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6309" , 0x118008094c528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6310" , 0x118008094c530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6311" , 0x118008094c538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6312" , 0x118008094c540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6313" , 0x118008094c548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6314" , 0x118008094c550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6315" , 0x118008094c558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6316" , 0x118008094c560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6317" , 0x118008094c568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6318" , 0x118008094c570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6319" , 0x118008094c578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6320" , 0x118008094c580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6321" , 0x118008094c588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6322" , 0x118008094c590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6323" , 0x118008094c598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6324" , 0x118008094c5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6325" , 0x118008094c5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6326" , 0x118008094c5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6327" , 0x118008094c5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6328" , 0x118008094c5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6329" , 0x118008094c5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6330" , 0x118008094c5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6331" , 0x118008094c5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6332" , 0x118008094c5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6333" , 0x118008094c5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6334" , 0x118008094c5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6335" , 0x118008094c5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6336" , 0x118008094c600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6337" , 0x118008094c608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6338" , 0x118008094c610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6339" , 0x118008094c618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6340" , 0x118008094c620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6341" , 0x118008094c628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6342" , 0x118008094c630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6343" , 0x118008094c638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6344" , 0x118008094c640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6345" , 0x118008094c648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6346" , 0x118008094c650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6347" , 0x118008094c658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6348" , 0x118008094c660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6349" , 0x118008094c668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6350" , 0x118008094c670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6351" , 0x118008094c678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6352" , 0x118008094c680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6353" , 0x118008094c688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6354" , 0x118008094c690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6355" , 0x118008094c698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6356" , 0x118008094c6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6357" , 0x118008094c6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6358" , 0x118008094c6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6359" , 0x118008094c6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6360" , 0x118008094c6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6361" , 0x118008094c6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6362" , 0x118008094c6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6363" , 0x118008094c6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6364" , 0x118008094c6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6365" , 0x118008094c6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6366" , 0x118008094c6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6367" , 0x118008094c6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6368" , 0x118008094c700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6369" , 0x118008094c708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6370" , 0x118008094c710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6371" , 0x118008094c718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6372" , 0x118008094c720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6373" , 0x118008094c728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6374" , 0x118008094c730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6375" , 0x118008094c738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6376" , 0x118008094c740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6377" , 0x118008094c748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6378" , 0x118008094c750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6379" , 0x118008094c758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6380" , 0x118008094c760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6381" , 0x118008094c768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6382" , 0x118008094c770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6383" , 0x118008094c778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6384" , 0x118008094c780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6385" , 0x118008094c788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6386" , 0x118008094c790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6387" , 0x118008094c798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6388" , 0x118008094c7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6389" , 0x118008094c7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6390" , 0x118008094c7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6391" , 0x118008094c7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6392" , 0x118008094c7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6393" , 0x118008094c7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6394" , 0x118008094c7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6395" , 0x118008094c7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6396" , 0x118008094c7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6397" , 0x118008094c7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6398" , 0x118008094c7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6399" , 0x118008094c7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6400" , 0x118008094c800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6401" , 0x118008094c808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6402" , 0x118008094c810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6403" , 0x118008094c818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6404" , 0x118008094c820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6405" , 0x118008094c828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6406" , 0x118008094c830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6407" , 0x118008094c838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6408" , 0x118008094c840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6409" , 0x118008094c848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6410" , 0x118008094c850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6411" , 0x118008094c858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6412" , 0x118008094c860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6413" , 0x118008094c868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6414" , 0x118008094c870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6415" , 0x118008094c878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6416" , 0x118008094c880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6417" , 0x118008094c888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6418" , 0x118008094c890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6419" , 0x118008094c898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6420" , 0x118008094c8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6421" , 0x118008094c8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6422" , 0x118008094c8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6423" , 0x118008094c8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6424" , 0x118008094c8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6425" , 0x118008094c8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6426" , 0x118008094c8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6427" , 0x118008094c8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6428" , 0x118008094c8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6429" , 0x118008094c8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6430" , 0x118008094c8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6431" , 0x118008094c8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6432" , 0x118008094c900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6433" , 0x118008094c908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6434" , 0x118008094c910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6435" , 0x118008094c918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6436" , 0x118008094c920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6437" , 0x118008094c928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6438" , 0x118008094c930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6439" , 0x118008094c938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6440" , 0x118008094c940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6441" , 0x118008094c948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6442" , 0x118008094c950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6443" , 0x118008094c958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6444" , 0x118008094c960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6445" , 0x118008094c968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6446" , 0x118008094c970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6447" , 0x118008094c978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6448" , 0x118008094c980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6449" , 0x118008094c988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6450" , 0x118008094c990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6451" , 0x118008094c998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6452" , 0x118008094c9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6453" , 0x118008094c9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6454" , 0x118008094c9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6455" , 0x118008094c9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6456" , 0x118008094c9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6457" , 0x118008094c9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6458" , 0x118008094c9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6459" , 0x118008094c9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6460" , 0x118008094c9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6461" , 0x118008094c9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6462" , 0x118008094c9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6463" , 0x118008094c9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6464" , 0x118008094ca00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6465" , 0x118008094ca08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6466" , 0x118008094ca10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6467" , 0x118008094ca18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6468" , 0x118008094ca20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6469" , 0x118008094ca28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6470" , 0x118008094ca30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6471" , 0x118008094ca38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6472" , 0x118008094ca40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6473" , 0x118008094ca48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6474" , 0x118008094ca50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6475" , 0x118008094ca58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6476" , 0x118008094ca60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6477" , 0x118008094ca68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6478" , 0x118008094ca70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6479" , 0x118008094ca78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6480" , 0x118008094ca80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6481" , 0x118008094ca88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6482" , 0x118008094ca90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6483" , 0x118008094ca98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6484" , 0x118008094caa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6485" , 0x118008094caa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6486" , 0x118008094cab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6487" , 0x118008094cab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6488" , 0x118008094cac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6489" , 0x118008094cac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6490" , 0x118008094cad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6491" , 0x118008094cad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6492" , 0x118008094cae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6493" , 0x118008094cae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6494" , 0x118008094caf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6495" , 0x118008094caf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6496" , 0x118008094cb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6497" , 0x118008094cb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6498" , 0x118008094cb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6499" , 0x118008094cb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6500" , 0x118008094cb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6501" , 0x118008094cb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6502" , 0x118008094cb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6503" , 0x118008094cb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6504" , 0x118008094cb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6505" , 0x118008094cb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6506" , 0x118008094cb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6507" , 0x118008094cb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6508" , 0x118008094cb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6509" , 0x118008094cb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6510" , 0x118008094cb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6511" , 0x118008094cb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6512" , 0x118008094cb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6513" , 0x118008094cb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6514" , 0x118008094cb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6515" , 0x118008094cb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6516" , 0x118008094cba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6517" , 0x118008094cba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6518" , 0x118008094cbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6519" , 0x118008094cbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6520" , 0x118008094cbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6521" , 0x118008094cbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6522" , 0x118008094cbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6523" , 0x118008094cbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6524" , 0x118008094cbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6525" , 0x118008094cbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6526" , 0x118008094cbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6527" , 0x118008094cbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6528" , 0x118008094cc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6529" , 0x118008094cc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6530" , 0x118008094cc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6531" , 0x118008094cc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6532" , 0x118008094cc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6533" , 0x118008094cc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6534" , 0x118008094cc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6535" , 0x118008094cc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6536" , 0x118008094cc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6537" , 0x118008094cc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6538" , 0x118008094cc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6539" , 0x118008094cc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6540" , 0x118008094cc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6541" , 0x118008094cc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6542" , 0x118008094cc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6543" , 0x118008094cc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6544" , 0x118008094cc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6545" , 0x118008094cc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6546" , 0x118008094cc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6547" , 0x118008094cc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6548" , 0x118008094cca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6549" , 0x118008094cca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6550" , 0x118008094ccb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6551" , 0x118008094ccb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6552" , 0x118008094ccc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6553" , 0x118008094ccc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6554" , 0x118008094ccd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6555" , 0x118008094ccd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6556" , 0x118008094cce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6557" , 0x118008094cce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6558" , 0x118008094ccf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6559" , 0x118008094ccf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6560" , 0x118008094cd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6561" , 0x118008094cd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6562" , 0x118008094cd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6563" , 0x118008094cd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6564" , 0x118008094cd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6565" , 0x118008094cd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6566" , 0x118008094cd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6567" , 0x118008094cd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6568" , 0x118008094cd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6569" , 0x118008094cd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6570" , 0x118008094cd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6571" , 0x118008094cd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6572" , 0x118008094cd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6573" , 0x118008094cd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6574" , 0x118008094cd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6575" , 0x118008094cd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6576" , 0x118008094cd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6577" , 0x118008094cd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6578" , 0x118008094cd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6579" , 0x118008094cd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6580" , 0x118008094cda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6581" , 0x118008094cda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6582" , 0x118008094cdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6583" , 0x118008094cdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6584" , 0x118008094cdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6585" , 0x118008094cdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6586" , 0x118008094cdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6587" , 0x118008094cdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6588" , 0x118008094cde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6589" , 0x118008094cde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6590" , 0x118008094cdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6591" , 0x118008094cdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6592" , 0x118008094ce00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6593" , 0x118008094ce08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6594" , 0x118008094ce10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6595" , 0x118008094ce18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6596" , 0x118008094ce20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6597" , 0x118008094ce28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6598" , 0x118008094ce30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6599" , 0x118008094ce38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6600" , 0x118008094ce40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6601" , 0x118008094ce48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6602" , 0x118008094ce50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6603" , 0x118008094ce58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6604" , 0x118008094ce60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6605" , 0x118008094ce68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6606" , 0x118008094ce70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6607" , 0x118008094ce78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6608" , 0x118008094ce80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6609" , 0x118008094ce88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6610" , 0x118008094ce90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6611" , 0x118008094ce98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6612" , 0x118008094cea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6613" , 0x118008094cea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6614" , 0x118008094ceb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6615" , 0x118008094ceb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6616" , 0x118008094cec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6617" , 0x118008094cec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6618" , 0x118008094ced0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6619" , 0x118008094ced8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6620" , 0x118008094cee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6621" , 0x118008094cee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6622" , 0x118008094cef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6623" , 0x118008094cef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6624" , 0x118008094cf00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6625" , 0x118008094cf08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6626" , 0x118008094cf10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6627" , 0x118008094cf18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6628" , 0x118008094cf20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6629" , 0x118008094cf28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6630" , 0x118008094cf30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6631" , 0x118008094cf38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6632" , 0x118008094cf40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6633" , 0x118008094cf48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6634" , 0x118008094cf50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6635" , 0x118008094cf58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6636" , 0x118008094cf60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6637" , 0x118008094cf68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6638" , 0x118008094cf70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6639" , 0x118008094cf78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6640" , 0x118008094cf80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6641" , 0x118008094cf88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6642" , 0x118008094cf90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6643" , 0x118008094cf98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6644" , 0x118008094cfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6645" , 0x118008094cfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6646" , 0x118008094cfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6647" , 0x118008094cfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6648" , 0x118008094cfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6649" , 0x118008094cfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6650" , 0x118008094cfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6651" , 0x118008094cfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6652" , 0x118008094cfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6653" , 0x118008094cfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6654" , 0x118008094cff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6655" , 0x118008094cff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6656" , 0x118008094d000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6657" , 0x118008094d008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6658" , 0x118008094d010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6659" , 0x118008094d018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6660" , 0x118008094d020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6661" , 0x118008094d028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6662" , 0x118008094d030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6663" , 0x118008094d038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6664" , 0x118008094d040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6665" , 0x118008094d048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6666" , 0x118008094d050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6667" , 0x118008094d058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6668" , 0x118008094d060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6669" , 0x118008094d068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6670" , 0x118008094d070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6671" , 0x118008094d078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6672" , 0x118008094d080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6673" , 0x118008094d088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6674" , 0x118008094d090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6675" , 0x118008094d098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6676" , 0x118008094d0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6677" , 0x118008094d0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6678" , 0x118008094d0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6679" , 0x118008094d0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6680" , 0x118008094d0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6681" , 0x118008094d0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6682" , 0x118008094d0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6683" , 0x118008094d0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6684" , 0x118008094d0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6685" , 0x118008094d0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6686" , 0x118008094d0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6687" , 0x118008094d0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6688" , 0x118008094d100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6689" , 0x118008094d108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6690" , 0x118008094d110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6691" , 0x118008094d118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6692" , 0x118008094d120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6693" , 0x118008094d128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6694" , 0x118008094d130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6695" , 0x118008094d138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6696" , 0x118008094d140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6697" , 0x118008094d148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6698" , 0x118008094d150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6699" , 0x118008094d158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6700" , 0x118008094d160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6701" , 0x118008094d168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6702" , 0x118008094d170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6703" , 0x118008094d178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6704" , 0x118008094d180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6705" , 0x118008094d188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6706" , 0x118008094d190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6707" , 0x118008094d198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6708" , 0x118008094d1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6709" , 0x118008094d1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6710" , 0x118008094d1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6711" , 0x118008094d1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6712" , 0x118008094d1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6713" , 0x118008094d1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6714" , 0x118008094d1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6715" , 0x118008094d1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6716" , 0x118008094d1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6717" , 0x118008094d1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6718" , 0x118008094d1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6719" , 0x118008094d1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6720" , 0x118008094d200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6721" , 0x118008094d208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6722" , 0x118008094d210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6723" , 0x118008094d218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6724" , 0x118008094d220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6725" , 0x118008094d228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6726" , 0x118008094d230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6727" , 0x118008094d238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6728" , 0x118008094d240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6729" , 0x118008094d248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6730" , 0x118008094d250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6731" , 0x118008094d258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6732" , 0x118008094d260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6733" , 0x118008094d268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6734" , 0x118008094d270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6735" , 0x118008094d278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6736" , 0x118008094d280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6737" , 0x118008094d288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6738" , 0x118008094d290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6739" , 0x118008094d298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6740" , 0x118008094d2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6741" , 0x118008094d2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6742" , 0x118008094d2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6743" , 0x118008094d2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6744" , 0x118008094d2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6745" , 0x118008094d2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6746" , 0x118008094d2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6747" , 0x118008094d2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6748" , 0x118008094d2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6749" , 0x118008094d2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6750" , 0x118008094d2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6751" , 0x118008094d2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6752" , 0x118008094d300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6753" , 0x118008094d308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6754" , 0x118008094d310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6755" , 0x118008094d318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6756" , 0x118008094d320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6757" , 0x118008094d328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6758" , 0x118008094d330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6759" , 0x118008094d338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6760" , 0x118008094d340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6761" , 0x118008094d348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6762" , 0x118008094d350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6763" , 0x118008094d358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6764" , 0x118008094d360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6765" , 0x118008094d368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6766" , 0x118008094d370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6767" , 0x118008094d378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6768" , 0x118008094d380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6769" , 0x118008094d388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6770" , 0x118008094d390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6771" , 0x118008094d398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6772" , 0x118008094d3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6773" , 0x118008094d3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6774" , 0x118008094d3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6775" , 0x118008094d3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6776" , 0x118008094d3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6777" , 0x118008094d3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6778" , 0x118008094d3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6779" , 0x118008094d3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6780" , 0x118008094d3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6781" , 0x118008094d3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6782" , 0x118008094d3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6783" , 0x118008094d3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6784" , 0x118008094d400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6785" , 0x118008094d408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6786" , 0x118008094d410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6787" , 0x118008094d418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6788" , 0x118008094d420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6789" , 0x118008094d428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6790" , 0x118008094d430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6791" , 0x118008094d438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6792" , 0x118008094d440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6793" , 0x118008094d448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6794" , 0x118008094d450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6795" , 0x118008094d458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6796" , 0x118008094d460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6797" , 0x118008094d468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6798" , 0x118008094d470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6799" , 0x118008094d478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6800" , 0x118008094d480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6801" , 0x118008094d488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6802" , 0x118008094d490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6803" , 0x118008094d498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6804" , 0x118008094d4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6805" , 0x118008094d4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6806" , 0x118008094d4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6807" , 0x118008094d4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6808" , 0x118008094d4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6809" , 0x118008094d4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6810" , 0x118008094d4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6811" , 0x118008094d4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6812" , 0x118008094d4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6813" , 0x118008094d4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6814" , 0x118008094d4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6815" , 0x118008094d4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6816" , 0x118008094d500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6817" , 0x118008094d508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6818" , 0x118008094d510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6819" , 0x118008094d518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6820" , 0x118008094d520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6821" , 0x118008094d528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6822" , 0x118008094d530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6823" , 0x118008094d538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6824" , 0x118008094d540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6825" , 0x118008094d548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6826" , 0x118008094d550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6827" , 0x118008094d558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6828" , 0x118008094d560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6829" , 0x118008094d568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6830" , 0x118008094d570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6831" , 0x118008094d578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6832" , 0x118008094d580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6833" , 0x118008094d588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6834" , 0x118008094d590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6835" , 0x118008094d598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6836" , 0x118008094d5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6837" , 0x118008094d5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6838" , 0x118008094d5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6839" , 0x118008094d5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6840" , 0x118008094d5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6841" , 0x118008094d5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6842" , 0x118008094d5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6843" , 0x118008094d5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6844" , 0x118008094d5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6845" , 0x118008094d5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6846" , 0x118008094d5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6847" , 0x118008094d5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6848" , 0x118008094d600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6849" , 0x118008094d608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6850" , 0x118008094d610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6851" , 0x118008094d618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6852" , 0x118008094d620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6853" , 0x118008094d628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6854" , 0x118008094d630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6855" , 0x118008094d638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6856" , 0x118008094d640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6857" , 0x118008094d648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6858" , 0x118008094d650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6859" , 0x118008094d658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6860" , 0x118008094d660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6861" , 0x118008094d668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6862" , 0x118008094d670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6863" , 0x118008094d678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6864" , 0x118008094d680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6865" , 0x118008094d688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6866" , 0x118008094d690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6867" , 0x118008094d698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6868" , 0x118008094d6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6869" , 0x118008094d6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6870" , 0x118008094d6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6871" , 0x118008094d6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6872" , 0x118008094d6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6873" , 0x118008094d6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6874" , 0x118008094d6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6875" , 0x118008094d6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6876" , 0x118008094d6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6877" , 0x118008094d6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6878" , 0x118008094d6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6879" , 0x118008094d6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6880" , 0x118008094d700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6881" , 0x118008094d708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6882" , 0x118008094d710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6883" , 0x118008094d718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6884" , 0x118008094d720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6885" , 0x118008094d728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6886" , 0x118008094d730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6887" , 0x118008094d738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6888" , 0x118008094d740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6889" , 0x118008094d748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6890" , 0x118008094d750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6891" , 0x118008094d758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6892" , 0x118008094d760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6893" , 0x118008094d768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6894" , 0x118008094d770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6895" , 0x118008094d778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6896" , 0x118008094d780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6897" , 0x118008094d788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6898" , 0x118008094d790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6899" , 0x118008094d798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6900" , 0x118008094d7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6901" , 0x118008094d7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6902" , 0x118008094d7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6903" , 0x118008094d7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6904" , 0x118008094d7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6905" , 0x118008094d7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6906" , 0x118008094d7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6907" , 0x118008094d7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6908" , 0x118008094d7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6909" , 0x118008094d7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6910" , 0x118008094d7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6911" , 0x118008094d7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6912" , 0x118008094d800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6913" , 0x118008094d808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6914" , 0x118008094d810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6915" , 0x118008094d818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6916" , 0x118008094d820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6917" , 0x118008094d828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6918" , 0x118008094d830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6919" , 0x118008094d838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6920" , 0x118008094d840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6921" , 0x118008094d848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6922" , 0x118008094d850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6923" , 0x118008094d858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6924" , 0x118008094d860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6925" , 0x118008094d868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6926" , 0x118008094d870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6927" , 0x118008094d878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6928" , 0x118008094d880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6929" , 0x118008094d888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6930" , 0x118008094d890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6931" , 0x118008094d898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6932" , 0x118008094d8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6933" , 0x118008094d8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6934" , 0x118008094d8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6935" , 0x118008094d8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6936" , 0x118008094d8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6937" , 0x118008094d8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6938" , 0x118008094d8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6939" , 0x118008094d8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6940" , 0x118008094d8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6941" , 0x118008094d8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6942" , 0x118008094d8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6943" , 0x118008094d8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6944" , 0x118008094d900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6945" , 0x118008094d908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6946" , 0x118008094d910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6947" , 0x118008094d918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6948" , 0x118008094d920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6949" , 0x118008094d928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6950" , 0x118008094d930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6951" , 0x118008094d938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6952" , 0x118008094d940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6953" , 0x118008094d948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6954" , 0x118008094d950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6955" , 0x118008094d958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6956" , 0x118008094d960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6957" , 0x118008094d968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6958" , 0x118008094d970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6959" , 0x118008094d978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6960" , 0x118008094d980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6961" , 0x118008094d988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6962" , 0x118008094d990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6963" , 0x118008094d998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6964" , 0x118008094d9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6965" , 0x118008094d9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6966" , 0x118008094d9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6967" , 0x118008094d9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6968" , 0x118008094d9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6969" , 0x118008094d9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6970" , 0x118008094d9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6971" , 0x118008094d9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6972" , 0x118008094d9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6973" , 0x118008094d9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6974" , 0x118008094d9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6975" , 0x118008094d9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6976" , 0x118008094da00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6977" , 0x118008094da08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6978" , 0x118008094da10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6979" , 0x118008094da18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6980" , 0x118008094da20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6981" , 0x118008094da28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6982" , 0x118008094da30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6983" , 0x118008094da38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6984" , 0x118008094da40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6985" , 0x118008094da48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6986" , 0x118008094da50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6987" , 0x118008094da58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6988" , 0x118008094da60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6989" , 0x118008094da68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6990" , 0x118008094da70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6991" , 0x118008094da78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6992" , 0x118008094da80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6993" , 0x118008094da88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6994" , 0x118008094da90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6995" , 0x118008094da98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6996" , 0x118008094daa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6997" , 0x118008094daa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6998" , 0x118008094dab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP6999" , 0x118008094dab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7000" , 0x118008094dac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7001" , 0x118008094dac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7002" , 0x118008094dad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7003" , 0x118008094dad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7004" , 0x118008094dae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7005" , 0x118008094dae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7006" , 0x118008094daf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7007" , 0x118008094daf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7008" , 0x118008094db00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7009" , 0x118008094db08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7010" , 0x118008094db10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7011" , 0x118008094db18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7012" , 0x118008094db20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7013" , 0x118008094db28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7014" , 0x118008094db30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7015" , 0x118008094db38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7016" , 0x118008094db40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7017" , 0x118008094db48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7018" , 0x118008094db50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7019" , 0x118008094db58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7020" , 0x118008094db60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7021" , 0x118008094db68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7022" , 0x118008094db70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7023" , 0x118008094db78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7024" , 0x118008094db80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7025" , 0x118008094db88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7026" , 0x118008094db90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7027" , 0x118008094db98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7028" , 0x118008094dba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7029" , 0x118008094dba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7030" , 0x118008094dbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7031" , 0x118008094dbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7032" , 0x118008094dbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7033" , 0x118008094dbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7034" , 0x118008094dbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7035" , 0x118008094dbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7036" , 0x118008094dbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7037" , 0x118008094dbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7038" , 0x118008094dbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7039" , 0x118008094dbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7040" , 0x118008094dc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7041" , 0x118008094dc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7042" , 0x118008094dc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7043" , 0x118008094dc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7044" , 0x118008094dc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7045" , 0x118008094dc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7046" , 0x118008094dc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7047" , 0x118008094dc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7048" , 0x118008094dc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7049" , 0x118008094dc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7050" , 0x118008094dc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7051" , 0x118008094dc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7052" , 0x118008094dc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7053" , 0x118008094dc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7054" , 0x118008094dc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7055" , 0x118008094dc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7056" , 0x118008094dc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7057" , 0x118008094dc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7058" , 0x118008094dc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7059" , 0x118008094dc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7060" , 0x118008094dca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7061" , 0x118008094dca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7062" , 0x118008094dcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7063" , 0x118008094dcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7064" , 0x118008094dcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7065" , 0x118008094dcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7066" , 0x118008094dcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7067" , 0x118008094dcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7068" , 0x118008094dce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7069" , 0x118008094dce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7070" , 0x118008094dcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7071" , 0x118008094dcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7072" , 0x118008094dd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7073" , 0x118008094dd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7074" , 0x118008094dd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7075" , 0x118008094dd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7076" , 0x118008094dd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7077" , 0x118008094dd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7078" , 0x118008094dd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7079" , 0x118008094dd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7080" , 0x118008094dd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7081" , 0x118008094dd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7082" , 0x118008094dd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7083" , 0x118008094dd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7084" , 0x118008094dd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7085" , 0x118008094dd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7086" , 0x118008094dd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7087" , 0x118008094dd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7088" , 0x118008094dd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7089" , 0x118008094dd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7090" , 0x118008094dd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7091" , 0x118008094dd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7092" , 0x118008094dda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7093" , 0x118008094dda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7094" , 0x118008094ddb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7095" , 0x118008094ddb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7096" , 0x118008094ddc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7097" , 0x118008094ddc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7098" , 0x118008094ddd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7099" , 0x118008094ddd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7100" , 0x118008094dde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7101" , 0x118008094dde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7102" , 0x118008094ddf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7103" , 0x118008094ddf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7104" , 0x118008094de00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7105" , 0x118008094de08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7106" , 0x118008094de10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7107" , 0x118008094de18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7108" , 0x118008094de20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7109" , 0x118008094de28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7110" , 0x118008094de30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7111" , 0x118008094de38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7112" , 0x118008094de40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7113" , 0x118008094de48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7114" , 0x118008094de50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7115" , 0x118008094de58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7116" , 0x118008094de60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7117" , 0x118008094de68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7118" , 0x118008094de70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7119" , 0x118008094de78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7120" , 0x118008094de80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7121" , 0x118008094de88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7122" , 0x118008094de90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7123" , 0x118008094de98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7124" , 0x118008094dea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7125" , 0x118008094dea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7126" , 0x118008094deb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7127" , 0x118008094deb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7128" , 0x118008094dec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7129" , 0x118008094dec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7130" , 0x118008094ded0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7131" , 0x118008094ded8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7132" , 0x118008094dee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7133" , 0x118008094dee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7134" , 0x118008094def0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7135" , 0x118008094def8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7136" , 0x118008094df00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7137" , 0x118008094df08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7138" , 0x118008094df10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7139" , 0x118008094df18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7140" , 0x118008094df20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7141" , 0x118008094df28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7142" , 0x118008094df30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7143" , 0x118008094df38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7144" , 0x118008094df40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7145" , 0x118008094df48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7146" , 0x118008094df50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7147" , 0x118008094df58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7148" , 0x118008094df60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7149" , 0x118008094df68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7150" , 0x118008094df70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7151" , 0x118008094df78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7152" , 0x118008094df80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7153" , 0x118008094df88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7154" , 0x118008094df90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7155" , 0x118008094df98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7156" , 0x118008094dfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7157" , 0x118008094dfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7158" , 0x118008094dfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7159" , 0x118008094dfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7160" , 0x118008094dfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7161" , 0x118008094dfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7162" , 0x118008094dfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7163" , 0x118008094dfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7164" , 0x118008094dfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7165" , 0x118008094dfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7166" , 0x118008094dff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7167" , 0x118008094dff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7168" , 0x118008094e000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7169" , 0x118008094e008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7170" , 0x118008094e010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7171" , 0x118008094e018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7172" , 0x118008094e020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7173" , 0x118008094e028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7174" , 0x118008094e030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7175" , 0x118008094e038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7176" , 0x118008094e040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7177" , 0x118008094e048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7178" , 0x118008094e050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7179" , 0x118008094e058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7180" , 0x118008094e060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7181" , 0x118008094e068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7182" , 0x118008094e070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7183" , 0x118008094e078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7184" , 0x118008094e080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7185" , 0x118008094e088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7186" , 0x118008094e090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7187" , 0x118008094e098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7188" , 0x118008094e0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7189" , 0x118008094e0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7190" , 0x118008094e0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7191" , 0x118008094e0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7192" , 0x118008094e0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7193" , 0x118008094e0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7194" , 0x118008094e0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7195" , 0x118008094e0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7196" , 0x118008094e0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7197" , 0x118008094e0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7198" , 0x118008094e0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7199" , 0x118008094e0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7200" , 0x118008094e100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7201" , 0x118008094e108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7202" , 0x118008094e110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7203" , 0x118008094e118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7204" , 0x118008094e120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7205" , 0x118008094e128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7206" , 0x118008094e130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7207" , 0x118008094e138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7208" , 0x118008094e140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7209" , 0x118008094e148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7210" , 0x118008094e150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7211" , 0x118008094e158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7212" , 0x118008094e160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7213" , 0x118008094e168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7214" , 0x118008094e170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7215" , 0x118008094e178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7216" , 0x118008094e180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7217" , 0x118008094e188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7218" , 0x118008094e190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7219" , 0x118008094e198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7220" , 0x118008094e1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7221" , 0x118008094e1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7222" , 0x118008094e1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7223" , 0x118008094e1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7224" , 0x118008094e1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7225" , 0x118008094e1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7226" , 0x118008094e1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7227" , 0x118008094e1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7228" , 0x118008094e1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7229" , 0x118008094e1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7230" , 0x118008094e1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7231" , 0x118008094e1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7232" , 0x118008094e200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7233" , 0x118008094e208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7234" , 0x118008094e210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7235" , 0x118008094e218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7236" , 0x118008094e220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7237" , 0x118008094e228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7238" , 0x118008094e230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7239" , 0x118008094e238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7240" , 0x118008094e240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7241" , 0x118008094e248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7242" , 0x118008094e250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7243" , 0x118008094e258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7244" , 0x118008094e260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7245" , 0x118008094e268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7246" , 0x118008094e270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7247" , 0x118008094e278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7248" , 0x118008094e280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7249" , 0x118008094e288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7250" , 0x118008094e290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7251" , 0x118008094e298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7252" , 0x118008094e2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7253" , 0x118008094e2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7254" , 0x118008094e2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7255" , 0x118008094e2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7256" , 0x118008094e2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7257" , 0x118008094e2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7258" , 0x118008094e2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7259" , 0x118008094e2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7260" , 0x118008094e2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7261" , 0x118008094e2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7262" , 0x118008094e2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7263" , 0x118008094e2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7264" , 0x118008094e300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7265" , 0x118008094e308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7266" , 0x118008094e310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7267" , 0x118008094e318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7268" , 0x118008094e320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7269" , 0x118008094e328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7270" , 0x118008094e330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7271" , 0x118008094e338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7272" , 0x118008094e340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7273" , 0x118008094e348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7274" , 0x118008094e350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7275" , 0x118008094e358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7276" , 0x118008094e360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7277" , 0x118008094e368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7278" , 0x118008094e370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7279" , 0x118008094e378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7280" , 0x118008094e380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7281" , 0x118008094e388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7282" , 0x118008094e390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7283" , 0x118008094e398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7284" , 0x118008094e3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7285" , 0x118008094e3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7286" , 0x118008094e3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7287" , 0x118008094e3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7288" , 0x118008094e3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7289" , 0x118008094e3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7290" , 0x118008094e3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7291" , 0x118008094e3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7292" , 0x118008094e3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7293" , 0x118008094e3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7294" , 0x118008094e3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7295" , 0x118008094e3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7296" , 0x118008094e400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7297" , 0x118008094e408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7298" , 0x118008094e410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7299" , 0x118008094e418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7300" , 0x118008094e420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7301" , 0x118008094e428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7302" , 0x118008094e430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7303" , 0x118008094e438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7304" , 0x118008094e440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7305" , 0x118008094e448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7306" , 0x118008094e450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7307" , 0x118008094e458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7308" , 0x118008094e460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7309" , 0x118008094e468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7310" , 0x118008094e470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7311" , 0x118008094e478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7312" , 0x118008094e480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7313" , 0x118008094e488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7314" , 0x118008094e490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7315" , 0x118008094e498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7316" , 0x118008094e4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7317" , 0x118008094e4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7318" , 0x118008094e4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7319" , 0x118008094e4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7320" , 0x118008094e4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7321" , 0x118008094e4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7322" , 0x118008094e4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7323" , 0x118008094e4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7324" , 0x118008094e4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7325" , 0x118008094e4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7326" , 0x118008094e4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7327" , 0x118008094e4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7328" , 0x118008094e500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7329" , 0x118008094e508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7330" , 0x118008094e510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7331" , 0x118008094e518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7332" , 0x118008094e520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7333" , 0x118008094e528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7334" , 0x118008094e530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7335" , 0x118008094e538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7336" , 0x118008094e540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7337" , 0x118008094e548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7338" , 0x118008094e550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7339" , 0x118008094e558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7340" , 0x118008094e560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7341" , 0x118008094e568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7342" , 0x118008094e570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7343" , 0x118008094e578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7344" , 0x118008094e580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7345" , 0x118008094e588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7346" , 0x118008094e590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7347" , 0x118008094e598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7348" , 0x118008094e5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7349" , 0x118008094e5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7350" , 0x118008094e5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7351" , 0x118008094e5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7352" , 0x118008094e5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7353" , 0x118008094e5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7354" , 0x118008094e5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7355" , 0x118008094e5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7356" , 0x118008094e5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7357" , 0x118008094e5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7358" , 0x118008094e5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7359" , 0x118008094e5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7360" , 0x118008094e600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7361" , 0x118008094e608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7362" , 0x118008094e610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7363" , 0x118008094e618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7364" , 0x118008094e620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7365" , 0x118008094e628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7366" , 0x118008094e630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7367" , 0x118008094e638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7368" , 0x118008094e640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7369" , 0x118008094e648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7370" , 0x118008094e650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7371" , 0x118008094e658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7372" , 0x118008094e660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7373" , 0x118008094e668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7374" , 0x118008094e670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7375" , 0x118008094e678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7376" , 0x118008094e680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7377" , 0x118008094e688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7378" , 0x118008094e690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7379" , 0x118008094e698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7380" , 0x118008094e6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7381" , 0x118008094e6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7382" , 0x118008094e6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7383" , 0x118008094e6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7384" , 0x118008094e6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7385" , 0x118008094e6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7386" , 0x118008094e6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7387" , 0x118008094e6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7388" , 0x118008094e6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7389" , 0x118008094e6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7390" , 0x118008094e6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7391" , 0x118008094e6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7392" , 0x118008094e700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7393" , 0x118008094e708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7394" , 0x118008094e710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7395" , 0x118008094e718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7396" , 0x118008094e720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7397" , 0x118008094e728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7398" , 0x118008094e730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7399" , 0x118008094e738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7400" , 0x118008094e740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7401" , 0x118008094e748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7402" , 0x118008094e750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7403" , 0x118008094e758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7404" , 0x118008094e760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7405" , 0x118008094e768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7406" , 0x118008094e770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7407" , 0x118008094e778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7408" , 0x118008094e780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7409" , 0x118008094e788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7410" , 0x118008094e790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7411" , 0x118008094e798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7412" , 0x118008094e7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7413" , 0x118008094e7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7414" , 0x118008094e7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7415" , 0x118008094e7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7416" , 0x118008094e7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7417" , 0x118008094e7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7418" , 0x118008094e7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7419" , 0x118008094e7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7420" , 0x118008094e7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7421" , 0x118008094e7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7422" , 0x118008094e7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7423" , 0x118008094e7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7424" , 0x118008094e800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7425" , 0x118008094e808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7426" , 0x118008094e810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7427" , 0x118008094e818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7428" , 0x118008094e820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7429" , 0x118008094e828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7430" , 0x118008094e830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7431" , 0x118008094e838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7432" , 0x118008094e840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7433" , 0x118008094e848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7434" , 0x118008094e850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7435" , 0x118008094e858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7436" , 0x118008094e860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7437" , 0x118008094e868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7438" , 0x118008094e870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7439" , 0x118008094e878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7440" , 0x118008094e880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7441" , 0x118008094e888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7442" , 0x118008094e890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7443" , 0x118008094e898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7444" , 0x118008094e8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7445" , 0x118008094e8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7446" , 0x118008094e8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7447" , 0x118008094e8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7448" , 0x118008094e8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7449" , 0x118008094e8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7450" , 0x118008094e8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7451" , 0x118008094e8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7452" , 0x118008094e8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7453" , 0x118008094e8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7454" , 0x118008094e8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7455" , 0x118008094e8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7456" , 0x118008094e900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7457" , 0x118008094e908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7458" , 0x118008094e910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7459" , 0x118008094e918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7460" , 0x118008094e920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7461" , 0x118008094e928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7462" , 0x118008094e930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7463" , 0x118008094e938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7464" , 0x118008094e940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7465" , 0x118008094e948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7466" , 0x118008094e950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7467" , 0x118008094e958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7468" , 0x118008094e960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7469" , 0x118008094e968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7470" , 0x118008094e970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7471" , 0x118008094e978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7472" , 0x118008094e980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7473" , 0x118008094e988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7474" , 0x118008094e990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7475" , 0x118008094e998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7476" , 0x118008094e9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7477" , 0x118008094e9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7478" , 0x118008094e9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7479" , 0x118008094e9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7480" , 0x118008094e9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7481" , 0x118008094e9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7482" , 0x118008094e9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7483" , 0x118008094e9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7484" , 0x118008094e9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7485" , 0x118008094e9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7486" , 0x118008094e9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7487" , 0x118008094e9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7488" , 0x118008094ea00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7489" , 0x118008094ea08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7490" , 0x118008094ea10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7491" , 0x118008094ea18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7492" , 0x118008094ea20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7493" , 0x118008094ea28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7494" , 0x118008094ea30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7495" , 0x118008094ea38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7496" , 0x118008094ea40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7497" , 0x118008094ea48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7498" , 0x118008094ea50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7499" , 0x118008094ea58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7500" , 0x118008094ea60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7501" , 0x118008094ea68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7502" , 0x118008094ea70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7503" , 0x118008094ea78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7504" , 0x118008094ea80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7505" , 0x118008094ea88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7506" , 0x118008094ea90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7507" , 0x118008094ea98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7508" , 0x118008094eaa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7509" , 0x118008094eaa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7510" , 0x118008094eab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7511" , 0x118008094eab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7512" , 0x118008094eac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7513" , 0x118008094eac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7514" , 0x118008094ead0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7515" , 0x118008094ead8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7516" , 0x118008094eae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7517" , 0x118008094eae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7518" , 0x118008094eaf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7519" , 0x118008094eaf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7520" , 0x118008094eb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7521" , 0x118008094eb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7522" , 0x118008094eb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7523" , 0x118008094eb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7524" , 0x118008094eb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7525" , 0x118008094eb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7526" , 0x118008094eb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7527" , 0x118008094eb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7528" , 0x118008094eb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7529" , 0x118008094eb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7530" , 0x118008094eb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7531" , 0x118008094eb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7532" , 0x118008094eb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7533" , 0x118008094eb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7534" , 0x118008094eb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7535" , 0x118008094eb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7536" , 0x118008094eb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7537" , 0x118008094eb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7538" , 0x118008094eb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7539" , 0x118008094eb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7540" , 0x118008094eba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7541" , 0x118008094eba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7542" , 0x118008094ebb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7543" , 0x118008094ebb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7544" , 0x118008094ebc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7545" , 0x118008094ebc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7546" , 0x118008094ebd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7547" , 0x118008094ebd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7548" , 0x118008094ebe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7549" , 0x118008094ebe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7550" , 0x118008094ebf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7551" , 0x118008094ebf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7552" , 0x118008094ec00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7553" , 0x118008094ec08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7554" , 0x118008094ec10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7555" , 0x118008094ec18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7556" , 0x118008094ec20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7557" , 0x118008094ec28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7558" , 0x118008094ec30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7559" , 0x118008094ec38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7560" , 0x118008094ec40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7561" , 0x118008094ec48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7562" , 0x118008094ec50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7563" , 0x118008094ec58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7564" , 0x118008094ec60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7565" , 0x118008094ec68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7566" , 0x118008094ec70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7567" , 0x118008094ec78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7568" , 0x118008094ec80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7569" , 0x118008094ec88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7570" , 0x118008094ec90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7571" , 0x118008094ec98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7572" , 0x118008094eca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7573" , 0x118008094eca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7574" , 0x118008094ecb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7575" , 0x118008094ecb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7576" , 0x118008094ecc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7577" , 0x118008094ecc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7578" , 0x118008094ecd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7579" , 0x118008094ecd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7580" , 0x118008094ece0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7581" , 0x118008094ece8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7582" , 0x118008094ecf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7583" , 0x118008094ecf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7584" , 0x118008094ed00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7585" , 0x118008094ed08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7586" , 0x118008094ed10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7587" , 0x118008094ed18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7588" , 0x118008094ed20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7589" , 0x118008094ed28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7590" , 0x118008094ed30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7591" , 0x118008094ed38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7592" , 0x118008094ed40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7593" , 0x118008094ed48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7594" , 0x118008094ed50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7595" , 0x118008094ed58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7596" , 0x118008094ed60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7597" , 0x118008094ed68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7598" , 0x118008094ed70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7599" , 0x118008094ed78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7600" , 0x118008094ed80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7601" , 0x118008094ed88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7602" , 0x118008094ed90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7603" , 0x118008094ed98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7604" , 0x118008094eda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7605" , 0x118008094eda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7606" , 0x118008094edb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7607" , 0x118008094edb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7608" , 0x118008094edc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7609" , 0x118008094edc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7610" , 0x118008094edd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7611" , 0x118008094edd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7612" , 0x118008094ede0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7613" , 0x118008094ede8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7614" , 0x118008094edf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7615" , 0x118008094edf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7616" , 0x118008094ee00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7617" , 0x118008094ee08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7618" , 0x118008094ee10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7619" , 0x118008094ee18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7620" , 0x118008094ee20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7621" , 0x118008094ee28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7622" , 0x118008094ee30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7623" , 0x118008094ee38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7624" , 0x118008094ee40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7625" , 0x118008094ee48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7626" , 0x118008094ee50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7627" , 0x118008094ee58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7628" , 0x118008094ee60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7629" , 0x118008094ee68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7630" , 0x118008094ee70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7631" , 0x118008094ee78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7632" , 0x118008094ee80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7633" , 0x118008094ee88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7634" , 0x118008094ee90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7635" , 0x118008094ee98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7636" , 0x118008094eea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7637" , 0x118008094eea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7638" , 0x118008094eeb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7639" , 0x118008094eeb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7640" , 0x118008094eec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7641" , 0x118008094eec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7642" , 0x118008094eed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7643" , 0x118008094eed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7644" , 0x118008094eee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7645" , 0x118008094eee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7646" , 0x118008094eef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7647" , 0x118008094eef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7648" , 0x118008094ef00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7649" , 0x118008094ef08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7650" , 0x118008094ef10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7651" , 0x118008094ef18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7652" , 0x118008094ef20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7653" , 0x118008094ef28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7654" , 0x118008094ef30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7655" , 0x118008094ef38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7656" , 0x118008094ef40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7657" , 0x118008094ef48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7658" , 0x118008094ef50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7659" , 0x118008094ef58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7660" , 0x118008094ef60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7661" , 0x118008094ef68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7662" , 0x118008094ef70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7663" , 0x118008094ef78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7664" , 0x118008094ef80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7665" , 0x118008094ef88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7666" , 0x118008094ef90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7667" , 0x118008094ef98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7668" , 0x118008094efa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7669" , 0x118008094efa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7670" , 0x118008094efb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7671" , 0x118008094efb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7672" , 0x118008094efc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7673" , 0x118008094efc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7674" , 0x118008094efd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7675" , 0x118008094efd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7676" , 0x118008094efe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7677" , 0x118008094efe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7678" , 0x118008094eff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7679" , 0x118008094eff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7680" , 0x118008094f000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7681" , 0x118008094f008ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7682" , 0x118008094f010ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7683" , 0x118008094f018ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7684" , 0x118008094f020ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7685" , 0x118008094f028ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7686" , 0x118008094f030ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7687" , 0x118008094f038ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7688" , 0x118008094f040ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7689" , 0x118008094f048ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7690" , 0x118008094f050ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7691" , 0x118008094f058ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7692" , 0x118008094f060ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7693" , 0x118008094f068ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7694" , 0x118008094f070ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7695" , 0x118008094f078ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7696" , 0x118008094f080ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7697" , 0x118008094f088ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7698" , 0x118008094f090ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7699" , 0x118008094f098ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7700" , 0x118008094f0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7701" , 0x118008094f0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7702" , 0x118008094f0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7703" , 0x118008094f0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7704" , 0x118008094f0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7705" , 0x118008094f0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7706" , 0x118008094f0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7707" , 0x118008094f0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7708" , 0x118008094f0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7709" , 0x118008094f0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7710" , 0x118008094f0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7711" , 0x118008094f0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7712" , 0x118008094f100ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7713" , 0x118008094f108ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7714" , 0x118008094f110ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7715" , 0x118008094f118ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7716" , 0x118008094f120ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7717" , 0x118008094f128ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7718" , 0x118008094f130ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7719" , 0x118008094f138ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7720" , 0x118008094f140ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7721" , 0x118008094f148ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7722" , 0x118008094f150ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7723" , 0x118008094f158ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7724" , 0x118008094f160ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7725" , 0x118008094f168ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7726" , 0x118008094f170ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7727" , 0x118008094f178ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7728" , 0x118008094f180ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7729" , 0x118008094f188ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7730" , 0x118008094f190ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7731" , 0x118008094f198ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7732" , 0x118008094f1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7733" , 0x118008094f1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7734" , 0x118008094f1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7735" , 0x118008094f1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7736" , 0x118008094f1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7737" , 0x118008094f1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7738" , 0x118008094f1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7739" , 0x118008094f1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7740" , 0x118008094f1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7741" , 0x118008094f1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7742" , 0x118008094f1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7743" , 0x118008094f1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7744" , 0x118008094f200ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7745" , 0x118008094f208ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7746" , 0x118008094f210ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7747" , 0x118008094f218ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7748" , 0x118008094f220ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7749" , 0x118008094f228ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7750" , 0x118008094f230ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7751" , 0x118008094f238ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7752" , 0x118008094f240ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7753" , 0x118008094f248ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7754" , 0x118008094f250ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7755" , 0x118008094f258ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7756" , 0x118008094f260ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7757" , 0x118008094f268ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7758" , 0x118008094f270ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7759" , 0x118008094f278ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7760" , 0x118008094f280ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7761" , 0x118008094f288ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7762" , 0x118008094f290ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7763" , 0x118008094f298ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7764" , 0x118008094f2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7765" , 0x118008094f2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7766" , 0x118008094f2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7767" , 0x118008094f2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7768" , 0x118008094f2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7769" , 0x118008094f2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7770" , 0x118008094f2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7771" , 0x118008094f2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7772" , 0x118008094f2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7773" , 0x118008094f2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7774" , 0x118008094f2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7775" , 0x118008094f2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7776" , 0x118008094f300ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7777" , 0x118008094f308ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7778" , 0x118008094f310ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7779" , 0x118008094f318ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7780" , 0x118008094f320ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7781" , 0x118008094f328ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7782" , 0x118008094f330ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7783" , 0x118008094f338ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7784" , 0x118008094f340ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7785" , 0x118008094f348ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7786" , 0x118008094f350ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7787" , 0x118008094f358ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7788" , 0x118008094f360ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7789" , 0x118008094f368ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7790" , 0x118008094f370ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7791" , 0x118008094f378ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7792" , 0x118008094f380ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7793" , 0x118008094f388ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7794" , 0x118008094f390ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7795" , 0x118008094f398ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7796" , 0x118008094f3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7797" , 0x118008094f3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7798" , 0x118008094f3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7799" , 0x118008094f3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7800" , 0x118008094f3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7801" , 0x118008094f3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7802" , 0x118008094f3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7803" , 0x118008094f3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7804" , 0x118008094f3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7805" , 0x118008094f3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7806" , 0x118008094f3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7807" , 0x118008094f3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7808" , 0x118008094f400ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7809" , 0x118008094f408ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7810" , 0x118008094f410ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7811" , 0x118008094f418ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7812" , 0x118008094f420ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7813" , 0x118008094f428ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7814" , 0x118008094f430ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7815" , 0x118008094f438ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7816" , 0x118008094f440ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7817" , 0x118008094f448ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7818" , 0x118008094f450ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7819" , 0x118008094f458ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7820" , 0x118008094f460ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7821" , 0x118008094f468ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7822" , 0x118008094f470ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7823" , 0x118008094f478ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7824" , 0x118008094f480ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7825" , 0x118008094f488ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7826" , 0x118008094f490ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7827" , 0x118008094f498ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7828" , 0x118008094f4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7829" , 0x118008094f4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7830" , 0x118008094f4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7831" , 0x118008094f4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7832" , 0x118008094f4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7833" , 0x118008094f4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7834" , 0x118008094f4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7835" , 0x118008094f4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7836" , 0x118008094f4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7837" , 0x118008094f4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7838" , 0x118008094f4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7839" , 0x118008094f4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7840" , 0x118008094f500ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7841" , 0x118008094f508ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7842" , 0x118008094f510ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7843" , 0x118008094f518ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7844" , 0x118008094f520ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7845" , 0x118008094f528ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7846" , 0x118008094f530ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7847" , 0x118008094f538ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7848" , 0x118008094f540ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7849" , 0x118008094f548ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7850" , 0x118008094f550ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7851" , 0x118008094f558ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7852" , 0x118008094f560ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7853" , 0x118008094f568ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7854" , 0x118008094f570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7855" , 0x118008094f578ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7856" , 0x118008094f580ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7857" , 0x118008094f588ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7858" , 0x118008094f590ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7859" , 0x118008094f598ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7860" , 0x118008094f5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7861" , 0x118008094f5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7862" , 0x118008094f5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7863" , 0x118008094f5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7864" , 0x118008094f5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7865" , 0x118008094f5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7866" , 0x118008094f5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7867" , 0x118008094f5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7868" , 0x118008094f5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7869" , 0x118008094f5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7870" , 0x118008094f5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7871" , 0x118008094f5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7872" , 0x118008094f600ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7873" , 0x118008094f608ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7874" , 0x118008094f610ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7875" , 0x118008094f618ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7876" , 0x118008094f620ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7877" , 0x118008094f628ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7878" , 0x118008094f630ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7879" , 0x118008094f638ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7880" , 0x118008094f640ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7881" , 0x118008094f648ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7882" , 0x118008094f650ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7883" , 0x118008094f658ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7884" , 0x118008094f660ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7885" , 0x118008094f668ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7886" , 0x118008094f670ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7887" , 0x118008094f678ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7888" , 0x118008094f680ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7889" , 0x118008094f688ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7890" , 0x118008094f690ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7891" , 0x118008094f698ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7892" , 0x118008094f6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7893" , 0x118008094f6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7894" , 0x118008094f6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7895" , 0x118008094f6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7896" , 0x118008094f6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7897" , 0x118008094f6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7898" , 0x118008094f6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7899" , 0x118008094f6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7900" , 0x118008094f6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7901" , 0x118008094f6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7902" , 0x118008094f6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7903" , 0x118008094f6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7904" , 0x118008094f700ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7905" , 0x118008094f708ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7906" , 0x118008094f710ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7907" , 0x118008094f718ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7908" , 0x118008094f720ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7909" , 0x118008094f728ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7910" , 0x118008094f730ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7911" , 0x118008094f738ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7912" , 0x118008094f740ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7913" , 0x118008094f748ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7914" , 0x118008094f750ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7915" , 0x118008094f758ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7916" , 0x118008094f760ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7917" , 0x118008094f768ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7918" , 0x118008094f770ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7919" , 0x118008094f778ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7920" , 0x118008094f780ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7921" , 0x118008094f788ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7922" , 0x118008094f790ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7923" , 0x118008094f798ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7924" , 0x118008094f7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7925" , 0x118008094f7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7926" , 0x118008094f7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7927" , 0x118008094f7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7928" , 0x118008094f7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7929" , 0x118008094f7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7930" , 0x118008094f7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7931" , 0x118008094f7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7932" , 0x118008094f7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7933" , 0x118008094f7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7934" , 0x118008094f7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7935" , 0x118008094f7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7936" , 0x118008094f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7937" , 0x118008094f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7938" , 0x118008094f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7939" , 0x118008094f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7940" , 0x118008094f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7941" , 0x118008094f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7942" , 0x118008094f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7943" , 0x118008094f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7944" , 0x118008094f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7945" , 0x118008094f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7946" , 0x118008094f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7947" , 0x118008094f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7948" , 0x118008094f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7949" , 0x118008094f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7950" , 0x118008094f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7951" , 0x118008094f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7952" , 0x118008094f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7953" , 0x118008094f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7954" , 0x118008094f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7955" , 0x118008094f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7956" , 0x118008094f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7957" , 0x118008094f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7958" , 0x118008094f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7959" , 0x118008094f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7960" , 0x118008094f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7961" , 0x118008094f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7962" , 0x118008094f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7963" , 0x118008094f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7964" , 0x118008094f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7965" , 0x118008094f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7966" , 0x118008094f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7967" , 0x118008094f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7968" , 0x118008094f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7969" , 0x118008094f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7970" , 0x118008094f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7971" , 0x118008094f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7972" , 0x118008094f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7973" , 0x118008094f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7974" , 0x118008094f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7975" , 0x118008094f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7976" , 0x118008094f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7977" , 0x118008094f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7978" , 0x118008094f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7979" , 0x118008094f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7980" , 0x118008094f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7981" , 0x118008094f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7982" , 0x118008094f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7983" , 0x118008094f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7984" , 0x118008094f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7985" , 0x118008094f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7986" , 0x118008094f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7987" , 0x118008094f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7988" , 0x118008094f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7989" , 0x118008094f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7990" , 0x118008094f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7991" , 0x118008094f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7992" , 0x118008094f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7993" , 0x118008094f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7994" , 0x118008094f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7995" , 0x118008094f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7996" , 0x118008094f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7997" , 0x118008094f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7998" , 0x118008094f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP7999" , 0x118008094f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8000" , 0x118008094fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8001" , 0x118008094fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8002" , 0x118008094fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8003" , 0x118008094fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8004" , 0x118008094fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8005" , 0x118008094fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8006" , 0x118008094fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8007" , 0x118008094fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8008" , 0x118008094fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8009" , 0x118008094fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8010" , 0x118008094fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8011" , 0x118008094fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8012" , 0x118008094fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8013" , 0x118008094fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8014" , 0x118008094fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8015" , 0x118008094fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8016" , 0x118008094fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8017" , 0x118008094fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8018" , 0x118008094fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8019" , 0x118008094fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8020" , 0x118008094faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8021" , 0x118008094faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8022" , 0x118008094fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8023" , 0x118008094fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8024" , 0x118008094fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8025" , 0x118008094fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8026" , 0x118008094fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8027" , 0x118008094fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8028" , 0x118008094fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8029" , 0x118008094fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8030" , 0x118008094faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8031" , 0x118008094faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8032" , 0x118008094fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8033" , 0x118008094fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8034" , 0x118008094fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8035" , 0x118008094fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8036" , 0x118008094fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8037" , 0x118008094fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8038" , 0x118008094fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8039" , 0x118008094fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8040" , 0x118008094fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8041" , 0x118008094fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8042" , 0x118008094fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8043" , 0x118008094fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8044" , 0x118008094fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8045" , 0x118008094fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8046" , 0x118008094fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8047" , 0x118008094fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8048" , 0x118008094fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8049" , 0x118008094fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8050" , 0x118008094fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8051" , 0x118008094fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8052" , 0x118008094fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8053" , 0x118008094fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8054" , 0x118008094fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8055" , 0x118008094fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8056" , 0x118008094fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8057" , 0x118008094fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8058" , 0x118008094fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8059" , 0x118008094fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8060" , 0x118008094fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8061" , 0x118008094fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8062" , 0x118008094fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8063" , 0x118008094fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8064" , 0x118008094fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8065" , 0x118008094fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8066" , 0x118008094fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8067" , 0x118008094fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8068" , 0x118008094fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8069" , 0x118008094fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8070" , 0x118008094fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8071" , 0x118008094fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8072" , 0x118008094fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8073" , 0x118008094fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8074" , 0x118008094fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8075" , 0x118008094fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8076" , 0x118008094fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8077" , 0x118008094fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8078" , 0x118008094fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8079" , 0x118008094fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8080" , 0x118008094fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8081" , 0x118008094fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8082" , 0x118008094fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8083" , 0x118008094fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8084" , 0x118008094fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8085" , 0x118008094fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8086" , 0x118008094fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8087" , 0x118008094fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8088" , 0x118008094fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8089" , 0x118008094fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8090" , 0x118008094fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8091" , 0x118008094fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8092" , 0x118008094fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8093" , 0x118008094fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8094" , 0x118008094fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8095" , 0x118008094fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8096" , 0x118008094fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8097" , 0x118008094fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8098" , 0x118008094fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8099" , 0x118008094fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8100" , 0x118008094fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8101" , 0x118008094fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8102" , 0x118008094fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8103" , 0x118008094fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8104" , 0x118008094fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8105" , 0x118008094fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8106" , 0x118008094fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8107" , 0x118008094fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8108" , 0x118008094fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8109" , 0x118008094fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8110" , 0x118008094fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8111" , 0x118008094fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8112" , 0x118008094fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8113" , 0x118008094fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8114" , 0x118008094fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8115" , 0x118008094fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8116" , 0x118008094fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8117" , 0x118008094fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8118" , 0x118008094fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8119" , 0x118008094fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8120" , 0x118008094fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8121" , 0x118008094fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8122" , 0x118008094fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8123" , 0x118008094fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8124" , 0x118008094fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8125" , 0x118008094fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8126" , 0x118008094fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8127" , 0x118008094fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8128" , 0x118008094fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8129" , 0x118008094fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8130" , 0x118008094fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8131" , 0x118008094fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8132" , 0x118008094fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8133" , 0x118008094fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8134" , 0x118008094fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8135" , 0x118008094fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8136" , 0x118008094fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8137" , 0x118008094fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8138" , 0x118008094fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8139" , 0x118008094fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8140" , 0x118008094fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8141" , 0x118008094fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8142" , 0x118008094fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8143" , 0x118008094fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8144" , 0x118008094fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8145" , 0x118008094fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8146" , 0x118008094fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8147" , 0x118008094fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8148" , 0x118008094fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8149" , 0x118008094fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8150" , 0x118008094feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8151" , 0x118008094feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8152" , 0x118008094fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8153" , 0x118008094fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8154" , 0x118008094fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8155" , 0x118008094fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8156" , 0x118008094fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8157" , 0x118008094fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8158" , 0x118008094fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8159" , 0x118008094fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8160" , 0x118008094ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8161" , 0x118008094ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8162" , 0x118008094ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8163" , 0x118008094ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8164" , 0x118008094ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8165" , 0x118008094ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8166" , 0x118008094ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8167" , 0x118008094ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8168" , 0x118008094ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8169" , 0x118008094ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8170" , 0x118008094ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8171" , 0x118008094ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8172" , 0x118008094ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8173" , 0x118008094ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8174" , 0x118008094ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8175" , 0x118008094ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8176" , 0x118008094ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8177" , 0x118008094ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8178" , 0x118008094ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8179" , 0x118008094ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8180" , 0x118008094ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8181" , 0x118008094ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8182" , 0x118008094ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8183" , 0x118008094ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8184" , 0x118008094ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8185" , 0x118008094ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8186" , 0x118008094ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8187" , 0x118008094ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8188" , 0x118008094ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8189" , 0x118008094ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8190" , 0x118008094fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP8191" , 0x118008094fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16128" , 0x118008095f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16129" , 0x118008095f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16130" , 0x118008095f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16131" , 0x118008095f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16132" , 0x118008095f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16133" , 0x118008095f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16134" , 0x118008095f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16135" , 0x118008095f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16136" , 0x118008095f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16137" , 0x118008095f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16138" , 0x118008095f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16139" , 0x118008095f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16140" , 0x118008095f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16141" , 0x118008095f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16142" , 0x118008095f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16143" , 0x118008095f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16144" , 0x118008095f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16145" , 0x118008095f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16146" , 0x118008095f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16147" , 0x118008095f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16148" , 0x118008095f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16149" , 0x118008095f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16150" , 0x118008095f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16151" , 0x118008095f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16152" , 0x118008095f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16153" , 0x118008095f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16154" , 0x118008095f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16155" , 0x118008095f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16156" , 0x118008095f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16157" , 0x118008095f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16158" , 0x118008095f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16159" , 0x118008095f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16160" , 0x118008095f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16161" , 0x118008095f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16162" , 0x118008095f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16163" , 0x118008095f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16164" , 0x118008095f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16165" , 0x118008095f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16166" , 0x118008095f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16167" , 0x118008095f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16168" , 0x118008095f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16169" , 0x118008095f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16170" , 0x118008095f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16171" , 0x118008095f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16172" , 0x118008095f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16173" , 0x118008095f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16174" , 0x118008095f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16175" , 0x118008095f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16176" , 0x118008095f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16177" , 0x118008095f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16178" , 0x118008095f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16179" , 0x118008095f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16180" , 0x118008095f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16181" , 0x118008095f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16182" , 0x118008095f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16183" , 0x118008095f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16184" , 0x118008095f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16185" , 0x118008095f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16186" , 0x118008095f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16187" , 0x118008095f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16188" , 0x118008095f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16189" , 0x118008095f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16190" , 0x118008095f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16191" , 0x118008095f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16192" , 0x118008095fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16193" , 0x118008095fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16194" , 0x118008095fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16195" , 0x118008095fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16196" , 0x118008095fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16197" , 0x118008095fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16198" , 0x118008095fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16199" , 0x118008095fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16200" , 0x118008095fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16201" , 0x118008095fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16202" , 0x118008095fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16203" , 0x118008095fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16204" , 0x118008095fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16205" , 0x118008095fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16206" , 0x118008095fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16207" , 0x118008095fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16208" , 0x118008095fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16209" , 0x118008095fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16210" , 0x118008095fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16211" , 0x118008095fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16212" , 0x118008095faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16213" , 0x118008095faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16214" , 0x118008095fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16215" , 0x118008095fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16216" , 0x118008095fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16217" , 0x118008095fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16218" , 0x118008095fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16219" , 0x118008095fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16220" , 0x118008095fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16221" , 0x118008095fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16222" , 0x118008095faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16223" , 0x118008095faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16224" , 0x118008095fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16225" , 0x118008095fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16226" , 0x118008095fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16227" , 0x118008095fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16228" , 0x118008095fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16229" , 0x118008095fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16230" , 0x118008095fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16231" , 0x118008095fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16232" , 0x118008095fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16233" , 0x118008095fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16234" , 0x118008095fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16235" , 0x118008095fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16236" , 0x118008095fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16237" , 0x118008095fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16238" , 0x118008095fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16239" , 0x118008095fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16240" , 0x118008095fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16241" , 0x118008095fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16242" , 0x118008095fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16243" , 0x118008095fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16244" , 0x118008095fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16245" , 0x118008095fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16246" , 0x118008095fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16247" , 0x118008095fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16248" , 0x118008095fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16249" , 0x118008095fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16250" , 0x118008095fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16251" , 0x118008095fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16252" , 0x118008095fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16253" , 0x118008095fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16254" , 0x118008095fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16255" , 0x118008095fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16256" , 0x118008095fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16257" , 0x118008095fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16258" , 0x118008095fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16259" , 0x118008095fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16260" , 0x118008095fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16261" , 0x118008095fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16262" , 0x118008095fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16263" , 0x118008095fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16264" , 0x118008095fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16265" , 0x118008095fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16266" , 0x118008095fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16267" , 0x118008095fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16268" , 0x118008095fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16269" , 0x118008095fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16270" , 0x118008095fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16271" , 0x118008095fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16272" , 0x118008095fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16273" , 0x118008095fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16274" , 0x118008095fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16275" , 0x118008095fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16276" , 0x118008095fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16277" , 0x118008095fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16278" , 0x118008095fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16279" , 0x118008095fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16280" , 0x118008095fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16281" , 0x118008095fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16282" , 0x118008095fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16283" , 0x118008095fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16284" , 0x118008095fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16285" , 0x118008095fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16286" , 0x118008095fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16287" , 0x118008095fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16288" , 0x118008095fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16289" , 0x118008095fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16290" , 0x118008095fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16291" , 0x118008095fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16292" , 0x118008095fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16293" , 0x118008095fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16294" , 0x118008095fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16295" , 0x118008095fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16296" , 0x118008095fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16297" , 0x118008095fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16298" , 0x118008095fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16299" , 0x118008095fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16300" , 0x118008095fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16301" , 0x118008095fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16302" , 0x118008095fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16303" , 0x118008095fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16304" , 0x118008095fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16305" , 0x118008095fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16306" , 0x118008095fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16307" , 0x118008095fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16308" , 0x118008095fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16309" , 0x118008095fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16310" , 0x118008095fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16311" , 0x118008095fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16312" , 0x118008095fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16313" , 0x118008095fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16314" , 0x118008095fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16315" , 0x118008095fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16316" , 0x118008095fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16317" , 0x118008095fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16318" , 0x118008095fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16319" , 0x118008095fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16320" , 0x118008095fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16321" , 0x118008095fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16322" , 0x118008095fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16323" , 0x118008095fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16324" , 0x118008095fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16325" , 0x118008095fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16326" , 0x118008095fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16327" , 0x118008095fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16328" , 0x118008095fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16329" , 0x118008095fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16330" , 0x118008095fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16331" , 0x118008095fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16332" , 0x118008095fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16333" , 0x118008095fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16334" , 0x118008095fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16335" , 0x118008095fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16336" , 0x118008095fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16337" , 0x118008095fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16338" , 0x118008095fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16339" , 0x118008095fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16340" , 0x118008095fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16341" , 0x118008095fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16342" , 0x118008095feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16343" , 0x118008095feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16344" , 0x118008095fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16345" , 0x118008095fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16346" , 0x118008095fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16347" , 0x118008095fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16348" , 0x118008095fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16349" , 0x118008095fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16350" , 0x118008095fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16351" , 0x118008095fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16352" , 0x118008095ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16353" , 0x118008095ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16354" , 0x118008095ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16355" , 0x118008095ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16356" , 0x118008095ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16357" , 0x118008095ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16358" , 0x118008095ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16359" , 0x118008095ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16360" , 0x118008095ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16361" , 0x118008095ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16362" , 0x118008095ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16363" , 0x118008095ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16364" , 0x118008095ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16365" , 0x118008095ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16366" , 0x118008095ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16367" , 0x118008095ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16368" , 0x118008095ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16369" , 0x118008095ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16370" , 0x118008095ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16371" , 0x118008095ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16372" , 0x118008095ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16373" , 0x118008095ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16374" , 0x118008095ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16375" , 0x118008095ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16376" , 0x118008095ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16377" , 0x118008095ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16378" , 0x118008095ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16379" , 0x118008095ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16380" , 0x118008095ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16381" , 0x118008095ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16382" , 0x118008095fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_COP0_MAP16383" , 0x118008095fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_CTL" , 0x1180080800000ull, CVMX_CSR_DB_TYPE_RSL, 64, 606},
- {"L2C_DUT_MAP0" , 0x1180080e00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1" , 0x1180080e00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2" , 0x1180080e00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3" , 0x1180080e00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4" , 0x1180080e00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5" , 0x1180080e00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6" , 0x1180080e00030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7" , 0x1180080e00038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8" , 0x1180080e00040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP9" , 0x1180080e00048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP10" , 0x1180080e00050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP11" , 0x1180080e00058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP12" , 0x1180080e00060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP13" , 0x1180080e00068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP14" , 0x1180080e00070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP15" , 0x1180080e00078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP16" , 0x1180080e00080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP17" , 0x1180080e00088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP18" , 0x1180080e00090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP19" , 0x1180080e00098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP20" , 0x1180080e000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP21" , 0x1180080e000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP22" , 0x1180080e000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP23" , 0x1180080e000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP24" , 0x1180080e000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP25" , 0x1180080e000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP26" , 0x1180080e000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP27" , 0x1180080e000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP28" , 0x1180080e000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP29" , 0x1180080e000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP30" , 0x1180080e000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP31" , 0x1180080e000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP32" , 0x1180080e00100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP33" , 0x1180080e00108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP34" , 0x1180080e00110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP35" , 0x1180080e00118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP36" , 0x1180080e00120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP37" , 0x1180080e00128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP38" , 0x1180080e00130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP39" , 0x1180080e00138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP40" , 0x1180080e00140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP41" , 0x1180080e00148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP42" , 0x1180080e00150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP43" , 0x1180080e00158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP44" , 0x1180080e00160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP45" , 0x1180080e00168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP46" , 0x1180080e00170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP47" , 0x1180080e00178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP48" , 0x1180080e00180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP49" , 0x1180080e00188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP50" , 0x1180080e00190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP51" , 0x1180080e00198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP52" , 0x1180080e001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP53" , 0x1180080e001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP54" , 0x1180080e001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP55" , 0x1180080e001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP56" , 0x1180080e001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP57" , 0x1180080e001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP58" , 0x1180080e001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP59" , 0x1180080e001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP60" , 0x1180080e001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP61" , 0x1180080e001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP62" , 0x1180080e001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP63" , 0x1180080e001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP64" , 0x1180080e00200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP65" , 0x1180080e00208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP66" , 0x1180080e00210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP67" , 0x1180080e00218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP68" , 0x1180080e00220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP69" , 0x1180080e00228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP70" , 0x1180080e00230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP71" , 0x1180080e00238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP72" , 0x1180080e00240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP73" , 0x1180080e00248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP74" , 0x1180080e00250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP75" , 0x1180080e00258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP76" , 0x1180080e00260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP77" , 0x1180080e00268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP78" , 0x1180080e00270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP79" , 0x1180080e00278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP80" , 0x1180080e00280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP81" , 0x1180080e00288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP82" , 0x1180080e00290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP83" , 0x1180080e00298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP84" , 0x1180080e002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP85" , 0x1180080e002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP86" , 0x1180080e002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP87" , 0x1180080e002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP88" , 0x1180080e002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP89" , 0x1180080e002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP90" , 0x1180080e002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP91" , 0x1180080e002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP92" , 0x1180080e002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP93" , 0x1180080e002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP94" , 0x1180080e002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP95" , 0x1180080e002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP96" , 0x1180080e00300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP97" , 0x1180080e00308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP98" , 0x1180080e00310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP99" , 0x1180080e00318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP100" , 0x1180080e00320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP101" , 0x1180080e00328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP102" , 0x1180080e00330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP103" , 0x1180080e00338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP104" , 0x1180080e00340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP105" , 0x1180080e00348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP106" , 0x1180080e00350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP107" , 0x1180080e00358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP108" , 0x1180080e00360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP109" , 0x1180080e00368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP110" , 0x1180080e00370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP111" , 0x1180080e00378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP112" , 0x1180080e00380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP113" , 0x1180080e00388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP114" , 0x1180080e00390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP115" , 0x1180080e00398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP116" , 0x1180080e003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP117" , 0x1180080e003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP118" , 0x1180080e003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP119" , 0x1180080e003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP120" , 0x1180080e003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP121" , 0x1180080e003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP122" , 0x1180080e003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP123" , 0x1180080e003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP124" , 0x1180080e003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP125" , 0x1180080e003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP126" , 0x1180080e003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP127" , 0x1180080e003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP128" , 0x1180080e00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP129" , 0x1180080e00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP130" , 0x1180080e00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP131" , 0x1180080e00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP132" , 0x1180080e00420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP133" , 0x1180080e00428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP134" , 0x1180080e00430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP135" , 0x1180080e00438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP136" , 0x1180080e00440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP137" , 0x1180080e00448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP138" , 0x1180080e00450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP139" , 0x1180080e00458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP140" , 0x1180080e00460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP141" , 0x1180080e00468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP142" , 0x1180080e00470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP143" , 0x1180080e00478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP144" , 0x1180080e00480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP145" , 0x1180080e00488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP146" , 0x1180080e00490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP147" , 0x1180080e00498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP148" , 0x1180080e004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP149" , 0x1180080e004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP150" , 0x1180080e004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP151" , 0x1180080e004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP152" , 0x1180080e004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP153" , 0x1180080e004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP154" , 0x1180080e004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP155" , 0x1180080e004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP156" , 0x1180080e004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP157" , 0x1180080e004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP158" , 0x1180080e004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP159" , 0x1180080e004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP160" , 0x1180080e00500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP161" , 0x1180080e00508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP162" , 0x1180080e00510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP163" , 0x1180080e00518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP164" , 0x1180080e00520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP165" , 0x1180080e00528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP166" , 0x1180080e00530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP167" , 0x1180080e00538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP168" , 0x1180080e00540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP169" , 0x1180080e00548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP170" , 0x1180080e00550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP171" , 0x1180080e00558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP172" , 0x1180080e00560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP173" , 0x1180080e00568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP174" , 0x1180080e00570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP175" , 0x1180080e00578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP176" , 0x1180080e00580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP177" , 0x1180080e00588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP178" , 0x1180080e00590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP179" , 0x1180080e00598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP180" , 0x1180080e005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP181" , 0x1180080e005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP182" , 0x1180080e005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP183" , 0x1180080e005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP184" , 0x1180080e005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP185" , 0x1180080e005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP186" , 0x1180080e005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP187" , 0x1180080e005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP188" , 0x1180080e005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP189" , 0x1180080e005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP190" , 0x1180080e005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP191" , 0x1180080e005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP192" , 0x1180080e00600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP193" , 0x1180080e00608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP194" , 0x1180080e00610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP195" , 0x1180080e00618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP196" , 0x1180080e00620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP197" , 0x1180080e00628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP198" , 0x1180080e00630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP199" , 0x1180080e00638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP200" , 0x1180080e00640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP201" , 0x1180080e00648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP202" , 0x1180080e00650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP203" , 0x1180080e00658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP204" , 0x1180080e00660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP205" , 0x1180080e00668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP206" , 0x1180080e00670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP207" , 0x1180080e00678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP208" , 0x1180080e00680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP209" , 0x1180080e00688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP210" , 0x1180080e00690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP211" , 0x1180080e00698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP212" , 0x1180080e006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP213" , 0x1180080e006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP214" , 0x1180080e006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP215" , 0x1180080e006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP216" , 0x1180080e006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP217" , 0x1180080e006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP218" , 0x1180080e006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP219" , 0x1180080e006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP220" , 0x1180080e006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP221" , 0x1180080e006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP222" , 0x1180080e006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP223" , 0x1180080e006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP224" , 0x1180080e00700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP225" , 0x1180080e00708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP226" , 0x1180080e00710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP227" , 0x1180080e00718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP228" , 0x1180080e00720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP229" , 0x1180080e00728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP230" , 0x1180080e00730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP231" , 0x1180080e00738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP232" , 0x1180080e00740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP233" , 0x1180080e00748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP234" , 0x1180080e00750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP235" , 0x1180080e00758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP236" , 0x1180080e00760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP237" , 0x1180080e00768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP238" , 0x1180080e00770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP239" , 0x1180080e00778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP240" , 0x1180080e00780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP241" , 0x1180080e00788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP242" , 0x1180080e00790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP243" , 0x1180080e00798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP244" , 0x1180080e007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP245" , 0x1180080e007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP246" , 0x1180080e007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP247" , 0x1180080e007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP248" , 0x1180080e007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP249" , 0x1180080e007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP250" , 0x1180080e007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP251" , 0x1180080e007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP252" , 0x1180080e007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP253" , 0x1180080e007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP254" , 0x1180080e007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP255" , 0x1180080e007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP256" , 0x1180080e00800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP257" , 0x1180080e00808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP258" , 0x1180080e00810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP259" , 0x1180080e00818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP260" , 0x1180080e00820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP261" , 0x1180080e00828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP262" , 0x1180080e00830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP263" , 0x1180080e00838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP264" , 0x1180080e00840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP265" , 0x1180080e00848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP266" , 0x1180080e00850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP267" , 0x1180080e00858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP268" , 0x1180080e00860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP269" , 0x1180080e00868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP270" , 0x1180080e00870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP271" , 0x1180080e00878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP272" , 0x1180080e00880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP273" , 0x1180080e00888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP274" , 0x1180080e00890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP275" , 0x1180080e00898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP276" , 0x1180080e008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP277" , 0x1180080e008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP278" , 0x1180080e008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP279" , 0x1180080e008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP280" , 0x1180080e008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP281" , 0x1180080e008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP282" , 0x1180080e008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP283" , 0x1180080e008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP284" , 0x1180080e008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP285" , 0x1180080e008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP286" , 0x1180080e008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP287" , 0x1180080e008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP288" , 0x1180080e00900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP289" , 0x1180080e00908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP290" , 0x1180080e00910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP291" , 0x1180080e00918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP292" , 0x1180080e00920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP293" , 0x1180080e00928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP294" , 0x1180080e00930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP295" , 0x1180080e00938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP296" , 0x1180080e00940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP297" , 0x1180080e00948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP298" , 0x1180080e00950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP299" , 0x1180080e00958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP300" , 0x1180080e00960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP301" , 0x1180080e00968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP302" , 0x1180080e00970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP303" , 0x1180080e00978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP304" , 0x1180080e00980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP305" , 0x1180080e00988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP306" , 0x1180080e00990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP307" , 0x1180080e00998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP308" , 0x1180080e009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP309" , 0x1180080e009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP310" , 0x1180080e009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP311" , 0x1180080e009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP312" , 0x1180080e009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP313" , 0x1180080e009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP314" , 0x1180080e009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP315" , 0x1180080e009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP316" , 0x1180080e009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP317" , 0x1180080e009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP318" , 0x1180080e009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP319" , 0x1180080e009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP320" , 0x1180080e00a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP321" , 0x1180080e00a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP322" , 0x1180080e00a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP323" , 0x1180080e00a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP324" , 0x1180080e00a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP325" , 0x1180080e00a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP326" , 0x1180080e00a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP327" , 0x1180080e00a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP328" , 0x1180080e00a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP329" , 0x1180080e00a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP330" , 0x1180080e00a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP331" , 0x1180080e00a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP332" , 0x1180080e00a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP333" , 0x1180080e00a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP334" , 0x1180080e00a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP335" , 0x1180080e00a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP336" , 0x1180080e00a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP337" , 0x1180080e00a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP338" , 0x1180080e00a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP339" , 0x1180080e00a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP340" , 0x1180080e00aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP341" , 0x1180080e00aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP342" , 0x1180080e00ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP343" , 0x1180080e00ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP344" , 0x1180080e00ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP345" , 0x1180080e00ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP346" , 0x1180080e00ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP347" , 0x1180080e00ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP348" , 0x1180080e00ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP349" , 0x1180080e00ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP350" , 0x1180080e00af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP351" , 0x1180080e00af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP352" , 0x1180080e00b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP353" , 0x1180080e00b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP354" , 0x1180080e00b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP355" , 0x1180080e00b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP356" , 0x1180080e00b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP357" , 0x1180080e00b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP358" , 0x1180080e00b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP359" , 0x1180080e00b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP360" , 0x1180080e00b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP361" , 0x1180080e00b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP362" , 0x1180080e00b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP363" , 0x1180080e00b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP364" , 0x1180080e00b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP365" , 0x1180080e00b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP366" , 0x1180080e00b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP367" , 0x1180080e00b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP368" , 0x1180080e00b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP369" , 0x1180080e00b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP370" , 0x1180080e00b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP371" , 0x1180080e00b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP372" , 0x1180080e00ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP373" , 0x1180080e00ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP374" , 0x1180080e00bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP375" , 0x1180080e00bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP376" , 0x1180080e00bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP377" , 0x1180080e00bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP378" , 0x1180080e00bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP379" , 0x1180080e00bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP380" , 0x1180080e00be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP381" , 0x1180080e00be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP382" , 0x1180080e00bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP383" , 0x1180080e00bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP384" , 0x1180080e00c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP385" , 0x1180080e00c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP386" , 0x1180080e00c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP387" , 0x1180080e00c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP388" , 0x1180080e00c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP389" , 0x1180080e00c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP390" , 0x1180080e00c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP391" , 0x1180080e00c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP392" , 0x1180080e00c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP393" , 0x1180080e00c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP394" , 0x1180080e00c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP395" , 0x1180080e00c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP396" , 0x1180080e00c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP397" , 0x1180080e00c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP398" , 0x1180080e00c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP399" , 0x1180080e00c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP400" , 0x1180080e00c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP401" , 0x1180080e00c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP402" , 0x1180080e00c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP403" , 0x1180080e00c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP404" , 0x1180080e00ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP405" , 0x1180080e00ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP406" , 0x1180080e00cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP407" , 0x1180080e00cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP408" , 0x1180080e00cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP409" , 0x1180080e00cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP410" , 0x1180080e00cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP411" , 0x1180080e00cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP412" , 0x1180080e00ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP413" , 0x1180080e00ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP414" , 0x1180080e00cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP415" , 0x1180080e00cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP416" , 0x1180080e00d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP417" , 0x1180080e00d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP418" , 0x1180080e00d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP419" , 0x1180080e00d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP420" , 0x1180080e00d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP421" , 0x1180080e00d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP422" , 0x1180080e00d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP423" , 0x1180080e00d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP424" , 0x1180080e00d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP425" , 0x1180080e00d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP426" , 0x1180080e00d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP427" , 0x1180080e00d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP428" , 0x1180080e00d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP429" , 0x1180080e00d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP430" , 0x1180080e00d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP431" , 0x1180080e00d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP432" , 0x1180080e00d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP433" , 0x1180080e00d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP434" , 0x1180080e00d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP435" , 0x1180080e00d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP436" , 0x1180080e00da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP437" , 0x1180080e00da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP438" , 0x1180080e00db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP439" , 0x1180080e00db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP440" , 0x1180080e00dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP441" , 0x1180080e00dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP442" , 0x1180080e00dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP443" , 0x1180080e00dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP444" , 0x1180080e00de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP445" , 0x1180080e00de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP446" , 0x1180080e00df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP447" , 0x1180080e00df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP448" , 0x1180080e00e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP449" , 0x1180080e00e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP450" , 0x1180080e00e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP451" , 0x1180080e00e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP452" , 0x1180080e00e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP453" , 0x1180080e00e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP454" , 0x1180080e00e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP455" , 0x1180080e00e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP456" , 0x1180080e00e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP457" , 0x1180080e00e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP458" , 0x1180080e00e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP459" , 0x1180080e00e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP460" , 0x1180080e00e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP461" , 0x1180080e00e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP462" , 0x1180080e00e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP463" , 0x1180080e00e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP464" , 0x1180080e00e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP465" , 0x1180080e00e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP466" , 0x1180080e00e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP467" , 0x1180080e00e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP468" , 0x1180080e00ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP469" , 0x1180080e00ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP470" , 0x1180080e00eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP471" , 0x1180080e00eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP472" , 0x1180080e00ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP473" , 0x1180080e00ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP474" , 0x1180080e00ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP475" , 0x1180080e00ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP476" , 0x1180080e00ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP477" , 0x1180080e00ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP478" , 0x1180080e00ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP479" , 0x1180080e00ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP480" , 0x1180080e00f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP481" , 0x1180080e00f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP482" , 0x1180080e00f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP483" , 0x1180080e00f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP484" , 0x1180080e00f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP485" , 0x1180080e00f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP486" , 0x1180080e00f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP487" , 0x1180080e00f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP488" , 0x1180080e00f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP489" , 0x1180080e00f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP490" , 0x1180080e00f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP491" , 0x1180080e00f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP492" , 0x1180080e00f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP493" , 0x1180080e00f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP494" , 0x1180080e00f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP495" , 0x1180080e00f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP496" , 0x1180080e00f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP497" , 0x1180080e00f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP498" , 0x1180080e00f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP499" , 0x1180080e00f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP500" , 0x1180080e00fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP501" , 0x1180080e00fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP502" , 0x1180080e00fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP503" , 0x1180080e00fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP504" , 0x1180080e00fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP505" , 0x1180080e00fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP506" , 0x1180080e00fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP507" , 0x1180080e00fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP508" , 0x1180080e00fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP509" , 0x1180080e00fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP510" , 0x1180080e00ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP511" , 0x1180080e00ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP512" , 0x1180080e01000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP513" , 0x1180080e01008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP514" , 0x1180080e01010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP515" , 0x1180080e01018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP516" , 0x1180080e01020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP517" , 0x1180080e01028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP518" , 0x1180080e01030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP519" , 0x1180080e01038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP520" , 0x1180080e01040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP521" , 0x1180080e01048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP522" , 0x1180080e01050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP523" , 0x1180080e01058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP524" , 0x1180080e01060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP525" , 0x1180080e01068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP526" , 0x1180080e01070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP527" , 0x1180080e01078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP528" , 0x1180080e01080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP529" , 0x1180080e01088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP530" , 0x1180080e01090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP531" , 0x1180080e01098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP532" , 0x1180080e010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP533" , 0x1180080e010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP534" , 0x1180080e010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP535" , 0x1180080e010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP536" , 0x1180080e010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP537" , 0x1180080e010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP538" , 0x1180080e010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP539" , 0x1180080e010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP540" , 0x1180080e010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP541" , 0x1180080e010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP542" , 0x1180080e010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP543" , 0x1180080e010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP544" , 0x1180080e01100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP545" , 0x1180080e01108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP546" , 0x1180080e01110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP547" , 0x1180080e01118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP548" , 0x1180080e01120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP549" , 0x1180080e01128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP550" , 0x1180080e01130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP551" , 0x1180080e01138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP552" , 0x1180080e01140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP553" , 0x1180080e01148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP554" , 0x1180080e01150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP555" , 0x1180080e01158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP556" , 0x1180080e01160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP557" , 0x1180080e01168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP558" , 0x1180080e01170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP559" , 0x1180080e01178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP560" , 0x1180080e01180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP561" , 0x1180080e01188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP562" , 0x1180080e01190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP563" , 0x1180080e01198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP564" , 0x1180080e011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP565" , 0x1180080e011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP566" , 0x1180080e011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP567" , 0x1180080e011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP568" , 0x1180080e011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP569" , 0x1180080e011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP570" , 0x1180080e011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP571" , 0x1180080e011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP572" , 0x1180080e011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP573" , 0x1180080e011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP574" , 0x1180080e011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP575" , 0x1180080e011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP576" , 0x1180080e01200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP577" , 0x1180080e01208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP578" , 0x1180080e01210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP579" , 0x1180080e01218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP580" , 0x1180080e01220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP581" , 0x1180080e01228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP582" , 0x1180080e01230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP583" , 0x1180080e01238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP584" , 0x1180080e01240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP585" , 0x1180080e01248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP586" , 0x1180080e01250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP587" , 0x1180080e01258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP588" , 0x1180080e01260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP589" , 0x1180080e01268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP590" , 0x1180080e01270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP591" , 0x1180080e01278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP592" , 0x1180080e01280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP593" , 0x1180080e01288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP594" , 0x1180080e01290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP595" , 0x1180080e01298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP596" , 0x1180080e012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP597" , 0x1180080e012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP598" , 0x1180080e012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP599" , 0x1180080e012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP600" , 0x1180080e012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP601" , 0x1180080e012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP602" , 0x1180080e012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP603" , 0x1180080e012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP604" , 0x1180080e012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP605" , 0x1180080e012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP606" , 0x1180080e012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP607" , 0x1180080e012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP608" , 0x1180080e01300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP609" , 0x1180080e01308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP610" , 0x1180080e01310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP611" , 0x1180080e01318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP612" , 0x1180080e01320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP613" , 0x1180080e01328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP614" , 0x1180080e01330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP615" , 0x1180080e01338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP616" , 0x1180080e01340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP617" , 0x1180080e01348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP618" , 0x1180080e01350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP619" , 0x1180080e01358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP620" , 0x1180080e01360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP621" , 0x1180080e01368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP622" , 0x1180080e01370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP623" , 0x1180080e01378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP624" , 0x1180080e01380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP625" , 0x1180080e01388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP626" , 0x1180080e01390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP627" , 0x1180080e01398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP628" , 0x1180080e013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP629" , 0x1180080e013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP630" , 0x1180080e013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP631" , 0x1180080e013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP632" , 0x1180080e013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP633" , 0x1180080e013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP634" , 0x1180080e013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP635" , 0x1180080e013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP636" , 0x1180080e013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP637" , 0x1180080e013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP638" , 0x1180080e013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP639" , 0x1180080e013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP640" , 0x1180080e01400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP641" , 0x1180080e01408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP642" , 0x1180080e01410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP643" , 0x1180080e01418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP644" , 0x1180080e01420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP645" , 0x1180080e01428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP646" , 0x1180080e01430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP647" , 0x1180080e01438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP648" , 0x1180080e01440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP649" , 0x1180080e01448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP650" , 0x1180080e01450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP651" , 0x1180080e01458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP652" , 0x1180080e01460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP653" , 0x1180080e01468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP654" , 0x1180080e01470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP655" , 0x1180080e01478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP656" , 0x1180080e01480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP657" , 0x1180080e01488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP658" , 0x1180080e01490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP659" , 0x1180080e01498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP660" , 0x1180080e014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP661" , 0x1180080e014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP662" , 0x1180080e014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP663" , 0x1180080e014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP664" , 0x1180080e014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP665" , 0x1180080e014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP666" , 0x1180080e014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP667" , 0x1180080e014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP668" , 0x1180080e014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP669" , 0x1180080e014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP670" , 0x1180080e014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP671" , 0x1180080e014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP672" , 0x1180080e01500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP673" , 0x1180080e01508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP674" , 0x1180080e01510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP675" , 0x1180080e01518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP676" , 0x1180080e01520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP677" , 0x1180080e01528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP678" , 0x1180080e01530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP679" , 0x1180080e01538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP680" , 0x1180080e01540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP681" , 0x1180080e01548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP682" , 0x1180080e01550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP683" , 0x1180080e01558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP684" , 0x1180080e01560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP685" , 0x1180080e01568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP686" , 0x1180080e01570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP687" , 0x1180080e01578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP688" , 0x1180080e01580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP689" , 0x1180080e01588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP690" , 0x1180080e01590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP691" , 0x1180080e01598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP692" , 0x1180080e015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP693" , 0x1180080e015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP694" , 0x1180080e015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP695" , 0x1180080e015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP696" , 0x1180080e015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP697" , 0x1180080e015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP698" , 0x1180080e015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP699" , 0x1180080e015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP700" , 0x1180080e015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP701" , 0x1180080e015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP702" , 0x1180080e015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP703" , 0x1180080e015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP704" , 0x1180080e01600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP705" , 0x1180080e01608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP706" , 0x1180080e01610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP707" , 0x1180080e01618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP708" , 0x1180080e01620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP709" , 0x1180080e01628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP710" , 0x1180080e01630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP711" , 0x1180080e01638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP712" , 0x1180080e01640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP713" , 0x1180080e01648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP714" , 0x1180080e01650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP715" , 0x1180080e01658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP716" , 0x1180080e01660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP717" , 0x1180080e01668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP718" , 0x1180080e01670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP719" , 0x1180080e01678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP720" , 0x1180080e01680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP721" , 0x1180080e01688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP722" , 0x1180080e01690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP723" , 0x1180080e01698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP724" , 0x1180080e016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP725" , 0x1180080e016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP726" , 0x1180080e016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP727" , 0x1180080e016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP728" , 0x1180080e016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP729" , 0x1180080e016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP730" , 0x1180080e016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP731" , 0x1180080e016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP732" , 0x1180080e016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP733" , 0x1180080e016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP734" , 0x1180080e016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP735" , 0x1180080e016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP736" , 0x1180080e01700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP737" , 0x1180080e01708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP738" , 0x1180080e01710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP739" , 0x1180080e01718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP740" , 0x1180080e01720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP741" , 0x1180080e01728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP742" , 0x1180080e01730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP743" , 0x1180080e01738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP744" , 0x1180080e01740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP745" , 0x1180080e01748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP746" , 0x1180080e01750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP747" , 0x1180080e01758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP748" , 0x1180080e01760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP749" , 0x1180080e01768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP750" , 0x1180080e01770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP751" , 0x1180080e01778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP752" , 0x1180080e01780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP753" , 0x1180080e01788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP754" , 0x1180080e01790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP755" , 0x1180080e01798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP756" , 0x1180080e017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP757" , 0x1180080e017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP758" , 0x1180080e017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP759" , 0x1180080e017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP760" , 0x1180080e017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP761" , 0x1180080e017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP762" , 0x1180080e017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP763" , 0x1180080e017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP764" , 0x1180080e017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP765" , 0x1180080e017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP766" , 0x1180080e017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP767" , 0x1180080e017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP768" , 0x1180080e01800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP769" , 0x1180080e01808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP770" , 0x1180080e01810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP771" , 0x1180080e01818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP772" , 0x1180080e01820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP773" , 0x1180080e01828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP774" , 0x1180080e01830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP775" , 0x1180080e01838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP776" , 0x1180080e01840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP777" , 0x1180080e01848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP778" , 0x1180080e01850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP779" , 0x1180080e01858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP780" , 0x1180080e01860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP781" , 0x1180080e01868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP782" , 0x1180080e01870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP783" , 0x1180080e01878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP784" , 0x1180080e01880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP785" , 0x1180080e01888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP786" , 0x1180080e01890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP787" , 0x1180080e01898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP788" , 0x1180080e018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP789" , 0x1180080e018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP790" , 0x1180080e018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP791" , 0x1180080e018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP792" , 0x1180080e018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP793" , 0x1180080e018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP794" , 0x1180080e018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP795" , 0x1180080e018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP796" , 0x1180080e018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP797" , 0x1180080e018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP798" , 0x1180080e018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP799" , 0x1180080e018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP800" , 0x1180080e01900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP801" , 0x1180080e01908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP802" , 0x1180080e01910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP803" , 0x1180080e01918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP804" , 0x1180080e01920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP805" , 0x1180080e01928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP806" , 0x1180080e01930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP807" , 0x1180080e01938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP808" , 0x1180080e01940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP809" , 0x1180080e01948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP810" , 0x1180080e01950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP811" , 0x1180080e01958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP812" , 0x1180080e01960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP813" , 0x1180080e01968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP814" , 0x1180080e01970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP815" , 0x1180080e01978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP816" , 0x1180080e01980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP817" , 0x1180080e01988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP818" , 0x1180080e01990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP819" , 0x1180080e01998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP820" , 0x1180080e019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP821" , 0x1180080e019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP822" , 0x1180080e019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP823" , 0x1180080e019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP824" , 0x1180080e019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP825" , 0x1180080e019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP826" , 0x1180080e019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP827" , 0x1180080e019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP828" , 0x1180080e019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP829" , 0x1180080e019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP830" , 0x1180080e019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP831" , 0x1180080e019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP832" , 0x1180080e01a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP833" , 0x1180080e01a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP834" , 0x1180080e01a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP835" , 0x1180080e01a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP836" , 0x1180080e01a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP837" , 0x1180080e01a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP838" , 0x1180080e01a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP839" , 0x1180080e01a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP840" , 0x1180080e01a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP841" , 0x1180080e01a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP842" , 0x1180080e01a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP843" , 0x1180080e01a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP844" , 0x1180080e01a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP845" , 0x1180080e01a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP846" , 0x1180080e01a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP847" , 0x1180080e01a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP848" , 0x1180080e01a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP849" , 0x1180080e01a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP850" , 0x1180080e01a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP851" , 0x1180080e01a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP852" , 0x1180080e01aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP853" , 0x1180080e01aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP854" , 0x1180080e01ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP855" , 0x1180080e01ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP856" , 0x1180080e01ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP857" , 0x1180080e01ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP858" , 0x1180080e01ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP859" , 0x1180080e01ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP860" , 0x1180080e01ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP861" , 0x1180080e01ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP862" , 0x1180080e01af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP863" , 0x1180080e01af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP864" , 0x1180080e01b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP865" , 0x1180080e01b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP866" , 0x1180080e01b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP867" , 0x1180080e01b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP868" , 0x1180080e01b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP869" , 0x1180080e01b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP870" , 0x1180080e01b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP871" , 0x1180080e01b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP872" , 0x1180080e01b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP873" , 0x1180080e01b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP874" , 0x1180080e01b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP875" , 0x1180080e01b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP876" , 0x1180080e01b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP877" , 0x1180080e01b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP878" , 0x1180080e01b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP879" , 0x1180080e01b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP880" , 0x1180080e01b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP881" , 0x1180080e01b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP882" , 0x1180080e01b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP883" , 0x1180080e01b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP884" , 0x1180080e01ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP885" , 0x1180080e01ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP886" , 0x1180080e01bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP887" , 0x1180080e01bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP888" , 0x1180080e01bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP889" , 0x1180080e01bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP890" , 0x1180080e01bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP891" , 0x1180080e01bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP892" , 0x1180080e01be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP893" , 0x1180080e01be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP894" , 0x1180080e01bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP895" , 0x1180080e01bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP896" , 0x1180080e01c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP897" , 0x1180080e01c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP898" , 0x1180080e01c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP899" , 0x1180080e01c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP900" , 0x1180080e01c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP901" , 0x1180080e01c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP902" , 0x1180080e01c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP903" , 0x1180080e01c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP904" , 0x1180080e01c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP905" , 0x1180080e01c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP906" , 0x1180080e01c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP907" , 0x1180080e01c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP908" , 0x1180080e01c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP909" , 0x1180080e01c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP910" , 0x1180080e01c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP911" , 0x1180080e01c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP912" , 0x1180080e01c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP913" , 0x1180080e01c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP914" , 0x1180080e01c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP915" , 0x1180080e01c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP916" , 0x1180080e01ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP917" , 0x1180080e01ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP918" , 0x1180080e01cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP919" , 0x1180080e01cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP920" , 0x1180080e01cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP921" , 0x1180080e01cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP922" , 0x1180080e01cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP923" , 0x1180080e01cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP924" , 0x1180080e01ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP925" , 0x1180080e01ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP926" , 0x1180080e01cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP927" , 0x1180080e01cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP928" , 0x1180080e01d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP929" , 0x1180080e01d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP930" , 0x1180080e01d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP931" , 0x1180080e01d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP932" , 0x1180080e01d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP933" , 0x1180080e01d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP934" , 0x1180080e01d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP935" , 0x1180080e01d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP936" , 0x1180080e01d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP937" , 0x1180080e01d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP938" , 0x1180080e01d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP939" , 0x1180080e01d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP940" , 0x1180080e01d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP941" , 0x1180080e01d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP942" , 0x1180080e01d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP943" , 0x1180080e01d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP944" , 0x1180080e01d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP945" , 0x1180080e01d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP946" , 0x1180080e01d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP947" , 0x1180080e01d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP948" , 0x1180080e01da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP949" , 0x1180080e01da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP950" , 0x1180080e01db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP951" , 0x1180080e01db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP952" , 0x1180080e01dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP953" , 0x1180080e01dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP954" , 0x1180080e01dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP955" , 0x1180080e01dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP956" , 0x1180080e01de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP957" , 0x1180080e01de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP958" , 0x1180080e01df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP959" , 0x1180080e01df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP960" , 0x1180080e01e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP961" , 0x1180080e01e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP962" , 0x1180080e01e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP963" , 0x1180080e01e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP964" , 0x1180080e01e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP965" , 0x1180080e01e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP966" , 0x1180080e01e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP967" , 0x1180080e01e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP968" , 0x1180080e01e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP969" , 0x1180080e01e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP970" , 0x1180080e01e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP971" , 0x1180080e01e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP972" , 0x1180080e01e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP973" , 0x1180080e01e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP974" , 0x1180080e01e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP975" , 0x1180080e01e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP976" , 0x1180080e01e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP977" , 0x1180080e01e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP978" , 0x1180080e01e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP979" , 0x1180080e01e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP980" , 0x1180080e01ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP981" , 0x1180080e01ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP982" , 0x1180080e01eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP983" , 0x1180080e01eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP984" , 0x1180080e01ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP985" , 0x1180080e01ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP986" , 0x1180080e01ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP987" , 0x1180080e01ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP988" , 0x1180080e01ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP989" , 0x1180080e01ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP990" , 0x1180080e01ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP991" , 0x1180080e01ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP992" , 0x1180080e01f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP993" , 0x1180080e01f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP994" , 0x1180080e01f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP995" , 0x1180080e01f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP996" , 0x1180080e01f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP997" , 0x1180080e01f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP998" , 0x1180080e01f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP999" , 0x1180080e01f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1000" , 0x1180080e01f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1001" , 0x1180080e01f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1002" , 0x1180080e01f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1003" , 0x1180080e01f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1004" , 0x1180080e01f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1005" , 0x1180080e01f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1006" , 0x1180080e01f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1007" , 0x1180080e01f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1008" , 0x1180080e01f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1009" , 0x1180080e01f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1010" , 0x1180080e01f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1011" , 0x1180080e01f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1012" , 0x1180080e01fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1013" , 0x1180080e01fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1014" , 0x1180080e01fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1015" , 0x1180080e01fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1016" , 0x1180080e01fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1017" , 0x1180080e01fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1018" , 0x1180080e01fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1019" , 0x1180080e01fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1020" , 0x1180080e01fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1021" , 0x1180080e01fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1022" , 0x1180080e01ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1023" , 0x1180080e01ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1024" , 0x1180080e02000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1025" , 0x1180080e02008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1026" , 0x1180080e02010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1027" , 0x1180080e02018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1028" , 0x1180080e02020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1029" , 0x1180080e02028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1030" , 0x1180080e02030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1031" , 0x1180080e02038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1032" , 0x1180080e02040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1033" , 0x1180080e02048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1034" , 0x1180080e02050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1035" , 0x1180080e02058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1036" , 0x1180080e02060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1037" , 0x1180080e02068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1038" , 0x1180080e02070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1039" , 0x1180080e02078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1040" , 0x1180080e02080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1041" , 0x1180080e02088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1042" , 0x1180080e02090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1043" , 0x1180080e02098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1044" , 0x1180080e020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1045" , 0x1180080e020a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1046" , 0x1180080e020b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1047" , 0x1180080e020b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1048" , 0x1180080e020c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1049" , 0x1180080e020c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1050" , 0x1180080e020d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1051" , 0x1180080e020d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1052" , 0x1180080e020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1053" , 0x1180080e020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1054" , 0x1180080e020f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1055" , 0x1180080e020f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1056" , 0x1180080e02100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1057" , 0x1180080e02108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1058" , 0x1180080e02110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1059" , 0x1180080e02118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1060" , 0x1180080e02120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1061" , 0x1180080e02128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1062" , 0x1180080e02130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1063" , 0x1180080e02138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1064" , 0x1180080e02140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1065" , 0x1180080e02148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1066" , 0x1180080e02150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1067" , 0x1180080e02158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1068" , 0x1180080e02160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1069" , 0x1180080e02168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1070" , 0x1180080e02170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1071" , 0x1180080e02178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1072" , 0x1180080e02180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1073" , 0x1180080e02188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1074" , 0x1180080e02190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1075" , 0x1180080e02198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1076" , 0x1180080e021a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1077" , 0x1180080e021a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1078" , 0x1180080e021b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1079" , 0x1180080e021b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1080" , 0x1180080e021c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1081" , 0x1180080e021c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1082" , 0x1180080e021d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1083" , 0x1180080e021d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1084" , 0x1180080e021e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1085" , 0x1180080e021e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1086" , 0x1180080e021f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1087" , 0x1180080e021f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1088" , 0x1180080e02200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1089" , 0x1180080e02208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1090" , 0x1180080e02210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1091" , 0x1180080e02218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1092" , 0x1180080e02220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1093" , 0x1180080e02228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1094" , 0x1180080e02230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1095" , 0x1180080e02238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1096" , 0x1180080e02240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1097" , 0x1180080e02248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1098" , 0x1180080e02250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1099" , 0x1180080e02258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1100" , 0x1180080e02260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1101" , 0x1180080e02268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1102" , 0x1180080e02270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1103" , 0x1180080e02278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1104" , 0x1180080e02280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1105" , 0x1180080e02288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1106" , 0x1180080e02290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1107" , 0x1180080e02298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1108" , 0x1180080e022a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1109" , 0x1180080e022a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1110" , 0x1180080e022b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1111" , 0x1180080e022b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1112" , 0x1180080e022c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1113" , 0x1180080e022c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1114" , 0x1180080e022d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1115" , 0x1180080e022d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1116" , 0x1180080e022e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1117" , 0x1180080e022e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1118" , 0x1180080e022f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1119" , 0x1180080e022f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1120" , 0x1180080e02300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1121" , 0x1180080e02308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1122" , 0x1180080e02310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1123" , 0x1180080e02318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1124" , 0x1180080e02320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1125" , 0x1180080e02328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1126" , 0x1180080e02330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1127" , 0x1180080e02338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1128" , 0x1180080e02340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1129" , 0x1180080e02348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1130" , 0x1180080e02350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1131" , 0x1180080e02358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1132" , 0x1180080e02360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1133" , 0x1180080e02368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1134" , 0x1180080e02370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1135" , 0x1180080e02378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1136" , 0x1180080e02380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1137" , 0x1180080e02388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1138" , 0x1180080e02390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1139" , 0x1180080e02398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1140" , 0x1180080e023a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1141" , 0x1180080e023a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1142" , 0x1180080e023b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1143" , 0x1180080e023b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1144" , 0x1180080e023c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1145" , 0x1180080e023c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1146" , 0x1180080e023d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1147" , 0x1180080e023d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1148" , 0x1180080e023e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1149" , 0x1180080e023e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1150" , 0x1180080e023f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1151" , 0x1180080e023f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1152" , 0x1180080e02400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1153" , 0x1180080e02408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1154" , 0x1180080e02410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1155" , 0x1180080e02418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1156" , 0x1180080e02420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1157" , 0x1180080e02428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1158" , 0x1180080e02430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1159" , 0x1180080e02438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1160" , 0x1180080e02440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1161" , 0x1180080e02448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1162" , 0x1180080e02450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1163" , 0x1180080e02458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1164" , 0x1180080e02460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1165" , 0x1180080e02468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1166" , 0x1180080e02470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1167" , 0x1180080e02478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1168" , 0x1180080e02480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1169" , 0x1180080e02488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1170" , 0x1180080e02490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1171" , 0x1180080e02498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1172" , 0x1180080e024a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1173" , 0x1180080e024a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1174" , 0x1180080e024b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1175" , 0x1180080e024b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1176" , 0x1180080e024c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1177" , 0x1180080e024c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1178" , 0x1180080e024d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1179" , 0x1180080e024d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1180" , 0x1180080e024e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1181" , 0x1180080e024e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1182" , 0x1180080e024f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1183" , 0x1180080e024f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1184" , 0x1180080e02500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1185" , 0x1180080e02508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1186" , 0x1180080e02510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1187" , 0x1180080e02518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1188" , 0x1180080e02520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1189" , 0x1180080e02528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1190" , 0x1180080e02530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1191" , 0x1180080e02538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1192" , 0x1180080e02540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1193" , 0x1180080e02548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1194" , 0x1180080e02550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1195" , 0x1180080e02558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1196" , 0x1180080e02560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1197" , 0x1180080e02568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1198" , 0x1180080e02570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1199" , 0x1180080e02578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1200" , 0x1180080e02580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1201" , 0x1180080e02588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1202" , 0x1180080e02590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1203" , 0x1180080e02598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1204" , 0x1180080e025a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1205" , 0x1180080e025a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1206" , 0x1180080e025b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1207" , 0x1180080e025b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1208" , 0x1180080e025c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1209" , 0x1180080e025c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1210" , 0x1180080e025d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1211" , 0x1180080e025d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1212" , 0x1180080e025e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1213" , 0x1180080e025e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1214" , 0x1180080e025f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1215" , 0x1180080e025f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1216" , 0x1180080e02600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1217" , 0x1180080e02608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1218" , 0x1180080e02610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1219" , 0x1180080e02618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1220" , 0x1180080e02620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1221" , 0x1180080e02628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1222" , 0x1180080e02630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1223" , 0x1180080e02638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1224" , 0x1180080e02640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1225" , 0x1180080e02648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1226" , 0x1180080e02650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1227" , 0x1180080e02658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1228" , 0x1180080e02660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1229" , 0x1180080e02668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1230" , 0x1180080e02670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1231" , 0x1180080e02678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1232" , 0x1180080e02680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1233" , 0x1180080e02688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1234" , 0x1180080e02690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1235" , 0x1180080e02698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1236" , 0x1180080e026a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1237" , 0x1180080e026a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1238" , 0x1180080e026b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1239" , 0x1180080e026b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1240" , 0x1180080e026c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1241" , 0x1180080e026c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1242" , 0x1180080e026d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1243" , 0x1180080e026d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1244" , 0x1180080e026e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1245" , 0x1180080e026e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1246" , 0x1180080e026f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1247" , 0x1180080e026f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1248" , 0x1180080e02700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1249" , 0x1180080e02708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1250" , 0x1180080e02710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1251" , 0x1180080e02718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1252" , 0x1180080e02720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1253" , 0x1180080e02728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1254" , 0x1180080e02730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1255" , 0x1180080e02738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1256" , 0x1180080e02740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1257" , 0x1180080e02748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1258" , 0x1180080e02750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1259" , 0x1180080e02758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1260" , 0x1180080e02760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1261" , 0x1180080e02768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1262" , 0x1180080e02770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1263" , 0x1180080e02778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1264" , 0x1180080e02780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1265" , 0x1180080e02788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1266" , 0x1180080e02790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1267" , 0x1180080e02798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1268" , 0x1180080e027a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1269" , 0x1180080e027a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1270" , 0x1180080e027b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1271" , 0x1180080e027b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1272" , 0x1180080e027c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1273" , 0x1180080e027c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1274" , 0x1180080e027d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1275" , 0x1180080e027d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1276" , 0x1180080e027e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1277" , 0x1180080e027e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1278" , 0x1180080e027f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1279" , 0x1180080e027f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1280" , 0x1180080e02800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1281" , 0x1180080e02808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1282" , 0x1180080e02810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1283" , 0x1180080e02818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1284" , 0x1180080e02820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1285" , 0x1180080e02828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1286" , 0x1180080e02830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1287" , 0x1180080e02838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1288" , 0x1180080e02840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1289" , 0x1180080e02848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1290" , 0x1180080e02850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1291" , 0x1180080e02858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1292" , 0x1180080e02860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1293" , 0x1180080e02868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1294" , 0x1180080e02870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1295" , 0x1180080e02878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1296" , 0x1180080e02880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1297" , 0x1180080e02888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1298" , 0x1180080e02890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1299" , 0x1180080e02898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1300" , 0x1180080e028a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1301" , 0x1180080e028a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1302" , 0x1180080e028b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1303" , 0x1180080e028b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1304" , 0x1180080e028c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1305" , 0x1180080e028c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1306" , 0x1180080e028d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1307" , 0x1180080e028d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1308" , 0x1180080e028e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1309" , 0x1180080e028e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1310" , 0x1180080e028f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1311" , 0x1180080e028f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1312" , 0x1180080e02900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1313" , 0x1180080e02908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1314" , 0x1180080e02910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1315" , 0x1180080e02918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1316" , 0x1180080e02920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1317" , 0x1180080e02928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1318" , 0x1180080e02930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1319" , 0x1180080e02938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1320" , 0x1180080e02940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1321" , 0x1180080e02948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1322" , 0x1180080e02950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1323" , 0x1180080e02958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1324" , 0x1180080e02960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1325" , 0x1180080e02968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1326" , 0x1180080e02970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1327" , 0x1180080e02978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1328" , 0x1180080e02980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1329" , 0x1180080e02988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1330" , 0x1180080e02990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1331" , 0x1180080e02998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1332" , 0x1180080e029a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1333" , 0x1180080e029a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1334" , 0x1180080e029b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1335" , 0x1180080e029b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1336" , 0x1180080e029c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1337" , 0x1180080e029c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1338" , 0x1180080e029d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1339" , 0x1180080e029d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1340" , 0x1180080e029e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1341" , 0x1180080e029e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1342" , 0x1180080e029f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1343" , 0x1180080e029f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1344" , 0x1180080e02a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1345" , 0x1180080e02a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1346" , 0x1180080e02a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1347" , 0x1180080e02a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1348" , 0x1180080e02a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1349" , 0x1180080e02a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1350" , 0x1180080e02a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1351" , 0x1180080e02a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1352" , 0x1180080e02a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1353" , 0x1180080e02a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1354" , 0x1180080e02a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1355" , 0x1180080e02a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1356" , 0x1180080e02a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1357" , 0x1180080e02a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1358" , 0x1180080e02a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1359" , 0x1180080e02a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1360" , 0x1180080e02a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1361" , 0x1180080e02a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1362" , 0x1180080e02a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1363" , 0x1180080e02a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1364" , 0x1180080e02aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1365" , 0x1180080e02aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1366" , 0x1180080e02ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1367" , 0x1180080e02ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1368" , 0x1180080e02ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1369" , 0x1180080e02ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1370" , 0x1180080e02ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1371" , 0x1180080e02ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1372" , 0x1180080e02ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1373" , 0x1180080e02ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1374" , 0x1180080e02af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1375" , 0x1180080e02af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1376" , 0x1180080e02b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1377" , 0x1180080e02b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1378" , 0x1180080e02b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1379" , 0x1180080e02b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1380" , 0x1180080e02b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1381" , 0x1180080e02b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1382" , 0x1180080e02b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1383" , 0x1180080e02b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1384" , 0x1180080e02b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1385" , 0x1180080e02b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1386" , 0x1180080e02b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1387" , 0x1180080e02b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1388" , 0x1180080e02b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1389" , 0x1180080e02b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1390" , 0x1180080e02b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1391" , 0x1180080e02b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1392" , 0x1180080e02b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1393" , 0x1180080e02b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1394" , 0x1180080e02b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1395" , 0x1180080e02b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1396" , 0x1180080e02ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1397" , 0x1180080e02ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1398" , 0x1180080e02bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1399" , 0x1180080e02bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1400" , 0x1180080e02bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1401" , 0x1180080e02bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1402" , 0x1180080e02bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1403" , 0x1180080e02bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1404" , 0x1180080e02be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1405" , 0x1180080e02be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1406" , 0x1180080e02bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1407" , 0x1180080e02bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1408" , 0x1180080e02c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1409" , 0x1180080e02c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1410" , 0x1180080e02c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1411" , 0x1180080e02c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1412" , 0x1180080e02c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1413" , 0x1180080e02c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1414" , 0x1180080e02c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1415" , 0x1180080e02c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1416" , 0x1180080e02c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1417" , 0x1180080e02c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1418" , 0x1180080e02c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1419" , 0x1180080e02c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1420" , 0x1180080e02c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1421" , 0x1180080e02c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1422" , 0x1180080e02c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1423" , 0x1180080e02c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1424" , 0x1180080e02c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1425" , 0x1180080e02c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1426" , 0x1180080e02c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1427" , 0x1180080e02c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1428" , 0x1180080e02ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1429" , 0x1180080e02ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1430" , 0x1180080e02cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1431" , 0x1180080e02cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1432" , 0x1180080e02cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1433" , 0x1180080e02cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1434" , 0x1180080e02cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1435" , 0x1180080e02cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1436" , 0x1180080e02ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1437" , 0x1180080e02ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1438" , 0x1180080e02cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1439" , 0x1180080e02cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1440" , 0x1180080e02d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1441" , 0x1180080e02d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1442" , 0x1180080e02d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1443" , 0x1180080e02d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1444" , 0x1180080e02d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1445" , 0x1180080e02d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1446" , 0x1180080e02d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1447" , 0x1180080e02d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1448" , 0x1180080e02d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1449" , 0x1180080e02d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1450" , 0x1180080e02d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1451" , 0x1180080e02d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1452" , 0x1180080e02d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1453" , 0x1180080e02d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1454" , 0x1180080e02d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1455" , 0x1180080e02d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1456" , 0x1180080e02d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1457" , 0x1180080e02d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1458" , 0x1180080e02d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1459" , 0x1180080e02d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1460" , 0x1180080e02da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1461" , 0x1180080e02da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1462" , 0x1180080e02db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1463" , 0x1180080e02db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1464" , 0x1180080e02dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1465" , 0x1180080e02dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1466" , 0x1180080e02dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1467" , 0x1180080e02dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1468" , 0x1180080e02de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1469" , 0x1180080e02de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1470" , 0x1180080e02df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1471" , 0x1180080e02df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1472" , 0x1180080e02e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1473" , 0x1180080e02e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1474" , 0x1180080e02e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1475" , 0x1180080e02e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1476" , 0x1180080e02e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1477" , 0x1180080e02e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1478" , 0x1180080e02e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1479" , 0x1180080e02e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1480" , 0x1180080e02e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1481" , 0x1180080e02e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1482" , 0x1180080e02e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1483" , 0x1180080e02e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1484" , 0x1180080e02e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1485" , 0x1180080e02e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1486" , 0x1180080e02e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1487" , 0x1180080e02e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1488" , 0x1180080e02e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1489" , 0x1180080e02e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1490" , 0x1180080e02e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1491" , 0x1180080e02e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1492" , 0x1180080e02ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1493" , 0x1180080e02ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1494" , 0x1180080e02eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1495" , 0x1180080e02eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1496" , 0x1180080e02ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1497" , 0x1180080e02ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1498" , 0x1180080e02ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1499" , 0x1180080e02ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1500" , 0x1180080e02ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1501" , 0x1180080e02ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1502" , 0x1180080e02ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1503" , 0x1180080e02ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1504" , 0x1180080e02f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1505" , 0x1180080e02f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1506" , 0x1180080e02f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1507" , 0x1180080e02f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1508" , 0x1180080e02f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1509" , 0x1180080e02f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1510" , 0x1180080e02f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1511" , 0x1180080e02f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1512" , 0x1180080e02f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1513" , 0x1180080e02f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1514" , 0x1180080e02f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1515" , 0x1180080e02f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1516" , 0x1180080e02f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1517" , 0x1180080e02f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1518" , 0x1180080e02f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1519" , 0x1180080e02f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1520" , 0x1180080e02f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1521" , 0x1180080e02f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1522" , 0x1180080e02f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1523" , 0x1180080e02f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1524" , 0x1180080e02fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1525" , 0x1180080e02fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1526" , 0x1180080e02fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1527" , 0x1180080e02fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1528" , 0x1180080e02fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1529" , 0x1180080e02fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1530" , 0x1180080e02fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1531" , 0x1180080e02fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1532" , 0x1180080e02fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1533" , 0x1180080e02fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1534" , 0x1180080e02ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1535" , 0x1180080e02ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1536" , 0x1180080e03000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1537" , 0x1180080e03008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1538" , 0x1180080e03010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1539" , 0x1180080e03018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1540" , 0x1180080e03020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1541" , 0x1180080e03028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1542" , 0x1180080e03030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1543" , 0x1180080e03038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1544" , 0x1180080e03040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1545" , 0x1180080e03048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1546" , 0x1180080e03050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1547" , 0x1180080e03058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1548" , 0x1180080e03060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1549" , 0x1180080e03068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1550" , 0x1180080e03070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1551" , 0x1180080e03078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1552" , 0x1180080e03080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1553" , 0x1180080e03088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1554" , 0x1180080e03090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1555" , 0x1180080e03098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1556" , 0x1180080e030a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1557" , 0x1180080e030a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1558" , 0x1180080e030b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1559" , 0x1180080e030b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1560" , 0x1180080e030c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1561" , 0x1180080e030c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1562" , 0x1180080e030d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1563" , 0x1180080e030d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1564" , 0x1180080e030e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1565" , 0x1180080e030e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1566" , 0x1180080e030f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1567" , 0x1180080e030f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1568" , 0x1180080e03100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1569" , 0x1180080e03108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1570" , 0x1180080e03110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1571" , 0x1180080e03118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1572" , 0x1180080e03120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1573" , 0x1180080e03128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1574" , 0x1180080e03130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1575" , 0x1180080e03138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1576" , 0x1180080e03140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1577" , 0x1180080e03148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1578" , 0x1180080e03150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1579" , 0x1180080e03158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1580" , 0x1180080e03160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1581" , 0x1180080e03168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1582" , 0x1180080e03170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1583" , 0x1180080e03178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1584" , 0x1180080e03180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1585" , 0x1180080e03188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1586" , 0x1180080e03190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1587" , 0x1180080e03198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1588" , 0x1180080e031a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1589" , 0x1180080e031a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1590" , 0x1180080e031b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1591" , 0x1180080e031b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1592" , 0x1180080e031c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1593" , 0x1180080e031c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1594" , 0x1180080e031d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1595" , 0x1180080e031d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1596" , 0x1180080e031e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1597" , 0x1180080e031e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1598" , 0x1180080e031f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1599" , 0x1180080e031f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1600" , 0x1180080e03200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1601" , 0x1180080e03208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1602" , 0x1180080e03210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1603" , 0x1180080e03218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1604" , 0x1180080e03220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1605" , 0x1180080e03228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1606" , 0x1180080e03230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1607" , 0x1180080e03238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1608" , 0x1180080e03240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1609" , 0x1180080e03248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1610" , 0x1180080e03250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1611" , 0x1180080e03258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1612" , 0x1180080e03260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1613" , 0x1180080e03268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1614" , 0x1180080e03270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1615" , 0x1180080e03278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1616" , 0x1180080e03280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1617" , 0x1180080e03288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1618" , 0x1180080e03290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1619" , 0x1180080e03298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1620" , 0x1180080e032a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1621" , 0x1180080e032a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1622" , 0x1180080e032b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1623" , 0x1180080e032b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1624" , 0x1180080e032c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1625" , 0x1180080e032c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1626" , 0x1180080e032d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1627" , 0x1180080e032d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1628" , 0x1180080e032e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1629" , 0x1180080e032e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1630" , 0x1180080e032f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1631" , 0x1180080e032f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1632" , 0x1180080e03300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1633" , 0x1180080e03308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1634" , 0x1180080e03310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1635" , 0x1180080e03318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1636" , 0x1180080e03320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1637" , 0x1180080e03328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1638" , 0x1180080e03330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1639" , 0x1180080e03338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1640" , 0x1180080e03340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1641" , 0x1180080e03348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1642" , 0x1180080e03350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1643" , 0x1180080e03358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1644" , 0x1180080e03360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1645" , 0x1180080e03368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1646" , 0x1180080e03370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1647" , 0x1180080e03378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1648" , 0x1180080e03380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1649" , 0x1180080e03388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1650" , 0x1180080e03390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1651" , 0x1180080e03398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1652" , 0x1180080e033a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1653" , 0x1180080e033a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1654" , 0x1180080e033b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1655" , 0x1180080e033b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1656" , 0x1180080e033c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1657" , 0x1180080e033c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1658" , 0x1180080e033d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1659" , 0x1180080e033d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1660" , 0x1180080e033e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1661" , 0x1180080e033e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1662" , 0x1180080e033f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1663" , 0x1180080e033f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1664" , 0x1180080e03400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1665" , 0x1180080e03408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1666" , 0x1180080e03410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1667" , 0x1180080e03418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1668" , 0x1180080e03420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1669" , 0x1180080e03428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1670" , 0x1180080e03430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1671" , 0x1180080e03438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1672" , 0x1180080e03440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1673" , 0x1180080e03448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1674" , 0x1180080e03450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1675" , 0x1180080e03458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1676" , 0x1180080e03460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1677" , 0x1180080e03468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1678" , 0x1180080e03470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1679" , 0x1180080e03478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1680" , 0x1180080e03480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1681" , 0x1180080e03488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1682" , 0x1180080e03490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1683" , 0x1180080e03498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1684" , 0x1180080e034a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1685" , 0x1180080e034a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1686" , 0x1180080e034b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1687" , 0x1180080e034b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1688" , 0x1180080e034c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1689" , 0x1180080e034c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1690" , 0x1180080e034d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1691" , 0x1180080e034d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1692" , 0x1180080e034e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1693" , 0x1180080e034e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1694" , 0x1180080e034f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1695" , 0x1180080e034f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1696" , 0x1180080e03500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1697" , 0x1180080e03508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1698" , 0x1180080e03510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1699" , 0x1180080e03518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1700" , 0x1180080e03520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1701" , 0x1180080e03528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1702" , 0x1180080e03530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1703" , 0x1180080e03538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1704" , 0x1180080e03540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1705" , 0x1180080e03548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1706" , 0x1180080e03550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1707" , 0x1180080e03558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1708" , 0x1180080e03560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1709" , 0x1180080e03568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1710" , 0x1180080e03570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1711" , 0x1180080e03578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1712" , 0x1180080e03580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1713" , 0x1180080e03588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1714" , 0x1180080e03590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1715" , 0x1180080e03598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1716" , 0x1180080e035a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1717" , 0x1180080e035a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1718" , 0x1180080e035b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1719" , 0x1180080e035b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1720" , 0x1180080e035c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1721" , 0x1180080e035c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1722" , 0x1180080e035d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1723" , 0x1180080e035d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1724" , 0x1180080e035e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1725" , 0x1180080e035e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1726" , 0x1180080e035f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1727" , 0x1180080e035f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1728" , 0x1180080e03600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1729" , 0x1180080e03608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1730" , 0x1180080e03610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1731" , 0x1180080e03618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1732" , 0x1180080e03620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1733" , 0x1180080e03628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1734" , 0x1180080e03630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1735" , 0x1180080e03638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1736" , 0x1180080e03640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1737" , 0x1180080e03648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1738" , 0x1180080e03650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1739" , 0x1180080e03658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1740" , 0x1180080e03660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1741" , 0x1180080e03668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1742" , 0x1180080e03670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1743" , 0x1180080e03678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1744" , 0x1180080e03680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1745" , 0x1180080e03688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1746" , 0x1180080e03690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1747" , 0x1180080e03698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1748" , 0x1180080e036a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1749" , 0x1180080e036a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1750" , 0x1180080e036b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1751" , 0x1180080e036b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1752" , 0x1180080e036c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1753" , 0x1180080e036c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1754" , 0x1180080e036d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1755" , 0x1180080e036d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1756" , 0x1180080e036e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1757" , 0x1180080e036e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1758" , 0x1180080e036f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1759" , 0x1180080e036f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1760" , 0x1180080e03700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1761" , 0x1180080e03708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1762" , 0x1180080e03710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1763" , 0x1180080e03718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1764" , 0x1180080e03720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1765" , 0x1180080e03728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1766" , 0x1180080e03730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1767" , 0x1180080e03738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1768" , 0x1180080e03740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1769" , 0x1180080e03748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1770" , 0x1180080e03750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1771" , 0x1180080e03758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1772" , 0x1180080e03760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1773" , 0x1180080e03768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1774" , 0x1180080e03770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1775" , 0x1180080e03778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1776" , 0x1180080e03780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1777" , 0x1180080e03788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1778" , 0x1180080e03790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1779" , 0x1180080e03798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1780" , 0x1180080e037a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1781" , 0x1180080e037a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1782" , 0x1180080e037b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1783" , 0x1180080e037b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1784" , 0x1180080e037c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1785" , 0x1180080e037c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1786" , 0x1180080e037d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1787" , 0x1180080e037d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1788" , 0x1180080e037e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1789" , 0x1180080e037e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1790" , 0x1180080e037f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1791" , 0x1180080e037f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1792" , 0x1180080e03800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1793" , 0x1180080e03808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1794" , 0x1180080e03810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1795" , 0x1180080e03818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1796" , 0x1180080e03820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1797" , 0x1180080e03828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1798" , 0x1180080e03830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1799" , 0x1180080e03838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1800" , 0x1180080e03840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1801" , 0x1180080e03848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1802" , 0x1180080e03850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1803" , 0x1180080e03858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1804" , 0x1180080e03860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1805" , 0x1180080e03868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1806" , 0x1180080e03870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1807" , 0x1180080e03878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1808" , 0x1180080e03880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1809" , 0x1180080e03888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1810" , 0x1180080e03890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1811" , 0x1180080e03898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1812" , 0x1180080e038a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1813" , 0x1180080e038a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1814" , 0x1180080e038b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1815" , 0x1180080e038b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1816" , 0x1180080e038c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1817" , 0x1180080e038c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1818" , 0x1180080e038d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1819" , 0x1180080e038d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1820" , 0x1180080e038e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1821" , 0x1180080e038e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1822" , 0x1180080e038f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1823" , 0x1180080e038f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1824" , 0x1180080e03900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1825" , 0x1180080e03908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1826" , 0x1180080e03910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1827" , 0x1180080e03918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1828" , 0x1180080e03920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1829" , 0x1180080e03928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1830" , 0x1180080e03930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1831" , 0x1180080e03938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1832" , 0x1180080e03940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1833" , 0x1180080e03948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1834" , 0x1180080e03950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1835" , 0x1180080e03958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1836" , 0x1180080e03960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1837" , 0x1180080e03968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1838" , 0x1180080e03970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1839" , 0x1180080e03978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1840" , 0x1180080e03980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1841" , 0x1180080e03988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1842" , 0x1180080e03990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1843" , 0x1180080e03998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1844" , 0x1180080e039a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1845" , 0x1180080e039a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1846" , 0x1180080e039b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1847" , 0x1180080e039b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1848" , 0x1180080e039c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1849" , 0x1180080e039c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1850" , 0x1180080e039d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1851" , 0x1180080e039d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1852" , 0x1180080e039e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1853" , 0x1180080e039e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1854" , 0x1180080e039f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1855" , 0x1180080e039f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1856" , 0x1180080e03a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1857" , 0x1180080e03a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1858" , 0x1180080e03a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1859" , 0x1180080e03a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1860" , 0x1180080e03a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1861" , 0x1180080e03a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1862" , 0x1180080e03a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1863" , 0x1180080e03a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1864" , 0x1180080e03a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1865" , 0x1180080e03a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1866" , 0x1180080e03a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1867" , 0x1180080e03a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1868" , 0x1180080e03a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1869" , 0x1180080e03a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1870" , 0x1180080e03a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1871" , 0x1180080e03a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1872" , 0x1180080e03a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1873" , 0x1180080e03a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1874" , 0x1180080e03a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1875" , 0x1180080e03a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1876" , 0x1180080e03aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1877" , 0x1180080e03aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1878" , 0x1180080e03ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1879" , 0x1180080e03ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1880" , 0x1180080e03ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1881" , 0x1180080e03ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1882" , 0x1180080e03ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1883" , 0x1180080e03ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1884" , 0x1180080e03ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1885" , 0x1180080e03ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1886" , 0x1180080e03af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1887" , 0x1180080e03af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1888" , 0x1180080e03b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1889" , 0x1180080e03b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1890" , 0x1180080e03b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1891" , 0x1180080e03b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1892" , 0x1180080e03b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1893" , 0x1180080e03b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1894" , 0x1180080e03b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1895" , 0x1180080e03b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1896" , 0x1180080e03b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1897" , 0x1180080e03b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1898" , 0x1180080e03b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1899" , 0x1180080e03b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1900" , 0x1180080e03b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1901" , 0x1180080e03b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1902" , 0x1180080e03b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1903" , 0x1180080e03b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1904" , 0x1180080e03b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1905" , 0x1180080e03b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1906" , 0x1180080e03b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1907" , 0x1180080e03b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1908" , 0x1180080e03ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1909" , 0x1180080e03ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1910" , 0x1180080e03bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1911" , 0x1180080e03bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1912" , 0x1180080e03bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1913" , 0x1180080e03bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1914" , 0x1180080e03bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1915" , 0x1180080e03bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1916" , 0x1180080e03be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1917" , 0x1180080e03be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1918" , 0x1180080e03bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1919" , 0x1180080e03bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1920" , 0x1180080e03c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1921" , 0x1180080e03c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1922" , 0x1180080e03c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1923" , 0x1180080e03c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1924" , 0x1180080e03c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1925" , 0x1180080e03c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1926" , 0x1180080e03c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1927" , 0x1180080e03c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1928" , 0x1180080e03c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1929" , 0x1180080e03c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1930" , 0x1180080e03c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1931" , 0x1180080e03c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1932" , 0x1180080e03c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1933" , 0x1180080e03c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1934" , 0x1180080e03c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1935" , 0x1180080e03c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1936" , 0x1180080e03c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1937" , 0x1180080e03c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1938" , 0x1180080e03c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1939" , 0x1180080e03c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1940" , 0x1180080e03ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1941" , 0x1180080e03ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1942" , 0x1180080e03cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1943" , 0x1180080e03cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1944" , 0x1180080e03cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1945" , 0x1180080e03cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1946" , 0x1180080e03cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1947" , 0x1180080e03cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1948" , 0x1180080e03ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1949" , 0x1180080e03ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1950" , 0x1180080e03cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1951" , 0x1180080e03cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1952" , 0x1180080e03d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1953" , 0x1180080e03d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1954" , 0x1180080e03d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1955" , 0x1180080e03d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1956" , 0x1180080e03d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1957" , 0x1180080e03d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1958" , 0x1180080e03d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1959" , 0x1180080e03d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1960" , 0x1180080e03d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1961" , 0x1180080e03d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1962" , 0x1180080e03d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1963" , 0x1180080e03d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1964" , 0x1180080e03d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1965" , 0x1180080e03d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1966" , 0x1180080e03d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1967" , 0x1180080e03d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1968" , 0x1180080e03d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1969" , 0x1180080e03d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1970" , 0x1180080e03d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1971" , 0x1180080e03d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1972" , 0x1180080e03da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1973" , 0x1180080e03da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1974" , 0x1180080e03db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1975" , 0x1180080e03db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1976" , 0x1180080e03dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1977" , 0x1180080e03dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1978" , 0x1180080e03dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1979" , 0x1180080e03dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1980" , 0x1180080e03de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1981" , 0x1180080e03de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1982" , 0x1180080e03df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1983" , 0x1180080e03df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1984" , 0x1180080e03e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1985" , 0x1180080e03e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1986" , 0x1180080e03e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1987" , 0x1180080e03e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1988" , 0x1180080e03e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1989" , 0x1180080e03e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1990" , 0x1180080e03e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1991" , 0x1180080e03e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1992" , 0x1180080e03e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1993" , 0x1180080e03e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1994" , 0x1180080e03e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1995" , 0x1180080e03e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1996" , 0x1180080e03e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1997" , 0x1180080e03e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1998" , 0x1180080e03e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP1999" , 0x1180080e03e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2000" , 0x1180080e03e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2001" , 0x1180080e03e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2002" , 0x1180080e03e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2003" , 0x1180080e03e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2004" , 0x1180080e03ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2005" , 0x1180080e03ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2006" , 0x1180080e03eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2007" , 0x1180080e03eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2008" , 0x1180080e03ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2009" , 0x1180080e03ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2010" , 0x1180080e03ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2011" , 0x1180080e03ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2012" , 0x1180080e03ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2013" , 0x1180080e03ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2014" , 0x1180080e03ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2015" , 0x1180080e03ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2016" , 0x1180080e03f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2017" , 0x1180080e03f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2018" , 0x1180080e03f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2019" , 0x1180080e03f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2020" , 0x1180080e03f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2021" , 0x1180080e03f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2022" , 0x1180080e03f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2023" , 0x1180080e03f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2024" , 0x1180080e03f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2025" , 0x1180080e03f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2026" , 0x1180080e03f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2027" , 0x1180080e03f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2028" , 0x1180080e03f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2029" , 0x1180080e03f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2030" , 0x1180080e03f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2031" , 0x1180080e03f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2032" , 0x1180080e03f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2033" , 0x1180080e03f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2034" , 0x1180080e03f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2035" , 0x1180080e03f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2036" , 0x1180080e03fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2037" , 0x1180080e03fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2038" , 0x1180080e03fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2039" , 0x1180080e03fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2040" , 0x1180080e03fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2041" , 0x1180080e03fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2042" , 0x1180080e03fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2043" , 0x1180080e03fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2044" , 0x1180080e03fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2045" , 0x1180080e03fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2046" , 0x1180080e03ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2047" , 0x1180080e03ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2048" , 0x1180080e04000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2049" , 0x1180080e04008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2050" , 0x1180080e04010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2051" , 0x1180080e04018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2052" , 0x1180080e04020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2053" , 0x1180080e04028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2054" , 0x1180080e04030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2055" , 0x1180080e04038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2056" , 0x1180080e04040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2057" , 0x1180080e04048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2058" , 0x1180080e04050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2059" , 0x1180080e04058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2060" , 0x1180080e04060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2061" , 0x1180080e04068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2062" , 0x1180080e04070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2063" , 0x1180080e04078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2064" , 0x1180080e04080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2065" , 0x1180080e04088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2066" , 0x1180080e04090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2067" , 0x1180080e04098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2068" , 0x1180080e040a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2069" , 0x1180080e040a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2070" , 0x1180080e040b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2071" , 0x1180080e040b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2072" , 0x1180080e040c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2073" , 0x1180080e040c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2074" , 0x1180080e040d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2075" , 0x1180080e040d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2076" , 0x1180080e040e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2077" , 0x1180080e040e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2078" , 0x1180080e040f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2079" , 0x1180080e040f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2080" , 0x1180080e04100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2081" , 0x1180080e04108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2082" , 0x1180080e04110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2083" , 0x1180080e04118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2084" , 0x1180080e04120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2085" , 0x1180080e04128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2086" , 0x1180080e04130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2087" , 0x1180080e04138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2088" , 0x1180080e04140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2089" , 0x1180080e04148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2090" , 0x1180080e04150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2091" , 0x1180080e04158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2092" , 0x1180080e04160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2093" , 0x1180080e04168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2094" , 0x1180080e04170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2095" , 0x1180080e04178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2096" , 0x1180080e04180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2097" , 0x1180080e04188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2098" , 0x1180080e04190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2099" , 0x1180080e04198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2100" , 0x1180080e041a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2101" , 0x1180080e041a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2102" , 0x1180080e041b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2103" , 0x1180080e041b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2104" , 0x1180080e041c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2105" , 0x1180080e041c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2106" , 0x1180080e041d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2107" , 0x1180080e041d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2108" , 0x1180080e041e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2109" , 0x1180080e041e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2110" , 0x1180080e041f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2111" , 0x1180080e041f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2112" , 0x1180080e04200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2113" , 0x1180080e04208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2114" , 0x1180080e04210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2115" , 0x1180080e04218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2116" , 0x1180080e04220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2117" , 0x1180080e04228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2118" , 0x1180080e04230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2119" , 0x1180080e04238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2120" , 0x1180080e04240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2121" , 0x1180080e04248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2122" , 0x1180080e04250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2123" , 0x1180080e04258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2124" , 0x1180080e04260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2125" , 0x1180080e04268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2126" , 0x1180080e04270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2127" , 0x1180080e04278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2128" , 0x1180080e04280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2129" , 0x1180080e04288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2130" , 0x1180080e04290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2131" , 0x1180080e04298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2132" , 0x1180080e042a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2133" , 0x1180080e042a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2134" , 0x1180080e042b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2135" , 0x1180080e042b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2136" , 0x1180080e042c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2137" , 0x1180080e042c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2138" , 0x1180080e042d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2139" , 0x1180080e042d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2140" , 0x1180080e042e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2141" , 0x1180080e042e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2142" , 0x1180080e042f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2143" , 0x1180080e042f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2144" , 0x1180080e04300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2145" , 0x1180080e04308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2146" , 0x1180080e04310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2147" , 0x1180080e04318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2148" , 0x1180080e04320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2149" , 0x1180080e04328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2150" , 0x1180080e04330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2151" , 0x1180080e04338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2152" , 0x1180080e04340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2153" , 0x1180080e04348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2154" , 0x1180080e04350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2155" , 0x1180080e04358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2156" , 0x1180080e04360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2157" , 0x1180080e04368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2158" , 0x1180080e04370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2159" , 0x1180080e04378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2160" , 0x1180080e04380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2161" , 0x1180080e04388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2162" , 0x1180080e04390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2163" , 0x1180080e04398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2164" , 0x1180080e043a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2165" , 0x1180080e043a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2166" , 0x1180080e043b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2167" , 0x1180080e043b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2168" , 0x1180080e043c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2169" , 0x1180080e043c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2170" , 0x1180080e043d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2171" , 0x1180080e043d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2172" , 0x1180080e043e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2173" , 0x1180080e043e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2174" , 0x1180080e043f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2175" , 0x1180080e043f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2176" , 0x1180080e04400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2177" , 0x1180080e04408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2178" , 0x1180080e04410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2179" , 0x1180080e04418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2180" , 0x1180080e04420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2181" , 0x1180080e04428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2182" , 0x1180080e04430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2183" , 0x1180080e04438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2184" , 0x1180080e04440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2185" , 0x1180080e04448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2186" , 0x1180080e04450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2187" , 0x1180080e04458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2188" , 0x1180080e04460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2189" , 0x1180080e04468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2190" , 0x1180080e04470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2191" , 0x1180080e04478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2192" , 0x1180080e04480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2193" , 0x1180080e04488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2194" , 0x1180080e04490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2195" , 0x1180080e04498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2196" , 0x1180080e044a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2197" , 0x1180080e044a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2198" , 0x1180080e044b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2199" , 0x1180080e044b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2200" , 0x1180080e044c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2201" , 0x1180080e044c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2202" , 0x1180080e044d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2203" , 0x1180080e044d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2204" , 0x1180080e044e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2205" , 0x1180080e044e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2206" , 0x1180080e044f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2207" , 0x1180080e044f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2208" , 0x1180080e04500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2209" , 0x1180080e04508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2210" , 0x1180080e04510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2211" , 0x1180080e04518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2212" , 0x1180080e04520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2213" , 0x1180080e04528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2214" , 0x1180080e04530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2215" , 0x1180080e04538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2216" , 0x1180080e04540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2217" , 0x1180080e04548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2218" , 0x1180080e04550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2219" , 0x1180080e04558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2220" , 0x1180080e04560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2221" , 0x1180080e04568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2222" , 0x1180080e04570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2223" , 0x1180080e04578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2224" , 0x1180080e04580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2225" , 0x1180080e04588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2226" , 0x1180080e04590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2227" , 0x1180080e04598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2228" , 0x1180080e045a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2229" , 0x1180080e045a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2230" , 0x1180080e045b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2231" , 0x1180080e045b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2232" , 0x1180080e045c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2233" , 0x1180080e045c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2234" , 0x1180080e045d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2235" , 0x1180080e045d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2236" , 0x1180080e045e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2237" , 0x1180080e045e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2238" , 0x1180080e045f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2239" , 0x1180080e045f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2240" , 0x1180080e04600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2241" , 0x1180080e04608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2242" , 0x1180080e04610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2243" , 0x1180080e04618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2244" , 0x1180080e04620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2245" , 0x1180080e04628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2246" , 0x1180080e04630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2247" , 0x1180080e04638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2248" , 0x1180080e04640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2249" , 0x1180080e04648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2250" , 0x1180080e04650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2251" , 0x1180080e04658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2252" , 0x1180080e04660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2253" , 0x1180080e04668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2254" , 0x1180080e04670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2255" , 0x1180080e04678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2256" , 0x1180080e04680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2257" , 0x1180080e04688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2258" , 0x1180080e04690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2259" , 0x1180080e04698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2260" , 0x1180080e046a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2261" , 0x1180080e046a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2262" , 0x1180080e046b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2263" , 0x1180080e046b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2264" , 0x1180080e046c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2265" , 0x1180080e046c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2266" , 0x1180080e046d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2267" , 0x1180080e046d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2268" , 0x1180080e046e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2269" , 0x1180080e046e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2270" , 0x1180080e046f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2271" , 0x1180080e046f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2272" , 0x1180080e04700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2273" , 0x1180080e04708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2274" , 0x1180080e04710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2275" , 0x1180080e04718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2276" , 0x1180080e04720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2277" , 0x1180080e04728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2278" , 0x1180080e04730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2279" , 0x1180080e04738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2280" , 0x1180080e04740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2281" , 0x1180080e04748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2282" , 0x1180080e04750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2283" , 0x1180080e04758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2284" , 0x1180080e04760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2285" , 0x1180080e04768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2286" , 0x1180080e04770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2287" , 0x1180080e04778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2288" , 0x1180080e04780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2289" , 0x1180080e04788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2290" , 0x1180080e04790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2291" , 0x1180080e04798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2292" , 0x1180080e047a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2293" , 0x1180080e047a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2294" , 0x1180080e047b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2295" , 0x1180080e047b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2296" , 0x1180080e047c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2297" , 0x1180080e047c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2298" , 0x1180080e047d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2299" , 0x1180080e047d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2300" , 0x1180080e047e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2301" , 0x1180080e047e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2302" , 0x1180080e047f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2303" , 0x1180080e047f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2304" , 0x1180080e04800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2305" , 0x1180080e04808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2306" , 0x1180080e04810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2307" , 0x1180080e04818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2308" , 0x1180080e04820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2309" , 0x1180080e04828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2310" , 0x1180080e04830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2311" , 0x1180080e04838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2312" , 0x1180080e04840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2313" , 0x1180080e04848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2314" , 0x1180080e04850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2315" , 0x1180080e04858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2316" , 0x1180080e04860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2317" , 0x1180080e04868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2318" , 0x1180080e04870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2319" , 0x1180080e04878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2320" , 0x1180080e04880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2321" , 0x1180080e04888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2322" , 0x1180080e04890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2323" , 0x1180080e04898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2324" , 0x1180080e048a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2325" , 0x1180080e048a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2326" , 0x1180080e048b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2327" , 0x1180080e048b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2328" , 0x1180080e048c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2329" , 0x1180080e048c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2330" , 0x1180080e048d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2331" , 0x1180080e048d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2332" , 0x1180080e048e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2333" , 0x1180080e048e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2334" , 0x1180080e048f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2335" , 0x1180080e048f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2336" , 0x1180080e04900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2337" , 0x1180080e04908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2338" , 0x1180080e04910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2339" , 0x1180080e04918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2340" , 0x1180080e04920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2341" , 0x1180080e04928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2342" , 0x1180080e04930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2343" , 0x1180080e04938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2344" , 0x1180080e04940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2345" , 0x1180080e04948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2346" , 0x1180080e04950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2347" , 0x1180080e04958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2348" , 0x1180080e04960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2349" , 0x1180080e04968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2350" , 0x1180080e04970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2351" , 0x1180080e04978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2352" , 0x1180080e04980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2353" , 0x1180080e04988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2354" , 0x1180080e04990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2355" , 0x1180080e04998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2356" , 0x1180080e049a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2357" , 0x1180080e049a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2358" , 0x1180080e049b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2359" , 0x1180080e049b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2360" , 0x1180080e049c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2361" , 0x1180080e049c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2362" , 0x1180080e049d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2363" , 0x1180080e049d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2364" , 0x1180080e049e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2365" , 0x1180080e049e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2366" , 0x1180080e049f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2367" , 0x1180080e049f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2368" , 0x1180080e04a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2369" , 0x1180080e04a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2370" , 0x1180080e04a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2371" , 0x1180080e04a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2372" , 0x1180080e04a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2373" , 0x1180080e04a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2374" , 0x1180080e04a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2375" , 0x1180080e04a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2376" , 0x1180080e04a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2377" , 0x1180080e04a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2378" , 0x1180080e04a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2379" , 0x1180080e04a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2380" , 0x1180080e04a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2381" , 0x1180080e04a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2382" , 0x1180080e04a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2383" , 0x1180080e04a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2384" , 0x1180080e04a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2385" , 0x1180080e04a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2386" , 0x1180080e04a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2387" , 0x1180080e04a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2388" , 0x1180080e04aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2389" , 0x1180080e04aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2390" , 0x1180080e04ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2391" , 0x1180080e04ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2392" , 0x1180080e04ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2393" , 0x1180080e04ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2394" , 0x1180080e04ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2395" , 0x1180080e04ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2396" , 0x1180080e04ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2397" , 0x1180080e04ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2398" , 0x1180080e04af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2399" , 0x1180080e04af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2400" , 0x1180080e04b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2401" , 0x1180080e04b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2402" , 0x1180080e04b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2403" , 0x1180080e04b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2404" , 0x1180080e04b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2405" , 0x1180080e04b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2406" , 0x1180080e04b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2407" , 0x1180080e04b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2408" , 0x1180080e04b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2409" , 0x1180080e04b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2410" , 0x1180080e04b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2411" , 0x1180080e04b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2412" , 0x1180080e04b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2413" , 0x1180080e04b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2414" , 0x1180080e04b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2415" , 0x1180080e04b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2416" , 0x1180080e04b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2417" , 0x1180080e04b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2418" , 0x1180080e04b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2419" , 0x1180080e04b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2420" , 0x1180080e04ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2421" , 0x1180080e04ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2422" , 0x1180080e04bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2423" , 0x1180080e04bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2424" , 0x1180080e04bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2425" , 0x1180080e04bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2426" , 0x1180080e04bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2427" , 0x1180080e04bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2428" , 0x1180080e04be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2429" , 0x1180080e04be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2430" , 0x1180080e04bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2431" , 0x1180080e04bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2432" , 0x1180080e04c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2433" , 0x1180080e04c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2434" , 0x1180080e04c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2435" , 0x1180080e04c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2436" , 0x1180080e04c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2437" , 0x1180080e04c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2438" , 0x1180080e04c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2439" , 0x1180080e04c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2440" , 0x1180080e04c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2441" , 0x1180080e04c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2442" , 0x1180080e04c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2443" , 0x1180080e04c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2444" , 0x1180080e04c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2445" , 0x1180080e04c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2446" , 0x1180080e04c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2447" , 0x1180080e04c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2448" , 0x1180080e04c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2449" , 0x1180080e04c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2450" , 0x1180080e04c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2451" , 0x1180080e04c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2452" , 0x1180080e04ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2453" , 0x1180080e04ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2454" , 0x1180080e04cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2455" , 0x1180080e04cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2456" , 0x1180080e04cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2457" , 0x1180080e04cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2458" , 0x1180080e04cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2459" , 0x1180080e04cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2460" , 0x1180080e04ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2461" , 0x1180080e04ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2462" , 0x1180080e04cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2463" , 0x1180080e04cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2464" , 0x1180080e04d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2465" , 0x1180080e04d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2466" , 0x1180080e04d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2467" , 0x1180080e04d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2468" , 0x1180080e04d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2469" , 0x1180080e04d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2470" , 0x1180080e04d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2471" , 0x1180080e04d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2472" , 0x1180080e04d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2473" , 0x1180080e04d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2474" , 0x1180080e04d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2475" , 0x1180080e04d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2476" , 0x1180080e04d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2477" , 0x1180080e04d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2478" , 0x1180080e04d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2479" , 0x1180080e04d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2480" , 0x1180080e04d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2481" , 0x1180080e04d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2482" , 0x1180080e04d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2483" , 0x1180080e04d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2484" , 0x1180080e04da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2485" , 0x1180080e04da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2486" , 0x1180080e04db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2487" , 0x1180080e04db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2488" , 0x1180080e04dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2489" , 0x1180080e04dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2490" , 0x1180080e04dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2491" , 0x1180080e04dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2492" , 0x1180080e04de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2493" , 0x1180080e04de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2494" , 0x1180080e04df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2495" , 0x1180080e04df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2496" , 0x1180080e04e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2497" , 0x1180080e04e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2498" , 0x1180080e04e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2499" , 0x1180080e04e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2500" , 0x1180080e04e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2501" , 0x1180080e04e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2502" , 0x1180080e04e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2503" , 0x1180080e04e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2504" , 0x1180080e04e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2505" , 0x1180080e04e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2506" , 0x1180080e04e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2507" , 0x1180080e04e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2508" , 0x1180080e04e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2509" , 0x1180080e04e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2510" , 0x1180080e04e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2511" , 0x1180080e04e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2512" , 0x1180080e04e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2513" , 0x1180080e04e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2514" , 0x1180080e04e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2515" , 0x1180080e04e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2516" , 0x1180080e04ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2517" , 0x1180080e04ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2518" , 0x1180080e04eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2519" , 0x1180080e04eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2520" , 0x1180080e04ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2521" , 0x1180080e04ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2522" , 0x1180080e04ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2523" , 0x1180080e04ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2524" , 0x1180080e04ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2525" , 0x1180080e04ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2526" , 0x1180080e04ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2527" , 0x1180080e04ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2528" , 0x1180080e04f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2529" , 0x1180080e04f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2530" , 0x1180080e04f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2531" , 0x1180080e04f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2532" , 0x1180080e04f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2533" , 0x1180080e04f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2534" , 0x1180080e04f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2535" , 0x1180080e04f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2536" , 0x1180080e04f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2537" , 0x1180080e04f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2538" , 0x1180080e04f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2539" , 0x1180080e04f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2540" , 0x1180080e04f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2541" , 0x1180080e04f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2542" , 0x1180080e04f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2543" , 0x1180080e04f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2544" , 0x1180080e04f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2545" , 0x1180080e04f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2546" , 0x1180080e04f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2547" , 0x1180080e04f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2548" , 0x1180080e04fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2549" , 0x1180080e04fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2550" , 0x1180080e04fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2551" , 0x1180080e04fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2552" , 0x1180080e04fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2553" , 0x1180080e04fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2554" , 0x1180080e04fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2555" , 0x1180080e04fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2556" , 0x1180080e04fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2557" , 0x1180080e04fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2558" , 0x1180080e04ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2559" , 0x1180080e04ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2560" , 0x1180080e05000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2561" , 0x1180080e05008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2562" , 0x1180080e05010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2563" , 0x1180080e05018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2564" , 0x1180080e05020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2565" , 0x1180080e05028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2566" , 0x1180080e05030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2567" , 0x1180080e05038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2568" , 0x1180080e05040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2569" , 0x1180080e05048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2570" , 0x1180080e05050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2571" , 0x1180080e05058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2572" , 0x1180080e05060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2573" , 0x1180080e05068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2574" , 0x1180080e05070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2575" , 0x1180080e05078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2576" , 0x1180080e05080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2577" , 0x1180080e05088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2578" , 0x1180080e05090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2579" , 0x1180080e05098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2580" , 0x1180080e050a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2581" , 0x1180080e050a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2582" , 0x1180080e050b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2583" , 0x1180080e050b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2584" , 0x1180080e050c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2585" , 0x1180080e050c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2586" , 0x1180080e050d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2587" , 0x1180080e050d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2588" , 0x1180080e050e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2589" , 0x1180080e050e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2590" , 0x1180080e050f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2591" , 0x1180080e050f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2592" , 0x1180080e05100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2593" , 0x1180080e05108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2594" , 0x1180080e05110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2595" , 0x1180080e05118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2596" , 0x1180080e05120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2597" , 0x1180080e05128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2598" , 0x1180080e05130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2599" , 0x1180080e05138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2600" , 0x1180080e05140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2601" , 0x1180080e05148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2602" , 0x1180080e05150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2603" , 0x1180080e05158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2604" , 0x1180080e05160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2605" , 0x1180080e05168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2606" , 0x1180080e05170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2607" , 0x1180080e05178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2608" , 0x1180080e05180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2609" , 0x1180080e05188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2610" , 0x1180080e05190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2611" , 0x1180080e05198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2612" , 0x1180080e051a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2613" , 0x1180080e051a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2614" , 0x1180080e051b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2615" , 0x1180080e051b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2616" , 0x1180080e051c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2617" , 0x1180080e051c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2618" , 0x1180080e051d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2619" , 0x1180080e051d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2620" , 0x1180080e051e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2621" , 0x1180080e051e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2622" , 0x1180080e051f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2623" , 0x1180080e051f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2624" , 0x1180080e05200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2625" , 0x1180080e05208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2626" , 0x1180080e05210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2627" , 0x1180080e05218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2628" , 0x1180080e05220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2629" , 0x1180080e05228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2630" , 0x1180080e05230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2631" , 0x1180080e05238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2632" , 0x1180080e05240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2633" , 0x1180080e05248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2634" , 0x1180080e05250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2635" , 0x1180080e05258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2636" , 0x1180080e05260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2637" , 0x1180080e05268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2638" , 0x1180080e05270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2639" , 0x1180080e05278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2640" , 0x1180080e05280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2641" , 0x1180080e05288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2642" , 0x1180080e05290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2643" , 0x1180080e05298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2644" , 0x1180080e052a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2645" , 0x1180080e052a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2646" , 0x1180080e052b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2647" , 0x1180080e052b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2648" , 0x1180080e052c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2649" , 0x1180080e052c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2650" , 0x1180080e052d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2651" , 0x1180080e052d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2652" , 0x1180080e052e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2653" , 0x1180080e052e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2654" , 0x1180080e052f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2655" , 0x1180080e052f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2656" , 0x1180080e05300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2657" , 0x1180080e05308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2658" , 0x1180080e05310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2659" , 0x1180080e05318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2660" , 0x1180080e05320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2661" , 0x1180080e05328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2662" , 0x1180080e05330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2663" , 0x1180080e05338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2664" , 0x1180080e05340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2665" , 0x1180080e05348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2666" , 0x1180080e05350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2667" , 0x1180080e05358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2668" , 0x1180080e05360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2669" , 0x1180080e05368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2670" , 0x1180080e05370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2671" , 0x1180080e05378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2672" , 0x1180080e05380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2673" , 0x1180080e05388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2674" , 0x1180080e05390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2675" , 0x1180080e05398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2676" , 0x1180080e053a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2677" , 0x1180080e053a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2678" , 0x1180080e053b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2679" , 0x1180080e053b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2680" , 0x1180080e053c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2681" , 0x1180080e053c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2682" , 0x1180080e053d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2683" , 0x1180080e053d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2684" , 0x1180080e053e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2685" , 0x1180080e053e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2686" , 0x1180080e053f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2687" , 0x1180080e053f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2688" , 0x1180080e05400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2689" , 0x1180080e05408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2690" , 0x1180080e05410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2691" , 0x1180080e05418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2692" , 0x1180080e05420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2693" , 0x1180080e05428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2694" , 0x1180080e05430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2695" , 0x1180080e05438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2696" , 0x1180080e05440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2697" , 0x1180080e05448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2698" , 0x1180080e05450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2699" , 0x1180080e05458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2700" , 0x1180080e05460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2701" , 0x1180080e05468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2702" , 0x1180080e05470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2703" , 0x1180080e05478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2704" , 0x1180080e05480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2705" , 0x1180080e05488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2706" , 0x1180080e05490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2707" , 0x1180080e05498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2708" , 0x1180080e054a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2709" , 0x1180080e054a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2710" , 0x1180080e054b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2711" , 0x1180080e054b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2712" , 0x1180080e054c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2713" , 0x1180080e054c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2714" , 0x1180080e054d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2715" , 0x1180080e054d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2716" , 0x1180080e054e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2717" , 0x1180080e054e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2718" , 0x1180080e054f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2719" , 0x1180080e054f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2720" , 0x1180080e05500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2721" , 0x1180080e05508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2722" , 0x1180080e05510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2723" , 0x1180080e05518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2724" , 0x1180080e05520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2725" , 0x1180080e05528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2726" , 0x1180080e05530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2727" , 0x1180080e05538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2728" , 0x1180080e05540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2729" , 0x1180080e05548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2730" , 0x1180080e05550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2731" , 0x1180080e05558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2732" , 0x1180080e05560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2733" , 0x1180080e05568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2734" , 0x1180080e05570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2735" , 0x1180080e05578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2736" , 0x1180080e05580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2737" , 0x1180080e05588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2738" , 0x1180080e05590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2739" , 0x1180080e05598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2740" , 0x1180080e055a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2741" , 0x1180080e055a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2742" , 0x1180080e055b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2743" , 0x1180080e055b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2744" , 0x1180080e055c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2745" , 0x1180080e055c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2746" , 0x1180080e055d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2747" , 0x1180080e055d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2748" , 0x1180080e055e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2749" , 0x1180080e055e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2750" , 0x1180080e055f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2751" , 0x1180080e055f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2752" , 0x1180080e05600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2753" , 0x1180080e05608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2754" , 0x1180080e05610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2755" , 0x1180080e05618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2756" , 0x1180080e05620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2757" , 0x1180080e05628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2758" , 0x1180080e05630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2759" , 0x1180080e05638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2760" , 0x1180080e05640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2761" , 0x1180080e05648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2762" , 0x1180080e05650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2763" , 0x1180080e05658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2764" , 0x1180080e05660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2765" , 0x1180080e05668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2766" , 0x1180080e05670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2767" , 0x1180080e05678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2768" , 0x1180080e05680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2769" , 0x1180080e05688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2770" , 0x1180080e05690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2771" , 0x1180080e05698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2772" , 0x1180080e056a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2773" , 0x1180080e056a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2774" , 0x1180080e056b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2775" , 0x1180080e056b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2776" , 0x1180080e056c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2777" , 0x1180080e056c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2778" , 0x1180080e056d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2779" , 0x1180080e056d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2780" , 0x1180080e056e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2781" , 0x1180080e056e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2782" , 0x1180080e056f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2783" , 0x1180080e056f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2784" , 0x1180080e05700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2785" , 0x1180080e05708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2786" , 0x1180080e05710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2787" , 0x1180080e05718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2788" , 0x1180080e05720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2789" , 0x1180080e05728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2790" , 0x1180080e05730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2791" , 0x1180080e05738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2792" , 0x1180080e05740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2793" , 0x1180080e05748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2794" , 0x1180080e05750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2795" , 0x1180080e05758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2796" , 0x1180080e05760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2797" , 0x1180080e05768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2798" , 0x1180080e05770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2799" , 0x1180080e05778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2800" , 0x1180080e05780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2801" , 0x1180080e05788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2802" , 0x1180080e05790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2803" , 0x1180080e05798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2804" , 0x1180080e057a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2805" , 0x1180080e057a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2806" , 0x1180080e057b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2807" , 0x1180080e057b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2808" , 0x1180080e057c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2809" , 0x1180080e057c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2810" , 0x1180080e057d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2811" , 0x1180080e057d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2812" , 0x1180080e057e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2813" , 0x1180080e057e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2814" , 0x1180080e057f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2815" , 0x1180080e057f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2816" , 0x1180080e05800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2817" , 0x1180080e05808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2818" , 0x1180080e05810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2819" , 0x1180080e05818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2820" , 0x1180080e05820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2821" , 0x1180080e05828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2822" , 0x1180080e05830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2823" , 0x1180080e05838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2824" , 0x1180080e05840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2825" , 0x1180080e05848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2826" , 0x1180080e05850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2827" , 0x1180080e05858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2828" , 0x1180080e05860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2829" , 0x1180080e05868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2830" , 0x1180080e05870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2831" , 0x1180080e05878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2832" , 0x1180080e05880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2833" , 0x1180080e05888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2834" , 0x1180080e05890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2835" , 0x1180080e05898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2836" , 0x1180080e058a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2837" , 0x1180080e058a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2838" , 0x1180080e058b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2839" , 0x1180080e058b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2840" , 0x1180080e058c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2841" , 0x1180080e058c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2842" , 0x1180080e058d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2843" , 0x1180080e058d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2844" , 0x1180080e058e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2845" , 0x1180080e058e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2846" , 0x1180080e058f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2847" , 0x1180080e058f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2848" , 0x1180080e05900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2849" , 0x1180080e05908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2850" , 0x1180080e05910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2851" , 0x1180080e05918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2852" , 0x1180080e05920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2853" , 0x1180080e05928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2854" , 0x1180080e05930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2855" , 0x1180080e05938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2856" , 0x1180080e05940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2857" , 0x1180080e05948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2858" , 0x1180080e05950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2859" , 0x1180080e05958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2860" , 0x1180080e05960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2861" , 0x1180080e05968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2862" , 0x1180080e05970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2863" , 0x1180080e05978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2864" , 0x1180080e05980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2865" , 0x1180080e05988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2866" , 0x1180080e05990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2867" , 0x1180080e05998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2868" , 0x1180080e059a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2869" , 0x1180080e059a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2870" , 0x1180080e059b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2871" , 0x1180080e059b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2872" , 0x1180080e059c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2873" , 0x1180080e059c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2874" , 0x1180080e059d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2875" , 0x1180080e059d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2876" , 0x1180080e059e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2877" , 0x1180080e059e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2878" , 0x1180080e059f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2879" , 0x1180080e059f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2880" , 0x1180080e05a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2881" , 0x1180080e05a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2882" , 0x1180080e05a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2883" , 0x1180080e05a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2884" , 0x1180080e05a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2885" , 0x1180080e05a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2886" , 0x1180080e05a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2887" , 0x1180080e05a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2888" , 0x1180080e05a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2889" , 0x1180080e05a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2890" , 0x1180080e05a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2891" , 0x1180080e05a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2892" , 0x1180080e05a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2893" , 0x1180080e05a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2894" , 0x1180080e05a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2895" , 0x1180080e05a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2896" , 0x1180080e05a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2897" , 0x1180080e05a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2898" , 0x1180080e05a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2899" , 0x1180080e05a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2900" , 0x1180080e05aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2901" , 0x1180080e05aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2902" , 0x1180080e05ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2903" , 0x1180080e05ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2904" , 0x1180080e05ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2905" , 0x1180080e05ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2906" , 0x1180080e05ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2907" , 0x1180080e05ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2908" , 0x1180080e05ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2909" , 0x1180080e05ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2910" , 0x1180080e05af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2911" , 0x1180080e05af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2912" , 0x1180080e05b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2913" , 0x1180080e05b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2914" , 0x1180080e05b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2915" , 0x1180080e05b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2916" , 0x1180080e05b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2917" , 0x1180080e05b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2918" , 0x1180080e05b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2919" , 0x1180080e05b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2920" , 0x1180080e05b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2921" , 0x1180080e05b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2922" , 0x1180080e05b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2923" , 0x1180080e05b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2924" , 0x1180080e05b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2925" , 0x1180080e05b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2926" , 0x1180080e05b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2927" , 0x1180080e05b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2928" , 0x1180080e05b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2929" , 0x1180080e05b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2930" , 0x1180080e05b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2931" , 0x1180080e05b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2932" , 0x1180080e05ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2933" , 0x1180080e05ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2934" , 0x1180080e05bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2935" , 0x1180080e05bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2936" , 0x1180080e05bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2937" , 0x1180080e05bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2938" , 0x1180080e05bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2939" , 0x1180080e05bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2940" , 0x1180080e05be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2941" , 0x1180080e05be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2942" , 0x1180080e05bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2943" , 0x1180080e05bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2944" , 0x1180080e05c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2945" , 0x1180080e05c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2946" , 0x1180080e05c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2947" , 0x1180080e05c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2948" , 0x1180080e05c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2949" , 0x1180080e05c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2950" , 0x1180080e05c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2951" , 0x1180080e05c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2952" , 0x1180080e05c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2953" , 0x1180080e05c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2954" , 0x1180080e05c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2955" , 0x1180080e05c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2956" , 0x1180080e05c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2957" , 0x1180080e05c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2958" , 0x1180080e05c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2959" , 0x1180080e05c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2960" , 0x1180080e05c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2961" , 0x1180080e05c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2962" , 0x1180080e05c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2963" , 0x1180080e05c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2964" , 0x1180080e05ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2965" , 0x1180080e05ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2966" , 0x1180080e05cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2967" , 0x1180080e05cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2968" , 0x1180080e05cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2969" , 0x1180080e05cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2970" , 0x1180080e05cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2971" , 0x1180080e05cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2972" , 0x1180080e05ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2973" , 0x1180080e05ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2974" , 0x1180080e05cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2975" , 0x1180080e05cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2976" , 0x1180080e05d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2977" , 0x1180080e05d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2978" , 0x1180080e05d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2979" , 0x1180080e05d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2980" , 0x1180080e05d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2981" , 0x1180080e05d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2982" , 0x1180080e05d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2983" , 0x1180080e05d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2984" , 0x1180080e05d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2985" , 0x1180080e05d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2986" , 0x1180080e05d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2987" , 0x1180080e05d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2988" , 0x1180080e05d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2989" , 0x1180080e05d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2990" , 0x1180080e05d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2991" , 0x1180080e05d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2992" , 0x1180080e05d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2993" , 0x1180080e05d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2994" , 0x1180080e05d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2995" , 0x1180080e05d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2996" , 0x1180080e05da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2997" , 0x1180080e05da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2998" , 0x1180080e05db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP2999" , 0x1180080e05db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3000" , 0x1180080e05dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3001" , 0x1180080e05dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3002" , 0x1180080e05dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3003" , 0x1180080e05dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3004" , 0x1180080e05de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3005" , 0x1180080e05de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3006" , 0x1180080e05df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3007" , 0x1180080e05df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3008" , 0x1180080e05e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3009" , 0x1180080e05e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3010" , 0x1180080e05e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3011" , 0x1180080e05e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3012" , 0x1180080e05e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3013" , 0x1180080e05e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3014" , 0x1180080e05e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3015" , 0x1180080e05e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3016" , 0x1180080e05e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3017" , 0x1180080e05e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3018" , 0x1180080e05e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3019" , 0x1180080e05e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3020" , 0x1180080e05e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3021" , 0x1180080e05e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3022" , 0x1180080e05e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3023" , 0x1180080e05e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3024" , 0x1180080e05e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3025" , 0x1180080e05e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3026" , 0x1180080e05e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3027" , 0x1180080e05e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3028" , 0x1180080e05ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3029" , 0x1180080e05ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3030" , 0x1180080e05eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3031" , 0x1180080e05eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3032" , 0x1180080e05ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3033" , 0x1180080e05ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3034" , 0x1180080e05ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3035" , 0x1180080e05ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3036" , 0x1180080e05ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3037" , 0x1180080e05ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3038" , 0x1180080e05ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3039" , 0x1180080e05ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3040" , 0x1180080e05f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3041" , 0x1180080e05f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3042" , 0x1180080e05f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3043" , 0x1180080e05f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3044" , 0x1180080e05f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3045" , 0x1180080e05f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3046" , 0x1180080e05f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3047" , 0x1180080e05f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3048" , 0x1180080e05f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3049" , 0x1180080e05f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3050" , 0x1180080e05f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3051" , 0x1180080e05f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3052" , 0x1180080e05f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3053" , 0x1180080e05f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3054" , 0x1180080e05f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3055" , 0x1180080e05f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3056" , 0x1180080e05f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3057" , 0x1180080e05f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3058" , 0x1180080e05f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3059" , 0x1180080e05f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3060" , 0x1180080e05fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3061" , 0x1180080e05fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3062" , 0x1180080e05fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3063" , 0x1180080e05fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3064" , 0x1180080e05fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3065" , 0x1180080e05fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3066" , 0x1180080e05fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3067" , 0x1180080e05fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3068" , 0x1180080e05fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3069" , 0x1180080e05fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3070" , 0x1180080e05ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3071" , 0x1180080e05ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3072" , 0x1180080e06000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3073" , 0x1180080e06008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3074" , 0x1180080e06010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3075" , 0x1180080e06018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3076" , 0x1180080e06020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3077" , 0x1180080e06028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3078" , 0x1180080e06030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3079" , 0x1180080e06038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3080" , 0x1180080e06040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3081" , 0x1180080e06048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3082" , 0x1180080e06050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3083" , 0x1180080e06058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3084" , 0x1180080e06060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3085" , 0x1180080e06068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3086" , 0x1180080e06070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3087" , 0x1180080e06078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3088" , 0x1180080e06080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3089" , 0x1180080e06088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3090" , 0x1180080e06090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3091" , 0x1180080e06098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3092" , 0x1180080e060a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3093" , 0x1180080e060a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3094" , 0x1180080e060b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3095" , 0x1180080e060b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3096" , 0x1180080e060c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3097" , 0x1180080e060c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3098" , 0x1180080e060d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3099" , 0x1180080e060d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3100" , 0x1180080e060e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3101" , 0x1180080e060e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3102" , 0x1180080e060f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3103" , 0x1180080e060f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3104" , 0x1180080e06100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3105" , 0x1180080e06108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3106" , 0x1180080e06110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3107" , 0x1180080e06118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3108" , 0x1180080e06120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3109" , 0x1180080e06128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3110" , 0x1180080e06130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3111" , 0x1180080e06138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3112" , 0x1180080e06140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3113" , 0x1180080e06148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3114" , 0x1180080e06150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3115" , 0x1180080e06158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3116" , 0x1180080e06160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3117" , 0x1180080e06168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3118" , 0x1180080e06170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3119" , 0x1180080e06178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3120" , 0x1180080e06180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3121" , 0x1180080e06188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3122" , 0x1180080e06190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3123" , 0x1180080e06198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3124" , 0x1180080e061a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3125" , 0x1180080e061a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3126" , 0x1180080e061b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3127" , 0x1180080e061b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3128" , 0x1180080e061c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3129" , 0x1180080e061c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3130" , 0x1180080e061d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3131" , 0x1180080e061d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3132" , 0x1180080e061e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3133" , 0x1180080e061e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3134" , 0x1180080e061f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3135" , 0x1180080e061f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3136" , 0x1180080e06200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3137" , 0x1180080e06208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3138" , 0x1180080e06210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3139" , 0x1180080e06218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3140" , 0x1180080e06220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3141" , 0x1180080e06228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3142" , 0x1180080e06230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3143" , 0x1180080e06238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3144" , 0x1180080e06240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3145" , 0x1180080e06248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3146" , 0x1180080e06250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3147" , 0x1180080e06258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3148" , 0x1180080e06260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3149" , 0x1180080e06268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3150" , 0x1180080e06270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3151" , 0x1180080e06278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3152" , 0x1180080e06280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3153" , 0x1180080e06288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3154" , 0x1180080e06290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3155" , 0x1180080e06298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3156" , 0x1180080e062a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3157" , 0x1180080e062a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3158" , 0x1180080e062b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3159" , 0x1180080e062b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3160" , 0x1180080e062c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3161" , 0x1180080e062c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3162" , 0x1180080e062d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3163" , 0x1180080e062d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3164" , 0x1180080e062e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3165" , 0x1180080e062e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3166" , 0x1180080e062f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3167" , 0x1180080e062f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3168" , 0x1180080e06300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3169" , 0x1180080e06308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3170" , 0x1180080e06310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3171" , 0x1180080e06318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3172" , 0x1180080e06320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3173" , 0x1180080e06328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3174" , 0x1180080e06330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3175" , 0x1180080e06338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3176" , 0x1180080e06340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3177" , 0x1180080e06348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3178" , 0x1180080e06350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3179" , 0x1180080e06358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3180" , 0x1180080e06360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3181" , 0x1180080e06368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3182" , 0x1180080e06370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3183" , 0x1180080e06378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3184" , 0x1180080e06380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3185" , 0x1180080e06388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3186" , 0x1180080e06390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3187" , 0x1180080e06398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3188" , 0x1180080e063a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3189" , 0x1180080e063a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3190" , 0x1180080e063b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3191" , 0x1180080e063b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3192" , 0x1180080e063c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3193" , 0x1180080e063c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3194" , 0x1180080e063d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3195" , 0x1180080e063d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3196" , 0x1180080e063e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3197" , 0x1180080e063e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3198" , 0x1180080e063f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3199" , 0x1180080e063f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3200" , 0x1180080e06400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3201" , 0x1180080e06408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3202" , 0x1180080e06410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3203" , 0x1180080e06418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3204" , 0x1180080e06420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3205" , 0x1180080e06428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3206" , 0x1180080e06430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3207" , 0x1180080e06438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3208" , 0x1180080e06440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3209" , 0x1180080e06448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3210" , 0x1180080e06450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3211" , 0x1180080e06458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3212" , 0x1180080e06460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3213" , 0x1180080e06468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3214" , 0x1180080e06470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3215" , 0x1180080e06478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3216" , 0x1180080e06480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3217" , 0x1180080e06488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3218" , 0x1180080e06490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3219" , 0x1180080e06498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3220" , 0x1180080e064a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3221" , 0x1180080e064a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3222" , 0x1180080e064b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3223" , 0x1180080e064b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3224" , 0x1180080e064c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3225" , 0x1180080e064c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3226" , 0x1180080e064d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3227" , 0x1180080e064d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3228" , 0x1180080e064e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3229" , 0x1180080e064e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3230" , 0x1180080e064f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3231" , 0x1180080e064f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3232" , 0x1180080e06500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3233" , 0x1180080e06508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3234" , 0x1180080e06510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3235" , 0x1180080e06518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3236" , 0x1180080e06520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3237" , 0x1180080e06528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3238" , 0x1180080e06530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3239" , 0x1180080e06538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3240" , 0x1180080e06540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3241" , 0x1180080e06548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3242" , 0x1180080e06550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3243" , 0x1180080e06558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3244" , 0x1180080e06560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3245" , 0x1180080e06568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3246" , 0x1180080e06570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3247" , 0x1180080e06578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3248" , 0x1180080e06580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3249" , 0x1180080e06588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3250" , 0x1180080e06590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3251" , 0x1180080e06598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3252" , 0x1180080e065a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3253" , 0x1180080e065a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3254" , 0x1180080e065b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3255" , 0x1180080e065b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3256" , 0x1180080e065c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3257" , 0x1180080e065c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3258" , 0x1180080e065d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3259" , 0x1180080e065d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3260" , 0x1180080e065e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3261" , 0x1180080e065e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3262" , 0x1180080e065f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3263" , 0x1180080e065f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3264" , 0x1180080e06600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3265" , 0x1180080e06608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3266" , 0x1180080e06610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3267" , 0x1180080e06618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3268" , 0x1180080e06620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3269" , 0x1180080e06628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3270" , 0x1180080e06630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3271" , 0x1180080e06638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3272" , 0x1180080e06640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3273" , 0x1180080e06648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3274" , 0x1180080e06650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3275" , 0x1180080e06658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3276" , 0x1180080e06660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3277" , 0x1180080e06668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3278" , 0x1180080e06670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3279" , 0x1180080e06678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3280" , 0x1180080e06680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3281" , 0x1180080e06688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3282" , 0x1180080e06690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3283" , 0x1180080e06698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3284" , 0x1180080e066a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3285" , 0x1180080e066a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3286" , 0x1180080e066b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3287" , 0x1180080e066b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3288" , 0x1180080e066c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3289" , 0x1180080e066c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3290" , 0x1180080e066d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3291" , 0x1180080e066d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3292" , 0x1180080e066e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3293" , 0x1180080e066e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3294" , 0x1180080e066f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3295" , 0x1180080e066f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3296" , 0x1180080e06700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3297" , 0x1180080e06708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3298" , 0x1180080e06710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3299" , 0x1180080e06718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3300" , 0x1180080e06720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3301" , 0x1180080e06728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3302" , 0x1180080e06730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3303" , 0x1180080e06738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3304" , 0x1180080e06740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3305" , 0x1180080e06748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3306" , 0x1180080e06750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3307" , 0x1180080e06758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3308" , 0x1180080e06760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3309" , 0x1180080e06768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3310" , 0x1180080e06770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3311" , 0x1180080e06778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3312" , 0x1180080e06780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3313" , 0x1180080e06788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3314" , 0x1180080e06790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3315" , 0x1180080e06798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3316" , 0x1180080e067a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3317" , 0x1180080e067a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3318" , 0x1180080e067b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3319" , 0x1180080e067b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3320" , 0x1180080e067c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3321" , 0x1180080e067c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3322" , 0x1180080e067d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3323" , 0x1180080e067d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3324" , 0x1180080e067e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3325" , 0x1180080e067e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3326" , 0x1180080e067f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3327" , 0x1180080e067f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3328" , 0x1180080e06800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3329" , 0x1180080e06808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3330" , 0x1180080e06810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3331" , 0x1180080e06818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3332" , 0x1180080e06820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3333" , 0x1180080e06828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3334" , 0x1180080e06830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3335" , 0x1180080e06838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3336" , 0x1180080e06840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3337" , 0x1180080e06848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3338" , 0x1180080e06850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3339" , 0x1180080e06858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3340" , 0x1180080e06860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3341" , 0x1180080e06868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3342" , 0x1180080e06870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3343" , 0x1180080e06878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3344" , 0x1180080e06880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3345" , 0x1180080e06888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3346" , 0x1180080e06890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3347" , 0x1180080e06898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3348" , 0x1180080e068a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3349" , 0x1180080e068a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3350" , 0x1180080e068b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3351" , 0x1180080e068b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3352" , 0x1180080e068c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3353" , 0x1180080e068c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3354" , 0x1180080e068d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3355" , 0x1180080e068d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3356" , 0x1180080e068e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3357" , 0x1180080e068e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3358" , 0x1180080e068f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3359" , 0x1180080e068f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3360" , 0x1180080e06900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3361" , 0x1180080e06908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3362" , 0x1180080e06910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3363" , 0x1180080e06918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3364" , 0x1180080e06920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3365" , 0x1180080e06928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3366" , 0x1180080e06930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3367" , 0x1180080e06938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3368" , 0x1180080e06940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3369" , 0x1180080e06948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3370" , 0x1180080e06950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3371" , 0x1180080e06958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3372" , 0x1180080e06960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3373" , 0x1180080e06968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3374" , 0x1180080e06970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3375" , 0x1180080e06978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3376" , 0x1180080e06980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3377" , 0x1180080e06988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3378" , 0x1180080e06990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3379" , 0x1180080e06998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3380" , 0x1180080e069a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3381" , 0x1180080e069a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3382" , 0x1180080e069b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3383" , 0x1180080e069b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3384" , 0x1180080e069c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3385" , 0x1180080e069c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3386" , 0x1180080e069d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3387" , 0x1180080e069d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3388" , 0x1180080e069e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3389" , 0x1180080e069e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3390" , 0x1180080e069f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3391" , 0x1180080e069f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3392" , 0x1180080e06a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3393" , 0x1180080e06a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3394" , 0x1180080e06a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3395" , 0x1180080e06a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3396" , 0x1180080e06a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3397" , 0x1180080e06a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3398" , 0x1180080e06a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3399" , 0x1180080e06a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3400" , 0x1180080e06a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3401" , 0x1180080e06a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3402" , 0x1180080e06a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3403" , 0x1180080e06a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3404" , 0x1180080e06a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3405" , 0x1180080e06a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3406" , 0x1180080e06a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3407" , 0x1180080e06a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3408" , 0x1180080e06a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3409" , 0x1180080e06a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3410" , 0x1180080e06a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3411" , 0x1180080e06a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3412" , 0x1180080e06aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3413" , 0x1180080e06aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3414" , 0x1180080e06ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3415" , 0x1180080e06ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3416" , 0x1180080e06ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3417" , 0x1180080e06ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3418" , 0x1180080e06ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3419" , 0x1180080e06ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3420" , 0x1180080e06ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3421" , 0x1180080e06ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3422" , 0x1180080e06af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3423" , 0x1180080e06af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3424" , 0x1180080e06b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3425" , 0x1180080e06b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3426" , 0x1180080e06b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3427" , 0x1180080e06b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3428" , 0x1180080e06b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3429" , 0x1180080e06b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3430" , 0x1180080e06b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3431" , 0x1180080e06b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3432" , 0x1180080e06b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3433" , 0x1180080e06b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3434" , 0x1180080e06b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3435" , 0x1180080e06b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3436" , 0x1180080e06b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3437" , 0x1180080e06b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3438" , 0x1180080e06b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3439" , 0x1180080e06b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3440" , 0x1180080e06b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3441" , 0x1180080e06b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3442" , 0x1180080e06b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3443" , 0x1180080e06b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3444" , 0x1180080e06ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3445" , 0x1180080e06ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3446" , 0x1180080e06bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3447" , 0x1180080e06bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3448" , 0x1180080e06bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3449" , 0x1180080e06bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3450" , 0x1180080e06bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3451" , 0x1180080e06bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3452" , 0x1180080e06be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3453" , 0x1180080e06be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3454" , 0x1180080e06bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3455" , 0x1180080e06bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3456" , 0x1180080e06c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3457" , 0x1180080e06c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3458" , 0x1180080e06c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3459" , 0x1180080e06c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3460" , 0x1180080e06c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3461" , 0x1180080e06c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3462" , 0x1180080e06c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3463" , 0x1180080e06c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3464" , 0x1180080e06c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3465" , 0x1180080e06c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3466" , 0x1180080e06c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3467" , 0x1180080e06c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3468" , 0x1180080e06c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3469" , 0x1180080e06c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3470" , 0x1180080e06c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3471" , 0x1180080e06c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3472" , 0x1180080e06c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3473" , 0x1180080e06c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3474" , 0x1180080e06c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3475" , 0x1180080e06c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3476" , 0x1180080e06ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3477" , 0x1180080e06ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3478" , 0x1180080e06cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3479" , 0x1180080e06cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3480" , 0x1180080e06cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3481" , 0x1180080e06cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3482" , 0x1180080e06cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3483" , 0x1180080e06cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3484" , 0x1180080e06ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3485" , 0x1180080e06ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3486" , 0x1180080e06cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3487" , 0x1180080e06cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3488" , 0x1180080e06d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3489" , 0x1180080e06d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3490" , 0x1180080e06d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3491" , 0x1180080e06d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3492" , 0x1180080e06d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3493" , 0x1180080e06d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3494" , 0x1180080e06d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3495" , 0x1180080e06d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3496" , 0x1180080e06d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3497" , 0x1180080e06d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3498" , 0x1180080e06d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3499" , 0x1180080e06d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3500" , 0x1180080e06d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3501" , 0x1180080e06d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3502" , 0x1180080e06d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3503" , 0x1180080e06d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3504" , 0x1180080e06d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3505" , 0x1180080e06d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3506" , 0x1180080e06d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3507" , 0x1180080e06d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3508" , 0x1180080e06da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3509" , 0x1180080e06da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3510" , 0x1180080e06db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3511" , 0x1180080e06db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3512" , 0x1180080e06dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3513" , 0x1180080e06dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3514" , 0x1180080e06dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3515" , 0x1180080e06dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3516" , 0x1180080e06de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3517" , 0x1180080e06de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3518" , 0x1180080e06df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3519" , 0x1180080e06df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3520" , 0x1180080e06e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3521" , 0x1180080e06e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3522" , 0x1180080e06e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3523" , 0x1180080e06e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3524" , 0x1180080e06e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3525" , 0x1180080e06e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3526" , 0x1180080e06e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3527" , 0x1180080e06e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3528" , 0x1180080e06e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3529" , 0x1180080e06e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3530" , 0x1180080e06e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3531" , 0x1180080e06e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3532" , 0x1180080e06e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3533" , 0x1180080e06e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3534" , 0x1180080e06e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3535" , 0x1180080e06e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3536" , 0x1180080e06e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3537" , 0x1180080e06e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3538" , 0x1180080e06e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3539" , 0x1180080e06e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3540" , 0x1180080e06ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3541" , 0x1180080e06ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3542" , 0x1180080e06eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3543" , 0x1180080e06eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3544" , 0x1180080e06ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3545" , 0x1180080e06ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3546" , 0x1180080e06ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3547" , 0x1180080e06ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3548" , 0x1180080e06ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3549" , 0x1180080e06ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3550" , 0x1180080e06ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3551" , 0x1180080e06ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3552" , 0x1180080e06f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3553" , 0x1180080e06f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3554" , 0x1180080e06f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3555" , 0x1180080e06f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3556" , 0x1180080e06f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3557" , 0x1180080e06f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3558" , 0x1180080e06f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3559" , 0x1180080e06f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3560" , 0x1180080e06f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3561" , 0x1180080e06f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3562" , 0x1180080e06f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3563" , 0x1180080e06f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3564" , 0x1180080e06f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3565" , 0x1180080e06f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3566" , 0x1180080e06f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3567" , 0x1180080e06f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3568" , 0x1180080e06f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3569" , 0x1180080e06f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3570" , 0x1180080e06f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3571" , 0x1180080e06f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3572" , 0x1180080e06fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3573" , 0x1180080e06fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3574" , 0x1180080e06fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3575" , 0x1180080e06fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3576" , 0x1180080e06fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3577" , 0x1180080e06fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3578" , 0x1180080e06fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3579" , 0x1180080e06fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3580" , 0x1180080e06fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3581" , 0x1180080e06fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3582" , 0x1180080e06ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3583" , 0x1180080e06ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3584" , 0x1180080e07000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3585" , 0x1180080e07008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3586" , 0x1180080e07010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3587" , 0x1180080e07018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3588" , 0x1180080e07020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3589" , 0x1180080e07028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3590" , 0x1180080e07030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3591" , 0x1180080e07038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3592" , 0x1180080e07040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3593" , 0x1180080e07048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3594" , 0x1180080e07050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3595" , 0x1180080e07058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3596" , 0x1180080e07060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3597" , 0x1180080e07068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3598" , 0x1180080e07070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3599" , 0x1180080e07078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3600" , 0x1180080e07080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3601" , 0x1180080e07088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3602" , 0x1180080e07090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3603" , 0x1180080e07098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3604" , 0x1180080e070a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3605" , 0x1180080e070a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3606" , 0x1180080e070b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3607" , 0x1180080e070b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3608" , 0x1180080e070c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3609" , 0x1180080e070c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3610" , 0x1180080e070d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3611" , 0x1180080e070d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3612" , 0x1180080e070e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3613" , 0x1180080e070e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3614" , 0x1180080e070f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3615" , 0x1180080e070f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3616" , 0x1180080e07100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3617" , 0x1180080e07108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3618" , 0x1180080e07110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3619" , 0x1180080e07118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3620" , 0x1180080e07120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3621" , 0x1180080e07128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3622" , 0x1180080e07130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3623" , 0x1180080e07138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3624" , 0x1180080e07140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3625" , 0x1180080e07148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3626" , 0x1180080e07150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3627" , 0x1180080e07158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3628" , 0x1180080e07160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3629" , 0x1180080e07168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3630" , 0x1180080e07170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3631" , 0x1180080e07178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3632" , 0x1180080e07180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3633" , 0x1180080e07188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3634" , 0x1180080e07190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3635" , 0x1180080e07198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3636" , 0x1180080e071a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3637" , 0x1180080e071a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3638" , 0x1180080e071b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3639" , 0x1180080e071b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3640" , 0x1180080e071c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3641" , 0x1180080e071c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3642" , 0x1180080e071d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3643" , 0x1180080e071d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3644" , 0x1180080e071e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3645" , 0x1180080e071e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3646" , 0x1180080e071f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3647" , 0x1180080e071f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3648" , 0x1180080e07200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3649" , 0x1180080e07208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3650" , 0x1180080e07210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3651" , 0x1180080e07218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3652" , 0x1180080e07220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3653" , 0x1180080e07228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3654" , 0x1180080e07230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3655" , 0x1180080e07238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3656" , 0x1180080e07240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3657" , 0x1180080e07248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3658" , 0x1180080e07250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3659" , 0x1180080e07258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3660" , 0x1180080e07260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3661" , 0x1180080e07268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3662" , 0x1180080e07270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3663" , 0x1180080e07278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3664" , 0x1180080e07280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3665" , 0x1180080e07288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3666" , 0x1180080e07290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3667" , 0x1180080e07298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3668" , 0x1180080e072a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3669" , 0x1180080e072a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3670" , 0x1180080e072b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3671" , 0x1180080e072b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3672" , 0x1180080e072c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3673" , 0x1180080e072c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3674" , 0x1180080e072d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3675" , 0x1180080e072d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3676" , 0x1180080e072e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3677" , 0x1180080e072e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3678" , 0x1180080e072f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3679" , 0x1180080e072f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3680" , 0x1180080e07300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3681" , 0x1180080e07308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3682" , 0x1180080e07310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3683" , 0x1180080e07318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3684" , 0x1180080e07320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3685" , 0x1180080e07328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3686" , 0x1180080e07330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3687" , 0x1180080e07338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3688" , 0x1180080e07340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3689" , 0x1180080e07348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3690" , 0x1180080e07350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3691" , 0x1180080e07358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3692" , 0x1180080e07360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3693" , 0x1180080e07368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3694" , 0x1180080e07370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3695" , 0x1180080e07378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3696" , 0x1180080e07380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3697" , 0x1180080e07388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3698" , 0x1180080e07390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3699" , 0x1180080e07398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3700" , 0x1180080e073a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3701" , 0x1180080e073a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3702" , 0x1180080e073b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3703" , 0x1180080e073b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3704" , 0x1180080e073c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3705" , 0x1180080e073c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3706" , 0x1180080e073d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3707" , 0x1180080e073d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3708" , 0x1180080e073e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3709" , 0x1180080e073e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3710" , 0x1180080e073f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3711" , 0x1180080e073f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3712" , 0x1180080e07400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3713" , 0x1180080e07408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3714" , 0x1180080e07410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3715" , 0x1180080e07418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3716" , 0x1180080e07420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3717" , 0x1180080e07428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3718" , 0x1180080e07430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3719" , 0x1180080e07438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3720" , 0x1180080e07440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3721" , 0x1180080e07448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3722" , 0x1180080e07450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3723" , 0x1180080e07458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3724" , 0x1180080e07460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3725" , 0x1180080e07468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3726" , 0x1180080e07470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3727" , 0x1180080e07478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3728" , 0x1180080e07480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3729" , 0x1180080e07488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3730" , 0x1180080e07490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3731" , 0x1180080e07498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3732" , 0x1180080e074a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3733" , 0x1180080e074a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3734" , 0x1180080e074b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3735" , 0x1180080e074b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3736" , 0x1180080e074c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3737" , 0x1180080e074c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3738" , 0x1180080e074d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3739" , 0x1180080e074d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3740" , 0x1180080e074e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3741" , 0x1180080e074e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3742" , 0x1180080e074f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3743" , 0x1180080e074f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3744" , 0x1180080e07500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3745" , 0x1180080e07508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3746" , 0x1180080e07510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3747" , 0x1180080e07518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3748" , 0x1180080e07520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3749" , 0x1180080e07528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3750" , 0x1180080e07530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3751" , 0x1180080e07538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3752" , 0x1180080e07540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3753" , 0x1180080e07548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3754" , 0x1180080e07550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3755" , 0x1180080e07558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3756" , 0x1180080e07560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3757" , 0x1180080e07568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3758" , 0x1180080e07570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3759" , 0x1180080e07578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3760" , 0x1180080e07580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3761" , 0x1180080e07588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3762" , 0x1180080e07590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3763" , 0x1180080e07598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3764" , 0x1180080e075a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3765" , 0x1180080e075a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3766" , 0x1180080e075b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3767" , 0x1180080e075b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3768" , 0x1180080e075c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3769" , 0x1180080e075c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3770" , 0x1180080e075d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3771" , 0x1180080e075d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3772" , 0x1180080e075e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3773" , 0x1180080e075e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3774" , 0x1180080e075f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3775" , 0x1180080e075f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3776" , 0x1180080e07600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3777" , 0x1180080e07608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3778" , 0x1180080e07610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3779" , 0x1180080e07618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3780" , 0x1180080e07620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3781" , 0x1180080e07628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3782" , 0x1180080e07630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3783" , 0x1180080e07638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3784" , 0x1180080e07640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3785" , 0x1180080e07648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3786" , 0x1180080e07650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3787" , 0x1180080e07658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3788" , 0x1180080e07660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3789" , 0x1180080e07668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3790" , 0x1180080e07670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3791" , 0x1180080e07678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3792" , 0x1180080e07680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3793" , 0x1180080e07688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3794" , 0x1180080e07690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3795" , 0x1180080e07698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3796" , 0x1180080e076a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3797" , 0x1180080e076a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3798" , 0x1180080e076b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3799" , 0x1180080e076b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3800" , 0x1180080e076c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3801" , 0x1180080e076c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3802" , 0x1180080e076d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3803" , 0x1180080e076d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3804" , 0x1180080e076e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3805" , 0x1180080e076e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3806" , 0x1180080e076f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3807" , 0x1180080e076f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3808" , 0x1180080e07700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3809" , 0x1180080e07708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3810" , 0x1180080e07710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3811" , 0x1180080e07718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3812" , 0x1180080e07720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3813" , 0x1180080e07728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3814" , 0x1180080e07730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3815" , 0x1180080e07738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3816" , 0x1180080e07740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3817" , 0x1180080e07748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3818" , 0x1180080e07750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3819" , 0x1180080e07758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3820" , 0x1180080e07760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3821" , 0x1180080e07768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3822" , 0x1180080e07770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3823" , 0x1180080e07778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3824" , 0x1180080e07780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3825" , 0x1180080e07788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3826" , 0x1180080e07790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3827" , 0x1180080e07798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3828" , 0x1180080e077a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3829" , 0x1180080e077a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3830" , 0x1180080e077b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3831" , 0x1180080e077b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3832" , 0x1180080e077c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3833" , 0x1180080e077c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3834" , 0x1180080e077d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3835" , 0x1180080e077d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3836" , 0x1180080e077e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3837" , 0x1180080e077e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3838" , 0x1180080e077f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3839" , 0x1180080e077f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3840" , 0x1180080e07800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3841" , 0x1180080e07808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3842" , 0x1180080e07810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3843" , 0x1180080e07818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3844" , 0x1180080e07820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3845" , 0x1180080e07828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3846" , 0x1180080e07830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3847" , 0x1180080e07838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3848" , 0x1180080e07840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3849" , 0x1180080e07848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3850" , 0x1180080e07850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3851" , 0x1180080e07858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3852" , 0x1180080e07860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3853" , 0x1180080e07868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3854" , 0x1180080e07870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3855" , 0x1180080e07878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3856" , 0x1180080e07880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3857" , 0x1180080e07888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3858" , 0x1180080e07890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3859" , 0x1180080e07898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3860" , 0x1180080e078a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3861" , 0x1180080e078a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3862" , 0x1180080e078b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3863" , 0x1180080e078b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3864" , 0x1180080e078c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3865" , 0x1180080e078c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3866" , 0x1180080e078d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3867" , 0x1180080e078d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3868" , 0x1180080e078e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3869" , 0x1180080e078e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3870" , 0x1180080e078f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3871" , 0x1180080e078f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3872" , 0x1180080e07900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3873" , 0x1180080e07908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3874" , 0x1180080e07910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3875" , 0x1180080e07918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3876" , 0x1180080e07920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3877" , 0x1180080e07928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3878" , 0x1180080e07930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3879" , 0x1180080e07938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3880" , 0x1180080e07940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3881" , 0x1180080e07948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3882" , 0x1180080e07950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3883" , 0x1180080e07958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3884" , 0x1180080e07960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3885" , 0x1180080e07968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3886" , 0x1180080e07970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3887" , 0x1180080e07978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3888" , 0x1180080e07980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3889" , 0x1180080e07988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3890" , 0x1180080e07990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3891" , 0x1180080e07998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3892" , 0x1180080e079a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3893" , 0x1180080e079a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3894" , 0x1180080e079b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3895" , 0x1180080e079b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3896" , 0x1180080e079c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3897" , 0x1180080e079c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3898" , 0x1180080e079d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3899" , 0x1180080e079d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3900" , 0x1180080e079e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3901" , 0x1180080e079e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3902" , 0x1180080e079f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3903" , 0x1180080e079f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3904" , 0x1180080e07a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3905" , 0x1180080e07a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3906" , 0x1180080e07a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3907" , 0x1180080e07a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3908" , 0x1180080e07a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3909" , 0x1180080e07a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3910" , 0x1180080e07a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3911" , 0x1180080e07a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3912" , 0x1180080e07a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3913" , 0x1180080e07a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3914" , 0x1180080e07a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3915" , 0x1180080e07a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3916" , 0x1180080e07a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3917" , 0x1180080e07a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3918" , 0x1180080e07a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3919" , 0x1180080e07a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3920" , 0x1180080e07a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3921" , 0x1180080e07a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3922" , 0x1180080e07a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3923" , 0x1180080e07a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3924" , 0x1180080e07aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3925" , 0x1180080e07aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3926" , 0x1180080e07ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3927" , 0x1180080e07ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3928" , 0x1180080e07ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3929" , 0x1180080e07ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3930" , 0x1180080e07ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3931" , 0x1180080e07ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3932" , 0x1180080e07ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3933" , 0x1180080e07ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3934" , 0x1180080e07af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3935" , 0x1180080e07af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3936" , 0x1180080e07b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3937" , 0x1180080e07b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3938" , 0x1180080e07b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3939" , 0x1180080e07b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3940" , 0x1180080e07b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3941" , 0x1180080e07b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3942" , 0x1180080e07b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3943" , 0x1180080e07b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3944" , 0x1180080e07b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3945" , 0x1180080e07b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3946" , 0x1180080e07b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3947" , 0x1180080e07b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3948" , 0x1180080e07b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3949" , 0x1180080e07b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3950" , 0x1180080e07b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3951" , 0x1180080e07b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3952" , 0x1180080e07b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3953" , 0x1180080e07b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3954" , 0x1180080e07b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3955" , 0x1180080e07b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3956" , 0x1180080e07ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3957" , 0x1180080e07ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3958" , 0x1180080e07bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3959" , 0x1180080e07bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3960" , 0x1180080e07bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3961" , 0x1180080e07bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3962" , 0x1180080e07bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3963" , 0x1180080e07bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3964" , 0x1180080e07be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3965" , 0x1180080e07be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3966" , 0x1180080e07bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3967" , 0x1180080e07bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3968" , 0x1180080e07c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3969" , 0x1180080e07c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3970" , 0x1180080e07c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3971" , 0x1180080e07c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3972" , 0x1180080e07c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3973" , 0x1180080e07c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3974" , 0x1180080e07c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3975" , 0x1180080e07c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3976" , 0x1180080e07c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3977" , 0x1180080e07c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3978" , 0x1180080e07c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3979" , 0x1180080e07c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3980" , 0x1180080e07c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3981" , 0x1180080e07c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3982" , 0x1180080e07c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3983" , 0x1180080e07c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3984" , 0x1180080e07c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3985" , 0x1180080e07c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3986" , 0x1180080e07c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3987" , 0x1180080e07c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3988" , 0x1180080e07ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3989" , 0x1180080e07ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3990" , 0x1180080e07cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3991" , 0x1180080e07cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3992" , 0x1180080e07cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3993" , 0x1180080e07cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3994" , 0x1180080e07cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3995" , 0x1180080e07cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3996" , 0x1180080e07ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3997" , 0x1180080e07ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3998" , 0x1180080e07cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP3999" , 0x1180080e07cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4000" , 0x1180080e07d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4001" , 0x1180080e07d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4002" , 0x1180080e07d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4003" , 0x1180080e07d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4004" , 0x1180080e07d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4005" , 0x1180080e07d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4006" , 0x1180080e07d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4007" , 0x1180080e07d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4008" , 0x1180080e07d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4009" , 0x1180080e07d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4010" , 0x1180080e07d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4011" , 0x1180080e07d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4012" , 0x1180080e07d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4013" , 0x1180080e07d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4014" , 0x1180080e07d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4015" , 0x1180080e07d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4016" , 0x1180080e07d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4017" , 0x1180080e07d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4018" , 0x1180080e07d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4019" , 0x1180080e07d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4020" , 0x1180080e07da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4021" , 0x1180080e07da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4022" , 0x1180080e07db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4023" , 0x1180080e07db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4024" , 0x1180080e07dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4025" , 0x1180080e07dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4026" , 0x1180080e07dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4027" , 0x1180080e07dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4028" , 0x1180080e07de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4029" , 0x1180080e07de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4030" , 0x1180080e07df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4031" , 0x1180080e07df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4032" , 0x1180080e07e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4033" , 0x1180080e07e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4034" , 0x1180080e07e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4035" , 0x1180080e07e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4036" , 0x1180080e07e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4037" , 0x1180080e07e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4038" , 0x1180080e07e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4039" , 0x1180080e07e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4040" , 0x1180080e07e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4041" , 0x1180080e07e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4042" , 0x1180080e07e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4043" , 0x1180080e07e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4044" , 0x1180080e07e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4045" , 0x1180080e07e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4046" , 0x1180080e07e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4047" , 0x1180080e07e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4048" , 0x1180080e07e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4049" , 0x1180080e07e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4050" , 0x1180080e07e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4051" , 0x1180080e07e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4052" , 0x1180080e07ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4053" , 0x1180080e07ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4054" , 0x1180080e07eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4055" , 0x1180080e07eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4056" , 0x1180080e07ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4057" , 0x1180080e07ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4058" , 0x1180080e07ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4059" , 0x1180080e07ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4060" , 0x1180080e07ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4061" , 0x1180080e07ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4062" , 0x1180080e07ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4063" , 0x1180080e07ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4064" , 0x1180080e07f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4065" , 0x1180080e07f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4066" , 0x1180080e07f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4067" , 0x1180080e07f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4068" , 0x1180080e07f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4069" , 0x1180080e07f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4070" , 0x1180080e07f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4071" , 0x1180080e07f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4072" , 0x1180080e07f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4073" , 0x1180080e07f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4074" , 0x1180080e07f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4075" , 0x1180080e07f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4076" , 0x1180080e07f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4077" , 0x1180080e07f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4078" , 0x1180080e07f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4079" , 0x1180080e07f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4080" , 0x1180080e07f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4081" , 0x1180080e07f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4082" , 0x1180080e07f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4083" , 0x1180080e07f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4084" , 0x1180080e07fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4085" , 0x1180080e07fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4086" , 0x1180080e07fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4087" , 0x1180080e07fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4088" , 0x1180080e07fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4089" , 0x1180080e07fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4090" , 0x1180080e07fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4091" , 0x1180080e07fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4092" , 0x1180080e07fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4093" , 0x1180080e07fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4094" , 0x1180080e07ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4095" , 0x1180080e07ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4096" , 0x1180080e08000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4097" , 0x1180080e08008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4098" , 0x1180080e08010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4099" , 0x1180080e08018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4100" , 0x1180080e08020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4101" , 0x1180080e08028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4102" , 0x1180080e08030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4103" , 0x1180080e08038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4104" , 0x1180080e08040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4105" , 0x1180080e08048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4106" , 0x1180080e08050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4107" , 0x1180080e08058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4108" , 0x1180080e08060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4109" , 0x1180080e08068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4110" , 0x1180080e08070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4111" , 0x1180080e08078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4112" , 0x1180080e08080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4113" , 0x1180080e08088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4114" , 0x1180080e08090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4115" , 0x1180080e08098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4116" , 0x1180080e080a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4117" , 0x1180080e080a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4118" , 0x1180080e080b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4119" , 0x1180080e080b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4120" , 0x1180080e080c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4121" , 0x1180080e080c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4122" , 0x1180080e080d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4123" , 0x1180080e080d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4124" , 0x1180080e080e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4125" , 0x1180080e080e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4126" , 0x1180080e080f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4127" , 0x1180080e080f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4128" , 0x1180080e08100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4129" , 0x1180080e08108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4130" , 0x1180080e08110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4131" , 0x1180080e08118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4132" , 0x1180080e08120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4133" , 0x1180080e08128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4134" , 0x1180080e08130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4135" , 0x1180080e08138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4136" , 0x1180080e08140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4137" , 0x1180080e08148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4138" , 0x1180080e08150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4139" , 0x1180080e08158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4140" , 0x1180080e08160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4141" , 0x1180080e08168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4142" , 0x1180080e08170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4143" , 0x1180080e08178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4144" , 0x1180080e08180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4145" , 0x1180080e08188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4146" , 0x1180080e08190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4147" , 0x1180080e08198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4148" , 0x1180080e081a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4149" , 0x1180080e081a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4150" , 0x1180080e081b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4151" , 0x1180080e081b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4152" , 0x1180080e081c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4153" , 0x1180080e081c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4154" , 0x1180080e081d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4155" , 0x1180080e081d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4156" , 0x1180080e081e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4157" , 0x1180080e081e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4158" , 0x1180080e081f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4159" , 0x1180080e081f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4160" , 0x1180080e08200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4161" , 0x1180080e08208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4162" , 0x1180080e08210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4163" , 0x1180080e08218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4164" , 0x1180080e08220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4165" , 0x1180080e08228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4166" , 0x1180080e08230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4167" , 0x1180080e08238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4168" , 0x1180080e08240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4169" , 0x1180080e08248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4170" , 0x1180080e08250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4171" , 0x1180080e08258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4172" , 0x1180080e08260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4173" , 0x1180080e08268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4174" , 0x1180080e08270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4175" , 0x1180080e08278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4176" , 0x1180080e08280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4177" , 0x1180080e08288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4178" , 0x1180080e08290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4179" , 0x1180080e08298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4180" , 0x1180080e082a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4181" , 0x1180080e082a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4182" , 0x1180080e082b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4183" , 0x1180080e082b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4184" , 0x1180080e082c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4185" , 0x1180080e082c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4186" , 0x1180080e082d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4187" , 0x1180080e082d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4188" , 0x1180080e082e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4189" , 0x1180080e082e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4190" , 0x1180080e082f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4191" , 0x1180080e082f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4192" , 0x1180080e08300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4193" , 0x1180080e08308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4194" , 0x1180080e08310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4195" , 0x1180080e08318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4196" , 0x1180080e08320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4197" , 0x1180080e08328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4198" , 0x1180080e08330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4199" , 0x1180080e08338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4200" , 0x1180080e08340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4201" , 0x1180080e08348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4202" , 0x1180080e08350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4203" , 0x1180080e08358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4204" , 0x1180080e08360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4205" , 0x1180080e08368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4206" , 0x1180080e08370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4207" , 0x1180080e08378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4208" , 0x1180080e08380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4209" , 0x1180080e08388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4210" , 0x1180080e08390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4211" , 0x1180080e08398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4212" , 0x1180080e083a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4213" , 0x1180080e083a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4214" , 0x1180080e083b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4215" , 0x1180080e083b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4216" , 0x1180080e083c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4217" , 0x1180080e083c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4218" , 0x1180080e083d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4219" , 0x1180080e083d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4220" , 0x1180080e083e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4221" , 0x1180080e083e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4222" , 0x1180080e083f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4223" , 0x1180080e083f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4224" , 0x1180080e08400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4225" , 0x1180080e08408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4226" , 0x1180080e08410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4227" , 0x1180080e08418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4228" , 0x1180080e08420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4229" , 0x1180080e08428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4230" , 0x1180080e08430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4231" , 0x1180080e08438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4232" , 0x1180080e08440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4233" , 0x1180080e08448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4234" , 0x1180080e08450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4235" , 0x1180080e08458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4236" , 0x1180080e08460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4237" , 0x1180080e08468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4238" , 0x1180080e08470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4239" , 0x1180080e08478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4240" , 0x1180080e08480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4241" , 0x1180080e08488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4242" , 0x1180080e08490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4243" , 0x1180080e08498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4244" , 0x1180080e084a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4245" , 0x1180080e084a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4246" , 0x1180080e084b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4247" , 0x1180080e084b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4248" , 0x1180080e084c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4249" , 0x1180080e084c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4250" , 0x1180080e084d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4251" , 0x1180080e084d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4252" , 0x1180080e084e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4253" , 0x1180080e084e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4254" , 0x1180080e084f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4255" , 0x1180080e084f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4256" , 0x1180080e08500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4257" , 0x1180080e08508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4258" , 0x1180080e08510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4259" , 0x1180080e08518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4260" , 0x1180080e08520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4261" , 0x1180080e08528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4262" , 0x1180080e08530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4263" , 0x1180080e08538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4264" , 0x1180080e08540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4265" , 0x1180080e08548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4266" , 0x1180080e08550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4267" , 0x1180080e08558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4268" , 0x1180080e08560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4269" , 0x1180080e08568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4270" , 0x1180080e08570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4271" , 0x1180080e08578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4272" , 0x1180080e08580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4273" , 0x1180080e08588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4274" , 0x1180080e08590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4275" , 0x1180080e08598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4276" , 0x1180080e085a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4277" , 0x1180080e085a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4278" , 0x1180080e085b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4279" , 0x1180080e085b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4280" , 0x1180080e085c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4281" , 0x1180080e085c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4282" , 0x1180080e085d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4283" , 0x1180080e085d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4284" , 0x1180080e085e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4285" , 0x1180080e085e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4286" , 0x1180080e085f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4287" , 0x1180080e085f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4288" , 0x1180080e08600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4289" , 0x1180080e08608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4290" , 0x1180080e08610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4291" , 0x1180080e08618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4292" , 0x1180080e08620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4293" , 0x1180080e08628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4294" , 0x1180080e08630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4295" , 0x1180080e08638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4296" , 0x1180080e08640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4297" , 0x1180080e08648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4298" , 0x1180080e08650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4299" , 0x1180080e08658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4300" , 0x1180080e08660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4301" , 0x1180080e08668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4302" , 0x1180080e08670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4303" , 0x1180080e08678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4304" , 0x1180080e08680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4305" , 0x1180080e08688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4306" , 0x1180080e08690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4307" , 0x1180080e08698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4308" , 0x1180080e086a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4309" , 0x1180080e086a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4310" , 0x1180080e086b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4311" , 0x1180080e086b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4312" , 0x1180080e086c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4313" , 0x1180080e086c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4314" , 0x1180080e086d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4315" , 0x1180080e086d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4316" , 0x1180080e086e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4317" , 0x1180080e086e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4318" , 0x1180080e086f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4319" , 0x1180080e086f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4320" , 0x1180080e08700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4321" , 0x1180080e08708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4322" , 0x1180080e08710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4323" , 0x1180080e08718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4324" , 0x1180080e08720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4325" , 0x1180080e08728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4326" , 0x1180080e08730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4327" , 0x1180080e08738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4328" , 0x1180080e08740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4329" , 0x1180080e08748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4330" , 0x1180080e08750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4331" , 0x1180080e08758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4332" , 0x1180080e08760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4333" , 0x1180080e08768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4334" , 0x1180080e08770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4335" , 0x1180080e08778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4336" , 0x1180080e08780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4337" , 0x1180080e08788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4338" , 0x1180080e08790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4339" , 0x1180080e08798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4340" , 0x1180080e087a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4341" , 0x1180080e087a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4342" , 0x1180080e087b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4343" , 0x1180080e087b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4344" , 0x1180080e087c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4345" , 0x1180080e087c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4346" , 0x1180080e087d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4347" , 0x1180080e087d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4348" , 0x1180080e087e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4349" , 0x1180080e087e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4350" , 0x1180080e087f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4351" , 0x1180080e087f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4352" , 0x1180080e08800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4353" , 0x1180080e08808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4354" , 0x1180080e08810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4355" , 0x1180080e08818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4356" , 0x1180080e08820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4357" , 0x1180080e08828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4358" , 0x1180080e08830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4359" , 0x1180080e08838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4360" , 0x1180080e08840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4361" , 0x1180080e08848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4362" , 0x1180080e08850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4363" , 0x1180080e08858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4364" , 0x1180080e08860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4365" , 0x1180080e08868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4366" , 0x1180080e08870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4367" , 0x1180080e08878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4368" , 0x1180080e08880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4369" , 0x1180080e08888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4370" , 0x1180080e08890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4371" , 0x1180080e08898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4372" , 0x1180080e088a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4373" , 0x1180080e088a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4374" , 0x1180080e088b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4375" , 0x1180080e088b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4376" , 0x1180080e088c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4377" , 0x1180080e088c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4378" , 0x1180080e088d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4379" , 0x1180080e088d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4380" , 0x1180080e088e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4381" , 0x1180080e088e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4382" , 0x1180080e088f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4383" , 0x1180080e088f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4384" , 0x1180080e08900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4385" , 0x1180080e08908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4386" , 0x1180080e08910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4387" , 0x1180080e08918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4388" , 0x1180080e08920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4389" , 0x1180080e08928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4390" , 0x1180080e08930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4391" , 0x1180080e08938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4392" , 0x1180080e08940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4393" , 0x1180080e08948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4394" , 0x1180080e08950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4395" , 0x1180080e08958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4396" , 0x1180080e08960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4397" , 0x1180080e08968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4398" , 0x1180080e08970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4399" , 0x1180080e08978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4400" , 0x1180080e08980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4401" , 0x1180080e08988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4402" , 0x1180080e08990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4403" , 0x1180080e08998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4404" , 0x1180080e089a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4405" , 0x1180080e089a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4406" , 0x1180080e089b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4407" , 0x1180080e089b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4408" , 0x1180080e089c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4409" , 0x1180080e089c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4410" , 0x1180080e089d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4411" , 0x1180080e089d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4412" , 0x1180080e089e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4413" , 0x1180080e089e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4414" , 0x1180080e089f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4415" , 0x1180080e089f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4416" , 0x1180080e08a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4417" , 0x1180080e08a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4418" , 0x1180080e08a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4419" , 0x1180080e08a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4420" , 0x1180080e08a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4421" , 0x1180080e08a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4422" , 0x1180080e08a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4423" , 0x1180080e08a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4424" , 0x1180080e08a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4425" , 0x1180080e08a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4426" , 0x1180080e08a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4427" , 0x1180080e08a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4428" , 0x1180080e08a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4429" , 0x1180080e08a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4430" , 0x1180080e08a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4431" , 0x1180080e08a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4432" , 0x1180080e08a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4433" , 0x1180080e08a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4434" , 0x1180080e08a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4435" , 0x1180080e08a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4436" , 0x1180080e08aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4437" , 0x1180080e08aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4438" , 0x1180080e08ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4439" , 0x1180080e08ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4440" , 0x1180080e08ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4441" , 0x1180080e08ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4442" , 0x1180080e08ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4443" , 0x1180080e08ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4444" , 0x1180080e08ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4445" , 0x1180080e08ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4446" , 0x1180080e08af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4447" , 0x1180080e08af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4448" , 0x1180080e08b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4449" , 0x1180080e08b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4450" , 0x1180080e08b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4451" , 0x1180080e08b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4452" , 0x1180080e08b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4453" , 0x1180080e08b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4454" , 0x1180080e08b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4455" , 0x1180080e08b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4456" , 0x1180080e08b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4457" , 0x1180080e08b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4458" , 0x1180080e08b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4459" , 0x1180080e08b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4460" , 0x1180080e08b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4461" , 0x1180080e08b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4462" , 0x1180080e08b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4463" , 0x1180080e08b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4464" , 0x1180080e08b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4465" , 0x1180080e08b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4466" , 0x1180080e08b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4467" , 0x1180080e08b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4468" , 0x1180080e08ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4469" , 0x1180080e08ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4470" , 0x1180080e08bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4471" , 0x1180080e08bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4472" , 0x1180080e08bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4473" , 0x1180080e08bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4474" , 0x1180080e08bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4475" , 0x1180080e08bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4476" , 0x1180080e08be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4477" , 0x1180080e08be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4478" , 0x1180080e08bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4479" , 0x1180080e08bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4480" , 0x1180080e08c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4481" , 0x1180080e08c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4482" , 0x1180080e08c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4483" , 0x1180080e08c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4484" , 0x1180080e08c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4485" , 0x1180080e08c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4486" , 0x1180080e08c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4487" , 0x1180080e08c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4488" , 0x1180080e08c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4489" , 0x1180080e08c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4490" , 0x1180080e08c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4491" , 0x1180080e08c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4492" , 0x1180080e08c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4493" , 0x1180080e08c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4494" , 0x1180080e08c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4495" , 0x1180080e08c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4496" , 0x1180080e08c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4497" , 0x1180080e08c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4498" , 0x1180080e08c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4499" , 0x1180080e08c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4500" , 0x1180080e08ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4501" , 0x1180080e08ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4502" , 0x1180080e08cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4503" , 0x1180080e08cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4504" , 0x1180080e08cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4505" , 0x1180080e08cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4506" , 0x1180080e08cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4507" , 0x1180080e08cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4508" , 0x1180080e08ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4509" , 0x1180080e08ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4510" , 0x1180080e08cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4511" , 0x1180080e08cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4512" , 0x1180080e08d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4513" , 0x1180080e08d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4514" , 0x1180080e08d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4515" , 0x1180080e08d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4516" , 0x1180080e08d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4517" , 0x1180080e08d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4518" , 0x1180080e08d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4519" , 0x1180080e08d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4520" , 0x1180080e08d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4521" , 0x1180080e08d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4522" , 0x1180080e08d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4523" , 0x1180080e08d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4524" , 0x1180080e08d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4525" , 0x1180080e08d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4526" , 0x1180080e08d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4527" , 0x1180080e08d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4528" , 0x1180080e08d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4529" , 0x1180080e08d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4530" , 0x1180080e08d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4531" , 0x1180080e08d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4532" , 0x1180080e08da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4533" , 0x1180080e08da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4534" , 0x1180080e08db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4535" , 0x1180080e08db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4536" , 0x1180080e08dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4537" , 0x1180080e08dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4538" , 0x1180080e08dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4539" , 0x1180080e08dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4540" , 0x1180080e08de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4541" , 0x1180080e08de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4542" , 0x1180080e08df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4543" , 0x1180080e08df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4544" , 0x1180080e08e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4545" , 0x1180080e08e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4546" , 0x1180080e08e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4547" , 0x1180080e08e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4548" , 0x1180080e08e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4549" , 0x1180080e08e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4550" , 0x1180080e08e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4551" , 0x1180080e08e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4552" , 0x1180080e08e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4553" , 0x1180080e08e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4554" , 0x1180080e08e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4555" , 0x1180080e08e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4556" , 0x1180080e08e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4557" , 0x1180080e08e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4558" , 0x1180080e08e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4559" , 0x1180080e08e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4560" , 0x1180080e08e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4561" , 0x1180080e08e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4562" , 0x1180080e08e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4563" , 0x1180080e08e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4564" , 0x1180080e08ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4565" , 0x1180080e08ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4566" , 0x1180080e08eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4567" , 0x1180080e08eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4568" , 0x1180080e08ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4569" , 0x1180080e08ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4570" , 0x1180080e08ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4571" , 0x1180080e08ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4572" , 0x1180080e08ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4573" , 0x1180080e08ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4574" , 0x1180080e08ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4575" , 0x1180080e08ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4576" , 0x1180080e08f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4577" , 0x1180080e08f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4578" , 0x1180080e08f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4579" , 0x1180080e08f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4580" , 0x1180080e08f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4581" , 0x1180080e08f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4582" , 0x1180080e08f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4583" , 0x1180080e08f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4584" , 0x1180080e08f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4585" , 0x1180080e08f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4586" , 0x1180080e08f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4587" , 0x1180080e08f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4588" , 0x1180080e08f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4589" , 0x1180080e08f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4590" , 0x1180080e08f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4591" , 0x1180080e08f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4592" , 0x1180080e08f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4593" , 0x1180080e08f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4594" , 0x1180080e08f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4595" , 0x1180080e08f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4596" , 0x1180080e08fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4597" , 0x1180080e08fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4598" , 0x1180080e08fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4599" , 0x1180080e08fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4600" , 0x1180080e08fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4601" , 0x1180080e08fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4602" , 0x1180080e08fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4603" , 0x1180080e08fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4604" , 0x1180080e08fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4605" , 0x1180080e08fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4606" , 0x1180080e08ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4607" , 0x1180080e08ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4608" , 0x1180080e09000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4609" , 0x1180080e09008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4610" , 0x1180080e09010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4611" , 0x1180080e09018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4612" , 0x1180080e09020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4613" , 0x1180080e09028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4614" , 0x1180080e09030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4615" , 0x1180080e09038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4616" , 0x1180080e09040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4617" , 0x1180080e09048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4618" , 0x1180080e09050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4619" , 0x1180080e09058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4620" , 0x1180080e09060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4621" , 0x1180080e09068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4622" , 0x1180080e09070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4623" , 0x1180080e09078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4624" , 0x1180080e09080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4625" , 0x1180080e09088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4626" , 0x1180080e09090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4627" , 0x1180080e09098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4628" , 0x1180080e090a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4629" , 0x1180080e090a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4630" , 0x1180080e090b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4631" , 0x1180080e090b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4632" , 0x1180080e090c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4633" , 0x1180080e090c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4634" , 0x1180080e090d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4635" , 0x1180080e090d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4636" , 0x1180080e090e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4637" , 0x1180080e090e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4638" , 0x1180080e090f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4639" , 0x1180080e090f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4640" , 0x1180080e09100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4641" , 0x1180080e09108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4642" , 0x1180080e09110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4643" , 0x1180080e09118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4644" , 0x1180080e09120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4645" , 0x1180080e09128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4646" , 0x1180080e09130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4647" , 0x1180080e09138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4648" , 0x1180080e09140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4649" , 0x1180080e09148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4650" , 0x1180080e09150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4651" , 0x1180080e09158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4652" , 0x1180080e09160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4653" , 0x1180080e09168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4654" , 0x1180080e09170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4655" , 0x1180080e09178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4656" , 0x1180080e09180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4657" , 0x1180080e09188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4658" , 0x1180080e09190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4659" , 0x1180080e09198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4660" , 0x1180080e091a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4661" , 0x1180080e091a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4662" , 0x1180080e091b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4663" , 0x1180080e091b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4664" , 0x1180080e091c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4665" , 0x1180080e091c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4666" , 0x1180080e091d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4667" , 0x1180080e091d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4668" , 0x1180080e091e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4669" , 0x1180080e091e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4670" , 0x1180080e091f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4671" , 0x1180080e091f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4672" , 0x1180080e09200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4673" , 0x1180080e09208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4674" , 0x1180080e09210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4675" , 0x1180080e09218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4676" , 0x1180080e09220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4677" , 0x1180080e09228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4678" , 0x1180080e09230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4679" , 0x1180080e09238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4680" , 0x1180080e09240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4681" , 0x1180080e09248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4682" , 0x1180080e09250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4683" , 0x1180080e09258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4684" , 0x1180080e09260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4685" , 0x1180080e09268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4686" , 0x1180080e09270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4687" , 0x1180080e09278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4688" , 0x1180080e09280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4689" , 0x1180080e09288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4690" , 0x1180080e09290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4691" , 0x1180080e09298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4692" , 0x1180080e092a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4693" , 0x1180080e092a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4694" , 0x1180080e092b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4695" , 0x1180080e092b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4696" , 0x1180080e092c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4697" , 0x1180080e092c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4698" , 0x1180080e092d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4699" , 0x1180080e092d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4700" , 0x1180080e092e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4701" , 0x1180080e092e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4702" , 0x1180080e092f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4703" , 0x1180080e092f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4704" , 0x1180080e09300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4705" , 0x1180080e09308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4706" , 0x1180080e09310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4707" , 0x1180080e09318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4708" , 0x1180080e09320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4709" , 0x1180080e09328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4710" , 0x1180080e09330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4711" , 0x1180080e09338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4712" , 0x1180080e09340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4713" , 0x1180080e09348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4714" , 0x1180080e09350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4715" , 0x1180080e09358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4716" , 0x1180080e09360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4717" , 0x1180080e09368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4718" , 0x1180080e09370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4719" , 0x1180080e09378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4720" , 0x1180080e09380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4721" , 0x1180080e09388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4722" , 0x1180080e09390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4723" , 0x1180080e09398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4724" , 0x1180080e093a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4725" , 0x1180080e093a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4726" , 0x1180080e093b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4727" , 0x1180080e093b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4728" , 0x1180080e093c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4729" , 0x1180080e093c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4730" , 0x1180080e093d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4731" , 0x1180080e093d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4732" , 0x1180080e093e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4733" , 0x1180080e093e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4734" , 0x1180080e093f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4735" , 0x1180080e093f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4736" , 0x1180080e09400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4737" , 0x1180080e09408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4738" , 0x1180080e09410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4739" , 0x1180080e09418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4740" , 0x1180080e09420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4741" , 0x1180080e09428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4742" , 0x1180080e09430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4743" , 0x1180080e09438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4744" , 0x1180080e09440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4745" , 0x1180080e09448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4746" , 0x1180080e09450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4747" , 0x1180080e09458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4748" , 0x1180080e09460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4749" , 0x1180080e09468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4750" , 0x1180080e09470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4751" , 0x1180080e09478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4752" , 0x1180080e09480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4753" , 0x1180080e09488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4754" , 0x1180080e09490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4755" , 0x1180080e09498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4756" , 0x1180080e094a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4757" , 0x1180080e094a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4758" , 0x1180080e094b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4759" , 0x1180080e094b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4760" , 0x1180080e094c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4761" , 0x1180080e094c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4762" , 0x1180080e094d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4763" , 0x1180080e094d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4764" , 0x1180080e094e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4765" , 0x1180080e094e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4766" , 0x1180080e094f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4767" , 0x1180080e094f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4768" , 0x1180080e09500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4769" , 0x1180080e09508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4770" , 0x1180080e09510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4771" , 0x1180080e09518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4772" , 0x1180080e09520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4773" , 0x1180080e09528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4774" , 0x1180080e09530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4775" , 0x1180080e09538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4776" , 0x1180080e09540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4777" , 0x1180080e09548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4778" , 0x1180080e09550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4779" , 0x1180080e09558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4780" , 0x1180080e09560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4781" , 0x1180080e09568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4782" , 0x1180080e09570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4783" , 0x1180080e09578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4784" , 0x1180080e09580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4785" , 0x1180080e09588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4786" , 0x1180080e09590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4787" , 0x1180080e09598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4788" , 0x1180080e095a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4789" , 0x1180080e095a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4790" , 0x1180080e095b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4791" , 0x1180080e095b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4792" , 0x1180080e095c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4793" , 0x1180080e095c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4794" , 0x1180080e095d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4795" , 0x1180080e095d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4796" , 0x1180080e095e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4797" , 0x1180080e095e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4798" , 0x1180080e095f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4799" , 0x1180080e095f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4800" , 0x1180080e09600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4801" , 0x1180080e09608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4802" , 0x1180080e09610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4803" , 0x1180080e09618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4804" , 0x1180080e09620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4805" , 0x1180080e09628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4806" , 0x1180080e09630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4807" , 0x1180080e09638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4808" , 0x1180080e09640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4809" , 0x1180080e09648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4810" , 0x1180080e09650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4811" , 0x1180080e09658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4812" , 0x1180080e09660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4813" , 0x1180080e09668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4814" , 0x1180080e09670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4815" , 0x1180080e09678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4816" , 0x1180080e09680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4817" , 0x1180080e09688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4818" , 0x1180080e09690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4819" , 0x1180080e09698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4820" , 0x1180080e096a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4821" , 0x1180080e096a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4822" , 0x1180080e096b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4823" , 0x1180080e096b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4824" , 0x1180080e096c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4825" , 0x1180080e096c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4826" , 0x1180080e096d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4827" , 0x1180080e096d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4828" , 0x1180080e096e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4829" , 0x1180080e096e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4830" , 0x1180080e096f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4831" , 0x1180080e096f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4832" , 0x1180080e09700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4833" , 0x1180080e09708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4834" , 0x1180080e09710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4835" , 0x1180080e09718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4836" , 0x1180080e09720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4837" , 0x1180080e09728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4838" , 0x1180080e09730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4839" , 0x1180080e09738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4840" , 0x1180080e09740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4841" , 0x1180080e09748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4842" , 0x1180080e09750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4843" , 0x1180080e09758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4844" , 0x1180080e09760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4845" , 0x1180080e09768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4846" , 0x1180080e09770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4847" , 0x1180080e09778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4848" , 0x1180080e09780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4849" , 0x1180080e09788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4850" , 0x1180080e09790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4851" , 0x1180080e09798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4852" , 0x1180080e097a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4853" , 0x1180080e097a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4854" , 0x1180080e097b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4855" , 0x1180080e097b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4856" , 0x1180080e097c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4857" , 0x1180080e097c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4858" , 0x1180080e097d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4859" , 0x1180080e097d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4860" , 0x1180080e097e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4861" , 0x1180080e097e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4862" , 0x1180080e097f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4863" , 0x1180080e097f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4864" , 0x1180080e09800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4865" , 0x1180080e09808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4866" , 0x1180080e09810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4867" , 0x1180080e09818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4868" , 0x1180080e09820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4869" , 0x1180080e09828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4870" , 0x1180080e09830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4871" , 0x1180080e09838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4872" , 0x1180080e09840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4873" , 0x1180080e09848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4874" , 0x1180080e09850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4875" , 0x1180080e09858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4876" , 0x1180080e09860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4877" , 0x1180080e09868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4878" , 0x1180080e09870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4879" , 0x1180080e09878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4880" , 0x1180080e09880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4881" , 0x1180080e09888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4882" , 0x1180080e09890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4883" , 0x1180080e09898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4884" , 0x1180080e098a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4885" , 0x1180080e098a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4886" , 0x1180080e098b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4887" , 0x1180080e098b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4888" , 0x1180080e098c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4889" , 0x1180080e098c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4890" , 0x1180080e098d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4891" , 0x1180080e098d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4892" , 0x1180080e098e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4893" , 0x1180080e098e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4894" , 0x1180080e098f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4895" , 0x1180080e098f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4896" , 0x1180080e09900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4897" , 0x1180080e09908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4898" , 0x1180080e09910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4899" , 0x1180080e09918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4900" , 0x1180080e09920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4901" , 0x1180080e09928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4902" , 0x1180080e09930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4903" , 0x1180080e09938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4904" , 0x1180080e09940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4905" , 0x1180080e09948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4906" , 0x1180080e09950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4907" , 0x1180080e09958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4908" , 0x1180080e09960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4909" , 0x1180080e09968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4910" , 0x1180080e09970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4911" , 0x1180080e09978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4912" , 0x1180080e09980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4913" , 0x1180080e09988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4914" , 0x1180080e09990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4915" , 0x1180080e09998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4916" , 0x1180080e099a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4917" , 0x1180080e099a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4918" , 0x1180080e099b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4919" , 0x1180080e099b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4920" , 0x1180080e099c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4921" , 0x1180080e099c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4922" , 0x1180080e099d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4923" , 0x1180080e099d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4924" , 0x1180080e099e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4925" , 0x1180080e099e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4926" , 0x1180080e099f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4927" , 0x1180080e099f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4928" , 0x1180080e09a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4929" , 0x1180080e09a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4930" , 0x1180080e09a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4931" , 0x1180080e09a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4932" , 0x1180080e09a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4933" , 0x1180080e09a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4934" , 0x1180080e09a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4935" , 0x1180080e09a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4936" , 0x1180080e09a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4937" , 0x1180080e09a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4938" , 0x1180080e09a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4939" , 0x1180080e09a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4940" , 0x1180080e09a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4941" , 0x1180080e09a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4942" , 0x1180080e09a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4943" , 0x1180080e09a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4944" , 0x1180080e09a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4945" , 0x1180080e09a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4946" , 0x1180080e09a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4947" , 0x1180080e09a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4948" , 0x1180080e09aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4949" , 0x1180080e09aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4950" , 0x1180080e09ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4951" , 0x1180080e09ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4952" , 0x1180080e09ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4953" , 0x1180080e09ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4954" , 0x1180080e09ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4955" , 0x1180080e09ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4956" , 0x1180080e09ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4957" , 0x1180080e09ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4958" , 0x1180080e09af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4959" , 0x1180080e09af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4960" , 0x1180080e09b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4961" , 0x1180080e09b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4962" , 0x1180080e09b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4963" , 0x1180080e09b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4964" , 0x1180080e09b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4965" , 0x1180080e09b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4966" , 0x1180080e09b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4967" , 0x1180080e09b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4968" , 0x1180080e09b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4969" , 0x1180080e09b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4970" , 0x1180080e09b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4971" , 0x1180080e09b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4972" , 0x1180080e09b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4973" , 0x1180080e09b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4974" , 0x1180080e09b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4975" , 0x1180080e09b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4976" , 0x1180080e09b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4977" , 0x1180080e09b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4978" , 0x1180080e09b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4979" , 0x1180080e09b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4980" , 0x1180080e09ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4981" , 0x1180080e09ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4982" , 0x1180080e09bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4983" , 0x1180080e09bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4984" , 0x1180080e09bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4985" , 0x1180080e09bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4986" , 0x1180080e09bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4987" , 0x1180080e09bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4988" , 0x1180080e09be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4989" , 0x1180080e09be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4990" , 0x1180080e09bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4991" , 0x1180080e09bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4992" , 0x1180080e09c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4993" , 0x1180080e09c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4994" , 0x1180080e09c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4995" , 0x1180080e09c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4996" , 0x1180080e09c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4997" , 0x1180080e09c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4998" , 0x1180080e09c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP4999" , 0x1180080e09c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5000" , 0x1180080e09c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5001" , 0x1180080e09c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5002" , 0x1180080e09c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5003" , 0x1180080e09c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5004" , 0x1180080e09c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5005" , 0x1180080e09c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5006" , 0x1180080e09c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5007" , 0x1180080e09c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5008" , 0x1180080e09c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5009" , 0x1180080e09c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5010" , 0x1180080e09c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5011" , 0x1180080e09c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5012" , 0x1180080e09ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5013" , 0x1180080e09ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5014" , 0x1180080e09cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5015" , 0x1180080e09cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5016" , 0x1180080e09cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5017" , 0x1180080e09cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5018" , 0x1180080e09cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5019" , 0x1180080e09cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5020" , 0x1180080e09ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5021" , 0x1180080e09ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5022" , 0x1180080e09cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5023" , 0x1180080e09cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5024" , 0x1180080e09d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5025" , 0x1180080e09d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5026" , 0x1180080e09d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5027" , 0x1180080e09d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5028" , 0x1180080e09d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5029" , 0x1180080e09d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5030" , 0x1180080e09d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5031" , 0x1180080e09d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5032" , 0x1180080e09d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5033" , 0x1180080e09d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5034" , 0x1180080e09d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5035" , 0x1180080e09d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5036" , 0x1180080e09d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5037" , 0x1180080e09d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5038" , 0x1180080e09d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5039" , 0x1180080e09d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5040" , 0x1180080e09d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5041" , 0x1180080e09d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5042" , 0x1180080e09d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5043" , 0x1180080e09d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5044" , 0x1180080e09da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5045" , 0x1180080e09da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5046" , 0x1180080e09db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5047" , 0x1180080e09db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5048" , 0x1180080e09dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5049" , 0x1180080e09dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5050" , 0x1180080e09dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5051" , 0x1180080e09dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5052" , 0x1180080e09de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5053" , 0x1180080e09de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5054" , 0x1180080e09df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5055" , 0x1180080e09df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5056" , 0x1180080e09e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5057" , 0x1180080e09e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5058" , 0x1180080e09e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5059" , 0x1180080e09e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5060" , 0x1180080e09e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5061" , 0x1180080e09e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5062" , 0x1180080e09e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5063" , 0x1180080e09e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5064" , 0x1180080e09e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5065" , 0x1180080e09e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5066" , 0x1180080e09e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5067" , 0x1180080e09e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5068" , 0x1180080e09e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5069" , 0x1180080e09e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5070" , 0x1180080e09e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5071" , 0x1180080e09e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5072" , 0x1180080e09e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5073" , 0x1180080e09e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5074" , 0x1180080e09e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5075" , 0x1180080e09e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5076" , 0x1180080e09ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5077" , 0x1180080e09ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5078" , 0x1180080e09eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5079" , 0x1180080e09eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5080" , 0x1180080e09ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5081" , 0x1180080e09ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5082" , 0x1180080e09ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5083" , 0x1180080e09ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5084" , 0x1180080e09ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5085" , 0x1180080e09ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5086" , 0x1180080e09ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5087" , 0x1180080e09ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5088" , 0x1180080e09f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5089" , 0x1180080e09f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5090" , 0x1180080e09f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5091" , 0x1180080e09f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5092" , 0x1180080e09f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5093" , 0x1180080e09f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5094" , 0x1180080e09f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5095" , 0x1180080e09f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5096" , 0x1180080e09f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5097" , 0x1180080e09f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5098" , 0x1180080e09f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5099" , 0x1180080e09f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5100" , 0x1180080e09f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5101" , 0x1180080e09f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5102" , 0x1180080e09f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5103" , 0x1180080e09f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5104" , 0x1180080e09f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5105" , 0x1180080e09f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5106" , 0x1180080e09f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5107" , 0x1180080e09f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5108" , 0x1180080e09fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5109" , 0x1180080e09fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5110" , 0x1180080e09fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5111" , 0x1180080e09fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5112" , 0x1180080e09fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5113" , 0x1180080e09fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5114" , 0x1180080e09fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5115" , 0x1180080e09fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5116" , 0x1180080e09fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5117" , 0x1180080e09fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5118" , 0x1180080e09ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5119" , 0x1180080e09ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5120" , 0x1180080e0a000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5121" , 0x1180080e0a008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5122" , 0x1180080e0a010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5123" , 0x1180080e0a018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5124" , 0x1180080e0a020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5125" , 0x1180080e0a028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5126" , 0x1180080e0a030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5127" , 0x1180080e0a038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5128" , 0x1180080e0a040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5129" , 0x1180080e0a048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5130" , 0x1180080e0a050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5131" , 0x1180080e0a058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5132" , 0x1180080e0a060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5133" , 0x1180080e0a068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5134" , 0x1180080e0a070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5135" , 0x1180080e0a078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5136" , 0x1180080e0a080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5137" , 0x1180080e0a088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5138" , 0x1180080e0a090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5139" , 0x1180080e0a098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5140" , 0x1180080e0a0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5141" , 0x1180080e0a0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5142" , 0x1180080e0a0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5143" , 0x1180080e0a0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5144" , 0x1180080e0a0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5145" , 0x1180080e0a0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5146" , 0x1180080e0a0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5147" , 0x1180080e0a0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5148" , 0x1180080e0a0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5149" , 0x1180080e0a0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5150" , 0x1180080e0a0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5151" , 0x1180080e0a0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5152" , 0x1180080e0a100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5153" , 0x1180080e0a108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5154" , 0x1180080e0a110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5155" , 0x1180080e0a118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5156" , 0x1180080e0a120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5157" , 0x1180080e0a128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5158" , 0x1180080e0a130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5159" , 0x1180080e0a138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5160" , 0x1180080e0a140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5161" , 0x1180080e0a148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5162" , 0x1180080e0a150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5163" , 0x1180080e0a158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5164" , 0x1180080e0a160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5165" , 0x1180080e0a168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5166" , 0x1180080e0a170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5167" , 0x1180080e0a178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5168" , 0x1180080e0a180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5169" , 0x1180080e0a188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5170" , 0x1180080e0a190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5171" , 0x1180080e0a198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5172" , 0x1180080e0a1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5173" , 0x1180080e0a1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5174" , 0x1180080e0a1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5175" , 0x1180080e0a1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5176" , 0x1180080e0a1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5177" , 0x1180080e0a1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5178" , 0x1180080e0a1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5179" , 0x1180080e0a1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5180" , 0x1180080e0a1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5181" , 0x1180080e0a1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5182" , 0x1180080e0a1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5183" , 0x1180080e0a1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5184" , 0x1180080e0a200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5185" , 0x1180080e0a208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5186" , 0x1180080e0a210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5187" , 0x1180080e0a218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5188" , 0x1180080e0a220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5189" , 0x1180080e0a228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5190" , 0x1180080e0a230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5191" , 0x1180080e0a238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5192" , 0x1180080e0a240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5193" , 0x1180080e0a248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5194" , 0x1180080e0a250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5195" , 0x1180080e0a258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5196" , 0x1180080e0a260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5197" , 0x1180080e0a268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5198" , 0x1180080e0a270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5199" , 0x1180080e0a278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5200" , 0x1180080e0a280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5201" , 0x1180080e0a288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5202" , 0x1180080e0a290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5203" , 0x1180080e0a298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5204" , 0x1180080e0a2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5205" , 0x1180080e0a2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5206" , 0x1180080e0a2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5207" , 0x1180080e0a2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5208" , 0x1180080e0a2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5209" , 0x1180080e0a2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5210" , 0x1180080e0a2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5211" , 0x1180080e0a2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5212" , 0x1180080e0a2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5213" , 0x1180080e0a2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5214" , 0x1180080e0a2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5215" , 0x1180080e0a2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5216" , 0x1180080e0a300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5217" , 0x1180080e0a308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5218" , 0x1180080e0a310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5219" , 0x1180080e0a318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5220" , 0x1180080e0a320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5221" , 0x1180080e0a328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5222" , 0x1180080e0a330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5223" , 0x1180080e0a338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5224" , 0x1180080e0a340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5225" , 0x1180080e0a348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5226" , 0x1180080e0a350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5227" , 0x1180080e0a358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5228" , 0x1180080e0a360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5229" , 0x1180080e0a368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5230" , 0x1180080e0a370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5231" , 0x1180080e0a378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5232" , 0x1180080e0a380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5233" , 0x1180080e0a388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5234" , 0x1180080e0a390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5235" , 0x1180080e0a398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5236" , 0x1180080e0a3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5237" , 0x1180080e0a3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5238" , 0x1180080e0a3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5239" , 0x1180080e0a3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5240" , 0x1180080e0a3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5241" , 0x1180080e0a3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5242" , 0x1180080e0a3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5243" , 0x1180080e0a3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5244" , 0x1180080e0a3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5245" , 0x1180080e0a3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5246" , 0x1180080e0a3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5247" , 0x1180080e0a3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5248" , 0x1180080e0a400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5249" , 0x1180080e0a408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5250" , 0x1180080e0a410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5251" , 0x1180080e0a418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5252" , 0x1180080e0a420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5253" , 0x1180080e0a428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5254" , 0x1180080e0a430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5255" , 0x1180080e0a438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5256" , 0x1180080e0a440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5257" , 0x1180080e0a448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5258" , 0x1180080e0a450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5259" , 0x1180080e0a458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5260" , 0x1180080e0a460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5261" , 0x1180080e0a468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5262" , 0x1180080e0a470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5263" , 0x1180080e0a478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5264" , 0x1180080e0a480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5265" , 0x1180080e0a488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5266" , 0x1180080e0a490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5267" , 0x1180080e0a498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5268" , 0x1180080e0a4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5269" , 0x1180080e0a4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5270" , 0x1180080e0a4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5271" , 0x1180080e0a4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5272" , 0x1180080e0a4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5273" , 0x1180080e0a4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5274" , 0x1180080e0a4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5275" , 0x1180080e0a4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5276" , 0x1180080e0a4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5277" , 0x1180080e0a4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5278" , 0x1180080e0a4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5279" , 0x1180080e0a4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5280" , 0x1180080e0a500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5281" , 0x1180080e0a508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5282" , 0x1180080e0a510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5283" , 0x1180080e0a518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5284" , 0x1180080e0a520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5285" , 0x1180080e0a528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5286" , 0x1180080e0a530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5287" , 0x1180080e0a538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5288" , 0x1180080e0a540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5289" , 0x1180080e0a548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5290" , 0x1180080e0a550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5291" , 0x1180080e0a558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5292" , 0x1180080e0a560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5293" , 0x1180080e0a568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5294" , 0x1180080e0a570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5295" , 0x1180080e0a578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5296" , 0x1180080e0a580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5297" , 0x1180080e0a588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5298" , 0x1180080e0a590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5299" , 0x1180080e0a598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5300" , 0x1180080e0a5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5301" , 0x1180080e0a5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5302" , 0x1180080e0a5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5303" , 0x1180080e0a5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5304" , 0x1180080e0a5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5305" , 0x1180080e0a5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5306" , 0x1180080e0a5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5307" , 0x1180080e0a5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5308" , 0x1180080e0a5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5309" , 0x1180080e0a5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5310" , 0x1180080e0a5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5311" , 0x1180080e0a5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5312" , 0x1180080e0a600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5313" , 0x1180080e0a608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5314" , 0x1180080e0a610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5315" , 0x1180080e0a618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5316" , 0x1180080e0a620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5317" , 0x1180080e0a628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5318" , 0x1180080e0a630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5319" , 0x1180080e0a638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5320" , 0x1180080e0a640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5321" , 0x1180080e0a648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5322" , 0x1180080e0a650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5323" , 0x1180080e0a658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5324" , 0x1180080e0a660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5325" , 0x1180080e0a668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5326" , 0x1180080e0a670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5327" , 0x1180080e0a678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5328" , 0x1180080e0a680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5329" , 0x1180080e0a688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5330" , 0x1180080e0a690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5331" , 0x1180080e0a698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5332" , 0x1180080e0a6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5333" , 0x1180080e0a6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5334" , 0x1180080e0a6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5335" , 0x1180080e0a6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5336" , 0x1180080e0a6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5337" , 0x1180080e0a6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5338" , 0x1180080e0a6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5339" , 0x1180080e0a6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5340" , 0x1180080e0a6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5341" , 0x1180080e0a6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5342" , 0x1180080e0a6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5343" , 0x1180080e0a6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5344" , 0x1180080e0a700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5345" , 0x1180080e0a708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5346" , 0x1180080e0a710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5347" , 0x1180080e0a718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5348" , 0x1180080e0a720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5349" , 0x1180080e0a728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5350" , 0x1180080e0a730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5351" , 0x1180080e0a738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5352" , 0x1180080e0a740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5353" , 0x1180080e0a748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5354" , 0x1180080e0a750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5355" , 0x1180080e0a758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5356" , 0x1180080e0a760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5357" , 0x1180080e0a768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5358" , 0x1180080e0a770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5359" , 0x1180080e0a778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5360" , 0x1180080e0a780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5361" , 0x1180080e0a788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5362" , 0x1180080e0a790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5363" , 0x1180080e0a798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5364" , 0x1180080e0a7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5365" , 0x1180080e0a7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5366" , 0x1180080e0a7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5367" , 0x1180080e0a7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5368" , 0x1180080e0a7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5369" , 0x1180080e0a7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5370" , 0x1180080e0a7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5371" , 0x1180080e0a7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5372" , 0x1180080e0a7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5373" , 0x1180080e0a7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5374" , 0x1180080e0a7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5375" , 0x1180080e0a7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5376" , 0x1180080e0a800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5377" , 0x1180080e0a808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5378" , 0x1180080e0a810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5379" , 0x1180080e0a818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5380" , 0x1180080e0a820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5381" , 0x1180080e0a828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5382" , 0x1180080e0a830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5383" , 0x1180080e0a838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5384" , 0x1180080e0a840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5385" , 0x1180080e0a848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5386" , 0x1180080e0a850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5387" , 0x1180080e0a858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5388" , 0x1180080e0a860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5389" , 0x1180080e0a868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5390" , 0x1180080e0a870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5391" , 0x1180080e0a878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5392" , 0x1180080e0a880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5393" , 0x1180080e0a888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5394" , 0x1180080e0a890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5395" , 0x1180080e0a898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5396" , 0x1180080e0a8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5397" , 0x1180080e0a8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5398" , 0x1180080e0a8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5399" , 0x1180080e0a8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5400" , 0x1180080e0a8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5401" , 0x1180080e0a8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5402" , 0x1180080e0a8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5403" , 0x1180080e0a8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5404" , 0x1180080e0a8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5405" , 0x1180080e0a8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5406" , 0x1180080e0a8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5407" , 0x1180080e0a8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5408" , 0x1180080e0a900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5409" , 0x1180080e0a908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5410" , 0x1180080e0a910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5411" , 0x1180080e0a918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5412" , 0x1180080e0a920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5413" , 0x1180080e0a928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5414" , 0x1180080e0a930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5415" , 0x1180080e0a938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5416" , 0x1180080e0a940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5417" , 0x1180080e0a948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5418" , 0x1180080e0a950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5419" , 0x1180080e0a958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5420" , 0x1180080e0a960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5421" , 0x1180080e0a968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5422" , 0x1180080e0a970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5423" , 0x1180080e0a978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5424" , 0x1180080e0a980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5425" , 0x1180080e0a988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5426" , 0x1180080e0a990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5427" , 0x1180080e0a998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5428" , 0x1180080e0a9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5429" , 0x1180080e0a9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5430" , 0x1180080e0a9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5431" , 0x1180080e0a9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5432" , 0x1180080e0a9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5433" , 0x1180080e0a9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5434" , 0x1180080e0a9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5435" , 0x1180080e0a9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5436" , 0x1180080e0a9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5437" , 0x1180080e0a9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5438" , 0x1180080e0a9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5439" , 0x1180080e0a9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5440" , 0x1180080e0aa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5441" , 0x1180080e0aa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5442" , 0x1180080e0aa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5443" , 0x1180080e0aa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5444" , 0x1180080e0aa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5445" , 0x1180080e0aa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5446" , 0x1180080e0aa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5447" , 0x1180080e0aa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5448" , 0x1180080e0aa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5449" , 0x1180080e0aa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5450" , 0x1180080e0aa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5451" , 0x1180080e0aa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5452" , 0x1180080e0aa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5453" , 0x1180080e0aa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5454" , 0x1180080e0aa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5455" , 0x1180080e0aa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5456" , 0x1180080e0aa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5457" , 0x1180080e0aa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5458" , 0x1180080e0aa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5459" , 0x1180080e0aa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5460" , 0x1180080e0aaa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5461" , 0x1180080e0aaa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5462" , 0x1180080e0aab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5463" , 0x1180080e0aab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5464" , 0x1180080e0aac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5465" , 0x1180080e0aac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5466" , 0x1180080e0aad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5467" , 0x1180080e0aad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5468" , 0x1180080e0aae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5469" , 0x1180080e0aae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5470" , 0x1180080e0aaf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5471" , 0x1180080e0aaf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5472" , 0x1180080e0ab00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5473" , 0x1180080e0ab08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5474" , 0x1180080e0ab10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5475" , 0x1180080e0ab18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5476" , 0x1180080e0ab20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5477" , 0x1180080e0ab28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5478" , 0x1180080e0ab30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5479" , 0x1180080e0ab38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5480" , 0x1180080e0ab40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5481" , 0x1180080e0ab48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5482" , 0x1180080e0ab50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5483" , 0x1180080e0ab58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5484" , 0x1180080e0ab60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5485" , 0x1180080e0ab68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5486" , 0x1180080e0ab70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5487" , 0x1180080e0ab78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5488" , 0x1180080e0ab80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5489" , 0x1180080e0ab88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5490" , 0x1180080e0ab90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5491" , 0x1180080e0ab98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5492" , 0x1180080e0aba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5493" , 0x1180080e0aba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5494" , 0x1180080e0abb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5495" , 0x1180080e0abb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5496" , 0x1180080e0abc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5497" , 0x1180080e0abc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5498" , 0x1180080e0abd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5499" , 0x1180080e0abd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5500" , 0x1180080e0abe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5501" , 0x1180080e0abe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5502" , 0x1180080e0abf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5503" , 0x1180080e0abf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5504" , 0x1180080e0ac00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5505" , 0x1180080e0ac08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5506" , 0x1180080e0ac10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5507" , 0x1180080e0ac18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5508" , 0x1180080e0ac20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5509" , 0x1180080e0ac28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5510" , 0x1180080e0ac30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5511" , 0x1180080e0ac38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5512" , 0x1180080e0ac40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5513" , 0x1180080e0ac48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5514" , 0x1180080e0ac50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5515" , 0x1180080e0ac58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5516" , 0x1180080e0ac60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5517" , 0x1180080e0ac68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5518" , 0x1180080e0ac70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5519" , 0x1180080e0ac78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5520" , 0x1180080e0ac80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5521" , 0x1180080e0ac88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5522" , 0x1180080e0ac90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5523" , 0x1180080e0ac98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5524" , 0x1180080e0aca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5525" , 0x1180080e0aca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5526" , 0x1180080e0acb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5527" , 0x1180080e0acb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5528" , 0x1180080e0acc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5529" , 0x1180080e0acc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5530" , 0x1180080e0acd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5531" , 0x1180080e0acd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5532" , 0x1180080e0ace0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5533" , 0x1180080e0ace8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5534" , 0x1180080e0acf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5535" , 0x1180080e0acf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5536" , 0x1180080e0ad00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5537" , 0x1180080e0ad08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5538" , 0x1180080e0ad10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5539" , 0x1180080e0ad18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5540" , 0x1180080e0ad20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5541" , 0x1180080e0ad28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5542" , 0x1180080e0ad30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5543" , 0x1180080e0ad38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5544" , 0x1180080e0ad40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5545" , 0x1180080e0ad48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5546" , 0x1180080e0ad50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5547" , 0x1180080e0ad58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5548" , 0x1180080e0ad60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5549" , 0x1180080e0ad68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5550" , 0x1180080e0ad70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5551" , 0x1180080e0ad78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5552" , 0x1180080e0ad80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5553" , 0x1180080e0ad88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5554" , 0x1180080e0ad90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5555" , 0x1180080e0ad98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5556" , 0x1180080e0ada0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5557" , 0x1180080e0ada8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5558" , 0x1180080e0adb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5559" , 0x1180080e0adb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5560" , 0x1180080e0adc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5561" , 0x1180080e0adc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5562" , 0x1180080e0add0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5563" , 0x1180080e0add8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5564" , 0x1180080e0ade0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5565" , 0x1180080e0ade8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5566" , 0x1180080e0adf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5567" , 0x1180080e0adf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5568" , 0x1180080e0ae00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5569" , 0x1180080e0ae08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5570" , 0x1180080e0ae10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5571" , 0x1180080e0ae18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5572" , 0x1180080e0ae20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5573" , 0x1180080e0ae28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5574" , 0x1180080e0ae30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5575" , 0x1180080e0ae38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5576" , 0x1180080e0ae40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5577" , 0x1180080e0ae48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5578" , 0x1180080e0ae50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5579" , 0x1180080e0ae58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5580" , 0x1180080e0ae60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5581" , 0x1180080e0ae68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5582" , 0x1180080e0ae70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5583" , 0x1180080e0ae78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5584" , 0x1180080e0ae80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5585" , 0x1180080e0ae88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5586" , 0x1180080e0ae90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5587" , 0x1180080e0ae98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5588" , 0x1180080e0aea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5589" , 0x1180080e0aea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5590" , 0x1180080e0aeb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5591" , 0x1180080e0aeb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5592" , 0x1180080e0aec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5593" , 0x1180080e0aec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5594" , 0x1180080e0aed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5595" , 0x1180080e0aed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5596" , 0x1180080e0aee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5597" , 0x1180080e0aee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5598" , 0x1180080e0aef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5599" , 0x1180080e0aef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5600" , 0x1180080e0af00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5601" , 0x1180080e0af08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5602" , 0x1180080e0af10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5603" , 0x1180080e0af18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5604" , 0x1180080e0af20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5605" , 0x1180080e0af28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5606" , 0x1180080e0af30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5607" , 0x1180080e0af38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5608" , 0x1180080e0af40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5609" , 0x1180080e0af48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5610" , 0x1180080e0af50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5611" , 0x1180080e0af58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5612" , 0x1180080e0af60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5613" , 0x1180080e0af68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5614" , 0x1180080e0af70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5615" , 0x1180080e0af78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5616" , 0x1180080e0af80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5617" , 0x1180080e0af88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5618" , 0x1180080e0af90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5619" , 0x1180080e0af98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5620" , 0x1180080e0afa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5621" , 0x1180080e0afa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5622" , 0x1180080e0afb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5623" , 0x1180080e0afb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5624" , 0x1180080e0afc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5625" , 0x1180080e0afc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5626" , 0x1180080e0afd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5627" , 0x1180080e0afd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5628" , 0x1180080e0afe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5629" , 0x1180080e0afe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5630" , 0x1180080e0aff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5631" , 0x1180080e0aff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5632" , 0x1180080e0b000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5633" , 0x1180080e0b008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5634" , 0x1180080e0b010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5635" , 0x1180080e0b018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5636" , 0x1180080e0b020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5637" , 0x1180080e0b028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5638" , 0x1180080e0b030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5639" , 0x1180080e0b038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5640" , 0x1180080e0b040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5641" , 0x1180080e0b048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5642" , 0x1180080e0b050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5643" , 0x1180080e0b058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5644" , 0x1180080e0b060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5645" , 0x1180080e0b068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5646" , 0x1180080e0b070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5647" , 0x1180080e0b078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5648" , 0x1180080e0b080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5649" , 0x1180080e0b088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5650" , 0x1180080e0b090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5651" , 0x1180080e0b098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5652" , 0x1180080e0b0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5653" , 0x1180080e0b0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5654" , 0x1180080e0b0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5655" , 0x1180080e0b0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5656" , 0x1180080e0b0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5657" , 0x1180080e0b0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5658" , 0x1180080e0b0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5659" , 0x1180080e0b0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5660" , 0x1180080e0b0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5661" , 0x1180080e0b0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5662" , 0x1180080e0b0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5663" , 0x1180080e0b0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5664" , 0x1180080e0b100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5665" , 0x1180080e0b108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5666" , 0x1180080e0b110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5667" , 0x1180080e0b118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5668" , 0x1180080e0b120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5669" , 0x1180080e0b128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5670" , 0x1180080e0b130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5671" , 0x1180080e0b138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5672" , 0x1180080e0b140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5673" , 0x1180080e0b148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5674" , 0x1180080e0b150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5675" , 0x1180080e0b158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5676" , 0x1180080e0b160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5677" , 0x1180080e0b168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5678" , 0x1180080e0b170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5679" , 0x1180080e0b178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5680" , 0x1180080e0b180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5681" , 0x1180080e0b188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5682" , 0x1180080e0b190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5683" , 0x1180080e0b198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5684" , 0x1180080e0b1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5685" , 0x1180080e0b1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5686" , 0x1180080e0b1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5687" , 0x1180080e0b1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5688" , 0x1180080e0b1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5689" , 0x1180080e0b1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5690" , 0x1180080e0b1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5691" , 0x1180080e0b1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5692" , 0x1180080e0b1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5693" , 0x1180080e0b1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5694" , 0x1180080e0b1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5695" , 0x1180080e0b1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5696" , 0x1180080e0b200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5697" , 0x1180080e0b208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5698" , 0x1180080e0b210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5699" , 0x1180080e0b218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5700" , 0x1180080e0b220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5701" , 0x1180080e0b228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5702" , 0x1180080e0b230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5703" , 0x1180080e0b238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5704" , 0x1180080e0b240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5705" , 0x1180080e0b248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5706" , 0x1180080e0b250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5707" , 0x1180080e0b258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5708" , 0x1180080e0b260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5709" , 0x1180080e0b268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5710" , 0x1180080e0b270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5711" , 0x1180080e0b278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5712" , 0x1180080e0b280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5713" , 0x1180080e0b288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5714" , 0x1180080e0b290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5715" , 0x1180080e0b298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5716" , 0x1180080e0b2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5717" , 0x1180080e0b2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5718" , 0x1180080e0b2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5719" , 0x1180080e0b2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5720" , 0x1180080e0b2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5721" , 0x1180080e0b2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5722" , 0x1180080e0b2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5723" , 0x1180080e0b2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5724" , 0x1180080e0b2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5725" , 0x1180080e0b2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5726" , 0x1180080e0b2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5727" , 0x1180080e0b2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5728" , 0x1180080e0b300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5729" , 0x1180080e0b308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5730" , 0x1180080e0b310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5731" , 0x1180080e0b318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5732" , 0x1180080e0b320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5733" , 0x1180080e0b328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5734" , 0x1180080e0b330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5735" , 0x1180080e0b338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5736" , 0x1180080e0b340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5737" , 0x1180080e0b348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5738" , 0x1180080e0b350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5739" , 0x1180080e0b358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5740" , 0x1180080e0b360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5741" , 0x1180080e0b368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5742" , 0x1180080e0b370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5743" , 0x1180080e0b378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5744" , 0x1180080e0b380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5745" , 0x1180080e0b388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5746" , 0x1180080e0b390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5747" , 0x1180080e0b398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5748" , 0x1180080e0b3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5749" , 0x1180080e0b3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5750" , 0x1180080e0b3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5751" , 0x1180080e0b3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5752" , 0x1180080e0b3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5753" , 0x1180080e0b3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5754" , 0x1180080e0b3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5755" , 0x1180080e0b3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5756" , 0x1180080e0b3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5757" , 0x1180080e0b3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5758" , 0x1180080e0b3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5759" , 0x1180080e0b3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5760" , 0x1180080e0b400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5761" , 0x1180080e0b408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5762" , 0x1180080e0b410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5763" , 0x1180080e0b418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5764" , 0x1180080e0b420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5765" , 0x1180080e0b428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5766" , 0x1180080e0b430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5767" , 0x1180080e0b438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5768" , 0x1180080e0b440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5769" , 0x1180080e0b448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5770" , 0x1180080e0b450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5771" , 0x1180080e0b458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5772" , 0x1180080e0b460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5773" , 0x1180080e0b468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5774" , 0x1180080e0b470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5775" , 0x1180080e0b478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5776" , 0x1180080e0b480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5777" , 0x1180080e0b488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5778" , 0x1180080e0b490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5779" , 0x1180080e0b498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5780" , 0x1180080e0b4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5781" , 0x1180080e0b4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5782" , 0x1180080e0b4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5783" , 0x1180080e0b4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5784" , 0x1180080e0b4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5785" , 0x1180080e0b4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5786" , 0x1180080e0b4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5787" , 0x1180080e0b4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5788" , 0x1180080e0b4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5789" , 0x1180080e0b4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5790" , 0x1180080e0b4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5791" , 0x1180080e0b4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5792" , 0x1180080e0b500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5793" , 0x1180080e0b508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5794" , 0x1180080e0b510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5795" , 0x1180080e0b518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5796" , 0x1180080e0b520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5797" , 0x1180080e0b528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5798" , 0x1180080e0b530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5799" , 0x1180080e0b538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5800" , 0x1180080e0b540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5801" , 0x1180080e0b548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5802" , 0x1180080e0b550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5803" , 0x1180080e0b558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5804" , 0x1180080e0b560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5805" , 0x1180080e0b568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5806" , 0x1180080e0b570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5807" , 0x1180080e0b578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5808" , 0x1180080e0b580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5809" , 0x1180080e0b588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5810" , 0x1180080e0b590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5811" , 0x1180080e0b598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5812" , 0x1180080e0b5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5813" , 0x1180080e0b5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5814" , 0x1180080e0b5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5815" , 0x1180080e0b5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5816" , 0x1180080e0b5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5817" , 0x1180080e0b5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5818" , 0x1180080e0b5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5819" , 0x1180080e0b5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5820" , 0x1180080e0b5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5821" , 0x1180080e0b5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5822" , 0x1180080e0b5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5823" , 0x1180080e0b5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5824" , 0x1180080e0b600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5825" , 0x1180080e0b608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5826" , 0x1180080e0b610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5827" , 0x1180080e0b618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5828" , 0x1180080e0b620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5829" , 0x1180080e0b628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5830" , 0x1180080e0b630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5831" , 0x1180080e0b638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5832" , 0x1180080e0b640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5833" , 0x1180080e0b648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5834" , 0x1180080e0b650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5835" , 0x1180080e0b658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5836" , 0x1180080e0b660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5837" , 0x1180080e0b668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5838" , 0x1180080e0b670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5839" , 0x1180080e0b678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5840" , 0x1180080e0b680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5841" , 0x1180080e0b688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5842" , 0x1180080e0b690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5843" , 0x1180080e0b698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5844" , 0x1180080e0b6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5845" , 0x1180080e0b6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5846" , 0x1180080e0b6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5847" , 0x1180080e0b6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5848" , 0x1180080e0b6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5849" , 0x1180080e0b6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5850" , 0x1180080e0b6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5851" , 0x1180080e0b6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5852" , 0x1180080e0b6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5853" , 0x1180080e0b6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5854" , 0x1180080e0b6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5855" , 0x1180080e0b6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5856" , 0x1180080e0b700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5857" , 0x1180080e0b708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5858" , 0x1180080e0b710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5859" , 0x1180080e0b718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5860" , 0x1180080e0b720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5861" , 0x1180080e0b728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5862" , 0x1180080e0b730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5863" , 0x1180080e0b738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5864" , 0x1180080e0b740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5865" , 0x1180080e0b748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5866" , 0x1180080e0b750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5867" , 0x1180080e0b758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5868" , 0x1180080e0b760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5869" , 0x1180080e0b768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5870" , 0x1180080e0b770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5871" , 0x1180080e0b778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5872" , 0x1180080e0b780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5873" , 0x1180080e0b788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5874" , 0x1180080e0b790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5875" , 0x1180080e0b798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5876" , 0x1180080e0b7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5877" , 0x1180080e0b7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5878" , 0x1180080e0b7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5879" , 0x1180080e0b7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5880" , 0x1180080e0b7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5881" , 0x1180080e0b7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5882" , 0x1180080e0b7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5883" , 0x1180080e0b7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5884" , 0x1180080e0b7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5885" , 0x1180080e0b7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5886" , 0x1180080e0b7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5887" , 0x1180080e0b7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5888" , 0x1180080e0b800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5889" , 0x1180080e0b808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5890" , 0x1180080e0b810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5891" , 0x1180080e0b818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5892" , 0x1180080e0b820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5893" , 0x1180080e0b828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5894" , 0x1180080e0b830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5895" , 0x1180080e0b838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5896" , 0x1180080e0b840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5897" , 0x1180080e0b848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5898" , 0x1180080e0b850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5899" , 0x1180080e0b858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5900" , 0x1180080e0b860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5901" , 0x1180080e0b868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5902" , 0x1180080e0b870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5903" , 0x1180080e0b878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5904" , 0x1180080e0b880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5905" , 0x1180080e0b888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5906" , 0x1180080e0b890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5907" , 0x1180080e0b898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5908" , 0x1180080e0b8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5909" , 0x1180080e0b8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5910" , 0x1180080e0b8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5911" , 0x1180080e0b8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5912" , 0x1180080e0b8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5913" , 0x1180080e0b8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5914" , 0x1180080e0b8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5915" , 0x1180080e0b8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5916" , 0x1180080e0b8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5917" , 0x1180080e0b8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5918" , 0x1180080e0b8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5919" , 0x1180080e0b8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5920" , 0x1180080e0b900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5921" , 0x1180080e0b908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5922" , 0x1180080e0b910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5923" , 0x1180080e0b918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5924" , 0x1180080e0b920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5925" , 0x1180080e0b928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5926" , 0x1180080e0b930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5927" , 0x1180080e0b938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5928" , 0x1180080e0b940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5929" , 0x1180080e0b948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5930" , 0x1180080e0b950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5931" , 0x1180080e0b958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5932" , 0x1180080e0b960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5933" , 0x1180080e0b968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5934" , 0x1180080e0b970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5935" , 0x1180080e0b978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5936" , 0x1180080e0b980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5937" , 0x1180080e0b988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5938" , 0x1180080e0b990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5939" , 0x1180080e0b998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5940" , 0x1180080e0b9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5941" , 0x1180080e0b9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5942" , 0x1180080e0b9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5943" , 0x1180080e0b9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5944" , 0x1180080e0b9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5945" , 0x1180080e0b9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5946" , 0x1180080e0b9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5947" , 0x1180080e0b9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5948" , 0x1180080e0b9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5949" , 0x1180080e0b9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5950" , 0x1180080e0b9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5951" , 0x1180080e0b9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5952" , 0x1180080e0ba00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5953" , 0x1180080e0ba08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5954" , 0x1180080e0ba10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5955" , 0x1180080e0ba18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5956" , 0x1180080e0ba20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5957" , 0x1180080e0ba28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5958" , 0x1180080e0ba30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5959" , 0x1180080e0ba38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5960" , 0x1180080e0ba40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5961" , 0x1180080e0ba48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5962" , 0x1180080e0ba50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5963" , 0x1180080e0ba58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5964" , 0x1180080e0ba60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5965" , 0x1180080e0ba68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5966" , 0x1180080e0ba70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5967" , 0x1180080e0ba78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5968" , 0x1180080e0ba80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5969" , 0x1180080e0ba88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5970" , 0x1180080e0ba90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5971" , 0x1180080e0ba98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5972" , 0x1180080e0baa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5973" , 0x1180080e0baa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5974" , 0x1180080e0bab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5975" , 0x1180080e0bab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5976" , 0x1180080e0bac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5977" , 0x1180080e0bac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5978" , 0x1180080e0bad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5979" , 0x1180080e0bad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5980" , 0x1180080e0bae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5981" , 0x1180080e0bae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5982" , 0x1180080e0baf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5983" , 0x1180080e0baf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5984" , 0x1180080e0bb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5985" , 0x1180080e0bb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5986" , 0x1180080e0bb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5987" , 0x1180080e0bb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5988" , 0x1180080e0bb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5989" , 0x1180080e0bb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5990" , 0x1180080e0bb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5991" , 0x1180080e0bb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5992" , 0x1180080e0bb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5993" , 0x1180080e0bb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5994" , 0x1180080e0bb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5995" , 0x1180080e0bb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5996" , 0x1180080e0bb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5997" , 0x1180080e0bb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5998" , 0x1180080e0bb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP5999" , 0x1180080e0bb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6000" , 0x1180080e0bb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6001" , 0x1180080e0bb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6002" , 0x1180080e0bb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6003" , 0x1180080e0bb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6004" , 0x1180080e0bba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6005" , 0x1180080e0bba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6006" , 0x1180080e0bbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6007" , 0x1180080e0bbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6008" , 0x1180080e0bbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6009" , 0x1180080e0bbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6010" , 0x1180080e0bbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6011" , 0x1180080e0bbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6012" , 0x1180080e0bbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6013" , 0x1180080e0bbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6014" , 0x1180080e0bbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6015" , 0x1180080e0bbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6016" , 0x1180080e0bc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6017" , 0x1180080e0bc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6018" , 0x1180080e0bc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6019" , 0x1180080e0bc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6020" , 0x1180080e0bc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6021" , 0x1180080e0bc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6022" , 0x1180080e0bc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6023" , 0x1180080e0bc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6024" , 0x1180080e0bc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6025" , 0x1180080e0bc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6026" , 0x1180080e0bc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6027" , 0x1180080e0bc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6028" , 0x1180080e0bc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6029" , 0x1180080e0bc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6030" , 0x1180080e0bc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6031" , 0x1180080e0bc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6032" , 0x1180080e0bc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6033" , 0x1180080e0bc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6034" , 0x1180080e0bc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6035" , 0x1180080e0bc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6036" , 0x1180080e0bca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6037" , 0x1180080e0bca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6038" , 0x1180080e0bcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6039" , 0x1180080e0bcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6040" , 0x1180080e0bcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6041" , 0x1180080e0bcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6042" , 0x1180080e0bcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6043" , 0x1180080e0bcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6044" , 0x1180080e0bce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6045" , 0x1180080e0bce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6046" , 0x1180080e0bcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6047" , 0x1180080e0bcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6048" , 0x1180080e0bd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6049" , 0x1180080e0bd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6050" , 0x1180080e0bd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6051" , 0x1180080e0bd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6052" , 0x1180080e0bd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6053" , 0x1180080e0bd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6054" , 0x1180080e0bd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6055" , 0x1180080e0bd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6056" , 0x1180080e0bd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6057" , 0x1180080e0bd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6058" , 0x1180080e0bd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6059" , 0x1180080e0bd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6060" , 0x1180080e0bd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6061" , 0x1180080e0bd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6062" , 0x1180080e0bd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6063" , 0x1180080e0bd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6064" , 0x1180080e0bd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6065" , 0x1180080e0bd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6066" , 0x1180080e0bd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6067" , 0x1180080e0bd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6068" , 0x1180080e0bda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6069" , 0x1180080e0bda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6070" , 0x1180080e0bdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6071" , 0x1180080e0bdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6072" , 0x1180080e0bdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6073" , 0x1180080e0bdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6074" , 0x1180080e0bdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6075" , 0x1180080e0bdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6076" , 0x1180080e0bde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6077" , 0x1180080e0bde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6078" , 0x1180080e0bdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6079" , 0x1180080e0bdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6080" , 0x1180080e0be00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6081" , 0x1180080e0be08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6082" , 0x1180080e0be10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6083" , 0x1180080e0be18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6084" , 0x1180080e0be20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6085" , 0x1180080e0be28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6086" , 0x1180080e0be30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6087" , 0x1180080e0be38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6088" , 0x1180080e0be40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6089" , 0x1180080e0be48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6090" , 0x1180080e0be50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6091" , 0x1180080e0be58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6092" , 0x1180080e0be60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6093" , 0x1180080e0be68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6094" , 0x1180080e0be70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6095" , 0x1180080e0be78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6096" , 0x1180080e0be80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6097" , 0x1180080e0be88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6098" , 0x1180080e0be90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6099" , 0x1180080e0be98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6100" , 0x1180080e0bea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6101" , 0x1180080e0bea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6102" , 0x1180080e0beb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6103" , 0x1180080e0beb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6104" , 0x1180080e0bec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6105" , 0x1180080e0bec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6106" , 0x1180080e0bed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6107" , 0x1180080e0bed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6108" , 0x1180080e0bee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6109" , 0x1180080e0bee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6110" , 0x1180080e0bef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6111" , 0x1180080e0bef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6112" , 0x1180080e0bf00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6113" , 0x1180080e0bf08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6114" , 0x1180080e0bf10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6115" , 0x1180080e0bf18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6116" , 0x1180080e0bf20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6117" , 0x1180080e0bf28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6118" , 0x1180080e0bf30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6119" , 0x1180080e0bf38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6120" , 0x1180080e0bf40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6121" , 0x1180080e0bf48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6122" , 0x1180080e0bf50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6123" , 0x1180080e0bf58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6124" , 0x1180080e0bf60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6125" , 0x1180080e0bf68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6126" , 0x1180080e0bf70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6127" , 0x1180080e0bf78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6128" , 0x1180080e0bf80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6129" , 0x1180080e0bf88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6130" , 0x1180080e0bf90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6131" , 0x1180080e0bf98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6132" , 0x1180080e0bfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6133" , 0x1180080e0bfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6134" , 0x1180080e0bfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6135" , 0x1180080e0bfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6136" , 0x1180080e0bfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6137" , 0x1180080e0bfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6138" , 0x1180080e0bfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6139" , 0x1180080e0bfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6140" , 0x1180080e0bfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6141" , 0x1180080e0bfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6142" , 0x1180080e0bff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6143" , 0x1180080e0bff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6144" , 0x1180080e0c000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6145" , 0x1180080e0c008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6146" , 0x1180080e0c010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6147" , 0x1180080e0c018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6148" , 0x1180080e0c020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6149" , 0x1180080e0c028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6150" , 0x1180080e0c030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6151" , 0x1180080e0c038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6152" , 0x1180080e0c040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6153" , 0x1180080e0c048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6154" , 0x1180080e0c050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6155" , 0x1180080e0c058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6156" , 0x1180080e0c060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6157" , 0x1180080e0c068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6158" , 0x1180080e0c070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6159" , 0x1180080e0c078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6160" , 0x1180080e0c080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6161" , 0x1180080e0c088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6162" , 0x1180080e0c090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6163" , 0x1180080e0c098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6164" , 0x1180080e0c0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6165" , 0x1180080e0c0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6166" , 0x1180080e0c0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6167" , 0x1180080e0c0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6168" , 0x1180080e0c0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6169" , 0x1180080e0c0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6170" , 0x1180080e0c0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6171" , 0x1180080e0c0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6172" , 0x1180080e0c0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6173" , 0x1180080e0c0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6174" , 0x1180080e0c0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6175" , 0x1180080e0c0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6176" , 0x1180080e0c100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6177" , 0x1180080e0c108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6178" , 0x1180080e0c110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6179" , 0x1180080e0c118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6180" , 0x1180080e0c120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6181" , 0x1180080e0c128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6182" , 0x1180080e0c130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6183" , 0x1180080e0c138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6184" , 0x1180080e0c140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6185" , 0x1180080e0c148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6186" , 0x1180080e0c150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6187" , 0x1180080e0c158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6188" , 0x1180080e0c160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6189" , 0x1180080e0c168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6190" , 0x1180080e0c170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6191" , 0x1180080e0c178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6192" , 0x1180080e0c180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6193" , 0x1180080e0c188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6194" , 0x1180080e0c190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6195" , 0x1180080e0c198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6196" , 0x1180080e0c1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6197" , 0x1180080e0c1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6198" , 0x1180080e0c1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6199" , 0x1180080e0c1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6200" , 0x1180080e0c1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6201" , 0x1180080e0c1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6202" , 0x1180080e0c1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6203" , 0x1180080e0c1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6204" , 0x1180080e0c1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6205" , 0x1180080e0c1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6206" , 0x1180080e0c1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6207" , 0x1180080e0c1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6208" , 0x1180080e0c200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6209" , 0x1180080e0c208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6210" , 0x1180080e0c210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6211" , 0x1180080e0c218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6212" , 0x1180080e0c220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6213" , 0x1180080e0c228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6214" , 0x1180080e0c230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6215" , 0x1180080e0c238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6216" , 0x1180080e0c240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6217" , 0x1180080e0c248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6218" , 0x1180080e0c250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6219" , 0x1180080e0c258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6220" , 0x1180080e0c260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6221" , 0x1180080e0c268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6222" , 0x1180080e0c270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6223" , 0x1180080e0c278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6224" , 0x1180080e0c280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6225" , 0x1180080e0c288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6226" , 0x1180080e0c290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6227" , 0x1180080e0c298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6228" , 0x1180080e0c2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6229" , 0x1180080e0c2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6230" , 0x1180080e0c2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6231" , 0x1180080e0c2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6232" , 0x1180080e0c2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6233" , 0x1180080e0c2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6234" , 0x1180080e0c2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6235" , 0x1180080e0c2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6236" , 0x1180080e0c2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6237" , 0x1180080e0c2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6238" , 0x1180080e0c2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6239" , 0x1180080e0c2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6240" , 0x1180080e0c300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6241" , 0x1180080e0c308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6242" , 0x1180080e0c310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6243" , 0x1180080e0c318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6244" , 0x1180080e0c320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6245" , 0x1180080e0c328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6246" , 0x1180080e0c330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6247" , 0x1180080e0c338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6248" , 0x1180080e0c340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6249" , 0x1180080e0c348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6250" , 0x1180080e0c350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6251" , 0x1180080e0c358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6252" , 0x1180080e0c360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6253" , 0x1180080e0c368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6254" , 0x1180080e0c370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6255" , 0x1180080e0c378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6256" , 0x1180080e0c380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6257" , 0x1180080e0c388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6258" , 0x1180080e0c390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6259" , 0x1180080e0c398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6260" , 0x1180080e0c3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6261" , 0x1180080e0c3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6262" , 0x1180080e0c3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6263" , 0x1180080e0c3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6264" , 0x1180080e0c3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6265" , 0x1180080e0c3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6266" , 0x1180080e0c3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6267" , 0x1180080e0c3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6268" , 0x1180080e0c3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6269" , 0x1180080e0c3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6270" , 0x1180080e0c3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6271" , 0x1180080e0c3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6272" , 0x1180080e0c400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6273" , 0x1180080e0c408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6274" , 0x1180080e0c410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6275" , 0x1180080e0c418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6276" , 0x1180080e0c420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6277" , 0x1180080e0c428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6278" , 0x1180080e0c430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6279" , 0x1180080e0c438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6280" , 0x1180080e0c440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6281" , 0x1180080e0c448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6282" , 0x1180080e0c450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6283" , 0x1180080e0c458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6284" , 0x1180080e0c460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6285" , 0x1180080e0c468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6286" , 0x1180080e0c470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6287" , 0x1180080e0c478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6288" , 0x1180080e0c480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6289" , 0x1180080e0c488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6290" , 0x1180080e0c490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6291" , 0x1180080e0c498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6292" , 0x1180080e0c4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6293" , 0x1180080e0c4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6294" , 0x1180080e0c4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6295" , 0x1180080e0c4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6296" , 0x1180080e0c4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6297" , 0x1180080e0c4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6298" , 0x1180080e0c4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6299" , 0x1180080e0c4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6300" , 0x1180080e0c4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6301" , 0x1180080e0c4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6302" , 0x1180080e0c4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6303" , 0x1180080e0c4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6304" , 0x1180080e0c500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6305" , 0x1180080e0c508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6306" , 0x1180080e0c510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6307" , 0x1180080e0c518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6308" , 0x1180080e0c520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6309" , 0x1180080e0c528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6310" , 0x1180080e0c530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6311" , 0x1180080e0c538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6312" , 0x1180080e0c540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6313" , 0x1180080e0c548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6314" , 0x1180080e0c550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6315" , 0x1180080e0c558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6316" , 0x1180080e0c560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6317" , 0x1180080e0c568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6318" , 0x1180080e0c570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6319" , 0x1180080e0c578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6320" , 0x1180080e0c580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6321" , 0x1180080e0c588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6322" , 0x1180080e0c590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6323" , 0x1180080e0c598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6324" , 0x1180080e0c5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6325" , 0x1180080e0c5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6326" , 0x1180080e0c5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6327" , 0x1180080e0c5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6328" , 0x1180080e0c5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6329" , 0x1180080e0c5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6330" , 0x1180080e0c5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6331" , 0x1180080e0c5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6332" , 0x1180080e0c5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6333" , 0x1180080e0c5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6334" , 0x1180080e0c5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6335" , 0x1180080e0c5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6336" , 0x1180080e0c600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6337" , 0x1180080e0c608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6338" , 0x1180080e0c610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6339" , 0x1180080e0c618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6340" , 0x1180080e0c620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6341" , 0x1180080e0c628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6342" , 0x1180080e0c630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6343" , 0x1180080e0c638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6344" , 0x1180080e0c640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6345" , 0x1180080e0c648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6346" , 0x1180080e0c650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6347" , 0x1180080e0c658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6348" , 0x1180080e0c660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6349" , 0x1180080e0c668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6350" , 0x1180080e0c670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6351" , 0x1180080e0c678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6352" , 0x1180080e0c680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6353" , 0x1180080e0c688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6354" , 0x1180080e0c690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6355" , 0x1180080e0c698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6356" , 0x1180080e0c6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6357" , 0x1180080e0c6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6358" , 0x1180080e0c6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6359" , 0x1180080e0c6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6360" , 0x1180080e0c6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6361" , 0x1180080e0c6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6362" , 0x1180080e0c6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6363" , 0x1180080e0c6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6364" , 0x1180080e0c6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6365" , 0x1180080e0c6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6366" , 0x1180080e0c6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6367" , 0x1180080e0c6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6368" , 0x1180080e0c700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6369" , 0x1180080e0c708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6370" , 0x1180080e0c710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6371" , 0x1180080e0c718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6372" , 0x1180080e0c720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6373" , 0x1180080e0c728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6374" , 0x1180080e0c730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6375" , 0x1180080e0c738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6376" , 0x1180080e0c740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6377" , 0x1180080e0c748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6378" , 0x1180080e0c750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6379" , 0x1180080e0c758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6380" , 0x1180080e0c760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6381" , 0x1180080e0c768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6382" , 0x1180080e0c770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6383" , 0x1180080e0c778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6384" , 0x1180080e0c780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6385" , 0x1180080e0c788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6386" , 0x1180080e0c790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6387" , 0x1180080e0c798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6388" , 0x1180080e0c7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6389" , 0x1180080e0c7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6390" , 0x1180080e0c7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6391" , 0x1180080e0c7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6392" , 0x1180080e0c7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6393" , 0x1180080e0c7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6394" , 0x1180080e0c7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6395" , 0x1180080e0c7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6396" , 0x1180080e0c7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6397" , 0x1180080e0c7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6398" , 0x1180080e0c7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6399" , 0x1180080e0c7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6400" , 0x1180080e0c800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6401" , 0x1180080e0c808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6402" , 0x1180080e0c810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6403" , 0x1180080e0c818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6404" , 0x1180080e0c820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6405" , 0x1180080e0c828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6406" , 0x1180080e0c830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6407" , 0x1180080e0c838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6408" , 0x1180080e0c840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6409" , 0x1180080e0c848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6410" , 0x1180080e0c850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6411" , 0x1180080e0c858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6412" , 0x1180080e0c860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6413" , 0x1180080e0c868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6414" , 0x1180080e0c870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6415" , 0x1180080e0c878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6416" , 0x1180080e0c880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6417" , 0x1180080e0c888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6418" , 0x1180080e0c890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6419" , 0x1180080e0c898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6420" , 0x1180080e0c8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6421" , 0x1180080e0c8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6422" , 0x1180080e0c8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6423" , 0x1180080e0c8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6424" , 0x1180080e0c8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6425" , 0x1180080e0c8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6426" , 0x1180080e0c8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6427" , 0x1180080e0c8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6428" , 0x1180080e0c8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6429" , 0x1180080e0c8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6430" , 0x1180080e0c8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6431" , 0x1180080e0c8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6432" , 0x1180080e0c900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6433" , 0x1180080e0c908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6434" , 0x1180080e0c910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6435" , 0x1180080e0c918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6436" , 0x1180080e0c920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6437" , 0x1180080e0c928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6438" , 0x1180080e0c930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6439" , 0x1180080e0c938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6440" , 0x1180080e0c940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6441" , 0x1180080e0c948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6442" , 0x1180080e0c950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6443" , 0x1180080e0c958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6444" , 0x1180080e0c960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6445" , 0x1180080e0c968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6446" , 0x1180080e0c970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6447" , 0x1180080e0c978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6448" , 0x1180080e0c980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6449" , 0x1180080e0c988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6450" , 0x1180080e0c990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6451" , 0x1180080e0c998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6452" , 0x1180080e0c9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6453" , 0x1180080e0c9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6454" , 0x1180080e0c9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6455" , 0x1180080e0c9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6456" , 0x1180080e0c9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6457" , 0x1180080e0c9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6458" , 0x1180080e0c9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6459" , 0x1180080e0c9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6460" , 0x1180080e0c9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6461" , 0x1180080e0c9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6462" , 0x1180080e0c9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6463" , 0x1180080e0c9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6464" , 0x1180080e0ca00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6465" , 0x1180080e0ca08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6466" , 0x1180080e0ca10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6467" , 0x1180080e0ca18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6468" , 0x1180080e0ca20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6469" , 0x1180080e0ca28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6470" , 0x1180080e0ca30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6471" , 0x1180080e0ca38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6472" , 0x1180080e0ca40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6473" , 0x1180080e0ca48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6474" , 0x1180080e0ca50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6475" , 0x1180080e0ca58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6476" , 0x1180080e0ca60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6477" , 0x1180080e0ca68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6478" , 0x1180080e0ca70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6479" , 0x1180080e0ca78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6480" , 0x1180080e0ca80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6481" , 0x1180080e0ca88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6482" , 0x1180080e0ca90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6483" , 0x1180080e0ca98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6484" , 0x1180080e0caa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6485" , 0x1180080e0caa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6486" , 0x1180080e0cab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6487" , 0x1180080e0cab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6488" , 0x1180080e0cac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6489" , 0x1180080e0cac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6490" , 0x1180080e0cad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6491" , 0x1180080e0cad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6492" , 0x1180080e0cae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6493" , 0x1180080e0cae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6494" , 0x1180080e0caf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6495" , 0x1180080e0caf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6496" , 0x1180080e0cb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6497" , 0x1180080e0cb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6498" , 0x1180080e0cb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6499" , 0x1180080e0cb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6500" , 0x1180080e0cb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6501" , 0x1180080e0cb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6502" , 0x1180080e0cb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6503" , 0x1180080e0cb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6504" , 0x1180080e0cb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6505" , 0x1180080e0cb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6506" , 0x1180080e0cb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6507" , 0x1180080e0cb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6508" , 0x1180080e0cb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6509" , 0x1180080e0cb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6510" , 0x1180080e0cb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6511" , 0x1180080e0cb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6512" , 0x1180080e0cb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6513" , 0x1180080e0cb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6514" , 0x1180080e0cb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6515" , 0x1180080e0cb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6516" , 0x1180080e0cba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6517" , 0x1180080e0cba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6518" , 0x1180080e0cbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6519" , 0x1180080e0cbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6520" , 0x1180080e0cbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6521" , 0x1180080e0cbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6522" , 0x1180080e0cbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6523" , 0x1180080e0cbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6524" , 0x1180080e0cbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6525" , 0x1180080e0cbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6526" , 0x1180080e0cbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6527" , 0x1180080e0cbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6528" , 0x1180080e0cc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6529" , 0x1180080e0cc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6530" , 0x1180080e0cc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6531" , 0x1180080e0cc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6532" , 0x1180080e0cc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6533" , 0x1180080e0cc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6534" , 0x1180080e0cc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6535" , 0x1180080e0cc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6536" , 0x1180080e0cc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6537" , 0x1180080e0cc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6538" , 0x1180080e0cc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6539" , 0x1180080e0cc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6540" , 0x1180080e0cc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6541" , 0x1180080e0cc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6542" , 0x1180080e0cc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6543" , 0x1180080e0cc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6544" , 0x1180080e0cc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6545" , 0x1180080e0cc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6546" , 0x1180080e0cc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6547" , 0x1180080e0cc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6548" , 0x1180080e0cca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6549" , 0x1180080e0cca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6550" , 0x1180080e0ccb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6551" , 0x1180080e0ccb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6552" , 0x1180080e0ccc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6553" , 0x1180080e0ccc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6554" , 0x1180080e0ccd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6555" , 0x1180080e0ccd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6556" , 0x1180080e0cce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6557" , 0x1180080e0cce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6558" , 0x1180080e0ccf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6559" , 0x1180080e0ccf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6560" , 0x1180080e0cd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6561" , 0x1180080e0cd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6562" , 0x1180080e0cd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6563" , 0x1180080e0cd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6564" , 0x1180080e0cd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6565" , 0x1180080e0cd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6566" , 0x1180080e0cd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6567" , 0x1180080e0cd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6568" , 0x1180080e0cd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6569" , 0x1180080e0cd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6570" , 0x1180080e0cd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6571" , 0x1180080e0cd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6572" , 0x1180080e0cd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6573" , 0x1180080e0cd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6574" , 0x1180080e0cd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6575" , 0x1180080e0cd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6576" , 0x1180080e0cd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6577" , 0x1180080e0cd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6578" , 0x1180080e0cd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6579" , 0x1180080e0cd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6580" , 0x1180080e0cda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6581" , 0x1180080e0cda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6582" , 0x1180080e0cdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6583" , 0x1180080e0cdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6584" , 0x1180080e0cdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6585" , 0x1180080e0cdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6586" , 0x1180080e0cdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6587" , 0x1180080e0cdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6588" , 0x1180080e0cde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6589" , 0x1180080e0cde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6590" , 0x1180080e0cdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6591" , 0x1180080e0cdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6592" , 0x1180080e0ce00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6593" , 0x1180080e0ce08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6594" , 0x1180080e0ce10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6595" , 0x1180080e0ce18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6596" , 0x1180080e0ce20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6597" , 0x1180080e0ce28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6598" , 0x1180080e0ce30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6599" , 0x1180080e0ce38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6600" , 0x1180080e0ce40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6601" , 0x1180080e0ce48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6602" , 0x1180080e0ce50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6603" , 0x1180080e0ce58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6604" , 0x1180080e0ce60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6605" , 0x1180080e0ce68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6606" , 0x1180080e0ce70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6607" , 0x1180080e0ce78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6608" , 0x1180080e0ce80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6609" , 0x1180080e0ce88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6610" , 0x1180080e0ce90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6611" , 0x1180080e0ce98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6612" , 0x1180080e0cea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6613" , 0x1180080e0cea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6614" , 0x1180080e0ceb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6615" , 0x1180080e0ceb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6616" , 0x1180080e0cec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6617" , 0x1180080e0cec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6618" , 0x1180080e0ced0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6619" , 0x1180080e0ced8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6620" , 0x1180080e0cee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6621" , 0x1180080e0cee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6622" , 0x1180080e0cef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6623" , 0x1180080e0cef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6624" , 0x1180080e0cf00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6625" , 0x1180080e0cf08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6626" , 0x1180080e0cf10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6627" , 0x1180080e0cf18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6628" , 0x1180080e0cf20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6629" , 0x1180080e0cf28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6630" , 0x1180080e0cf30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6631" , 0x1180080e0cf38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6632" , 0x1180080e0cf40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6633" , 0x1180080e0cf48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6634" , 0x1180080e0cf50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6635" , 0x1180080e0cf58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6636" , 0x1180080e0cf60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6637" , 0x1180080e0cf68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6638" , 0x1180080e0cf70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6639" , 0x1180080e0cf78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6640" , 0x1180080e0cf80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6641" , 0x1180080e0cf88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6642" , 0x1180080e0cf90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6643" , 0x1180080e0cf98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6644" , 0x1180080e0cfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6645" , 0x1180080e0cfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6646" , 0x1180080e0cfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6647" , 0x1180080e0cfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6648" , 0x1180080e0cfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6649" , 0x1180080e0cfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6650" , 0x1180080e0cfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6651" , 0x1180080e0cfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6652" , 0x1180080e0cfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6653" , 0x1180080e0cfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6654" , 0x1180080e0cff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6655" , 0x1180080e0cff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6656" , 0x1180080e0d000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6657" , 0x1180080e0d008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6658" , 0x1180080e0d010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6659" , 0x1180080e0d018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6660" , 0x1180080e0d020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6661" , 0x1180080e0d028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6662" , 0x1180080e0d030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6663" , 0x1180080e0d038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6664" , 0x1180080e0d040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6665" , 0x1180080e0d048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6666" , 0x1180080e0d050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6667" , 0x1180080e0d058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6668" , 0x1180080e0d060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6669" , 0x1180080e0d068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6670" , 0x1180080e0d070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6671" , 0x1180080e0d078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6672" , 0x1180080e0d080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6673" , 0x1180080e0d088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6674" , 0x1180080e0d090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6675" , 0x1180080e0d098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6676" , 0x1180080e0d0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6677" , 0x1180080e0d0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6678" , 0x1180080e0d0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6679" , 0x1180080e0d0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6680" , 0x1180080e0d0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6681" , 0x1180080e0d0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6682" , 0x1180080e0d0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6683" , 0x1180080e0d0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6684" , 0x1180080e0d0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6685" , 0x1180080e0d0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6686" , 0x1180080e0d0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6687" , 0x1180080e0d0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6688" , 0x1180080e0d100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6689" , 0x1180080e0d108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6690" , 0x1180080e0d110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6691" , 0x1180080e0d118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6692" , 0x1180080e0d120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6693" , 0x1180080e0d128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6694" , 0x1180080e0d130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6695" , 0x1180080e0d138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6696" , 0x1180080e0d140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6697" , 0x1180080e0d148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6698" , 0x1180080e0d150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6699" , 0x1180080e0d158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6700" , 0x1180080e0d160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6701" , 0x1180080e0d168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6702" , 0x1180080e0d170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6703" , 0x1180080e0d178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6704" , 0x1180080e0d180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6705" , 0x1180080e0d188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6706" , 0x1180080e0d190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6707" , 0x1180080e0d198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6708" , 0x1180080e0d1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6709" , 0x1180080e0d1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6710" , 0x1180080e0d1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6711" , 0x1180080e0d1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6712" , 0x1180080e0d1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6713" , 0x1180080e0d1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6714" , 0x1180080e0d1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6715" , 0x1180080e0d1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6716" , 0x1180080e0d1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6717" , 0x1180080e0d1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6718" , 0x1180080e0d1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6719" , 0x1180080e0d1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6720" , 0x1180080e0d200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6721" , 0x1180080e0d208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6722" , 0x1180080e0d210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6723" , 0x1180080e0d218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6724" , 0x1180080e0d220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6725" , 0x1180080e0d228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6726" , 0x1180080e0d230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6727" , 0x1180080e0d238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6728" , 0x1180080e0d240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6729" , 0x1180080e0d248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6730" , 0x1180080e0d250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6731" , 0x1180080e0d258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6732" , 0x1180080e0d260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6733" , 0x1180080e0d268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6734" , 0x1180080e0d270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6735" , 0x1180080e0d278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6736" , 0x1180080e0d280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6737" , 0x1180080e0d288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6738" , 0x1180080e0d290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6739" , 0x1180080e0d298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6740" , 0x1180080e0d2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6741" , 0x1180080e0d2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6742" , 0x1180080e0d2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6743" , 0x1180080e0d2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6744" , 0x1180080e0d2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6745" , 0x1180080e0d2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6746" , 0x1180080e0d2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6747" , 0x1180080e0d2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6748" , 0x1180080e0d2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6749" , 0x1180080e0d2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6750" , 0x1180080e0d2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6751" , 0x1180080e0d2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6752" , 0x1180080e0d300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6753" , 0x1180080e0d308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6754" , 0x1180080e0d310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6755" , 0x1180080e0d318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6756" , 0x1180080e0d320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6757" , 0x1180080e0d328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6758" , 0x1180080e0d330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6759" , 0x1180080e0d338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6760" , 0x1180080e0d340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6761" , 0x1180080e0d348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6762" , 0x1180080e0d350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6763" , 0x1180080e0d358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6764" , 0x1180080e0d360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6765" , 0x1180080e0d368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6766" , 0x1180080e0d370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6767" , 0x1180080e0d378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6768" , 0x1180080e0d380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6769" , 0x1180080e0d388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6770" , 0x1180080e0d390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6771" , 0x1180080e0d398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6772" , 0x1180080e0d3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6773" , 0x1180080e0d3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6774" , 0x1180080e0d3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6775" , 0x1180080e0d3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6776" , 0x1180080e0d3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6777" , 0x1180080e0d3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6778" , 0x1180080e0d3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6779" , 0x1180080e0d3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6780" , 0x1180080e0d3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6781" , 0x1180080e0d3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6782" , 0x1180080e0d3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6783" , 0x1180080e0d3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6784" , 0x1180080e0d400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6785" , 0x1180080e0d408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6786" , 0x1180080e0d410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6787" , 0x1180080e0d418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6788" , 0x1180080e0d420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6789" , 0x1180080e0d428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6790" , 0x1180080e0d430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6791" , 0x1180080e0d438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6792" , 0x1180080e0d440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6793" , 0x1180080e0d448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6794" , 0x1180080e0d450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6795" , 0x1180080e0d458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6796" , 0x1180080e0d460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6797" , 0x1180080e0d468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6798" , 0x1180080e0d470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6799" , 0x1180080e0d478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6800" , 0x1180080e0d480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6801" , 0x1180080e0d488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6802" , 0x1180080e0d490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6803" , 0x1180080e0d498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6804" , 0x1180080e0d4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6805" , 0x1180080e0d4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6806" , 0x1180080e0d4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6807" , 0x1180080e0d4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6808" , 0x1180080e0d4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6809" , 0x1180080e0d4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6810" , 0x1180080e0d4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6811" , 0x1180080e0d4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6812" , 0x1180080e0d4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6813" , 0x1180080e0d4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6814" , 0x1180080e0d4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6815" , 0x1180080e0d4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6816" , 0x1180080e0d500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6817" , 0x1180080e0d508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6818" , 0x1180080e0d510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6819" , 0x1180080e0d518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6820" , 0x1180080e0d520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6821" , 0x1180080e0d528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6822" , 0x1180080e0d530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6823" , 0x1180080e0d538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6824" , 0x1180080e0d540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6825" , 0x1180080e0d548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6826" , 0x1180080e0d550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6827" , 0x1180080e0d558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6828" , 0x1180080e0d560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6829" , 0x1180080e0d568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6830" , 0x1180080e0d570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6831" , 0x1180080e0d578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6832" , 0x1180080e0d580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6833" , 0x1180080e0d588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6834" , 0x1180080e0d590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6835" , 0x1180080e0d598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6836" , 0x1180080e0d5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6837" , 0x1180080e0d5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6838" , 0x1180080e0d5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6839" , 0x1180080e0d5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6840" , 0x1180080e0d5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6841" , 0x1180080e0d5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6842" , 0x1180080e0d5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6843" , 0x1180080e0d5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6844" , 0x1180080e0d5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6845" , 0x1180080e0d5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6846" , 0x1180080e0d5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6847" , 0x1180080e0d5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6848" , 0x1180080e0d600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6849" , 0x1180080e0d608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6850" , 0x1180080e0d610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6851" , 0x1180080e0d618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6852" , 0x1180080e0d620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6853" , 0x1180080e0d628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6854" , 0x1180080e0d630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6855" , 0x1180080e0d638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6856" , 0x1180080e0d640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6857" , 0x1180080e0d648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6858" , 0x1180080e0d650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6859" , 0x1180080e0d658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6860" , 0x1180080e0d660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6861" , 0x1180080e0d668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6862" , 0x1180080e0d670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6863" , 0x1180080e0d678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6864" , 0x1180080e0d680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6865" , 0x1180080e0d688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6866" , 0x1180080e0d690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6867" , 0x1180080e0d698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6868" , 0x1180080e0d6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6869" , 0x1180080e0d6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6870" , 0x1180080e0d6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6871" , 0x1180080e0d6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6872" , 0x1180080e0d6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6873" , 0x1180080e0d6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6874" , 0x1180080e0d6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6875" , 0x1180080e0d6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6876" , 0x1180080e0d6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6877" , 0x1180080e0d6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6878" , 0x1180080e0d6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6879" , 0x1180080e0d6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6880" , 0x1180080e0d700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6881" , 0x1180080e0d708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6882" , 0x1180080e0d710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6883" , 0x1180080e0d718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6884" , 0x1180080e0d720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6885" , 0x1180080e0d728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6886" , 0x1180080e0d730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6887" , 0x1180080e0d738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6888" , 0x1180080e0d740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6889" , 0x1180080e0d748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6890" , 0x1180080e0d750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6891" , 0x1180080e0d758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6892" , 0x1180080e0d760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6893" , 0x1180080e0d768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6894" , 0x1180080e0d770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6895" , 0x1180080e0d778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6896" , 0x1180080e0d780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6897" , 0x1180080e0d788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6898" , 0x1180080e0d790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6899" , 0x1180080e0d798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6900" , 0x1180080e0d7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6901" , 0x1180080e0d7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6902" , 0x1180080e0d7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6903" , 0x1180080e0d7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6904" , 0x1180080e0d7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6905" , 0x1180080e0d7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6906" , 0x1180080e0d7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6907" , 0x1180080e0d7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6908" , 0x1180080e0d7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6909" , 0x1180080e0d7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6910" , 0x1180080e0d7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6911" , 0x1180080e0d7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6912" , 0x1180080e0d800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6913" , 0x1180080e0d808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6914" , 0x1180080e0d810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6915" , 0x1180080e0d818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6916" , 0x1180080e0d820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6917" , 0x1180080e0d828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6918" , 0x1180080e0d830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6919" , 0x1180080e0d838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6920" , 0x1180080e0d840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6921" , 0x1180080e0d848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6922" , 0x1180080e0d850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6923" , 0x1180080e0d858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6924" , 0x1180080e0d860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6925" , 0x1180080e0d868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6926" , 0x1180080e0d870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6927" , 0x1180080e0d878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6928" , 0x1180080e0d880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6929" , 0x1180080e0d888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6930" , 0x1180080e0d890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6931" , 0x1180080e0d898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6932" , 0x1180080e0d8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6933" , 0x1180080e0d8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6934" , 0x1180080e0d8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6935" , 0x1180080e0d8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6936" , 0x1180080e0d8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6937" , 0x1180080e0d8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6938" , 0x1180080e0d8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6939" , 0x1180080e0d8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6940" , 0x1180080e0d8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6941" , 0x1180080e0d8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6942" , 0x1180080e0d8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6943" , 0x1180080e0d8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6944" , 0x1180080e0d900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6945" , 0x1180080e0d908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6946" , 0x1180080e0d910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6947" , 0x1180080e0d918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6948" , 0x1180080e0d920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6949" , 0x1180080e0d928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6950" , 0x1180080e0d930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6951" , 0x1180080e0d938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6952" , 0x1180080e0d940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6953" , 0x1180080e0d948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6954" , 0x1180080e0d950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6955" , 0x1180080e0d958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6956" , 0x1180080e0d960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6957" , 0x1180080e0d968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6958" , 0x1180080e0d970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6959" , 0x1180080e0d978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6960" , 0x1180080e0d980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6961" , 0x1180080e0d988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6962" , 0x1180080e0d990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6963" , 0x1180080e0d998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6964" , 0x1180080e0d9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6965" , 0x1180080e0d9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6966" , 0x1180080e0d9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6967" , 0x1180080e0d9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6968" , 0x1180080e0d9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6969" , 0x1180080e0d9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6970" , 0x1180080e0d9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6971" , 0x1180080e0d9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6972" , 0x1180080e0d9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6973" , 0x1180080e0d9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6974" , 0x1180080e0d9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6975" , 0x1180080e0d9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6976" , 0x1180080e0da00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6977" , 0x1180080e0da08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6978" , 0x1180080e0da10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6979" , 0x1180080e0da18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6980" , 0x1180080e0da20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6981" , 0x1180080e0da28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6982" , 0x1180080e0da30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6983" , 0x1180080e0da38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6984" , 0x1180080e0da40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6985" , 0x1180080e0da48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6986" , 0x1180080e0da50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6987" , 0x1180080e0da58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6988" , 0x1180080e0da60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6989" , 0x1180080e0da68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6990" , 0x1180080e0da70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6991" , 0x1180080e0da78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6992" , 0x1180080e0da80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6993" , 0x1180080e0da88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6994" , 0x1180080e0da90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6995" , 0x1180080e0da98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6996" , 0x1180080e0daa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6997" , 0x1180080e0daa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6998" , 0x1180080e0dab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP6999" , 0x1180080e0dab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7000" , 0x1180080e0dac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7001" , 0x1180080e0dac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7002" , 0x1180080e0dad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7003" , 0x1180080e0dad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7004" , 0x1180080e0dae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7005" , 0x1180080e0dae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7006" , 0x1180080e0daf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7007" , 0x1180080e0daf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7008" , 0x1180080e0db00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7009" , 0x1180080e0db08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7010" , 0x1180080e0db10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7011" , 0x1180080e0db18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7012" , 0x1180080e0db20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7013" , 0x1180080e0db28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7014" , 0x1180080e0db30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7015" , 0x1180080e0db38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7016" , 0x1180080e0db40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7017" , 0x1180080e0db48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7018" , 0x1180080e0db50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7019" , 0x1180080e0db58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7020" , 0x1180080e0db60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7021" , 0x1180080e0db68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7022" , 0x1180080e0db70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7023" , 0x1180080e0db78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7024" , 0x1180080e0db80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7025" , 0x1180080e0db88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7026" , 0x1180080e0db90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7027" , 0x1180080e0db98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7028" , 0x1180080e0dba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7029" , 0x1180080e0dba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7030" , 0x1180080e0dbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7031" , 0x1180080e0dbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7032" , 0x1180080e0dbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7033" , 0x1180080e0dbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7034" , 0x1180080e0dbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7035" , 0x1180080e0dbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7036" , 0x1180080e0dbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7037" , 0x1180080e0dbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7038" , 0x1180080e0dbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7039" , 0x1180080e0dbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7040" , 0x1180080e0dc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7041" , 0x1180080e0dc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7042" , 0x1180080e0dc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7043" , 0x1180080e0dc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7044" , 0x1180080e0dc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7045" , 0x1180080e0dc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7046" , 0x1180080e0dc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7047" , 0x1180080e0dc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7048" , 0x1180080e0dc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7049" , 0x1180080e0dc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7050" , 0x1180080e0dc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7051" , 0x1180080e0dc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7052" , 0x1180080e0dc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7053" , 0x1180080e0dc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7054" , 0x1180080e0dc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7055" , 0x1180080e0dc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7056" , 0x1180080e0dc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7057" , 0x1180080e0dc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7058" , 0x1180080e0dc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7059" , 0x1180080e0dc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7060" , 0x1180080e0dca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7061" , 0x1180080e0dca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7062" , 0x1180080e0dcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7063" , 0x1180080e0dcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7064" , 0x1180080e0dcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7065" , 0x1180080e0dcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7066" , 0x1180080e0dcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7067" , 0x1180080e0dcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7068" , 0x1180080e0dce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7069" , 0x1180080e0dce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7070" , 0x1180080e0dcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7071" , 0x1180080e0dcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7072" , 0x1180080e0dd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7073" , 0x1180080e0dd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7074" , 0x1180080e0dd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7075" , 0x1180080e0dd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7076" , 0x1180080e0dd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7077" , 0x1180080e0dd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7078" , 0x1180080e0dd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7079" , 0x1180080e0dd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7080" , 0x1180080e0dd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7081" , 0x1180080e0dd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7082" , 0x1180080e0dd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7083" , 0x1180080e0dd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7084" , 0x1180080e0dd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7085" , 0x1180080e0dd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7086" , 0x1180080e0dd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7087" , 0x1180080e0dd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7088" , 0x1180080e0dd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7089" , 0x1180080e0dd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7090" , 0x1180080e0dd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7091" , 0x1180080e0dd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7092" , 0x1180080e0dda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7093" , 0x1180080e0dda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7094" , 0x1180080e0ddb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7095" , 0x1180080e0ddb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7096" , 0x1180080e0ddc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7097" , 0x1180080e0ddc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7098" , 0x1180080e0ddd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7099" , 0x1180080e0ddd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7100" , 0x1180080e0dde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7101" , 0x1180080e0dde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7102" , 0x1180080e0ddf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7103" , 0x1180080e0ddf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7104" , 0x1180080e0de00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7105" , 0x1180080e0de08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7106" , 0x1180080e0de10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7107" , 0x1180080e0de18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7108" , 0x1180080e0de20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7109" , 0x1180080e0de28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7110" , 0x1180080e0de30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7111" , 0x1180080e0de38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7112" , 0x1180080e0de40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7113" , 0x1180080e0de48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7114" , 0x1180080e0de50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7115" , 0x1180080e0de58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7116" , 0x1180080e0de60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7117" , 0x1180080e0de68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7118" , 0x1180080e0de70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7119" , 0x1180080e0de78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7120" , 0x1180080e0de80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7121" , 0x1180080e0de88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7122" , 0x1180080e0de90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7123" , 0x1180080e0de98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7124" , 0x1180080e0dea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7125" , 0x1180080e0dea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7126" , 0x1180080e0deb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7127" , 0x1180080e0deb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7128" , 0x1180080e0dec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7129" , 0x1180080e0dec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7130" , 0x1180080e0ded0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7131" , 0x1180080e0ded8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7132" , 0x1180080e0dee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7133" , 0x1180080e0dee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7134" , 0x1180080e0def0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7135" , 0x1180080e0def8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7136" , 0x1180080e0df00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7137" , 0x1180080e0df08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7138" , 0x1180080e0df10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7139" , 0x1180080e0df18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7140" , 0x1180080e0df20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7141" , 0x1180080e0df28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7142" , 0x1180080e0df30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7143" , 0x1180080e0df38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7144" , 0x1180080e0df40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7145" , 0x1180080e0df48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7146" , 0x1180080e0df50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7147" , 0x1180080e0df58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7148" , 0x1180080e0df60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7149" , 0x1180080e0df68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7150" , 0x1180080e0df70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7151" , 0x1180080e0df78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7152" , 0x1180080e0df80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7153" , 0x1180080e0df88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7154" , 0x1180080e0df90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7155" , 0x1180080e0df98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7156" , 0x1180080e0dfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7157" , 0x1180080e0dfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7158" , 0x1180080e0dfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7159" , 0x1180080e0dfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7160" , 0x1180080e0dfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7161" , 0x1180080e0dfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7162" , 0x1180080e0dfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7163" , 0x1180080e0dfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7164" , 0x1180080e0dfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7165" , 0x1180080e0dfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7166" , 0x1180080e0dff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7167" , 0x1180080e0dff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7168" , 0x1180080e0e000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7169" , 0x1180080e0e008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7170" , 0x1180080e0e010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7171" , 0x1180080e0e018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7172" , 0x1180080e0e020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7173" , 0x1180080e0e028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7174" , 0x1180080e0e030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7175" , 0x1180080e0e038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7176" , 0x1180080e0e040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7177" , 0x1180080e0e048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7178" , 0x1180080e0e050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7179" , 0x1180080e0e058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7180" , 0x1180080e0e060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7181" , 0x1180080e0e068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7182" , 0x1180080e0e070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7183" , 0x1180080e0e078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7184" , 0x1180080e0e080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7185" , 0x1180080e0e088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7186" , 0x1180080e0e090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7187" , 0x1180080e0e098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7188" , 0x1180080e0e0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7189" , 0x1180080e0e0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7190" , 0x1180080e0e0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7191" , 0x1180080e0e0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7192" , 0x1180080e0e0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7193" , 0x1180080e0e0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7194" , 0x1180080e0e0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7195" , 0x1180080e0e0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7196" , 0x1180080e0e0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7197" , 0x1180080e0e0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7198" , 0x1180080e0e0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7199" , 0x1180080e0e0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7200" , 0x1180080e0e100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7201" , 0x1180080e0e108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7202" , 0x1180080e0e110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7203" , 0x1180080e0e118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7204" , 0x1180080e0e120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7205" , 0x1180080e0e128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7206" , 0x1180080e0e130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7207" , 0x1180080e0e138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7208" , 0x1180080e0e140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7209" , 0x1180080e0e148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7210" , 0x1180080e0e150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7211" , 0x1180080e0e158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7212" , 0x1180080e0e160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7213" , 0x1180080e0e168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7214" , 0x1180080e0e170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7215" , 0x1180080e0e178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7216" , 0x1180080e0e180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7217" , 0x1180080e0e188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7218" , 0x1180080e0e190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7219" , 0x1180080e0e198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7220" , 0x1180080e0e1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7221" , 0x1180080e0e1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7222" , 0x1180080e0e1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7223" , 0x1180080e0e1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7224" , 0x1180080e0e1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7225" , 0x1180080e0e1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7226" , 0x1180080e0e1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7227" , 0x1180080e0e1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7228" , 0x1180080e0e1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7229" , 0x1180080e0e1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7230" , 0x1180080e0e1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7231" , 0x1180080e0e1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7232" , 0x1180080e0e200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7233" , 0x1180080e0e208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7234" , 0x1180080e0e210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7235" , 0x1180080e0e218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7236" , 0x1180080e0e220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7237" , 0x1180080e0e228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7238" , 0x1180080e0e230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7239" , 0x1180080e0e238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7240" , 0x1180080e0e240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7241" , 0x1180080e0e248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7242" , 0x1180080e0e250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7243" , 0x1180080e0e258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7244" , 0x1180080e0e260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7245" , 0x1180080e0e268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7246" , 0x1180080e0e270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7247" , 0x1180080e0e278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7248" , 0x1180080e0e280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7249" , 0x1180080e0e288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7250" , 0x1180080e0e290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7251" , 0x1180080e0e298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7252" , 0x1180080e0e2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7253" , 0x1180080e0e2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7254" , 0x1180080e0e2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7255" , 0x1180080e0e2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7256" , 0x1180080e0e2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7257" , 0x1180080e0e2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7258" , 0x1180080e0e2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7259" , 0x1180080e0e2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7260" , 0x1180080e0e2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7261" , 0x1180080e0e2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7262" , 0x1180080e0e2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7263" , 0x1180080e0e2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7264" , 0x1180080e0e300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7265" , 0x1180080e0e308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7266" , 0x1180080e0e310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7267" , 0x1180080e0e318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7268" , 0x1180080e0e320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7269" , 0x1180080e0e328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7270" , 0x1180080e0e330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7271" , 0x1180080e0e338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7272" , 0x1180080e0e340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7273" , 0x1180080e0e348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7274" , 0x1180080e0e350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7275" , 0x1180080e0e358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7276" , 0x1180080e0e360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7277" , 0x1180080e0e368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7278" , 0x1180080e0e370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7279" , 0x1180080e0e378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7280" , 0x1180080e0e380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7281" , 0x1180080e0e388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7282" , 0x1180080e0e390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7283" , 0x1180080e0e398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7284" , 0x1180080e0e3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7285" , 0x1180080e0e3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7286" , 0x1180080e0e3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7287" , 0x1180080e0e3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7288" , 0x1180080e0e3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7289" , 0x1180080e0e3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7290" , 0x1180080e0e3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7291" , 0x1180080e0e3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7292" , 0x1180080e0e3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7293" , 0x1180080e0e3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7294" , 0x1180080e0e3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7295" , 0x1180080e0e3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7296" , 0x1180080e0e400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7297" , 0x1180080e0e408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7298" , 0x1180080e0e410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7299" , 0x1180080e0e418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7300" , 0x1180080e0e420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7301" , 0x1180080e0e428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7302" , 0x1180080e0e430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7303" , 0x1180080e0e438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7304" , 0x1180080e0e440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7305" , 0x1180080e0e448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7306" , 0x1180080e0e450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7307" , 0x1180080e0e458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7308" , 0x1180080e0e460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7309" , 0x1180080e0e468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7310" , 0x1180080e0e470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7311" , 0x1180080e0e478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7312" , 0x1180080e0e480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7313" , 0x1180080e0e488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7314" , 0x1180080e0e490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7315" , 0x1180080e0e498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7316" , 0x1180080e0e4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7317" , 0x1180080e0e4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7318" , 0x1180080e0e4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7319" , 0x1180080e0e4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7320" , 0x1180080e0e4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7321" , 0x1180080e0e4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7322" , 0x1180080e0e4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7323" , 0x1180080e0e4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7324" , 0x1180080e0e4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7325" , 0x1180080e0e4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7326" , 0x1180080e0e4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7327" , 0x1180080e0e4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7328" , 0x1180080e0e500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7329" , 0x1180080e0e508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7330" , 0x1180080e0e510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7331" , 0x1180080e0e518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7332" , 0x1180080e0e520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7333" , 0x1180080e0e528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7334" , 0x1180080e0e530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7335" , 0x1180080e0e538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7336" , 0x1180080e0e540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7337" , 0x1180080e0e548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7338" , 0x1180080e0e550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7339" , 0x1180080e0e558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7340" , 0x1180080e0e560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7341" , 0x1180080e0e568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7342" , 0x1180080e0e570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7343" , 0x1180080e0e578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7344" , 0x1180080e0e580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7345" , 0x1180080e0e588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7346" , 0x1180080e0e590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7347" , 0x1180080e0e598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7348" , 0x1180080e0e5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7349" , 0x1180080e0e5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7350" , 0x1180080e0e5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7351" , 0x1180080e0e5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7352" , 0x1180080e0e5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7353" , 0x1180080e0e5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7354" , 0x1180080e0e5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7355" , 0x1180080e0e5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7356" , 0x1180080e0e5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7357" , 0x1180080e0e5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7358" , 0x1180080e0e5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7359" , 0x1180080e0e5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7360" , 0x1180080e0e600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7361" , 0x1180080e0e608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7362" , 0x1180080e0e610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7363" , 0x1180080e0e618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7364" , 0x1180080e0e620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7365" , 0x1180080e0e628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7366" , 0x1180080e0e630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7367" , 0x1180080e0e638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7368" , 0x1180080e0e640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7369" , 0x1180080e0e648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7370" , 0x1180080e0e650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7371" , 0x1180080e0e658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7372" , 0x1180080e0e660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7373" , 0x1180080e0e668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7374" , 0x1180080e0e670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7375" , 0x1180080e0e678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7376" , 0x1180080e0e680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7377" , 0x1180080e0e688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7378" , 0x1180080e0e690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7379" , 0x1180080e0e698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7380" , 0x1180080e0e6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7381" , 0x1180080e0e6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7382" , 0x1180080e0e6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7383" , 0x1180080e0e6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7384" , 0x1180080e0e6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7385" , 0x1180080e0e6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7386" , 0x1180080e0e6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7387" , 0x1180080e0e6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7388" , 0x1180080e0e6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7389" , 0x1180080e0e6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7390" , 0x1180080e0e6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7391" , 0x1180080e0e6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7392" , 0x1180080e0e700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7393" , 0x1180080e0e708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7394" , 0x1180080e0e710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7395" , 0x1180080e0e718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7396" , 0x1180080e0e720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7397" , 0x1180080e0e728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7398" , 0x1180080e0e730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7399" , 0x1180080e0e738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7400" , 0x1180080e0e740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7401" , 0x1180080e0e748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7402" , 0x1180080e0e750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7403" , 0x1180080e0e758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7404" , 0x1180080e0e760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7405" , 0x1180080e0e768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7406" , 0x1180080e0e770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7407" , 0x1180080e0e778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7408" , 0x1180080e0e780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7409" , 0x1180080e0e788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7410" , 0x1180080e0e790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7411" , 0x1180080e0e798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7412" , 0x1180080e0e7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7413" , 0x1180080e0e7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7414" , 0x1180080e0e7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7415" , 0x1180080e0e7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7416" , 0x1180080e0e7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7417" , 0x1180080e0e7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7418" , 0x1180080e0e7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7419" , 0x1180080e0e7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7420" , 0x1180080e0e7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7421" , 0x1180080e0e7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7422" , 0x1180080e0e7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7423" , 0x1180080e0e7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7424" , 0x1180080e0e800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7425" , 0x1180080e0e808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7426" , 0x1180080e0e810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7427" , 0x1180080e0e818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7428" , 0x1180080e0e820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7429" , 0x1180080e0e828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7430" , 0x1180080e0e830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7431" , 0x1180080e0e838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7432" , 0x1180080e0e840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7433" , 0x1180080e0e848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7434" , 0x1180080e0e850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7435" , 0x1180080e0e858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7436" , 0x1180080e0e860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7437" , 0x1180080e0e868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7438" , 0x1180080e0e870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7439" , 0x1180080e0e878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7440" , 0x1180080e0e880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7441" , 0x1180080e0e888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7442" , 0x1180080e0e890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7443" , 0x1180080e0e898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7444" , 0x1180080e0e8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7445" , 0x1180080e0e8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7446" , 0x1180080e0e8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7447" , 0x1180080e0e8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7448" , 0x1180080e0e8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7449" , 0x1180080e0e8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7450" , 0x1180080e0e8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7451" , 0x1180080e0e8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7452" , 0x1180080e0e8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7453" , 0x1180080e0e8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7454" , 0x1180080e0e8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7455" , 0x1180080e0e8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7456" , 0x1180080e0e900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7457" , 0x1180080e0e908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7458" , 0x1180080e0e910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7459" , 0x1180080e0e918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7460" , 0x1180080e0e920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7461" , 0x1180080e0e928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7462" , 0x1180080e0e930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7463" , 0x1180080e0e938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7464" , 0x1180080e0e940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7465" , 0x1180080e0e948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7466" , 0x1180080e0e950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7467" , 0x1180080e0e958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7468" , 0x1180080e0e960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7469" , 0x1180080e0e968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7470" , 0x1180080e0e970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7471" , 0x1180080e0e978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7472" , 0x1180080e0e980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7473" , 0x1180080e0e988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7474" , 0x1180080e0e990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7475" , 0x1180080e0e998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7476" , 0x1180080e0e9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7477" , 0x1180080e0e9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7478" , 0x1180080e0e9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7479" , 0x1180080e0e9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7480" , 0x1180080e0e9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7481" , 0x1180080e0e9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7482" , 0x1180080e0e9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7483" , 0x1180080e0e9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7484" , 0x1180080e0e9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7485" , 0x1180080e0e9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7486" , 0x1180080e0e9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7487" , 0x1180080e0e9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7488" , 0x1180080e0ea00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7489" , 0x1180080e0ea08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7490" , 0x1180080e0ea10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7491" , 0x1180080e0ea18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7492" , 0x1180080e0ea20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7493" , 0x1180080e0ea28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7494" , 0x1180080e0ea30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7495" , 0x1180080e0ea38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7496" , 0x1180080e0ea40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7497" , 0x1180080e0ea48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7498" , 0x1180080e0ea50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7499" , 0x1180080e0ea58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7500" , 0x1180080e0ea60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7501" , 0x1180080e0ea68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7502" , 0x1180080e0ea70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7503" , 0x1180080e0ea78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7504" , 0x1180080e0ea80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7505" , 0x1180080e0ea88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7506" , 0x1180080e0ea90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7507" , 0x1180080e0ea98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7508" , 0x1180080e0eaa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7509" , 0x1180080e0eaa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7510" , 0x1180080e0eab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7511" , 0x1180080e0eab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7512" , 0x1180080e0eac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7513" , 0x1180080e0eac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7514" , 0x1180080e0ead0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7515" , 0x1180080e0ead8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7516" , 0x1180080e0eae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7517" , 0x1180080e0eae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7518" , 0x1180080e0eaf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7519" , 0x1180080e0eaf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7520" , 0x1180080e0eb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7521" , 0x1180080e0eb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7522" , 0x1180080e0eb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7523" , 0x1180080e0eb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7524" , 0x1180080e0eb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7525" , 0x1180080e0eb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7526" , 0x1180080e0eb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7527" , 0x1180080e0eb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7528" , 0x1180080e0eb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7529" , 0x1180080e0eb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7530" , 0x1180080e0eb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7531" , 0x1180080e0eb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7532" , 0x1180080e0eb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7533" , 0x1180080e0eb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7534" , 0x1180080e0eb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7535" , 0x1180080e0eb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7536" , 0x1180080e0eb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7537" , 0x1180080e0eb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7538" , 0x1180080e0eb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7539" , 0x1180080e0eb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7540" , 0x1180080e0eba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7541" , 0x1180080e0eba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7542" , 0x1180080e0ebb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7543" , 0x1180080e0ebb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7544" , 0x1180080e0ebc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7545" , 0x1180080e0ebc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7546" , 0x1180080e0ebd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7547" , 0x1180080e0ebd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7548" , 0x1180080e0ebe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7549" , 0x1180080e0ebe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7550" , 0x1180080e0ebf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7551" , 0x1180080e0ebf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7552" , 0x1180080e0ec00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7553" , 0x1180080e0ec08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7554" , 0x1180080e0ec10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7555" , 0x1180080e0ec18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7556" , 0x1180080e0ec20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7557" , 0x1180080e0ec28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7558" , 0x1180080e0ec30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7559" , 0x1180080e0ec38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7560" , 0x1180080e0ec40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7561" , 0x1180080e0ec48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7562" , 0x1180080e0ec50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7563" , 0x1180080e0ec58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7564" , 0x1180080e0ec60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7565" , 0x1180080e0ec68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7566" , 0x1180080e0ec70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7567" , 0x1180080e0ec78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7568" , 0x1180080e0ec80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7569" , 0x1180080e0ec88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7570" , 0x1180080e0ec90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7571" , 0x1180080e0ec98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7572" , 0x1180080e0eca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7573" , 0x1180080e0eca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7574" , 0x1180080e0ecb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7575" , 0x1180080e0ecb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7576" , 0x1180080e0ecc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7577" , 0x1180080e0ecc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7578" , 0x1180080e0ecd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7579" , 0x1180080e0ecd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7580" , 0x1180080e0ece0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7581" , 0x1180080e0ece8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7582" , 0x1180080e0ecf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7583" , 0x1180080e0ecf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7584" , 0x1180080e0ed00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7585" , 0x1180080e0ed08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7586" , 0x1180080e0ed10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7587" , 0x1180080e0ed18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7588" , 0x1180080e0ed20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7589" , 0x1180080e0ed28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7590" , 0x1180080e0ed30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7591" , 0x1180080e0ed38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7592" , 0x1180080e0ed40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7593" , 0x1180080e0ed48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7594" , 0x1180080e0ed50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7595" , 0x1180080e0ed58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7596" , 0x1180080e0ed60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7597" , 0x1180080e0ed68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7598" , 0x1180080e0ed70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7599" , 0x1180080e0ed78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7600" , 0x1180080e0ed80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7601" , 0x1180080e0ed88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7602" , 0x1180080e0ed90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7603" , 0x1180080e0ed98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7604" , 0x1180080e0eda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7605" , 0x1180080e0eda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7606" , 0x1180080e0edb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7607" , 0x1180080e0edb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7608" , 0x1180080e0edc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7609" , 0x1180080e0edc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7610" , 0x1180080e0edd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7611" , 0x1180080e0edd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7612" , 0x1180080e0ede0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7613" , 0x1180080e0ede8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7614" , 0x1180080e0edf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7615" , 0x1180080e0edf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7616" , 0x1180080e0ee00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7617" , 0x1180080e0ee08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7618" , 0x1180080e0ee10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7619" , 0x1180080e0ee18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7620" , 0x1180080e0ee20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7621" , 0x1180080e0ee28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7622" , 0x1180080e0ee30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7623" , 0x1180080e0ee38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7624" , 0x1180080e0ee40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7625" , 0x1180080e0ee48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7626" , 0x1180080e0ee50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7627" , 0x1180080e0ee58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7628" , 0x1180080e0ee60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7629" , 0x1180080e0ee68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7630" , 0x1180080e0ee70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7631" , 0x1180080e0ee78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7632" , 0x1180080e0ee80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7633" , 0x1180080e0ee88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7634" , 0x1180080e0ee90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7635" , 0x1180080e0ee98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7636" , 0x1180080e0eea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7637" , 0x1180080e0eea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7638" , 0x1180080e0eeb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7639" , 0x1180080e0eeb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7640" , 0x1180080e0eec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7641" , 0x1180080e0eec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7642" , 0x1180080e0eed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7643" , 0x1180080e0eed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7644" , 0x1180080e0eee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7645" , 0x1180080e0eee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7646" , 0x1180080e0eef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7647" , 0x1180080e0eef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7648" , 0x1180080e0ef00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7649" , 0x1180080e0ef08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7650" , 0x1180080e0ef10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7651" , 0x1180080e0ef18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7652" , 0x1180080e0ef20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7653" , 0x1180080e0ef28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7654" , 0x1180080e0ef30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7655" , 0x1180080e0ef38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7656" , 0x1180080e0ef40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7657" , 0x1180080e0ef48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7658" , 0x1180080e0ef50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7659" , 0x1180080e0ef58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7660" , 0x1180080e0ef60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7661" , 0x1180080e0ef68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7662" , 0x1180080e0ef70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7663" , 0x1180080e0ef78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7664" , 0x1180080e0ef80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7665" , 0x1180080e0ef88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7666" , 0x1180080e0ef90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7667" , 0x1180080e0ef98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7668" , 0x1180080e0efa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7669" , 0x1180080e0efa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7670" , 0x1180080e0efb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7671" , 0x1180080e0efb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7672" , 0x1180080e0efc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7673" , 0x1180080e0efc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7674" , 0x1180080e0efd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7675" , 0x1180080e0efd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7676" , 0x1180080e0efe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7677" , 0x1180080e0efe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7678" , 0x1180080e0eff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7679" , 0x1180080e0eff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7680" , 0x1180080e0f000ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7681" , 0x1180080e0f008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7682" , 0x1180080e0f010ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7683" , 0x1180080e0f018ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7684" , 0x1180080e0f020ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7685" , 0x1180080e0f028ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7686" , 0x1180080e0f030ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7687" , 0x1180080e0f038ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7688" , 0x1180080e0f040ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7689" , 0x1180080e0f048ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7690" , 0x1180080e0f050ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7691" , 0x1180080e0f058ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7692" , 0x1180080e0f060ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7693" , 0x1180080e0f068ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7694" , 0x1180080e0f070ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7695" , 0x1180080e0f078ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7696" , 0x1180080e0f080ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7697" , 0x1180080e0f088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7698" , 0x1180080e0f090ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7699" , 0x1180080e0f098ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7700" , 0x1180080e0f0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7701" , 0x1180080e0f0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7702" , 0x1180080e0f0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7703" , 0x1180080e0f0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7704" , 0x1180080e0f0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7705" , 0x1180080e0f0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7706" , 0x1180080e0f0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7707" , 0x1180080e0f0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7708" , 0x1180080e0f0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7709" , 0x1180080e0f0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7710" , 0x1180080e0f0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7711" , 0x1180080e0f0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7712" , 0x1180080e0f100ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7713" , 0x1180080e0f108ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7714" , 0x1180080e0f110ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7715" , 0x1180080e0f118ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7716" , 0x1180080e0f120ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7717" , 0x1180080e0f128ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7718" , 0x1180080e0f130ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7719" , 0x1180080e0f138ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7720" , 0x1180080e0f140ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7721" , 0x1180080e0f148ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7722" , 0x1180080e0f150ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7723" , 0x1180080e0f158ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7724" , 0x1180080e0f160ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7725" , 0x1180080e0f168ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7726" , 0x1180080e0f170ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7727" , 0x1180080e0f178ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7728" , 0x1180080e0f180ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7729" , 0x1180080e0f188ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7730" , 0x1180080e0f190ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7731" , 0x1180080e0f198ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7732" , 0x1180080e0f1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7733" , 0x1180080e0f1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7734" , 0x1180080e0f1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7735" , 0x1180080e0f1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7736" , 0x1180080e0f1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7737" , 0x1180080e0f1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7738" , 0x1180080e0f1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7739" , 0x1180080e0f1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7740" , 0x1180080e0f1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7741" , 0x1180080e0f1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7742" , 0x1180080e0f1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7743" , 0x1180080e0f1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7744" , 0x1180080e0f200ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7745" , 0x1180080e0f208ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7746" , 0x1180080e0f210ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7747" , 0x1180080e0f218ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7748" , 0x1180080e0f220ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7749" , 0x1180080e0f228ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7750" , 0x1180080e0f230ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7751" , 0x1180080e0f238ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7752" , 0x1180080e0f240ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7753" , 0x1180080e0f248ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7754" , 0x1180080e0f250ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7755" , 0x1180080e0f258ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7756" , 0x1180080e0f260ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7757" , 0x1180080e0f268ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7758" , 0x1180080e0f270ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7759" , 0x1180080e0f278ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7760" , 0x1180080e0f280ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7761" , 0x1180080e0f288ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7762" , 0x1180080e0f290ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7763" , 0x1180080e0f298ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7764" , 0x1180080e0f2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7765" , 0x1180080e0f2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7766" , 0x1180080e0f2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7767" , 0x1180080e0f2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7768" , 0x1180080e0f2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7769" , 0x1180080e0f2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7770" , 0x1180080e0f2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7771" , 0x1180080e0f2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7772" , 0x1180080e0f2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7773" , 0x1180080e0f2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7774" , 0x1180080e0f2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7775" , 0x1180080e0f2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7776" , 0x1180080e0f300ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7777" , 0x1180080e0f308ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7778" , 0x1180080e0f310ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7779" , 0x1180080e0f318ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7780" , 0x1180080e0f320ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7781" , 0x1180080e0f328ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7782" , 0x1180080e0f330ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7783" , 0x1180080e0f338ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7784" , 0x1180080e0f340ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7785" , 0x1180080e0f348ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7786" , 0x1180080e0f350ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7787" , 0x1180080e0f358ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7788" , 0x1180080e0f360ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7789" , 0x1180080e0f368ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7790" , 0x1180080e0f370ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7791" , 0x1180080e0f378ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7792" , 0x1180080e0f380ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7793" , 0x1180080e0f388ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7794" , 0x1180080e0f390ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7795" , 0x1180080e0f398ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7796" , 0x1180080e0f3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7797" , 0x1180080e0f3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7798" , 0x1180080e0f3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7799" , 0x1180080e0f3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7800" , 0x1180080e0f3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7801" , 0x1180080e0f3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7802" , 0x1180080e0f3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7803" , 0x1180080e0f3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7804" , 0x1180080e0f3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7805" , 0x1180080e0f3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7806" , 0x1180080e0f3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7807" , 0x1180080e0f3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7808" , 0x1180080e0f400ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7809" , 0x1180080e0f408ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7810" , 0x1180080e0f410ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7811" , 0x1180080e0f418ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7812" , 0x1180080e0f420ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7813" , 0x1180080e0f428ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7814" , 0x1180080e0f430ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7815" , 0x1180080e0f438ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7816" , 0x1180080e0f440ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7817" , 0x1180080e0f448ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7818" , 0x1180080e0f450ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7819" , 0x1180080e0f458ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7820" , 0x1180080e0f460ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7821" , 0x1180080e0f468ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7822" , 0x1180080e0f470ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7823" , 0x1180080e0f478ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7824" , 0x1180080e0f480ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7825" , 0x1180080e0f488ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7826" , 0x1180080e0f490ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7827" , 0x1180080e0f498ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7828" , 0x1180080e0f4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7829" , 0x1180080e0f4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7830" , 0x1180080e0f4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7831" , 0x1180080e0f4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7832" , 0x1180080e0f4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7833" , 0x1180080e0f4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7834" , 0x1180080e0f4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7835" , 0x1180080e0f4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7836" , 0x1180080e0f4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7837" , 0x1180080e0f4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7838" , 0x1180080e0f4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7839" , 0x1180080e0f4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7840" , 0x1180080e0f500ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7841" , 0x1180080e0f508ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7842" , 0x1180080e0f510ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7843" , 0x1180080e0f518ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7844" , 0x1180080e0f520ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7845" , 0x1180080e0f528ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7846" , 0x1180080e0f530ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7847" , 0x1180080e0f538ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7848" , 0x1180080e0f540ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7849" , 0x1180080e0f548ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7850" , 0x1180080e0f550ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7851" , 0x1180080e0f558ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7852" , 0x1180080e0f560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7853" , 0x1180080e0f568ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7854" , 0x1180080e0f570ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7855" , 0x1180080e0f578ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7856" , 0x1180080e0f580ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7857" , 0x1180080e0f588ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7858" , 0x1180080e0f590ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7859" , 0x1180080e0f598ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7860" , 0x1180080e0f5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7861" , 0x1180080e0f5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7862" , 0x1180080e0f5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7863" , 0x1180080e0f5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7864" , 0x1180080e0f5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7865" , 0x1180080e0f5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7866" , 0x1180080e0f5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7867" , 0x1180080e0f5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7868" , 0x1180080e0f5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7869" , 0x1180080e0f5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7870" , 0x1180080e0f5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7871" , 0x1180080e0f5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7872" , 0x1180080e0f600ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7873" , 0x1180080e0f608ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7874" , 0x1180080e0f610ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7875" , 0x1180080e0f618ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7876" , 0x1180080e0f620ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7877" , 0x1180080e0f628ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7878" , 0x1180080e0f630ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7879" , 0x1180080e0f638ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7880" , 0x1180080e0f640ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7881" , 0x1180080e0f648ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7882" , 0x1180080e0f650ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7883" , 0x1180080e0f658ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7884" , 0x1180080e0f660ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7885" , 0x1180080e0f668ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7886" , 0x1180080e0f670ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7887" , 0x1180080e0f678ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7888" , 0x1180080e0f680ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7889" , 0x1180080e0f688ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7890" , 0x1180080e0f690ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7891" , 0x1180080e0f698ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7892" , 0x1180080e0f6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7893" , 0x1180080e0f6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7894" , 0x1180080e0f6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7895" , 0x1180080e0f6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7896" , 0x1180080e0f6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7897" , 0x1180080e0f6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7898" , 0x1180080e0f6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7899" , 0x1180080e0f6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7900" , 0x1180080e0f6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7901" , 0x1180080e0f6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7902" , 0x1180080e0f6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7903" , 0x1180080e0f6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7904" , 0x1180080e0f700ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7905" , 0x1180080e0f708ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7906" , 0x1180080e0f710ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7907" , 0x1180080e0f718ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7908" , 0x1180080e0f720ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7909" , 0x1180080e0f728ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7910" , 0x1180080e0f730ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7911" , 0x1180080e0f738ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7912" , 0x1180080e0f740ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7913" , 0x1180080e0f748ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7914" , 0x1180080e0f750ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7915" , 0x1180080e0f758ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7916" , 0x1180080e0f760ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7917" , 0x1180080e0f768ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7918" , 0x1180080e0f770ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7919" , 0x1180080e0f778ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7920" , 0x1180080e0f780ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7921" , 0x1180080e0f788ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7922" , 0x1180080e0f790ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7923" , 0x1180080e0f798ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7924" , 0x1180080e0f7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7925" , 0x1180080e0f7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7926" , 0x1180080e0f7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7927" , 0x1180080e0f7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7928" , 0x1180080e0f7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7929" , 0x1180080e0f7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7930" , 0x1180080e0f7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7931" , 0x1180080e0f7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7932" , 0x1180080e0f7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7933" , 0x1180080e0f7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7934" , 0x1180080e0f7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7935" , 0x1180080e0f7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7936" , 0x1180080e0f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7937" , 0x1180080e0f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7938" , 0x1180080e0f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7939" , 0x1180080e0f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7940" , 0x1180080e0f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7941" , 0x1180080e0f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7942" , 0x1180080e0f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7943" , 0x1180080e0f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7944" , 0x1180080e0f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7945" , 0x1180080e0f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7946" , 0x1180080e0f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7947" , 0x1180080e0f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7948" , 0x1180080e0f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7949" , 0x1180080e0f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7950" , 0x1180080e0f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7951" , 0x1180080e0f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7952" , 0x1180080e0f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7953" , 0x1180080e0f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7954" , 0x1180080e0f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7955" , 0x1180080e0f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7956" , 0x1180080e0f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7957" , 0x1180080e0f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7958" , 0x1180080e0f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7959" , 0x1180080e0f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7960" , 0x1180080e0f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7961" , 0x1180080e0f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7962" , 0x1180080e0f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7963" , 0x1180080e0f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7964" , 0x1180080e0f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7965" , 0x1180080e0f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7966" , 0x1180080e0f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7967" , 0x1180080e0f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7968" , 0x1180080e0f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7969" , 0x1180080e0f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7970" , 0x1180080e0f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7971" , 0x1180080e0f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7972" , 0x1180080e0f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7973" , 0x1180080e0f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7974" , 0x1180080e0f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7975" , 0x1180080e0f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7976" , 0x1180080e0f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7977" , 0x1180080e0f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7978" , 0x1180080e0f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7979" , 0x1180080e0f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7980" , 0x1180080e0f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7981" , 0x1180080e0f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7982" , 0x1180080e0f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7983" , 0x1180080e0f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7984" , 0x1180080e0f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7985" , 0x1180080e0f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7986" , 0x1180080e0f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7987" , 0x1180080e0f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7988" , 0x1180080e0f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7989" , 0x1180080e0f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7990" , 0x1180080e0f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7991" , 0x1180080e0f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7992" , 0x1180080e0f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7993" , 0x1180080e0f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7994" , 0x1180080e0f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7995" , 0x1180080e0f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7996" , 0x1180080e0f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7997" , 0x1180080e0f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7998" , 0x1180080e0f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP7999" , 0x1180080e0f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8000" , 0x1180080e0fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8001" , 0x1180080e0fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8002" , 0x1180080e0fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8003" , 0x1180080e0fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8004" , 0x1180080e0fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8005" , 0x1180080e0fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8006" , 0x1180080e0fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8007" , 0x1180080e0fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8008" , 0x1180080e0fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8009" , 0x1180080e0fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8010" , 0x1180080e0fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8011" , 0x1180080e0fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8012" , 0x1180080e0fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8013" , 0x1180080e0fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8014" , 0x1180080e0fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8015" , 0x1180080e0fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8016" , 0x1180080e0fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8017" , 0x1180080e0fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8018" , 0x1180080e0fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8019" , 0x1180080e0fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8020" , 0x1180080e0faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8021" , 0x1180080e0faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8022" , 0x1180080e0fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8023" , 0x1180080e0fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8024" , 0x1180080e0fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8025" , 0x1180080e0fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8026" , 0x1180080e0fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8027" , 0x1180080e0fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8028" , 0x1180080e0fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8029" , 0x1180080e0fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8030" , 0x1180080e0faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8031" , 0x1180080e0faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8032" , 0x1180080e0fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8033" , 0x1180080e0fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8034" , 0x1180080e0fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8035" , 0x1180080e0fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8036" , 0x1180080e0fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8037" , 0x1180080e0fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8038" , 0x1180080e0fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8039" , 0x1180080e0fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8040" , 0x1180080e0fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8041" , 0x1180080e0fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8042" , 0x1180080e0fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8043" , 0x1180080e0fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8044" , 0x1180080e0fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8045" , 0x1180080e0fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8046" , 0x1180080e0fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8047" , 0x1180080e0fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8048" , 0x1180080e0fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8049" , 0x1180080e0fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8050" , 0x1180080e0fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8051" , 0x1180080e0fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8052" , 0x1180080e0fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8053" , 0x1180080e0fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8054" , 0x1180080e0fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8055" , 0x1180080e0fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8056" , 0x1180080e0fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8057" , 0x1180080e0fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8058" , 0x1180080e0fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8059" , 0x1180080e0fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8060" , 0x1180080e0fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8061" , 0x1180080e0fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8062" , 0x1180080e0fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8063" , 0x1180080e0fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8064" , 0x1180080e0fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8065" , 0x1180080e0fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8066" , 0x1180080e0fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8067" , 0x1180080e0fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8068" , 0x1180080e0fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8069" , 0x1180080e0fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8070" , 0x1180080e0fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8071" , 0x1180080e0fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8072" , 0x1180080e0fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8073" , 0x1180080e0fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8074" , 0x1180080e0fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8075" , 0x1180080e0fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8076" , 0x1180080e0fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8077" , 0x1180080e0fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8078" , 0x1180080e0fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8079" , 0x1180080e0fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8080" , 0x1180080e0fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8081" , 0x1180080e0fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8082" , 0x1180080e0fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8083" , 0x1180080e0fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8084" , 0x1180080e0fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8085" , 0x1180080e0fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8086" , 0x1180080e0fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8087" , 0x1180080e0fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8088" , 0x1180080e0fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8089" , 0x1180080e0fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8090" , 0x1180080e0fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8091" , 0x1180080e0fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8092" , 0x1180080e0fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8093" , 0x1180080e0fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8094" , 0x1180080e0fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8095" , 0x1180080e0fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8096" , 0x1180080e0fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8097" , 0x1180080e0fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8098" , 0x1180080e0fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8099" , 0x1180080e0fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8100" , 0x1180080e0fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8101" , 0x1180080e0fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8102" , 0x1180080e0fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8103" , 0x1180080e0fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8104" , 0x1180080e0fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8105" , 0x1180080e0fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8106" , 0x1180080e0fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8107" , 0x1180080e0fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8108" , 0x1180080e0fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8109" , 0x1180080e0fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8110" , 0x1180080e0fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8111" , 0x1180080e0fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8112" , 0x1180080e0fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8113" , 0x1180080e0fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8114" , 0x1180080e0fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8115" , 0x1180080e0fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8116" , 0x1180080e0fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8117" , 0x1180080e0fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8118" , 0x1180080e0fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8119" , 0x1180080e0fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8120" , 0x1180080e0fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8121" , 0x1180080e0fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8122" , 0x1180080e0fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8123" , 0x1180080e0fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8124" , 0x1180080e0fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8125" , 0x1180080e0fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8126" , 0x1180080e0fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8127" , 0x1180080e0fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8128" , 0x1180080e0fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8129" , 0x1180080e0fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8130" , 0x1180080e0fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8131" , 0x1180080e0fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8132" , 0x1180080e0fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8133" , 0x1180080e0fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8134" , 0x1180080e0fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8135" , 0x1180080e0fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8136" , 0x1180080e0fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8137" , 0x1180080e0fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8138" , 0x1180080e0fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8139" , 0x1180080e0fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8140" , 0x1180080e0fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8141" , 0x1180080e0fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8142" , 0x1180080e0fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8143" , 0x1180080e0fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8144" , 0x1180080e0fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8145" , 0x1180080e0fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8146" , 0x1180080e0fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8147" , 0x1180080e0fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8148" , 0x1180080e0fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8149" , 0x1180080e0fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8150" , 0x1180080e0feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8151" , 0x1180080e0feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8152" , 0x1180080e0fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8153" , 0x1180080e0fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8154" , 0x1180080e0fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8155" , 0x1180080e0fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8156" , 0x1180080e0fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8157" , 0x1180080e0fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8158" , 0x1180080e0fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8159" , 0x1180080e0fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8160" , 0x1180080e0ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8161" , 0x1180080e0ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8162" , 0x1180080e0ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8163" , 0x1180080e0ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8164" , 0x1180080e0ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8165" , 0x1180080e0ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8166" , 0x1180080e0ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8167" , 0x1180080e0ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8168" , 0x1180080e0ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8169" , 0x1180080e0ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8170" , 0x1180080e0ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8171" , 0x1180080e0ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8172" , 0x1180080e0ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8173" , 0x1180080e0ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8174" , 0x1180080e0ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8175" , 0x1180080e0ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8176" , 0x1180080e0ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8177" , 0x1180080e0ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8178" , 0x1180080e0ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8179" , 0x1180080e0ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8180" , 0x1180080e0ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8181" , 0x1180080e0ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8182" , 0x1180080e0ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8183" , 0x1180080e0ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8184" , 0x1180080e0ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8185" , 0x1180080e0ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8186" , 0x1180080e0ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8187" , 0x1180080e0ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8188" , 0x1180080e0ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8189" , 0x1180080e0ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8190" , 0x1180080e0fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_DUT_MAP8191" , 0x1180080e0fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_ERR_TDT0" , 0x1180080a007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {"L2C_ERR_TDT1" , 0x1180080a407e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {"L2C_ERR_TDT2" , 0x1180080a807e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {"L2C_ERR_TDT3" , 0x1180080ac07e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {"L2C_ERR_TTG0" , 0x1180080a007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
- {"L2C_ERR_TTG1" , 0x1180080a407e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
- {"L2C_ERR_TTG2" , 0x1180080a807e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
- {"L2C_ERR_TTG3" , 0x1180080ac07e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
- {"L2C_ERR_VBF0" , 0x1180080c007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
- {"L2C_ERR_VBF1" , 0x1180080c407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
- {"L2C_ERR_VBF2" , 0x1180080c807f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
- {"L2C_ERR_VBF3" , 0x1180080cc07f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
- {"L2C_ERR_XMC" , 0x11800808007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_INT_ENA" , 0x1180080800020ull, CVMX_CSR_DB_TYPE_RSL, 64, 612},
- {"L2C_INT_REG" , 0x1180080800018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_IOC0_PFC" , 0x1180080800420ull, CVMX_CSR_DB_TYPE_RSL, 64, 614},
- {"L2C_IOR0_PFC" , 0x1180080800428ull, CVMX_CSR_DB_TYPE_RSL, 64, 615},
- {"L2C_QOS_IOB0" , 0x1180080880200ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"L2C_QOS_IOB1" , 0x1180080880208ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"L2C_QOS_PP0" , 0x1180080880000ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP1" , 0x1180080880008ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP2" , 0x1180080880010ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP3" , 0x1180080880018ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP4" , 0x1180080880020ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP5" , 0x1180080880028ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP6" , 0x1180080880030ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP7" , 0x1180080880038ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP8" , 0x1180080880040ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP9" , 0x1180080880048ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP10" , 0x1180080880050ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP11" , 0x1180080880058ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP12" , 0x1180080880060ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP13" , 0x1180080880068ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP14" , 0x1180080880070ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP15" , 0x1180080880078ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP16" , 0x1180080880080ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP17" , 0x1180080880088ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP18" , 0x1180080880090ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP19" , 0x1180080880098ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP20" , 0x11800808800a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP21" , 0x11800808800a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP22" , 0x11800808800b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP23" , 0x11800808800b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP24" , 0x11800808800c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP25" , 0x11800808800c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP26" , 0x11800808800d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP27" , 0x11800808800d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP28" , 0x11800808800e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP29" , 0x11800808800e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP30" , 0x11800808800f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_PP31" , 0x11800808800f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_QOS_WGT" , 0x1180080800008ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
- {"L2C_RSC0_PFC" , 0x1180080800410ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"L2C_RSC1_PFC" , 0x1180080800450ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"L2C_RSC2_PFC" , 0x1180080800490ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"L2C_RSC3_PFC" , 0x11800808004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"L2C_RSD0_PFC" , 0x1180080800418ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"L2C_RSD1_PFC" , 0x1180080800458ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"L2C_RSD2_PFC" , 0x1180080800498ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"L2C_RSD3_PFC" , 0x11800808004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"L2C_TAD0_ECC0" , 0x1180080a00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"L2C_TAD1_ECC0" , 0x1180080a40018ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"L2C_TAD2_ECC0" , 0x1180080a80018ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"L2C_TAD3_ECC0" , 0x1180080ac0018ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"L2C_TAD0_ECC1" , 0x1180080a00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"L2C_TAD1_ECC1" , 0x1180080a40020ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"L2C_TAD2_ECC1" , 0x1180080a80020ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"L2C_TAD3_ECC1" , 0x1180080ac0020ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"L2C_TAD0_IEN" , 0x1180080a00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_TAD1_IEN" , 0x1180080a40000ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_TAD2_IEN" , 0x1180080a80000ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_TAD3_IEN" , 0x1180080ac0000ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_TAD0_INT" , 0x1180080a00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"L2C_TAD1_INT" , 0x1180080a40028ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"L2C_TAD2_INT" , 0x1180080a80028ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"L2C_TAD3_INT" , 0x1180080ac0028ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"L2C_TAD0_PFC0" , 0x1180080a00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"L2C_TAD1_PFC0" , 0x1180080a40400ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"L2C_TAD2_PFC0" , 0x1180080a80400ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"L2C_TAD3_PFC0" , 0x1180080ac0400ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"L2C_TAD0_PFC1" , 0x1180080a00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"L2C_TAD1_PFC1" , 0x1180080a40408ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"L2C_TAD2_PFC1" , 0x1180080a80408ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"L2C_TAD3_PFC1" , 0x1180080ac0408ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"L2C_TAD0_PFC2" , 0x1180080a00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"L2C_TAD1_PFC2" , 0x1180080a40410ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"L2C_TAD2_PFC2" , 0x1180080a80410ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"L2C_TAD3_PFC2" , 0x1180080ac0410ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"L2C_TAD0_PFC3" , 0x1180080a00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"L2C_TAD1_PFC3" , 0x1180080a40418ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"L2C_TAD2_PFC3" , 0x1180080a80418ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"L2C_TAD3_PFC3" , 0x1180080ac0418ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"L2C_TAD0_PRF" , 0x1180080a00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"L2C_TAD1_PRF" , 0x1180080a40008ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"L2C_TAD2_PRF" , 0x1180080a80008ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"L2C_TAD3_PRF" , 0x1180080ac0008ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"L2C_TAD0_TAG" , 0x1180080a00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"L2C_TAD1_TAG" , 0x1180080a40010ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"L2C_TAD2_TAG" , 0x1180080a80010ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"L2C_TAD3_TAG" , 0x1180080ac0010ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"L2C_VER_ID" , 0x11800808007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"L2C_VER_IOB" , 0x11800808007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"L2C_VER_MSC" , 0x11800808007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"L2C_VER_PP" , 0x11800808007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"L2C_VIRTID_IOB0" , 0x11800808c0200ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"L2C_VIRTID_IOB1" , 0x11800808c0208ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"L2C_VIRTID_PP0" , 0x11800808c0000ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP1" , 0x11800808c0008ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP2" , 0x11800808c0010ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP3" , 0x11800808c0018ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP4" , 0x11800808c0020ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP5" , 0x11800808c0028ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP6" , 0x11800808c0030ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP7" , 0x11800808c0038ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP8" , 0x11800808c0040ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP9" , 0x11800808c0048ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP10" , 0x11800808c0050ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP11" , 0x11800808c0058ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP12" , 0x11800808c0060ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP13" , 0x11800808c0068ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP14" , 0x11800808c0070ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP15" , 0x11800808c0078ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP16" , 0x11800808c0080ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP17" , 0x11800808c0088ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP18" , 0x11800808c0090ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP19" , 0x11800808c0098ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP20" , 0x11800808c00a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP21" , 0x11800808c00a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP22" , 0x11800808c00b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP23" , 0x11800808c00b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP24" , 0x11800808c00c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP25" , 0x11800808c00c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP26" , 0x11800808c00d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP27" , 0x11800808c00d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP28" , 0x11800808c00e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP29" , 0x11800808c00e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP30" , 0x11800808c00f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VIRTID_PP31" , 0x11800808c00f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VRT_CTL" , 0x1180080800010ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
- {"L2C_VRT_MEM0" , 0x1180080900000ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1" , 0x1180080900008ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM2" , 0x1180080900010ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM3" , 0x1180080900018ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM4" , 0x1180080900020ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM5" , 0x1180080900028ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM6" , 0x1180080900030ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM7" , 0x1180080900038ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM8" , 0x1180080900040ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM9" , 0x1180080900048ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM10" , 0x1180080900050ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM11" , 0x1180080900058ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM12" , 0x1180080900060ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM13" , 0x1180080900068ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM14" , 0x1180080900070ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM15" , 0x1180080900078ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM16" , 0x1180080900080ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM17" , 0x1180080900088ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM18" , 0x1180080900090ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM19" , 0x1180080900098ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM20" , 0x11800809000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM21" , 0x11800809000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM22" , 0x11800809000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM23" , 0x11800809000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM24" , 0x11800809000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM25" , 0x11800809000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM26" , 0x11800809000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM27" , 0x11800809000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM28" , 0x11800809000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM29" , 0x11800809000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM30" , 0x11800809000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM31" , 0x11800809000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM32" , 0x1180080900100ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM33" , 0x1180080900108ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM34" , 0x1180080900110ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM35" , 0x1180080900118ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM36" , 0x1180080900120ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM37" , 0x1180080900128ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM38" , 0x1180080900130ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM39" , 0x1180080900138ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM40" , 0x1180080900140ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM41" , 0x1180080900148ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM42" , 0x1180080900150ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM43" , 0x1180080900158ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM44" , 0x1180080900160ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM45" , 0x1180080900168ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM46" , 0x1180080900170ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM47" , 0x1180080900178ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM48" , 0x1180080900180ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM49" , 0x1180080900188ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM50" , 0x1180080900190ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM51" , 0x1180080900198ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM52" , 0x11800809001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM53" , 0x11800809001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM54" , 0x11800809001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM55" , 0x11800809001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM56" , 0x11800809001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM57" , 0x11800809001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM58" , 0x11800809001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM59" , 0x11800809001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM60" , 0x11800809001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM61" , 0x11800809001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM62" , 0x11800809001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM63" , 0x11800809001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM64" , 0x1180080900200ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM65" , 0x1180080900208ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM66" , 0x1180080900210ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM67" , 0x1180080900218ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM68" , 0x1180080900220ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM69" , 0x1180080900228ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM70" , 0x1180080900230ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM71" , 0x1180080900238ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM72" , 0x1180080900240ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM73" , 0x1180080900248ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM74" , 0x1180080900250ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM75" , 0x1180080900258ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM76" , 0x1180080900260ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM77" , 0x1180080900268ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM78" , 0x1180080900270ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM79" , 0x1180080900278ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM80" , 0x1180080900280ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM81" , 0x1180080900288ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM82" , 0x1180080900290ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM83" , 0x1180080900298ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM84" , 0x11800809002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM85" , 0x11800809002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM86" , 0x11800809002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM87" , 0x11800809002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM88" , 0x11800809002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM89" , 0x11800809002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM90" , 0x11800809002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM91" , 0x11800809002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM92" , 0x11800809002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM93" , 0x11800809002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM94" , 0x11800809002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM95" , 0x11800809002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM96" , 0x1180080900300ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM97" , 0x1180080900308ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM98" , 0x1180080900310ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM99" , 0x1180080900318ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM100" , 0x1180080900320ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM101" , 0x1180080900328ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM102" , 0x1180080900330ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM103" , 0x1180080900338ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM104" , 0x1180080900340ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM105" , 0x1180080900348ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM106" , 0x1180080900350ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM107" , 0x1180080900358ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM108" , 0x1180080900360ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM109" , 0x1180080900368ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM110" , 0x1180080900370ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM111" , 0x1180080900378ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM112" , 0x1180080900380ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM113" , 0x1180080900388ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM114" , 0x1180080900390ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM115" , 0x1180080900398ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM116" , 0x11800809003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM117" , 0x11800809003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM118" , 0x11800809003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM119" , 0x11800809003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM120" , 0x11800809003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM121" , 0x11800809003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM122" , 0x11800809003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM123" , 0x11800809003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM124" , 0x11800809003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM125" , 0x11800809003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM126" , 0x11800809003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM127" , 0x11800809003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM128" , 0x1180080900400ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM129" , 0x1180080900408ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM130" , 0x1180080900410ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM131" , 0x1180080900418ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM132" , 0x1180080900420ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM133" , 0x1180080900428ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM134" , 0x1180080900430ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM135" , 0x1180080900438ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM136" , 0x1180080900440ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM137" , 0x1180080900448ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM138" , 0x1180080900450ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM139" , 0x1180080900458ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM140" , 0x1180080900460ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM141" , 0x1180080900468ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM142" , 0x1180080900470ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM143" , 0x1180080900478ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM144" , 0x1180080900480ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM145" , 0x1180080900488ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM146" , 0x1180080900490ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM147" , 0x1180080900498ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM148" , 0x11800809004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM149" , 0x11800809004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM150" , 0x11800809004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM151" , 0x11800809004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM152" , 0x11800809004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM153" , 0x11800809004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM154" , 0x11800809004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM155" , 0x11800809004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM156" , 0x11800809004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM157" , 0x11800809004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM158" , 0x11800809004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM159" , 0x11800809004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM160" , 0x1180080900500ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM161" , 0x1180080900508ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM162" , 0x1180080900510ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM163" , 0x1180080900518ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM164" , 0x1180080900520ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM165" , 0x1180080900528ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM166" , 0x1180080900530ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM167" , 0x1180080900538ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM168" , 0x1180080900540ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM169" , 0x1180080900548ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM170" , 0x1180080900550ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM171" , 0x1180080900558ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM172" , 0x1180080900560ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM173" , 0x1180080900568ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM174" , 0x1180080900570ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM175" , 0x1180080900578ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM176" , 0x1180080900580ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM177" , 0x1180080900588ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM178" , 0x1180080900590ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM179" , 0x1180080900598ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM180" , 0x11800809005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM181" , 0x11800809005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM182" , 0x11800809005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM183" , 0x11800809005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM184" , 0x11800809005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM185" , 0x11800809005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM186" , 0x11800809005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM187" , 0x11800809005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM188" , 0x11800809005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM189" , 0x11800809005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM190" , 0x11800809005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM191" , 0x11800809005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM192" , 0x1180080900600ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM193" , 0x1180080900608ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM194" , 0x1180080900610ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM195" , 0x1180080900618ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM196" , 0x1180080900620ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM197" , 0x1180080900628ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM198" , 0x1180080900630ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM199" , 0x1180080900638ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM200" , 0x1180080900640ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM201" , 0x1180080900648ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM202" , 0x1180080900650ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM203" , 0x1180080900658ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM204" , 0x1180080900660ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM205" , 0x1180080900668ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM206" , 0x1180080900670ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM207" , 0x1180080900678ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM208" , 0x1180080900680ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM209" , 0x1180080900688ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM210" , 0x1180080900690ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM211" , 0x1180080900698ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM212" , 0x11800809006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM213" , 0x11800809006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM214" , 0x11800809006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM215" , 0x11800809006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM216" , 0x11800809006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM217" , 0x11800809006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM218" , 0x11800809006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM219" , 0x11800809006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM220" , 0x11800809006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM221" , 0x11800809006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM222" , 0x11800809006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM223" , 0x11800809006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM224" , 0x1180080900700ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM225" , 0x1180080900708ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM226" , 0x1180080900710ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM227" , 0x1180080900718ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM228" , 0x1180080900720ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM229" , 0x1180080900728ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM230" , 0x1180080900730ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM231" , 0x1180080900738ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM232" , 0x1180080900740ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM233" , 0x1180080900748ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM234" , 0x1180080900750ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM235" , 0x1180080900758ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM236" , 0x1180080900760ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM237" , 0x1180080900768ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM238" , 0x1180080900770ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM239" , 0x1180080900778ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM240" , 0x1180080900780ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM241" , 0x1180080900788ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM242" , 0x1180080900790ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM243" , 0x1180080900798ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM244" , 0x11800809007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM245" , 0x11800809007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM246" , 0x11800809007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM247" , 0x11800809007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM248" , 0x11800809007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM249" , 0x11800809007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM250" , 0x11800809007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM251" , 0x11800809007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM252" , 0x11800809007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM253" , 0x11800809007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM254" , 0x11800809007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM255" , 0x11800809007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM256" , 0x1180080900800ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM257" , 0x1180080900808ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM258" , 0x1180080900810ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM259" , 0x1180080900818ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM260" , 0x1180080900820ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM261" , 0x1180080900828ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM262" , 0x1180080900830ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM263" , 0x1180080900838ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM264" , 0x1180080900840ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM265" , 0x1180080900848ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM266" , 0x1180080900850ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM267" , 0x1180080900858ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM268" , 0x1180080900860ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM269" , 0x1180080900868ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM270" , 0x1180080900870ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM271" , 0x1180080900878ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM272" , 0x1180080900880ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM273" , 0x1180080900888ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM274" , 0x1180080900890ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM275" , 0x1180080900898ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM276" , 0x11800809008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM277" , 0x11800809008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM278" , 0x11800809008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM279" , 0x11800809008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM280" , 0x11800809008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM281" , 0x11800809008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM282" , 0x11800809008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM283" , 0x11800809008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM284" , 0x11800809008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM285" , 0x11800809008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM286" , 0x11800809008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM287" , 0x11800809008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM288" , 0x1180080900900ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM289" , 0x1180080900908ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM290" , 0x1180080900910ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM291" , 0x1180080900918ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM292" , 0x1180080900920ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM293" , 0x1180080900928ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM294" , 0x1180080900930ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM295" , 0x1180080900938ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM296" , 0x1180080900940ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM297" , 0x1180080900948ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM298" , 0x1180080900950ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM299" , 0x1180080900958ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM300" , 0x1180080900960ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM301" , 0x1180080900968ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM302" , 0x1180080900970ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM303" , 0x1180080900978ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM304" , 0x1180080900980ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM305" , 0x1180080900988ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM306" , 0x1180080900990ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM307" , 0x1180080900998ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM308" , 0x11800809009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM309" , 0x11800809009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM310" , 0x11800809009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM311" , 0x11800809009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM312" , 0x11800809009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM313" , 0x11800809009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM314" , 0x11800809009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM315" , 0x11800809009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM316" , 0x11800809009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM317" , 0x11800809009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM318" , 0x11800809009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM319" , 0x11800809009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM320" , 0x1180080900a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM321" , 0x1180080900a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM322" , 0x1180080900a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM323" , 0x1180080900a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM324" , 0x1180080900a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM325" , 0x1180080900a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM326" , 0x1180080900a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM327" , 0x1180080900a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM328" , 0x1180080900a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM329" , 0x1180080900a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM330" , 0x1180080900a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM331" , 0x1180080900a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM332" , 0x1180080900a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM333" , 0x1180080900a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM334" , 0x1180080900a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM335" , 0x1180080900a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM336" , 0x1180080900a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM337" , 0x1180080900a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM338" , 0x1180080900a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM339" , 0x1180080900a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM340" , 0x1180080900aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM341" , 0x1180080900aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM342" , 0x1180080900ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM343" , 0x1180080900ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM344" , 0x1180080900ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM345" , 0x1180080900ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM346" , 0x1180080900ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM347" , 0x1180080900ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM348" , 0x1180080900ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM349" , 0x1180080900ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM350" , 0x1180080900af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM351" , 0x1180080900af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM352" , 0x1180080900b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM353" , 0x1180080900b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM354" , 0x1180080900b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM355" , 0x1180080900b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM356" , 0x1180080900b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM357" , 0x1180080900b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM358" , 0x1180080900b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM359" , 0x1180080900b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM360" , 0x1180080900b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM361" , 0x1180080900b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM362" , 0x1180080900b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM363" , 0x1180080900b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM364" , 0x1180080900b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM365" , 0x1180080900b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM366" , 0x1180080900b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM367" , 0x1180080900b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM368" , 0x1180080900b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM369" , 0x1180080900b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM370" , 0x1180080900b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM371" , 0x1180080900b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM372" , 0x1180080900ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM373" , 0x1180080900ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM374" , 0x1180080900bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM375" , 0x1180080900bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM376" , 0x1180080900bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM377" , 0x1180080900bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM378" , 0x1180080900bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM379" , 0x1180080900bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM380" , 0x1180080900be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM381" , 0x1180080900be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM382" , 0x1180080900bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM383" , 0x1180080900bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM384" , 0x1180080900c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM385" , 0x1180080900c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM386" , 0x1180080900c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM387" , 0x1180080900c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM388" , 0x1180080900c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM389" , 0x1180080900c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM390" , 0x1180080900c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM391" , 0x1180080900c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM392" , 0x1180080900c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM393" , 0x1180080900c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM394" , 0x1180080900c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM395" , 0x1180080900c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM396" , 0x1180080900c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM397" , 0x1180080900c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM398" , 0x1180080900c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM399" , 0x1180080900c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM400" , 0x1180080900c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM401" , 0x1180080900c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM402" , 0x1180080900c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM403" , 0x1180080900c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM404" , 0x1180080900ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM405" , 0x1180080900ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM406" , 0x1180080900cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM407" , 0x1180080900cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM408" , 0x1180080900cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM409" , 0x1180080900cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM410" , 0x1180080900cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM411" , 0x1180080900cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM412" , 0x1180080900ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM413" , 0x1180080900ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM414" , 0x1180080900cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM415" , 0x1180080900cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM416" , 0x1180080900d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM417" , 0x1180080900d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM418" , 0x1180080900d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM419" , 0x1180080900d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM420" , 0x1180080900d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM421" , 0x1180080900d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM422" , 0x1180080900d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM423" , 0x1180080900d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM424" , 0x1180080900d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM425" , 0x1180080900d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM426" , 0x1180080900d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM427" , 0x1180080900d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM428" , 0x1180080900d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM429" , 0x1180080900d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM430" , 0x1180080900d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM431" , 0x1180080900d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM432" , 0x1180080900d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM433" , 0x1180080900d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM434" , 0x1180080900d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM435" , 0x1180080900d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM436" , 0x1180080900da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM437" , 0x1180080900da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM438" , 0x1180080900db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM439" , 0x1180080900db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM440" , 0x1180080900dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM441" , 0x1180080900dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM442" , 0x1180080900dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM443" , 0x1180080900dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM444" , 0x1180080900de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM445" , 0x1180080900de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM446" , 0x1180080900df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM447" , 0x1180080900df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM448" , 0x1180080900e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM449" , 0x1180080900e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM450" , 0x1180080900e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM451" , 0x1180080900e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM452" , 0x1180080900e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM453" , 0x1180080900e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM454" , 0x1180080900e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM455" , 0x1180080900e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM456" , 0x1180080900e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM457" , 0x1180080900e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM458" , 0x1180080900e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM459" , 0x1180080900e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM460" , 0x1180080900e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM461" , 0x1180080900e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM462" , 0x1180080900e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM463" , 0x1180080900e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM464" , 0x1180080900e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM465" , 0x1180080900e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM466" , 0x1180080900e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM467" , 0x1180080900e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM468" , 0x1180080900ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM469" , 0x1180080900ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM470" , 0x1180080900eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM471" , 0x1180080900eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM472" , 0x1180080900ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM473" , 0x1180080900ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM474" , 0x1180080900ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM475" , 0x1180080900ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM476" , 0x1180080900ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM477" , 0x1180080900ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM478" , 0x1180080900ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM479" , 0x1180080900ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM480" , 0x1180080900f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM481" , 0x1180080900f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM482" , 0x1180080900f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM483" , 0x1180080900f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM484" , 0x1180080900f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM485" , 0x1180080900f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM486" , 0x1180080900f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM487" , 0x1180080900f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM488" , 0x1180080900f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM489" , 0x1180080900f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM490" , 0x1180080900f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM491" , 0x1180080900f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM492" , 0x1180080900f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM493" , 0x1180080900f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM494" , 0x1180080900f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM495" , 0x1180080900f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM496" , 0x1180080900f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM497" , 0x1180080900f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM498" , 0x1180080900f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM499" , 0x1180080900f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM500" , 0x1180080900fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM501" , 0x1180080900fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM502" , 0x1180080900fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM503" , 0x1180080900fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM504" , 0x1180080900fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM505" , 0x1180080900fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM506" , 0x1180080900fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM507" , 0x1180080900fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM508" , 0x1180080900fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM509" , 0x1180080900fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM510" , 0x1180080900ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM511" , 0x1180080900ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM512" , 0x1180080901000ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM513" , 0x1180080901008ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM514" , 0x1180080901010ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM515" , 0x1180080901018ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM516" , 0x1180080901020ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM517" , 0x1180080901028ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM518" , 0x1180080901030ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM519" , 0x1180080901038ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM520" , 0x1180080901040ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM521" , 0x1180080901048ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM522" , 0x1180080901050ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM523" , 0x1180080901058ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM524" , 0x1180080901060ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM525" , 0x1180080901068ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM526" , 0x1180080901070ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM527" , 0x1180080901078ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM528" , 0x1180080901080ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM529" , 0x1180080901088ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM530" , 0x1180080901090ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM531" , 0x1180080901098ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM532" , 0x11800809010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM533" , 0x11800809010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM534" , 0x11800809010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM535" , 0x11800809010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM536" , 0x11800809010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM537" , 0x11800809010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM538" , 0x11800809010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM539" , 0x11800809010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM540" , 0x11800809010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM541" , 0x11800809010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM542" , 0x11800809010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM543" , 0x11800809010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM544" , 0x1180080901100ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM545" , 0x1180080901108ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM546" , 0x1180080901110ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM547" , 0x1180080901118ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM548" , 0x1180080901120ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM549" , 0x1180080901128ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM550" , 0x1180080901130ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM551" , 0x1180080901138ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM552" , 0x1180080901140ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM553" , 0x1180080901148ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM554" , 0x1180080901150ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM555" , 0x1180080901158ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM556" , 0x1180080901160ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM557" , 0x1180080901168ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM558" , 0x1180080901170ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM559" , 0x1180080901178ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM560" , 0x1180080901180ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM561" , 0x1180080901188ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM562" , 0x1180080901190ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM563" , 0x1180080901198ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM564" , 0x11800809011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM565" , 0x11800809011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM566" , 0x11800809011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM567" , 0x11800809011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM568" , 0x11800809011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM569" , 0x11800809011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM570" , 0x11800809011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM571" , 0x11800809011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM572" , 0x11800809011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM573" , 0x11800809011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM574" , 0x11800809011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM575" , 0x11800809011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM576" , 0x1180080901200ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM577" , 0x1180080901208ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM578" , 0x1180080901210ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM579" , 0x1180080901218ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM580" , 0x1180080901220ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM581" , 0x1180080901228ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM582" , 0x1180080901230ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM583" , 0x1180080901238ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM584" , 0x1180080901240ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM585" , 0x1180080901248ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM586" , 0x1180080901250ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM587" , 0x1180080901258ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM588" , 0x1180080901260ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM589" , 0x1180080901268ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM590" , 0x1180080901270ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM591" , 0x1180080901278ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM592" , 0x1180080901280ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM593" , 0x1180080901288ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM594" , 0x1180080901290ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM595" , 0x1180080901298ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM596" , 0x11800809012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM597" , 0x11800809012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM598" , 0x11800809012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM599" , 0x11800809012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM600" , 0x11800809012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM601" , 0x11800809012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM602" , 0x11800809012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM603" , 0x11800809012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM604" , 0x11800809012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM605" , 0x11800809012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM606" , 0x11800809012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM607" , 0x11800809012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM608" , 0x1180080901300ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM609" , 0x1180080901308ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM610" , 0x1180080901310ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM611" , 0x1180080901318ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM612" , 0x1180080901320ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM613" , 0x1180080901328ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM614" , 0x1180080901330ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM615" , 0x1180080901338ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM616" , 0x1180080901340ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM617" , 0x1180080901348ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM618" , 0x1180080901350ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM619" , 0x1180080901358ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM620" , 0x1180080901360ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM621" , 0x1180080901368ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM622" , 0x1180080901370ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM623" , 0x1180080901378ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM624" , 0x1180080901380ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM625" , 0x1180080901388ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM626" , 0x1180080901390ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM627" , 0x1180080901398ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM628" , 0x11800809013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM629" , 0x11800809013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM630" , 0x11800809013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM631" , 0x11800809013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM632" , 0x11800809013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM633" , 0x11800809013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM634" , 0x11800809013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM635" , 0x11800809013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM636" , 0x11800809013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM637" , 0x11800809013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM638" , 0x11800809013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM639" , 0x11800809013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM640" , 0x1180080901400ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM641" , 0x1180080901408ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM642" , 0x1180080901410ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM643" , 0x1180080901418ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM644" , 0x1180080901420ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM645" , 0x1180080901428ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM646" , 0x1180080901430ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM647" , 0x1180080901438ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM648" , 0x1180080901440ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM649" , 0x1180080901448ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM650" , 0x1180080901450ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM651" , 0x1180080901458ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM652" , 0x1180080901460ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM653" , 0x1180080901468ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM654" , 0x1180080901470ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM655" , 0x1180080901478ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM656" , 0x1180080901480ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM657" , 0x1180080901488ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM658" , 0x1180080901490ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM659" , 0x1180080901498ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM660" , 0x11800809014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM661" , 0x11800809014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM662" , 0x11800809014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM663" , 0x11800809014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM664" , 0x11800809014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM665" , 0x11800809014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM666" , 0x11800809014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM667" , 0x11800809014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM668" , 0x11800809014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM669" , 0x11800809014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM670" , 0x11800809014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM671" , 0x11800809014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM672" , 0x1180080901500ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM673" , 0x1180080901508ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM674" , 0x1180080901510ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM675" , 0x1180080901518ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM676" , 0x1180080901520ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM677" , 0x1180080901528ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM678" , 0x1180080901530ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM679" , 0x1180080901538ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM680" , 0x1180080901540ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM681" , 0x1180080901548ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM682" , 0x1180080901550ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM683" , 0x1180080901558ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM684" , 0x1180080901560ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM685" , 0x1180080901568ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM686" , 0x1180080901570ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM687" , 0x1180080901578ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM688" , 0x1180080901580ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM689" , 0x1180080901588ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM690" , 0x1180080901590ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM691" , 0x1180080901598ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM692" , 0x11800809015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM693" , 0x11800809015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM694" , 0x11800809015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM695" , 0x11800809015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM696" , 0x11800809015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM697" , 0x11800809015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM698" , 0x11800809015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM699" , 0x11800809015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM700" , 0x11800809015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM701" , 0x11800809015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM702" , 0x11800809015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM703" , 0x11800809015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM704" , 0x1180080901600ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM705" , 0x1180080901608ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM706" , 0x1180080901610ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM707" , 0x1180080901618ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM708" , 0x1180080901620ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM709" , 0x1180080901628ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM710" , 0x1180080901630ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM711" , 0x1180080901638ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM712" , 0x1180080901640ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM713" , 0x1180080901648ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM714" , 0x1180080901650ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM715" , 0x1180080901658ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM716" , 0x1180080901660ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM717" , 0x1180080901668ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM718" , 0x1180080901670ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM719" , 0x1180080901678ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM720" , 0x1180080901680ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM721" , 0x1180080901688ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM722" , 0x1180080901690ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM723" , 0x1180080901698ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM724" , 0x11800809016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM725" , 0x11800809016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM726" , 0x11800809016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM727" , 0x11800809016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM728" , 0x11800809016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM729" , 0x11800809016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM730" , 0x11800809016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM731" , 0x11800809016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM732" , 0x11800809016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM733" , 0x11800809016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM734" , 0x11800809016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM735" , 0x11800809016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM736" , 0x1180080901700ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM737" , 0x1180080901708ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM738" , 0x1180080901710ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM739" , 0x1180080901718ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM740" , 0x1180080901720ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM741" , 0x1180080901728ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM742" , 0x1180080901730ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM743" , 0x1180080901738ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM744" , 0x1180080901740ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM745" , 0x1180080901748ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM746" , 0x1180080901750ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM747" , 0x1180080901758ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM748" , 0x1180080901760ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM749" , 0x1180080901768ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM750" , 0x1180080901770ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM751" , 0x1180080901778ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM752" , 0x1180080901780ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM753" , 0x1180080901788ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM754" , 0x1180080901790ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM755" , 0x1180080901798ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM756" , 0x11800809017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM757" , 0x11800809017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM758" , 0x11800809017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM759" , 0x11800809017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM760" , 0x11800809017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM761" , 0x11800809017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM762" , 0x11800809017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM763" , 0x11800809017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM764" , 0x11800809017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM765" , 0x11800809017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM766" , 0x11800809017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM767" , 0x11800809017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM768" , 0x1180080901800ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM769" , 0x1180080901808ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM770" , 0x1180080901810ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM771" , 0x1180080901818ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM772" , 0x1180080901820ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM773" , 0x1180080901828ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM774" , 0x1180080901830ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM775" , 0x1180080901838ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM776" , 0x1180080901840ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM777" , 0x1180080901848ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM778" , 0x1180080901850ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM779" , 0x1180080901858ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM780" , 0x1180080901860ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM781" , 0x1180080901868ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM782" , 0x1180080901870ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM783" , 0x1180080901878ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM784" , 0x1180080901880ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM785" , 0x1180080901888ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM786" , 0x1180080901890ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM787" , 0x1180080901898ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM788" , 0x11800809018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM789" , 0x11800809018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM790" , 0x11800809018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM791" , 0x11800809018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM792" , 0x11800809018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM793" , 0x11800809018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM794" , 0x11800809018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM795" , 0x11800809018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM796" , 0x11800809018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM797" , 0x11800809018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM798" , 0x11800809018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM799" , 0x11800809018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM800" , 0x1180080901900ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM801" , 0x1180080901908ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM802" , 0x1180080901910ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM803" , 0x1180080901918ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM804" , 0x1180080901920ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM805" , 0x1180080901928ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM806" , 0x1180080901930ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM807" , 0x1180080901938ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM808" , 0x1180080901940ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM809" , 0x1180080901948ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM810" , 0x1180080901950ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM811" , 0x1180080901958ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM812" , 0x1180080901960ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM813" , 0x1180080901968ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM814" , 0x1180080901970ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM815" , 0x1180080901978ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM816" , 0x1180080901980ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM817" , 0x1180080901988ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM818" , 0x1180080901990ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM819" , 0x1180080901998ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM820" , 0x11800809019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM821" , 0x11800809019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM822" , 0x11800809019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM823" , 0x11800809019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM824" , 0x11800809019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM825" , 0x11800809019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM826" , 0x11800809019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM827" , 0x11800809019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM828" , 0x11800809019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM829" , 0x11800809019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM830" , 0x11800809019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM831" , 0x11800809019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM832" , 0x1180080901a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM833" , 0x1180080901a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM834" , 0x1180080901a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM835" , 0x1180080901a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM836" , 0x1180080901a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM837" , 0x1180080901a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM838" , 0x1180080901a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM839" , 0x1180080901a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM840" , 0x1180080901a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM841" , 0x1180080901a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM842" , 0x1180080901a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM843" , 0x1180080901a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM844" , 0x1180080901a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM845" , 0x1180080901a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM846" , 0x1180080901a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM847" , 0x1180080901a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM848" , 0x1180080901a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM849" , 0x1180080901a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM850" , 0x1180080901a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM851" , 0x1180080901a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM852" , 0x1180080901aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM853" , 0x1180080901aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM854" , 0x1180080901ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM855" , 0x1180080901ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM856" , 0x1180080901ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM857" , 0x1180080901ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM858" , 0x1180080901ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM859" , 0x1180080901ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM860" , 0x1180080901ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM861" , 0x1180080901ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM862" , 0x1180080901af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM863" , 0x1180080901af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM864" , 0x1180080901b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM865" , 0x1180080901b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM866" , 0x1180080901b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM867" , 0x1180080901b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM868" , 0x1180080901b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM869" , 0x1180080901b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM870" , 0x1180080901b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM871" , 0x1180080901b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM872" , 0x1180080901b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM873" , 0x1180080901b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM874" , 0x1180080901b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM875" , 0x1180080901b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM876" , 0x1180080901b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM877" , 0x1180080901b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM878" , 0x1180080901b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM879" , 0x1180080901b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM880" , 0x1180080901b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM881" , 0x1180080901b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM882" , 0x1180080901b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM883" , 0x1180080901b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM884" , 0x1180080901ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM885" , 0x1180080901ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM886" , 0x1180080901bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM887" , 0x1180080901bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM888" , 0x1180080901bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM889" , 0x1180080901bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM890" , 0x1180080901bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM891" , 0x1180080901bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM892" , 0x1180080901be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM893" , 0x1180080901be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM894" , 0x1180080901bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM895" , 0x1180080901bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM896" , 0x1180080901c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM897" , 0x1180080901c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM898" , 0x1180080901c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM899" , 0x1180080901c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM900" , 0x1180080901c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM901" , 0x1180080901c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM902" , 0x1180080901c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM903" , 0x1180080901c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM904" , 0x1180080901c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM905" , 0x1180080901c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM906" , 0x1180080901c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM907" , 0x1180080901c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM908" , 0x1180080901c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM909" , 0x1180080901c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM910" , 0x1180080901c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM911" , 0x1180080901c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM912" , 0x1180080901c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM913" , 0x1180080901c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM914" , 0x1180080901c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM915" , 0x1180080901c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM916" , 0x1180080901ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM917" , 0x1180080901ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM918" , 0x1180080901cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM919" , 0x1180080901cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM920" , 0x1180080901cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM921" , 0x1180080901cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM922" , 0x1180080901cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM923" , 0x1180080901cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM924" , 0x1180080901ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM925" , 0x1180080901ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM926" , 0x1180080901cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM927" , 0x1180080901cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM928" , 0x1180080901d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM929" , 0x1180080901d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM930" , 0x1180080901d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM931" , 0x1180080901d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM932" , 0x1180080901d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM933" , 0x1180080901d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM934" , 0x1180080901d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM935" , 0x1180080901d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM936" , 0x1180080901d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM937" , 0x1180080901d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM938" , 0x1180080901d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM939" , 0x1180080901d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM940" , 0x1180080901d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM941" , 0x1180080901d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM942" , 0x1180080901d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM943" , 0x1180080901d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM944" , 0x1180080901d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM945" , 0x1180080901d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM946" , 0x1180080901d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM947" , 0x1180080901d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM948" , 0x1180080901da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM949" , 0x1180080901da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM950" , 0x1180080901db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM951" , 0x1180080901db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM952" , 0x1180080901dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM953" , 0x1180080901dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM954" , 0x1180080901dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM955" , 0x1180080901dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM956" , 0x1180080901de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM957" , 0x1180080901de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM958" , 0x1180080901df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM959" , 0x1180080901df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM960" , 0x1180080901e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM961" , 0x1180080901e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM962" , 0x1180080901e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM963" , 0x1180080901e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM964" , 0x1180080901e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM965" , 0x1180080901e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM966" , 0x1180080901e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM967" , 0x1180080901e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM968" , 0x1180080901e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM969" , 0x1180080901e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM970" , 0x1180080901e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM971" , 0x1180080901e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM972" , 0x1180080901e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM973" , 0x1180080901e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM974" , 0x1180080901e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM975" , 0x1180080901e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM976" , 0x1180080901e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM977" , 0x1180080901e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM978" , 0x1180080901e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM979" , 0x1180080901e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM980" , 0x1180080901ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM981" , 0x1180080901ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM982" , 0x1180080901eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM983" , 0x1180080901eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM984" , 0x1180080901ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM985" , 0x1180080901ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM986" , 0x1180080901ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM987" , 0x1180080901ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM988" , 0x1180080901ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM989" , 0x1180080901ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM990" , 0x1180080901ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM991" , 0x1180080901ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM992" , 0x1180080901f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM993" , 0x1180080901f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM994" , 0x1180080901f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM995" , 0x1180080901f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM996" , 0x1180080901f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM997" , 0x1180080901f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM998" , 0x1180080901f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM999" , 0x1180080901f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1000" , 0x1180080901f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1001" , 0x1180080901f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1002" , 0x1180080901f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1003" , 0x1180080901f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1004" , 0x1180080901f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1005" , 0x1180080901f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1006" , 0x1180080901f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1007" , 0x1180080901f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1008" , 0x1180080901f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1009" , 0x1180080901f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1010" , 0x1180080901f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1011" , 0x1180080901f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1012" , 0x1180080901fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1013" , 0x1180080901fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1014" , 0x1180080901fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1015" , 0x1180080901fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1016" , 0x1180080901fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1017" , 0x1180080901fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1018" , 0x1180080901fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1019" , 0x1180080901fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1020" , 0x1180080901fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1021" , 0x1180080901fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1022" , 0x1180080901ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VRT_MEM1023" , 0x1180080901ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_WPAR_IOB0" , 0x1180080840200ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
- {"L2C_WPAR_IOB1" , 0x1180080840208ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
- {"L2C_WPAR_PP0" , 0x1180080840000ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP1" , 0x1180080840008ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP2" , 0x1180080840010ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP3" , 0x1180080840018ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP4" , 0x1180080840020ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP5" , 0x1180080840028ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP6" , 0x1180080840030ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP7" , 0x1180080840038ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP8" , 0x1180080840040ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP9" , 0x1180080840048ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP10" , 0x1180080840050ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP11" , 0x1180080840058ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP12" , 0x1180080840060ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP13" , 0x1180080840068ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP14" , 0x1180080840070ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP15" , 0x1180080840078ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP16" , 0x1180080840080ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP17" , 0x1180080840088ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP18" , 0x1180080840090ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP19" , 0x1180080840098ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP20" , 0x11800808400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP21" , 0x11800808400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP22" , 0x11800808400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP23" , 0x11800808400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP24" , 0x11800808400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP25" , 0x11800808400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP26" , 0x11800808400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP27" , 0x11800808400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP28" , 0x11800808400e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP29" , 0x11800808400e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP30" , 0x11800808400f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_WPAR_PP31" , 0x11800808400f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_XMC0_PFC" , 0x1180080800400ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"L2C_XMC1_PFC" , 0x1180080800440ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"L2C_XMC2_PFC" , 0x1180080800480ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"L2C_XMC3_PFC" , 0x11800808004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"L2C_XMC_CMD" , 0x1180080800028ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_XMD0_PFC" , 0x1180080800408ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
- {"L2C_XMD1_PFC" , 0x1180080800448ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
- {"L2C_XMD2_PFC" , 0x1180080800488ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
- {"L2C_XMD3_PFC" , 0x11800808004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
- {"LMC0_CHAR_CTL" , 0x1180088000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"LMC1_CHAR_CTL" , 0x1180089000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"LMC2_CHAR_CTL" , 0x118008a000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"LMC3_CHAR_CTL" , 0x118008b000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"LMC0_CHAR_MASK0" , 0x1180088000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"LMC1_CHAR_MASK0" , 0x1180089000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"LMC2_CHAR_MASK0" , 0x118008a000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"LMC3_CHAR_MASK0" , 0x118008b000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"LMC0_CHAR_MASK1" , 0x1180088000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"LMC1_CHAR_MASK1" , 0x1180089000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"LMC2_CHAR_MASK1" , 0x118008a000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"LMC3_CHAR_MASK1" , 0x118008b000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"LMC0_CHAR_MASK2" , 0x1180088000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"LMC1_CHAR_MASK2" , 0x1180089000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"LMC2_CHAR_MASK2" , 0x118008a000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"LMC3_CHAR_MASK2" , 0x118008b000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"LMC0_CHAR_MASK3" , 0x1180088000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
- {"LMC1_CHAR_MASK3" , 0x1180089000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
- {"LMC2_CHAR_MASK3" , 0x118008a000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
- {"LMC3_CHAR_MASK3" , 0x118008b000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
- {"LMC0_CHAR_MASK4" , 0x1180088000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"LMC1_CHAR_MASK4" , 0x1180089000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"LMC2_CHAR_MASK4" , 0x118008a000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"LMC3_CHAR_MASK4" , 0x118008b000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"LMC0_COMP_CTL2" , 0x11800880001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"LMC1_COMP_CTL2" , 0x11800890001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"LMC2_COMP_CTL2" , 0x118008a0001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"LMC3_COMP_CTL2" , 0x118008b0001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"LMC0_CONFIG" , 0x1180088000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"LMC1_CONFIG" , 0x1180089000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"LMC2_CONFIG" , 0x118008a000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"LMC3_CONFIG" , 0x118008b000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"LMC0_CONTROL" , 0x1180088000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"LMC1_CONTROL" , 0x1180089000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"LMC2_CONTROL" , 0x118008a000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"LMC3_CONTROL" , 0x118008b000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"LMC0_DCLK_CNT" , 0x11800880001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"LMC1_DCLK_CNT" , 0x11800890001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"LMC2_DCLK_CNT" , 0x118008a0001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"LMC3_DCLK_CNT" , 0x118008b0001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"LMC0_DDR_PLL_CTL" , 0x1180088000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"LMC1_DDR_PLL_CTL" , 0x1180089000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"LMC2_DDR_PLL_CTL" , 0x118008a000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"LMC3_DDR_PLL_CTL" , 0x118008b000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"LMC0_DIMM000_PARAMS" , 0x1180088000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC0_DIMM001_PARAMS" , 0x1180088000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC1_DIMM000_PARAMS" , 0x1180089000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC1_DIMM001_PARAMS" , 0x1180089000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC2_DIMM000_PARAMS" , 0x118008a000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC2_DIMM001_PARAMS" , 0x118008a000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC3_DIMM000_PARAMS" , 0x118008b000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC3_DIMM001_PARAMS" , 0x118008b000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC0_DIMM_CTL" , 0x1180088000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"LMC1_DIMM_CTL" , 0x1180089000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"LMC2_DIMM_CTL" , 0x118008a000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"LMC3_DIMM_CTL" , 0x118008b000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"LMC0_DLL_CTL2" , 0x11800880001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"LMC1_DLL_CTL2" , 0x11800890001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"LMC2_DLL_CTL2" , 0x118008a0001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"LMC3_DLL_CTL2" , 0x118008b0001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"LMC0_DLL_CTL3" , 0x1180088000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"LMC1_DLL_CTL3" , 0x1180089000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"LMC2_DLL_CTL3" , 0x118008a000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"LMC3_DLL_CTL3" , 0x118008b000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"LMC1_DUAL_MEMCFG" , 0x1180089000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"LMC2_DUAL_MEMCFG" , 0x118008a000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"LMC3_DUAL_MEMCFG" , 0x118008b000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"LMC1_ECC_SYND" , 0x1180089000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"LMC2_ECC_SYND" , 0x118008a000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"LMC3_ECC_SYND" , 0x118008b000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC1_FADR" , 0x1180089000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC2_FADR" , 0x118008a000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC3_FADR" , 0x118008b000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC0_IFB_CNT" , 0x11800880001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"LMC1_IFB_CNT" , 0x11800890001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"LMC2_IFB_CNT" , 0x118008a0001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"LMC3_IFB_CNT" , 0x118008b0001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"LMC0_INT" , 0x11800880001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"LMC1_INT" , 0x11800890001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"LMC2_INT" , 0x118008a0001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"LMC3_INT" , 0x118008b0001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"LMC0_INT_EN" , 0x11800880001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"LMC1_INT_EN" , 0x11800890001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"LMC2_INT_EN" , 0x118008a0001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"LMC3_INT_EN" , 0x118008b0001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"LMC0_MODEREG_PARAMS0" , 0x11800880001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"LMC1_MODEREG_PARAMS0" , 0x11800890001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"LMC2_MODEREG_PARAMS0" , 0x118008a0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"LMC3_MODEREG_PARAMS0" , 0x118008b0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"LMC0_MODEREG_PARAMS1" , 0x1180088000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"LMC1_MODEREG_PARAMS1" , 0x1180089000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"LMC2_MODEREG_PARAMS1" , 0x118008a000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"LMC3_MODEREG_PARAMS1" , 0x118008b000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"LMC0_NXM" , 0x11800880000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"LMC1_NXM" , 0x11800890000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"LMC2_NXM" , 0x118008a0000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"LMC3_NXM" , 0x118008b0000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"LMC0_OPS_CNT" , 0x11800880001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"LMC1_OPS_CNT" , 0x11800890001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"LMC2_OPS_CNT" , 0x118008a0001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"LMC3_OPS_CNT" , 0x118008b0001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"LMC0_PHY_CTL" , 0x1180088000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"LMC1_PHY_CTL" , 0x1180089000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"LMC2_PHY_CTL" , 0x118008a000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"LMC3_PHY_CTL" , 0x118008b000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"LMC0_RESET_CTL" , 0x1180088000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"LMC1_RESET_CTL" , 0x1180089000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"LMC2_RESET_CTL" , 0x118008a000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"LMC3_RESET_CTL" , 0x118008b000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"LMC0_RLEVEL_CTL" , 0x11800880002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
- {"LMC1_RLEVEL_CTL" , 0x11800890002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
- {"LMC2_RLEVEL_CTL" , 0x118008a0002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
- {"LMC3_RLEVEL_CTL" , 0x118008b0002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
- {"LMC0_RLEVEL_DBG" , 0x11800880002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"LMC1_RLEVEL_DBG" , 0x11800890002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"LMC2_RLEVEL_DBG" , 0x118008a0002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"LMC3_RLEVEL_DBG" , 0x118008b0002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"LMC0_RLEVEL_RANK000" , 0x1180088000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC0_RLEVEL_RANK001" , 0x1180088000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC0_RLEVEL_RANK002" , 0x1180088000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC0_RLEVEL_RANK003" , 0x1180088000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC1_RLEVEL_RANK000" , 0x1180089000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC1_RLEVEL_RANK001" , 0x1180089000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC1_RLEVEL_RANK002" , 0x1180089000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC1_RLEVEL_RANK003" , 0x1180089000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC2_RLEVEL_RANK000" , 0x118008a000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC2_RLEVEL_RANK001" , 0x118008a000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC2_RLEVEL_RANK002" , 0x118008a000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC2_RLEVEL_RANK003" , 0x118008a000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC3_RLEVEL_RANK000" , 0x118008b000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC3_RLEVEL_RANK001" , 0x118008b000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC3_RLEVEL_RANK002" , 0x118008b000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC3_RLEVEL_RANK003" , 0x118008b000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC0_RODT_MASK" , 0x1180088000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"LMC1_RODT_MASK" , 0x1180089000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"LMC2_RODT_MASK" , 0x118008a000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"LMC3_RODT_MASK" , 0x118008b000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"LMC0_SLOT_CTL0" , 0x11800880001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"LMC1_SLOT_CTL0" , 0x11800890001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"LMC2_SLOT_CTL0" , 0x118008a0001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"LMC3_SLOT_CTL0" , 0x118008b0001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"LMC0_SLOT_CTL1" , 0x1180088000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"LMC1_SLOT_CTL1" , 0x1180089000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"LMC2_SLOT_CTL1" , 0x118008a000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"LMC3_SLOT_CTL1" , 0x118008b000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"LMC0_SLOT_CTL2" , 0x1180088000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"LMC1_SLOT_CTL2" , 0x1180089000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"LMC2_SLOT_CTL2" , 0x118008a000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"LMC3_SLOT_CTL2" , 0x118008b000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"LMC0_TIMING_PARAMS0" , 0x1180088000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
- {"LMC1_TIMING_PARAMS0" , 0x1180089000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
- {"LMC2_TIMING_PARAMS0" , 0x118008a000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
- {"LMC3_TIMING_PARAMS0" , 0x118008b000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
- {"LMC0_TIMING_PARAMS1" , 0x11800880001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC1_TIMING_PARAMS1" , 0x11800890001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC2_TIMING_PARAMS1" , 0x118008a0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC3_TIMING_PARAMS1" , 0x118008b0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC0_TRO_CTL" , 0x1180088000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"LMC1_TRO_CTL" , 0x1180089000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"LMC2_TRO_CTL" , 0x118008a000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"LMC3_TRO_CTL" , 0x118008b000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"LMC0_TRO_STAT" , 0x1180088000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"LMC1_TRO_STAT" , 0x1180089000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"LMC2_TRO_STAT" , 0x118008a000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"LMC3_TRO_STAT" , 0x118008b000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"LMC0_WLEVEL_CTL" , 0x1180088000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"LMC1_WLEVEL_CTL" , 0x1180089000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"LMC2_WLEVEL_CTL" , 0x118008a000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"LMC3_WLEVEL_CTL" , 0x118008b000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"LMC0_WLEVEL_DBG" , 0x1180088000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"LMC1_WLEVEL_DBG" , 0x1180089000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"LMC2_WLEVEL_DBG" , 0x118008a000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"LMC3_WLEVEL_DBG" , 0x118008b000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"LMC0_WLEVEL_RANK000" , 0x11800880002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC0_WLEVEL_RANK001" , 0x11800880002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC0_WLEVEL_RANK002" , 0x11800880002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC0_WLEVEL_RANK003" , 0x11800880002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC1_WLEVEL_RANK000" , 0x11800890002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC1_WLEVEL_RANK001" , 0x11800890002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC1_WLEVEL_RANK002" , 0x11800890002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC1_WLEVEL_RANK003" , 0x11800890002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC2_WLEVEL_RANK000" , 0x118008a0002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC2_WLEVEL_RANK001" , 0x118008a0002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC2_WLEVEL_RANK002" , 0x118008a0002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC2_WLEVEL_RANK003" , 0x118008a0002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC3_WLEVEL_RANK000" , 0x118008b0002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC3_WLEVEL_RANK001" , 0x118008b0002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC3_WLEVEL_RANK002" , 0x118008b0002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC3_WLEVEL_RANK003" , 0x118008b0002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC0_WODT_MASK" , 0x11800880001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"LMC1_WODT_MASK" , 0x11800890001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"LMC2_WODT_MASK" , 0x118008a0001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"LMC3_WODT_MASK" , 0x118008b0001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"MIO_BOOT_PIN_DEFS" , 0x11800000000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"MIO_FUS_READ_TIMES" , 0x1180000001570ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"MIO_FUS_REPAIR_RES0" , 0x1180000001558ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"MIO_FUS_REPAIR_RES1" , 0x1180000001560ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"MIO_FUS_REPAIR_RES2" , 0x1180000001568ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"MIO_GPIO_COMP" , 0x11800000000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"MIO_NDF_DMA_CFG" , 0x1180000000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"MIO_NDF_DMA_INT" , 0x1180000000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"MIO_NDF_DMA_INT_EN" , 0x1180000000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"MIO_PTP_CLOCK_CFG" , 0x1070000000f00ull, CVMX_CSR_DB_TYPE_NCB, 64, 723},
- {"MIO_PTP_CLOCK_COMP" , 0x1070000000f18ull, CVMX_CSR_DB_TYPE_NCB, 64, 724},
- {"MIO_PTP_CLOCK_HI" , 0x1070000000f10ull, CVMX_CSR_DB_TYPE_NCB, 64, 725},
- {"MIO_PTP_CLOCK_LO" , 0x1070000000f08ull, CVMX_CSR_DB_TYPE_NCB, 64, 726},
- {"MIO_PTP_EVT_CNT" , 0x1070000000f28ull, CVMX_CSR_DB_TYPE_NCB, 64, 727},
- {"MIO_PTP_TIMESTAMP" , 0x1070000000f20ull, CVMX_CSR_DB_TYPE_NCB, 64, 728},
- {"MIO_QLM0_CFG" , 0x1180000001590ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"MIO_QLM1_CFG" , 0x1180000001598ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"MIO_QLM2_CFG" , 0x11800000015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"MIO_QLM3_CFG" , 0x11800000015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"MIO_QLM4_CFG" , 0x11800000015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
- {"MIO_RST_BOOT" , 0x1180000001600ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
- {"MIO_RST_CFG" , 0x1180000001610ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
- {"MIO_RST_CTL0" , 0x1180000001618ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"MIO_RST_CTL1" , 0x1180000001620ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
- {"MIO_RST_DELAY" , 0x1180000001608ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
- {"MIO_RST_INT" , 0x1180000001628ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
- {"MIO_RST_INT_EN" , 0x1180000001630ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 765},
- {"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
- {"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
- {"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 768},
- {"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 769},
- {"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 770},
- {"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 771},
- {"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 772},
- {"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 773},
- {"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 774},
- {"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 775},
- {"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 776},
- {"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 777},
- {"MIX0_TSCTL" , 0x1070000100068ull, CVMX_CSR_DB_TYPE_NCB, 64, 778},
- {"MIX0_TSTAMP" , 0x1070000100060ull, CVMX_CSR_DB_TYPE_NCB, 64, 779},
- {"NDF_BT_PG_INFO" , 0x1070001000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 780},
- {"NDF_CMD" , 0x1070001000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 781},
- {"NDF_DRBELL" , 0x1070001000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 782},
- {"NDF_ECC_CNT" , 0x1070001000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 783},
- {"NDF_INT" , 0x1070001000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 784},
- {"NDF_INT_EN" , 0x1070001000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 785},
- {"NDF_MISC" , 0x1070001000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 786},
- {"NDF_ST_REG" , 0x1070001000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 787},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 788},
- {"PCIEEP1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 788},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 789},
- {"PCIEEP1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 789},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 790},
- {"PCIEEP1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 790},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 791},
- {"PCIEEP1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 791},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 792},
- {"PCIEEP1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 792},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 793},
- {"PCIEEP1_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 793},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 794},
- {"PCIEEP1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 794},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 795},
- {"PCIEEP1_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 795},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 796},
- {"PCIEEP1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 796},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 797},
- {"PCIEEP1_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 797},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 798},
- {"PCIEEP1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 798},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 799},
- {"PCIEEP1_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 799},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 800},
- {"PCIEEP1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 800},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 801},
- {"PCIEEP1_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 801},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 802},
- {"PCIEEP1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 802},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 803},
- {"PCIEEP1_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 803},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 804},
- {"PCIEEP1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 804},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 805},
- {"PCIEEP1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 805},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 806},
- {"PCIEEP1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 806},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 807},
- {"PCIEEP1_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 807},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 808},
- {"PCIEEP1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 808},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 809},
- {"PCIEEP1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 809},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 810},
- {"PCIEEP1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 810},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 811},
- {"PCIEEP1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 811},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 812},
- {"PCIEEP1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 812},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 813},
- {"PCIEEP1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 813},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 814},
- {"PCIEEP1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 814},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 815},
- {"PCIEEP1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 815},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 816},
- {"PCIEEP1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 816},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 817},
- {"PCIEEP1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 817},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 818},
- {"PCIEEP1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 818},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 819},
- {"PCIEEP1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 819},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 820},
- {"PCIEEP1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 820},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 821},
- {"PCIEEP1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 821},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 822},
- {"PCIEEP1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 822},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 823},
- {"PCIEEP1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 823},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 824},
- {"PCIEEP1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 824},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 825},
- {"PCIEEP1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 825},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 826},
- {"PCIEEP1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 826},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 827},
- {"PCIEEP1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 827},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 828},
- {"PCIEEP1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 828},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 829},
- {"PCIEEP1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 829},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 830},
- {"PCIEEP1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 830},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 831},
- {"PCIEEP1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 831},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 832},
- {"PCIEEP1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 832},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 833},
- {"PCIEEP1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 833},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 834},
- {"PCIEEP1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 834},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 835},
- {"PCIEEP1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 835},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 836},
- {"PCIEEP1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 836},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 837},
- {"PCIEEP1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 837},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 838},
- {"PCIEEP1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 838},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 839},
- {"PCIEEP1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 839},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 840},
- {"PCIEEP1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 840},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 841},
- {"PCIEEP1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 841},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 842},
- {"PCIEEP1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 842},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 843},
- {"PCIEEP1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 843},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 844},
- {"PCIEEP1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 844},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 845},
- {"PCIEEP1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 845},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 846},
- {"PCIEEP1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 846},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 847},
- {"PCIEEP1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 847},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 848},
- {"PCIEEP1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 848},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 849},
- {"PCIEEP1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 849},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 850},
- {"PCIEEP1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 850},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 851},
- {"PCIEEP1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 851},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 852},
- {"PCIEEP1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 852},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 853},
- {"PCIEEP1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 853},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 854},
- {"PCIEEP1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 854},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 855},
- {"PCIEEP1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 855},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 856},
- {"PCIEEP1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 856},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 857},
- {"PCIEEP1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 857},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 858},
- {"PCIEEP1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 858},
- {"PCIEEP0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 859},
- {"PCIEEP1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 859},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 860},
- {"PCIEEP1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 860},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 861},
- {"PCIEEP1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 861},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 862},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 862},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 863},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 863},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 864},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 864},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 865},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 865},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 866},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 866},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 867},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 867},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 868},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 868},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 869},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 869},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 870},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 870},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 871},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 871},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 872},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 872},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 873},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 873},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 874},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 874},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 875},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 875},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 876},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 876},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 877},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 877},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 878},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 878},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 879},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 879},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 880},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 880},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 881},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 881},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 882},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 882},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 883},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 883},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 884},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 884},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 885},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 885},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 886},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 886},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 887},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 887},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 888},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 888},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 889},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 889},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 890},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 890},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 891},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 891},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 892},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 892},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 893},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 893},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 894},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 894},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 895},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 895},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 896},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 896},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 897},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 897},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 898},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 898},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 899},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 899},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 900},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 900},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 901},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 901},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 902},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 902},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 903},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 903},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 904},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 904},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 905},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 905},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 906},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 906},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 907},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 907},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 908},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 908},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 909},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 909},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 910},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 910},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 911},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 911},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 912},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 912},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 913},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 913},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 914},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 914},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 915},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 915},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 916},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 916},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 917},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 917},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 918},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 918},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 919},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 919},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 920},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 920},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 921},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 921},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 922},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 922},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 923},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 923},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 924},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 924},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 925},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 925},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 926},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 926},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 927},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 927},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 928},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 928},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 929},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 929},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 930},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 930},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 931},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 931},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 932},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 932},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 933},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 933},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 934},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 934},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 935},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 935},
- {"PCIERC0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 936},
- {"PCIERC1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 936},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 937},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 937},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 938},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 938},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS0_AN002_ADV_REG" , 0x11800b0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS0_AN003_ADV_REG" , 0x11800b0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS1_AN000_ADV_REG" , 0x11800b1001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS1_AN001_ADV_REG" , 0x11800b1001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS1_AN002_ADV_REG" , 0x11800b1001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS1_AN003_ADV_REG" , 0x11800b1001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS2_AN000_ADV_REG" , 0x11800b2001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS2_AN001_ADV_REG" , 0x11800b2001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS2_AN002_ADV_REG" , 0x11800b2001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS2_AN003_ADV_REG" , 0x11800b2001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS3_AN000_ADV_REG" , 0x11800b3001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS3_AN001_ADV_REG" , 0x11800b3001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS3_AN002_ADV_REG" , 0x11800b3001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS3_AN003_ADV_REG" , 0x11800b3001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS4_AN000_ADV_REG" , 0x11800b4001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS4_AN001_ADV_REG" , 0x11800b4001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS4_AN002_ADV_REG" , 0x11800b4001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS4_AN003_ADV_REG" , 0x11800b4001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS0_AN002_EXT_ST_REG" , 0x11800b0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS0_AN003_EXT_ST_REG" , 0x11800b0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS1_AN000_EXT_ST_REG" , 0x11800b1001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS1_AN001_EXT_ST_REG" , 0x11800b1001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS1_AN002_EXT_ST_REG" , 0x11800b1001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS1_AN003_EXT_ST_REG" , 0x11800b1001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS2_AN000_EXT_ST_REG" , 0x11800b2001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS2_AN001_EXT_ST_REG" , 0x11800b2001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS2_AN002_EXT_ST_REG" , 0x11800b2001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS2_AN003_EXT_ST_REG" , 0x11800b2001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS3_AN000_EXT_ST_REG" , 0x11800b3001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS3_AN001_EXT_ST_REG" , 0x11800b3001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS3_AN002_EXT_ST_REG" , 0x11800b3001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS3_AN003_EXT_ST_REG" , 0x11800b3001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS4_AN000_EXT_ST_REG" , 0x11800b4001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS4_AN001_EXT_ST_REG" , 0x11800b4001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS4_AN002_EXT_ST_REG" , 0x11800b4001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS4_AN003_EXT_ST_REG" , 0x11800b4001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS0_AN002_LP_ABIL_REG" , 0x11800b0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS0_AN003_LP_ABIL_REG" , 0x11800b0001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS1_AN000_LP_ABIL_REG" , 0x11800b1001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS1_AN001_LP_ABIL_REG" , 0x11800b1001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS1_AN002_LP_ABIL_REG" , 0x11800b1001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS1_AN003_LP_ABIL_REG" , 0x11800b1001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS2_AN000_LP_ABIL_REG" , 0x11800b2001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS2_AN001_LP_ABIL_REG" , 0x11800b2001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS2_AN002_LP_ABIL_REG" , 0x11800b2001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS2_AN003_LP_ABIL_REG" , 0x11800b2001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS3_AN000_LP_ABIL_REG" , 0x11800b3001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS3_AN001_LP_ABIL_REG" , 0x11800b3001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS3_AN002_LP_ABIL_REG" , 0x11800b3001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS3_AN003_LP_ABIL_REG" , 0x11800b3001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS4_AN000_LP_ABIL_REG" , 0x11800b4001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS4_AN001_LP_ABIL_REG" , 0x11800b4001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS4_AN002_LP_ABIL_REG" , 0x11800b4001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS4_AN003_LP_ABIL_REG" , 0x11800b4001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS0_AN002_RESULTS_REG" , 0x11800b0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS0_AN003_RESULTS_REG" , 0x11800b0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS1_AN000_RESULTS_REG" , 0x11800b1001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS1_AN001_RESULTS_REG" , 0x11800b1001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS1_AN002_RESULTS_REG" , 0x11800b1001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS1_AN003_RESULTS_REG" , 0x11800b1001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS2_AN000_RESULTS_REG" , 0x11800b2001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS2_AN001_RESULTS_REG" , 0x11800b2001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS2_AN002_RESULTS_REG" , 0x11800b2001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS2_AN003_RESULTS_REG" , 0x11800b2001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS3_AN000_RESULTS_REG" , 0x11800b3001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS3_AN001_RESULTS_REG" , 0x11800b3001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS3_AN002_RESULTS_REG" , 0x11800b3001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS3_AN003_RESULTS_REG" , 0x11800b3001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS4_AN000_RESULTS_REG" , 0x11800b4001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS4_AN001_RESULTS_REG" , 0x11800b4001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS4_AN002_RESULTS_REG" , 0x11800b4001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS4_AN003_RESULTS_REG" , 0x11800b4001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS0_INT002_EN_REG" , 0x11800b0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS0_INT003_EN_REG" , 0x11800b0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS1_INT000_EN_REG" , 0x11800b1001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS1_INT001_EN_REG" , 0x11800b1001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS1_INT002_EN_REG" , 0x11800b1001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS1_INT003_EN_REG" , 0x11800b1001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS2_INT000_EN_REG" , 0x11800b2001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS2_INT001_EN_REG" , 0x11800b2001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS2_INT002_EN_REG" , 0x11800b2001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS2_INT003_EN_REG" , 0x11800b2001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS3_INT000_EN_REG" , 0x11800b3001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS3_INT001_EN_REG" , 0x11800b3001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS3_INT002_EN_REG" , 0x11800b3001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS3_INT003_EN_REG" , 0x11800b3001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS4_INT000_EN_REG" , 0x11800b4001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS4_INT001_EN_REG" , 0x11800b4001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS4_INT002_EN_REG" , 0x11800b4001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS4_INT003_EN_REG" , 0x11800b4001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS0_INT002_REG" , 0x11800b0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS0_INT003_REG" , 0x11800b0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS1_INT000_REG" , 0x11800b1001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS1_INT001_REG" , 0x11800b1001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS1_INT002_REG" , 0x11800b1001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS1_INT003_REG" , 0x11800b1001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS2_INT000_REG" , 0x11800b2001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS2_INT001_REG" , 0x11800b2001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS2_INT002_REG" , 0x11800b2001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS2_INT003_REG" , 0x11800b2001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS3_INT000_REG" , 0x11800b3001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS3_INT001_REG" , 0x11800b3001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS3_INT002_REG" , 0x11800b3001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS3_INT003_REG" , 0x11800b3001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS4_INT000_REG" , 0x11800b4001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS4_INT001_REG" , 0x11800b4001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS4_INT002_REG" , 0x11800b4001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS4_INT003_REG" , 0x11800b4001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS0_LINK002_TIMER_COUNT_REG", 0x11800b0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS0_LINK003_TIMER_COUNT_REG", 0x11800b0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS1_LINK000_TIMER_COUNT_REG", 0x11800b1001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS1_LINK001_TIMER_COUNT_REG", 0x11800b1001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS1_LINK002_TIMER_COUNT_REG", 0x11800b1001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS1_LINK003_TIMER_COUNT_REG", 0x11800b1001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS2_LINK000_TIMER_COUNT_REG", 0x11800b2001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS2_LINK001_TIMER_COUNT_REG", 0x11800b2001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS2_LINK002_TIMER_COUNT_REG", 0x11800b2001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS2_LINK003_TIMER_COUNT_REG", 0x11800b2001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS3_LINK000_TIMER_COUNT_REG", 0x11800b3001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS3_LINK001_TIMER_COUNT_REG", 0x11800b3001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS3_LINK002_TIMER_COUNT_REG", 0x11800b3001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS3_LINK003_TIMER_COUNT_REG", 0x11800b3001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS4_LINK000_TIMER_COUNT_REG", 0x11800b4001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS4_LINK001_TIMER_COUNT_REG", 0x11800b4001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS4_LINK002_TIMER_COUNT_REG", 0x11800b4001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS4_LINK003_TIMER_COUNT_REG", 0x11800b4001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS0_LOG_ANL002_REG" , 0x11800b0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS0_LOG_ANL003_REG" , 0x11800b0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS1_LOG_ANL000_REG" , 0x11800b1001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS1_LOG_ANL001_REG" , 0x11800b1001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS1_LOG_ANL002_REG" , 0x11800b1001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS1_LOG_ANL003_REG" , 0x11800b1001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS2_LOG_ANL000_REG" , 0x11800b2001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS2_LOG_ANL001_REG" , 0x11800b2001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS2_LOG_ANL002_REG" , 0x11800b2001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS2_LOG_ANL003_REG" , 0x11800b2001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS3_LOG_ANL000_REG" , 0x11800b3001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS3_LOG_ANL001_REG" , 0x11800b3001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS3_LOG_ANL002_REG" , 0x11800b3001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS3_LOG_ANL003_REG" , 0x11800b3001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS4_LOG_ANL000_REG" , 0x11800b4001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS4_LOG_ANL001_REG" , 0x11800b4001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS4_LOG_ANL002_REG" , 0x11800b4001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS4_LOG_ANL003_REG" , 0x11800b4001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS0_MISC002_CTL_REG" , 0x11800b0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS0_MISC003_CTL_REG" , 0x11800b0001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS1_MISC000_CTL_REG" , 0x11800b1001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS1_MISC001_CTL_REG" , 0x11800b1001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS1_MISC002_CTL_REG" , 0x11800b1001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS1_MISC003_CTL_REG" , 0x11800b1001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS2_MISC000_CTL_REG" , 0x11800b2001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS2_MISC001_CTL_REG" , 0x11800b2001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS2_MISC002_CTL_REG" , 0x11800b2001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS2_MISC003_CTL_REG" , 0x11800b2001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS3_MISC000_CTL_REG" , 0x11800b3001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS3_MISC001_CTL_REG" , 0x11800b3001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS3_MISC002_CTL_REG" , 0x11800b3001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS3_MISC003_CTL_REG" , 0x11800b3001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS4_MISC000_CTL_REG" , 0x11800b4001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS4_MISC001_CTL_REG" , 0x11800b4001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS4_MISC002_CTL_REG" , 0x11800b4001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS4_MISC003_CTL_REG" , 0x11800b4001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS0_MR002_CONTROL_REG" , 0x11800b0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS0_MR003_CONTROL_REG" , 0x11800b0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS1_MR000_CONTROL_REG" , 0x11800b1001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS1_MR001_CONTROL_REG" , 0x11800b1001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS1_MR002_CONTROL_REG" , 0x11800b1001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS1_MR003_CONTROL_REG" , 0x11800b1001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS2_MR000_CONTROL_REG" , 0x11800b2001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS2_MR001_CONTROL_REG" , 0x11800b2001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS2_MR002_CONTROL_REG" , 0x11800b2001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS2_MR003_CONTROL_REG" , 0x11800b2001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS3_MR000_CONTROL_REG" , 0x11800b3001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS3_MR001_CONTROL_REG" , 0x11800b3001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS3_MR002_CONTROL_REG" , 0x11800b3001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS3_MR003_CONTROL_REG" , 0x11800b3001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS4_MR000_CONTROL_REG" , 0x11800b4001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS4_MR001_CONTROL_REG" , 0x11800b4001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS4_MR002_CONTROL_REG" , 0x11800b4001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS4_MR003_CONTROL_REG" , 0x11800b4001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS0_MR002_STATUS_REG" , 0x11800b0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS0_MR003_STATUS_REG" , 0x11800b0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS1_MR000_STATUS_REG" , 0x11800b1001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS1_MR001_STATUS_REG" , 0x11800b1001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS1_MR002_STATUS_REG" , 0x11800b1001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS1_MR003_STATUS_REG" , 0x11800b1001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS2_MR000_STATUS_REG" , 0x11800b2001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS2_MR001_STATUS_REG" , 0x11800b2001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS2_MR002_STATUS_REG" , 0x11800b2001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS2_MR003_STATUS_REG" , 0x11800b2001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS3_MR000_STATUS_REG" , 0x11800b3001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS3_MR001_STATUS_REG" , 0x11800b3001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS3_MR002_STATUS_REG" , 0x11800b3001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS3_MR003_STATUS_REG" , 0x11800b3001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS4_MR000_STATUS_REG" , 0x11800b4001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS4_MR001_STATUS_REG" , 0x11800b4001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS4_MR002_STATUS_REG" , 0x11800b4001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS4_MR003_STATUS_REG" , 0x11800b4001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS0_RX002_STATES_REG" , 0x11800b0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS0_RX003_STATES_REG" , 0x11800b0001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS1_RX000_STATES_REG" , 0x11800b1001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS1_RX001_STATES_REG" , 0x11800b1001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS1_RX002_STATES_REG" , 0x11800b1001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS1_RX003_STATES_REG" , 0x11800b1001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS2_RX000_STATES_REG" , 0x11800b2001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS2_RX001_STATES_REG" , 0x11800b2001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS2_RX002_STATES_REG" , 0x11800b2001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS2_RX003_STATES_REG" , 0x11800b2001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS3_RX000_STATES_REG" , 0x11800b3001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS3_RX001_STATES_REG" , 0x11800b3001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS3_RX002_STATES_REG" , 0x11800b3001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS3_RX003_STATES_REG" , 0x11800b3001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS4_RX000_STATES_REG" , 0x11800b4001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS4_RX001_STATES_REG" , 0x11800b4001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS4_RX002_STATES_REG" , 0x11800b4001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS4_RX003_STATES_REG" , 0x11800b4001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS0_RX002_SYNC_REG" , 0x11800b0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS0_RX003_SYNC_REG" , 0x11800b0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS1_RX000_SYNC_REG" , 0x11800b1001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS1_RX001_SYNC_REG" , 0x11800b1001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS1_RX002_SYNC_REG" , 0x11800b1001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS1_RX003_SYNC_REG" , 0x11800b1001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS2_RX000_SYNC_REG" , 0x11800b2001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS2_RX001_SYNC_REG" , 0x11800b2001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS2_RX002_SYNC_REG" , 0x11800b2001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS2_RX003_SYNC_REG" , 0x11800b2001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS3_RX000_SYNC_REG" , 0x11800b3001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS3_RX001_SYNC_REG" , 0x11800b3001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS3_RX002_SYNC_REG" , 0x11800b3001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS3_RX003_SYNC_REG" , 0x11800b3001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS4_RX000_SYNC_REG" , 0x11800b4001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS4_RX001_SYNC_REG" , 0x11800b4001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS4_RX002_SYNC_REG" , 0x11800b4001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS4_RX003_SYNC_REG" , 0x11800b4001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS0_SGM002_AN_ADV_REG" , 0x11800b0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS0_SGM003_AN_ADV_REG" , 0x11800b0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS1_SGM000_AN_ADV_REG" , 0x11800b1001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS1_SGM001_AN_ADV_REG" , 0x11800b1001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS1_SGM002_AN_ADV_REG" , 0x11800b1001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS1_SGM003_AN_ADV_REG" , 0x11800b1001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS2_SGM000_AN_ADV_REG" , 0x11800b2001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS2_SGM001_AN_ADV_REG" , 0x11800b2001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS2_SGM002_AN_ADV_REG" , 0x11800b2001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS2_SGM003_AN_ADV_REG" , 0x11800b2001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS3_SGM000_AN_ADV_REG" , 0x11800b3001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS3_SGM001_AN_ADV_REG" , 0x11800b3001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS3_SGM002_AN_ADV_REG" , 0x11800b3001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS3_SGM003_AN_ADV_REG" , 0x11800b3001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS4_SGM000_AN_ADV_REG" , 0x11800b4001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS4_SGM001_AN_ADV_REG" , 0x11800b4001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS4_SGM002_AN_ADV_REG" , 0x11800b4001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS4_SGM003_AN_ADV_REG" , 0x11800b4001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS0_SGM002_LP_ADV_REG" , 0x11800b0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS0_SGM003_LP_ADV_REG" , 0x11800b0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS1_SGM000_LP_ADV_REG" , 0x11800b1001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS1_SGM001_LP_ADV_REG" , 0x11800b1001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS1_SGM002_LP_ADV_REG" , 0x11800b1001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS1_SGM003_LP_ADV_REG" , 0x11800b1001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS2_SGM000_LP_ADV_REG" , 0x11800b2001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS2_SGM001_LP_ADV_REG" , 0x11800b2001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS2_SGM002_LP_ADV_REG" , 0x11800b2001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS2_SGM003_LP_ADV_REG" , 0x11800b2001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS3_SGM000_LP_ADV_REG" , 0x11800b3001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS3_SGM001_LP_ADV_REG" , 0x11800b3001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS3_SGM002_LP_ADV_REG" , 0x11800b3001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS3_SGM003_LP_ADV_REG" , 0x11800b3001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS4_SGM000_LP_ADV_REG" , 0x11800b4001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS4_SGM001_LP_ADV_REG" , 0x11800b4001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS4_SGM002_LP_ADV_REG" , 0x11800b4001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS4_SGM003_LP_ADV_REG" , 0x11800b4001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS0_TX002_STATES_REG" , 0x11800b0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS0_TX003_STATES_REG" , 0x11800b0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS1_TX000_STATES_REG" , 0x11800b1001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS1_TX001_STATES_REG" , 0x11800b1001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS1_TX002_STATES_REG" , 0x11800b1001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS1_TX003_STATES_REG" , 0x11800b1001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS2_TX000_STATES_REG" , 0x11800b2001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS2_TX001_STATES_REG" , 0x11800b2001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS2_TX002_STATES_REG" , 0x11800b2001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS2_TX003_STATES_REG" , 0x11800b2001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS3_TX000_STATES_REG" , 0x11800b3001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS3_TX001_STATES_REG" , 0x11800b3001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS3_TX002_STATES_REG" , 0x11800b3001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS3_TX003_STATES_REG" , 0x11800b3001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS4_TX000_STATES_REG" , 0x11800b4001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS4_TX001_STATES_REG" , 0x11800b4001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS4_TX002_STATES_REG" , 0x11800b4001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS4_TX003_STATES_REG" , 0x11800b4001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS0_TX_RX002_POLARITY_REG" , 0x11800b0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS0_TX_RX003_POLARITY_REG" , 0x11800b0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS1_TX_RX000_POLARITY_REG" , 0x11800b1001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS1_TX_RX001_POLARITY_REG" , 0x11800b1001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS1_TX_RX002_POLARITY_REG" , 0x11800b1001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS1_TX_RX003_POLARITY_REG" , 0x11800b1001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS2_TX_RX000_POLARITY_REG" , 0x11800b2001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS2_TX_RX001_POLARITY_REG" , 0x11800b2001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS2_TX_RX002_POLARITY_REG" , 0x11800b2001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS2_TX_RX003_POLARITY_REG" , 0x11800b2001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS3_TX_RX000_POLARITY_REG" , 0x11800b3001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS3_TX_RX001_POLARITY_REG" , 0x11800b3001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS3_TX_RX002_POLARITY_REG" , 0x11800b3001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS3_TX_RX003_POLARITY_REG" , 0x11800b3001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS4_TX_RX000_POLARITY_REG" , 0x11800b4001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS4_TX_RX001_POLARITY_REG" , 0x11800b4001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS4_TX_RX002_POLARITY_REG" , 0x11800b4001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS4_TX_RX003_POLARITY_REG" , 0x11800b4001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCSX0_10GBX_STATUS_REG" , 0x11800b0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCSX1_10GBX_STATUS_REG" , 0x11800b1000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCSX2_10GBX_STATUS_REG" , 0x11800b2000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCSX3_10GBX_STATUS_REG" , 0x11800b3000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCSX4_10GBX_STATUS_REG" , 0x11800b4000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCSX0_BIST_STATUS_REG" , 0x11800b0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCSX1_BIST_STATUS_REG" , 0x11800b1000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCSX2_BIST_STATUS_REG" , 0x11800b2000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCSX3_BIST_STATUS_REG" , 0x11800b3000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCSX4_BIST_STATUS_REG" , 0x11800b4000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800b0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCSX1_BIT_LOCK_STATUS_REG" , 0x11800b1000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCSX2_BIT_LOCK_STATUS_REG" , 0x11800b2000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCSX3_BIT_LOCK_STATUS_REG" , 0x11800b3000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCSX4_BIT_LOCK_STATUS_REG" , 0x11800b4000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCSX0_CONTROL1_REG" , 0x11800b0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCSX1_CONTROL1_REG" , 0x11800b1000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCSX2_CONTROL1_REG" , 0x11800b2000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCSX3_CONTROL1_REG" , 0x11800b3000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCSX4_CONTROL1_REG" , 0x11800b4000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCSX0_CONTROL2_REG" , 0x11800b0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCSX1_CONTROL2_REG" , 0x11800b1000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCSX2_CONTROL2_REG" , 0x11800b2000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCSX3_CONTROL2_REG" , 0x11800b3000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCSX4_CONTROL2_REG" , 0x11800b4000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCSX0_INT_EN_REG" , 0x11800b0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCSX1_INT_EN_REG" , 0x11800b1000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCSX2_INT_EN_REG" , 0x11800b2000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCSX3_INT_EN_REG" , 0x11800b3000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCSX4_INT_EN_REG" , 0x11800b4000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCSX0_INT_REG" , 0x11800b0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCSX1_INT_REG" , 0x11800b1000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCSX2_INT_REG" , 0x11800b2000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCSX3_INT_REG" , 0x11800b3000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCSX4_INT_REG" , 0x11800b4000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCSX0_LOG_ANL_REG" , 0x11800b0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCSX1_LOG_ANL_REG" , 0x11800b1000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCSX2_LOG_ANL_REG" , 0x11800b2000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCSX3_LOG_ANL_REG" , 0x11800b3000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCSX4_LOG_ANL_REG" , 0x11800b4000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCSX0_MISC_CTL_REG" , 0x11800b0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCSX1_MISC_CTL_REG" , 0x11800b1000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCSX2_MISC_CTL_REG" , 0x11800b2000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCSX3_MISC_CTL_REG" , 0x11800b3000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCSX4_MISC_CTL_REG" , 0x11800b4000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCSX0_RX_SYNC_STATES_REG" , 0x11800b0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCSX1_RX_SYNC_STATES_REG" , 0x11800b1000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCSX2_RX_SYNC_STATES_REG" , 0x11800b2000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCSX3_RX_SYNC_STATES_REG" , 0x11800b3000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCSX4_RX_SYNC_STATES_REG" , 0x11800b4000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCSX0_SPD_ABIL_REG" , 0x11800b0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCSX1_SPD_ABIL_REG" , 0x11800b1000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCSX2_SPD_ABIL_REG" , 0x11800b2000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCSX3_SPD_ABIL_REG" , 0x11800b3000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCSX4_SPD_ABIL_REG" , 0x11800b4000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCSX0_STATUS1_REG" , 0x11800b0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCSX1_STATUS1_REG" , 0x11800b1000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCSX2_STATUS1_REG" , 0x11800b2000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCSX3_STATUS1_REG" , 0x11800b3000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCSX4_STATUS1_REG" , 0x11800b4000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCSX0_STATUS2_REG" , 0x11800b0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCSX1_STATUS2_REG" , 0x11800b1000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCSX2_STATUS2_REG" , 0x11800b2000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCSX3_STATUS2_REG" , 0x11800b3000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCSX4_STATUS2_REG" , 0x11800b4000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCSX0_TX_RX_POLARITY_REG" , 0x11800b0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCSX1_TX_RX_POLARITY_REG" , 0x11800b1000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCSX2_TX_RX_POLARITY_REG" , 0x11800b2000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCSX3_TX_RX_POLARITY_REG" , 0x11800b3000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCSX4_TX_RX_POLARITY_REG" , 0x11800b4000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCSX0_TX_RX_STATES_REG" , 0x11800b0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCSX1_TX_RX_STATES_REG" , 0x11800b1000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCSX2_TX_RX_STATES_REG" , 0x11800b2000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCSX3_TX_RX_STATES_REG" , 0x11800b3000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCSX4_TX_RX_STATES_REG" , 0x11800b4000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PEM0_BAR1_INDEX000" , 0x11800c00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX001" , 0x11800c00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX002" , 0x11800c00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX003" , 0x11800c00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX004" , 0x11800c00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX005" , 0x11800c00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX006" , 0x11800c00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX007" , 0x11800c00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX008" , 0x11800c00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX009" , 0x11800c00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX010" , 0x11800c00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX011" , 0x11800c0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX012" , 0x11800c0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX013" , 0x11800c0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX014" , 0x11800c0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR1_INDEX015" , 0x11800c0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX000" , 0x11800c10000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX001" , 0x11800c10000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX002" , 0x11800c10000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX003" , 0x11800c10000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX004" , 0x11800c10000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX005" , 0x11800c10000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX006" , 0x11800c10000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX007" , 0x11800c10000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX008" , 0x11800c10000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX009" , 0x11800c10000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX010" , 0x11800c10000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX011" , 0x11800c1000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX012" , 0x11800c1000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX013" , 0x11800c1000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX014" , 0x11800c1000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM1_BAR1_INDEX015" , 0x11800c1000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PEM0_BAR2_MASK" , 0x11800c0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
- {"PEM1_BAR2_MASK" , 0x11800c1000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
- {"PEM0_BAR_CTL" , 0x11800c0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
- {"PEM1_BAR_CTL" , 0x11800c1000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
- {"PEM0_BIST_STATUS" , 0x11800c0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
- {"PEM1_BIST_STATUS" , 0x11800c1000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
- {"PEM0_BIST_STATUS2" , 0x11800c0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 975},
- {"PEM1_BIST_STATUS2" , 0x11800c1000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 975},
- {"PEM0_CFG_RD" , 0x11800c0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 976},
- {"PEM1_CFG_RD" , 0x11800c1000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 976},
- {"PEM0_CFG_WR" , 0x11800c0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 977},
- {"PEM1_CFG_WR" , 0x11800c1000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 977},
- {"PEM0_CPL_LUT_VALID" , 0x11800c0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 978},
- {"PEM1_CPL_LUT_VALID" , 0x11800c1000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 978},
- {"PEM0_CTL_STATUS" , 0x11800c0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 979},
- {"PEM1_CTL_STATUS" , 0x11800c1000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 979},
- {"PEM0_DBG_INFO" , 0x11800c0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 980},
- {"PEM1_DBG_INFO" , 0x11800c1000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 980},
- {"PEM0_DBG_INFO_EN" , 0x11800c00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 981},
- {"PEM1_DBG_INFO_EN" , 0x11800c10000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 981},
- {"PEM0_DIAG_STATUS" , 0x11800c0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 982},
- {"PEM1_DIAG_STATUS" , 0x11800c1000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 982},
- {"PEM0_INT_ENB" , 0x11800c0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 983},
- {"PEM1_INT_ENB" , 0x11800c1000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 983},
- {"PEM0_INT_ENB_INT" , 0x11800c0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 984},
- {"PEM1_INT_ENB_INT" , 0x11800c1000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 984},
- {"PEM0_INT_SUM" , 0x11800c0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 985},
- {"PEM1_INT_SUM" , 0x11800c1000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 985},
- {"PEM0_P2N_BAR0_START" , 0x11800c0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_P2N_BAR0_START" , 0x11800c1000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_P2N_BAR1_START" , 0x11800c0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 987},
- {"PEM1_P2N_BAR1_START" , 0x11800c1000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 987},
- {"PEM0_P2N_BAR2_START" , 0x11800c0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 988},
- {"PEM1_P2N_BAR2_START" , 0x11800c1000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 988},
- {"PEM0_P2P_BAR000_END" , 0x11800c0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"PEM0_P2P_BAR001_END" , 0x11800c0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"PEM0_P2P_BAR002_END" , 0x11800c0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"PEM0_P2P_BAR003_END" , 0x11800c0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"PEM1_P2P_BAR000_END" , 0x11800c1000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"PEM1_P2P_BAR001_END" , 0x11800c1000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"PEM1_P2P_BAR002_END" , 0x11800c1000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"PEM1_P2P_BAR003_END" , 0x11800c1000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"PEM0_P2P_BAR000_START" , 0x11800c0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"PEM0_P2P_BAR001_START" , 0x11800c0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"PEM0_P2P_BAR002_START" , 0x11800c0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"PEM0_P2P_BAR003_START" , 0x11800c0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"PEM1_P2P_BAR000_START" , 0x11800c1000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"PEM1_P2P_BAR001_START" , 0x11800c1000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"PEM1_P2P_BAR002_START" , 0x11800c1000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"PEM1_P2P_BAR003_START" , 0x11800c1000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"PEM0_TLP_CREDITS" , 0x11800c0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 991},
- {"PEM1_TLP_CREDITS" , 0x11800c1000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 991},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 992},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 993},
- {"PIP_CLKEN" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"PIP_DSA_SRC_GRP" , 0x11800a0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 996},
- {"PIP_DSA_VID_GRP" , 0x11800a0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 997},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 998},
- {"PIP_FRM_LEN_CHK1" , 0x11800a0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 998},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 999},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1000},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1001},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1002},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1003},
- {"PIP_PRI_TBL0" , 0x11800a0004000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL1" , 0x11800a0004008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL2" , 0x11800a0004010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL3" , 0x11800a0004018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL4" , 0x11800a0004020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL5" , 0x11800a0004028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL6" , 0x11800a0004030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL7" , 0x11800a0004038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL8" , 0x11800a0004040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL9" , 0x11800a0004048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL10" , 0x11800a0004050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL11" , 0x11800a0004058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL12" , 0x11800a0004060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL13" , 0x11800a0004068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL14" , 0x11800a0004070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL15" , 0x11800a0004078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL16" , 0x11800a0004080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL17" , 0x11800a0004088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL18" , 0x11800a0004090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL19" , 0x11800a0004098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL20" , 0x11800a00040a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL21" , 0x11800a00040a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL22" , 0x11800a00040b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL23" , 0x11800a00040b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL24" , 0x11800a00040c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL25" , 0x11800a00040c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL26" , 0x11800a00040d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL27" , 0x11800a00040d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL28" , 0x11800a00040e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL29" , 0x11800a00040e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL30" , 0x11800a00040f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL31" , 0x11800a00040f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL32" , 0x11800a0004100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL33" , 0x11800a0004108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL34" , 0x11800a0004110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL35" , 0x11800a0004118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL36" , 0x11800a0004120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL37" , 0x11800a0004128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL38" , 0x11800a0004130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL39" , 0x11800a0004138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL40" , 0x11800a0004140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL41" , 0x11800a0004148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL42" , 0x11800a0004150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL43" , 0x11800a0004158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL44" , 0x11800a0004160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL45" , 0x11800a0004168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL46" , 0x11800a0004170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL47" , 0x11800a0004178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL48" , 0x11800a0004180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL49" , 0x11800a0004188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL50" , 0x11800a0004190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL51" , 0x11800a0004198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL52" , 0x11800a00041a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL53" , 0x11800a00041a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL54" , 0x11800a00041b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL55" , 0x11800a00041b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL56" , 0x11800a00041c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL57" , 0x11800a00041c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL58" , 0x11800a00041d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL59" , 0x11800a00041d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL60" , 0x11800a00041e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL61" , 0x11800a00041e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL62" , 0x11800a00041f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL63" , 0x11800a00041f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL64" , 0x11800a0004200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL65" , 0x11800a0004208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL66" , 0x11800a0004210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL67" , 0x11800a0004218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL68" , 0x11800a0004220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL69" , 0x11800a0004228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL70" , 0x11800a0004230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL71" , 0x11800a0004238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL72" , 0x11800a0004240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL73" , 0x11800a0004248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL74" , 0x11800a0004250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL75" , 0x11800a0004258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL76" , 0x11800a0004260ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL77" , 0x11800a0004268ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL78" , 0x11800a0004270ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL79" , 0x11800a0004278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL80" , 0x11800a0004280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL81" , 0x11800a0004288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL82" , 0x11800a0004290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL83" , 0x11800a0004298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL84" , 0x11800a00042a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL85" , 0x11800a00042a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL86" , 0x11800a00042b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL87" , 0x11800a00042b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL88" , 0x11800a00042c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL89" , 0x11800a00042c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL90" , 0x11800a00042d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL91" , 0x11800a00042d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL92" , 0x11800a00042e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL93" , 0x11800a00042e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL94" , 0x11800a00042f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL95" , 0x11800a00042f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL96" , 0x11800a0004300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL97" , 0x11800a0004308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL98" , 0x11800a0004310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL99" , 0x11800a0004318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL100" , 0x11800a0004320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL101" , 0x11800a0004328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL102" , 0x11800a0004330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL103" , 0x11800a0004338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL104" , 0x11800a0004340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL105" , 0x11800a0004348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL106" , 0x11800a0004350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL107" , 0x11800a0004358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL108" , 0x11800a0004360ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL109" , 0x11800a0004368ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL110" , 0x11800a0004370ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL111" , 0x11800a0004378ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL112" , 0x11800a0004380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL113" , 0x11800a0004388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL114" , 0x11800a0004390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL115" , 0x11800a0004398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL116" , 0x11800a00043a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL117" , 0x11800a00043a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL118" , 0x11800a00043b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL119" , 0x11800a00043b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL120" , 0x11800a00043c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL121" , 0x11800a00043c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL122" , 0x11800a00043d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL123" , 0x11800a00043d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL124" , 0x11800a00043e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL125" , 0x11800a00043e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL126" , 0x11800a00043f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL127" , 0x11800a00043f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL128" , 0x11800a0004400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL129" , 0x11800a0004408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL130" , 0x11800a0004410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL131" , 0x11800a0004418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL132" , 0x11800a0004420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL133" , 0x11800a0004428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL134" , 0x11800a0004430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL135" , 0x11800a0004438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL136" , 0x11800a0004440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL137" , 0x11800a0004448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL138" , 0x11800a0004450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL139" , 0x11800a0004458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL140" , 0x11800a0004460ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL141" , 0x11800a0004468ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL142" , 0x11800a0004470ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL143" , 0x11800a0004478ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL144" , 0x11800a0004480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL145" , 0x11800a0004488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL146" , 0x11800a0004490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL147" , 0x11800a0004498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL148" , 0x11800a00044a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL149" , 0x11800a00044a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL150" , 0x11800a00044b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL151" , 0x11800a00044b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL152" , 0x11800a00044c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL153" , 0x11800a00044c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL154" , 0x11800a00044d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL155" , 0x11800a00044d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL156" , 0x11800a00044e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL157" , 0x11800a00044e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL158" , 0x11800a00044f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL159" , 0x11800a00044f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL160" , 0x11800a0004500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL161" , 0x11800a0004508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL162" , 0x11800a0004510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL163" , 0x11800a0004518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL164" , 0x11800a0004520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL165" , 0x11800a0004528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL166" , 0x11800a0004530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL167" , 0x11800a0004538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL168" , 0x11800a0004540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL169" , 0x11800a0004548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL170" , 0x11800a0004550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL171" , 0x11800a0004558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL172" , 0x11800a0004560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL173" , 0x11800a0004568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL174" , 0x11800a0004570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL175" , 0x11800a0004578ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL176" , 0x11800a0004580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL177" , 0x11800a0004588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL178" , 0x11800a0004590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL179" , 0x11800a0004598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL180" , 0x11800a00045a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL181" , 0x11800a00045a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL182" , 0x11800a00045b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL183" , 0x11800a00045b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL184" , 0x11800a00045c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL185" , 0x11800a00045c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL186" , 0x11800a00045d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL187" , 0x11800a00045d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL188" , 0x11800a00045e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL189" , 0x11800a00045e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL190" , 0x11800a00045f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL191" , 0x11800a00045f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL192" , 0x11800a0004600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL193" , 0x11800a0004608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL194" , 0x11800a0004610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL195" , 0x11800a0004618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL196" , 0x11800a0004620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL197" , 0x11800a0004628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL198" , 0x11800a0004630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL199" , 0x11800a0004638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL200" , 0x11800a0004640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL201" , 0x11800a0004648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL202" , 0x11800a0004650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL203" , 0x11800a0004658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL204" , 0x11800a0004660ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL205" , 0x11800a0004668ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL206" , 0x11800a0004670ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL207" , 0x11800a0004678ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL208" , 0x11800a0004680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL209" , 0x11800a0004688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL210" , 0x11800a0004690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL211" , 0x11800a0004698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL212" , 0x11800a00046a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL213" , 0x11800a00046a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL214" , 0x11800a00046b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL215" , 0x11800a00046b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL216" , 0x11800a00046c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL217" , 0x11800a00046c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL218" , 0x11800a00046d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL219" , 0x11800a00046d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL220" , 0x11800a00046e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL221" , 0x11800a00046e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL222" , 0x11800a00046f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL223" , 0x11800a00046f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL224" , 0x11800a0004700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL225" , 0x11800a0004708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL226" , 0x11800a0004710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL227" , 0x11800a0004718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL228" , 0x11800a0004720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL229" , 0x11800a0004728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL230" , 0x11800a0004730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL231" , 0x11800a0004738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL232" , 0x11800a0004740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL233" , 0x11800a0004748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL234" , 0x11800a0004750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL235" , 0x11800a0004758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL236" , 0x11800a0004760ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL237" , 0x11800a0004768ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL238" , 0x11800a0004770ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL239" , 0x11800a0004778ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL240" , 0x11800a0004780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL241" , 0x11800a0004788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL242" , 0x11800a0004790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL243" , 0x11800a0004798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL244" , 0x11800a00047a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL245" , 0x11800a00047a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL246" , 0x11800a00047b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL247" , 0x11800a00047b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL248" , 0x11800a00047c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL249" , 0x11800a00047c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL250" , 0x11800a00047d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL251" , 0x11800a00047d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL252" , 0x11800a00047e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL253" , 0x11800a00047e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL254" , 0x11800a00047f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRI_TBL255" , 0x11800a00047f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG4" , 0x11800a0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG5" , 0x11800a0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG6" , 0x11800a0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG7" , 0x11800a0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG8" , 0x11800a0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG9" , 0x11800a0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG10" , 0x11800a0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG11" , 0x11800a0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG12" , 0x11800a0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG13" , 0x11800a0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG14" , 0x11800a0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG15" , 0x11800a0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG16" , 0x11800a0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG17" , 0x11800a0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG18" , 0x11800a0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG19" , 0x11800a0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG20" , 0x11800a00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG21" , 0x11800a00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG22" , 0x11800a00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG23" , 0x11800a00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG24" , 0x11800a00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG25" , 0x11800a00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG26" , 0x11800a00002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG27" , 0x11800a00002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG28" , 0x11800a00002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG29" , 0x11800a00002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG30" , 0x11800a00002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG31" , 0x11800a00002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG40" , 0x11800a0000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG41" , 0x11800a0000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG42" , 0x11800a0000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG43" , 0x11800a0000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG44" , 0x11800a0000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG45" , 0x11800a0000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG46" , 0x11800a0000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG47" , 0x11800a0000378ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG48" , 0x11800a0000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG49" , 0x11800a0000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG50" , 0x11800a0000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG51" , 0x11800a0000398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG52" , 0x11800a00003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG53" , 0x11800a00003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG54" , 0x11800a00003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG55" , 0x11800a00003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG56" , 0x11800a00003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG57" , 0x11800a00003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG58" , 0x11800a00003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG59" , 0x11800a00003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG60" , 0x11800a00003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG61" , 0x11800a00003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG62" , 0x11800a00003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFG63" , 0x11800a00003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PIP_PRT_CFGB0" , 0x11800a0008000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB1" , 0x11800a0008008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB2" , 0x11800a0008010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB3" , 0x11800a0008018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB4" , 0x11800a0008020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB5" , 0x11800a0008028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB6" , 0x11800a0008030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB7" , 0x11800a0008038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB8" , 0x11800a0008040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB9" , 0x11800a0008048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB10" , 0x11800a0008050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB11" , 0x11800a0008058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB12" , 0x11800a0008060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB13" , 0x11800a0008068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB14" , 0x11800a0008070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB15" , 0x11800a0008078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB16" , 0x11800a0008080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB17" , 0x11800a0008088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB18" , 0x11800a0008090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB19" , 0x11800a0008098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB20" , 0x11800a00080a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB21" , 0x11800a00080a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB22" , 0x11800a00080b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB23" , 0x11800a00080b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB24" , 0x11800a00080c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB25" , 0x11800a00080c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB26" , 0x11800a00080d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB27" , 0x11800a00080d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB28" , 0x11800a00080e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB29" , 0x11800a00080e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB30" , 0x11800a00080f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB31" , 0x11800a00080f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB32" , 0x11800a0008100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB33" , 0x11800a0008108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB34" , 0x11800a0008110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB35" , 0x11800a0008118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB36" , 0x11800a0008120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB37" , 0x11800a0008128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB38" , 0x11800a0008130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB39" , 0x11800a0008138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB40" , 0x11800a0008140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB41" , 0x11800a0008148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB42" , 0x11800a0008150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB43" , 0x11800a0008158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB44" , 0x11800a0008160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB45" , 0x11800a0008168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB46" , 0x11800a0008170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB47" , 0x11800a0008178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB48" , 0x11800a0008180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB49" , 0x11800a0008188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB50" , 0x11800a0008190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB51" , 0x11800a0008198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB52" , 0x11800a00081a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB53" , 0x11800a00081a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB54" , 0x11800a00081b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB55" , 0x11800a00081b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB56" , 0x11800a00081c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB57" , 0x11800a00081c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB58" , 0x11800a00081d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB59" , 0x11800a00081d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB60" , 0x11800a00081e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB61" , 0x11800a00081e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB62" , 0x11800a00081f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_CFGB63" , 0x11800a00081f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG4" , 0x11800a0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG5" , 0x11800a0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG6" , 0x11800a0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG7" , 0x11800a0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG8" , 0x11800a0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG9" , 0x11800a0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG10" , 0x11800a0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG11" , 0x11800a0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG12" , 0x11800a0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG13" , 0x11800a0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG14" , 0x11800a0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG15" , 0x11800a0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG16" , 0x11800a0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG17" , 0x11800a0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG18" , 0x11800a0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG19" , 0x11800a0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG20" , 0x11800a00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG21" , 0x11800a00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG22" , 0x11800a00004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG23" , 0x11800a00004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG24" , 0x11800a00004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG25" , 0x11800a00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG26" , 0x11800a00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG27" , 0x11800a00004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG28" , 0x11800a00004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG29" , 0x11800a00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG30" , 0x11800a00004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG31" , 0x11800a00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG40" , 0x11800a0000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG41" , 0x11800a0000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG42" , 0x11800a0000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG43" , 0x11800a0000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG44" , 0x11800a0000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG45" , 0x11800a0000568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG46" , 0x11800a0000570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG47" , 0x11800a0000578ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG48" , 0x11800a0000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG49" , 0x11800a0000588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG50" , 0x11800a0000590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG51" , 0x11800a0000598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG52" , 0x11800a00005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG53" , 0x11800a00005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG54" , 0x11800a00005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG55" , 0x11800a00005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG56" , 0x11800a00005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG57" , 0x11800a00005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG58" , 0x11800a00005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG59" , 0x11800a00005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG60" , 0x11800a00005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG61" , 0x11800a00005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG62" , 0x11800a00005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_PRT_TAG63" , 0x11800a00005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1009},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1010},
- {"PIP_STAT0_0" , 0x11800a0040000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_1" , 0x11800a0040080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_2" , 0x11800a0040100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_3" , 0x11800a0040180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_4" , 0x11800a0040200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_5" , 0x11800a0040280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_6" , 0x11800a0040300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_7" , 0x11800a0040380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_8" , 0x11800a0040400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_9" , 0x11800a0040480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_10" , 0x11800a0040500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_11" , 0x11800a0040580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_12" , 0x11800a0040600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_13" , 0x11800a0040680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_14" , 0x11800a0040700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_15" , 0x11800a0040780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_16" , 0x11800a0040800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_17" , 0x11800a0040880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_18" , 0x11800a0040900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_19" , 0x11800a0040980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_20" , 0x11800a0040a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_21" , 0x11800a0040a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_22" , 0x11800a0040b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_23" , 0x11800a0040b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_24" , 0x11800a0040c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_25" , 0x11800a0040c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_26" , 0x11800a0040d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_27" , 0x11800a0040d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_28" , 0x11800a0040e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_29" , 0x11800a0040e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_30" , 0x11800a0040f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_31" , 0x11800a0040f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_32" , 0x11800a0041000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_33" , 0x11800a0041080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_34" , 0x11800a0041100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_35" , 0x11800a0041180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_36" , 0x11800a0041200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_37" , 0x11800a0041280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_38" , 0x11800a0041300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_39" , 0x11800a0041380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_40" , 0x11800a0041400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_41" , 0x11800a0041480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_42" , 0x11800a0041500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_43" , 0x11800a0041580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_44" , 0x11800a0041600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_45" , 0x11800a0041680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_46" , 0x11800a0041700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_47" , 0x11800a0041780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_48" , 0x11800a0041800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_49" , 0x11800a0041880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_50" , 0x11800a0041900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_51" , 0x11800a0041980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_52" , 0x11800a0041a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_53" , 0x11800a0041a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_54" , 0x11800a0041b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_55" , 0x11800a0041b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_56" , 0x11800a0041c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_57" , 0x11800a0041c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_58" , 0x11800a0041d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_59" , 0x11800a0041d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_60" , 0x11800a0041e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_61" , 0x11800a0041e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_62" , 0x11800a0041f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT0_63" , 0x11800a0041f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_STAT10_0" , 0x11800a0040050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_1" , 0x11800a00400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_2" , 0x11800a0040150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_3" , 0x11800a00401d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_4" , 0x11800a0040250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_5" , 0x11800a00402d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_6" , 0x11800a0040350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_7" , 0x11800a00403d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_8" , 0x11800a0040450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_9" , 0x11800a00404d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_10" , 0x11800a0040550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_11" , 0x11800a00405d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_12" , 0x11800a0040650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_13" , 0x11800a00406d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_14" , 0x11800a0040750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_15" , 0x11800a00407d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_16" , 0x11800a0040850ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_17" , 0x11800a00408d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_18" , 0x11800a0040950ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_19" , 0x11800a00409d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_20" , 0x11800a0040a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_21" , 0x11800a0040ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_22" , 0x11800a0040b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_23" , 0x11800a0040bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_24" , 0x11800a0040c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_25" , 0x11800a0040cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_26" , 0x11800a0040d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_27" , 0x11800a0040dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_28" , 0x11800a0040e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_29" , 0x11800a0040ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_30" , 0x11800a0040f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_31" , 0x11800a0040fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_32" , 0x11800a0041050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_33" , 0x11800a00410d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_34" , 0x11800a0041150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_35" , 0x11800a00411d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_36" , 0x11800a0041250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_37" , 0x11800a00412d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_38" , 0x11800a0041350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_39" , 0x11800a00413d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_40" , 0x11800a0041450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_41" , 0x11800a00414d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_42" , 0x11800a0041550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_43" , 0x11800a00415d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_44" , 0x11800a0041650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_45" , 0x11800a00416d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_46" , 0x11800a0041750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_47" , 0x11800a00417d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_48" , 0x11800a0041850ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_49" , 0x11800a00418d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_50" , 0x11800a0041950ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_51" , 0x11800a00419d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_52" , 0x11800a0041a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_53" , 0x11800a0041ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_54" , 0x11800a0041b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_55" , 0x11800a0041bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_56" , 0x11800a0041c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_57" , 0x11800a0041cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_58" , 0x11800a0041d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_59" , 0x11800a0041dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_60" , 0x11800a0041e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_61" , 0x11800a0041ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_62" , 0x11800a0041f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT10_63" , 0x11800a0041fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_STAT11_0" , 0x11800a0040058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_1" , 0x11800a00400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_2" , 0x11800a0040158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_3" , 0x11800a00401d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_4" , 0x11800a0040258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_5" , 0x11800a00402d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_6" , 0x11800a0040358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_7" , 0x11800a00403d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_8" , 0x11800a0040458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_9" , 0x11800a00404d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_10" , 0x11800a0040558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_11" , 0x11800a00405d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_12" , 0x11800a0040658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_13" , 0x11800a00406d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_14" , 0x11800a0040758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_15" , 0x11800a00407d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_16" , 0x11800a0040858ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_17" , 0x11800a00408d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_18" , 0x11800a0040958ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_19" , 0x11800a00409d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_20" , 0x11800a0040a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_21" , 0x11800a0040ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_22" , 0x11800a0040b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_23" , 0x11800a0040bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_24" , 0x11800a0040c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_25" , 0x11800a0040cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_26" , 0x11800a0040d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_27" , 0x11800a0040dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_28" , 0x11800a0040e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_29" , 0x11800a0040ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_30" , 0x11800a0040f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_31" , 0x11800a0040fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_32" , 0x11800a0041058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_33" , 0x11800a00410d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_34" , 0x11800a0041158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_35" , 0x11800a00411d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_36" , 0x11800a0041258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_37" , 0x11800a00412d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_38" , 0x11800a0041358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_39" , 0x11800a00413d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_40" , 0x11800a0041458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_41" , 0x11800a00414d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_42" , 0x11800a0041558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_43" , 0x11800a00415d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_44" , 0x11800a0041658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_45" , 0x11800a00416d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_46" , 0x11800a0041758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_47" , 0x11800a00417d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_48" , 0x11800a0041858ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_49" , 0x11800a00418d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_50" , 0x11800a0041958ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_51" , 0x11800a00419d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_52" , 0x11800a0041a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_53" , 0x11800a0041ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_54" , 0x11800a0041b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_55" , 0x11800a0041bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_56" , 0x11800a0041c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_57" , 0x11800a0041cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_58" , 0x11800a0041d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_59" , 0x11800a0041dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_60" , 0x11800a0041e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_61" , 0x11800a0041ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_62" , 0x11800a0041f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT11_63" , 0x11800a0041fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_STAT1_0" , 0x11800a0040008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_1" , 0x11800a0040088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_2" , 0x11800a0040108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_3" , 0x11800a0040188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_4" , 0x11800a0040208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_5" , 0x11800a0040288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_6" , 0x11800a0040308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_7" , 0x11800a0040388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_8" , 0x11800a0040408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_9" , 0x11800a0040488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_10" , 0x11800a0040508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_11" , 0x11800a0040588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_12" , 0x11800a0040608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_13" , 0x11800a0040688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_14" , 0x11800a0040708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_15" , 0x11800a0040788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_16" , 0x11800a0040808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_17" , 0x11800a0040888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_18" , 0x11800a0040908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_19" , 0x11800a0040988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_20" , 0x11800a0040a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_21" , 0x11800a0040a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_22" , 0x11800a0040b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_23" , 0x11800a0040b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_24" , 0x11800a0040c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_25" , 0x11800a0040c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_26" , 0x11800a0040d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_27" , 0x11800a0040d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_28" , 0x11800a0040e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_29" , 0x11800a0040e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_30" , 0x11800a0040f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_31" , 0x11800a0040f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_32" , 0x11800a0041008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_33" , 0x11800a0041088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_34" , 0x11800a0041108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_35" , 0x11800a0041188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_36" , 0x11800a0041208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_37" , 0x11800a0041288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_38" , 0x11800a0041308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_39" , 0x11800a0041388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_40" , 0x11800a0041408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_41" , 0x11800a0041488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_42" , 0x11800a0041508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_43" , 0x11800a0041588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_44" , 0x11800a0041608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_45" , 0x11800a0041688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_46" , 0x11800a0041708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_47" , 0x11800a0041788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_48" , 0x11800a0041808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_49" , 0x11800a0041888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_50" , 0x11800a0041908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_51" , 0x11800a0041988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_52" , 0x11800a0041a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_53" , 0x11800a0041a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_54" , 0x11800a0041b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_55" , 0x11800a0041b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_56" , 0x11800a0041c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_57" , 0x11800a0041c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_58" , 0x11800a0041d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_59" , 0x11800a0041d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_60" , 0x11800a0041e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_61" , 0x11800a0041e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_62" , 0x11800a0041f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT1_63" , 0x11800a0041f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_STAT2_0" , 0x11800a0040010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_1" , 0x11800a0040090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_2" , 0x11800a0040110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_3" , 0x11800a0040190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_4" , 0x11800a0040210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_5" , 0x11800a0040290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_6" , 0x11800a0040310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_7" , 0x11800a0040390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_8" , 0x11800a0040410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_9" , 0x11800a0040490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_10" , 0x11800a0040510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_11" , 0x11800a0040590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_12" , 0x11800a0040610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_13" , 0x11800a0040690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_14" , 0x11800a0040710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_15" , 0x11800a0040790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_16" , 0x11800a0040810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_17" , 0x11800a0040890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_18" , 0x11800a0040910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_19" , 0x11800a0040990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_20" , 0x11800a0040a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_21" , 0x11800a0040a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_22" , 0x11800a0040b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_23" , 0x11800a0040b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_24" , 0x11800a0040c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_25" , 0x11800a0040c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_26" , 0x11800a0040d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_27" , 0x11800a0040d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_28" , 0x11800a0040e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_29" , 0x11800a0040e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_30" , 0x11800a0040f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_31" , 0x11800a0040f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_32" , 0x11800a0041010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_33" , 0x11800a0041090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_34" , 0x11800a0041110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_35" , 0x11800a0041190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_36" , 0x11800a0041210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_37" , 0x11800a0041290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_38" , 0x11800a0041310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_39" , 0x11800a0041390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_40" , 0x11800a0041410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_41" , 0x11800a0041490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_42" , 0x11800a0041510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_43" , 0x11800a0041590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_44" , 0x11800a0041610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_45" , 0x11800a0041690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_46" , 0x11800a0041710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_47" , 0x11800a0041790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_48" , 0x11800a0041810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_49" , 0x11800a0041890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_50" , 0x11800a0041910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_51" , 0x11800a0041990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_52" , 0x11800a0041a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_53" , 0x11800a0041a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_54" , 0x11800a0041b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_55" , 0x11800a0041b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_56" , 0x11800a0041c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_57" , 0x11800a0041c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_58" , 0x11800a0041d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_59" , 0x11800a0041d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_60" , 0x11800a0041e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_61" , 0x11800a0041e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_62" , 0x11800a0041f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT2_63" , 0x11800a0041f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_STAT3_0" , 0x11800a0040018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_1" , 0x11800a0040098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_2" , 0x11800a0040118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_3" , 0x11800a0040198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_4" , 0x11800a0040218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_5" , 0x11800a0040298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_6" , 0x11800a0040318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_7" , 0x11800a0040398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_8" , 0x11800a0040418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_9" , 0x11800a0040498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_10" , 0x11800a0040518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_11" , 0x11800a0040598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_12" , 0x11800a0040618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_13" , 0x11800a0040698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_14" , 0x11800a0040718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_15" , 0x11800a0040798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_16" , 0x11800a0040818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_17" , 0x11800a0040898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_18" , 0x11800a0040918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_19" , 0x11800a0040998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_20" , 0x11800a0040a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_21" , 0x11800a0040a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_22" , 0x11800a0040b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_23" , 0x11800a0040b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_24" , 0x11800a0040c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_25" , 0x11800a0040c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_26" , 0x11800a0040d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_27" , 0x11800a0040d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_28" , 0x11800a0040e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_29" , 0x11800a0040e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_30" , 0x11800a0040f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_31" , 0x11800a0040f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_32" , 0x11800a0041018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_33" , 0x11800a0041098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_34" , 0x11800a0041118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_35" , 0x11800a0041198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_36" , 0x11800a0041218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_37" , 0x11800a0041298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_38" , 0x11800a0041318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_39" , 0x11800a0041398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_40" , 0x11800a0041418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_41" , 0x11800a0041498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_42" , 0x11800a0041518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_43" , 0x11800a0041598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_44" , 0x11800a0041618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_45" , 0x11800a0041698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_46" , 0x11800a0041718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_47" , 0x11800a0041798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_48" , 0x11800a0041818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_49" , 0x11800a0041898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_50" , 0x11800a0041918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_51" , 0x11800a0041998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_52" , 0x11800a0041a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_53" , 0x11800a0041a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_54" , 0x11800a0041b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_55" , 0x11800a0041b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_56" , 0x11800a0041c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_57" , 0x11800a0041c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_58" , 0x11800a0041d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_59" , 0x11800a0041d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_60" , 0x11800a0041e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_61" , 0x11800a0041e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_62" , 0x11800a0041f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT3_63" , 0x11800a0041f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_STAT4_0" , 0x11800a0040020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_1" , 0x11800a00400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_2" , 0x11800a0040120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_3" , 0x11800a00401a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_4" , 0x11800a0040220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_5" , 0x11800a00402a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_6" , 0x11800a0040320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_7" , 0x11800a00403a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_8" , 0x11800a0040420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_9" , 0x11800a00404a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_10" , 0x11800a0040520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_11" , 0x11800a00405a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_12" , 0x11800a0040620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_13" , 0x11800a00406a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_14" , 0x11800a0040720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_15" , 0x11800a00407a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_16" , 0x11800a0040820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_17" , 0x11800a00408a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_18" , 0x11800a0040920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_19" , 0x11800a00409a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_20" , 0x11800a0040a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_21" , 0x11800a0040aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_22" , 0x11800a0040b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_23" , 0x11800a0040ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_24" , 0x11800a0040c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_25" , 0x11800a0040ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_26" , 0x11800a0040d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_27" , 0x11800a0040da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_28" , 0x11800a0040e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_29" , 0x11800a0040ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_30" , 0x11800a0040f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_31" , 0x11800a0040fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_32" , 0x11800a0041020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_33" , 0x11800a00410a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_34" , 0x11800a0041120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_35" , 0x11800a00411a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_36" , 0x11800a0041220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_37" , 0x11800a00412a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_38" , 0x11800a0041320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_39" , 0x11800a00413a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_40" , 0x11800a0041420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_41" , 0x11800a00414a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_42" , 0x11800a0041520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_43" , 0x11800a00415a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_44" , 0x11800a0041620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_45" , 0x11800a00416a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_46" , 0x11800a0041720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_47" , 0x11800a00417a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_48" , 0x11800a0041820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_49" , 0x11800a00418a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_50" , 0x11800a0041920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_51" , 0x11800a00419a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_52" , 0x11800a0041a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_53" , 0x11800a0041aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_54" , 0x11800a0041b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_55" , 0x11800a0041ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_56" , 0x11800a0041c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_57" , 0x11800a0041ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_58" , 0x11800a0041d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_59" , 0x11800a0041da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_60" , 0x11800a0041e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_61" , 0x11800a0041ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_62" , 0x11800a0041f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT4_63" , 0x11800a0041fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_STAT5_0" , 0x11800a0040028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_1" , 0x11800a00400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_2" , 0x11800a0040128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_3" , 0x11800a00401a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_4" , 0x11800a0040228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_5" , 0x11800a00402a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_6" , 0x11800a0040328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_7" , 0x11800a00403a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_8" , 0x11800a0040428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_9" , 0x11800a00404a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_10" , 0x11800a0040528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_11" , 0x11800a00405a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_12" , 0x11800a0040628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_13" , 0x11800a00406a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_14" , 0x11800a0040728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_15" , 0x11800a00407a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_16" , 0x11800a0040828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_17" , 0x11800a00408a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_18" , 0x11800a0040928ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_19" , 0x11800a00409a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_20" , 0x11800a0040a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_21" , 0x11800a0040aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_22" , 0x11800a0040b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_23" , 0x11800a0040ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_24" , 0x11800a0040c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_25" , 0x11800a0040ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_26" , 0x11800a0040d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_27" , 0x11800a0040da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_28" , 0x11800a0040e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_29" , 0x11800a0040ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_30" , 0x11800a0040f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_31" , 0x11800a0040fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_32" , 0x11800a0041028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_33" , 0x11800a00410a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_34" , 0x11800a0041128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_35" , 0x11800a00411a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_36" , 0x11800a0041228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_37" , 0x11800a00412a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_38" , 0x11800a0041328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_39" , 0x11800a00413a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_40" , 0x11800a0041428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_41" , 0x11800a00414a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_42" , 0x11800a0041528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_43" , 0x11800a00415a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_44" , 0x11800a0041628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_45" , 0x11800a00416a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_46" , 0x11800a0041728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_47" , 0x11800a00417a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_48" , 0x11800a0041828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_49" , 0x11800a00418a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_50" , 0x11800a0041928ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_51" , 0x11800a00419a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_52" , 0x11800a0041a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_53" , 0x11800a0041aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_54" , 0x11800a0041b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_55" , 0x11800a0041ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_56" , 0x11800a0041c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_57" , 0x11800a0041ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_58" , 0x11800a0041d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_59" , 0x11800a0041da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_60" , 0x11800a0041e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_61" , 0x11800a0041ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_62" , 0x11800a0041f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT5_63" , 0x11800a0041fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_STAT6_0" , 0x11800a0040030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_1" , 0x11800a00400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_2" , 0x11800a0040130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_3" , 0x11800a00401b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_4" , 0x11800a0040230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_5" , 0x11800a00402b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_6" , 0x11800a0040330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_7" , 0x11800a00403b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_8" , 0x11800a0040430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_9" , 0x11800a00404b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_10" , 0x11800a0040530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_11" , 0x11800a00405b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_12" , 0x11800a0040630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_13" , 0x11800a00406b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_14" , 0x11800a0040730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_15" , 0x11800a00407b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_16" , 0x11800a0040830ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_17" , 0x11800a00408b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_18" , 0x11800a0040930ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_19" , 0x11800a00409b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_20" , 0x11800a0040a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_21" , 0x11800a0040ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_22" , 0x11800a0040b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_23" , 0x11800a0040bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_24" , 0x11800a0040c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_25" , 0x11800a0040cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_26" , 0x11800a0040d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_27" , 0x11800a0040db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_28" , 0x11800a0040e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_29" , 0x11800a0040eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_30" , 0x11800a0040f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_31" , 0x11800a0040fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_32" , 0x11800a0041030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_33" , 0x11800a00410b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_34" , 0x11800a0041130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_35" , 0x11800a00411b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_36" , 0x11800a0041230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_37" , 0x11800a00412b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_38" , 0x11800a0041330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_39" , 0x11800a00413b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_40" , 0x11800a0041430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_41" , 0x11800a00414b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_42" , 0x11800a0041530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_43" , 0x11800a00415b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_44" , 0x11800a0041630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_45" , 0x11800a00416b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_46" , 0x11800a0041730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_47" , 0x11800a00417b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_48" , 0x11800a0041830ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_49" , 0x11800a00418b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_50" , 0x11800a0041930ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_51" , 0x11800a00419b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_52" , 0x11800a0041a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_53" , 0x11800a0041ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_54" , 0x11800a0041b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_55" , 0x11800a0041bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_56" , 0x11800a0041c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_57" , 0x11800a0041cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_58" , 0x11800a0041d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_59" , 0x11800a0041db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_60" , 0x11800a0041e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_61" , 0x11800a0041eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_62" , 0x11800a0041f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT6_63" , 0x11800a0041fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_STAT7_0" , 0x11800a0040038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_1" , 0x11800a00400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_2" , 0x11800a0040138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_3" , 0x11800a00401b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_4" , 0x11800a0040238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_5" , 0x11800a00402b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_6" , 0x11800a0040338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_7" , 0x11800a00403b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_8" , 0x11800a0040438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_9" , 0x11800a00404b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_10" , 0x11800a0040538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_11" , 0x11800a00405b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_12" , 0x11800a0040638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_13" , 0x11800a00406b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_14" , 0x11800a0040738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_15" , 0x11800a00407b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_16" , 0x11800a0040838ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_17" , 0x11800a00408b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_18" , 0x11800a0040938ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_19" , 0x11800a00409b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_20" , 0x11800a0040a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_21" , 0x11800a0040ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_22" , 0x11800a0040b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_23" , 0x11800a0040bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_24" , 0x11800a0040c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_25" , 0x11800a0040cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_26" , 0x11800a0040d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_27" , 0x11800a0040db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_28" , 0x11800a0040e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_29" , 0x11800a0040eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_30" , 0x11800a0040f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_31" , 0x11800a0040fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_32" , 0x11800a0041038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_33" , 0x11800a00410b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_34" , 0x11800a0041138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_35" , 0x11800a00411b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_36" , 0x11800a0041238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_37" , 0x11800a00412b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_38" , 0x11800a0041338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_39" , 0x11800a00413b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_40" , 0x11800a0041438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_41" , 0x11800a00414b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_42" , 0x11800a0041538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_43" , 0x11800a00415b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_44" , 0x11800a0041638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_45" , 0x11800a00416b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_46" , 0x11800a0041738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_47" , 0x11800a00417b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_48" , 0x11800a0041838ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_49" , 0x11800a00418b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_50" , 0x11800a0041938ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_51" , 0x11800a00419b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_52" , 0x11800a0041a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_53" , 0x11800a0041ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_54" , 0x11800a0041b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_55" , 0x11800a0041bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_56" , 0x11800a0041c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_57" , 0x11800a0041cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_58" , 0x11800a0041d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_59" , 0x11800a0041db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_60" , 0x11800a0041e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_61" , 0x11800a0041eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_62" , 0x11800a0041f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT7_63" , 0x11800a0041fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_STAT8_0" , 0x11800a0040040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_1" , 0x11800a00400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_2" , 0x11800a0040140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_3" , 0x11800a00401c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_4" , 0x11800a0040240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_5" , 0x11800a00402c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_6" , 0x11800a0040340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_7" , 0x11800a00403c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_8" , 0x11800a0040440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_9" , 0x11800a00404c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_10" , 0x11800a0040540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_11" , 0x11800a00405c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_12" , 0x11800a0040640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_13" , 0x11800a00406c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_14" , 0x11800a0040740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_15" , 0x11800a00407c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_16" , 0x11800a0040840ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_17" , 0x11800a00408c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_18" , 0x11800a0040940ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_19" , 0x11800a00409c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_20" , 0x11800a0040a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_21" , 0x11800a0040ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_22" , 0x11800a0040b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_23" , 0x11800a0040bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_24" , 0x11800a0040c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_25" , 0x11800a0040cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_26" , 0x11800a0040d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_27" , 0x11800a0040dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_28" , 0x11800a0040e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_29" , 0x11800a0040ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_30" , 0x11800a0040f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_31" , 0x11800a0040fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_32" , 0x11800a0041040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_33" , 0x11800a00410c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_34" , 0x11800a0041140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_35" , 0x11800a00411c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_36" , 0x11800a0041240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_37" , 0x11800a00412c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_38" , 0x11800a0041340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_39" , 0x11800a00413c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_40" , 0x11800a0041440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_41" , 0x11800a00414c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_42" , 0x11800a0041540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_43" , 0x11800a00415c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_44" , 0x11800a0041640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_45" , 0x11800a00416c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_46" , 0x11800a0041740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_47" , 0x11800a00417c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_48" , 0x11800a0041840ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_49" , 0x11800a00418c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_50" , 0x11800a0041940ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_51" , 0x11800a00419c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_52" , 0x11800a0041a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_53" , 0x11800a0041ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_54" , 0x11800a0041b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_55" , 0x11800a0041bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_56" , 0x11800a0041c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_57" , 0x11800a0041cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_58" , 0x11800a0041d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_59" , 0x11800a0041dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_60" , 0x11800a0041e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_61" , 0x11800a0041ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_62" , 0x11800a0041f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT8_63" , 0x11800a0041fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_STAT9_0" , 0x11800a0040048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_1" , 0x11800a00400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_2" , 0x11800a0040148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_3" , 0x11800a00401c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_4" , 0x11800a0040248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_5" , 0x11800a00402c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_6" , 0x11800a0040348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_7" , 0x11800a00403c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_8" , 0x11800a0040448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_9" , 0x11800a00404c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_10" , 0x11800a0040548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_11" , 0x11800a00405c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_12" , 0x11800a0040648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_13" , 0x11800a00406c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_14" , 0x11800a0040748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_15" , 0x11800a00407c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_16" , 0x11800a0040848ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_17" , 0x11800a00408c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_18" , 0x11800a0040948ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_19" , 0x11800a00409c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_20" , 0x11800a0040a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_21" , 0x11800a0040ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_22" , 0x11800a0040b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_23" , 0x11800a0040bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_24" , 0x11800a0040c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_25" , 0x11800a0040cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_26" , 0x11800a0040d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_27" , 0x11800a0040dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_28" , 0x11800a0040e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_29" , 0x11800a0040ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_30" , 0x11800a0040f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_31" , 0x11800a0040fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_32" , 0x11800a0041048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_33" , 0x11800a00410c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_34" , 0x11800a0041148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_35" , 0x11800a00411c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_36" , 0x11800a0041248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_37" , 0x11800a00412c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_38" , 0x11800a0041348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_39" , 0x11800a00413c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_40" , 0x11800a0041448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_41" , 0x11800a00414c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_42" , 0x11800a0041548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_43" , 0x11800a00415c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_44" , 0x11800a0041648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_45" , 0x11800a00416c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_46" , 0x11800a0041748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_47" , 0x11800a00417c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_48" , 0x11800a0041848ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_49" , 0x11800a00418c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_50" , 0x11800a0041948ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_51" , 0x11800a00419c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_52" , 0x11800a0041a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_53" , 0x11800a0041ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_54" , 0x11800a0041b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_55" , 0x11800a0041bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_56" , 0x11800a0041c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_57" , 0x11800a0041cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_58" , 0x11800a0041d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_59" , 0x11800a0041dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_60" , 0x11800a0041e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_61" , 0x11800a0041ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_62" , 0x11800a0041f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT9_63" , 0x11800a0041fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1023},
- {"PIP_STAT_INB_ERRS_PKND0" , 0x11800a0020010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND1" , 0x11800a0020030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND2" , 0x11800a0020050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND3" , 0x11800a0020070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND4" , 0x11800a0020090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND5" , 0x11800a00200b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND6" , 0x11800a00200d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND7" , 0x11800a00200f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND8" , 0x11800a0020110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND9" , 0x11800a0020130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND10" , 0x11800a0020150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND11" , 0x11800a0020170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND12" , 0x11800a0020190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND13" , 0x11800a00201b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND14" , 0x11800a00201d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND15" , 0x11800a00201f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND16" , 0x11800a0020210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND17" , 0x11800a0020230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND18" , 0x11800a0020250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND19" , 0x11800a0020270ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND20" , 0x11800a0020290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND21" , 0x11800a00202b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND22" , 0x11800a00202d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND23" , 0x11800a00202f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND24" , 0x11800a0020310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND25" , 0x11800a0020330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND26" , 0x11800a0020350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND27" , 0x11800a0020370ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND28" , 0x11800a0020390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND29" , 0x11800a00203b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND30" , 0x11800a00203d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND31" , 0x11800a00203f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND32" , 0x11800a0020410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND33" , 0x11800a0020430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND34" , 0x11800a0020450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND35" , 0x11800a0020470ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND36" , 0x11800a0020490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND37" , 0x11800a00204b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND38" , 0x11800a00204d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND39" , 0x11800a00204f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND40" , 0x11800a0020510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND41" , 0x11800a0020530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND42" , 0x11800a0020550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND43" , 0x11800a0020570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND44" , 0x11800a0020590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND45" , 0x11800a00205b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND46" , 0x11800a00205d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND47" , 0x11800a00205f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND48" , 0x11800a0020610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND49" , 0x11800a0020630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND50" , 0x11800a0020650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND51" , 0x11800a0020670ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND52" , 0x11800a0020690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND53" , 0x11800a00206b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND54" , 0x11800a00206d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND55" , 0x11800a00206f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND56" , 0x11800a0020710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND57" , 0x11800a0020730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND58" , 0x11800a0020750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND59" , 0x11800a0020770ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND60" , 0x11800a0020790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND61" , 0x11800a00207b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND62" , 0x11800a00207d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_ERRS_PKND63" , 0x11800a00207f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_STAT_INB_OCTS_PKND0" , 0x11800a0020008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND1" , 0x11800a0020028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND2" , 0x11800a0020048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND3" , 0x11800a0020068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND4" , 0x11800a0020088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND5" , 0x11800a00200a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND6" , 0x11800a00200c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND7" , 0x11800a00200e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND8" , 0x11800a0020108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND9" , 0x11800a0020128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND10" , 0x11800a0020148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND11" , 0x11800a0020168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND12" , 0x11800a0020188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND13" , 0x11800a00201a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND14" , 0x11800a00201c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND15" , 0x11800a00201e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND16" , 0x11800a0020208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND17" , 0x11800a0020228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND18" , 0x11800a0020248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND19" , 0x11800a0020268ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND20" , 0x11800a0020288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND21" , 0x11800a00202a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND22" , 0x11800a00202c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND23" , 0x11800a00202e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND24" , 0x11800a0020308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND25" , 0x11800a0020328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND26" , 0x11800a0020348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND27" , 0x11800a0020368ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND28" , 0x11800a0020388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND29" , 0x11800a00203a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND30" , 0x11800a00203c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND31" , 0x11800a00203e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND32" , 0x11800a0020408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND33" , 0x11800a0020428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND34" , 0x11800a0020448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND35" , 0x11800a0020468ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND36" , 0x11800a0020488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND37" , 0x11800a00204a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND38" , 0x11800a00204c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND39" , 0x11800a00204e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND40" , 0x11800a0020508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND41" , 0x11800a0020528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND42" , 0x11800a0020548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND43" , 0x11800a0020568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND44" , 0x11800a0020588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND45" , 0x11800a00205a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND46" , 0x11800a00205c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND47" , 0x11800a00205e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND48" , 0x11800a0020608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND49" , 0x11800a0020628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND50" , 0x11800a0020648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND51" , 0x11800a0020668ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND52" , 0x11800a0020688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND53" , 0x11800a00206a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND54" , 0x11800a00206c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND55" , 0x11800a00206e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND56" , 0x11800a0020708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND57" , 0x11800a0020728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND58" , 0x11800a0020748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND59" , 0x11800a0020768ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND60" , 0x11800a0020788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND61" , 0x11800a00207a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND62" , 0x11800a00207c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_OCTS_PKND63" , 0x11800a00207e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_STAT_INB_PKTS_PKND0" , 0x11800a0020000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND1" , 0x11800a0020020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND2" , 0x11800a0020040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND3" , 0x11800a0020060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND4" , 0x11800a0020080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND5" , 0x11800a00200a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND6" , 0x11800a00200c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND7" , 0x11800a00200e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND8" , 0x11800a0020100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND9" , 0x11800a0020120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND10" , 0x11800a0020140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND11" , 0x11800a0020160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND12" , 0x11800a0020180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND13" , 0x11800a00201a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND14" , 0x11800a00201c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND15" , 0x11800a00201e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND16" , 0x11800a0020200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND17" , 0x11800a0020220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND18" , 0x11800a0020240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND19" , 0x11800a0020260ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND20" , 0x11800a0020280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND21" , 0x11800a00202a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND22" , 0x11800a00202c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND23" , 0x11800a00202e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND24" , 0x11800a0020300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND25" , 0x11800a0020320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND26" , 0x11800a0020340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND27" , 0x11800a0020360ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND28" , 0x11800a0020380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND29" , 0x11800a00203a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND30" , 0x11800a00203c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND31" , 0x11800a00203e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND32" , 0x11800a0020400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND33" , 0x11800a0020420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND34" , 0x11800a0020440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND35" , 0x11800a0020460ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND36" , 0x11800a0020480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND37" , 0x11800a00204a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND38" , 0x11800a00204c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND39" , 0x11800a00204e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND40" , 0x11800a0020500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND41" , 0x11800a0020520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND42" , 0x11800a0020540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND43" , 0x11800a0020560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND44" , 0x11800a0020580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND45" , 0x11800a00205a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND46" , 0x11800a00205c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND47" , 0x11800a00205e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND48" , 0x11800a0020600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND49" , 0x11800a0020620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND50" , 0x11800a0020640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND51" , 0x11800a0020660ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND52" , 0x11800a0020680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND53" , 0x11800a00206a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND54" , 0x11800a00206c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND55" , 0x11800a00206e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND56" , 0x11800a0020700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND57" , 0x11800a0020720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND58" , 0x11800a0020740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND59" , 0x11800a0020760ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND60" , 0x11800a0020780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND61" , 0x11800a00207a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND62" , 0x11800a00207c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_STAT_INB_PKTS_PKND63" , 0x11800a00207e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_SUB_PKIND_FCS0" , 0x11800a0080000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1029},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1030},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1043},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1047},
- {"PKO_MEM_IPORT_PTRS" , 0x1180050001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PKO_MEM_IPORT_QOS" , 0x1180050001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1049},
- {"PKO_MEM_IQUEUE_PTRS" , 0x1180050001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1050},
- {"PKO_MEM_IQUEUE_QOS" , 0x1180050001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1051},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1052},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1053},
- {"PKO_MEM_THROTTLE_INT" , 0x1180050001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1054},
- {"PKO_MEM_THROTTLE_PIPE" , 0x1180050001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1055},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1056},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1057},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1058},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1059},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1060},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1061},
- {"PKO_REG_DEBUG4" , 0x11800500000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"PKO_REG_ENGINE_INFLIGHT1" , 0x1180050000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1064},
- {"PKO_REG_ENGINE_STORAGE0" , 0x1180050000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1065},
- {"PKO_REG_ENGINE_STORAGE1" , 0x1180050000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1065},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1066},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1067},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1068},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1069},
- {"PKO_REG_LOOPBACK_BPID" , 0x1180050000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1070},
- {"PKO_REG_LOOPBACK_PKIND" , 0x1180050000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1071},
- {"PKO_REG_MIN_PKT" , 0x1180050000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1072},
- {"PKO_REG_PREEMPT" , 0x1180050000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1073},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1074},
- {"PKO_REG_QUEUE_PREEMPT" , 0x1180050000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1075},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1076},
- {"PKO_REG_THROTTLE" , 0x1180050000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1077},
- {"PKO_REG_TIMESTAMP" , 0x1180050000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1078},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1079},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1080},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1081},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1082},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1083},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1084},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1085},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1086},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1088},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1089},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1090},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1092},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1093},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1094},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1095},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1096},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1097},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1098},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1099},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1100},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1101},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1102},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1103},
- {"RNM_EER_DBG" , 0x1180040000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1104},
- {"RNM_EER_KEY" , 0x1180040000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1105},
- {"RNM_SERIAL_NUM" , 0x1180040000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1106},
- {"SLI_BIST_STATUS" , 0x11f0000010580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1107},
- {"SLI_CTL_PORT0" , 0x11f0000010050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1108},
- {"SLI_CTL_PORT1" , 0x11f0000010060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1108},
- {"SLI_CTL_STATUS" , 0x11f0000010570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1109},
- {"SLI_DATA_OUT_CNT" , 0x11f00000105f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1110},
- {"SLI_DBG_DATA" , 0x11f0000010310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1111},
- {"SLI_DBG_SELECT" , 0x11f0000010300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1112},
- {"SLI_DMA0_CNT" , 0x11f0000010400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1113},
- {"SLI_DMA1_CNT" , 0x11f0000010410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1113},
- {"SLI_DMA0_INT_LEVEL" , 0x11f00000103e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1114},
- {"SLI_DMA1_INT_LEVEL" , 0x11f00000103f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1114},
- {"SLI_DMA0_TIM" , 0x11f0000010420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1115},
- {"SLI_DMA1_TIM" , 0x11f0000010430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1115},
- {"SLI_INT_ENB_CIU" , 0x11f0000013cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1116},
- {"SLI_INT_ENB_PORT0" , 0x11f0000010340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1117},
- {"SLI_INT_ENB_PORT1" , 0x11f0000010350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1117},
- {"SLI_INT_SUM" , 0x11f0000010330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1118},
- {"SLI_LAST_WIN_RDATA0" , 0x11f0000010600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1119},
- {"SLI_LAST_WIN_RDATA1" , 0x11f0000010610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1120},
- {"SLI_MAC_CREDIT_CNT" , 0x11f0000013d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1121},
- {"SLI_MAC_NUMBER" , 0x3e00ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1122},
- {"SLI_MEM_ACCESS_CTL" , 0x11f00000102f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1123},
- {"SLI_MEM_ACCESS_SUBID12" , 0x11f00000100e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID13" , 0x11f00000100f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID14" , 0x11f0000010100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID15" , 0x11f0000010110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID16" , 0x11f0000010120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID17" , 0x11f0000010130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID18" , 0x11f0000010140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID19" , 0x11f0000010150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID20" , 0x11f0000010160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID21" , 0x11f0000010170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID22" , 0x11f0000010180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID23" , 0x11f0000010190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID24" , 0x11f00000101a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID25" , 0x11f00000101b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID26" , 0x11f00000101c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MEM_ACCESS_SUBID27" , 0x11f00000101d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1124},
- {"SLI_MSI_ENB0" , 0x11f0000013c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1125},
- {"SLI_MSI_ENB1" , 0x11f0000013c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1126},
- {"SLI_MSI_ENB2" , 0x11f0000013c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1127},
- {"SLI_MSI_ENB3" , 0x11f0000013c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1128},
- {"SLI_MSI_RCV0" , 0x11f0000013c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1129},
- {"SLI_MSI_RCV1" , 0x11f0000013c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1130},
- {"SLI_MSI_RCV2" , 0x11f0000013c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1131},
- {"SLI_MSI_RCV3" , 0x11f0000013c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1132},
- {"SLI_MSI_RD_MAP" , 0x11f0000013ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1133},
- {"SLI_MSI_W1C_ENB0" , 0x11f0000013cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1134},
- {"SLI_MSI_W1C_ENB1" , 0x11f0000013d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1135},
- {"SLI_MSI_W1C_ENB2" , 0x11f0000013d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1136},
- {"SLI_MSI_W1C_ENB3" , 0x11f0000013d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1137},
- {"SLI_MSI_W1S_ENB0" , 0x11f0000013d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1138},
- {"SLI_MSI_W1S_ENB1" , 0x11f0000013d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1139},
- {"SLI_MSI_W1S_ENB2" , 0x11f0000013d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1140},
- {"SLI_MSI_W1S_ENB3" , 0x11f0000013d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1141},
- {"SLI_MSI_WR_MAP" , 0x11f0000013c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1142},
- {"SLI_PCIE_MSI_RCV" , 0x11f0000013cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1143},
- {"SLI_PCIE_MSI_RCV_B1" , 0x11f0000010650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1144},
- {"SLI_PCIE_MSI_RCV_B2" , 0x11f0000010660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_PCIE_MSI_RCV_B3" , 0x11f0000010670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1146},
- {"SLI_PKT0_CNTS" , 0x11f0000012400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT1_CNTS" , 0x11f0000012410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT2_CNTS" , 0x11f0000012420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT3_CNTS" , 0x11f0000012430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT4_CNTS" , 0x11f0000012440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT5_CNTS" , 0x11f0000012450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT6_CNTS" , 0x11f0000012460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT7_CNTS" , 0x11f0000012470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT8_CNTS" , 0x11f0000012480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT9_CNTS" , 0x11f0000012490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT10_CNTS" , 0x11f00000124a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT11_CNTS" , 0x11f00000124b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT12_CNTS" , 0x11f00000124c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT13_CNTS" , 0x11f00000124d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT14_CNTS" , 0x11f00000124e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT15_CNTS" , 0x11f00000124f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT16_CNTS" , 0x11f0000012500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT17_CNTS" , 0x11f0000012510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT18_CNTS" , 0x11f0000012520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT19_CNTS" , 0x11f0000012530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT20_CNTS" , 0x11f0000012540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT21_CNTS" , 0x11f0000012550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT22_CNTS" , 0x11f0000012560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT23_CNTS" , 0x11f0000012570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT24_CNTS" , 0x11f0000012580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT25_CNTS" , 0x11f0000012590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT26_CNTS" , 0x11f00000125a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT27_CNTS" , 0x11f00000125b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT28_CNTS" , 0x11f00000125c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT29_CNTS" , 0x11f00000125d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT30_CNTS" , 0x11f00000125e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT31_CNTS" , 0x11f00000125f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_PKT0_INSTR_BADDR" , 0x11f0000012800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT1_INSTR_BADDR" , 0x11f0000012810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT2_INSTR_BADDR" , 0x11f0000012820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT3_INSTR_BADDR" , 0x11f0000012830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT4_INSTR_BADDR" , 0x11f0000012840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT5_INSTR_BADDR" , 0x11f0000012850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT6_INSTR_BADDR" , 0x11f0000012860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT7_INSTR_BADDR" , 0x11f0000012870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT8_INSTR_BADDR" , 0x11f0000012880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT9_INSTR_BADDR" , 0x11f0000012890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT10_INSTR_BADDR" , 0x11f00000128a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT11_INSTR_BADDR" , 0x11f00000128b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT12_INSTR_BADDR" , 0x11f00000128c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT13_INSTR_BADDR" , 0x11f00000128d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT14_INSTR_BADDR" , 0x11f00000128e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT15_INSTR_BADDR" , 0x11f00000128f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT16_INSTR_BADDR" , 0x11f0000012900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT17_INSTR_BADDR" , 0x11f0000012910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT18_INSTR_BADDR" , 0x11f0000012920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT19_INSTR_BADDR" , 0x11f0000012930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT20_INSTR_BADDR" , 0x11f0000012940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT21_INSTR_BADDR" , 0x11f0000012950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT22_INSTR_BADDR" , 0x11f0000012960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT23_INSTR_BADDR" , 0x11f0000012970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT24_INSTR_BADDR" , 0x11f0000012980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT25_INSTR_BADDR" , 0x11f0000012990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT26_INSTR_BADDR" , 0x11f00000129a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT27_INSTR_BADDR" , 0x11f00000129b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT28_INSTR_BADDR" , 0x11f00000129c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT29_INSTR_BADDR" , 0x11f00000129d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT30_INSTR_BADDR" , 0x11f00000129e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT31_INSTR_BADDR" , 0x11f00000129f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_PKT0_INSTR_BAOFF_DBELL" , 0x11f0000012c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT1_INSTR_BAOFF_DBELL" , 0x11f0000012c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT2_INSTR_BAOFF_DBELL" , 0x11f0000012c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT3_INSTR_BAOFF_DBELL" , 0x11f0000012c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT4_INSTR_BAOFF_DBELL" , 0x11f0000012c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT5_INSTR_BAOFF_DBELL" , 0x11f0000012c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT6_INSTR_BAOFF_DBELL" , 0x11f0000012c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT7_INSTR_BAOFF_DBELL" , 0x11f0000012c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT8_INSTR_BAOFF_DBELL" , 0x11f0000012c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT9_INSTR_BAOFF_DBELL" , 0x11f0000012c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT10_INSTR_BAOFF_DBELL" , 0x11f0000012ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT11_INSTR_BAOFF_DBELL" , 0x11f0000012cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT12_INSTR_BAOFF_DBELL" , 0x11f0000012cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT13_INSTR_BAOFF_DBELL" , 0x11f0000012cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT14_INSTR_BAOFF_DBELL" , 0x11f0000012ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT15_INSTR_BAOFF_DBELL" , 0x11f0000012cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT16_INSTR_BAOFF_DBELL" , 0x11f0000012d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT17_INSTR_BAOFF_DBELL" , 0x11f0000012d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT18_INSTR_BAOFF_DBELL" , 0x11f0000012d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT19_INSTR_BAOFF_DBELL" , 0x11f0000012d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT20_INSTR_BAOFF_DBELL" , 0x11f0000012d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT21_INSTR_BAOFF_DBELL" , 0x11f0000012d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT22_INSTR_BAOFF_DBELL" , 0x11f0000012d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT23_INSTR_BAOFF_DBELL" , 0x11f0000012d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT24_INSTR_BAOFF_DBELL" , 0x11f0000012d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT25_INSTR_BAOFF_DBELL" , 0x11f0000012d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT26_INSTR_BAOFF_DBELL" , 0x11f0000012da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT27_INSTR_BAOFF_DBELL" , 0x11f0000012db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT28_INSTR_BAOFF_DBELL" , 0x11f0000012dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT29_INSTR_BAOFF_DBELL" , 0x11f0000012dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT30_INSTR_BAOFF_DBELL" , 0x11f0000012de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT31_INSTR_BAOFF_DBELL" , 0x11f0000012df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_PKT0_INSTR_FIFO_RSIZE" , 0x11f0000013000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT1_INSTR_FIFO_RSIZE" , 0x11f0000013010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT2_INSTR_FIFO_RSIZE" , 0x11f0000013020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT3_INSTR_FIFO_RSIZE" , 0x11f0000013030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT4_INSTR_FIFO_RSIZE" , 0x11f0000013040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT5_INSTR_FIFO_RSIZE" , 0x11f0000013050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT6_INSTR_FIFO_RSIZE" , 0x11f0000013060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT7_INSTR_FIFO_RSIZE" , 0x11f0000013070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT8_INSTR_FIFO_RSIZE" , 0x11f0000013080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT9_INSTR_FIFO_RSIZE" , 0x11f0000013090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT10_INSTR_FIFO_RSIZE" , 0x11f00000130a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT11_INSTR_FIFO_RSIZE" , 0x11f00000130b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT12_INSTR_FIFO_RSIZE" , 0x11f00000130c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT13_INSTR_FIFO_RSIZE" , 0x11f00000130d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT14_INSTR_FIFO_RSIZE" , 0x11f00000130e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT15_INSTR_FIFO_RSIZE" , 0x11f00000130f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT16_INSTR_FIFO_RSIZE" , 0x11f0000013100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT17_INSTR_FIFO_RSIZE" , 0x11f0000013110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT18_INSTR_FIFO_RSIZE" , 0x11f0000013120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT19_INSTR_FIFO_RSIZE" , 0x11f0000013130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT20_INSTR_FIFO_RSIZE" , 0x11f0000013140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT21_INSTR_FIFO_RSIZE" , 0x11f0000013150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT22_INSTR_FIFO_RSIZE" , 0x11f0000013160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT23_INSTR_FIFO_RSIZE" , 0x11f0000013170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT24_INSTR_FIFO_RSIZE" , 0x11f0000013180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT25_INSTR_FIFO_RSIZE" , 0x11f0000013190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT26_INSTR_FIFO_RSIZE" , 0x11f00000131a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT27_INSTR_FIFO_RSIZE" , 0x11f00000131b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT28_INSTR_FIFO_RSIZE" , 0x11f00000131c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT29_INSTR_FIFO_RSIZE" , 0x11f00000131d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT30_INSTR_FIFO_RSIZE" , 0x11f00000131e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT31_INSTR_FIFO_RSIZE" , 0x11f00000131f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_PKT0_INSTR_HEADER" , 0x11f0000013400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT1_INSTR_HEADER" , 0x11f0000013410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT2_INSTR_HEADER" , 0x11f0000013420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT3_INSTR_HEADER" , 0x11f0000013430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT4_INSTR_HEADER" , 0x11f0000013440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT5_INSTR_HEADER" , 0x11f0000013450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT6_INSTR_HEADER" , 0x11f0000013460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT7_INSTR_HEADER" , 0x11f0000013470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT8_INSTR_HEADER" , 0x11f0000013480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT9_INSTR_HEADER" , 0x11f0000013490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT10_INSTR_HEADER" , 0x11f00000134a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT11_INSTR_HEADER" , 0x11f00000134b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT12_INSTR_HEADER" , 0x11f00000134c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT13_INSTR_HEADER" , 0x11f00000134d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT14_INSTR_HEADER" , 0x11f00000134e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT15_INSTR_HEADER" , 0x11f00000134f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT16_INSTR_HEADER" , 0x11f0000013500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT17_INSTR_HEADER" , 0x11f0000013510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT18_INSTR_HEADER" , 0x11f0000013520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT19_INSTR_HEADER" , 0x11f0000013530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT20_INSTR_HEADER" , 0x11f0000013540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT21_INSTR_HEADER" , 0x11f0000013550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT22_INSTR_HEADER" , 0x11f0000013560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT23_INSTR_HEADER" , 0x11f0000013570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT24_INSTR_HEADER" , 0x11f0000013580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT25_INSTR_HEADER" , 0x11f0000013590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT26_INSTR_HEADER" , 0x11f00000135a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT27_INSTR_HEADER" , 0x11f00000135b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT28_INSTR_HEADER" , 0x11f00000135c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT29_INSTR_HEADER" , 0x11f00000135d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT30_INSTR_HEADER" , 0x11f00000135e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT31_INSTR_HEADER" , 0x11f00000135f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_PKT0_OUT_SIZE" , 0x11f0000010c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT1_OUT_SIZE" , 0x11f0000010c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT2_OUT_SIZE" , 0x11f0000010c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT3_OUT_SIZE" , 0x11f0000010c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT4_OUT_SIZE" , 0x11f0000010c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT5_OUT_SIZE" , 0x11f0000010c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT6_OUT_SIZE" , 0x11f0000010c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT7_OUT_SIZE" , 0x11f0000010c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT8_OUT_SIZE" , 0x11f0000010c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT9_OUT_SIZE" , 0x11f0000010c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT10_OUT_SIZE" , 0x11f0000010ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT11_OUT_SIZE" , 0x11f0000010cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT12_OUT_SIZE" , 0x11f0000010cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT13_OUT_SIZE" , 0x11f0000010cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT14_OUT_SIZE" , 0x11f0000010ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT15_OUT_SIZE" , 0x11f0000010cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT16_OUT_SIZE" , 0x11f0000010d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT17_OUT_SIZE" , 0x11f0000010d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT18_OUT_SIZE" , 0x11f0000010d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT19_OUT_SIZE" , 0x11f0000010d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT20_OUT_SIZE" , 0x11f0000010d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT21_OUT_SIZE" , 0x11f0000010d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT22_OUT_SIZE" , 0x11f0000010d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT23_OUT_SIZE" , 0x11f0000010d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT24_OUT_SIZE" , 0x11f0000010d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT25_OUT_SIZE" , 0x11f0000010d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT26_OUT_SIZE" , 0x11f0000010da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT27_OUT_SIZE" , 0x11f0000010db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT28_OUT_SIZE" , 0x11f0000010dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT29_OUT_SIZE" , 0x11f0000010dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT30_OUT_SIZE" , 0x11f0000010de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT31_OUT_SIZE" , 0x11f0000010df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_PKT0_SLIST_BADDR" , 0x11f0000011400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT1_SLIST_BADDR" , 0x11f0000011410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT2_SLIST_BADDR" , 0x11f0000011420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT3_SLIST_BADDR" , 0x11f0000011430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT4_SLIST_BADDR" , 0x11f0000011440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT5_SLIST_BADDR" , 0x11f0000011450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT6_SLIST_BADDR" , 0x11f0000011460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT7_SLIST_BADDR" , 0x11f0000011470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT8_SLIST_BADDR" , 0x11f0000011480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT9_SLIST_BADDR" , 0x11f0000011490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT10_SLIST_BADDR" , 0x11f00000114a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT11_SLIST_BADDR" , 0x11f00000114b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT12_SLIST_BADDR" , 0x11f00000114c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT13_SLIST_BADDR" , 0x11f00000114d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT14_SLIST_BADDR" , 0x11f00000114e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT15_SLIST_BADDR" , 0x11f00000114f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT16_SLIST_BADDR" , 0x11f0000011500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT17_SLIST_BADDR" , 0x11f0000011510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT18_SLIST_BADDR" , 0x11f0000011520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT19_SLIST_BADDR" , 0x11f0000011530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT20_SLIST_BADDR" , 0x11f0000011540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT21_SLIST_BADDR" , 0x11f0000011550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT22_SLIST_BADDR" , 0x11f0000011560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT23_SLIST_BADDR" , 0x11f0000011570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT24_SLIST_BADDR" , 0x11f0000011580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT25_SLIST_BADDR" , 0x11f0000011590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT26_SLIST_BADDR" , 0x11f00000115a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT27_SLIST_BADDR" , 0x11f00000115b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT28_SLIST_BADDR" , 0x11f00000115c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT29_SLIST_BADDR" , 0x11f00000115d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT30_SLIST_BADDR" , 0x11f00000115e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT31_SLIST_BADDR" , 0x11f00000115f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_PKT0_SLIST_BAOFF_DBELL" , 0x11f0000011800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT1_SLIST_BAOFF_DBELL" , 0x11f0000011810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT2_SLIST_BAOFF_DBELL" , 0x11f0000011820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT3_SLIST_BAOFF_DBELL" , 0x11f0000011830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT4_SLIST_BAOFF_DBELL" , 0x11f0000011840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT5_SLIST_BAOFF_DBELL" , 0x11f0000011850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT6_SLIST_BAOFF_DBELL" , 0x11f0000011860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT7_SLIST_BAOFF_DBELL" , 0x11f0000011870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT8_SLIST_BAOFF_DBELL" , 0x11f0000011880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT9_SLIST_BAOFF_DBELL" , 0x11f0000011890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT10_SLIST_BAOFF_DBELL" , 0x11f00000118a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT11_SLIST_BAOFF_DBELL" , 0x11f00000118b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT12_SLIST_BAOFF_DBELL" , 0x11f00000118c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT13_SLIST_BAOFF_DBELL" , 0x11f00000118d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT14_SLIST_BAOFF_DBELL" , 0x11f00000118e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT15_SLIST_BAOFF_DBELL" , 0x11f00000118f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT16_SLIST_BAOFF_DBELL" , 0x11f0000011900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT17_SLIST_BAOFF_DBELL" , 0x11f0000011910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT18_SLIST_BAOFF_DBELL" , 0x11f0000011920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT19_SLIST_BAOFF_DBELL" , 0x11f0000011930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT20_SLIST_BAOFF_DBELL" , 0x11f0000011940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT21_SLIST_BAOFF_DBELL" , 0x11f0000011950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT22_SLIST_BAOFF_DBELL" , 0x11f0000011960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT23_SLIST_BAOFF_DBELL" , 0x11f0000011970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT24_SLIST_BAOFF_DBELL" , 0x11f0000011980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT25_SLIST_BAOFF_DBELL" , 0x11f0000011990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT26_SLIST_BAOFF_DBELL" , 0x11f00000119a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT27_SLIST_BAOFF_DBELL" , 0x11f00000119b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT28_SLIST_BAOFF_DBELL" , 0x11f00000119c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT29_SLIST_BAOFF_DBELL" , 0x11f00000119d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT30_SLIST_BAOFF_DBELL" , 0x11f00000119e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT31_SLIST_BAOFF_DBELL" , 0x11f00000119f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_PKT0_SLIST_FIFO_RSIZE" , 0x11f0000011c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT1_SLIST_FIFO_RSIZE" , 0x11f0000011c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT2_SLIST_FIFO_RSIZE" , 0x11f0000011c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT3_SLIST_FIFO_RSIZE" , 0x11f0000011c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT4_SLIST_FIFO_RSIZE" , 0x11f0000011c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT5_SLIST_FIFO_RSIZE" , 0x11f0000011c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT6_SLIST_FIFO_RSIZE" , 0x11f0000011c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT7_SLIST_FIFO_RSIZE" , 0x11f0000011c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT8_SLIST_FIFO_RSIZE" , 0x11f0000011c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT9_SLIST_FIFO_RSIZE" , 0x11f0000011c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT10_SLIST_FIFO_RSIZE" , 0x11f0000011ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT11_SLIST_FIFO_RSIZE" , 0x11f0000011cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT12_SLIST_FIFO_RSIZE" , 0x11f0000011cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT13_SLIST_FIFO_RSIZE" , 0x11f0000011cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT14_SLIST_FIFO_RSIZE" , 0x11f0000011ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT15_SLIST_FIFO_RSIZE" , 0x11f0000011cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT16_SLIST_FIFO_RSIZE" , 0x11f0000011d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT17_SLIST_FIFO_RSIZE" , 0x11f0000011d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT18_SLIST_FIFO_RSIZE" , 0x11f0000011d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT19_SLIST_FIFO_RSIZE" , 0x11f0000011d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT20_SLIST_FIFO_RSIZE" , 0x11f0000011d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT21_SLIST_FIFO_RSIZE" , 0x11f0000011d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT22_SLIST_FIFO_RSIZE" , 0x11f0000011d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT23_SLIST_FIFO_RSIZE" , 0x11f0000011d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT24_SLIST_FIFO_RSIZE" , 0x11f0000011d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT25_SLIST_FIFO_RSIZE" , 0x11f0000011d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT26_SLIST_FIFO_RSIZE" , 0x11f0000011da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT27_SLIST_FIFO_RSIZE" , 0x11f0000011db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT28_SLIST_FIFO_RSIZE" , 0x11f0000011dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT29_SLIST_FIFO_RSIZE" , 0x11f0000011dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT30_SLIST_FIFO_RSIZE" , 0x11f0000011de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT31_SLIST_FIFO_RSIZE" , 0x11f0000011df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_PKT_CNT_INT" , 0x11f0000011130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1156},
- {"SLI_PKT_CNT_INT_ENB" , 0x11f0000011150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1157},
- {"SLI_PKT_CTL" , 0x11f0000011220ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1158},
- {"SLI_PKT_DATA_OUT_ES" , 0x11f00000110b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1159},
- {"SLI_PKT_DATA_OUT_NS" , 0x11f00000110a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1160},
- {"SLI_PKT_DATA_OUT_ROR" , 0x11f0000011090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1161},
- {"SLI_PKT_DPADDR" , 0x11f0000011080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1162},
- {"SLI_PKT_IN_DONE0_CNTS" , 0x11f0000012000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE1_CNTS" , 0x11f0000012010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE2_CNTS" , 0x11f0000012020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE3_CNTS" , 0x11f0000012030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE4_CNTS" , 0x11f0000012040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE5_CNTS" , 0x11f0000012050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE6_CNTS" , 0x11f0000012060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE7_CNTS" , 0x11f0000012070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE8_CNTS" , 0x11f0000012080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE9_CNTS" , 0x11f0000012090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE10_CNTS" , 0x11f00000120a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE11_CNTS" , 0x11f00000120b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE12_CNTS" , 0x11f00000120c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE13_CNTS" , 0x11f00000120d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE14_CNTS" , 0x11f00000120e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE15_CNTS" , 0x11f00000120f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE16_CNTS" , 0x11f0000012100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE17_CNTS" , 0x11f0000012110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE18_CNTS" , 0x11f0000012120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE19_CNTS" , 0x11f0000012130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE20_CNTS" , 0x11f0000012140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE21_CNTS" , 0x11f0000012150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE22_CNTS" , 0x11f0000012160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE23_CNTS" , 0x11f0000012170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE24_CNTS" , 0x11f0000012180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE25_CNTS" , 0x11f0000012190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE26_CNTS" , 0x11f00000121a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE27_CNTS" , 0x11f00000121b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE28_CNTS" , 0x11f00000121c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE29_CNTS" , 0x11f00000121d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE30_CNTS" , 0x11f00000121e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_DONE31_CNTS" , 0x11f00000121f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PKT_IN_INSTR_COUNTS" , 0x11f0000011200ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1164},
- {"SLI_PKT_IN_PCIE_PORT" , 0x11f00000111b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1165},
- {"SLI_PKT_INPUT_CONTROL" , 0x11f0000011170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1166},
- {"SLI_PKT_INSTR_ENB" , 0x11f0000011000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1167},
- {"SLI_PKT_INSTR_RD_SIZE" , 0x11f00000111a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT_INSTR_SIZE" , 0x11f0000011020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT_INT_LEVELS" , 0x11f0000011120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT_IPTR" , 0x11f0000011070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT_OUT_BMODE" , 0x11f00000110d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT_OUT_BP_EN" , 0x11f0000011240ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT_OUT_ENB" , 0x11f0000011010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT_OUTPUT_WMARK" , 0x11f0000011180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT_PCIE_PORT" , 0x11f00000110e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT_PORT_IN_RST" , 0x11f00000111f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1177},
- {"SLI_PKT_SLIST_ES" , 0x11f0000011050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1178},
- {"SLI_PKT_SLIST_NS" , 0x11f0000011040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1179},
- {"SLI_PKT_SLIST_ROR" , 0x11f0000011030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1180},
- {"SLI_PKT_TIME_INT" , 0x11f0000011140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1181},
- {"SLI_PKT_TIME_INT_ENB" , 0x11f0000011160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1182},
- {"SLI_PORT0_PKIND" , 0x11f0000010800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT1_PKIND" , 0x11f0000010810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT2_PKIND" , 0x11f0000010820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT3_PKIND" , 0x11f0000010830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT4_PKIND" , 0x11f0000010840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT5_PKIND" , 0x11f0000010850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT6_PKIND" , 0x11f0000010860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT7_PKIND" , 0x11f0000010870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT8_PKIND" , 0x11f0000010880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT9_PKIND" , 0x11f0000010890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT10_PKIND" , 0x11f00000108a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT11_PKIND" , 0x11f00000108b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT12_PKIND" , 0x11f00000108c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT13_PKIND" , 0x11f00000108d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT14_PKIND" , 0x11f00000108e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT15_PKIND" , 0x11f00000108f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT16_PKIND" , 0x11f0000010900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT17_PKIND" , 0x11f0000010910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT18_PKIND" , 0x11f0000010920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT19_PKIND" , 0x11f0000010930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT20_PKIND" , 0x11f0000010940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT21_PKIND" , 0x11f0000010950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT22_PKIND" , 0x11f0000010960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT23_PKIND" , 0x11f0000010970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT24_PKIND" , 0x11f0000010980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT25_PKIND" , 0x11f0000010990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT26_PKIND" , 0x11f00000109a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT27_PKIND" , 0x11f00000109b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT28_PKIND" , 0x11f00000109c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT29_PKIND" , 0x11f00000109d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT30_PKIND" , 0x11f00000109e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PORT31_PKIND" , 0x11f00000109f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_S2M_PORT0_CTL" , 0x11f0000013d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_S2M_PORT1_CTL" , 0x11f0000013d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_SCRATCH_1" , 0x11f00000103c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1185},
- {"SLI_SCRATCH_2" , 0x11f00000103d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1186},
- {"SLI_STATE1" , 0x11f0000010620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1187},
- {"SLI_STATE2" , 0x11f0000010630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1188},
- {"SLI_STATE3" , 0x11f0000010640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1189},
- {"SLI_TX_PIPE" , 0x11f0000011230ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1190},
- {"SLI_WIN_RD_ADDR" , 0x10ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1191},
- {"SLI_WIN_RD_DATA" , 0x40ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1192},
- {"SLI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1193},
- {"SLI_WIN_WR_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1194},
- {"SLI_WIN_WR_MASK" , 0x30ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1195},
- {"SLI_WINDOW_CTL" , 0x11f00000102e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1196},
- {"SMI0_CLK" , 0x1180000003818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1197},
- {"SMI1_CLK" , 0x1180000003898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1197},
- {"SMI2_CLK" , 0x1180000003918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1197},
- {"SMI3_CLK" , 0x1180000003998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1197},
- {"SMI0_CMD" , 0x1180000003800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1198},
- {"SMI1_CMD" , 0x1180000003880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1198},
- {"SMI2_CMD" , 0x1180000003900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1198},
- {"SMI3_CMD" , 0x1180000003980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1198},
- {"SMI0_EN" , 0x1180000003820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1199},
- {"SMI1_EN" , 0x11800000038a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1199},
- {"SMI2_EN" , 0x1180000003920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1199},
- {"SMI3_EN" , 0x11800000039a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1199},
- {"SMI0_RD_DAT" , 0x1180000003810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1200},
- {"SMI1_RD_DAT" , 0x1180000003890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1200},
- {"SMI2_RD_DAT" , 0x1180000003910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1200},
- {"SMI3_RD_DAT" , 0x1180000003990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1200},
- {"SMI0_WR_DAT" , 0x1180000003808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1201},
- {"SMI1_WR_DAT" , 0x1180000003888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1201},
- {"SMI2_WR_DAT" , 0x1180000003908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1201},
- {"SMI3_WR_DAT" , 0x1180000003988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1201},
- {"SMI_DRV_CTL" , 0x1180000001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1202},
- {"SSO_BIST_STAT" , 0x1670000001078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1203},
- {"SSO_CFG" , 0x1670000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1204},
- {"SSO_DS_PC" , 0x1670000001070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1205},
- {"SSO_ERR" , 0x1670000001038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1206},
- {"SSO_ERR_ENB" , 0x1670000001030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1207},
- {"SSO_FIDX_ECC_CTL" , 0x16700000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1208},
- {"SSO_FIDX_ECC_ST" , 0x16700000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1209},
- {"SSO_FPAGE_CNT" , 0x1670000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1210},
- {"SSO_GWE_CFG" , 0x1670000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1211},
- {"SSO_IDX_ECC_CTL" , 0x16700000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1212},
- {"SSO_IDX_ECC_ST" , 0x16700000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1213},
- {"SSO_IQ_CNT0" , 0x1670000009000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1214},
- {"SSO_IQ_CNT1" , 0x1670000009008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1214},
- {"SSO_IQ_CNT2" , 0x1670000009010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1214},
- {"SSO_IQ_CNT3" , 0x1670000009018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1214},
- {"SSO_IQ_CNT4" , 0x1670000009020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1214},
- {"SSO_IQ_CNT5" , 0x1670000009028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1214},
- {"SSO_IQ_CNT6" , 0x1670000009030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1214},
- {"SSO_IQ_CNT7" , 0x1670000009038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1214},
- {"SSO_IQ_COM_CNT" , 0x1670000001058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1215},
- {"SSO_IQ_INT" , 0x1670000001048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1216},
- {"SSO_IQ_INT_EN" , 0x1670000001050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1217},
- {"SSO_IQ_THR0" , 0x167000000a000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1218},
- {"SSO_IQ_THR1" , 0x167000000a008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1218},
- {"SSO_IQ_THR2" , 0x167000000a010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1218},
- {"SSO_IQ_THR3" , 0x167000000a018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1218},
- {"SSO_IQ_THR4" , 0x167000000a020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1218},
- {"SSO_IQ_THR5" , 0x167000000a028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1218},
- {"SSO_IQ_THR6" , 0x167000000a030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1218},
- {"SSO_IQ_THR7" , 0x167000000a038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1218},
- {"SSO_NOS_CNT" , 0x1670000001040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1219},
- {"SSO_NW_TIM" , 0x1670000001028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1220},
- {"SSO_OTH_ECC_CTL" , 0x16700000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1221},
- {"SSO_OTH_ECC_ST" , 0x16700000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1222},
- {"SSO_PND_ECC_CTL" , 0x16700000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1223},
- {"SSO_PND_ECC_ST" , 0x16700000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1224},
- {"SSO_PP0_GRP_MSK" , 0x1670000006000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP1_GRP_MSK" , 0x1670000006008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP2_GRP_MSK" , 0x1670000006010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP3_GRP_MSK" , 0x1670000006018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP4_GRP_MSK" , 0x1670000006020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP5_GRP_MSK" , 0x1670000006028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP6_GRP_MSK" , 0x1670000006030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP7_GRP_MSK" , 0x1670000006038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP8_GRP_MSK" , 0x1670000006040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP9_GRP_MSK" , 0x1670000006048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP10_GRP_MSK" , 0x1670000006050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP11_GRP_MSK" , 0x1670000006058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP12_GRP_MSK" , 0x1670000006060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP13_GRP_MSK" , 0x1670000006068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP14_GRP_MSK" , 0x1670000006070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP15_GRP_MSK" , 0x1670000006078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP16_GRP_MSK" , 0x1670000006080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP17_GRP_MSK" , 0x1670000006088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP18_GRP_MSK" , 0x1670000006090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP19_GRP_MSK" , 0x1670000006098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP20_GRP_MSK" , 0x16700000060a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP21_GRP_MSK" , 0x16700000060a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP22_GRP_MSK" , 0x16700000060b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP23_GRP_MSK" , 0x16700000060b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP24_GRP_MSK" , 0x16700000060c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP25_GRP_MSK" , 0x16700000060c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP26_GRP_MSK" , 0x16700000060d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP27_GRP_MSK" , 0x16700000060d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP28_GRP_MSK" , 0x16700000060e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP29_GRP_MSK" , 0x16700000060e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP30_GRP_MSK" , 0x16700000060f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP31_GRP_MSK" , 0x16700000060f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_PP0_QOS_PRI" , 0x1670000003000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP1_QOS_PRI" , 0x1670000003008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP2_QOS_PRI" , 0x1670000003010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP3_QOS_PRI" , 0x1670000003018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP4_QOS_PRI" , 0x1670000003020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP5_QOS_PRI" , 0x1670000003028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP6_QOS_PRI" , 0x1670000003030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP7_QOS_PRI" , 0x1670000003038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP8_QOS_PRI" , 0x1670000003040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP9_QOS_PRI" , 0x1670000003048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP10_QOS_PRI" , 0x1670000003050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP11_QOS_PRI" , 0x1670000003058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP12_QOS_PRI" , 0x1670000003060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP13_QOS_PRI" , 0x1670000003068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP14_QOS_PRI" , 0x1670000003070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP15_QOS_PRI" , 0x1670000003078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP16_QOS_PRI" , 0x1670000003080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP17_QOS_PRI" , 0x1670000003088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP18_QOS_PRI" , 0x1670000003090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP19_QOS_PRI" , 0x1670000003098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP20_QOS_PRI" , 0x16700000030a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP21_QOS_PRI" , 0x16700000030a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP22_QOS_PRI" , 0x16700000030b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP23_QOS_PRI" , 0x16700000030b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP24_QOS_PRI" , 0x16700000030c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP25_QOS_PRI" , 0x16700000030c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP26_QOS_PRI" , 0x16700000030d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP27_QOS_PRI" , 0x16700000030d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP28_QOS_PRI" , 0x16700000030e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP29_QOS_PRI" , 0x16700000030e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP30_QOS_PRI" , 0x16700000030f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP31_QOS_PRI" , 0x16700000030f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_PP_STRICT" , 0x16700000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1227},
- {"SSO_QOS0_RND" , 0x1670000002000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1228},
- {"SSO_QOS1_RND" , 0x1670000002008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1228},
- {"SSO_QOS2_RND" , 0x1670000002010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1228},
- {"SSO_QOS3_RND" , 0x1670000002018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1228},
- {"SSO_QOS4_RND" , 0x1670000002020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1228},
- {"SSO_QOS5_RND" , 0x1670000002028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1228},
- {"SSO_QOS6_RND" , 0x1670000002030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1228},
- {"SSO_QOS7_RND" , 0x1670000002038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1228},
- {"SSO_QOS_THR0" , 0x167000000b000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1229},
- {"SSO_QOS_THR1" , 0x167000000b008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1229},
- {"SSO_QOS_THR2" , 0x167000000b010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1229},
- {"SSO_QOS_THR3" , 0x167000000b018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1229},
- {"SSO_QOS_THR4" , 0x167000000b020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1229},
- {"SSO_QOS_THR5" , 0x167000000b028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1229},
- {"SSO_QOS_THR6" , 0x167000000b030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1229},
- {"SSO_QOS_THR7" , 0x167000000b038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1229},
- {"SSO_QOS_WE" , 0x1670000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1230},
- {"SSO_RWQ_HEAD_PTR0" , 0x167000000c000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1231},
- {"SSO_RWQ_HEAD_PTR1" , 0x167000000c008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1231},
- {"SSO_RWQ_HEAD_PTR2" , 0x167000000c010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1231},
- {"SSO_RWQ_HEAD_PTR3" , 0x167000000c018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1231},
- {"SSO_RWQ_HEAD_PTR4" , 0x167000000c020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1231},
- {"SSO_RWQ_HEAD_PTR5" , 0x167000000c028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1231},
- {"SSO_RWQ_HEAD_PTR6" , 0x167000000c030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1231},
- {"SSO_RWQ_HEAD_PTR7" , 0x167000000c038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1231},
- {"SSO_RWQ_POP_FPTR" , 0x167000000c408ull, CVMX_CSR_DB_TYPE_NCB, 64, 1232},
- {"SSO_RWQ_PSH_FPTR" , 0x167000000c400ull, CVMX_CSR_DB_TYPE_NCB, 64, 1233},
- {"SSO_RWQ_TAIL_PTR0" , 0x167000000c200ull, CVMX_CSR_DB_TYPE_NCB, 64, 1234},
- {"SSO_RWQ_TAIL_PTR1" , 0x167000000c208ull, CVMX_CSR_DB_TYPE_NCB, 64, 1234},
- {"SSO_RWQ_TAIL_PTR2" , 0x167000000c210ull, CVMX_CSR_DB_TYPE_NCB, 64, 1234},
- {"SSO_RWQ_TAIL_PTR3" , 0x167000000c218ull, CVMX_CSR_DB_TYPE_NCB, 64, 1234},
- {"SSO_RWQ_TAIL_PTR4" , 0x167000000c220ull, CVMX_CSR_DB_TYPE_NCB, 64, 1234},
- {"SSO_RWQ_TAIL_PTR5" , 0x167000000c228ull, CVMX_CSR_DB_TYPE_NCB, 64, 1234},
- {"SSO_RWQ_TAIL_PTR6" , 0x167000000c230ull, CVMX_CSR_DB_TYPE_NCB, 64, 1234},
- {"SSO_RWQ_TAIL_PTR7" , 0x167000000c238ull, CVMX_CSR_DB_TYPE_NCB, 64, 1234},
- {"SSO_TS_PC" , 0x1670000001068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1235},
- {"SSO_WA_COM_PC" , 0x1670000001060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1236},
- {"SSO_WA_PC0" , 0x1670000005000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1237},
- {"SSO_WA_PC1" , 0x1670000005008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1237},
- {"SSO_WA_PC2" , 0x1670000005010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1237},
- {"SSO_WA_PC3" , 0x1670000005018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1237},
- {"SSO_WA_PC4" , 0x1670000005020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1237},
- {"SSO_WA_PC5" , 0x1670000005028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1237},
- {"SSO_WA_PC6" , 0x1670000005030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1237},
- {"SSO_WA_PC7" , 0x1670000005038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1237},
- {"SSO_WQ_INT" , 0x1670000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1238},
- {"SSO_WQ_INT_CNT0" , 0x1670000008000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT1" , 0x1670000008008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT2" , 0x1670000008010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT3" , 0x1670000008018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT4" , 0x1670000008020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT5" , 0x1670000008028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT6" , 0x1670000008030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT7" , 0x1670000008038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT8" , 0x1670000008040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT9" , 0x1670000008048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT10" , 0x1670000008050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT11" , 0x1670000008058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT12" , 0x1670000008060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT13" , 0x1670000008068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT14" , 0x1670000008070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT15" , 0x1670000008078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT16" , 0x1670000008080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT17" , 0x1670000008088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT18" , 0x1670000008090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT19" , 0x1670000008098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT20" , 0x16700000080a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT21" , 0x16700000080a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT22" , 0x16700000080b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT23" , 0x16700000080b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT24" , 0x16700000080c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT25" , 0x16700000080c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT26" , 0x16700000080d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT27" , 0x16700000080d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT28" , 0x16700000080e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT29" , 0x16700000080e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT30" , 0x16700000080f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT31" , 0x16700000080f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT32" , 0x1670000008100ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT33" , 0x1670000008108ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT34" , 0x1670000008110ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT35" , 0x1670000008118ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT36" , 0x1670000008120ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT37" , 0x1670000008128ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT38" , 0x1670000008130ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT39" , 0x1670000008138ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT40" , 0x1670000008140ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT41" , 0x1670000008148ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT42" , 0x1670000008150ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT43" , 0x1670000008158ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT44" , 0x1670000008160ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT45" , 0x1670000008168ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT46" , 0x1670000008170ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT47" , 0x1670000008178ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT48" , 0x1670000008180ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT49" , 0x1670000008188ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT50" , 0x1670000008190ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT51" , 0x1670000008198ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT52" , 0x16700000081a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT53" , 0x16700000081a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT54" , 0x16700000081b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT55" , 0x16700000081b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT56" , 0x16700000081c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT57" , 0x16700000081c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT58" , 0x16700000081d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT59" , 0x16700000081d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT60" , 0x16700000081e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT61" , 0x16700000081e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT62" , 0x16700000081f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_CNT63" , 0x16700000081f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_WQ_INT_PC" , 0x1670000001020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1240},
- {"SSO_WQ_INT_THR0" , 0x1670000007000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR1" , 0x1670000007008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR2" , 0x1670000007010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR3" , 0x1670000007018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR4" , 0x1670000007020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR5" , 0x1670000007028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR6" , 0x1670000007030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR7" , 0x1670000007038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR8" , 0x1670000007040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR9" , 0x1670000007048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR10" , 0x1670000007050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR11" , 0x1670000007058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR12" , 0x1670000007060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR13" , 0x1670000007068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR14" , 0x1670000007070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR15" , 0x1670000007078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR16" , 0x1670000007080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR17" , 0x1670000007088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR18" , 0x1670000007090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR19" , 0x1670000007098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR20" , 0x16700000070a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR21" , 0x16700000070a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR22" , 0x16700000070b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR23" , 0x16700000070b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR24" , 0x16700000070c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR25" , 0x16700000070c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR26" , 0x16700000070d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR27" , 0x16700000070d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR28" , 0x16700000070e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR29" , 0x16700000070e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR30" , 0x16700000070f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR31" , 0x16700000070f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR32" , 0x1670000007100ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR33" , 0x1670000007108ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR34" , 0x1670000007110ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR35" , 0x1670000007118ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR36" , 0x1670000007120ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR37" , 0x1670000007128ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR38" , 0x1670000007130ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR39" , 0x1670000007138ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR40" , 0x1670000007140ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR41" , 0x1670000007148ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR42" , 0x1670000007150ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR43" , 0x1670000007158ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR44" , 0x1670000007160ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR45" , 0x1670000007168ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR46" , 0x1670000007170ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR47" , 0x1670000007178ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR48" , 0x1670000007180ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR49" , 0x1670000007188ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR50" , 0x1670000007190ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR51" , 0x1670000007198ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR52" , 0x16700000071a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR53" , 0x16700000071a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR54" , 0x16700000071b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR55" , 0x16700000071b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR56" , 0x16700000071c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR57" , 0x16700000071c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR58" , 0x16700000071d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR59" , 0x16700000071d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR60" , 0x16700000071e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR61" , 0x16700000071e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR62" , 0x16700000071f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_INT_THR63" , 0x16700000071f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_WQ_IQ_DIS" , 0x1670000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1242},
- {"SSO_WS_PC0" , 0x1670000004000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC1" , 0x1670000004008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC2" , 0x1670000004010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC3" , 0x1670000004018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC4" , 0x1670000004020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC5" , 0x1670000004028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC6" , 0x1670000004030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC7" , 0x1670000004038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC8" , 0x1670000004040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC9" , 0x1670000004048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC10" , 0x1670000004050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC11" , 0x1670000004058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC12" , 0x1670000004060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC13" , 0x1670000004068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC14" , 0x1670000004070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC15" , 0x1670000004078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC16" , 0x1670000004080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC17" , 0x1670000004088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC18" , 0x1670000004090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC19" , 0x1670000004098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC20" , 0x16700000040a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC21" , 0x16700000040a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC22" , 0x16700000040b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC23" , 0x16700000040b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC24" , 0x16700000040c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC25" , 0x16700000040c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC26" , 0x16700000040d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC27" , 0x16700000040d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC28" , 0x16700000040e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC29" , 0x16700000040e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC30" , 0x16700000040f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC31" , 0x16700000040f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC32" , 0x1670000004100ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC33" , 0x1670000004108ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC34" , 0x1670000004110ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC35" , 0x1670000004118ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC36" , 0x1670000004120ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC37" , 0x1670000004128ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC38" , 0x1670000004130ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC39" , 0x1670000004138ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC40" , 0x1670000004140ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC41" , 0x1670000004148ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC42" , 0x1670000004150ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC43" , 0x1670000004158ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC44" , 0x1670000004160ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC45" , 0x1670000004168ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC46" , 0x1670000004170ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC47" , 0x1670000004178ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC48" , 0x1670000004180ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC49" , 0x1670000004188ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC50" , 0x1670000004190ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC51" , 0x1670000004198ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC52" , 0x16700000041a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC53" , 0x16700000041a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC54" , 0x16700000041b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC55" , 0x16700000041b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC56" , 0x16700000041c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC57" , 0x16700000041c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC58" , 0x16700000041d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC59" , 0x16700000041d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC60" , 0x16700000041e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC61" , 0x16700000041e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC62" , 0x16700000041f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_WS_PC63" , 0x16700000041f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"TIM_BIST_RESULT" , 0x1180058000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1244},
- {"TIM_DBG2" , 0x11800580000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1245},
- {"TIM_DBG3" , 0x11800580000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1246},
- {"TIM_ECC_CFG" , 0x1180058000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1247},
- {"TIM_FR_RN_TT" , 0x1180058000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1248},
- {"TIM_INT0" , 0x1180058000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1249},
- {"TIM_INT0_EN" , 0x1180058000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1250},
- {"TIM_INT0_EVENT" , 0x1180058000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1251},
- {"TIM_INT_ECCERR" , 0x1180058000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1252},
- {"TIM_INT_ECCERR_EN" , 0x1180058000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1253},
- {"TIM_INT_ECCERR_EVENT0" , 0x1180058000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1254},
- {"TIM_INT_ECCERR_EVENT1" , 0x1180058000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1255},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1256},
- {"TIM_RING0_CTL0" , 0x1180058002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING1_CTL0" , 0x1180058002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING2_CTL0" , 0x1180058002010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING3_CTL0" , 0x1180058002018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING4_CTL0" , 0x1180058002020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING5_CTL0" , 0x1180058002028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING6_CTL0" , 0x1180058002030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING7_CTL0" , 0x1180058002038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING8_CTL0" , 0x1180058002040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING9_CTL0" , 0x1180058002048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING10_CTL0" , 0x1180058002050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING11_CTL0" , 0x1180058002058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING12_CTL0" , 0x1180058002060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING13_CTL0" , 0x1180058002068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING14_CTL0" , 0x1180058002070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING15_CTL0" , 0x1180058002078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING16_CTL0" , 0x1180058002080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING17_CTL0" , 0x1180058002088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING18_CTL0" , 0x1180058002090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING19_CTL0" , 0x1180058002098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING20_CTL0" , 0x11800580020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING21_CTL0" , 0x11800580020a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING22_CTL0" , 0x11800580020b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING23_CTL0" , 0x11800580020b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING24_CTL0" , 0x11800580020c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING25_CTL0" , 0x11800580020c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING26_CTL0" , 0x11800580020d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING27_CTL0" , 0x11800580020d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING28_CTL0" , 0x11800580020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING29_CTL0" , 0x11800580020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING30_CTL0" , 0x11800580020f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING31_CTL0" , 0x11800580020f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING32_CTL0" , 0x1180058002100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING33_CTL0" , 0x1180058002108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING34_CTL0" , 0x1180058002110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING35_CTL0" , 0x1180058002118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING36_CTL0" , 0x1180058002120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING37_CTL0" , 0x1180058002128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING38_CTL0" , 0x1180058002130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING39_CTL0" , 0x1180058002138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING40_CTL0" , 0x1180058002140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING41_CTL0" , 0x1180058002148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING42_CTL0" , 0x1180058002150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING43_CTL0" , 0x1180058002158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING44_CTL0" , 0x1180058002160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING45_CTL0" , 0x1180058002168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING46_CTL0" , 0x1180058002170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING47_CTL0" , 0x1180058002178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING48_CTL0" , 0x1180058002180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING49_CTL0" , 0x1180058002188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING50_CTL0" , 0x1180058002190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING51_CTL0" , 0x1180058002198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING52_CTL0" , 0x11800580021a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING53_CTL0" , 0x11800580021a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING54_CTL0" , 0x11800580021b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING55_CTL0" , 0x11800580021b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING56_CTL0" , 0x11800580021c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING57_CTL0" , 0x11800580021c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING58_CTL0" , 0x11800580021d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING59_CTL0" , 0x11800580021d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING60_CTL0" , 0x11800580021e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING61_CTL0" , 0x11800580021e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING62_CTL0" , 0x11800580021f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING63_CTL0" , 0x11800580021f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1257},
- {"TIM_RING0_CTL1" , 0x1180058002400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING1_CTL1" , 0x1180058002408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING2_CTL1" , 0x1180058002410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING3_CTL1" , 0x1180058002418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING4_CTL1" , 0x1180058002420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING5_CTL1" , 0x1180058002428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING6_CTL1" , 0x1180058002430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING7_CTL1" , 0x1180058002438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING8_CTL1" , 0x1180058002440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING9_CTL1" , 0x1180058002448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING10_CTL1" , 0x1180058002450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING11_CTL1" , 0x1180058002458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING12_CTL1" , 0x1180058002460ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING13_CTL1" , 0x1180058002468ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING14_CTL1" , 0x1180058002470ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING15_CTL1" , 0x1180058002478ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING16_CTL1" , 0x1180058002480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING17_CTL1" , 0x1180058002488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING18_CTL1" , 0x1180058002490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING19_CTL1" , 0x1180058002498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING20_CTL1" , 0x11800580024a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING21_CTL1" , 0x11800580024a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING22_CTL1" , 0x11800580024b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING23_CTL1" , 0x11800580024b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING24_CTL1" , 0x11800580024c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING25_CTL1" , 0x11800580024c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING26_CTL1" , 0x11800580024d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING27_CTL1" , 0x11800580024d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING28_CTL1" , 0x11800580024e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING29_CTL1" , 0x11800580024e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING30_CTL1" , 0x11800580024f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING31_CTL1" , 0x11800580024f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING32_CTL1" , 0x1180058002500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING33_CTL1" , 0x1180058002508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING34_CTL1" , 0x1180058002510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING35_CTL1" , 0x1180058002518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING36_CTL1" , 0x1180058002520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING37_CTL1" , 0x1180058002528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING38_CTL1" , 0x1180058002530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING39_CTL1" , 0x1180058002538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING40_CTL1" , 0x1180058002540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING41_CTL1" , 0x1180058002548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING42_CTL1" , 0x1180058002550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING43_CTL1" , 0x1180058002558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING44_CTL1" , 0x1180058002560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING45_CTL1" , 0x1180058002568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING46_CTL1" , 0x1180058002570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING47_CTL1" , 0x1180058002578ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING48_CTL1" , 0x1180058002580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING49_CTL1" , 0x1180058002588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING50_CTL1" , 0x1180058002590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING51_CTL1" , 0x1180058002598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING52_CTL1" , 0x11800580025a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING53_CTL1" , 0x11800580025a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING54_CTL1" , 0x11800580025b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING55_CTL1" , 0x11800580025b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING56_CTL1" , 0x11800580025c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING57_CTL1" , 0x11800580025c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING58_CTL1" , 0x11800580025d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING59_CTL1" , 0x11800580025d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING60_CTL1" , 0x11800580025e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING61_CTL1" , 0x11800580025e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING62_CTL1" , 0x11800580025f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING63_CTL1" , 0x11800580025f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1258},
- {"TIM_RING0_CTL2" , 0x1180058002800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING1_CTL2" , 0x1180058002808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING2_CTL2" , 0x1180058002810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING3_CTL2" , 0x1180058002818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING4_CTL2" , 0x1180058002820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING5_CTL2" , 0x1180058002828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING6_CTL2" , 0x1180058002830ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING7_CTL2" , 0x1180058002838ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING8_CTL2" , 0x1180058002840ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING9_CTL2" , 0x1180058002848ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING10_CTL2" , 0x1180058002850ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING11_CTL2" , 0x1180058002858ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING12_CTL2" , 0x1180058002860ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING13_CTL2" , 0x1180058002868ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING14_CTL2" , 0x1180058002870ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING15_CTL2" , 0x1180058002878ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING16_CTL2" , 0x1180058002880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING17_CTL2" , 0x1180058002888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING18_CTL2" , 0x1180058002890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING19_CTL2" , 0x1180058002898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING20_CTL2" , 0x11800580028a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING21_CTL2" , 0x11800580028a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING22_CTL2" , 0x11800580028b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING23_CTL2" , 0x11800580028b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING24_CTL2" , 0x11800580028c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING25_CTL2" , 0x11800580028c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING26_CTL2" , 0x11800580028d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING27_CTL2" , 0x11800580028d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING28_CTL2" , 0x11800580028e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING29_CTL2" , 0x11800580028e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING30_CTL2" , 0x11800580028f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING31_CTL2" , 0x11800580028f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING32_CTL2" , 0x1180058002900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING33_CTL2" , 0x1180058002908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING34_CTL2" , 0x1180058002910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING35_CTL2" , 0x1180058002918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING36_CTL2" , 0x1180058002920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING37_CTL2" , 0x1180058002928ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING38_CTL2" , 0x1180058002930ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING39_CTL2" , 0x1180058002938ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING40_CTL2" , 0x1180058002940ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING41_CTL2" , 0x1180058002948ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING42_CTL2" , 0x1180058002950ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING43_CTL2" , 0x1180058002958ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING44_CTL2" , 0x1180058002960ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING45_CTL2" , 0x1180058002968ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING46_CTL2" , 0x1180058002970ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING47_CTL2" , 0x1180058002978ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING48_CTL2" , 0x1180058002980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING49_CTL2" , 0x1180058002988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING50_CTL2" , 0x1180058002990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING51_CTL2" , 0x1180058002998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING52_CTL2" , 0x11800580029a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING53_CTL2" , 0x11800580029a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING54_CTL2" , 0x11800580029b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING55_CTL2" , 0x11800580029b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING56_CTL2" , 0x11800580029c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING57_CTL2" , 0x11800580029c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING58_CTL2" , 0x11800580029d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING59_CTL2" , 0x11800580029d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING60_CTL2" , 0x11800580029e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING61_CTL2" , 0x11800580029e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING62_CTL2" , 0x11800580029f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING63_CTL2" , 0x11800580029f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1259},
- {"TIM_RING0_DBG0" , 0x1180058003000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING1_DBG0" , 0x1180058003008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING2_DBG0" , 0x1180058003010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING3_DBG0" , 0x1180058003018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING4_DBG0" , 0x1180058003020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING5_DBG0" , 0x1180058003028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING6_DBG0" , 0x1180058003030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING7_DBG0" , 0x1180058003038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING8_DBG0" , 0x1180058003040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING9_DBG0" , 0x1180058003048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING10_DBG0" , 0x1180058003050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING11_DBG0" , 0x1180058003058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING12_DBG0" , 0x1180058003060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING13_DBG0" , 0x1180058003068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING14_DBG0" , 0x1180058003070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING15_DBG0" , 0x1180058003078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING16_DBG0" , 0x1180058003080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING17_DBG0" , 0x1180058003088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING18_DBG0" , 0x1180058003090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING19_DBG0" , 0x1180058003098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING20_DBG0" , 0x11800580030a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING21_DBG0" , 0x11800580030a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING22_DBG0" , 0x11800580030b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING23_DBG0" , 0x11800580030b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING24_DBG0" , 0x11800580030c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING25_DBG0" , 0x11800580030c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING26_DBG0" , 0x11800580030d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING27_DBG0" , 0x11800580030d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING28_DBG0" , 0x11800580030e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING29_DBG0" , 0x11800580030e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING30_DBG0" , 0x11800580030f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING31_DBG0" , 0x11800580030f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING32_DBG0" , 0x1180058003100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING33_DBG0" , 0x1180058003108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING34_DBG0" , 0x1180058003110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING35_DBG0" , 0x1180058003118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING36_DBG0" , 0x1180058003120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING37_DBG0" , 0x1180058003128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING38_DBG0" , 0x1180058003130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING39_DBG0" , 0x1180058003138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING40_DBG0" , 0x1180058003140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING41_DBG0" , 0x1180058003148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING42_DBG0" , 0x1180058003150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING43_DBG0" , 0x1180058003158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING44_DBG0" , 0x1180058003160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING45_DBG0" , 0x1180058003168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING46_DBG0" , 0x1180058003170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING47_DBG0" , 0x1180058003178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING48_DBG0" , 0x1180058003180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING49_DBG0" , 0x1180058003188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING50_DBG0" , 0x1180058003190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING51_DBG0" , 0x1180058003198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING52_DBG0" , 0x11800580031a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING53_DBG0" , 0x11800580031a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING54_DBG0" , 0x11800580031b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING55_DBG0" , 0x11800580031b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING56_DBG0" , 0x11800580031c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING57_DBG0" , 0x11800580031c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING58_DBG0" , 0x11800580031d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING59_DBG0" , 0x11800580031d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING60_DBG0" , 0x11800580031e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING61_DBG0" , 0x11800580031e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING62_DBG0" , 0x11800580031f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING63_DBG0" , 0x11800580031f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1260},
- {"TIM_RING0_DBG1" , 0x1180058001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING1_DBG1" , 0x1180058001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING2_DBG1" , 0x1180058001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING3_DBG1" , 0x1180058001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING4_DBG1" , 0x1180058001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING5_DBG1" , 0x1180058001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING6_DBG1" , 0x1180058001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING7_DBG1" , 0x1180058001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING8_DBG1" , 0x1180058001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING9_DBG1" , 0x1180058001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING10_DBG1" , 0x1180058001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING11_DBG1" , 0x1180058001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING12_DBG1" , 0x1180058001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING13_DBG1" , 0x1180058001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING14_DBG1" , 0x1180058001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING15_DBG1" , 0x1180058001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING16_DBG1" , 0x1180058001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING17_DBG1" , 0x1180058001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING18_DBG1" , 0x1180058001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING19_DBG1" , 0x1180058001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING20_DBG1" , 0x11800580012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING21_DBG1" , 0x11800580012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING22_DBG1" , 0x11800580012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING23_DBG1" , 0x11800580012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING24_DBG1" , 0x11800580012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING25_DBG1" , 0x11800580012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING26_DBG1" , 0x11800580012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING27_DBG1" , 0x11800580012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING28_DBG1" , 0x11800580012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING29_DBG1" , 0x11800580012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING30_DBG1" , 0x11800580012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING31_DBG1" , 0x11800580012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING32_DBG1" , 0x1180058001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING33_DBG1" , 0x1180058001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING34_DBG1" , 0x1180058001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING35_DBG1" , 0x1180058001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING36_DBG1" , 0x1180058001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING37_DBG1" , 0x1180058001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING38_DBG1" , 0x1180058001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING39_DBG1" , 0x1180058001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING40_DBG1" , 0x1180058001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING41_DBG1" , 0x1180058001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING42_DBG1" , 0x1180058001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING43_DBG1" , 0x1180058001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING44_DBG1" , 0x1180058001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING45_DBG1" , 0x1180058001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING46_DBG1" , 0x1180058001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING47_DBG1" , 0x1180058001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING48_DBG1" , 0x1180058001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING49_DBG1" , 0x1180058001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING50_DBG1" , 0x1180058001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING51_DBG1" , 0x1180058001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING52_DBG1" , 0x11800580013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING53_DBG1" , 0x11800580013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING54_DBG1" , 0x11800580013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING55_DBG1" , 0x11800580013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING56_DBG1" , 0x11800580013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING57_DBG1" , 0x11800580013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING58_DBG1" , 0x11800580013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING59_DBG1" , 0x11800580013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING60_DBG1" , 0x11800580013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING61_DBG1" , 0x11800580013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING62_DBG1" , 0x11800580013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TIM_RING63_DBG1" , 0x11800580013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1261},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1262},
- {"TRA1_BIST_STATUS" , 0x11800a8100010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1262},
- {"TRA2_BIST_STATUS" , 0x11800a8200010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1262},
- {"TRA3_BIST_STATUS" , 0x11800a8300010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1262},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1263},
- {"TRA1_CTL" , 0x11800a8100000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1263},
- {"TRA2_CTL" , 0x11800a8200000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1263},
- {"TRA3_CTL" , 0x11800a8300000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1263},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1264},
- {"TRA1_CYCLES_SINCE" , 0x11800a8100018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1264},
- {"TRA2_CYCLES_SINCE" , 0x11800a8200018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1264},
- {"TRA3_CYCLES_SINCE" , 0x11800a8300018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1264},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1265},
- {"TRA1_CYCLES_SINCE1" , 0x11800a8100028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1265},
- {"TRA2_CYCLES_SINCE1" , 0x11800a8200028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1265},
- {"TRA3_CYCLES_SINCE1" , 0x11800a8300028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1265},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1266},
- {"TRA1_FILT_ADR_ADR" , 0x11800a8100058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1266},
- {"TRA2_FILT_ADR_ADR" , 0x11800a8200058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1266},
- {"TRA3_FILT_ADR_ADR" , 0x11800a8300058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1266},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1267},
- {"TRA1_FILT_ADR_MSK" , 0x11800a8100060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1267},
- {"TRA2_FILT_ADR_MSK" , 0x11800a8200060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1267},
- {"TRA3_FILT_ADR_MSK" , 0x11800a8300060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1267},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1268},
- {"TRA1_FILT_CMD" , 0x11800a8100040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1268},
- {"TRA2_FILT_CMD" , 0x11800a8200040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1268},
- {"TRA3_FILT_CMD" , 0x11800a8300040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1268},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1269},
- {"TRA1_FILT_DID" , 0x11800a8100050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1269},
- {"TRA2_FILT_DID" , 0x11800a8200050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1269},
- {"TRA3_FILT_DID" , 0x11800a8300050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1269},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1270},
- {"TRA1_FILT_SID" , 0x11800a8100048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1270},
- {"TRA2_FILT_SID" , 0x11800a8200048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1270},
- {"TRA3_FILT_SID" , 0x11800a8300048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1270},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1271},
- {"TRA1_INT_STATUS" , 0x11800a8100008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1271},
- {"TRA2_INT_STATUS" , 0x11800a8200008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1271},
- {"TRA3_INT_STATUS" , 0x11800a8300008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1271},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1272},
- {"TRA1_READ_DAT" , 0x11800a8100020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1272},
- {"TRA2_READ_DAT" , 0x11800a8200020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1272},
- {"TRA3_READ_DAT" , 0x11800a8300020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1272},
- {"TRA0_READ_DAT_HI" , 0x11800a8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1273},
- {"TRA1_READ_DAT_HI" , 0x11800a8100030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1273},
- {"TRA2_READ_DAT_HI" , 0x11800a8200030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1273},
- {"TRA3_READ_DAT_HI" , 0x11800a8300030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1273},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1274},
- {"TRA1_TRIG0_ADR_ADR" , 0x11800a8100098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1274},
- {"TRA2_TRIG0_ADR_ADR" , 0x11800a8200098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1274},
- {"TRA3_TRIG0_ADR_ADR" , 0x11800a8300098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1274},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1275},
- {"TRA1_TRIG0_ADR_MSK" , 0x11800a81000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1275},
- {"TRA2_TRIG0_ADR_MSK" , 0x11800a82000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1275},
- {"TRA3_TRIG0_ADR_MSK" , 0x11800a83000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1275},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1276},
- {"TRA1_TRIG0_CMD" , 0x11800a8100080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1276},
- {"TRA2_TRIG0_CMD" , 0x11800a8200080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1276},
- {"TRA3_TRIG0_CMD" , 0x11800a8300080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1276},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1277},
- {"TRA1_TRIG0_DID" , 0x11800a8100090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1277},
- {"TRA2_TRIG0_DID" , 0x11800a8200090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1277},
- {"TRA3_TRIG0_DID" , 0x11800a8300090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1277},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1278},
- {"TRA1_TRIG0_SID" , 0x11800a8100088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1278},
- {"TRA2_TRIG0_SID" , 0x11800a8200088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1278},
- {"TRA3_TRIG0_SID" , 0x11800a8300088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1278},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1279},
- {"TRA1_TRIG1_ADR_ADR" , 0x11800a81000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1279},
- {"TRA2_TRIG1_ADR_ADR" , 0x11800a82000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1279},
- {"TRA3_TRIG1_ADR_ADR" , 0x11800a83000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1279},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1280},
- {"TRA1_TRIG1_ADR_MSK" , 0x11800a81000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1280},
- {"TRA2_TRIG1_ADR_MSK" , 0x11800a82000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1280},
- {"TRA3_TRIG1_ADR_MSK" , 0x11800a83000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1280},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TRA1_TRIG1_CMD" , 0x11800a81000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TRA2_TRIG1_CMD" , 0x11800a82000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TRA3_TRIG1_CMD" , 0x11800a83000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TRA1_TRIG1_DID" , 0x11800a81000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TRA2_TRIG1_DID" , 0x11800a82000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TRA3_TRIG1_DID" , 0x11800a83000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TRA1_TRIG1_SID" , 0x11800a81000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TRA2_TRIG1_SID" , 0x11800a82000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TRA3_TRIG1_SID" , 0x11800a83000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"UAHC0_EHCI_ASYNCLISTADDR" , 0x16f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 1284},
- {"UAHC0_EHCI_CONFIGFLAG" , 0x16f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 1285},
- {"UAHC0_EHCI_CTRLDSSEGMENT" , 0x16f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 1286},
- {"UAHC0_EHCI_FRINDEX" , 0x16f000000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 1287},
- {"UAHC0_EHCI_HCCAPBASE" , 0x16f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 1288},
- {"UAHC0_EHCI_HCCPARAMS" , 0x16f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 1289},
- {"UAHC0_EHCI_HCSPARAMS" , 0x16f0000000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 1290},
- {"UAHC0_EHCI_INSNREG00" , 0x16f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 32, 1291},
- {"UAHC0_EHCI_INSNREG03" , 0x16f000000009cull, CVMX_CSR_DB_TYPE_NCB, 32, 1292},
- {"UAHC0_EHCI_INSNREG04" , 0x16f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 1293},
- {"UAHC0_EHCI_INSNREG06" , 0x16f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 1294},
- {"UAHC0_EHCI_INSNREG07" , 0x16f00000000ecull, CVMX_CSR_DB_TYPE_NCB, 32, 1295},
- {"UAHC0_EHCI_PERIODICLISTBASE" , 0x16f0000000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 1296},
- {"UAHC0_EHCI_PORTSC001" , 0x16f0000000054ull, CVMX_CSR_DB_TYPE_NCB, 32, 1297},
- {"UAHC0_EHCI_PORTSC002" , 0x16f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 32, 1297},
- {"UAHC0_EHCI_USBCMD" , 0x16f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 1298},
- {"UAHC0_EHCI_USBINTR" , 0x16f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 1299},
- {"UAHC0_EHCI_USBSTS" , 0x16f0000000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 1300},
- {"UAHC0_OHCI0_HCBULKCURRENTED" , 0x16f000000042cull, CVMX_CSR_DB_TYPE_NCB, 32, 1301},
- {"UAHC0_OHCI0_HCBULKHEADED" , 0x16f0000000428ull, CVMX_CSR_DB_TYPE_NCB, 32, 1302},
- {"UAHC0_OHCI0_HCCOMMANDSTATUS" , 0x16f0000000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 1303},
- {"UAHC0_OHCI0_HCCONTROL" , 0x16f0000000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 1304},
- {"UAHC0_OHCI0_HCCONTROLCURRENTED", 0x16f0000000424ull, CVMX_CSR_DB_TYPE_NCB, 32, 1305},
- {"UAHC0_OHCI0_HCCONTROLHEADED" , 0x16f0000000420ull, CVMX_CSR_DB_TYPE_NCB, 32, 1306},
- {"UAHC0_OHCI0_HCDONEHEAD" , 0x16f0000000430ull, CVMX_CSR_DB_TYPE_NCB, 32, 1307},
- {"UAHC0_OHCI0_HCFMINTERVAL" , 0x16f0000000434ull, CVMX_CSR_DB_TYPE_NCB, 32, 1308},
- {"UAHC0_OHCI0_HCFMNUMBER" , 0x16f000000043cull, CVMX_CSR_DB_TYPE_NCB, 32, 1309},
- {"UAHC0_OHCI0_HCFMREMAINING" , 0x16f0000000438ull, CVMX_CSR_DB_TYPE_NCB, 32, 1310},
- {"UAHC0_OHCI0_HCHCCA" , 0x16f0000000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 1311},
- {"UAHC0_OHCI0_HCINTERRUPTDISABLE", 0x16f0000000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 1312},
- {"UAHC0_OHCI0_HCINTERRUPTENABLE", 0x16f0000000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 1313},
- {"UAHC0_OHCI0_HCINTERRUPTSTATUS", 0x16f000000040cull, CVMX_CSR_DB_TYPE_NCB, 32, 1314},
- {"UAHC0_OHCI0_HCLSTHRESHOLD" , 0x16f0000000444ull, CVMX_CSR_DB_TYPE_NCB, 32, 1315},
- {"UAHC0_OHCI0_HCPERIODCURRENTED", 0x16f000000041cull, CVMX_CSR_DB_TYPE_NCB, 32, 1316},
- {"UAHC0_OHCI0_HCPERIODICSTART" , 0x16f0000000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 1317},
- {"UAHC0_OHCI0_HCREVISION" , 0x16f0000000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 1318},
- {"UAHC0_OHCI0_HCRHDESCRIPTORA" , 0x16f0000000448ull, CVMX_CSR_DB_TYPE_NCB, 32, 1319},
- {"UAHC0_OHCI0_HCRHDESCRIPTORB" , 0x16f000000044cull, CVMX_CSR_DB_TYPE_NCB, 32, 1320},
- {"UAHC0_OHCI0_HCRHPORTSTATUS001", 0x16f0000000454ull, CVMX_CSR_DB_TYPE_NCB, 32, 1321},
- {"UAHC0_OHCI0_HCRHPORTSTATUS002", 0x16f0000000458ull, CVMX_CSR_DB_TYPE_NCB, 32, 1321},
- {"UAHC0_OHCI0_HCRHSTATUS" , 0x16f0000000450ull, CVMX_CSR_DB_TYPE_NCB, 32, 1322},
- {"UAHC0_OHCI0_INSNREG06" , 0x16f0000000498ull, CVMX_CSR_DB_TYPE_NCB, 32, 1323},
- {"UAHC0_OHCI0_INSNREG07" , 0x16f000000049cull, CVMX_CSR_DB_TYPE_NCB, 32, 1324},
- {"UCTL0_BIST_STATUS" , 0x118006f0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1325},
- {"UCTL0_CLK_RST_CTL" , 0x118006f000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1326},
- {"UCTL0_EHCI_CTL" , 0x118006f000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1327},
- {"UCTL0_EHCI_FLA" , 0x118006f0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1328},
- {"UCTL0_ERTO_CTL" , 0x118006f000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1329},
- {"UCTL0_IF_ENA" , 0x118006f000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1330},
- {"UCTL0_INT_ENA" , 0x118006f000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1331},
- {"UCTL0_INT_REG" , 0x118006f000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1332},
- {"UCTL0_OHCI_CTL" , 0x118006f000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1333},
- {"UCTL0_ORTO_CTL" , 0x118006f000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1334},
- {"UCTL0_UPHY_CTL_STATUS" , 0x118006f000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1335},
- {"UCTL0_UPHY_PORT000_CTL_STATUS", 0x118006f000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1336},
- {"UCTL0_UPHY_PORT001_CTL_STATUS", 0x118006f000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1336},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1337},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1338},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1339},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1340},
- {"ZIP_CORE0_BIST_STATUS" , 0x1180038000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1341},
- {"ZIP_CORE1_BIST_STATUS" , 0x1180038000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1341},
- {"ZIP_CTL_BIST_STATUS" , 0x1180038000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1342},
- {"ZIP_CTL_CFG" , 0x1180038000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1343},
- {"ZIP_DBG_CORE0_INST" , 0x1180038000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1344},
- {"ZIP_DBG_CORE1_INST" , 0x1180038000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1344},
- {"ZIP_DBG_CORE0_STA" , 0x1180038000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1345},
- {"ZIP_DBG_CORE1_STA" , 0x1180038000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1345},
- {"ZIP_DBG_QUE0_STA" , 0x1180038000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1346},
- {"ZIP_DBG_QUE1_STA" , 0x1180038000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1346},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1347},
- {"ZIP_ECC_CTL" , 0x1180038000568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1348},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1349},
- {"ZIP_INT_ENA" , 0x1180038000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1350},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1351},
- {"ZIP_INT_REG" , 0x1180038000570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1352},
- {"ZIP_QUE0_BUF" , 0x1180038000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1353},
- {"ZIP_QUE1_BUF" , 0x1180038000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1353},
- {"ZIP_QUE0_ECC_ERR_STA" , 0x1180038000590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1354},
- {"ZIP_QUE1_ECC_ERR_STA" , 0x1180038000598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1354},
- {"ZIP_QUE0_MAP" , 0x1180038000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1355},
- {"ZIP_QUE1_MAP" , 0x1180038000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1355},
- {"ZIP_QUE_ENA" , 0x1180038000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1356},
- {"ZIP_QUE_PRI" , 0x1180038000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1357},
- {"ZIP_THROTTLE" , 0x1180038000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1358},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn68xxp1[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_21" , 4, 18, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_24_25" , 24, 2, 0, "RAZ", 1, 1, 0, 0},
- {"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRFLW1" , 35, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP1" , 36, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH1" , 37, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 0, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"RX_EN" , 4, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"TX_EN" , 5, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"BURST" , 6, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 2, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 2, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 2, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 2, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 3, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 4, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 9, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 10, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 10, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 10, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 10, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 11, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 12, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 13, "RO", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 7, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"NULL_DIS" , 10, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 13, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 13, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 14, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 14, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 15, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 15, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 16, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 16, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 17, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 18, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 19, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 19, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 20, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 20, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 21, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 21, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 21, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 22, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 22, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 23, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 23, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 27, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 27, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 32, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 32, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 33, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 33, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 34, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 35, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 35, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 36, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 36, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 37, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 37, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 38, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 38, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 39, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 39, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 40, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 41, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 60, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 2, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 61, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 64, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 64, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 64, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 64, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 64, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 64, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 65, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 65, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 65, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 65, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 65, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 65, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 68, "RAZ", 1, 1, 0, 0},
- {"BP" , 4, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 68, "RAZ", 1, 1, 0, 0},
- {"EN" , 8, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 68, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 1, 71, "R/W", 0, 0, 0ull, 0ull},
- {"CLKRST" , 1, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"ENABLE" , 2, 1, 71, "R/W", 0, 0, 1ull, 1ull},
- {"COMP" , 3, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"DLLRST" , 4, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_SET" , 8, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_14" , 13, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_BYP" , 15, 1, 71, "R/W", 0, 1, 1ull, 0},
- {"CLKRX_SET" , 16, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_22" , 21, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKRX_BYP" , 23, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"CLK_SET" , 24, 5, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_NCTL" , 32, 6, 71, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_38_39" , 38, 2, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_PCTL" , 40, 6, 71, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_46_47" , 46, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_NCTL" , 48, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_54_55" , 54, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_PCTL" , 56, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_BYP" , 63, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"ACK" , 0, 1, 72, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 72, "RAZ", 1, 1, 0, 0},
- {"ACK" , 0, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 73, "RAZ", 1, 1, 0, 0},
- {"ACK" , 0, 1, 74, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 74, "RAZ", 1, 1, 0, 0},
- {"ACK" , 0, 1, 75, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 75, "RAZ", 1, 1, 0, 0},
- {"GPIO" , 0, 16, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 76, "RAZ", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 77, "RAZ", 1, 0, 0, 0ull},
- {"GPIO" , 0, 16, 78, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 78, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 79, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 79, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 79, "R/W", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 79, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 79, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 79, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 79, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 79, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 79, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 80, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 80, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 80, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 80, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 81, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 81, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 81, "R/W1", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 81, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 81, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 81, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 81, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 81, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 81, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 82, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 82, "RAZ", 0, 0, 0ull, 0ull},
- {"MBOX" , 0, 4, 83, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 83, "RAZ", 1, 0, 0, 0ull},
- {"MBOX" , 0, 4, 84, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 84, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 85, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 85, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 86, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 86, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 87, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 87, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 88, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 88, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 88, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 88, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 88, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 88, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 88, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 88, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 89, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 89, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 89, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 89, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 89, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 89, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 89, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 89, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 90, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 90, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 90, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 90, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 90, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 90, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 90, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 90, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 91, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 91, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 91, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 91, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 91, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 92, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 92, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 92, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 92, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 92, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 93, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 93, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 93, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 93, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 93, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 94, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 94, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 94, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 94, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 94, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 94, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 94, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 94, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 94, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 95, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 95, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 95, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 95, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 95, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 95, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 95, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 95, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 95, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 96, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 96, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 96, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 96, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 96, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 96, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 96, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 96, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 96, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 97, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 98, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 99, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 99, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 100, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 102, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 103, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 103, "RAZ", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 104, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 104, "RAZ", 1, 0, 0, 0ull},
- {"GPIO" , 0, 16, 105, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 105, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 106, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 106, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 106, "R/W", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 106, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 106, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 106, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 106, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 106, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 106, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 107, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 107, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 107, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 107, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 107, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 107, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 107, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 107, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 107, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 108, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 108, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 108, "R/W1", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 108, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 108, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 108, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 108, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 108, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 108, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 109, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 109, "RAZ", 0, 0, 0ull, 0ull},
- {"MBOX" , 0, 4, 110, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 110, "RAZ", 1, 0, 0, 0ull},
- {"MBOX" , 0, 4, 111, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 111, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 112, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 113, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 114, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 114, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 115, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 115, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 115, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 115, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 115, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 115, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 115, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 115, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 116, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 116, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 116, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 116, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 116, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 116, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 116, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 116, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 117, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 117, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 117, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 117, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 117, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 117, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 117, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 117, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 118, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 118, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 118, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 118, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 118, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 119, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 119, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 119, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 119, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 119, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 120, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 120, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 120, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 120, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 120, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 121, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 121, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 121, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 121, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 121, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 121, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 121, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 121, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 121, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 122, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 122, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 122, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 122, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 122, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 122, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 122, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 122, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 122, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 123, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 123, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 123, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 123, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 123, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 123, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 123, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 123, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 123, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 124, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 124, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 125, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 125, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 126, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 126, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 127, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 129, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 130, "RAZ", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 131, "RAZ", 1, 0, 0, 0ull},
- {"GPIO" , 0, 16, 132, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 132, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 133, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 133, "R/W", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 133, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 133, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 133, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 134, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 134, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 134, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 134, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 135, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 135, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 135, "R/W1", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 135, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 135, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 135, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 135, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 135, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 135, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 136, "RAZ", 0, 0, 0ull, 0ull},
- {"MBOX" , 0, 4, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 137, "RAZ", 1, 0, 0, 0ull},
- {"MBOX" , 0, 4, 138, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 138, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 139, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 139, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 140, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 140, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 141, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 141, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 142, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 142, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 142, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 142, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 142, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 142, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 142, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 142, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 143, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 143, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 143, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 143, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 143, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 143, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 143, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 143, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 144, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 144, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 144, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 144, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 144, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 144, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 144, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 144, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 145, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 145, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 145, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 145, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 145, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 146, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 146, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 146, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 146, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 146, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 147, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 147, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 147, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 147, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 147, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 148, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 148, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 148, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 148, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 148, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 148, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 148, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 148, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 148, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 149, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 149, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 149, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 149, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 149, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 149, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 149, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 149, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 149, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 150, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 150, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 150, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 150, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 150, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 150, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 150, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 150, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 150, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 151, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 152, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 152, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 153, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 153, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 154, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 155, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 156, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 157, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 157, "RAZ", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 158, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 158, "RAZ", 1, 0, 0, 0ull},
- {"GPIO" , 0, 16, 159, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 159, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 160, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 160, "R/W", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 160, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 160, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 160, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 161, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 161, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 161, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 161, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 162, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 162, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 162, "R/W1", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 162, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 162, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 162, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 162, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 162, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 162, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 163, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 163, "RAZ", 0, 0, 0ull, 0ull},
- {"MBOX" , 0, 4, 164, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 164, "RAZ", 1, 0, 0, 0ull},
- {"MBOX" , 0, 4, 165, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 165, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 166, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 166, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 167, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 167, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 168, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 168, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 169, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 169, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 169, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 169, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 169, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 169, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 169, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 169, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 170, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 170, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 170, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 170, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 170, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 170, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 170, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 170, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 171, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 171, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 171, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 171, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 171, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 171, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 171, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 171, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 172, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 172, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 172, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 172, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 172, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 173, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 173, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 173, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 173, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 173, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 174, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 174, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 174, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 174, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 174, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 175, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 175, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 175, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 175, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 175, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 175, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 175, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 175, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 175, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 176, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 176, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 176, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 176, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 176, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 176, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 176, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 176, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 176, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 177, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 177, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 177, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 177, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 177, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 177, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 177, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 177, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 177, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 178, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 178, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 179, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 179, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 180, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 180, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 181, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 183, "R/W1", 0, 0, 0ull, 0ull},
- {"READY" , 0, 1, 184, "RO", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 184, "RAZ", 1, 1, 0, 0},
- {"ECC_ENA" , 0, 1, 185, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND" , 1, 2, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 185, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 186, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 186, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 186, "RAZ", 1, 1, 0, 0},
- {"SYNDROM" , 4, 9, 186, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 186, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 16, 7, 186, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 186, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 3, 187, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_3_63" , 3, 61, 187, "RAZ", 1, 1, 0, 0},
- {"MSI_RCV" , 0, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 188, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 189, "RAZ", 1, 1, 0, 0},
- {"IP_NUM" , 4, 2, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 189, "RAZ", 1, 1, 0, 0},
- {"PP_NUM" , 8, 5, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 189, "RAZ", 1, 1, 0, 0},
- {"MSI_NUM" , 0, 8, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 190, "RAZ", 1, 1, 0, 0},
- {"NEWINT" , 16, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 190, "RAZ", 1, 1, 0, 0},
- {"INTR" , 20, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 190, "RAZ", 1, 1, 0, 0},
- {"MSI_NUM" , 0, 8, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 191, "RAZ", 1, 1, 0, 0},
- {"NEWINT" , 16, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 191, "RAZ", 1, 1, 0, 0},
- {"INTR" , 20, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 191, "RAZ", 1, 1, 0, 0},
- {"MSI_NUM" , 0, 8, 192, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 192, "RAZ", 1, 1, 0, 0},
- {"NEWINT" , 16, 1, 192, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 192, "RAZ", 1, 1, 0, 0},
- {"INTR" , 20, 1, 192, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 192, "RAZ", 1, 1, 0, 0},
- {"GPIO" , 0, 16, 193, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 193, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 194, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 194, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 194, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 194, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 194, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 195, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 195, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 196, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 196, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 196, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 196, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 196, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 196, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 196, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 196, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 197, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 197, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 197, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 197, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 197, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 198, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 198, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 198, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 198, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 198, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 198, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 198, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 198, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 198, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 199, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 199, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 200, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 201, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 201, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 202, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 202, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 202, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 202, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 202, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 202, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 202, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 202, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 202, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 203, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 204, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 204, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 204, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 204, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 204, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 204, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 204, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 204, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 205, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 205, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 205, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 205, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 205, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 206, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 206, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 206, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 206, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 206, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 206, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 206, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 206, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 206, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 207, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 207, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 208, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 209, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 209, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 210, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 210, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 210, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 210, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 210, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 211, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 211, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 212, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 212, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 212, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 212, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 212, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 212, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 212, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 212, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 212, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 212, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 212, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 213, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 213, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 213, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 213, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 213, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 213, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 214, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 214, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 214, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 214, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 214, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 214, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 214, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 214, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 214, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 215, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 215, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 216, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 217, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 218, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 218, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 218, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 218, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 218, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 219, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 219, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 220, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 220, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 220, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 220, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 220, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 220, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 220, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 220, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 220, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 220, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 220, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 221, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 221, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 221, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 221, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 221, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 221, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 222, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 222, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 222, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 222, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 222, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 222, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 222, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 222, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 222, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 223, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 223, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 224, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 225, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 226, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 226, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 226, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 226, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 226, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 227, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 227, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 228, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 228, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 229, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 229, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 229, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 229, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 229, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 229, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 229, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 229, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 230, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 230, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 230, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 230, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 230, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 231, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 231, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 231, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 231, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 231, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 231, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 231, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 231, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 231, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 232, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 232, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 233, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 234, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 234, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 235, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 235, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 235, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 235, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 235, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 236, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 236, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 237, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 237, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 238, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 238, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 238, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 238, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 238, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 238, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 238, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 238, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 239, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 239, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 239, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 239, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 239, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 240, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 240, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 240, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 240, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 240, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 240, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 240, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 240, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 240, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 241, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 241, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 242, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 243, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 243, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 244, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 244, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 244, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 244, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 244, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 245, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 245, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 246, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 246, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 247, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 247, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 247, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 247, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 247, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 247, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 247, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 247, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 248, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 248, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 248, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 248, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 248, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 249, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 249, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 249, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 249, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 249, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 249, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 249, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 249, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 249, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 250, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 250, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 251, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 252, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 252, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 253, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 253, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 253, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 253, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 253, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 254, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 254, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 255, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 255, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 256, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 256, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 256, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 256, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 256, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 256, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 256, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 256, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 257, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 257, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 257, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 257, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 257, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 258, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 258, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 258, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 258, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 258, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_39" , 34, 6, 258, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 258, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 258, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 258, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 259, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 259, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 260, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 1, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 2, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 3, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"IO" , 4, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"MEM" , 5, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"PKT" , 6, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 7, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_59" , 8, 52, 261, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 60, 4, 261, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 1, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 2, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 3, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"IO" , 4, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"MEM" , 5, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"PKT" , 6, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 7, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_59" , 8, 52, 262, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 60, 4, 262, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 1, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 2, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 3, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"IO" , 4, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"MEM" , 5, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"PKT" , 6, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 7, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_59" , 8, 52, 263, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 60, 4, 263, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 1, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 2, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 3, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"IO" , 4, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"MEM" , 5, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"PKT" , 6, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 7, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_59" , 8, 52, 264, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 60, 4, 264, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 7, 265, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 265, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 32, 266, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 266, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 32, 267, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 267, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 268, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 5, 269, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 269, "RAZ", 1, 1, 0, 0},
- {"IRQ" , 8, 2, 269, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 269, "RAZ", 1, 1, 0, 0},
- {"SEL" , 16, 3, 269, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_19_63" , 19, 45, 269, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 270, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 271, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 271, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 32, 272, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 272, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 273, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 273, "RAZ", 1, 1, 0, 0},
- {"PP_BIST" , 0, 32, 274, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 274, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 32, 275, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 276, "R/W", 1, 1, 0, 0},
- {"RST0" , 0, 1, 277, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 31, 277, "R/W", 0, 0, 2147483647ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 277, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 278, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 278, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 278, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 278, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 278, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 278, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 278, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 278, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 279, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 279, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 279, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 279, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 279, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 279, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 279, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 279, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 280, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 280, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 280, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 280, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 280, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 280, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 280, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 280, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 281, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 281, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 281, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 281, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 281, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 281, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 281, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 281, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 282, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 282, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 282, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 282, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 282, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 282, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 282, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 282, "R/W", 0, 1, 0ull, 0},
- {"BYPASS" , 0, 4, 283, "R/W", 0, 1, 0ull, 0},
- {"MUX_SEL" , 4, 3, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 283, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_15" , 11, 5, 283, "RAZ", 1, 1, 0, 0},
- {"BYPASS_EXT" , 16, 1, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 283, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 284, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 284, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_39" , 37, 3, 284, "RAZ", 1, 1, 0, 0},
- {"SELECT" , 40, 5, 284, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_60" , 45, 16, 284, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 284, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 284, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 284, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 285, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 285, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 286, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 286, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 287, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 287, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 288, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 288, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 289, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 289, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 289, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 290, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 290, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 290, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 290, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 290, "RAZ", 1, 1, 0, 0},
- {"PDB" , 0, 3, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"RDF" , 4, 3, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"DTX" , 8, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"DTX1" , 10, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"DTX2" , 12, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"STX" , 16, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"STX1" , 18, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"STX2" , 20, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"GFB" , 24, 3, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"MRP" , 28, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"GFU" , 0, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"GIB" , 1, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"GIF" , 2, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"NCD" , 3, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"GUTP" , 4, 3, 292, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"GUTV" , 8, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 9, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"RAM1" , 10, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"RAM2" , 11, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"RAM3" , 12, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC1RAM1" , 13, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC1RAM2" , 14, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC1RAM3" , 15, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC2RAM1" , 16, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC2RAM2" , 17, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC2RAM3" , 18, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DLC0RAM" , 19, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DLC1RAM" , 20, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"DTECLKDIS" , 0, 1, 293, "R/W", 0, 0, 1ull, 0ull},
- {"CLDTECRIP" , 1, 3, 293, "R/W", 0, 0, 0ull, 0ull},
- {"CLMSKCRIP" , 4, 4, 293, "R/W", 0, 0, 0ull, 0ull},
- {"REPL_ENA" , 8, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"DLCSTART_BIST" , 9, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"DLCCLEAR_BIST" , 10, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 293, "RAZ", 1, 1, 0, 0},
- {"IMODE" , 0, 1, 294, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 1, 1, 294, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 2, 1, 294, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_4" , 3, 2, 294, "RAZ", 1, 1, 0, 0},
- {"SBDLCK" , 5, 1, 294, "R/W", 0, 0, 0ull, 0ull},
- {"SBDNUM" , 6, 6, 294, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 294, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 20, 295, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 295, "RAZ", 1, 1, 0, 0},
- {"SBD0" , 0, 64, 296, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 297, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 298, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 299, "RO", 1, 1, 0, 0},
- {"SIZE" , 0, 9, 300, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 300, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 300, "R/W", 0, 1, 1ull, 0},
- {"MSEGBASE" , 20, 6, 300, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 300, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 301, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 35, 301, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 301, "RAZ", 1, 1, 0, 0},
- {"RAM1FADR" , 0, 14, 302, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 302, "RAZ", 1, 1, 0, 0},
- {"RAM2FADR" , 16, 9, 302, "RO", 1, 1, 0, 0},
- {"RESERVED_25_31" , 25, 7, 302, "RAZ", 1, 1, 0, 0},
- {"RAM3FADR" , 32, 12, 302, "RO", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 302, "RAZ", 1, 1, 0, 0},
- {"DBLOVF" , 0, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC0PERR" , 1, 3, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC1PERR" , 4, 3, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC2PERR" , 7, 3, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_12" , 10, 3, 303, "RAZ", 1, 1, 0, 0},
- {"DLC0_OVFERR" , 13, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"DLC1_OVFERR" , 14, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 303, "RAZ", 1, 1, 0, 0},
- {"CNDRD" , 16, 1, 303, "RO", 0, 0, 0ull, 0ull},
- {"DFANXM" , 17, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"REPLERR" , 18, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 303, "RAZ", 1, 1, 0, 0},
- {"DBLINA" , 0, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"DC0PENA" , 1, 3, 304, "R/W", 0, 0, 0ull, 0ull},
- {"DC1PENA" , 4, 3, 304, "R/W", 0, 0, 0ull, 0ull},
- {"DC2PENA" , 7, 3, 304, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_12" , 10, 3, 304, "RAZ", 1, 1, 0, 0},
- {"DLC0_OVFENA" , 13, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"DLC1_OVFENA" , 14, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_16" , 15, 2, 304, "RAZ", 1, 1, 0, 0},
- {"DFANXMENA" , 17, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"REPLERRENA" , 18, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 304, "RAZ", 1, 1, 0, 0},
- {"HIDAT" , 0, 64, 305, "R/W", 1, 1, 0, 0},
- {"PFCNT0" , 0, 64, 306, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 307, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 307, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 307, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 307, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 307, "RAZ", 1, 1, 0, 0},
- {"PFCNT1" , 0, 64, 308, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 309, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 309, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 309, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 309, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 309, "RAZ", 1, 1, 0, 0},
- {"PFCNT2" , 0, 64, 310, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 311, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 311, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 311, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 311, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 311, "RAZ", 1, 1, 0, 0},
- {"PFCNT3" , 0, 64, 312, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 313, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 313, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 313, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 313, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 313, "RAZ", 1, 1, 0, 0},
- {"CNT0ENA" , 0, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 1, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 2, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 3, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0WCLR" , 4, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1WCLR" , 5, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2WCLR" , 6, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3WCLR" , 7, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RCLR" , 8, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RCLR" , 9, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RCLR" , 10, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RCLR" , 11, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"SNODE" , 12, 3, 314, "R/W", 0, 0, 0ull, 0ull},
- {"ENODE" , 15, 3, 314, "R/W", 0, 0, 0ull, 0ull},
- {"EDNODE" , 18, 2, 314, "R/W", 0, 0, 0ull, 0ull},
- {"PMODE" , 20, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"VGID" , 21, 8, 314, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 314, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 45, 315, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_63" , 45, 19, 315, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 316, "R/W", 0, 0, 0ull, 1ull},
- {"CLK" , 1, 1, 316, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 316, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 317, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 317, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 317, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 318, "WO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 318, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 319, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 319, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 320, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 33, 320, "R/W", 0, 1, 0ull, 0},
- {"IDLE" , 40, 1, 320, "RO", 0, 1, 1ull, 0},
- {"RESERVED_41_47" , 41, 7, 320, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 48, 14, 320, "R/W", 0, 1, 64ull, 0},
- {"RESERVED_62_63" , 62, 2, 320, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 3, 321, "R/W", 0, 0, 6ull, 6ull},
- {"RESERVED_3_63" , 3, 61, 321, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 40, 322, "RO", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 322, "RAZ", 1, 1, 0, 0},
- {"STATE" , 0, 64, 323, "RO", 0, 1, 0ull, 0},
- {"STATE" , 0, 64, 324, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_13" , 0, 14, 325, "RAZ", 1, 1, 0, 0},
- {"O_MODE" , 14, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 325, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 325, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 325, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 325, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_47" , 34, 14, 325, "RAZ", 1, 1, 0, 0},
- {"DMA_ENB" , 48, 6, 325, "R/W", 0, 0, 0ull, 63ull},
- {"RESERVED_54_55" , 54, 2, 325, "RAZ", 1, 1, 0, 0},
- {"PKT_EN" , 56, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"PKT_HP" , 57, 1, 325, "RO", 0, 0, 0ull, 0ull},
- {"COMMIT_MODE" , 58, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"FFP_DIS" , 59, 1, 325, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_EN1" , 60, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_61_63" , 61, 3, 325, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 326, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 326, "RAZ", 1, 1, 0, 0},
- {"BLKS" , 0, 4, 327, "R/W", 0, 1, 2ull, 0},
- {"BASE" , 4, 5, 327, "RO", 1, 1, 0, 0},
- {"RESERVED_9_31" , 9, 23, 327, "RAZ", 1, 1, 0, 0},
- {"COMPBLKS" , 32, 5, 327, "RO", 1, 1, 0, 0},
- {"RESERVED_37_63" , 37, 27, 327, "RAZ", 1, 1, 0, 0},
- {"RSL" , 0, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB" , 1, 1, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 328, "RAZ", 1, 1, 0, 0},
- {"FFP" , 4, 4, 328, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 328, "RAZ", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 329, "R/W", 0, 0, 0ull, 0ull},
- {"DMADBO" , 8, 8, 329, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 329, "R/W", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 329, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 329, "R/W", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 330, "RAZ", 1, 1, 0, 0},
- {"DMADBO" , 8, 8, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 330, "RAZ", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 330, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 330, "RAZ", 1, 1, 0, 0},
- {"SINFO" , 0, 6, 331, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 331, "RAZ", 1, 1, 0, 0},
- {"IINFO" , 8, 6, 331, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 331, "RAZ", 1, 1, 0, 0},
- {"PKTERR" , 0, 1, 332, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 332, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 333, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 333, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 334, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 334, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 335, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 335, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 336, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 336, "RAZ", 1, 1, 0, 0},
- {"EN_RSP" , 0, 8, 337, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 337, "RAZ", 1, 1, 0, 0},
- {"EN_RST" , 16, 8, 337, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 337, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 338, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 338, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 2, 339, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 339, "RAZ", 1, 1, 0, 0},
- {"MRRS_LIM" , 3, 1, 339, "R/W", 0, 0, 0ull, 0ull},
- {"MPS" , 4, 1, 339, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 339, "RAZ", 1, 1, 0, 0},
- {"MPS_LIM" , 7, 1, 339, "R/W", 0, 0, 0ull, 0ull},
- {"MOLR" , 8, 6, 339, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_14_15" , 14, 2, 339, "RAZ", 1, 1, 0, 0},
- {"RD_MODE" , 16, 1, 339, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 339, "RAZ", 1, 1, 0, 0},
- {"QLM_CFG" , 20, 1, 339, "RO", 1, 1, 0, 0},
- {"RESERVED_21_23" , 21, 3, 339, "RAZ", 1, 1, 0, 0},
- {"HALT" , 24, 1, 339, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 339, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 340, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 340, "RO", 0, 1, 0ull, 0},
- {"REQQ" , 0, 3, 341, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 341, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 4, 1, 341, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 341, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 8, 1, 341, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 341, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 342, "RO", 0, 1, 0ull, 0},
- {"POOL" , 33, 5, 342, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 342, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 343, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 343, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 344, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 344, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 344, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 344, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 344, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 344, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OFF" , 18, 1, 344, "R/W", 0, 0, 0ull, 0ull},
- {"RET_OFF" , 19, 1, 344, "R/W", 0, 0, 0ull, 0ull},
- {"FREE_EN" , 20, 1, 344, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 344, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 345, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 345, "R/W", 0, 0, 164ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 345, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 346, "R/W", 0, 0, 224ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 346, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 347, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 347, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 347, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 348, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 348, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 349, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 349, "R/W", 0, 0, 164ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 349, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 350, "R/W", 0, 0, 224ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 350, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"FREE8" , 44, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q8_UND" , 45, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q8_COFF" , 46, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"Q8_PERR" , 47, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"POOL8TH" , 48, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"PADDR_E" , 49, 1, 351, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_63" , 50, 14, 351, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE8" , 44, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q8_UND" , 45, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q8_COFF" , 46, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q8_PERR" , 47, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL8TH" , 48, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"PADDR_E" , 49, 1, 352, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_50_63" , 50, 14, 352, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 32, 353, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 353, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 354, "R/W", 0, 1, 8589934591ull, 0},
- {"RESERVED_33_63" , 33, 31, 354, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 355, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 355, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 32, 356, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 356, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 32, 357, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 357, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 358, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 358, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 359, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 359, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 360, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 360, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 360, "RO", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 361, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 361, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 361, "RO", 0, 0, 0ull, 7ull},
- {"THRESH" , 0, 32, 362, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 362, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 363, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 363, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 363, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 363, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 364, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 364, "RAZ", 1, 1, 0, 0},
- {"BPID" , 0, 6, 365, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 365, "RAZ", 1, 1, 0, 0},
- {"VAL" , 8, 1, 365, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 365, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 16, 1, 365, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 365, "RAZ", 1, 1, 0, 0},
- {"MSK_AND" , 0, 16, 366, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 366, "RAZ", 1, 1, 0, 0},
- {"MSK_OR" , 32, 16, 366, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 366, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 367, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 367, "RAZ", 1, 1, 0, 0},
- {"DIS" , 0, 16, 368, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 368, "RAZ", 1, 1, 0, 0},
- {"MSK" , 0, 16, 369, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 369, "RAZ", 1, 1, 0, 0},
- {"LOGL_EN" , 0, 16, 370, "R/W", 0, 1, 65535ull, 0},
- {"PHYS_EN" , 16, 1, 370, "R/W", 0, 1, 1ull, 0},
- {"HG2RX_EN" , 17, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"HG2TX_EN" , 18, 1, 370, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 370, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 371, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 371, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 371, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 3, 371, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 371, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 4, 371, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 371, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 372, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_15" , 6, 10, 372, "RAZ", 1, 1, 0, 0},
- {"PIPE" , 16, 7, 372, "RO", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 372, "RAZ", 1, 1, 0, 0},
- {"STOP" , 0, 4, 373, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 373, "RAZ", 1, 1, 0, 0},
- {"BP" , 8, 4, 373, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 373, "RAZ", 1, 1, 0, 0},
- {"OVR" , 16, 4, 373, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 373, "RAZ", 1, 1, 0, 0},
- {"RX_EN" , 0, 1, 374, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EN" , 1, 1, 374, "R/W", 0, 0, 0ull, 0ull},
- {"DRP_EN" , 2, 1, 374, "R/W", 0, 0, 0ull, 0ull},
- {"BCK_EN" , 3, 1, 374, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 374, "RAZ", 1, 1, 0, 0},
- {"PHYS_BP" , 16, 16, 374, "R/W", 0, 1, 65535ull, 0},
- {"LOGL_EN" , 32, 16, 374, "R/W", 0, 0, 255ull, 255ull},
- {"PHYS_EN" , 48, 16, 374, "R/W", 0, 0, 255ull, 255ull},
- {"EN" , 0, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 375, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 375, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 375, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 375, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 375, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 375, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 375, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 375, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_15" , 14, 2, 375, "RAZ", 1, 1, 0, 0},
- {"PKND" , 16, 6, 375, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 375, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 376, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 377, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 378, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 379, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 380, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 381, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 382, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 382, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 383, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 383, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 383, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 383, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 384, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 384, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 385, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 385, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 385, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 385, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 385, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 385, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 385, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 385, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 385, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 386, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 386, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 386, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 386, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 386, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 386, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 386, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 386, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 386, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 386, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 386, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 386, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 386, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 387, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 387, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 388, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 388, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 388, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 388, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 388, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 388, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 389, "R/W1C", 0, 1, 0ull, 0},
- {"CAREXT" , 1, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 389, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 389, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 389, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 389, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 389, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 390, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 390, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 391, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 391, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 392, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 392, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 393, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 393, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 394, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 394, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 395, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 395, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 396, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 396, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 397, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 397, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 398, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 398, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 399, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 399, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 400, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 400, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 401, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 401, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 402, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 402, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 402, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 403, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 403, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 404, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 404, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 11, 405, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_11_63" , 11, 53, 405, "RAZ", 1, 1, 0, 0},
- {"LGTIM2GO" , 0, 16, 406, "RO", 0, 1, 0ull, 0},
- {"XOF" , 16, 16, 406, "RO", 0, 0, 0ull, 0ull},
- {"PHTIM2GO" , 32, 16, 406, "RO", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 406, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 4, 407, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 407, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 4, 407, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 407, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 408, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 408, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 409, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 409, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 409, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 409, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 409, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 410, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 410, "RAZ", 1, 1, 0, 0},
- {"DISPARITY" , 0, 1, 411, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 411, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 412, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 412, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 0, 1, 413, "R/W", 0, 1, 0ull, 0},
- {"START_BIST" , 1, 1, 413, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 413, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 414, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 414, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 414, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 415, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 415, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 415, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 415, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 415, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 416, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 416, "RAZ", 1, 1, 0, 0},
- {"XOFF" , 0, 16, 417, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 417, "RAZ", 1, 1, 0, 0},
- {"XON" , 0, 16, 418, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 418, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 419, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 419, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 419, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 420, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 420, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 421, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 421, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 422, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 422, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 423, "RO", 1, 1, 0, 0},
- {"MSG_TIME" , 16, 16, 423, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 423, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 424, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 424, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 7, 425, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 425, "RAZ", 1, 1, 0, 0},
- {"NUMP" , 16, 5, 425, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_31" , 21, 11, 425, "RAZ", 1, 1, 0, 0},
- {"IGN_BP" , 32, 1, 425, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 425, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 426, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 426, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 427, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 427, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 428, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 428, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 429, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 429, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 430, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 430, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 431, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 431, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 432, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 432, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 433, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 433, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 434, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 434, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 435, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 435, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 436, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 436, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 437, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 437, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 438, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 438, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 439, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 439, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 10, 440, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_10_63" , 10, 54, 440, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 441, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 441, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 442, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 442, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 443, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 443, "RAZ", 1, 1, 0, 0},
- {"TX_XOF" , 0, 16, 444, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 444, "RAZ", 1, 1, 0, 0},
- {"TX_XON" , 0, 16, 445, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 445, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 446, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 446, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 446, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"PKO_NXP" , 1, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 447, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 447, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 447, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 447, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 447, "R/W", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 447, "R/W", 0, 0, 0ull, 0ull},
- {"XCHANGE" , 24, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 447, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 448, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO_NXP" , 1, 1, 448, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 448, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 448, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 448, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 448, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 448, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 448, "R/W1C", 0, 0, 0ull, 0ull},
- {"XCHANGE" , 24, 1, 448, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 448, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 449, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 449, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 450, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 450, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 451, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 451, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 451, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 451, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 452, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 452, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 453, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 453, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 454, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_5_63" , 5, 59, 454, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 455, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 455, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 455, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 455, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 455, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 455, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 455, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 456, "R/W", 0, 0, 6ull, 6ull},
- {"EN" , 4, 1, 456, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 456, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 457, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 457, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 457, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 457, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 457, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 457, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 457, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 457, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCE_SEL" , 15, 2, 457, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 457, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 458, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 458, "RAZ", 1, 1, 0, 0},
- {"LANE_SEL" , 0, 2, 459, "R/W", 0, 0, 0ull, 0ull},
- {"DIV" , 2, 1, 459, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 459, "RAZ", 1, 1, 0, 0},
- {"QLM_SEL" , 8, 3, 459, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 459, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 460, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 460, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 461, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 461, "RAZ", 1, 1, 0, 0},
- {"SEL" , 0, 4, 462, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 462, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 463, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 463, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 464, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 464, "RAZ", 1, 1, 0, 0},
- {"TLK0_TXF0" , 0, 1, 465, "RO", 0, 1, 0ull, 0},
- {"TLK0_TXF1" , 1, 1, 465, "RO", 0, 1, 0ull, 0},
- {"TLK0_TXF2" , 2, 1, 465, "RO", 0, 1, 0ull, 0},
- {"TLK0_STAT" , 3, 1, 465, "RO", 0, 1, 0ull, 0},
- {"TLK0_FWC" , 4, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 465, "RAZ", 0, 1, 0ull, 0},
- {"TLK1_TXF0" , 6, 1, 465, "RO", 0, 1, 0ull, 0},
- {"TLK1_TXF1" , 7, 1, 465, "RO", 0, 1, 0ull, 0},
- {"TLK1_TXF2" , 8, 1, 465, "RO", 0, 1, 0ull, 0},
- {"TLK1_STAT" , 9, 1, 465, "RO", 0, 1, 0ull, 0},
- {"TLK1_FWC" , 10, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 465, "RAZ", 0, 1, 0ull, 0},
- {"RLK0_STAT" , 12, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLK0_FWC" , 13, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 465, "RAZ", 0, 1, 0ull, 0},
- {"RLK1_STAT" , 16, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLK1_FWC" , 17, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_19" , 18, 2, 465, "RAZ", 0, 1, 0ull, 0},
- {"RLE0_DSK0" , 20, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE0_DSK1" , 21, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE1_DSK0" , 22, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE1_DSK1" , 23, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE2_DSK0" , 24, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE2_DSK1" , 25, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE3_DSK0" , 26, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE3_DSK1" , 27, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE4_DSK0" , 28, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE4_DSK1" , 29, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE5_DSK0" , 30, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE5_DSK1" , 31, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE6_DSK0" , 32, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE6_DSK1" , 33, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE7_DSK0" , 34, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RLE7_DSK1" , 35, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_51" , 36, 16, 465, "RAZ", 0, 1, 0ull, 0},
- {"RXF_MEM0" , 52, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RXF_MEM1" , 53, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RXF_MEM2" , 54, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RXF_PMAP" , 55, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RXF_X2P0" , 56, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RXF_X2P1" , 57, 1, 465, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 465, "RAZ", 0, 1, 0ull, 0},
- {"RXF_XLINK" , 0, 1, 466, "R/W", 0, 1, 0ull, 0},
- {"CCLK_DIS" , 1, 1, 466, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 466, "RAZ", 0, 1, 0ull, 0},
- {"RXF_LNK0_PERR" , 0, 1, 467, "R/W1C", 0, 1, 0ull, 0},
- {"RXF_LNK1_PERR" , 1, 1, 467, "R/W1C", 0, 1, 0ull, 0},
- {"RXF_CTL_PERR" , 2, 1, 467, "R/W1C", 0, 1, 0ull, 0},
- {"RXF_POP_EMPTY" , 3, 1, 467, "R/W1C", 0, 1, 0ull, 0},
- {"RXF_PUSH_FULL" , 4, 1, 467, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 467, "RAZ", 0, 1, 0ull, 0},
- {"RXF_LNK0_PERR" , 0, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"RXF_LNK1_PERR" , 1, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"RXF_CTL_PERR" , 2, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"RXF_POP_EMPTY" , 3, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"RXF_PUSH_FULL" , 4, 1, 468, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 468, "RAZ", 0, 1, 0ull, 0},
- {"GBL_INT" , 0, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK0_INT" , 1, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK1_INT" , 2, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLK0_INT" , 3, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLK1_INT" , 4, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE0_INT" , 5, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE1_INT" , 6, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE2_INT" , 7, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE3_INT" , 8, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE4_INT" , 9, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE5_INT" , 10, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE6_INT" , 11, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE7_INT" , 12, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RESERVED_13_63" , 13, 51, 469, "RAZ", 0, 1, 0ull, 0},
- {"TX_DIS_SCRAM" , 0, 8, 470, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 470, "RAZ", 0, 1, 0ull, 0},
- {"TX_DIS_DISPR" , 16, 8, 470, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_31" , 24, 8, 470, "RAZ", 0, 1, 0ull, 0},
- {"TX_BAD_LANE_SEL" , 32, 8, 470, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_47" , 40, 8, 470, "RAZ", 0, 1, 0ull, 0},
- {"TX_BAD_SCRAM_CNT" , 48, 3, 470, "R/W", 0, 1, 0ull, 0},
- {"TX_BAD_SYNC_CNT" , 51, 3, 470, "R/W", 0, 1, 0ull, 0},
- {"TX_BAD_6467_CNT" , 54, 5, 470, "R/W", 0, 1, 0ull, 0},
- {"TX_BAD_CRC32" , 59, 1, 470, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 470, "RAZ", 0, 1, 0ull, 0},
- {"TX_LNE_STAT" , 0, 8, 471, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_8_15" , 8, 8, 471, "RAZ", 0, 1, 0ull, 0},
- {"TX_LNK_STAT" , 16, 8, 471, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_24_31" , 24, 8, 471, "RAZ", 0, 1, 0ull, 0},
- {"RX_LNE_STAT" , 32, 8, 471, "RO", 0, 1, 0ull, 0},
- {"RESERVED_40_47" , 40, 8, 471, "RAZ", 0, 1, 0ull, 0},
- {"RX_LNK_STAT" , 48, 8, 471, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 471, "RAZ", 0, 1, 0ull, 0},
- {"LANE_ENA" , 0, 8, 472, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 472, "RAZ", 0, 1, 0ull, 0},
- {"CAL_DEPTH" , 16, 9, 472, "R/W", 0, 1, 144ull, 0},
- {"RESERVED_25_25" , 25, 1, 472, "RAZ", 0, 1, 0ull, 0},
- {"BRST_MAX" , 26, 5, 472, "R/W", 0, 1, 4ull, 0},
- {"LANE_REV" , 31, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"BRST_SHRT" , 32, 7, 472, "R/W", 0, 1, 4ull, 0},
- {"MFRM_LEN" , 39, 13, 472, "R/W", 0, 1, 1024ull, 0},
- {"CAL_ENA" , 52, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"MLTUSE_FC_ENA" , 53, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"LNK_STATS_ENA" , 54, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"LNK_STATS_RDCLR" , 55, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"PTRN_MODE" , 56, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_57_61" , 57, 5, 472, "RAZ", 0, 1, 0ull, 0},
- {"EXT_LPBK" , 62, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"EXT_LPBK_FC" , 63, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"RX_BDRY_LOCK_ENA" , 0, 8, 473, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 473, "RAZ", 0, 1, 0ull, 0},
- {"RX_ALIGN_ENA" , 16, 1, 473, "R/W", 0, 1, 0ull, 0},
- {"RX_LINK_FC" , 17, 1, 473, "RO", 0, 1, 0ull, 0},
- {"TX_LINK_FC" , 18, 1, 473, "RO", 0, 1, 0ull, 0},
- {"LA_MODE" , 19, 1, 473, "R/W", 0, 1, 0ull, 0},
- {"PKT_ENA" , 20, 1, 473, "R/W", 0, 1, 0ull, 0},
- {"PKT_FLUSH" , 21, 1, 473, "WR0", 0, 1, 0ull, 0},
- {"RX_FIFO_MAX" , 22, 12, 473, "R/W", 0, 1, 1024ull, 0},
- {"RESERVED_34_35" , 34, 2, 473, "RAZ", 0, 1, 0ull, 0},
- {"RX_FIFO_HWM" , 36, 12, 473, "R/W", 0, 1, 512ull, 0},
- {"RESERVED_48_49" , 48, 2, 473, "RAZ", 0, 1, 0ull, 0},
- {"RX_FIFO_CNT" , 50, 12, 473, "RO", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 473, "RAZ", 0, 1, 0ull, 0},
- {"STATUS" , 0, 64, 474, "RO", 0, 1, 0ull, 0},
- {"STATUS" , 0, 64, 475, "RO", 0, 1, 0ull, 0},
- {"INDEX" , 0, 6, 476, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 476, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 8, 6, 476, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 476, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 8, 477, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 477, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 8, 477, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_30" , 24, 7, 477, "RAZ", 0, 1, 0ull, 0},
- {"CLR" , 31, 1, 477, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 477, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 8, 478, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 478, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 8, 478, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_30" , 24, 7, 478, "RAZ", 0, 1, 0ull, 0},
- {"CLR" , 31, 1, 478, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 478, "RAZ", 0, 1, 0ull, 0},
- {"LANE_ALIGN_FAIL" , 0, 1, 479, "R/W1C", 0, 1, 0ull, 0},
- {"CRC24_ERR" , 1, 1, 479, "R/W1C", 0, 1, 0ull, 0},
- {"WORD_SYNC_DONE" , 2, 1, 479, "R/W1C", 0, 1, 0ull, 0},
- {"LANE_ALIGN_DONE" , 3, 1, 479, "R/W1C", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 4, 1, 479, "R/W1C", 0, 1, 0ull, 0},
- {"LANE_BAD_WORD" , 5, 1, 479, "R/W1C", 0, 1, 0ull, 0},
- {"PKT_DROP_RXF" , 6, 1, 479, "R/W1C", 0, 1, 0ull, 0},
- {"PKT_DROP_RID" , 7, 1, 479, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 479, "RAZ", 0, 1, 0ull, 0},
- {"LANE_ALIGN_FAIL" , 0, 1, 480, "R/W", 0, 1, 0ull, 0},
- {"CRC24_ERR" , 1, 1, 480, "R/W", 0, 1, 0ull, 0},
- {"WORD_SYNC_DONE" , 2, 1, 480, "R/W", 0, 1, 0ull, 0},
- {"LANE_ALIGN_DONE" , 3, 1, 480, "R/W", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 4, 1, 480, "R/W", 0, 1, 0ull, 0},
- {"LANE_BAD_WORD" , 5, 1, 480, "R/W", 0, 1, 0ull, 0},
- {"PKT_DROP_RXF" , 6, 1, 480, "R/W", 0, 1, 0ull, 0},
- {"PKT_DROP_RID" , 7, 1, 480, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 480, "RAZ", 0, 1, 0ull, 0},
- {"CNT" , 0, 16, 481, "R/W", 0, 1, 10240ull, 0},
- {"RESERVED_16_63" , 16, 48, 481, "RAZ", 0, 1, 0ull, 0},
- {"PORT_PIPE0" , 0, 7, 482, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL0" , 7, 2, 482, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE1" , 9, 7, 482, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL1" , 16, 2, 482, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE2" , 18, 7, 482, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL2" , 25, 2, 482, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE3" , 27, 7, 482, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL3" , 34, 2, 482, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 482, "RAZ", 0, 1, 0ull, 0},
- {"PORT_PIPE4" , 0, 7, 483, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL4" , 7, 2, 483, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE5" , 9, 7, 483, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL5" , 16, 2, 483, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE6" , 18, 7, 483, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL6" , 25, 2, 483, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE7" , 27, 7, 483, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL7" , 34, 2, 483, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 483, "RAZ", 0, 1, 0ull, 0},
- {"RX_PKT" , 0, 28, 484, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 484, "RAZ", 0, 1, 0ull, 0},
- {"RX_BYTES" , 0, 36, 485, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 485, "RAZ", 0, 1, 0ull, 0},
- {"CRC24_MATCH_CNT" , 0, 27, 486, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_27_63" , 27, 37, 486, "RAZ", 0, 1, 0ull, 0},
- {"CRC24_ERR_CNT" , 0, 18, 487, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 487, "RAZ", 0, 1, 0ull, 0},
- {"BRST_CNT" , 0, 16, 488, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 488, "RAZ", 0, 1, 0ull, 0},
- {"BRST_NOT_FULL_CNT" , 32, 16, 488, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 488, "RAZ", 0, 1, 0ull, 0},
- {"BRST_MAX_ERR_CNT" , 0, 16, 489, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 489, "RAZ", 0, 1, 0ull, 0},
- {"BRST_SHRT_ERR_CNT" , 0, 16, 490, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 490, "RAZ", 0, 1, 0ull, 0},
- {"ALIGN_CNT" , 0, 16, 491, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 491, "RAZ", 0, 1, 0ull, 0},
- {"ALIGN_ERR_CNT" , 0, 16, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 492, "RAZ", 0, 1, 0ull, 0},
- {"BAD_64B67B_CNT" , 0, 16, 493, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 493, "RAZ", 0, 1, 0ull, 0},
- {"PKT_DROP_RXF_CNT" , 0, 16, 494, "R/W", 0, 1, 0ull, 0},
- {"PKT_DROP_RID_CNT" , 16, 16, 494, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 494, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_0_63" , 0, 64, 495, "RAZ", 0, 1, 0ull, 0},
- {"STAT_ENA" , 0, 1, 496, "R/W", 0, 1, 0ull, 0},
- {"STAT_RDCLR" , 1, 1, 496, "R/W", 0, 1, 0ull, 0},
- {"RX_DIS_SCRAM" , 2, 1, 496, "R/W", 0, 0, 0ull, 0ull},
- {"RX_DIS_UKWN" , 3, 1, 496, "R/W", 0, 0, 0ull, 0ull},
- {"RX_BDRY_SYNC" , 4, 1, 496, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 496, "RAZ", 0, 1, 0ull, 0},
- {"SERDES_LOCK_LOSS" , 0, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"BDRY_SYNC_LOSS" , 1, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"CRC32_ERR" , 2, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"UKWN_CNTL_WORD" , 3, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"SCRM_SYNC_LOSS" , 4, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"DSKEW_FIFO_OVFL" , 5, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"STAT_MSG" , 6, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 7, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"BAD_64B67B" , 8, 1, 497, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 497, "RAZ", 0, 1, 0ull, 0},
- {"SERDES_LOCK_LOSS" , 0, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"BDRY_SYNC_LOSS" , 1, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"CRC32_ERR" , 2, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"UKWN_CNTL_WORD" , 3, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"SCRM_SYNC_LOSS" , 4, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"DSKEW_FIFO_OVFL" , 5, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"STAT_MSG" , 6, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 7, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"BAD_64B67B" , 8, 1, 498, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 498, "RAZ", 0, 1, 0ull, 0},
- {"SER_LOCK_LOSS_CNT" , 0, 18, 499, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 499, "RAZ", 0, 1, 0ull, 0},
- {"BDRY_SYNC_LOSS_CNT" , 0, 18, 500, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 500, "RAZ", 0, 1, 0ull, 0},
- {"SYNCW_BAD_CNT" , 0, 18, 501, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 501, "RAZ", 0, 1, 0ull, 0},
- {"SYNCW_GOOD_CNT" , 32, 18, 501, "RO", 0, 1, 0ull, 0},
- {"RESERVED_50_63" , 50, 14, 501, "RAZ", 0, 1, 0ull, 0},
- {"BAD_64B67B_CNT" , 0, 18, 502, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 502, "RAZ", 0, 1, 0ull, 0},
- {"DATA_WORD_CNT" , 0, 27, 503, "RO", 0, 1, 0ull, 0},
- {"RESERVED_27_31" , 27, 5, 503, "RAZ", 0, 1, 0ull, 0},
- {"CNTL_WORD_CNT" , 32, 27, 503, "RO", 0, 1, 0ull, 0},
- {"RESERVED_59_63" , 59, 5, 503, "RAZ", 0, 1, 0ull, 0},
- {"UNKWN_WORD_CNT" , 0, 18, 504, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 504, "RAZ", 0, 1, 0ull, 0},
- {"SCRM_SYNC_LOSS_CNT" , 0, 18, 505, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 505, "RAZ", 0, 1, 0ull, 0},
- {"SCRM_MATCH_CNT" , 0, 18, 506, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 506, "RAZ", 0, 1, 0ull, 0},
- {"SKIPW_GOOD_CNT" , 0, 18, 507, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 507, "RAZ", 0, 1, 0ull, 0},
- {"CRC32_MATCH_CNT" , 0, 27, 508, "RO", 0, 1, 0ull, 0},
- {"RESERVED_27_31" , 27, 5, 508, "RAZ", 0, 1, 0ull, 0},
- {"CRC32_ERR_CNT" , 32, 18, 508, "RO", 0, 1, 0ull, 0},
- {"RESERVED_50_63" , 50, 14, 508, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 9, 509, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_15" , 9, 7, 509, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 9, 509, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 509, "RAZ", 0, 1, 0ull, 0},
- {"PORT_KIND" , 0, 6, 510, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 510, "RAZ", 0, 1, 0ull, 0},
- {"SER_HAUL" , 0, 2, 511, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 511, "RAZ", 0, 1, 0ull, 0},
- {"SER_PWRUP" , 4, 2, 511, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 511, "RAZ", 0, 1, 0ull, 0},
- {"SER_RESET_N" , 8, 8, 511, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_23" , 16, 8, 511, "RAZ", 0, 1, 0ull, 0},
- {"SER_TXPOL" , 24, 8, 511, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 511, "RAZ", 0, 1, 0ull, 0},
- {"SER_RXPOL" , 40, 8, 511, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_55" , 48, 8, 511, "RAZ", 0, 1, 0ull, 0},
- {"SER_RXPOL_AUTO" , 56, 1, 511, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_57_63" , 57, 7, 511, "RAZ", 0, 1, 0ull, 0},
- {"LANE_ENA" , 0, 8, 512, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 512, "RAZ", 0, 1, 0ull, 0},
- {"CAL_DEPTH" , 16, 9, 512, "R/W", 0, 1, 72ull, 0},
- {"RESERVED_25_25" , 25, 1, 512, "RAZ", 0, 1, 0ull, 0},
- {"BRST_MAX" , 26, 5, 512, "R/W", 0, 1, 4ull, 0},
- {"LANE_REV" , 31, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"BRST_SHRT" , 32, 7, 512, "R/W", 0, 1, 4ull, 0},
- {"MFRM_LEN" , 39, 13, 512, "R/W", 0, 1, 1024ull, 0},
- {"CAL_ENA" , 52, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"MLTUSE_FC_ENA" , 53, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"LNK_STATS_ENA" , 54, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_55_55" , 55, 1, 512, "RAZ", 0, 1, 0ull, 0},
- {"PTRN_MODE" , 56, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_57_60" , 57, 4, 512, "RAZ", 0, 1, 0ull, 0},
- {"INT_LPBK" , 61, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"EXT_LPBK" , 62, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"EXT_LPBK_FC" , 63, 1, 512, "R/W", 0, 1, 0ull, 0},
- {"TX_MLTUSE" , 0, 8, 513, "R/W", 0, 1, 0ull, 0},
- {"RMATCH" , 8, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"RX_LINK_FC_IGN" , 9, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"RX_LINK_FC_PKT" , 10, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"TX_LINK_FC_JAM" , 11, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_16" , 12, 5, 513, "RAZ", 0, 1, 0ull, 0},
- {"RX_LINK_FC" , 17, 1, 513, "RO", 0, 1, 0ull, 0},
- {"TX_LINK_FC" , 18, 1, 513, "RO", 0, 1, 0ull, 0},
- {"LA_MODE" , 19, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"PKT_ENA" , 20, 1, 513, "R/W", 0, 1, 1ull, 0},
- {"PKT_FLUSH" , 21, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"SKIP_CNT" , 22, 4, 513, "R/W", 0, 1, 1ull, 0},
- {"PTP_DELAY" , 26, 5, 513, "R/W", 0, 1, 26ull, 0},
- {"PIPE_CRD_DIS" , 31, 1, 513, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 513, "RAZ", 0, 1, 0ull, 0},
- {"TX_BAD_CTLW1" , 0, 1, 514, "R/W", 0, 1, 0ull, 0},
- {"TX_BAD_CTLW2" , 1, 1, 514, "R/W", 0, 1, 0ull, 0},
- {"TX_BAD_CRC24" , 2, 1, 514, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 514, "RAZ", 0, 1, 0ull, 0},
- {"STATUS" , 0, 64, 515, "RO", 0, 1, 18446744073709551615ull, 0},
- {"RESERVED_0_63" , 0, 64, 516, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 6, 517, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 517, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 8, 6, 517, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 517, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 7, 518, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 518, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 7, 518, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 518, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 8, 519, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 519, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 8, 519, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_30" , 24, 7, 519, "RAZ", 0, 1, 0ull, 0},
- {"CLR" , 31, 1, 519, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 519, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 8, 520, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 520, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 8, 520, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_30" , 24, 7, 520, "RAZ", 0, 1, 0ull, 0},
- {"CLR" , 31, 1, 520, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 520, "RAZ", 0, 1, 0ull, 0},
- {"TXF_ERR" , 0, 1, 521, "R/W1C", 0, 1, 0ull, 0},
- {"BAD_SEQ" , 1, 1, 521, "R/W1C", 0, 1, 0ull, 0},
- {"BAD_PIPE" , 2, 1, 521, "R/W1C", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 3, 1, 521, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 521, "RAZ", 0, 1, 0ull, 0},
- {"TXF_ERR" , 0, 1, 522, "R/W", 0, 1, 0ull, 0},
- {"BAD_SEQ" , 1, 1, 522, "R/W", 0, 1, 0ull, 0},
- {"BAD_PIPE" , 2, 1, 522, "R/W", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 3, 1, 522, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 522, "RAZ", 0, 1, 0ull, 0},
- {"BPID0" , 0, 6, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_6" , 6, 1, 523, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL0" , 7, 2, 523, "R/W", 0, 1, 0ull, 0},
- {"BPID1" , 9, 6, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 523, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL1" , 16, 2, 523, "R/W", 0, 1, 0ull, 0},
- {"BPID2" , 18, 6, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_24" , 24, 1, 523, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL2" , 25, 2, 523, "R/W", 0, 1, 0ull, 0},
- {"BPID3" , 27, 6, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_33" , 33, 1, 523, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL3" , 34, 2, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 523, "RAZ", 0, 1, 0ull, 0},
- {"BPID4" , 0, 6, 524, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_6" , 6, 1, 524, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL4" , 7, 2, 524, "R/W", 0, 1, 0ull, 0},
- {"BPID5" , 9, 6, 524, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 524, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL5" , 16, 2, 524, "R/W", 0, 1, 0ull, 0},
- {"BPID6" , 18, 6, 524, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_24" , 24, 1, 524, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL6" , 25, 2, 524, "R/W", 0, 1, 0ull, 0},
- {"BPID7" , 27, 6, 524, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_33" , 33, 1, 524, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL7" , 34, 2, 524, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 524, "RAZ", 0, 1, 0ull, 0},
- {"CHANNEL" , 0, 8, 525, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 525, "RAZ", 0, 1, 0ull, 0},
- {"TX_PKT" , 0, 28, 526, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 526, "RAZ", 0, 1, 0ull, 0},
- {"TX_BYTES" , 0, 36, 527, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 527, "RAZ", 0, 1, 0ull, 0},
- {"BASE" , 0, 7, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 528, "RAZ", 0, 1, 0ull, 0},
- {"NUMP" , 16, 8, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 528, "RAZ", 0, 1, 0ull, 0},
- {"RATE_LIMIT" , 0, 16, 529, "R/W", 0, 1, 1024ull, 0},
- {"TIME_LIMIT" , 16, 16, 529, "R/W", 0, 1, 256ull, 0},
- {"BRST_LIMIT" , 32, 16, 529, "R/W", 0, 1, 1024ull, 0},
- {"GRNLRTY" , 48, 2, 529, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_50_63" , 50, 14, 529, "RAZ", 0, 1, 0ull, 0},
- {"ICRP1" , 0, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 1, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 530, "RAZ", 1, 1, 0, 0},
- {"IOCFIF" , 4, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RSDFIF" , 5, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"IORFIF" , 6, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"XMCFIF" , 7, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"XMDFIF" , 8, 1, 530, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 530, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_5" , 0, 6, 531, "RAZ", 0, 0, 0ull, 0ull},
- {"XMC_PER" , 6, 4, 531, "R/W", 0, 0, 0ull, 0ull},
- {"FIF_DLY" , 10, 1, 531, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 531, "RAZ", 1, 1, 0, 0},
- {"NCB_WR" , 0, 3, 532, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_5" , 3, 3, 532, "R/W", 0, 0, 0ull, 0ull},
- {"PKO_RD" , 6, 4, 532, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 532, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 2, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 3, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 4, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 5, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 6, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 7, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 8, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 9, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 10, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 11, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 12, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"IOCFIF" , 13, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"RSDFIF" , 14, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"IORFIF" , 15, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"XMCFIF" , 16, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"XMDFIF" , 17, 1, 533, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 533, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 534, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 534, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 534, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVR5" , 5, 1, 534, "R/W", 0, 0, 0ull, 0ull},
- {"XMC_PER" , 6, 4, 534, "R/W", 0, 0, 0ull, 0ull},
- {"FIF_DLY" , 10, 1, 534, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 534, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 535, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 535, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 535, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 536, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 536, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 536, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 536, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 536, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 537, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 537, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 537, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 537, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 537, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 538, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 539, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_63" , 0, 64, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_63" , 0, 64, 541, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 542, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 542, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 542, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 543, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 543, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 543, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 543, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 544, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 544, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 544, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 544, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 544, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 545, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 546, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 547, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 547, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 547, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 548, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 548, "RAZ", 1, 1, 0, 0},
- {"NCB_WR" , 0, 3, 549, "R/W", 0, 1, 0ull, 0},
- {"NCB_RD" , 3, 3, 549, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 6, 3, 549, "R/W", 0, 1, 2ull, 0},
- {"RESERVED_9_63" , 9, 55, 549, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 550, "R/W", 0, 1, 14ull, 0},
- {"RESERVED_7_63" , 7, 57, 550, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 551, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_7_63" , 7, 57, 551, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 552, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_7_63" , 7, 57, 552, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 553, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_7_63" , 7, 57, 553, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 554, "R/W", 0, 1, 12ull, 0},
- {"RESERVED_7_63" , 7, 57, 554, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 555, "R/W", 0, 1, 40ull, 0},
- {"RESERVED_7_63" , 7, 57, 555, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 556, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_7_63" , 7, 57, 556, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 557, "R/W", 0, 1, 8ull, 0},
- {"RESERVED_7_63" , 7, 57, 557, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 558, "R/W", 0, 1, 8ull, 0},
- {"RESERVED_7_63" , 7, 57, 558, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 559, "R/W", 0, 1, 24ull, 0},
- {"RESERVED_7_63" , 7, 57, 559, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 560, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_7_63" , 7, 57, 560, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 561, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 561, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 562, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 562, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 563, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 563, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"PBM4" , 18, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"IIO0" , 19, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"IIO1" , 20, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"IIWO0" , 21, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"IIWO1" , 22, 1, 564, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 564, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 565, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 565, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 565, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 566, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 566, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 567, "RO", 0, 0, 0ull, 0ull},
- {"IOB_WR" , 0, 8, 568, "R/W", 0, 0, 8ull, 8ull},
- {"IOB_WRC" , 8, 8, 568, "RO", 0, 1, 8ull, 0},
- {"RESERVED_16_63" , 16, 48, 568, "RAZ", 1, 1, 0, 0},
- {"IPD_EN" , 0, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 569, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 569, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"CLKEN" , 15, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"RST_DONE" , 16, 1, 569, "RO", 0, 0, 1ull, 0ull},
- {"USE_SOP" , 17, 1, 569, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 569, "RAZ", 1, 1, 0, 0},
- {"PM0_SYN" , 0, 2, 570, "R/W", 0, 0, 0ull, 0ull},
- {"PM1_SYN" , 2, 2, 570, "R/W", 0, 0, 0ull, 0ull},
- {"PM2_SYN" , 4, 2, 570, "R/W", 0, 0, 0ull, 0ull},
- {"PM3_SYN" , 6, 2, 570, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 570, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 571, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 571, "R/W", 0, 0, 1ull, 1ull},
- {"PRADDR" , 9, 8, 571, "RO", 1, 1, 0, 0},
- {"WRADDR" , 17, 8, 571, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 25, 7, 571, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_32_63" , 32, 32, 571, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 572, "RO", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 572, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 3, 573, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 573, "R/W", 0, 0, 1ull, 1ull},
- {"PRADDR" , 4, 3, 573, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 7, 3, 573, "RO", 0, 0, 5ull, 5ull},
- {"PTR" , 10, 33, 573, "RO", 1, 1, 0, 0},
- {"RESERVED_43_63" , 43, 21, 573, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"SOP" , 12, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"EOP" , 13, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"DAT" , 14, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PW0_SBE" , 15, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PW0_DBE" , 16, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PW1_SBE" , 17, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PW1_DBE" , 18, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PW2_SBE" , 19, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PW2_DBE" , 20, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PW3_SBE" , 21, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PW3_DBE" , 22, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 574, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"SOP" , 12, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"EOP" , 13, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"DAT" , 14, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW0_SBE" , 15, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW0_DBE" , 16, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW1_SBE" , 17, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW1_DBE" , 18, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW2_SBE" , 19, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW2_DBE" , 20, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW3_SBE" , 21, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW3_DBE" , 22, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 575, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 576, "RO", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 576, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 577, "RO", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 577, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 578, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 578, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 64, 579, "R/W", 0, 0, 0ull, 0ull},
- {"MB_SIZE" , 0, 12, 580, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 580, "RAZ", 1, 1, 0, 0},
- {"REASM" , 0, 6, 581, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 581, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 582, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 582, "R/W", 0, 0, 1ull, 1ull},
- {"MAX_PKT" , 8, 7, 582, "RO", 0, 0, 64ull, 64ull},
- {"PTR" , 15, 33, 582, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 582, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 583, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 583, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 584, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 585, "R/W", 0, 0, 0ull, 1ull},
- {"SOP" , 0, 64, 586, "RO", 0, 1, 0ull, 0},
- {"WQE_PCNT" , 0, 7, 587, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 587, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 587, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 587, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 587, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 587, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 588, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 588, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 589, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 589, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 64, 590, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 0, 14, 591, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 14, 14, 591, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 591, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 592, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 592, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 592, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 592, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 592, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 593, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 593, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 593, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 594, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 594, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 594, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 595, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 595, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 596, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 596, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 596, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 596, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 597, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 597, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 598, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 598, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 599, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 599, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 599, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 599, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 599, "RAZ", 1, 1, 0, 0},
- {"DISABLE" , 0, 1, 600, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 600, "RAZ", 1, 1, 0, 0},
- {"MAXDRAM" , 4, 4, 600, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_8_63" , 8, 56, 600, "RAZ", 1, 1, 0, 0},
- {"TDFFL" , 0, 4, 601, "RO", 1, 0, 0, 0ull},
- {"VRTFL" , 4, 4, 601, "RO", 1, 0, 0, 0ull},
- {"DUTRESFL" , 8, 4, 601, "RO", 1, 0, 0, 0ull},
- {"IOCDATFL" , 12, 4, 601, "RO", 1, 0, 0, 0ull},
- {"IOCCMDFL" , 16, 4, 601, "RO", 1, 0, 0, 0ull},
- {"TDPFL" , 20, 4, 601, "RO", 1, 0, 0, 0ull},
- {"XBFFL" , 24, 4, 601, "RO", 1, 0, 0, 0ull},
- {"RBFFL" , 28, 4, 601, "RO", 1, 0, 0, 0ull},
- {"DUTFL" , 32, 32, 601, "RO", 1, 0, 0, 0ull},
- {"VBFFL" , 0, 4, 602, "RO", 1, 0, 0, 0ull},
- {"RDFFL" , 4, 1, 602, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_61" , 5, 57, 602, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 62, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 63, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFL" , 0, 8, 603, "RO", 1, 0, 0, 0ull},
- {"FBFFL" , 8, 8, 603, "RO", 1, 0, 0, 0ull},
- {"SBFFL" , 16, 8, 603, "RO", 1, 0, 0, 0ull},
- {"FBFRSPFL" , 24, 8, 603, "RO", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 603, "RAZ", 1, 1, 0, 0},
- {"TAGFL" , 0, 16, 604, "RO", 1, 0, 0, 0ull},
- {"LRUFL" , 16, 1, 604, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 604, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 605, "R/W", 1, 1, 0, 0},
- {"DISIDXALIAS" , 0, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"DISECC" , 1, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"VAB_THRESH" , 2, 4, 606, "R/W", 0, 0, 0ull, 0ull},
- {"EF_CNT" , 6, 7, 606, "R/W", 0, 0, 0ull, 4ull},
- {"EF_ENA" , 13, 1, 606, "R/W", 0, 0, 0ull, 1ull},
- {"XMC_ARB_MODE" , 14, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"RSP_ARB_MODE" , 15, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"MAXLFB" , 16, 4, 606, "R/W", 0, 0, 0ull, 0ull},
- {"MAXVAB" , 20, 4, 606, "R/W", 0, 0, 0ull, 0ull},
- {"DISCCLK" , 24, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFDBE" , 25, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFSBE" , 26, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"DISSTGL2I" , 27, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 606, "RAZ", 1, 1, 0, 0},
- {"VALID" , 0, 1, 607, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_9" , 1, 9, 607, "RAZ", 1, 1, 0, 0},
- {"TAG" , 10, 28, 607, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 607, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 608, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 608, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 4, 18, 608, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_49" , 22, 28, 608, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 10, 608, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 608, "R/W1C", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 608, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 608, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 608, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 609, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_6" , 2, 5, 609, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 7, 15, 609, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_49" , 22, 28, 609, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 6, 609, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_60" , 56, 5, 609, "RAZ", 1, 1, 0, 0},
- {"NOWAY" , 61, 1, 609, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 609, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 609, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 610, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_49" , 2, 48, 610, "RAZ", 1, 1, 0, 0},
- {"VSYN" , 50, 10, 610, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 610, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 610, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 38, 611, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_47" , 38, 10, 611, "RAZ", 1, 1, 0, 0},
- {"SID" , 48, 6, 611, "RO", 0, 1, 0ull, 0},
- {"RESERVED_54_57" , 54, 4, 611, "RAZ", 1, 1, 0, 0},
- {"CMD" , 58, 6, 611, "RO", 0, 1, 0ull, 0},
- {"HOLERD" , 0, 1, 612, "R/W", 0, 0, 0ull, 1ull},
- {"HOLEWR" , 1, 1, 612, "R/W", 0, 0, 0ull, 1ull},
- {"VRTWR" , 2, 1, 612, "R/W", 0, 0, 0ull, 1ull},
- {"VRTIDRNG" , 3, 1, 612, "R/W", 0, 0, 0ull, 1ull},
- {"VRTADRNG" , 4, 1, 612, "R/W", 0, 0, 0ull, 1ull},
- {"VRTPE" , 5, 1, 612, "R/W", 0, 0, 0ull, 1ull},
- {"BIGWR" , 6, 1, 612, "R/W", 0, 0, 0ull, 1ull},
- {"BIGRD" , 7, 1, 612, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 612, "RAZ", 1, 1, 0, 0},
- {"HOLERD" , 0, 1, 613, "R/W1C", 0, 0, 0ull, 0ull},
- {"HOLEWR" , 1, 1, 613, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTWR" , 2, 1, 613, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTIDRNG" , 3, 1, 613, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTADRNG" , 4, 1, 613, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTPE" , 5, 1, 613, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGWR" , 6, 1, 613, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGRD" , 7, 1, 613, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 613, "RAZ", 1, 1, 0, 0},
- {"TAD0" , 16, 1, 613, "RO", 0, 0, 0ull, 0ull},
- {"TAD1" , 17, 1, 613, "RO", 0, 0, 0ull, 0ull},
- {"TAD2" , 18, 1, 613, "RO", 0, 0, 0ull, 0ull},
- {"TAD3" , 19, 1, 613, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 613, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 614, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 615, "R/W", 0, 1, 0ull, 0},
- {"LVL" , 0, 3, 616, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 616, "RAZ", 1, 1, 0, 0},
- {"DWBLVL" , 4, 3, 616, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 616, "RAZ", 1, 1, 0, 0},
- {"LVL" , 0, 3, 617, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 617, "RAZ", 1, 1, 0, 0},
- {"WGT0" , 0, 8, 618, "R/W", 0, 0, 255ull, 255ull},
- {"WGT1" , 8, 8, 618, "R/W", 0, 0, 255ull, 255ull},
- {"WGT2" , 16, 8, 618, "R/W", 0, 0, 255ull, 255ull},
- {"WGT3" , 24, 8, 618, "R/W", 0, 0, 255ull, 255ull},
- {"WGT4" , 32, 8, 618, "R/W", 0, 0, 255ull, 255ull},
- {"WGT5" , 40, 8, 618, "R/W", 0, 0, 255ull, 255ull},
- {"WGT6" , 48, 8, 618, "R/W", 0, 0, 255ull, 255ull},
- {"WGT7" , 56, 8, 618, "R/W", 0, 0, 255ull, 255ull},
- {"COUNT" , 0, 64, 619, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 620, "R/W", 0, 1, 0ull, 0},
- {"OW0ECC" , 0, 10, 621, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 621, "RAZ", 1, 1, 0, 0},
- {"OW1ECC" , 16, 10, 621, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 621, "RAZ", 1, 1, 0, 0},
- {"OW2ECC" , 32, 10, 621, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 621, "RAZ", 1, 1, 0, 0},
- {"OW3ECC" , 48, 10, 621, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 621, "RAZ", 1, 1, 0, 0},
- {"OW4ECC" , 0, 10, 622, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 622, "RAZ", 1, 1, 0, 0},
- {"OW5ECC" , 16, 10, 622, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 622, "RAZ", 1, 1, 0, 0},
- {"OW6ECC" , 32, 10, 622, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 622, "RAZ", 1, 1, 0, 0},
- {"OW7ECC" , 48, 10, 622, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 622, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 623, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 623, "R/W", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 623, "R/W", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 623, "R/W", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 623, "R/W", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 623, "R/W", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 623, "R/W", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 623, "R/W", 0, 0, 0ull, 1ull},
- {"WRDISLMC" , 8, 1, 623, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 623, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 624, "R/W1C", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 624, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 624, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 624, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 624, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 624, "R/W1C", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 624, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 624, "R/W1C", 0, 0, 0ull, 0ull},
- {"WRDISLMC" , 8, 1, 624, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 624, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 625, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 626, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 627, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 628, "R/W", 0, 1, 0ull, 0},
- {"CNT0SEL" , 0, 8, 629, "R/W", 0, 0, 0ull, 1ull},
- {"CNT1SEL" , 8, 8, 629, "R/W", 0, 0, 0ull, 1ull},
- {"CNT2SEL" , 16, 8, 629, "R/W", 0, 0, 0ull, 1ull},
- {"CNT3SEL" , 24, 8, 629, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 629, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 0, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"DIRTY" , 1, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"VALID" , 2, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"USE" , 3, 1, 630, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_16" , 4, 13, 630, "RAZ", 1, 1, 0, 0},
- {"TAG" , 17, 19, 630, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_39" , 36, 4, 630, "RAZ", 1, 1, 0, 0},
- {"ECC" , 40, 6, 630, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_63" , 46, 18, 630, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 631, "R/W1C", 0, 0, 0ull, 0ull},
- {"MASK" , 0, 2, 632, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 632, "RAZ", 1, 1, 0, 0},
- {"DWB" , 0, 1, 633, "R/W1C", 0, 0, 0ull, 0ull},
- {"INVL2" , 1, 1, 633, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 633, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 32, 634, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 634, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 635, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 635, "RAZ", 1, 1, 0, 0},
- {"DWBID" , 8, 6, 635, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 635, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 636, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 636, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 637, "R/W", 0, 0, 0ull, 1ull},
- {"NUMID" , 1, 3, 637, "R/W", 0, 0, 5ull, 5ull},
- {"MEMSZ" , 4, 3, 637, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_7_7" , 7, 1, 637, "RAZ", 1, 1, 0, 0},
- {"OOBERR" , 8, 1, 637, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 637, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 32, 638, "R/W", 0, 0, 0ull, 0ull},
- {"PARITY" , 32, 4, 638, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 638, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 639, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 639, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 640, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 640, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 641, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 38, 642, "R/W", 1, 1, 0, 0},
- {"RESERVED_38_56" , 38, 19, 642, "RAZ", 1, 1, 0, 0},
- {"CMD" , 57, 6, 642, "R/W", 1, 1, 0, 0},
- {"INUSE" , 63, 1, 642, "RO", 0, 0, 0ull, 0ull},
- {"COUNT" , 0, 64, 643, "R/W", 0, 1, 0ull, 0},
- {"PRBS" , 0, 32, 644, "R/W", 1, 1, 0, 0},
- {"PROG" , 32, 8, 644, "R/W", 1, 1, 0, 0},
- {"SEL" , 40, 1, 644, "R/W", 1, 1, 0, 0},
- {"EN" , 41, 1, 644, "R/W", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 644, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 645, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 646, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 646, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 647, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 648, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 648, "R/W", 1, 1, 0, 0},
- {"CKE_MASK" , 0, 2, 649, "R/W", 1, 1, 0, 0},
- {"CS0_N_MASK" , 2, 2, 649, "R/W", 1, 1, 0, 0},
- {"CS1_N_MASK" , 4, 2, 649, "R/W", 1, 1, 0, 0},
- {"ODT0_MASK" , 6, 2, 649, "R/W", 1, 1, 0, 0},
- {"ODT1_MASK" , 8, 2, 649, "R/W", 1, 1, 0, 0},
- {"RAS_N_MASK" , 10, 1, 649, "R/W", 1, 1, 0, 0},
- {"CAS_N_MASK" , 11, 1, 649, "R/W", 1, 1, 0, 0},
- {"WE_N_MASK" , 12, 1, 649, "R/W", 1, 1, 0, 0},
- {"BA_MASK" , 13, 3, 649, "R/W", 1, 1, 0, 0},
- {"A_MASK" , 16, 16, 649, "R/W", 1, 1, 0, 0},
- {"RESET_N_MASK" , 32, 1, 649, "R/W", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 649, "R/W", 1, 1, 0, 0},
- {"DQX_CTL" , 0, 4, 650, "R/W", 0, 1, 4ull, 0},
- {"CK_CTL" , 4, 4, 650, "R/W", 0, 1, 4ull, 0},
- {"CMD_CTL" , 8, 4, 650, "R/W", 0, 1, 4ull, 0},
- {"RODT_CTL" , 12, 4, 650, "R/W", 0, 1, 0ull, 0},
- {"NTUNE" , 16, 4, 650, "R/W", 0, 1, 0ull, 0},
- {"PTUNE" , 20, 4, 650, "R/W", 0, 1, 0ull, 0},
- {"BYP" , 24, 1, 650, "R/W", 0, 1, 0ull, 0},
- {"M180" , 25, 1, 650, "R/W", 0, 1, 0ull, 0},
- {"DDR__NTUNE" , 26, 4, 650, "RO", 1, 1, 0, 0},
- {"DDR__PTUNE" , 30, 4, 650, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 650, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 651, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 651, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 651, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 651, "R/W", 0, 1, 5ull, 0},
- {"IDLEPOWER" , 9, 3, 651, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 12, 4, 651, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 16, 1, 651, "R/W", 0, 0, 0ull, 1ull},
- {"RESET" , 17, 1, 651, "R/W", 0, 1, 0ull, 0},
- {"REF_ZQCS_INT" , 18, 19, 651, "R/W", 1, 1, 0, 0},
- {"SEQUENCE" , 37, 3, 651, "R/W", 0, 0, 0ull, 0ull},
- {"EARLY_DQX" , 40, 1, 651, "R/W", 0, 0, 0ull, 0ull},
- {"SREF_WITH_DLL" , 41, 1, 651, "R/W", 0, 0, 0ull, 0ull},
- {"RANK_ENA" , 42, 1, 651, "R/W", 0, 1, 0ull, 0},
- {"RANKMASK" , 43, 4, 651, "R/W", 0, 1, 0ull, 0},
- {"MIRRMASK" , 47, 4, 651, "R/W", 0, 1, 0ull, 0},
- {"INIT_STATUS" , 51, 4, 651, "R/W1", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R0" , 55, 1, 651, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R1" , 56, 1, 651, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R0" , 57, 1, 651, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R1" , 58, 1, 651, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_59_63" , 59, 5, 651, "RAZ", 1, 1, 0, 0},
- {"RDIMM_ENA" , 0, 1, 652, "R/W", 0, 1, 0ull, 0},
- {"BWCNT" , 1, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 2, 1, 652, "R/W", 0, 0, 0ull, 1ull},
- {"POCAS" , 3, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH2" , 4, 2, 652, "R/W", 0, 0, 0ull, 1ull},
- {"THROTTLE_RD" , 6, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"THROTTLE_WR" , 7, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_RD" , 8, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_WR" , 9, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"ELEV_PRIO_DIS" , 10, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"NXM_WRITE_EN" , 11, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 12, 4, 652, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 16, 1, 652, "R/W", 0, 0, 0ull, 1ull},
- {"AUTO_DCLKDIS" , 17, 1, 652, "R/W", 0, 0, 0ull, 1ull},
- {"INT_ZQCS_DIS" , 18, 1, 652, "R/W", 0, 0, 1ull, 0ull},
- {"EXT_ZQCS_DIS" , 19, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 20, 2, 652, "R/W", 0, 0, 0ull, 0ull},
- {"WODT_BPRCH" , 22, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_BPRCH" , 23, 1, 652, "R/W", 0, 0, 0ull, 0ull},
- {"CRM_MAX" , 24, 5, 652, "R/W", 0, 0, 31ull, 31ull},
- {"CRM_THR" , 29, 5, 652, "R/W", 0, 0, 0ull, 8ull},
- {"CRM_CNT" , 34, 5, 652, "RO", 0, 0, 0ull, 0ull},
- {"THRMAX" , 39, 4, 652, "R/W", 0, 0, 15ull, 2ull},
- {"PERSUB" , 43, 8, 652, "R/W", 0, 0, 0ull, 0ull},
- {"THRCNT" , 51, 12, 652, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_63_63" , 63, 1, 652, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT" , 0, 64, 653, "RO", 0, 1, 0ull, 0},
- {"CLKF" , 0, 7, 654, "R/W", 0, 1, 48ull, 0},
- {"RESET_N" , 7, 1, 654, "R/W", 0, 0, 0ull, 1ull},
- {"CPB" , 8, 3, 654, "R/W", 0, 0, 0ull, 1ull},
- {"CPS" , 11, 3, 654, "R/W", 0, 0, 0ull, 1ull},
- {"DIFFAMP" , 14, 4, 654, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_PS_EN" , 18, 3, 654, "R/W", 0, 1, 2ull, 0},
- {"DDR_DIV_RESET" , 21, 1, 654, "R/W", 0, 0, 1ull, 0ull},
- {"DFM_PS_EN" , 22, 3, 654, "R/W", 0, 1, 2ull, 0},
- {"DFM_DIV_RESET" , 25, 1, 654, "R/W", 0, 0, 1ull, 0ull},
- {"JTG_TEST_MODE" , 26, 1, 654, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 654, "RAZ", 1, 1, 0, 0},
- {"RC0" , 0, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC1" , 4, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC2" , 8, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC3" , 12, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC4" , 16, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC5" , 20, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC6" , 24, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC7" , 28, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC8" , 32, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC9" , 36, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC10" , 40, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC11" , 44, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC12" , 48, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC13" , 52, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC14" , 56, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"RC15" , 60, 4, 655, "R/W", 0, 0, 0ull, 0ull},
- {"DIMM0_WMASK" , 0, 16, 656, "R/W", 0, 0, 65535ull, 65535ull},
- {"DIMM1_WMASK" , 16, 16, 656, "R/W", 0, 0, 65535ull, 65535ull},
- {"TCWS" , 32, 13, 656, "R/W", 0, 0, 1248ull, 1248ull},
- {"PARITY" , 45, 1, 656, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 656, "RAZ", 1, 1, 0, 0},
- {"BYP_SETTING" , 0, 8, 657, "R/W", 0, 0, 0ull, 0ull},
- {"BYP_SEL" , 8, 4, 657, "R/W", 0, 0, 0ull, 0ull},
- {"QUAD_DLL_ENA" , 12, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 13, 1, 657, "R/W", 0, 0, 1ull, 0ull},
- {"DLL_BRINGUP" , 14, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"INTF_EN" , 15, 1, 657, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 657, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 658, "R/W", 0, 0, 0ull, 0ull},
- {"BYTE_SEL" , 6, 4, 658, "R/W", 0, 0, 0ull, 0ull},
- {"MODE_SEL" , 10, 2, 658, "R/W", 0, 0, 0ull, 0ull},
- {"LOAD_OFFSET" , 12, 1, 658, "WR0", 0, 0, 0ull, 0ull},
- {"OFFSET_ENA" , 13, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYTE_SEL" , 14, 4, 658, "R/W", 0, 0, 1ull, 1ull},
- {"DLL_MODE" , 18, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"FINE_TUNE_MODE" , 19, 1, 658, "R/W", 0, 0, 0ull, 1ull},
- {"DLL90_SETTING" , 20, 8, 658, "RO", 1, 1, 0, 0},
- {"DLL_FAST" , 28, 1, 658, "RO", 1, 1, 0, 0},
- {"DCLK90_BYP_SETTING" , 29, 8, 658, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_BYP_SEL" , 37, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_RECAL_DIS" , 38, 1, 658, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_90_DLY_BYP" , 39, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_FWD" , 40, 1, 658, "WR0", 0, 0, 0ull, 0ull},
- {"RESERVED_41_63" , 41, 23, 658, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 659, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 659, "RAZ", 1, 1, 0, 0},
- {"ROW_LSB" , 16, 3, 659, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_19_63" , 19, 45, 659, "RAZ", 1, 1, 0, 0},
- {"MRDSYN0" , 0, 8, 660, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 660, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 660, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 660, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 660, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 14, 661, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 14, 16, 661, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 30, 3, 661, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 33, 1, 661, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 34, 2, 661, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 661, "RAZ", 1, 1, 0, 0},
- {"IFBCNT" , 0, 64, 662, "RO", 0, 1, 1ull, 0},
- {"NXM_WR_ERR" , 0, 1, 663, "R/W1C", 0, 0, 0ull, 0ull},
- {"SEC_ERR" , 1, 4, 663, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 5, 4, 663, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 663, "RAZ", 1, 1, 0, 0},
- {"INTR_NXM_WR_ENA" , 0, 1, 664, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_SEC_ENA" , 1, 1, 664, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 2, 1, 664, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 664, "RAZ", 1, 1, 0, 0},
- {"CWL" , 0, 3, 665, "R/W", 0, 0, 0ull, 0ull},
- {"MPRLOC" , 3, 2, 665, "R/W", 0, 0, 0ull, 0ull},
- {"MPR" , 5, 1, 665, "R/W", 0, 0, 0ull, 0ull},
- {"DLL" , 6, 1, 665, "R/W", 0, 0, 0ull, 0ull},
- {"AL" , 7, 2, 665, "R/W", 0, 0, 0ull, 0ull},
- {"WLEV" , 9, 1, 665, "RO", 0, 0, 0ull, 0ull},
- {"TDQS" , 10, 1, 665, "R/W", 0, 0, 0ull, 0ull},
- {"QOFF" , 11, 1, 665, "R/W", 0, 0, 0ull, 0ull},
- {"BL" , 12, 2, 665, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 14, 4, 665, "R/W", 0, 0, 2ull, 2ull},
- {"RBT" , 18, 1, 665, "RO", 0, 0, 1ull, 1ull},
- {"TM" , 19, 1, 665, "R/W", 0, 0, 0ull, 0ull},
- {"DLLR" , 20, 1, 665, "R/W", 0, 0, 0ull, 0ull},
- {"WRP" , 21, 3, 665, "R/W", 0, 0, 0ull, 0ull},
- {"PPD" , 24, 1, 665, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 665, "RAZ", 1, 1, 0, 0},
- {"PASR_00" , 0, 3, 666, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_00" , 3, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_00" , 4, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_00" , 5, 2, 666, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_00" , 7, 2, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_00" , 9, 3, 666, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_01" , 12, 3, 666, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_01" , 15, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_01" , 16, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_01" , 17, 2, 666, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_01" , 19, 2, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_01" , 21, 3, 666, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_10" , 24, 3, 666, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_10" , 27, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_10" , 28, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_10" , 29, 2, 666, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_10" , 31, 2, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_10" , 33, 3, 666, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_11" , 36, 3, 666, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_11" , 39, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_11" , 40, 1, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_11" , 41, 2, 666, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_11" , 43, 2, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_11" , 45, 3, 666, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 666, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 667, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R0" , 8, 4, 667, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R1" , 12, 4, 667, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R0" , 16, 4, 667, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R1" , 20, 4, 667, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R0" , 24, 4, 667, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R1" , 28, 4, 667, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R0" , 32, 4, 667, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R1" , 36, 4, 667, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 667, "RAZ", 1, 1, 0, 0},
- {"OPSCNT" , 0, 64, 668, "RO", 0, 1, 1ull, 0},
- {"TS_STAGGER" , 0, 1, 669, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK_POS" , 1, 1, 669, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK" , 2, 1, 669, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT0" , 3, 4, 669, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE0" , 7, 1, 669, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT1" , 8, 4, 669, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE1" , 12, 1, 669, "R/W", 0, 1, 0ull, 0},
- {"LV_MODE" , 13, 1, 669, "R/W", 0, 1, 0ull, 0},
- {"RX_ALWAYS_ON" , 14, 1, 669, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 669, "RAZ", 1, 1, 0, 0},
- {"DDR3RST" , 0, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PWARM" , 1, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSOFT" , 2, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSV" , 3, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 670, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 671, "R/W", 0, 1, 0ull, 0},
- {"OFFSET" , 4, 4, 671, "R/W", 0, 0, 2ull, 2ull},
- {"OFFSET_EN" , 8, 1, 671, "R/W", 0, 0, 1ull, 1ull},
- {"OR_DIS" , 9, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 10, 8, 671, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_0" , 18, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_1" , 19, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_2" , 20, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_3" , 21, 1, 671, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 671, "RAZ", 1, 1, 0, 0},
- {"BITMASK" , 0, 64, 672, "RO", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 6, 673, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 6, 6, 673, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 12, 6, 673, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 18, 6, 673, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 24, 6, 673, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 30, 6, 673, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 36, 6, 673, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 42, 6, 673, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 48, 6, 673, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 54, 2, 673, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 673, "RAZ", 1, 1, 0, 0},
- {"RODT_D0_R0" , 0, 8, 674, "R/W", 0, 1, 0ull, 0},
- {"RODT_D0_R1" , 8, 8, 674, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R0" , 16, 8, 674, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R1" , 24, 8, 674, "R/W", 0, 1, 0ull, 0},
- {"RODT_D2_R0" , 32, 8, 674, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R1" , 40, 8, 674, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R0" , 48, 8, 674, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R1" , 56, 8, 674, "R/W", 0, 0, 0ull, 0ull},
- {"R2R_INIT" , 0, 6, 675, "R/W", 0, 1, 1ull, 0},
- {"R2W_INIT" , 6, 6, 675, "R/W", 0, 1, 6ull, 0},
- {"W2R_INIT" , 12, 6, 675, "R/W", 0, 1, 9ull, 0},
- {"W2W_INIT" , 18, 6, 675, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_24_63" , 24, 40, 675, "RAZ", 1, 1, 0, 0},
- {"R2R_XRANK_INIT" , 0, 6, 676, "R/W", 0, 1, 3ull, 0},
- {"R2W_XRANK_INIT" , 6, 6, 676, "R/W", 0, 1, 6ull, 0},
- {"W2R_XRANK_INIT" , 12, 6, 676, "R/W", 0, 1, 4ull, 0},
- {"W2W_XRANK_INIT" , 18, 6, 676, "R/W", 0, 1, 5ull, 0},
- {"RESERVED_24_63" , 24, 40, 676, "RAZ", 1, 1, 0, 0},
- {"R2R_XDIMM_INIT" , 0, 6, 677, "R/W", 0, 1, 4ull, 0},
- {"R2W_XDIMM_INIT" , 6, 6, 677, "R/W", 0, 1, 7ull, 0},
- {"W2R_XDIMM_INIT" , 12, 6, 677, "R/W", 0, 1, 4ull, 0},
- {"W2W_XDIMM_INIT" , 18, 6, 677, "R/W", 0, 1, 6ull, 0},
- {"RESERVED_24_63" , 24, 40, 677, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_9" , 0, 10, 678, "RAZ", 1, 1, 0, 0},
- {"TZQCS" , 10, 4, 678, "R/W", 0, 0, 4ull, 4ull},
- {"TCKE" , 14, 4, 678, "R/W", 0, 0, 3ull, 3ull},
- {"TXPR" , 18, 4, 678, "R/W", 0, 0, 5ull, 5ull},
- {"TMRD" , 22, 4, 678, "R/W", 0, 0, 4ull, 4ull},
- {"TMOD" , 26, 4, 678, "R/W", 0, 0, 12ull, 12ull},
- {"TDLLK" , 30, 4, 678, "R/W", 0, 0, 2ull, 2ull},
- {"TZQINIT" , 34, 4, 678, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 38, 4, 678, "R/W", 0, 0, 6ull, 6ull},
- {"TCKSRE" , 42, 4, 678, "R/W", 0, 0, 5ull, 5ull},
- {"TRP_EXT" , 46, 1, 678, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 678, "RAZ", 1, 1, 0, 0},
- {"TMPRR" , 0, 4, 679, "R/W", 0, 0, 1ull, 1ull},
- {"TRAS" , 4, 5, 679, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 9, 4, 679, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 13, 4, 679, "R/W", 0, 0, 2ull, 3ull},
- {"TRFC" , 17, 5, 679, "R/W", 0, 0, 6ull, 7ull},
- {"TRRD" , 22, 3, 679, "R/W", 0, 0, 2ull, 2ull},
- {"TXP" , 25, 3, 679, "R/W", 0, 0, 3ull, 3ull},
- {"TWLMRD" , 28, 4, 679, "R/W", 0, 0, 10ull, 10ull},
- {"TWLDQSEN" , 32, 4, 679, "R/W", 0, 0, 7ull, 7ull},
- {"TFAW" , 36, 5, 679, "R/W", 0, 0, 0ull, 9ull},
- {"TXPDLL" , 41, 5, 679, "R/W", 0, 0, 0ull, 10ull},
- {"TRAS_EXT" , 46, 1, 679, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 679, "RAZ", 1, 1, 0, 0},
- {"TRESET" , 0, 1, 680, "R/W", 0, 1, 1ull, 0},
- {"RCLK_CNT" , 1, 32, 680, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 680, "RAZ", 1, 1, 0, 0},
- {"RING_CNT" , 0, 32, 681, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 681, "RAZ", 1, 1, 0, 0},
- {"LANEMASK" , 0, 9, 682, "R/W", 0, 1, 0ull, 0},
- {"SSET" , 9, 1, 682, "R/W", 0, 1, 0ull, 0},
- {"OR_DIS" , 10, 1, 682, "R/W", 0, 1, 0ull, 0},
- {"BITMASK" , 11, 8, 682, "R/W", 0, 1, 0ull, 0},
- {"RTT_NOM" , 19, 3, 682, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 682, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 683, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 4, 8, 683, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 683, "RAZ", 1, 1, 0, 0},
- {"BYTE0" , 0, 5, 684, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 5, 5, 684, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 10, 5, 684, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 15, 5, 684, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 20, 5, 684, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 25, 5, 684, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 30, 5, 684, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 35, 5, 684, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 40, 5, 684, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 45, 2, 684, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_63" , 47, 17, 684, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 685, "R/W", 0, 1, 255ull, 0},
- {"WODT_D0_R1" , 8, 8, 685, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R0" , 16, 8, 685, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R1" , 24, 8, 685, "R/W", 0, 1, 255ull, 0},
- {"WODT_D2_R0" , 32, 8, 685, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D2_R1" , 40, 8, 685, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R0" , 48, 8, 685, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R1" , 56, 8, 685, "R/W", 0, 0, 255ull, 0ull},
- {"STAT" , 0, 10, 686, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 686, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 687, "R/W", 1, 1, 0, 0},
- {"PCTL" , 6, 6, 687, "R/W", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 687, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 688, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 688, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 688, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 688, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 688, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 688, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 688, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 688, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 688, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 688, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 689, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 689, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 689, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 690, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 690, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 690, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 691, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 691, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 691, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 691, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 691, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 691, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 691, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 691, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 691, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 691, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 691, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 691, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 691, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 691, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 691, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 692, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 692, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 692, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 693, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 693, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 693, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 694, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 694, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 694, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 695, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 695, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 695, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 695, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 695, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 696, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 697, "RAZ", 1, 1, 0, 0},
- {"NAND" , 8, 1, 697, "RO", 1, 1, 0, 0},
- {"TERM" , 9, 2, 697, "RO", 1, 1, 0, 0},
- {"DMACK_P0" , 11, 1, 697, "RO", 1, 1, 0, 0},
- {"DMACK_P1" , 12, 1, 697, "RO", 1, 1, 0, 0},
- {"RESERVED_13_13" , 13, 1, 697, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 14, 1, 697, "RO", 1, 1, 0, 0},
- {"ALE" , 15, 1, 697, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 697, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 16, 698, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 698, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 698, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 698, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 698, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 698, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 698, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 698, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 698, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 698, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 698, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 698, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 698, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 699, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 699, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 699, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 699, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 699, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 699, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 699, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 699, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 699, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 699, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 699, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 699, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 699, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 700, "R/W", 0, 0, 25ull, 25ull},
- {"RESERVED_6_7" , 6, 2, 700, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 700, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 700, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 700, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 700, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 701, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 702, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 702, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 703, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 703, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 704, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 704, "RO", 1, 1, 0, 0},
- {"RESERVED_24_25" , 24, 2, 704, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 704, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 704, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 704, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 704, "RO", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 704, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 704, "RO", 1, 1, 0, 0},
- {"DORM_CRYPTO" , 34, 1, 704, "RO", 1, 1, 0, 0},
- {"POWER_LIMIT" , 35, 2, 704, "RO", 1, 1, 0, 0},
- {"RESERVED_37_63" , 37, 27, 704, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 705, "RAZ", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 705, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 705, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 705, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 705, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 705, "RO", 1, 1, 0, 0},
- {"ZIP_INFO" , 29, 2, 705, "RO", 1, 1, 0, 0},
- {"RESERVED_31_31" , 31, 1, 705, "RAZ", 1, 1, 0, 0},
- {"L2C_CRIP" , 32, 3, 705, "RO", 1, 1, 0, 0},
- {"PLL_HALF_DIS" , 35, 1, 705, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_MAN" , 36, 1, 705, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_RSV" , 37, 1, 705, "RO", 1, 1, 0, 0},
- {"EMA" , 38, 2, 705, "RO", 1, 1, 0, 0},
- {"RESERVED_40_40" , 40, 1, 705, "RAZ", 1, 1, 0, 0},
- {"DFA_INFO_CLM" , 41, 4, 705, "RO", 1, 1, 0, 0},
- {"DFA_INFO_DTE" , 45, 3, 705, "RO", 1, 1, 0, 0},
- {"PLL_CTL" , 48, 10, 705, "RO", 1, 1, 0, 0},
- {"RESERVED_58_63" , 58, 6, 705, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 706, "RAZ", 1, 1, 0, 0},
- {"RESERVED_3_3" , 3, 1, 706, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 706, "RAZ", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 706, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 707, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 708, "RAZ", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 708, "RAZ", 0, 1, 0ull, 0},
- {"PNR_COUT_SEL" , 2, 2, 708, "R/W", 0, 1, 0ull, 0},
- {"PNR_COUT_RST" , 4, 1, 708, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_SEL" , 5, 2, 708, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_RST" , 7, 1, 708, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_31" , 8, 24, 708, "RAZ", 1, 1, 0, 0},
- {"RCLK_ALIGN_L" , 32, 8, 708, "RO", 1, 1, 0, 0},
- {"RCLK_ALIGN_R" , 40, 8, 708, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 708, "RO", 1, 1, 0, 0},
- {"PROG" , 0, 1, 709, "R/W", 1, 1, 0, 0},
- {"SOFT" , 1, 1, 709, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 709, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 6, 710, "R/W", 0, 1, 1ull, 0},
- {"SCLK_HI" , 6, 15, 710, "R/W", 0, 1, 5000ull, 0},
- {"SCLK_LO" , 21, 4, 710, "R/W", 0, 1, 1ull, 0},
- {"OUT" , 25, 7, 710, "R/W", 0, 1, 1ull, 0},
- {"PROG_PIN" , 32, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"FSRC_PIN" , 33, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"VGATE_PIN" , 34, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 710, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 711, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 711, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 711, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 711, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 711, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 711, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 711, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 10, 712, "R/W", 0, 1, 999ull, 0},
- {"SDH" , 10, 4, 712, "R/W", 0, 1, 0ull, 0},
- {"PRH" , 14, 4, 712, "R/W", 0, 1, 6ull, 0},
- {"FSH" , 18, 4, 712, "R/W", 0, 1, 15ull, 0},
- {"SCH" , 22, 4, 712, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_26_63" , 26, 38, 712, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 18, 713, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 18, 18, 713, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 36, 18, 713, "RO", 0, 0, 0ull, 0ull},
- {"TOO_MANY" , 54, 1, 713, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 713, "RAZ", 1, 1, 0, 0},
- {"REPAIR3" , 0, 18, 714, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR4" , 18, 18, 714, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR5" , 36, 18, 714, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 714, "RAZ", 1, 1, 0, 0},
- {"REPAIR6" , 0, 18, 715, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 715, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 716, "RAZ", 1, 1, 0, 0},
- {"REPAIR1" , 14, 14, 716, "RAZ", 1, 1, 0, 0},
- {"REPAIR2" , 28, 14, 716, "RAZ", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 716, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 717, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 717, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 4, 718, "R/W", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 718, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 719, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 6, 6, 719, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_12_63" , 12, 52, 719, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 720, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 720, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 720, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 720, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 720, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 720, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 720, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 720, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 720, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 720, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 721, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 721, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 722, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 722, "RAZ", 1, 1, 0, 0},
- {"PTP_EN" , 0, 1, 723, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EN" , 1, 1, 723, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_IN" , 2, 6, 723, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EN" , 8, 1, 723, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EDGE" , 9, 1, 723, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_IN" , 10, 6, 723, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EN" , 16, 1, 723, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EDGE" , 17, 1, 723, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_IN" , 18, 6, 723, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 723, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 724, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 724, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 725, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 726, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 726, "RAZ", 1, 1, 0, 0},
- {"CNTR" , 0, 64, 727, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 728, "R/W", 0, 0, 0ull, 0ull},
- {"QLM_CFG" , 0, 3, 729, "RO", 1, 1, 0, 0},
- {"RESERVED_3_7" , 3, 5, 729, "RAZ", 1, 1, 0, 0},
- {"QLM_SPD" , 8, 4, 729, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 729, "RAZ", 1, 1, 0, 0},
- {"RBOOT_PIN" , 0, 1, 730, "RO", 1, 1, 0, 0},
- {"RBOOT" , 1, 1, 730, "R/W", 1, 1, 0, 0},
- {"LBOOT" , 2, 10, 730, "R/W1C", 1, 1, 0, 0},
- {"QLM0_SPD" , 12, 4, 730, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 16, 4, 730, "RO", 1, 1, 0, 0},
- {"QLM2_SPD" , 20, 4, 730, "RO", 1, 1, 0, 0},
- {"PNR_MUL" , 24, 6, 730, "RO", 1, 1, 0, 0},
- {"C_MUL" , 30, 6, 730, "RO", 1, 1, 0, 0},
- {"QLM3_SPD" , 36, 4, 730, "RO", 1, 1, 0, 0},
- {"QLM4_SPD" , 40, 4, 730, "RO", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 730, "RAZ", 1, 1, 0, 0},
- {"SOFT_CLR_BIST" , 0, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"WARM_CLR_BIST" , 1, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"CNTL_CLR_BIST" , 2, 1, 731, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 731, "RAZ", 1, 1, 0, 0},
- {"BIST_DELAY" , 8, 56, 731, "RO", 1, 1, 0, 0},
- {"RST_VAL" , 0, 1, 732, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 732, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 732, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 732, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 732, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 732, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 732, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 732, "RO", 1, 1, 0, 0},
- {"PRST_LINK" , 9, 1, 732, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 732, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST_DLY" , 0, 16, 733, "R/W", 0, 1, 2047ull, 0},
- {"WARM_RST_DLY" , 16, 16, 733, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_32_63" , 32, 32, 733, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 734, "R/W1C", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 734, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 734, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 734, "R/W1C", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 734, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 734, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 735, "R/W", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 735, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 735, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 735, "R/W", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 735, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 735, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 736, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 736, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 736, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 736, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 736, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 736, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 736, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 736, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 736, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 736, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 736, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 736, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 736, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 737, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 737, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 737, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 737, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 737, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 737, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 737, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 737, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 737, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 737, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 737, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 737, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 738, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 738, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 738, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 739, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 739, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 739, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 740, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 740, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 741, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 741, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 742, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 742, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 743, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 743, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 743, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 743, "RAZ", 1, 1, 0, 0},
- {"TXTRIG" , 4, 2, 743, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 743, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 743, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 744, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 744, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 745, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 745, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 745, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 745, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 745, "RAZ", 1, 1, 0, 0},
- {"PTIME" , 7, 1, 745, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 745, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 746, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 746, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 746, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 746, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 747, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 747, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 747, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 747, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 747, "RAZ", 1, 1, 0, 0},
- {"BRK" , 6, 1, 747, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 747, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 747, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 748, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 748, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 748, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 748, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 748, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 748, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 748, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 748, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 748, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 749, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 749, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 749, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 749, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 749, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 749, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 749, "RAZ", 1, 1, 0, 0},
- {"DCTS" , 0, 1, 750, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 750, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 750, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 750, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 750, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 750, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 750, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 750, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 750, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 751, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 751, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 752, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 752, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 753, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 753, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 753, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 753, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 754, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 754, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 755, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 755, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 756, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 756, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 757, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 757, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 757, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 757, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 758, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 758, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 759, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 759, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 760, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 760, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 761, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 761, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 762, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 762, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 763, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 763, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 764, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 764, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 764, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 764, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 764, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 764, "RAZ", 1, 1, 0, 0},
- {"ORFDAT" , 0, 1, 765, "RO", 0, 0, 0ull, 0ull},
- {"IRFDAT" , 1, 1, 765, "RO", 0, 0, 0ull, 0ull},
- {"IPFDAT" , 2, 1, 765, "RO", 0, 0, 0ull, 0ull},
- {"MRQDAT" , 3, 1, 765, "RO", 0, 0, 0ull, 0ull},
- {"MRGDAT" , 4, 1, 765, "RO", 0, 0, 0ull, 0ull},
- {"OPFDAT" , 5, 1, 765, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 765, "RAZ", 0, 0, 0ull, 0ull},
- {"MRQ_HWM" , 0, 2, 766, "R/W", 0, 0, 0ull, 1ull},
- {"NBTARB" , 2, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"LENDIAN" , 3, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 4, 1, 766, "R/W", 0, 0, 1ull, 0ull},
- {"EN" , 5, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 6, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"CRC_STRIP" , 7, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"TS_THRESH" , 8, 4, 766, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 766, "RAZ", 1, 1, 0, 0},
- {"OVFENA" , 0, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"IVFENA" , 1, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"OTHENA" , 2, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"ITHENA" , 3, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_DRPENA" , 4, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"IRUNENA" , 5, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"ORUNENA" , 6, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"TSENA" , 7, 1, 767, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 767, "RAZ", 1, 1, 0, 0},
- {"IRCNT" , 0, 20, 768, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 768, "RAZ", 1, 1, 0, 0},
- {"IRHWM" , 0, 20, 769, "R/W", 0, 0, 0ull, 0ull},
- {"IBPLWM" , 20, 20, 769, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 769, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 770, "RAZ", 1, 1, 0, 0},
- {"IBASE" , 3, 37, 770, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 40, 20, 770, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 770, "RAZ", 1, 1, 0, 0},
- {"IDBELL" , 0, 20, 771, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 771, "RAZ", 1, 1, 0, 0},
- {"ITLPTR" , 32, 20, 771, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 771, "RAZ", 1, 1, 0, 0},
- {"ODBLOVF" , 0, 1, 772, "R/W1C", 0, 0, 0ull, 0ull},
- {"IDBLOVF" , 1, 1, 772, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORTHRESH" , 2, 1, 772, "RO", 0, 0, 0ull, 0ull},
- {"IRTHRESH" , 3, 1, 772, "RO", 0, 0, 0ull, 0ull},
- {"DATA_DRP" , 4, 1, 772, "R/W1C", 0, 0, 0ull, 0ull},
- {"IRUN" , 5, 1, 772, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORUN" , 6, 1, 772, "R/W1C", 0, 0, 0ull, 0ull},
- {"TS" , 7, 1, 772, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 772, "RAZ", 1, 1, 0, 0},
- {"ORCNT" , 0, 20, 773, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 773, "RAZ", 1, 1, 0, 0},
- {"ORHWM" , 0, 20, 774, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 774, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 775, "RAZ", 1, 1, 0, 0},
- {"OBASE" , 3, 37, 775, "R/W", 0, 1, 0ull, 0},
- {"OSIZE" , 40, 20, 775, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 775, "RAZ", 1, 1, 0, 0},
- {"ODBELL" , 0, 20, 776, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 776, "RAZ", 1, 1, 0, 0},
- {"OTLPTR" , 32, 20, 776, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 776, "RAZ", 1, 1, 0, 0},
- {"OREMCNT" , 0, 20, 777, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 777, "RAZ", 1, 1, 0, 0},
- {"IREMCNT" , 32, 20, 777, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_52_63" , 52, 12, 777, "RAZ", 1, 1, 0, 0},
- {"TSCNT" , 0, 5, 778, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 778, "RAZ", 1, 1, 0, 0},
- {"TSTOT" , 8, 5, 778, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 778, "RAZ", 1, 1, 0, 0},
- {"TSAVL" , 16, 5, 778, "RO", 0, 0, 4ull, 4ull},
- {"RESERVED_21_63" , 21, 43, 778, "RAZ", 1, 1, 0, 0},
- {"TSTAMP" , 0, 64, 779, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 3, 780, "R/W", 0, 1, 0ull, 0},
- {"ADR_CYC" , 3, 4, 780, "R/W", 0, 1, 8ull, 0},
- {"T_MULT" , 7, 4, 780, "R/W", 0, 1, 9ull, 0},
- {"RESERVED_11_63" , 11, 53, 780, "RAZ", 1, 1, 0, 0},
- {"NF_CMD" , 0, 64, 781, "R/W", 0, 1, 0ull, 0},
- {"CNT" , 0, 8, 782, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 782, "RAZ", 1, 1, 0, 0},
- {"ECC_ERR" , 0, 8, 783, "RO", 0, 1, 0ull, 0},
- {"XOR_ECC" , 8, 24, 783, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 783, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 784, "R/W1C", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 784, "R/W1C", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 784, "R/W1C", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 784, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 784, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 784, "R/W1C", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 784, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 784, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 785, "R/W", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 785, "R/W", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 785, "R/W", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 785, "R/W", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 785, "R/W", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 785, "R/W", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 785, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 785, "RAZ", 1, 1, 0, 0},
- {"RST_FF" , 0, 1, 786, "R/W", 0, 0, 0ull, 0ull},
- {"EX_DIS" , 1, 1, 786, "R/W", 0, 0, 0ull, 0ull},
- {"BT_DIS" , 2, 1, 786, "R/W", 0, 0, 0ull, 1ull},
- {"BT_DMA" , 3, 1, 786, "R/W", 0, 1, 0ull, 0},
- {"RD_CMD" , 4, 1, 786, "R/W", 0, 0, 0ull, 0ull},
- {"RD_VAL" , 5, 1, 786, "RO", 0, 1, 0ull, 0},
- {"RD_DONE" , 6, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"FR_BYT" , 7, 11, 786, "RO", 0, 1, 0ull, 0},
- {"WAIT_CNT" , 18, 6, 786, "R/W", 0, 1, 20ull, 0},
- {"NBR_HWM" , 24, 3, 786, "R/W", 0, 0, 3ull, 3ull},
- {"MB_DIS" , 27, 1, 786, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 786, "RAZ", 1, 1, 0, 0},
- {"MAIN_SM" , 0, 3, 787, "RO", 0, 1, 0ull, 0},
- {"MAIN_BAD" , 3, 1, 787, "RO", 0, 1, 0ull, 0},
- {"RD_FF" , 4, 2, 787, "RO", 0, 1, 0ull, 0},
- {"RD_FF_BAD" , 6, 1, 787, "RO", 0, 1, 0ull, 0},
- {"BT_SM" , 7, 4, 787, "RO", 0, 1, 0ull, 0},
- {"EXE_SM" , 11, 4, 787, "RO", 0, 1, 0ull, 0},
- {"EXE_IDLE" , 15, 1, 787, "RO", 0, 1, 1ull, 0},
- {"RESERVED_16_63" , 16, 48, 787, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 788, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 788, "RO/WRSL", 0, 0, 145ull, 145ull},
- {"ISAE" , 0, 1, 789, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 789, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 789, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 789, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 789, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 789, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 789, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 789, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 789, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 789, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 789, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 789, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 789, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 789, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 789, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 789, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 789, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 789, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 790, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PI" , 8, 8, 790, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 790, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 790, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 791, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 791, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 791, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 791, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 791, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 792, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 792, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 792, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 792, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 792, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 793, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 793, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 794, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 795, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 796, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 796, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 796, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 796, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 796, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 797, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 797, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 798, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 799, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 800, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 800, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 800, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 800, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 801, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 801, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_8" , 0, 9, 802, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 9, 23, 802, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 803, "WORSL", 0, 0, 511ull, 511ull},
- {"CISP" , 0, 32, 804, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 805, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 805, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 806, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 806, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 807, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 807, "WORSL", 0, 0, 32767ull, 32767ull},
- {"CP" , 0, 8, 808, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 808, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 809, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 809, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 809, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 809, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 810, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 810, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 810, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 810, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 810, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 810, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 810, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 810, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 810, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 810, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 811, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 811, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 811, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 811, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 811, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 811, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 811, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 811, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 811, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 811, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 811, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 811, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 812, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 812, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 812, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 812, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 812, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 812, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PVM" , 24, 1, 812, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 812, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 813, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 813, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 814, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 815, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 815, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 816, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 816, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 816, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 816, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 816, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 816, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 816, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 817, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 817, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 817, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 817, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 817, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 817, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 817, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 817, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 817, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 817, "RO", 0, 0, 0ull, 0ull},
- {"FLR" , 28, 1, 817, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 817, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 818, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 818, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 818, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 818, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 818, "R/W", 0, 0, 2ull, 2ull},
- {"I_FLR" , 15, 1, 818, "RO", 0, 0, 0ull, 0ull},
- {"CE_D" , 16, 1, 818, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 818, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 818, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 818, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 818, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 818, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 818, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 819, "RO/WRSL", 1, 1, 0, 0},
- {"MLW" , 4, 6, 819, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"ASLPMS" , 10, 2, 819, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 819, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 819, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 819, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 819, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 819, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 819, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 819, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 819, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 820, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 820, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 820, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 820, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 820, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 820, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 820, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 820, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 820, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 820, "RO", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 820, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 820, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 820, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 820, "RO", 0, 0, 0ull, 8ull},
- {"RESERVED_26_26" , 26, 1, 820, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 820, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 820, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 820, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 820, "RAZ", 1, 1, 0, 0},
- {"CTRS" , 0, 4, 821, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 821, "RO", 0, 0, 1ull, 1ull},
- {"ARI" , 5, 1, 821, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OPS" , 6, 1, 821, "RO", 0, 0, 0ull, 0ull},
- {"ATOM32S" , 7, 1, 821, "RO", 0, 0, 0ull, 0ull},
- {"ATOM64S" , 8, 1, 821, "RO", 0, 0, 0ull, 0ull},
- {"ATOM128S" , 9, 1, 821, "RO", 0, 0, 0ull, 0ull},
- {"NOROPRPR" , 10, 1, 821, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 821, "RAZ", 1, 1, 0, 0},
- {"TPH" , 12, 2, 821, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 821, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 822, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 822, "R/W", 0, 0, 0ull, 0ull},
- {"ARI" , 5, 1, 822, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP" , 6, 1, 822, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP_EB" , 7, 1, 822, "RO", 0, 0, 0ull, 0ull},
- {"ID0_RQ" , 8, 1, 822, "RO", 0, 0, 0ull, 0ull},
- {"ID0_CP" , 9, 1, 822, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 822, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 823, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 823, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 823, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 823, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 824, "R/W", 1, 0, 0, 2ull},
- {"EC" , 4, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 824, "RO", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 824, "RO", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 824, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 824, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 824, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 824, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 824, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 825, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 825, "RO", 0, 0, 2ull, 2ull},
- {"NCO" , 20, 12, 825, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 826, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 826, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 826, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 826, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 827, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 827, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 827, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 827, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 828, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 828, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 828, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 828, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 828, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 828, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 828, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 828, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 828, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 829, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 829, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 829, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 830, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 830, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 830, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 830, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 830, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 831, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 831, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 831, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 831, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 831, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 831, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 832, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 833, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 834, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 835, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 836, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 836, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 837, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 838, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 838, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 838, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 838, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 838, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 838, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 839, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 839, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 839, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 839, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 839, "R/W", 0, 0, 3ull, 3ull},
- {"EASPML1" , 30, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 839, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 840, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 840, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 840, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 840, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 840, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 840, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 840, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 840, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 840, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 840, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_22_31" , 22, 10, 840, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 841, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 841, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 841, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 841, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 841, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 842, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 842, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 842, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 842, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 842, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 842, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 842, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 842, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 843, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 843, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 843, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 844, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 844, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 844, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 845, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 846, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 847, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 847, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 847, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 848, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 848, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 848, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 849, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 849, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 849, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 850, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 850, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 850, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 850, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 851, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 851, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 851, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 851, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 852, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 852, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 852, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 852, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 853, "RO/WRSL", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 853, "RO/WRSL", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 853, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 853, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 853, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 853, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 853, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 854, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"HEADER_CREDITS" , 12, 8, 854, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 854, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 854, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 854, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 855, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 855, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 855, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 855, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 855, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 856, "RO/WRSL", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 856, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 856, "RO/WRSL", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 856, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 857, "RO/WRSL", 0, 0, 136ull, 136ull},
- {"RESERVED_14_15" , 14, 2, 857, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 857, "RO/WRSL", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 857, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 858, "RO/WRSL", 0, 0, 679ull, 679ull},
- {"RESERVED_14_15" , 14, 2, 858, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 858, "RO/WRSL", 0, 0, 133ull, 133ull},
- {"RESERVED_26_31" , 26, 6, 858, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 859, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 859, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 859, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 860, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 861, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 862, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 862, "R/W", 0, 0, 145ull, 145ull},
- {"ISAE" , 0, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 863, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 863, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 863, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 863, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 863, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 863, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 863, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 863, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 863, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 863, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 863, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 863, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 863, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 863, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 863, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 863, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 863, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 863, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 864, "R/W", 0, 0, 0ull, 0ull},
- {"PI" , 8, 8, 864, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 864, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 864, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 865, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 865, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 865, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 865, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 865, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 866, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 867, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 868, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 868, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 868, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 868, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 869, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 869, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 869, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 869, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 869, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 869, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 869, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 869, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 869, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 869, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 869, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 869, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 869, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 869, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 869, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 869, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 869, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 870, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 870, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 870, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 870, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 871, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 871, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 871, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 871, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 871, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 871, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 872, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 873, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 874, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 874, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 875, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 875, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 876, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 877, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 877, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 877, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 877, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 877, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 877, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 877, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 877, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 877, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 877, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 877, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 877, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 877, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 877, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 877, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 878, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 878, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 878, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 878, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 878, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 878, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 878, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 878, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 878, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 878, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 879, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 879, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 879, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 879, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 879, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 879, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 879, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 879, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 879, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 879, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 879, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 879, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 880, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 880, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 880, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 880, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 880, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 880, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 881, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 881, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 882, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 883, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 883, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 884, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 884, "R/W", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 884, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 884, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 884, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 884, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 884, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 885, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 885, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 885, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 885, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 885, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 885, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 885, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 885, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 885, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 885, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 885, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 886, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 886, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 886, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 886, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 886, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 886, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 886, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 886, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 886, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 886, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 886, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 886, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 886, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 886, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 886, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 886, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 886, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 886, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 886, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 887, "R/W", 1, 1, 0, 0},
- {"MLW" , 4, 6, 887, "R/W", 0, 0, 8ull, 8ull},
- {"ASLPMS" , 10, 2, 887, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 887, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 887, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 887, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 887, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 887, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 887, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_23" , 22, 2, 887, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 887, "R/W", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 888, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 888, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 888, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 888, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 888, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 888, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 888, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 888, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 888, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 888, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 888, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 888, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 888, "RO", 1, 1, 0, 0},
- {"NLW" , 20, 6, 888, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 888, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 888, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 888, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 888, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 889, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 889, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 889, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 889, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 890, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 890, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 890, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 890, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 890, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 890, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 890, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 890, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 890, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 890, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 890, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 890, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 890, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 890, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 891, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 891, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 891, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 891, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 891, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 891, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 891, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 891, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 892, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 892, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 892, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 892, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 893, "RO", 0, 0, 0ull, 0ull},
- {"CTDS" , 4, 1, 893, "RO", 0, 0, 1ull, 1ull},
- {"ARI" , 5, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OPS" , 6, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"ATOM32S" , 7, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"ATOM64S" , 8, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"ATOM128S" , 9, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"NOROPRPR" , 10, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 893, "RAZ", 1, 1, 0, 0},
- {"TPH" , 12, 2, 893, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 893, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 894, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"ARI" , 5, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP" , 6, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP_EB" , 7, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"ID0_RQ" , 8, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"ID0_CP" , 9, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 894, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 895, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 895, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 895, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 895, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 896, "R/W", 1, 1, 0, 0},
- {"EC" , 4, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 896, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 896, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 896, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 896, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 896, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 897, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 898, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 899, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 899, "RO", 0, 0, 2ull, 2ull},
- {"NCO" , 20, 12, 899, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 900, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 900, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 900, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 900, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 901, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 901, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 901, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 901, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 902, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 902, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 902, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 902, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 902, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 902, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 902, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 902, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 903, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 903, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 903, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 903, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 903, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 903, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 903, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 903, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 903, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 904, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 904, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 904, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 905, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 905, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 905, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 905, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 906, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 907, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 908, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 909, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 910, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 910, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 910, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 910, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 911, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 911, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 911, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 911, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 911, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 911, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 911, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 911, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 911, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 912, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 912, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 913, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 913, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 914, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 915, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 915, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 915, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 915, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 915, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 915, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 916, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 916, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 916, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 916, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 916, "R/W", 0, 0, 3ull, 3ull},
- {"EASPML1" , 30, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 916, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 917, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 917, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 917, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 917, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 917, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_22_31" , 22, 10, 917, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 918, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 918, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 918, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 918, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 918, "R/W", 0, 0, 0ull, 0ull},
- {"NTSS" , 0, 4, 919, "R/W", 0, 0, 10ull, 10ull},
- {"RESERVED_4_7" , 4, 4, 919, "RO", 1, 1, 0, 0},
- {"NSKPS" , 8, 3, 919, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_11_13" , 11, 3, 919, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 919, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 919, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 919, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 919, "RO", 1, 1, 0, 0},
- {"SKPIV" , 0, 11, 920, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 920, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 920, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 921, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 921, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 921, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 922, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 923, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 924, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 924, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 924, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 925, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 925, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 925, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 926, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 926, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 926, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 927, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 927, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 927, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 927, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 928, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 928, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 928, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 928, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 929, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 929, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 929, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 929, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 930, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 930, "R/W", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 930, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 930, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 930, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 930, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 930, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 931, "R/W", 0, 0, 32ull, 32ull},
- {"HEADER_CREDITS" , 12, 8, 931, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 931, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 931, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 931, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 932, "R/W", 0, 0, 256ull, 256ull},
- {"HEADER_CREDITS" , 12, 8, 932, "R/W", 0, 0, 127ull, 127ull},
- {"RESERVED_20_20" , 20, 1, 932, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 932, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 932, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 933, "R/W", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 933, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 933, "R/W", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 933, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 934, "R/W", 0, 0, 136ull, 136ull},
- {"RESERVED_14_15" , 14, 2, 934, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 934, "R/W", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 934, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 935, "R/W", 0, 0, 679ull, 679ull},
- {"RESERVED_14_15" , 14, 2, 935, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 935, "R/W", 0, 0, 133ull, 133ull},
- {"RESERVED_26_31" , 26, 6, 935, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 936, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 936, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 936, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 936, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 936, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 936, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 936, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 937, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 938, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 939, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 939, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 939, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 939, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 939, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 939, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 939, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 939, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 939, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 940, "RO", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 940, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 940, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 940, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 940, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 940, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 941, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 941, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 941, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 941, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 941, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 941, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 941, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 941, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 941, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 942, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 942, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 942, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 942, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 942, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 942, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 943, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 12, 1, 943, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 943, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 12, 1, 944, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 944, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 945, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 945, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 946, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 946, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 946, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 946, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 947, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 947, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 947, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 947, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 947, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 947, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 947, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 947, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 948, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 948, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 948, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 948, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 948, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 948, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 948, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 948, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 948, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 948, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 948, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 948, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 948, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 949, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 949, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 949, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 949, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 949, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 949, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 949, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 949, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 950, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 950, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 950, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 950, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 950, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 950, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 950, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 951, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 951, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 951, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 952, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 952, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 952, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 952, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 952, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 952, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 952, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 952, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 953, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 953, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 953, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 953, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 953, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 953, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 953, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 954, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 954, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 954, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 954, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 955, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 955, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 955, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 955, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 955, "RAZ", 1, 1, 0, 0},
- {"L0SYNC" , 0, 1, 956, "RO", 0, 0, 0ull, 1ull},
- {"L1SYNC" , 1, 1, 956, "RO", 0, 0, 0ull, 1ull},
- {"L2SYNC" , 2, 1, 956, "RO", 0, 0, 0ull, 1ull},
- {"L3SYNC" , 3, 1, 956, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_4_10" , 4, 7, 956, "RAZ", 1, 1, 0, 0},
- {"PATTST" , 11, 1, 956, "RO", 0, 0, 0ull, 0ull},
- {"ALIGND" , 12, 1, 956, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_63" , 13, 51, 956, "RAZ", 1, 1, 0, 0},
- {"BIST_STATUS" , 0, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 957, "RAZ", 1, 1, 0, 0},
- {"BITLCK0" , 0, 1, 958, "RO", 0, 1, 0ull, 0},
- {"BITLCK1" , 1, 1, 958, "RO", 0, 1, 0ull, 0},
- {"BITLCK2" , 2, 1, 958, "RO", 0, 1, 0ull, 0},
- {"BITLCK3" , 3, 1, 958, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 958, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 959, "RAZ", 1, 1, 0, 0},
- {"SPD" , 2, 4, 959, "RO", 0, 0, 0ull, 0ull},
- {"SPDSEL0" , 6, 1, 959, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_10" , 7, 4, 959, "RAZ", 1, 1, 0, 0},
- {"LO_PWR" , 11, 1, 959, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 959, "RAZ", 1, 1, 0, 0},
- {"SPDSEL1" , 13, 1, 959, "RO", 0, 0, 1ull, 1ull},
- {"LOOPBCK1" , 14, 1, 959, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 959, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 959, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 960, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 960, "RAZ", 1, 1, 0, 0},
- {"TXFLT_EN" , 0, 1, 961, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 1, 1, 961, "R/W", 0, 0, 0ull, 1ull},
- {"RXSYNBAD_EN" , 2, 1, 961, "R/W", 0, 0, 0ull, 1ull},
- {"BITLCKLS_EN" , 3, 1, 961, "R/W", 0, 0, 0ull, 1ull},
- {"SYNLOS_EN" , 4, 1, 961, "R/W", 0, 0, 0ull, 1ull},
- {"ALGNLOS_EN" , 5, 1, 961, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 6, 1, 961, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 961, "RAZ", 1, 1, 0, 0},
- {"TXFLT" , 0, 1, 962, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 1, 1, 962, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXSYNBAD" , 2, 1, 962, "R/W1C", 0, 0, 0ull, 0ull},
- {"BITLCKLS" , 3, 1, 962, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNLOS" , 4, 1, 962, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALGNLOS" , 5, 1, 962, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 6, 1, 962, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 962, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 963, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 963, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 963, "R/W1C", 0, 0, 0ull, 0ull},
- {"DROP_LN" , 4, 2, 963, "R/W", 0, 0, 0ull, 0ull},
- {"ENC_MODE" , 6, 1, 963, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 963, "RAZ", 1, 1, 0, 0},
- {"GMXENO" , 0, 1, 964, "R/W", 0, 0, 0ull, 0ull},
- {"XAUI" , 1, 1, 964, "RO", 1, 1, 0, 0},
- {"RX_SWAP" , 2, 1, 964, "R/W", 0, 1, 0ull, 0},
- {"TX_SWAP" , 3, 1, 964, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 964, "RAZ", 1, 1, 0, 0},
- {"SYNC0ST" , 0, 4, 965, "RO", 0, 1, 0ull, 0},
- {"SYNC1ST" , 4, 4, 965, "RO", 0, 1, 0ull, 0},
- {"SYNC2ST" , 8, 4, 965, "RO", 0, 1, 0ull, 0},
- {"SYNC3ST" , 12, 4, 965, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 965, "RAZ", 1, 1, 0, 0},
- {"TENGB" , 0, 1, 966, "RO", 0, 0, 1ull, 1ull},
- {"TENPASST" , 1, 1, 966, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 966, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 967, "RAZ", 1, 1, 0, 0},
- {"LPABLE" , 1, 1, 967, "RO", 0, 0, 1ull, 1ull},
- {"RCV_LNK" , 2, 1, 967, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_3_6" , 3, 4, 967, "RAZ", 1, 1, 0, 0},
- {"FLT" , 7, 1, 967, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 967, "RAZ", 1, 1, 0, 0},
- {"TENGB_R" , 0, 1, 968, "RO", 0, 0, 0ull, 0ull},
- {"TENGB_X" , 1, 1, 968, "RO", 0, 0, 1ull, 1ull},
- {"TENGB_W" , 2, 1, 968, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_9" , 3, 7, 968, "RAZ", 1, 1, 0, 0},
- {"RCVFLT" , 10, 1, 968, "RC", 0, 0, 0ull, 0ull},
- {"XMTFLT" , 11, 1, 968, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 968, "RAZ", 1, 1, 0, 0},
- {"DEV" , 14, 2, 968, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_16_63" , 16, 48, 968, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 969, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 969, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_TXPLRT" , 2, 4, 969, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_RXPLRT" , 6, 4, 969, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 969, "RAZ", 1, 1, 0, 0},
- {"TX_ST" , 0, 3, 970, "RO", 0, 1, 0ull, 0},
- {"RX_ST" , 3, 2, 970, "RO", 0, 1, 0ull, 0},
- {"ALGN_ST" , 5, 3, 970, "RO", 0, 1, 0ull, 0},
- {"RXBAD" , 8, 1, 970, "RO", 0, 0, 0ull, 0ull},
- {"SYN0BAD" , 9, 1, 970, "RO", 0, 0, 0ull, 0ull},
- {"SYN1BAD" , 10, 1, 970, "RO", 0, 0, 0ull, 0ull},
- {"SYN2BAD" , 11, 1, 970, "RO", 0, 0, 0ull, 0ull},
- {"SYN3BAD" , 12, 1, 970, "RO", 0, 0, 0ull, 0ull},
- {"TERM_ERR" , 13, 1, 970, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 970, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 971, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 971, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 971, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 16, 971, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 971, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 972, "RAZ", 1, 1, 0, 0},
- {"MASK" , 3, 35, 972, "R/W", 0, 0, 34359738367ull, 34359738367ull},
- {"RESERVED_38_63" , 38, 26, 972, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 973, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 973, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 973, "R/W", 0, 0, 0ull, 1ull},
- {"BAR1_SIZ" , 4, 3, 973, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_7_63" , 7, 57, 973, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 974, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 974, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 974, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 3, 1, 974, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 4, 1, 974, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 5, 1, 974, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 6, 1, 974, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 7, 1, 974, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 974, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 975, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 975, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 975, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 975, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 975, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 975, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 6, 1, 975, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 7, 1, 975, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 8, 1, 975, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 9, 1, 975, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 975, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 976, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 976, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 977, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 977, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 978, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 978, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"FAST_LM" , 2, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 979, "R/W", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 979, "RAZ", 0, 0, 0ull, 0ull},
- {"CFG_RTRY" , 16, 16, 979, "R/W", 0, 0, 0ull, 32ull},
- {"RESERVED_32_33" , 32, 2, 979, "RAZ", 1, 1, 0, 0},
- {"PBUS" , 34, 8, 979, "RO", 1, 1, 0, 0},
- {"DNUM" , 42, 5, 979, "RO", 1, 1, 0, 0},
- {"AUTO_SD" , 47, 1, 979, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 979, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 980, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 980, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 981, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 981, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 982, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 982, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 982, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 982, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 982, "RO", 1, 1, 0, 0},
- {"AERI" , 0, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 983, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 983, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 984, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 984, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 985, "RO", 0, 0, 0ull, 0ull},
- {"SE" , 1, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"PMEI" , 2, 1, 985, "RO", 0, 0, 0ull, 0ull},
- {"PMEM" , 3, 1, 985, "RO", 0, 0, 0ull, 0ull},
- {"UP_B1" , 4, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_B2" , 5, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_BX" , 6, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B1" , 7, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B2" , 8, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_BX" , 9, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"EXC" , 10, 1, 985, "RO", 0, 0, 0ull, 0ull},
- {"RDLK" , 11, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_ER" , 12, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_DR" , 13, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 985, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 986, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 986, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 987, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 987, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_40" , 0, 41, 988, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 41, 23, 988, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 989, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 989, "R/W", 0, 1, 4503599627370495ull, 0},
- {"RESERVED_0_11" , 0, 12, 990, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 990, "R/W", 0, 1, 4503599627370495ull, 0},
- {"SLI_P" , 0, 8, 991, "R/W", 0, 0, 128ull, 128ull},
- {"SLI_NP" , 8, 8, 991, "R/W", 0, 0, 16ull, 16ull},
- {"SLI_CPL" , 16, 8, 991, "R/W", 0, 0, 128ull, 128ull},
- {"PEM_P" , 24, 8, 991, "R/W", 0, 0, 128ull, 128ull},
- {"PEM_NP" , 32, 8, 991, "R/W", 0, 0, 16ull, 16ull},
- {"PEM_CPL" , 40, 8, 991, "R/W", 0, 0, 128ull, 128ull},
- {"PEAI_PPF" , 48, 8, 991, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_56_63" , 56, 8, 991, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 992, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 992, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 992, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 992, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 992, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 20, 993, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 993, "RAZ", 1, 1, 0, 0},
- {"CLKEN" , 0, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 994, "RAZ", 0, 1, 0ull, 0},
- {"DPRT" , 0, 16, 995, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 995, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 995, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 995, "RAZ", 1, 1, 0, 0},
- {"MAP0" , 0, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MAP0" , 0, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 997, "R/W", 0, 0, 0ull, 0ull},
- {"MINLEN" , 0, 16, 998, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 998, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 998, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 999, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 999, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 999, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 999, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 999, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 999, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 999, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 999, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 1000, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 1000, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 1000, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 1000, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 1000, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 1000, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 1000, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 1000, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 1000, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 1000, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 1000, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 1000, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 1000, "RAZ", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SID" , 24, 1, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SCMD" , 25, 1, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_TVID" , 26, 1, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"IHMSK_DIS" , 27, 1, 1000, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 1000, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 1001, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 1001, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 1002, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 1002, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 1003, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1003, "RAZ", 1, 1, 0, 0},
- {"VLAN2_QOS" , 0, 3, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1004, "RAZ", 1, 1, 0, 0},
- {"HG2_QOS" , 4, 3, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 1004, "RAZ", 1, 1, 0, 0},
- {"DIFF2_QOS" , 8, 3, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 1004, "RAZ", 1, 1, 0, 0},
- {"VLAN2_BPID" , 16, 6, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1004, "RAZ", 1, 1, 0, 0},
- {"HG2_BPID" , 24, 6, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 1004, "RAZ", 1, 1, 0, 0},
- {"DIFF2_BPID" , 32, 6, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 1004, "RAZ", 1, 1, 0, 0},
- {"VLAN2_PADD" , 40, 8, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"HG2_PADD" , 48, 8, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"DIFF2_PADD" , 56, 8, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"SKIP" , 0, 7, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 1005, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_EN" , 10, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"HIGIG_EN" , 11, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"CRC_EN" , 12, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 1005, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 1005, "RAZ", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"HG_QOS" , 27, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT" , 28, 4, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 1005, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 1005, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 1005, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 1005, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_CHK_SEL" , 53, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"IH_PRI" , 54, 1, 1005, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 1005, "RAZ", 1, 1, 0, 0},
- {"BPID" , 0, 6, 1006, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_15" , 6, 10, 1006, "RAZ", 1, 1, 0, 0},
- {"BASE" , 16, 8, 1006, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 1006, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_MSB" , 40, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_42_43" , 42, 2, 1007, "RAZ", 1, 1, 0, 0},
- {"GRPTAGMASK_MSB" , 44, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_47" , 46, 2, 1007, "RAZ", 1, 1, 0, 0},
- {"GRPTAGBASE_MSB" , 48, 2, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 1007, "RAZ", 1, 1, 0, 0},
- {"INC_HWCHK" , 52, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"PORTADD_EN" , 53, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 1007, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 1008, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 1008, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 1008, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 1008, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 1008, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 6, 1008, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 1008, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 1008, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1008, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 1009, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 1009, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 1010, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1010, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 1011, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 1011, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 1012, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 1012, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 1013, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 1013, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 1014, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 1014, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 1015, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 1015, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 1016, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 1016, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 1017, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 1017, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 1018, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 1018, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 1019, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 1019, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 1020, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 1020, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 1021, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 1021, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 1022, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 1022, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 1023, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_7" , 1, 7, 1023, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 1, 1023, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 1023, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 1024, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1024, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 1025, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 1025, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 1026, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1026, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 64, 1027, "R/W", 0, 0, 18446744073709551615ull, 18446744073709551615ull},
- {"EN" , 0, 8, 1028, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1028, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1029, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1029, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 1030, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 1030, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1030, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 1031, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 1031, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 1031, "RO", 1, 1, 0, 0},
- {"COUNT" , 0, 32, 1032, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 1032, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 1033, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 1033, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 1034, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 1034, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 1034, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 1034, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 1035, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 1035, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 1035, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 1035, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 1035, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 1036, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 1036, "RO", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 1036, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 1036, "RO", 1, 1, 0, 0},
- {"MOD" , 0, 3, 1037, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 1037, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 1037, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 1037, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 1037, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 1037, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 1037, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 1037, "RO", 1, 1, 0, 0},
- {"STATE" , 0, 64, 1038, "RO", 1, 1, 0, 0},
- {"STATE" , 0, 64, 1039, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1040, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 1040, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 1040, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 1040, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 1040, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 1041, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 1042, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 1042, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 1042, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 1042, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 1042, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 1042, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 1042, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 1042, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 1042, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 1042, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 1042, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 1042, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 1042, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 1043, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 1043, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 1043, "RO", 1, 0, 0, 0ull},
- {"MAJOR_3" , 54, 1, 1043, "RO", 1, 0, 0, 0ull},
- {"PTP" , 55, 1, 1043, "RO", 1, 0, 0, 0ull},
- {"UID_2" , 56, 1, 1043, "RO", 1, 0, 0, 0ull},
- {"RESERVED_57_63" , 57, 7, 1043, "RO", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 1044, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 1044, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 1044, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 1044, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 1044, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 1044, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 1044, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 1044, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 1044, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 1044, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 1044, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 1044, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 1044, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 7, 1045, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 7, 7, 1045, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 14, 33, 1045, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 47, 13, 1045, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 60, 1, 1045, "RO", 1, 0, 0, 0ull},
- {"QOS" , 61, 3, 1045, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 5, 1046, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 5, 1, 1046, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 6, 1, 1046, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 7, 1, 1046, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 8, 1, 1046, "RO", 1, 0, 0, 0ull},
- {"RESERVED_9_15" , 9, 7, 1046, "RO", 1, 1, 0, 0},
- {"DOORBELL" , 16, 20, 1046, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 36, 1, 1046, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 1046, "RO", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 1047, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 1047, "RO", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 1047, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 1047, "RO", 1, 1, 0, 0},
- {"IPID" , 0, 7, 1048, "R/W", 1, 1, 0, 0},
- {"RESERVED_7_7" , 7, 1, 1048, "RAZ", 1, 1, 0, 0},
- {"EID" , 8, 5, 1048, "R/W", 1, 1, 0, 0},
- {"RESERVED_13_15" , 13, 3, 1048, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 5, 1048, "R/W", 1, 1, 0, 0},
- {"RESERVED_21_23" , 21, 3, 1048, "RAZ", 1, 1, 0, 0},
- {"PIPE" , 24, 7, 1048, "R/W", 1, 1, 0, 0},
- {"RESERVED_31_49" , 31, 19, 1048, "RAZ", 1, 1, 0, 0},
- {"MIN_PKT" , 50, 3, 1048, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 1048, "R/W", 1, 1, 0, 0},
- {"STATIC_P" , 61, 1, 1048, "R/W", 1, 0, 0, 0ull},
- {"CRC" , 62, 1, 1048, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_63_63" , 63, 1, 1048, "R/W", 1, 0, 0, 0ull},
- {"IPID" , 0, 7, 1049, "R/W", 1, 1, 0, 0},
- {"RESERVED_7_7" , 7, 1, 1049, "RAZ", 1, 1, 0, 0},
- {"EID" , 8, 5, 1049, "R/W", 1, 1, 0, 0},
- {"RESERVED_13_52" , 13, 40, 1049, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 1049, "R/W", 1, 1, 0, 0},
- {"RESERVED_61_63" , 61, 3, 1049, "RAZ", 1, 1, 0, 0},
- {"QID" , 0, 8, 1050, "R/W", 1, 0, 0, 0ull},
- {"IPID" , 8, 7, 1050, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_15_15" , 15, 1, 1050, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 16, 5, 1050, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 21, 1, 1050, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 22, 31, 1050, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 1050, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 1050, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 1050, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 1050, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 8, 1051, "R/W", 1, 0, 0, 0ull},
- {"IPID" , 8, 7, 1051, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_15_52" , 15, 38, 1051, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 1051, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 1051, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 7, 1052, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1052, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 1052, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 1052, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 1052, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 7, 1053, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1053, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 1053, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 1053, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 5, 1054, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_5_7" , 5, 3, 1054, "RAZ", 1, 1, 0, 0},
- {"PACKET" , 8, 6, 1054, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_14_31" , 14, 18, 1054, "RAZ", 1, 1, 0, 0},
- {"WORD" , 32, 15, 1054, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_47_63" , 47, 17, 1054, "RAZ", 1, 1, 0, 0},
- {"PIPE" , 0, 7, 1055, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1055, "RAZ", 1, 1, 0, 0},
- {"PACKET" , 8, 6, 1055, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_14_31" , 14, 18, 1055, "RAZ", 1, 1, 0, 0},
- {"WORD" , 32, 15, 1055, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_47_63" , 47, 17, 1055, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 1056, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 1056, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 1056, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 1056, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 1056, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 1056, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 6, 1056, "RO", 1, 0, 0, 0ull},
- {"RESERVED_21_21" , 21, 1, 1056, "RAZ", 1, 1, 0, 0},
- {"PRT_PSB7" , 22, 1, 1056, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 1056, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 1056, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 1056, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 1056, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 2, 1056, "RO", 1, 0, 0, 0ull},
- {"RESERVED_31_31" , 31, 1, 1056, "RAZ", 1, 1, 0, 0},
- {"OUT_DAT" , 32, 1, 1056, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 1056, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 1056, "RO", 1, 0, 0, 0ull},
- {"RESERVED_35_63" , 35, 29, 1056, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 1057, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 1057, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 1057, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 1057, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 1058, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 1059, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 1060, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 1061, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 1062, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE1" , 4, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE2" , 8, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE3" , 12, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE4" , 16, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE5" , 20, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE6" , 24, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE7" , 28, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE8" , 32, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE9" , 36, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE10" , 40, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE11" , 44, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE12" , 48, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE13" , 52, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE14" , 56, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE15" , 60, 4, 1063, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE16" , 0, 4, 1064, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE17" , 4, 4, 1064, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE18" , 8, 4, 1064, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE19" , 12, 4, 1064, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_16_63" , 16, 48, 1064, "RAZ", 1, 1, 0, 0},
- {"ENGINE0" , 0, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE1" , 4, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE2" , 8, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE3" , 12, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE4" , 16, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE5" , 20, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE6" , 24, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE7" , 28, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE8" , 32, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE9" , 36, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE10" , 40, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE11" , 44, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE12" , 48, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE13" , 52, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE14" , 56, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE15" , 60, 4, 1065, "R/W", 0, 0, 1ull, 1ull},
- {"MASK" , 0, 20, 1066, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1066, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 1067, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 1067, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 1067, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOOPBACK" , 3, 1, 1067, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1067, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 1068, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 1068, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 1068, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 1068, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA_THROTTLE" , 4, 1, 1068, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_PERF0" , 5, 1, 1068, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_PERF1" , 6, 1, 1068, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 1068, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 1069, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 1069, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 1069, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBACK" , 3, 1, 1069, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1069, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1070, "RAZ", 1, 1, 0, 0},
- {"BPID0" , 4, 6, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1070, "RAZ", 1, 1, 0, 0},
- {"BPID1" , 11, 6, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_17" , 17, 1, 1070, "RAZ", 1, 1, 0, 0},
- {"BPID2" , 18, 6, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_24" , 24, 1, 1070, "RAZ", 1, 1, 0, 0},
- {"BPID3" , 25, 6, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1070, "RAZ", 1, 1, 0, 0},
- {"BPID4" , 32, 6, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_38" , 38, 1, 1070, "RAZ", 1, 1, 0, 0},
- {"BPID5" , 39, 6, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_45" , 45, 1, 1070, "RAZ", 1, 1, 0, 0},
- {"BPID6" , 46, 6, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_52_52" , 52, 1, 1070, "RAZ", 1, 1, 0, 0},
- {"BPID7" , 53, 6, 1070, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 1070, "RAZ", 1, 1, 0, 0},
- {"NUM_PORTS" , 0, 4, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"PKIND0" , 4, 6, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1071, "RAZ", 1, 1, 0, 0},
- {"PKIND1" , 11, 6, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_17" , 17, 1, 1071, "RAZ", 1, 1, 0, 0},
- {"PKIND2" , 18, 6, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_24" , 24, 1, 1071, "RAZ", 1, 1, 0, 0},
- {"PKIND3" , 25, 6, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1071, "RAZ", 1, 1, 0, 0},
- {"PKIND4" , 32, 6, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_38" , 38, 1, 1071, "RAZ", 1, 1, 0, 0},
- {"PKIND5" , 39, 6, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_45" , 45, 1, 1071, "RAZ", 1, 1, 0, 0},
- {"PKIND6" , 46, 6, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_52_52" , 52, 1, 1071, "RAZ", 1, 1, 0, 0},
- {"PKIND7" , 53, 6, 1071, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 1071, "RAZ", 1, 1, 0, 0},
- {"SIZE0" , 0, 8, 1072, "RO", 0, 0, 0ull, 0ull},
- {"SIZE1" , 8, 8, 1072, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE2" , 16, 8, 1072, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE3" , 24, 8, 1072, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE4" , 32, 8, 1072, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE5" , 40, 8, 1072, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE6" , 48, 8, 1072, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE7" , 56, 8, 1072, "R/W", 0, 0, 0ull, 0ull},
- {"MIN_SIZE" , 0, 16, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1073, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1074, "RAZ", 1, 1, 0, 0},
- {"PREEMPTER" , 0, 1, 1075, "R/W", 0, 0, 0ull, 0ull},
- {"PREEMPTEE" , 1, 1, 1075, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1075, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1076, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 1076, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1076, "RAZ", 1, 1, 0, 0},
- {"INT_MASK" , 0, 32, 1077, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1077, "RAZ", 0, 0, 0ull, 0ull},
- {"WQE_WORD" , 0, 4, 1078, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_4_63" , 4, 60, 1078, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 1079, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 1080, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 1081, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 1082, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 1082, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 1082, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 1082, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 1082, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1083, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 1083, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 1083, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 1083, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 1083, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 1084, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 1084, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 1084, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 1085, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 1085, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 1085, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 1085, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 1085, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 1085, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 1085, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 1085, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 1085, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 1085, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 1086, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1087, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 1087, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 1087, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1088, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 1088, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 1088, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 1088, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 1088, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 1088, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 1088, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 1089, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 1089, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 1090, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 1091, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 1092, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 1093, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 1093, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 1093, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 1093, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 1093, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 1093, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 1093, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 1093, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 1093, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 1093, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 1093, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 1093, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 1093, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 1093, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 1093, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 1093, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 1093, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 1093, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1094, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 1094, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 1094, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 1095, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 1095, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1096, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 1096, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 1096, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1097, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 1097, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 1097, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 1097, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 1097, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 1097, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 1097, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1098, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1098, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1099, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1099, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 1100, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 1100, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 1101, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 1101, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1101, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 1102, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 1102, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1102, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 1103, "R/W", 0, 0, 0ull, 0ull},
- {"EER_VAL" , 9, 1, 1103, "RO", 0, 0, 0ull, 0ull},
- {"EER_LCK" , 10, 1, 1103, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 1103, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 1104, "RO", 1, 1, 0, 0},
- {"KEY" , 0, 64, 1105, "WO", 0, 0, 0ull, 0ull},
- {"DAT" , 0, 64, 1106, "RO", 1, 1, 0, 0},
- {"NCB_CMD" , 0, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_0" , 2, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_1" , 3, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_0" , 4, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_1" , 5, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 1107, "RAZ", 1, 1, 0, 0},
- {"P2N1_P1" , 9, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_24" , 19, 6, 1107, "RAZ", 1, 1, 0, 0},
- {"CPL_P1" , 25, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_O" , 27, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_C" , 28, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_O" , 29, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"NCB_REQ" , 31, 1, 1107, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1107, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_4" , 1, 4, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"PTLP_RO" , 5, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 1108, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 1108, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 1108, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 1108, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 1108, "R/W", 0, 0, 3ull, 3ull},
- {"WAITL_COM" , 16, 1, 1108, "R/W", 0, 1, 0ull, 0},
- {"DIS_PORT" , 17, 1, 1108, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTA" , 18, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 19, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 20, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 21, 1, 1108, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 1108, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 1109, "RO", 1, 1, 0, 0},
- {"P0_NTAGS" , 8, 6, 1109, "R/W", 0, 0, 32ull, 32ull},
- {"P1_NTAGS" , 14, 6, 1109, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_63" , 20, 44, 1109, "RAZ", 1, 1, 0, 0},
- {"P0_FCNT" , 0, 6, 1110, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 1110, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 1110, "RO", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 1110, "RO", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 1110, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 1111, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 1111, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 1111, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 32, 1112, "R/W", 0, 1, 0ull, 0},
- {"ADBG_SEL" , 32, 1, 1112, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 1112, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1113, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1113, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1114, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 1114, "R/W", 0, 1, 0ull, 0},
- {"TIM" , 0, 32, 1115, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1115, "RAZ", 1, 1, 0, 0},
- {"RML_TO" , 0, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 1116, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"PIPE_ERR" , 61, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT1" , 17, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"MAC0_INT" , 18, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"MAC1_INT" , 19, 1, 1117, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_31" , 20, 12, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"PIPE_ERR" , 61, 1, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 1117, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT" , 4, 1, 1118, "RO", 0, 0, 0ull, 0ull},
- {"PTIME" , 5, 1, 1118, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_WI" , 9, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_B0" , 10, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_WI" , 11, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_B0" , 12, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_WI" , 13, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_B0" , 14, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_WI" , 15, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO_INT0" , 16, 1, 1118, "RO", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 1118, "RO", 0, 0, 0ull, 0ull},
- {"MAC0_INT" , 18, 1, 1118, "RO", 0, 0, 0ull, 0ull},
- {"MAC1_INT" , 19, 1, 1118, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 1118, "RAZ", 1, 1, 0, 0},
- {"DMAFI" , 32, 2, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 1118, "RO", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 1118, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 1118, "RAZ", 1, 1, 0, 0},
- {"PIDBOF" , 48, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 1118, "RAZ", 1, 1, 0, 0},
- {"PGL_ERR" , 52, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 1118, "RAZ", 1, 1, 0, 0},
- {"ILL_PAD" , 60, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIPE_ERR" , 61, 1, 1118, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 1118, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 1119, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 1120, "RO", 0, 1, 0ull, 0},
- {"P0_PCNT" , 0, 8, 1121, "R/W", 0, 0, 128ull, 128ull},
- {"P0_NCNT" , 8, 8, 1121, "R/W", 0, 0, 16ull, 16ull},
- {"P0_CCNT" , 16, 8, 1121, "R/W", 0, 0, 128ull, 128ull},
- {"P1_PCNT" , 24, 8, 1121, "R/W", 0, 0, 128ull, 128ull},
- {"P1_NCNT" , 32, 8, 1121, "R/W", 0, 0, 16ull, 16ull},
- {"P1_CCNT" , 40, 8, 1121, "R/W", 0, 0, 128ull, 128ull},
- {"P0_P_D" , 48, 1, 1121, "R/W", 0, 0, 1ull, 1ull},
- {"P0_N_D" , 49, 1, 1121, "R/W", 0, 0, 1ull, 1ull},
- {"P0_C_D" , 50, 1, 1121, "R/W", 0, 0, 1ull, 1ull},
- {"P1_P_D" , 51, 1, 1121, "R/W", 0, 0, 1ull, 1ull},
- {"P1_N_D" , 52, 1, 1121, "R/W", 0, 0, 1ull, 1ull},
- {"P1_C_D" , 53, 1, 1121, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_54_63" , 54, 10, 1121, "RAZ", 1, 1, 0, 0},
- {"NUM" , 0, 8, 1122, "RO", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 1122, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 1123, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 1123, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 1123, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"BA" , 2, 28, 1124, "R/W", 0, 1, 0ull, 0},
- {"RTYPE" , 30, 2, 1124, "R/W", 0, 1, 0ull, 0},
- {"WTYPE" , 32, 2, 1124, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 1124, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 1124, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 3, 1124, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 42, 1, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 1124, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 1125, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 1126, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 1127, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 1128, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 1129, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 1130, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 1131, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 1132, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 1133, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 1133, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1133, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 64, 1134, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 1135, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1140, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1141, "R/W", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 1142, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 1142, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1142, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 1143, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 1143, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1144, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 1144, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1144, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 1145, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 1145, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 1145, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 1146, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 1146, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1146, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1147, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 32, 22, 1147, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 1147, "RO", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 1148, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 1148, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 1149, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 1149, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 1150, "R/W", 0, 1, 0ull, 0},
- {"FCNT" , 32, 5, 1150, "RO", 0, 1, 0ull, 0},
- {"WRP" , 37, 9, 1150, "RO", 0, 1, 0ull, 0},
- {"RRP" , 46, 9, 1150, "RO", 0, 1, 0ull, 0},
- {"MAX" , 55, 9, 1150, "RO", 0, 1, 16ull, 0},
- {"NTAG" , 0, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"NTT" , 1, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"NGRP" , 2, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"NQOS" , 3, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_5" , 4, 2, 1151, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 1151, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_13" , 13, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 1151, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_20" , 16, 5, 1151, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"RNTAG" , 22, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"RNTT" , 23, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"RNGRP" , 24, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"RNQOS" , 25, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_27" , 26, 2, 1151, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 1151, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_35" , 35, 1, 1151, "RAZ", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 1151, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_42" , 38, 5, 1151, "RAZ", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 1151, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 1151, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 1152, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 16, 7, 1152, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 1152, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1153, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 4, 60, 1153, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 1154, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 1154, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 1155, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1155, "RO", 0, 1, 0ull, 0},
- {"PORT" , 0, 32, 1156, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1156, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1157, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1157, "RAZ", 1, 1, 0, 0},
- {"PKT_BP" , 0, 4, 1158, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 4, 1, 1158, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1158, "RAZ", 1, 1, 0, 0},
- {"ES" , 0, 64, 1159, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 1160, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1160, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 1161, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1161, "RAZ", 1, 1, 0, 0},
- {"DPTR" , 0, 32, 1162, "R/W", 0, 0, 0ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 1162, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1163, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1163, "RO", 0, 1, 0ull, 0},
- {"RD_CNT" , 0, 32, 1164, "RO", 0, 1, 0ull, 0},
- {"WR_CNT" , 32, 32, 1164, "RO", 0, 1, 0ull, 0},
- {"PP" , 0, 64, 1165, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 0, 1, 1166, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 1166, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 1166, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 1166, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 1166, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 1166, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 1166, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 1166, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 22, 1, 1166, "R/W", 0, 0, 0ull, 1ull},
- {"PIN_RST" , 23, 1, 1166, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_39" , 24, 16, 1166, "RAZ", 1, 1, 0, 0},
- {"PRC_IDLE" , 40, 1, 1166, "RO", 0, 1, 0ull, 0},
- {"RESERVED_41_47" , 41, 7, 1166, "RAZ", 1, 1, 0, 0},
- {"GII_RDS" , 48, 7, 1166, "RO", 0, 1, 0ull, 0},
- {"GII_ERST" , 55, 1, 1166, "RO", 0, 1, 0ull, 0},
- {"PRD_RDS" , 56, 7, 1166, "RO", 0, 1, 0ull, 0},
- {"PRD_ERST" , 63, 1, 1166, "RO", 0, 1, 0ull, 0},
- {"ENB" , 0, 32, 1167, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1167, "RAZ", 1, 1, 0, 0},
- {"RDSIZE" , 0, 64, 1168, "R/W", 0, 1, 0ull, 0},
- {"IS_64B" , 0, 32, 1169, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1169, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1170, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 22, 1170, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_63" , 54, 10, 1170, "RAZ", 1, 1, 0, 0},
- {"IPTR" , 0, 32, 1171, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1171, "RAZ", 1, 1, 0, 0},
- {"BMODE" , 0, 32, 1172, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1172, "RAZ", 1, 1, 0, 0},
- {"BP_EN" , 0, 32, 1173, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 1173, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 1174, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1174, "RAZ", 1, 1, 0, 0},
- {"WMARK" , 0, 32, 1175, "R/W", 0, 0, 0ull, 14ull},
- {"RESERVED_32_63" , 32, 32, 1175, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 64, 1176, "R/W", 0, 1, 0ull, 0},
- {"OUT_RST" , 0, 32, 1177, "RO", 0, 1, 0ull, 0},
- {"IN_RST" , 32, 32, 1177, "RO", 0, 1, 0ull, 0},
- {"ES" , 0, 64, 1178, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 1179, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1179, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 1180, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1180, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1181, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1181, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1182, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1182, "RAZ", 1, 1, 0, 0},
- {"PKIND" , 0, 6, 1183, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 1183, "RAZ", 1, 1, 0, 0},
- {"BPKIND" , 8, 6, 1183, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 1183, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 3, 1184, "R/W", 0, 0, 2ull, 2ull},
- {"BAR0_D" , 3, 1, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"WIND_D" , 4, 1, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1184, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 1185, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 1186, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 1187, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 1187, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 1187, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 1187, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 1188, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 1188, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 1188, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 1188, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 1188, "RO", 0, 1, 1ull, 0},
- {"RESERVED_47_47" , 47, 1, 1188, "RAZ", 1, 1, 0, 0},
- {"NNP1" , 48, 8, 1188, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 1188, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 1189, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 1189, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 1189, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 1189, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 1189, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 7, 1190, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 1190, "RAZ", 1, 1, 0, 0},
- {"NUMP" , 16, 8, 1190, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 1190, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 1191, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 1191, "R/W", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 1191, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_51_63" , 51, 13, 1191, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 1192, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 1193, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 1193, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 1193, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 1193, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 1194, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 1195, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1195, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 1196, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 1196, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 1197, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 1197, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 1197, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 1197, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 1197, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1197, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 1198, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1198, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 1198, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 1198, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 1198, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1198, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1199, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1199, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 1200, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 1200, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 1200, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1200, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 1201, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 1201, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 1201, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1201, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 1202, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_6_7" , 6, 2, 1202, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 6, 1202, "R/W", 0, 0, 19ull, 19ull},
- {"RESERVED_14_63" , 14, 50, 1202, "RAZ", 1, 1, 0, 0},
- {"OTH" , 0, 2, 1203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 1203, "RAZ", 1, 1, 0, 0},
- {"PEND" , 8, 2, 1203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 1203, "RAZ", 1, 1, 0, 0},
- {"FIDX" , 16, 1, 1203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 1203, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 20, 1, 1203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 1203, "RAZ", 1, 1, 0, 0},
- {"NCBO" , 24, 4, 1203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_30" , 28, 3, 1203, "RAZ", 1, 1, 0, 0},
- {"SOC" , 31, 1, 1203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_33" , 32, 2, 1203, "RAZ", 1, 1, 0, 0},
- {"RWI_DAT" , 34, 1, 1203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_41" , 35, 7, 1203, "RAZ", 1, 1, 0, 0},
- {"RWO" , 42, 2, 1203, "RO", 0, 0, 0ull, 0ull},
- {"RWO_DAT" , 44, 1, 1203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_51" , 45, 7, 1203, "RAZ", 1, 1, 0, 0},
- {"FPTR" , 52, 2, 1203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 1203, "RAZ", 1, 1, 0, 0},
- {"RWEN" , 0, 1, 1204, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 1, 1, 1204, "R/W", 0, 0, 0ull, 0ull},
- {"LDT" , 2, 1, 1204, "R/W", 0, 0, 1ull, 1ull},
- {"STT" , 3, 1, 1204, "R/W", 0, 0, 1ull, 1ull},
- {"RWQ_BYP_DIS" , 4, 1, 1204, "R/W", 0, 0, 0ull, 0ull},
- {"RWIO_BYP_DIS" , 5, 1, 1204, "R/W", 0, 0, 0ull, 0ull},
- {"WFE_THR" , 6, 1, 1204, "R/W", 0, 0, 0ull, 0ull},
- {"RWO_FLUSH" , 7, 1, 1204, "WR0", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1204, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 64, 1205, "R/W", 0, 1, 0ull, 0},
- {"FIDX_SBE" , 0, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"FIDX_DBE" , 1, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"IDX_SBE" , 2, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"IDX_DBE" , 3, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"OTH_SBE1" , 4, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"OTH_DBE1" , 5, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"OTH_SBE0" , 6, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"OTH_DBE0" , 7, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"PND_SBE1" , 8, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"PND_DBE1" , 9, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"PND_SBE0" , 10, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"PND_DBE0" , 11, 1, 1206, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_12_31" , 12, 20, 1206, "RAZ", 1, 1, 0, 0},
- {"IOP" , 32, 11, 1206, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_43_44" , 43, 2, 1206, "RAZ", 1, 1, 0, 0},
- {"FPE" , 45, 1, 1206, "R/W1C", 0, 0, 0ull, 0ull},
- {"AWE" , 46, 1, 1206, "R/W1C", 0, 0, 0ull, 0ull},
- {"BFP" , 47, 1, 1206, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1206, "RAZ", 1, 1, 0, 0},
- {"FIDX_SBE_IE" , 0, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"FIDX_DBE_IE" , 1, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"IDX_SBE_IE" , 2, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"IDX_DBE_IE" , 3, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"OTH_SBE1_IE" , 4, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"OTH_DBE1_IE" , 5, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"OTH_SBE0_IE" , 6, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"OTH_DBE0_IE" , 7, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"PND_SBE1_IE" , 8, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"PND_DBE1_IE" , 9, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"PND_SBE0_IE" , 10, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"PND_DBE0_IE" , 11, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_31" , 12, 20, 1207, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 11, 1207, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_44" , 43, 2, 1207, "RAZ", 1, 1, 0, 0},
- {"FPE_IE" , 45, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"AWE_IE" , 46, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"BFP_IE" , 47, 1, 1207, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 1207, "RAZ", 1, 1, 0, 0},
- {"ECC_ENA" , 0, 1, 1208, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND" , 1, 2, 1208, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1208, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1209, "RAZ", 1, 1, 0, 0},
- {"SYNDROM" , 4, 5, 1209, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 1209, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 16, 11, 1209, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 1209, "RAZ", 1, 1, 0, 0},
- {"FPAGE_CNT" , 0, 32, 1210, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1210, "RAZ", 1, 1, 0, 0},
- {"GWE_DIS" , 0, 1, 1211, "R/W", 0, 0, 0ull, 0ull},
- {"GWE_RAH" , 1, 1, 1211, "R/W", 0, 0, 0ull, 0ull},
- {"GWE_FPOR" , 2, 1, 1211, "R/W", 0, 0, 0ull, 0ull},
- {"GWE_POE" , 3, 1, 1211, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1211, "RAZ", 1, 1, 0, 0},
- {"ECC_ENA" , 0, 1, 1212, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND" , 1, 2, 1212, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1212, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1213, "RAZ", 1, 1, 0, 0},
- {"SYNDROM" , 4, 5, 1213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 1213, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 16, 11, 1213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 1213, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 1214, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1214, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 1215, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1215, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 1216, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 1216, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 1217, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 1217, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 1218, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 1218, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 12, 1219, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 1219, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 1220, "R/W", 0, 0, 0ull, 1023ull},
- {"RESERVED_10_63" , 10, 54, 1220, "RAZ", 1, 1, 0, 0},
- {"ECC_ENA0" , 0, 1, 1221, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND0" , 1, 2, 1221, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA1" , 3, 1, 1221, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND1" , 4, 2, 1221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1221, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1222, "RAZ", 1, 1, 0, 0},
- {"SYNDROM0" , 4, 7, 1222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 1222, "RAZ", 1, 1, 0, 0},
- {"ADDR0" , 16, 11, 1222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_35" , 27, 9, 1222, "RAZ", 1, 1, 0, 0},
- {"SYNDROM1" , 36, 7, 1222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_43_47" , 43, 5, 1222, "RAZ", 1, 1, 0, 0},
- {"ADDR1" , 48, 11, 1222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 1222, "RAZ", 1, 1, 0, 0},
- {"ECC_ENA0" , 0, 1, 1223, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND0" , 1, 2, 1223, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA1" , 3, 1, 1223, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND1" , 4, 2, 1223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1223, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1224, "RAZ", 1, 1, 0, 0},
- {"SYNDROM0" , 4, 7, 1224, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 1224, "RAZ", 1, 1, 0, 0},
- {"ADDR0" , 16, 11, 1224, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_35" , 27, 9, 1224, "RAZ", 1, 1, 0, 0},
- {"SYNDROM1" , 36, 7, 1224, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_43_47" , 43, 5, 1224, "RAZ", 1, 1, 0, 0},
- {"ADDR1" , 48, 11, 1224, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 1224, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 64, 1225, "R/W", 0, 0, 18446744073709551615ull, 18446744073709551615ull},
- {"QOS0_PRI" , 0, 4, 1226, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_7" , 4, 4, 1226, "RAZ", 1, 1, 0, 0},
- {"QOS1_PRI" , 8, 4, 1226, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 1226, "RAZ", 1, 1, 0, 0},
- {"QOS2_PRI" , 16, 4, 1226, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_23" , 20, 4, 1226, "RAZ", 1, 1, 0, 0},
- {"QOS3_PRI" , 24, 4, 1226, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 1226, "RAZ", 1, 1, 0, 0},
- {"QOS4_PRI" , 32, 4, 1226, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 1226, "RAZ", 1, 1, 0, 0},
- {"QOS5_PRI" , 40, 4, 1226, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_47" , 44, 4, 1226, "RAZ", 1, 1, 0, 0},
- {"QOS6_PRI" , 48, 4, 1226, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_52_55" , 52, 4, 1226, "RAZ", 1, 1, 0, 0},
- {"QOS7_PRI" , 56, 4, 1226, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 1226, "RAZ", 1, 1, 0, 0},
- {"PP_STRICT" , 0, 32, 1227, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1227, "RAZ", 1, 1, 0, 0},
- {"RNDS_QOS" , 0, 8, 1228, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_8_63" , 8, 56, 1228, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 12, 1229, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_13" , 12, 2, 1229, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 14, 12, 1229, "R/W", 0, 1, 241ull, 0},
- {"RESERVED_26_27" , 26, 2, 1229, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 28, 12, 1229, "RO", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 1229, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 0, 12, 1230, "RO", 0, 1, 2000ull, 0},
- {"RESERVED_12_13" , 12, 2, 1230, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 14, 12, 1230, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 1230, "RAZ", 1, 1, 0, 0},
- {"RCTR" , 0, 5, 1231, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_6" , 5, 2, 1231, "RAZ", 1, 1, 0, 0},
- {"PTR" , 7, 31, 1231, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1231, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 1232, "RAZ", 1, 1, 0, 0},
- {"FPTR" , 7, 31, 1232, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_62" , 38, 25, 1232, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 1232, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_6" , 0, 7, 1233, "RAZ", 1, 1, 0, 0},
- {"FPTR" , 7, 31, 1233, "WO", 0, 1, 0ull, 0},
- {"RESERVED_38_62" , 38, 25, 1233, "RAZ", 1, 1, 0, 0},
- {"FULL" , 63, 1, 1233, "RO", 0, 1, 0ull, 0},
- {"RCTR" , 0, 5, 1234, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_6" , 5, 2, 1234, "RAZ", 1, 1, 0, 0},
- {"PTR" , 7, 31, 1234, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1234, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 64, 1235, "R/W", 0, 1, 0ull, 0},
- {"WA_PC" , 0, 64, 1236, "R/W", 0, 1, 0ull, 0},
- {"WA_PC" , 0, 64, 1237, "R/W", 0, 1, 0ull, 0},
- {"WQ_INT" , 0, 64, 1238, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_CNT" , 0, 12, 1239, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_13" , 12, 2, 1239, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 14, 12, 1239, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_27" , 26, 2, 1239, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 28, 4, 1239, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1239, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1240, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 1240, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 1240, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 1240, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 1240, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 12, 1241, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_13" , 12, 2, 1241, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 14, 12, 1241, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_27" , 26, 2, 1241, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 28, 4, 1241, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 32, 1, 1241, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 1241, "RAZ", 1, 1, 0, 0},
- {"IQ_DIS" , 0, 64, 1242, "R/W1", 0, 1, 0ull, 0},
- {"WS_PC" , 0, 64, 1243, "R/W", 0, 1, 0ull, 0},
- {"RDS_MEM" , 0, 1, 1244, "RO", 1, 0, 0, 0ull},
- {"LSLR_FIFO" , 1, 1, 1244, "RO", 1, 0, 0, 0ull},
- {"WQE_FIFO" , 2, 1, 1244, "RO", 1, 0, 0, 0ull},
- {"RESERVED_3_63" , 3, 61, 1244, "RAZ", 1, 1, 0, 0},
- {"FSM0_STATE" , 0, 4, 1245, "RO", 0, 0, 0ull, 0ull},
- {"FSM1_STATE" , 4, 4, 1245, "RO", 0, 0, 0ull, 0ull},
- {"FSM2_STATE" , 8, 4, 1245, "RO", 0, 0, 0ull, 0ull},
- {"FSM3_STATE" , 12, 4, 1245, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1245, "RAZ", 1, 1, 0, 0},
- {"WQE_FIFO_LEVEL" , 32, 8, 1245, "RO", 0, 0, 0ull, 0ull},
- {"RWF_FIFO_LEVEL" , 40, 5, 1245, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 1245, "RAZ", 1, 1, 0, 0},
- {"GNT_FIFO_LEVEL" , 48, 3, 1245, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_51_55" , 51, 5, 1245, "RAZ", 1, 1, 0, 0},
- {"MEM_ALLOC_REG" , 56, 8, 1245, "RO", 0, 0, 0ull, 0ull},
- {"RINGS_PENDING_VEC" , 0, 64, 1246, "RO", 0, 0, 0ull, 0ull},
- {"ECC_EN" , 0, 1, 1247, "R/W", 0, 0, 1ull, 1ull},
- {"ECC_FLP_SYN" , 1, 2, 1247, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1247, "RAZ", 1, 1, 0, 0},
- {"FR_RN_TT" , 0, 22, 1248, "R/W", 0, 0, 1024ull, 1024ull},
- {"RESERVED_22_63" , 22, 42, 1248, "RAZ", 1, 1, 0, 0},
- {"INT0" , 0, 64, 1249, "R/W1C", 0, 0, 0ull, 0ull},
- {"INT0_EN" , 0, 64, 1250, "R/W", 0, 0, 0ull, 0ull},
- {"RING_ID" , 0, 6, 1251, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1251, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 1252, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 1252, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1252, "RAZ", 1, 1, 0, 0},
- {"SBE_EN" , 0, 1, 1253, "R/W", 0, 0, 0ull, 0ull},
- {"DBE_EN" , 1, 1, 1253, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1253, "RAZ", 1, 1, 0, 0},
- {"ADD" , 0, 8, 1254, "RO", 0, 0, 0ull, 0ull},
- {"SYND" , 8, 7, 1254, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 1254, "RAZ", 1, 1, 0, 0},
- {"ORG_RDS_DAT" , 0, 48, 1255, "RO", 0, 0, 0ull, 0ull},
- {"ORG_ECC" , 48, 7, 1255, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 1255, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 1256, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 1256, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 1256, "WO", 0, 0, 0ull, 0ull},
- {"ENA_DFB" , 3, 1, 1256, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_GPIO" , 4, 1, 1256, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO_EDGE" , 5, 2, 1256, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 1256, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 1257, "R/W", 1, 0, 0, 0ull},
- {"TIMERCOUNT" , 22, 22, 1257, "R/W", 1, 0, 0, 0ull},
- {"INTC" , 44, 2, 1257, "R/W", 1, 0, 0, 0ull},
- {"ENA" , 46, 1, 1257, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_47_63" , 47, 17, 1257, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 1258, "R/W", 1, 0, 0, 0ull},
- {"BUCKET" , 20, 20, 1258, "R/W", 1, 0, 0, 0ull},
- {"CPOOL" , 40, 3, 1258, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_43_63" , 43, 21, 1258, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 31, 1259, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_33" , 31, 3, 1259, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 34, 13, 1259, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_47_63" , 47, 17, 1259, "RAZ", 1, 1, 0, 0},
- {"CUR_BUCKET" , 0, 20, 1260, "RO", 0, 0, 0ull, 0ull},
- {"TIMERCOUNT" , 20, 22, 1260, "RO", 0, 0, 4096ull, 0ull},
- {"FR_RN_HT" , 42, 22, 1260, "RO", 0, 0, 0ull, 0ull},
- {"RING_ESR" , 0, 2, 1261, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1261, "RAZ", 1, 1, 0, 0},
- {"TDF" , 0, 1, 1262, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1262, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"CLKALWAYS" , 15, 1, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"RDAT_MD" , 16, 1, 1263, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1263, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 1264, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 1264, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 1264, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 1265, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 1265, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 1265, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1265, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 1265, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1266, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1266, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1267, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1267, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1268, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1268, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1268, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1268, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1268, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1268, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1269, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1269, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1269, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1269, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1269, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 8, 1270, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1270, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1270, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1270, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1270, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1270, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1270, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 1271, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 1271, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 1271, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 1271, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1271, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 1272, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 5, 1273, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1273, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1274, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1274, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1275, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1275, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1276, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1276, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1276, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1276, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1276, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1276, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1277, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1277, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1277, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1277, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1277, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 8, 1278, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1278, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1278, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1278, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1278, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1278, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1278, "R/W", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1279, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1280, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1280, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1281, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1281, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1281, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1281, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1281, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1281, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1282, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1282, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1282, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1282, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1282, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 8, 1283, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1283, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1283, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1283, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1283, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1283, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1283, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 1284, "R/W", 0, 1, 0ull, 0},
- {"LPL" , 5, 27, 1284, "R/W", 0, 1, 0ull, 0},
- {"CF" , 0, 1, 1285, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_31" , 1, 31, 1285, "R/W", 0, 0, 0ull, 0ull},
- {"CTRLDSSEG" , 0, 32, 1286, "R/W", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1287, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_31" , 14, 18, 1287, "RO", 0, 0, 0ull, 0ull},
- {"CAPLENGTH" , 0, 8, 1288, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_15" , 8, 8, 1288, "RO", 0, 0, 0ull, 0ull},
- {"HCIVERSION" , 16, 16, 1288, "RO", 0, 0, 256ull, 256ull},
- {"AC64" , 0, 1, 1289, "RO", 0, 0, 1ull, 1ull},
- {"PFLF" , 1, 1, 1289, "RO", 0, 0, 0ull, 0ull},
- {"ASPC" , 2, 1, 1289, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1289, "RO", 0, 0, 0ull, 0ull},
- {"IST" , 4, 4, 1289, "RO", 0, 0, 2ull, 2ull},
- {"EECP" , 8, 8, 1289, "RO", 0, 0, 160ull, 160ull},
- {"RESERVED_16_31" , 16, 16, 1289, "RO", 0, 0, 0ull, 0ull},
- {"N_PORTS" , 0, 4, 1290, "RO", 0, 0, 2ull, 2ull},
- {"PPC" , 4, 1, 1290, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 1290, "RO", 0, 0, 0ull, 0ull},
- {"PRR" , 7, 1, 1290, "RO", 0, 0, 0ull, 0ull},
- {"N_PCC" , 8, 4, 1290, "RO", 0, 0, 2ull, 2ull},
- {"N_CC" , 12, 4, 1290, "RO", 0, 0, 1ull, 1ull},
- {"P_INDICATOR" , 16, 1, 1290, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 1290, "RO", 0, 0, 0ull, 0ull},
- {"DPN" , 20, 4, 1290, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1290, "RO", 0, 0, 0ull, 0ull},
- {"EN" , 0, 1, 1291, "R/W", 0, 0, 0ull, 0ull},
- {"MFMC" , 1, 13, 1291, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 1291, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_0" , 0, 1, 1292, "R/W", 0, 0, 0ull, 0ull},
- {"TA_OFF" , 1, 8, 1292, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1292, "R/W", 0, 0, 0ull, 0ull},
- {"TXTX_TADAO" , 10, 3, 1292, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 1292, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_RW" , 0, 1, 1293, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_FW" , 1, 1, 1293, "R/W", 0, 0, 0ull, 0ull},
- {"PESD" , 2, 1, 1293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1293, "RAZ", 0, 0, 0ull, 0ull},
- {"NAKRF_DIS" , 4, 1, 1293, "R/W", 0, 0, 0ull, 0ull},
- {"AUTO_DIS" , 5, 1, 1293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 1293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_30" , 0, 31, 1294, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1294, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1295, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 1296, "R/W", 0, 1, 0ull, 0},
- {"BADDR" , 12, 20, 1296, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1297, "RO", 0, 0, 0ull, 0ull},
- {"CSC" , 1, 1, 1297, "R/W1C", 0, 0, 0ull, 0ull},
- {"PED" , 2, 1, 1297, "R/W", 0, 0, 0ull, 0ull},
- {"PEDC" , 3, 1, 1297, "R/W1C", 0, 0, 0ull, 0ull},
- {"OCA" , 4, 1, 1297, "RO", 0, 0, 0ull, 0ull},
- {"OCC" , 5, 1, 1297, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPR" , 6, 1, 1297, "R/W", 0, 0, 0ull, 0ull},
- {"SPD" , 7, 1, 1297, "R/W", 0, 0, 0ull, 0ull},
- {"PRST" , 8, 1, 1297, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1297, "RO", 0, 0, 0ull, 0ull},
- {"LSTS" , 10, 2, 1297, "RO", 0, 1, 0ull, 0},
- {"PP" , 12, 1, 1297, "RO", 0, 0, 1ull, 1ull},
- {"PO" , 13, 1, 1297, "R/W", 0, 0, 1ull, 0ull},
- {"PIC" , 14, 2, 1297, "R/W", 0, 0, 0ull, 0ull},
- {"PTC" , 16, 4, 1297, "R/W", 0, 0, 0ull, 0ull},
- {"WKCNNT_E" , 20, 1, 1297, "R/W", 0, 0, 0ull, 0ull},
- {"WKDSCNNT_E" , 21, 1, 1297, "R/W", 0, 0, 0ull, 0ull},
- {"WKOC_E" , 22, 1, 1297, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 1297, "RO", 0, 0, 0ull, 0ull},
- {"RS" , 0, 1, 1298, "R/W", 0, 0, 0ull, 1ull},
- {"HCRESET" , 1, 1, 1298, "R/W", 0, 0, 0ull, 0ull},
- {"FLS" , 2, 2, 1298, "RO", 0, 0, 0ull, 0ull},
- {"PS_EN" , 4, 1, 1298, "R/W", 0, 0, 0ull, 0ull},
- {"AS_EN" , 5, 1, 1298, "R/W", 0, 0, 0ull, 0ull},
- {"IAA_DB" , 6, 1, 1298, "R/W", 0, 0, 0ull, 0ull},
- {"LHCR" , 7, 1, 1298, "R/W", 0, 0, 0ull, 0ull},
- {"ASPMC" , 8, 2, 1298, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1298, "RO", 0, 0, 0ull, 0ull},
- {"ASPM_EN" , 11, 1, 1298, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 1298, "RO", 0, 0, 0ull, 0ull},
- {"ITC" , 16, 8, 1298, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_24_31" , 24, 8, 1298, "RO", 0, 0, 0ull, 0ull},
- {"USBINT_EN" , 0, 1, 1299, "R/W", 0, 1, 0ull, 0},
- {"USBERRINT_EN" , 1, 1, 1299, "R/W", 0, 1, 0ull, 0},
- {"PCI_EN" , 2, 1, 1299, "R/W", 0, 1, 0ull, 0},
- {"FLRO_EN" , 3, 1, 1299, "R/W", 0, 1, 0ull, 0},
- {"HSERR_EN" , 4, 1, 1299, "R/W", 0, 1, 0ull, 0},
- {"IOAA_EN" , 5, 1, 1299, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 1299, "RO", 0, 0, 0ull, 0ull},
- {"USBINT" , 0, 1, 1300, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBERRINT" , 1, 1, 1300, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCD" , 2, 1, 1300, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLRO" , 3, 1, 1300, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSYSERR" , 4, 1, 1300, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOAA" , 5, 1, 1300, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 1300, "RO", 0, 0, 0ull, 0ull},
- {"HCHTD" , 12, 1, 1300, "RO", 0, 0, 1ull, 0ull},
- {"RECLM" , 13, 1, 1300, "RO", 0, 0, 0ull, 0ull},
- {"PSS" , 14, 1, 1300, "RO", 0, 0, 0ull, 0ull},
- {"ASS" , 15, 1, 1300, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1300, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1301, "R/W", 0, 0, 0ull, 0ull},
- {"BCED" , 4, 28, 1301, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1302, "R/W", 0, 0, 0ull, 0ull},
- {"BHED" , 4, 28, 1302, "R/W", 0, 1, 0ull, 0},
- {"HCR" , 0, 1, 1303, "R/W", 0, 0, 0ull, 0ull},
- {"CLF" , 1, 1, 1303, "R/W", 0, 0, 0ull, 0ull},
- {"BLF" , 2, 1, 1303, "R/W", 0, 0, 0ull, 0ull},
- {"OCR" , 3, 1, 1303, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1303, "RO", 0, 0, 0ull, 0ull},
- {"SOC" , 16, 2, 1303, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 1303, "RO", 0, 0, 0ull, 0ull},
- {"CBSR" , 0, 2, 1304, "R/W", 0, 1, 0ull, 0},
- {"PLE" , 2, 1, 1304, "R/W", 0, 0, 0ull, 0ull},
- {"IE" , 3, 1, 1304, "R/W", 0, 0, 0ull, 0ull},
- {"CLE" , 4, 1, 1304, "R/W", 0, 0, 0ull, 0ull},
- {"BLE" , 5, 1, 1304, "R/W", 0, 0, 0ull, 0ull},
- {"HCFS" , 6, 2, 1304, "R/W", 0, 0, 0ull, 0ull},
- {"IR" , 8, 1, 1304, "R/W", 0, 0, 0ull, 0ull},
- {"RWC" , 9, 1, 1304, "R/W", 0, 0, 0ull, 0ull},
- {"RWE" , 10, 1, 1304, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 1304, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1305, "R/W", 0, 0, 0ull, 0ull},
- {"CCED" , 4, 28, 1305, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1306, "R/W", 0, 0, 0ull, 0ull},
- {"CHED" , 4, 28, 1306, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1307, "RO", 0, 0, 0ull, 0ull},
- {"DH" , 4, 28, 1307, "RO", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1308, "R/W", 0, 1, 11999ull, 0},
- {"RESERVED_14_15" , 14, 2, 1308, "R/W", 0, 0, 0ull, 0ull},
- {"FSMPS" , 16, 15, 1308, "R/W", 0, 1, 0ull, 0},
- {"FIT" , 31, 1, 1308, "R/W", 0, 0, 0ull, 0ull},
- {"FN" , 0, 16, 1309, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 1309, "RO", 0, 0, 0ull, 0ull},
- {"FR" , 0, 14, 1310, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_30" , 14, 17, 1310, "RO", 0, 0, 0ull, 0ull},
- {"FRT" , 31, 1, 1310, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1311, "R/W", 0, 0, 0ull, 0ull},
- {"HCCA" , 8, 24, 1311, "R/W", 0, 1, 0ull, 0},
- {"SO" , 0, 1, 1312, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1312, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1312, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1312, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1312, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1312, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1312, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1312, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1312, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1312, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1313, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1313, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1313, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1313, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1313, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1313, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1313, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1313, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1313, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1313, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1314, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1314, "R/W1C", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1314, "R/W1C", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1314, "R/W1C", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1314, "R/W1C", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1314, "R/W1C", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1314, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1314, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1314, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1314, "RO", 0, 0, 0ull, 0ull},
- {"LST" , 0, 12, 1315, "R/W", 0, 1, 1576ull, 0},
- {"RESERVED_12_31" , 12, 20, 1315, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1316, "RO", 0, 0, 0ull, 0ull},
- {"PCED" , 4, 28, 1316, "RO", 0, 1, 0ull, 0},
- {"PS" , 0, 14, 1317, "R/W", 0, 0, 0ull, 15975ull},
- {"RESERVED_14_31" , 14, 18, 1317, "R/W", 0, 0, 0ull, 0ull},
- {"REV" , 0, 8, 1318, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_31" , 8, 24, 1318, "RO", 0, 0, 0ull, 0ull},
- {"NDP" , 0, 8, 1319, "RO", 0, 0, 2ull, 2ull},
- {"NPS" , 8, 1, 1319, "R/W", 0, 0, 0ull, 0ull},
- {"PSM" , 9, 1, 1319, "R/W", 0, 0, 1ull, 1ull},
- {"DT" , 10, 1, 1319, "RO", 0, 0, 0ull, 0ull},
- {"OCPM" , 11, 1, 1319, "R/W", 1, 1, 0, 0},
- {"NOCP" , 12, 1, 1319, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_23" , 13, 11, 1319, "RO", 0, 0, 0ull, 0ull},
- {"POTPGT" , 24, 8, 1319, "R/W", 0, 0, 1ull, 1ull},
- {"DR" , 0, 16, 1320, "R/W", 0, 0, 0ull, 0ull},
- {"PPCM" , 16, 16, 1320, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"PES" , 1, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"PSS" , 2, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"POCI" , 3, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"PRS" , 4, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"PPS" , 8, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"LSDA" , 9, 1, 1321, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_15" , 10, 6, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"CSC" , 16, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"PESC" , 17, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"PSSC" , 18, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"OCIC" , 19, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"PRSC" , 20, 1, 1321, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_31" , 21, 11, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"LPS" , 0, 1, 1322, "R/W", 0, 0, 0ull, 0ull},
- {"OCI" , 1, 1, 1322, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_14" , 2, 13, 1322, "RO", 0, 0, 0ull, 0ull},
- {"DRWE" , 15, 1, 1322, "R/W", 0, 1, 0ull, 0},
- {"LPSC" , 16, 1, 1322, "R/W", 0, 1, 0ull, 0},
- {"CCIC" , 17, 1, 1322, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_18_30" , 18, 13, 1322, "RO", 0, 0, 0ull, 0ull},
- {"CRWE" , 31, 1, 1322, "WO", 1, 1, 0, 0},
- {"RESERVED_0_30" , 0, 31, 1323, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1323, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1324, "RO", 0, 0, 0ull, 0ull},
- {"PPAF_BIS" , 0, 1, 1325, "RO", 0, 0, 0ull, 0ull},
- {"WRBM_BIS" , 1, 1, 1325, "RO", 0, 0, 0ull, 0ull},
- {"ORBM_BIS" , 2, 1, 1325, "RO", 0, 0, 0ull, 0ull},
- {"ERBM_BIS" , 3, 1, 1325, "RO", 0, 0, 0ull, 0ull},
- {"DESC_BIS" , 4, 1, 1325, "RO", 0, 0, 0ull, 0ull},
- {"DATA_BIS" , 5, 1, 1325, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1325, "RO", 1, 1, 0, 0},
- {"HRST" , 0, 1, 1326, "R/W", 0, 0, 0ull, 1ull},
- {"P_PRST" , 1, 1, 1326, "R/W", 0, 0, 0ull, 1ull},
- {"P_POR" , 2, 1, 1326, "R/W", 0, 0, 1ull, 0ull},
- {"P_COM_ON" , 3, 1, 1326, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 1326, "R/W", 0, 1, 0ull, 0},
- {"P_REFCLK_DIV" , 5, 2, 1326, "R/W", 0, 0, 0ull, 0ull},
- {"P_REFCLK_SEL" , 7, 2, 1326, "R/W", 0, 0, 0ull, 0ull},
- {"H_DIV" , 9, 4, 1326, "R/W", 0, 0, 6ull, 6ull},
- {"O_CLKDIV_EN" , 13, 1, 1326, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_EN" , 14, 1, 1326, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_RST" , 15, 1, 1326, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_BYP" , 16, 1, 1326, "R/W", 0, 0, 0ull, 0ull},
- {"O_CLKDIV_RST" , 17, 1, 1326, "R/W", 0, 0, 0ull, 1ull},
- {"APP_START_CLK" , 18, 1, 1326, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_SUSP_LGCY" , 19, 1, 1326, "R/W", 0, 0, 1ull, 1ull},
- {"OHCI_SM" , 20, 1, 1326, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_CLKCKTRST" , 21, 1, 1326, "R/W", 0, 0, 1ull, 1ull},
- {"EHCI_SM" , 22, 1, 1326, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 23, 1, 1326, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 24, 1, 1326, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1326, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1327, "R/W", 0, 1, 0ull, 0},
- {"EHCI_64B_ADDR_EN" , 8, 1, 1327, "R/W", 0, 0, 1ull, 1ull},
- {"INV_REG_A2" , 9, 1, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1327, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1327, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"DESC_RBM" , 19, 1, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1327, "RAZ", 1, 1, 0, 0},
- {"FLA" , 0, 6, 1328, "R/W", 0, 0, 0ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 1328, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 1329, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 5, 27, 1329, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1329, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1330, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1330, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1331, "R/W", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1331, "R/W", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1331, "R/W", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1331, "R/W", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1331, "R/W", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1331, "R/W", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1331, "R/W", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1331, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1331, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1332, "R/W1C", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1332, "R/W1C", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1332, "R/W1C", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1332, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1332, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1332, "R/W1C", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1332, "R/W1C", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1332, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1332, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1333, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_8" , 8, 1, 1333, "RAZ", 1, 1, 0, 0},
- {"INV_REG_A2" , 9, 1, 1333, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1333, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1333, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1333, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1333, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1333, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1333, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1333, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1333, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1334, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 8, 24, 1334, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1334, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 1335, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_EN" , 1, 1, 1335, "R/W", 0, 0, 0ull, 0ull},
- {"UPHY_BIST" , 2, 1, 1335, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_EN" , 3, 1, 1335, "R/W", 0, 0, 0ull, 0ull},
- {"SIDDQ" , 4, 1, 1335, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 5, 1, 1335, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 6, 1, 1335, "R/W", 0, 0, 0ull, 0ull},
- {"HSBIST" , 7, 1, 1335, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ERR" , 8, 1, 1335, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 9, 1, 1335, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1335, "RAZ", 1, 1, 0, 0},
- {"TDATA_IN" , 0, 8, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 8, 4, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 12, 1, 1336, "R/W", 0, 0, 1ull, 0ull},
- {"TCLK" , 13, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_EN" , 14, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"COMPDISTUNE" , 15, 3, 1336, "R/W", 0, 0, 4ull, 4ull},
- {"SQRXTUNE" , 18, 3, 1336, "R/W", 0, 0, 4ull, 4ull},
- {"TXFSLSTUNE" , 21, 4, 1336, "R/W", 0, 0, 3ull, 3ull},
- {"TXPREEMPHASISTUNE" , 25, 1, 1336, "R/W", 0, 0, 0ull, 1ull},
- {"TXRISETUNE" , 26, 1, 1336, "R/W", 0, 0, 0ull, 1ull},
- {"TXVREFTUNE" , 27, 4, 1336, "R/W", 0, 0, 5ull, 15ull},
- {"TXHSVXTUNE" , 31, 2, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 33, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"VBUSVLDEXT" , 34, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"DPPULLDOWN" , 35, 1, 1336, "R/W", 0, 0, 1ull, 1ull},
- {"DMPULLDOWN" , 36, 1, 1336, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFEN" , 37, 1, 1336, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFENH" , 38, 1, 1336, "R/W", 0, 0, 1ull, 1ull},
- {"TDATA_OUT" , 39, 4, 1336, "RO", 1, 1, 0, 0},
- {"RESERVED_43_63" , 43, 21, 1336, "RAZ", 1, 1, 0, 0},
- {"ZIP_CTL" , 0, 4, 1337, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 53, 1337, "RO", 1, 0, 0, 0ull},
- {"RESERVED_57_63" , 57, 7, 1337, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1338, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 1338, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 1338, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 1338, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 1338, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 1339, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 1339, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1339, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 1340, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 1340, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 1340, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 1340, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 1340, "RO", 0, 0, 31744ull, 31744ull},
- {"RESERVED_48_63" , 48, 16, 1340, "RAZ", 1, 1, 0, 0},
- {"BSTATUS" , 0, 53, 1341, "RO", 1, 0, 0, 0ull},
- {"RESERVED_53_63" , 53, 11, 1341, "RAZ", 1, 1, 0, 0},
- {"BSTATUS" , 0, 7, 1342, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_63" , 7, 57, 1342, "RAZ", 1, 1, 0, 0},
- {"LMOD" , 0, 1, 1343, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 1, 1, 1343, "RO", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 1343, "RAZ", 1, 0, 0, 0ull},
- {"WKQF" , 4, 2, 1343, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_7" , 6, 2, 1343, "RAZ", 1, 0, 0, 0ull},
- {"LDF" , 8, 3, 1343, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_11_11" , 11, 1, 1343, "RAZ", 1, 0, 0, 0ull},
- {"STCF" , 12, 3, 1343, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_15_15" , 15, 1, 1343, "RAZ", 1, 0, 0, 0ull},
- {"GSTF" , 16, 3, 1343, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_19_19" , 19, 1, 1343, "RAZ", 1, 0, 0, 0ull},
- {"IPRF" , 20, 2, 1343, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_22_23" , 22, 2, 1343, "RAZ", 1, 0, 0, 0ull},
- {"ILDF" , 24, 3, 1343, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_27_63" , 27, 37, 1343, "RAZ", 1, 0, 0, 0ull},
- {"IID" , 0, 32, 1344, "RO", 0, 1, 0ull, 0},
- {"QID" , 32, 1, 1344, "RO", 0, 1, 0ull, 0},
- {"RESERVED_33_62" , 33, 30, 1344, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 63, 1, 1344, "RO", 0, 1, 0ull, 0},
- {"NIE" , 0, 32, 1345, "RO", 0, 1, 0ull, 0},
- {"IST" , 32, 5, 1345, "RO", 0, 1, 0ull, 0},
- {"RESERVED_37_62" , 37, 26, 1345, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 63, 1, 1345, "RO", 0, 1, 0ull, 0},
- {"NII" , 0, 32, 1346, "RO", 0, 1, 0ull, 0},
- {"CDBC" , 32, 20, 1346, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_62" , 52, 11, 1346, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 63, 1, 1346, "RO", 0, 1, 0ull, 0},
- {"ASSERTS" , 0, 30, 1347, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 1347, "RAZ", 1, 1, 0, 0},
- {"IBEN" , 0, 1, 1348, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_31" , 1, 31, 1348, "RAZ", 1, 1, 0, 0},
- {"IBGE" , 32, 2, 1348, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 1348, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1349, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1349, "RAZ", 1, 1, 0, 0},
- {"FIFE" , 0, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"IBSBE" , 1, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"IBDBE" , 2, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 1350, "RAZ", 1, 0, 0, 0ull},
- {"DOORBELL0" , 8, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL1" , 9, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1350, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1351, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1351, "RAZ", 1, 1, 0, 0},
- {"FIFE" , 0, 1, 1352, "RO", 0, 0, 0ull, 0ull},
- {"IBSBE" , 1, 1, 1352, "R/W1C", 0, 0, 0ull, 0ull},
- {"IBDBE" , 2, 1, 1352, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 1352, "RAZ", 1, 0, 0, 0ull},
- {"DOORBELL0" , 8, 1, 1352, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL1" , 9, 1, 1352, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1352, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1353, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 1353, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 1353, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 1353, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 1353, "RAZ", 1, 1, 0, 0},
- {"INUM" , 0, 32, 1354, "RO", 0, 0, 0ull, 0ull},
- {"WNUM" , 32, 3, 1354, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 1354, "RAZ", 1, 1, 0, 0},
- {"ZCE" , 0, 2, 1355, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_2_63" , 2, 62, 1355, "RAZ", 1, 1, 0, 0},
- {"ENA" , 0, 2, 1356, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_2_63" , 2, 62, 1356, "RAZ", 1, 1, 0, 0},
- {"PRI" , 0, 2, 1357, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1357, "RAZ", 1, 1, 0, 0},
- {"MAX_INFL" , 0, 5, 1358, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 1358, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn68xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 14, 0},
- {"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 14},
- {"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 13, 16},
- {"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 1, 29},
- {"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 1, 30},
- {"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 1, 31},
- {"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 32},
- {"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 7, 1, 33},
- {"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 34},
- {"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 2, 35},
- {"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 4, 37},
- {"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 11, 2, 41},
- {"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 11, 43},
- {"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 14, 54},
- {"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 68},
- {"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 15, 2, 70},
- {"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 72},
- {"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 17, 21, 74},
- {"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 21, 95},
- {"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 19, 2, 116},
- {"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 118},
- {"cvmx_agl_gmx_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 21, 4, 120},
- {"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 124},
- {"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 23, 2, 126},
- {"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 128},
- {"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 25, 2, 130},
- {"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 132},
- {"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 27, 2, 134},
- {"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 136},
- {"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 29, 2, 138},
- {"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 140},
- {"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 31, 2, 142},
- {"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 4, 144},
- {"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 33, 2, 148},
- {"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 150},
- {"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 35, 2, 152},
- {"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 4, 154},
- {"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 37, 4, 158},
- {"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 2, 162},
- {"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 39, 3, 164},
- {"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 5, 167},
- {"cvmx_agl_gmx_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 41, 2, 172},
- {"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 3, 174},
- {"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 43, 2, 177},
- {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 179},
- {"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 45, 2, 181},
- {"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 183},
- {"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 47, 2, 185},
- {"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 187},
- {"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 49, 2, 189},
- {"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 191},
- {"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 51, 2, 193},
- {"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 195},
- {"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 53, 2, 197},
- {"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 199},
- {"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 55, 2, 201},
- {"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 203},
- {"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 57, 2, 205},
- {"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 207},
- {"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 59, 2, 209},
- {"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 211},
- {"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 61, 2, 213},
- {"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 215},
- {"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 63, 3, 217},
- {"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 12, 220},
- {"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 12, 232},
- {"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 244},
- {"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 2, 246},
- {"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 6, 248},
- {"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 69, 2, 254},
- {"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 70, 2, 256},
- {"cvmx_agl_prt#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 23, 258},
- {"cvmx_ciu2_ack_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 72, 2, 281},
- {"cvmx_ciu2_ack_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 74, 2, 283},
- {"cvmx_ciu2_ack_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 106, 2, 285},
- {"cvmx_ciu2_ack_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 138, 2, 287},
- {"cvmx_ciu2_en_io#_int_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 170, 2, 289},
- {"cvmx_ciu2_en_io#_int_gpio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 172, 2, 291},
- {"cvmx_ciu2_en_io#_int_gpio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 174, 2, 293},
- {"cvmx_ciu2_en_io#_int_io" , CVMX_CSR_DB_TYPE_NCB, 64, 176, 9, 295},
- {"cvmx_ciu2_en_io#_int_io_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 178, 9, 304},
- {"cvmx_ciu2_en_io#_int_io_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 180, 9, 313},
- {"cvmx_ciu2_en_io#_int_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 182, 2, 322},
- {"cvmx_ciu2_en_io#_int_mbox_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 184, 2, 324},
- {"cvmx_ciu2_en_io#_int_mbox_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 186, 2, 326},
- {"cvmx_ciu2_en_io#_int_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 188, 2, 328},
- {"cvmx_ciu2_en_io#_int_mem_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 190, 2, 330},
- {"cvmx_ciu2_en_io#_int_mem_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 192, 2, 332},
- {"cvmx_ciu2_en_io#_int_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 194, 21, 334},
- {"cvmx_ciu2_en_io#_int_mio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 196, 21, 355},
- {"cvmx_ciu2_en_io#_int_mio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 198, 21, 376},
- {"cvmx_ciu2_en_io#_int_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 200, 12, 397},
- {"cvmx_ciu2_en_io#_int_pkt_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 202, 12, 409},
- {"cvmx_ciu2_en_io#_int_pkt_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 204, 12, 421},
- {"cvmx_ciu2_en_io#_int_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 206, 26, 433},
- {"cvmx_ciu2_en_io#_int_rml_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 208, 26, 459},
- {"cvmx_ciu2_en_io#_int_rml_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 210, 26, 485},
- {"cvmx_ciu2_en_io#_int_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 212, 2, 511},
- {"cvmx_ciu2_en_io#_int_wdog_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 214, 2, 513},
- {"cvmx_ciu2_en_io#_int_wdog_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 216, 2, 515},
- {"cvmx_ciu2_en_io#_int_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 218, 1, 517},
- {"cvmx_ciu2_en_io#_int_wrkq_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 220, 1, 518},
- {"cvmx_ciu2_en_io#_int_wrkq_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 222, 1, 519},
- {"cvmx_ciu2_en_pp#_ip2_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 2, 520},
- {"cvmx_ciu2_en_pp#_ip2_gpio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 256, 2, 522},
- {"cvmx_ciu2_en_pp#_ip2_gpio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 288, 2, 524},
- {"cvmx_ciu2_en_pp#_ip2_io" , CVMX_CSR_DB_TYPE_NCB, 64, 320, 9, 526},
- {"cvmx_ciu2_en_pp#_ip2_io_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 352, 9, 535},
- {"cvmx_ciu2_en_pp#_ip2_io_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 384, 9, 544},
- {"cvmx_ciu2_en_pp#_ip2_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 416, 2, 553},
- {"cvmx_ciu2_en_pp#_ip2_mbox_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 448, 2, 555},
- {"cvmx_ciu2_en_pp#_ip2_mbox_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 480, 2, 557},
- {"cvmx_ciu2_en_pp#_ip2_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 512, 2, 559},
- {"cvmx_ciu2_en_pp#_ip2_mem_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 544, 2, 561},
- {"cvmx_ciu2_en_pp#_ip2_mem_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 576, 2, 563},
- {"cvmx_ciu2_en_pp#_ip2_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 608, 21, 565},
- {"cvmx_ciu2_en_pp#_ip2_mio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 640, 21, 586},
- {"cvmx_ciu2_en_pp#_ip2_mio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 672, 21, 607},
- {"cvmx_ciu2_en_pp#_ip2_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 704, 12, 628},
- {"cvmx_ciu2_en_pp#_ip2_pkt_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 736, 12, 640},
- {"cvmx_ciu2_en_pp#_ip2_pkt_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 768, 12, 652},
- {"cvmx_ciu2_en_pp#_ip2_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 800, 26, 664},
- {"cvmx_ciu2_en_pp#_ip2_rml_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 832, 26, 690},
- {"cvmx_ciu2_en_pp#_ip2_rml_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 864, 26, 716},
- {"cvmx_ciu2_en_pp#_ip2_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 896, 2, 742},
- {"cvmx_ciu2_en_pp#_ip2_wdog_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 928, 2, 744},
- {"cvmx_ciu2_en_pp#_ip2_wdog_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 960, 2, 746},
- {"cvmx_ciu2_en_pp#_ip2_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 992, 1, 748},
- {"cvmx_ciu2_en_pp#_ip2_wrkq_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1024, 1, 749},
- {"cvmx_ciu2_en_pp#_ip2_wrkq_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1056, 1, 750},
- {"cvmx_ciu2_en_pp#_ip3_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 1088, 2, 751},
- {"cvmx_ciu2_en_pp#_ip3_gpio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1120, 2, 753},
- {"cvmx_ciu2_en_pp#_ip3_gpio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1152, 2, 755},
- {"cvmx_ciu2_en_pp#_ip3_io" , CVMX_CSR_DB_TYPE_NCB, 64, 1184, 9, 757},
- {"cvmx_ciu2_en_pp#_ip3_io_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 1216, 9, 766},
- {"cvmx_ciu2_en_pp#_ip3_io_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 1248, 9, 775},
- {"cvmx_ciu2_en_pp#_ip3_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 1280, 2, 784},
- {"cvmx_ciu2_en_pp#_ip3_mbox_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1312, 2, 786},
- {"cvmx_ciu2_en_pp#_ip3_mbox_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1344, 2, 788},
- {"cvmx_ciu2_en_pp#_ip3_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 1376, 2, 790},
- {"cvmx_ciu2_en_pp#_ip3_mem_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1408, 2, 792},
- {"cvmx_ciu2_en_pp#_ip3_mem_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1440, 2, 794},
- {"cvmx_ciu2_en_pp#_ip3_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 1472, 21, 796},
- {"cvmx_ciu2_en_pp#_ip3_mio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1504, 21, 817},
- {"cvmx_ciu2_en_pp#_ip3_mio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1536, 21, 838},
- {"cvmx_ciu2_en_pp#_ip3_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 1568, 12, 859},
- {"cvmx_ciu2_en_pp#_ip3_pkt_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1600, 12, 871},
- {"cvmx_ciu2_en_pp#_ip3_pkt_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1632, 12, 883},
- {"cvmx_ciu2_en_pp#_ip3_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 1664, 26, 895},
- {"cvmx_ciu2_en_pp#_ip3_rml_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1696, 26, 921},
- {"cvmx_ciu2_en_pp#_ip3_rml_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1728, 26, 947},
- {"cvmx_ciu2_en_pp#_ip3_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 1760, 2, 973},
- {"cvmx_ciu2_en_pp#_ip3_wdog_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1792, 2, 975},
- {"cvmx_ciu2_en_pp#_ip3_wdog_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1824, 2, 977},
- {"cvmx_ciu2_en_pp#_ip3_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 1856, 1, 979},
- {"cvmx_ciu2_en_pp#_ip3_wrkq_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1888, 1, 980},
- {"cvmx_ciu2_en_pp#_ip3_wrkq_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 1920, 1, 981},
- {"cvmx_ciu2_en_pp#_ip4_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 1952, 2, 982},
- {"cvmx_ciu2_en_pp#_ip4_gpio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 1984, 2, 984},
- {"cvmx_ciu2_en_pp#_ip4_gpio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2016, 2, 986},
- {"cvmx_ciu2_en_pp#_ip4_io" , CVMX_CSR_DB_TYPE_NCB, 64, 2048, 9, 988},
- {"cvmx_ciu2_en_pp#_ip4_io_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 2080, 9, 997},
- {"cvmx_ciu2_en_pp#_ip4_io_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 2112, 9, 1006},
- {"cvmx_ciu2_en_pp#_ip4_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 2144, 2, 1015},
- {"cvmx_ciu2_en_pp#_ip4_mbox_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2176, 2, 1017},
- {"cvmx_ciu2_en_pp#_ip4_mbox_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2208, 2, 1019},
- {"cvmx_ciu2_en_pp#_ip4_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 2240, 2, 1021},
- {"cvmx_ciu2_en_pp#_ip4_mem_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2272, 2, 1023},
- {"cvmx_ciu2_en_pp#_ip4_mem_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2304, 2, 1025},
- {"cvmx_ciu2_en_pp#_ip4_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 2336, 21, 1027},
- {"cvmx_ciu2_en_pp#_ip4_mio_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2368, 21, 1048},
- {"cvmx_ciu2_en_pp#_ip4_mio_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2400, 21, 1069},
- {"cvmx_ciu2_en_pp#_ip4_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 2432, 12, 1090},
- {"cvmx_ciu2_en_pp#_ip4_pkt_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2464, 12, 1102},
- {"cvmx_ciu2_en_pp#_ip4_pkt_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2496, 12, 1114},
- {"cvmx_ciu2_en_pp#_ip4_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 2528, 26, 1126},
- {"cvmx_ciu2_en_pp#_ip4_rml_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2560, 26, 1152},
- {"cvmx_ciu2_en_pp#_ip4_rml_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2592, 26, 1178},
- {"cvmx_ciu2_en_pp#_ip4_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 2624, 2, 1204},
- {"cvmx_ciu2_en_pp#_ip4_wdog_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2656, 2, 1206},
- {"cvmx_ciu2_en_pp#_ip4_wdog_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2688, 2, 1208},
- {"cvmx_ciu2_en_pp#_ip4_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 2720, 1, 1210},
- {"cvmx_ciu2_en_pp#_ip4_wrkq_w1c", CVMX_CSR_DB_TYPE_NCB, 64, 2752, 1, 1211},
- {"cvmx_ciu2_en_pp#_ip4_wrkq_w1s", CVMX_CSR_DB_TYPE_NCB, 64, 2784, 1, 1212},
- {"cvmx_ciu2_intr_ciu_ready" , CVMX_CSR_DB_TYPE_NCB, 64, 2816, 2, 1213},
- {"cvmx_ciu2_intr_ram_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2817, 3, 1215},
- {"cvmx_ciu2_intr_ram_ecc_st" , CVMX_CSR_DB_TYPE_NCB, 64, 2818, 7, 1218},
- {"cvmx_ciu2_intr_slowdown" , CVMX_CSR_DB_TYPE_NCB, 64, 2819, 2, 1225},
- {"cvmx_ciu2_msi_rcv#" , CVMX_CSR_DB_TYPE_NCB, 64, 2820, 2, 1227},
- {"cvmx_ciu2_msi_sel#" , CVMX_CSR_DB_TYPE_NCB, 64, 3076, 6, 1229},
- {"cvmx_ciu2_msired_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 3332, 6, 1235},
- {"cvmx_ciu2_msired_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 3364, 6, 1241},
- {"cvmx_ciu2_msired_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 3396, 6, 1247},
- {"cvmx_ciu2_raw_io#_int_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 3428, 2, 1253},
- {"cvmx_ciu2_raw_io#_int_io" , CVMX_CSR_DB_TYPE_NCB, 64, 3430, 9, 1255},
- {"cvmx_ciu2_raw_io#_int_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 3432, 2, 1264},
- {"cvmx_ciu2_raw_io#_int_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 3434, 21, 1266},
- {"cvmx_ciu2_raw_io#_int_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 3436, 12, 1287},
- {"cvmx_ciu2_raw_io#_int_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 3438, 26, 1299},
- {"cvmx_ciu2_raw_io#_int_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 3440, 2, 1325},
- {"cvmx_ciu2_raw_io#_int_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 3442, 1, 1327},
- {"cvmx_ciu2_raw_pp#_ip2_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 3444, 2, 1328},
- {"cvmx_ciu2_raw_pp#_ip2_io" , CVMX_CSR_DB_TYPE_NCB, 64, 3476, 9, 1330},
- {"cvmx_ciu2_raw_pp#_ip2_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 3508, 2, 1339},
- {"cvmx_ciu2_raw_pp#_ip2_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 3540, 21, 1341},
- {"cvmx_ciu2_raw_pp#_ip2_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 3572, 12, 1362},
- {"cvmx_ciu2_raw_pp#_ip2_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 3604, 26, 1374},
- {"cvmx_ciu2_raw_pp#_ip2_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 3636, 2, 1400},
- {"cvmx_ciu2_raw_pp#_ip2_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 3668, 1, 1402},
- {"cvmx_ciu2_raw_pp#_ip3_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 3700, 2, 1403},
- {"cvmx_ciu2_raw_pp#_ip3_io" , CVMX_CSR_DB_TYPE_NCB, 64, 3732, 9, 1405},
- {"cvmx_ciu2_raw_pp#_ip3_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 3764, 2, 1414},
- {"cvmx_ciu2_raw_pp#_ip3_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 3796, 21, 1416},
- {"cvmx_ciu2_raw_pp#_ip3_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 3828, 12, 1437},
- {"cvmx_ciu2_raw_pp#_ip3_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 3860, 26, 1449},
- {"cvmx_ciu2_raw_pp#_ip3_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 3892, 2, 1475},
- {"cvmx_ciu2_raw_pp#_ip3_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 3924, 1, 1477},
- {"cvmx_ciu2_raw_pp#_ip4_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 3956, 2, 1478},
- {"cvmx_ciu2_raw_pp#_ip4_io" , CVMX_CSR_DB_TYPE_NCB, 64, 3988, 9, 1480},
- {"cvmx_ciu2_raw_pp#_ip4_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 4020, 2, 1489},
- {"cvmx_ciu2_raw_pp#_ip4_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 4052, 21, 1491},
- {"cvmx_ciu2_raw_pp#_ip4_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 4084, 12, 1512},
- {"cvmx_ciu2_raw_pp#_ip4_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 4116, 26, 1524},
- {"cvmx_ciu2_raw_pp#_ip4_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 4148, 2, 1550},
- {"cvmx_ciu2_raw_pp#_ip4_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 4180, 1, 1552},
- {"cvmx_ciu2_src_io#_int_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 4212, 2, 1553},
- {"cvmx_ciu2_src_io#_int_io" , CVMX_CSR_DB_TYPE_NCB, 64, 4214, 9, 1555},
- {"cvmx_ciu2_src_io#_int_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 4216, 2, 1564},
- {"cvmx_ciu2_src_io#_int_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 4218, 2, 1566},
- {"cvmx_ciu2_src_io#_int_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 4220, 21, 1568},
- {"cvmx_ciu2_src_io#_int_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 4222, 12, 1589},
- {"cvmx_ciu2_src_io#_int_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 4224, 26, 1601},
- {"cvmx_ciu2_src_io#_int_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 4226, 2, 1627},
- {"cvmx_ciu2_src_io#_int_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 4228, 1, 1629},
- {"cvmx_ciu2_src_pp#_ip2_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 4230, 2, 1630},
- {"cvmx_ciu2_src_pp#_ip2_io" , CVMX_CSR_DB_TYPE_NCB, 64, 4262, 9, 1632},
- {"cvmx_ciu2_src_pp#_ip2_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 4294, 2, 1641},
- {"cvmx_ciu2_src_pp#_ip2_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 4326, 2, 1643},
- {"cvmx_ciu2_src_pp#_ip2_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 4358, 21, 1645},
- {"cvmx_ciu2_src_pp#_ip2_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 4390, 12, 1666},
- {"cvmx_ciu2_src_pp#_ip2_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 4422, 26, 1678},
- {"cvmx_ciu2_src_pp#_ip2_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 4454, 2, 1704},
- {"cvmx_ciu2_src_pp#_ip2_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 4486, 1, 1706},
- {"cvmx_ciu2_src_pp#_ip3_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 4518, 2, 1707},
- {"cvmx_ciu2_src_pp#_ip3_io" , CVMX_CSR_DB_TYPE_NCB, 64, 4550, 9, 1709},
- {"cvmx_ciu2_src_pp#_ip3_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 4582, 2, 1718},
- {"cvmx_ciu2_src_pp#_ip3_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 4614, 2, 1720},
- {"cvmx_ciu2_src_pp#_ip3_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 4646, 21, 1722},
- {"cvmx_ciu2_src_pp#_ip3_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 4678, 12, 1743},
- {"cvmx_ciu2_src_pp#_ip3_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 4710, 26, 1755},
- {"cvmx_ciu2_src_pp#_ip3_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 4742, 2, 1781},
- {"cvmx_ciu2_src_pp#_ip3_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 4774, 1, 1783},
- {"cvmx_ciu2_src_pp#_ip4_gpio" , CVMX_CSR_DB_TYPE_NCB, 64, 4806, 2, 1784},
- {"cvmx_ciu2_src_pp#_ip4_io" , CVMX_CSR_DB_TYPE_NCB, 64, 4838, 9, 1786},
- {"cvmx_ciu2_src_pp#_ip4_mbox" , CVMX_CSR_DB_TYPE_NCB, 64, 4870, 2, 1795},
- {"cvmx_ciu2_src_pp#_ip4_mem" , CVMX_CSR_DB_TYPE_NCB, 64, 4902, 2, 1797},
- {"cvmx_ciu2_src_pp#_ip4_mio" , CVMX_CSR_DB_TYPE_NCB, 64, 4934, 21, 1799},
- {"cvmx_ciu2_src_pp#_ip4_pkt" , CVMX_CSR_DB_TYPE_NCB, 64, 4966, 12, 1820},
- {"cvmx_ciu2_src_pp#_ip4_rml" , CVMX_CSR_DB_TYPE_NCB, 64, 4998, 26, 1832},
- {"cvmx_ciu2_src_pp#_ip4_wdog" , CVMX_CSR_DB_TYPE_NCB, 64, 5030, 2, 1858},
- {"cvmx_ciu2_src_pp#_ip4_wrkq" , CVMX_CSR_DB_TYPE_NCB, 64, 5062, 1, 1860},
- {"cvmx_ciu2_sum_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 5094, 10, 1861},
- {"cvmx_ciu2_sum_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 5096, 10, 1871},
- {"cvmx_ciu2_sum_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 5128, 10, 1881},
- {"cvmx_ciu2_sum_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 5160, 10, 1891},
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 5192, 2, 1901},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 5193, 2, 1903},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 5194, 2, 1905},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 5195, 2, 1907},
- {"cvmx_ciu_int_dbg_sel" , CVMX_CSR_DB_TYPE_NCB, 64, 5196, 6, 1909},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 5197, 2, 1915},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 5229, 2, 1917},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 5261, 2, 1919},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 5262, 2, 1921},
- {"cvmx_ciu_pp_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 5263, 2, 1923},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 5264, 2, 1925},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 5265, 1, 1927},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 5297, 3, 1928},
- {"cvmx_ciu_qlm0" , CVMX_CSR_DB_TYPE_NCB, 64, 5298, 8, 1931},
- {"cvmx_ciu_qlm1" , CVMX_CSR_DB_TYPE_NCB, 64, 5299, 13, 1939},
- {"cvmx_ciu_qlm2" , CVMX_CSR_DB_TYPE_NCB, 64, 5300, 13, 1952},
- {"cvmx_ciu_qlm3" , CVMX_CSR_DB_TYPE_NCB, 64, 5301, 13, 1965},
- {"cvmx_ciu_qlm4" , CVMX_CSR_DB_TYPE_NCB, 64, 5302, 13, 1978},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 5303, 7, 1991},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 5304, 8, 1998},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 5305, 2, 2006},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 5306, 2, 2008},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 5307, 2, 2010},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 5308, 2, 2012},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 5309, 3, 2014},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 5313, 7, 2017},
- {"cvmx_dfa_bist0" , CVMX_CSR_DB_TYPE_RSL, 64, 5345, 16, 2024},
- {"cvmx_dfa_bist1" , CVMX_CSR_DB_TYPE_RSL, 64, 5346, 20, 2040},
- {"cvmx_dfa_config" , CVMX_CSR_DB_TYPE_RSL, 64, 5347, 7, 2060},
- {"cvmx_dfa_control" , CVMX_CSR_DB_TYPE_RSL, 64, 5348, 7, 2067},
- {"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 5349, 2, 2074},
- {"cvmx_dfa_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 5350, 1, 2076},
- {"cvmx_dfa_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 5351, 1, 2077},
- {"cvmx_dfa_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 5352, 1, 2078},
- {"cvmx_dfa_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 5353, 1, 2079},
- {"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 5354, 5, 2080},
- {"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 5355, 3, 2085},
- {"cvmx_dfa_dtcfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 5356, 6, 2088},
- {"cvmx_dfa_error" , CVMX_CSR_DB_TYPE_RSL, 64, 5357, 12, 2094},
- {"cvmx_dfa_intmsk" , CVMX_CSR_DB_TYPE_RSL, 64, 5358, 11, 2106},
- {"cvmx_dfa_memhidat" , CVMX_CSR_DB_TYPE_NCB, 64, 5359, 1, 2117},
- {"cvmx_dfa_pfc0_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5360, 1, 2118},
- {"cvmx_dfa_pfc0_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5361, 5, 2119},
- {"cvmx_dfa_pfc1_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5362, 1, 2124},
- {"cvmx_dfa_pfc1_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5363, 5, 2125},
- {"cvmx_dfa_pfc2_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5364, 1, 2130},
- {"cvmx_dfa_pfc2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5365, 5, 2131},
- {"cvmx_dfa_pfc3_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 5366, 1, 2136},
- {"cvmx_dfa_pfc3_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5367, 5, 2137},
- {"cvmx_dfa_pfc_gctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5368, 18, 2142},
- {"cvmx_dpi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 5369, 2, 2160},
- {"cvmx_dpi_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 5370, 3, 2162},
- {"cvmx_dpi_dma#_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 5371, 3, 2165},
- {"cvmx_dpi_dma#_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 5379, 2, 2168},
- {"cvmx_dpi_dma#_err_rsp_status", CVMX_CSR_DB_TYPE_NCB, 64, 5387, 2, 2170},
- {"cvmx_dpi_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 5395, 6, 2172},
- {"cvmx_dpi_dma#_iflight" , CVMX_CSR_DB_TYPE_NCB, 64, 5403, 2, 2178},
- {"cvmx_dpi_dma#_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 5411, 2, 2180},
- {"cvmx_dpi_dma#_reqbnk0" , CVMX_CSR_DB_TYPE_NCB, 64, 5419, 1, 2182},
- {"cvmx_dpi_dma#_reqbnk1" , CVMX_CSR_DB_TYPE_NCB, 64, 5427, 1, 2183},
- {"cvmx_dpi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 5435, 20, 2184},
- {"cvmx_dpi_dma_eng#_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5436, 2, 2204},
- {"cvmx_dpi_dma_pp#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5442, 2, 2206},
- {"cvmx_dpi_eng#_buf" , CVMX_CSR_DB_TYPE_NCB, 64, 5474, 5, 2208},
- {"cvmx_dpi_info_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 5480, 5, 2213},
- {"cvmx_dpi_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5481, 15, 2218},
- {"cvmx_dpi_int_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 5482, 15, 2233},
- {"cvmx_dpi_ncb#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5483, 2, 2248},
- {"cvmx_dpi_pint_info" , CVMX_CSR_DB_TYPE_NCB, 64, 5484, 4, 2250},
- {"cvmx_dpi_pkt_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 5485, 2, 2254},
- {"cvmx_dpi_req_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 5486, 2, 2256},
- {"cvmx_dpi_req_err_rsp_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5487, 2, 2258},
- {"cvmx_dpi_req_err_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 5488, 2, 2260},
- {"cvmx_dpi_req_err_rst_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5489, 2, 2262},
- {"cvmx_dpi_req_err_skip_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 5490, 4, 2264},
- {"cvmx_dpi_req_gbl_en" , CVMX_CSR_DB_TYPE_NCB, 64, 5491, 2, 2268},
- {"cvmx_dpi_sli_prt#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5492, 14, 2270},
- {"cvmx_dpi_sli_prt#_err" , CVMX_CSR_DB_TYPE_NCB, 64, 5494, 2, 2284},
- {"cvmx_dpi_sli_prt#_err_info" , CVMX_CSR_DB_TYPE_NCB, 64, 5496, 6, 2286},
- {"cvmx_fpa_addr_range_error" , CVMX_CSR_DB_TYPE_RSL, 64, 5498, 3, 2292},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5499, 6, 2295},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5500, 10, 2301},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 5501, 3, 2311},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 5508, 2, 2314},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 5515, 3, 2316},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 5516, 2, 2319},
- {"cvmx_fpa_fpf8_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 5517, 3, 2321},
- {"cvmx_fpa_fpf8_size" , CVMX_CSR_DB_TYPE_RSL, 64, 5518, 2, 2324},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 5519, 51, 2326},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 5520, 51, 2377},
- {"cvmx_fpa_packet_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 5521, 2, 2428},
- {"cvmx_fpa_pool#_end_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 5522, 2, 2430},
- {"cvmx_fpa_pool#_start_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 5531, 2, 2432},
- {"cvmx_fpa_pool#_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 5540, 2, 2434},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 5549, 2, 2436},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 5558, 2, 2438},
- {"cvmx_fpa_que8_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 5566, 2, 2440},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 5567, 3, 2442},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 5568, 3, 2445},
- {"cvmx_fpa_wqe_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 5569, 2, 2448},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5570, 7, 2450},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 5575, 2, 2457},
- {"cvmx_gmx#_bpid_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 5580, 6, 2459},
- {"cvmx_gmx#_bpid_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 5660, 4, 2465},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5665, 2, 2469},
- {"cvmx_gmx#_ebp_dis" , CVMX_CSR_DB_TYPE_RSL, 64, 5670, 2, 2471},
- {"cvmx_gmx#_ebp_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 5675, 2, 2473},
- {"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 5680, 5, 2475},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 5685, 7, 2480},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 5690, 4, 2487},
- {"cvmx_gmx#_pipe_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5695, 6, 2491},
- {"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5700, 8, 2497},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 5705, 12, 2505},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 5725, 1, 2517},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 5745, 1, 2518},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 5765, 1, 2519},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 5785, 1, 2520},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 5805, 1, 2521},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 5825, 1, 2522},
- {"cvmx_gmx#_rx#_adr_cam_all_en", CVMX_CSR_DB_TYPE_RSL, 64, 5845, 2, 2523},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5865, 2, 2525},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5885, 4, 2527},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 5905, 2, 2531},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 5925, 9, 2533},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5945, 13, 2542},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 5965, 2, 2555},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5985, 27, 2557},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6005, 27, 2584},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 6025, 2, 2611},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 6045, 2, 2613},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6065, 2, 2615},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 6085, 2, 2617},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 6105, 2, 2619},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 6125, 2, 2621},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 6145, 2, 2623},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 6165, 2, 2625},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 6185, 2, 2627},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 6205, 2, 2629},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 6225, 2, 2631},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 6245, 2, 2633},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 6265, 4, 2635},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 6285, 2, 2639},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 6305, 2, 2641},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 6325, 2, 2643},
- {"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6345, 4, 2645},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 6350, 4, 2649},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 6355, 2, 2653},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 6360, 5, 2655},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6365, 2, 2660},
- {"cvmx_gmx#_rxaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6370, 2, 2662},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 6375, 2, 2664},
- {"cvmx_gmx#_soft_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 6395, 3, 2666},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 6400, 3, 2669},
- {"cvmx_gmx#_tb_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6405, 2, 2672},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 6410, 5, 2674},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 6430, 2, 2679},
- {"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 6450, 2, 2681},
- {"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 6455, 2, 2683},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6460, 3, 2685},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 6480, 2, 2688},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 6500, 2, 2690},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 6520, 2, 2692},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 6540, 3, 2694},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 6560, 2, 2697},
- {"cvmx_gmx#_tx#_pipe" , CVMX_CSR_DB_TYPE_RSL, 64, 6580, 6, 2699},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6600, 2, 2705},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 6620, 2, 2707},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 6640, 2, 2709},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 6660, 2, 2711},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 6680, 2, 2713},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 6700, 2, 2715},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 6720, 2, 2717},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 6740, 2, 2719},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 6760, 2, 2721},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 6780, 2, 2723},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 6800, 2, 2725},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 6820, 2, 2727},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 6840, 2, 2729},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6860, 2, 2731},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 6880, 2, 2733},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 6900, 2, 2735},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 6905, 2, 2737},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 6910, 2, 2739},
- {"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 6915, 2, 2741},
- {"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 6920, 2, 2743},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 6925, 3, 2745},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 6930, 10, 2748},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6935, 10, 2758},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 6940, 2, 2768},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 6945, 2, 2770},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 6950, 6, 2772},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 6955, 2, 2778},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 6960, 2, 2780},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 6965, 2, 2782},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6970, 9, 2784},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 6975, 3, 2793},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 6980, 10, 2796},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 6996, 2, 2806},
- {"cvmx_gpio_clk_qlm#" , CVMX_CSR_DB_TYPE_NCB, 64, 7000, 5, 2808},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 7002, 2, 2813},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 7003, 2, 2815},
- {"cvmx_gpio_tim_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 7004, 2, 2817},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 7005, 2, 2819},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 7006, 2, 2821},
- {"cvmx_ilk_bist_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 7007, 44, 2823},
- {"cvmx_ilk_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 7008, 5, 2867},
- {"cvmx_ilk_gbl_int" , CVMX_CSR_DB_TYPE_RSL, 64, 7009, 6, 2872},
- {"cvmx_ilk_gbl_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 7010, 6, 2878},
- {"cvmx_ilk_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 7011, 14, 2884},
- {"cvmx_ilk_lne_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 7012, 11, 2898},
- {"cvmx_ilk_lne_sts_msg" , CVMX_CSR_DB_TYPE_RSL, 64, 7013, 8, 2909},
- {"cvmx_ilk_rx#_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 7014, 19, 2917},
- {"cvmx_ilk_rx#_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 7016, 14, 2936},
- {"cvmx_ilk_rx#_flow_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 7018, 1, 2950},
- {"cvmx_ilk_rx#_flow_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 7020, 1, 2951},
- {"cvmx_ilk_rx#_idx_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 7022, 4, 2952},
- {"cvmx_ilk_rx#_idx_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 7024, 6, 2956},
- {"cvmx_ilk_rx#_idx_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 7026, 6, 2962},
- {"cvmx_ilk_rx#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 7028, 10, 2968},
- {"cvmx_ilk_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 7030, 10, 2978},
- {"cvmx_ilk_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 7032, 2, 2988},
- {"cvmx_ilk_rx#_mem_cal0" , CVMX_CSR_DB_TYPE_RSL, 64, 7034, 9, 2990},
- {"cvmx_ilk_rx#_mem_cal1" , CVMX_CSR_DB_TYPE_RSL, 64, 7036, 9, 2999},
- {"cvmx_ilk_rx#_mem_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 7038, 2, 3008},
- {"cvmx_ilk_rx#_mem_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 7040, 2, 3010},
- {"cvmx_ilk_rx#_rid" , CVMX_CSR_DB_TYPE_RSL, 64, 7042, 2, 3012},
- {"cvmx_ilk_rx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 7044, 2, 3014},
- {"cvmx_ilk_rx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 7046, 2, 3016},
- {"cvmx_ilk_rx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 7048, 4, 3018},
- {"cvmx_ilk_rx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 7050, 2, 3022},
- {"cvmx_ilk_rx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 7052, 2, 3024},
- {"cvmx_ilk_rx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 7054, 2, 3026},
- {"cvmx_ilk_rx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 7056, 2, 3028},
- {"cvmx_ilk_rx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 7058, 2, 3030},
- {"cvmx_ilk_rx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 7060, 3, 3032},
- {"cvmx_ilk_rx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 7062, 1, 3035},
- {"cvmx_ilk_rx_lne#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 7064, 9, 3036},
- {"cvmx_ilk_rx_lne#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 7072, 10, 3045},
- {"cvmx_ilk_rx_lne#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 7080, 10, 3055},
- {"cvmx_ilk_rx_lne#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 7088, 2, 3065},
- {"cvmx_ilk_rx_lne#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 7096, 2, 3067},
- {"cvmx_ilk_rx_lne#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 7104, 4, 3069},
- {"cvmx_ilk_rx_lne#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 7112, 2, 3073},
- {"cvmx_ilk_rx_lne#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 7120, 4, 3075},
- {"cvmx_ilk_rx_lne#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 7128, 2, 3079},
- {"cvmx_ilk_rx_lne#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 7136, 2, 3081},
- {"cvmx_ilk_rx_lne#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 7144, 2, 3083},
- {"cvmx_ilk_rx_lne#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 7152, 2, 3085},
- {"cvmx_ilk_rx_lne#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 7160, 4, 3087},
- {"cvmx_ilk_rxf_idx_pmap" , CVMX_CSR_DB_TYPE_RSL, 64, 7168, 4, 3091},
- {"cvmx_ilk_rxf_mem_pmap" , CVMX_CSR_DB_TYPE_RSL, 64, 7169, 2, 3095},
- {"cvmx_ilk_ser_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 7170, 12, 3097},
- {"cvmx_ilk_tx#_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 7171, 17, 3109},
- {"cvmx_ilk_tx#_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 7173, 16, 3126},
- {"cvmx_ilk_tx#_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 7175, 4, 3142},
- {"cvmx_ilk_tx#_flow_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 7177, 1, 3146},
- {"cvmx_ilk_tx#_flow_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 7179, 1, 3147},
- {"cvmx_ilk_tx#_idx_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 7181, 4, 3148},
- {"cvmx_ilk_tx#_idx_pmap" , CVMX_CSR_DB_TYPE_RSL, 64, 7183, 4, 3152},
- {"cvmx_ilk_tx#_idx_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 7185, 6, 3156},
- {"cvmx_ilk_tx#_idx_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 7187, 6, 3162},
- {"cvmx_ilk_tx#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 7189, 5, 3168},
- {"cvmx_ilk_tx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 7191, 5, 3173},
- {"cvmx_ilk_tx#_mem_cal0" , CVMX_CSR_DB_TYPE_RSL, 64, 7193, 13, 3178},
- {"cvmx_ilk_tx#_mem_cal1" , CVMX_CSR_DB_TYPE_RSL, 64, 7195, 13, 3191},
- {"cvmx_ilk_tx#_mem_pmap" , CVMX_CSR_DB_TYPE_RSL, 64, 7197, 4, 3204},
- {"cvmx_ilk_tx#_mem_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 7199, 2, 3208},
- {"cvmx_ilk_tx#_mem_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 7201, 2, 3210},
- {"cvmx_ilk_tx#_pipe" , CVMX_CSR_DB_TYPE_RSL, 64, 7203, 4, 3212},
- {"cvmx_ilk_tx#_rmatch" , CVMX_CSR_DB_TYPE_RSL, 64, 7205, 5, 3216},
- {"cvmx_iob1_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7207, 9, 3221},
- {"cvmx_iob1_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7208, 4, 3230},
- {"cvmx_iob1_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 7209, 4, 3234},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7210, 19, 3238},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7211, 9, 3257},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 7212, 3, 3266},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 7213, 5, 3269},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 7214, 5, 3274},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 7215, 1, 3279},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 7216, 1, 3280},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 7217, 1, 3281},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 7218, 1, 3282},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 7219, 3, 3283},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 7220, 5, 3286},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 7221, 5, 3291},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 7222, 1, 3296},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 7223, 1, 3297},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 7224, 3, 3298},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 7225, 3, 3301},
- {"cvmx_iob_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 7226, 4, 3304},
- {"cvmx_iob_to_ncb_did_00_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7227, 2, 3308},
- {"cvmx_iob_to_ncb_did_111_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7228, 2, 3310},
- {"cvmx_iob_to_ncb_did_223_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7229, 2, 3312},
- {"cvmx_iob_to_ncb_did_24_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7230, 2, 3314},
- {"cvmx_iob_to_ncb_did_32_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7231, 2, 3316},
- {"cvmx_iob_to_ncb_did_40_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7232, 2, 3318},
- {"cvmx_iob_to_ncb_did_55_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7233, 2, 3320},
- {"cvmx_iob_to_ncb_did_64_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7234, 2, 3322},
- {"cvmx_iob_to_ncb_did_79_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7235, 2, 3324},
- {"cvmx_iob_to_ncb_did_96_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7236, 2, 3326},
- {"cvmx_iob_to_ncb_did_98_credits", CVMX_CSR_DB_TYPE_RSL, 64, 7237, 2, 3328},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 7238, 2, 3330},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 7239, 2, 3332},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 7240, 2, 3334},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 7241, 24, 3336},
- {"cvmx_ipd_bpid#_mbuf_th" , CVMX_CSR_DB_TYPE_NCB, 64, 7242, 3, 3360},
- {"cvmx_ipd_bpid_bp_counter#" , CVMX_CSR_DB_TYPE_NCB, 64, 7306, 2, 3363},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 7370, 1, 3365},
- {"cvmx_ipd_credits" , CVMX_CSR_DB_TYPE_NCB, 64, 7371, 3, 3366},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 7372, 18, 3369},
- {"cvmx_ipd_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 7373, 5, 3387},
- {"cvmx_ipd_free_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 7374, 6, 3392},
- {"cvmx_ipd_free_ptr_value" , CVMX_CSR_DB_TYPE_NCB, 64, 7375, 2, 3398},
- {"cvmx_ipd_hold_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 7376, 6, 3400},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 7377, 24, 3406},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 7378, 24, 3430},
- {"cvmx_ipd_next_pkt_ptr" , CVMX_CSR_DB_TYPE_NCB, 64, 7379, 2, 3454},
- {"cvmx_ipd_next_wqe_ptr" , CVMX_CSR_DB_TYPE_NCB, 64, 7380, 2, 3456},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 7381, 2, 3458},
- {"cvmx_ipd_on_bp_drop_pkt#" , CVMX_CSR_DB_TYPE_NCB, 64, 7382, 1, 3460},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 7383, 2, 3461},
- {"cvmx_ipd_pkt_err" , CVMX_CSR_DB_TYPE_NCB, 64, 7384, 2, 3463},
- {"cvmx_ipd_port_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 7385, 5, 3465},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 7386, 2, 3470},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 7898, 1, 3472},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 7906, 1, 3473},
- {"cvmx_ipd_port_sop#" , CVMX_CSR_DB_TYPE_NCB, 64, 7914, 1, 3474},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 7915, 6, 3475},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 7916, 2, 3481},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 7924, 2, 3483},
- {"cvmx_ipd_red_bpid_enable#" , CVMX_CSR_DB_TYPE_NCB, 64, 7925, 1, 3485},
- {"cvmx_ipd_red_delay" , CVMX_CSR_DB_TYPE_NCB, 64, 7926, 3, 3486},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 7927, 5, 3489},
- {"cvmx_ipd_req_wgt" , CVMX_CSR_DB_TYPE_NCB, 64, 7935, 8, 3494},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 7936, 3, 3502},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 7937, 3, 3505},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 7938, 2, 3508},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7939, 4, 3510},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7940, 3, 3514},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 7941, 5, 3517},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 7942, 5, 3522},
- {"cvmx_l2c_big_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7943, 4, 3527},
- {"cvmx_l2c_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 7944, 9, 3531},
- {"cvmx_l2c_bst_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 7945, 5, 3540},
- {"cvmx_l2c_bst_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 7949, 5, 3545},
- {"cvmx_l2c_bst_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 7953, 3, 3550},
- {"cvmx_l2c_cop0_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 7957, 1, 3553},
- {"cvmx_l2c_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 16405, 16, 3554},
- {"cvmx_l2c_dut_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 16406, 4, 3570},
- {"cvmx_l2c_err_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 24598, 9, 3574},
- {"cvmx_l2c_err_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 24602, 9, 3583},
- {"cvmx_l2c_err_vbf#" , CVMX_CSR_DB_TYPE_RSL, 64, 24606, 6, 3592},
- {"cvmx_l2c_err_xmc" , CVMX_CSR_DB_TYPE_RSL, 64, 24610, 5, 3598},
- {"cvmx_l2c_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 24611, 9, 3603},
- {"cvmx_l2c_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 24612, 14, 3612},
- {"cvmx_l2c_ioc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 24613, 1, 3626},
- {"cvmx_l2c_ior#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 24614, 1, 3627},
- {"cvmx_l2c_qos_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 24615, 4, 3628},
- {"cvmx_l2c_qos_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 24617, 2, 3632},
- {"cvmx_l2c_qos_wgt" , CVMX_CSR_DB_TYPE_RSL, 64, 24649, 8, 3634},
- {"cvmx_l2c_rsc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 24650, 1, 3642},
- {"cvmx_l2c_rsd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 24654, 1, 3643},
- {"cvmx_l2c_tad#_ecc0" , CVMX_CSR_DB_TYPE_RSL, 64, 24658, 8, 3644},
- {"cvmx_l2c_tad#_ecc1" , CVMX_CSR_DB_TYPE_RSL, 64, 24662, 8, 3652},
- {"cvmx_l2c_tad#_ien" , CVMX_CSR_DB_TYPE_RSL, 64, 24666, 10, 3660},
- {"cvmx_l2c_tad#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 24670, 10, 3670},
- {"cvmx_l2c_tad#_pfc0" , CVMX_CSR_DB_TYPE_RSL, 64, 24674, 1, 3680},
- {"cvmx_l2c_tad#_pfc1" , CVMX_CSR_DB_TYPE_RSL, 64, 24678, 1, 3681},
- {"cvmx_l2c_tad#_pfc2" , CVMX_CSR_DB_TYPE_RSL, 64, 24682, 1, 3682},
- {"cvmx_l2c_tad#_pfc3" , CVMX_CSR_DB_TYPE_RSL, 64, 24686, 1, 3683},
- {"cvmx_l2c_tad#_prf" , CVMX_CSR_DB_TYPE_RSL, 64, 24690, 5, 3684},
- {"cvmx_l2c_tad#_tag" , CVMX_CSR_DB_TYPE_RSL, 64, 24694, 9, 3689},
- {"cvmx_l2c_ver_id" , CVMX_CSR_DB_TYPE_RSL, 64, 24698, 1, 3698},
- {"cvmx_l2c_ver_iob" , CVMX_CSR_DB_TYPE_RSL, 64, 24699, 2, 3699},
- {"cvmx_l2c_ver_msc" , CVMX_CSR_DB_TYPE_RSL, 64, 24700, 3, 3701},
- {"cvmx_l2c_ver_pp" , CVMX_CSR_DB_TYPE_RSL, 64, 24701, 2, 3704},
- {"cvmx_l2c_virtid_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 24702, 4, 3706},
- {"cvmx_l2c_virtid_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 24704, 2, 3710},
- {"cvmx_l2c_vrt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 24736, 6, 3712},
- {"cvmx_l2c_vrt_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 24737, 3, 3718},
- {"cvmx_l2c_wpar_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 25761, 2, 3721},
- {"cvmx_l2c_wpar_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 25763, 2, 3723},
- {"cvmx_l2c_xmc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 25795, 1, 3725},
- {"cvmx_l2c_xmc_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 25799, 4, 3726},
- {"cvmx_l2c_xmd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 25800, 1, 3730},
- {"cvmx_lmc#_char_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25804, 7, 3731},
- {"cvmx_lmc#_char_mask0" , CVMX_CSR_DB_TYPE_RSL, 64, 25808, 1, 3738},
- {"cvmx_lmc#_char_mask1" , CVMX_CSR_DB_TYPE_RSL, 64, 25812, 2, 3739},
- {"cvmx_lmc#_char_mask2" , CVMX_CSR_DB_TYPE_RSL, 64, 25816, 1, 3741},
- {"cvmx_lmc#_char_mask3" , CVMX_CSR_DB_TYPE_RSL, 64, 25820, 2, 3742},
- {"cvmx_lmc#_char_mask4" , CVMX_CSR_DB_TYPE_RSL, 64, 25824, 12, 3744},
- {"cvmx_lmc#_comp_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 25828, 11, 3756},
- {"cvmx_lmc#_config" , CVMX_CSR_DB_TYPE_RSL, 64, 25832, 21, 3767},
- {"cvmx_lmc#_control" , CVMX_CSR_DB_TYPE_RSL, 64, 25836, 26, 3788},
- {"cvmx_lmc#_dclk_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 25840, 1, 3814},
- {"cvmx_lmc#_ddr_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25844, 11, 3815},
- {"cvmx_lmc#_dimm#_params" , CVMX_CSR_DB_TYPE_RSL, 64, 25848, 16, 3826},
- {"cvmx_lmc#_dimm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25856, 5, 3842},
- {"cvmx_lmc#_dll_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 25860, 7, 3847},
- {"cvmx_lmc#_dll_ctl3" , CVMX_CSR_DB_TYPE_RSL, 64, 25864, 16, 3854},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 25868, 4, 3870},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 25872, 5, 3874},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 25876, 6, 3879},
- {"cvmx_lmc#_ifb_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 25880, 1, 3885},
- {"cvmx_lmc#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 25884, 4, 3886},
- {"cvmx_lmc#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 25888, 4, 3890},
- {"cvmx_lmc#_modereg_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 25892, 16, 3894},
- {"cvmx_lmc#_modereg_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 25896, 25, 3910},
- {"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 25900, 10, 3935},
- {"cvmx_lmc#_ops_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 25904, 1, 3945},
- {"cvmx_lmc#_phy_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25908, 10, 3946},
- {"cvmx_lmc#_reset_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25912, 5, 3956},
- {"cvmx_lmc#_rlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25916, 10, 3961},
- {"cvmx_lmc#_rlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 25920, 1, 3971},
- {"cvmx_lmc#_rlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 25924, 11, 3972},
- {"cvmx_lmc#_rodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 25940, 8, 3983},
- {"cvmx_lmc#_slot_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 25944, 5, 3991},
- {"cvmx_lmc#_slot_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 25948, 5, 3996},
- {"cvmx_lmc#_slot_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 25952, 5, 4001},
- {"cvmx_lmc#_timing_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 25956, 12, 4006},
- {"cvmx_lmc#_timing_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 25960, 13, 4018},
- {"cvmx_lmc#_tro_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25964, 3, 4031},
- {"cvmx_lmc#_tro_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 25968, 2, 4034},
- {"cvmx_lmc#_wlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 25972, 6, 4036},
- {"cvmx_lmc#_wlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 25976, 3, 4042},
- {"cvmx_lmc#_wlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 25980, 11, 4045},
- {"cvmx_lmc#_wodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 25996, 8, 4056},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 26000, 2, 4064},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 26001, 3, 4066},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 26002, 10, 4069},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 26004, 3, 4079},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 26006, 3, 4082},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 26008, 15, 4085},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 26010, 3, 4100},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 26011, 3, 4103},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 26012, 3, 4106},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 26013, 5, 4109},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 26015, 1, 4114},
- {"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 26016, 9, 4115},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 26017, 13, 4124},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 26025, 13, 4137},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 26033, 6, 4150},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 26034, 1, 4156},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 26036, 2, 4157},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 26037, 2, 4159},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 26038, 12, 4161},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 26039, 18, 4173},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 26040, 4, 4191},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 26041, 1, 4195},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 26042, 10, 4196},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 26043, 3, 4206},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 26044, 8, 4209},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 26045, 7, 4217},
- {"cvmx_mio_fus_read_times" , CVMX_CSR_DB_TYPE_RSL, 64, 26046, 6, 4224},
- {"cvmx_mio_fus_repair_res0" , CVMX_CSR_DB_TYPE_RSL, 64, 26047, 5, 4230},
- {"cvmx_mio_fus_repair_res1" , CVMX_CSR_DB_TYPE_RSL, 64, 26048, 4, 4235},
- {"cvmx_mio_fus_repair_res2" , CVMX_CSR_DB_TYPE_RSL, 64, 26049, 2, 4239},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 26050, 4, 4241},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 26051, 2, 4245},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 26052, 2, 4247},
- {"cvmx_mio_gpio_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 26053, 3, 4249},
- {"cvmx_mio_ndf_dma_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 26054, 10, 4252},
- {"cvmx_mio_ndf_dma_int" , CVMX_CSR_DB_TYPE_RSL, 64, 26055, 2, 4262},
- {"cvmx_mio_ndf_dma_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 26056, 2, 4264},
- {"cvmx_mio_ptp_ckout_hi_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 26057, 2, 4266},
- {"cvmx_mio_ptp_ckout_lo_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 26058, 2, 4268},
- {"cvmx_mio_ptp_ckout_thresh_hi", CVMX_CSR_DB_TYPE_NCB, 64, 26059, 1, 4270},
- {"cvmx_mio_ptp_ckout_thresh_lo", CVMX_CSR_DB_TYPE_NCB, 64, 26060, 2, 4271},
- {"cvmx_mio_ptp_clock_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 26061, 20, 4273},
- {"cvmx_mio_ptp_clock_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 26062, 2, 4293},
- {"cvmx_mio_ptp_clock_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 26063, 1, 4295},
- {"cvmx_mio_ptp_clock_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 26064, 2, 4296},
- {"cvmx_mio_ptp_evt_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 26065, 1, 4298},
- {"cvmx_mio_ptp_pps_hi_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 26066, 2, 4299},
- {"cvmx_mio_ptp_pps_lo_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 26067, 2, 4301},
- {"cvmx_mio_ptp_pps_thresh_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 26068, 1, 4303},
- {"cvmx_mio_ptp_pps_thresh_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 26069, 2, 4304},
- {"cvmx_mio_ptp_timestamp" , CVMX_CSR_DB_TYPE_NCB, 64, 26070, 1, 4306},
- {"cvmx_mio_qlm#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 26071, 4, 4307},
- {"cvmx_mio_rst_boot" , CVMX_CSR_DB_TYPE_RSL, 64, 26076, 13, 4311},
- {"cvmx_mio_rst_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 26077, 5, 4324},
- {"cvmx_mio_rst_cntl#" , CVMX_CSR_DB_TYPE_RSL, 64, 26078, 10, 4329},
- {"cvmx_mio_rst_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 26080, 10, 4339},
- {"cvmx_mio_rst_delay" , CVMX_CSR_DB_TYPE_RSL, 64, 26082, 3, 4349},
- {"cvmx_mio_rst_int" , CVMX_CSR_DB_TYPE_RSL, 64, 26083, 6, 4352},
- {"cvmx_mio_rst_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 26084, 6, 4358},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 26085, 13, 4364},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 26087, 12, 4377},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 26089, 3, 4389},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 26091, 3, 4392},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 26093, 2, 4395},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 26095, 2, 4397},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 26097, 2, 4399},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 26099, 7, 4401},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 26101, 2, 4408},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 26103, 7, 4410},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 26105, 4, 4417},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 26107, 8, 4421},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 26109, 9, 4429},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 26111, 7, 4438},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 26113, 9, 4445},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 26115, 2, 4454},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 26117, 2, 4456},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 26119, 4, 4458},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 26121, 2, 4462},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 26123, 2, 4464},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 26125, 2, 4466},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 26127, 4, 4468},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 26129, 2, 4472},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 26131, 2, 4474},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 26133, 2, 4476},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 26135, 2, 4478},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 26137, 2, 4480},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 26139, 2, 4482},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 26141, 6, 4484},
- {"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 26143, 7, 4490},
- {"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 26144, 9, 4497},
- {"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 26145, 9, 4506},
- {"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 26146, 2, 4515},
- {"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 26147, 3, 4517},
- {"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 26148, 4, 4520},
- {"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 26149, 4, 4524},
- {"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 26150, 9, 4528},
- {"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 26151, 2, 4537},
- {"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 26152, 2, 4539},
- {"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 26153, 4, 4541},
- {"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 26154, 4, 4545},
- {"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 26155, 4, 4549},
- {"cvmx_mix#_tsctl" , CVMX_CSR_DB_TYPE_NCB, 64, 26156, 6, 4553},
- {"cvmx_mix#_tstamp" , CVMX_CSR_DB_TYPE_NCB, 64, 26157, 1, 4559},
- {"cvmx_ndf_bt_pg_info" , CVMX_CSR_DB_TYPE_NCB, 64, 26158, 4, 4560},
- {"cvmx_ndf_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 26159, 1, 4564},
- {"cvmx_ndf_drbell" , CVMX_CSR_DB_TYPE_NCB, 64, 26160, 2, 4565},
- {"cvmx_ndf_ecc_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 26161, 3, 4567},
- {"cvmx_ndf_int" , CVMX_CSR_DB_TYPE_NCB, 64, 26162, 8, 4570},
- {"cvmx_ndf_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 26163, 8, 4578},
- {"cvmx_ndf_misc" , CVMX_CSR_DB_TYPE_NCB, 64, 26164, 12, 4586},
- {"cvmx_ndf_st_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 26165, 8, 4598},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26166, 2, 4606},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26168, 24, 4608},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26170, 4, 4632},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26172, 5, 4636},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26174, 5, 4641},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26176, 2, 4646},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26178, 1, 4648},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26180, 1, 4649},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26182, 5, 4650},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26184, 2, 4655},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26186, 1, 4657},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26188, 1, 4658},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26190, 4, 4659},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26192, 2, 4663},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26194, 2, 4665},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26196, 1, 4667},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26198, 1, 4668},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26200, 2, 4669},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26202, 3, 4671},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26204, 2, 4674},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26206, 2, 4676},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26208, 4, 4678},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26210, 10, 4682},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26212, 12, 4692},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26214, 8, 4704},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26216, 2, 4712},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26218, 1, 4714},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26220, 2, 4715},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26222, 7, 4717},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26224, 12, 4724},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26226, 19, 4736},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26228, 12, 4755},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26230, 20, 4767},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26232, 11, 4787},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26234, 8, 4798},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26236, 4, 4806},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26238, 11, 4810},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26240, 3, 4821},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26242, 16, 4824},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26244, 16, 4840},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26246, 16, 4856},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26248, 9, 4872},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26250, 9, 4881},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26252, 6, 4890},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26254, 1, 4896},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26256, 1, 4897},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26258, 1, 4898},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26260, 1, 4899},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26262, 2, 4900},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26264, 1, 4902},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26266, 6, 4903},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26268, 7, 4909},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26270, 11, 4916},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26272, 5, 4927},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26274, 6, 4932},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26276, 19, 4938},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26278, 5, 4957},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26280, 1, 4962},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26282, 1, 4963},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26284, 3, 4964},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26286, 3, 4967},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26288, 3, 4970},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26290, 4, 4973},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26292, 4, 4977},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26294, 4, 4981},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26296, 7, 4985},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26298, 5, 4992},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26300, 5, 4997},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26302, 4, 5002},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26304, 4, 5006},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26306, 4, 5010},
- {"cvmx_pcieep#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26308, 7, 5014},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26310, 1, 5021},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 26312, 1, 5022},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26314, 2, 5023},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26316, 24, 5025},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26318, 4, 5049},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26320, 5, 5053},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26322, 1, 5058},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26324, 1, 5059},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26326, 4, 5060},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26328, 17, 5064},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26330, 4, 5081},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26332, 6, 5085},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26334, 1, 5091},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26336, 1, 5092},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26338, 2, 5093},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26340, 2, 5095},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26342, 1, 5097},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26344, 15, 5098},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26346, 10, 5113},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26348, 12, 5123},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26350, 7, 5135},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26352, 2, 5142},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26354, 1, 5144},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26356, 2, 5145},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26358, 7, 5147},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26360, 11, 5154},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26362, 19, 5165},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26364, 12, 5184},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26366, 20, 5196},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26368, 12, 5216},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26370, 22, 5228},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26372, 8, 5250},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26374, 4, 5258},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26376, 11, 5262},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26378, 8, 5273},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26380, 4, 5281},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26382, 11, 5285},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26384, 1, 5296},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26386, 1, 5297},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26388, 3, 5298},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26390, 16, 5301},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26392, 16, 5317},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26394, 16, 5333},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26396, 9, 5349},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26398, 9, 5358},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26400, 6, 5367},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26402, 1, 5373},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26404, 1, 5374},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26406, 1, 5375},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26408, 1, 5376},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26410, 4, 5377},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26412, 9, 5381},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26414, 2, 5390},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26416, 2, 5392},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26418, 1, 5394},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26420, 6, 5395},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26422, 7, 5401},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26424, 11, 5408},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26426, 5, 5419},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26428, 6, 5424},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26430, 19, 5430},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26432, 5, 5449},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26434, 1, 5454},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26436, 1, 5455},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26438, 3, 5456},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26440, 3, 5459},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26442, 3, 5462},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26444, 4, 5465},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26446, 4, 5469},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26448, 4, 5473},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26450, 7, 5477},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26452, 5, 5484},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26454, 5, 5489},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26456, 4, 5494},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26458, 4, 5498},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26460, 4, 5502},
- {"cvmx_pcierc#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26462, 7, 5506},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26464, 1, 5513},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 26466, 1, 5514},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26468, 9, 5515},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26488, 6, 5524},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26508, 9, 5530},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26528, 6, 5539},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26548, 14, 5545},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26568, 14, 5559},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 26588, 2, 5573},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26608, 4, 5575},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26628, 8, 5579},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26648, 13, 5587},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26668, 17, 5600},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26688, 7, 5617},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26708, 3, 5624},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26728, 8, 5627},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26748, 7, 5635},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26768, 4, 5642},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 26788, 5, 5646},
- {"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26808, 8, 5651},
- {"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26813, 2, 5659},
- {"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 26818, 5, 5661},
- {"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26823, 10, 5666},
- {"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26828, 2, 5676},
- {"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26833, 8, 5678},
- {"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26838, 8, 5686},
- {"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26843, 6, 5694},
- {"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26848, 5, 5700},
- {"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 26853, 5, 5705},
- {"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26858, 3, 5710},
- {"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26863, 6, 5713},
- {"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26868, 9, 5719},
- {"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 26873, 5, 5728},
- {"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 26878, 10, 5733},
- {"cvmx_pem#_bar1_index#" , CVMX_CSR_DB_TYPE_RSL, 64, 26883, 5, 5743},
- {"cvmx_pem#_bar2_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 26915, 3, 5748},
- {"cvmx_pem#_bar_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 26917, 5, 5751},
- {"cvmx_pem#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 26919, 9, 5756},
- {"cvmx_pem#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 26921, 11, 5765},
- {"cvmx_pem#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 26923, 2, 5776},
- {"cvmx_pem#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 26925, 2, 5778},
- {"cvmx_pem#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 26927, 2, 5780},
- {"cvmx_pem#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 26929, 18, 5782},
- {"cvmx_pem#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 26931, 32, 5800},
- {"cvmx_pem#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 26933, 32, 5832},
- {"cvmx_pem#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 26935, 5, 5864},
- {"cvmx_pem#_inb_read_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 26937, 2, 5869},
- {"cvmx_pem#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 26939, 15, 5871},
- {"cvmx_pem#_int_enb_int" , CVMX_CSR_DB_TYPE_RSL, 64, 26941, 15, 5886},
- {"cvmx_pem#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 26943, 15, 5901},
- {"cvmx_pem#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 26945, 2, 5916},
- {"cvmx_pem#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 26947, 2, 5918},
- {"cvmx_pem#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 26949, 2, 5920},
- {"cvmx_pem#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 26951, 2, 5922},
- {"cvmx_pem#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 26959, 2, 5924},
- {"cvmx_pem#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 26967, 8, 5926},
- {"cvmx_pip_alt_skip_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 26969, 12, 5934},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 26973, 5, 5946},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 26974, 2, 5951},
- {"cvmx_pip_bsel_ext_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 26975, 7, 5953},
- {"cvmx_pip_bsel_ext_pos#" , CVMX_CSR_DB_TYPE_RSL, 64, 26979, 16, 5960},
- {"cvmx_pip_bsel_tbl_ent#" , CVMX_CSR_DB_TYPE_RSL, 64, 26983, 12, 5976},
- {"cvmx_pip_clken" , CVMX_CSR_DB_TYPE_RSL, 64, 27495, 2, 5988},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 27496, 4, 5990},
- {"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 27500, 16, 5994},
- {"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 27501, 16, 6010},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 27502, 3, 6026},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 27504, 8, 6029},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 27505, 22, 6037},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 27506, 14, 6059},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 27507, 14, 6073},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 27508, 2, 6087},
- {"cvmx_pip_pri_tbl#" , CVMX_CSR_DB_TYPE_RSL, 64, 27509, 15, 6089},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 27765, 30, 6104},
- {"cvmx_pip_prt_cfgb#" , CVMX_CSR_DB_TYPE_RSL, 64, 27829, 10, 6134},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 27893, 33, 6144},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 27957, 9, 6177},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 27965, 2, 6186},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 27966, 2, 6188},
- {"cvmx_pip_stat0_#" , CVMX_CSR_DB_TYPE_RSL, 64, 27967, 2, 6190},
- {"cvmx_pip_stat10_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28031, 2, 6192},
- {"cvmx_pip_stat11_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28095, 2, 6194},
- {"cvmx_pip_stat1_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28159, 2, 6196},
- {"cvmx_pip_stat2_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28223, 2, 6198},
- {"cvmx_pip_stat3_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28287, 2, 6200},
- {"cvmx_pip_stat4_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28351, 2, 6202},
- {"cvmx_pip_stat5_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28415, 2, 6204},
- {"cvmx_pip_stat6_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28479, 2, 6206},
- {"cvmx_pip_stat7_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28543, 2, 6208},
- {"cvmx_pip_stat8_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28607, 2, 6210},
- {"cvmx_pip_stat9_#" , CVMX_CSR_DB_TYPE_RSL, 64, 28671, 2, 6212},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 28735, 4, 6214},
- {"cvmx_pip_stat_inb_errs_pknd#", CVMX_CSR_DB_TYPE_RSL, 64, 28736, 2, 6218},
- {"cvmx_pip_stat_inb_octs_pknd#", CVMX_CSR_DB_TYPE_RSL, 64, 28800, 2, 6220},
- {"cvmx_pip_stat_inb_pkts_pknd#", CVMX_CSR_DB_TYPE_RSL, 64, 28864, 2, 6222},
- {"cvmx_pip_sub_pkind_fcs#" , CVMX_CSR_DB_TYPE_RSL, 64, 28928, 1, 6224},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 28929, 2, 6225},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 28993, 2, 6227},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 28994, 3, 6229},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 28995, 3, 6232},
- {"cvmx_pip_vlan_etypes#" , CVMX_CSR_DB_TYPE_RSL, 64, 28996, 4, 6235},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 28998, 2, 6239},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 28999, 2, 6241},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 29000, 4, 6243},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 29001, 5, 6247},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 29002, 4, 6252},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 29003, 8, 6256},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 29004, 1, 6264},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 29005, 1, 6265},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 29006, 5, 6266},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 29007, 1, 6271},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 29008, 13, 6272},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 29009, 7, 6285},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 29010, 13, 6292},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 29011, 6, 6305},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 29012, 9, 6311},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 29013, 4, 6320},
- {"cvmx_pko_mem_iport_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 29014, 13, 6324},
- {"cvmx_pko_mem_iport_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 29015, 6, 6337},
- {"cvmx_pko_mem_iqueue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 29016, 10, 6343},
- {"cvmx_pko_mem_iqueue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 29017, 5, 6353},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 29018, 5, 6358},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 29019, 4, 6363},
- {"cvmx_pko_mem_throttle_int" , CVMX_CSR_DB_TYPE_RSL, 64, 29020, 6, 6367},
- {"cvmx_pko_mem_throttle_pipe" , CVMX_CSR_DB_TYPE_RSL, 64, 29021, 6, 6373},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 29022, 20, 6379},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 29023, 4, 6399},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 29024, 1, 6403},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 29025, 1, 6404},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 29026, 1, 6405},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 29027, 1, 6406},
- {"cvmx_pko_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 29028, 1, 6407},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 29029, 16, 6408},
- {"cvmx_pko_reg_engine_inflight1", CVMX_CSR_DB_TYPE_RSL, 64, 29030, 5, 6424},
- {"cvmx_pko_reg_engine_storage#", CVMX_CSR_DB_TYPE_RSL, 64, 29031, 16, 6429},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 29033, 2, 6445},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 29034, 5, 6447},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 29035, 10, 6452},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 29036, 5, 6462},
- {"cvmx_pko_reg_loopback_bpid" , CVMX_CSR_DB_TYPE_RSL, 64, 29037, 17, 6467},
- {"cvmx_pko_reg_loopback_pkind" , CVMX_CSR_DB_TYPE_RSL, 64, 29038, 17, 6484},
- {"cvmx_pko_reg_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 29039, 8, 6501},
- {"cvmx_pko_reg_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 29040, 2, 6509},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 29041, 2, 6511},
- {"cvmx_pko_reg_queue_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 29042, 3, 6513},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 29043, 3, 6516},
- {"cvmx_pko_reg_throttle" , CVMX_CSR_DB_TYPE_RSL, 64, 29044, 2, 6519},
- {"cvmx_pko_reg_timestamp" , CVMX_CSR_DB_TYPE_RSL, 64, 29045, 2, 6521},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 29046, 1, 6523},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 29047, 1, 6524},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 29048, 1, 6525},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 29049, 5, 6526},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 29050, 5, 6531},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 29051, 4, 6536},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 29052, 10, 6540},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 29053, 1, 6550},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 29054, 3, 6551},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 29055, 7, 6554},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 29056, 2, 6561},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 29057, 1, 6563},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 29058, 1, 6564},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 29059, 1, 6565},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 29060, 18, 6566},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 29061, 3, 6584},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 29062, 2, 6587},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 29063, 3, 6589},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 29064, 7, 6592},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 29065, 2, 6599},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 29066, 2, 6601},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 29067, 2, 6603},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 29068, 3, 6605},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 29069, 3, 6608},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 29070, 9, 6611},
- {"cvmx_rnm_eer_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 29071, 1, 6620},
- {"cvmx_rnm_eer_key" , CVMX_CSR_DB_TYPE_RSL, 64, 29072, 1, 6621},
- {"cvmx_rnm_serial_num" , CVMX_CSR_DB_TYPE_RSL, 64, 29073, 1, 6622},
- {"cvmx_sli_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29074, 26, 6623},
- {"cvmx_sli_ctl_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29075, 16, 6649},
- {"cvmx_sli_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29077, 4, 6665},
- {"cvmx_sli_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29078, 5, 6669},
- {"cvmx_sli_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29079, 3, 6674},
- {"cvmx_sli_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29080, 3, 6677},
- {"cvmx_sli_dma#_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29081, 2, 6680},
- {"cvmx_sli_dma#_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29083, 2, 6682},
- {"cvmx_sli_dma#_tim" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29085, 2, 6684},
- {"cvmx_sli_int_enb_ciu" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29087, 36, 6686},
- {"cvmx_sli_int_enb_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29088, 38, 6722},
- {"cvmx_sli_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29090, 38, 6760},
- {"cvmx_sli_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29091, 1, 6798},
- {"cvmx_sli_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29092, 1, 6799},
- {"cvmx_sli_mac_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29093, 13, 6800},
- {"cvmx_sli_mac_number" , CVMX_CSR_DB_TYPE_PEXP, 64, 29094, 2, 6813},
- {"cvmx_sli_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29095, 3, 6815},
- {"cvmx_sli_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29096, 10, 6818},
- {"cvmx_sli_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29112, 1, 6828},
- {"cvmx_sli_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29113, 1, 6829},
- {"cvmx_sli_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29114, 1, 6830},
- {"cvmx_sli_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29115, 1, 6831},
- {"cvmx_sli_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29116, 1, 6832},
- {"cvmx_sli_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29117, 1, 6833},
- {"cvmx_sli_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29118, 1, 6834},
- {"cvmx_sli_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29119, 1, 6835},
- {"cvmx_sli_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29120, 3, 6836},
- {"cvmx_sli_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29121, 1, 6839},
- {"cvmx_sli_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29122, 1, 6840},
- {"cvmx_sli_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29123, 1, 6841},
- {"cvmx_sli_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29124, 1, 6842},
- {"cvmx_sli_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29125, 1, 6843},
- {"cvmx_sli_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29126, 1, 6844},
- {"cvmx_sli_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29127, 1, 6845},
- {"cvmx_sli_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29128, 1, 6846},
- {"cvmx_sli_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29129, 3, 6847},
- {"cvmx_sli_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29130, 2, 6850},
- {"cvmx_sli_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29131, 3, 6852},
- {"cvmx_sli_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29132, 3, 6855},
- {"cvmx_sli_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29133, 3, 6858},
- {"cvmx_sli_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29134, 3, 6861},
- {"cvmx_sli_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29166, 2, 6864},
- {"cvmx_sli_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29198, 2, 6866},
- {"cvmx_sli_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29230, 5, 6868},
- {"cvmx_sli_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29262, 21, 6873},
- {"cvmx_sli_pkt#_out_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29294, 3, 6894},
- {"cvmx_sli_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29326, 2, 6897},
- {"cvmx_sli_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29358, 2, 6899},
- {"cvmx_sli_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29390, 2, 6901},
- {"cvmx_sli_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29422, 2, 6903},
- {"cvmx_sli_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29423, 2, 6905},
- {"cvmx_sli_pkt_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29424, 3, 6907},
- {"cvmx_sli_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29425, 1, 6910},
- {"cvmx_sli_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29426, 2, 6911},
- {"cvmx_sli_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29427, 2, 6913},
- {"cvmx_sli_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29428, 2, 6915},
- {"cvmx_sli_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29429, 2, 6917},
- {"cvmx_sli_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29461, 2, 6919},
- {"cvmx_sli_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29462, 1, 6921},
- {"cvmx_sli_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29463, 17, 6922},
- {"cvmx_sli_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29464, 2, 6939},
- {"cvmx_sli_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29465, 1, 6941},
- {"cvmx_sli_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29466, 2, 6942},
- {"cvmx_sli_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29467, 3, 6944},
- {"cvmx_sli_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29468, 2, 6947},
- {"cvmx_sli_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29469, 2, 6949},
- {"cvmx_sli_pkt_out_bp_en" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29470, 2, 6951},
- {"cvmx_sli_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29471, 2, 6953},
- {"cvmx_sli_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29472, 2, 6955},
- {"cvmx_sli_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29473, 1, 6957},
- {"cvmx_sli_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29474, 2, 6958},
- {"cvmx_sli_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29475, 1, 6960},
- {"cvmx_sli_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29476, 2, 6961},
- {"cvmx_sli_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29477, 2, 6963},
- {"cvmx_sli_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29478, 2, 6965},
- {"cvmx_sli_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29479, 2, 6967},
- {"cvmx_sli_port#_pkind" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29480, 8, 6969},
- {"cvmx_sli_s2m_port#_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29512, 4, 6977},
- {"cvmx_sli_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29514, 1, 6981},
- {"cvmx_sli_scratch_2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29515, 1, 6982},
- {"cvmx_sli_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29516, 4, 6983},
- {"cvmx_sli_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29517, 8, 6987},
- {"cvmx_sli_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29518, 5, 6995},
- {"cvmx_sli_tx_pipe" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29519, 4, 7000},
- {"cvmx_sli_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 29520, 4, 7004},
- {"cvmx_sli_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 29521, 1, 7008},
- {"cvmx_sli_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 29522, 4, 7009},
- {"cvmx_sli_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 29523, 1, 7013},
- {"cvmx_sli_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 29524, 2, 7014},
- {"cvmx_sli_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 29525, 2, 7016},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 29526, 10, 7018},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 29530, 6, 7028},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 29534, 2, 7034},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 29538, 4, 7036},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 29542, 4, 7040},
- {"cvmx_smi_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 29546, 4, 7044},
- {"cvmx_sso_active_cycles" , CVMX_CSR_DB_TYPE_NCB, 64, 29547, 1, 7048},
- {"cvmx_sso_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 29548, 21, 7049},
- {"cvmx_sso_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 29549, 15, 7070},
- {"cvmx_sso_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 29550, 1, 7085},
- {"cvmx_sso_err" , CVMX_CSR_DB_TYPE_NCB, 64, 29551, 19, 7086},
- {"cvmx_sso_err_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 29552, 19, 7105},
- {"cvmx_sso_fidx_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 29553, 3, 7124},
- {"cvmx_sso_fidx_ecc_st" , CVMX_CSR_DB_TYPE_NCB, 64, 29554, 5, 7127},
- {"cvmx_sso_fpage_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 29555, 2, 7132},
- {"cvmx_sso_gwe_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 29556, 11, 7134},
- {"cvmx_sso_idx_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 29557, 3, 7145},
- {"cvmx_sso_idx_ecc_st" , CVMX_CSR_DB_TYPE_NCB, 64, 29558, 5, 7148},
- {"cvmx_sso_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 29559, 2, 7153},
- {"cvmx_sso_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 29567, 2, 7155},
- {"cvmx_sso_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 29568, 2, 7157},
- {"cvmx_sso_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 29569, 2, 7159},
- {"cvmx_sso_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 29570, 2, 7161},
- {"cvmx_sso_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 29578, 2, 7163},
- {"cvmx_sso_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 29579, 2, 7165},
- {"cvmx_sso_oth_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 29580, 5, 7167},
- {"cvmx_sso_oth_ecc_st" , CVMX_CSR_DB_TYPE_NCB, 64, 29581, 9, 7172},
- {"cvmx_sso_pnd_ecc_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 29582, 5, 7181},
- {"cvmx_sso_pnd_ecc_st" , CVMX_CSR_DB_TYPE_NCB, 64, 29583, 9, 7186},
- {"cvmx_sso_pp#_grp_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 29584, 1, 7195},
- {"cvmx_sso_pp#_qos_pri" , CVMX_CSR_DB_TYPE_NCB, 64, 29616, 16, 7196},
- {"cvmx_sso_pp_strict" , CVMX_CSR_DB_TYPE_NCB, 64, 29648, 2, 7212},
- {"cvmx_sso_qos#_rnd" , CVMX_CSR_DB_TYPE_NCB, 64, 29649, 2, 7214},
- {"cvmx_sso_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 29657, 6, 7216},
- {"cvmx_sso_qos_we" , CVMX_CSR_DB_TYPE_NCB, 64, 29665, 4, 7222},
- {"cvmx_sso_reset" , CVMX_CSR_DB_TYPE_NCB, 64, 29666, 2, 7226},
- {"cvmx_sso_rwq_head_ptr#" , CVMX_CSR_DB_TYPE_NCB, 64, 29667, 4, 7228},
- {"cvmx_sso_rwq_pop_fptr" , CVMX_CSR_DB_TYPE_NCB, 64, 29675, 5, 7232},
- {"cvmx_sso_rwq_psh_fptr" , CVMX_CSR_DB_TYPE_NCB, 64, 29676, 5, 7237},
- {"cvmx_sso_rwq_tail_ptr#" , CVMX_CSR_DB_TYPE_NCB, 64, 29677, 4, 7242},
- {"cvmx_sso_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 29685, 1, 7246},
- {"cvmx_sso_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 29686, 1, 7247},
- {"cvmx_sso_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 29687, 1, 7248},
- {"cvmx_sso_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 29695, 1, 7249},
- {"cvmx_sso_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 29696, 6, 7250},
- {"cvmx_sso_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 29760, 5, 7256},
- {"cvmx_sso_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 29761, 7, 7261},
- {"cvmx_sso_wq_iq_dis" , CVMX_CSR_DB_TYPE_NCB, 64, 29825, 1, 7268},
- {"cvmx_sso_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 29826, 1, 7269},
- {"cvmx_tim_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 29890, 4, 7270},
- {"cvmx_tim_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 29891, 11, 7274},
- {"cvmx_tim_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 29892, 1, 7285},
- {"cvmx_tim_ecc_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 29893, 3, 7286},
- {"cvmx_tim_fr_rn_tt" , CVMX_CSR_DB_TYPE_RSL, 64, 29894, 4, 7289},
- {"cvmx_tim_gpio_en" , CVMX_CSR_DB_TYPE_RSL, 64, 29895, 1, 7293},
- {"cvmx_tim_int0" , CVMX_CSR_DB_TYPE_RSL, 64, 29896, 1, 7294},
- {"cvmx_tim_int0_en" , CVMX_CSR_DB_TYPE_RSL, 64, 29897, 1, 7295},
- {"cvmx_tim_int0_event" , CVMX_CSR_DB_TYPE_RSL, 64, 29898, 2, 7296},
- {"cvmx_tim_int_eccerr" , CVMX_CSR_DB_TYPE_RSL, 64, 29899, 3, 7298},
- {"cvmx_tim_int_eccerr_en" , CVMX_CSR_DB_TYPE_RSL, 64, 29900, 3, 7301},
- {"cvmx_tim_int_eccerr_event0" , CVMX_CSR_DB_TYPE_RSL, 64, 29901, 3, 7304},
- {"cvmx_tim_int_eccerr_event1" , CVMX_CSR_DB_TYPE_RSL, 64, 29902, 3, 7307},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 29903, 7, 7310},
- {"cvmx_tim_ring#_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 29904, 5, 7317},
- {"cvmx_tim_ring#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 29968, 8, 7322},
- {"cvmx_tim_ring#_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 30032, 4, 7330},
- {"cvmx_tim_ring#_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 30096, 3, 7334},
- {"cvmx_tim_ring#_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 30160, 2, 7337},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 30224, 2, 7339},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 30228, 14, 7341},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 30232, 3, 7355},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 30236, 5, 7358},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 30240, 2, 7363},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 30244, 2, 7365},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 30248, 57, 7367},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 30252, 20, 7424},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 30256, 7, 7444},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 30260, 5, 7451},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 30264, 1, 7456},
- {"cvmx_tra#_read_dat_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 30268, 2, 7457},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 30272, 2, 7459},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 30276, 2, 7461},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 30280, 57, 7463},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 30284, 20, 7520},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 30288, 7, 7540},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 30292, 2, 7547},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 30296, 2, 7549},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 30300, 57, 7551},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 30304, 20, 7608},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 30308, 7, 7628},
- {"cvmx_uahc#_ehci_asynclistaddr", CVMX_CSR_DB_TYPE_NCB, 32, 30312, 2, 7635},
- {"cvmx_uahc#_ehci_configflag" , CVMX_CSR_DB_TYPE_NCB, 32, 30313, 2, 7637},
- {"cvmx_uahc#_ehci_ctrldssegment", CVMX_CSR_DB_TYPE_NCB, 32, 30314, 1, 7639},
- {"cvmx_uahc#_ehci_frindex" , CVMX_CSR_DB_TYPE_NCB, 32, 30315, 2, 7640},
- {"cvmx_uahc#_ehci_hccapbase" , CVMX_CSR_DB_TYPE_NCB, 32, 30316, 3, 7642},
- {"cvmx_uahc#_ehci_hccparams" , CVMX_CSR_DB_TYPE_NCB, 32, 30317, 7, 7645},
- {"cvmx_uahc#_ehci_hcsparams" , CVMX_CSR_DB_TYPE_NCB, 32, 30318, 10, 7652},
- {"cvmx_uahc#_ehci_insnreg00" , CVMX_CSR_DB_TYPE_NCB, 32, 30319, 3, 7662},
- {"cvmx_uahc#_ehci_insnreg03" , CVMX_CSR_DB_TYPE_NCB, 32, 30320, 5, 7665},
- {"cvmx_uahc#_ehci_insnreg04" , CVMX_CSR_DB_TYPE_NCB, 32, 30321, 7, 7670},
- {"cvmx_uahc#_ehci_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 30322, 2, 7677},
- {"cvmx_uahc#_ehci_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 30323, 1, 7679},
- {"cvmx_uahc#_ehci_periodiclistbase", CVMX_CSR_DB_TYPE_NCB, 32, 30324, 2, 7680},
- {"cvmx_uahc#_ehci_portsc#" , CVMX_CSR_DB_TYPE_NCB, 32, 30325, 19, 7682},
- {"cvmx_uahc#_ehci_usbcmd" , CVMX_CSR_DB_TYPE_NCB, 32, 30327, 13, 7701},
- {"cvmx_uahc#_ehci_usbintr" , CVMX_CSR_DB_TYPE_NCB, 32, 30328, 7, 7714},
- {"cvmx_uahc#_ehci_usbsts" , CVMX_CSR_DB_TYPE_NCB, 32, 30329, 12, 7721},
- {"cvmx_uahc#_ohci0_hcbulkcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 30330, 2, 7733},
- {"cvmx_uahc#_ohci0_hcbulkheaded", CVMX_CSR_DB_TYPE_NCB, 32, 30331, 2, 7735},
- {"cvmx_uahc#_ohci0_hccommandstatus", CVMX_CSR_DB_TYPE_NCB, 32, 30332, 7, 7737},
- {"cvmx_uahc#_ohci0_hccontrol" , CVMX_CSR_DB_TYPE_NCB, 32, 30333, 10, 7744},
- {"cvmx_uahc#_ohci0_hccontrolcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 30334, 2, 7754},
- {"cvmx_uahc#_ohci0_hccontrolheaded", CVMX_CSR_DB_TYPE_NCB, 32, 30335, 2, 7756},
- {"cvmx_uahc#_ohci0_hcdonehead" , CVMX_CSR_DB_TYPE_NCB, 32, 30336, 2, 7758},
- {"cvmx_uahc#_ohci0_hcfminterval", CVMX_CSR_DB_TYPE_NCB, 32, 30337, 4, 7760},
- {"cvmx_uahc#_ohci0_hcfmnumber" , CVMX_CSR_DB_TYPE_NCB, 32, 30338, 2, 7764},
- {"cvmx_uahc#_ohci0_hcfmremaining", CVMX_CSR_DB_TYPE_NCB, 32, 30339, 3, 7766},
- {"cvmx_uahc#_ohci0_hchcca" , CVMX_CSR_DB_TYPE_NCB, 32, 30340, 2, 7769},
- {"cvmx_uahc#_ohci0_hcinterruptdisable", CVMX_CSR_DB_TYPE_NCB, 32, 30341, 10, 7771},
- {"cvmx_uahc#_ohci0_hcinterruptenable", CVMX_CSR_DB_TYPE_NCB, 32, 30342, 10, 7781},
- {"cvmx_uahc#_ohci0_hcinterruptstatus", CVMX_CSR_DB_TYPE_NCB, 32, 30343, 10, 7791},
- {"cvmx_uahc#_ohci0_hclsthreshold", CVMX_CSR_DB_TYPE_NCB, 32, 30344, 2, 7801},
- {"cvmx_uahc#_ohci0_hcperiodcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 30345, 2, 7803},
- {"cvmx_uahc#_ohci0_hcperiodicstart", CVMX_CSR_DB_TYPE_NCB, 32, 30346, 2, 7805},
- {"cvmx_uahc#_ohci0_hcrevision" , CVMX_CSR_DB_TYPE_NCB, 32, 30347, 2, 7807},
- {"cvmx_uahc#_ohci0_hcrhdescriptora", CVMX_CSR_DB_TYPE_NCB, 32, 30348, 8, 7809},
- {"cvmx_uahc#_ohci0_hcrhdescriptorb", CVMX_CSR_DB_TYPE_NCB, 32, 30349, 2, 7817},
- {"cvmx_uahc#_ohci0_hcrhportstatus#", CVMX_CSR_DB_TYPE_NCB, 32, 30350, 15, 7819},
- {"cvmx_uahc#_ohci0_hcrhstatus" , CVMX_CSR_DB_TYPE_NCB, 32, 30352, 8, 7834},
- {"cvmx_uahc#_ohci0_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 30353, 2, 7842},
- {"cvmx_uahc#_ohci0_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 30354, 1, 7844},
- {"cvmx_uctl#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 30355, 7, 7845},
- {"cvmx_uctl#_clk_rst_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 30356, 21, 7852},
- {"cvmx_uctl#_ehci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 30357, 12, 7873},
- {"cvmx_uctl#_ehci_fla" , CVMX_CSR_DB_TYPE_RSL, 64, 30358, 2, 7885},
- {"cvmx_uctl#_erto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 30359, 3, 7887},
- {"cvmx_uctl#_if_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 30360, 2, 7890},
- {"cvmx_uctl#_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 30361, 9, 7892},
- {"cvmx_uctl#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 30362, 9, 7901},
- {"cvmx_uctl#_ohci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 30363, 11, 7910},
- {"cvmx_uctl#_orto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 30364, 3, 7921},
- {"cvmx_uctl#_uphy_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 30365, 11, 7924},
- {"cvmx_uctl#_uphy_port#_ctl_status", CVMX_CSR_DB_TYPE_RSL, 64, 30366, 20, 7935},
- {"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 30368, 3, 7955},
- {"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 30369, 5, 7958},
- {"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 30370, 3, 7963},
- {"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 30371, 8, 7966},
- {"cvmx_zip_core#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 30372, 2, 7974},
- {"cvmx_zip_ctl_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 30374, 2, 7976},
- {"cvmx_zip_ctl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 30375, 15, 7978},
- {"cvmx_zip_dbg_core#_inst" , CVMX_CSR_DB_TYPE_RSL, 64, 30376, 4, 7993},
- {"cvmx_zip_dbg_core#_sta" , CVMX_CSR_DB_TYPE_RSL, 64, 30378, 4, 7997},
- {"cvmx_zip_dbg_que#_sta" , CVMX_CSR_DB_TYPE_RSL, 64, 30380, 4, 8001},
- {"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 30382, 2, 8005},
- {"cvmx_zip_ecc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 30383, 4, 8007},
- {"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 30384, 2, 8011},
- {"cvmx_zip_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 30385, 7, 8013},
- {"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 30386, 2, 8020},
- {"cvmx_zip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 30387, 7, 8022},
- {"cvmx_zip_que#_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 30388, 5, 8029},
- {"cvmx_zip_que#_ecc_err_sta" , CVMX_CSR_DB_TYPE_RSL, 64, 30390, 3, 8034},
- {"cvmx_zip_que#_map" , CVMX_CSR_DB_TYPE_RSL, 64, 30392, 2, 8037},
- {"cvmx_zip_que_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 30394, 2, 8039},
- {"cvmx_zip_que_pri" , CVMX_CSR_DB_TYPE_RSL, 64, 30395, 2, 8041},
- {"cvmx_zip_throttle" , CVMX_CSR_DB_TYPE_RSL, 64, 30396, 2, 8043},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn68xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"AGL_GMX_BAD_REG" , 0x11800e0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
- {"AGL_GMX_BIST" , 0x11800e0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
- {"AGL_GMX_PRT0_CFG" , 0x11800e0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
- {"AGL_GMX_RX0_ADR_CAM0" , 0x11800e0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
- {"AGL_GMX_RX0_ADR_CAM1" , 0x11800e0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
- {"AGL_GMX_RX0_ADR_CAM2" , 0x11800e0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
- {"AGL_GMX_RX0_ADR_CAM3" , 0x11800e0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
- {"AGL_GMX_RX0_ADR_CAM4" , 0x11800e00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
- {"AGL_GMX_RX0_ADR_CAM5" , 0x11800e00001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
- {"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800e0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
- {"AGL_GMX_RX0_ADR_CTL" , 0x11800e0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
- {"AGL_GMX_RX0_DECISION" , 0x11800e0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
- {"AGL_GMX_RX0_FRM_CHK" , 0x11800e0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
- {"AGL_GMX_RX0_FRM_CTL" , 0x11800e0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
- {"AGL_GMX_RX0_FRM_MAX" , 0x11800e0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
- {"AGL_GMX_RX0_FRM_MIN" , 0x11800e0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
- {"AGL_GMX_RX0_IFG" , 0x11800e0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
- {"AGL_GMX_RX0_INT_EN" , 0x11800e0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
- {"AGL_GMX_RX0_INT_REG" , 0x11800e0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
- {"AGL_GMX_RX0_JABBER" , 0x11800e0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
- {"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800e0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
- {"AGL_GMX_RX0_RX_INBND" , 0x11800e0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
- {"AGL_GMX_RX0_STATS_CTL" , 0x11800e0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
- {"AGL_GMX_RX0_STATS_OCTS" , 0x11800e0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
- {"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800e0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
- {"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800e00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
- {"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800e00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
- {"AGL_GMX_RX0_STATS_PKTS" , 0x11800e0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
- {"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800e00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
- {"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800e0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
- {"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800e00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
- {"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800e00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
- {"AGL_GMX_RX0_UDD_SKP" , 0x11800e0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
- {"AGL_GMX_RX_BP_DROP0" , 0x11800e0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
- {"AGL_GMX_RX_BP_OFF0" , 0x11800e0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
- {"AGL_GMX_RX_BP_ON0" , 0x11800e0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
- {"AGL_GMX_RX_PRT_INFO" , 0x11800e00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
- {"AGL_GMX_RX_TX_STATUS" , 0x11800e00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
- {"AGL_GMX_SMAC0" , 0x11800e0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
- {"AGL_GMX_STAT_BP" , 0x11800e0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
- {"AGL_GMX_TX0_APPEND" , 0x11800e0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
- {"AGL_GMX_TX0_CLK" , 0x11800e0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
- {"AGL_GMX_TX0_CTL" , 0x11800e0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
- {"AGL_GMX_TX0_MIN_PKT" , 0x11800e0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
- {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800e0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
- {"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800e0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
- {"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800e0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
- {"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800e0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
- {"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800e0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
- {"AGL_GMX_TX0_STAT0" , 0x11800e0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
- {"AGL_GMX_TX0_STAT1" , 0x11800e0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
- {"AGL_GMX_TX0_STAT2" , 0x11800e0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
- {"AGL_GMX_TX0_STAT3" , 0x11800e0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
- {"AGL_GMX_TX0_STAT4" , 0x11800e00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
- {"AGL_GMX_TX0_STAT5" , 0x11800e00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
- {"AGL_GMX_TX0_STAT6" , 0x11800e00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
- {"AGL_GMX_TX0_STAT7" , 0x11800e00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
- {"AGL_GMX_TX0_STAT8" , 0x11800e00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
- {"AGL_GMX_TX0_STAT9" , 0x11800e00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
- {"AGL_GMX_TX0_STATS_CTL" , 0x11800e0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
- {"AGL_GMX_TX0_THRESH" , 0x11800e0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
- {"AGL_GMX_TX_BP" , 0x11800e00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
- {"AGL_GMX_TX_COL_ATTEMPT" , 0x11800e0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
- {"AGL_GMX_TX_IFG" , 0x11800e0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
- {"AGL_GMX_TX_INT_EN" , 0x11800e0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
- {"AGL_GMX_TX_INT_REG" , 0x11800e0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
- {"AGL_GMX_TX_JAM" , 0x11800e0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
- {"AGL_GMX_TX_LFSR" , 0x11800e00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
- {"AGL_GMX_TX_OVR_BP" , 0x11800e00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
- {"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800e00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
- {"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800e00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
- {"AGL_PRT0_CTL" , 0x11800e0002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
- {"CIU2_ACK_IO0_INT" , 0x10701080c0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU2_ACK_IO1_INT" , 0x10701082c0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"CIU2_ACK_PP0_IP2" , 0x10701000c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP1_IP2" , 0x10701002c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP2_IP2" , 0x10701004c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP3_IP2" , 0x10701006c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP4_IP2" , 0x10701008c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP5_IP2" , 0x1070100ac0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP6_IP2" , 0x1070100cc0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP7_IP2" , 0x1070100ec0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP8_IP2" , 0x10701010c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP9_IP2" , 0x10701012c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP10_IP2" , 0x10701014c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP11_IP2" , 0x10701016c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP12_IP2" , 0x10701018c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP13_IP2" , 0x1070101ac0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP14_IP2" , 0x1070101cc0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP15_IP2" , 0x1070101ec0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP16_IP2" , 0x10701020c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP17_IP2" , 0x10701022c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP18_IP2" , 0x10701024c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP19_IP2" , 0x10701026c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP20_IP2" , 0x10701028c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP21_IP2" , 0x1070102ac0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP22_IP2" , 0x1070102cc0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP23_IP2" , 0x1070102ec0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP24_IP2" , 0x10701030c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP25_IP2" , 0x10701032c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP26_IP2" , 0x10701034c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP27_IP2" , 0x10701036c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP28_IP2" , 0x10701038c0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP29_IP2" , 0x1070103ac0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP30_IP2" , 0x1070103cc0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP31_IP2" , 0x1070103ec0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"CIU2_ACK_PP0_IP3" , 0x10701000c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP1_IP3" , 0x10701002c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP2_IP3" , 0x10701004c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP3_IP3" , 0x10701006c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP4_IP3" , 0x10701008c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP5_IP3" , 0x1070100ac0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP6_IP3" , 0x1070100cc0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP7_IP3" , 0x1070100ec0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP8_IP3" , 0x10701010c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP9_IP3" , 0x10701012c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP10_IP3" , 0x10701014c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP11_IP3" , 0x10701016c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP12_IP3" , 0x10701018c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP13_IP3" , 0x1070101ac0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP14_IP3" , 0x1070101cc0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP15_IP3" , 0x1070101ec0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP16_IP3" , 0x10701020c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP17_IP3" , 0x10701022c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP18_IP3" , 0x10701024c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP19_IP3" , 0x10701026c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP20_IP3" , 0x10701028c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP21_IP3" , 0x1070102ac0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP22_IP3" , 0x1070102cc0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP23_IP3" , 0x1070102ec0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP24_IP3" , 0x10701030c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP25_IP3" , 0x10701032c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP26_IP3" , 0x10701034c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP27_IP3" , 0x10701036c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP28_IP3" , 0x10701038c0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP29_IP3" , 0x1070103ac0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP30_IP3" , 0x1070103cc0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP31_IP3" , 0x1070103ec0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"CIU2_ACK_PP0_IP4" , 0x10701000c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP1_IP4" , 0x10701002c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP2_IP4" , 0x10701004c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP3_IP4" , 0x10701006c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP4_IP4" , 0x10701008c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP5_IP4" , 0x1070100ac0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP6_IP4" , 0x1070100cc0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP7_IP4" , 0x1070100ec0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP8_IP4" , 0x10701010c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP9_IP4" , 0x10701012c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP10_IP4" , 0x10701014c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP11_IP4" , 0x10701016c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP12_IP4" , 0x10701018c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP13_IP4" , 0x1070101ac0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP14_IP4" , 0x1070101cc0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP15_IP4" , 0x1070101ec0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP16_IP4" , 0x10701020c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP17_IP4" , 0x10701022c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP18_IP4" , 0x10701024c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP19_IP4" , 0x10701026c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP20_IP4" , 0x10701028c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP21_IP4" , 0x1070102ac0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP22_IP4" , 0x1070102cc0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP23_IP4" , 0x1070102ec0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP24_IP4" , 0x10701030c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP25_IP4" , 0x10701032c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP26_IP4" , 0x10701034c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP27_IP4" , 0x10701036c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP28_IP4" , 0x10701038c0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP29_IP4" , 0x1070103ac0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP30_IP4" , 0x1070103cc0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_ACK_PP31_IP4" , 0x1070103ec0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"CIU2_EN_IO0_INT_GPIO" , 0x1070108097800ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU2_EN_IO1_INT_GPIO" , 0x1070108297800ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"CIU2_EN_IO0_INT_GPIO_W1C" , 0x10701080b7800ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU2_EN_IO1_INT_GPIO_W1C" , 0x10701082b7800ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"CIU2_EN_IO0_INT_GPIO_W1S" , 0x10701080a7800ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU2_EN_IO1_INT_GPIO_W1S" , 0x10701082a7800ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"CIU2_EN_IO0_INT_IO" , 0x1070108094800ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU2_EN_IO1_INT_IO" , 0x1070108294800ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"CIU2_EN_IO0_INT_IO_W1C" , 0x10701080b4800ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU2_EN_IO1_INT_IO_W1C" , 0x10701082b4800ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"CIU2_EN_IO0_INT_IO_W1S" , 0x10701080a4800ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU2_EN_IO1_INT_IO_W1S" , 0x10701082a4800ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"CIU2_EN_IO0_INT_MBOX" , 0x1070108098800ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU2_EN_IO1_INT_MBOX" , 0x1070108298800ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"CIU2_EN_IO0_INT_MBOX_W1C" , 0x10701080b8800ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU2_EN_IO1_INT_MBOX_W1C" , 0x10701082b8800ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"CIU2_EN_IO0_INT_MBOX_W1S" , 0x10701080a8800ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU2_EN_IO1_INT_MBOX_W1S" , 0x10701082a8800ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"CIU2_EN_IO0_INT_MEM" , 0x1070108095800ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU2_EN_IO1_INT_MEM" , 0x1070108295800ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"CIU2_EN_IO0_INT_MEM_W1C" , 0x10701080b5800ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU2_EN_IO1_INT_MEM_W1C" , 0x10701082b5800ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"CIU2_EN_IO0_INT_MEM_W1S" , 0x10701080a5800ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU2_EN_IO1_INT_MEM_W1S" , 0x10701082a5800ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"CIU2_EN_IO0_INT_MIO" , 0x1070108093800ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU2_EN_IO1_INT_MIO" , 0x1070108293800ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"CIU2_EN_IO0_INT_MIO_W1C" , 0x10701080b3800ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU2_EN_IO1_INT_MIO_W1C" , 0x10701082b3800ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"CIU2_EN_IO0_INT_MIO_W1S" , 0x10701080a3800ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU2_EN_IO1_INT_MIO_W1S" , 0x10701082a3800ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
- {"CIU2_EN_IO0_INT_PKT" , 0x1070108096800ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU2_EN_IO1_INT_PKT" , 0x1070108296800ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
- {"CIU2_EN_IO0_INT_PKT_W1C" , 0x10701080b6800ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU2_EN_IO1_INT_PKT_W1C" , 0x10701082b6800ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
- {"CIU2_EN_IO0_INT_PKT_W1S" , 0x10701080a6800ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU2_EN_IO1_INT_PKT_W1S" , 0x10701082a6800ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
- {"CIU2_EN_IO0_INT_RML" , 0x1070108092800ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU2_EN_IO1_INT_RML" , 0x1070108292800ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
- {"CIU2_EN_IO0_INT_RML_W1C" , 0x10701080b2800ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU2_EN_IO1_INT_RML_W1C" , 0x10701082b2800ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
- {"CIU2_EN_IO0_INT_RML_W1S" , 0x10701080a2800ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU2_EN_IO1_INT_RML_W1S" , 0x10701082a2800ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
- {"CIU2_EN_IO0_INT_WDOG" , 0x1070108091800ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU2_EN_IO1_INT_WDOG" , 0x1070108291800ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
- {"CIU2_EN_IO0_INT_WDOG_W1C" , 0x10701080b1800ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU2_EN_IO1_INT_WDOG_W1C" , 0x10701082b1800ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
- {"CIU2_EN_IO0_INT_WDOG_W1S" , 0x10701080a1800ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU2_EN_IO1_INT_WDOG_W1S" , 0x10701082a1800ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
- {"CIU2_EN_IO0_INT_WRKQ" , 0x1070108090800ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU2_EN_IO1_INT_WRKQ" , 0x1070108290800ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
- {"CIU2_EN_IO0_INT_WRKQ_W1C" , 0x10701080b0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU2_EN_IO1_INT_WRKQ_W1C" , 0x10701082b0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
- {"CIU2_EN_IO0_INT_WRKQ_W1S" , 0x10701080a0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU2_EN_IO1_INT_WRKQ_W1S" , 0x10701082a0800ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
- {"CIU2_EN_PP0_IP2_GPIO" , 0x1070100097000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP1_IP2_GPIO" , 0x1070100297000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP2_IP2_GPIO" , 0x1070100497000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP3_IP2_GPIO" , 0x1070100697000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP4_IP2_GPIO" , 0x1070100897000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP5_IP2_GPIO" , 0x1070100a97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP6_IP2_GPIO" , 0x1070100c97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP7_IP2_GPIO" , 0x1070100e97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP8_IP2_GPIO" , 0x1070101097000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP9_IP2_GPIO" , 0x1070101297000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP10_IP2_GPIO" , 0x1070101497000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP11_IP2_GPIO" , 0x1070101697000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP12_IP2_GPIO" , 0x1070101897000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP13_IP2_GPIO" , 0x1070101a97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP14_IP2_GPIO" , 0x1070101c97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP15_IP2_GPIO" , 0x1070101e97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP16_IP2_GPIO" , 0x1070102097000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP17_IP2_GPIO" , 0x1070102297000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP18_IP2_GPIO" , 0x1070102497000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP19_IP2_GPIO" , 0x1070102697000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP20_IP2_GPIO" , 0x1070102897000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP21_IP2_GPIO" , 0x1070102a97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP22_IP2_GPIO" , 0x1070102c97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP23_IP2_GPIO" , 0x1070102e97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP24_IP2_GPIO" , 0x1070103097000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP25_IP2_GPIO" , 0x1070103297000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP26_IP2_GPIO" , 0x1070103497000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP27_IP2_GPIO" , 0x1070103697000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP28_IP2_GPIO" , 0x1070103897000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP29_IP2_GPIO" , 0x1070103a97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP30_IP2_GPIO" , 0x1070103c97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP31_IP2_GPIO" , 0x1070103e97000ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
- {"CIU2_EN_PP0_IP2_GPIO_W1C" , 0x10701000b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP1_IP2_GPIO_W1C" , 0x10701002b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP2_IP2_GPIO_W1C" , 0x10701004b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP3_IP2_GPIO_W1C" , 0x10701006b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP4_IP2_GPIO_W1C" , 0x10701008b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP5_IP2_GPIO_W1C" , 0x1070100ab7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP6_IP2_GPIO_W1C" , 0x1070100cb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP7_IP2_GPIO_W1C" , 0x1070100eb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP8_IP2_GPIO_W1C" , 0x10701010b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP9_IP2_GPIO_W1C" , 0x10701012b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP10_IP2_GPIO_W1C" , 0x10701014b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP11_IP2_GPIO_W1C" , 0x10701016b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP12_IP2_GPIO_W1C" , 0x10701018b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP13_IP2_GPIO_W1C" , 0x1070101ab7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP14_IP2_GPIO_W1C" , 0x1070101cb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP15_IP2_GPIO_W1C" , 0x1070101eb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP16_IP2_GPIO_W1C" , 0x10701020b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP17_IP2_GPIO_W1C" , 0x10701022b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP18_IP2_GPIO_W1C" , 0x10701024b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP19_IP2_GPIO_W1C" , 0x10701026b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP20_IP2_GPIO_W1C" , 0x10701028b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP21_IP2_GPIO_W1C" , 0x1070102ab7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP22_IP2_GPIO_W1C" , 0x1070102cb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP23_IP2_GPIO_W1C" , 0x1070102eb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP24_IP2_GPIO_W1C" , 0x10701030b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP25_IP2_GPIO_W1C" , 0x10701032b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP26_IP2_GPIO_W1C" , 0x10701034b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP27_IP2_GPIO_W1C" , 0x10701036b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP28_IP2_GPIO_W1C" , 0x10701038b7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP29_IP2_GPIO_W1C" , 0x1070103ab7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP30_IP2_GPIO_W1C" , 0x1070103cb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP31_IP2_GPIO_W1C" , 0x1070103eb7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
- {"CIU2_EN_PP0_IP2_GPIO_W1S" , 0x10701000a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP1_IP2_GPIO_W1S" , 0x10701002a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP2_IP2_GPIO_W1S" , 0x10701004a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP3_IP2_GPIO_W1S" , 0x10701006a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP4_IP2_GPIO_W1S" , 0x10701008a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP5_IP2_GPIO_W1S" , 0x1070100aa7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP6_IP2_GPIO_W1S" , 0x1070100ca7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP7_IP2_GPIO_W1S" , 0x1070100ea7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP8_IP2_GPIO_W1S" , 0x10701010a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP9_IP2_GPIO_W1S" , 0x10701012a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP10_IP2_GPIO_W1S" , 0x10701014a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP11_IP2_GPIO_W1S" , 0x10701016a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP12_IP2_GPIO_W1S" , 0x10701018a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP13_IP2_GPIO_W1S" , 0x1070101aa7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP14_IP2_GPIO_W1S" , 0x1070101ca7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP15_IP2_GPIO_W1S" , 0x1070101ea7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP16_IP2_GPIO_W1S" , 0x10701020a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP17_IP2_GPIO_W1S" , 0x10701022a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP18_IP2_GPIO_W1S" , 0x10701024a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP19_IP2_GPIO_W1S" , 0x10701026a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP20_IP2_GPIO_W1S" , 0x10701028a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP21_IP2_GPIO_W1S" , 0x1070102aa7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP22_IP2_GPIO_W1S" , 0x1070102ca7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP23_IP2_GPIO_W1S" , 0x1070102ea7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP24_IP2_GPIO_W1S" , 0x10701030a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP25_IP2_GPIO_W1S" , 0x10701032a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP26_IP2_GPIO_W1S" , 0x10701034a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP27_IP2_GPIO_W1S" , 0x10701036a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP28_IP2_GPIO_W1S" , 0x10701038a7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP29_IP2_GPIO_W1S" , 0x1070103aa7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP30_IP2_GPIO_W1S" , 0x1070103ca7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP31_IP2_GPIO_W1S" , 0x1070103ea7000ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
- {"CIU2_EN_PP0_IP2_IO" , 0x1070100094000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP1_IP2_IO" , 0x1070100294000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP2_IP2_IO" , 0x1070100494000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP3_IP2_IO" , 0x1070100694000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP4_IP2_IO" , 0x1070100894000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP5_IP2_IO" , 0x1070100a94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP6_IP2_IO" , 0x1070100c94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP7_IP2_IO" , 0x1070100e94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP8_IP2_IO" , 0x1070101094000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP9_IP2_IO" , 0x1070101294000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP10_IP2_IO" , 0x1070101494000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP11_IP2_IO" , 0x1070101694000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP12_IP2_IO" , 0x1070101894000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP13_IP2_IO" , 0x1070101a94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP14_IP2_IO" , 0x1070101c94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP15_IP2_IO" , 0x1070101e94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP16_IP2_IO" , 0x1070102094000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP17_IP2_IO" , 0x1070102294000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP18_IP2_IO" , 0x1070102494000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP19_IP2_IO" , 0x1070102694000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP20_IP2_IO" , 0x1070102894000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP21_IP2_IO" , 0x1070102a94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP22_IP2_IO" , 0x1070102c94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP23_IP2_IO" , 0x1070102e94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP24_IP2_IO" , 0x1070103094000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP25_IP2_IO" , 0x1070103294000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP26_IP2_IO" , 0x1070103494000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP27_IP2_IO" , 0x1070103694000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP28_IP2_IO" , 0x1070103894000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP29_IP2_IO" , 0x1070103a94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP30_IP2_IO" , 0x1070103c94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP31_IP2_IO" , 0x1070103e94000ull, CVMX_CSR_DB_TYPE_NCB, 64, 106},
- {"CIU2_EN_PP0_IP2_IO_W1C" , 0x10701000b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP1_IP2_IO_W1C" , 0x10701002b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP2_IP2_IO_W1C" , 0x10701004b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP3_IP2_IO_W1C" , 0x10701006b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP4_IP2_IO_W1C" , 0x10701008b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP5_IP2_IO_W1C" , 0x1070100ab4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP6_IP2_IO_W1C" , 0x1070100cb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP7_IP2_IO_W1C" , 0x1070100eb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP8_IP2_IO_W1C" , 0x10701010b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP9_IP2_IO_W1C" , 0x10701012b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP10_IP2_IO_W1C" , 0x10701014b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP11_IP2_IO_W1C" , 0x10701016b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP12_IP2_IO_W1C" , 0x10701018b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP13_IP2_IO_W1C" , 0x1070101ab4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP14_IP2_IO_W1C" , 0x1070101cb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP15_IP2_IO_W1C" , 0x1070101eb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP16_IP2_IO_W1C" , 0x10701020b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP17_IP2_IO_W1C" , 0x10701022b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP18_IP2_IO_W1C" , 0x10701024b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP19_IP2_IO_W1C" , 0x10701026b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP20_IP2_IO_W1C" , 0x10701028b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP21_IP2_IO_W1C" , 0x1070102ab4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP22_IP2_IO_W1C" , 0x1070102cb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP23_IP2_IO_W1C" , 0x1070102eb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP24_IP2_IO_W1C" , 0x10701030b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP25_IP2_IO_W1C" , 0x10701032b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP26_IP2_IO_W1C" , 0x10701034b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP27_IP2_IO_W1C" , 0x10701036b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP28_IP2_IO_W1C" , 0x10701038b4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP29_IP2_IO_W1C" , 0x1070103ab4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP30_IP2_IO_W1C" , 0x1070103cb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP31_IP2_IO_W1C" , 0x1070103eb4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 107},
- {"CIU2_EN_PP0_IP2_IO_W1S" , 0x10701000a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP1_IP2_IO_W1S" , 0x10701002a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP2_IP2_IO_W1S" , 0x10701004a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP3_IP2_IO_W1S" , 0x10701006a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP4_IP2_IO_W1S" , 0x10701008a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP5_IP2_IO_W1S" , 0x1070100aa4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP6_IP2_IO_W1S" , 0x1070100ca4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP7_IP2_IO_W1S" , 0x1070100ea4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP8_IP2_IO_W1S" , 0x10701010a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP9_IP2_IO_W1S" , 0x10701012a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP10_IP2_IO_W1S" , 0x10701014a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP11_IP2_IO_W1S" , 0x10701016a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP12_IP2_IO_W1S" , 0x10701018a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP13_IP2_IO_W1S" , 0x1070101aa4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP14_IP2_IO_W1S" , 0x1070101ca4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP15_IP2_IO_W1S" , 0x1070101ea4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP16_IP2_IO_W1S" , 0x10701020a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP17_IP2_IO_W1S" , 0x10701022a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP18_IP2_IO_W1S" , 0x10701024a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP19_IP2_IO_W1S" , 0x10701026a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP20_IP2_IO_W1S" , 0x10701028a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP21_IP2_IO_W1S" , 0x1070102aa4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP22_IP2_IO_W1S" , 0x1070102ca4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP23_IP2_IO_W1S" , 0x1070102ea4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP24_IP2_IO_W1S" , 0x10701030a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP25_IP2_IO_W1S" , 0x10701032a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP26_IP2_IO_W1S" , 0x10701034a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP27_IP2_IO_W1S" , 0x10701036a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP28_IP2_IO_W1S" , 0x10701038a4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP29_IP2_IO_W1S" , 0x1070103aa4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP30_IP2_IO_W1S" , 0x1070103ca4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP31_IP2_IO_W1S" , 0x1070103ea4000ull, CVMX_CSR_DB_TYPE_NCB, 64, 108},
- {"CIU2_EN_PP0_IP2_MBOX" , 0x1070100098000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP1_IP2_MBOX" , 0x1070100298000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP2_IP2_MBOX" , 0x1070100498000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP3_IP2_MBOX" , 0x1070100698000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP4_IP2_MBOX" , 0x1070100898000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP5_IP2_MBOX" , 0x1070100a98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP6_IP2_MBOX" , 0x1070100c98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP7_IP2_MBOX" , 0x1070100e98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP8_IP2_MBOX" , 0x1070101098000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP9_IP2_MBOX" , 0x1070101298000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP10_IP2_MBOX" , 0x1070101498000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP11_IP2_MBOX" , 0x1070101698000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP12_IP2_MBOX" , 0x1070101898000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP13_IP2_MBOX" , 0x1070101a98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP14_IP2_MBOX" , 0x1070101c98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP15_IP2_MBOX" , 0x1070101e98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP16_IP2_MBOX" , 0x1070102098000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP17_IP2_MBOX" , 0x1070102298000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP18_IP2_MBOX" , 0x1070102498000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP19_IP2_MBOX" , 0x1070102698000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP20_IP2_MBOX" , 0x1070102898000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP21_IP2_MBOX" , 0x1070102a98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP22_IP2_MBOX" , 0x1070102c98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP23_IP2_MBOX" , 0x1070102e98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP24_IP2_MBOX" , 0x1070103098000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP25_IP2_MBOX" , 0x1070103298000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP26_IP2_MBOX" , 0x1070103498000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP27_IP2_MBOX" , 0x1070103698000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP28_IP2_MBOX" , 0x1070103898000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP29_IP2_MBOX" , 0x1070103a98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP30_IP2_MBOX" , 0x1070103c98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP31_IP2_MBOX" , 0x1070103e98000ull, CVMX_CSR_DB_TYPE_NCB, 64, 109},
- {"CIU2_EN_PP0_IP2_MBOX_W1C" , 0x10701000b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP1_IP2_MBOX_W1C" , 0x10701002b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP2_IP2_MBOX_W1C" , 0x10701004b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP3_IP2_MBOX_W1C" , 0x10701006b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP4_IP2_MBOX_W1C" , 0x10701008b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP5_IP2_MBOX_W1C" , 0x1070100ab8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP6_IP2_MBOX_W1C" , 0x1070100cb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP7_IP2_MBOX_W1C" , 0x1070100eb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP8_IP2_MBOX_W1C" , 0x10701010b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP9_IP2_MBOX_W1C" , 0x10701012b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP10_IP2_MBOX_W1C" , 0x10701014b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP11_IP2_MBOX_W1C" , 0x10701016b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP12_IP2_MBOX_W1C" , 0x10701018b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP13_IP2_MBOX_W1C" , 0x1070101ab8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP14_IP2_MBOX_W1C" , 0x1070101cb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP15_IP2_MBOX_W1C" , 0x1070101eb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP16_IP2_MBOX_W1C" , 0x10701020b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP17_IP2_MBOX_W1C" , 0x10701022b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP18_IP2_MBOX_W1C" , 0x10701024b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP19_IP2_MBOX_W1C" , 0x10701026b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP20_IP2_MBOX_W1C" , 0x10701028b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP21_IP2_MBOX_W1C" , 0x1070102ab8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP22_IP2_MBOX_W1C" , 0x1070102cb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP23_IP2_MBOX_W1C" , 0x1070102eb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP24_IP2_MBOX_W1C" , 0x10701030b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP25_IP2_MBOX_W1C" , 0x10701032b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP26_IP2_MBOX_W1C" , 0x10701034b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP27_IP2_MBOX_W1C" , 0x10701036b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP28_IP2_MBOX_W1C" , 0x10701038b8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP29_IP2_MBOX_W1C" , 0x1070103ab8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP30_IP2_MBOX_W1C" , 0x1070103cb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP31_IP2_MBOX_W1C" , 0x1070103eb8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 110},
- {"CIU2_EN_PP0_IP2_MBOX_W1S" , 0x10701000a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP1_IP2_MBOX_W1S" , 0x10701002a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP2_IP2_MBOX_W1S" , 0x10701004a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP3_IP2_MBOX_W1S" , 0x10701006a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP4_IP2_MBOX_W1S" , 0x10701008a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP5_IP2_MBOX_W1S" , 0x1070100aa8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP6_IP2_MBOX_W1S" , 0x1070100ca8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP7_IP2_MBOX_W1S" , 0x1070100ea8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP8_IP2_MBOX_W1S" , 0x10701010a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP9_IP2_MBOX_W1S" , 0x10701012a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP10_IP2_MBOX_W1S" , 0x10701014a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP11_IP2_MBOX_W1S" , 0x10701016a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP12_IP2_MBOX_W1S" , 0x10701018a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP13_IP2_MBOX_W1S" , 0x1070101aa8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP14_IP2_MBOX_W1S" , 0x1070101ca8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP15_IP2_MBOX_W1S" , 0x1070101ea8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP16_IP2_MBOX_W1S" , 0x10701020a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP17_IP2_MBOX_W1S" , 0x10701022a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP18_IP2_MBOX_W1S" , 0x10701024a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP19_IP2_MBOX_W1S" , 0x10701026a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP20_IP2_MBOX_W1S" , 0x10701028a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP21_IP2_MBOX_W1S" , 0x1070102aa8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP22_IP2_MBOX_W1S" , 0x1070102ca8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP23_IP2_MBOX_W1S" , 0x1070102ea8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP24_IP2_MBOX_W1S" , 0x10701030a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP25_IP2_MBOX_W1S" , 0x10701032a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP26_IP2_MBOX_W1S" , 0x10701034a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP27_IP2_MBOX_W1S" , 0x10701036a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP28_IP2_MBOX_W1S" , 0x10701038a8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP29_IP2_MBOX_W1S" , 0x1070103aa8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP30_IP2_MBOX_W1S" , 0x1070103ca8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP31_IP2_MBOX_W1S" , 0x1070103ea8000ull, CVMX_CSR_DB_TYPE_NCB, 64, 111},
- {"CIU2_EN_PP0_IP2_MEM" , 0x1070100095000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP1_IP2_MEM" , 0x1070100295000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP2_IP2_MEM" , 0x1070100495000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP3_IP2_MEM" , 0x1070100695000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP4_IP2_MEM" , 0x1070100895000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP5_IP2_MEM" , 0x1070100a95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP6_IP2_MEM" , 0x1070100c95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP7_IP2_MEM" , 0x1070100e95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP8_IP2_MEM" , 0x1070101095000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP9_IP2_MEM" , 0x1070101295000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP10_IP2_MEM" , 0x1070101495000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP11_IP2_MEM" , 0x1070101695000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP12_IP2_MEM" , 0x1070101895000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP13_IP2_MEM" , 0x1070101a95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP14_IP2_MEM" , 0x1070101c95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP15_IP2_MEM" , 0x1070101e95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP16_IP2_MEM" , 0x1070102095000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP17_IP2_MEM" , 0x1070102295000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP18_IP2_MEM" , 0x1070102495000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP19_IP2_MEM" , 0x1070102695000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP20_IP2_MEM" , 0x1070102895000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP21_IP2_MEM" , 0x1070102a95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP22_IP2_MEM" , 0x1070102c95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP23_IP2_MEM" , 0x1070102e95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP24_IP2_MEM" , 0x1070103095000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP25_IP2_MEM" , 0x1070103295000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP26_IP2_MEM" , 0x1070103495000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP27_IP2_MEM" , 0x1070103695000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP28_IP2_MEM" , 0x1070103895000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP29_IP2_MEM" , 0x1070103a95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP30_IP2_MEM" , 0x1070103c95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP31_IP2_MEM" , 0x1070103e95000ull, CVMX_CSR_DB_TYPE_NCB, 64, 112},
- {"CIU2_EN_PP0_IP2_MEM_W1C" , 0x10701000b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP1_IP2_MEM_W1C" , 0x10701002b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP2_IP2_MEM_W1C" , 0x10701004b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP3_IP2_MEM_W1C" , 0x10701006b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP4_IP2_MEM_W1C" , 0x10701008b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP5_IP2_MEM_W1C" , 0x1070100ab5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP6_IP2_MEM_W1C" , 0x1070100cb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP7_IP2_MEM_W1C" , 0x1070100eb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP8_IP2_MEM_W1C" , 0x10701010b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP9_IP2_MEM_W1C" , 0x10701012b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP10_IP2_MEM_W1C" , 0x10701014b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP11_IP2_MEM_W1C" , 0x10701016b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP12_IP2_MEM_W1C" , 0x10701018b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP13_IP2_MEM_W1C" , 0x1070101ab5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP14_IP2_MEM_W1C" , 0x1070101cb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP15_IP2_MEM_W1C" , 0x1070101eb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP16_IP2_MEM_W1C" , 0x10701020b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP17_IP2_MEM_W1C" , 0x10701022b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP18_IP2_MEM_W1C" , 0x10701024b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP19_IP2_MEM_W1C" , 0x10701026b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP20_IP2_MEM_W1C" , 0x10701028b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP21_IP2_MEM_W1C" , 0x1070102ab5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP22_IP2_MEM_W1C" , 0x1070102cb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP23_IP2_MEM_W1C" , 0x1070102eb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP24_IP2_MEM_W1C" , 0x10701030b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP25_IP2_MEM_W1C" , 0x10701032b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP26_IP2_MEM_W1C" , 0x10701034b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP27_IP2_MEM_W1C" , 0x10701036b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP28_IP2_MEM_W1C" , 0x10701038b5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP29_IP2_MEM_W1C" , 0x1070103ab5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP30_IP2_MEM_W1C" , 0x1070103cb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP31_IP2_MEM_W1C" , 0x1070103eb5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 113},
- {"CIU2_EN_PP0_IP2_MEM_W1S" , 0x10701000a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP1_IP2_MEM_W1S" , 0x10701002a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP2_IP2_MEM_W1S" , 0x10701004a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP3_IP2_MEM_W1S" , 0x10701006a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP4_IP2_MEM_W1S" , 0x10701008a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP5_IP2_MEM_W1S" , 0x1070100aa5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP6_IP2_MEM_W1S" , 0x1070100ca5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP7_IP2_MEM_W1S" , 0x1070100ea5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP8_IP2_MEM_W1S" , 0x10701010a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP9_IP2_MEM_W1S" , 0x10701012a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP10_IP2_MEM_W1S" , 0x10701014a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP11_IP2_MEM_W1S" , 0x10701016a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP12_IP2_MEM_W1S" , 0x10701018a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP13_IP2_MEM_W1S" , 0x1070101aa5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP14_IP2_MEM_W1S" , 0x1070101ca5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP15_IP2_MEM_W1S" , 0x1070101ea5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP16_IP2_MEM_W1S" , 0x10701020a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP17_IP2_MEM_W1S" , 0x10701022a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP18_IP2_MEM_W1S" , 0x10701024a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP19_IP2_MEM_W1S" , 0x10701026a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP20_IP2_MEM_W1S" , 0x10701028a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP21_IP2_MEM_W1S" , 0x1070102aa5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP22_IP2_MEM_W1S" , 0x1070102ca5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP23_IP2_MEM_W1S" , 0x1070102ea5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP24_IP2_MEM_W1S" , 0x10701030a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP25_IP2_MEM_W1S" , 0x10701032a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP26_IP2_MEM_W1S" , 0x10701034a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP27_IP2_MEM_W1S" , 0x10701036a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP28_IP2_MEM_W1S" , 0x10701038a5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP29_IP2_MEM_W1S" , 0x1070103aa5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP30_IP2_MEM_W1S" , 0x1070103ca5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP31_IP2_MEM_W1S" , 0x1070103ea5000ull, CVMX_CSR_DB_TYPE_NCB, 64, 114},
- {"CIU2_EN_PP0_IP2_MIO" , 0x1070100093000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP1_IP2_MIO" , 0x1070100293000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP2_IP2_MIO" , 0x1070100493000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP3_IP2_MIO" , 0x1070100693000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP4_IP2_MIO" , 0x1070100893000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP5_IP2_MIO" , 0x1070100a93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP6_IP2_MIO" , 0x1070100c93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP7_IP2_MIO" , 0x1070100e93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP8_IP2_MIO" , 0x1070101093000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP9_IP2_MIO" , 0x1070101293000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP10_IP2_MIO" , 0x1070101493000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP11_IP2_MIO" , 0x1070101693000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP12_IP2_MIO" , 0x1070101893000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP13_IP2_MIO" , 0x1070101a93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP14_IP2_MIO" , 0x1070101c93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP15_IP2_MIO" , 0x1070101e93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP16_IP2_MIO" , 0x1070102093000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP17_IP2_MIO" , 0x1070102293000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP18_IP2_MIO" , 0x1070102493000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP19_IP2_MIO" , 0x1070102693000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP20_IP2_MIO" , 0x1070102893000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP21_IP2_MIO" , 0x1070102a93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP22_IP2_MIO" , 0x1070102c93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP23_IP2_MIO" , 0x1070102e93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP24_IP2_MIO" , 0x1070103093000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP25_IP2_MIO" , 0x1070103293000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP26_IP2_MIO" , 0x1070103493000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP27_IP2_MIO" , 0x1070103693000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP28_IP2_MIO" , 0x1070103893000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP29_IP2_MIO" , 0x1070103a93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP30_IP2_MIO" , 0x1070103c93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP31_IP2_MIO" , 0x1070103e93000ull, CVMX_CSR_DB_TYPE_NCB, 64, 115},
- {"CIU2_EN_PP0_IP2_MIO_W1C" , 0x10701000b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP1_IP2_MIO_W1C" , 0x10701002b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP2_IP2_MIO_W1C" , 0x10701004b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP3_IP2_MIO_W1C" , 0x10701006b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP4_IP2_MIO_W1C" , 0x10701008b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP5_IP2_MIO_W1C" , 0x1070100ab3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP6_IP2_MIO_W1C" , 0x1070100cb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP7_IP2_MIO_W1C" , 0x1070100eb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP8_IP2_MIO_W1C" , 0x10701010b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP9_IP2_MIO_W1C" , 0x10701012b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP10_IP2_MIO_W1C" , 0x10701014b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP11_IP2_MIO_W1C" , 0x10701016b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP12_IP2_MIO_W1C" , 0x10701018b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP13_IP2_MIO_W1C" , 0x1070101ab3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP14_IP2_MIO_W1C" , 0x1070101cb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP15_IP2_MIO_W1C" , 0x1070101eb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP16_IP2_MIO_W1C" , 0x10701020b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP17_IP2_MIO_W1C" , 0x10701022b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP18_IP2_MIO_W1C" , 0x10701024b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP19_IP2_MIO_W1C" , 0x10701026b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP20_IP2_MIO_W1C" , 0x10701028b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP21_IP2_MIO_W1C" , 0x1070102ab3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP22_IP2_MIO_W1C" , 0x1070102cb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP23_IP2_MIO_W1C" , 0x1070102eb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP24_IP2_MIO_W1C" , 0x10701030b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP25_IP2_MIO_W1C" , 0x10701032b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP26_IP2_MIO_W1C" , 0x10701034b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP27_IP2_MIO_W1C" , 0x10701036b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP28_IP2_MIO_W1C" , 0x10701038b3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP29_IP2_MIO_W1C" , 0x1070103ab3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP30_IP2_MIO_W1C" , 0x1070103cb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP31_IP2_MIO_W1C" , 0x1070103eb3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 116},
- {"CIU2_EN_PP0_IP2_MIO_W1S" , 0x10701000a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP1_IP2_MIO_W1S" , 0x10701002a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP2_IP2_MIO_W1S" , 0x10701004a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP3_IP2_MIO_W1S" , 0x10701006a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP4_IP2_MIO_W1S" , 0x10701008a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP5_IP2_MIO_W1S" , 0x1070100aa3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP6_IP2_MIO_W1S" , 0x1070100ca3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP7_IP2_MIO_W1S" , 0x1070100ea3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP8_IP2_MIO_W1S" , 0x10701010a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP9_IP2_MIO_W1S" , 0x10701012a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP10_IP2_MIO_W1S" , 0x10701014a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP11_IP2_MIO_W1S" , 0x10701016a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP12_IP2_MIO_W1S" , 0x10701018a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP13_IP2_MIO_W1S" , 0x1070101aa3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP14_IP2_MIO_W1S" , 0x1070101ca3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP15_IP2_MIO_W1S" , 0x1070101ea3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP16_IP2_MIO_W1S" , 0x10701020a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP17_IP2_MIO_W1S" , 0x10701022a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP18_IP2_MIO_W1S" , 0x10701024a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP19_IP2_MIO_W1S" , 0x10701026a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP20_IP2_MIO_W1S" , 0x10701028a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP21_IP2_MIO_W1S" , 0x1070102aa3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP22_IP2_MIO_W1S" , 0x1070102ca3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP23_IP2_MIO_W1S" , 0x1070102ea3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP24_IP2_MIO_W1S" , 0x10701030a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP25_IP2_MIO_W1S" , 0x10701032a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP26_IP2_MIO_W1S" , 0x10701034a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP27_IP2_MIO_W1S" , 0x10701036a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP28_IP2_MIO_W1S" , 0x10701038a3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP29_IP2_MIO_W1S" , 0x1070103aa3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP30_IP2_MIO_W1S" , 0x1070103ca3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP31_IP2_MIO_W1S" , 0x1070103ea3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 117},
- {"CIU2_EN_PP0_IP2_PKT" , 0x1070100096000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP1_IP2_PKT" , 0x1070100296000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP2_IP2_PKT" , 0x1070100496000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP3_IP2_PKT" , 0x1070100696000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP4_IP2_PKT" , 0x1070100896000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP5_IP2_PKT" , 0x1070100a96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP6_IP2_PKT" , 0x1070100c96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP7_IP2_PKT" , 0x1070100e96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP8_IP2_PKT" , 0x1070101096000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP9_IP2_PKT" , 0x1070101296000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP10_IP2_PKT" , 0x1070101496000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP11_IP2_PKT" , 0x1070101696000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP12_IP2_PKT" , 0x1070101896000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP13_IP2_PKT" , 0x1070101a96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP14_IP2_PKT" , 0x1070101c96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP15_IP2_PKT" , 0x1070101e96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP16_IP2_PKT" , 0x1070102096000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP17_IP2_PKT" , 0x1070102296000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP18_IP2_PKT" , 0x1070102496000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP19_IP2_PKT" , 0x1070102696000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP20_IP2_PKT" , 0x1070102896000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP21_IP2_PKT" , 0x1070102a96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP22_IP2_PKT" , 0x1070102c96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP23_IP2_PKT" , 0x1070102e96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP24_IP2_PKT" , 0x1070103096000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP25_IP2_PKT" , 0x1070103296000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP26_IP2_PKT" , 0x1070103496000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP27_IP2_PKT" , 0x1070103696000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP28_IP2_PKT" , 0x1070103896000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP29_IP2_PKT" , 0x1070103a96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP30_IP2_PKT" , 0x1070103c96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP31_IP2_PKT" , 0x1070103e96000ull, CVMX_CSR_DB_TYPE_NCB, 64, 118},
- {"CIU2_EN_PP0_IP2_PKT_W1C" , 0x10701000b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP1_IP2_PKT_W1C" , 0x10701002b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP2_IP2_PKT_W1C" , 0x10701004b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP3_IP2_PKT_W1C" , 0x10701006b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP4_IP2_PKT_W1C" , 0x10701008b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP5_IP2_PKT_W1C" , 0x1070100ab6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP6_IP2_PKT_W1C" , 0x1070100cb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP7_IP2_PKT_W1C" , 0x1070100eb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP8_IP2_PKT_W1C" , 0x10701010b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP9_IP2_PKT_W1C" , 0x10701012b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP10_IP2_PKT_W1C" , 0x10701014b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP11_IP2_PKT_W1C" , 0x10701016b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP12_IP2_PKT_W1C" , 0x10701018b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP13_IP2_PKT_W1C" , 0x1070101ab6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP14_IP2_PKT_W1C" , 0x1070101cb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP15_IP2_PKT_W1C" , 0x1070101eb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP16_IP2_PKT_W1C" , 0x10701020b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP17_IP2_PKT_W1C" , 0x10701022b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP18_IP2_PKT_W1C" , 0x10701024b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP19_IP2_PKT_W1C" , 0x10701026b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP20_IP2_PKT_W1C" , 0x10701028b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP21_IP2_PKT_W1C" , 0x1070102ab6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP22_IP2_PKT_W1C" , 0x1070102cb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP23_IP2_PKT_W1C" , 0x1070102eb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP24_IP2_PKT_W1C" , 0x10701030b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP25_IP2_PKT_W1C" , 0x10701032b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP26_IP2_PKT_W1C" , 0x10701034b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP27_IP2_PKT_W1C" , 0x10701036b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP28_IP2_PKT_W1C" , 0x10701038b6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP29_IP2_PKT_W1C" , 0x1070103ab6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP30_IP2_PKT_W1C" , 0x1070103cb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP31_IP2_PKT_W1C" , 0x1070103eb6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 119},
- {"CIU2_EN_PP0_IP2_PKT_W1S" , 0x10701000a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP1_IP2_PKT_W1S" , 0x10701002a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP2_IP2_PKT_W1S" , 0x10701004a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP3_IP2_PKT_W1S" , 0x10701006a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP4_IP2_PKT_W1S" , 0x10701008a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP5_IP2_PKT_W1S" , 0x1070100aa6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP6_IP2_PKT_W1S" , 0x1070100ca6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP7_IP2_PKT_W1S" , 0x1070100ea6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP8_IP2_PKT_W1S" , 0x10701010a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP9_IP2_PKT_W1S" , 0x10701012a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP10_IP2_PKT_W1S" , 0x10701014a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP11_IP2_PKT_W1S" , 0x10701016a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP12_IP2_PKT_W1S" , 0x10701018a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP13_IP2_PKT_W1S" , 0x1070101aa6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP14_IP2_PKT_W1S" , 0x1070101ca6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP15_IP2_PKT_W1S" , 0x1070101ea6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP16_IP2_PKT_W1S" , 0x10701020a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP17_IP2_PKT_W1S" , 0x10701022a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP18_IP2_PKT_W1S" , 0x10701024a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP19_IP2_PKT_W1S" , 0x10701026a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP20_IP2_PKT_W1S" , 0x10701028a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP21_IP2_PKT_W1S" , 0x1070102aa6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP22_IP2_PKT_W1S" , 0x1070102ca6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP23_IP2_PKT_W1S" , 0x1070102ea6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP24_IP2_PKT_W1S" , 0x10701030a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP25_IP2_PKT_W1S" , 0x10701032a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP26_IP2_PKT_W1S" , 0x10701034a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP27_IP2_PKT_W1S" , 0x10701036a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP28_IP2_PKT_W1S" , 0x10701038a6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP29_IP2_PKT_W1S" , 0x1070103aa6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP30_IP2_PKT_W1S" , 0x1070103ca6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP31_IP2_PKT_W1S" , 0x1070103ea6000ull, CVMX_CSR_DB_TYPE_NCB, 64, 120},
- {"CIU2_EN_PP0_IP2_RML" , 0x1070100092000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP1_IP2_RML" , 0x1070100292000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP2_IP2_RML" , 0x1070100492000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP3_IP2_RML" , 0x1070100692000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP4_IP2_RML" , 0x1070100892000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP5_IP2_RML" , 0x1070100a92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP6_IP2_RML" , 0x1070100c92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP7_IP2_RML" , 0x1070100e92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP8_IP2_RML" , 0x1070101092000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP9_IP2_RML" , 0x1070101292000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP10_IP2_RML" , 0x1070101492000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP11_IP2_RML" , 0x1070101692000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP12_IP2_RML" , 0x1070101892000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP13_IP2_RML" , 0x1070101a92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP14_IP2_RML" , 0x1070101c92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP15_IP2_RML" , 0x1070101e92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP16_IP2_RML" , 0x1070102092000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP17_IP2_RML" , 0x1070102292000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP18_IP2_RML" , 0x1070102492000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP19_IP2_RML" , 0x1070102692000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP20_IP2_RML" , 0x1070102892000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP21_IP2_RML" , 0x1070102a92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP22_IP2_RML" , 0x1070102c92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP23_IP2_RML" , 0x1070102e92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP24_IP2_RML" , 0x1070103092000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP25_IP2_RML" , 0x1070103292000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP26_IP2_RML" , 0x1070103492000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP27_IP2_RML" , 0x1070103692000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP28_IP2_RML" , 0x1070103892000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP29_IP2_RML" , 0x1070103a92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP30_IP2_RML" , 0x1070103c92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP31_IP2_RML" , 0x1070103e92000ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
- {"CIU2_EN_PP0_IP2_RML_W1C" , 0x10701000b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP1_IP2_RML_W1C" , 0x10701002b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP2_IP2_RML_W1C" , 0x10701004b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP3_IP2_RML_W1C" , 0x10701006b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP4_IP2_RML_W1C" , 0x10701008b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP5_IP2_RML_W1C" , 0x1070100ab2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP6_IP2_RML_W1C" , 0x1070100cb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP7_IP2_RML_W1C" , 0x1070100eb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP8_IP2_RML_W1C" , 0x10701010b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP9_IP2_RML_W1C" , 0x10701012b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP10_IP2_RML_W1C" , 0x10701014b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP11_IP2_RML_W1C" , 0x10701016b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP12_IP2_RML_W1C" , 0x10701018b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP13_IP2_RML_W1C" , 0x1070101ab2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP14_IP2_RML_W1C" , 0x1070101cb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP15_IP2_RML_W1C" , 0x1070101eb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP16_IP2_RML_W1C" , 0x10701020b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP17_IP2_RML_W1C" , 0x10701022b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP18_IP2_RML_W1C" , 0x10701024b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP19_IP2_RML_W1C" , 0x10701026b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP20_IP2_RML_W1C" , 0x10701028b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP21_IP2_RML_W1C" , 0x1070102ab2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP22_IP2_RML_W1C" , 0x1070102cb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP23_IP2_RML_W1C" , 0x1070102eb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP24_IP2_RML_W1C" , 0x10701030b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP25_IP2_RML_W1C" , 0x10701032b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP26_IP2_RML_W1C" , 0x10701034b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP27_IP2_RML_W1C" , 0x10701036b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP28_IP2_RML_W1C" , 0x10701038b2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP29_IP2_RML_W1C" , 0x1070103ab2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP30_IP2_RML_W1C" , 0x1070103cb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP31_IP2_RML_W1C" , 0x1070103eb2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
- {"CIU2_EN_PP0_IP2_RML_W1S" , 0x10701000a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP1_IP2_RML_W1S" , 0x10701002a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP2_IP2_RML_W1S" , 0x10701004a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP3_IP2_RML_W1S" , 0x10701006a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP4_IP2_RML_W1S" , 0x10701008a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP5_IP2_RML_W1S" , 0x1070100aa2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP6_IP2_RML_W1S" , 0x1070100ca2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP7_IP2_RML_W1S" , 0x1070100ea2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP8_IP2_RML_W1S" , 0x10701010a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP9_IP2_RML_W1S" , 0x10701012a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP10_IP2_RML_W1S" , 0x10701014a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP11_IP2_RML_W1S" , 0x10701016a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP12_IP2_RML_W1S" , 0x10701018a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP13_IP2_RML_W1S" , 0x1070101aa2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP14_IP2_RML_W1S" , 0x1070101ca2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP15_IP2_RML_W1S" , 0x1070101ea2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP16_IP2_RML_W1S" , 0x10701020a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP17_IP2_RML_W1S" , 0x10701022a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP18_IP2_RML_W1S" , 0x10701024a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP19_IP2_RML_W1S" , 0x10701026a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP20_IP2_RML_W1S" , 0x10701028a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP21_IP2_RML_W1S" , 0x1070102aa2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP22_IP2_RML_W1S" , 0x1070102ca2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP23_IP2_RML_W1S" , 0x1070102ea2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP24_IP2_RML_W1S" , 0x10701030a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP25_IP2_RML_W1S" , 0x10701032a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP26_IP2_RML_W1S" , 0x10701034a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP27_IP2_RML_W1S" , 0x10701036a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP28_IP2_RML_W1S" , 0x10701038a2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP29_IP2_RML_W1S" , 0x1070103aa2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP30_IP2_RML_W1S" , 0x1070103ca2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP31_IP2_RML_W1S" , 0x1070103ea2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
- {"CIU2_EN_PP0_IP2_WDOG" , 0x1070100091000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP1_IP2_WDOG" , 0x1070100291000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP2_IP2_WDOG" , 0x1070100491000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP3_IP2_WDOG" , 0x1070100691000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP4_IP2_WDOG" , 0x1070100891000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP5_IP2_WDOG" , 0x1070100a91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP6_IP2_WDOG" , 0x1070100c91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP7_IP2_WDOG" , 0x1070100e91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP8_IP2_WDOG" , 0x1070101091000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP9_IP2_WDOG" , 0x1070101291000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP10_IP2_WDOG" , 0x1070101491000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP11_IP2_WDOG" , 0x1070101691000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP12_IP2_WDOG" , 0x1070101891000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP13_IP2_WDOG" , 0x1070101a91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP14_IP2_WDOG" , 0x1070101c91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP15_IP2_WDOG" , 0x1070101e91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP16_IP2_WDOG" , 0x1070102091000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP17_IP2_WDOG" , 0x1070102291000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP18_IP2_WDOG" , 0x1070102491000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP19_IP2_WDOG" , 0x1070102691000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP20_IP2_WDOG" , 0x1070102891000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP21_IP2_WDOG" , 0x1070102a91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP22_IP2_WDOG" , 0x1070102c91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP23_IP2_WDOG" , 0x1070102e91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP24_IP2_WDOG" , 0x1070103091000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP25_IP2_WDOG" , 0x1070103291000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP26_IP2_WDOG" , 0x1070103491000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP27_IP2_WDOG" , 0x1070103691000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP28_IP2_WDOG" , 0x1070103891000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP29_IP2_WDOG" , 0x1070103a91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP30_IP2_WDOG" , 0x1070103c91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP31_IP2_WDOG" , 0x1070103e91000ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
- {"CIU2_EN_PP0_IP2_WDOG_W1C" , 0x10701000b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP1_IP2_WDOG_W1C" , 0x10701002b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP2_IP2_WDOG_W1C" , 0x10701004b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP3_IP2_WDOG_W1C" , 0x10701006b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP4_IP2_WDOG_W1C" , 0x10701008b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP5_IP2_WDOG_W1C" , 0x1070100ab1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP6_IP2_WDOG_W1C" , 0x1070100cb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP7_IP2_WDOG_W1C" , 0x1070100eb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP8_IP2_WDOG_W1C" , 0x10701010b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP9_IP2_WDOG_W1C" , 0x10701012b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP10_IP2_WDOG_W1C" , 0x10701014b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP11_IP2_WDOG_W1C" , 0x10701016b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP12_IP2_WDOG_W1C" , 0x10701018b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP13_IP2_WDOG_W1C" , 0x1070101ab1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP14_IP2_WDOG_W1C" , 0x1070101cb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP15_IP2_WDOG_W1C" , 0x1070101eb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP16_IP2_WDOG_W1C" , 0x10701020b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP17_IP2_WDOG_W1C" , 0x10701022b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP18_IP2_WDOG_W1C" , 0x10701024b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP19_IP2_WDOG_W1C" , 0x10701026b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP20_IP2_WDOG_W1C" , 0x10701028b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP21_IP2_WDOG_W1C" , 0x1070102ab1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP22_IP2_WDOG_W1C" , 0x1070102cb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP23_IP2_WDOG_W1C" , 0x1070102eb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP24_IP2_WDOG_W1C" , 0x10701030b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP25_IP2_WDOG_W1C" , 0x10701032b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP26_IP2_WDOG_W1C" , 0x10701034b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP27_IP2_WDOG_W1C" , 0x10701036b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP28_IP2_WDOG_W1C" , 0x10701038b1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP29_IP2_WDOG_W1C" , 0x1070103ab1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP30_IP2_WDOG_W1C" , 0x1070103cb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP31_IP2_WDOG_W1C" , 0x1070103eb1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
- {"CIU2_EN_PP0_IP2_WDOG_W1S" , 0x10701000a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP1_IP2_WDOG_W1S" , 0x10701002a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP2_IP2_WDOG_W1S" , 0x10701004a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP3_IP2_WDOG_W1S" , 0x10701006a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP4_IP2_WDOG_W1S" , 0x10701008a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP5_IP2_WDOG_W1S" , 0x1070100aa1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP6_IP2_WDOG_W1S" , 0x1070100ca1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP7_IP2_WDOG_W1S" , 0x1070100ea1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP8_IP2_WDOG_W1S" , 0x10701010a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP9_IP2_WDOG_W1S" , 0x10701012a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP10_IP2_WDOG_W1S" , 0x10701014a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP11_IP2_WDOG_W1S" , 0x10701016a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP12_IP2_WDOG_W1S" , 0x10701018a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP13_IP2_WDOG_W1S" , 0x1070101aa1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP14_IP2_WDOG_W1S" , 0x1070101ca1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP15_IP2_WDOG_W1S" , 0x1070101ea1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP16_IP2_WDOG_W1S" , 0x10701020a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP17_IP2_WDOG_W1S" , 0x10701022a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP18_IP2_WDOG_W1S" , 0x10701024a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP19_IP2_WDOG_W1S" , 0x10701026a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP20_IP2_WDOG_W1S" , 0x10701028a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP21_IP2_WDOG_W1S" , 0x1070102aa1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP22_IP2_WDOG_W1S" , 0x1070102ca1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP23_IP2_WDOG_W1S" , 0x1070102ea1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP24_IP2_WDOG_W1S" , 0x10701030a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP25_IP2_WDOG_W1S" , 0x10701032a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP26_IP2_WDOG_W1S" , 0x10701034a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP27_IP2_WDOG_W1S" , 0x10701036a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP28_IP2_WDOG_W1S" , 0x10701038a1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP29_IP2_WDOG_W1S" , 0x1070103aa1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP30_IP2_WDOG_W1S" , 0x1070103ca1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP31_IP2_WDOG_W1S" , 0x1070103ea1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
- {"CIU2_EN_PP0_IP2_WRKQ" , 0x1070100090000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP1_IP2_WRKQ" , 0x1070100290000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP2_IP2_WRKQ" , 0x1070100490000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP3_IP2_WRKQ" , 0x1070100690000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP4_IP2_WRKQ" , 0x1070100890000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP5_IP2_WRKQ" , 0x1070100a90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP6_IP2_WRKQ" , 0x1070100c90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP7_IP2_WRKQ" , 0x1070100e90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP8_IP2_WRKQ" , 0x1070101090000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP9_IP2_WRKQ" , 0x1070101290000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP10_IP2_WRKQ" , 0x1070101490000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP11_IP2_WRKQ" , 0x1070101690000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP12_IP2_WRKQ" , 0x1070101890000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP13_IP2_WRKQ" , 0x1070101a90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP14_IP2_WRKQ" , 0x1070101c90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP15_IP2_WRKQ" , 0x1070101e90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP16_IP2_WRKQ" , 0x1070102090000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP17_IP2_WRKQ" , 0x1070102290000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP18_IP2_WRKQ" , 0x1070102490000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP19_IP2_WRKQ" , 0x1070102690000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP20_IP2_WRKQ" , 0x1070102890000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP21_IP2_WRKQ" , 0x1070102a90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP22_IP2_WRKQ" , 0x1070102c90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP23_IP2_WRKQ" , 0x1070102e90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP24_IP2_WRKQ" , 0x1070103090000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP25_IP2_WRKQ" , 0x1070103290000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP26_IP2_WRKQ" , 0x1070103490000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP27_IP2_WRKQ" , 0x1070103690000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP28_IP2_WRKQ" , 0x1070103890000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP29_IP2_WRKQ" , 0x1070103a90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP30_IP2_WRKQ" , 0x1070103c90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP31_IP2_WRKQ" , 0x1070103e90000ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
- {"CIU2_EN_PP0_IP2_WRKQ_W1C" , 0x10701000b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP1_IP2_WRKQ_W1C" , 0x10701002b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP2_IP2_WRKQ_W1C" , 0x10701004b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP3_IP2_WRKQ_W1C" , 0x10701006b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP4_IP2_WRKQ_W1C" , 0x10701008b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP5_IP2_WRKQ_W1C" , 0x1070100ab0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP6_IP2_WRKQ_W1C" , 0x1070100cb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP7_IP2_WRKQ_W1C" , 0x1070100eb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP8_IP2_WRKQ_W1C" , 0x10701010b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP9_IP2_WRKQ_W1C" , 0x10701012b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP10_IP2_WRKQ_W1C" , 0x10701014b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP11_IP2_WRKQ_W1C" , 0x10701016b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP12_IP2_WRKQ_W1C" , 0x10701018b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP13_IP2_WRKQ_W1C" , 0x1070101ab0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP14_IP2_WRKQ_W1C" , 0x1070101cb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP15_IP2_WRKQ_W1C" , 0x1070101eb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP16_IP2_WRKQ_W1C" , 0x10701020b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP17_IP2_WRKQ_W1C" , 0x10701022b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP18_IP2_WRKQ_W1C" , 0x10701024b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP19_IP2_WRKQ_W1C" , 0x10701026b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP20_IP2_WRKQ_W1C" , 0x10701028b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP21_IP2_WRKQ_W1C" , 0x1070102ab0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP22_IP2_WRKQ_W1C" , 0x1070102cb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP23_IP2_WRKQ_W1C" , 0x1070102eb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP24_IP2_WRKQ_W1C" , 0x10701030b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP25_IP2_WRKQ_W1C" , 0x10701032b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP26_IP2_WRKQ_W1C" , 0x10701034b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP27_IP2_WRKQ_W1C" , 0x10701036b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP28_IP2_WRKQ_W1C" , 0x10701038b0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP29_IP2_WRKQ_W1C" , 0x1070103ab0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP30_IP2_WRKQ_W1C" , 0x1070103cb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP31_IP2_WRKQ_W1C" , 0x1070103eb0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
- {"CIU2_EN_PP0_IP2_WRKQ_W1S" , 0x10701000a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP1_IP2_WRKQ_W1S" , 0x10701002a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP2_IP2_WRKQ_W1S" , 0x10701004a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP3_IP2_WRKQ_W1S" , 0x10701006a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP4_IP2_WRKQ_W1S" , 0x10701008a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP5_IP2_WRKQ_W1S" , 0x1070100aa0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP6_IP2_WRKQ_W1S" , 0x1070100ca0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP7_IP2_WRKQ_W1S" , 0x1070100ea0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP8_IP2_WRKQ_W1S" , 0x10701010a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP9_IP2_WRKQ_W1S" , 0x10701012a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP10_IP2_WRKQ_W1S" , 0x10701014a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP11_IP2_WRKQ_W1S" , 0x10701016a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP12_IP2_WRKQ_W1S" , 0x10701018a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP13_IP2_WRKQ_W1S" , 0x1070101aa0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP14_IP2_WRKQ_W1S" , 0x1070101ca0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP15_IP2_WRKQ_W1S" , 0x1070101ea0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP16_IP2_WRKQ_W1S" , 0x10701020a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP17_IP2_WRKQ_W1S" , 0x10701022a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP18_IP2_WRKQ_W1S" , 0x10701024a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP19_IP2_WRKQ_W1S" , 0x10701026a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP20_IP2_WRKQ_W1S" , 0x10701028a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP21_IP2_WRKQ_W1S" , 0x1070102aa0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP22_IP2_WRKQ_W1S" , 0x1070102ca0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP23_IP2_WRKQ_W1S" , 0x1070102ea0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP24_IP2_WRKQ_W1S" , 0x10701030a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP25_IP2_WRKQ_W1S" , 0x10701032a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP26_IP2_WRKQ_W1S" , 0x10701034a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP27_IP2_WRKQ_W1S" , 0x10701036a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP28_IP2_WRKQ_W1S" , 0x10701038a0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP29_IP2_WRKQ_W1S" , 0x1070103aa0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP30_IP2_WRKQ_W1S" , 0x1070103ca0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP31_IP2_WRKQ_W1S" , 0x1070103ea0000ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
- {"CIU2_EN_PP0_IP3_GPIO" , 0x1070100097200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP1_IP3_GPIO" , 0x1070100297200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP2_IP3_GPIO" , 0x1070100497200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP3_IP3_GPIO" , 0x1070100697200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP4_IP3_GPIO" , 0x1070100897200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP5_IP3_GPIO" , 0x1070100a97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP6_IP3_GPIO" , 0x1070100c97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP7_IP3_GPIO" , 0x1070100e97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP8_IP3_GPIO" , 0x1070101097200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP9_IP3_GPIO" , 0x1070101297200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP10_IP3_GPIO" , 0x1070101497200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP11_IP3_GPIO" , 0x1070101697200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP12_IP3_GPIO" , 0x1070101897200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP13_IP3_GPIO" , 0x1070101a97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP14_IP3_GPIO" , 0x1070101c97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP15_IP3_GPIO" , 0x1070101e97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP16_IP3_GPIO" , 0x1070102097200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP17_IP3_GPIO" , 0x1070102297200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP18_IP3_GPIO" , 0x1070102497200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP19_IP3_GPIO" , 0x1070102697200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP20_IP3_GPIO" , 0x1070102897200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP21_IP3_GPIO" , 0x1070102a97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP22_IP3_GPIO" , 0x1070102c97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP23_IP3_GPIO" , 0x1070102e97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP24_IP3_GPIO" , 0x1070103097200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP25_IP3_GPIO" , 0x1070103297200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP26_IP3_GPIO" , 0x1070103497200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP27_IP3_GPIO" , 0x1070103697200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP28_IP3_GPIO" , 0x1070103897200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP29_IP3_GPIO" , 0x1070103a97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP30_IP3_GPIO" , 0x1070103c97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP31_IP3_GPIO" , 0x1070103e97200ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
- {"CIU2_EN_PP0_IP3_GPIO_W1C" , 0x10701000b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP1_IP3_GPIO_W1C" , 0x10701002b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP2_IP3_GPIO_W1C" , 0x10701004b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP3_IP3_GPIO_W1C" , 0x10701006b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP4_IP3_GPIO_W1C" , 0x10701008b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP5_IP3_GPIO_W1C" , 0x1070100ab7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP6_IP3_GPIO_W1C" , 0x1070100cb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP7_IP3_GPIO_W1C" , 0x1070100eb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP8_IP3_GPIO_W1C" , 0x10701010b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP9_IP3_GPIO_W1C" , 0x10701012b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP10_IP3_GPIO_W1C" , 0x10701014b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP11_IP3_GPIO_W1C" , 0x10701016b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP12_IP3_GPIO_W1C" , 0x10701018b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP13_IP3_GPIO_W1C" , 0x1070101ab7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP14_IP3_GPIO_W1C" , 0x1070101cb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP15_IP3_GPIO_W1C" , 0x1070101eb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP16_IP3_GPIO_W1C" , 0x10701020b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP17_IP3_GPIO_W1C" , 0x10701022b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP18_IP3_GPIO_W1C" , 0x10701024b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP19_IP3_GPIO_W1C" , 0x10701026b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP20_IP3_GPIO_W1C" , 0x10701028b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP21_IP3_GPIO_W1C" , 0x1070102ab7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP22_IP3_GPIO_W1C" , 0x1070102cb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP23_IP3_GPIO_W1C" , 0x1070102eb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP24_IP3_GPIO_W1C" , 0x10701030b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP25_IP3_GPIO_W1C" , 0x10701032b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP26_IP3_GPIO_W1C" , 0x10701034b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP27_IP3_GPIO_W1C" , 0x10701036b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP28_IP3_GPIO_W1C" , 0x10701038b7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP29_IP3_GPIO_W1C" , 0x1070103ab7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP30_IP3_GPIO_W1C" , 0x1070103cb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP31_IP3_GPIO_W1C" , 0x1070103eb7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 131},
- {"CIU2_EN_PP0_IP3_GPIO_W1S" , 0x10701000a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP1_IP3_GPIO_W1S" , 0x10701002a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP2_IP3_GPIO_W1S" , 0x10701004a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP3_IP3_GPIO_W1S" , 0x10701006a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP4_IP3_GPIO_W1S" , 0x10701008a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP5_IP3_GPIO_W1S" , 0x1070100aa7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP6_IP3_GPIO_W1S" , 0x1070100ca7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP7_IP3_GPIO_W1S" , 0x1070100ea7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP8_IP3_GPIO_W1S" , 0x10701010a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP9_IP3_GPIO_W1S" , 0x10701012a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP10_IP3_GPIO_W1S" , 0x10701014a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP11_IP3_GPIO_W1S" , 0x10701016a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP12_IP3_GPIO_W1S" , 0x10701018a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP13_IP3_GPIO_W1S" , 0x1070101aa7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP14_IP3_GPIO_W1S" , 0x1070101ca7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP15_IP3_GPIO_W1S" , 0x1070101ea7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP16_IP3_GPIO_W1S" , 0x10701020a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP17_IP3_GPIO_W1S" , 0x10701022a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP18_IP3_GPIO_W1S" , 0x10701024a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP19_IP3_GPIO_W1S" , 0x10701026a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP20_IP3_GPIO_W1S" , 0x10701028a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP21_IP3_GPIO_W1S" , 0x1070102aa7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP22_IP3_GPIO_W1S" , 0x1070102ca7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP23_IP3_GPIO_W1S" , 0x1070102ea7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP24_IP3_GPIO_W1S" , 0x10701030a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP25_IP3_GPIO_W1S" , 0x10701032a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP26_IP3_GPIO_W1S" , 0x10701034a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP27_IP3_GPIO_W1S" , 0x10701036a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP28_IP3_GPIO_W1S" , 0x10701038a7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP29_IP3_GPIO_W1S" , 0x1070103aa7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP30_IP3_GPIO_W1S" , 0x1070103ca7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP31_IP3_GPIO_W1S" , 0x1070103ea7200ull, CVMX_CSR_DB_TYPE_NCB, 64, 132},
- {"CIU2_EN_PP0_IP3_IO" , 0x1070100094200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP1_IP3_IO" , 0x1070100294200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP2_IP3_IO" , 0x1070100494200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP3_IP3_IO" , 0x1070100694200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP4_IP3_IO" , 0x1070100894200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP5_IP3_IO" , 0x1070100a94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP6_IP3_IO" , 0x1070100c94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP7_IP3_IO" , 0x1070100e94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP8_IP3_IO" , 0x1070101094200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP9_IP3_IO" , 0x1070101294200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP10_IP3_IO" , 0x1070101494200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP11_IP3_IO" , 0x1070101694200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP12_IP3_IO" , 0x1070101894200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP13_IP3_IO" , 0x1070101a94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP14_IP3_IO" , 0x1070101c94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP15_IP3_IO" , 0x1070101e94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP16_IP3_IO" , 0x1070102094200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP17_IP3_IO" , 0x1070102294200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP18_IP3_IO" , 0x1070102494200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP19_IP3_IO" , 0x1070102694200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP20_IP3_IO" , 0x1070102894200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP21_IP3_IO" , 0x1070102a94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP22_IP3_IO" , 0x1070102c94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP23_IP3_IO" , 0x1070102e94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP24_IP3_IO" , 0x1070103094200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP25_IP3_IO" , 0x1070103294200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP26_IP3_IO" , 0x1070103494200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP27_IP3_IO" , 0x1070103694200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP28_IP3_IO" , 0x1070103894200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP29_IP3_IO" , 0x1070103a94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP30_IP3_IO" , 0x1070103c94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP31_IP3_IO" , 0x1070103e94200ull, CVMX_CSR_DB_TYPE_NCB, 64, 133},
- {"CIU2_EN_PP0_IP3_IO_W1C" , 0x10701000b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP1_IP3_IO_W1C" , 0x10701002b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP2_IP3_IO_W1C" , 0x10701004b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP3_IP3_IO_W1C" , 0x10701006b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP4_IP3_IO_W1C" , 0x10701008b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP5_IP3_IO_W1C" , 0x1070100ab4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP6_IP3_IO_W1C" , 0x1070100cb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP7_IP3_IO_W1C" , 0x1070100eb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP8_IP3_IO_W1C" , 0x10701010b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP9_IP3_IO_W1C" , 0x10701012b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP10_IP3_IO_W1C" , 0x10701014b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP11_IP3_IO_W1C" , 0x10701016b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP12_IP3_IO_W1C" , 0x10701018b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP13_IP3_IO_W1C" , 0x1070101ab4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP14_IP3_IO_W1C" , 0x1070101cb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP15_IP3_IO_W1C" , 0x1070101eb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP16_IP3_IO_W1C" , 0x10701020b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP17_IP3_IO_W1C" , 0x10701022b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP18_IP3_IO_W1C" , 0x10701024b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP19_IP3_IO_W1C" , 0x10701026b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP20_IP3_IO_W1C" , 0x10701028b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP21_IP3_IO_W1C" , 0x1070102ab4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP22_IP3_IO_W1C" , 0x1070102cb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP23_IP3_IO_W1C" , 0x1070102eb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP24_IP3_IO_W1C" , 0x10701030b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP25_IP3_IO_W1C" , 0x10701032b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP26_IP3_IO_W1C" , 0x10701034b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP27_IP3_IO_W1C" , 0x10701036b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP28_IP3_IO_W1C" , 0x10701038b4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP29_IP3_IO_W1C" , 0x1070103ab4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP30_IP3_IO_W1C" , 0x1070103cb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP31_IP3_IO_W1C" , 0x1070103eb4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 134},
- {"CIU2_EN_PP0_IP3_IO_W1S" , 0x10701000a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP1_IP3_IO_W1S" , 0x10701002a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP2_IP3_IO_W1S" , 0x10701004a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP3_IP3_IO_W1S" , 0x10701006a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP4_IP3_IO_W1S" , 0x10701008a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP5_IP3_IO_W1S" , 0x1070100aa4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP6_IP3_IO_W1S" , 0x1070100ca4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP7_IP3_IO_W1S" , 0x1070100ea4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP8_IP3_IO_W1S" , 0x10701010a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP9_IP3_IO_W1S" , 0x10701012a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP10_IP3_IO_W1S" , 0x10701014a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP11_IP3_IO_W1S" , 0x10701016a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP12_IP3_IO_W1S" , 0x10701018a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP13_IP3_IO_W1S" , 0x1070101aa4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP14_IP3_IO_W1S" , 0x1070101ca4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP15_IP3_IO_W1S" , 0x1070101ea4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP16_IP3_IO_W1S" , 0x10701020a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP17_IP3_IO_W1S" , 0x10701022a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP18_IP3_IO_W1S" , 0x10701024a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP19_IP3_IO_W1S" , 0x10701026a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP20_IP3_IO_W1S" , 0x10701028a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP21_IP3_IO_W1S" , 0x1070102aa4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP22_IP3_IO_W1S" , 0x1070102ca4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP23_IP3_IO_W1S" , 0x1070102ea4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP24_IP3_IO_W1S" , 0x10701030a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP25_IP3_IO_W1S" , 0x10701032a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP26_IP3_IO_W1S" , 0x10701034a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP27_IP3_IO_W1S" , 0x10701036a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP28_IP3_IO_W1S" , 0x10701038a4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP29_IP3_IO_W1S" , 0x1070103aa4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP30_IP3_IO_W1S" , 0x1070103ca4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP31_IP3_IO_W1S" , 0x1070103ea4200ull, CVMX_CSR_DB_TYPE_NCB, 64, 135},
- {"CIU2_EN_PP0_IP3_MBOX" , 0x1070100098200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP1_IP3_MBOX" , 0x1070100298200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP2_IP3_MBOX" , 0x1070100498200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP3_IP3_MBOX" , 0x1070100698200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP4_IP3_MBOX" , 0x1070100898200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP5_IP3_MBOX" , 0x1070100a98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP6_IP3_MBOX" , 0x1070100c98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP7_IP3_MBOX" , 0x1070100e98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP8_IP3_MBOX" , 0x1070101098200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP9_IP3_MBOX" , 0x1070101298200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP10_IP3_MBOX" , 0x1070101498200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP11_IP3_MBOX" , 0x1070101698200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP12_IP3_MBOX" , 0x1070101898200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP13_IP3_MBOX" , 0x1070101a98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP14_IP3_MBOX" , 0x1070101c98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP15_IP3_MBOX" , 0x1070101e98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP16_IP3_MBOX" , 0x1070102098200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP17_IP3_MBOX" , 0x1070102298200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP18_IP3_MBOX" , 0x1070102498200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP19_IP3_MBOX" , 0x1070102698200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP20_IP3_MBOX" , 0x1070102898200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP21_IP3_MBOX" , 0x1070102a98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP22_IP3_MBOX" , 0x1070102c98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP23_IP3_MBOX" , 0x1070102e98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP24_IP3_MBOX" , 0x1070103098200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP25_IP3_MBOX" , 0x1070103298200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP26_IP3_MBOX" , 0x1070103498200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP27_IP3_MBOX" , 0x1070103698200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP28_IP3_MBOX" , 0x1070103898200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP29_IP3_MBOX" , 0x1070103a98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP30_IP3_MBOX" , 0x1070103c98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP31_IP3_MBOX" , 0x1070103e98200ull, CVMX_CSR_DB_TYPE_NCB, 64, 136},
- {"CIU2_EN_PP0_IP3_MBOX_W1C" , 0x10701000b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP1_IP3_MBOX_W1C" , 0x10701002b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP2_IP3_MBOX_W1C" , 0x10701004b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP3_IP3_MBOX_W1C" , 0x10701006b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP4_IP3_MBOX_W1C" , 0x10701008b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP5_IP3_MBOX_W1C" , 0x1070100ab8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP6_IP3_MBOX_W1C" , 0x1070100cb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP7_IP3_MBOX_W1C" , 0x1070100eb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP8_IP3_MBOX_W1C" , 0x10701010b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP9_IP3_MBOX_W1C" , 0x10701012b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP10_IP3_MBOX_W1C" , 0x10701014b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP11_IP3_MBOX_W1C" , 0x10701016b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP12_IP3_MBOX_W1C" , 0x10701018b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP13_IP3_MBOX_W1C" , 0x1070101ab8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP14_IP3_MBOX_W1C" , 0x1070101cb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP15_IP3_MBOX_W1C" , 0x1070101eb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP16_IP3_MBOX_W1C" , 0x10701020b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP17_IP3_MBOX_W1C" , 0x10701022b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP18_IP3_MBOX_W1C" , 0x10701024b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP19_IP3_MBOX_W1C" , 0x10701026b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP20_IP3_MBOX_W1C" , 0x10701028b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP21_IP3_MBOX_W1C" , 0x1070102ab8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP22_IP3_MBOX_W1C" , 0x1070102cb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP23_IP3_MBOX_W1C" , 0x1070102eb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP24_IP3_MBOX_W1C" , 0x10701030b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP25_IP3_MBOX_W1C" , 0x10701032b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP26_IP3_MBOX_W1C" , 0x10701034b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP27_IP3_MBOX_W1C" , 0x10701036b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP28_IP3_MBOX_W1C" , 0x10701038b8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP29_IP3_MBOX_W1C" , 0x1070103ab8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP30_IP3_MBOX_W1C" , 0x1070103cb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP31_IP3_MBOX_W1C" , 0x1070103eb8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 137},
- {"CIU2_EN_PP0_IP3_MBOX_W1S" , 0x10701000a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP1_IP3_MBOX_W1S" , 0x10701002a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP2_IP3_MBOX_W1S" , 0x10701004a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP3_IP3_MBOX_W1S" , 0x10701006a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP4_IP3_MBOX_W1S" , 0x10701008a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP5_IP3_MBOX_W1S" , 0x1070100aa8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP6_IP3_MBOX_W1S" , 0x1070100ca8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP7_IP3_MBOX_W1S" , 0x1070100ea8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP8_IP3_MBOX_W1S" , 0x10701010a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP9_IP3_MBOX_W1S" , 0x10701012a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP10_IP3_MBOX_W1S" , 0x10701014a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP11_IP3_MBOX_W1S" , 0x10701016a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP12_IP3_MBOX_W1S" , 0x10701018a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP13_IP3_MBOX_W1S" , 0x1070101aa8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP14_IP3_MBOX_W1S" , 0x1070101ca8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP15_IP3_MBOX_W1S" , 0x1070101ea8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP16_IP3_MBOX_W1S" , 0x10701020a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP17_IP3_MBOX_W1S" , 0x10701022a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP18_IP3_MBOX_W1S" , 0x10701024a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP19_IP3_MBOX_W1S" , 0x10701026a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP20_IP3_MBOX_W1S" , 0x10701028a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP21_IP3_MBOX_W1S" , 0x1070102aa8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP22_IP3_MBOX_W1S" , 0x1070102ca8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP23_IP3_MBOX_W1S" , 0x1070102ea8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP24_IP3_MBOX_W1S" , 0x10701030a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP25_IP3_MBOX_W1S" , 0x10701032a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP26_IP3_MBOX_W1S" , 0x10701034a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP27_IP3_MBOX_W1S" , 0x10701036a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP28_IP3_MBOX_W1S" , 0x10701038a8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP29_IP3_MBOX_W1S" , 0x1070103aa8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP30_IP3_MBOX_W1S" , 0x1070103ca8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP31_IP3_MBOX_W1S" , 0x1070103ea8200ull, CVMX_CSR_DB_TYPE_NCB, 64, 138},
- {"CIU2_EN_PP0_IP3_MEM" , 0x1070100095200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP1_IP3_MEM" , 0x1070100295200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP2_IP3_MEM" , 0x1070100495200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP3_IP3_MEM" , 0x1070100695200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP4_IP3_MEM" , 0x1070100895200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP5_IP3_MEM" , 0x1070100a95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP6_IP3_MEM" , 0x1070100c95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP7_IP3_MEM" , 0x1070100e95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP8_IP3_MEM" , 0x1070101095200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP9_IP3_MEM" , 0x1070101295200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP10_IP3_MEM" , 0x1070101495200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP11_IP3_MEM" , 0x1070101695200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP12_IP3_MEM" , 0x1070101895200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP13_IP3_MEM" , 0x1070101a95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP14_IP3_MEM" , 0x1070101c95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP15_IP3_MEM" , 0x1070101e95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP16_IP3_MEM" , 0x1070102095200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP17_IP3_MEM" , 0x1070102295200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP18_IP3_MEM" , 0x1070102495200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP19_IP3_MEM" , 0x1070102695200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP20_IP3_MEM" , 0x1070102895200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP21_IP3_MEM" , 0x1070102a95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP22_IP3_MEM" , 0x1070102c95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP23_IP3_MEM" , 0x1070102e95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP24_IP3_MEM" , 0x1070103095200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP25_IP3_MEM" , 0x1070103295200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP26_IP3_MEM" , 0x1070103495200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP27_IP3_MEM" , 0x1070103695200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP28_IP3_MEM" , 0x1070103895200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP29_IP3_MEM" , 0x1070103a95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP30_IP3_MEM" , 0x1070103c95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP31_IP3_MEM" , 0x1070103e95200ull, CVMX_CSR_DB_TYPE_NCB, 64, 139},
- {"CIU2_EN_PP0_IP3_MEM_W1C" , 0x10701000b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP1_IP3_MEM_W1C" , 0x10701002b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP2_IP3_MEM_W1C" , 0x10701004b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP3_IP3_MEM_W1C" , 0x10701006b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP4_IP3_MEM_W1C" , 0x10701008b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP5_IP3_MEM_W1C" , 0x1070100ab5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP6_IP3_MEM_W1C" , 0x1070100cb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP7_IP3_MEM_W1C" , 0x1070100eb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP8_IP3_MEM_W1C" , 0x10701010b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP9_IP3_MEM_W1C" , 0x10701012b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP10_IP3_MEM_W1C" , 0x10701014b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP11_IP3_MEM_W1C" , 0x10701016b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP12_IP3_MEM_W1C" , 0x10701018b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP13_IP3_MEM_W1C" , 0x1070101ab5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP14_IP3_MEM_W1C" , 0x1070101cb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP15_IP3_MEM_W1C" , 0x1070101eb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP16_IP3_MEM_W1C" , 0x10701020b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP17_IP3_MEM_W1C" , 0x10701022b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP18_IP3_MEM_W1C" , 0x10701024b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP19_IP3_MEM_W1C" , 0x10701026b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP20_IP3_MEM_W1C" , 0x10701028b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP21_IP3_MEM_W1C" , 0x1070102ab5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP22_IP3_MEM_W1C" , 0x1070102cb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP23_IP3_MEM_W1C" , 0x1070102eb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP24_IP3_MEM_W1C" , 0x10701030b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP25_IP3_MEM_W1C" , 0x10701032b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP26_IP3_MEM_W1C" , 0x10701034b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP27_IP3_MEM_W1C" , 0x10701036b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP28_IP3_MEM_W1C" , 0x10701038b5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP29_IP3_MEM_W1C" , 0x1070103ab5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP30_IP3_MEM_W1C" , 0x1070103cb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP31_IP3_MEM_W1C" , 0x1070103eb5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 140},
- {"CIU2_EN_PP0_IP3_MEM_W1S" , 0x10701000a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP1_IP3_MEM_W1S" , 0x10701002a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP2_IP3_MEM_W1S" , 0x10701004a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP3_IP3_MEM_W1S" , 0x10701006a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP4_IP3_MEM_W1S" , 0x10701008a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP5_IP3_MEM_W1S" , 0x1070100aa5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP6_IP3_MEM_W1S" , 0x1070100ca5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP7_IP3_MEM_W1S" , 0x1070100ea5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP8_IP3_MEM_W1S" , 0x10701010a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP9_IP3_MEM_W1S" , 0x10701012a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP10_IP3_MEM_W1S" , 0x10701014a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP11_IP3_MEM_W1S" , 0x10701016a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP12_IP3_MEM_W1S" , 0x10701018a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP13_IP3_MEM_W1S" , 0x1070101aa5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP14_IP3_MEM_W1S" , 0x1070101ca5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP15_IP3_MEM_W1S" , 0x1070101ea5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP16_IP3_MEM_W1S" , 0x10701020a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP17_IP3_MEM_W1S" , 0x10701022a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP18_IP3_MEM_W1S" , 0x10701024a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP19_IP3_MEM_W1S" , 0x10701026a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP20_IP3_MEM_W1S" , 0x10701028a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP21_IP3_MEM_W1S" , 0x1070102aa5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP22_IP3_MEM_W1S" , 0x1070102ca5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP23_IP3_MEM_W1S" , 0x1070102ea5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP24_IP3_MEM_W1S" , 0x10701030a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP25_IP3_MEM_W1S" , 0x10701032a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP26_IP3_MEM_W1S" , 0x10701034a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP27_IP3_MEM_W1S" , 0x10701036a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP28_IP3_MEM_W1S" , 0x10701038a5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP29_IP3_MEM_W1S" , 0x1070103aa5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP30_IP3_MEM_W1S" , 0x1070103ca5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP31_IP3_MEM_W1S" , 0x1070103ea5200ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
- {"CIU2_EN_PP0_IP3_MIO" , 0x1070100093200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP1_IP3_MIO" , 0x1070100293200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP2_IP3_MIO" , 0x1070100493200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP3_IP3_MIO" , 0x1070100693200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP4_IP3_MIO" , 0x1070100893200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP5_IP3_MIO" , 0x1070100a93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP6_IP3_MIO" , 0x1070100c93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP7_IP3_MIO" , 0x1070100e93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP8_IP3_MIO" , 0x1070101093200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP9_IP3_MIO" , 0x1070101293200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP10_IP3_MIO" , 0x1070101493200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP11_IP3_MIO" , 0x1070101693200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP12_IP3_MIO" , 0x1070101893200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP13_IP3_MIO" , 0x1070101a93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP14_IP3_MIO" , 0x1070101c93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP15_IP3_MIO" , 0x1070101e93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP16_IP3_MIO" , 0x1070102093200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP17_IP3_MIO" , 0x1070102293200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP18_IP3_MIO" , 0x1070102493200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP19_IP3_MIO" , 0x1070102693200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP20_IP3_MIO" , 0x1070102893200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP21_IP3_MIO" , 0x1070102a93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP22_IP3_MIO" , 0x1070102c93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP23_IP3_MIO" , 0x1070102e93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP24_IP3_MIO" , 0x1070103093200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP25_IP3_MIO" , 0x1070103293200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP26_IP3_MIO" , 0x1070103493200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP27_IP3_MIO" , 0x1070103693200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP28_IP3_MIO" , 0x1070103893200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP29_IP3_MIO" , 0x1070103a93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP30_IP3_MIO" , 0x1070103c93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP31_IP3_MIO" , 0x1070103e93200ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
- {"CIU2_EN_PP0_IP3_MIO_W1C" , 0x10701000b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP1_IP3_MIO_W1C" , 0x10701002b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP2_IP3_MIO_W1C" , 0x10701004b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP3_IP3_MIO_W1C" , 0x10701006b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP4_IP3_MIO_W1C" , 0x10701008b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP5_IP3_MIO_W1C" , 0x1070100ab3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP6_IP3_MIO_W1C" , 0x1070100cb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP7_IP3_MIO_W1C" , 0x1070100eb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP8_IP3_MIO_W1C" , 0x10701010b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP9_IP3_MIO_W1C" , 0x10701012b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP10_IP3_MIO_W1C" , 0x10701014b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP11_IP3_MIO_W1C" , 0x10701016b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP12_IP3_MIO_W1C" , 0x10701018b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP13_IP3_MIO_W1C" , 0x1070101ab3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP14_IP3_MIO_W1C" , 0x1070101cb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP15_IP3_MIO_W1C" , 0x1070101eb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP16_IP3_MIO_W1C" , 0x10701020b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP17_IP3_MIO_W1C" , 0x10701022b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP18_IP3_MIO_W1C" , 0x10701024b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP19_IP3_MIO_W1C" , 0x10701026b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP20_IP3_MIO_W1C" , 0x10701028b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP21_IP3_MIO_W1C" , 0x1070102ab3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP22_IP3_MIO_W1C" , 0x1070102cb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP23_IP3_MIO_W1C" , 0x1070102eb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP24_IP3_MIO_W1C" , 0x10701030b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP25_IP3_MIO_W1C" , 0x10701032b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP26_IP3_MIO_W1C" , 0x10701034b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP27_IP3_MIO_W1C" , 0x10701036b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP28_IP3_MIO_W1C" , 0x10701038b3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP29_IP3_MIO_W1C" , 0x1070103ab3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP30_IP3_MIO_W1C" , 0x1070103cb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP31_IP3_MIO_W1C" , 0x1070103eb3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
- {"CIU2_EN_PP0_IP3_MIO_W1S" , 0x10701000a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP1_IP3_MIO_W1S" , 0x10701002a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP2_IP3_MIO_W1S" , 0x10701004a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP3_IP3_MIO_W1S" , 0x10701006a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP4_IP3_MIO_W1S" , 0x10701008a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP5_IP3_MIO_W1S" , 0x1070100aa3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP6_IP3_MIO_W1S" , 0x1070100ca3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP7_IP3_MIO_W1S" , 0x1070100ea3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP8_IP3_MIO_W1S" , 0x10701010a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP9_IP3_MIO_W1S" , 0x10701012a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP10_IP3_MIO_W1S" , 0x10701014a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP11_IP3_MIO_W1S" , 0x10701016a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP12_IP3_MIO_W1S" , 0x10701018a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP13_IP3_MIO_W1S" , 0x1070101aa3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP14_IP3_MIO_W1S" , 0x1070101ca3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP15_IP3_MIO_W1S" , 0x1070101ea3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP16_IP3_MIO_W1S" , 0x10701020a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP17_IP3_MIO_W1S" , 0x10701022a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP18_IP3_MIO_W1S" , 0x10701024a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP19_IP3_MIO_W1S" , 0x10701026a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP20_IP3_MIO_W1S" , 0x10701028a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP21_IP3_MIO_W1S" , 0x1070102aa3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP22_IP3_MIO_W1S" , 0x1070102ca3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP23_IP3_MIO_W1S" , 0x1070102ea3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP24_IP3_MIO_W1S" , 0x10701030a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP25_IP3_MIO_W1S" , 0x10701032a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP26_IP3_MIO_W1S" , 0x10701034a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP27_IP3_MIO_W1S" , 0x10701036a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP28_IP3_MIO_W1S" , 0x10701038a3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP29_IP3_MIO_W1S" , 0x1070103aa3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP30_IP3_MIO_W1S" , 0x1070103ca3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP31_IP3_MIO_W1S" , 0x1070103ea3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
- {"CIU2_EN_PP0_IP3_PKT" , 0x1070100096200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP1_IP3_PKT" , 0x1070100296200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP2_IP3_PKT" , 0x1070100496200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP3_IP3_PKT" , 0x1070100696200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP4_IP3_PKT" , 0x1070100896200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP5_IP3_PKT" , 0x1070100a96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP6_IP3_PKT" , 0x1070100c96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP7_IP3_PKT" , 0x1070100e96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP8_IP3_PKT" , 0x1070101096200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP9_IP3_PKT" , 0x1070101296200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP10_IP3_PKT" , 0x1070101496200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP11_IP3_PKT" , 0x1070101696200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP12_IP3_PKT" , 0x1070101896200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP13_IP3_PKT" , 0x1070101a96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP14_IP3_PKT" , 0x1070101c96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP15_IP3_PKT" , 0x1070101e96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP16_IP3_PKT" , 0x1070102096200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP17_IP3_PKT" , 0x1070102296200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP18_IP3_PKT" , 0x1070102496200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP19_IP3_PKT" , 0x1070102696200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP20_IP3_PKT" , 0x1070102896200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP21_IP3_PKT" , 0x1070102a96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP22_IP3_PKT" , 0x1070102c96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP23_IP3_PKT" , 0x1070102e96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP24_IP3_PKT" , 0x1070103096200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP25_IP3_PKT" , 0x1070103296200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP26_IP3_PKT" , 0x1070103496200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP27_IP3_PKT" , 0x1070103696200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP28_IP3_PKT" , 0x1070103896200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP29_IP3_PKT" , 0x1070103a96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP30_IP3_PKT" , 0x1070103c96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP31_IP3_PKT" , 0x1070103e96200ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
- {"CIU2_EN_PP0_IP3_PKT_W1C" , 0x10701000b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP1_IP3_PKT_W1C" , 0x10701002b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP2_IP3_PKT_W1C" , 0x10701004b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP3_IP3_PKT_W1C" , 0x10701006b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP4_IP3_PKT_W1C" , 0x10701008b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP5_IP3_PKT_W1C" , 0x1070100ab6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP6_IP3_PKT_W1C" , 0x1070100cb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP7_IP3_PKT_W1C" , 0x1070100eb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP8_IP3_PKT_W1C" , 0x10701010b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP9_IP3_PKT_W1C" , 0x10701012b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP10_IP3_PKT_W1C" , 0x10701014b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP11_IP3_PKT_W1C" , 0x10701016b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP12_IP3_PKT_W1C" , 0x10701018b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP13_IP3_PKT_W1C" , 0x1070101ab6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP14_IP3_PKT_W1C" , 0x1070101cb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP15_IP3_PKT_W1C" , 0x1070101eb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP16_IP3_PKT_W1C" , 0x10701020b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP17_IP3_PKT_W1C" , 0x10701022b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP18_IP3_PKT_W1C" , 0x10701024b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP19_IP3_PKT_W1C" , 0x10701026b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP20_IP3_PKT_W1C" , 0x10701028b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP21_IP3_PKT_W1C" , 0x1070102ab6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP22_IP3_PKT_W1C" , 0x1070102cb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP23_IP3_PKT_W1C" , 0x1070102eb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP24_IP3_PKT_W1C" , 0x10701030b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP25_IP3_PKT_W1C" , 0x10701032b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP26_IP3_PKT_W1C" , 0x10701034b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP27_IP3_PKT_W1C" , 0x10701036b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP28_IP3_PKT_W1C" , 0x10701038b6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP29_IP3_PKT_W1C" , 0x1070103ab6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP30_IP3_PKT_W1C" , 0x1070103cb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP31_IP3_PKT_W1C" , 0x1070103eb6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
- {"CIU2_EN_PP0_IP3_PKT_W1S" , 0x10701000a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP1_IP3_PKT_W1S" , 0x10701002a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP2_IP3_PKT_W1S" , 0x10701004a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP3_IP3_PKT_W1S" , 0x10701006a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP4_IP3_PKT_W1S" , 0x10701008a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP5_IP3_PKT_W1S" , 0x1070100aa6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP6_IP3_PKT_W1S" , 0x1070100ca6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP7_IP3_PKT_W1S" , 0x1070100ea6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP8_IP3_PKT_W1S" , 0x10701010a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP9_IP3_PKT_W1S" , 0x10701012a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP10_IP3_PKT_W1S" , 0x10701014a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP11_IP3_PKT_W1S" , 0x10701016a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP12_IP3_PKT_W1S" , 0x10701018a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP13_IP3_PKT_W1S" , 0x1070101aa6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP14_IP3_PKT_W1S" , 0x1070101ca6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP15_IP3_PKT_W1S" , 0x1070101ea6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP16_IP3_PKT_W1S" , 0x10701020a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP17_IP3_PKT_W1S" , 0x10701022a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP18_IP3_PKT_W1S" , 0x10701024a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP19_IP3_PKT_W1S" , 0x10701026a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP20_IP3_PKT_W1S" , 0x10701028a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP21_IP3_PKT_W1S" , 0x1070102aa6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP22_IP3_PKT_W1S" , 0x1070102ca6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP23_IP3_PKT_W1S" , 0x1070102ea6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP24_IP3_PKT_W1S" , 0x10701030a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP25_IP3_PKT_W1S" , 0x10701032a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP26_IP3_PKT_W1S" , 0x10701034a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP27_IP3_PKT_W1S" , 0x10701036a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP28_IP3_PKT_W1S" , 0x10701038a6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP29_IP3_PKT_W1S" , 0x1070103aa6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP30_IP3_PKT_W1S" , 0x1070103ca6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP31_IP3_PKT_W1S" , 0x1070103ea6200ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
- {"CIU2_EN_PP0_IP3_RML" , 0x1070100092200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP1_IP3_RML" , 0x1070100292200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP2_IP3_RML" , 0x1070100492200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP3_IP3_RML" , 0x1070100692200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP4_IP3_RML" , 0x1070100892200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP5_IP3_RML" , 0x1070100a92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP6_IP3_RML" , 0x1070100c92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP7_IP3_RML" , 0x1070100e92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP8_IP3_RML" , 0x1070101092200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP9_IP3_RML" , 0x1070101292200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP10_IP3_RML" , 0x1070101492200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP11_IP3_RML" , 0x1070101692200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP12_IP3_RML" , 0x1070101892200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP13_IP3_RML" , 0x1070101a92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP14_IP3_RML" , 0x1070101c92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP15_IP3_RML" , 0x1070101e92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP16_IP3_RML" , 0x1070102092200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP17_IP3_RML" , 0x1070102292200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP18_IP3_RML" , 0x1070102492200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP19_IP3_RML" , 0x1070102692200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP20_IP3_RML" , 0x1070102892200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP21_IP3_RML" , 0x1070102a92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP22_IP3_RML" , 0x1070102c92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP23_IP3_RML" , 0x1070102e92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP24_IP3_RML" , 0x1070103092200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP25_IP3_RML" , 0x1070103292200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP26_IP3_RML" , 0x1070103492200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP27_IP3_RML" , 0x1070103692200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP28_IP3_RML" , 0x1070103892200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP29_IP3_RML" , 0x1070103a92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP30_IP3_RML" , 0x1070103c92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP31_IP3_RML" , 0x1070103e92200ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
- {"CIU2_EN_PP0_IP3_RML_W1C" , 0x10701000b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP1_IP3_RML_W1C" , 0x10701002b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP2_IP3_RML_W1C" , 0x10701004b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP3_IP3_RML_W1C" , 0x10701006b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP4_IP3_RML_W1C" , 0x10701008b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP5_IP3_RML_W1C" , 0x1070100ab2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP6_IP3_RML_W1C" , 0x1070100cb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP7_IP3_RML_W1C" , 0x1070100eb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP8_IP3_RML_W1C" , 0x10701010b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP9_IP3_RML_W1C" , 0x10701012b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP10_IP3_RML_W1C" , 0x10701014b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP11_IP3_RML_W1C" , 0x10701016b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP12_IP3_RML_W1C" , 0x10701018b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP13_IP3_RML_W1C" , 0x1070101ab2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP14_IP3_RML_W1C" , 0x1070101cb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP15_IP3_RML_W1C" , 0x1070101eb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP16_IP3_RML_W1C" , 0x10701020b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP17_IP3_RML_W1C" , 0x10701022b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP18_IP3_RML_W1C" , 0x10701024b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP19_IP3_RML_W1C" , 0x10701026b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP20_IP3_RML_W1C" , 0x10701028b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP21_IP3_RML_W1C" , 0x1070102ab2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP22_IP3_RML_W1C" , 0x1070102cb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP23_IP3_RML_W1C" , 0x1070102eb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP24_IP3_RML_W1C" , 0x10701030b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP25_IP3_RML_W1C" , 0x10701032b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP26_IP3_RML_W1C" , 0x10701034b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP27_IP3_RML_W1C" , 0x10701036b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP28_IP3_RML_W1C" , 0x10701038b2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP29_IP3_RML_W1C" , 0x1070103ab2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP30_IP3_RML_W1C" , 0x1070103cb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP31_IP3_RML_W1C" , 0x1070103eb2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
- {"CIU2_EN_PP0_IP3_RML_W1S" , 0x10701000a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP1_IP3_RML_W1S" , 0x10701002a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP2_IP3_RML_W1S" , 0x10701004a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP3_IP3_RML_W1S" , 0x10701006a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP4_IP3_RML_W1S" , 0x10701008a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP5_IP3_RML_W1S" , 0x1070100aa2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP6_IP3_RML_W1S" , 0x1070100ca2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP7_IP3_RML_W1S" , 0x1070100ea2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP8_IP3_RML_W1S" , 0x10701010a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP9_IP3_RML_W1S" , 0x10701012a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP10_IP3_RML_W1S" , 0x10701014a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP11_IP3_RML_W1S" , 0x10701016a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP12_IP3_RML_W1S" , 0x10701018a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP13_IP3_RML_W1S" , 0x1070101aa2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP14_IP3_RML_W1S" , 0x1070101ca2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP15_IP3_RML_W1S" , 0x1070101ea2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP16_IP3_RML_W1S" , 0x10701020a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP17_IP3_RML_W1S" , 0x10701022a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP18_IP3_RML_W1S" , 0x10701024a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP19_IP3_RML_W1S" , 0x10701026a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP20_IP3_RML_W1S" , 0x10701028a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP21_IP3_RML_W1S" , 0x1070102aa2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP22_IP3_RML_W1S" , 0x1070102ca2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP23_IP3_RML_W1S" , 0x1070102ea2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP24_IP3_RML_W1S" , 0x10701030a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP25_IP3_RML_W1S" , 0x10701032a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP26_IP3_RML_W1S" , 0x10701034a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP27_IP3_RML_W1S" , 0x10701036a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP28_IP3_RML_W1S" , 0x10701038a2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP29_IP3_RML_W1S" , 0x1070103aa2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP30_IP3_RML_W1S" , 0x1070103ca2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP31_IP3_RML_W1S" , 0x1070103ea2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
- {"CIU2_EN_PP0_IP3_WDOG" , 0x1070100091200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP1_IP3_WDOG" , 0x1070100291200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP2_IP3_WDOG" , 0x1070100491200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP3_IP3_WDOG" , 0x1070100691200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP4_IP3_WDOG" , 0x1070100891200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP5_IP3_WDOG" , 0x1070100a91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP6_IP3_WDOG" , 0x1070100c91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP7_IP3_WDOG" , 0x1070100e91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP8_IP3_WDOG" , 0x1070101091200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP9_IP3_WDOG" , 0x1070101291200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP10_IP3_WDOG" , 0x1070101491200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP11_IP3_WDOG" , 0x1070101691200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP12_IP3_WDOG" , 0x1070101891200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP13_IP3_WDOG" , 0x1070101a91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP14_IP3_WDOG" , 0x1070101c91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP15_IP3_WDOG" , 0x1070101e91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP16_IP3_WDOG" , 0x1070102091200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP17_IP3_WDOG" , 0x1070102291200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP18_IP3_WDOG" , 0x1070102491200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP19_IP3_WDOG" , 0x1070102691200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP20_IP3_WDOG" , 0x1070102891200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP21_IP3_WDOG" , 0x1070102a91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP22_IP3_WDOG" , 0x1070102c91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP23_IP3_WDOG" , 0x1070102e91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP24_IP3_WDOG" , 0x1070103091200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP25_IP3_WDOG" , 0x1070103291200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP26_IP3_WDOG" , 0x1070103491200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP27_IP3_WDOG" , 0x1070103691200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP28_IP3_WDOG" , 0x1070103891200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP29_IP3_WDOG" , 0x1070103a91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP30_IP3_WDOG" , 0x1070103c91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP31_IP3_WDOG" , 0x1070103e91200ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
- {"CIU2_EN_PP0_IP3_WDOG_W1C" , 0x10701000b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP1_IP3_WDOG_W1C" , 0x10701002b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP2_IP3_WDOG_W1C" , 0x10701004b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP3_IP3_WDOG_W1C" , 0x10701006b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP4_IP3_WDOG_W1C" , 0x10701008b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP5_IP3_WDOG_W1C" , 0x1070100ab1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP6_IP3_WDOG_W1C" , 0x1070100cb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP7_IP3_WDOG_W1C" , 0x1070100eb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP8_IP3_WDOG_W1C" , 0x10701010b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP9_IP3_WDOG_W1C" , 0x10701012b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP10_IP3_WDOG_W1C" , 0x10701014b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP11_IP3_WDOG_W1C" , 0x10701016b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP12_IP3_WDOG_W1C" , 0x10701018b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP13_IP3_WDOG_W1C" , 0x1070101ab1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP14_IP3_WDOG_W1C" , 0x1070101cb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP15_IP3_WDOG_W1C" , 0x1070101eb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP16_IP3_WDOG_W1C" , 0x10701020b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP17_IP3_WDOG_W1C" , 0x10701022b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP18_IP3_WDOG_W1C" , 0x10701024b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP19_IP3_WDOG_W1C" , 0x10701026b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP20_IP3_WDOG_W1C" , 0x10701028b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP21_IP3_WDOG_W1C" , 0x1070102ab1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP22_IP3_WDOG_W1C" , 0x1070102cb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP23_IP3_WDOG_W1C" , 0x1070102eb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP24_IP3_WDOG_W1C" , 0x10701030b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP25_IP3_WDOG_W1C" , 0x10701032b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP26_IP3_WDOG_W1C" , 0x10701034b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP27_IP3_WDOG_W1C" , 0x10701036b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP28_IP3_WDOG_W1C" , 0x10701038b1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP29_IP3_WDOG_W1C" , 0x1070103ab1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP30_IP3_WDOG_W1C" , 0x1070103cb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP31_IP3_WDOG_W1C" , 0x1070103eb1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
- {"CIU2_EN_PP0_IP3_WDOG_W1S" , 0x10701000a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP1_IP3_WDOG_W1S" , 0x10701002a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP2_IP3_WDOG_W1S" , 0x10701004a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP3_IP3_WDOG_W1S" , 0x10701006a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP4_IP3_WDOG_W1S" , 0x10701008a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP5_IP3_WDOG_W1S" , 0x1070100aa1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP6_IP3_WDOG_W1S" , 0x1070100ca1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP7_IP3_WDOG_W1S" , 0x1070100ea1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP8_IP3_WDOG_W1S" , 0x10701010a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP9_IP3_WDOG_W1S" , 0x10701012a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP10_IP3_WDOG_W1S" , 0x10701014a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP11_IP3_WDOG_W1S" , 0x10701016a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP12_IP3_WDOG_W1S" , 0x10701018a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP13_IP3_WDOG_W1S" , 0x1070101aa1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP14_IP3_WDOG_W1S" , 0x1070101ca1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP15_IP3_WDOG_W1S" , 0x1070101ea1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP16_IP3_WDOG_W1S" , 0x10701020a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP17_IP3_WDOG_W1S" , 0x10701022a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP18_IP3_WDOG_W1S" , 0x10701024a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP19_IP3_WDOG_W1S" , 0x10701026a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP20_IP3_WDOG_W1S" , 0x10701028a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP21_IP3_WDOG_W1S" , 0x1070102aa1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP22_IP3_WDOG_W1S" , 0x1070102ca1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP23_IP3_WDOG_W1S" , 0x1070102ea1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP24_IP3_WDOG_W1S" , 0x10701030a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP25_IP3_WDOG_W1S" , 0x10701032a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP26_IP3_WDOG_W1S" , 0x10701034a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP27_IP3_WDOG_W1S" , 0x10701036a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP28_IP3_WDOG_W1S" , 0x10701038a1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP29_IP3_WDOG_W1S" , 0x1070103aa1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP30_IP3_WDOG_W1S" , 0x1070103ca1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP31_IP3_WDOG_W1S" , 0x1070103ea1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
- {"CIU2_EN_PP0_IP3_WRKQ" , 0x1070100090200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP1_IP3_WRKQ" , 0x1070100290200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP2_IP3_WRKQ" , 0x1070100490200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP3_IP3_WRKQ" , 0x1070100690200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP4_IP3_WRKQ" , 0x1070100890200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP5_IP3_WRKQ" , 0x1070100a90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP6_IP3_WRKQ" , 0x1070100c90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP7_IP3_WRKQ" , 0x1070100e90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP8_IP3_WRKQ" , 0x1070101090200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP9_IP3_WRKQ" , 0x1070101290200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP10_IP3_WRKQ" , 0x1070101490200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP11_IP3_WRKQ" , 0x1070101690200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP12_IP3_WRKQ" , 0x1070101890200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP13_IP3_WRKQ" , 0x1070101a90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP14_IP3_WRKQ" , 0x1070101c90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP15_IP3_WRKQ" , 0x1070101e90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP16_IP3_WRKQ" , 0x1070102090200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP17_IP3_WRKQ" , 0x1070102290200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP18_IP3_WRKQ" , 0x1070102490200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP19_IP3_WRKQ" , 0x1070102690200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP20_IP3_WRKQ" , 0x1070102890200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP21_IP3_WRKQ" , 0x1070102a90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP22_IP3_WRKQ" , 0x1070102c90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP23_IP3_WRKQ" , 0x1070102e90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP24_IP3_WRKQ" , 0x1070103090200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP25_IP3_WRKQ" , 0x1070103290200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP26_IP3_WRKQ" , 0x1070103490200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP27_IP3_WRKQ" , 0x1070103690200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP28_IP3_WRKQ" , 0x1070103890200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP29_IP3_WRKQ" , 0x1070103a90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP30_IP3_WRKQ" , 0x1070103c90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP31_IP3_WRKQ" , 0x1070103e90200ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
- {"CIU2_EN_PP0_IP3_WRKQ_W1C" , 0x10701000b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP1_IP3_WRKQ_W1C" , 0x10701002b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP2_IP3_WRKQ_W1C" , 0x10701004b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP3_IP3_WRKQ_W1C" , 0x10701006b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP4_IP3_WRKQ_W1C" , 0x10701008b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP5_IP3_WRKQ_W1C" , 0x1070100ab0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP6_IP3_WRKQ_W1C" , 0x1070100cb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP7_IP3_WRKQ_W1C" , 0x1070100eb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP8_IP3_WRKQ_W1C" , 0x10701010b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP9_IP3_WRKQ_W1C" , 0x10701012b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP10_IP3_WRKQ_W1C" , 0x10701014b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP11_IP3_WRKQ_W1C" , 0x10701016b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP12_IP3_WRKQ_W1C" , 0x10701018b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP13_IP3_WRKQ_W1C" , 0x1070101ab0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP14_IP3_WRKQ_W1C" , 0x1070101cb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP15_IP3_WRKQ_W1C" , 0x1070101eb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP16_IP3_WRKQ_W1C" , 0x10701020b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP17_IP3_WRKQ_W1C" , 0x10701022b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP18_IP3_WRKQ_W1C" , 0x10701024b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP19_IP3_WRKQ_W1C" , 0x10701026b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP20_IP3_WRKQ_W1C" , 0x10701028b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP21_IP3_WRKQ_W1C" , 0x1070102ab0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP22_IP3_WRKQ_W1C" , 0x1070102cb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP23_IP3_WRKQ_W1C" , 0x1070102eb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP24_IP3_WRKQ_W1C" , 0x10701030b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP25_IP3_WRKQ_W1C" , 0x10701032b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP26_IP3_WRKQ_W1C" , 0x10701034b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP27_IP3_WRKQ_W1C" , 0x10701036b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP28_IP3_WRKQ_W1C" , 0x10701038b0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP29_IP3_WRKQ_W1C" , 0x1070103ab0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP30_IP3_WRKQ_W1C" , 0x1070103cb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP31_IP3_WRKQ_W1C" , 0x1070103eb0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
- {"CIU2_EN_PP0_IP3_WRKQ_W1S" , 0x10701000a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP1_IP3_WRKQ_W1S" , 0x10701002a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP2_IP3_WRKQ_W1S" , 0x10701004a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP3_IP3_WRKQ_W1S" , 0x10701006a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP4_IP3_WRKQ_W1S" , 0x10701008a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP5_IP3_WRKQ_W1S" , 0x1070100aa0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP6_IP3_WRKQ_W1S" , 0x1070100ca0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP7_IP3_WRKQ_W1S" , 0x1070100ea0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP8_IP3_WRKQ_W1S" , 0x10701010a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP9_IP3_WRKQ_W1S" , 0x10701012a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP10_IP3_WRKQ_W1S" , 0x10701014a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP11_IP3_WRKQ_W1S" , 0x10701016a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP12_IP3_WRKQ_W1S" , 0x10701018a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP13_IP3_WRKQ_W1S" , 0x1070101aa0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP14_IP3_WRKQ_W1S" , 0x1070101ca0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP15_IP3_WRKQ_W1S" , 0x1070101ea0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP16_IP3_WRKQ_W1S" , 0x10701020a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP17_IP3_WRKQ_W1S" , 0x10701022a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP18_IP3_WRKQ_W1S" , 0x10701024a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP19_IP3_WRKQ_W1S" , 0x10701026a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP20_IP3_WRKQ_W1S" , 0x10701028a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP21_IP3_WRKQ_W1S" , 0x1070102aa0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP22_IP3_WRKQ_W1S" , 0x1070102ca0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP23_IP3_WRKQ_W1S" , 0x1070102ea0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP24_IP3_WRKQ_W1S" , 0x10701030a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP25_IP3_WRKQ_W1S" , 0x10701032a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP26_IP3_WRKQ_W1S" , 0x10701034a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP27_IP3_WRKQ_W1S" , 0x10701036a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP28_IP3_WRKQ_W1S" , 0x10701038a0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP29_IP3_WRKQ_W1S" , 0x1070103aa0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP30_IP3_WRKQ_W1S" , 0x1070103ca0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP31_IP3_WRKQ_W1S" , 0x1070103ea0200ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
- {"CIU2_EN_PP0_IP4_GPIO" , 0x1070100097400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP1_IP4_GPIO" , 0x1070100297400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP2_IP4_GPIO" , 0x1070100497400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP3_IP4_GPIO" , 0x1070100697400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP4_IP4_GPIO" , 0x1070100897400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP5_IP4_GPIO" , 0x1070100a97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP6_IP4_GPIO" , 0x1070100c97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP7_IP4_GPIO" , 0x1070100e97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP8_IP4_GPIO" , 0x1070101097400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP9_IP4_GPIO" , 0x1070101297400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP10_IP4_GPIO" , 0x1070101497400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP11_IP4_GPIO" , 0x1070101697400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP12_IP4_GPIO" , 0x1070101897400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP13_IP4_GPIO" , 0x1070101a97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP14_IP4_GPIO" , 0x1070101c97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP15_IP4_GPIO" , 0x1070101e97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP16_IP4_GPIO" , 0x1070102097400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP17_IP4_GPIO" , 0x1070102297400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP18_IP4_GPIO" , 0x1070102497400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP19_IP4_GPIO" , 0x1070102697400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP20_IP4_GPIO" , 0x1070102897400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP21_IP4_GPIO" , 0x1070102a97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP22_IP4_GPIO" , 0x1070102c97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP23_IP4_GPIO" , 0x1070102e97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP24_IP4_GPIO" , 0x1070103097400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP25_IP4_GPIO" , 0x1070103297400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP26_IP4_GPIO" , 0x1070103497400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP27_IP4_GPIO" , 0x1070103697400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP28_IP4_GPIO" , 0x1070103897400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP29_IP4_GPIO" , 0x1070103a97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP30_IP4_GPIO" , 0x1070103c97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP31_IP4_GPIO" , 0x1070103e97400ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
- {"CIU2_EN_PP0_IP4_GPIO_W1C" , 0x10701000b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP1_IP4_GPIO_W1C" , 0x10701002b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP2_IP4_GPIO_W1C" , 0x10701004b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP3_IP4_GPIO_W1C" , 0x10701006b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP4_IP4_GPIO_W1C" , 0x10701008b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP5_IP4_GPIO_W1C" , 0x1070100ab7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP6_IP4_GPIO_W1C" , 0x1070100cb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP7_IP4_GPIO_W1C" , 0x1070100eb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP8_IP4_GPIO_W1C" , 0x10701010b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP9_IP4_GPIO_W1C" , 0x10701012b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP10_IP4_GPIO_W1C" , 0x10701014b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP11_IP4_GPIO_W1C" , 0x10701016b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP12_IP4_GPIO_W1C" , 0x10701018b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP13_IP4_GPIO_W1C" , 0x1070101ab7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP14_IP4_GPIO_W1C" , 0x1070101cb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP15_IP4_GPIO_W1C" , 0x1070101eb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP16_IP4_GPIO_W1C" , 0x10701020b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP17_IP4_GPIO_W1C" , 0x10701022b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP18_IP4_GPIO_W1C" , 0x10701024b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP19_IP4_GPIO_W1C" , 0x10701026b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP20_IP4_GPIO_W1C" , 0x10701028b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP21_IP4_GPIO_W1C" , 0x1070102ab7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP22_IP4_GPIO_W1C" , 0x1070102cb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP23_IP4_GPIO_W1C" , 0x1070102eb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP24_IP4_GPIO_W1C" , 0x10701030b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP25_IP4_GPIO_W1C" , 0x10701032b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP26_IP4_GPIO_W1C" , 0x10701034b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP27_IP4_GPIO_W1C" , 0x10701036b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP28_IP4_GPIO_W1C" , 0x10701038b7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP29_IP4_GPIO_W1C" , 0x1070103ab7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP30_IP4_GPIO_W1C" , 0x1070103cb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP31_IP4_GPIO_W1C" , 0x1070103eb7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
- {"CIU2_EN_PP0_IP4_GPIO_W1S" , 0x10701000a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP1_IP4_GPIO_W1S" , 0x10701002a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP2_IP4_GPIO_W1S" , 0x10701004a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP3_IP4_GPIO_W1S" , 0x10701006a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP4_IP4_GPIO_W1S" , 0x10701008a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP5_IP4_GPIO_W1S" , 0x1070100aa7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP6_IP4_GPIO_W1S" , 0x1070100ca7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP7_IP4_GPIO_W1S" , 0x1070100ea7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP8_IP4_GPIO_W1S" , 0x10701010a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP9_IP4_GPIO_W1S" , 0x10701012a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP10_IP4_GPIO_W1S" , 0x10701014a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP11_IP4_GPIO_W1S" , 0x10701016a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP12_IP4_GPIO_W1S" , 0x10701018a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP13_IP4_GPIO_W1S" , 0x1070101aa7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP14_IP4_GPIO_W1S" , 0x1070101ca7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP15_IP4_GPIO_W1S" , 0x1070101ea7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP16_IP4_GPIO_W1S" , 0x10701020a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP17_IP4_GPIO_W1S" , 0x10701022a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP18_IP4_GPIO_W1S" , 0x10701024a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP19_IP4_GPIO_W1S" , 0x10701026a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP20_IP4_GPIO_W1S" , 0x10701028a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP21_IP4_GPIO_W1S" , 0x1070102aa7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP22_IP4_GPIO_W1S" , 0x1070102ca7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP23_IP4_GPIO_W1S" , 0x1070102ea7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP24_IP4_GPIO_W1S" , 0x10701030a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP25_IP4_GPIO_W1S" , 0x10701032a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP26_IP4_GPIO_W1S" , 0x10701034a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP27_IP4_GPIO_W1S" , 0x10701036a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP28_IP4_GPIO_W1S" , 0x10701038a7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP29_IP4_GPIO_W1S" , 0x1070103aa7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP30_IP4_GPIO_W1S" , 0x1070103ca7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP31_IP4_GPIO_W1S" , 0x1070103ea7400ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
- {"CIU2_EN_PP0_IP4_IO" , 0x1070100094400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP1_IP4_IO" , 0x1070100294400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP2_IP4_IO" , 0x1070100494400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP3_IP4_IO" , 0x1070100694400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP4_IP4_IO" , 0x1070100894400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP5_IP4_IO" , 0x1070100a94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP6_IP4_IO" , 0x1070100c94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP7_IP4_IO" , 0x1070100e94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP8_IP4_IO" , 0x1070101094400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP9_IP4_IO" , 0x1070101294400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP10_IP4_IO" , 0x1070101494400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP11_IP4_IO" , 0x1070101694400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP12_IP4_IO" , 0x1070101894400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP13_IP4_IO" , 0x1070101a94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP14_IP4_IO" , 0x1070101c94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP15_IP4_IO" , 0x1070101e94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP16_IP4_IO" , 0x1070102094400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP17_IP4_IO" , 0x1070102294400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP18_IP4_IO" , 0x1070102494400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP19_IP4_IO" , 0x1070102694400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP20_IP4_IO" , 0x1070102894400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP21_IP4_IO" , 0x1070102a94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP22_IP4_IO" , 0x1070102c94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP23_IP4_IO" , 0x1070102e94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP24_IP4_IO" , 0x1070103094400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP25_IP4_IO" , 0x1070103294400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP26_IP4_IO" , 0x1070103494400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP27_IP4_IO" , 0x1070103694400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP28_IP4_IO" , 0x1070103894400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP29_IP4_IO" , 0x1070103a94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP30_IP4_IO" , 0x1070103c94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP31_IP4_IO" , 0x1070103e94400ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
- {"CIU2_EN_PP0_IP4_IO_W1C" , 0x10701000b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP1_IP4_IO_W1C" , 0x10701002b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP2_IP4_IO_W1C" , 0x10701004b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP3_IP4_IO_W1C" , 0x10701006b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP4_IP4_IO_W1C" , 0x10701008b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP5_IP4_IO_W1C" , 0x1070100ab4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP6_IP4_IO_W1C" , 0x1070100cb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP7_IP4_IO_W1C" , 0x1070100eb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP8_IP4_IO_W1C" , 0x10701010b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP9_IP4_IO_W1C" , 0x10701012b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP10_IP4_IO_W1C" , 0x10701014b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP11_IP4_IO_W1C" , 0x10701016b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP12_IP4_IO_W1C" , 0x10701018b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP13_IP4_IO_W1C" , 0x1070101ab4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP14_IP4_IO_W1C" , 0x1070101cb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP15_IP4_IO_W1C" , 0x1070101eb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP16_IP4_IO_W1C" , 0x10701020b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP17_IP4_IO_W1C" , 0x10701022b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP18_IP4_IO_W1C" , 0x10701024b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP19_IP4_IO_W1C" , 0x10701026b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP20_IP4_IO_W1C" , 0x10701028b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP21_IP4_IO_W1C" , 0x1070102ab4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP22_IP4_IO_W1C" , 0x1070102cb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP23_IP4_IO_W1C" , 0x1070102eb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP24_IP4_IO_W1C" , 0x10701030b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP25_IP4_IO_W1C" , 0x10701032b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP26_IP4_IO_W1C" , 0x10701034b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP27_IP4_IO_W1C" , 0x10701036b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP28_IP4_IO_W1C" , 0x10701038b4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP29_IP4_IO_W1C" , 0x1070103ab4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP30_IP4_IO_W1C" , 0x1070103cb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP31_IP4_IO_W1C" , 0x1070103eb4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
- {"CIU2_EN_PP0_IP4_IO_W1S" , 0x10701000a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP1_IP4_IO_W1S" , 0x10701002a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP2_IP4_IO_W1S" , 0x10701004a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP3_IP4_IO_W1S" , 0x10701006a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP4_IP4_IO_W1S" , 0x10701008a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP5_IP4_IO_W1S" , 0x1070100aa4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP6_IP4_IO_W1S" , 0x1070100ca4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP7_IP4_IO_W1S" , 0x1070100ea4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP8_IP4_IO_W1S" , 0x10701010a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP9_IP4_IO_W1S" , 0x10701012a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP10_IP4_IO_W1S" , 0x10701014a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP11_IP4_IO_W1S" , 0x10701016a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP12_IP4_IO_W1S" , 0x10701018a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP13_IP4_IO_W1S" , 0x1070101aa4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP14_IP4_IO_W1S" , 0x1070101ca4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP15_IP4_IO_W1S" , 0x1070101ea4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP16_IP4_IO_W1S" , 0x10701020a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP17_IP4_IO_W1S" , 0x10701022a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP18_IP4_IO_W1S" , 0x10701024a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP19_IP4_IO_W1S" , 0x10701026a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP20_IP4_IO_W1S" , 0x10701028a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP21_IP4_IO_W1S" , 0x1070102aa4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP22_IP4_IO_W1S" , 0x1070102ca4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP23_IP4_IO_W1S" , 0x1070102ea4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP24_IP4_IO_W1S" , 0x10701030a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP25_IP4_IO_W1S" , 0x10701032a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP26_IP4_IO_W1S" , 0x10701034a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP27_IP4_IO_W1S" , 0x10701036a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP28_IP4_IO_W1S" , 0x10701038a4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP29_IP4_IO_W1S" , 0x1070103aa4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP30_IP4_IO_W1S" , 0x1070103ca4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP31_IP4_IO_W1S" , 0x1070103ea4400ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
- {"CIU2_EN_PP0_IP4_MBOX" , 0x1070100098400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP1_IP4_MBOX" , 0x1070100298400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP2_IP4_MBOX" , 0x1070100498400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP3_IP4_MBOX" , 0x1070100698400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP4_IP4_MBOX" , 0x1070100898400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP5_IP4_MBOX" , 0x1070100a98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP6_IP4_MBOX" , 0x1070100c98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP7_IP4_MBOX" , 0x1070100e98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP8_IP4_MBOX" , 0x1070101098400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP9_IP4_MBOX" , 0x1070101298400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP10_IP4_MBOX" , 0x1070101498400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP11_IP4_MBOX" , 0x1070101698400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP12_IP4_MBOX" , 0x1070101898400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP13_IP4_MBOX" , 0x1070101a98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP14_IP4_MBOX" , 0x1070101c98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP15_IP4_MBOX" , 0x1070101e98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP16_IP4_MBOX" , 0x1070102098400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP17_IP4_MBOX" , 0x1070102298400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP18_IP4_MBOX" , 0x1070102498400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP19_IP4_MBOX" , 0x1070102698400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP20_IP4_MBOX" , 0x1070102898400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP21_IP4_MBOX" , 0x1070102a98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP22_IP4_MBOX" , 0x1070102c98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP23_IP4_MBOX" , 0x1070102e98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP24_IP4_MBOX" , 0x1070103098400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP25_IP4_MBOX" , 0x1070103298400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP26_IP4_MBOX" , 0x1070103498400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP27_IP4_MBOX" , 0x1070103698400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP28_IP4_MBOX" , 0x1070103898400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP29_IP4_MBOX" , 0x1070103a98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP30_IP4_MBOX" , 0x1070103c98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP31_IP4_MBOX" , 0x1070103e98400ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
- {"CIU2_EN_PP0_IP4_MBOX_W1C" , 0x10701000b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP1_IP4_MBOX_W1C" , 0x10701002b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP2_IP4_MBOX_W1C" , 0x10701004b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP3_IP4_MBOX_W1C" , 0x10701006b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP4_IP4_MBOX_W1C" , 0x10701008b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP5_IP4_MBOX_W1C" , 0x1070100ab8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP6_IP4_MBOX_W1C" , 0x1070100cb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP7_IP4_MBOX_W1C" , 0x1070100eb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP8_IP4_MBOX_W1C" , 0x10701010b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP9_IP4_MBOX_W1C" , 0x10701012b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP10_IP4_MBOX_W1C" , 0x10701014b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP11_IP4_MBOX_W1C" , 0x10701016b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP12_IP4_MBOX_W1C" , 0x10701018b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP13_IP4_MBOX_W1C" , 0x1070101ab8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP14_IP4_MBOX_W1C" , 0x1070101cb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP15_IP4_MBOX_W1C" , 0x1070101eb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP16_IP4_MBOX_W1C" , 0x10701020b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP17_IP4_MBOX_W1C" , 0x10701022b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP18_IP4_MBOX_W1C" , 0x10701024b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP19_IP4_MBOX_W1C" , 0x10701026b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP20_IP4_MBOX_W1C" , 0x10701028b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP21_IP4_MBOX_W1C" , 0x1070102ab8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP22_IP4_MBOX_W1C" , 0x1070102cb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP23_IP4_MBOX_W1C" , 0x1070102eb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP24_IP4_MBOX_W1C" , 0x10701030b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP25_IP4_MBOX_W1C" , 0x10701032b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP26_IP4_MBOX_W1C" , 0x10701034b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP27_IP4_MBOX_W1C" , 0x10701036b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP28_IP4_MBOX_W1C" , 0x10701038b8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP29_IP4_MBOX_W1C" , 0x1070103ab8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP30_IP4_MBOX_W1C" , 0x1070103cb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP31_IP4_MBOX_W1C" , 0x1070103eb8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
- {"CIU2_EN_PP0_IP4_MBOX_W1S" , 0x10701000a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP1_IP4_MBOX_W1S" , 0x10701002a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP2_IP4_MBOX_W1S" , 0x10701004a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP3_IP4_MBOX_W1S" , 0x10701006a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP4_IP4_MBOX_W1S" , 0x10701008a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP5_IP4_MBOX_W1S" , 0x1070100aa8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP6_IP4_MBOX_W1S" , 0x1070100ca8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP7_IP4_MBOX_W1S" , 0x1070100ea8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP8_IP4_MBOX_W1S" , 0x10701010a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP9_IP4_MBOX_W1S" , 0x10701012a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP10_IP4_MBOX_W1S" , 0x10701014a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP11_IP4_MBOX_W1S" , 0x10701016a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP12_IP4_MBOX_W1S" , 0x10701018a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP13_IP4_MBOX_W1S" , 0x1070101aa8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP14_IP4_MBOX_W1S" , 0x1070101ca8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP15_IP4_MBOX_W1S" , 0x1070101ea8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP16_IP4_MBOX_W1S" , 0x10701020a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP17_IP4_MBOX_W1S" , 0x10701022a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP18_IP4_MBOX_W1S" , 0x10701024a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP19_IP4_MBOX_W1S" , 0x10701026a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP20_IP4_MBOX_W1S" , 0x10701028a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP21_IP4_MBOX_W1S" , 0x1070102aa8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP22_IP4_MBOX_W1S" , 0x1070102ca8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP23_IP4_MBOX_W1S" , 0x1070102ea8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP24_IP4_MBOX_W1S" , 0x10701030a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP25_IP4_MBOX_W1S" , 0x10701032a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP26_IP4_MBOX_W1S" , 0x10701034a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP27_IP4_MBOX_W1S" , 0x10701036a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP28_IP4_MBOX_W1S" , 0x10701038a8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP29_IP4_MBOX_W1S" , 0x1070103aa8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP30_IP4_MBOX_W1S" , 0x1070103ca8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP31_IP4_MBOX_W1S" , 0x1070103ea8400ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
- {"CIU2_EN_PP0_IP4_MEM" , 0x1070100095400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP1_IP4_MEM" , 0x1070100295400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP2_IP4_MEM" , 0x1070100495400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP3_IP4_MEM" , 0x1070100695400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP4_IP4_MEM" , 0x1070100895400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP5_IP4_MEM" , 0x1070100a95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP6_IP4_MEM" , 0x1070100c95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP7_IP4_MEM" , 0x1070100e95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP8_IP4_MEM" , 0x1070101095400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP9_IP4_MEM" , 0x1070101295400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP10_IP4_MEM" , 0x1070101495400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP11_IP4_MEM" , 0x1070101695400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP12_IP4_MEM" , 0x1070101895400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP13_IP4_MEM" , 0x1070101a95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP14_IP4_MEM" , 0x1070101c95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP15_IP4_MEM" , 0x1070101e95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP16_IP4_MEM" , 0x1070102095400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP17_IP4_MEM" , 0x1070102295400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP18_IP4_MEM" , 0x1070102495400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP19_IP4_MEM" , 0x1070102695400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP20_IP4_MEM" , 0x1070102895400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP21_IP4_MEM" , 0x1070102a95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP22_IP4_MEM" , 0x1070102c95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP23_IP4_MEM" , 0x1070102e95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP24_IP4_MEM" , 0x1070103095400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP25_IP4_MEM" , 0x1070103295400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP26_IP4_MEM" , 0x1070103495400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP27_IP4_MEM" , 0x1070103695400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP28_IP4_MEM" , 0x1070103895400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP29_IP4_MEM" , 0x1070103a95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP30_IP4_MEM" , 0x1070103c95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP31_IP4_MEM" , 0x1070103e95400ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
- {"CIU2_EN_PP0_IP4_MEM_W1C" , 0x10701000b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP1_IP4_MEM_W1C" , 0x10701002b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP2_IP4_MEM_W1C" , 0x10701004b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP3_IP4_MEM_W1C" , 0x10701006b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP4_IP4_MEM_W1C" , 0x10701008b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP5_IP4_MEM_W1C" , 0x1070100ab5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP6_IP4_MEM_W1C" , 0x1070100cb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP7_IP4_MEM_W1C" , 0x1070100eb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP8_IP4_MEM_W1C" , 0x10701010b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP9_IP4_MEM_W1C" , 0x10701012b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP10_IP4_MEM_W1C" , 0x10701014b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP11_IP4_MEM_W1C" , 0x10701016b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP12_IP4_MEM_W1C" , 0x10701018b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP13_IP4_MEM_W1C" , 0x1070101ab5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP14_IP4_MEM_W1C" , 0x1070101cb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP15_IP4_MEM_W1C" , 0x1070101eb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP16_IP4_MEM_W1C" , 0x10701020b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP17_IP4_MEM_W1C" , 0x10701022b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP18_IP4_MEM_W1C" , 0x10701024b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP19_IP4_MEM_W1C" , 0x10701026b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP20_IP4_MEM_W1C" , 0x10701028b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP21_IP4_MEM_W1C" , 0x1070102ab5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP22_IP4_MEM_W1C" , 0x1070102cb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP23_IP4_MEM_W1C" , 0x1070102eb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP24_IP4_MEM_W1C" , 0x10701030b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP25_IP4_MEM_W1C" , 0x10701032b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP26_IP4_MEM_W1C" , 0x10701034b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP27_IP4_MEM_W1C" , 0x10701036b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP28_IP4_MEM_W1C" , 0x10701038b5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP29_IP4_MEM_W1C" , 0x1070103ab5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP30_IP4_MEM_W1C" , 0x1070103cb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP31_IP4_MEM_W1C" , 0x1070103eb5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
- {"CIU2_EN_PP0_IP4_MEM_W1S" , 0x10701000a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP1_IP4_MEM_W1S" , 0x10701002a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP2_IP4_MEM_W1S" , 0x10701004a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP3_IP4_MEM_W1S" , 0x10701006a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP4_IP4_MEM_W1S" , 0x10701008a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP5_IP4_MEM_W1S" , 0x1070100aa5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP6_IP4_MEM_W1S" , 0x1070100ca5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP7_IP4_MEM_W1S" , 0x1070100ea5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP8_IP4_MEM_W1S" , 0x10701010a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP9_IP4_MEM_W1S" , 0x10701012a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP10_IP4_MEM_W1S" , 0x10701014a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP11_IP4_MEM_W1S" , 0x10701016a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP12_IP4_MEM_W1S" , 0x10701018a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP13_IP4_MEM_W1S" , 0x1070101aa5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP14_IP4_MEM_W1S" , 0x1070101ca5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP15_IP4_MEM_W1S" , 0x1070101ea5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP16_IP4_MEM_W1S" , 0x10701020a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP17_IP4_MEM_W1S" , 0x10701022a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP18_IP4_MEM_W1S" , 0x10701024a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP19_IP4_MEM_W1S" , 0x10701026a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP20_IP4_MEM_W1S" , 0x10701028a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP21_IP4_MEM_W1S" , 0x1070102aa5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP22_IP4_MEM_W1S" , 0x1070102ca5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP23_IP4_MEM_W1S" , 0x1070102ea5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP24_IP4_MEM_W1S" , 0x10701030a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP25_IP4_MEM_W1S" , 0x10701032a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP26_IP4_MEM_W1S" , 0x10701034a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP27_IP4_MEM_W1S" , 0x10701036a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP28_IP4_MEM_W1S" , 0x10701038a5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP29_IP4_MEM_W1S" , 0x1070103aa5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP30_IP4_MEM_W1S" , 0x1070103ca5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP31_IP4_MEM_W1S" , 0x1070103ea5400ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
- {"CIU2_EN_PP0_IP4_MIO" , 0x1070100093400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP1_IP4_MIO" , 0x1070100293400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP2_IP4_MIO" , 0x1070100493400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP3_IP4_MIO" , 0x1070100693400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP4_IP4_MIO" , 0x1070100893400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP5_IP4_MIO" , 0x1070100a93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP6_IP4_MIO" , 0x1070100c93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP7_IP4_MIO" , 0x1070100e93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP8_IP4_MIO" , 0x1070101093400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP9_IP4_MIO" , 0x1070101293400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP10_IP4_MIO" , 0x1070101493400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP11_IP4_MIO" , 0x1070101693400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP12_IP4_MIO" , 0x1070101893400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP13_IP4_MIO" , 0x1070101a93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP14_IP4_MIO" , 0x1070101c93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP15_IP4_MIO" , 0x1070101e93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP16_IP4_MIO" , 0x1070102093400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP17_IP4_MIO" , 0x1070102293400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP18_IP4_MIO" , 0x1070102493400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP19_IP4_MIO" , 0x1070102693400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP20_IP4_MIO" , 0x1070102893400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP21_IP4_MIO" , 0x1070102a93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP22_IP4_MIO" , 0x1070102c93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP23_IP4_MIO" , 0x1070102e93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP24_IP4_MIO" , 0x1070103093400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP25_IP4_MIO" , 0x1070103293400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP26_IP4_MIO" , 0x1070103493400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP27_IP4_MIO" , 0x1070103693400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP28_IP4_MIO" , 0x1070103893400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP29_IP4_MIO" , 0x1070103a93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP30_IP4_MIO" , 0x1070103c93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP31_IP4_MIO" , 0x1070103e93400ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
- {"CIU2_EN_PP0_IP4_MIO_W1C" , 0x10701000b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP1_IP4_MIO_W1C" , 0x10701002b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP2_IP4_MIO_W1C" , 0x10701004b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP3_IP4_MIO_W1C" , 0x10701006b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP4_IP4_MIO_W1C" , 0x10701008b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP5_IP4_MIO_W1C" , 0x1070100ab3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP6_IP4_MIO_W1C" , 0x1070100cb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP7_IP4_MIO_W1C" , 0x1070100eb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP8_IP4_MIO_W1C" , 0x10701010b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP9_IP4_MIO_W1C" , 0x10701012b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP10_IP4_MIO_W1C" , 0x10701014b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP11_IP4_MIO_W1C" , 0x10701016b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP12_IP4_MIO_W1C" , 0x10701018b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP13_IP4_MIO_W1C" , 0x1070101ab3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP14_IP4_MIO_W1C" , 0x1070101cb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP15_IP4_MIO_W1C" , 0x1070101eb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP16_IP4_MIO_W1C" , 0x10701020b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP17_IP4_MIO_W1C" , 0x10701022b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP18_IP4_MIO_W1C" , 0x10701024b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP19_IP4_MIO_W1C" , 0x10701026b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP20_IP4_MIO_W1C" , 0x10701028b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP21_IP4_MIO_W1C" , 0x1070102ab3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP22_IP4_MIO_W1C" , 0x1070102cb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP23_IP4_MIO_W1C" , 0x1070102eb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP24_IP4_MIO_W1C" , 0x10701030b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP25_IP4_MIO_W1C" , 0x10701032b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP26_IP4_MIO_W1C" , 0x10701034b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP27_IP4_MIO_W1C" , 0x10701036b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP28_IP4_MIO_W1C" , 0x10701038b3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP29_IP4_MIO_W1C" , 0x1070103ab3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP30_IP4_MIO_W1C" , 0x1070103cb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP31_IP4_MIO_W1C" , 0x1070103eb3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
- {"CIU2_EN_PP0_IP4_MIO_W1S" , 0x10701000a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP1_IP4_MIO_W1S" , 0x10701002a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP2_IP4_MIO_W1S" , 0x10701004a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP3_IP4_MIO_W1S" , 0x10701006a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP4_IP4_MIO_W1S" , 0x10701008a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP5_IP4_MIO_W1S" , 0x1070100aa3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP6_IP4_MIO_W1S" , 0x1070100ca3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP7_IP4_MIO_W1S" , 0x1070100ea3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP8_IP4_MIO_W1S" , 0x10701010a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP9_IP4_MIO_W1S" , 0x10701012a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP10_IP4_MIO_W1S" , 0x10701014a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP11_IP4_MIO_W1S" , 0x10701016a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP12_IP4_MIO_W1S" , 0x10701018a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP13_IP4_MIO_W1S" , 0x1070101aa3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP14_IP4_MIO_W1S" , 0x1070101ca3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP15_IP4_MIO_W1S" , 0x1070101ea3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP16_IP4_MIO_W1S" , 0x10701020a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP17_IP4_MIO_W1S" , 0x10701022a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP18_IP4_MIO_W1S" , 0x10701024a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP19_IP4_MIO_W1S" , 0x10701026a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP20_IP4_MIO_W1S" , 0x10701028a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP21_IP4_MIO_W1S" , 0x1070102aa3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP22_IP4_MIO_W1S" , 0x1070102ca3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP23_IP4_MIO_W1S" , 0x1070102ea3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP24_IP4_MIO_W1S" , 0x10701030a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP25_IP4_MIO_W1S" , 0x10701032a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP26_IP4_MIO_W1S" , 0x10701034a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP27_IP4_MIO_W1S" , 0x10701036a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP28_IP4_MIO_W1S" , 0x10701038a3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP29_IP4_MIO_W1S" , 0x1070103aa3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP30_IP4_MIO_W1S" , 0x1070103ca3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP31_IP4_MIO_W1S" , 0x1070103ea3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
- {"CIU2_EN_PP0_IP4_PKT" , 0x1070100096400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP1_IP4_PKT" , 0x1070100296400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP2_IP4_PKT" , 0x1070100496400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP3_IP4_PKT" , 0x1070100696400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP4_IP4_PKT" , 0x1070100896400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP5_IP4_PKT" , 0x1070100a96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP6_IP4_PKT" , 0x1070100c96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP7_IP4_PKT" , 0x1070100e96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP8_IP4_PKT" , 0x1070101096400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP9_IP4_PKT" , 0x1070101296400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP10_IP4_PKT" , 0x1070101496400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP11_IP4_PKT" , 0x1070101696400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP12_IP4_PKT" , 0x1070101896400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP13_IP4_PKT" , 0x1070101a96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP14_IP4_PKT" , 0x1070101c96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP15_IP4_PKT" , 0x1070101e96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP16_IP4_PKT" , 0x1070102096400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP17_IP4_PKT" , 0x1070102296400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP18_IP4_PKT" , 0x1070102496400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP19_IP4_PKT" , 0x1070102696400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP20_IP4_PKT" , 0x1070102896400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP21_IP4_PKT" , 0x1070102a96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP22_IP4_PKT" , 0x1070102c96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP23_IP4_PKT" , 0x1070102e96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP24_IP4_PKT" , 0x1070103096400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP25_IP4_PKT" , 0x1070103296400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP26_IP4_PKT" , 0x1070103496400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP27_IP4_PKT" , 0x1070103696400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP28_IP4_PKT" , 0x1070103896400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP29_IP4_PKT" , 0x1070103a96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP30_IP4_PKT" , 0x1070103c96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP31_IP4_PKT" , 0x1070103e96400ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
- {"CIU2_EN_PP0_IP4_PKT_W1C" , 0x10701000b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP1_IP4_PKT_W1C" , 0x10701002b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP2_IP4_PKT_W1C" , 0x10701004b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP3_IP4_PKT_W1C" , 0x10701006b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP4_IP4_PKT_W1C" , 0x10701008b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP5_IP4_PKT_W1C" , 0x1070100ab6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP6_IP4_PKT_W1C" , 0x1070100cb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP7_IP4_PKT_W1C" , 0x1070100eb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP8_IP4_PKT_W1C" , 0x10701010b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP9_IP4_PKT_W1C" , 0x10701012b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP10_IP4_PKT_W1C" , 0x10701014b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP11_IP4_PKT_W1C" , 0x10701016b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP12_IP4_PKT_W1C" , 0x10701018b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP13_IP4_PKT_W1C" , 0x1070101ab6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP14_IP4_PKT_W1C" , 0x1070101cb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP15_IP4_PKT_W1C" , 0x1070101eb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP16_IP4_PKT_W1C" , 0x10701020b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP17_IP4_PKT_W1C" , 0x10701022b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP18_IP4_PKT_W1C" , 0x10701024b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP19_IP4_PKT_W1C" , 0x10701026b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP20_IP4_PKT_W1C" , 0x10701028b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP21_IP4_PKT_W1C" , 0x1070102ab6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP22_IP4_PKT_W1C" , 0x1070102cb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP23_IP4_PKT_W1C" , 0x1070102eb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP24_IP4_PKT_W1C" , 0x10701030b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP25_IP4_PKT_W1C" , 0x10701032b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP26_IP4_PKT_W1C" , 0x10701034b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP27_IP4_PKT_W1C" , 0x10701036b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP28_IP4_PKT_W1C" , 0x10701038b6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP29_IP4_PKT_W1C" , 0x1070103ab6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP30_IP4_PKT_W1C" , 0x1070103cb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP31_IP4_PKT_W1C" , 0x1070103eb6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
- {"CIU2_EN_PP0_IP4_PKT_W1S" , 0x10701000a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP1_IP4_PKT_W1S" , 0x10701002a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP2_IP4_PKT_W1S" , 0x10701004a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP3_IP4_PKT_W1S" , 0x10701006a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP4_IP4_PKT_W1S" , 0x10701008a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP5_IP4_PKT_W1S" , 0x1070100aa6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP6_IP4_PKT_W1S" , 0x1070100ca6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP7_IP4_PKT_W1S" , 0x1070100ea6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP8_IP4_PKT_W1S" , 0x10701010a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP9_IP4_PKT_W1S" , 0x10701012a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP10_IP4_PKT_W1S" , 0x10701014a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP11_IP4_PKT_W1S" , 0x10701016a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP12_IP4_PKT_W1S" , 0x10701018a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP13_IP4_PKT_W1S" , 0x1070101aa6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP14_IP4_PKT_W1S" , 0x1070101ca6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP15_IP4_PKT_W1S" , 0x1070101ea6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP16_IP4_PKT_W1S" , 0x10701020a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP17_IP4_PKT_W1S" , 0x10701022a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP18_IP4_PKT_W1S" , 0x10701024a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP19_IP4_PKT_W1S" , 0x10701026a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP20_IP4_PKT_W1S" , 0x10701028a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP21_IP4_PKT_W1S" , 0x1070102aa6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP22_IP4_PKT_W1S" , 0x1070102ca6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP23_IP4_PKT_W1S" , 0x1070102ea6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP24_IP4_PKT_W1S" , 0x10701030a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP25_IP4_PKT_W1S" , 0x10701032a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP26_IP4_PKT_W1S" , 0x10701034a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP27_IP4_PKT_W1S" , 0x10701036a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP28_IP4_PKT_W1S" , 0x10701038a6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP29_IP4_PKT_W1S" , 0x1070103aa6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP30_IP4_PKT_W1S" , 0x1070103ca6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP31_IP4_PKT_W1S" , 0x1070103ea6400ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
- {"CIU2_EN_PP0_IP4_RML" , 0x1070100092400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP1_IP4_RML" , 0x1070100292400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP2_IP4_RML" , 0x1070100492400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP3_IP4_RML" , 0x1070100692400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP4_IP4_RML" , 0x1070100892400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP5_IP4_RML" , 0x1070100a92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP6_IP4_RML" , 0x1070100c92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP7_IP4_RML" , 0x1070100e92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP8_IP4_RML" , 0x1070101092400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP9_IP4_RML" , 0x1070101292400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP10_IP4_RML" , 0x1070101492400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP11_IP4_RML" , 0x1070101692400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP12_IP4_RML" , 0x1070101892400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP13_IP4_RML" , 0x1070101a92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP14_IP4_RML" , 0x1070101c92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP15_IP4_RML" , 0x1070101e92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP16_IP4_RML" , 0x1070102092400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP17_IP4_RML" , 0x1070102292400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP18_IP4_RML" , 0x1070102492400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP19_IP4_RML" , 0x1070102692400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP20_IP4_RML" , 0x1070102892400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP21_IP4_RML" , 0x1070102a92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP22_IP4_RML" , 0x1070102c92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP23_IP4_RML" , 0x1070102e92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP24_IP4_RML" , 0x1070103092400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP25_IP4_RML" , 0x1070103292400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP26_IP4_RML" , 0x1070103492400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP27_IP4_RML" , 0x1070103692400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP28_IP4_RML" , 0x1070103892400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP29_IP4_RML" , 0x1070103a92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP30_IP4_RML" , 0x1070103c92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP31_IP4_RML" , 0x1070103e92400ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
- {"CIU2_EN_PP0_IP4_RML_W1C" , 0x10701000b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP1_IP4_RML_W1C" , 0x10701002b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP2_IP4_RML_W1C" , 0x10701004b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP3_IP4_RML_W1C" , 0x10701006b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP4_IP4_RML_W1C" , 0x10701008b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP5_IP4_RML_W1C" , 0x1070100ab2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP6_IP4_RML_W1C" , 0x1070100cb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP7_IP4_RML_W1C" , 0x1070100eb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP8_IP4_RML_W1C" , 0x10701010b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP9_IP4_RML_W1C" , 0x10701012b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP10_IP4_RML_W1C" , 0x10701014b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP11_IP4_RML_W1C" , 0x10701016b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP12_IP4_RML_W1C" , 0x10701018b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP13_IP4_RML_W1C" , 0x1070101ab2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP14_IP4_RML_W1C" , 0x1070101cb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP15_IP4_RML_W1C" , 0x1070101eb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP16_IP4_RML_W1C" , 0x10701020b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP17_IP4_RML_W1C" , 0x10701022b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP18_IP4_RML_W1C" , 0x10701024b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP19_IP4_RML_W1C" , 0x10701026b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP20_IP4_RML_W1C" , 0x10701028b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP21_IP4_RML_W1C" , 0x1070102ab2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP22_IP4_RML_W1C" , 0x1070102cb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP23_IP4_RML_W1C" , 0x1070102eb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP24_IP4_RML_W1C" , 0x10701030b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP25_IP4_RML_W1C" , 0x10701032b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP26_IP4_RML_W1C" , 0x10701034b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP27_IP4_RML_W1C" , 0x10701036b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP28_IP4_RML_W1C" , 0x10701038b2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP29_IP4_RML_W1C" , 0x1070103ab2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP30_IP4_RML_W1C" , 0x1070103cb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP31_IP4_RML_W1C" , 0x1070103eb2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
- {"CIU2_EN_PP0_IP4_RML_W1S" , 0x10701000a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP1_IP4_RML_W1S" , 0x10701002a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP2_IP4_RML_W1S" , 0x10701004a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP3_IP4_RML_W1S" , 0x10701006a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP4_IP4_RML_W1S" , 0x10701008a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP5_IP4_RML_W1S" , 0x1070100aa2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP6_IP4_RML_W1S" , 0x1070100ca2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP7_IP4_RML_W1S" , 0x1070100ea2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP8_IP4_RML_W1S" , 0x10701010a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP9_IP4_RML_W1S" , 0x10701012a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP10_IP4_RML_W1S" , 0x10701014a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP11_IP4_RML_W1S" , 0x10701016a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP12_IP4_RML_W1S" , 0x10701018a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP13_IP4_RML_W1S" , 0x1070101aa2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP14_IP4_RML_W1S" , 0x1070101ca2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP15_IP4_RML_W1S" , 0x1070101ea2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP16_IP4_RML_W1S" , 0x10701020a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP17_IP4_RML_W1S" , 0x10701022a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP18_IP4_RML_W1S" , 0x10701024a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP19_IP4_RML_W1S" , 0x10701026a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP20_IP4_RML_W1S" , 0x10701028a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP21_IP4_RML_W1S" , 0x1070102aa2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP22_IP4_RML_W1S" , 0x1070102ca2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP23_IP4_RML_W1S" , 0x1070102ea2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP24_IP4_RML_W1S" , 0x10701030a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP25_IP4_RML_W1S" , 0x10701032a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP26_IP4_RML_W1S" , 0x10701034a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP27_IP4_RML_W1S" , 0x10701036a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP28_IP4_RML_W1S" , 0x10701038a2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP29_IP4_RML_W1S" , 0x1070103aa2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP30_IP4_RML_W1S" , 0x1070103ca2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP31_IP4_RML_W1S" , 0x1070103ea2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
- {"CIU2_EN_PP0_IP4_WDOG" , 0x1070100091400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP1_IP4_WDOG" , 0x1070100291400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP2_IP4_WDOG" , 0x1070100491400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP3_IP4_WDOG" , 0x1070100691400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP4_IP4_WDOG" , 0x1070100891400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP5_IP4_WDOG" , 0x1070100a91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP6_IP4_WDOG" , 0x1070100c91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP7_IP4_WDOG" , 0x1070100e91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP8_IP4_WDOG" , 0x1070101091400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP9_IP4_WDOG" , 0x1070101291400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP10_IP4_WDOG" , 0x1070101491400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP11_IP4_WDOG" , 0x1070101691400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP12_IP4_WDOG" , 0x1070101891400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP13_IP4_WDOG" , 0x1070101a91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP14_IP4_WDOG" , 0x1070101c91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP15_IP4_WDOG" , 0x1070101e91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP16_IP4_WDOG" , 0x1070102091400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP17_IP4_WDOG" , 0x1070102291400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP18_IP4_WDOG" , 0x1070102491400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP19_IP4_WDOG" , 0x1070102691400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP20_IP4_WDOG" , 0x1070102891400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP21_IP4_WDOG" , 0x1070102a91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP22_IP4_WDOG" , 0x1070102c91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP23_IP4_WDOG" , 0x1070102e91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP24_IP4_WDOG" , 0x1070103091400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP25_IP4_WDOG" , 0x1070103291400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP26_IP4_WDOG" , 0x1070103491400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP27_IP4_WDOG" , 0x1070103691400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP28_IP4_WDOG" , 0x1070103891400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP29_IP4_WDOG" , 0x1070103a91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP30_IP4_WDOG" , 0x1070103c91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP31_IP4_WDOG" , 0x1070103e91400ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
- {"CIU2_EN_PP0_IP4_WDOG_W1C" , 0x10701000b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP1_IP4_WDOG_W1C" , 0x10701002b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP2_IP4_WDOG_W1C" , 0x10701004b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP3_IP4_WDOG_W1C" , 0x10701006b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP4_IP4_WDOG_W1C" , 0x10701008b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP5_IP4_WDOG_W1C" , 0x1070100ab1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP6_IP4_WDOG_W1C" , 0x1070100cb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP7_IP4_WDOG_W1C" , 0x1070100eb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP8_IP4_WDOG_W1C" , 0x10701010b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP9_IP4_WDOG_W1C" , 0x10701012b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP10_IP4_WDOG_W1C" , 0x10701014b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP11_IP4_WDOG_W1C" , 0x10701016b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP12_IP4_WDOG_W1C" , 0x10701018b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP13_IP4_WDOG_W1C" , 0x1070101ab1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP14_IP4_WDOG_W1C" , 0x1070101cb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP15_IP4_WDOG_W1C" , 0x1070101eb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP16_IP4_WDOG_W1C" , 0x10701020b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP17_IP4_WDOG_W1C" , 0x10701022b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP18_IP4_WDOG_W1C" , 0x10701024b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP19_IP4_WDOG_W1C" , 0x10701026b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP20_IP4_WDOG_W1C" , 0x10701028b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP21_IP4_WDOG_W1C" , 0x1070102ab1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP22_IP4_WDOG_W1C" , 0x1070102cb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP23_IP4_WDOG_W1C" , 0x1070102eb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP24_IP4_WDOG_W1C" , 0x10701030b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP25_IP4_WDOG_W1C" , 0x10701032b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP26_IP4_WDOG_W1C" , 0x10701034b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP27_IP4_WDOG_W1C" , 0x10701036b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP28_IP4_WDOG_W1C" , 0x10701038b1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP29_IP4_WDOG_W1C" , 0x1070103ab1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP30_IP4_WDOG_W1C" , 0x1070103cb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP31_IP4_WDOG_W1C" , 0x1070103eb1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
- {"CIU2_EN_PP0_IP4_WDOG_W1S" , 0x10701000a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP1_IP4_WDOG_W1S" , 0x10701002a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP2_IP4_WDOG_W1S" , 0x10701004a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP3_IP4_WDOG_W1S" , 0x10701006a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP4_IP4_WDOG_W1S" , 0x10701008a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP5_IP4_WDOG_W1S" , 0x1070100aa1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP6_IP4_WDOG_W1S" , 0x1070100ca1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP7_IP4_WDOG_W1S" , 0x1070100ea1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP8_IP4_WDOG_W1S" , 0x10701010a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP9_IP4_WDOG_W1S" , 0x10701012a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP10_IP4_WDOG_W1S" , 0x10701014a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP11_IP4_WDOG_W1S" , 0x10701016a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP12_IP4_WDOG_W1S" , 0x10701018a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP13_IP4_WDOG_W1S" , 0x1070101aa1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP14_IP4_WDOG_W1S" , 0x1070101ca1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP15_IP4_WDOG_W1S" , 0x1070101ea1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP16_IP4_WDOG_W1S" , 0x10701020a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP17_IP4_WDOG_W1S" , 0x10701022a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP18_IP4_WDOG_W1S" , 0x10701024a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP19_IP4_WDOG_W1S" , 0x10701026a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP20_IP4_WDOG_W1S" , 0x10701028a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP21_IP4_WDOG_W1S" , 0x1070102aa1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP22_IP4_WDOG_W1S" , 0x1070102ca1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP23_IP4_WDOG_W1S" , 0x1070102ea1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP24_IP4_WDOG_W1S" , 0x10701030a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP25_IP4_WDOG_W1S" , 0x10701032a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP26_IP4_WDOG_W1S" , 0x10701034a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP27_IP4_WDOG_W1S" , 0x10701036a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP28_IP4_WDOG_W1S" , 0x10701038a1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP29_IP4_WDOG_W1S" , 0x1070103aa1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP30_IP4_WDOG_W1S" , 0x1070103ca1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP31_IP4_WDOG_W1S" , 0x1070103ea1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
- {"CIU2_EN_PP0_IP4_WRKQ" , 0x1070100090400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP1_IP4_WRKQ" , 0x1070100290400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP2_IP4_WRKQ" , 0x1070100490400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP3_IP4_WRKQ" , 0x1070100690400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP4_IP4_WRKQ" , 0x1070100890400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP5_IP4_WRKQ" , 0x1070100a90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP6_IP4_WRKQ" , 0x1070100c90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP7_IP4_WRKQ" , 0x1070100e90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP8_IP4_WRKQ" , 0x1070101090400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP9_IP4_WRKQ" , 0x1070101290400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP10_IP4_WRKQ" , 0x1070101490400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP11_IP4_WRKQ" , 0x1070101690400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP12_IP4_WRKQ" , 0x1070101890400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP13_IP4_WRKQ" , 0x1070101a90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP14_IP4_WRKQ" , 0x1070101c90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP15_IP4_WRKQ" , 0x1070101e90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP16_IP4_WRKQ" , 0x1070102090400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP17_IP4_WRKQ" , 0x1070102290400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP18_IP4_WRKQ" , 0x1070102490400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP19_IP4_WRKQ" , 0x1070102690400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP20_IP4_WRKQ" , 0x1070102890400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP21_IP4_WRKQ" , 0x1070102a90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP22_IP4_WRKQ" , 0x1070102c90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP23_IP4_WRKQ" , 0x1070102e90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP24_IP4_WRKQ" , 0x1070103090400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP25_IP4_WRKQ" , 0x1070103290400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP26_IP4_WRKQ" , 0x1070103490400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP27_IP4_WRKQ" , 0x1070103690400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP28_IP4_WRKQ" , 0x1070103890400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP29_IP4_WRKQ" , 0x1070103a90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP30_IP4_WRKQ" , 0x1070103c90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP31_IP4_WRKQ" , 0x1070103e90400ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
- {"CIU2_EN_PP0_IP4_WRKQ_W1C" , 0x10701000b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP1_IP4_WRKQ_W1C" , 0x10701002b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP2_IP4_WRKQ_W1C" , 0x10701004b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP3_IP4_WRKQ_W1C" , 0x10701006b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP4_IP4_WRKQ_W1C" , 0x10701008b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP5_IP4_WRKQ_W1C" , 0x1070100ab0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP6_IP4_WRKQ_W1C" , 0x1070100cb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP7_IP4_WRKQ_W1C" , 0x1070100eb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP8_IP4_WRKQ_W1C" , 0x10701010b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP9_IP4_WRKQ_W1C" , 0x10701012b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP10_IP4_WRKQ_W1C" , 0x10701014b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP11_IP4_WRKQ_W1C" , 0x10701016b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP12_IP4_WRKQ_W1C" , 0x10701018b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP13_IP4_WRKQ_W1C" , 0x1070101ab0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP14_IP4_WRKQ_W1C" , 0x1070101cb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP15_IP4_WRKQ_W1C" , 0x1070101eb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP16_IP4_WRKQ_W1C" , 0x10701020b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP17_IP4_WRKQ_W1C" , 0x10701022b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP18_IP4_WRKQ_W1C" , 0x10701024b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP19_IP4_WRKQ_W1C" , 0x10701026b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP20_IP4_WRKQ_W1C" , 0x10701028b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP21_IP4_WRKQ_W1C" , 0x1070102ab0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP22_IP4_WRKQ_W1C" , 0x1070102cb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP23_IP4_WRKQ_W1C" , 0x1070102eb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP24_IP4_WRKQ_W1C" , 0x10701030b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP25_IP4_WRKQ_W1C" , 0x10701032b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP26_IP4_WRKQ_W1C" , 0x10701034b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP27_IP4_WRKQ_W1C" , 0x10701036b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP28_IP4_WRKQ_W1C" , 0x10701038b0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP29_IP4_WRKQ_W1C" , 0x1070103ab0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP30_IP4_WRKQ_W1C" , 0x1070103cb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP31_IP4_WRKQ_W1C" , 0x1070103eb0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
- {"CIU2_EN_PP0_IP4_WRKQ_W1S" , 0x10701000a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP1_IP4_WRKQ_W1S" , 0x10701002a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP2_IP4_WRKQ_W1S" , 0x10701004a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP3_IP4_WRKQ_W1S" , 0x10701006a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP4_IP4_WRKQ_W1S" , 0x10701008a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP5_IP4_WRKQ_W1S" , 0x1070100aa0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP6_IP4_WRKQ_W1S" , 0x1070100ca0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP7_IP4_WRKQ_W1S" , 0x1070100ea0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP8_IP4_WRKQ_W1S" , 0x10701010a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP9_IP4_WRKQ_W1S" , 0x10701012a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP10_IP4_WRKQ_W1S" , 0x10701014a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP11_IP4_WRKQ_W1S" , 0x10701016a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP12_IP4_WRKQ_W1S" , 0x10701018a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP13_IP4_WRKQ_W1S" , 0x1070101aa0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP14_IP4_WRKQ_W1S" , 0x1070101ca0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP15_IP4_WRKQ_W1S" , 0x1070101ea0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP16_IP4_WRKQ_W1S" , 0x10701020a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP17_IP4_WRKQ_W1S" , 0x10701022a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP18_IP4_WRKQ_W1S" , 0x10701024a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP19_IP4_WRKQ_W1S" , 0x10701026a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP20_IP4_WRKQ_W1S" , 0x10701028a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP21_IP4_WRKQ_W1S" , 0x1070102aa0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP22_IP4_WRKQ_W1S" , 0x1070102ca0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP23_IP4_WRKQ_W1S" , 0x1070102ea0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP24_IP4_WRKQ_W1S" , 0x10701030a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP25_IP4_WRKQ_W1S" , 0x10701032a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP26_IP4_WRKQ_W1S" , 0x10701034a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP27_IP4_WRKQ_W1S" , 0x10701036a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP28_IP4_WRKQ_W1S" , 0x10701038a0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP29_IP4_WRKQ_W1S" , 0x1070103aa0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP30_IP4_WRKQ_W1S" , 0x1070103ca0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_EN_PP31_IP4_WRKQ_W1S" , 0x1070103ea0400ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
- {"CIU2_INTR_CIU_READY" , 0x1070100102008ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
- {"CIU2_INTR_RAM_ECC_CTL" , 0x1070100102010ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
- {"CIU2_INTR_RAM_ECC_ST" , 0x1070100102018ull, CVMX_CSR_DB_TYPE_NCB, 64, 186},
- {"CIU2_INTR_SLOWDOWN" , 0x1070100102000ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
- {"CIU2_MSI_RCV0" , 0x10701000c2000ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV1" , 0x10701000c2008ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV2" , 0x10701000c2010ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV3" , 0x10701000c2018ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV4" , 0x10701000c2020ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV5" , 0x10701000c2028ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV6" , 0x10701000c2030ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV7" , 0x10701000c2038ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV8" , 0x10701000c2040ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV9" , 0x10701000c2048ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV10" , 0x10701000c2050ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV11" , 0x10701000c2058ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV12" , 0x10701000c2060ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV13" , 0x10701000c2068ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV14" , 0x10701000c2070ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV15" , 0x10701000c2078ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV16" , 0x10701000c2080ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV17" , 0x10701000c2088ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV18" , 0x10701000c2090ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV19" , 0x10701000c2098ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV20" , 0x10701000c20a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV21" , 0x10701000c20a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV22" , 0x10701000c20b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV23" , 0x10701000c20b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV24" , 0x10701000c20c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV25" , 0x10701000c20c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV26" , 0x10701000c20d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV27" , 0x10701000c20d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV28" , 0x10701000c20e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV29" , 0x10701000c20e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV30" , 0x10701000c20f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV31" , 0x10701000c20f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV32" , 0x10701000c2100ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV33" , 0x10701000c2108ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV34" , 0x10701000c2110ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV35" , 0x10701000c2118ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV36" , 0x10701000c2120ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV37" , 0x10701000c2128ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV38" , 0x10701000c2130ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV39" , 0x10701000c2138ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV40" , 0x10701000c2140ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV41" , 0x10701000c2148ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV42" , 0x10701000c2150ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV43" , 0x10701000c2158ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV44" , 0x10701000c2160ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV45" , 0x10701000c2168ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV46" , 0x10701000c2170ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV47" , 0x10701000c2178ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV48" , 0x10701000c2180ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV49" , 0x10701000c2188ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV50" , 0x10701000c2190ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV51" , 0x10701000c2198ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV52" , 0x10701000c21a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV53" , 0x10701000c21a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV54" , 0x10701000c21b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV55" , 0x10701000c21b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV56" , 0x10701000c21c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV57" , 0x10701000c21c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV58" , 0x10701000c21d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV59" , 0x10701000c21d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV60" , 0x10701000c21e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV61" , 0x10701000c21e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV62" , 0x10701000c21f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV63" , 0x10701000c21f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV64" , 0x10701000c2200ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV65" , 0x10701000c2208ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV66" , 0x10701000c2210ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV67" , 0x10701000c2218ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV68" , 0x10701000c2220ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV69" , 0x10701000c2228ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV70" , 0x10701000c2230ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV71" , 0x10701000c2238ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV72" , 0x10701000c2240ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV73" , 0x10701000c2248ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV74" , 0x10701000c2250ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV75" , 0x10701000c2258ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV76" , 0x10701000c2260ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV77" , 0x10701000c2268ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV78" , 0x10701000c2270ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV79" , 0x10701000c2278ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV80" , 0x10701000c2280ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV81" , 0x10701000c2288ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV82" , 0x10701000c2290ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV83" , 0x10701000c2298ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV84" , 0x10701000c22a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV85" , 0x10701000c22a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV86" , 0x10701000c22b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV87" , 0x10701000c22b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV88" , 0x10701000c22c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV89" , 0x10701000c22c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV90" , 0x10701000c22d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV91" , 0x10701000c22d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV92" , 0x10701000c22e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV93" , 0x10701000c22e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV94" , 0x10701000c22f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV95" , 0x10701000c22f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV96" , 0x10701000c2300ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV97" , 0x10701000c2308ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV98" , 0x10701000c2310ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV99" , 0x10701000c2318ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV100" , 0x10701000c2320ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV101" , 0x10701000c2328ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV102" , 0x10701000c2330ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV103" , 0x10701000c2338ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV104" , 0x10701000c2340ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV105" , 0x10701000c2348ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV106" , 0x10701000c2350ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV107" , 0x10701000c2358ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV108" , 0x10701000c2360ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV109" , 0x10701000c2368ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV110" , 0x10701000c2370ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV111" , 0x10701000c2378ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV112" , 0x10701000c2380ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV113" , 0x10701000c2388ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV114" , 0x10701000c2390ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV115" , 0x10701000c2398ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV116" , 0x10701000c23a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV117" , 0x10701000c23a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV118" , 0x10701000c23b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV119" , 0x10701000c23b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV120" , 0x10701000c23c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV121" , 0x10701000c23c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV122" , 0x10701000c23d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV123" , 0x10701000c23d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV124" , 0x10701000c23e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV125" , 0x10701000c23e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV126" , 0x10701000c23f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV127" , 0x10701000c23f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV128" , 0x10701000c2400ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV129" , 0x10701000c2408ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV130" , 0x10701000c2410ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV131" , 0x10701000c2418ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV132" , 0x10701000c2420ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV133" , 0x10701000c2428ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV134" , 0x10701000c2430ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV135" , 0x10701000c2438ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV136" , 0x10701000c2440ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV137" , 0x10701000c2448ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV138" , 0x10701000c2450ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV139" , 0x10701000c2458ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV140" , 0x10701000c2460ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV141" , 0x10701000c2468ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV142" , 0x10701000c2470ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV143" , 0x10701000c2478ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV144" , 0x10701000c2480ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV145" , 0x10701000c2488ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV146" , 0x10701000c2490ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV147" , 0x10701000c2498ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV148" , 0x10701000c24a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV149" , 0x10701000c24a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV150" , 0x10701000c24b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV151" , 0x10701000c24b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV152" , 0x10701000c24c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV153" , 0x10701000c24c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV154" , 0x10701000c24d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV155" , 0x10701000c24d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV156" , 0x10701000c24e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV157" , 0x10701000c24e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV158" , 0x10701000c24f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV159" , 0x10701000c24f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV160" , 0x10701000c2500ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV161" , 0x10701000c2508ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV162" , 0x10701000c2510ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV163" , 0x10701000c2518ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV164" , 0x10701000c2520ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV165" , 0x10701000c2528ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV166" , 0x10701000c2530ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV167" , 0x10701000c2538ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV168" , 0x10701000c2540ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV169" , 0x10701000c2548ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV170" , 0x10701000c2550ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV171" , 0x10701000c2558ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV172" , 0x10701000c2560ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV173" , 0x10701000c2568ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV174" , 0x10701000c2570ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV175" , 0x10701000c2578ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV176" , 0x10701000c2580ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV177" , 0x10701000c2588ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV178" , 0x10701000c2590ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV179" , 0x10701000c2598ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV180" , 0x10701000c25a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV181" , 0x10701000c25a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV182" , 0x10701000c25b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV183" , 0x10701000c25b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV184" , 0x10701000c25c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV185" , 0x10701000c25c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV186" , 0x10701000c25d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV187" , 0x10701000c25d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV188" , 0x10701000c25e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV189" , 0x10701000c25e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV190" , 0x10701000c25f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV191" , 0x10701000c25f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV192" , 0x10701000c2600ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV193" , 0x10701000c2608ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV194" , 0x10701000c2610ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV195" , 0x10701000c2618ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV196" , 0x10701000c2620ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV197" , 0x10701000c2628ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV198" , 0x10701000c2630ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV199" , 0x10701000c2638ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV200" , 0x10701000c2640ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV201" , 0x10701000c2648ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV202" , 0x10701000c2650ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV203" , 0x10701000c2658ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV204" , 0x10701000c2660ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV205" , 0x10701000c2668ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV206" , 0x10701000c2670ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV207" , 0x10701000c2678ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV208" , 0x10701000c2680ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV209" , 0x10701000c2688ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV210" , 0x10701000c2690ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV211" , 0x10701000c2698ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV212" , 0x10701000c26a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV213" , 0x10701000c26a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV214" , 0x10701000c26b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV215" , 0x10701000c26b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV216" , 0x10701000c26c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV217" , 0x10701000c26c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV218" , 0x10701000c26d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV219" , 0x10701000c26d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV220" , 0x10701000c26e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV221" , 0x10701000c26e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV222" , 0x10701000c26f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV223" , 0x10701000c26f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV224" , 0x10701000c2700ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV225" , 0x10701000c2708ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV226" , 0x10701000c2710ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV227" , 0x10701000c2718ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV228" , 0x10701000c2720ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV229" , 0x10701000c2728ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV230" , 0x10701000c2730ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV231" , 0x10701000c2738ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV232" , 0x10701000c2740ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV233" , 0x10701000c2748ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV234" , 0x10701000c2750ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV235" , 0x10701000c2758ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV236" , 0x10701000c2760ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV237" , 0x10701000c2768ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV238" , 0x10701000c2770ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV239" , 0x10701000c2778ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV240" , 0x10701000c2780ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV241" , 0x10701000c2788ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV242" , 0x10701000c2790ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV243" , 0x10701000c2798ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV244" , 0x10701000c27a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV245" , 0x10701000c27a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV246" , 0x10701000c27b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV247" , 0x10701000c27b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV248" , 0x10701000c27c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV249" , 0x10701000c27c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV250" , 0x10701000c27d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV251" , 0x10701000c27d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV252" , 0x10701000c27e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV253" , 0x10701000c27e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV254" , 0x10701000c27f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_RCV255" , 0x10701000c27f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
- {"CIU2_MSI_SEL0" , 0x10701000c3000ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL1" , 0x10701000c3008ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL2" , 0x10701000c3010ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL3" , 0x10701000c3018ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL4" , 0x10701000c3020ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL5" , 0x10701000c3028ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL6" , 0x10701000c3030ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL7" , 0x10701000c3038ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL8" , 0x10701000c3040ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL9" , 0x10701000c3048ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL10" , 0x10701000c3050ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL11" , 0x10701000c3058ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL12" , 0x10701000c3060ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL13" , 0x10701000c3068ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL14" , 0x10701000c3070ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL15" , 0x10701000c3078ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL16" , 0x10701000c3080ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL17" , 0x10701000c3088ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL18" , 0x10701000c3090ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL19" , 0x10701000c3098ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL20" , 0x10701000c30a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL21" , 0x10701000c30a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL22" , 0x10701000c30b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL23" , 0x10701000c30b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL24" , 0x10701000c30c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL25" , 0x10701000c30c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL26" , 0x10701000c30d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL27" , 0x10701000c30d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL28" , 0x10701000c30e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL29" , 0x10701000c30e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL30" , 0x10701000c30f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL31" , 0x10701000c30f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL32" , 0x10701000c3100ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL33" , 0x10701000c3108ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL34" , 0x10701000c3110ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL35" , 0x10701000c3118ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL36" , 0x10701000c3120ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL37" , 0x10701000c3128ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL38" , 0x10701000c3130ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL39" , 0x10701000c3138ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL40" , 0x10701000c3140ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL41" , 0x10701000c3148ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL42" , 0x10701000c3150ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL43" , 0x10701000c3158ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL44" , 0x10701000c3160ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL45" , 0x10701000c3168ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL46" , 0x10701000c3170ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL47" , 0x10701000c3178ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL48" , 0x10701000c3180ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL49" , 0x10701000c3188ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL50" , 0x10701000c3190ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL51" , 0x10701000c3198ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL52" , 0x10701000c31a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL53" , 0x10701000c31a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL54" , 0x10701000c31b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL55" , 0x10701000c31b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL56" , 0x10701000c31c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL57" , 0x10701000c31c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL58" , 0x10701000c31d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL59" , 0x10701000c31d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL60" , 0x10701000c31e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL61" , 0x10701000c31e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL62" , 0x10701000c31f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL63" , 0x10701000c31f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL64" , 0x10701000c3200ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL65" , 0x10701000c3208ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL66" , 0x10701000c3210ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL67" , 0x10701000c3218ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL68" , 0x10701000c3220ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL69" , 0x10701000c3228ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL70" , 0x10701000c3230ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL71" , 0x10701000c3238ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL72" , 0x10701000c3240ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL73" , 0x10701000c3248ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL74" , 0x10701000c3250ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL75" , 0x10701000c3258ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL76" , 0x10701000c3260ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL77" , 0x10701000c3268ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL78" , 0x10701000c3270ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL79" , 0x10701000c3278ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL80" , 0x10701000c3280ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL81" , 0x10701000c3288ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL82" , 0x10701000c3290ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL83" , 0x10701000c3298ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL84" , 0x10701000c32a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL85" , 0x10701000c32a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL86" , 0x10701000c32b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL87" , 0x10701000c32b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL88" , 0x10701000c32c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL89" , 0x10701000c32c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL90" , 0x10701000c32d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL91" , 0x10701000c32d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL92" , 0x10701000c32e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL93" , 0x10701000c32e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL94" , 0x10701000c32f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL95" , 0x10701000c32f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL96" , 0x10701000c3300ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL97" , 0x10701000c3308ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL98" , 0x10701000c3310ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL99" , 0x10701000c3318ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL100" , 0x10701000c3320ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL101" , 0x10701000c3328ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL102" , 0x10701000c3330ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL103" , 0x10701000c3338ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL104" , 0x10701000c3340ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL105" , 0x10701000c3348ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL106" , 0x10701000c3350ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL107" , 0x10701000c3358ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL108" , 0x10701000c3360ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL109" , 0x10701000c3368ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL110" , 0x10701000c3370ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL111" , 0x10701000c3378ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL112" , 0x10701000c3380ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL113" , 0x10701000c3388ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL114" , 0x10701000c3390ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL115" , 0x10701000c3398ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL116" , 0x10701000c33a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL117" , 0x10701000c33a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL118" , 0x10701000c33b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL119" , 0x10701000c33b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL120" , 0x10701000c33c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL121" , 0x10701000c33c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL122" , 0x10701000c33d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL123" , 0x10701000c33d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL124" , 0x10701000c33e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL125" , 0x10701000c33e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL126" , 0x10701000c33f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL127" , 0x10701000c33f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL128" , 0x10701000c3400ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL129" , 0x10701000c3408ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL130" , 0x10701000c3410ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL131" , 0x10701000c3418ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL132" , 0x10701000c3420ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL133" , 0x10701000c3428ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL134" , 0x10701000c3430ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL135" , 0x10701000c3438ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL136" , 0x10701000c3440ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL137" , 0x10701000c3448ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL138" , 0x10701000c3450ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL139" , 0x10701000c3458ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL140" , 0x10701000c3460ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL141" , 0x10701000c3468ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL142" , 0x10701000c3470ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL143" , 0x10701000c3478ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL144" , 0x10701000c3480ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL145" , 0x10701000c3488ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL146" , 0x10701000c3490ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL147" , 0x10701000c3498ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL148" , 0x10701000c34a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL149" , 0x10701000c34a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL150" , 0x10701000c34b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL151" , 0x10701000c34b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL152" , 0x10701000c34c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL153" , 0x10701000c34c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL154" , 0x10701000c34d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL155" , 0x10701000c34d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL156" , 0x10701000c34e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL157" , 0x10701000c34e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL158" , 0x10701000c34f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL159" , 0x10701000c34f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL160" , 0x10701000c3500ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL161" , 0x10701000c3508ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL162" , 0x10701000c3510ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL163" , 0x10701000c3518ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL164" , 0x10701000c3520ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL165" , 0x10701000c3528ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL166" , 0x10701000c3530ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL167" , 0x10701000c3538ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL168" , 0x10701000c3540ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL169" , 0x10701000c3548ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL170" , 0x10701000c3550ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL171" , 0x10701000c3558ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL172" , 0x10701000c3560ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL173" , 0x10701000c3568ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL174" , 0x10701000c3570ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL175" , 0x10701000c3578ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL176" , 0x10701000c3580ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL177" , 0x10701000c3588ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL178" , 0x10701000c3590ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL179" , 0x10701000c3598ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL180" , 0x10701000c35a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL181" , 0x10701000c35a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL182" , 0x10701000c35b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL183" , 0x10701000c35b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL184" , 0x10701000c35c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL185" , 0x10701000c35c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL186" , 0x10701000c35d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL187" , 0x10701000c35d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL188" , 0x10701000c35e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL189" , 0x10701000c35e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL190" , 0x10701000c35f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL191" , 0x10701000c35f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL192" , 0x10701000c3600ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL193" , 0x10701000c3608ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL194" , 0x10701000c3610ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL195" , 0x10701000c3618ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL196" , 0x10701000c3620ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL197" , 0x10701000c3628ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL198" , 0x10701000c3630ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL199" , 0x10701000c3638ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL200" , 0x10701000c3640ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL201" , 0x10701000c3648ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL202" , 0x10701000c3650ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL203" , 0x10701000c3658ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL204" , 0x10701000c3660ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL205" , 0x10701000c3668ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL206" , 0x10701000c3670ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL207" , 0x10701000c3678ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL208" , 0x10701000c3680ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL209" , 0x10701000c3688ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL210" , 0x10701000c3690ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL211" , 0x10701000c3698ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL212" , 0x10701000c36a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL213" , 0x10701000c36a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL214" , 0x10701000c36b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL215" , 0x10701000c36b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL216" , 0x10701000c36c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL217" , 0x10701000c36c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL218" , 0x10701000c36d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL219" , 0x10701000c36d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL220" , 0x10701000c36e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL221" , 0x10701000c36e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL222" , 0x10701000c36f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL223" , 0x10701000c36f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL224" , 0x10701000c3700ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL225" , 0x10701000c3708ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL226" , 0x10701000c3710ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL227" , 0x10701000c3718ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL228" , 0x10701000c3720ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL229" , 0x10701000c3728ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL230" , 0x10701000c3730ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL231" , 0x10701000c3738ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL232" , 0x10701000c3740ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL233" , 0x10701000c3748ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL234" , 0x10701000c3750ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL235" , 0x10701000c3758ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL236" , 0x10701000c3760ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL237" , 0x10701000c3768ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL238" , 0x10701000c3770ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL239" , 0x10701000c3778ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL240" , 0x10701000c3780ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL241" , 0x10701000c3788ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL242" , 0x10701000c3790ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL243" , 0x10701000c3798ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL244" , 0x10701000c37a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL245" , 0x10701000c37a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL246" , 0x10701000c37b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL247" , 0x10701000c37b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL248" , 0x10701000c37c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL249" , 0x10701000c37c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL250" , 0x10701000c37d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL251" , 0x10701000c37d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL252" , 0x10701000c37e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL253" , 0x10701000c37e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL254" , 0x10701000c37f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSI_SEL255" , 0x10701000c37f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
- {"CIU2_MSIRED_PP0_IP2" , 0x10701000c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP1_IP2" , 0x10701002c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP2_IP2" , 0x10701004c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP3_IP2" , 0x10701006c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP4_IP2" , 0x10701008c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP5_IP2" , 0x1070100ac1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP6_IP2" , 0x1070100cc1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP7_IP2" , 0x1070100ec1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP8_IP2" , 0x10701010c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP9_IP2" , 0x10701012c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP10_IP2" , 0x10701014c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP11_IP2" , 0x10701016c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP12_IP2" , 0x10701018c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP13_IP2" , 0x1070101ac1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP14_IP2" , 0x1070101cc1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP15_IP2" , 0x1070101ec1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP16_IP2" , 0x10701020c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP17_IP2" , 0x10701022c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP18_IP2" , 0x10701024c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP19_IP2" , 0x10701026c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP20_IP2" , 0x10701028c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP21_IP2" , 0x1070102ac1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP22_IP2" , 0x1070102cc1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP23_IP2" , 0x1070102ec1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP24_IP2" , 0x10701030c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP25_IP2" , 0x10701032c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP26_IP2" , 0x10701034c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP27_IP2" , 0x10701036c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP28_IP2" , 0x10701038c1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP29_IP2" , 0x1070103ac1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP30_IP2" , 0x1070103cc1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP31_IP2" , 0x1070103ec1000ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
- {"CIU2_MSIRED_PP0_IP3" , 0x10701000c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP1_IP3" , 0x10701002c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP2_IP3" , 0x10701004c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP3_IP3" , 0x10701006c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP4_IP3" , 0x10701008c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP5_IP3" , 0x1070100ac1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP6_IP3" , 0x1070100cc1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP7_IP3" , 0x1070100ec1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP8_IP3" , 0x10701010c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP9_IP3" , 0x10701012c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP10_IP3" , 0x10701014c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP11_IP3" , 0x10701016c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP12_IP3" , 0x10701018c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP13_IP3" , 0x1070101ac1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP14_IP3" , 0x1070101cc1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP15_IP3" , 0x1070101ec1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP16_IP3" , 0x10701020c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP17_IP3" , 0x10701022c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP18_IP3" , 0x10701024c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP19_IP3" , 0x10701026c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP20_IP3" , 0x10701028c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP21_IP3" , 0x1070102ac1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP22_IP3" , 0x1070102cc1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP23_IP3" , 0x1070102ec1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP24_IP3" , 0x10701030c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP25_IP3" , 0x10701032c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP26_IP3" , 0x10701034c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP27_IP3" , 0x10701036c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP28_IP3" , 0x10701038c1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP29_IP3" , 0x1070103ac1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP30_IP3" , 0x1070103cc1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP31_IP3" , 0x1070103ec1200ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
- {"CIU2_MSIRED_PP0_IP4" , 0x10701000c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP1_IP4" , 0x10701002c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP2_IP4" , 0x10701004c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP3_IP4" , 0x10701006c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP4_IP4" , 0x10701008c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP5_IP4" , 0x1070100ac1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP6_IP4" , 0x1070100cc1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP7_IP4" , 0x1070100ec1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP8_IP4" , 0x10701010c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP9_IP4" , 0x10701012c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP10_IP4" , 0x10701014c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP11_IP4" , 0x10701016c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP12_IP4" , 0x10701018c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP13_IP4" , 0x1070101ac1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP14_IP4" , 0x1070101cc1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP15_IP4" , 0x1070101ec1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP16_IP4" , 0x10701020c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP17_IP4" , 0x10701022c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP18_IP4" , 0x10701024c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP19_IP4" , 0x10701026c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP20_IP4" , 0x10701028c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP21_IP4" , 0x1070102ac1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP22_IP4" , 0x1070102cc1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP23_IP4" , 0x1070102ec1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP24_IP4" , 0x10701030c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP25_IP4" , 0x10701032c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP26_IP4" , 0x10701034c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP27_IP4" , 0x10701036c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP28_IP4" , 0x10701038c1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP29_IP4" , 0x1070103ac1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP30_IP4" , 0x1070103cc1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_MSIRED_PP31_IP4" , 0x1070103ec1400ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
- {"CIU2_RAW_IO0_INT_GPIO" , 0x1070108047800ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
- {"CIU2_RAW_IO1_INT_GPIO" , 0x1070108247800ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
- {"CIU2_RAW_IO0_INT_IO" , 0x1070108044800ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"CIU2_RAW_IO1_INT_IO" , 0x1070108244800ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
- {"CIU2_RAW_IO0_INT_MEM" , 0x1070108045800ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"CIU2_RAW_IO1_INT_MEM" , 0x1070108245800ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
- {"CIU2_RAW_IO0_INT_MIO" , 0x1070108043800ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"CIU2_RAW_IO1_INT_MIO" , 0x1070108243800ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
- {"CIU2_RAW_IO0_INT_PKT" , 0x1070108046800ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"CIU2_RAW_IO1_INT_PKT" , 0x1070108246800ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
- {"CIU2_RAW_IO0_INT_RML" , 0x1070108042800ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"CIU2_RAW_IO1_INT_RML" , 0x1070108242800ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
- {"CIU2_RAW_IO0_INT_WDOG" , 0x1070108041800ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"CIU2_RAW_IO1_INT_WDOG" , 0x1070108241800ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
- {"CIU2_RAW_IO0_INT_WRKQ" , 0x1070108040800ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"CIU2_RAW_IO1_INT_WRKQ" , 0x1070108240800ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
- {"CIU2_RAW_PP0_IP2_GPIO" , 0x1070100047000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP1_IP2_GPIO" , 0x1070100247000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP2_IP2_GPIO" , 0x1070100447000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP3_IP2_GPIO" , 0x1070100647000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP4_IP2_GPIO" , 0x1070100847000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP5_IP2_GPIO" , 0x1070100a47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP6_IP2_GPIO" , 0x1070100c47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP7_IP2_GPIO" , 0x1070100e47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP8_IP2_GPIO" , 0x1070101047000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP9_IP2_GPIO" , 0x1070101247000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP10_IP2_GPIO" , 0x1070101447000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP11_IP2_GPIO" , 0x1070101647000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP12_IP2_GPIO" , 0x1070101847000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP13_IP2_GPIO" , 0x1070101a47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP14_IP2_GPIO" , 0x1070101c47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP15_IP2_GPIO" , 0x1070101e47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP16_IP2_GPIO" , 0x1070102047000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP17_IP2_GPIO" , 0x1070102247000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP18_IP2_GPIO" , 0x1070102447000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP19_IP2_GPIO" , 0x1070102647000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP20_IP2_GPIO" , 0x1070102847000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP21_IP2_GPIO" , 0x1070102a47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP22_IP2_GPIO" , 0x1070102c47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP23_IP2_GPIO" , 0x1070102e47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP24_IP2_GPIO" , 0x1070103047000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP25_IP2_GPIO" , 0x1070103247000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP26_IP2_GPIO" , 0x1070103447000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP27_IP2_GPIO" , 0x1070103647000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP28_IP2_GPIO" , 0x1070103847000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP29_IP2_GPIO" , 0x1070103a47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP30_IP2_GPIO" , 0x1070103c47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP31_IP2_GPIO" , 0x1070103e47000ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
- {"CIU2_RAW_PP0_IP2_IO" , 0x1070100044000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP1_IP2_IO" , 0x1070100244000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP2_IP2_IO" , 0x1070100444000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP3_IP2_IO" , 0x1070100644000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP4_IP2_IO" , 0x1070100844000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP5_IP2_IO" , 0x1070100a44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP6_IP2_IO" , 0x1070100c44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP7_IP2_IO" , 0x1070100e44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP8_IP2_IO" , 0x1070101044000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP9_IP2_IO" , 0x1070101244000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP10_IP2_IO" , 0x1070101444000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP11_IP2_IO" , 0x1070101644000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP12_IP2_IO" , 0x1070101844000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP13_IP2_IO" , 0x1070101a44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP14_IP2_IO" , 0x1070101c44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP15_IP2_IO" , 0x1070101e44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP16_IP2_IO" , 0x1070102044000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP17_IP2_IO" , 0x1070102244000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP18_IP2_IO" , 0x1070102444000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP19_IP2_IO" , 0x1070102644000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP20_IP2_IO" , 0x1070102844000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP21_IP2_IO" , 0x1070102a44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP22_IP2_IO" , 0x1070102c44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP23_IP2_IO" , 0x1070102e44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP24_IP2_IO" , 0x1070103044000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP25_IP2_IO" , 0x1070103244000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP26_IP2_IO" , 0x1070103444000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP27_IP2_IO" , 0x1070103644000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP28_IP2_IO" , 0x1070103844000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP29_IP2_IO" , 0x1070103a44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP30_IP2_IO" , 0x1070103c44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP31_IP2_IO" , 0x1070103e44000ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
- {"CIU2_RAW_PP0_IP2_MEM" , 0x1070100045000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP1_IP2_MEM" , 0x1070100245000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP2_IP2_MEM" , 0x1070100445000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP3_IP2_MEM" , 0x1070100645000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP4_IP2_MEM" , 0x1070100845000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP5_IP2_MEM" , 0x1070100a45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP6_IP2_MEM" , 0x1070100c45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP7_IP2_MEM" , 0x1070100e45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP8_IP2_MEM" , 0x1070101045000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP9_IP2_MEM" , 0x1070101245000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP10_IP2_MEM" , 0x1070101445000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP11_IP2_MEM" , 0x1070101645000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP12_IP2_MEM" , 0x1070101845000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP13_IP2_MEM" , 0x1070101a45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP14_IP2_MEM" , 0x1070101c45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP15_IP2_MEM" , 0x1070101e45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP16_IP2_MEM" , 0x1070102045000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP17_IP2_MEM" , 0x1070102245000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP18_IP2_MEM" , 0x1070102445000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP19_IP2_MEM" , 0x1070102645000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP20_IP2_MEM" , 0x1070102845000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP21_IP2_MEM" , 0x1070102a45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP22_IP2_MEM" , 0x1070102c45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP23_IP2_MEM" , 0x1070102e45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP24_IP2_MEM" , 0x1070103045000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP25_IP2_MEM" , 0x1070103245000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP26_IP2_MEM" , 0x1070103445000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP27_IP2_MEM" , 0x1070103645000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP28_IP2_MEM" , 0x1070103845000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP29_IP2_MEM" , 0x1070103a45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP30_IP2_MEM" , 0x1070103c45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP31_IP2_MEM" , 0x1070103e45000ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
- {"CIU2_RAW_PP0_IP2_MIO" , 0x1070100043000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP1_IP2_MIO" , 0x1070100243000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP2_IP2_MIO" , 0x1070100443000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP3_IP2_MIO" , 0x1070100643000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP4_IP2_MIO" , 0x1070100843000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP5_IP2_MIO" , 0x1070100a43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP6_IP2_MIO" , 0x1070100c43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP7_IP2_MIO" , 0x1070100e43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP8_IP2_MIO" , 0x1070101043000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP9_IP2_MIO" , 0x1070101243000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP10_IP2_MIO" , 0x1070101443000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP11_IP2_MIO" , 0x1070101643000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP12_IP2_MIO" , 0x1070101843000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP13_IP2_MIO" , 0x1070101a43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP14_IP2_MIO" , 0x1070101c43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP15_IP2_MIO" , 0x1070101e43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP16_IP2_MIO" , 0x1070102043000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP17_IP2_MIO" , 0x1070102243000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP18_IP2_MIO" , 0x1070102443000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP19_IP2_MIO" , 0x1070102643000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP20_IP2_MIO" , 0x1070102843000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP21_IP2_MIO" , 0x1070102a43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP22_IP2_MIO" , 0x1070102c43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP23_IP2_MIO" , 0x1070102e43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP24_IP2_MIO" , 0x1070103043000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP25_IP2_MIO" , 0x1070103243000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP26_IP2_MIO" , 0x1070103443000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP27_IP2_MIO" , 0x1070103643000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP28_IP2_MIO" , 0x1070103843000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP29_IP2_MIO" , 0x1070103a43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP30_IP2_MIO" , 0x1070103c43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP31_IP2_MIO" , 0x1070103e43000ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
- {"CIU2_RAW_PP0_IP2_PKT" , 0x1070100046000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP1_IP2_PKT" , 0x1070100246000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP2_IP2_PKT" , 0x1070100446000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP3_IP2_PKT" , 0x1070100646000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP4_IP2_PKT" , 0x1070100846000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP5_IP2_PKT" , 0x1070100a46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP6_IP2_PKT" , 0x1070100c46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP7_IP2_PKT" , 0x1070100e46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP8_IP2_PKT" , 0x1070101046000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP9_IP2_PKT" , 0x1070101246000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP10_IP2_PKT" , 0x1070101446000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP11_IP2_PKT" , 0x1070101646000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP12_IP2_PKT" , 0x1070101846000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP13_IP2_PKT" , 0x1070101a46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP14_IP2_PKT" , 0x1070101c46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP15_IP2_PKT" , 0x1070101e46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP16_IP2_PKT" , 0x1070102046000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP17_IP2_PKT" , 0x1070102246000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP18_IP2_PKT" , 0x1070102446000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP19_IP2_PKT" , 0x1070102646000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP20_IP2_PKT" , 0x1070102846000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP21_IP2_PKT" , 0x1070102a46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP22_IP2_PKT" , 0x1070102c46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP23_IP2_PKT" , 0x1070102e46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP24_IP2_PKT" , 0x1070103046000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP25_IP2_PKT" , 0x1070103246000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP26_IP2_PKT" , 0x1070103446000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP27_IP2_PKT" , 0x1070103646000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP28_IP2_PKT" , 0x1070103846000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP29_IP2_PKT" , 0x1070103a46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP30_IP2_PKT" , 0x1070103c46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP31_IP2_PKT" , 0x1070103e46000ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
- {"CIU2_RAW_PP0_IP2_RML" , 0x1070100042000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP1_IP2_RML" , 0x1070100242000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP2_IP2_RML" , 0x1070100442000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP3_IP2_RML" , 0x1070100642000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP4_IP2_RML" , 0x1070100842000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP5_IP2_RML" , 0x1070100a42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP6_IP2_RML" , 0x1070100c42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP7_IP2_RML" , 0x1070100e42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP8_IP2_RML" , 0x1070101042000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP9_IP2_RML" , 0x1070101242000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP10_IP2_RML" , 0x1070101442000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP11_IP2_RML" , 0x1070101642000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP12_IP2_RML" , 0x1070101842000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP13_IP2_RML" , 0x1070101a42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP14_IP2_RML" , 0x1070101c42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP15_IP2_RML" , 0x1070101e42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP16_IP2_RML" , 0x1070102042000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP17_IP2_RML" , 0x1070102242000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP18_IP2_RML" , 0x1070102442000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP19_IP2_RML" , 0x1070102642000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP20_IP2_RML" , 0x1070102842000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP21_IP2_RML" , 0x1070102a42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP22_IP2_RML" , 0x1070102c42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP23_IP2_RML" , 0x1070102e42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP24_IP2_RML" , 0x1070103042000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP25_IP2_RML" , 0x1070103242000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP26_IP2_RML" , 0x1070103442000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP27_IP2_RML" , 0x1070103642000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP28_IP2_RML" , 0x1070103842000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP29_IP2_RML" , 0x1070103a42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP30_IP2_RML" , 0x1070103c42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP31_IP2_RML" , 0x1070103e42000ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
- {"CIU2_RAW_PP0_IP2_WDOG" , 0x1070100041000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP1_IP2_WDOG" , 0x1070100241000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP2_IP2_WDOG" , 0x1070100441000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP3_IP2_WDOG" , 0x1070100641000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP4_IP2_WDOG" , 0x1070100841000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP5_IP2_WDOG" , 0x1070100a41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP6_IP2_WDOG" , 0x1070100c41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP7_IP2_WDOG" , 0x1070100e41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP8_IP2_WDOG" , 0x1070101041000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP9_IP2_WDOG" , 0x1070101241000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP10_IP2_WDOG" , 0x1070101441000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP11_IP2_WDOG" , 0x1070101641000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP12_IP2_WDOG" , 0x1070101841000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP13_IP2_WDOG" , 0x1070101a41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP14_IP2_WDOG" , 0x1070101c41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP15_IP2_WDOG" , 0x1070101e41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP16_IP2_WDOG" , 0x1070102041000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP17_IP2_WDOG" , 0x1070102241000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP18_IP2_WDOG" , 0x1070102441000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP19_IP2_WDOG" , 0x1070102641000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP20_IP2_WDOG" , 0x1070102841000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP21_IP2_WDOG" , 0x1070102a41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP22_IP2_WDOG" , 0x1070102c41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP23_IP2_WDOG" , 0x1070102e41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP24_IP2_WDOG" , 0x1070103041000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP25_IP2_WDOG" , 0x1070103241000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP26_IP2_WDOG" , 0x1070103441000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP27_IP2_WDOG" , 0x1070103641000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP28_IP2_WDOG" , 0x1070103841000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP29_IP2_WDOG" , 0x1070103a41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP30_IP2_WDOG" , 0x1070103c41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP31_IP2_WDOG" , 0x1070103e41000ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
- {"CIU2_RAW_PP0_IP2_WRKQ" , 0x1070100040000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP1_IP2_WRKQ" , 0x1070100240000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP2_IP2_WRKQ" , 0x1070100440000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP3_IP2_WRKQ" , 0x1070100640000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP4_IP2_WRKQ" , 0x1070100840000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP5_IP2_WRKQ" , 0x1070100a40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP6_IP2_WRKQ" , 0x1070100c40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP7_IP2_WRKQ" , 0x1070100e40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP8_IP2_WRKQ" , 0x1070101040000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP9_IP2_WRKQ" , 0x1070101240000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP10_IP2_WRKQ" , 0x1070101440000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP11_IP2_WRKQ" , 0x1070101640000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP12_IP2_WRKQ" , 0x1070101840000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP13_IP2_WRKQ" , 0x1070101a40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP14_IP2_WRKQ" , 0x1070101c40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP15_IP2_WRKQ" , 0x1070101e40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP16_IP2_WRKQ" , 0x1070102040000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP17_IP2_WRKQ" , 0x1070102240000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP18_IP2_WRKQ" , 0x1070102440000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP19_IP2_WRKQ" , 0x1070102640000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP20_IP2_WRKQ" , 0x1070102840000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP21_IP2_WRKQ" , 0x1070102a40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP22_IP2_WRKQ" , 0x1070102c40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP23_IP2_WRKQ" , 0x1070102e40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP24_IP2_WRKQ" , 0x1070103040000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP25_IP2_WRKQ" , 0x1070103240000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP26_IP2_WRKQ" , 0x1070103440000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP27_IP2_WRKQ" , 0x1070103640000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP28_IP2_WRKQ" , 0x1070103840000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP29_IP2_WRKQ" , 0x1070103a40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP30_IP2_WRKQ" , 0x1070103c40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP31_IP2_WRKQ" , 0x1070103e40000ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
- {"CIU2_RAW_PP0_IP3_GPIO" , 0x1070100047200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP1_IP3_GPIO" , 0x1070100247200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP2_IP3_GPIO" , 0x1070100447200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP3_IP3_GPIO" , 0x1070100647200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP4_IP3_GPIO" , 0x1070100847200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP5_IP3_GPIO" , 0x1070100a47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP6_IP3_GPIO" , 0x1070100c47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP7_IP3_GPIO" , 0x1070100e47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP8_IP3_GPIO" , 0x1070101047200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP9_IP3_GPIO" , 0x1070101247200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP10_IP3_GPIO" , 0x1070101447200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP11_IP3_GPIO" , 0x1070101647200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP12_IP3_GPIO" , 0x1070101847200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP13_IP3_GPIO" , 0x1070101a47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP14_IP3_GPIO" , 0x1070101c47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP15_IP3_GPIO" , 0x1070101e47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP16_IP3_GPIO" , 0x1070102047200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP17_IP3_GPIO" , 0x1070102247200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP18_IP3_GPIO" , 0x1070102447200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP19_IP3_GPIO" , 0x1070102647200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP20_IP3_GPIO" , 0x1070102847200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP21_IP3_GPIO" , 0x1070102a47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP22_IP3_GPIO" , 0x1070102c47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP23_IP3_GPIO" , 0x1070102e47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP24_IP3_GPIO" , 0x1070103047200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP25_IP3_GPIO" , 0x1070103247200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP26_IP3_GPIO" , 0x1070103447200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP27_IP3_GPIO" , 0x1070103647200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP28_IP3_GPIO" , 0x1070103847200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP29_IP3_GPIO" , 0x1070103a47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP30_IP3_GPIO" , 0x1070103c47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP31_IP3_GPIO" , 0x1070103e47200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
- {"CIU2_RAW_PP0_IP3_IO" , 0x1070100044200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP1_IP3_IO" , 0x1070100244200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP2_IP3_IO" , 0x1070100444200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP3_IP3_IO" , 0x1070100644200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP4_IP3_IO" , 0x1070100844200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP5_IP3_IO" , 0x1070100a44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP6_IP3_IO" , 0x1070100c44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP7_IP3_IO" , 0x1070100e44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP8_IP3_IO" , 0x1070101044200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP9_IP3_IO" , 0x1070101244200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP10_IP3_IO" , 0x1070101444200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP11_IP3_IO" , 0x1070101644200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP12_IP3_IO" , 0x1070101844200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP13_IP3_IO" , 0x1070101a44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP14_IP3_IO" , 0x1070101c44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP15_IP3_IO" , 0x1070101e44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP16_IP3_IO" , 0x1070102044200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP17_IP3_IO" , 0x1070102244200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP18_IP3_IO" , 0x1070102444200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP19_IP3_IO" , 0x1070102644200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP20_IP3_IO" , 0x1070102844200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP21_IP3_IO" , 0x1070102a44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP22_IP3_IO" , 0x1070102c44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP23_IP3_IO" , 0x1070102e44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP24_IP3_IO" , 0x1070103044200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP25_IP3_IO" , 0x1070103244200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP26_IP3_IO" , 0x1070103444200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP27_IP3_IO" , 0x1070103644200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP28_IP3_IO" , 0x1070103844200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP29_IP3_IO" , 0x1070103a44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP30_IP3_IO" , 0x1070103c44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP31_IP3_IO" , 0x1070103e44200ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
- {"CIU2_RAW_PP0_IP3_MEM" , 0x1070100045200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP1_IP3_MEM" , 0x1070100245200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP2_IP3_MEM" , 0x1070100445200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP3_IP3_MEM" , 0x1070100645200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP4_IP3_MEM" , 0x1070100845200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP5_IP3_MEM" , 0x1070100a45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP6_IP3_MEM" , 0x1070100c45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP7_IP3_MEM" , 0x1070100e45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP8_IP3_MEM" , 0x1070101045200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP9_IP3_MEM" , 0x1070101245200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP10_IP3_MEM" , 0x1070101445200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP11_IP3_MEM" , 0x1070101645200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP12_IP3_MEM" , 0x1070101845200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP13_IP3_MEM" , 0x1070101a45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP14_IP3_MEM" , 0x1070101c45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP15_IP3_MEM" , 0x1070101e45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP16_IP3_MEM" , 0x1070102045200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP17_IP3_MEM" , 0x1070102245200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP18_IP3_MEM" , 0x1070102445200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP19_IP3_MEM" , 0x1070102645200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP20_IP3_MEM" , 0x1070102845200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP21_IP3_MEM" , 0x1070102a45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP22_IP3_MEM" , 0x1070102c45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP23_IP3_MEM" , 0x1070102e45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP24_IP3_MEM" , 0x1070103045200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP25_IP3_MEM" , 0x1070103245200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP26_IP3_MEM" , 0x1070103445200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP27_IP3_MEM" , 0x1070103645200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP28_IP3_MEM" , 0x1070103845200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP29_IP3_MEM" , 0x1070103a45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP30_IP3_MEM" , 0x1070103c45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP31_IP3_MEM" , 0x1070103e45200ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
- {"CIU2_RAW_PP0_IP3_MIO" , 0x1070100043200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP1_IP3_MIO" , 0x1070100243200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP2_IP3_MIO" , 0x1070100443200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP3_IP3_MIO" , 0x1070100643200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP4_IP3_MIO" , 0x1070100843200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP5_IP3_MIO" , 0x1070100a43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP6_IP3_MIO" , 0x1070100c43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP7_IP3_MIO" , 0x1070100e43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP8_IP3_MIO" , 0x1070101043200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP9_IP3_MIO" , 0x1070101243200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP10_IP3_MIO" , 0x1070101443200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP11_IP3_MIO" , 0x1070101643200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP12_IP3_MIO" , 0x1070101843200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP13_IP3_MIO" , 0x1070101a43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP14_IP3_MIO" , 0x1070101c43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP15_IP3_MIO" , 0x1070101e43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP16_IP3_MIO" , 0x1070102043200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP17_IP3_MIO" , 0x1070102243200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP18_IP3_MIO" , 0x1070102443200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP19_IP3_MIO" , 0x1070102643200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP20_IP3_MIO" , 0x1070102843200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP21_IP3_MIO" , 0x1070102a43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP22_IP3_MIO" , 0x1070102c43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP23_IP3_MIO" , 0x1070102e43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP24_IP3_MIO" , 0x1070103043200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP25_IP3_MIO" , 0x1070103243200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP26_IP3_MIO" , 0x1070103443200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP27_IP3_MIO" , 0x1070103643200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP28_IP3_MIO" , 0x1070103843200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP29_IP3_MIO" , 0x1070103a43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP30_IP3_MIO" , 0x1070103c43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP31_IP3_MIO" , 0x1070103e43200ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
- {"CIU2_RAW_PP0_IP3_PKT" , 0x1070100046200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP1_IP3_PKT" , 0x1070100246200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP2_IP3_PKT" , 0x1070100446200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP3_IP3_PKT" , 0x1070100646200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP4_IP3_PKT" , 0x1070100846200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP5_IP3_PKT" , 0x1070100a46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP6_IP3_PKT" , 0x1070100c46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP7_IP3_PKT" , 0x1070100e46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP8_IP3_PKT" , 0x1070101046200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP9_IP3_PKT" , 0x1070101246200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP10_IP3_PKT" , 0x1070101446200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP11_IP3_PKT" , 0x1070101646200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP12_IP3_PKT" , 0x1070101846200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP13_IP3_PKT" , 0x1070101a46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP14_IP3_PKT" , 0x1070101c46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP15_IP3_PKT" , 0x1070101e46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP16_IP3_PKT" , 0x1070102046200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP17_IP3_PKT" , 0x1070102246200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP18_IP3_PKT" , 0x1070102446200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP19_IP3_PKT" , 0x1070102646200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP20_IP3_PKT" , 0x1070102846200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP21_IP3_PKT" , 0x1070102a46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP22_IP3_PKT" , 0x1070102c46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP23_IP3_PKT" , 0x1070102e46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP24_IP3_PKT" , 0x1070103046200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP25_IP3_PKT" , 0x1070103246200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP26_IP3_PKT" , 0x1070103446200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP27_IP3_PKT" , 0x1070103646200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP28_IP3_PKT" , 0x1070103846200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP29_IP3_PKT" , 0x1070103a46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP30_IP3_PKT" , 0x1070103c46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP31_IP3_PKT" , 0x1070103e46200ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
- {"CIU2_RAW_PP0_IP3_RML" , 0x1070100042200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP1_IP3_RML" , 0x1070100242200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP2_IP3_RML" , 0x1070100442200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP3_IP3_RML" , 0x1070100642200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP4_IP3_RML" , 0x1070100842200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP5_IP3_RML" , 0x1070100a42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP6_IP3_RML" , 0x1070100c42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP7_IP3_RML" , 0x1070100e42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP8_IP3_RML" , 0x1070101042200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP9_IP3_RML" , 0x1070101242200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP10_IP3_RML" , 0x1070101442200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP11_IP3_RML" , 0x1070101642200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP12_IP3_RML" , 0x1070101842200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP13_IP3_RML" , 0x1070101a42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP14_IP3_RML" , 0x1070101c42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP15_IP3_RML" , 0x1070101e42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP16_IP3_RML" , 0x1070102042200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP17_IP3_RML" , 0x1070102242200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP18_IP3_RML" , 0x1070102442200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP19_IP3_RML" , 0x1070102642200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP20_IP3_RML" , 0x1070102842200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP21_IP3_RML" , 0x1070102a42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP22_IP3_RML" , 0x1070102c42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP23_IP3_RML" , 0x1070102e42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP24_IP3_RML" , 0x1070103042200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP25_IP3_RML" , 0x1070103242200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP26_IP3_RML" , 0x1070103442200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP27_IP3_RML" , 0x1070103642200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP28_IP3_RML" , 0x1070103842200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP29_IP3_RML" , 0x1070103a42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP30_IP3_RML" , 0x1070103c42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP31_IP3_RML" , 0x1070103e42200ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
- {"CIU2_RAW_PP0_IP3_WDOG" , 0x1070100041200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP1_IP3_WDOG" , 0x1070100241200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP2_IP3_WDOG" , 0x1070100441200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP3_IP3_WDOG" , 0x1070100641200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP4_IP3_WDOG" , 0x1070100841200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP5_IP3_WDOG" , 0x1070100a41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP6_IP3_WDOG" , 0x1070100c41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP7_IP3_WDOG" , 0x1070100e41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP8_IP3_WDOG" , 0x1070101041200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP9_IP3_WDOG" , 0x1070101241200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP10_IP3_WDOG" , 0x1070101441200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP11_IP3_WDOG" , 0x1070101641200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP12_IP3_WDOG" , 0x1070101841200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP13_IP3_WDOG" , 0x1070101a41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP14_IP3_WDOG" , 0x1070101c41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP15_IP3_WDOG" , 0x1070101e41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP16_IP3_WDOG" , 0x1070102041200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP17_IP3_WDOG" , 0x1070102241200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP18_IP3_WDOG" , 0x1070102441200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP19_IP3_WDOG" , 0x1070102641200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP20_IP3_WDOG" , 0x1070102841200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP21_IP3_WDOG" , 0x1070102a41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP22_IP3_WDOG" , 0x1070102c41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP23_IP3_WDOG" , 0x1070102e41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP24_IP3_WDOG" , 0x1070103041200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP25_IP3_WDOG" , 0x1070103241200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP26_IP3_WDOG" , 0x1070103441200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP27_IP3_WDOG" , 0x1070103641200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP28_IP3_WDOG" , 0x1070103841200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP29_IP3_WDOG" , 0x1070103a41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP30_IP3_WDOG" , 0x1070103c41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP31_IP3_WDOG" , 0x1070103e41200ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
- {"CIU2_RAW_PP0_IP3_WRKQ" , 0x1070100040200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP1_IP3_WRKQ" , 0x1070100240200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP2_IP3_WRKQ" , 0x1070100440200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP3_IP3_WRKQ" , 0x1070100640200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP4_IP3_WRKQ" , 0x1070100840200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP5_IP3_WRKQ" , 0x1070100a40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP6_IP3_WRKQ" , 0x1070100c40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP7_IP3_WRKQ" , 0x1070100e40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP8_IP3_WRKQ" , 0x1070101040200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP9_IP3_WRKQ" , 0x1070101240200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP10_IP3_WRKQ" , 0x1070101440200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP11_IP3_WRKQ" , 0x1070101640200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP12_IP3_WRKQ" , 0x1070101840200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP13_IP3_WRKQ" , 0x1070101a40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP14_IP3_WRKQ" , 0x1070101c40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP15_IP3_WRKQ" , 0x1070101e40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP16_IP3_WRKQ" , 0x1070102040200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP17_IP3_WRKQ" , 0x1070102240200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP18_IP3_WRKQ" , 0x1070102440200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP19_IP3_WRKQ" , 0x1070102640200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP20_IP3_WRKQ" , 0x1070102840200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP21_IP3_WRKQ" , 0x1070102a40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP22_IP3_WRKQ" , 0x1070102c40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP23_IP3_WRKQ" , 0x1070102e40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP24_IP3_WRKQ" , 0x1070103040200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP25_IP3_WRKQ" , 0x1070103240200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP26_IP3_WRKQ" , 0x1070103440200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP27_IP3_WRKQ" , 0x1070103640200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP28_IP3_WRKQ" , 0x1070103840200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP29_IP3_WRKQ" , 0x1070103a40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP30_IP3_WRKQ" , 0x1070103c40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP31_IP3_WRKQ" , 0x1070103e40200ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
- {"CIU2_RAW_PP0_IP4_GPIO" , 0x1070100047400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP1_IP4_GPIO" , 0x1070100247400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP2_IP4_GPIO" , 0x1070100447400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP3_IP4_GPIO" , 0x1070100647400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP4_IP4_GPIO" , 0x1070100847400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP5_IP4_GPIO" , 0x1070100a47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP6_IP4_GPIO" , 0x1070100c47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP7_IP4_GPIO" , 0x1070100e47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP8_IP4_GPIO" , 0x1070101047400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP9_IP4_GPIO" , 0x1070101247400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP10_IP4_GPIO" , 0x1070101447400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP11_IP4_GPIO" , 0x1070101647400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP12_IP4_GPIO" , 0x1070101847400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP13_IP4_GPIO" , 0x1070101a47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP14_IP4_GPIO" , 0x1070101c47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP15_IP4_GPIO" , 0x1070101e47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP16_IP4_GPIO" , 0x1070102047400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP17_IP4_GPIO" , 0x1070102247400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP18_IP4_GPIO" , 0x1070102447400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP19_IP4_GPIO" , 0x1070102647400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP20_IP4_GPIO" , 0x1070102847400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP21_IP4_GPIO" , 0x1070102a47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP22_IP4_GPIO" , 0x1070102c47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP23_IP4_GPIO" , 0x1070102e47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP24_IP4_GPIO" , 0x1070103047400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP25_IP4_GPIO" , 0x1070103247400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP26_IP4_GPIO" , 0x1070103447400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP27_IP4_GPIO" , 0x1070103647400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP28_IP4_GPIO" , 0x1070103847400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP29_IP4_GPIO" , 0x1070103a47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP30_IP4_GPIO" , 0x1070103c47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP31_IP4_GPIO" , 0x1070103e47400ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
- {"CIU2_RAW_PP0_IP4_IO" , 0x1070100044400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP1_IP4_IO" , 0x1070100244400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP2_IP4_IO" , 0x1070100444400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP3_IP4_IO" , 0x1070100644400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP4_IP4_IO" , 0x1070100844400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP5_IP4_IO" , 0x1070100a44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP6_IP4_IO" , 0x1070100c44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP7_IP4_IO" , 0x1070100e44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP8_IP4_IO" , 0x1070101044400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP9_IP4_IO" , 0x1070101244400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP10_IP4_IO" , 0x1070101444400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP11_IP4_IO" , 0x1070101644400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP12_IP4_IO" , 0x1070101844400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP13_IP4_IO" , 0x1070101a44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP14_IP4_IO" , 0x1070101c44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP15_IP4_IO" , 0x1070101e44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP16_IP4_IO" , 0x1070102044400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP17_IP4_IO" , 0x1070102244400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP18_IP4_IO" , 0x1070102444400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP19_IP4_IO" , 0x1070102644400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP20_IP4_IO" , 0x1070102844400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP21_IP4_IO" , 0x1070102a44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP22_IP4_IO" , 0x1070102c44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP23_IP4_IO" , 0x1070102e44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP24_IP4_IO" , 0x1070103044400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP25_IP4_IO" , 0x1070103244400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP26_IP4_IO" , 0x1070103444400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP27_IP4_IO" , 0x1070103644400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP28_IP4_IO" , 0x1070103844400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP29_IP4_IO" , 0x1070103a44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP30_IP4_IO" , 0x1070103c44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP31_IP4_IO" , 0x1070103e44400ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
- {"CIU2_RAW_PP0_IP4_MEM" , 0x1070100045400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP1_IP4_MEM" , 0x1070100245400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP2_IP4_MEM" , 0x1070100445400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP3_IP4_MEM" , 0x1070100645400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP4_IP4_MEM" , 0x1070100845400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP5_IP4_MEM" , 0x1070100a45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP6_IP4_MEM" , 0x1070100c45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP7_IP4_MEM" , 0x1070100e45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP8_IP4_MEM" , 0x1070101045400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP9_IP4_MEM" , 0x1070101245400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP10_IP4_MEM" , 0x1070101445400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP11_IP4_MEM" , 0x1070101645400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP12_IP4_MEM" , 0x1070101845400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP13_IP4_MEM" , 0x1070101a45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP14_IP4_MEM" , 0x1070101c45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP15_IP4_MEM" , 0x1070101e45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP16_IP4_MEM" , 0x1070102045400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP17_IP4_MEM" , 0x1070102245400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP18_IP4_MEM" , 0x1070102445400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP19_IP4_MEM" , 0x1070102645400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP20_IP4_MEM" , 0x1070102845400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP21_IP4_MEM" , 0x1070102a45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP22_IP4_MEM" , 0x1070102c45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP23_IP4_MEM" , 0x1070102e45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP24_IP4_MEM" , 0x1070103045400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP25_IP4_MEM" , 0x1070103245400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP26_IP4_MEM" , 0x1070103445400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP27_IP4_MEM" , 0x1070103645400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP28_IP4_MEM" , 0x1070103845400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP29_IP4_MEM" , 0x1070103a45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP30_IP4_MEM" , 0x1070103c45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP31_IP4_MEM" , 0x1070103e45400ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
- {"CIU2_RAW_PP0_IP4_MIO" , 0x1070100043400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP1_IP4_MIO" , 0x1070100243400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP2_IP4_MIO" , 0x1070100443400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP3_IP4_MIO" , 0x1070100643400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP4_IP4_MIO" , 0x1070100843400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP5_IP4_MIO" , 0x1070100a43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP6_IP4_MIO" , 0x1070100c43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP7_IP4_MIO" , 0x1070100e43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP8_IP4_MIO" , 0x1070101043400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP9_IP4_MIO" , 0x1070101243400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP10_IP4_MIO" , 0x1070101443400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP11_IP4_MIO" , 0x1070101643400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP12_IP4_MIO" , 0x1070101843400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP13_IP4_MIO" , 0x1070101a43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP14_IP4_MIO" , 0x1070101c43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP15_IP4_MIO" , 0x1070101e43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP16_IP4_MIO" , 0x1070102043400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP17_IP4_MIO" , 0x1070102243400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP18_IP4_MIO" , 0x1070102443400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP19_IP4_MIO" , 0x1070102643400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP20_IP4_MIO" , 0x1070102843400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP21_IP4_MIO" , 0x1070102a43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP22_IP4_MIO" , 0x1070102c43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP23_IP4_MIO" , 0x1070102e43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP24_IP4_MIO" , 0x1070103043400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP25_IP4_MIO" , 0x1070103243400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP26_IP4_MIO" , 0x1070103443400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP27_IP4_MIO" , 0x1070103643400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP28_IP4_MIO" , 0x1070103843400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP29_IP4_MIO" , 0x1070103a43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP30_IP4_MIO" , 0x1070103c43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP31_IP4_MIO" , 0x1070103e43400ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
- {"CIU2_RAW_PP0_IP4_PKT" , 0x1070100046400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP1_IP4_PKT" , 0x1070100246400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP2_IP4_PKT" , 0x1070100446400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP3_IP4_PKT" , 0x1070100646400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP4_IP4_PKT" , 0x1070100846400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP5_IP4_PKT" , 0x1070100a46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP6_IP4_PKT" , 0x1070100c46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP7_IP4_PKT" , 0x1070100e46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP8_IP4_PKT" , 0x1070101046400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP9_IP4_PKT" , 0x1070101246400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP10_IP4_PKT" , 0x1070101446400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP11_IP4_PKT" , 0x1070101646400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP12_IP4_PKT" , 0x1070101846400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP13_IP4_PKT" , 0x1070101a46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP14_IP4_PKT" , 0x1070101c46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP15_IP4_PKT" , 0x1070101e46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP16_IP4_PKT" , 0x1070102046400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP17_IP4_PKT" , 0x1070102246400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP18_IP4_PKT" , 0x1070102446400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP19_IP4_PKT" , 0x1070102646400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP20_IP4_PKT" , 0x1070102846400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP21_IP4_PKT" , 0x1070102a46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP22_IP4_PKT" , 0x1070102c46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP23_IP4_PKT" , 0x1070102e46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP24_IP4_PKT" , 0x1070103046400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP25_IP4_PKT" , 0x1070103246400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP26_IP4_PKT" , 0x1070103446400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP27_IP4_PKT" , 0x1070103646400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP28_IP4_PKT" , 0x1070103846400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP29_IP4_PKT" , 0x1070103a46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP30_IP4_PKT" , 0x1070103c46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP31_IP4_PKT" , 0x1070103e46400ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
- {"CIU2_RAW_PP0_IP4_RML" , 0x1070100042400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP1_IP4_RML" , 0x1070100242400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP2_IP4_RML" , 0x1070100442400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP3_IP4_RML" , 0x1070100642400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP4_IP4_RML" , 0x1070100842400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP5_IP4_RML" , 0x1070100a42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP6_IP4_RML" , 0x1070100c42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP7_IP4_RML" , 0x1070100e42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP8_IP4_RML" , 0x1070101042400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP9_IP4_RML" , 0x1070101242400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP10_IP4_RML" , 0x1070101442400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP11_IP4_RML" , 0x1070101642400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP12_IP4_RML" , 0x1070101842400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP13_IP4_RML" , 0x1070101a42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP14_IP4_RML" , 0x1070101c42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP15_IP4_RML" , 0x1070101e42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP16_IP4_RML" , 0x1070102042400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP17_IP4_RML" , 0x1070102242400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP18_IP4_RML" , 0x1070102442400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP19_IP4_RML" , 0x1070102642400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP20_IP4_RML" , 0x1070102842400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP21_IP4_RML" , 0x1070102a42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP22_IP4_RML" , 0x1070102c42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP23_IP4_RML" , 0x1070102e42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP24_IP4_RML" , 0x1070103042400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP25_IP4_RML" , 0x1070103242400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP26_IP4_RML" , 0x1070103442400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP27_IP4_RML" , 0x1070103642400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP28_IP4_RML" , 0x1070103842400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP29_IP4_RML" , 0x1070103a42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP30_IP4_RML" , 0x1070103c42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP31_IP4_RML" , 0x1070103e42400ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
- {"CIU2_RAW_PP0_IP4_WDOG" , 0x1070100041400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP1_IP4_WDOG" , 0x1070100241400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP2_IP4_WDOG" , 0x1070100441400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP3_IP4_WDOG" , 0x1070100641400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP4_IP4_WDOG" , 0x1070100841400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP5_IP4_WDOG" , 0x1070100a41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP6_IP4_WDOG" , 0x1070100c41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP7_IP4_WDOG" , 0x1070100e41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP8_IP4_WDOG" , 0x1070101041400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP9_IP4_WDOG" , 0x1070101241400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP10_IP4_WDOG" , 0x1070101441400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP11_IP4_WDOG" , 0x1070101641400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP12_IP4_WDOG" , 0x1070101841400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP13_IP4_WDOG" , 0x1070101a41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP14_IP4_WDOG" , 0x1070101c41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP15_IP4_WDOG" , 0x1070101e41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP16_IP4_WDOG" , 0x1070102041400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP17_IP4_WDOG" , 0x1070102241400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP18_IP4_WDOG" , 0x1070102441400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP19_IP4_WDOG" , 0x1070102641400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP20_IP4_WDOG" , 0x1070102841400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP21_IP4_WDOG" , 0x1070102a41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP22_IP4_WDOG" , 0x1070102c41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP23_IP4_WDOG" , 0x1070102e41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP24_IP4_WDOG" , 0x1070103041400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP25_IP4_WDOG" , 0x1070103241400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP26_IP4_WDOG" , 0x1070103441400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP27_IP4_WDOG" , 0x1070103641400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP28_IP4_WDOG" , 0x1070103841400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP29_IP4_WDOG" , 0x1070103a41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP30_IP4_WDOG" , 0x1070103c41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP31_IP4_WDOG" , 0x1070103e41400ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
- {"CIU2_RAW_PP0_IP4_WRKQ" , 0x1070100040400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP1_IP4_WRKQ" , 0x1070100240400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP2_IP4_WRKQ" , 0x1070100440400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP3_IP4_WRKQ" , 0x1070100640400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP4_IP4_WRKQ" , 0x1070100840400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP5_IP4_WRKQ" , 0x1070100a40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP6_IP4_WRKQ" , 0x1070100c40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP7_IP4_WRKQ" , 0x1070100e40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP8_IP4_WRKQ" , 0x1070101040400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP9_IP4_WRKQ" , 0x1070101240400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP10_IP4_WRKQ" , 0x1070101440400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP11_IP4_WRKQ" , 0x1070101640400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP12_IP4_WRKQ" , 0x1070101840400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP13_IP4_WRKQ" , 0x1070101a40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP14_IP4_WRKQ" , 0x1070101c40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP15_IP4_WRKQ" , 0x1070101e40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP16_IP4_WRKQ" , 0x1070102040400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP17_IP4_WRKQ" , 0x1070102240400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP18_IP4_WRKQ" , 0x1070102440400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP19_IP4_WRKQ" , 0x1070102640400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP20_IP4_WRKQ" , 0x1070102840400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP21_IP4_WRKQ" , 0x1070102a40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP22_IP4_WRKQ" , 0x1070102c40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP23_IP4_WRKQ" , 0x1070102e40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP24_IP4_WRKQ" , 0x1070103040400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP25_IP4_WRKQ" , 0x1070103240400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP26_IP4_WRKQ" , 0x1070103440400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP27_IP4_WRKQ" , 0x1070103640400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP28_IP4_WRKQ" , 0x1070103840400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP29_IP4_WRKQ" , 0x1070103a40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP30_IP4_WRKQ" , 0x1070103c40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_RAW_PP31_IP4_WRKQ" , 0x1070103e40400ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
- {"CIU2_SRC_IO0_INT_GPIO" , 0x1070108087800ull, CVMX_CSR_DB_TYPE_NCB, 64, 225},
- {"CIU2_SRC_IO1_INT_GPIO" , 0x1070108287800ull, CVMX_CSR_DB_TYPE_NCB, 64, 225},
- {"CIU2_SRC_IO0_INT_IO" , 0x1070108084800ull, CVMX_CSR_DB_TYPE_NCB, 64, 226},
- {"CIU2_SRC_IO1_INT_IO" , 0x1070108284800ull, CVMX_CSR_DB_TYPE_NCB, 64, 226},
- {"CIU2_SRC_IO0_INT_MBOX" , 0x1070108088800ull, CVMX_CSR_DB_TYPE_NCB, 64, 227},
- {"CIU2_SRC_IO1_INT_MBOX" , 0x1070108288800ull, CVMX_CSR_DB_TYPE_NCB, 64, 227},
- {"CIU2_SRC_IO0_INT_MEM" , 0x1070108085800ull, CVMX_CSR_DB_TYPE_NCB, 64, 228},
- {"CIU2_SRC_IO1_INT_MEM" , 0x1070108285800ull, CVMX_CSR_DB_TYPE_NCB, 64, 228},
- {"CIU2_SRC_IO0_INT_MIO" , 0x1070108083800ull, CVMX_CSR_DB_TYPE_NCB, 64, 229},
- {"CIU2_SRC_IO1_INT_MIO" , 0x1070108283800ull, CVMX_CSR_DB_TYPE_NCB, 64, 229},
- {"CIU2_SRC_IO0_INT_PKT" , 0x1070108086800ull, CVMX_CSR_DB_TYPE_NCB, 64, 230},
- {"CIU2_SRC_IO1_INT_PKT" , 0x1070108286800ull, CVMX_CSR_DB_TYPE_NCB, 64, 230},
- {"CIU2_SRC_IO0_INT_RML" , 0x1070108082800ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"CIU2_SRC_IO1_INT_RML" , 0x1070108282800ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
- {"CIU2_SRC_IO0_INT_WDOG" , 0x1070108081800ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"CIU2_SRC_IO1_INT_WDOG" , 0x1070108281800ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
- {"CIU2_SRC_IO0_INT_WRKQ" , 0x1070108080800ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"CIU2_SRC_IO1_INT_WRKQ" , 0x1070108280800ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
- {"CIU2_SRC_PP0_IP2_GPIO" , 0x1070100087000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP1_IP2_GPIO" , 0x1070100287000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP2_IP2_GPIO" , 0x1070100487000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP3_IP2_GPIO" , 0x1070100687000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP4_IP2_GPIO" , 0x1070100887000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP5_IP2_GPIO" , 0x1070100a87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP6_IP2_GPIO" , 0x1070100c87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP7_IP2_GPIO" , 0x1070100e87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP8_IP2_GPIO" , 0x1070101087000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP9_IP2_GPIO" , 0x1070101287000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP10_IP2_GPIO" , 0x1070101487000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP11_IP2_GPIO" , 0x1070101687000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP12_IP2_GPIO" , 0x1070101887000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP13_IP2_GPIO" , 0x1070101a87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP14_IP2_GPIO" , 0x1070101c87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP15_IP2_GPIO" , 0x1070101e87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP16_IP2_GPIO" , 0x1070102087000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP17_IP2_GPIO" , 0x1070102287000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP18_IP2_GPIO" , 0x1070102487000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP19_IP2_GPIO" , 0x1070102687000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP20_IP2_GPIO" , 0x1070102887000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP21_IP2_GPIO" , 0x1070102a87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP22_IP2_GPIO" , 0x1070102c87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP23_IP2_GPIO" , 0x1070102e87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP24_IP2_GPIO" , 0x1070103087000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP25_IP2_GPIO" , 0x1070103287000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP26_IP2_GPIO" , 0x1070103487000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP27_IP2_GPIO" , 0x1070103687000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP28_IP2_GPIO" , 0x1070103887000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP29_IP2_GPIO" , 0x1070103a87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP30_IP2_GPIO" , 0x1070103c87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP31_IP2_GPIO" , 0x1070103e87000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
- {"CIU2_SRC_PP0_IP2_IO" , 0x1070100084000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP1_IP2_IO" , 0x1070100284000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP2_IP2_IO" , 0x1070100484000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP3_IP2_IO" , 0x1070100684000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP4_IP2_IO" , 0x1070100884000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP5_IP2_IO" , 0x1070100a84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP6_IP2_IO" , 0x1070100c84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP7_IP2_IO" , 0x1070100e84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP8_IP2_IO" , 0x1070101084000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP9_IP2_IO" , 0x1070101284000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP10_IP2_IO" , 0x1070101484000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP11_IP2_IO" , 0x1070101684000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP12_IP2_IO" , 0x1070101884000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP13_IP2_IO" , 0x1070101a84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP14_IP2_IO" , 0x1070101c84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP15_IP2_IO" , 0x1070101e84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP16_IP2_IO" , 0x1070102084000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP17_IP2_IO" , 0x1070102284000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP18_IP2_IO" , 0x1070102484000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP19_IP2_IO" , 0x1070102684000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP20_IP2_IO" , 0x1070102884000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP21_IP2_IO" , 0x1070102a84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP22_IP2_IO" , 0x1070102c84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP23_IP2_IO" , 0x1070102e84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP24_IP2_IO" , 0x1070103084000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP25_IP2_IO" , 0x1070103284000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP26_IP2_IO" , 0x1070103484000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP27_IP2_IO" , 0x1070103684000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP28_IP2_IO" , 0x1070103884000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP29_IP2_IO" , 0x1070103a84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP30_IP2_IO" , 0x1070103c84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP31_IP2_IO" , 0x1070103e84000ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
- {"CIU2_SRC_PP0_IP2_MBOX" , 0x1070100088000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP1_IP2_MBOX" , 0x1070100288000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP2_IP2_MBOX" , 0x1070100488000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP3_IP2_MBOX" , 0x1070100688000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP4_IP2_MBOX" , 0x1070100888000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP5_IP2_MBOX" , 0x1070100a88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP6_IP2_MBOX" , 0x1070100c88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP7_IP2_MBOX" , 0x1070100e88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP8_IP2_MBOX" , 0x1070101088000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP9_IP2_MBOX" , 0x1070101288000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP10_IP2_MBOX" , 0x1070101488000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP11_IP2_MBOX" , 0x1070101688000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP12_IP2_MBOX" , 0x1070101888000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP13_IP2_MBOX" , 0x1070101a88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP14_IP2_MBOX" , 0x1070101c88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP15_IP2_MBOX" , 0x1070101e88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP16_IP2_MBOX" , 0x1070102088000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP17_IP2_MBOX" , 0x1070102288000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP18_IP2_MBOX" , 0x1070102488000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP19_IP2_MBOX" , 0x1070102688000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP20_IP2_MBOX" , 0x1070102888000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP21_IP2_MBOX" , 0x1070102a88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP22_IP2_MBOX" , 0x1070102c88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP23_IP2_MBOX" , 0x1070102e88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP24_IP2_MBOX" , 0x1070103088000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP25_IP2_MBOX" , 0x1070103288000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP26_IP2_MBOX" , 0x1070103488000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP27_IP2_MBOX" , 0x1070103688000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP28_IP2_MBOX" , 0x1070103888000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP29_IP2_MBOX" , 0x1070103a88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP30_IP2_MBOX" , 0x1070103c88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP31_IP2_MBOX" , 0x1070103e88000ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
- {"CIU2_SRC_PP0_IP2_MEM" , 0x1070100085000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP1_IP2_MEM" , 0x1070100285000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP2_IP2_MEM" , 0x1070100485000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP3_IP2_MEM" , 0x1070100685000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP4_IP2_MEM" , 0x1070100885000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP5_IP2_MEM" , 0x1070100a85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP6_IP2_MEM" , 0x1070100c85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP7_IP2_MEM" , 0x1070100e85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP8_IP2_MEM" , 0x1070101085000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP9_IP2_MEM" , 0x1070101285000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP10_IP2_MEM" , 0x1070101485000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP11_IP2_MEM" , 0x1070101685000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP12_IP2_MEM" , 0x1070101885000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP13_IP2_MEM" , 0x1070101a85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP14_IP2_MEM" , 0x1070101c85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP15_IP2_MEM" , 0x1070101e85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP16_IP2_MEM" , 0x1070102085000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP17_IP2_MEM" , 0x1070102285000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP18_IP2_MEM" , 0x1070102485000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP19_IP2_MEM" , 0x1070102685000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP20_IP2_MEM" , 0x1070102885000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP21_IP2_MEM" , 0x1070102a85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP22_IP2_MEM" , 0x1070102c85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP23_IP2_MEM" , 0x1070102e85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP24_IP2_MEM" , 0x1070103085000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP25_IP2_MEM" , 0x1070103285000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP26_IP2_MEM" , 0x1070103485000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP27_IP2_MEM" , 0x1070103685000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP28_IP2_MEM" , 0x1070103885000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP29_IP2_MEM" , 0x1070103a85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP30_IP2_MEM" , 0x1070103c85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP31_IP2_MEM" , 0x1070103e85000ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
- {"CIU2_SRC_PP0_IP2_MIO" , 0x1070100083000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP1_IP2_MIO" , 0x1070100283000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP2_IP2_MIO" , 0x1070100483000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP3_IP2_MIO" , 0x1070100683000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP4_IP2_MIO" , 0x1070100883000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP5_IP2_MIO" , 0x1070100a83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP6_IP2_MIO" , 0x1070100c83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP7_IP2_MIO" , 0x1070100e83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP8_IP2_MIO" , 0x1070101083000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP9_IP2_MIO" , 0x1070101283000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP10_IP2_MIO" , 0x1070101483000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP11_IP2_MIO" , 0x1070101683000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP12_IP2_MIO" , 0x1070101883000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP13_IP2_MIO" , 0x1070101a83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP14_IP2_MIO" , 0x1070101c83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP15_IP2_MIO" , 0x1070101e83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP16_IP2_MIO" , 0x1070102083000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP17_IP2_MIO" , 0x1070102283000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP18_IP2_MIO" , 0x1070102483000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP19_IP2_MIO" , 0x1070102683000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP20_IP2_MIO" , 0x1070102883000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP21_IP2_MIO" , 0x1070102a83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP22_IP2_MIO" , 0x1070102c83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP23_IP2_MIO" , 0x1070102e83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP24_IP2_MIO" , 0x1070103083000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP25_IP2_MIO" , 0x1070103283000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP26_IP2_MIO" , 0x1070103483000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP27_IP2_MIO" , 0x1070103683000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP28_IP2_MIO" , 0x1070103883000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP29_IP2_MIO" , 0x1070103a83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP30_IP2_MIO" , 0x1070103c83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP31_IP2_MIO" , 0x1070103e83000ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
- {"CIU2_SRC_PP0_IP2_PKT" , 0x1070100086000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP1_IP2_PKT" , 0x1070100286000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP2_IP2_PKT" , 0x1070100486000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP3_IP2_PKT" , 0x1070100686000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP4_IP2_PKT" , 0x1070100886000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP5_IP2_PKT" , 0x1070100a86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP6_IP2_PKT" , 0x1070100c86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP7_IP2_PKT" , 0x1070100e86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP8_IP2_PKT" , 0x1070101086000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP9_IP2_PKT" , 0x1070101286000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP10_IP2_PKT" , 0x1070101486000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP11_IP2_PKT" , 0x1070101686000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP12_IP2_PKT" , 0x1070101886000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP13_IP2_PKT" , 0x1070101a86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP14_IP2_PKT" , 0x1070101c86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP15_IP2_PKT" , 0x1070101e86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP16_IP2_PKT" , 0x1070102086000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP17_IP2_PKT" , 0x1070102286000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP18_IP2_PKT" , 0x1070102486000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP19_IP2_PKT" , 0x1070102686000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP20_IP2_PKT" , 0x1070102886000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP21_IP2_PKT" , 0x1070102a86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP22_IP2_PKT" , 0x1070102c86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP23_IP2_PKT" , 0x1070102e86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP24_IP2_PKT" , 0x1070103086000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP25_IP2_PKT" , 0x1070103286000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP26_IP2_PKT" , 0x1070103486000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP27_IP2_PKT" , 0x1070103686000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP28_IP2_PKT" , 0x1070103886000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP29_IP2_PKT" , 0x1070103a86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP30_IP2_PKT" , 0x1070103c86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP31_IP2_PKT" , 0x1070103e86000ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
- {"CIU2_SRC_PP0_IP2_RML" , 0x1070100082000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP1_IP2_RML" , 0x1070100282000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP2_IP2_RML" , 0x1070100482000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP3_IP2_RML" , 0x1070100682000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP4_IP2_RML" , 0x1070100882000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP5_IP2_RML" , 0x1070100a82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP6_IP2_RML" , 0x1070100c82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP7_IP2_RML" , 0x1070100e82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP8_IP2_RML" , 0x1070101082000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP9_IP2_RML" , 0x1070101282000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP10_IP2_RML" , 0x1070101482000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP11_IP2_RML" , 0x1070101682000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP12_IP2_RML" , 0x1070101882000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP13_IP2_RML" , 0x1070101a82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP14_IP2_RML" , 0x1070101c82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP15_IP2_RML" , 0x1070101e82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP16_IP2_RML" , 0x1070102082000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP17_IP2_RML" , 0x1070102282000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP18_IP2_RML" , 0x1070102482000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP19_IP2_RML" , 0x1070102682000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP20_IP2_RML" , 0x1070102882000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP21_IP2_RML" , 0x1070102a82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP22_IP2_RML" , 0x1070102c82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP23_IP2_RML" , 0x1070102e82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP24_IP2_RML" , 0x1070103082000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP25_IP2_RML" , 0x1070103282000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP26_IP2_RML" , 0x1070103482000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP27_IP2_RML" , 0x1070103682000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP28_IP2_RML" , 0x1070103882000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP29_IP2_RML" , 0x1070103a82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP30_IP2_RML" , 0x1070103c82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP31_IP2_RML" , 0x1070103e82000ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
- {"CIU2_SRC_PP0_IP2_WDOG" , 0x1070100081000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP1_IP2_WDOG" , 0x1070100281000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP2_IP2_WDOG" , 0x1070100481000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP3_IP2_WDOG" , 0x1070100681000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP4_IP2_WDOG" , 0x1070100881000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP5_IP2_WDOG" , 0x1070100a81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP6_IP2_WDOG" , 0x1070100c81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP7_IP2_WDOG" , 0x1070100e81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP8_IP2_WDOG" , 0x1070101081000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP9_IP2_WDOG" , 0x1070101281000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP10_IP2_WDOG" , 0x1070101481000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP11_IP2_WDOG" , 0x1070101681000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP12_IP2_WDOG" , 0x1070101881000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP13_IP2_WDOG" , 0x1070101a81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP14_IP2_WDOG" , 0x1070101c81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP15_IP2_WDOG" , 0x1070101e81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP16_IP2_WDOG" , 0x1070102081000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP17_IP2_WDOG" , 0x1070102281000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP18_IP2_WDOG" , 0x1070102481000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP19_IP2_WDOG" , 0x1070102681000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP20_IP2_WDOG" , 0x1070102881000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP21_IP2_WDOG" , 0x1070102a81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP22_IP2_WDOG" , 0x1070102c81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP23_IP2_WDOG" , 0x1070102e81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP24_IP2_WDOG" , 0x1070103081000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP25_IP2_WDOG" , 0x1070103281000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP26_IP2_WDOG" , 0x1070103481000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP27_IP2_WDOG" , 0x1070103681000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP28_IP2_WDOG" , 0x1070103881000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP29_IP2_WDOG" , 0x1070103a81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP30_IP2_WDOG" , 0x1070103c81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP31_IP2_WDOG" , 0x1070103e81000ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
- {"CIU2_SRC_PP0_IP2_WRKQ" , 0x1070100080000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP1_IP2_WRKQ" , 0x1070100280000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP2_IP2_WRKQ" , 0x1070100480000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP3_IP2_WRKQ" , 0x1070100680000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP4_IP2_WRKQ" , 0x1070100880000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP5_IP2_WRKQ" , 0x1070100a80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP6_IP2_WRKQ" , 0x1070100c80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP7_IP2_WRKQ" , 0x1070100e80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP8_IP2_WRKQ" , 0x1070101080000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP9_IP2_WRKQ" , 0x1070101280000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP10_IP2_WRKQ" , 0x1070101480000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP11_IP2_WRKQ" , 0x1070101680000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP12_IP2_WRKQ" , 0x1070101880000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP13_IP2_WRKQ" , 0x1070101a80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP14_IP2_WRKQ" , 0x1070101c80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP15_IP2_WRKQ" , 0x1070101e80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP16_IP2_WRKQ" , 0x1070102080000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP17_IP2_WRKQ" , 0x1070102280000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP18_IP2_WRKQ" , 0x1070102480000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP19_IP2_WRKQ" , 0x1070102680000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP20_IP2_WRKQ" , 0x1070102880000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP21_IP2_WRKQ" , 0x1070102a80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP22_IP2_WRKQ" , 0x1070102c80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP23_IP2_WRKQ" , 0x1070102e80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP24_IP2_WRKQ" , 0x1070103080000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP25_IP2_WRKQ" , 0x1070103280000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP26_IP2_WRKQ" , 0x1070103480000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP27_IP2_WRKQ" , 0x1070103680000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP28_IP2_WRKQ" , 0x1070103880000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP29_IP2_WRKQ" , 0x1070103a80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP30_IP2_WRKQ" , 0x1070103c80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP31_IP2_WRKQ" , 0x1070103e80000ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
- {"CIU2_SRC_PP0_IP3_GPIO" , 0x1070100087200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP1_IP3_GPIO" , 0x1070100287200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP2_IP3_GPIO" , 0x1070100487200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP3_IP3_GPIO" , 0x1070100687200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP4_IP3_GPIO" , 0x1070100887200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP5_IP3_GPIO" , 0x1070100a87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP6_IP3_GPIO" , 0x1070100c87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP7_IP3_GPIO" , 0x1070100e87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP8_IP3_GPIO" , 0x1070101087200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP9_IP3_GPIO" , 0x1070101287200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP10_IP3_GPIO" , 0x1070101487200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP11_IP3_GPIO" , 0x1070101687200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP12_IP3_GPIO" , 0x1070101887200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP13_IP3_GPIO" , 0x1070101a87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP14_IP3_GPIO" , 0x1070101c87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP15_IP3_GPIO" , 0x1070101e87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP16_IP3_GPIO" , 0x1070102087200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP17_IP3_GPIO" , 0x1070102287200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP18_IP3_GPIO" , 0x1070102487200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP19_IP3_GPIO" , 0x1070102687200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP20_IP3_GPIO" , 0x1070102887200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP21_IP3_GPIO" , 0x1070102a87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP22_IP3_GPIO" , 0x1070102c87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP23_IP3_GPIO" , 0x1070102e87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP24_IP3_GPIO" , 0x1070103087200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP25_IP3_GPIO" , 0x1070103287200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP26_IP3_GPIO" , 0x1070103487200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP27_IP3_GPIO" , 0x1070103687200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP28_IP3_GPIO" , 0x1070103887200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP29_IP3_GPIO" , 0x1070103a87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP30_IP3_GPIO" , 0x1070103c87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP31_IP3_GPIO" , 0x1070103e87200ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
- {"CIU2_SRC_PP0_IP3_IO" , 0x1070100084200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP1_IP3_IO" , 0x1070100284200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP2_IP3_IO" , 0x1070100484200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP3_IP3_IO" , 0x1070100684200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP4_IP3_IO" , 0x1070100884200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP5_IP3_IO" , 0x1070100a84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP6_IP3_IO" , 0x1070100c84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP7_IP3_IO" , 0x1070100e84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP8_IP3_IO" , 0x1070101084200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP9_IP3_IO" , 0x1070101284200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP10_IP3_IO" , 0x1070101484200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP11_IP3_IO" , 0x1070101684200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP12_IP3_IO" , 0x1070101884200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP13_IP3_IO" , 0x1070101a84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP14_IP3_IO" , 0x1070101c84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP15_IP3_IO" , 0x1070101e84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP16_IP3_IO" , 0x1070102084200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP17_IP3_IO" , 0x1070102284200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP18_IP3_IO" , 0x1070102484200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP19_IP3_IO" , 0x1070102684200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP20_IP3_IO" , 0x1070102884200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP21_IP3_IO" , 0x1070102a84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP22_IP3_IO" , 0x1070102c84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP23_IP3_IO" , 0x1070102e84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP24_IP3_IO" , 0x1070103084200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP25_IP3_IO" , 0x1070103284200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP26_IP3_IO" , 0x1070103484200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP27_IP3_IO" , 0x1070103684200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP28_IP3_IO" , 0x1070103884200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP29_IP3_IO" , 0x1070103a84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP30_IP3_IO" , 0x1070103c84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP31_IP3_IO" , 0x1070103e84200ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
- {"CIU2_SRC_PP0_IP3_MBOX" , 0x1070100088200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP1_IP3_MBOX" , 0x1070100288200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP2_IP3_MBOX" , 0x1070100488200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP3_IP3_MBOX" , 0x1070100688200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP4_IP3_MBOX" , 0x1070100888200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP5_IP3_MBOX" , 0x1070100a88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP6_IP3_MBOX" , 0x1070100c88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP7_IP3_MBOX" , 0x1070100e88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP8_IP3_MBOX" , 0x1070101088200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP9_IP3_MBOX" , 0x1070101288200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP10_IP3_MBOX" , 0x1070101488200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP11_IP3_MBOX" , 0x1070101688200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP12_IP3_MBOX" , 0x1070101888200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP13_IP3_MBOX" , 0x1070101a88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP14_IP3_MBOX" , 0x1070101c88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP15_IP3_MBOX" , 0x1070101e88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP16_IP3_MBOX" , 0x1070102088200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP17_IP3_MBOX" , 0x1070102288200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP18_IP3_MBOX" , 0x1070102488200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP19_IP3_MBOX" , 0x1070102688200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP20_IP3_MBOX" , 0x1070102888200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP21_IP3_MBOX" , 0x1070102a88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP22_IP3_MBOX" , 0x1070102c88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP23_IP3_MBOX" , 0x1070102e88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP24_IP3_MBOX" , 0x1070103088200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP25_IP3_MBOX" , 0x1070103288200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP26_IP3_MBOX" , 0x1070103488200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP27_IP3_MBOX" , 0x1070103688200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP28_IP3_MBOX" , 0x1070103888200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP29_IP3_MBOX" , 0x1070103a88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP30_IP3_MBOX" , 0x1070103c88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP31_IP3_MBOX" , 0x1070103e88200ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
- {"CIU2_SRC_PP0_IP3_MEM" , 0x1070100085200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP1_IP3_MEM" , 0x1070100285200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP2_IP3_MEM" , 0x1070100485200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP3_IP3_MEM" , 0x1070100685200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP4_IP3_MEM" , 0x1070100885200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP5_IP3_MEM" , 0x1070100a85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP6_IP3_MEM" , 0x1070100c85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP7_IP3_MEM" , 0x1070100e85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP8_IP3_MEM" , 0x1070101085200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP9_IP3_MEM" , 0x1070101285200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP10_IP3_MEM" , 0x1070101485200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP11_IP3_MEM" , 0x1070101685200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP12_IP3_MEM" , 0x1070101885200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP13_IP3_MEM" , 0x1070101a85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP14_IP3_MEM" , 0x1070101c85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP15_IP3_MEM" , 0x1070101e85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP16_IP3_MEM" , 0x1070102085200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP17_IP3_MEM" , 0x1070102285200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP18_IP3_MEM" , 0x1070102485200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP19_IP3_MEM" , 0x1070102685200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP20_IP3_MEM" , 0x1070102885200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP21_IP3_MEM" , 0x1070102a85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP22_IP3_MEM" , 0x1070102c85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP23_IP3_MEM" , 0x1070102e85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP24_IP3_MEM" , 0x1070103085200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP25_IP3_MEM" , 0x1070103285200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP26_IP3_MEM" , 0x1070103485200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP27_IP3_MEM" , 0x1070103685200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP28_IP3_MEM" , 0x1070103885200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP29_IP3_MEM" , 0x1070103a85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP30_IP3_MEM" , 0x1070103c85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP31_IP3_MEM" , 0x1070103e85200ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
- {"CIU2_SRC_PP0_IP3_MIO" , 0x1070100083200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP1_IP3_MIO" , 0x1070100283200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP2_IP3_MIO" , 0x1070100483200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP3_IP3_MIO" , 0x1070100683200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP4_IP3_MIO" , 0x1070100883200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP5_IP3_MIO" , 0x1070100a83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP6_IP3_MIO" , 0x1070100c83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP7_IP3_MIO" , 0x1070100e83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP8_IP3_MIO" , 0x1070101083200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP9_IP3_MIO" , 0x1070101283200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP10_IP3_MIO" , 0x1070101483200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP11_IP3_MIO" , 0x1070101683200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP12_IP3_MIO" , 0x1070101883200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP13_IP3_MIO" , 0x1070101a83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP14_IP3_MIO" , 0x1070101c83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP15_IP3_MIO" , 0x1070101e83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP16_IP3_MIO" , 0x1070102083200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP17_IP3_MIO" , 0x1070102283200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP18_IP3_MIO" , 0x1070102483200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP19_IP3_MIO" , 0x1070102683200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP20_IP3_MIO" , 0x1070102883200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP21_IP3_MIO" , 0x1070102a83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP22_IP3_MIO" , 0x1070102c83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP23_IP3_MIO" , 0x1070102e83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP24_IP3_MIO" , 0x1070103083200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP25_IP3_MIO" , 0x1070103283200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP26_IP3_MIO" , 0x1070103483200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP27_IP3_MIO" , 0x1070103683200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP28_IP3_MIO" , 0x1070103883200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP29_IP3_MIO" , 0x1070103a83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP30_IP3_MIO" , 0x1070103c83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP31_IP3_MIO" , 0x1070103e83200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
- {"CIU2_SRC_PP0_IP3_PKT" , 0x1070100086200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP1_IP3_PKT" , 0x1070100286200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP2_IP3_PKT" , 0x1070100486200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP3_IP3_PKT" , 0x1070100686200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP4_IP3_PKT" , 0x1070100886200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP5_IP3_PKT" , 0x1070100a86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP6_IP3_PKT" , 0x1070100c86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP7_IP3_PKT" , 0x1070100e86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP8_IP3_PKT" , 0x1070101086200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP9_IP3_PKT" , 0x1070101286200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP10_IP3_PKT" , 0x1070101486200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP11_IP3_PKT" , 0x1070101686200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP12_IP3_PKT" , 0x1070101886200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP13_IP3_PKT" , 0x1070101a86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP14_IP3_PKT" , 0x1070101c86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP15_IP3_PKT" , 0x1070101e86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP16_IP3_PKT" , 0x1070102086200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP17_IP3_PKT" , 0x1070102286200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP18_IP3_PKT" , 0x1070102486200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP19_IP3_PKT" , 0x1070102686200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP20_IP3_PKT" , 0x1070102886200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP21_IP3_PKT" , 0x1070102a86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP22_IP3_PKT" , 0x1070102c86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP23_IP3_PKT" , 0x1070102e86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP24_IP3_PKT" , 0x1070103086200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP25_IP3_PKT" , 0x1070103286200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP26_IP3_PKT" , 0x1070103486200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP27_IP3_PKT" , 0x1070103686200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP28_IP3_PKT" , 0x1070103886200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP29_IP3_PKT" , 0x1070103a86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP30_IP3_PKT" , 0x1070103c86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP31_IP3_PKT" , 0x1070103e86200ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
- {"CIU2_SRC_PP0_IP3_RML" , 0x1070100082200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP1_IP3_RML" , 0x1070100282200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP2_IP3_RML" , 0x1070100482200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP3_IP3_RML" , 0x1070100682200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP4_IP3_RML" , 0x1070100882200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP5_IP3_RML" , 0x1070100a82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP6_IP3_RML" , 0x1070100c82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP7_IP3_RML" , 0x1070100e82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP8_IP3_RML" , 0x1070101082200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP9_IP3_RML" , 0x1070101282200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP10_IP3_RML" , 0x1070101482200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP11_IP3_RML" , 0x1070101682200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP12_IP3_RML" , 0x1070101882200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP13_IP3_RML" , 0x1070101a82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP14_IP3_RML" , 0x1070101c82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP15_IP3_RML" , 0x1070101e82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP16_IP3_RML" , 0x1070102082200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP17_IP3_RML" , 0x1070102282200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP18_IP3_RML" , 0x1070102482200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP19_IP3_RML" , 0x1070102682200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP20_IP3_RML" , 0x1070102882200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP21_IP3_RML" , 0x1070102a82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP22_IP3_RML" , 0x1070102c82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP23_IP3_RML" , 0x1070102e82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP24_IP3_RML" , 0x1070103082200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP25_IP3_RML" , 0x1070103282200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP26_IP3_RML" , 0x1070103482200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP27_IP3_RML" , 0x1070103682200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP28_IP3_RML" , 0x1070103882200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP29_IP3_RML" , 0x1070103a82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP30_IP3_RML" , 0x1070103c82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP31_IP3_RML" , 0x1070103e82200ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
- {"CIU2_SRC_PP0_IP3_WDOG" , 0x1070100081200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP1_IP3_WDOG" , 0x1070100281200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP2_IP3_WDOG" , 0x1070100481200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP3_IP3_WDOG" , 0x1070100681200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP4_IP3_WDOG" , 0x1070100881200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP5_IP3_WDOG" , 0x1070100a81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP6_IP3_WDOG" , 0x1070100c81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP7_IP3_WDOG" , 0x1070100e81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP8_IP3_WDOG" , 0x1070101081200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP9_IP3_WDOG" , 0x1070101281200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP10_IP3_WDOG" , 0x1070101481200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP11_IP3_WDOG" , 0x1070101681200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP12_IP3_WDOG" , 0x1070101881200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP13_IP3_WDOG" , 0x1070101a81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP14_IP3_WDOG" , 0x1070101c81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP15_IP3_WDOG" , 0x1070101e81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP16_IP3_WDOG" , 0x1070102081200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP17_IP3_WDOG" , 0x1070102281200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP18_IP3_WDOG" , 0x1070102481200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP19_IP3_WDOG" , 0x1070102681200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP20_IP3_WDOG" , 0x1070102881200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP21_IP3_WDOG" , 0x1070102a81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP22_IP3_WDOG" , 0x1070102c81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP23_IP3_WDOG" , 0x1070102e81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP24_IP3_WDOG" , 0x1070103081200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP25_IP3_WDOG" , 0x1070103281200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP26_IP3_WDOG" , 0x1070103481200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP27_IP3_WDOG" , 0x1070103681200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP28_IP3_WDOG" , 0x1070103881200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP29_IP3_WDOG" , 0x1070103a81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP30_IP3_WDOG" , 0x1070103c81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP31_IP3_WDOG" , 0x1070103e81200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
- {"CIU2_SRC_PP0_IP3_WRKQ" , 0x1070100080200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP1_IP3_WRKQ" , 0x1070100280200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP2_IP3_WRKQ" , 0x1070100480200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP3_IP3_WRKQ" , 0x1070100680200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP4_IP3_WRKQ" , 0x1070100880200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP5_IP3_WRKQ" , 0x1070100a80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP6_IP3_WRKQ" , 0x1070100c80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP7_IP3_WRKQ" , 0x1070100e80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP8_IP3_WRKQ" , 0x1070101080200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP9_IP3_WRKQ" , 0x1070101280200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP10_IP3_WRKQ" , 0x1070101480200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP11_IP3_WRKQ" , 0x1070101680200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP12_IP3_WRKQ" , 0x1070101880200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP13_IP3_WRKQ" , 0x1070101a80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP14_IP3_WRKQ" , 0x1070101c80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP15_IP3_WRKQ" , 0x1070101e80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP16_IP3_WRKQ" , 0x1070102080200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP17_IP3_WRKQ" , 0x1070102280200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP18_IP3_WRKQ" , 0x1070102480200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP19_IP3_WRKQ" , 0x1070102680200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP20_IP3_WRKQ" , 0x1070102880200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP21_IP3_WRKQ" , 0x1070102a80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP22_IP3_WRKQ" , 0x1070102c80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP23_IP3_WRKQ" , 0x1070102e80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP24_IP3_WRKQ" , 0x1070103080200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP25_IP3_WRKQ" , 0x1070103280200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP26_IP3_WRKQ" , 0x1070103480200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP27_IP3_WRKQ" , 0x1070103680200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP28_IP3_WRKQ" , 0x1070103880200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP29_IP3_WRKQ" , 0x1070103a80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP30_IP3_WRKQ" , 0x1070103c80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP31_IP3_WRKQ" , 0x1070103e80200ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
- {"CIU2_SRC_PP0_IP4_GPIO" , 0x1070100087400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP1_IP4_GPIO" , 0x1070100287400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP2_IP4_GPIO" , 0x1070100487400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP3_IP4_GPIO" , 0x1070100687400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP4_IP4_GPIO" , 0x1070100887400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP5_IP4_GPIO" , 0x1070100a87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP6_IP4_GPIO" , 0x1070100c87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP7_IP4_GPIO" , 0x1070100e87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP8_IP4_GPIO" , 0x1070101087400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP9_IP4_GPIO" , 0x1070101287400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP10_IP4_GPIO" , 0x1070101487400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP11_IP4_GPIO" , 0x1070101687400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP12_IP4_GPIO" , 0x1070101887400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP13_IP4_GPIO" , 0x1070101a87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP14_IP4_GPIO" , 0x1070101c87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP15_IP4_GPIO" , 0x1070101e87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP16_IP4_GPIO" , 0x1070102087400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP17_IP4_GPIO" , 0x1070102287400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP18_IP4_GPIO" , 0x1070102487400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP19_IP4_GPIO" , 0x1070102687400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP20_IP4_GPIO" , 0x1070102887400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP21_IP4_GPIO" , 0x1070102a87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP22_IP4_GPIO" , 0x1070102c87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP23_IP4_GPIO" , 0x1070102e87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP24_IP4_GPIO" , 0x1070103087400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP25_IP4_GPIO" , 0x1070103287400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP26_IP4_GPIO" , 0x1070103487400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP27_IP4_GPIO" , 0x1070103687400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP28_IP4_GPIO" , 0x1070103887400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP29_IP4_GPIO" , 0x1070103a87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP30_IP4_GPIO" , 0x1070103c87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP31_IP4_GPIO" , 0x1070103e87400ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
- {"CIU2_SRC_PP0_IP4_IO" , 0x1070100084400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP1_IP4_IO" , 0x1070100284400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP2_IP4_IO" , 0x1070100484400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP3_IP4_IO" , 0x1070100684400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP4_IP4_IO" , 0x1070100884400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP5_IP4_IO" , 0x1070100a84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP6_IP4_IO" , 0x1070100c84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP7_IP4_IO" , 0x1070100e84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP8_IP4_IO" , 0x1070101084400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP9_IP4_IO" , 0x1070101284400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP10_IP4_IO" , 0x1070101484400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP11_IP4_IO" , 0x1070101684400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP12_IP4_IO" , 0x1070101884400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP13_IP4_IO" , 0x1070101a84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP14_IP4_IO" , 0x1070101c84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP15_IP4_IO" , 0x1070101e84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP16_IP4_IO" , 0x1070102084400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP17_IP4_IO" , 0x1070102284400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP18_IP4_IO" , 0x1070102484400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP19_IP4_IO" , 0x1070102684400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP20_IP4_IO" , 0x1070102884400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP21_IP4_IO" , 0x1070102a84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP22_IP4_IO" , 0x1070102c84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP23_IP4_IO" , 0x1070102e84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP24_IP4_IO" , 0x1070103084400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP25_IP4_IO" , 0x1070103284400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP26_IP4_IO" , 0x1070103484400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP27_IP4_IO" , 0x1070103684400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP28_IP4_IO" , 0x1070103884400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP29_IP4_IO" , 0x1070103a84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP30_IP4_IO" , 0x1070103c84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP31_IP4_IO" , 0x1070103e84400ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
- {"CIU2_SRC_PP0_IP4_MBOX" , 0x1070100088400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP1_IP4_MBOX" , 0x1070100288400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP2_IP4_MBOX" , 0x1070100488400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP3_IP4_MBOX" , 0x1070100688400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP4_IP4_MBOX" , 0x1070100888400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP5_IP4_MBOX" , 0x1070100a88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP6_IP4_MBOX" , 0x1070100c88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP7_IP4_MBOX" , 0x1070100e88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP8_IP4_MBOX" , 0x1070101088400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP9_IP4_MBOX" , 0x1070101288400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP10_IP4_MBOX" , 0x1070101488400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP11_IP4_MBOX" , 0x1070101688400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP12_IP4_MBOX" , 0x1070101888400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP13_IP4_MBOX" , 0x1070101a88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP14_IP4_MBOX" , 0x1070101c88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP15_IP4_MBOX" , 0x1070101e88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP16_IP4_MBOX" , 0x1070102088400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP17_IP4_MBOX" , 0x1070102288400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP18_IP4_MBOX" , 0x1070102488400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP19_IP4_MBOX" , 0x1070102688400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP20_IP4_MBOX" , 0x1070102888400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP21_IP4_MBOX" , 0x1070102a88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP22_IP4_MBOX" , 0x1070102c88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP23_IP4_MBOX" , 0x1070102e88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP24_IP4_MBOX" , 0x1070103088400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP25_IP4_MBOX" , 0x1070103288400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP26_IP4_MBOX" , 0x1070103488400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP27_IP4_MBOX" , 0x1070103688400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP28_IP4_MBOX" , 0x1070103888400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP29_IP4_MBOX" , 0x1070103a88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP30_IP4_MBOX" , 0x1070103c88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP31_IP4_MBOX" , 0x1070103e88400ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
- {"CIU2_SRC_PP0_IP4_MEM" , 0x1070100085400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP1_IP4_MEM" , 0x1070100285400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP2_IP4_MEM" , 0x1070100485400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP3_IP4_MEM" , 0x1070100685400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP4_IP4_MEM" , 0x1070100885400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP5_IP4_MEM" , 0x1070100a85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP6_IP4_MEM" , 0x1070100c85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP7_IP4_MEM" , 0x1070100e85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP8_IP4_MEM" , 0x1070101085400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP9_IP4_MEM" , 0x1070101285400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP10_IP4_MEM" , 0x1070101485400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP11_IP4_MEM" , 0x1070101685400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP12_IP4_MEM" , 0x1070101885400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP13_IP4_MEM" , 0x1070101a85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP14_IP4_MEM" , 0x1070101c85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP15_IP4_MEM" , 0x1070101e85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP16_IP4_MEM" , 0x1070102085400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP17_IP4_MEM" , 0x1070102285400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP18_IP4_MEM" , 0x1070102485400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP19_IP4_MEM" , 0x1070102685400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP20_IP4_MEM" , 0x1070102885400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP21_IP4_MEM" , 0x1070102a85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP22_IP4_MEM" , 0x1070102c85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP23_IP4_MEM" , 0x1070102e85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP24_IP4_MEM" , 0x1070103085400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP25_IP4_MEM" , 0x1070103285400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP26_IP4_MEM" , 0x1070103485400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP27_IP4_MEM" , 0x1070103685400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP28_IP4_MEM" , 0x1070103885400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP29_IP4_MEM" , 0x1070103a85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP30_IP4_MEM" , 0x1070103c85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP31_IP4_MEM" , 0x1070103e85400ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
- {"CIU2_SRC_PP0_IP4_MIO" , 0x1070100083400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP1_IP4_MIO" , 0x1070100283400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP2_IP4_MIO" , 0x1070100483400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP3_IP4_MIO" , 0x1070100683400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP4_IP4_MIO" , 0x1070100883400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP5_IP4_MIO" , 0x1070100a83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP6_IP4_MIO" , 0x1070100c83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP7_IP4_MIO" , 0x1070100e83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP8_IP4_MIO" , 0x1070101083400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP9_IP4_MIO" , 0x1070101283400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP10_IP4_MIO" , 0x1070101483400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP11_IP4_MIO" , 0x1070101683400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP12_IP4_MIO" , 0x1070101883400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP13_IP4_MIO" , 0x1070101a83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP14_IP4_MIO" , 0x1070101c83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP15_IP4_MIO" , 0x1070101e83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP16_IP4_MIO" , 0x1070102083400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP17_IP4_MIO" , 0x1070102283400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP18_IP4_MIO" , 0x1070102483400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP19_IP4_MIO" , 0x1070102683400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP20_IP4_MIO" , 0x1070102883400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP21_IP4_MIO" , 0x1070102a83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP22_IP4_MIO" , 0x1070102c83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP23_IP4_MIO" , 0x1070102e83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP24_IP4_MIO" , 0x1070103083400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP25_IP4_MIO" , 0x1070103283400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP26_IP4_MIO" , 0x1070103483400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP27_IP4_MIO" , 0x1070103683400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP28_IP4_MIO" , 0x1070103883400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP29_IP4_MIO" , 0x1070103a83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP30_IP4_MIO" , 0x1070103c83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP31_IP4_MIO" , 0x1070103e83400ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
- {"CIU2_SRC_PP0_IP4_PKT" , 0x1070100086400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP1_IP4_PKT" , 0x1070100286400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP2_IP4_PKT" , 0x1070100486400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP3_IP4_PKT" , 0x1070100686400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP4_IP4_PKT" , 0x1070100886400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP5_IP4_PKT" , 0x1070100a86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP6_IP4_PKT" , 0x1070100c86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP7_IP4_PKT" , 0x1070100e86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP8_IP4_PKT" , 0x1070101086400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP9_IP4_PKT" , 0x1070101286400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP10_IP4_PKT" , 0x1070101486400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP11_IP4_PKT" , 0x1070101686400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP12_IP4_PKT" , 0x1070101886400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP13_IP4_PKT" , 0x1070101a86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP14_IP4_PKT" , 0x1070101c86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP15_IP4_PKT" , 0x1070101e86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP16_IP4_PKT" , 0x1070102086400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP17_IP4_PKT" , 0x1070102286400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP18_IP4_PKT" , 0x1070102486400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP19_IP4_PKT" , 0x1070102686400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP20_IP4_PKT" , 0x1070102886400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP21_IP4_PKT" , 0x1070102a86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP22_IP4_PKT" , 0x1070102c86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP23_IP4_PKT" , 0x1070102e86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP24_IP4_PKT" , 0x1070103086400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP25_IP4_PKT" , 0x1070103286400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP26_IP4_PKT" , 0x1070103486400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP27_IP4_PKT" , 0x1070103686400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP28_IP4_PKT" , 0x1070103886400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP29_IP4_PKT" , 0x1070103a86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP30_IP4_PKT" , 0x1070103c86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP31_IP4_PKT" , 0x1070103e86400ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
- {"CIU2_SRC_PP0_IP4_RML" , 0x1070100082400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP1_IP4_RML" , 0x1070100282400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP2_IP4_RML" , 0x1070100482400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP3_IP4_RML" , 0x1070100682400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP4_IP4_RML" , 0x1070100882400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP5_IP4_RML" , 0x1070100a82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP6_IP4_RML" , 0x1070100c82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP7_IP4_RML" , 0x1070100e82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP8_IP4_RML" , 0x1070101082400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP9_IP4_RML" , 0x1070101282400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP10_IP4_RML" , 0x1070101482400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP11_IP4_RML" , 0x1070101682400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP12_IP4_RML" , 0x1070101882400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP13_IP4_RML" , 0x1070101a82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP14_IP4_RML" , 0x1070101c82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP15_IP4_RML" , 0x1070101e82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP16_IP4_RML" , 0x1070102082400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP17_IP4_RML" , 0x1070102282400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP18_IP4_RML" , 0x1070102482400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP19_IP4_RML" , 0x1070102682400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP20_IP4_RML" , 0x1070102882400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP21_IP4_RML" , 0x1070102a82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP22_IP4_RML" , 0x1070102c82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP23_IP4_RML" , 0x1070102e82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP24_IP4_RML" , 0x1070103082400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP25_IP4_RML" , 0x1070103282400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP26_IP4_RML" , 0x1070103482400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP27_IP4_RML" , 0x1070103682400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP28_IP4_RML" , 0x1070103882400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP29_IP4_RML" , 0x1070103a82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP30_IP4_RML" , 0x1070103c82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP31_IP4_RML" , 0x1070103e82400ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
- {"CIU2_SRC_PP0_IP4_WDOG" , 0x1070100081400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP1_IP4_WDOG" , 0x1070100281400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP2_IP4_WDOG" , 0x1070100481400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP3_IP4_WDOG" , 0x1070100681400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP4_IP4_WDOG" , 0x1070100881400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP5_IP4_WDOG" , 0x1070100a81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP6_IP4_WDOG" , 0x1070100c81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP7_IP4_WDOG" , 0x1070100e81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP8_IP4_WDOG" , 0x1070101081400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP9_IP4_WDOG" , 0x1070101281400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP10_IP4_WDOG" , 0x1070101481400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP11_IP4_WDOG" , 0x1070101681400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP12_IP4_WDOG" , 0x1070101881400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP13_IP4_WDOG" , 0x1070101a81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP14_IP4_WDOG" , 0x1070101c81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP15_IP4_WDOG" , 0x1070101e81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP16_IP4_WDOG" , 0x1070102081400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP17_IP4_WDOG" , 0x1070102281400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP18_IP4_WDOG" , 0x1070102481400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP19_IP4_WDOG" , 0x1070102681400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP20_IP4_WDOG" , 0x1070102881400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP21_IP4_WDOG" , 0x1070102a81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP22_IP4_WDOG" , 0x1070102c81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP23_IP4_WDOG" , 0x1070102e81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP24_IP4_WDOG" , 0x1070103081400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP25_IP4_WDOG" , 0x1070103281400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP26_IP4_WDOG" , 0x1070103481400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP27_IP4_WDOG" , 0x1070103681400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP28_IP4_WDOG" , 0x1070103881400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP29_IP4_WDOG" , 0x1070103a81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP30_IP4_WDOG" , 0x1070103c81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP31_IP4_WDOG" , 0x1070103e81400ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
- {"CIU2_SRC_PP0_IP4_WRKQ" , 0x1070100080400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP1_IP4_WRKQ" , 0x1070100280400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP2_IP4_WRKQ" , 0x1070100480400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP3_IP4_WRKQ" , 0x1070100680400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP4_IP4_WRKQ" , 0x1070100880400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP5_IP4_WRKQ" , 0x1070100a80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP6_IP4_WRKQ" , 0x1070100c80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP7_IP4_WRKQ" , 0x1070100e80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP8_IP4_WRKQ" , 0x1070101080400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP9_IP4_WRKQ" , 0x1070101280400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP10_IP4_WRKQ" , 0x1070101480400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP11_IP4_WRKQ" , 0x1070101680400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP12_IP4_WRKQ" , 0x1070101880400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP13_IP4_WRKQ" , 0x1070101a80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP14_IP4_WRKQ" , 0x1070101c80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP15_IP4_WRKQ" , 0x1070101e80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP16_IP4_WRKQ" , 0x1070102080400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP17_IP4_WRKQ" , 0x1070102280400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP18_IP4_WRKQ" , 0x1070102480400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP19_IP4_WRKQ" , 0x1070102680400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP20_IP4_WRKQ" , 0x1070102880400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP21_IP4_WRKQ" , 0x1070102a80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP22_IP4_WRKQ" , 0x1070102c80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP23_IP4_WRKQ" , 0x1070102e80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP24_IP4_WRKQ" , 0x1070103080400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP25_IP4_WRKQ" , 0x1070103280400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP26_IP4_WRKQ" , 0x1070103480400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP27_IP4_WRKQ" , 0x1070103680400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP28_IP4_WRKQ" , 0x1070103880400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP29_IP4_WRKQ" , 0x1070103a80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP30_IP4_WRKQ" , 0x1070103c80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SRC_PP31_IP4_WRKQ" , 0x1070103e80400ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
- {"CIU2_SUM_IO0_INT" , 0x1070100000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"CIU2_SUM_IO1_INT" , 0x1070100000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
- {"CIU2_SUM_PP0_IP2" , 0x1070100000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP1_IP2" , 0x1070100000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP2_IP2" , 0x1070100000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP3_IP2" , 0x1070100000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP4_IP2" , 0x1070100000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP5_IP2" , 0x1070100000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP6_IP2" , 0x1070100000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP7_IP2" , 0x1070100000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP8_IP2" , 0x1070100000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP9_IP2" , 0x1070100000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP10_IP2" , 0x1070100000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP11_IP2" , 0x1070100000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP12_IP2" , 0x1070100000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP13_IP2" , 0x1070100000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP14_IP2" , 0x1070100000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP15_IP2" , 0x1070100000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP16_IP2" , 0x1070100000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP17_IP2" , 0x1070100000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP18_IP2" , 0x1070100000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP19_IP2" , 0x1070100000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP20_IP2" , 0x10701000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP21_IP2" , 0x10701000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP22_IP2" , 0x10701000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP23_IP2" , 0x10701000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP24_IP2" , 0x10701000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP25_IP2" , 0x10701000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP26_IP2" , 0x10701000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP27_IP2" , 0x10701000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP28_IP2" , 0x10701000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP29_IP2" , 0x10701000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP30_IP2" , 0x10701000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP31_IP2" , 0x10701000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
- {"CIU2_SUM_PP0_IP3" , 0x1070100000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP1_IP3" , 0x1070100000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP2_IP3" , 0x1070100000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP3_IP3" , 0x1070100000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP4_IP3" , 0x1070100000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP5_IP3" , 0x1070100000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP6_IP3" , 0x1070100000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP7_IP3" , 0x1070100000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP8_IP3" , 0x1070100000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP9_IP3" , 0x1070100000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP10_IP3" , 0x1070100000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP11_IP3" , 0x1070100000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP12_IP3" , 0x1070100000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP13_IP3" , 0x1070100000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP14_IP3" , 0x1070100000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP15_IP3" , 0x1070100000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP16_IP3" , 0x1070100000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP17_IP3" , 0x1070100000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP18_IP3" , 0x1070100000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP19_IP3" , 0x1070100000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP20_IP3" , 0x10701000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP21_IP3" , 0x10701000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP22_IP3" , 0x10701000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP23_IP3" , 0x10701000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP24_IP3" , 0x10701000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP25_IP3" , 0x10701000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP26_IP3" , 0x10701000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP27_IP3" , 0x10701000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP28_IP3" , 0x10701000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP29_IP3" , 0x10701000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP30_IP3" , 0x10701000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP31_IP3" , 0x10701000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
- {"CIU2_SUM_PP0_IP4" , 0x1070100000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP1_IP4" , 0x1070100000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP2_IP4" , 0x1070100000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP3_IP4" , 0x1070100000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP4_IP4" , 0x1070100000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP5_IP4" , 0x1070100000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP6_IP4" , 0x1070100000430ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP7_IP4" , 0x1070100000438ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP8_IP4" , 0x1070100000440ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP9_IP4" , 0x1070100000448ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP10_IP4" , 0x1070100000450ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP11_IP4" , 0x1070100000458ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP12_IP4" , 0x1070100000460ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP13_IP4" , 0x1070100000468ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP14_IP4" , 0x1070100000470ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP15_IP4" , 0x1070100000478ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP16_IP4" , 0x1070100000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP17_IP4" , 0x1070100000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP18_IP4" , 0x1070100000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP19_IP4" , 0x1070100000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP20_IP4" , 0x10701000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP21_IP4" , 0x10701000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP22_IP4" , 0x10701000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP23_IP4" , 0x10701000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP24_IP4" , 0x10701000004c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP25_IP4" , 0x10701000004c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP26_IP4" , 0x10701000004d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP27_IP4" , 0x10701000004d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP28_IP4" , 0x10701000004e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP29_IP4" , 0x10701000004e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP30_IP4" , 0x10701000004f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU2_SUM_PP31_IP4" , 0x10701000004f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 265},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 266},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 267},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
- {"CIU_INT_DBG_SEL" , 0x10700000007d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 269},
- {"CIU_MBOX_CLR0" , 0x1070100100600ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR1" , 0x1070100100608ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR2" , 0x1070100100610ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR3" , 0x1070100100618ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR4" , 0x1070100100620ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR5" , 0x1070100100628ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR6" , 0x1070100100630ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR7" , 0x1070100100638ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR8" , 0x1070100100640ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR9" , 0x1070100100648ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR10" , 0x1070100100650ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR11" , 0x1070100100658ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR12" , 0x1070100100660ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR13" , 0x1070100100668ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR14" , 0x1070100100670ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR15" , 0x1070100100678ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR16" , 0x1070100100680ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR17" , 0x1070100100688ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR18" , 0x1070100100690ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR19" , 0x1070100100698ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR20" , 0x10701001006a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR21" , 0x10701001006a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR22" , 0x10701001006b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR23" , 0x10701001006b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR24" , 0x10701001006c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR25" , 0x10701001006c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR26" , 0x10701001006d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR27" , 0x10701001006d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR28" , 0x10701001006e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR29" , 0x10701001006e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR30" , 0x10701001006f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_CLR31" , 0x10701001006f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
- {"CIU_MBOX_SET0" , 0x1070100100400ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET1" , 0x1070100100408ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET2" , 0x1070100100410ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET3" , 0x1070100100418ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET4" , 0x1070100100420ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET5" , 0x1070100100428ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET6" , 0x1070100100430ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET7" , 0x1070100100438ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET8" , 0x1070100100440ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET9" , 0x1070100100448ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET10" , 0x1070100100450ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET11" , 0x1070100100458ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET12" , 0x1070100100460ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET13" , 0x1070100100468ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET14" , 0x1070100100470ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET15" , 0x1070100100478ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET16" , 0x1070100100480ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET17" , 0x1070100100488ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET18" , 0x1070100100490ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET19" , 0x1070100100498ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET20" , 0x10701001004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET21" , 0x10701001004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET22" , 0x10701001004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET23" , 0x10701001004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET24" , 0x10701001004c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET25" , 0x10701001004c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET26" , 0x10701001004d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET27" , 0x10701001004d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET28" , 0x10701001004e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET29" , 0x10701001004e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET30" , 0x10701001004f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_MBOX_SET31" , 0x10701001004f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 272},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 273},
- {"CIU_PP_BIST_STAT" , 0x10700000007e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 274},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 275},
- {"CIU_PP_POKE0" , 0x1070100100200ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE1" , 0x1070100100208ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE2" , 0x1070100100210ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE3" , 0x1070100100218ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE4" , 0x1070100100220ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE5" , 0x1070100100228ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE6" , 0x1070100100230ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE7" , 0x1070100100238ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE8" , 0x1070100100240ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE9" , 0x1070100100248ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE10" , 0x1070100100250ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE11" , 0x1070100100258ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE12" , 0x1070100100260ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE13" , 0x1070100100268ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE14" , 0x1070100100270ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE15" , 0x1070100100278ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE16" , 0x1070100100280ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE17" , 0x1070100100288ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE18" , 0x1070100100290ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE19" , 0x1070100100298ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE20" , 0x10701001002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE21" , 0x10701001002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE22" , 0x10701001002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE23" , 0x10701001002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE24" , 0x10701001002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE25" , 0x10701001002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE26" , 0x10701001002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE27" , 0x10701001002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE28" , 0x10701001002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE29" , 0x10701001002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE30" , 0x10701001002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_POKE31" , 0x10701001002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
- {"CIU_QLM0" , 0x1070000000780ull, CVMX_CSR_DB_TYPE_NCB, 64, 278},
- {"CIU_QLM1" , 0x1070000000788ull, CVMX_CSR_DB_TYPE_NCB, 64, 279},
- {"CIU_QLM2" , 0x1070000000790ull, CVMX_CSR_DB_TYPE_NCB, 64, 280},
- {"CIU_QLM3" , 0x1070000000798ull, CVMX_CSR_DB_TYPE_NCB, 64, 281},
- {"CIU_QLM4" , 0x10700000007a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 282},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 283},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 284},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 285},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 287},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 288},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
- {"CIU_WDOG0" , 0x1070100100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG1" , 0x1070100100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG2" , 0x1070100100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG3" , 0x1070100100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG4" , 0x1070100100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG5" , 0x1070100100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG6" , 0x1070100100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG7" , 0x1070100100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG8" , 0x1070100100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG9" , 0x1070100100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG10" , 0x1070100100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG11" , 0x1070100100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG12" , 0x1070100100060ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG13" , 0x1070100100068ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG14" , 0x1070100100070ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG15" , 0x1070100100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG16" , 0x1070100100080ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG17" , 0x1070100100088ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG18" , 0x1070100100090ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG19" , 0x1070100100098ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG20" , 0x10701001000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG21" , 0x10701001000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG22" , 0x10701001000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG23" , 0x10701001000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG24" , 0x10701001000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG25" , 0x10701001000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG26" , 0x10701001000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG27" , 0x10701001000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG28" , 0x10701001000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG29" , 0x10701001000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG30" , 0x10701001000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"CIU_WDOG31" , 0x10701001000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
- {"DFA_BIST0" , 0x11800370007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"DFA_BIST1" , 0x11800370007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"DFA_CONFIG" , 0x1180037000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"DFA_CONTROL" , 0x1180037000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
- {"DFA_DEBUG0" , 0x1180037000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"DFA_DEBUG1" , 0x1180037000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"DFA_DEBUG2" , 0x1180037000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"DFA_DEBUG3" , 0x1180037000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
- {"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
- {"DFA_DTCFADR" , 0x1180037000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"DFA_ERROR" , 0x1180037000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"DFA_INTMSK" , 0x1180037000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"DFA_MEMHIDAT" , 0x1370700000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 305},
- {"DFA_PFC0_CNT" , 0x1180037000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"DFA_PFC0_CTL" , 0x1180037000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"DFA_PFC1_CNT" , 0x11800370000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"DFA_PFC1_CTL" , 0x1180037000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"DFA_PFC2_CNT" , 0x11800370000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"DFA_PFC2_CTL" , 0x11800370000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"DFA_PFC3_CNT" , 0x11800370000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"DFA_PFC3_CTL" , 0x11800370000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"DFA_PFC_GCTL" , 0x1180037000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"DPI_BIST_STATUS" , 0x1df0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 315},
- {"DPI_CTL" , 0x1df0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
- {"DPI_DMA0_COUNTS" , 0x1df0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA1_COUNTS" , 0x1df0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA2_COUNTS" , 0x1df0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA3_COUNTS" , 0x1df0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA4_COUNTS" , 0x1df0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA5_COUNTS" , 0x1df0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA6_COUNTS" , 0x1df0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA7_COUNTS" , 0x1df0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
- {"DPI_DMA0_DBELL" , 0x1df0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA1_DBELL" , 0x1df0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA2_DBELL" , 0x1df0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA3_DBELL" , 0x1df0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA4_DBELL" , 0x1df0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA5_DBELL" , 0x1df0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA6_DBELL" , 0x1df0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA7_DBELL" , 0x1df0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
- {"DPI_DMA0_ERR_RSP_STATUS" , 0x1df0000000a80ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA1_ERR_RSP_STATUS" , 0x1df0000000a88ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA2_ERR_RSP_STATUS" , 0x1df0000000a90ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA3_ERR_RSP_STATUS" , 0x1df0000000a98ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA4_ERR_RSP_STATUS" , 0x1df0000000aa0ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA5_ERR_RSP_STATUS" , 0x1df0000000aa8ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA6_ERR_RSP_STATUS" , 0x1df0000000ab0ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA7_ERR_RSP_STATUS" , 0x1df0000000ab8ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
- {"DPI_DMA0_IBUFF_SADDR" , 0x1df0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA1_IBUFF_SADDR" , 0x1df0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA2_IBUFF_SADDR" , 0x1df0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA3_IBUFF_SADDR" , 0x1df0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA4_IBUFF_SADDR" , 0x1df00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA5_IBUFF_SADDR" , 0x1df00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA6_IBUFF_SADDR" , 0x1df00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA7_IBUFF_SADDR" , 0x1df00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
- {"DPI_DMA0_IFLIGHT" , 0x1df0000000a00ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA1_IFLIGHT" , 0x1df0000000a08ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA2_IFLIGHT" , 0x1df0000000a10ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA3_IFLIGHT" , 0x1df0000000a18ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA4_IFLIGHT" , 0x1df0000000a20ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA5_IFLIGHT" , 0x1df0000000a28ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA6_IFLIGHT" , 0x1df0000000a30ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA7_IFLIGHT" , 0x1df0000000a38ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
- {"DPI_DMA0_NADDR" , 0x1df0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA1_NADDR" , 0x1df0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA2_NADDR" , 0x1df0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA3_NADDR" , 0x1df0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA4_NADDR" , 0x1df00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA5_NADDR" , 0x1df00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA6_NADDR" , 0x1df00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA7_NADDR" , 0x1df00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
- {"DPI_DMA0_REQBNK0" , 0x1df0000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA1_REQBNK0" , 0x1df0000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA2_REQBNK0" , 0x1df0000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA3_REQBNK0" , 0x1df0000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA4_REQBNK0" , 0x1df0000000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA5_REQBNK0" , 0x1df0000000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA6_REQBNK0" , 0x1df0000000430ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA7_REQBNK0" , 0x1df0000000438ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
- {"DPI_DMA0_REQBNK1" , 0x1df0000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA1_REQBNK1" , 0x1df0000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA2_REQBNK1" , 0x1df0000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA3_REQBNK1" , 0x1df0000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA4_REQBNK1" , 0x1df00000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA5_REQBNK1" , 0x1df00000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA6_REQBNK1" , 0x1df00000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA7_REQBNK1" , 0x1df00000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
- {"DPI_DMA_CONTROL" , 0x1df0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 325},
- {"DPI_DMA_ENG0_EN" , 0x1df0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_ENG1_EN" , 0x1df0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_ENG2_EN" , 0x1df0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_ENG3_EN" , 0x1df0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_ENG4_EN" , 0x1df00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_ENG5_EN" , 0x1df00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
- {"DPI_DMA_PP0_CNT" , 0x1df0000000b00ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP1_CNT" , 0x1df0000000b08ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP2_CNT" , 0x1df0000000b10ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP3_CNT" , 0x1df0000000b18ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP4_CNT" , 0x1df0000000b20ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP5_CNT" , 0x1df0000000b28ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP6_CNT" , 0x1df0000000b30ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP7_CNT" , 0x1df0000000b38ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP8_CNT" , 0x1df0000000b40ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP9_CNT" , 0x1df0000000b48ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP10_CNT" , 0x1df0000000b50ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP11_CNT" , 0x1df0000000b58ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP12_CNT" , 0x1df0000000b60ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP13_CNT" , 0x1df0000000b68ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP14_CNT" , 0x1df0000000b70ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP15_CNT" , 0x1df0000000b78ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP16_CNT" , 0x1df0000000b80ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP17_CNT" , 0x1df0000000b88ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP18_CNT" , 0x1df0000000b90ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP19_CNT" , 0x1df0000000b98ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP20_CNT" , 0x1df0000000ba0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP21_CNT" , 0x1df0000000ba8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP22_CNT" , 0x1df0000000bb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP23_CNT" , 0x1df0000000bb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP24_CNT" , 0x1df0000000bc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP25_CNT" , 0x1df0000000bc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP26_CNT" , 0x1df0000000bd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP27_CNT" , 0x1df0000000bd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP28_CNT" , 0x1df0000000be0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP29_CNT" , 0x1df0000000be8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP30_CNT" , 0x1df0000000bf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_DMA_PP31_CNT" , 0x1df0000000bf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
- {"DPI_ENG0_BUF" , 0x1df0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"DPI_ENG1_BUF" , 0x1df0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"DPI_ENG2_BUF" , 0x1df0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"DPI_ENG3_BUF" , 0x1df0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"DPI_ENG4_BUF" , 0x1df00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"DPI_ENG5_BUF" , 0x1df00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
- {"DPI_INFO_REG" , 0x1df0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
- {"DPI_INT_EN" , 0x1df0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
- {"DPI_INT_REG" , 0x1df0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
- {"DPI_NCB0_CFG" , 0x1df0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
- {"DPI_PINT_INFO" , 0x1df0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
- {"DPI_PKT_ERR_RSP" , 0x1df0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
- {"DPI_REQ_ERR_RSP" , 0x1df0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
- {"DPI_REQ_ERR_RSP_EN" , 0x1df0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
- {"DPI_REQ_ERR_RST" , 0x1df0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
- {"DPI_REQ_ERR_RST_EN" , 0x1df0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
- {"DPI_REQ_ERR_SKIP_COMP" , 0x1df0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
- {"DPI_REQ_GBL_EN" , 0x1df0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
- {"DPI_SLI_PRT0_CFG" , 0x1df0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"DPI_SLI_PRT1_CFG" , 0x1df0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
- {"DPI_SLI_PRT0_ERR" , 0x1df0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"DPI_SLI_PRT1_ERR" , 0x1df0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
- {"DPI_SLI_PRT0_ERR_INFO" , 0x1df0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"DPI_SLI_PRT1_ERR_INFO" , 0x1df0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
- {"FPA_ADDR_RANGE_ERROR" , 0x1180028000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"FPA_FPF8_MARKS" , 0x1180028000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"FPA_FPF8_SIZE" , 0x1180028000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"FPA_PACKET_THRESHOLD" , 0x1180028000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"FPA_POOL0_END_ADDR" , 0x1180028000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL1_END_ADDR" , 0x1180028000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL2_END_ADDR" , 0x1180028000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL3_END_ADDR" , 0x1180028000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL4_END_ADDR" , 0x1180028000378ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL5_END_ADDR" , 0x1180028000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL6_END_ADDR" , 0x1180028000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL7_END_ADDR" , 0x1180028000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL8_END_ADDR" , 0x1180028000398ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"FPA_POOL0_START_ADDR" , 0x1180028000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_POOL1_START_ADDR" , 0x1180028000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_POOL2_START_ADDR" , 0x1180028000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_POOL3_START_ADDR" , 0x1180028000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_POOL4_START_ADDR" , 0x1180028000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_POOL5_START_ADDR" , 0x1180028000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_POOL6_START_ADDR" , 0x1180028000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_POOL7_START_ADDR" , 0x1180028000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_POOL8_START_ADDR" , 0x1180028000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"FPA_POOL0_THRESHOLD" , 0x1180028000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_POOL1_THRESHOLD" , 0x1180028000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_POOL2_THRESHOLD" , 0x1180028000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_POOL3_THRESHOLD" , 0x1180028000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_POOL4_THRESHOLD" , 0x1180028000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_POOL5_THRESHOLD" , 0x1180028000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_POOL6_THRESHOLD" , 0x1180028000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_POOL7_THRESHOLD" , 0x1180028000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_POOL8_THRESHOLD" , 0x1180028000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"FPA_QUE8_AVAILABLE" , 0x11800280000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"FPA_QUE8_PAGE_INDEX" , 0x1180028000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"FPA_WQE_THRESHOLD" , 0x1180028000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX1_BAD_REG" , 0x1180009000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX2_BAD_REG" , 0x118000a000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX3_BAD_REG" , 0x118000b000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX4_BAD_REG" , 0x118000c000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX1_BIST" , 0x1180009000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX2_BIST" , 0x118000a000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX3_BIST" , 0x118000b000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX4_BIST" , 0x118000c000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX0_BPID_MAP000" , 0x1180008000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP001" , 0x1180008000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP002" , 0x1180008000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP003" , 0x1180008000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP004" , 0x11800080006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP005" , 0x11800080006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP006" , 0x11800080006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP007" , 0x11800080006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP008" , 0x11800080006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP009" , 0x11800080006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP010" , 0x11800080006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP011" , 0x11800080006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP012" , 0x11800080006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP013" , 0x11800080006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP014" , 0x11800080006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MAP015" , 0x11800080006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP000" , 0x1180009000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP001" , 0x1180009000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP002" , 0x1180009000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP003" , 0x1180009000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP004" , 0x11800090006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP005" , 0x11800090006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP006" , 0x11800090006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP007" , 0x11800090006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP008" , 0x11800090006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP009" , 0x11800090006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP010" , 0x11800090006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP011" , 0x11800090006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP012" , 0x11800090006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP013" , 0x11800090006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP014" , 0x11800090006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX1_BPID_MAP015" , 0x11800090006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP000" , 0x118000a000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP001" , 0x118000a000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP002" , 0x118000a000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP003" , 0x118000a000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP004" , 0x118000a0006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP005" , 0x118000a0006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP006" , 0x118000a0006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP007" , 0x118000a0006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP008" , 0x118000a0006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP009" , 0x118000a0006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP010" , 0x118000a0006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP011" , 0x118000a0006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP012" , 0x118000a0006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP013" , 0x118000a0006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP014" , 0x118000a0006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX2_BPID_MAP015" , 0x118000a0006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP000" , 0x118000b000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP001" , 0x118000b000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP002" , 0x118000b000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP003" , 0x118000b000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP004" , 0x118000b0006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP005" , 0x118000b0006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP006" , 0x118000b0006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP007" , 0x118000b0006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP008" , 0x118000b0006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP009" , 0x118000b0006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP010" , 0x118000b0006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP011" , 0x118000b0006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP012" , 0x118000b0006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP013" , 0x118000b0006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP014" , 0x118000b0006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX3_BPID_MAP015" , 0x118000b0006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP000" , 0x118000c000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP001" , 0x118000c000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP002" , 0x118000c000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP003" , 0x118000c000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP004" , 0x118000c0006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP005" , 0x118000c0006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP006" , 0x118000c0006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP007" , 0x118000c0006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP008" , 0x118000c0006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP009" , 0x118000c0006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP010" , 0x118000c0006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP011" , 0x118000c0006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP012" , 0x118000c0006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP013" , 0x118000c0006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP014" , 0x118000c0006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX4_BPID_MAP015" , 0x118000c0006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_BPID_MSK" , 0x1180008000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX1_BPID_MSK" , 0x1180009000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX2_BPID_MSK" , 0x118000a000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX3_BPID_MSK" , 0x118000b000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX4_BPID_MSK" , 0x118000c000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX1_CLK_EN" , 0x11800090007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX2_CLK_EN" , 0x118000a0007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX3_CLK_EN" , 0x118000b0007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX4_CLK_EN" , 0x118000c0007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX0_EBP_DIS" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX1_EBP_DIS" , 0x1180009000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX2_EBP_DIS" , 0x118000a000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX3_EBP_DIS" , 0x118000b000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX4_EBP_DIS" , 0x118000c000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX0_EBP_MSK" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX1_EBP_MSK" , 0x1180009000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX2_EBP_MSK" , 0x118000a000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX3_EBP_MSK" , 0x118000b000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX4_EBP_MSK" , 0x118000c000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX1_HG2_CONTROL" , 0x1180009000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX2_HG2_CONTROL" , 0x118000a000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX3_HG2_CONTROL" , 0x118000b000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX4_HG2_CONTROL" , 0x118000c000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX1_INF_MODE" , 0x11800090007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX2_INF_MODE" , 0x118000a0007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX3_INF_MODE" , 0x118000b0007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX4_INF_MODE" , 0x118000c0007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX1_NXA_ADR" , 0x1180009000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX2_NXA_ADR" , 0x118000a000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX3_NXA_ADR" , 0x118000b000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX4_NXA_ADR" , 0x118000c000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX0_PIPE_STATUS" , 0x1180008000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX1_PIPE_STATUS" , 0x1180009000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX2_PIPE_STATUS" , 0x118000a000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX3_PIPE_STATUS" , 0x118000b000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX4_PIPE_STATUS" , 0x118000c000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX1_PRT000_CBFC_CTL" , 0x1180009000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX2_PRT000_CBFC_CTL" , 0x118000a000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX3_PRT000_CBFC_CTL" , 0x118000b000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX4_PRT000_CBFC_CTL" , 0x118000c000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX1_PRT000_CFG" , 0x1180009000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX1_PRT001_CFG" , 0x1180009000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX1_PRT002_CFG" , 0x1180009001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX1_PRT003_CFG" , 0x1180009001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX2_PRT000_CFG" , 0x118000a000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX2_PRT001_CFG" , 0x118000a000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX2_PRT002_CFG" , 0x118000a001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX2_PRT003_CFG" , 0x118000a001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX3_PRT000_CFG" , 0x118000b000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX3_PRT001_CFG" , 0x118000b000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX3_PRT002_CFG" , 0x118000b001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX3_PRT003_CFG" , 0x118000b001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX4_PRT000_CFG" , 0x118000c000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX4_PRT001_CFG" , 0x118000c000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX4_PRT002_CFG" , 0x118000c001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX4_PRT003_CFG" , 0x118000c001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX1_RX000_ADR_CAM0" , 0x1180009000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX1_RX001_ADR_CAM0" , 0x1180009000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX1_RX002_ADR_CAM0" , 0x1180009001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX1_RX003_ADR_CAM0" , 0x1180009001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX2_RX000_ADR_CAM0" , 0x118000a000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX2_RX001_ADR_CAM0" , 0x118000a000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX2_RX002_ADR_CAM0" , 0x118000a001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX2_RX003_ADR_CAM0" , 0x118000a001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX3_RX000_ADR_CAM0" , 0x118000b000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX3_RX001_ADR_CAM0" , 0x118000b000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX3_RX002_ADR_CAM0" , 0x118000b001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX3_RX003_ADR_CAM0" , 0x118000b001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX4_RX000_ADR_CAM0" , 0x118000c000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX4_RX001_ADR_CAM0" , 0x118000c000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX4_RX002_ADR_CAM0" , 0x118000c001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX4_RX003_ADR_CAM0" , 0x118000c001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX1_RX000_ADR_CAM1" , 0x1180009000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX1_RX001_ADR_CAM1" , 0x1180009000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX1_RX002_ADR_CAM1" , 0x1180009001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX1_RX003_ADR_CAM1" , 0x1180009001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX2_RX000_ADR_CAM1" , 0x118000a000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX2_RX001_ADR_CAM1" , 0x118000a000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX2_RX002_ADR_CAM1" , 0x118000a001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX2_RX003_ADR_CAM1" , 0x118000a001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX3_RX000_ADR_CAM1" , 0x118000b000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX3_RX001_ADR_CAM1" , 0x118000b000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX3_RX002_ADR_CAM1" , 0x118000b001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX3_RX003_ADR_CAM1" , 0x118000b001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX4_RX000_ADR_CAM1" , 0x118000c000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX4_RX001_ADR_CAM1" , 0x118000c000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX4_RX002_ADR_CAM1" , 0x118000c001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX4_RX003_ADR_CAM1" , 0x118000c001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX1_RX000_ADR_CAM2" , 0x1180009000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX1_RX001_ADR_CAM2" , 0x1180009000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX1_RX002_ADR_CAM2" , 0x1180009001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX1_RX003_ADR_CAM2" , 0x1180009001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX2_RX000_ADR_CAM2" , 0x118000a000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX2_RX001_ADR_CAM2" , 0x118000a000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX2_RX002_ADR_CAM2" , 0x118000a001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX2_RX003_ADR_CAM2" , 0x118000a001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX3_RX000_ADR_CAM2" , 0x118000b000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX3_RX001_ADR_CAM2" , 0x118000b000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX3_RX002_ADR_CAM2" , 0x118000b001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX3_RX003_ADR_CAM2" , 0x118000b001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX4_RX000_ADR_CAM2" , 0x118000c000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX4_RX001_ADR_CAM2" , 0x118000c000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX4_RX002_ADR_CAM2" , 0x118000c001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX4_RX003_ADR_CAM2" , 0x118000c001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX1_RX000_ADR_CAM3" , 0x1180009000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX1_RX001_ADR_CAM3" , 0x1180009000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX1_RX002_ADR_CAM3" , 0x1180009001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX1_RX003_ADR_CAM3" , 0x1180009001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX2_RX000_ADR_CAM3" , 0x118000a000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX2_RX001_ADR_CAM3" , 0x118000a000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX2_RX002_ADR_CAM3" , 0x118000a001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX2_RX003_ADR_CAM3" , 0x118000a001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX3_RX000_ADR_CAM3" , 0x118000b000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX3_RX001_ADR_CAM3" , 0x118000b000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX3_RX002_ADR_CAM3" , 0x118000b001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX3_RX003_ADR_CAM3" , 0x118000b001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX4_RX000_ADR_CAM3" , 0x118000c000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX4_RX001_ADR_CAM3" , 0x118000c000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX4_RX002_ADR_CAM3" , 0x118000c001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX4_RX003_ADR_CAM3" , 0x118000c001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX1_RX000_ADR_CAM4" , 0x11800090001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX1_RX001_ADR_CAM4" , 0x11800090009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX1_RX002_ADR_CAM4" , 0x11800090011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX1_RX003_ADR_CAM4" , 0x11800090019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX2_RX000_ADR_CAM4" , 0x118000a0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX2_RX001_ADR_CAM4" , 0x118000a0009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX2_RX002_ADR_CAM4" , 0x118000a0011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX2_RX003_ADR_CAM4" , 0x118000a0019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX3_RX000_ADR_CAM4" , 0x118000b0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX3_RX001_ADR_CAM4" , 0x118000b0009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX3_RX002_ADR_CAM4" , 0x118000b0011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX3_RX003_ADR_CAM4" , 0x118000b0019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX4_RX000_ADR_CAM4" , 0x118000c0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX4_RX001_ADR_CAM4" , 0x118000c0009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX4_RX002_ADR_CAM4" , 0x118000c0011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX4_RX003_ADR_CAM4" , 0x118000c0019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX1_RX000_ADR_CAM5" , 0x11800090001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX1_RX001_ADR_CAM5" , 0x11800090009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX1_RX002_ADR_CAM5" , 0x11800090011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX1_RX003_ADR_CAM5" , 0x11800090019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX2_RX000_ADR_CAM5" , 0x118000a0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX2_RX001_ADR_CAM5" , 0x118000a0009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX2_RX002_ADR_CAM5" , 0x118000a0011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX2_RX003_ADR_CAM5" , 0x118000a0019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX3_RX000_ADR_CAM5" , 0x118000b0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX3_RX001_ADR_CAM5" , 0x118000b0009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX3_RX002_ADR_CAM5" , 0x118000b0011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX3_RX003_ADR_CAM5" , 0x118000b0019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX4_RX000_ADR_CAM5" , 0x118000c0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX4_RX001_ADR_CAM5" , 0x118000c0009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX4_RX002_ADR_CAM5" , 0x118000c0011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX4_RX003_ADR_CAM5" , 0x118000c0019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX0_RX000_ADR_CAM_ALL_EN" , 0x1180008000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX0_RX001_ADR_CAM_ALL_EN" , 0x1180008000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX0_RX002_ADR_CAM_ALL_EN" , 0x1180008001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX0_RX003_ADR_CAM_ALL_EN" , 0x1180008001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX1_RX000_ADR_CAM_ALL_EN" , 0x1180009000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX1_RX001_ADR_CAM_ALL_EN" , 0x1180009000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX1_RX002_ADR_CAM_ALL_EN" , 0x1180009001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX1_RX003_ADR_CAM_ALL_EN" , 0x1180009001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX2_RX000_ADR_CAM_ALL_EN" , 0x118000a000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX2_RX001_ADR_CAM_ALL_EN" , 0x118000a000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX2_RX002_ADR_CAM_ALL_EN" , 0x118000a001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX2_RX003_ADR_CAM_ALL_EN" , 0x118000a001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX3_RX000_ADR_CAM_ALL_EN" , 0x118000b000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX3_RX001_ADR_CAM_ALL_EN" , 0x118000b000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX3_RX002_ADR_CAM_ALL_EN" , 0x118000b001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX3_RX003_ADR_CAM_ALL_EN" , 0x118000b001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX4_RX000_ADR_CAM_ALL_EN" , 0x118000c000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX4_RX001_ADR_CAM_ALL_EN" , 0x118000c000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX4_RX002_ADR_CAM_ALL_EN" , 0x118000c001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX4_RX003_ADR_CAM_ALL_EN" , 0x118000c001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX1_RX000_ADR_CAM_EN" , 0x1180009000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX1_RX001_ADR_CAM_EN" , 0x1180009000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX1_RX002_ADR_CAM_EN" , 0x1180009001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX1_RX003_ADR_CAM_EN" , 0x1180009001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX2_RX000_ADR_CAM_EN" , 0x118000a000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX2_RX001_ADR_CAM_EN" , 0x118000a000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX2_RX002_ADR_CAM_EN" , 0x118000a001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX2_RX003_ADR_CAM_EN" , 0x118000a001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX3_RX000_ADR_CAM_EN" , 0x118000b000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX3_RX001_ADR_CAM_EN" , 0x118000b000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX3_RX002_ADR_CAM_EN" , 0x118000b001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX3_RX003_ADR_CAM_EN" , 0x118000b001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX4_RX000_ADR_CAM_EN" , 0x118000c000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX4_RX001_ADR_CAM_EN" , 0x118000c000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX4_RX002_ADR_CAM_EN" , 0x118000c001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX4_RX003_ADR_CAM_EN" , 0x118000c001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX1_RX000_ADR_CTL" , 0x1180009000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX1_RX001_ADR_CTL" , 0x1180009000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX1_RX002_ADR_CTL" , 0x1180009001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX1_RX003_ADR_CTL" , 0x1180009001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX2_RX000_ADR_CTL" , 0x118000a000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX2_RX001_ADR_CTL" , 0x118000a000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX2_RX002_ADR_CTL" , 0x118000a001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX2_RX003_ADR_CTL" , 0x118000a001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX3_RX000_ADR_CTL" , 0x118000b000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX3_RX001_ADR_CTL" , 0x118000b000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX3_RX002_ADR_CTL" , 0x118000b001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX3_RX003_ADR_CTL" , 0x118000b001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX4_RX000_ADR_CTL" , 0x118000c000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX4_RX001_ADR_CTL" , 0x118000c000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX4_RX002_ADR_CTL" , 0x118000c001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX4_RX003_ADR_CTL" , 0x118000c001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX1_RX000_DECISION" , 0x1180009000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX1_RX001_DECISION" , 0x1180009000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX1_RX002_DECISION" , 0x1180009001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX1_RX003_DECISION" , 0x1180009001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX2_RX000_DECISION" , 0x118000a000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX2_RX001_DECISION" , 0x118000a000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX2_RX002_DECISION" , 0x118000a001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX2_RX003_DECISION" , 0x118000a001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX3_RX000_DECISION" , 0x118000b000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX3_RX001_DECISION" , 0x118000b000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX3_RX002_DECISION" , 0x118000b001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX3_RX003_DECISION" , 0x118000b001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX4_RX000_DECISION" , 0x118000c000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX4_RX001_DECISION" , 0x118000c000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX4_RX002_DECISION" , 0x118000c001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX4_RX003_DECISION" , 0x118000c001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX1_RX000_FRM_CHK" , 0x1180009000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX1_RX001_FRM_CHK" , 0x1180009000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX1_RX002_FRM_CHK" , 0x1180009001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX1_RX003_FRM_CHK" , 0x1180009001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX2_RX000_FRM_CHK" , 0x118000a000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX2_RX001_FRM_CHK" , 0x118000a000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX2_RX002_FRM_CHK" , 0x118000a001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX2_RX003_FRM_CHK" , 0x118000a001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX3_RX000_FRM_CHK" , 0x118000b000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX3_RX001_FRM_CHK" , 0x118000b000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX3_RX002_FRM_CHK" , 0x118000b001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX3_RX003_FRM_CHK" , 0x118000b001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX4_RX000_FRM_CHK" , 0x118000c000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX4_RX001_FRM_CHK" , 0x118000c000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX4_RX002_FRM_CHK" , 0x118000c001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX4_RX003_FRM_CHK" , 0x118000c001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX1_RX000_FRM_CTL" , 0x1180009000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX1_RX001_FRM_CTL" , 0x1180009000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX1_RX002_FRM_CTL" , 0x1180009001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX1_RX003_FRM_CTL" , 0x1180009001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX2_RX000_FRM_CTL" , 0x118000a000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX2_RX001_FRM_CTL" , 0x118000a000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX2_RX002_FRM_CTL" , 0x118000a001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX2_RX003_FRM_CTL" , 0x118000a001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX3_RX000_FRM_CTL" , 0x118000b000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX3_RX001_FRM_CTL" , 0x118000b000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX3_RX002_FRM_CTL" , 0x118000b001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX3_RX003_FRM_CTL" , 0x118000b001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX4_RX000_FRM_CTL" , 0x118000c000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX4_RX001_FRM_CTL" , 0x118000c000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX4_RX002_FRM_CTL" , 0x118000c001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX4_RX003_FRM_CTL" , 0x118000c001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX1_RX000_IFG" , 0x1180009000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX1_RX001_IFG" , 0x1180009000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX1_RX002_IFG" , 0x1180009001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX1_RX003_IFG" , 0x1180009001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX2_RX000_IFG" , 0x118000a000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX2_RX001_IFG" , 0x118000a000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX2_RX002_IFG" , 0x118000a001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX2_RX003_IFG" , 0x118000a001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX3_RX000_IFG" , 0x118000b000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX3_RX001_IFG" , 0x118000b000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX3_RX002_IFG" , 0x118000b001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX3_RX003_IFG" , 0x118000b001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX4_RX000_IFG" , 0x118000c000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX4_RX001_IFG" , 0x118000c000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX4_RX002_IFG" , 0x118000c001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX4_RX003_IFG" , 0x118000c001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX1_RX000_INT_EN" , 0x1180009000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX1_RX001_INT_EN" , 0x1180009000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX1_RX002_INT_EN" , 0x1180009001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX1_RX003_INT_EN" , 0x1180009001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX2_RX000_INT_EN" , 0x118000a000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX2_RX001_INT_EN" , 0x118000a000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX2_RX002_INT_EN" , 0x118000a001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX2_RX003_INT_EN" , 0x118000a001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX3_RX000_INT_EN" , 0x118000b000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX3_RX001_INT_EN" , 0x118000b000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX3_RX002_INT_EN" , 0x118000b001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX3_RX003_INT_EN" , 0x118000b001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX4_RX000_INT_EN" , 0x118000c000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX4_RX001_INT_EN" , 0x118000c000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX4_RX002_INT_EN" , 0x118000c001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX4_RX003_INT_EN" , 0x118000c001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX1_RX000_INT_REG" , 0x1180009000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX1_RX001_INT_REG" , 0x1180009000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX1_RX002_INT_REG" , 0x1180009001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX1_RX003_INT_REG" , 0x1180009001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX2_RX000_INT_REG" , 0x118000a000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX2_RX001_INT_REG" , 0x118000a000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX2_RX002_INT_REG" , 0x118000a001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX2_RX003_INT_REG" , 0x118000a001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX3_RX000_INT_REG" , 0x118000b000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX3_RX001_INT_REG" , 0x118000b000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX3_RX002_INT_REG" , 0x118000b001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX3_RX003_INT_REG" , 0x118000b001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX4_RX000_INT_REG" , 0x118000c000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX4_RX001_INT_REG" , 0x118000c000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX4_RX002_INT_REG" , 0x118000c001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX4_RX003_INT_REG" , 0x118000c001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX1_RX000_JABBER" , 0x1180009000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX1_RX001_JABBER" , 0x1180009000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX1_RX002_JABBER" , 0x1180009001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX1_RX003_JABBER" , 0x1180009001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX2_RX000_JABBER" , 0x118000a000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX2_RX001_JABBER" , 0x118000a000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX2_RX002_JABBER" , 0x118000a001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX2_RX003_JABBER" , 0x118000a001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX3_RX000_JABBER" , 0x118000b000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX3_RX001_JABBER" , 0x118000b000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX3_RX002_JABBER" , 0x118000b001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX3_RX003_JABBER" , 0x118000b001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX4_RX000_JABBER" , 0x118000c000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX4_RX001_JABBER" , 0x118000c000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX4_RX002_JABBER" , 0x118000c001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX4_RX003_JABBER" , 0x118000c001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180009000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180009000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180009001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180009001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX2_RX000_PAUSE_DROP_TIME" , 0x118000a000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX2_RX001_PAUSE_DROP_TIME" , 0x118000a000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX2_RX002_PAUSE_DROP_TIME" , 0x118000a001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX2_RX003_PAUSE_DROP_TIME" , 0x118000a001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX3_RX000_PAUSE_DROP_TIME" , 0x118000b000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX3_RX001_PAUSE_DROP_TIME" , 0x118000b000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX3_RX002_PAUSE_DROP_TIME" , 0x118000b001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX3_RX003_PAUSE_DROP_TIME" , 0x118000b001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX4_RX000_PAUSE_DROP_TIME" , 0x118000c000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX4_RX001_PAUSE_DROP_TIME" , 0x118000c000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX4_RX002_PAUSE_DROP_TIME" , 0x118000c001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX4_RX003_PAUSE_DROP_TIME" , 0x118000c001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX1_RX000_STATS_CTL" , 0x1180009000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX1_RX001_STATS_CTL" , 0x1180009000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX1_RX002_STATS_CTL" , 0x1180009001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX1_RX003_STATS_CTL" , 0x1180009001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX2_RX000_STATS_CTL" , 0x118000a000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX2_RX001_STATS_CTL" , 0x118000a000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX2_RX002_STATS_CTL" , 0x118000a001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX2_RX003_STATS_CTL" , 0x118000a001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX3_RX000_STATS_CTL" , 0x118000b000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX3_RX001_STATS_CTL" , 0x118000b000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX3_RX002_STATS_CTL" , 0x118000b001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX3_RX003_STATS_CTL" , 0x118000b001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX4_RX000_STATS_CTL" , 0x118000c000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX4_RX001_STATS_CTL" , 0x118000c000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX4_RX002_STATS_CTL" , 0x118000c001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX4_RX003_STATS_CTL" , 0x118000c001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX1_RX000_STATS_OCTS" , 0x1180009000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX1_RX001_STATS_OCTS" , 0x1180009000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX1_RX002_STATS_OCTS" , 0x1180009001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX1_RX003_STATS_OCTS" , 0x1180009001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX2_RX000_STATS_OCTS" , 0x118000a000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX2_RX001_STATS_OCTS" , 0x118000a000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX2_RX002_STATS_OCTS" , 0x118000a001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX2_RX003_STATS_OCTS" , 0x118000a001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX3_RX000_STATS_OCTS" , 0x118000b000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX3_RX001_STATS_OCTS" , 0x118000b000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX3_RX002_STATS_OCTS" , 0x118000b001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX3_RX003_STATS_OCTS" , 0x118000b001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX4_RX000_STATS_OCTS" , 0x118000c000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX4_RX001_STATS_OCTS" , 0x118000c000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX4_RX002_STATS_OCTS" , 0x118000c001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX4_RX003_STATS_OCTS" , 0x118000c001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX1_RX000_STATS_OCTS_CTL" , 0x1180009000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX1_RX001_STATS_OCTS_CTL" , 0x1180009000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX1_RX002_STATS_OCTS_CTL" , 0x1180009001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX1_RX003_STATS_OCTS_CTL" , 0x1180009001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX2_RX000_STATS_OCTS_CTL" , 0x118000a000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX2_RX001_STATS_OCTS_CTL" , 0x118000a000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX2_RX002_STATS_OCTS_CTL" , 0x118000a001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX2_RX003_STATS_OCTS_CTL" , 0x118000a001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX3_RX000_STATS_OCTS_CTL" , 0x118000b000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX3_RX001_STATS_OCTS_CTL" , 0x118000b000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX3_RX002_STATS_OCTS_CTL" , 0x118000b001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX3_RX003_STATS_OCTS_CTL" , 0x118000b001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX4_RX000_STATS_OCTS_CTL" , 0x118000c000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX4_RX001_STATS_OCTS_CTL" , 0x118000c000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX4_RX002_STATS_OCTS_CTL" , 0x118000c001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX4_RX003_STATS_OCTS_CTL" , 0x118000c001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800090000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800090008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800090010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800090018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX2_RX000_STATS_OCTS_DMAC" , 0x118000a0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX2_RX001_STATS_OCTS_DMAC" , 0x118000a0008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX2_RX002_STATS_OCTS_DMAC" , 0x118000a0010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX2_RX003_STATS_OCTS_DMAC" , 0x118000a0018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX3_RX000_STATS_OCTS_DMAC" , 0x118000b0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX3_RX001_STATS_OCTS_DMAC" , 0x118000b0008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX3_RX002_STATS_OCTS_DMAC" , 0x118000b0010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX3_RX003_STATS_OCTS_DMAC" , 0x118000b0018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX4_RX000_STATS_OCTS_DMAC" , 0x118000c0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX4_RX001_STATS_OCTS_DMAC" , 0x118000c0008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX4_RX002_STATS_OCTS_DMAC" , 0x118000c0010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX4_RX003_STATS_OCTS_DMAC" , 0x118000c0018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX1_RX000_STATS_OCTS_DRP" , 0x11800090000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX1_RX001_STATS_OCTS_DRP" , 0x11800090008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX1_RX002_STATS_OCTS_DRP" , 0x11800090010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX1_RX003_STATS_OCTS_DRP" , 0x11800090018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX2_RX000_STATS_OCTS_DRP" , 0x118000a0000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX2_RX001_STATS_OCTS_DRP" , 0x118000a0008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX2_RX002_STATS_OCTS_DRP" , 0x118000a0010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX2_RX003_STATS_OCTS_DRP" , 0x118000a0018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX3_RX000_STATS_OCTS_DRP" , 0x118000b0000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX3_RX001_STATS_OCTS_DRP" , 0x118000b0008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX3_RX002_STATS_OCTS_DRP" , 0x118000b0010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX3_RX003_STATS_OCTS_DRP" , 0x118000b0018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX4_RX000_STATS_OCTS_DRP" , 0x118000c0000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX4_RX001_STATS_OCTS_DRP" , 0x118000c0008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX4_RX002_STATS_OCTS_DRP" , 0x118000c0010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX4_RX003_STATS_OCTS_DRP" , 0x118000c0018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX1_RX000_STATS_PKTS" , 0x1180009000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX1_RX001_STATS_PKTS" , 0x1180009000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX1_RX002_STATS_PKTS" , 0x1180009001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX1_RX003_STATS_PKTS" , 0x1180009001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX2_RX000_STATS_PKTS" , 0x118000a000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX2_RX001_STATS_PKTS" , 0x118000a000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX2_RX002_STATS_PKTS" , 0x118000a001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX2_RX003_STATS_PKTS" , 0x118000a001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX3_RX000_STATS_PKTS" , 0x118000b000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX3_RX001_STATS_PKTS" , 0x118000b000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX3_RX002_STATS_PKTS" , 0x118000b001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX3_RX003_STATS_PKTS" , 0x118000b001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX4_RX000_STATS_PKTS" , 0x118000c000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX4_RX001_STATS_PKTS" , 0x118000c000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX4_RX002_STATS_PKTS" , 0x118000c001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX4_RX003_STATS_PKTS" , 0x118000c001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX1_RX000_STATS_PKTS_BAD" , 0x11800090000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX1_RX001_STATS_PKTS_BAD" , 0x11800090008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX1_RX002_STATS_PKTS_BAD" , 0x11800090010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX1_RX003_STATS_PKTS_BAD" , 0x11800090018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX2_RX000_STATS_PKTS_BAD" , 0x118000a0000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX2_RX001_STATS_PKTS_BAD" , 0x118000a0008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX2_RX002_STATS_PKTS_BAD" , 0x118000a0010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX2_RX003_STATS_PKTS_BAD" , 0x118000a0018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX3_RX000_STATS_PKTS_BAD" , 0x118000b0000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX3_RX001_STATS_PKTS_BAD" , 0x118000b0008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX3_RX002_STATS_PKTS_BAD" , 0x118000b0010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX3_RX003_STATS_PKTS_BAD" , 0x118000b0018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX4_RX000_STATS_PKTS_BAD" , 0x118000c0000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX4_RX001_STATS_PKTS_BAD" , 0x118000c0008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX4_RX002_STATS_PKTS_BAD" , 0x118000c0010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX4_RX003_STATS_PKTS_BAD" , 0x118000c0018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX1_RX000_STATS_PKTS_CTL" , 0x1180009000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX1_RX001_STATS_PKTS_CTL" , 0x1180009000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX1_RX002_STATS_PKTS_CTL" , 0x1180009001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX1_RX003_STATS_PKTS_CTL" , 0x1180009001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX2_RX000_STATS_PKTS_CTL" , 0x118000a000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX2_RX001_STATS_PKTS_CTL" , 0x118000a000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX2_RX002_STATS_PKTS_CTL" , 0x118000a001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX2_RX003_STATS_PKTS_CTL" , 0x118000a001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX3_RX000_STATS_PKTS_CTL" , 0x118000b000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX3_RX001_STATS_PKTS_CTL" , 0x118000b000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX3_RX002_STATS_PKTS_CTL" , 0x118000b001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX3_RX003_STATS_PKTS_CTL" , 0x118000b001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX4_RX000_STATS_PKTS_CTL" , 0x118000c000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX4_RX001_STATS_PKTS_CTL" , 0x118000c000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX4_RX002_STATS_PKTS_CTL" , 0x118000c001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX4_RX003_STATS_PKTS_CTL" , 0x118000c001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800090000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800090008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800090010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800090018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX2_RX000_STATS_PKTS_DMAC" , 0x118000a0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX2_RX001_STATS_PKTS_DMAC" , 0x118000a0008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX2_RX002_STATS_PKTS_DMAC" , 0x118000a0010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX2_RX003_STATS_PKTS_DMAC" , 0x118000a0018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX3_RX000_STATS_PKTS_DMAC" , 0x118000b0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX3_RX001_STATS_PKTS_DMAC" , 0x118000b0008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX3_RX002_STATS_PKTS_DMAC" , 0x118000b0010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX3_RX003_STATS_PKTS_DMAC" , 0x118000b0018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX4_RX000_STATS_PKTS_DMAC" , 0x118000c0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX4_RX001_STATS_PKTS_DMAC" , 0x118000c0008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX4_RX002_STATS_PKTS_DMAC" , 0x118000c0010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX4_RX003_STATS_PKTS_DMAC" , 0x118000c0018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX1_RX000_STATS_PKTS_DRP" , 0x11800090000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX1_RX001_STATS_PKTS_DRP" , 0x11800090008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX1_RX002_STATS_PKTS_DRP" , 0x11800090010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX1_RX003_STATS_PKTS_DRP" , 0x11800090018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX2_RX000_STATS_PKTS_DRP" , 0x118000a0000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX2_RX001_STATS_PKTS_DRP" , 0x118000a0008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX2_RX002_STATS_PKTS_DRP" , 0x118000a0010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX2_RX003_STATS_PKTS_DRP" , 0x118000a0018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX3_RX000_STATS_PKTS_DRP" , 0x118000b0000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX3_RX001_STATS_PKTS_DRP" , 0x118000b0008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX3_RX002_STATS_PKTS_DRP" , 0x118000b0010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX3_RX003_STATS_PKTS_DRP" , 0x118000b0018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX4_RX000_STATS_PKTS_DRP" , 0x118000c0000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX4_RX001_STATS_PKTS_DRP" , 0x118000c0008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX4_RX002_STATS_PKTS_DRP" , 0x118000c0010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX4_RX003_STATS_PKTS_DRP" , 0x118000c0018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX1_RX000_UDD_SKP" , 0x1180009000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX1_RX001_UDD_SKP" , 0x1180009000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX1_RX002_UDD_SKP" , 0x1180009001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX1_RX003_UDD_SKP" , 0x1180009001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX2_RX000_UDD_SKP" , 0x118000a000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX2_RX001_UDD_SKP" , 0x118000a000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX2_RX002_UDD_SKP" , 0x118000a001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX2_RX003_UDD_SKP" , 0x118000a001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX3_RX000_UDD_SKP" , 0x118000b000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX3_RX001_UDD_SKP" , 0x118000b000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX3_RX002_UDD_SKP" , 0x118000b001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX3_RX003_UDD_SKP" , 0x118000b001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX4_RX000_UDD_SKP" , 0x118000c000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX4_RX001_UDD_SKP" , 0x118000c000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX4_RX002_UDD_SKP" , 0x118000c001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX4_RX003_UDD_SKP" , 0x118000c001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX1_RX_BP_DROP000" , 0x1180009000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX1_RX_BP_DROP001" , 0x1180009000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX1_RX_BP_DROP002" , 0x1180009000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX1_RX_BP_DROP003" , 0x1180009000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX2_RX_BP_DROP000" , 0x118000a000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX2_RX_BP_DROP001" , 0x118000a000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX2_RX_BP_DROP002" , 0x118000a000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX2_RX_BP_DROP003" , 0x118000a000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX3_RX_BP_DROP000" , 0x118000b000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX3_RX_BP_DROP001" , 0x118000b000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX3_RX_BP_DROP002" , 0x118000b000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX3_RX_BP_DROP003" , 0x118000b000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX4_RX_BP_DROP000" , 0x118000c000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX4_RX_BP_DROP001" , 0x118000c000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX4_RX_BP_DROP002" , 0x118000c000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX4_RX_BP_DROP003" , 0x118000c000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX1_RX_BP_OFF000" , 0x1180009000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX1_RX_BP_OFF001" , 0x1180009000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX1_RX_BP_OFF002" , 0x1180009000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX1_RX_BP_OFF003" , 0x1180009000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX2_RX_BP_OFF000" , 0x118000a000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX2_RX_BP_OFF001" , 0x118000a000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX2_RX_BP_OFF002" , 0x118000a000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX2_RX_BP_OFF003" , 0x118000a000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX3_RX_BP_OFF000" , 0x118000b000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX3_RX_BP_OFF001" , 0x118000b000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX3_RX_BP_OFF002" , 0x118000b000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX3_RX_BP_OFF003" , 0x118000b000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX4_RX_BP_OFF000" , 0x118000c000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX4_RX_BP_OFF001" , 0x118000c000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX4_RX_BP_OFF002" , 0x118000c000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX4_RX_BP_OFF003" , 0x118000c000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX1_RX_BP_ON000" , 0x1180009000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX1_RX_BP_ON001" , 0x1180009000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX1_RX_BP_ON002" , 0x1180009000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX1_RX_BP_ON003" , 0x1180009000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX2_RX_BP_ON000" , 0x118000a000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX2_RX_BP_ON001" , 0x118000a000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX2_RX_BP_ON002" , 0x118000a000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX2_RX_BP_ON003" , 0x118000a000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX3_RX_BP_ON000" , 0x118000b000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX3_RX_BP_ON001" , 0x118000b000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX3_RX_BP_ON002" , 0x118000b000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX3_RX_BP_ON003" , 0x118000b000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX4_RX_BP_ON000" , 0x118000c000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX4_RX_BP_ON001" , 0x118000c000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX4_RX_BP_ON002" , 0x118000c000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX4_RX_BP_ON003" , 0x118000c000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
- {"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"GMX1_RX_HG2_STATUS" , 0x1180009000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"GMX2_RX_HG2_STATUS" , 0x118000a000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"GMX3_RX_HG2_STATUS" , 0x118000b000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"GMX4_RX_HG2_STATUS" , 0x118000c000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"GMX1_RX_PRT_INFO" , 0x11800090004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"GMX2_RX_PRT_INFO" , 0x118000a0004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"GMX3_RX_PRT_INFO" , 0x118000b0004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"GMX4_RX_PRT_INFO" , 0x118000c0004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"GMX1_RX_PRTS" , 0x1180009000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"GMX2_RX_PRTS" , 0x118000a000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"GMX3_RX_PRTS" , 0x118000b000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"GMX4_RX_PRTS" , 0x118000c000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX1_RX_XAUI_BAD_COL" , 0x1180009000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX2_RX_XAUI_BAD_COL" , 0x118000a000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX3_RX_XAUI_BAD_COL" , 0x118000b000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX4_RX_XAUI_BAD_COL" , 0x118000c000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"GMX1_RX_XAUI_CTL" , 0x1180009000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"GMX2_RX_XAUI_CTL" , 0x118000a000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"GMX3_RX_XAUI_CTL" , 0x118000b000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"GMX4_RX_XAUI_CTL" , 0x118000c000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"GMX0_RXAUI_CTL" , 0x1180008000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"GMX1_RXAUI_CTL" , 0x1180009000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"GMX2_RXAUI_CTL" , 0x118000a000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"GMX3_RXAUI_CTL" , 0x118000b000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"GMX4_RXAUI_CTL" , 0x118000c000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX0_SMAC003" , 0x1180008001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX1_SMAC000" , 0x1180009000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX1_SMAC001" , 0x1180009000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX1_SMAC002" , 0x1180009001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX1_SMAC003" , 0x1180009001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX2_SMAC000" , 0x118000a000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX2_SMAC001" , 0x118000a000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX2_SMAC002" , 0x118000a001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX2_SMAC003" , 0x118000a001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX3_SMAC000" , 0x118000b000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX3_SMAC001" , 0x118000b000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX3_SMAC002" , 0x118000b001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX3_SMAC003" , 0x118000b001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX4_SMAC000" , 0x118000c000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX4_SMAC001" , 0x118000c000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX4_SMAC002" , 0x118000c001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX4_SMAC003" , 0x118000c001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"GMX0_SOFT_BIST" , 0x11800080007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX1_SOFT_BIST" , 0x11800090007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX2_SOFT_BIST" , 0x118000a0007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX3_SOFT_BIST" , 0x118000b0007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX4_SOFT_BIST" , 0x118000c0007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"GMX1_STAT_BP" , 0x1180009000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"GMX2_STAT_BP" , 0x118000a000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"GMX3_STAT_BP" , 0x118000b000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"GMX4_STAT_BP" , 0x118000c000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"GMX0_TB_REG" , 0x11800080007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"GMX1_TB_REG" , 0x11800090007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"GMX2_TB_REG" , 0x118000a0007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"GMX3_TB_REG" , 0x118000b0007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"GMX4_TB_REG" , 0x118000c0007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX0_TX003_APPEND" , 0x1180008001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX1_TX000_APPEND" , 0x1180009000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX1_TX001_APPEND" , 0x1180009000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX1_TX002_APPEND" , 0x1180009001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX1_TX003_APPEND" , 0x1180009001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX2_TX000_APPEND" , 0x118000a000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX2_TX001_APPEND" , 0x118000a000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX2_TX002_APPEND" , 0x118000a001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX2_TX003_APPEND" , 0x118000a001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX3_TX000_APPEND" , 0x118000b000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX3_TX001_APPEND" , 0x118000b000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX3_TX002_APPEND" , 0x118000b001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX3_TX003_APPEND" , 0x118000b001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX4_TX000_APPEND" , 0x118000c000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX4_TX001_APPEND" , 0x118000c000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX4_TX002_APPEND" , 0x118000c001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX4_TX003_APPEND" , 0x118000c001a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX0_TX003_BURST" , 0x1180008001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX1_TX000_BURST" , 0x1180009000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX1_TX001_BURST" , 0x1180009000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX1_TX002_BURST" , 0x1180009001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX1_TX003_BURST" , 0x1180009001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX2_TX000_BURST" , 0x118000a000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX2_TX001_BURST" , 0x118000a000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX2_TX002_BURST" , 0x118000a001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX2_TX003_BURST" , 0x118000a001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX3_TX000_BURST" , 0x118000b000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX3_TX001_BURST" , 0x118000b000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX3_TX002_BURST" , 0x118000b001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX3_TX003_BURST" , 0x118000b001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX4_TX000_BURST" , 0x118000c000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX4_TX001_BURST" , 0x118000c000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX4_TX002_BURST" , 0x118000c001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX4_TX003_BURST" , 0x118000c001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"GMX0_TX000_CBFC_XOFF" , 0x11800080005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX1_TX000_CBFC_XOFF" , 0x11800090005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX2_TX000_CBFC_XOFF" , 0x118000a0005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX3_TX000_CBFC_XOFF" , 0x118000b0005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX4_TX000_CBFC_XOFF" , 0x118000c0005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"GMX0_TX000_CBFC_XON" , 0x11800080005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX1_TX000_CBFC_XON" , 0x11800090005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX2_TX000_CBFC_XON" , 0x118000a0005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX3_TX000_CBFC_XON" , 0x118000b0005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX4_TX000_CBFC_XON" , 0x118000c0005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX0_TX003_CTL" , 0x1180008001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX1_TX000_CTL" , 0x1180009000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX1_TX001_CTL" , 0x1180009000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX1_TX002_CTL" , 0x1180009001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX1_TX003_CTL" , 0x1180009001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX2_TX000_CTL" , 0x118000a000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX2_TX001_CTL" , 0x118000a000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX2_TX002_CTL" , 0x118000a001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX2_TX003_CTL" , 0x118000a001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX3_TX000_CTL" , 0x118000b000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX3_TX001_CTL" , 0x118000b000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX3_TX002_CTL" , 0x118000b001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX3_TX003_CTL" , 0x118000b001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX4_TX000_CTL" , 0x118000c000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX4_TX001_CTL" , 0x118000c000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX4_TX002_CTL" , 0x118000c001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX4_TX003_CTL" , 0x118000c001a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX0_TX003_MIN_PKT" , 0x1180008001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX1_TX000_MIN_PKT" , 0x1180009000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX1_TX001_MIN_PKT" , 0x1180009000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX1_TX002_MIN_PKT" , 0x1180009001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX1_TX003_MIN_PKT" , 0x1180009001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX2_TX000_MIN_PKT" , 0x118000a000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX2_TX001_MIN_PKT" , 0x118000a000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX2_TX002_MIN_PKT" , 0x118000a001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX2_TX003_MIN_PKT" , 0x118000a001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX3_TX000_MIN_PKT" , 0x118000b000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX3_TX001_MIN_PKT" , 0x118000b000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX3_TX002_MIN_PKT" , 0x118000b001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX3_TX003_MIN_PKT" , 0x118000b001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX4_TX000_MIN_PKT" , 0x118000c000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX4_TX001_MIN_PKT" , 0x118000c000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX4_TX002_MIN_PKT" , 0x118000c001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX4_TX003_MIN_PKT" , 0x118000c001a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180009000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180009000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180009001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180009001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX2_TX000_PAUSE_PKT_INTERVAL", 0x118000a000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX2_TX001_PAUSE_PKT_INTERVAL", 0x118000a000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX2_TX002_PAUSE_PKT_INTERVAL", 0x118000a001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX2_TX003_PAUSE_PKT_INTERVAL", 0x118000a001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX3_TX000_PAUSE_PKT_INTERVAL", 0x118000b000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX3_TX001_PAUSE_PKT_INTERVAL", 0x118000b000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX3_TX002_PAUSE_PKT_INTERVAL", 0x118000b001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX3_TX003_PAUSE_PKT_INTERVAL", 0x118000b001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX4_TX000_PAUSE_PKT_INTERVAL", 0x118000c000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX4_TX001_PAUSE_PKT_INTERVAL", 0x118000c000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX4_TX002_PAUSE_PKT_INTERVAL", 0x118000c001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX4_TX003_PAUSE_PKT_INTERVAL", 0x118000c001a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180009000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180009000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180009001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180009001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX2_TX000_PAUSE_PKT_TIME" , 0x118000a000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX2_TX001_PAUSE_PKT_TIME" , 0x118000a000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX2_TX002_PAUSE_PKT_TIME" , 0x118000a001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX2_TX003_PAUSE_PKT_TIME" , 0x118000a001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX3_TX000_PAUSE_PKT_TIME" , 0x118000b000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX3_TX001_PAUSE_PKT_TIME" , 0x118000b000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX3_TX002_PAUSE_PKT_TIME" , 0x118000b001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX3_TX003_PAUSE_PKT_TIME" , 0x118000b001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX4_TX000_PAUSE_PKT_TIME" , 0x118000c000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX4_TX001_PAUSE_PKT_TIME" , 0x118000c000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX4_TX002_PAUSE_PKT_TIME" , 0x118000c001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX4_TX003_PAUSE_PKT_TIME" , 0x118000c001a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX0_TX003_PAUSE_TOGO" , 0x1180008001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX1_TX000_PAUSE_TOGO" , 0x1180009000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX1_TX001_PAUSE_TOGO" , 0x1180009000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX1_TX002_PAUSE_TOGO" , 0x1180009001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX1_TX003_PAUSE_TOGO" , 0x1180009001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX2_TX000_PAUSE_TOGO" , 0x118000a000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX2_TX001_PAUSE_TOGO" , 0x118000a000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX2_TX002_PAUSE_TOGO" , 0x118000a001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX2_TX003_PAUSE_TOGO" , 0x118000a001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX3_TX000_PAUSE_TOGO" , 0x118000b000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX3_TX001_PAUSE_TOGO" , 0x118000b000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX3_TX002_PAUSE_TOGO" , 0x118000b001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX3_TX003_PAUSE_TOGO" , 0x118000b001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX4_TX000_PAUSE_TOGO" , 0x118000c000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX4_TX001_PAUSE_TOGO" , 0x118000c000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX4_TX002_PAUSE_TOGO" , 0x118000c001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX4_TX003_PAUSE_TOGO" , 0x118000c001a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX0_TX003_PAUSE_ZERO" , 0x1180008001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX1_TX000_PAUSE_ZERO" , 0x1180009000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX1_TX001_PAUSE_ZERO" , 0x1180009000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX1_TX002_PAUSE_ZERO" , 0x1180009001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX1_TX003_PAUSE_ZERO" , 0x1180009001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX2_TX000_PAUSE_ZERO" , 0x118000a000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX2_TX001_PAUSE_ZERO" , 0x118000a000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX2_TX002_PAUSE_ZERO" , 0x118000a001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX2_TX003_PAUSE_ZERO" , 0x118000a001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX3_TX000_PAUSE_ZERO" , 0x118000b000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX3_TX001_PAUSE_ZERO" , 0x118000b000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX3_TX002_PAUSE_ZERO" , 0x118000b001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX3_TX003_PAUSE_ZERO" , 0x118000b001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX4_TX000_PAUSE_ZERO" , 0x118000c000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX4_TX001_PAUSE_ZERO" , 0x118000c000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX4_TX002_PAUSE_ZERO" , 0x118000c001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX4_TX003_PAUSE_ZERO" , 0x118000c001a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"GMX0_TX000_PIPE" , 0x1180008000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX0_TX001_PIPE" , 0x1180008000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX0_TX002_PIPE" , 0x1180008001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX0_TX003_PIPE" , 0x1180008001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX1_TX000_PIPE" , 0x1180009000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX1_TX001_PIPE" , 0x1180009000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX1_TX002_PIPE" , 0x1180009001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX1_TX003_PIPE" , 0x1180009001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX2_TX000_PIPE" , 0x118000a000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX2_TX001_PIPE" , 0x118000a000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX2_TX002_PIPE" , 0x118000a001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX2_TX003_PIPE" , 0x118000a001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX3_TX000_PIPE" , 0x118000b000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX3_TX001_PIPE" , 0x118000b000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX3_TX002_PIPE" , 0x118000b001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX3_TX003_PIPE" , 0x118000b001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX4_TX000_PIPE" , 0x118000c000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX4_TX001_PIPE" , 0x118000c000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX4_TX002_PIPE" , 0x118000c001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX4_TX003_PIPE" , 0x118000c001b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX0_TX003_SGMII_CTL" , 0x1180008001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX1_TX000_SGMII_CTL" , 0x1180009000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX1_TX001_SGMII_CTL" , 0x1180009000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX1_TX002_SGMII_CTL" , 0x1180009001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX1_TX003_SGMII_CTL" , 0x1180009001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX2_TX000_SGMII_CTL" , 0x118000a000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX2_TX001_SGMII_CTL" , 0x118000a000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX2_TX002_SGMII_CTL" , 0x118000a001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX2_TX003_SGMII_CTL" , 0x118000a001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX3_TX000_SGMII_CTL" , 0x118000b000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX3_TX001_SGMII_CTL" , 0x118000b000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX3_TX002_SGMII_CTL" , 0x118000b001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX3_TX003_SGMII_CTL" , 0x118000b001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX4_TX000_SGMII_CTL" , 0x118000c000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX4_TX001_SGMII_CTL" , 0x118000c000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX4_TX002_SGMII_CTL" , 0x118000c001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX4_TX003_SGMII_CTL" , 0x118000c001b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX0_TX003_SLOT" , 0x1180008001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX1_TX000_SLOT" , 0x1180009000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX1_TX001_SLOT" , 0x1180009000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX1_TX002_SLOT" , 0x1180009001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX1_TX003_SLOT" , 0x1180009001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX2_TX000_SLOT" , 0x118000a000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX2_TX001_SLOT" , 0x118000a000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX2_TX002_SLOT" , 0x118000a001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX2_TX003_SLOT" , 0x118000a001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX3_TX000_SLOT" , 0x118000b000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX3_TX001_SLOT" , 0x118000b000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX3_TX002_SLOT" , 0x118000b001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX3_TX003_SLOT" , 0x118000b001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX4_TX000_SLOT" , 0x118000c000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX4_TX001_SLOT" , 0x118000c000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX4_TX002_SLOT" , 0x118000c001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX4_TX003_SLOT" , 0x118000c001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX0_TX003_SOFT_PAUSE" , 0x1180008001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX1_TX000_SOFT_PAUSE" , 0x1180009000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX1_TX001_SOFT_PAUSE" , 0x1180009000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX1_TX002_SOFT_PAUSE" , 0x1180009001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX1_TX003_SOFT_PAUSE" , 0x1180009001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX2_TX000_SOFT_PAUSE" , 0x118000a000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX2_TX001_SOFT_PAUSE" , 0x118000a000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX2_TX002_SOFT_PAUSE" , 0x118000a001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX2_TX003_SOFT_PAUSE" , 0x118000a001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX3_TX000_SOFT_PAUSE" , 0x118000b000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX3_TX001_SOFT_PAUSE" , 0x118000b000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX3_TX002_SOFT_PAUSE" , 0x118000b001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX3_TX003_SOFT_PAUSE" , 0x118000b001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX4_TX000_SOFT_PAUSE" , 0x118000c000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX4_TX001_SOFT_PAUSE" , 0x118000c000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX4_TX002_SOFT_PAUSE" , 0x118000c001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX4_TX003_SOFT_PAUSE" , 0x118000c001a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX0_TX003_STAT0" , 0x1180008001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX1_TX000_STAT0" , 0x1180009000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX1_TX001_STAT0" , 0x1180009000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX1_TX002_STAT0" , 0x1180009001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX1_TX003_STAT0" , 0x1180009001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX2_TX000_STAT0" , 0x118000a000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX2_TX001_STAT0" , 0x118000a000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX2_TX002_STAT0" , 0x118000a001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX2_TX003_STAT0" , 0x118000a001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX3_TX000_STAT0" , 0x118000b000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX3_TX001_STAT0" , 0x118000b000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX3_TX002_STAT0" , 0x118000b001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX3_TX003_STAT0" , 0x118000b001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX4_TX000_STAT0" , 0x118000c000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX4_TX001_STAT0" , 0x118000c000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX4_TX002_STAT0" , 0x118000c001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX4_TX003_STAT0" , 0x118000c001a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX0_TX003_STAT1" , 0x1180008001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX1_TX000_STAT1" , 0x1180009000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX1_TX001_STAT1" , 0x1180009000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX1_TX002_STAT1" , 0x1180009001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX1_TX003_STAT1" , 0x1180009001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX2_TX000_STAT1" , 0x118000a000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX2_TX001_STAT1" , 0x118000a000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX2_TX002_STAT1" , 0x118000a001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX2_TX003_STAT1" , 0x118000a001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX3_TX000_STAT1" , 0x118000b000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX3_TX001_STAT1" , 0x118000b000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX3_TX002_STAT1" , 0x118000b001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX3_TX003_STAT1" , 0x118000b001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX4_TX000_STAT1" , 0x118000c000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX4_TX001_STAT1" , 0x118000c000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX4_TX002_STAT1" , 0x118000c001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX4_TX003_STAT1" , 0x118000c001a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX0_TX003_STAT2" , 0x1180008001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX1_TX000_STAT2" , 0x1180009000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX1_TX001_STAT2" , 0x1180009000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX1_TX002_STAT2" , 0x1180009001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX1_TX003_STAT2" , 0x1180009001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX2_TX000_STAT2" , 0x118000a000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX2_TX001_STAT2" , 0x118000a000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX2_TX002_STAT2" , 0x118000a001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX2_TX003_STAT2" , 0x118000a001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX3_TX000_STAT2" , 0x118000b000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX3_TX001_STAT2" , 0x118000b000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX3_TX002_STAT2" , 0x118000b001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX3_TX003_STAT2" , 0x118000b001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX4_TX000_STAT2" , 0x118000c000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX4_TX001_STAT2" , 0x118000c000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX4_TX002_STAT2" , 0x118000c001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX4_TX003_STAT2" , 0x118000c001a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX0_TX003_STAT3" , 0x1180008001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX1_TX000_STAT3" , 0x1180009000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX1_TX001_STAT3" , 0x1180009000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX1_TX002_STAT3" , 0x1180009001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX1_TX003_STAT3" , 0x1180009001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX2_TX000_STAT3" , 0x118000a000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX2_TX001_STAT3" , 0x118000a000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX2_TX002_STAT3" , 0x118000a001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX2_TX003_STAT3" , 0x118000a001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX3_TX000_STAT3" , 0x118000b000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX3_TX001_STAT3" , 0x118000b000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX3_TX002_STAT3" , 0x118000b001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX3_TX003_STAT3" , 0x118000b001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX4_TX000_STAT3" , 0x118000c000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX4_TX001_STAT3" , 0x118000c000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX4_TX002_STAT3" , 0x118000c001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX4_TX003_STAT3" , 0x118000c001a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX0_TX002_STAT4" , 0x11800080012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX0_TX003_STAT4" , 0x1180008001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX1_TX000_STAT4" , 0x11800090002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX1_TX001_STAT4" , 0x1180009000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX1_TX002_STAT4" , 0x11800090012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX1_TX003_STAT4" , 0x1180009001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX2_TX000_STAT4" , 0x118000a0002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX2_TX001_STAT4" , 0x118000a000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX2_TX002_STAT4" , 0x118000a0012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX2_TX003_STAT4" , 0x118000a001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX3_TX000_STAT4" , 0x118000b0002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX3_TX001_STAT4" , 0x118000b000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX3_TX002_STAT4" , 0x118000b0012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX3_TX003_STAT4" , 0x118000b001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX4_TX000_STAT4" , 0x118000c0002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX4_TX001_STAT4" , 0x118000c000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX4_TX002_STAT4" , 0x118000c0012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX4_TX003_STAT4" , 0x118000c001aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX0_TX002_STAT5" , 0x11800080012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX0_TX003_STAT5" , 0x1180008001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX1_TX000_STAT5" , 0x11800090002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX1_TX001_STAT5" , 0x1180009000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX1_TX002_STAT5" , 0x11800090012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX1_TX003_STAT5" , 0x1180009001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX2_TX000_STAT5" , 0x118000a0002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX2_TX001_STAT5" , 0x118000a000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX2_TX002_STAT5" , 0x118000a0012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX2_TX003_STAT5" , 0x118000a001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX3_TX000_STAT5" , 0x118000b0002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX3_TX001_STAT5" , 0x118000b000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX3_TX002_STAT5" , 0x118000b0012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX3_TX003_STAT5" , 0x118000b001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX4_TX000_STAT5" , 0x118000c0002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX4_TX001_STAT5" , 0x118000c000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX4_TX002_STAT5" , 0x118000c0012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX4_TX003_STAT5" , 0x118000c001aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX0_TX002_STAT6" , 0x11800080012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX0_TX003_STAT6" , 0x1180008001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX1_TX000_STAT6" , 0x11800090002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX1_TX001_STAT6" , 0x1180009000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX1_TX002_STAT6" , 0x11800090012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX1_TX003_STAT6" , 0x1180009001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX2_TX000_STAT6" , 0x118000a0002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX2_TX001_STAT6" , 0x118000a000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX2_TX002_STAT6" , 0x118000a0012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX2_TX003_STAT6" , 0x118000a001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX3_TX000_STAT6" , 0x118000b0002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX3_TX001_STAT6" , 0x118000b000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX3_TX002_STAT6" , 0x118000b0012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX3_TX003_STAT6" , 0x118000b001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX4_TX000_STAT6" , 0x118000c0002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX4_TX001_STAT6" , 0x118000c000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX4_TX002_STAT6" , 0x118000c0012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX4_TX003_STAT6" , 0x118000c001ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX0_TX002_STAT7" , 0x11800080012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX0_TX003_STAT7" , 0x1180008001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX1_TX000_STAT7" , 0x11800090002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX1_TX001_STAT7" , 0x1180009000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX1_TX002_STAT7" , 0x11800090012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX1_TX003_STAT7" , 0x1180009001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX2_TX000_STAT7" , 0x118000a0002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX2_TX001_STAT7" , 0x118000a000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX2_TX002_STAT7" , 0x118000a0012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX2_TX003_STAT7" , 0x118000a001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX3_TX000_STAT7" , 0x118000b0002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX3_TX001_STAT7" , 0x118000b000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX3_TX002_STAT7" , 0x118000b0012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX3_TX003_STAT7" , 0x118000b001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX4_TX000_STAT7" , 0x118000c0002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX4_TX001_STAT7" , 0x118000c000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX4_TX002_STAT7" , 0x118000c0012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX4_TX003_STAT7" , 0x118000c001ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX0_TX002_STAT8" , 0x11800080012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX0_TX003_STAT8" , 0x1180008001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX1_TX000_STAT8" , 0x11800090002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX1_TX001_STAT8" , 0x1180009000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX1_TX002_STAT8" , 0x11800090012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX1_TX003_STAT8" , 0x1180009001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX2_TX000_STAT8" , 0x118000a0002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX2_TX001_STAT8" , 0x118000a000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX2_TX002_STAT8" , 0x118000a0012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX2_TX003_STAT8" , 0x118000a001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX3_TX000_STAT8" , 0x118000b0002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX3_TX001_STAT8" , 0x118000b000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX3_TX002_STAT8" , 0x118000b0012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX3_TX003_STAT8" , 0x118000b001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX4_TX000_STAT8" , 0x118000c0002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX4_TX001_STAT8" , 0x118000c000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX4_TX002_STAT8" , 0x118000c0012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX4_TX003_STAT8" , 0x118000c001ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX0_TX002_STAT9" , 0x11800080012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX0_TX003_STAT9" , 0x1180008001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX1_TX000_STAT9" , 0x11800090002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX1_TX001_STAT9" , 0x1180009000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX1_TX002_STAT9" , 0x11800090012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX1_TX003_STAT9" , 0x1180009001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX2_TX000_STAT9" , 0x118000a0002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX2_TX001_STAT9" , 0x118000a000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX2_TX002_STAT9" , 0x118000a0012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX2_TX003_STAT9" , 0x118000a001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX3_TX000_STAT9" , 0x118000b0002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX3_TX001_STAT9" , 0x118000b000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX3_TX002_STAT9" , 0x118000b0012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX3_TX003_STAT9" , 0x118000b001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX4_TX000_STAT9" , 0x118000c0002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX4_TX001_STAT9" , 0x118000c000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX4_TX002_STAT9" , 0x118000c0012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX4_TX003_STAT9" , 0x118000c001ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX0_TX003_STATS_CTL" , 0x1180008001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX1_TX000_STATS_CTL" , 0x1180009000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX1_TX001_STATS_CTL" , 0x1180009000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX1_TX002_STATS_CTL" , 0x1180009001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX1_TX003_STATS_CTL" , 0x1180009001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX2_TX000_STATS_CTL" , 0x118000a000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX2_TX001_STATS_CTL" , 0x118000a000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX2_TX002_STATS_CTL" , 0x118000a001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX2_TX003_STATS_CTL" , 0x118000a001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX3_TX000_STATS_CTL" , 0x118000b000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX3_TX001_STATS_CTL" , 0x118000b000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX3_TX002_STATS_CTL" , 0x118000b001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX3_TX003_STATS_CTL" , 0x118000b001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX4_TX000_STATS_CTL" , 0x118000c000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX4_TX001_STATS_CTL" , 0x118000c000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX4_TX002_STATS_CTL" , 0x118000c001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX4_TX003_STATS_CTL" , 0x118000c001a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX0_TX003_THRESH" , 0x1180008001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX1_TX000_THRESH" , 0x1180009000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX1_TX001_THRESH" , 0x1180009000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX1_TX002_THRESH" , 0x1180009001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX1_TX003_THRESH" , 0x1180009001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX2_TX000_THRESH" , 0x118000a000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX2_TX001_THRESH" , 0x118000a000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX2_TX002_THRESH" , 0x118000a001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX2_TX003_THRESH" , 0x118000a001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX3_TX000_THRESH" , 0x118000b000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX3_TX001_THRESH" , 0x118000b000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX3_TX002_THRESH" , 0x118000b001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX3_TX003_THRESH" , 0x118000b001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX4_TX000_THRESH" , 0x118000c000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX4_TX001_THRESH" , 0x118000c000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX4_TX002_THRESH" , 0x118000c001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX4_TX003_THRESH" , 0x118000c001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"GMX1_TX_BP" , 0x11800090004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"GMX2_TX_BP" , 0x118000a0004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"GMX3_TX_BP" , 0x118000b0004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"GMX4_TX_BP" , 0x118000c0004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"GMX1_TX_COL_ATTEMPT" , 0x1180009000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"GMX2_TX_COL_ATTEMPT" , 0x118000a000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"GMX3_TX_COL_ATTEMPT" , 0x118000b000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"GMX4_TX_COL_ATTEMPT" , 0x118000c000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"GMX1_TX_CORRUPT" , 0x11800090004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"GMX2_TX_CORRUPT" , 0x118000a0004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"GMX3_TX_CORRUPT" , 0x118000b0004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"GMX4_TX_CORRUPT" , 0x118000c0004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
- {"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"GMX1_TX_HG2_REG1" , 0x1180009000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"GMX2_TX_HG2_REG1" , 0x118000a000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"GMX3_TX_HG2_REG1" , 0x118000b000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"GMX4_TX_HG2_REG1" , 0x118000c000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
- {"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"GMX1_TX_HG2_REG2" , 0x1180009000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"GMX2_TX_HG2_REG2" , 0x118000a000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"GMX3_TX_HG2_REG2" , 0x118000b000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"GMX4_TX_HG2_REG2" , 0x118000c000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"GMX1_TX_IFG" , 0x1180009000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"GMX2_TX_IFG" , 0x118000a000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"GMX3_TX_IFG" , 0x118000b000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"GMX4_TX_IFG" , 0x118000c000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"GMX1_TX_INT_EN" , 0x1180009000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"GMX2_TX_INT_EN" , 0x118000a000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"GMX3_TX_INT_EN" , 0x118000b000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"GMX4_TX_INT_EN" , 0x118000c000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"GMX1_TX_INT_REG" , 0x1180009000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"GMX2_TX_INT_REG" , 0x118000a000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"GMX3_TX_INT_REG" , 0x118000b000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"GMX4_TX_INT_REG" , 0x118000c000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"GMX1_TX_JAM" , 0x1180009000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"GMX2_TX_JAM" , 0x118000a000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"GMX3_TX_JAM" , 0x118000b000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"GMX4_TX_JAM" , 0x118000c000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"GMX1_TX_LFSR" , 0x11800090004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"GMX2_TX_LFSR" , 0x118000a0004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"GMX3_TX_LFSR" , 0x118000b0004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"GMX4_TX_LFSR" , 0x118000c0004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"GMX1_TX_OVR_BP" , 0x11800090004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"GMX2_TX_OVR_BP" , 0x118000a0004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"GMX3_TX_OVR_BP" , 0x118000b0004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"GMX4_TX_OVR_BP" , 0x118000c0004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800090004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"GMX2_TX_PAUSE_PKT_DMAC" , 0x118000a0004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"GMX3_TX_PAUSE_PKT_DMAC" , 0x118000b0004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"GMX4_TX_PAUSE_PKT_DMAC" , 0x118000c0004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800090004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"GMX2_TX_PAUSE_PKT_TYPE" , 0x118000a0004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"GMX3_TX_PAUSE_PKT_TYPE" , 0x118000b0004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"GMX4_TX_PAUSE_PKT_TYPE" , 0x118000c0004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"GMX1_TX_PRTS" , 0x1180009000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"GMX2_TX_PRTS" , 0x118000a000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"GMX3_TX_PRTS" , 0x118000b000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"GMX4_TX_PRTS" , 0x118000c000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"GMX1_TX_XAUI_CTL" , 0x1180009000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"GMX2_TX_XAUI_CTL" , 0x118000a000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"GMX3_TX_XAUI_CTL" , 0x118000b000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"GMX4_TX_XAUI_CTL" , 0x118000c000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"GMX1_XAUI_EXT_LOOPBACK" , 0x1180009000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"GMX2_XAUI_EXT_LOOPBACK" , 0x118000a000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"GMX3_XAUI_EXT_LOOPBACK" , 0x118000b000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"GMX4_XAUI_EXT_LOOPBACK" , 0x118000c000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"GPIO_CLK_QLM0" , 0x10700000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 463},
- {"GPIO_CLK_QLM1" , 0x10700000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 463},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
- {"GPIO_TIM_CTL" , 0x10700000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 466},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 468},
- {"ILK_BIST_SUM" , 0x1180014000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
- {"ILK_GBL_CFG" , 0x1180014000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"ILK_GBL_INT" , 0x1180014000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"ILK_GBL_INT_EN" , 0x1180014000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"ILK_INT_SUM" , 0x1180014000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"ILK_LNE_DBG" , 0x1180014030008ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"ILK_LNE_STS_MSG" , 0x1180014030000ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"ILK_RX0_CFG0" , 0x1180014020000ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"ILK_RX1_CFG0" , 0x1180014024000ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"ILK_RX0_CFG1" , 0x1180014020008ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"ILK_RX1_CFG1" , 0x1180014024008ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"ILK_RX0_FLOW_CTL0" , 0x1180014020090ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"ILK_RX1_FLOW_CTL0" , 0x1180014024090ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"ILK_RX0_FLOW_CTL1" , 0x1180014020098ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"ILK_RX1_FLOW_CTL1" , 0x1180014024098ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"ILK_RX0_IDX_CAL" , 0x11800140200a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"ILK_RX1_IDX_CAL" , 0x11800140240a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"ILK_RX0_IDX_STAT0" , 0x1180014020070ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"ILK_RX1_IDX_STAT0" , 0x1180014024070ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"ILK_RX0_IDX_STAT1" , 0x1180014020078ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"ILK_RX1_IDX_STAT1" , 0x1180014024078ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"ILK_RX0_INT" , 0x1180014020010ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"ILK_RX1_INT" , 0x1180014024010ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"ILK_RX0_INT_EN" , 0x1180014020018ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"ILK_RX1_INT_EN" , 0x1180014024018ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"ILK_RX0_JABBER" , 0x11800140200b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"ILK_RX1_JABBER" , 0x11800140240b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"ILK_RX0_MEM_CAL0" , 0x11800140200a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"ILK_RX1_MEM_CAL0" , 0x11800140240a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"ILK_RX0_MEM_CAL1" , 0x11800140200b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"ILK_RX1_MEM_CAL1" , 0x11800140240b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"ILK_RX0_MEM_STAT0" , 0x1180014020080ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"ILK_RX1_MEM_STAT0" , 0x1180014024080ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"ILK_RX0_MEM_STAT1" , 0x1180014020088ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"ILK_RX1_MEM_STAT1" , 0x1180014024088ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"ILK_RX0_RID" , 0x11800140200c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"ILK_RX1_RID" , 0x11800140240c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"ILK_RX0_STAT0" , 0x1180014020020ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"ILK_RX1_STAT0" , 0x1180014024020ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"ILK_RX0_STAT1" , 0x1180014020028ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"ILK_RX1_STAT1" , 0x1180014024028ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"ILK_RX0_STAT2" , 0x1180014020030ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"ILK_RX1_STAT2" , 0x1180014024030ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"ILK_RX0_STAT3" , 0x1180014020038ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"ILK_RX1_STAT3" , 0x1180014024038ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"ILK_RX0_STAT4" , 0x1180014020040ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"ILK_RX1_STAT4" , 0x1180014024040ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"ILK_RX0_STAT5" , 0x1180014020048ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"ILK_RX1_STAT5" , 0x1180014024048ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"ILK_RX0_STAT6" , 0x1180014020050ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"ILK_RX1_STAT6" , 0x1180014024050ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"ILK_RX0_STAT7" , 0x1180014020058ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"ILK_RX1_STAT7" , 0x1180014024058ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"ILK_RX0_STAT8" , 0x1180014020060ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"ILK_RX1_STAT8" , 0x1180014024060ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"ILK_RX0_STAT9" , 0x1180014020068ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"ILK_RX1_STAT9" , 0x1180014024068ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"ILK_RX_LNE0_CFG" , 0x1180014038000ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE1_CFG" , 0x1180014038400ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE2_CFG" , 0x1180014038800ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE3_CFG" , 0x1180014038c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE4_CFG" , 0x1180014039000ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE5_CFG" , 0x1180014039400ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE6_CFG" , 0x1180014039800ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE7_CFG" , 0x1180014039c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"ILK_RX_LNE0_INT" , 0x1180014038008ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE1_INT" , 0x1180014038408ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE2_INT" , 0x1180014038808ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE3_INT" , 0x1180014038c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE4_INT" , 0x1180014039008ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE5_INT" , 0x1180014039408ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE6_INT" , 0x1180014039808ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE7_INT" , 0x1180014039c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"ILK_RX_LNE0_INT_EN" , 0x1180014038010ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE1_INT_EN" , 0x1180014038410ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE2_INT_EN" , 0x1180014038810ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE3_INT_EN" , 0x1180014038c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE4_INT_EN" , 0x1180014039010ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE5_INT_EN" , 0x1180014039410ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE6_INT_EN" , 0x1180014039810ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE7_INT_EN" , 0x1180014039c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"ILK_RX_LNE0_STAT0" , 0x1180014038018ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE1_STAT0" , 0x1180014038418ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE2_STAT0" , 0x1180014038818ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE3_STAT0" , 0x1180014038c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE4_STAT0" , 0x1180014039018ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE5_STAT0" , 0x1180014039418ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE6_STAT0" , 0x1180014039818ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE7_STAT0" , 0x1180014039c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"ILK_RX_LNE0_STAT1" , 0x1180014038020ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE1_STAT1" , 0x1180014038420ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE2_STAT1" , 0x1180014038820ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE3_STAT1" , 0x1180014038c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE4_STAT1" , 0x1180014039020ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE5_STAT1" , 0x1180014039420ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE6_STAT1" , 0x1180014039820ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE7_STAT1" , 0x1180014039c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"ILK_RX_LNE0_STAT2" , 0x1180014038028ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE1_STAT2" , 0x1180014038428ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE2_STAT2" , 0x1180014038828ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE3_STAT2" , 0x1180014038c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE4_STAT2" , 0x1180014039028ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE5_STAT2" , 0x1180014039428ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE6_STAT2" , 0x1180014039828ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE7_STAT2" , 0x1180014039c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"ILK_RX_LNE0_STAT3" , 0x1180014038030ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE1_STAT3" , 0x1180014038430ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE2_STAT3" , 0x1180014038830ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE3_STAT3" , 0x1180014038c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE4_STAT3" , 0x1180014039030ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE5_STAT3" , 0x1180014039430ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE6_STAT3" , 0x1180014039830ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE7_STAT3" , 0x1180014039c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"ILK_RX_LNE0_STAT4" , 0x1180014038038ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE1_STAT4" , 0x1180014038438ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE2_STAT4" , 0x1180014038838ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE3_STAT4" , 0x1180014038c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE4_STAT4" , 0x1180014039038ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE5_STAT4" , 0x1180014039438ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE6_STAT4" , 0x1180014039838ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE7_STAT4" , 0x1180014039c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"ILK_RX_LNE0_STAT5" , 0x1180014038040ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"ILK_RX_LNE1_STAT5" , 0x1180014038440ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"ILK_RX_LNE2_STAT5" , 0x1180014038840ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"ILK_RX_LNE3_STAT5" , 0x1180014038c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"ILK_RX_LNE4_STAT5" , 0x1180014039040ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"ILK_RX_LNE5_STAT5" , 0x1180014039440ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"ILK_RX_LNE6_STAT5" , 0x1180014039840ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"ILK_RX_LNE7_STAT5" , 0x1180014039c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"ILK_RX_LNE0_STAT6" , 0x1180014038048ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"ILK_RX_LNE1_STAT6" , 0x1180014038448ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"ILK_RX_LNE2_STAT6" , 0x1180014038848ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"ILK_RX_LNE3_STAT6" , 0x1180014038c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"ILK_RX_LNE4_STAT6" , 0x1180014039048ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"ILK_RX_LNE5_STAT6" , 0x1180014039448ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"ILK_RX_LNE6_STAT6" , 0x1180014039848ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"ILK_RX_LNE7_STAT6" , 0x1180014039c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"ILK_RX_LNE0_STAT7" , 0x1180014038050ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"ILK_RX_LNE1_STAT7" , 0x1180014038450ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"ILK_RX_LNE2_STAT7" , 0x1180014038850ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"ILK_RX_LNE3_STAT7" , 0x1180014038c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"ILK_RX_LNE4_STAT7" , 0x1180014039050ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"ILK_RX_LNE5_STAT7" , 0x1180014039450ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"ILK_RX_LNE6_STAT7" , 0x1180014039850ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"ILK_RX_LNE7_STAT7" , 0x1180014039c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"ILK_RX_LNE0_STAT8" , 0x1180014038058ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"ILK_RX_LNE1_STAT8" , 0x1180014038458ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"ILK_RX_LNE2_STAT8" , 0x1180014038858ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"ILK_RX_LNE3_STAT8" , 0x1180014038c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"ILK_RX_LNE4_STAT8" , 0x1180014039058ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"ILK_RX_LNE5_STAT8" , 0x1180014039458ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"ILK_RX_LNE6_STAT8" , 0x1180014039858ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"ILK_RX_LNE7_STAT8" , 0x1180014039c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"ILK_RX_LNE0_STAT9" , 0x1180014038060ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"ILK_RX_LNE1_STAT9" , 0x1180014038460ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"ILK_RX_LNE2_STAT9" , 0x1180014038860ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"ILK_RX_LNE3_STAT9" , 0x1180014038c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"ILK_RX_LNE4_STAT9" , 0x1180014039060ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"ILK_RX_LNE5_STAT9" , 0x1180014039460ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"ILK_RX_LNE6_STAT9" , 0x1180014039860ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"ILK_RX_LNE7_STAT9" , 0x1180014039c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"ILK_RXF_IDX_PMAP" , 0x1180014000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"ILK_RXF_MEM_PMAP" , 0x1180014000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"ILK_SER_CFG" , 0x1180014000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"ILK_TX0_CFG0" , 0x1180014010000ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"ILK_TX1_CFG0" , 0x1180014014000ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"ILK_TX0_CFG1" , 0x1180014010008ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"ILK_TX1_CFG1" , 0x1180014014008ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"ILK_TX0_DBG" , 0x1180014010070ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"ILK_TX1_DBG" , 0x1180014014070ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"ILK_TX0_FLOW_CTL0" , 0x1180014010048ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"ILK_TX1_FLOW_CTL0" , 0x1180014014048ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"ILK_TX0_FLOW_CTL1" , 0x1180014010050ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"ILK_TX1_FLOW_CTL1" , 0x1180014014050ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"ILK_TX0_IDX_CAL" , 0x1180014010058ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"ILK_TX1_IDX_CAL" , 0x1180014014058ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"ILK_TX0_IDX_PMAP" , 0x1180014010010ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"ILK_TX1_IDX_PMAP" , 0x1180014014010ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"ILK_TX0_IDX_STAT0" , 0x1180014010020ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"ILK_TX1_IDX_STAT0" , 0x1180014014020ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"ILK_TX0_IDX_STAT1" , 0x1180014010028ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"ILK_TX1_IDX_STAT1" , 0x1180014014028ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"ILK_TX0_INT" , 0x1180014010078ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"ILK_TX1_INT" , 0x1180014014078ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"ILK_TX0_INT_EN" , 0x1180014010080ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"ILK_TX1_INT_EN" , 0x1180014014080ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"ILK_TX0_MEM_CAL0" , 0x1180014010060ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"ILK_TX1_MEM_CAL0" , 0x1180014014060ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"ILK_TX0_MEM_CAL1" , 0x1180014010068ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"ILK_TX1_MEM_CAL1" , 0x1180014014068ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"ILK_TX0_MEM_PMAP" , 0x1180014010018ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"ILK_TX1_MEM_PMAP" , 0x1180014014018ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"ILK_TX0_MEM_STAT0" , 0x1180014010030ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"ILK_TX1_MEM_STAT0" , 0x1180014014030ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"ILK_TX0_MEM_STAT1" , 0x1180014010038ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"ILK_TX1_MEM_STAT1" , 0x1180014014038ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"ILK_TX0_PIPE" , 0x1180014010088ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"ILK_TX1_PIPE" , 0x1180014014088ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"ILK_TX0_RMATCH" , 0x1180014010040ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"ILK_TX1_RMATCH" , 0x1180014014040ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"IOB1_BIST_STATUS" , 0x11800f00107f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"IOB1_CTL_STATUS" , 0x11800f0010050ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"IOB1_TO_CMB_CREDITS" , 0x11800f00100b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"IOB_TO_CMB_CREDITS" , 0x11800f00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"IOB_TO_NCB_DID_00_CREDITS" , 0x11800f0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"IOB_TO_NCB_DID_111_CREDITS" , 0x11800f0000b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"IOB_TO_NCB_DID_223_CREDITS" , 0x11800f0000ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"IOB_TO_NCB_DID_24_CREDITS" , 0x11800f00008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"IOB_TO_NCB_DID_32_CREDITS" , 0x11800f0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"IOB_TO_NCB_DID_40_CREDITS" , 0x11800f0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"IOB_TO_NCB_DID_55_CREDITS" , 0x11800f00009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"IOB_TO_NCB_DID_64_CREDITS" , 0x11800f0000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {"IOB_TO_NCB_DID_79_CREDITS" , 0x11800f0000a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
- {"IOB_TO_NCB_DID_96_CREDITS" , 0x11800f0000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
- {"IOB_TO_NCB_DID_98_CREDITS" , 0x11800f0000b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 567},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 568},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 569},
- {"IPD_BPID0_MBUF_TH" , 0x14f0000002000ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID1_MBUF_TH" , 0x14f0000002008ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID2_MBUF_TH" , 0x14f0000002010ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID3_MBUF_TH" , 0x14f0000002018ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID4_MBUF_TH" , 0x14f0000002020ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID5_MBUF_TH" , 0x14f0000002028ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID6_MBUF_TH" , 0x14f0000002030ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID7_MBUF_TH" , 0x14f0000002038ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID8_MBUF_TH" , 0x14f0000002040ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID9_MBUF_TH" , 0x14f0000002048ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID10_MBUF_TH" , 0x14f0000002050ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID11_MBUF_TH" , 0x14f0000002058ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID12_MBUF_TH" , 0x14f0000002060ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID13_MBUF_TH" , 0x14f0000002068ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID14_MBUF_TH" , 0x14f0000002070ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID15_MBUF_TH" , 0x14f0000002078ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID16_MBUF_TH" , 0x14f0000002080ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID17_MBUF_TH" , 0x14f0000002088ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID18_MBUF_TH" , 0x14f0000002090ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID19_MBUF_TH" , 0x14f0000002098ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID20_MBUF_TH" , 0x14f00000020a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID21_MBUF_TH" , 0x14f00000020a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID22_MBUF_TH" , 0x14f00000020b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID23_MBUF_TH" , 0x14f00000020b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID24_MBUF_TH" , 0x14f00000020c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID25_MBUF_TH" , 0x14f00000020c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID26_MBUF_TH" , 0x14f00000020d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID27_MBUF_TH" , 0x14f00000020d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID28_MBUF_TH" , 0x14f00000020e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID29_MBUF_TH" , 0x14f00000020e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID30_MBUF_TH" , 0x14f00000020f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID31_MBUF_TH" , 0x14f00000020f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID32_MBUF_TH" , 0x14f0000002100ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID33_MBUF_TH" , 0x14f0000002108ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID34_MBUF_TH" , 0x14f0000002110ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID35_MBUF_TH" , 0x14f0000002118ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID36_MBUF_TH" , 0x14f0000002120ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID37_MBUF_TH" , 0x14f0000002128ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID38_MBUF_TH" , 0x14f0000002130ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID39_MBUF_TH" , 0x14f0000002138ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID40_MBUF_TH" , 0x14f0000002140ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID41_MBUF_TH" , 0x14f0000002148ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID42_MBUF_TH" , 0x14f0000002150ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID43_MBUF_TH" , 0x14f0000002158ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID44_MBUF_TH" , 0x14f0000002160ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID45_MBUF_TH" , 0x14f0000002168ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID46_MBUF_TH" , 0x14f0000002170ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID47_MBUF_TH" , 0x14f0000002178ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID48_MBUF_TH" , 0x14f0000002180ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID49_MBUF_TH" , 0x14f0000002188ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID50_MBUF_TH" , 0x14f0000002190ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID51_MBUF_TH" , 0x14f0000002198ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID52_MBUF_TH" , 0x14f00000021a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID53_MBUF_TH" , 0x14f00000021a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID54_MBUF_TH" , 0x14f00000021b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID55_MBUF_TH" , 0x14f00000021b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID56_MBUF_TH" , 0x14f00000021c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID57_MBUF_TH" , 0x14f00000021c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID58_MBUF_TH" , 0x14f00000021d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID59_MBUF_TH" , 0x14f00000021d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID60_MBUF_TH" , 0x14f00000021e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID61_MBUF_TH" , 0x14f00000021e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID62_MBUF_TH" , 0x14f00000021f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID63_MBUF_TH" , 0x14f00000021f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
- {"IPD_BPID_BP_COUNTER0" , 0x14f0000003000ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER1" , 0x14f0000003008ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER2" , 0x14f0000003010ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER3" , 0x14f0000003018ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER4" , 0x14f0000003020ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER5" , 0x14f0000003028ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER6" , 0x14f0000003030ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER7" , 0x14f0000003038ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER8" , 0x14f0000003040ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER9" , 0x14f0000003048ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER10" , 0x14f0000003050ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER11" , 0x14f0000003058ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER12" , 0x14f0000003060ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER13" , 0x14f0000003068ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER14" , 0x14f0000003070ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER15" , 0x14f0000003078ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER16" , 0x14f0000003080ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER17" , 0x14f0000003088ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER18" , 0x14f0000003090ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER19" , 0x14f0000003098ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER20" , 0x14f00000030a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER21" , 0x14f00000030a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER22" , 0x14f00000030b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER23" , 0x14f00000030b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER24" , 0x14f00000030c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER25" , 0x14f00000030c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER26" , 0x14f00000030d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER27" , 0x14f00000030d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER28" , 0x14f00000030e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER29" , 0x14f00000030e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER30" , 0x14f00000030f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER31" , 0x14f00000030f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER32" , 0x14f0000003100ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER33" , 0x14f0000003108ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER34" , 0x14f0000003110ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER35" , 0x14f0000003118ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER36" , 0x14f0000003120ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER37" , 0x14f0000003128ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER38" , 0x14f0000003130ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER39" , 0x14f0000003138ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER40" , 0x14f0000003140ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER41" , 0x14f0000003148ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER42" , 0x14f0000003150ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER43" , 0x14f0000003158ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER44" , 0x14f0000003160ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER45" , 0x14f0000003168ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER46" , 0x14f0000003170ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER47" , 0x14f0000003178ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER48" , 0x14f0000003180ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER49" , 0x14f0000003188ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER50" , 0x14f0000003190ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER51" , 0x14f0000003198ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER52" , 0x14f00000031a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER53" , 0x14f00000031a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER54" , 0x14f00000031b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER55" , 0x14f00000031b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER56" , 0x14f00000031c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER57" , 0x14f00000031c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER58" , 0x14f00000031d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER59" , 0x14f00000031d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER60" , 0x14f00000031e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER61" , 0x14f00000031e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER62" , 0x14f00000031f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_BPID_BP_COUNTER63" , 0x14f00000031f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 572},
- {"IPD_CREDITS" , 0x14f0000004410ull, CVMX_CSR_DB_TYPE_NCB, 64, 573},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 574},
- {"IPD_ECC_CTL" , 0x14f0000004408ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
- {"IPD_FREE_PTR_FIFO_CTL" , 0x14f0000000780ull, CVMX_CSR_DB_TYPE_NCB, 64, 576},
- {"IPD_FREE_PTR_VALUE" , 0x14f0000000788ull, CVMX_CSR_DB_TYPE_NCB, 64, 577},
- {"IPD_HOLD_PTR_FIFO_CTL" , 0x14f0000000790ull, CVMX_CSR_DB_TYPE_NCB, 64, 578},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 579},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 580},
- {"IPD_NEXT_PKT_PTR" , 0x14f00000007a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 581},
- {"IPD_NEXT_WQE_PTR" , 0x14f00000007a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 582},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
- {"IPD_ON_BP_DROP_PKT0" , 0x14f0000004100ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
- {"IPD_PKT_ERR" , 0x14f00000003f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 586},
- {"IPD_PORT_PTR_FIFO_CTL" , 0x14f0000000798ull, CVMX_CSR_DB_TYPE_NCB, 64, 587},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_32_CNT" , 0x14f0000000988ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_33_CNT" , 0x14f0000000990ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_34_CNT" , 0x14f0000000998ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_35_CNT" , 0x14f00000009a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_36_CNT" , 0x14f00000009a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_37_CNT" , 0x14f00000009b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_38_CNT" , 0x14f00000009b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_39_CNT" , 0x14f00000009c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_40_CNT" , 0x14f00000009c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_41_CNT" , 0x14f00000009d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_42_CNT" , 0x14f00000009d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_43_CNT" , 0x14f00000009e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_44_CNT" , 0x14f00000009e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_45_CNT" , 0x14f00000009f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_46_CNT" , 0x14f00000009f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_47_CNT" , 0x14f0000000a00ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_48_CNT" , 0x14f0000000a08ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_49_CNT" , 0x14f0000000a10ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_50_CNT" , 0x14f0000000a18ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_51_CNT" , 0x14f0000000a20ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_52_CNT" , 0x14f0000000a28ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_53_CNT" , 0x14f0000000a30ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_54_CNT" , 0x14f0000000a38ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_55_CNT" , 0x14f0000000a40ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_56_CNT" , 0x14f0000000a48ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_57_CNT" , 0x14f0000000a50ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_58_CNT" , 0x14f0000000a58ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_59_CNT" , 0x14f0000000a60ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_60_CNT" , 0x14f0000000a68ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_61_CNT" , 0x14f0000000a70ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_62_CNT" , 0x14f0000000a78ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_63_CNT" , 0x14f0000000a80ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_64_CNT" , 0x14f0000000a88ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_65_CNT" , 0x14f0000000a90ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_66_CNT" , 0x14f0000000a98ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_67_CNT" , 0x14f0000000aa0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_68_CNT" , 0x14f0000000aa8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_69_CNT" , 0x14f0000000ab0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_70_CNT" , 0x14f0000000ab8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_71_CNT" , 0x14f0000000ac0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_72_CNT" , 0x14f0000000ac8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_73_CNT" , 0x14f0000000ad0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_74_CNT" , 0x14f0000000ad8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_75_CNT" , 0x14f0000000ae0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_76_CNT" , 0x14f0000000ae8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_77_CNT" , 0x14f0000000af0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_78_CNT" , 0x14f0000000af8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_79_CNT" , 0x14f0000000b00ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_80_CNT" , 0x14f0000000b08ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_81_CNT" , 0x14f0000000b10ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_82_CNT" , 0x14f0000000b18ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_83_CNT" , 0x14f0000000b20ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_84_CNT" , 0x14f0000000b28ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_85_CNT" , 0x14f0000000b30ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_86_CNT" , 0x14f0000000b38ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_87_CNT" , 0x14f0000000b40ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_88_CNT" , 0x14f0000000b48ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_89_CNT" , 0x14f0000000b50ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_90_CNT" , 0x14f0000000b58ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_91_CNT" , 0x14f0000000b60ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_92_CNT" , 0x14f0000000b68ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_93_CNT" , 0x14f0000000b70ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_94_CNT" , 0x14f0000000b78ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_95_CNT" , 0x14f0000000b80ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_96_CNT" , 0x14f0000000b88ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_97_CNT" , 0x14f0000000b90ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_98_CNT" , 0x14f0000000b98ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_99_CNT" , 0x14f0000000ba0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_100_CNT" , 0x14f0000000ba8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_101_CNT" , 0x14f0000000bb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_102_CNT" , 0x14f0000000bb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_103_CNT" , 0x14f0000000bc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_104_CNT" , 0x14f0000000bc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_105_CNT" , 0x14f0000000bd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_106_CNT" , 0x14f0000000bd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_107_CNT" , 0x14f0000000be0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_108_CNT" , 0x14f0000000be8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_109_CNT" , 0x14f0000000bf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_110_CNT" , 0x14f0000000bf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_111_CNT" , 0x14f0000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_112_CNT" , 0x14f0000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_113_CNT" , 0x14f0000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_114_CNT" , 0x14f0000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_115_CNT" , 0x14f0000000c20ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_116_CNT" , 0x14f0000000c28ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_117_CNT" , 0x14f0000000c30ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_118_CNT" , 0x14f0000000c38ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_119_CNT" , 0x14f0000000c40ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_120_CNT" , 0x14f0000000c48ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_121_CNT" , 0x14f0000000c50ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_122_CNT" , 0x14f0000000c58ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_123_CNT" , 0x14f0000000c60ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_124_CNT" , 0x14f0000000c68ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_125_CNT" , 0x14f0000000c70ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_126_CNT" , 0x14f0000000c78ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_127_CNT" , 0x14f0000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_128_CNT" , 0x14f0000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_129_CNT" , 0x14f0000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_130_CNT" , 0x14f0000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_131_CNT" , 0x14f0000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_132_CNT" , 0x14f0000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_133_CNT" , 0x14f0000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_134_CNT" , 0x14f0000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_135_CNT" , 0x14f0000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_136_CNT" , 0x14f0000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_137_CNT" , 0x14f0000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_138_CNT" , 0x14f0000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_139_CNT" , 0x14f0000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_140_CNT" , 0x14f0000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_141_CNT" , 0x14f0000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_142_CNT" , 0x14f0000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_143_CNT" , 0x14f0000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_144_CNT" , 0x14f0000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_145_CNT" , 0x14f0000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_146_CNT" , 0x14f0000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_147_CNT" , 0x14f0000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_148_CNT" , 0x14f0000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_149_CNT" , 0x14f0000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_150_CNT" , 0x14f0000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_151_CNT" , 0x14f0000000d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_152_CNT" , 0x14f0000000d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_153_CNT" , 0x14f0000000d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_154_CNT" , 0x14f0000000d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_155_CNT" , 0x14f0000000d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_156_CNT" , 0x14f0000000d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_157_CNT" , 0x14f0000000d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_158_CNT" , 0x14f0000000d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_159_CNT" , 0x14f0000000d80ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_160_CNT" , 0x14f0000000d88ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_161_CNT" , 0x14f0000000d90ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_162_CNT" , 0x14f0000000d98ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_163_CNT" , 0x14f0000000da0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_164_CNT" , 0x14f0000000da8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_165_CNT" , 0x14f0000000db0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_166_CNT" , 0x14f0000000db8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_167_CNT" , 0x14f0000000dc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_168_CNT" , 0x14f0000000dc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_169_CNT" , 0x14f0000000dd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_170_CNT" , 0x14f0000000dd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_171_CNT" , 0x14f0000000de0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_172_CNT" , 0x14f0000000de8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_173_CNT" , 0x14f0000000df0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_174_CNT" , 0x14f0000000df8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_175_CNT" , 0x14f0000000e00ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_176_CNT" , 0x14f0000000e08ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_177_CNT" , 0x14f0000000e10ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_178_CNT" , 0x14f0000000e18ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_179_CNT" , 0x14f0000000e20ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_180_CNT" , 0x14f0000000e28ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_181_CNT" , 0x14f0000000e30ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_182_CNT" , 0x14f0000000e38ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_183_CNT" , 0x14f0000000e40ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_184_CNT" , 0x14f0000000e48ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_185_CNT" , 0x14f0000000e50ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_186_CNT" , 0x14f0000000e58ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_187_CNT" , 0x14f0000000e60ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_188_CNT" , 0x14f0000000e68ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_189_CNT" , 0x14f0000000e70ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_190_CNT" , 0x14f0000000e78ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_191_CNT" , 0x14f0000000e80ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_192_CNT" , 0x14f0000000e88ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_193_CNT" , 0x14f0000000e90ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_194_CNT" , 0x14f0000000e98ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_195_CNT" , 0x14f0000000ea0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_196_CNT" , 0x14f0000000ea8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_197_CNT" , 0x14f0000000eb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_198_CNT" , 0x14f0000000eb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_199_CNT" , 0x14f0000000ec0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_200_CNT" , 0x14f0000000ec8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_201_CNT" , 0x14f0000000ed0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_202_CNT" , 0x14f0000000ed8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_203_CNT" , 0x14f0000000ee0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_204_CNT" , 0x14f0000000ee8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_205_CNT" , 0x14f0000000ef0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_206_CNT" , 0x14f0000000ef8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_207_CNT" , 0x14f0000000f00ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_208_CNT" , 0x14f0000000f08ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_209_CNT" , 0x14f0000000f10ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_210_CNT" , 0x14f0000000f18ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_211_CNT" , 0x14f0000000f20ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_212_CNT" , 0x14f0000000f28ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_213_CNT" , 0x14f0000000f30ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_214_CNT" , 0x14f0000000f38ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_215_CNT" , 0x14f0000000f40ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_216_CNT" , 0x14f0000000f48ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_217_CNT" , 0x14f0000000f50ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_218_CNT" , 0x14f0000000f58ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_219_CNT" , 0x14f0000000f60ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_220_CNT" , 0x14f0000000f68ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_221_CNT" , 0x14f0000000f70ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_222_CNT" , 0x14f0000000f78ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_223_CNT" , 0x14f0000000f80ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_224_CNT" , 0x14f0000000f88ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_225_CNT" , 0x14f0000000f90ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_226_CNT" , 0x14f0000000f98ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_227_CNT" , 0x14f0000000fa0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_228_CNT" , 0x14f0000000fa8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_229_CNT" , 0x14f0000000fb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_230_CNT" , 0x14f0000000fb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_231_CNT" , 0x14f0000000fc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_232_CNT" , 0x14f0000000fc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_233_CNT" , 0x14f0000000fd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_234_CNT" , 0x14f0000000fd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_235_CNT" , 0x14f0000000fe0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_236_CNT" , 0x14f0000000fe8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_237_CNT" , 0x14f0000000ff0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_238_CNT" , 0x14f0000000ff8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_239_CNT" , 0x14f0000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_240_CNT" , 0x14f0000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_241_CNT" , 0x14f0000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_242_CNT" , 0x14f0000001018ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_243_CNT" , 0x14f0000001020ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_244_CNT" , 0x14f0000001028ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_245_CNT" , 0x14f0000001030ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_246_CNT" , 0x14f0000001038ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_247_CNT" , 0x14f0000001040ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_248_CNT" , 0x14f0000001048ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_249_CNT" , 0x14f0000001050ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_250_CNT" , 0x14f0000001058ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_251_CNT" , 0x14f0000001060ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_252_CNT" , 0x14f0000001068ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_253_CNT" , 0x14f0000001070ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_254_CNT" , 0x14f0000001078ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_255_CNT" , 0x14f0000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_256_CNT" , 0x14f0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_257_CNT" , 0x14f0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_258_CNT" , 0x14f0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_259_CNT" , 0x14f00000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_260_CNT" , 0x14f00000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_261_CNT" , 0x14f00000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_262_CNT" , 0x14f00000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_263_CNT" , 0x14f00000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_264_CNT" , 0x14f00000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_265_CNT" , 0x14f00000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_266_CNT" , 0x14f00000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_267_CNT" , 0x14f00000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_268_CNT" , 0x14f00000010e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_269_CNT" , 0x14f00000010f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_270_CNT" , 0x14f00000010f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_271_CNT" , 0x14f0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_272_CNT" , 0x14f0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_273_CNT" , 0x14f0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_274_CNT" , 0x14f0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_275_CNT" , 0x14f0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_276_CNT" , 0x14f0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_277_CNT" , 0x14f0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_278_CNT" , 0x14f0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_279_CNT" , 0x14f0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_280_CNT" , 0x14f0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_281_CNT" , 0x14f0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_282_CNT" , 0x14f0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_283_CNT" , 0x14f0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_284_CNT" , 0x14f0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_285_CNT" , 0x14f0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_286_CNT" , 0x14f0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_287_CNT" , 0x14f0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_320_CNT" , 0x14f0000001288ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_321_CNT" , 0x14f0000001290ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_322_CNT" , 0x14f0000001298ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_323_CNT" , 0x14f00000012a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_324_CNT" , 0x14f00000012a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_325_CNT" , 0x14f00000012b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_326_CNT" , 0x14f00000012b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_327_CNT" , 0x14f00000012c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_328_CNT" , 0x14f00000012c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_329_CNT" , 0x14f00000012d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_330_CNT" , 0x14f00000012d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_331_CNT" , 0x14f00000012e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_332_CNT" , 0x14f00000012e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_333_CNT" , 0x14f00000012f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_334_CNT" , 0x14f00000012f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_335_CNT" , 0x14f0000001300ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_336_CNT" , 0x14f0000001308ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_337_CNT" , 0x14f0000001310ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_338_CNT" , 0x14f0000001318ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_339_CNT" , 0x14f0000001320ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_340_CNT" , 0x14f0000001328ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_341_CNT" , 0x14f0000001330ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_342_CNT" , 0x14f0000001338ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_343_CNT" , 0x14f0000001340ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_344_CNT" , 0x14f0000001348ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_345_CNT" , 0x14f0000001350ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_346_CNT" , 0x14f0000001358ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_347_CNT" , 0x14f0000001360ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_348_CNT" , 0x14f0000001368ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_349_CNT" , 0x14f0000001370ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_350_CNT" , 0x14f0000001378ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_351_CNT" , 0x14f0000001380ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_352_CNT" , 0x14f0000001388ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_353_CNT" , 0x14f0000001390ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_354_CNT" , 0x14f0000001398ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_355_CNT" , 0x14f00000013a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_356_CNT" , 0x14f00000013a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_357_CNT" , 0x14f00000013b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_358_CNT" , 0x14f00000013b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_359_CNT" , 0x14f00000013c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_360_CNT" , 0x14f00000013c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_361_CNT" , 0x14f00000013d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_362_CNT" , 0x14f00000013d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_363_CNT" , 0x14f00000013e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_364_CNT" , 0x14f00000013e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_365_CNT" , 0x14f00000013f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_366_CNT" , 0x14f00000013f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_367_CNT" , 0x14f0000001400ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_368_CNT" , 0x14f0000001408ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_369_CNT" , 0x14f0000001410ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_370_CNT" , 0x14f0000001418ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_371_CNT" , 0x14f0000001420ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_372_CNT" , 0x14f0000001428ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_373_CNT" , 0x14f0000001430ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_374_CNT" , 0x14f0000001438ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_375_CNT" , 0x14f0000001440ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_376_CNT" , 0x14f0000001448ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_377_CNT" , 0x14f0000001450ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_378_CNT" , 0x14f0000001458ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_379_CNT" , 0x14f0000001460ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_380_CNT" , 0x14f0000001468ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_381_CNT" , 0x14f0000001470ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_382_CNT" , 0x14f0000001478ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_383_CNT" , 0x14f0000001480ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_384_CNT" , 0x14f0000001488ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_385_CNT" , 0x14f0000001490ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_386_CNT" , 0x14f0000001498ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_387_CNT" , 0x14f00000014a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_388_CNT" , 0x14f00000014a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_389_CNT" , 0x14f00000014b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_390_CNT" , 0x14f00000014b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_391_CNT" , 0x14f00000014c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_392_CNT" , 0x14f00000014c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_393_CNT" , 0x14f00000014d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_394_CNT" , 0x14f00000014d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_395_CNT" , 0x14f00000014e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_396_CNT" , 0x14f00000014e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_397_CNT" , 0x14f00000014f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_398_CNT" , 0x14f00000014f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_399_CNT" , 0x14f0000001500ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_400_CNT" , 0x14f0000001508ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_401_CNT" , 0x14f0000001510ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_402_CNT" , 0x14f0000001518ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_403_CNT" , 0x14f0000001520ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_404_CNT" , 0x14f0000001528ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_405_CNT" , 0x14f0000001530ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_406_CNT" , 0x14f0000001538ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_407_CNT" , 0x14f0000001540ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_408_CNT" , 0x14f0000001548ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_409_CNT" , 0x14f0000001550ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_410_CNT" , 0x14f0000001558ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_411_CNT" , 0x14f0000001560ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_412_CNT" , 0x14f0000001568ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_413_CNT" , 0x14f0000001570ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_414_CNT" , 0x14f0000001578ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_415_CNT" , 0x14f0000001580ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_416_CNT" , 0x14f0000001588ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_417_CNT" , 0x14f0000001590ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_418_CNT" , 0x14f0000001598ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_419_CNT" , 0x14f00000015a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_420_CNT" , 0x14f00000015a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_421_CNT" , 0x14f00000015b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_422_CNT" , 0x14f00000015b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_423_CNT" , 0x14f00000015c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_424_CNT" , 0x14f00000015c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_425_CNT" , 0x14f00000015d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_426_CNT" , 0x14f00000015d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_427_CNT" , 0x14f00000015e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_428_CNT" , 0x14f00000015e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_429_CNT" , 0x14f00000015f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_430_CNT" , 0x14f00000015f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_431_CNT" , 0x14f0000001600ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_432_CNT" , 0x14f0000001608ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_433_CNT" , 0x14f0000001610ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_434_CNT" , 0x14f0000001618ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_435_CNT" , 0x14f0000001620ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_436_CNT" , 0x14f0000001628ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_437_CNT" , 0x14f0000001630ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_438_CNT" , 0x14f0000001638ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_439_CNT" , 0x14f0000001640ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_440_CNT" , 0x14f0000001648ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_441_CNT" , 0x14f0000001650ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_442_CNT" , 0x14f0000001658ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_443_CNT" , 0x14f0000001660ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_444_CNT" , 0x14f0000001668ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_445_CNT" , 0x14f0000001670ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_446_CNT" , 0x14f0000001678ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_447_CNT" , 0x14f0000001680ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_448_CNT" , 0x14f0000001688ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_449_CNT" , 0x14f0000001690ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_450_CNT" , 0x14f0000001698ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_451_CNT" , 0x14f00000016a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_452_CNT" , 0x14f00000016a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_453_CNT" , 0x14f00000016b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_454_CNT" , 0x14f00000016b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_455_CNT" , 0x14f00000016c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_456_CNT" , 0x14f00000016c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_457_CNT" , 0x14f00000016d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_458_CNT" , 0x14f00000016d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_459_CNT" , 0x14f00000016e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_460_CNT" , 0x14f00000016e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_461_CNT" , 0x14f00000016f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_462_CNT" , 0x14f00000016f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_463_CNT" , 0x14f0000001700ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_464_CNT" , 0x14f0000001708ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_465_CNT" , 0x14f0000001710ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_466_CNT" , 0x14f0000001718ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_467_CNT" , 0x14f0000001720ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_468_CNT" , 0x14f0000001728ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_469_CNT" , 0x14f0000001730ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_470_CNT" , 0x14f0000001738ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_471_CNT" , 0x14f0000001740ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_472_CNT" , 0x14f0000001748ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_473_CNT" , 0x14f0000001750ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_474_CNT" , 0x14f0000001758ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_475_CNT" , 0x14f0000001760ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_476_CNT" , 0x14f0000001768ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_477_CNT" , 0x14f0000001770ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_478_CNT" , 0x14f0000001778ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_479_CNT" , 0x14f0000001780ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_480_CNT" , 0x14f0000001788ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_481_CNT" , 0x14f0000001790ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_482_CNT" , 0x14f0000001798ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_483_CNT" , 0x14f00000017a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_484_CNT" , 0x14f00000017a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_485_CNT" , 0x14f00000017b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_486_CNT" , 0x14f00000017b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_487_CNT" , 0x14f00000017c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_488_CNT" , 0x14f00000017c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_489_CNT" , 0x14f00000017d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_490_CNT" , 0x14f00000017d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_491_CNT" , 0x14f00000017e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_492_CNT" , 0x14f00000017e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_493_CNT" , 0x14f00000017f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_494_CNT" , 0x14f00000017f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_495_CNT" , 0x14f0000001800ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_496_CNT" , 0x14f0000001808ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_497_CNT" , 0x14f0000001810ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_498_CNT" , 0x14f0000001818ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_499_CNT" , 0x14f0000001820ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_500_CNT" , 0x14f0000001828ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_501_CNT" , 0x14f0000001830ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_502_CNT" , 0x14f0000001838ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_503_CNT" , 0x14f0000001840ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_504_CNT" , 0x14f0000001848ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_505_CNT" , 0x14f0000001850ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_506_CNT" , 0x14f0000001858ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_507_CNT" , 0x14f0000001860ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_508_CNT" , 0x14f0000001868ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_509_CNT" , 0x14f0000001870ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_510_CNT" , 0x14f0000001878ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_511_CNT" , 0x14f0000001880ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"IPD_PORT_QOS_INT1" , 0x14f0000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"IPD_PORT_QOS_INT2" , 0x14f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"IPD_PORT_QOS_INT3" , 0x14f0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"IPD_PORT_QOS_INT5" , 0x14f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"IPD_PORT_QOS_INT6" , 0x14f0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"IPD_PORT_QOS_INT7" , 0x14f0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"IPD_PORT_QOS_INT_ENB1" , 0x14f0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"IPD_PORT_QOS_INT_ENB2" , 0x14f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"IPD_PORT_QOS_INT_ENB3" , 0x14f0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"IPD_PORT_QOS_INT_ENB5" , 0x14f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"IPD_PORT_QOS_INT_ENB6" , 0x14f0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"IPD_PORT_QOS_INT_ENB7" , 0x14f0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
- {"IPD_PORT_SOP0" , 0x14f0000004400ull, CVMX_CSR_DB_TYPE_NCB, 64, 591},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
- {"IPD_RED_BPID_ENABLE0" , 0x14f0000004200ull, CVMX_CSR_DB_TYPE_NCB, 64, 595},
- {"IPD_RED_DELAY" , 0x14f0000004300ull, CVMX_CSR_DB_TYPE_NCB, 64, 596},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
- {"IPD_REQ_WGT" , 0x14f0000004418ull, CVMX_CSR_DB_TYPE_NCB, 64, 598},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 599},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 600},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 601},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"L2C_BIG_CTL" , 0x1180080800030ull, CVMX_CSR_DB_TYPE_RSL, 64, 606},
- {"L2C_BST" , 0x11800808007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"L2C_BST_MEM0" , 0x1180080c007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {"L2C_BST_MEM1" , 0x1180080c407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {"L2C_BST_MEM2" , 0x1180080c807f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {"L2C_BST_MEM3" , 0x1180080cc07f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {"L2C_BST_TDT0" , 0x1180080a007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
- {"L2C_BST_TDT1" , 0x1180080a407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
- {"L2C_BST_TDT2" , 0x1180080a807f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
- {"L2C_BST_TDT3" , 0x1180080ac07f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
- {"L2C_BST_TTG0" , 0x1180080a007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
- {"L2C_BST_TTG1" , 0x1180080a407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
- {"L2C_BST_TTG2" , 0x1180080a807f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
- {"L2C_BST_TTG3" , 0x1180080ac07f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
- {"L2C_COP0_MAP0" , 0x1180080940000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1" , 0x1180080940008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2" , 0x1180080940010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3" , 0x1180080940018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4" , 0x1180080940020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5" , 0x1180080940028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6" , 0x1180080940030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7" , 0x1180080940038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8" , 0x1180080940040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP9" , 0x1180080940048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP10" , 0x1180080940050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP11" , 0x1180080940058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP12" , 0x1180080940060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP13" , 0x1180080940068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP14" , 0x1180080940070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP15" , 0x1180080940078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16" , 0x1180080940080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP17" , 0x1180080940088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP18" , 0x1180080940090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP19" , 0x1180080940098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP20" , 0x11800809400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP21" , 0x11800809400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP22" , 0x11800809400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP23" , 0x11800809400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP24" , 0x11800809400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP25" , 0x11800809400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP26" , 0x11800809400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP27" , 0x11800809400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP28" , 0x11800809400e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP29" , 0x11800809400e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP30" , 0x11800809400f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP31" , 0x11800809400f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP32" , 0x1180080940100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP33" , 0x1180080940108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP34" , 0x1180080940110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP35" , 0x1180080940118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP36" , 0x1180080940120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP37" , 0x1180080940128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP38" , 0x1180080940130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP39" , 0x1180080940138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP40" , 0x1180080940140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP41" , 0x1180080940148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP42" , 0x1180080940150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP43" , 0x1180080940158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP44" , 0x1180080940160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP45" , 0x1180080940168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP46" , 0x1180080940170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP47" , 0x1180080940178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP48" , 0x1180080940180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP49" , 0x1180080940188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP50" , 0x1180080940190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP51" , 0x1180080940198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP52" , 0x11800809401a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP53" , 0x11800809401a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP54" , 0x11800809401b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP55" , 0x11800809401b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP56" , 0x11800809401c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP57" , 0x11800809401c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP58" , 0x11800809401d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP59" , 0x11800809401d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP60" , 0x11800809401e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP61" , 0x11800809401e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP62" , 0x11800809401f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP63" , 0x11800809401f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP64" , 0x1180080940200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP65" , 0x1180080940208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP66" , 0x1180080940210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP67" , 0x1180080940218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP68" , 0x1180080940220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP69" , 0x1180080940228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP70" , 0x1180080940230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP71" , 0x1180080940238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP72" , 0x1180080940240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP73" , 0x1180080940248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP74" , 0x1180080940250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP75" , 0x1180080940258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP76" , 0x1180080940260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP77" , 0x1180080940268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP78" , 0x1180080940270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP79" , 0x1180080940278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP80" , 0x1180080940280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP81" , 0x1180080940288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP82" , 0x1180080940290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP83" , 0x1180080940298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP84" , 0x11800809402a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP85" , 0x11800809402a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP86" , 0x11800809402b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP87" , 0x11800809402b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP88" , 0x11800809402c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP89" , 0x11800809402c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP90" , 0x11800809402d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP91" , 0x11800809402d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP92" , 0x11800809402e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP93" , 0x11800809402e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP94" , 0x11800809402f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP95" , 0x11800809402f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP96" , 0x1180080940300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP97" , 0x1180080940308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP98" , 0x1180080940310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP99" , 0x1180080940318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP100" , 0x1180080940320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP101" , 0x1180080940328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP102" , 0x1180080940330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP103" , 0x1180080940338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP104" , 0x1180080940340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP105" , 0x1180080940348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP106" , 0x1180080940350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP107" , 0x1180080940358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP108" , 0x1180080940360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP109" , 0x1180080940368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP110" , 0x1180080940370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP111" , 0x1180080940378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP112" , 0x1180080940380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP113" , 0x1180080940388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP114" , 0x1180080940390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP115" , 0x1180080940398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP116" , 0x11800809403a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP117" , 0x11800809403a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP118" , 0x11800809403b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP119" , 0x11800809403b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP120" , 0x11800809403c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP121" , 0x11800809403c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP122" , 0x11800809403d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP123" , 0x11800809403d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP124" , 0x11800809403e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP125" , 0x11800809403e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP126" , 0x11800809403f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP127" , 0x11800809403f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP128" , 0x1180080940400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP129" , 0x1180080940408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP130" , 0x1180080940410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP131" , 0x1180080940418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP132" , 0x1180080940420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP133" , 0x1180080940428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP134" , 0x1180080940430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP135" , 0x1180080940438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP136" , 0x1180080940440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP137" , 0x1180080940448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP138" , 0x1180080940450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP139" , 0x1180080940458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP140" , 0x1180080940460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP141" , 0x1180080940468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP142" , 0x1180080940470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP143" , 0x1180080940478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP144" , 0x1180080940480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP145" , 0x1180080940488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP146" , 0x1180080940490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP147" , 0x1180080940498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP148" , 0x11800809404a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP149" , 0x11800809404a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP150" , 0x11800809404b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP151" , 0x11800809404b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP152" , 0x11800809404c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP153" , 0x11800809404c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP154" , 0x11800809404d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP155" , 0x11800809404d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP156" , 0x11800809404e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP157" , 0x11800809404e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP158" , 0x11800809404f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP159" , 0x11800809404f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP160" , 0x1180080940500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP161" , 0x1180080940508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP162" , 0x1180080940510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP163" , 0x1180080940518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP164" , 0x1180080940520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP165" , 0x1180080940528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP166" , 0x1180080940530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP167" , 0x1180080940538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP168" , 0x1180080940540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP169" , 0x1180080940548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP170" , 0x1180080940550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP171" , 0x1180080940558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP172" , 0x1180080940560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP173" , 0x1180080940568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP174" , 0x1180080940570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP175" , 0x1180080940578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP176" , 0x1180080940580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP177" , 0x1180080940588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP178" , 0x1180080940590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP179" , 0x1180080940598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP180" , 0x11800809405a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP181" , 0x11800809405a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP182" , 0x11800809405b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP183" , 0x11800809405b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP184" , 0x11800809405c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP185" , 0x11800809405c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP186" , 0x11800809405d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP187" , 0x11800809405d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP188" , 0x11800809405e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP189" , 0x11800809405e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP190" , 0x11800809405f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP191" , 0x11800809405f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP192" , 0x1180080940600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP193" , 0x1180080940608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP194" , 0x1180080940610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP195" , 0x1180080940618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP196" , 0x1180080940620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP197" , 0x1180080940628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP198" , 0x1180080940630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP199" , 0x1180080940638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP200" , 0x1180080940640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP201" , 0x1180080940648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP202" , 0x1180080940650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP203" , 0x1180080940658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP204" , 0x1180080940660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP205" , 0x1180080940668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP206" , 0x1180080940670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP207" , 0x1180080940678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP208" , 0x1180080940680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP209" , 0x1180080940688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP210" , 0x1180080940690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP211" , 0x1180080940698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP212" , 0x11800809406a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP213" , 0x11800809406a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP214" , 0x11800809406b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP215" , 0x11800809406b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP216" , 0x11800809406c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP217" , 0x11800809406c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP218" , 0x11800809406d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP219" , 0x11800809406d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP220" , 0x11800809406e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP221" , 0x11800809406e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP222" , 0x11800809406f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP223" , 0x11800809406f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP224" , 0x1180080940700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP225" , 0x1180080940708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP226" , 0x1180080940710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP227" , 0x1180080940718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP228" , 0x1180080940720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP229" , 0x1180080940728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP230" , 0x1180080940730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP231" , 0x1180080940738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP232" , 0x1180080940740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP233" , 0x1180080940748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP234" , 0x1180080940750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP235" , 0x1180080940758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP236" , 0x1180080940760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP237" , 0x1180080940768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP238" , 0x1180080940770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP239" , 0x1180080940778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP240" , 0x1180080940780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP241" , 0x1180080940788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP242" , 0x1180080940790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP243" , 0x1180080940798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP244" , 0x11800809407a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP245" , 0x11800809407a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP246" , 0x11800809407b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP247" , 0x11800809407b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP248" , 0x11800809407c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP249" , 0x11800809407c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP250" , 0x11800809407d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP251" , 0x11800809407d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP252" , 0x11800809407e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP253" , 0x11800809407e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP254" , 0x11800809407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP255" , 0x11800809407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP256" , 0x1180080940800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP257" , 0x1180080940808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP258" , 0x1180080940810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP259" , 0x1180080940818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP260" , 0x1180080940820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP261" , 0x1180080940828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP262" , 0x1180080940830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP263" , 0x1180080940838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP264" , 0x1180080940840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP265" , 0x1180080940848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP266" , 0x1180080940850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP267" , 0x1180080940858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP268" , 0x1180080940860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP269" , 0x1180080940868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP270" , 0x1180080940870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP271" , 0x1180080940878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP272" , 0x1180080940880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP273" , 0x1180080940888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP274" , 0x1180080940890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP275" , 0x1180080940898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP276" , 0x11800809408a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP277" , 0x11800809408a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP278" , 0x11800809408b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP279" , 0x11800809408b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP280" , 0x11800809408c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP281" , 0x11800809408c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP282" , 0x11800809408d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP283" , 0x11800809408d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP284" , 0x11800809408e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP285" , 0x11800809408e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP286" , 0x11800809408f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP287" , 0x11800809408f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP288" , 0x1180080940900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP289" , 0x1180080940908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP290" , 0x1180080940910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP291" , 0x1180080940918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP292" , 0x1180080940920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP293" , 0x1180080940928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP294" , 0x1180080940930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP295" , 0x1180080940938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP296" , 0x1180080940940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP297" , 0x1180080940948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP298" , 0x1180080940950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP299" , 0x1180080940958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP300" , 0x1180080940960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP301" , 0x1180080940968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP302" , 0x1180080940970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP303" , 0x1180080940978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP304" , 0x1180080940980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP305" , 0x1180080940988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP306" , 0x1180080940990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP307" , 0x1180080940998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP308" , 0x11800809409a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP309" , 0x11800809409a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP310" , 0x11800809409b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP311" , 0x11800809409b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP312" , 0x11800809409c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP313" , 0x11800809409c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP314" , 0x11800809409d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP315" , 0x11800809409d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP316" , 0x11800809409e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP317" , 0x11800809409e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP318" , 0x11800809409f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP319" , 0x11800809409f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP320" , 0x1180080940a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP321" , 0x1180080940a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP322" , 0x1180080940a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP323" , 0x1180080940a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP324" , 0x1180080940a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP325" , 0x1180080940a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP326" , 0x1180080940a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP327" , 0x1180080940a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP328" , 0x1180080940a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP329" , 0x1180080940a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP330" , 0x1180080940a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP331" , 0x1180080940a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP332" , 0x1180080940a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP333" , 0x1180080940a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP334" , 0x1180080940a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP335" , 0x1180080940a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP336" , 0x1180080940a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP337" , 0x1180080940a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP338" , 0x1180080940a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP339" , 0x1180080940a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP340" , 0x1180080940aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP341" , 0x1180080940aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP342" , 0x1180080940ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP343" , 0x1180080940ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP344" , 0x1180080940ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP345" , 0x1180080940ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP346" , 0x1180080940ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP347" , 0x1180080940ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP348" , 0x1180080940ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP349" , 0x1180080940ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP350" , 0x1180080940af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP351" , 0x1180080940af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP352" , 0x1180080940b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP353" , 0x1180080940b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP354" , 0x1180080940b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP355" , 0x1180080940b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP356" , 0x1180080940b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP357" , 0x1180080940b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP358" , 0x1180080940b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP359" , 0x1180080940b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP360" , 0x1180080940b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP361" , 0x1180080940b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP362" , 0x1180080940b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP363" , 0x1180080940b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP364" , 0x1180080940b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP365" , 0x1180080940b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP366" , 0x1180080940b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP367" , 0x1180080940b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP368" , 0x1180080940b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP369" , 0x1180080940b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP370" , 0x1180080940b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP371" , 0x1180080940b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP372" , 0x1180080940ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP373" , 0x1180080940ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP374" , 0x1180080940bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP375" , 0x1180080940bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP376" , 0x1180080940bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP377" , 0x1180080940bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP378" , 0x1180080940bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP379" , 0x1180080940bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP380" , 0x1180080940be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP381" , 0x1180080940be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP382" , 0x1180080940bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP383" , 0x1180080940bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP384" , 0x1180080940c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP385" , 0x1180080940c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP386" , 0x1180080940c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP387" , 0x1180080940c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP388" , 0x1180080940c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP389" , 0x1180080940c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP390" , 0x1180080940c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP391" , 0x1180080940c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP392" , 0x1180080940c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP393" , 0x1180080940c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP394" , 0x1180080940c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP395" , 0x1180080940c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP396" , 0x1180080940c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP397" , 0x1180080940c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP398" , 0x1180080940c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP399" , 0x1180080940c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP400" , 0x1180080940c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP401" , 0x1180080940c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP402" , 0x1180080940c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP403" , 0x1180080940c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP404" , 0x1180080940ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP405" , 0x1180080940ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP406" , 0x1180080940cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP407" , 0x1180080940cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP408" , 0x1180080940cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP409" , 0x1180080940cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP410" , 0x1180080940cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP411" , 0x1180080940cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP412" , 0x1180080940ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP413" , 0x1180080940ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP414" , 0x1180080940cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP415" , 0x1180080940cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP416" , 0x1180080940d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP417" , 0x1180080940d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP418" , 0x1180080940d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP419" , 0x1180080940d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP420" , 0x1180080940d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP421" , 0x1180080940d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP422" , 0x1180080940d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP423" , 0x1180080940d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP424" , 0x1180080940d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP425" , 0x1180080940d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP426" , 0x1180080940d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP427" , 0x1180080940d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP428" , 0x1180080940d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP429" , 0x1180080940d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP430" , 0x1180080940d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP431" , 0x1180080940d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP432" , 0x1180080940d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP433" , 0x1180080940d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP434" , 0x1180080940d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP435" , 0x1180080940d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP436" , 0x1180080940da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP437" , 0x1180080940da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP438" , 0x1180080940db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP439" , 0x1180080940db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP440" , 0x1180080940dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP441" , 0x1180080940dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP442" , 0x1180080940dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP443" , 0x1180080940dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP444" , 0x1180080940de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP445" , 0x1180080940de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP446" , 0x1180080940df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP447" , 0x1180080940df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP448" , 0x1180080940e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP449" , 0x1180080940e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP450" , 0x1180080940e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP451" , 0x1180080940e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP452" , 0x1180080940e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP453" , 0x1180080940e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP454" , 0x1180080940e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP455" , 0x1180080940e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP456" , 0x1180080940e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP457" , 0x1180080940e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP458" , 0x1180080940e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP459" , 0x1180080940e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP460" , 0x1180080940e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP461" , 0x1180080940e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP462" , 0x1180080940e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP463" , 0x1180080940e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP464" , 0x1180080940e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP465" , 0x1180080940e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP466" , 0x1180080940e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP467" , 0x1180080940e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP468" , 0x1180080940ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP469" , 0x1180080940ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP470" , 0x1180080940eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP471" , 0x1180080940eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP472" , 0x1180080940ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP473" , 0x1180080940ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP474" , 0x1180080940ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP475" , 0x1180080940ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP476" , 0x1180080940ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP477" , 0x1180080940ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP478" , 0x1180080940ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP479" , 0x1180080940ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP480" , 0x1180080940f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP481" , 0x1180080940f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP482" , 0x1180080940f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP483" , 0x1180080940f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP484" , 0x1180080940f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP485" , 0x1180080940f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP486" , 0x1180080940f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP487" , 0x1180080940f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP488" , 0x1180080940f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP489" , 0x1180080940f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP490" , 0x1180080940f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP491" , 0x1180080940f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP492" , 0x1180080940f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP493" , 0x1180080940f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP494" , 0x1180080940f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP495" , 0x1180080940f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP496" , 0x1180080940f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP497" , 0x1180080940f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP498" , 0x1180080940f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP499" , 0x1180080940f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP500" , 0x1180080940fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP501" , 0x1180080940fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP502" , 0x1180080940fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP503" , 0x1180080940fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP504" , 0x1180080940fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP505" , 0x1180080940fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP506" , 0x1180080940fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP507" , 0x1180080940fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP508" , 0x1180080940fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP509" , 0x1180080940fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP510" , 0x1180080940ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP511" , 0x1180080940ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP512" , 0x1180080941000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP513" , 0x1180080941008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP514" , 0x1180080941010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP515" , 0x1180080941018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP516" , 0x1180080941020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP517" , 0x1180080941028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP518" , 0x1180080941030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP519" , 0x1180080941038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP520" , 0x1180080941040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP521" , 0x1180080941048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP522" , 0x1180080941050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP523" , 0x1180080941058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP524" , 0x1180080941060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP525" , 0x1180080941068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP526" , 0x1180080941070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP527" , 0x1180080941078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP528" , 0x1180080941080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP529" , 0x1180080941088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP530" , 0x1180080941090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP531" , 0x1180080941098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP532" , 0x11800809410a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP533" , 0x11800809410a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP534" , 0x11800809410b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP535" , 0x11800809410b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP536" , 0x11800809410c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP537" , 0x11800809410c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP538" , 0x11800809410d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP539" , 0x11800809410d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP540" , 0x11800809410e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP541" , 0x11800809410e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP542" , 0x11800809410f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP543" , 0x11800809410f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP544" , 0x1180080941100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP545" , 0x1180080941108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP546" , 0x1180080941110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP547" , 0x1180080941118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP548" , 0x1180080941120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP549" , 0x1180080941128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP550" , 0x1180080941130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP551" , 0x1180080941138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP552" , 0x1180080941140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP553" , 0x1180080941148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP554" , 0x1180080941150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP555" , 0x1180080941158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP556" , 0x1180080941160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP557" , 0x1180080941168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP558" , 0x1180080941170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP559" , 0x1180080941178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP560" , 0x1180080941180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP561" , 0x1180080941188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP562" , 0x1180080941190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP563" , 0x1180080941198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP564" , 0x11800809411a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP565" , 0x11800809411a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP566" , 0x11800809411b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP567" , 0x11800809411b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP568" , 0x11800809411c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP569" , 0x11800809411c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP570" , 0x11800809411d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP571" , 0x11800809411d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP572" , 0x11800809411e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP573" , 0x11800809411e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP574" , 0x11800809411f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP575" , 0x11800809411f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP576" , 0x1180080941200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP577" , 0x1180080941208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP578" , 0x1180080941210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP579" , 0x1180080941218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP580" , 0x1180080941220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP581" , 0x1180080941228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP582" , 0x1180080941230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP583" , 0x1180080941238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP584" , 0x1180080941240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP585" , 0x1180080941248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP586" , 0x1180080941250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP587" , 0x1180080941258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP588" , 0x1180080941260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP589" , 0x1180080941268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP590" , 0x1180080941270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP591" , 0x1180080941278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP592" , 0x1180080941280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP593" , 0x1180080941288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP594" , 0x1180080941290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP595" , 0x1180080941298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP596" , 0x11800809412a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP597" , 0x11800809412a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP598" , 0x11800809412b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP599" , 0x11800809412b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP600" , 0x11800809412c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP601" , 0x11800809412c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP602" , 0x11800809412d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP603" , 0x11800809412d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP604" , 0x11800809412e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP605" , 0x11800809412e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP606" , 0x11800809412f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP607" , 0x11800809412f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP608" , 0x1180080941300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP609" , 0x1180080941308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP610" , 0x1180080941310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP611" , 0x1180080941318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP612" , 0x1180080941320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP613" , 0x1180080941328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP614" , 0x1180080941330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP615" , 0x1180080941338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP616" , 0x1180080941340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP617" , 0x1180080941348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP618" , 0x1180080941350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP619" , 0x1180080941358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP620" , 0x1180080941360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP621" , 0x1180080941368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP622" , 0x1180080941370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP623" , 0x1180080941378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP624" , 0x1180080941380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP625" , 0x1180080941388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP626" , 0x1180080941390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP627" , 0x1180080941398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP628" , 0x11800809413a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP629" , 0x11800809413a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP630" , 0x11800809413b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP631" , 0x11800809413b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP632" , 0x11800809413c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP633" , 0x11800809413c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP634" , 0x11800809413d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP635" , 0x11800809413d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP636" , 0x11800809413e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP637" , 0x11800809413e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP638" , 0x11800809413f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP639" , 0x11800809413f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP640" , 0x1180080941400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP641" , 0x1180080941408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP642" , 0x1180080941410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP643" , 0x1180080941418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP644" , 0x1180080941420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP645" , 0x1180080941428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP646" , 0x1180080941430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP647" , 0x1180080941438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP648" , 0x1180080941440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP649" , 0x1180080941448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP650" , 0x1180080941450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP651" , 0x1180080941458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP652" , 0x1180080941460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP653" , 0x1180080941468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP654" , 0x1180080941470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP655" , 0x1180080941478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP656" , 0x1180080941480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP657" , 0x1180080941488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP658" , 0x1180080941490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP659" , 0x1180080941498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP660" , 0x11800809414a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP661" , 0x11800809414a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP662" , 0x11800809414b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP663" , 0x11800809414b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP664" , 0x11800809414c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP665" , 0x11800809414c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP666" , 0x11800809414d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP667" , 0x11800809414d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP668" , 0x11800809414e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP669" , 0x11800809414e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP670" , 0x11800809414f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP671" , 0x11800809414f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP672" , 0x1180080941500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP673" , 0x1180080941508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP674" , 0x1180080941510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP675" , 0x1180080941518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP676" , 0x1180080941520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP677" , 0x1180080941528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP678" , 0x1180080941530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP679" , 0x1180080941538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP680" , 0x1180080941540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP681" , 0x1180080941548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP682" , 0x1180080941550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP683" , 0x1180080941558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP684" , 0x1180080941560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP685" , 0x1180080941568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP686" , 0x1180080941570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP687" , 0x1180080941578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP688" , 0x1180080941580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP689" , 0x1180080941588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP690" , 0x1180080941590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP691" , 0x1180080941598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP692" , 0x11800809415a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP693" , 0x11800809415a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP694" , 0x11800809415b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP695" , 0x11800809415b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP696" , 0x11800809415c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP697" , 0x11800809415c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP698" , 0x11800809415d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP699" , 0x11800809415d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP700" , 0x11800809415e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP701" , 0x11800809415e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP702" , 0x11800809415f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP703" , 0x11800809415f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP704" , 0x1180080941600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP705" , 0x1180080941608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP706" , 0x1180080941610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP707" , 0x1180080941618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP708" , 0x1180080941620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP709" , 0x1180080941628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP710" , 0x1180080941630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP711" , 0x1180080941638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP712" , 0x1180080941640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP713" , 0x1180080941648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP714" , 0x1180080941650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP715" , 0x1180080941658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP716" , 0x1180080941660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP717" , 0x1180080941668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP718" , 0x1180080941670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP719" , 0x1180080941678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP720" , 0x1180080941680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP721" , 0x1180080941688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP722" , 0x1180080941690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP723" , 0x1180080941698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP724" , 0x11800809416a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP725" , 0x11800809416a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP726" , 0x11800809416b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP727" , 0x11800809416b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP728" , 0x11800809416c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP729" , 0x11800809416c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP730" , 0x11800809416d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP731" , 0x11800809416d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP732" , 0x11800809416e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP733" , 0x11800809416e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP734" , 0x11800809416f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP735" , 0x11800809416f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP736" , 0x1180080941700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP737" , 0x1180080941708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP738" , 0x1180080941710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP739" , 0x1180080941718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP740" , 0x1180080941720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP741" , 0x1180080941728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP742" , 0x1180080941730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP743" , 0x1180080941738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP744" , 0x1180080941740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP745" , 0x1180080941748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP746" , 0x1180080941750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP747" , 0x1180080941758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP748" , 0x1180080941760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP749" , 0x1180080941768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP750" , 0x1180080941770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP751" , 0x1180080941778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP752" , 0x1180080941780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP753" , 0x1180080941788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP754" , 0x1180080941790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP755" , 0x1180080941798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP756" , 0x11800809417a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP757" , 0x11800809417a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP758" , 0x11800809417b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP759" , 0x11800809417b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP760" , 0x11800809417c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP761" , 0x11800809417c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP762" , 0x11800809417d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP763" , 0x11800809417d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP764" , 0x11800809417e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP765" , 0x11800809417e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP766" , 0x11800809417f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP767" , 0x11800809417f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP768" , 0x1180080941800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP769" , 0x1180080941808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP770" , 0x1180080941810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP771" , 0x1180080941818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP772" , 0x1180080941820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP773" , 0x1180080941828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP774" , 0x1180080941830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP775" , 0x1180080941838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP776" , 0x1180080941840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP777" , 0x1180080941848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP778" , 0x1180080941850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP779" , 0x1180080941858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP780" , 0x1180080941860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP781" , 0x1180080941868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP782" , 0x1180080941870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP783" , 0x1180080941878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP784" , 0x1180080941880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP785" , 0x1180080941888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP786" , 0x1180080941890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP787" , 0x1180080941898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP788" , 0x11800809418a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP789" , 0x11800809418a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP790" , 0x11800809418b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP791" , 0x11800809418b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP792" , 0x11800809418c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP793" , 0x11800809418c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP794" , 0x11800809418d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP795" , 0x11800809418d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP796" , 0x11800809418e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP797" , 0x11800809418e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP798" , 0x11800809418f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP799" , 0x11800809418f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP800" , 0x1180080941900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP801" , 0x1180080941908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP802" , 0x1180080941910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP803" , 0x1180080941918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP804" , 0x1180080941920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP805" , 0x1180080941928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP806" , 0x1180080941930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP807" , 0x1180080941938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP808" , 0x1180080941940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP809" , 0x1180080941948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP810" , 0x1180080941950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP811" , 0x1180080941958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP812" , 0x1180080941960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP813" , 0x1180080941968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP814" , 0x1180080941970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP815" , 0x1180080941978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP816" , 0x1180080941980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP817" , 0x1180080941988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP818" , 0x1180080941990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP819" , 0x1180080941998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP820" , 0x11800809419a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP821" , 0x11800809419a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP822" , 0x11800809419b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP823" , 0x11800809419b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP824" , 0x11800809419c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP825" , 0x11800809419c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP826" , 0x11800809419d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP827" , 0x11800809419d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP828" , 0x11800809419e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP829" , 0x11800809419e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP830" , 0x11800809419f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP831" , 0x11800809419f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP832" , 0x1180080941a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP833" , 0x1180080941a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP834" , 0x1180080941a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP835" , 0x1180080941a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP836" , 0x1180080941a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP837" , 0x1180080941a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP838" , 0x1180080941a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP839" , 0x1180080941a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP840" , 0x1180080941a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP841" , 0x1180080941a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP842" , 0x1180080941a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP843" , 0x1180080941a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP844" , 0x1180080941a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP845" , 0x1180080941a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP846" , 0x1180080941a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP847" , 0x1180080941a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP848" , 0x1180080941a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP849" , 0x1180080941a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP850" , 0x1180080941a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP851" , 0x1180080941a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP852" , 0x1180080941aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP853" , 0x1180080941aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP854" , 0x1180080941ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP855" , 0x1180080941ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP856" , 0x1180080941ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP857" , 0x1180080941ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP858" , 0x1180080941ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP859" , 0x1180080941ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP860" , 0x1180080941ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP861" , 0x1180080941ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP862" , 0x1180080941af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP863" , 0x1180080941af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP864" , 0x1180080941b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP865" , 0x1180080941b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP866" , 0x1180080941b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP867" , 0x1180080941b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP868" , 0x1180080941b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP869" , 0x1180080941b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP870" , 0x1180080941b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP871" , 0x1180080941b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP872" , 0x1180080941b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP873" , 0x1180080941b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP874" , 0x1180080941b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP875" , 0x1180080941b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP876" , 0x1180080941b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP877" , 0x1180080941b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP878" , 0x1180080941b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP879" , 0x1180080941b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP880" , 0x1180080941b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP881" , 0x1180080941b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP882" , 0x1180080941b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP883" , 0x1180080941b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP884" , 0x1180080941ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP885" , 0x1180080941ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP886" , 0x1180080941bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP887" , 0x1180080941bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP888" , 0x1180080941bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP889" , 0x1180080941bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP890" , 0x1180080941bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP891" , 0x1180080941bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP892" , 0x1180080941be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP893" , 0x1180080941be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP894" , 0x1180080941bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP895" , 0x1180080941bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP896" , 0x1180080941c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP897" , 0x1180080941c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP898" , 0x1180080941c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP899" , 0x1180080941c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP900" , 0x1180080941c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP901" , 0x1180080941c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP902" , 0x1180080941c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP903" , 0x1180080941c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP904" , 0x1180080941c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP905" , 0x1180080941c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP906" , 0x1180080941c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP907" , 0x1180080941c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP908" , 0x1180080941c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP909" , 0x1180080941c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP910" , 0x1180080941c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP911" , 0x1180080941c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP912" , 0x1180080941c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP913" , 0x1180080941c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP914" , 0x1180080941c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP915" , 0x1180080941c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP916" , 0x1180080941ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP917" , 0x1180080941ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP918" , 0x1180080941cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP919" , 0x1180080941cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP920" , 0x1180080941cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP921" , 0x1180080941cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP922" , 0x1180080941cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP923" , 0x1180080941cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP924" , 0x1180080941ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP925" , 0x1180080941ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP926" , 0x1180080941cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP927" , 0x1180080941cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP928" , 0x1180080941d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP929" , 0x1180080941d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP930" , 0x1180080941d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP931" , 0x1180080941d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP932" , 0x1180080941d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP933" , 0x1180080941d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP934" , 0x1180080941d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP935" , 0x1180080941d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP936" , 0x1180080941d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP937" , 0x1180080941d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP938" , 0x1180080941d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP939" , 0x1180080941d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP940" , 0x1180080941d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP941" , 0x1180080941d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP942" , 0x1180080941d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP943" , 0x1180080941d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP944" , 0x1180080941d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP945" , 0x1180080941d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP946" , 0x1180080941d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP947" , 0x1180080941d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP948" , 0x1180080941da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP949" , 0x1180080941da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP950" , 0x1180080941db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP951" , 0x1180080941db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP952" , 0x1180080941dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP953" , 0x1180080941dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP954" , 0x1180080941dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP955" , 0x1180080941dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP956" , 0x1180080941de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP957" , 0x1180080941de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP958" , 0x1180080941df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP959" , 0x1180080941df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP960" , 0x1180080941e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP961" , 0x1180080941e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP962" , 0x1180080941e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP963" , 0x1180080941e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP964" , 0x1180080941e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP965" , 0x1180080941e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP966" , 0x1180080941e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP967" , 0x1180080941e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP968" , 0x1180080941e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP969" , 0x1180080941e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP970" , 0x1180080941e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP971" , 0x1180080941e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP972" , 0x1180080941e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP973" , 0x1180080941e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP974" , 0x1180080941e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP975" , 0x1180080941e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP976" , 0x1180080941e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP977" , 0x1180080941e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP978" , 0x1180080941e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP979" , 0x1180080941e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP980" , 0x1180080941ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP981" , 0x1180080941ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP982" , 0x1180080941eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP983" , 0x1180080941eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP984" , 0x1180080941ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP985" , 0x1180080941ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP986" , 0x1180080941ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP987" , 0x1180080941ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP988" , 0x1180080941ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP989" , 0x1180080941ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP990" , 0x1180080941ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP991" , 0x1180080941ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP992" , 0x1180080941f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP993" , 0x1180080941f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP994" , 0x1180080941f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP995" , 0x1180080941f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP996" , 0x1180080941f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP997" , 0x1180080941f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP998" , 0x1180080941f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP999" , 0x1180080941f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1000" , 0x1180080941f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1001" , 0x1180080941f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1002" , 0x1180080941f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1003" , 0x1180080941f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1004" , 0x1180080941f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1005" , 0x1180080941f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1006" , 0x1180080941f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1007" , 0x1180080941f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1008" , 0x1180080941f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1009" , 0x1180080941f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1010" , 0x1180080941f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1011" , 0x1180080941f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1012" , 0x1180080941fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1013" , 0x1180080941fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1014" , 0x1180080941fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1015" , 0x1180080941fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1016" , 0x1180080941fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1017" , 0x1180080941fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1018" , 0x1180080941fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1019" , 0x1180080941fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1020" , 0x1180080941fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1021" , 0x1180080941fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1022" , 0x1180080941ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1023" , 0x1180080941ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1024" , 0x1180080942000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1025" , 0x1180080942008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1026" , 0x1180080942010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1027" , 0x1180080942018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1028" , 0x1180080942020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1029" , 0x1180080942028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1030" , 0x1180080942030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1031" , 0x1180080942038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1032" , 0x1180080942040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1033" , 0x1180080942048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1034" , 0x1180080942050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1035" , 0x1180080942058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1036" , 0x1180080942060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1037" , 0x1180080942068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1038" , 0x1180080942070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1039" , 0x1180080942078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1040" , 0x1180080942080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1041" , 0x1180080942088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1042" , 0x1180080942090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1043" , 0x1180080942098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1044" , 0x11800809420a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1045" , 0x11800809420a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1046" , 0x11800809420b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1047" , 0x11800809420b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1048" , 0x11800809420c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1049" , 0x11800809420c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1050" , 0x11800809420d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1051" , 0x11800809420d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1052" , 0x11800809420e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1053" , 0x11800809420e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1054" , 0x11800809420f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1055" , 0x11800809420f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1056" , 0x1180080942100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1057" , 0x1180080942108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1058" , 0x1180080942110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1059" , 0x1180080942118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1060" , 0x1180080942120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1061" , 0x1180080942128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1062" , 0x1180080942130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1063" , 0x1180080942138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1064" , 0x1180080942140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1065" , 0x1180080942148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1066" , 0x1180080942150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1067" , 0x1180080942158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1068" , 0x1180080942160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1069" , 0x1180080942168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1070" , 0x1180080942170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1071" , 0x1180080942178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1072" , 0x1180080942180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1073" , 0x1180080942188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1074" , 0x1180080942190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1075" , 0x1180080942198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1076" , 0x11800809421a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1077" , 0x11800809421a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1078" , 0x11800809421b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1079" , 0x11800809421b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1080" , 0x11800809421c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1081" , 0x11800809421c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1082" , 0x11800809421d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1083" , 0x11800809421d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1084" , 0x11800809421e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1085" , 0x11800809421e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1086" , 0x11800809421f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1087" , 0x11800809421f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1088" , 0x1180080942200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1089" , 0x1180080942208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1090" , 0x1180080942210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1091" , 0x1180080942218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1092" , 0x1180080942220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1093" , 0x1180080942228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1094" , 0x1180080942230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1095" , 0x1180080942238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1096" , 0x1180080942240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1097" , 0x1180080942248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1098" , 0x1180080942250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1099" , 0x1180080942258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1100" , 0x1180080942260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1101" , 0x1180080942268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1102" , 0x1180080942270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1103" , 0x1180080942278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1104" , 0x1180080942280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1105" , 0x1180080942288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1106" , 0x1180080942290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1107" , 0x1180080942298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1108" , 0x11800809422a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1109" , 0x11800809422a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1110" , 0x11800809422b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1111" , 0x11800809422b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1112" , 0x11800809422c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1113" , 0x11800809422c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1114" , 0x11800809422d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1115" , 0x11800809422d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1116" , 0x11800809422e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1117" , 0x11800809422e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1118" , 0x11800809422f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1119" , 0x11800809422f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1120" , 0x1180080942300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1121" , 0x1180080942308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1122" , 0x1180080942310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1123" , 0x1180080942318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1124" , 0x1180080942320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1125" , 0x1180080942328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1126" , 0x1180080942330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1127" , 0x1180080942338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1128" , 0x1180080942340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1129" , 0x1180080942348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1130" , 0x1180080942350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1131" , 0x1180080942358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1132" , 0x1180080942360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1133" , 0x1180080942368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1134" , 0x1180080942370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1135" , 0x1180080942378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1136" , 0x1180080942380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1137" , 0x1180080942388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1138" , 0x1180080942390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1139" , 0x1180080942398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1140" , 0x11800809423a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1141" , 0x11800809423a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1142" , 0x11800809423b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1143" , 0x11800809423b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1144" , 0x11800809423c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1145" , 0x11800809423c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1146" , 0x11800809423d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1147" , 0x11800809423d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1148" , 0x11800809423e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1149" , 0x11800809423e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1150" , 0x11800809423f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1151" , 0x11800809423f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1152" , 0x1180080942400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1153" , 0x1180080942408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1154" , 0x1180080942410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1155" , 0x1180080942418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1156" , 0x1180080942420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1157" , 0x1180080942428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1158" , 0x1180080942430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1159" , 0x1180080942438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1160" , 0x1180080942440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1161" , 0x1180080942448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1162" , 0x1180080942450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1163" , 0x1180080942458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1164" , 0x1180080942460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1165" , 0x1180080942468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1166" , 0x1180080942470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1167" , 0x1180080942478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1168" , 0x1180080942480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1169" , 0x1180080942488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1170" , 0x1180080942490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1171" , 0x1180080942498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1172" , 0x11800809424a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1173" , 0x11800809424a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1174" , 0x11800809424b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1175" , 0x11800809424b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1176" , 0x11800809424c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1177" , 0x11800809424c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1178" , 0x11800809424d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1179" , 0x11800809424d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1180" , 0x11800809424e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1181" , 0x11800809424e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1182" , 0x11800809424f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1183" , 0x11800809424f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1184" , 0x1180080942500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1185" , 0x1180080942508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1186" , 0x1180080942510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1187" , 0x1180080942518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1188" , 0x1180080942520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1189" , 0x1180080942528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1190" , 0x1180080942530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1191" , 0x1180080942538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1192" , 0x1180080942540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1193" , 0x1180080942548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1194" , 0x1180080942550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1195" , 0x1180080942558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1196" , 0x1180080942560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1197" , 0x1180080942568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1198" , 0x1180080942570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1199" , 0x1180080942578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1200" , 0x1180080942580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1201" , 0x1180080942588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1202" , 0x1180080942590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1203" , 0x1180080942598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1204" , 0x11800809425a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1205" , 0x11800809425a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1206" , 0x11800809425b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1207" , 0x11800809425b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1208" , 0x11800809425c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1209" , 0x11800809425c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1210" , 0x11800809425d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1211" , 0x11800809425d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1212" , 0x11800809425e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1213" , 0x11800809425e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1214" , 0x11800809425f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1215" , 0x11800809425f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1216" , 0x1180080942600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1217" , 0x1180080942608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1218" , 0x1180080942610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1219" , 0x1180080942618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1220" , 0x1180080942620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1221" , 0x1180080942628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1222" , 0x1180080942630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1223" , 0x1180080942638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1224" , 0x1180080942640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1225" , 0x1180080942648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1226" , 0x1180080942650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1227" , 0x1180080942658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1228" , 0x1180080942660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1229" , 0x1180080942668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1230" , 0x1180080942670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1231" , 0x1180080942678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1232" , 0x1180080942680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1233" , 0x1180080942688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1234" , 0x1180080942690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1235" , 0x1180080942698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1236" , 0x11800809426a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1237" , 0x11800809426a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1238" , 0x11800809426b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1239" , 0x11800809426b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1240" , 0x11800809426c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1241" , 0x11800809426c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1242" , 0x11800809426d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1243" , 0x11800809426d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1244" , 0x11800809426e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1245" , 0x11800809426e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1246" , 0x11800809426f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1247" , 0x11800809426f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1248" , 0x1180080942700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1249" , 0x1180080942708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1250" , 0x1180080942710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1251" , 0x1180080942718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1252" , 0x1180080942720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1253" , 0x1180080942728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1254" , 0x1180080942730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1255" , 0x1180080942738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1256" , 0x1180080942740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1257" , 0x1180080942748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1258" , 0x1180080942750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1259" , 0x1180080942758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1260" , 0x1180080942760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1261" , 0x1180080942768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1262" , 0x1180080942770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1263" , 0x1180080942778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1264" , 0x1180080942780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1265" , 0x1180080942788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1266" , 0x1180080942790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1267" , 0x1180080942798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1268" , 0x11800809427a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1269" , 0x11800809427a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1270" , 0x11800809427b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1271" , 0x11800809427b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1272" , 0x11800809427c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1273" , 0x11800809427c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1274" , 0x11800809427d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1275" , 0x11800809427d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1276" , 0x11800809427e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1277" , 0x11800809427e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1278" , 0x11800809427f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1279" , 0x11800809427f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1280" , 0x1180080942800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1281" , 0x1180080942808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1282" , 0x1180080942810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1283" , 0x1180080942818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1284" , 0x1180080942820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1285" , 0x1180080942828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1286" , 0x1180080942830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1287" , 0x1180080942838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1288" , 0x1180080942840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1289" , 0x1180080942848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1290" , 0x1180080942850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1291" , 0x1180080942858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1292" , 0x1180080942860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1293" , 0x1180080942868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1294" , 0x1180080942870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1295" , 0x1180080942878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1296" , 0x1180080942880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1297" , 0x1180080942888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1298" , 0x1180080942890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1299" , 0x1180080942898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1300" , 0x11800809428a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1301" , 0x11800809428a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1302" , 0x11800809428b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1303" , 0x11800809428b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1304" , 0x11800809428c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1305" , 0x11800809428c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1306" , 0x11800809428d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1307" , 0x11800809428d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1308" , 0x11800809428e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1309" , 0x11800809428e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1310" , 0x11800809428f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1311" , 0x11800809428f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1312" , 0x1180080942900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1313" , 0x1180080942908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1314" , 0x1180080942910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1315" , 0x1180080942918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1316" , 0x1180080942920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1317" , 0x1180080942928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1318" , 0x1180080942930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1319" , 0x1180080942938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1320" , 0x1180080942940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1321" , 0x1180080942948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1322" , 0x1180080942950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1323" , 0x1180080942958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1324" , 0x1180080942960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1325" , 0x1180080942968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1326" , 0x1180080942970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1327" , 0x1180080942978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1328" , 0x1180080942980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1329" , 0x1180080942988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1330" , 0x1180080942990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1331" , 0x1180080942998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1332" , 0x11800809429a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1333" , 0x11800809429a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1334" , 0x11800809429b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1335" , 0x11800809429b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1336" , 0x11800809429c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1337" , 0x11800809429c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1338" , 0x11800809429d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1339" , 0x11800809429d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1340" , 0x11800809429e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1341" , 0x11800809429e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1342" , 0x11800809429f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1343" , 0x11800809429f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1344" , 0x1180080942a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1345" , 0x1180080942a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1346" , 0x1180080942a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1347" , 0x1180080942a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1348" , 0x1180080942a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1349" , 0x1180080942a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1350" , 0x1180080942a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1351" , 0x1180080942a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1352" , 0x1180080942a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1353" , 0x1180080942a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1354" , 0x1180080942a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1355" , 0x1180080942a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1356" , 0x1180080942a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1357" , 0x1180080942a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1358" , 0x1180080942a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1359" , 0x1180080942a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1360" , 0x1180080942a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1361" , 0x1180080942a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1362" , 0x1180080942a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1363" , 0x1180080942a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1364" , 0x1180080942aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1365" , 0x1180080942aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1366" , 0x1180080942ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1367" , 0x1180080942ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1368" , 0x1180080942ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1369" , 0x1180080942ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1370" , 0x1180080942ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1371" , 0x1180080942ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1372" , 0x1180080942ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1373" , 0x1180080942ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1374" , 0x1180080942af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1375" , 0x1180080942af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1376" , 0x1180080942b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1377" , 0x1180080942b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1378" , 0x1180080942b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1379" , 0x1180080942b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1380" , 0x1180080942b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1381" , 0x1180080942b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1382" , 0x1180080942b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1383" , 0x1180080942b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1384" , 0x1180080942b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1385" , 0x1180080942b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1386" , 0x1180080942b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1387" , 0x1180080942b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1388" , 0x1180080942b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1389" , 0x1180080942b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1390" , 0x1180080942b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1391" , 0x1180080942b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1392" , 0x1180080942b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1393" , 0x1180080942b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1394" , 0x1180080942b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1395" , 0x1180080942b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1396" , 0x1180080942ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1397" , 0x1180080942ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1398" , 0x1180080942bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1399" , 0x1180080942bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1400" , 0x1180080942bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1401" , 0x1180080942bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1402" , 0x1180080942bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1403" , 0x1180080942bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1404" , 0x1180080942be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1405" , 0x1180080942be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1406" , 0x1180080942bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1407" , 0x1180080942bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1408" , 0x1180080942c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1409" , 0x1180080942c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1410" , 0x1180080942c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1411" , 0x1180080942c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1412" , 0x1180080942c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1413" , 0x1180080942c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1414" , 0x1180080942c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1415" , 0x1180080942c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1416" , 0x1180080942c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1417" , 0x1180080942c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1418" , 0x1180080942c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1419" , 0x1180080942c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1420" , 0x1180080942c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1421" , 0x1180080942c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1422" , 0x1180080942c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1423" , 0x1180080942c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1424" , 0x1180080942c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1425" , 0x1180080942c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1426" , 0x1180080942c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1427" , 0x1180080942c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1428" , 0x1180080942ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1429" , 0x1180080942ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1430" , 0x1180080942cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1431" , 0x1180080942cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1432" , 0x1180080942cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1433" , 0x1180080942cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1434" , 0x1180080942cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1435" , 0x1180080942cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1436" , 0x1180080942ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1437" , 0x1180080942ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1438" , 0x1180080942cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1439" , 0x1180080942cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1440" , 0x1180080942d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1441" , 0x1180080942d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1442" , 0x1180080942d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1443" , 0x1180080942d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1444" , 0x1180080942d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1445" , 0x1180080942d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1446" , 0x1180080942d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1447" , 0x1180080942d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1448" , 0x1180080942d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1449" , 0x1180080942d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1450" , 0x1180080942d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1451" , 0x1180080942d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1452" , 0x1180080942d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1453" , 0x1180080942d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1454" , 0x1180080942d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1455" , 0x1180080942d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1456" , 0x1180080942d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1457" , 0x1180080942d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1458" , 0x1180080942d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1459" , 0x1180080942d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1460" , 0x1180080942da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1461" , 0x1180080942da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1462" , 0x1180080942db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1463" , 0x1180080942db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1464" , 0x1180080942dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1465" , 0x1180080942dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1466" , 0x1180080942dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1467" , 0x1180080942dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1468" , 0x1180080942de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1469" , 0x1180080942de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1470" , 0x1180080942df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1471" , 0x1180080942df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1472" , 0x1180080942e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1473" , 0x1180080942e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1474" , 0x1180080942e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1475" , 0x1180080942e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1476" , 0x1180080942e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1477" , 0x1180080942e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1478" , 0x1180080942e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1479" , 0x1180080942e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1480" , 0x1180080942e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1481" , 0x1180080942e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1482" , 0x1180080942e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1483" , 0x1180080942e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1484" , 0x1180080942e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1485" , 0x1180080942e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1486" , 0x1180080942e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1487" , 0x1180080942e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1488" , 0x1180080942e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1489" , 0x1180080942e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1490" , 0x1180080942e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1491" , 0x1180080942e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1492" , 0x1180080942ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1493" , 0x1180080942ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1494" , 0x1180080942eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1495" , 0x1180080942eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1496" , 0x1180080942ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1497" , 0x1180080942ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1498" , 0x1180080942ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1499" , 0x1180080942ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1500" , 0x1180080942ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1501" , 0x1180080942ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1502" , 0x1180080942ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1503" , 0x1180080942ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1504" , 0x1180080942f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1505" , 0x1180080942f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1506" , 0x1180080942f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1507" , 0x1180080942f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1508" , 0x1180080942f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1509" , 0x1180080942f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1510" , 0x1180080942f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1511" , 0x1180080942f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1512" , 0x1180080942f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1513" , 0x1180080942f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1514" , 0x1180080942f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1515" , 0x1180080942f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1516" , 0x1180080942f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1517" , 0x1180080942f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1518" , 0x1180080942f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1519" , 0x1180080942f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1520" , 0x1180080942f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1521" , 0x1180080942f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1522" , 0x1180080942f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1523" , 0x1180080942f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1524" , 0x1180080942fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1525" , 0x1180080942fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1526" , 0x1180080942fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1527" , 0x1180080942fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1528" , 0x1180080942fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1529" , 0x1180080942fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1530" , 0x1180080942fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1531" , 0x1180080942fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1532" , 0x1180080942fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1533" , 0x1180080942fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1534" , 0x1180080942ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1535" , 0x1180080942ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1536" , 0x1180080943000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1537" , 0x1180080943008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1538" , 0x1180080943010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1539" , 0x1180080943018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1540" , 0x1180080943020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1541" , 0x1180080943028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1542" , 0x1180080943030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1543" , 0x1180080943038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1544" , 0x1180080943040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1545" , 0x1180080943048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1546" , 0x1180080943050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1547" , 0x1180080943058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1548" , 0x1180080943060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1549" , 0x1180080943068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1550" , 0x1180080943070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1551" , 0x1180080943078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1552" , 0x1180080943080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1553" , 0x1180080943088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1554" , 0x1180080943090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1555" , 0x1180080943098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1556" , 0x11800809430a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1557" , 0x11800809430a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1558" , 0x11800809430b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1559" , 0x11800809430b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1560" , 0x11800809430c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1561" , 0x11800809430c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1562" , 0x11800809430d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1563" , 0x11800809430d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1564" , 0x11800809430e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1565" , 0x11800809430e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1566" , 0x11800809430f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1567" , 0x11800809430f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1568" , 0x1180080943100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1569" , 0x1180080943108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1570" , 0x1180080943110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1571" , 0x1180080943118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1572" , 0x1180080943120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1573" , 0x1180080943128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1574" , 0x1180080943130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1575" , 0x1180080943138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1576" , 0x1180080943140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1577" , 0x1180080943148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1578" , 0x1180080943150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1579" , 0x1180080943158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1580" , 0x1180080943160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1581" , 0x1180080943168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1582" , 0x1180080943170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1583" , 0x1180080943178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1584" , 0x1180080943180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1585" , 0x1180080943188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1586" , 0x1180080943190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1587" , 0x1180080943198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1588" , 0x11800809431a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1589" , 0x11800809431a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1590" , 0x11800809431b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1591" , 0x11800809431b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1592" , 0x11800809431c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1593" , 0x11800809431c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1594" , 0x11800809431d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1595" , 0x11800809431d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1596" , 0x11800809431e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1597" , 0x11800809431e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1598" , 0x11800809431f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1599" , 0x11800809431f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1600" , 0x1180080943200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1601" , 0x1180080943208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1602" , 0x1180080943210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1603" , 0x1180080943218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1604" , 0x1180080943220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1605" , 0x1180080943228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1606" , 0x1180080943230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1607" , 0x1180080943238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1608" , 0x1180080943240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1609" , 0x1180080943248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1610" , 0x1180080943250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1611" , 0x1180080943258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1612" , 0x1180080943260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1613" , 0x1180080943268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1614" , 0x1180080943270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1615" , 0x1180080943278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1616" , 0x1180080943280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1617" , 0x1180080943288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1618" , 0x1180080943290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1619" , 0x1180080943298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1620" , 0x11800809432a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1621" , 0x11800809432a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1622" , 0x11800809432b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1623" , 0x11800809432b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1624" , 0x11800809432c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1625" , 0x11800809432c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1626" , 0x11800809432d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1627" , 0x11800809432d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1628" , 0x11800809432e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1629" , 0x11800809432e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1630" , 0x11800809432f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1631" , 0x11800809432f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1632" , 0x1180080943300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1633" , 0x1180080943308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1634" , 0x1180080943310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1635" , 0x1180080943318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1636" , 0x1180080943320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1637" , 0x1180080943328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1638" , 0x1180080943330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1639" , 0x1180080943338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1640" , 0x1180080943340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1641" , 0x1180080943348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1642" , 0x1180080943350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1643" , 0x1180080943358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1644" , 0x1180080943360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1645" , 0x1180080943368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1646" , 0x1180080943370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1647" , 0x1180080943378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1648" , 0x1180080943380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1649" , 0x1180080943388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1650" , 0x1180080943390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1651" , 0x1180080943398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1652" , 0x11800809433a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1653" , 0x11800809433a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1654" , 0x11800809433b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1655" , 0x11800809433b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1656" , 0x11800809433c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1657" , 0x11800809433c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1658" , 0x11800809433d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1659" , 0x11800809433d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1660" , 0x11800809433e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1661" , 0x11800809433e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1662" , 0x11800809433f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1663" , 0x11800809433f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1664" , 0x1180080943400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1665" , 0x1180080943408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1666" , 0x1180080943410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1667" , 0x1180080943418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1668" , 0x1180080943420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1669" , 0x1180080943428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1670" , 0x1180080943430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1671" , 0x1180080943438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1672" , 0x1180080943440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1673" , 0x1180080943448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1674" , 0x1180080943450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1675" , 0x1180080943458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1676" , 0x1180080943460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1677" , 0x1180080943468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1678" , 0x1180080943470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1679" , 0x1180080943478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1680" , 0x1180080943480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1681" , 0x1180080943488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1682" , 0x1180080943490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1683" , 0x1180080943498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1684" , 0x11800809434a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1685" , 0x11800809434a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1686" , 0x11800809434b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1687" , 0x11800809434b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1688" , 0x11800809434c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1689" , 0x11800809434c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1690" , 0x11800809434d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1691" , 0x11800809434d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1692" , 0x11800809434e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1693" , 0x11800809434e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1694" , 0x11800809434f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1695" , 0x11800809434f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1696" , 0x1180080943500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1697" , 0x1180080943508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1698" , 0x1180080943510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1699" , 0x1180080943518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1700" , 0x1180080943520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1701" , 0x1180080943528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1702" , 0x1180080943530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1703" , 0x1180080943538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1704" , 0x1180080943540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1705" , 0x1180080943548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1706" , 0x1180080943550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1707" , 0x1180080943558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1708" , 0x1180080943560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1709" , 0x1180080943568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1710" , 0x1180080943570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1711" , 0x1180080943578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1712" , 0x1180080943580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1713" , 0x1180080943588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1714" , 0x1180080943590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1715" , 0x1180080943598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1716" , 0x11800809435a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1717" , 0x11800809435a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1718" , 0x11800809435b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1719" , 0x11800809435b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1720" , 0x11800809435c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1721" , 0x11800809435c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1722" , 0x11800809435d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1723" , 0x11800809435d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1724" , 0x11800809435e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1725" , 0x11800809435e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1726" , 0x11800809435f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1727" , 0x11800809435f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1728" , 0x1180080943600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1729" , 0x1180080943608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1730" , 0x1180080943610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1731" , 0x1180080943618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1732" , 0x1180080943620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1733" , 0x1180080943628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1734" , 0x1180080943630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1735" , 0x1180080943638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1736" , 0x1180080943640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1737" , 0x1180080943648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1738" , 0x1180080943650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1739" , 0x1180080943658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1740" , 0x1180080943660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1741" , 0x1180080943668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1742" , 0x1180080943670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1743" , 0x1180080943678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1744" , 0x1180080943680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1745" , 0x1180080943688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1746" , 0x1180080943690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1747" , 0x1180080943698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1748" , 0x11800809436a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1749" , 0x11800809436a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1750" , 0x11800809436b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1751" , 0x11800809436b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1752" , 0x11800809436c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1753" , 0x11800809436c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1754" , 0x11800809436d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1755" , 0x11800809436d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1756" , 0x11800809436e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1757" , 0x11800809436e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1758" , 0x11800809436f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1759" , 0x11800809436f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1760" , 0x1180080943700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1761" , 0x1180080943708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1762" , 0x1180080943710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1763" , 0x1180080943718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1764" , 0x1180080943720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1765" , 0x1180080943728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1766" , 0x1180080943730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1767" , 0x1180080943738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1768" , 0x1180080943740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1769" , 0x1180080943748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1770" , 0x1180080943750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1771" , 0x1180080943758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1772" , 0x1180080943760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1773" , 0x1180080943768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1774" , 0x1180080943770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1775" , 0x1180080943778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1776" , 0x1180080943780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1777" , 0x1180080943788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1778" , 0x1180080943790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1779" , 0x1180080943798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1780" , 0x11800809437a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1781" , 0x11800809437a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1782" , 0x11800809437b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1783" , 0x11800809437b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1784" , 0x11800809437c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1785" , 0x11800809437c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1786" , 0x11800809437d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1787" , 0x11800809437d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1788" , 0x11800809437e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1789" , 0x11800809437e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1790" , 0x11800809437f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1791" , 0x11800809437f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1792" , 0x1180080943800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1793" , 0x1180080943808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1794" , 0x1180080943810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1795" , 0x1180080943818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1796" , 0x1180080943820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1797" , 0x1180080943828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1798" , 0x1180080943830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1799" , 0x1180080943838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1800" , 0x1180080943840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1801" , 0x1180080943848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1802" , 0x1180080943850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1803" , 0x1180080943858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1804" , 0x1180080943860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1805" , 0x1180080943868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1806" , 0x1180080943870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1807" , 0x1180080943878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1808" , 0x1180080943880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1809" , 0x1180080943888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1810" , 0x1180080943890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1811" , 0x1180080943898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1812" , 0x11800809438a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1813" , 0x11800809438a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1814" , 0x11800809438b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1815" , 0x11800809438b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1816" , 0x11800809438c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1817" , 0x11800809438c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1818" , 0x11800809438d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1819" , 0x11800809438d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1820" , 0x11800809438e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1821" , 0x11800809438e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1822" , 0x11800809438f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1823" , 0x11800809438f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1824" , 0x1180080943900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1825" , 0x1180080943908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1826" , 0x1180080943910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1827" , 0x1180080943918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1828" , 0x1180080943920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1829" , 0x1180080943928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1830" , 0x1180080943930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1831" , 0x1180080943938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1832" , 0x1180080943940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1833" , 0x1180080943948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1834" , 0x1180080943950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1835" , 0x1180080943958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1836" , 0x1180080943960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1837" , 0x1180080943968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1838" , 0x1180080943970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1839" , 0x1180080943978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1840" , 0x1180080943980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1841" , 0x1180080943988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1842" , 0x1180080943990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1843" , 0x1180080943998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1844" , 0x11800809439a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1845" , 0x11800809439a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1846" , 0x11800809439b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1847" , 0x11800809439b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1848" , 0x11800809439c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1849" , 0x11800809439c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1850" , 0x11800809439d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1851" , 0x11800809439d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1852" , 0x11800809439e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1853" , 0x11800809439e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1854" , 0x11800809439f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1855" , 0x11800809439f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1856" , 0x1180080943a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1857" , 0x1180080943a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1858" , 0x1180080943a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1859" , 0x1180080943a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1860" , 0x1180080943a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1861" , 0x1180080943a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1862" , 0x1180080943a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1863" , 0x1180080943a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1864" , 0x1180080943a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1865" , 0x1180080943a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1866" , 0x1180080943a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1867" , 0x1180080943a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1868" , 0x1180080943a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1869" , 0x1180080943a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1870" , 0x1180080943a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1871" , 0x1180080943a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1872" , 0x1180080943a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1873" , 0x1180080943a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1874" , 0x1180080943a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1875" , 0x1180080943a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1876" , 0x1180080943aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1877" , 0x1180080943aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1878" , 0x1180080943ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1879" , 0x1180080943ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1880" , 0x1180080943ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1881" , 0x1180080943ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1882" , 0x1180080943ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1883" , 0x1180080943ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1884" , 0x1180080943ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1885" , 0x1180080943ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1886" , 0x1180080943af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1887" , 0x1180080943af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1888" , 0x1180080943b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1889" , 0x1180080943b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1890" , 0x1180080943b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1891" , 0x1180080943b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1892" , 0x1180080943b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1893" , 0x1180080943b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1894" , 0x1180080943b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1895" , 0x1180080943b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1896" , 0x1180080943b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1897" , 0x1180080943b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1898" , 0x1180080943b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1899" , 0x1180080943b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1900" , 0x1180080943b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1901" , 0x1180080943b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1902" , 0x1180080943b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1903" , 0x1180080943b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1904" , 0x1180080943b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1905" , 0x1180080943b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1906" , 0x1180080943b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1907" , 0x1180080943b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1908" , 0x1180080943ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1909" , 0x1180080943ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1910" , 0x1180080943bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1911" , 0x1180080943bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1912" , 0x1180080943bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1913" , 0x1180080943bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1914" , 0x1180080943bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1915" , 0x1180080943bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1916" , 0x1180080943be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1917" , 0x1180080943be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1918" , 0x1180080943bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1919" , 0x1180080943bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1920" , 0x1180080943c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1921" , 0x1180080943c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1922" , 0x1180080943c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1923" , 0x1180080943c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1924" , 0x1180080943c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1925" , 0x1180080943c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1926" , 0x1180080943c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1927" , 0x1180080943c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1928" , 0x1180080943c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1929" , 0x1180080943c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1930" , 0x1180080943c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1931" , 0x1180080943c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1932" , 0x1180080943c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1933" , 0x1180080943c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1934" , 0x1180080943c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1935" , 0x1180080943c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1936" , 0x1180080943c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1937" , 0x1180080943c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1938" , 0x1180080943c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1939" , 0x1180080943c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1940" , 0x1180080943ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1941" , 0x1180080943ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1942" , 0x1180080943cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1943" , 0x1180080943cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1944" , 0x1180080943cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1945" , 0x1180080943cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1946" , 0x1180080943cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1947" , 0x1180080943cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1948" , 0x1180080943ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1949" , 0x1180080943ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1950" , 0x1180080943cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1951" , 0x1180080943cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1952" , 0x1180080943d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1953" , 0x1180080943d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1954" , 0x1180080943d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1955" , 0x1180080943d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1956" , 0x1180080943d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1957" , 0x1180080943d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1958" , 0x1180080943d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1959" , 0x1180080943d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1960" , 0x1180080943d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1961" , 0x1180080943d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1962" , 0x1180080943d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1963" , 0x1180080943d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1964" , 0x1180080943d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1965" , 0x1180080943d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1966" , 0x1180080943d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1967" , 0x1180080943d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1968" , 0x1180080943d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1969" , 0x1180080943d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1970" , 0x1180080943d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1971" , 0x1180080943d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1972" , 0x1180080943da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1973" , 0x1180080943da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1974" , 0x1180080943db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1975" , 0x1180080943db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1976" , 0x1180080943dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1977" , 0x1180080943dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1978" , 0x1180080943dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1979" , 0x1180080943dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1980" , 0x1180080943de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1981" , 0x1180080943de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1982" , 0x1180080943df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1983" , 0x1180080943df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1984" , 0x1180080943e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1985" , 0x1180080943e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1986" , 0x1180080943e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1987" , 0x1180080943e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1988" , 0x1180080943e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1989" , 0x1180080943e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1990" , 0x1180080943e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1991" , 0x1180080943e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1992" , 0x1180080943e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1993" , 0x1180080943e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1994" , 0x1180080943e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1995" , 0x1180080943e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1996" , 0x1180080943e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1997" , 0x1180080943e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1998" , 0x1180080943e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP1999" , 0x1180080943e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2000" , 0x1180080943e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2001" , 0x1180080943e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2002" , 0x1180080943e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2003" , 0x1180080943e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2004" , 0x1180080943ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2005" , 0x1180080943ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2006" , 0x1180080943eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2007" , 0x1180080943eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2008" , 0x1180080943ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2009" , 0x1180080943ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2010" , 0x1180080943ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2011" , 0x1180080943ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2012" , 0x1180080943ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2013" , 0x1180080943ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2014" , 0x1180080943ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2015" , 0x1180080943ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2016" , 0x1180080943f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2017" , 0x1180080943f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2018" , 0x1180080943f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2019" , 0x1180080943f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2020" , 0x1180080943f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2021" , 0x1180080943f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2022" , 0x1180080943f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2023" , 0x1180080943f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2024" , 0x1180080943f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2025" , 0x1180080943f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2026" , 0x1180080943f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2027" , 0x1180080943f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2028" , 0x1180080943f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2029" , 0x1180080943f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2030" , 0x1180080943f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2031" , 0x1180080943f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2032" , 0x1180080943f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2033" , 0x1180080943f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2034" , 0x1180080943f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2035" , 0x1180080943f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2036" , 0x1180080943fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2037" , 0x1180080943fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2038" , 0x1180080943fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2039" , 0x1180080943fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2040" , 0x1180080943fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2041" , 0x1180080943fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2042" , 0x1180080943fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2043" , 0x1180080943fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2044" , 0x1180080943fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2045" , 0x1180080943fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2046" , 0x1180080943ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2047" , 0x1180080943ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2048" , 0x1180080944000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2049" , 0x1180080944008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2050" , 0x1180080944010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2051" , 0x1180080944018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2052" , 0x1180080944020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2053" , 0x1180080944028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2054" , 0x1180080944030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2055" , 0x1180080944038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2056" , 0x1180080944040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2057" , 0x1180080944048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2058" , 0x1180080944050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2059" , 0x1180080944058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2060" , 0x1180080944060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2061" , 0x1180080944068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2062" , 0x1180080944070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2063" , 0x1180080944078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2064" , 0x1180080944080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2065" , 0x1180080944088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2066" , 0x1180080944090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2067" , 0x1180080944098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2068" , 0x11800809440a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2069" , 0x11800809440a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2070" , 0x11800809440b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2071" , 0x11800809440b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2072" , 0x11800809440c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2073" , 0x11800809440c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2074" , 0x11800809440d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2075" , 0x11800809440d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2076" , 0x11800809440e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2077" , 0x11800809440e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2078" , 0x11800809440f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2079" , 0x11800809440f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2080" , 0x1180080944100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2081" , 0x1180080944108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2082" , 0x1180080944110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2083" , 0x1180080944118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2084" , 0x1180080944120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2085" , 0x1180080944128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2086" , 0x1180080944130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2087" , 0x1180080944138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2088" , 0x1180080944140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2089" , 0x1180080944148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2090" , 0x1180080944150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2091" , 0x1180080944158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2092" , 0x1180080944160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2093" , 0x1180080944168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2094" , 0x1180080944170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2095" , 0x1180080944178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2096" , 0x1180080944180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2097" , 0x1180080944188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2098" , 0x1180080944190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2099" , 0x1180080944198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2100" , 0x11800809441a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2101" , 0x11800809441a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2102" , 0x11800809441b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2103" , 0x11800809441b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2104" , 0x11800809441c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2105" , 0x11800809441c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2106" , 0x11800809441d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2107" , 0x11800809441d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2108" , 0x11800809441e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2109" , 0x11800809441e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2110" , 0x11800809441f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2111" , 0x11800809441f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2112" , 0x1180080944200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2113" , 0x1180080944208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2114" , 0x1180080944210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2115" , 0x1180080944218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2116" , 0x1180080944220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2117" , 0x1180080944228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2118" , 0x1180080944230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2119" , 0x1180080944238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2120" , 0x1180080944240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2121" , 0x1180080944248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2122" , 0x1180080944250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2123" , 0x1180080944258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2124" , 0x1180080944260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2125" , 0x1180080944268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2126" , 0x1180080944270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2127" , 0x1180080944278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2128" , 0x1180080944280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2129" , 0x1180080944288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2130" , 0x1180080944290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2131" , 0x1180080944298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2132" , 0x11800809442a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2133" , 0x11800809442a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2134" , 0x11800809442b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2135" , 0x11800809442b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2136" , 0x11800809442c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2137" , 0x11800809442c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2138" , 0x11800809442d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2139" , 0x11800809442d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2140" , 0x11800809442e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2141" , 0x11800809442e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2142" , 0x11800809442f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2143" , 0x11800809442f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2144" , 0x1180080944300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2145" , 0x1180080944308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2146" , 0x1180080944310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2147" , 0x1180080944318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2148" , 0x1180080944320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2149" , 0x1180080944328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2150" , 0x1180080944330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2151" , 0x1180080944338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2152" , 0x1180080944340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2153" , 0x1180080944348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2154" , 0x1180080944350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2155" , 0x1180080944358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2156" , 0x1180080944360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2157" , 0x1180080944368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2158" , 0x1180080944370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2159" , 0x1180080944378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2160" , 0x1180080944380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2161" , 0x1180080944388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2162" , 0x1180080944390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2163" , 0x1180080944398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2164" , 0x11800809443a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2165" , 0x11800809443a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2166" , 0x11800809443b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2167" , 0x11800809443b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2168" , 0x11800809443c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2169" , 0x11800809443c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2170" , 0x11800809443d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2171" , 0x11800809443d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2172" , 0x11800809443e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2173" , 0x11800809443e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2174" , 0x11800809443f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2175" , 0x11800809443f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2176" , 0x1180080944400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2177" , 0x1180080944408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2178" , 0x1180080944410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2179" , 0x1180080944418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2180" , 0x1180080944420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2181" , 0x1180080944428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2182" , 0x1180080944430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2183" , 0x1180080944438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2184" , 0x1180080944440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2185" , 0x1180080944448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2186" , 0x1180080944450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2187" , 0x1180080944458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2188" , 0x1180080944460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2189" , 0x1180080944468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2190" , 0x1180080944470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2191" , 0x1180080944478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2192" , 0x1180080944480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2193" , 0x1180080944488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2194" , 0x1180080944490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2195" , 0x1180080944498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2196" , 0x11800809444a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2197" , 0x11800809444a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2198" , 0x11800809444b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2199" , 0x11800809444b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2200" , 0x11800809444c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2201" , 0x11800809444c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2202" , 0x11800809444d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2203" , 0x11800809444d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2204" , 0x11800809444e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2205" , 0x11800809444e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2206" , 0x11800809444f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2207" , 0x11800809444f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2208" , 0x1180080944500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2209" , 0x1180080944508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2210" , 0x1180080944510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2211" , 0x1180080944518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2212" , 0x1180080944520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2213" , 0x1180080944528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2214" , 0x1180080944530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2215" , 0x1180080944538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2216" , 0x1180080944540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2217" , 0x1180080944548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2218" , 0x1180080944550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2219" , 0x1180080944558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2220" , 0x1180080944560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2221" , 0x1180080944568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2222" , 0x1180080944570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2223" , 0x1180080944578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2224" , 0x1180080944580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2225" , 0x1180080944588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2226" , 0x1180080944590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2227" , 0x1180080944598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2228" , 0x11800809445a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2229" , 0x11800809445a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2230" , 0x11800809445b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2231" , 0x11800809445b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2232" , 0x11800809445c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2233" , 0x11800809445c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2234" , 0x11800809445d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2235" , 0x11800809445d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2236" , 0x11800809445e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2237" , 0x11800809445e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2238" , 0x11800809445f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2239" , 0x11800809445f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2240" , 0x1180080944600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2241" , 0x1180080944608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2242" , 0x1180080944610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2243" , 0x1180080944618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2244" , 0x1180080944620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2245" , 0x1180080944628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2246" , 0x1180080944630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2247" , 0x1180080944638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2248" , 0x1180080944640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2249" , 0x1180080944648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2250" , 0x1180080944650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2251" , 0x1180080944658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2252" , 0x1180080944660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2253" , 0x1180080944668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2254" , 0x1180080944670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2255" , 0x1180080944678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2256" , 0x1180080944680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2257" , 0x1180080944688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2258" , 0x1180080944690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2259" , 0x1180080944698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2260" , 0x11800809446a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2261" , 0x11800809446a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2262" , 0x11800809446b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2263" , 0x11800809446b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2264" , 0x11800809446c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2265" , 0x11800809446c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2266" , 0x11800809446d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2267" , 0x11800809446d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2268" , 0x11800809446e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2269" , 0x11800809446e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2270" , 0x11800809446f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2271" , 0x11800809446f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2272" , 0x1180080944700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2273" , 0x1180080944708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2274" , 0x1180080944710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2275" , 0x1180080944718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2276" , 0x1180080944720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2277" , 0x1180080944728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2278" , 0x1180080944730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2279" , 0x1180080944738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2280" , 0x1180080944740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2281" , 0x1180080944748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2282" , 0x1180080944750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2283" , 0x1180080944758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2284" , 0x1180080944760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2285" , 0x1180080944768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2286" , 0x1180080944770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2287" , 0x1180080944778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2288" , 0x1180080944780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2289" , 0x1180080944788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2290" , 0x1180080944790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2291" , 0x1180080944798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2292" , 0x11800809447a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2293" , 0x11800809447a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2294" , 0x11800809447b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2295" , 0x11800809447b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2296" , 0x11800809447c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2297" , 0x11800809447c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2298" , 0x11800809447d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2299" , 0x11800809447d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2300" , 0x11800809447e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2301" , 0x11800809447e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2302" , 0x11800809447f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2303" , 0x11800809447f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2304" , 0x1180080944800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2305" , 0x1180080944808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2306" , 0x1180080944810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2307" , 0x1180080944818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2308" , 0x1180080944820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2309" , 0x1180080944828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2310" , 0x1180080944830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2311" , 0x1180080944838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2312" , 0x1180080944840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2313" , 0x1180080944848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2314" , 0x1180080944850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2315" , 0x1180080944858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2316" , 0x1180080944860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2317" , 0x1180080944868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2318" , 0x1180080944870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2319" , 0x1180080944878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2320" , 0x1180080944880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2321" , 0x1180080944888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2322" , 0x1180080944890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2323" , 0x1180080944898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2324" , 0x11800809448a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2325" , 0x11800809448a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2326" , 0x11800809448b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2327" , 0x11800809448b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2328" , 0x11800809448c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2329" , 0x11800809448c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2330" , 0x11800809448d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2331" , 0x11800809448d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2332" , 0x11800809448e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2333" , 0x11800809448e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2334" , 0x11800809448f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2335" , 0x11800809448f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2336" , 0x1180080944900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2337" , 0x1180080944908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2338" , 0x1180080944910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2339" , 0x1180080944918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2340" , 0x1180080944920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2341" , 0x1180080944928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2342" , 0x1180080944930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2343" , 0x1180080944938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2344" , 0x1180080944940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2345" , 0x1180080944948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2346" , 0x1180080944950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2347" , 0x1180080944958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2348" , 0x1180080944960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2349" , 0x1180080944968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2350" , 0x1180080944970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2351" , 0x1180080944978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2352" , 0x1180080944980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2353" , 0x1180080944988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2354" , 0x1180080944990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2355" , 0x1180080944998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2356" , 0x11800809449a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2357" , 0x11800809449a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2358" , 0x11800809449b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2359" , 0x11800809449b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2360" , 0x11800809449c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2361" , 0x11800809449c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2362" , 0x11800809449d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2363" , 0x11800809449d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2364" , 0x11800809449e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2365" , 0x11800809449e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2366" , 0x11800809449f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2367" , 0x11800809449f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2368" , 0x1180080944a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2369" , 0x1180080944a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2370" , 0x1180080944a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2371" , 0x1180080944a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2372" , 0x1180080944a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2373" , 0x1180080944a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2374" , 0x1180080944a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2375" , 0x1180080944a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2376" , 0x1180080944a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2377" , 0x1180080944a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2378" , 0x1180080944a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2379" , 0x1180080944a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2380" , 0x1180080944a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2381" , 0x1180080944a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2382" , 0x1180080944a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2383" , 0x1180080944a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2384" , 0x1180080944a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2385" , 0x1180080944a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2386" , 0x1180080944a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2387" , 0x1180080944a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2388" , 0x1180080944aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2389" , 0x1180080944aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2390" , 0x1180080944ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2391" , 0x1180080944ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2392" , 0x1180080944ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2393" , 0x1180080944ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2394" , 0x1180080944ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2395" , 0x1180080944ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2396" , 0x1180080944ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2397" , 0x1180080944ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2398" , 0x1180080944af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2399" , 0x1180080944af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2400" , 0x1180080944b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2401" , 0x1180080944b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2402" , 0x1180080944b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2403" , 0x1180080944b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2404" , 0x1180080944b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2405" , 0x1180080944b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2406" , 0x1180080944b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2407" , 0x1180080944b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2408" , 0x1180080944b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2409" , 0x1180080944b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2410" , 0x1180080944b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2411" , 0x1180080944b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2412" , 0x1180080944b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2413" , 0x1180080944b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2414" , 0x1180080944b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2415" , 0x1180080944b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2416" , 0x1180080944b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2417" , 0x1180080944b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2418" , 0x1180080944b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2419" , 0x1180080944b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2420" , 0x1180080944ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2421" , 0x1180080944ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2422" , 0x1180080944bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2423" , 0x1180080944bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2424" , 0x1180080944bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2425" , 0x1180080944bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2426" , 0x1180080944bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2427" , 0x1180080944bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2428" , 0x1180080944be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2429" , 0x1180080944be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2430" , 0x1180080944bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2431" , 0x1180080944bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2432" , 0x1180080944c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2433" , 0x1180080944c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2434" , 0x1180080944c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2435" , 0x1180080944c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2436" , 0x1180080944c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2437" , 0x1180080944c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2438" , 0x1180080944c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2439" , 0x1180080944c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2440" , 0x1180080944c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2441" , 0x1180080944c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2442" , 0x1180080944c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2443" , 0x1180080944c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2444" , 0x1180080944c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2445" , 0x1180080944c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2446" , 0x1180080944c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2447" , 0x1180080944c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2448" , 0x1180080944c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2449" , 0x1180080944c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2450" , 0x1180080944c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2451" , 0x1180080944c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2452" , 0x1180080944ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2453" , 0x1180080944ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2454" , 0x1180080944cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2455" , 0x1180080944cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2456" , 0x1180080944cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2457" , 0x1180080944cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2458" , 0x1180080944cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2459" , 0x1180080944cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2460" , 0x1180080944ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2461" , 0x1180080944ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2462" , 0x1180080944cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2463" , 0x1180080944cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2464" , 0x1180080944d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2465" , 0x1180080944d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2466" , 0x1180080944d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2467" , 0x1180080944d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2468" , 0x1180080944d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2469" , 0x1180080944d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2470" , 0x1180080944d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2471" , 0x1180080944d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2472" , 0x1180080944d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2473" , 0x1180080944d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2474" , 0x1180080944d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2475" , 0x1180080944d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2476" , 0x1180080944d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2477" , 0x1180080944d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2478" , 0x1180080944d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2479" , 0x1180080944d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2480" , 0x1180080944d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2481" , 0x1180080944d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2482" , 0x1180080944d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2483" , 0x1180080944d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2484" , 0x1180080944da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2485" , 0x1180080944da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2486" , 0x1180080944db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2487" , 0x1180080944db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2488" , 0x1180080944dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2489" , 0x1180080944dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2490" , 0x1180080944dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2491" , 0x1180080944dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2492" , 0x1180080944de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2493" , 0x1180080944de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2494" , 0x1180080944df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2495" , 0x1180080944df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2496" , 0x1180080944e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2497" , 0x1180080944e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2498" , 0x1180080944e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2499" , 0x1180080944e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2500" , 0x1180080944e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2501" , 0x1180080944e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2502" , 0x1180080944e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2503" , 0x1180080944e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2504" , 0x1180080944e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2505" , 0x1180080944e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2506" , 0x1180080944e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2507" , 0x1180080944e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2508" , 0x1180080944e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2509" , 0x1180080944e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2510" , 0x1180080944e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2511" , 0x1180080944e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2512" , 0x1180080944e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2513" , 0x1180080944e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2514" , 0x1180080944e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2515" , 0x1180080944e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2516" , 0x1180080944ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2517" , 0x1180080944ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2518" , 0x1180080944eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2519" , 0x1180080944eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2520" , 0x1180080944ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2521" , 0x1180080944ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2522" , 0x1180080944ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2523" , 0x1180080944ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2524" , 0x1180080944ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2525" , 0x1180080944ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2526" , 0x1180080944ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2527" , 0x1180080944ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2528" , 0x1180080944f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2529" , 0x1180080944f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2530" , 0x1180080944f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2531" , 0x1180080944f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2532" , 0x1180080944f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2533" , 0x1180080944f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2534" , 0x1180080944f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2535" , 0x1180080944f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2536" , 0x1180080944f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2537" , 0x1180080944f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2538" , 0x1180080944f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2539" , 0x1180080944f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2540" , 0x1180080944f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2541" , 0x1180080944f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2542" , 0x1180080944f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2543" , 0x1180080944f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2544" , 0x1180080944f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2545" , 0x1180080944f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2546" , 0x1180080944f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2547" , 0x1180080944f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2548" , 0x1180080944fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2549" , 0x1180080944fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2550" , 0x1180080944fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2551" , 0x1180080944fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2552" , 0x1180080944fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2553" , 0x1180080944fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2554" , 0x1180080944fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2555" , 0x1180080944fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2556" , 0x1180080944fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2557" , 0x1180080944fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2558" , 0x1180080944ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2559" , 0x1180080944ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2560" , 0x1180080945000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2561" , 0x1180080945008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2562" , 0x1180080945010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2563" , 0x1180080945018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2564" , 0x1180080945020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2565" , 0x1180080945028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2566" , 0x1180080945030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2567" , 0x1180080945038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2568" , 0x1180080945040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2569" , 0x1180080945048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2570" , 0x1180080945050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2571" , 0x1180080945058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2572" , 0x1180080945060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2573" , 0x1180080945068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2574" , 0x1180080945070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2575" , 0x1180080945078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2576" , 0x1180080945080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2577" , 0x1180080945088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2578" , 0x1180080945090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2579" , 0x1180080945098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2580" , 0x11800809450a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2581" , 0x11800809450a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2582" , 0x11800809450b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2583" , 0x11800809450b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2584" , 0x11800809450c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2585" , 0x11800809450c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2586" , 0x11800809450d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2587" , 0x11800809450d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2588" , 0x11800809450e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2589" , 0x11800809450e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2590" , 0x11800809450f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2591" , 0x11800809450f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2592" , 0x1180080945100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2593" , 0x1180080945108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2594" , 0x1180080945110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2595" , 0x1180080945118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2596" , 0x1180080945120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2597" , 0x1180080945128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2598" , 0x1180080945130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2599" , 0x1180080945138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2600" , 0x1180080945140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2601" , 0x1180080945148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2602" , 0x1180080945150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2603" , 0x1180080945158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2604" , 0x1180080945160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2605" , 0x1180080945168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2606" , 0x1180080945170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2607" , 0x1180080945178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2608" , 0x1180080945180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2609" , 0x1180080945188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2610" , 0x1180080945190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2611" , 0x1180080945198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2612" , 0x11800809451a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2613" , 0x11800809451a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2614" , 0x11800809451b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2615" , 0x11800809451b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2616" , 0x11800809451c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2617" , 0x11800809451c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2618" , 0x11800809451d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2619" , 0x11800809451d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2620" , 0x11800809451e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2621" , 0x11800809451e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2622" , 0x11800809451f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2623" , 0x11800809451f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2624" , 0x1180080945200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2625" , 0x1180080945208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2626" , 0x1180080945210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2627" , 0x1180080945218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2628" , 0x1180080945220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2629" , 0x1180080945228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2630" , 0x1180080945230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2631" , 0x1180080945238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2632" , 0x1180080945240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2633" , 0x1180080945248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2634" , 0x1180080945250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2635" , 0x1180080945258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2636" , 0x1180080945260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2637" , 0x1180080945268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2638" , 0x1180080945270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2639" , 0x1180080945278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2640" , 0x1180080945280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2641" , 0x1180080945288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2642" , 0x1180080945290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2643" , 0x1180080945298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2644" , 0x11800809452a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2645" , 0x11800809452a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2646" , 0x11800809452b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2647" , 0x11800809452b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2648" , 0x11800809452c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2649" , 0x11800809452c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2650" , 0x11800809452d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2651" , 0x11800809452d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2652" , 0x11800809452e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2653" , 0x11800809452e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2654" , 0x11800809452f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2655" , 0x11800809452f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2656" , 0x1180080945300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2657" , 0x1180080945308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2658" , 0x1180080945310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2659" , 0x1180080945318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2660" , 0x1180080945320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2661" , 0x1180080945328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2662" , 0x1180080945330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2663" , 0x1180080945338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2664" , 0x1180080945340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2665" , 0x1180080945348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2666" , 0x1180080945350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2667" , 0x1180080945358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2668" , 0x1180080945360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2669" , 0x1180080945368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2670" , 0x1180080945370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2671" , 0x1180080945378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2672" , 0x1180080945380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2673" , 0x1180080945388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2674" , 0x1180080945390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2675" , 0x1180080945398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2676" , 0x11800809453a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2677" , 0x11800809453a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2678" , 0x11800809453b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2679" , 0x11800809453b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2680" , 0x11800809453c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2681" , 0x11800809453c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2682" , 0x11800809453d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2683" , 0x11800809453d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2684" , 0x11800809453e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2685" , 0x11800809453e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2686" , 0x11800809453f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2687" , 0x11800809453f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2688" , 0x1180080945400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2689" , 0x1180080945408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2690" , 0x1180080945410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2691" , 0x1180080945418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2692" , 0x1180080945420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2693" , 0x1180080945428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2694" , 0x1180080945430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2695" , 0x1180080945438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2696" , 0x1180080945440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2697" , 0x1180080945448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2698" , 0x1180080945450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2699" , 0x1180080945458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2700" , 0x1180080945460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2701" , 0x1180080945468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2702" , 0x1180080945470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2703" , 0x1180080945478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2704" , 0x1180080945480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2705" , 0x1180080945488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2706" , 0x1180080945490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2707" , 0x1180080945498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2708" , 0x11800809454a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2709" , 0x11800809454a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2710" , 0x11800809454b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2711" , 0x11800809454b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2712" , 0x11800809454c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2713" , 0x11800809454c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2714" , 0x11800809454d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2715" , 0x11800809454d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2716" , 0x11800809454e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2717" , 0x11800809454e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2718" , 0x11800809454f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2719" , 0x11800809454f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2720" , 0x1180080945500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2721" , 0x1180080945508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2722" , 0x1180080945510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2723" , 0x1180080945518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2724" , 0x1180080945520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2725" , 0x1180080945528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2726" , 0x1180080945530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2727" , 0x1180080945538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2728" , 0x1180080945540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2729" , 0x1180080945548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2730" , 0x1180080945550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2731" , 0x1180080945558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2732" , 0x1180080945560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2733" , 0x1180080945568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2734" , 0x1180080945570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2735" , 0x1180080945578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2736" , 0x1180080945580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2737" , 0x1180080945588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2738" , 0x1180080945590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2739" , 0x1180080945598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2740" , 0x11800809455a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2741" , 0x11800809455a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2742" , 0x11800809455b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2743" , 0x11800809455b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2744" , 0x11800809455c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2745" , 0x11800809455c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2746" , 0x11800809455d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2747" , 0x11800809455d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2748" , 0x11800809455e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2749" , 0x11800809455e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2750" , 0x11800809455f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2751" , 0x11800809455f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2752" , 0x1180080945600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2753" , 0x1180080945608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2754" , 0x1180080945610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2755" , 0x1180080945618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2756" , 0x1180080945620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2757" , 0x1180080945628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2758" , 0x1180080945630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2759" , 0x1180080945638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2760" , 0x1180080945640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2761" , 0x1180080945648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2762" , 0x1180080945650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2763" , 0x1180080945658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2764" , 0x1180080945660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2765" , 0x1180080945668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2766" , 0x1180080945670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2767" , 0x1180080945678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2768" , 0x1180080945680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2769" , 0x1180080945688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2770" , 0x1180080945690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2771" , 0x1180080945698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2772" , 0x11800809456a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2773" , 0x11800809456a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2774" , 0x11800809456b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2775" , 0x11800809456b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2776" , 0x11800809456c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2777" , 0x11800809456c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2778" , 0x11800809456d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2779" , 0x11800809456d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2780" , 0x11800809456e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2781" , 0x11800809456e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2782" , 0x11800809456f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2783" , 0x11800809456f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2784" , 0x1180080945700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2785" , 0x1180080945708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2786" , 0x1180080945710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2787" , 0x1180080945718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2788" , 0x1180080945720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2789" , 0x1180080945728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2790" , 0x1180080945730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2791" , 0x1180080945738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2792" , 0x1180080945740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2793" , 0x1180080945748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2794" , 0x1180080945750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2795" , 0x1180080945758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2796" , 0x1180080945760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2797" , 0x1180080945768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2798" , 0x1180080945770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2799" , 0x1180080945778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2800" , 0x1180080945780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2801" , 0x1180080945788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2802" , 0x1180080945790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2803" , 0x1180080945798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2804" , 0x11800809457a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2805" , 0x11800809457a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2806" , 0x11800809457b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2807" , 0x11800809457b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2808" , 0x11800809457c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2809" , 0x11800809457c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2810" , 0x11800809457d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2811" , 0x11800809457d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2812" , 0x11800809457e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2813" , 0x11800809457e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2814" , 0x11800809457f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2815" , 0x11800809457f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2816" , 0x1180080945800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2817" , 0x1180080945808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2818" , 0x1180080945810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2819" , 0x1180080945818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2820" , 0x1180080945820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2821" , 0x1180080945828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2822" , 0x1180080945830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2823" , 0x1180080945838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2824" , 0x1180080945840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2825" , 0x1180080945848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2826" , 0x1180080945850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2827" , 0x1180080945858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2828" , 0x1180080945860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2829" , 0x1180080945868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2830" , 0x1180080945870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2831" , 0x1180080945878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2832" , 0x1180080945880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2833" , 0x1180080945888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2834" , 0x1180080945890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2835" , 0x1180080945898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2836" , 0x11800809458a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2837" , 0x11800809458a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2838" , 0x11800809458b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2839" , 0x11800809458b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2840" , 0x11800809458c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2841" , 0x11800809458c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2842" , 0x11800809458d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2843" , 0x11800809458d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2844" , 0x11800809458e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2845" , 0x11800809458e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2846" , 0x11800809458f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2847" , 0x11800809458f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2848" , 0x1180080945900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2849" , 0x1180080945908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2850" , 0x1180080945910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2851" , 0x1180080945918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2852" , 0x1180080945920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2853" , 0x1180080945928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2854" , 0x1180080945930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2855" , 0x1180080945938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2856" , 0x1180080945940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2857" , 0x1180080945948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2858" , 0x1180080945950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2859" , 0x1180080945958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2860" , 0x1180080945960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2861" , 0x1180080945968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2862" , 0x1180080945970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2863" , 0x1180080945978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2864" , 0x1180080945980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2865" , 0x1180080945988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2866" , 0x1180080945990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2867" , 0x1180080945998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2868" , 0x11800809459a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2869" , 0x11800809459a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2870" , 0x11800809459b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2871" , 0x11800809459b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2872" , 0x11800809459c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2873" , 0x11800809459c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2874" , 0x11800809459d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2875" , 0x11800809459d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2876" , 0x11800809459e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2877" , 0x11800809459e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2878" , 0x11800809459f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2879" , 0x11800809459f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2880" , 0x1180080945a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2881" , 0x1180080945a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2882" , 0x1180080945a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2883" , 0x1180080945a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2884" , 0x1180080945a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2885" , 0x1180080945a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2886" , 0x1180080945a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2887" , 0x1180080945a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2888" , 0x1180080945a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2889" , 0x1180080945a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2890" , 0x1180080945a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2891" , 0x1180080945a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2892" , 0x1180080945a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2893" , 0x1180080945a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2894" , 0x1180080945a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2895" , 0x1180080945a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2896" , 0x1180080945a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2897" , 0x1180080945a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2898" , 0x1180080945a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2899" , 0x1180080945a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2900" , 0x1180080945aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2901" , 0x1180080945aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2902" , 0x1180080945ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2903" , 0x1180080945ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2904" , 0x1180080945ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2905" , 0x1180080945ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2906" , 0x1180080945ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2907" , 0x1180080945ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2908" , 0x1180080945ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2909" , 0x1180080945ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2910" , 0x1180080945af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2911" , 0x1180080945af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2912" , 0x1180080945b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2913" , 0x1180080945b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2914" , 0x1180080945b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2915" , 0x1180080945b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2916" , 0x1180080945b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2917" , 0x1180080945b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2918" , 0x1180080945b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2919" , 0x1180080945b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2920" , 0x1180080945b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2921" , 0x1180080945b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2922" , 0x1180080945b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2923" , 0x1180080945b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2924" , 0x1180080945b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2925" , 0x1180080945b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2926" , 0x1180080945b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2927" , 0x1180080945b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2928" , 0x1180080945b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2929" , 0x1180080945b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2930" , 0x1180080945b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2931" , 0x1180080945b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2932" , 0x1180080945ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2933" , 0x1180080945ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2934" , 0x1180080945bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2935" , 0x1180080945bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2936" , 0x1180080945bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2937" , 0x1180080945bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2938" , 0x1180080945bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2939" , 0x1180080945bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2940" , 0x1180080945be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2941" , 0x1180080945be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2942" , 0x1180080945bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2943" , 0x1180080945bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2944" , 0x1180080945c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2945" , 0x1180080945c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2946" , 0x1180080945c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2947" , 0x1180080945c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2948" , 0x1180080945c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2949" , 0x1180080945c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2950" , 0x1180080945c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2951" , 0x1180080945c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2952" , 0x1180080945c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2953" , 0x1180080945c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2954" , 0x1180080945c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2955" , 0x1180080945c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2956" , 0x1180080945c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2957" , 0x1180080945c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2958" , 0x1180080945c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2959" , 0x1180080945c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2960" , 0x1180080945c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2961" , 0x1180080945c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2962" , 0x1180080945c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2963" , 0x1180080945c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2964" , 0x1180080945ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2965" , 0x1180080945ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2966" , 0x1180080945cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2967" , 0x1180080945cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2968" , 0x1180080945cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2969" , 0x1180080945cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2970" , 0x1180080945cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2971" , 0x1180080945cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2972" , 0x1180080945ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2973" , 0x1180080945ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2974" , 0x1180080945cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2975" , 0x1180080945cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2976" , 0x1180080945d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2977" , 0x1180080945d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2978" , 0x1180080945d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2979" , 0x1180080945d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2980" , 0x1180080945d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2981" , 0x1180080945d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2982" , 0x1180080945d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2983" , 0x1180080945d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2984" , 0x1180080945d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2985" , 0x1180080945d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2986" , 0x1180080945d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2987" , 0x1180080945d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2988" , 0x1180080945d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2989" , 0x1180080945d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2990" , 0x1180080945d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2991" , 0x1180080945d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2992" , 0x1180080945d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2993" , 0x1180080945d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2994" , 0x1180080945d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2995" , 0x1180080945d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2996" , 0x1180080945da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2997" , 0x1180080945da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2998" , 0x1180080945db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP2999" , 0x1180080945db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3000" , 0x1180080945dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3001" , 0x1180080945dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3002" , 0x1180080945dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3003" , 0x1180080945dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3004" , 0x1180080945de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3005" , 0x1180080945de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3006" , 0x1180080945df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3007" , 0x1180080945df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3008" , 0x1180080945e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3009" , 0x1180080945e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3010" , 0x1180080945e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3011" , 0x1180080945e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3012" , 0x1180080945e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3013" , 0x1180080945e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3014" , 0x1180080945e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3015" , 0x1180080945e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3016" , 0x1180080945e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3017" , 0x1180080945e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3018" , 0x1180080945e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3019" , 0x1180080945e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3020" , 0x1180080945e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3021" , 0x1180080945e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3022" , 0x1180080945e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3023" , 0x1180080945e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3024" , 0x1180080945e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3025" , 0x1180080945e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3026" , 0x1180080945e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3027" , 0x1180080945e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3028" , 0x1180080945ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3029" , 0x1180080945ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3030" , 0x1180080945eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3031" , 0x1180080945eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3032" , 0x1180080945ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3033" , 0x1180080945ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3034" , 0x1180080945ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3035" , 0x1180080945ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3036" , 0x1180080945ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3037" , 0x1180080945ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3038" , 0x1180080945ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3039" , 0x1180080945ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3040" , 0x1180080945f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3041" , 0x1180080945f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3042" , 0x1180080945f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3043" , 0x1180080945f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3044" , 0x1180080945f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3045" , 0x1180080945f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3046" , 0x1180080945f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3047" , 0x1180080945f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3048" , 0x1180080945f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3049" , 0x1180080945f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3050" , 0x1180080945f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3051" , 0x1180080945f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3052" , 0x1180080945f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3053" , 0x1180080945f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3054" , 0x1180080945f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3055" , 0x1180080945f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3056" , 0x1180080945f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3057" , 0x1180080945f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3058" , 0x1180080945f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3059" , 0x1180080945f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3060" , 0x1180080945fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3061" , 0x1180080945fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3062" , 0x1180080945fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3063" , 0x1180080945fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3064" , 0x1180080945fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3065" , 0x1180080945fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3066" , 0x1180080945fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3067" , 0x1180080945fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3068" , 0x1180080945fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3069" , 0x1180080945fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3070" , 0x1180080945ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3071" , 0x1180080945ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3072" , 0x1180080946000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3073" , 0x1180080946008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3074" , 0x1180080946010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3075" , 0x1180080946018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3076" , 0x1180080946020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3077" , 0x1180080946028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3078" , 0x1180080946030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3079" , 0x1180080946038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3080" , 0x1180080946040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3081" , 0x1180080946048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3082" , 0x1180080946050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3083" , 0x1180080946058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3084" , 0x1180080946060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3085" , 0x1180080946068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3086" , 0x1180080946070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3087" , 0x1180080946078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3088" , 0x1180080946080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3089" , 0x1180080946088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3090" , 0x1180080946090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3091" , 0x1180080946098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3092" , 0x11800809460a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3093" , 0x11800809460a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3094" , 0x11800809460b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3095" , 0x11800809460b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3096" , 0x11800809460c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3097" , 0x11800809460c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3098" , 0x11800809460d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3099" , 0x11800809460d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3100" , 0x11800809460e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3101" , 0x11800809460e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3102" , 0x11800809460f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3103" , 0x11800809460f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3104" , 0x1180080946100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3105" , 0x1180080946108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3106" , 0x1180080946110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3107" , 0x1180080946118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3108" , 0x1180080946120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3109" , 0x1180080946128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3110" , 0x1180080946130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3111" , 0x1180080946138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3112" , 0x1180080946140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3113" , 0x1180080946148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3114" , 0x1180080946150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3115" , 0x1180080946158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3116" , 0x1180080946160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3117" , 0x1180080946168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3118" , 0x1180080946170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3119" , 0x1180080946178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3120" , 0x1180080946180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3121" , 0x1180080946188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3122" , 0x1180080946190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3123" , 0x1180080946198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3124" , 0x11800809461a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3125" , 0x11800809461a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3126" , 0x11800809461b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3127" , 0x11800809461b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3128" , 0x11800809461c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3129" , 0x11800809461c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3130" , 0x11800809461d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3131" , 0x11800809461d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3132" , 0x11800809461e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3133" , 0x11800809461e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3134" , 0x11800809461f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3135" , 0x11800809461f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3136" , 0x1180080946200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3137" , 0x1180080946208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3138" , 0x1180080946210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3139" , 0x1180080946218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3140" , 0x1180080946220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3141" , 0x1180080946228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3142" , 0x1180080946230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3143" , 0x1180080946238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3144" , 0x1180080946240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3145" , 0x1180080946248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3146" , 0x1180080946250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3147" , 0x1180080946258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3148" , 0x1180080946260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3149" , 0x1180080946268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3150" , 0x1180080946270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3151" , 0x1180080946278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3152" , 0x1180080946280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3153" , 0x1180080946288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3154" , 0x1180080946290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3155" , 0x1180080946298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3156" , 0x11800809462a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3157" , 0x11800809462a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3158" , 0x11800809462b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3159" , 0x11800809462b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3160" , 0x11800809462c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3161" , 0x11800809462c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3162" , 0x11800809462d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3163" , 0x11800809462d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3164" , 0x11800809462e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3165" , 0x11800809462e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3166" , 0x11800809462f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3167" , 0x11800809462f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3168" , 0x1180080946300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3169" , 0x1180080946308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3170" , 0x1180080946310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3171" , 0x1180080946318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3172" , 0x1180080946320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3173" , 0x1180080946328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3174" , 0x1180080946330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3175" , 0x1180080946338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3176" , 0x1180080946340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3177" , 0x1180080946348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3178" , 0x1180080946350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3179" , 0x1180080946358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3180" , 0x1180080946360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3181" , 0x1180080946368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3182" , 0x1180080946370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3183" , 0x1180080946378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3184" , 0x1180080946380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3185" , 0x1180080946388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3186" , 0x1180080946390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3187" , 0x1180080946398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3188" , 0x11800809463a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3189" , 0x11800809463a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3190" , 0x11800809463b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3191" , 0x11800809463b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3192" , 0x11800809463c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3193" , 0x11800809463c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3194" , 0x11800809463d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3195" , 0x11800809463d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3196" , 0x11800809463e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3197" , 0x11800809463e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3198" , 0x11800809463f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3199" , 0x11800809463f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3200" , 0x1180080946400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3201" , 0x1180080946408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3202" , 0x1180080946410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3203" , 0x1180080946418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3204" , 0x1180080946420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3205" , 0x1180080946428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3206" , 0x1180080946430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3207" , 0x1180080946438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3208" , 0x1180080946440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3209" , 0x1180080946448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3210" , 0x1180080946450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3211" , 0x1180080946458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3212" , 0x1180080946460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3213" , 0x1180080946468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3214" , 0x1180080946470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3215" , 0x1180080946478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3216" , 0x1180080946480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3217" , 0x1180080946488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3218" , 0x1180080946490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3219" , 0x1180080946498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3220" , 0x11800809464a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3221" , 0x11800809464a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3222" , 0x11800809464b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3223" , 0x11800809464b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3224" , 0x11800809464c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3225" , 0x11800809464c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3226" , 0x11800809464d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3227" , 0x11800809464d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3228" , 0x11800809464e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3229" , 0x11800809464e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3230" , 0x11800809464f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3231" , 0x11800809464f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3232" , 0x1180080946500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3233" , 0x1180080946508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3234" , 0x1180080946510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3235" , 0x1180080946518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3236" , 0x1180080946520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3237" , 0x1180080946528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3238" , 0x1180080946530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3239" , 0x1180080946538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3240" , 0x1180080946540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3241" , 0x1180080946548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3242" , 0x1180080946550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3243" , 0x1180080946558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3244" , 0x1180080946560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3245" , 0x1180080946568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3246" , 0x1180080946570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3247" , 0x1180080946578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3248" , 0x1180080946580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3249" , 0x1180080946588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3250" , 0x1180080946590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3251" , 0x1180080946598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3252" , 0x11800809465a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3253" , 0x11800809465a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3254" , 0x11800809465b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3255" , 0x11800809465b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3256" , 0x11800809465c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3257" , 0x11800809465c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3258" , 0x11800809465d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3259" , 0x11800809465d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3260" , 0x11800809465e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3261" , 0x11800809465e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3262" , 0x11800809465f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3263" , 0x11800809465f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3264" , 0x1180080946600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3265" , 0x1180080946608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3266" , 0x1180080946610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3267" , 0x1180080946618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3268" , 0x1180080946620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3269" , 0x1180080946628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3270" , 0x1180080946630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3271" , 0x1180080946638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3272" , 0x1180080946640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3273" , 0x1180080946648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3274" , 0x1180080946650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3275" , 0x1180080946658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3276" , 0x1180080946660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3277" , 0x1180080946668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3278" , 0x1180080946670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3279" , 0x1180080946678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3280" , 0x1180080946680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3281" , 0x1180080946688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3282" , 0x1180080946690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3283" , 0x1180080946698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3284" , 0x11800809466a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3285" , 0x11800809466a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3286" , 0x11800809466b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3287" , 0x11800809466b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3288" , 0x11800809466c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3289" , 0x11800809466c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3290" , 0x11800809466d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3291" , 0x11800809466d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3292" , 0x11800809466e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3293" , 0x11800809466e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3294" , 0x11800809466f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3295" , 0x11800809466f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3296" , 0x1180080946700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3297" , 0x1180080946708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3298" , 0x1180080946710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3299" , 0x1180080946718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3300" , 0x1180080946720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3301" , 0x1180080946728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3302" , 0x1180080946730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3303" , 0x1180080946738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3304" , 0x1180080946740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3305" , 0x1180080946748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3306" , 0x1180080946750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3307" , 0x1180080946758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3308" , 0x1180080946760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3309" , 0x1180080946768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3310" , 0x1180080946770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3311" , 0x1180080946778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3312" , 0x1180080946780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3313" , 0x1180080946788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3314" , 0x1180080946790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3315" , 0x1180080946798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3316" , 0x11800809467a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3317" , 0x11800809467a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3318" , 0x11800809467b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3319" , 0x11800809467b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3320" , 0x11800809467c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3321" , 0x11800809467c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3322" , 0x11800809467d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3323" , 0x11800809467d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3324" , 0x11800809467e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3325" , 0x11800809467e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3326" , 0x11800809467f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3327" , 0x11800809467f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3328" , 0x1180080946800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3329" , 0x1180080946808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3330" , 0x1180080946810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3331" , 0x1180080946818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3332" , 0x1180080946820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3333" , 0x1180080946828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3334" , 0x1180080946830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3335" , 0x1180080946838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3336" , 0x1180080946840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3337" , 0x1180080946848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3338" , 0x1180080946850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3339" , 0x1180080946858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3340" , 0x1180080946860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3341" , 0x1180080946868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3342" , 0x1180080946870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3343" , 0x1180080946878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3344" , 0x1180080946880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3345" , 0x1180080946888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3346" , 0x1180080946890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3347" , 0x1180080946898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3348" , 0x11800809468a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3349" , 0x11800809468a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3350" , 0x11800809468b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3351" , 0x11800809468b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3352" , 0x11800809468c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3353" , 0x11800809468c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3354" , 0x11800809468d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3355" , 0x11800809468d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3356" , 0x11800809468e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3357" , 0x11800809468e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3358" , 0x11800809468f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3359" , 0x11800809468f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3360" , 0x1180080946900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3361" , 0x1180080946908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3362" , 0x1180080946910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3363" , 0x1180080946918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3364" , 0x1180080946920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3365" , 0x1180080946928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3366" , 0x1180080946930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3367" , 0x1180080946938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3368" , 0x1180080946940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3369" , 0x1180080946948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3370" , 0x1180080946950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3371" , 0x1180080946958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3372" , 0x1180080946960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3373" , 0x1180080946968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3374" , 0x1180080946970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3375" , 0x1180080946978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3376" , 0x1180080946980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3377" , 0x1180080946988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3378" , 0x1180080946990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3379" , 0x1180080946998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3380" , 0x11800809469a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3381" , 0x11800809469a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3382" , 0x11800809469b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3383" , 0x11800809469b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3384" , 0x11800809469c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3385" , 0x11800809469c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3386" , 0x11800809469d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3387" , 0x11800809469d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3388" , 0x11800809469e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3389" , 0x11800809469e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3390" , 0x11800809469f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3391" , 0x11800809469f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3392" , 0x1180080946a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3393" , 0x1180080946a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3394" , 0x1180080946a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3395" , 0x1180080946a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3396" , 0x1180080946a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3397" , 0x1180080946a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3398" , 0x1180080946a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3399" , 0x1180080946a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3400" , 0x1180080946a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3401" , 0x1180080946a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3402" , 0x1180080946a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3403" , 0x1180080946a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3404" , 0x1180080946a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3405" , 0x1180080946a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3406" , 0x1180080946a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3407" , 0x1180080946a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3408" , 0x1180080946a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3409" , 0x1180080946a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3410" , 0x1180080946a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3411" , 0x1180080946a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3412" , 0x1180080946aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3413" , 0x1180080946aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3414" , 0x1180080946ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3415" , 0x1180080946ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3416" , 0x1180080946ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3417" , 0x1180080946ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3418" , 0x1180080946ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3419" , 0x1180080946ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3420" , 0x1180080946ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3421" , 0x1180080946ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3422" , 0x1180080946af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3423" , 0x1180080946af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3424" , 0x1180080946b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3425" , 0x1180080946b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3426" , 0x1180080946b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3427" , 0x1180080946b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3428" , 0x1180080946b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3429" , 0x1180080946b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3430" , 0x1180080946b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3431" , 0x1180080946b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3432" , 0x1180080946b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3433" , 0x1180080946b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3434" , 0x1180080946b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3435" , 0x1180080946b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3436" , 0x1180080946b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3437" , 0x1180080946b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3438" , 0x1180080946b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3439" , 0x1180080946b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3440" , 0x1180080946b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3441" , 0x1180080946b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3442" , 0x1180080946b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3443" , 0x1180080946b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3444" , 0x1180080946ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3445" , 0x1180080946ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3446" , 0x1180080946bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3447" , 0x1180080946bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3448" , 0x1180080946bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3449" , 0x1180080946bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3450" , 0x1180080946bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3451" , 0x1180080946bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3452" , 0x1180080946be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3453" , 0x1180080946be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3454" , 0x1180080946bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3455" , 0x1180080946bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3456" , 0x1180080946c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3457" , 0x1180080946c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3458" , 0x1180080946c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3459" , 0x1180080946c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3460" , 0x1180080946c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3461" , 0x1180080946c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3462" , 0x1180080946c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3463" , 0x1180080946c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3464" , 0x1180080946c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3465" , 0x1180080946c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3466" , 0x1180080946c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3467" , 0x1180080946c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3468" , 0x1180080946c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3469" , 0x1180080946c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3470" , 0x1180080946c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3471" , 0x1180080946c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3472" , 0x1180080946c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3473" , 0x1180080946c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3474" , 0x1180080946c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3475" , 0x1180080946c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3476" , 0x1180080946ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3477" , 0x1180080946ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3478" , 0x1180080946cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3479" , 0x1180080946cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3480" , 0x1180080946cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3481" , 0x1180080946cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3482" , 0x1180080946cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3483" , 0x1180080946cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3484" , 0x1180080946ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3485" , 0x1180080946ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3486" , 0x1180080946cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3487" , 0x1180080946cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3488" , 0x1180080946d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3489" , 0x1180080946d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3490" , 0x1180080946d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3491" , 0x1180080946d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3492" , 0x1180080946d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3493" , 0x1180080946d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3494" , 0x1180080946d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3495" , 0x1180080946d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3496" , 0x1180080946d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3497" , 0x1180080946d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3498" , 0x1180080946d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3499" , 0x1180080946d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3500" , 0x1180080946d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3501" , 0x1180080946d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3502" , 0x1180080946d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3503" , 0x1180080946d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3504" , 0x1180080946d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3505" , 0x1180080946d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3506" , 0x1180080946d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3507" , 0x1180080946d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3508" , 0x1180080946da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3509" , 0x1180080946da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3510" , 0x1180080946db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3511" , 0x1180080946db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3512" , 0x1180080946dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3513" , 0x1180080946dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3514" , 0x1180080946dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3515" , 0x1180080946dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3516" , 0x1180080946de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3517" , 0x1180080946de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3518" , 0x1180080946df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3519" , 0x1180080946df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3520" , 0x1180080946e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3521" , 0x1180080946e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3522" , 0x1180080946e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3523" , 0x1180080946e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3524" , 0x1180080946e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3525" , 0x1180080946e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3526" , 0x1180080946e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3527" , 0x1180080946e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3528" , 0x1180080946e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3529" , 0x1180080946e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3530" , 0x1180080946e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3531" , 0x1180080946e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3532" , 0x1180080946e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3533" , 0x1180080946e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3534" , 0x1180080946e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3535" , 0x1180080946e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3536" , 0x1180080946e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3537" , 0x1180080946e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3538" , 0x1180080946e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3539" , 0x1180080946e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3540" , 0x1180080946ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3541" , 0x1180080946ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3542" , 0x1180080946eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3543" , 0x1180080946eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3544" , 0x1180080946ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3545" , 0x1180080946ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3546" , 0x1180080946ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3547" , 0x1180080946ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3548" , 0x1180080946ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3549" , 0x1180080946ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3550" , 0x1180080946ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3551" , 0x1180080946ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3552" , 0x1180080946f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3553" , 0x1180080946f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3554" , 0x1180080946f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3555" , 0x1180080946f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3556" , 0x1180080946f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3557" , 0x1180080946f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3558" , 0x1180080946f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3559" , 0x1180080946f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3560" , 0x1180080946f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3561" , 0x1180080946f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3562" , 0x1180080946f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3563" , 0x1180080946f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3564" , 0x1180080946f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3565" , 0x1180080946f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3566" , 0x1180080946f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3567" , 0x1180080946f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3568" , 0x1180080946f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3569" , 0x1180080946f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3570" , 0x1180080946f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3571" , 0x1180080946f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3572" , 0x1180080946fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3573" , 0x1180080946fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3574" , 0x1180080946fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3575" , 0x1180080946fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3576" , 0x1180080946fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3577" , 0x1180080946fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3578" , 0x1180080946fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3579" , 0x1180080946fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3580" , 0x1180080946fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3581" , 0x1180080946fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3582" , 0x1180080946ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3583" , 0x1180080946ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3584" , 0x1180080947000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3585" , 0x1180080947008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3586" , 0x1180080947010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3587" , 0x1180080947018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3588" , 0x1180080947020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3589" , 0x1180080947028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3590" , 0x1180080947030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3591" , 0x1180080947038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3592" , 0x1180080947040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3593" , 0x1180080947048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3594" , 0x1180080947050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3595" , 0x1180080947058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3596" , 0x1180080947060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3597" , 0x1180080947068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3598" , 0x1180080947070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3599" , 0x1180080947078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3600" , 0x1180080947080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3601" , 0x1180080947088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3602" , 0x1180080947090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3603" , 0x1180080947098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3604" , 0x11800809470a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3605" , 0x11800809470a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3606" , 0x11800809470b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3607" , 0x11800809470b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3608" , 0x11800809470c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3609" , 0x11800809470c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3610" , 0x11800809470d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3611" , 0x11800809470d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3612" , 0x11800809470e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3613" , 0x11800809470e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3614" , 0x11800809470f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3615" , 0x11800809470f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3616" , 0x1180080947100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3617" , 0x1180080947108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3618" , 0x1180080947110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3619" , 0x1180080947118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3620" , 0x1180080947120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3621" , 0x1180080947128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3622" , 0x1180080947130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3623" , 0x1180080947138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3624" , 0x1180080947140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3625" , 0x1180080947148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3626" , 0x1180080947150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3627" , 0x1180080947158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3628" , 0x1180080947160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3629" , 0x1180080947168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3630" , 0x1180080947170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3631" , 0x1180080947178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3632" , 0x1180080947180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3633" , 0x1180080947188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3634" , 0x1180080947190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3635" , 0x1180080947198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3636" , 0x11800809471a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3637" , 0x11800809471a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3638" , 0x11800809471b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3639" , 0x11800809471b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3640" , 0x11800809471c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3641" , 0x11800809471c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3642" , 0x11800809471d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3643" , 0x11800809471d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3644" , 0x11800809471e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3645" , 0x11800809471e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3646" , 0x11800809471f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3647" , 0x11800809471f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3648" , 0x1180080947200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3649" , 0x1180080947208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3650" , 0x1180080947210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3651" , 0x1180080947218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3652" , 0x1180080947220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3653" , 0x1180080947228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3654" , 0x1180080947230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3655" , 0x1180080947238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3656" , 0x1180080947240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3657" , 0x1180080947248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3658" , 0x1180080947250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3659" , 0x1180080947258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3660" , 0x1180080947260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3661" , 0x1180080947268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3662" , 0x1180080947270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3663" , 0x1180080947278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3664" , 0x1180080947280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3665" , 0x1180080947288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3666" , 0x1180080947290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3667" , 0x1180080947298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3668" , 0x11800809472a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3669" , 0x11800809472a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3670" , 0x11800809472b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3671" , 0x11800809472b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3672" , 0x11800809472c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3673" , 0x11800809472c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3674" , 0x11800809472d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3675" , 0x11800809472d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3676" , 0x11800809472e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3677" , 0x11800809472e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3678" , 0x11800809472f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3679" , 0x11800809472f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3680" , 0x1180080947300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3681" , 0x1180080947308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3682" , 0x1180080947310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3683" , 0x1180080947318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3684" , 0x1180080947320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3685" , 0x1180080947328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3686" , 0x1180080947330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3687" , 0x1180080947338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3688" , 0x1180080947340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3689" , 0x1180080947348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3690" , 0x1180080947350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3691" , 0x1180080947358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3692" , 0x1180080947360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3693" , 0x1180080947368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3694" , 0x1180080947370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3695" , 0x1180080947378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3696" , 0x1180080947380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3697" , 0x1180080947388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3698" , 0x1180080947390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3699" , 0x1180080947398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3700" , 0x11800809473a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3701" , 0x11800809473a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3702" , 0x11800809473b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3703" , 0x11800809473b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3704" , 0x11800809473c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3705" , 0x11800809473c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3706" , 0x11800809473d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3707" , 0x11800809473d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3708" , 0x11800809473e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3709" , 0x11800809473e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3710" , 0x11800809473f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3711" , 0x11800809473f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3712" , 0x1180080947400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3713" , 0x1180080947408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3714" , 0x1180080947410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3715" , 0x1180080947418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3716" , 0x1180080947420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3717" , 0x1180080947428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3718" , 0x1180080947430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3719" , 0x1180080947438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3720" , 0x1180080947440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3721" , 0x1180080947448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3722" , 0x1180080947450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3723" , 0x1180080947458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3724" , 0x1180080947460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3725" , 0x1180080947468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3726" , 0x1180080947470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3727" , 0x1180080947478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3728" , 0x1180080947480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3729" , 0x1180080947488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3730" , 0x1180080947490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3731" , 0x1180080947498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3732" , 0x11800809474a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3733" , 0x11800809474a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3734" , 0x11800809474b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3735" , 0x11800809474b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3736" , 0x11800809474c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3737" , 0x11800809474c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3738" , 0x11800809474d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3739" , 0x11800809474d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3740" , 0x11800809474e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3741" , 0x11800809474e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3742" , 0x11800809474f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3743" , 0x11800809474f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3744" , 0x1180080947500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3745" , 0x1180080947508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3746" , 0x1180080947510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3747" , 0x1180080947518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3748" , 0x1180080947520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3749" , 0x1180080947528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3750" , 0x1180080947530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3751" , 0x1180080947538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3752" , 0x1180080947540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3753" , 0x1180080947548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3754" , 0x1180080947550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3755" , 0x1180080947558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3756" , 0x1180080947560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3757" , 0x1180080947568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3758" , 0x1180080947570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3759" , 0x1180080947578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3760" , 0x1180080947580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3761" , 0x1180080947588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3762" , 0x1180080947590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3763" , 0x1180080947598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3764" , 0x11800809475a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3765" , 0x11800809475a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3766" , 0x11800809475b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3767" , 0x11800809475b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3768" , 0x11800809475c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3769" , 0x11800809475c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3770" , 0x11800809475d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3771" , 0x11800809475d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3772" , 0x11800809475e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3773" , 0x11800809475e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3774" , 0x11800809475f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3775" , 0x11800809475f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3776" , 0x1180080947600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3777" , 0x1180080947608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3778" , 0x1180080947610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3779" , 0x1180080947618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3780" , 0x1180080947620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3781" , 0x1180080947628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3782" , 0x1180080947630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3783" , 0x1180080947638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3784" , 0x1180080947640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3785" , 0x1180080947648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3786" , 0x1180080947650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3787" , 0x1180080947658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3788" , 0x1180080947660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3789" , 0x1180080947668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3790" , 0x1180080947670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3791" , 0x1180080947678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3792" , 0x1180080947680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3793" , 0x1180080947688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3794" , 0x1180080947690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3795" , 0x1180080947698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3796" , 0x11800809476a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3797" , 0x11800809476a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3798" , 0x11800809476b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3799" , 0x11800809476b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3800" , 0x11800809476c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3801" , 0x11800809476c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3802" , 0x11800809476d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3803" , 0x11800809476d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3804" , 0x11800809476e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3805" , 0x11800809476e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3806" , 0x11800809476f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3807" , 0x11800809476f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3808" , 0x1180080947700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3809" , 0x1180080947708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3810" , 0x1180080947710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3811" , 0x1180080947718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3812" , 0x1180080947720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3813" , 0x1180080947728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3814" , 0x1180080947730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3815" , 0x1180080947738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3816" , 0x1180080947740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3817" , 0x1180080947748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3818" , 0x1180080947750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3819" , 0x1180080947758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3820" , 0x1180080947760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3821" , 0x1180080947768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3822" , 0x1180080947770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3823" , 0x1180080947778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3824" , 0x1180080947780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3825" , 0x1180080947788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3826" , 0x1180080947790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3827" , 0x1180080947798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3828" , 0x11800809477a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3829" , 0x11800809477a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3830" , 0x11800809477b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3831" , 0x11800809477b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3832" , 0x11800809477c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3833" , 0x11800809477c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3834" , 0x11800809477d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3835" , 0x11800809477d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3836" , 0x11800809477e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3837" , 0x11800809477e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3838" , 0x11800809477f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3839" , 0x11800809477f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3840" , 0x1180080947800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3841" , 0x1180080947808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3842" , 0x1180080947810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3843" , 0x1180080947818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3844" , 0x1180080947820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3845" , 0x1180080947828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3846" , 0x1180080947830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3847" , 0x1180080947838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3848" , 0x1180080947840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3849" , 0x1180080947848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3850" , 0x1180080947850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3851" , 0x1180080947858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3852" , 0x1180080947860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3853" , 0x1180080947868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3854" , 0x1180080947870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3855" , 0x1180080947878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3856" , 0x1180080947880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3857" , 0x1180080947888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3858" , 0x1180080947890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3859" , 0x1180080947898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3860" , 0x11800809478a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3861" , 0x11800809478a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3862" , 0x11800809478b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3863" , 0x11800809478b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3864" , 0x11800809478c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3865" , 0x11800809478c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3866" , 0x11800809478d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3867" , 0x11800809478d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3868" , 0x11800809478e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3869" , 0x11800809478e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3870" , 0x11800809478f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3871" , 0x11800809478f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3872" , 0x1180080947900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3873" , 0x1180080947908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3874" , 0x1180080947910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3875" , 0x1180080947918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3876" , 0x1180080947920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3877" , 0x1180080947928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3878" , 0x1180080947930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3879" , 0x1180080947938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3880" , 0x1180080947940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3881" , 0x1180080947948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3882" , 0x1180080947950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3883" , 0x1180080947958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3884" , 0x1180080947960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3885" , 0x1180080947968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3886" , 0x1180080947970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3887" , 0x1180080947978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3888" , 0x1180080947980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3889" , 0x1180080947988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3890" , 0x1180080947990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3891" , 0x1180080947998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3892" , 0x11800809479a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3893" , 0x11800809479a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3894" , 0x11800809479b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3895" , 0x11800809479b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3896" , 0x11800809479c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3897" , 0x11800809479c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3898" , 0x11800809479d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3899" , 0x11800809479d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3900" , 0x11800809479e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3901" , 0x11800809479e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3902" , 0x11800809479f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3903" , 0x11800809479f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3904" , 0x1180080947a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3905" , 0x1180080947a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3906" , 0x1180080947a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3907" , 0x1180080947a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3908" , 0x1180080947a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3909" , 0x1180080947a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3910" , 0x1180080947a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3911" , 0x1180080947a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3912" , 0x1180080947a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3913" , 0x1180080947a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3914" , 0x1180080947a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3915" , 0x1180080947a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3916" , 0x1180080947a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3917" , 0x1180080947a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3918" , 0x1180080947a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3919" , 0x1180080947a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3920" , 0x1180080947a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3921" , 0x1180080947a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3922" , 0x1180080947a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3923" , 0x1180080947a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3924" , 0x1180080947aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3925" , 0x1180080947aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3926" , 0x1180080947ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3927" , 0x1180080947ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3928" , 0x1180080947ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3929" , 0x1180080947ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3930" , 0x1180080947ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3931" , 0x1180080947ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3932" , 0x1180080947ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3933" , 0x1180080947ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3934" , 0x1180080947af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3935" , 0x1180080947af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3936" , 0x1180080947b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3937" , 0x1180080947b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3938" , 0x1180080947b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3939" , 0x1180080947b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3940" , 0x1180080947b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3941" , 0x1180080947b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3942" , 0x1180080947b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3943" , 0x1180080947b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3944" , 0x1180080947b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3945" , 0x1180080947b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3946" , 0x1180080947b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3947" , 0x1180080947b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3948" , 0x1180080947b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3949" , 0x1180080947b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3950" , 0x1180080947b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3951" , 0x1180080947b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3952" , 0x1180080947b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3953" , 0x1180080947b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3954" , 0x1180080947b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3955" , 0x1180080947b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3956" , 0x1180080947ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3957" , 0x1180080947ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3958" , 0x1180080947bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3959" , 0x1180080947bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3960" , 0x1180080947bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3961" , 0x1180080947bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3962" , 0x1180080947bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3963" , 0x1180080947bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3964" , 0x1180080947be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3965" , 0x1180080947be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3966" , 0x1180080947bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3967" , 0x1180080947bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3968" , 0x1180080947c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3969" , 0x1180080947c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3970" , 0x1180080947c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3971" , 0x1180080947c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3972" , 0x1180080947c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3973" , 0x1180080947c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3974" , 0x1180080947c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3975" , 0x1180080947c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3976" , 0x1180080947c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3977" , 0x1180080947c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3978" , 0x1180080947c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3979" , 0x1180080947c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3980" , 0x1180080947c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3981" , 0x1180080947c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3982" , 0x1180080947c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3983" , 0x1180080947c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3984" , 0x1180080947c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3985" , 0x1180080947c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3986" , 0x1180080947c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3987" , 0x1180080947c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3988" , 0x1180080947ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3989" , 0x1180080947ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3990" , 0x1180080947cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3991" , 0x1180080947cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3992" , 0x1180080947cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3993" , 0x1180080947cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3994" , 0x1180080947cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3995" , 0x1180080947cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3996" , 0x1180080947ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3997" , 0x1180080947ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3998" , 0x1180080947cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP3999" , 0x1180080947cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4000" , 0x1180080947d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4001" , 0x1180080947d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4002" , 0x1180080947d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4003" , 0x1180080947d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4004" , 0x1180080947d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4005" , 0x1180080947d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4006" , 0x1180080947d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4007" , 0x1180080947d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4008" , 0x1180080947d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4009" , 0x1180080947d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4010" , 0x1180080947d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4011" , 0x1180080947d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4012" , 0x1180080947d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4013" , 0x1180080947d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4014" , 0x1180080947d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4015" , 0x1180080947d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4016" , 0x1180080947d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4017" , 0x1180080947d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4018" , 0x1180080947d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4019" , 0x1180080947d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4020" , 0x1180080947da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4021" , 0x1180080947da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4022" , 0x1180080947db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4023" , 0x1180080947db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4024" , 0x1180080947dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4025" , 0x1180080947dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4026" , 0x1180080947dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4027" , 0x1180080947dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4028" , 0x1180080947de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4029" , 0x1180080947de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4030" , 0x1180080947df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4031" , 0x1180080947df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4032" , 0x1180080947e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4033" , 0x1180080947e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4034" , 0x1180080947e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4035" , 0x1180080947e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4036" , 0x1180080947e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4037" , 0x1180080947e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4038" , 0x1180080947e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4039" , 0x1180080947e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4040" , 0x1180080947e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4041" , 0x1180080947e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4042" , 0x1180080947e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4043" , 0x1180080947e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4044" , 0x1180080947e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4045" , 0x1180080947e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4046" , 0x1180080947e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4047" , 0x1180080947e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4048" , 0x1180080947e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4049" , 0x1180080947e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4050" , 0x1180080947e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4051" , 0x1180080947e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4052" , 0x1180080947ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4053" , 0x1180080947ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4054" , 0x1180080947eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4055" , 0x1180080947eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4056" , 0x1180080947ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4057" , 0x1180080947ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4058" , 0x1180080947ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4059" , 0x1180080947ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4060" , 0x1180080947ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4061" , 0x1180080947ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4062" , 0x1180080947ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4063" , 0x1180080947ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4064" , 0x1180080947f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4065" , 0x1180080947f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4066" , 0x1180080947f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4067" , 0x1180080947f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4068" , 0x1180080947f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4069" , 0x1180080947f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4070" , 0x1180080947f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4071" , 0x1180080947f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4072" , 0x1180080947f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4073" , 0x1180080947f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4074" , 0x1180080947f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4075" , 0x1180080947f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4076" , 0x1180080947f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4077" , 0x1180080947f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4078" , 0x1180080947f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4079" , 0x1180080947f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4080" , 0x1180080947f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4081" , 0x1180080947f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4082" , 0x1180080947f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4083" , 0x1180080947f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4084" , 0x1180080947fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4085" , 0x1180080947fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4086" , 0x1180080947fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4087" , 0x1180080947fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4088" , 0x1180080947fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4089" , 0x1180080947fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4090" , 0x1180080947fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4091" , 0x1180080947fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4092" , 0x1180080947fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4093" , 0x1180080947fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4094" , 0x1180080947ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4095" , 0x1180080947ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4096" , 0x1180080948000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4097" , 0x1180080948008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4098" , 0x1180080948010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4099" , 0x1180080948018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4100" , 0x1180080948020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4101" , 0x1180080948028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4102" , 0x1180080948030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4103" , 0x1180080948038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4104" , 0x1180080948040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4105" , 0x1180080948048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4106" , 0x1180080948050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4107" , 0x1180080948058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4108" , 0x1180080948060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4109" , 0x1180080948068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4110" , 0x1180080948070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4111" , 0x1180080948078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4112" , 0x1180080948080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4113" , 0x1180080948088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4114" , 0x1180080948090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4115" , 0x1180080948098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4116" , 0x11800809480a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4117" , 0x11800809480a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4118" , 0x11800809480b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4119" , 0x11800809480b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4120" , 0x11800809480c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4121" , 0x11800809480c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4122" , 0x11800809480d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4123" , 0x11800809480d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4124" , 0x11800809480e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4125" , 0x11800809480e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4126" , 0x11800809480f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4127" , 0x11800809480f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4128" , 0x1180080948100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4129" , 0x1180080948108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4130" , 0x1180080948110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4131" , 0x1180080948118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4132" , 0x1180080948120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4133" , 0x1180080948128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4134" , 0x1180080948130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4135" , 0x1180080948138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4136" , 0x1180080948140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4137" , 0x1180080948148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4138" , 0x1180080948150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4139" , 0x1180080948158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4140" , 0x1180080948160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4141" , 0x1180080948168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4142" , 0x1180080948170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4143" , 0x1180080948178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4144" , 0x1180080948180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4145" , 0x1180080948188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4146" , 0x1180080948190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4147" , 0x1180080948198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4148" , 0x11800809481a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4149" , 0x11800809481a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4150" , 0x11800809481b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4151" , 0x11800809481b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4152" , 0x11800809481c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4153" , 0x11800809481c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4154" , 0x11800809481d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4155" , 0x11800809481d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4156" , 0x11800809481e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4157" , 0x11800809481e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4158" , 0x11800809481f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4159" , 0x11800809481f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4160" , 0x1180080948200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4161" , 0x1180080948208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4162" , 0x1180080948210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4163" , 0x1180080948218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4164" , 0x1180080948220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4165" , 0x1180080948228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4166" , 0x1180080948230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4167" , 0x1180080948238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4168" , 0x1180080948240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4169" , 0x1180080948248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4170" , 0x1180080948250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4171" , 0x1180080948258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4172" , 0x1180080948260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4173" , 0x1180080948268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4174" , 0x1180080948270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4175" , 0x1180080948278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4176" , 0x1180080948280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4177" , 0x1180080948288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4178" , 0x1180080948290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4179" , 0x1180080948298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4180" , 0x11800809482a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4181" , 0x11800809482a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4182" , 0x11800809482b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4183" , 0x11800809482b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4184" , 0x11800809482c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4185" , 0x11800809482c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4186" , 0x11800809482d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4187" , 0x11800809482d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4188" , 0x11800809482e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4189" , 0x11800809482e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4190" , 0x11800809482f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4191" , 0x11800809482f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4192" , 0x1180080948300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4193" , 0x1180080948308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4194" , 0x1180080948310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4195" , 0x1180080948318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4196" , 0x1180080948320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4197" , 0x1180080948328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4198" , 0x1180080948330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4199" , 0x1180080948338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4200" , 0x1180080948340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4201" , 0x1180080948348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4202" , 0x1180080948350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4203" , 0x1180080948358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4204" , 0x1180080948360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4205" , 0x1180080948368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4206" , 0x1180080948370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4207" , 0x1180080948378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4208" , 0x1180080948380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4209" , 0x1180080948388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4210" , 0x1180080948390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4211" , 0x1180080948398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4212" , 0x11800809483a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4213" , 0x11800809483a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4214" , 0x11800809483b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4215" , 0x11800809483b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4216" , 0x11800809483c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4217" , 0x11800809483c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4218" , 0x11800809483d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4219" , 0x11800809483d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4220" , 0x11800809483e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4221" , 0x11800809483e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4222" , 0x11800809483f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4223" , 0x11800809483f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4224" , 0x1180080948400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4225" , 0x1180080948408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4226" , 0x1180080948410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4227" , 0x1180080948418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4228" , 0x1180080948420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4229" , 0x1180080948428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4230" , 0x1180080948430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4231" , 0x1180080948438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4232" , 0x1180080948440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4233" , 0x1180080948448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4234" , 0x1180080948450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4235" , 0x1180080948458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4236" , 0x1180080948460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4237" , 0x1180080948468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4238" , 0x1180080948470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4239" , 0x1180080948478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4240" , 0x1180080948480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4241" , 0x1180080948488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4242" , 0x1180080948490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4243" , 0x1180080948498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4244" , 0x11800809484a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4245" , 0x11800809484a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4246" , 0x11800809484b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4247" , 0x11800809484b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4248" , 0x11800809484c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4249" , 0x11800809484c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4250" , 0x11800809484d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4251" , 0x11800809484d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4252" , 0x11800809484e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4253" , 0x11800809484e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4254" , 0x11800809484f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4255" , 0x11800809484f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4256" , 0x1180080948500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4257" , 0x1180080948508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4258" , 0x1180080948510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4259" , 0x1180080948518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4260" , 0x1180080948520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4261" , 0x1180080948528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4262" , 0x1180080948530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4263" , 0x1180080948538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4264" , 0x1180080948540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4265" , 0x1180080948548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4266" , 0x1180080948550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4267" , 0x1180080948558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4268" , 0x1180080948560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4269" , 0x1180080948568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4270" , 0x1180080948570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4271" , 0x1180080948578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4272" , 0x1180080948580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4273" , 0x1180080948588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4274" , 0x1180080948590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4275" , 0x1180080948598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4276" , 0x11800809485a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4277" , 0x11800809485a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4278" , 0x11800809485b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4279" , 0x11800809485b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4280" , 0x11800809485c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4281" , 0x11800809485c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4282" , 0x11800809485d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4283" , 0x11800809485d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4284" , 0x11800809485e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4285" , 0x11800809485e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4286" , 0x11800809485f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4287" , 0x11800809485f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4288" , 0x1180080948600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4289" , 0x1180080948608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4290" , 0x1180080948610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4291" , 0x1180080948618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4292" , 0x1180080948620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4293" , 0x1180080948628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4294" , 0x1180080948630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4295" , 0x1180080948638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4296" , 0x1180080948640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4297" , 0x1180080948648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4298" , 0x1180080948650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4299" , 0x1180080948658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4300" , 0x1180080948660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4301" , 0x1180080948668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4302" , 0x1180080948670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4303" , 0x1180080948678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4304" , 0x1180080948680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4305" , 0x1180080948688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4306" , 0x1180080948690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4307" , 0x1180080948698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4308" , 0x11800809486a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4309" , 0x11800809486a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4310" , 0x11800809486b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4311" , 0x11800809486b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4312" , 0x11800809486c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4313" , 0x11800809486c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4314" , 0x11800809486d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4315" , 0x11800809486d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4316" , 0x11800809486e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4317" , 0x11800809486e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4318" , 0x11800809486f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4319" , 0x11800809486f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4320" , 0x1180080948700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4321" , 0x1180080948708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4322" , 0x1180080948710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4323" , 0x1180080948718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4324" , 0x1180080948720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4325" , 0x1180080948728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4326" , 0x1180080948730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4327" , 0x1180080948738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4328" , 0x1180080948740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4329" , 0x1180080948748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4330" , 0x1180080948750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4331" , 0x1180080948758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4332" , 0x1180080948760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4333" , 0x1180080948768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4334" , 0x1180080948770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4335" , 0x1180080948778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4336" , 0x1180080948780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4337" , 0x1180080948788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4338" , 0x1180080948790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4339" , 0x1180080948798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4340" , 0x11800809487a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4341" , 0x11800809487a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4342" , 0x11800809487b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4343" , 0x11800809487b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4344" , 0x11800809487c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4345" , 0x11800809487c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4346" , 0x11800809487d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4347" , 0x11800809487d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4348" , 0x11800809487e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4349" , 0x11800809487e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4350" , 0x11800809487f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4351" , 0x11800809487f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4352" , 0x1180080948800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4353" , 0x1180080948808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4354" , 0x1180080948810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4355" , 0x1180080948818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4356" , 0x1180080948820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4357" , 0x1180080948828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4358" , 0x1180080948830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4359" , 0x1180080948838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4360" , 0x1180080948840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4361" , 0x1180080948848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4362" , 0x1180080948850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4363" , 0x1180080948858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4364" , 0x1180080948860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4365" , 0x1180080948868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4366" , 0x1180080948870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4367" , 0x1180080948878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4368" , 0x1180080948880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4369" , 0x1180080948888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4370" , 0x1180080948890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4371" , 0x1180080948898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4372" , 0x11800809488a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4373" , 0x11800809488a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4374" , 0x11800809488b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4375" , 0x11800809488b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4376" , 0x11800809488c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4377" , 0x11800809488c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4378" , 0x11800809488d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4379" , 0x11800809488d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4380" , 0x11800809488e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4381" , 0x11800809488e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4382" , 0x11800809488f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4383" , 0x11800809488f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4384" , 0x1180080948900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4385" , 0x1180080948908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4386" , 0x1180080948910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4387" , 0x1180080948918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4388" , 0x1180080948920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4389" , 0x1180080948928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4390" , 0x1180080948930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4391" , 0x1180080948938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4392" , 0x1180080948940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4393" , 0x1180080948948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4394" , 0x1180080948950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4395" , 0x1180080948958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4396" , 0x1180080948960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4397" , 0x1180080948968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4398" , 0x1180080948970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4399" , 0x1180080948978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4400" , 0x1180080948980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4401" , 0x1180080948988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4402" , 0x1180080948990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4403" , 0x1180080948998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4404" , 0x11800809489a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4405" , 0x11800809489a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4406" , 0x11800809489b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4407" , 0x11800809489b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4408" , 0x11800809489c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4409" , 0x11800809489c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4410" , 0x11800809489d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4411" , 0x11800809489d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4412" , 0x11800809489e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4413" , 0x11800809489e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4414" , 0x11800809489f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4415" , 0x11800809489f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4416" , 0x1180080948a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4417" , 0x1180080948a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4418" , 0x1180080948a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4419" , 0x1180080948a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4420" , 0x1180080948a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4421" , 0x1180080948a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4422" , 0x1180080948a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4423" , 0x1180080948a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4424" , 0x1180080948a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4425" , 0x1180080948a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4426" , 0x1180080948a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4427" , 0x1180080948a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4428" , 0x1180080948a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4429" , 0x1180080948a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4430" , 0x1180080948a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4431" , 0x1180080948a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4432" , 0x1180080948a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4433" , 0x1180080948a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4434" , 0x1180080948a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4435" , 0x1180080948a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4436" , 0x1180080948aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4437" , 0x1180080948aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4438" , 0x1180080948ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4439" , 0x1180080948ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4440" , 0x1180080948ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4441" , 0x1180080948ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4442" , 0x1180080948ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4443" , 0x1180080948ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4444" , 0x1180080948ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4445" , 0x1180080948ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4446" , 0x1180080948af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4447" , 0x1180080948af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4448" , 0x1180080948b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4449" , 0x1180080948b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4450" , 0x1180080948b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4451" , 0x1180080948b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4452" , 0x1180080948b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4453" , 0x1180080948b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4454" , 0x1180080948b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4455" , 0x1180080948b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4456" , 0x1180080948b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4457" , 0x1180080948b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4458" , 0x1180080948b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4459" , 0x1180080948b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4460" , 0x1180080948b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4461" , 0x1180080948b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4462" , 0x1180080948b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4463" , 0x1180080948b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4464" , 0x1180080948b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4465" , 0x1180080948b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4466" , 0x1180080948b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4467" , 0x1180080948b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4468" , 0x1180080948ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4469" , 0x1180080948ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4470" , 0x1180080948bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4471" , 0x1180080948bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4472" , 0x1180080948bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4473" , 0x1180080948bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4474" , 0x1180080948bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4475" , 0x1180080948bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4476" , 0x1180080948be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4477" , 0x1180080948be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4478" , 0x1180080948bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4479" , 0x1180080948bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4480" , 0x1180080948c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4481" , 0x1180080948c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4482" , 0x1180080948c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4483" , 0x1180080948c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4484" , 0x1180080948c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4485" , 0x1180080948c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4486" , 0x1180080948c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4487" , 0x1180080948c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4488" , 0x1180080948c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4489" , 0x1180080948c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4490" , 0x1180080948c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4491" , 0x1180080948c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4492" , 0x1180080948c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4493" , 0x1180080948c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4494" , 0x1180080948c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4495" , 0x1180080948c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4496" , 0x1180080948c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4497" , 0x1180080948c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4498" , 0x1180080948c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4499" , 0x1180080948c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4500" , 0x1180080948ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4501" , 0x1180080948ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4502" , 0x1180080948cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4503" , 0x1180080948cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4504" , 0x1180080948cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4505" , 0x1180080948cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4506" , 0x1180080948cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4507" , 0x1180080948cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4508" , 0x1180080948ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4509" , 0x1180080948ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4510" , 0x1180080948cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4511" , 0x1180080948cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4512" , 0x1180080948d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4513" , 0x1180080948d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4514" , 0x1180080948d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4515" , 0x1180080948d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4516" , 0x1180080948d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4517" , 0x1180080948d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4518" , 0x1180080948d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4519" , 0x1180080948d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4520" , 0x1180080948d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4521" , 0x1180080948d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4522" , 0x1180080948d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4523" , 0x1180080948d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4524" , 0x1180080948d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4525" , 0x1180080948d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4526" , 0x1180080948d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4527" , 0x1180080948d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4528" , 0x1180080948d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4529" , 0x1180080948d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4530" , 0x1180080948d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4531" , 0x1180080948d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4532" , 0x1180080948da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4533" , 0x1180080948da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4534" , 0x1180080948db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4535" , 0x1180080948db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4536" , 0x1180080948dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4537" , 0x1180080948dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4538" , 0x1180080948dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4539" , 0x1180080948dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4540" , 0x1180080948de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4541" , 0x1180080948de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4542" , 0x1180080948df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4543" , 0x1180080948df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4544" , 0x1180080948e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4545" , 0x1180080948e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4546" , 0x1180080948e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4547" , 0x1180080948e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4548" , 0x1180080948e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4549" , 0x1180080948e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4550" , 0x1180080948e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4551" , 0x1180080948e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4552" , 0x1180080948e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4553" , 0x1180080948e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4554" , 0x1180080948e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4555" , 0x1180080948e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4556" , 0x1180080948e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4557" , 0x1180080948e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4558" , 0x1180080948e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4559" , 0x1180080948e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4560" , 0x1180080948e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4561" , 0x1180080948e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4562" , 0x1180080948e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4563" , 0x1180080948e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4564" , 0x1180080948ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4565" , 0x1180080948ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4566" , 0x1180080948eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4567" , 0x1180080948eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4568" , 0x1180080948ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4569" , 0x1180080948ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4570" , 0x1180080948ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4571" , 0x1180080948ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4572" , 0x1180080948ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4573" , 0x1180080948ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4574" , 0x1180080948ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4575" , 0x1180080948ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4576" , 0x1180080948f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4577" , 0x1180080948f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4578" , 0x1180080948f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4579" , 0x1180080948f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4580" , 0x1180080948f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4581" , 0x1180080948f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4582" , 0x1180080948f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4583" , 0x1180080948f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4584" , 0x1180080948f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4585" , 0x1180080948f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4586" , 0x1180080948f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4587" , 0x1180080948f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4588" , 0x1180080948f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4589" , 0x1180080948f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4590" , 0x1180080948f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4591" , 0x1180080948f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4592" , 0x1180080948f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4593" , 0x1180080948f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4594" , 0x1180080948f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4595" , 0x1180080948f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4596" , 0x1180080948fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4597" , 0x1180080948fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4598" , 0x1180080948fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4599" , 0x1180080948fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4600" , 0x1180080948fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4601" , 0x1180080948fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4602" , 0x1180080948fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4603" , 0x1180080948fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4604" , 0x1180080948fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4605" , 0x1180080948fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4606" , 0x1180080948ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4607" , 0x1180080948ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4608" , 0x1180080949000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4609" , 0x1180080949008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4610" , 0x1180080949010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4611" , 0x1180080949018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4612" , 0x1180080949020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4613" , 0x1180080949028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4614" , 0x1180080949030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4615" , 0x1180080949038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4616" , 0x1180080949040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4617" , 0x1180080949048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4618" , 0x1180080949050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4619" , 0x1180080949058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4620" , 0x1180080949060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4621" , 0x1180080949068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4622" , 0x1180080949070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4623" , 0x1180080949078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4624" , 0x1180080949080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4625" , 0x1180080949088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4626" , 0x1180080949090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4627" , 0x1180080949098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4628" , 0x11800809490a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4629" , 0x11800809490a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4630" , 0x11800809490b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4631" , 0x11800809490b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4632" , 0x11800809490c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4633" , 0x11800809490c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4634" , 0x11800809490d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4635" , 0x11800809490d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4636" , 0x11800809490e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4637" , 0x11800809490e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4638" , 0x11800809490f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4639" , 0x11800809490f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4640" , 0x1180080949100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4641" , 0x1180080949108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4642" , 0x1180080949110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4643" , 0x1180080949118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4644" , 0x1180080949120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4645" , 0x1180080949128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4646" , 0x1180080949130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4647" , 0x1180080949138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4648" , 0x1180080949140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4649" , 0x1180080949148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4650" , 0x1180080949150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4651" , 0x1180080949158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4652" , 0x1180080949160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4653" , 0x1180080949168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4654" , 0x1180080949170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4655" , 0x1180080949178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4656" , 0x1180080949180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4657" , 0x1180080949188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4658" , 0x1180080949190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4659" , 0x1180080949198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4660" , 0x11800809491a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4661" , 0x11800809491a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4662" , 0x11800809491b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4663" , 0x11800809491b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4664" , 0x11800809491c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4665" , 0x11800809491c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4666" , 0x11800809491d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4667" , 0x11800809491d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4668" , 0x11800809491e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4669" , 0x11800809491e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4670" , 0x11800809491f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4671" , 0x11800809491f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4672" , 0x1180080949200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4673" , 0x1180080949208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4674" , 0x1180080949210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4675" , 0x1180080949218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4676" , 0x1180080949220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4677" , 0x1180080949228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4678" , 0x1180080949230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4679" , 0x1180080949238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4680" , 0x1180080949240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4681" , 0x1180080949248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4682" , 0x1180080949250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4683" , 0x1180080949258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4684" , 0x1180080949260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4685" , 0x1180080949268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4686" , 0x1180080949270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4687" , 0x1180080949278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4688" , 0x1180080949280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4689" , 0x1180080949288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4690" , 0x1180080949290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4691" , 0x1180080949298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4692" , 0x11800809492a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4693" , 0x11800809492a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4694" , 0x11800809492b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4695" , 0x11800809492b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4696" , 0x11800809492c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4697" , 0x11800809492c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4698" , 0x11800809492d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4699" , 0x11800809492d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4700" , 0x11800809492e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4701" , 0x11800809492e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4702" , 0x11800809492f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4703" , 0x11800809492f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4704" , 0x1180080949300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4705" , 0x1180080949308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4706" , 0x1180080949310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4707" , 0x1180080949318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4708" , 0x1180080949320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4709" , 0x1180080949328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4710" , 0x1180080949330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4711" , 0x1180080949338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4712" , 0x1180080949340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4713" , 0x1180080949348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4714" , 0x1180080949350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4715" , 0x1180080949358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4716" , 0x1180080949360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4717" , 0x1180080949368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4718" , 0x1180080949370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4719" , 0x1180080949378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4720" , 0x1180080949380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4721" , 0x1180080949388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4722" , 0x1180080949390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4723" , 0x1180080949398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4724" , 0x11800809493a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4725" , 0x11800809493a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4726" , 0x11800809493b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4727" , 0x11800809493b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4728" , 0x11800809493c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4729" , 0x11800809493c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4730" , 0x11800809493d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4731" , 0x11800809493d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4732" , 0x11800809493e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4733" , 0x11800809493e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4734" , 0x11800809493f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4735" , 0x11800809493f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4736" , 0x1180080949400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4737" , 0x1180080949408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4738" , 0x1180080949410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4739" , 0x1180080949418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4740" , 0x1180080949420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4741" , 0x1180080949428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4742" , 0x1180080949430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4743" , 0x1180080949438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4744" , 0x1180080949440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4745" , 0x1180080949448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4746" , 0x1180080949450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4747" , 0x1180080949458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4748" , 0x1180080949460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4749" , 0x1180080949468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4750" , 0x1180080949470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4751" , 0x1180080949478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4752" , 0x1180080949480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4753" , 0x1180080949488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4754" , 0x1180080949490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4755" , 0x1180080949498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4756" , 0x11800809494a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4757" , 0x11800809494a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4758" , 0x11800809494b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4759" , 0x11800809494b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4760" , 0x11800809494c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4761" , 0x11800809494c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4762" , 0x11800809494d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4763" , 0x11800809494d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4764" , 0x11800809494e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4765" , 0x11800809494e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4766" , 0x11800809494f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4767" , 0x11800809494f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4768" , 0x1180080949500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4769" , 0x1180080949508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4770" , 0x1180080949510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4771" , 0x1180080949518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4772" , 0x1180080949520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4773" , 0x1180080949528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4774" , 0x1180080949530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4775" , 0x1180080949538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4776" , 0x1180080949540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4777" , 0x1180080949548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4778" , 0x1180080949550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4779" , 0x1180080949558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4780" , 0x1180080949560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4781" , 0x1180080949568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4782" , 0x1180080949570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4783" , 0x1180080949578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4784" , 0x1180080949580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4785" , 0x1180080949588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4786" , 0x1180080949590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4787" , 0x1180080949598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4788" , 0x11800809495a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4789" , 0x11800809495a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4790" , 0x11800809495b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4791" , 0x11800809495b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4792" , 0x11800809495c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4793" , 0x11800809495c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4794" , 0x11800809495d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4795" , 0x11800809495d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4796" , 0x11800809495e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4797" , 0x11800809495e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4798" , 0x11800809495f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4799" , 0x11800809495f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4800" , 0x1180080949600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4801" , 0x1180080949608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4802" , 0x1180080949610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4803" , 0x1180080949618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4804" , 0x1180080949620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4805" , 0x1180080949628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4806" , 0x1180080949630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4807" , 0x1180080949638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4808" , 0x1180080949640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4809" , 0x1180080949648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4810" , 0x1180080949650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4811" , 0x1180080949658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4812" , 0x1180080949660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4813" , 0x1180080949668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4814" , 0x1180080949670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4815" , 0x1180080949678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4816" , 0x1180080949680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4817" , 0x1180080949688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4818" , 0x1180080949690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4819" , 0x1180080949698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4820" , 0x11800809496a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4821" , 0x11800809496a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4822" , 0x11800809496b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4823" , 0x11800809496b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4824" , 0x11800809496c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4825" , 0x11800809496c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4826" , 0x11800809496d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4827" , 0x11800809496d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4828" , 0x11800809496e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4829" , 0x11800809496e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4830" , 0x11800809496f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4831" , 0x11800809496f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4832" , 0x1180080949700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4833" , 0x1180080949708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4834" , 0x1180080949710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4835" , 0x1180080949718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4836" , 0x1180080949720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4837" , 0x1180080949728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4838" , 0x1180080949730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4839" , 0x1180080949738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4840" , 0x1180080949740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4841" , 0x1180080949748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4842" , 0x1180080949750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4843" , 0x1180080949758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4844" , 0x1180080949760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4845" , 0x1180080949768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4846" , 0x1180080949770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4847" , 0x1180080949778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4848" , 0x1180080949780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4849" , 0x1180080949788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4850" , 0x1180080949790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4851" , 0x1180080949798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4852" , 0x11800809497a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4853" , 0x11800809497a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4854" , 0x11800809497b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4855" , 0x11800809497b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4856" , 0x11800809497c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4857" , 0x11800809497c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4858" , 0x11800809497d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4859" , 0x11800809497d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4860" , 0x11800809497e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4861" , 0x11800809497e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4862" , 0x11800809497f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4863" , 0x11800809497f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4864" , 0x1180080949800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4865" , 0x1180080949808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4866" , 0x1180080949810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4867" , 0x1180080949818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4868" , 0x1180080949820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4869" , 0x1180080949828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4870" , 0x1180080949830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4871" , 0x1180080949838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4872" , 0x1180080949840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4873" , 0x1180080949848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4874" , 0x1180080949850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4875" , 0x1180080949858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4876" , 0x1180080949860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4877" , 0x1180080949868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4878" , 0x1180080949870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4879" , 0x1180080949878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4880" , 0x1180080949880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4881" , 0x1180080949888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4882" , 0x1180080949890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4883" , 0x1180080949898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4884" , 0x11800809498a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4885" , 0x11800809498a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4886" , 0x11800809498b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4887" , 0x11800809498b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4888" , 0x11800809498c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4889" , 0x11800809498c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4890" , 0x11800809498d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4891" , 0x11800809498d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4892" , 0x11800809498e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4893" , 0x11800809498e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4894" , 0x11800809498f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4895" , 0x11800809498f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4896" , 0x1180080949900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4897" , 0x1180080949908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4898" , 0x1180080949910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4899" , 0x1180080949918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4900" , 0x1180080949920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4901" , 0x1180080949928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4902" , 0x1180080949930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4903" , 0x1180080949938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4904" , 0x1180080949940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4905" , 0x1180080949948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4906" , 0x1180080949950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4907" , 0x1180080949958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4908" , 0x1180080949960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4909" , 0x1180080949968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4910" , 0x1180080949970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4911" , 0x1180080949978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4912" , 0x1180080949980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4913" , 0x1180080949988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4914" , 0x1180080949990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4915" , 0x1180080949998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4916" , 0x11800809499a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4917" , 0x11800809499a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4918" , 0x11800809499b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4919" , 0x11800809499b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4920" , 0x11800809499c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4921" , 0x11800809499c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4922" , 0x11800809499d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4923" , 0x11800809499d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4924" , 0x11800809499e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4925" , 0x11800809499e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4926" , 0x11800809499f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4927" , 0x11800809499f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4928" , 0x1180080949a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4929" , 0x1180080949a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4930" , 0x1180080949a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4931" , 0x1180080949a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4932" , 0x1180080949a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4933" , 0x1180080949a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4934" , 0x1180080949a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4935" , 0x1180080949a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4936" , 0x1180080949a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4937" , 0x1180080949a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4938" , 0x1180080949a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4939" , 0x1180080949a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4940" , 0x1180080949a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4941" , 0x1180080949a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4942" , 0x1180080949a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4943" , 0x1180080949a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4944" , 0x1180080949a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4945" , 0x1180080949a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4946" , 0x1180080949a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4947" , 0x1180080949a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4948" , 0x1180080949aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4949" , 0x1180080949aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4950" , 0x1180080949ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4951" , 0x1180080949ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4952" , 0x1180080949ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4953" , 0x1180080949ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4954" , 0x1180080949ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4955" , 0x1180080949ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4956" , 0x1180080949ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4957" , 0x1180080949ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4958" , 0x1180080949af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4959" , 0x1180080949af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4960" , 0x1180080949b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4961" , 0x1180080949b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4962" , 0x1180080949b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4963" , 0x1180080949b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4964" , 0x1180080949b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4965" , 0x1180080949b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4966" , 0x1180080949b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4967" , 0x1180080949b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4968" , 0x1180080949b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4969" , 0x1180080949b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4970" , 0x1180080949b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4971" , 0x1180080949b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4972" , 0x1180080949b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4973" , 0x1180080949b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4974" , 0x1180080949b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4975" , 0x1180080949b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4976" , 0x1180080949b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4977" , 0x1180080949b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4978" , 0x1180080949b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4979" , 0x1180080949b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4980" , 0x1180080949ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4981" , 0x1180080949ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4982" , 0x1180080949bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4983" , 0x1180080949bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4984" , 0x1180080949bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4985" , 0x1180080949bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4986" , 0x1180080949bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4987" , 0x1180080949bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4988" , 0x1180080949be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4989" , 0x1180080949be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4990" , 0x1180080949bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4991" , 0x1180080949bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4992" , 0x1180080949c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4993" , 0x1180080949c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4994" , 0x1180080949c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4995" , 0x1180080949c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4996" , 0x1180080949c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4997" , 0x1180080949c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4998" , 0x1180080949c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP4999" , 0x1180080949c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5000" , 0x1180080949c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5001" , 0x1180080949c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5002" , 0x1180080949c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5003" , 0x1180080949c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5004" , 0x1180080949c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5005" , 0x1180080949c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5006" , 0x1180080949c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5007" , 0x1180080949c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5008" , 0x1180080949c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5009" , 0x1180080949c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5010" , 0x1180080949c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5011" , 0x1180080949c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5012" , 0x1180080949ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5013" , 0x1180080949ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5014" , 0x1180080949cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5015" , 0x1180080949cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5016" , 0x1180080949cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5017" , 0x1180080949cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5018" , 0x1180080949cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5019" , 0x1180080949cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5020" , 0x1180080949ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5021" , 0x1180080949ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5022" , 0x1180080949cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5023" , 0x1180080949cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5024" , 0x1180080949d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5025" , 0x1180080949d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5026" , 0x1180080949d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5027" , 0x1180080949d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5028" , 0x1180080949d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5029" , 0x1180080949d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5030" , 0x1180080949d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5031" , 0x1180080949d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5032" , 0x1180080949d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5033" , 0x1180080949d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5034" , 0x1180080949d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5035" , 0x1180080949d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5036" , 0x1180080949d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5037" , 0x1180080949d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5038" , 0x1180080949d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5039" , 0x1180080949d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5040" , 0x1180080949d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5041" , 0x1180080949d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5042" , 0x1180080949d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5043" , 0x1180080949d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5044" , 0x1180080949da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5045" , 0x1180080949da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5046" , 0x1180080949db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5047" , 0x1180080949db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5048" , 0x1180080949dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5049" , 0x1180080949dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5050" , 0x1180080949dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5051" , 0x1180080949dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5052" , 0x1180080949de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5053" , 0x1180080949de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5054" , 0x1180080949df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5055" , 0x1180080949df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5056" , 0x1180080949e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5057" , 0x1180080949e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5058" , 0x1180080949e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5059" , 0x1180080949e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5060" , 0x1180080949e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5061" , 0x1180080949e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5062" , 0x1180080949e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5063" , 0x1180080949e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5064" , 0x1180080949e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5065" , 0x1180080949e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5066" , 0x1180080949e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5067" , 0x1180080949e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5068" , 0x1180080949e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5069" , 0x1180080949e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5070" , 0x1180080949e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5071" , 0x1180080949e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5072" , 0x1180080949e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5073" , 0x1180080949e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5074" , 0x1180080949e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5075" , 0x1180080949e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5076" , 0x1180080949ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5077" , 0x1180080949ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5078" , 0x1180080949eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5079" , 0x1180080949eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5080" , 0x1180080949ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5081" , 0x1180080949ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5082" , 0x1180080949ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5083" , 0x1180080949ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5084" , 0x1180080949ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5085" , 0x1180080949ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5086" , 0x1180080949ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5087" , 0x1180080949ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5088" , 0x1180080949f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5089" , 0x1180080949f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5090" , 0x1180080949f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5091" , 0x1180080949f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5092" , 0x1180080949f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5093" , 0x1180080949f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5094" , 0x1180080949f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5095" , 0x1180080949f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5096" , 0x1180080949f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5097" , 0x1180080949f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5098" , 0x1180080949f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5099" , 0x1180080949f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5100" , 0x1180080949f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5101" , 0x1180080949f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5102" , 0x1180080949f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5103" , 0x1180080949f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5104" , 0x1180080949f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5105" , 0x1180080949f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5106" , 0x1180080949f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5107" , 0x1180080949f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5108" , 0x1180080949fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5109" , 0x1180080949fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5110" , 0x1180080949fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5111" , 0x1180080949fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5112" , 0x1180080949fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5113" , 0x1180080949fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5114" , 0x1180080949fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5115" , 0x1180080949fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5116" , 0x1180080949fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5117" , 0x1180080949fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5118" , 0x1180080949ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5119" , 0x1180080949ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5120" , 0x118008094a000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5121" , 0x118008094a008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5122" , 0x118008094a010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5123" , 0x118008094a018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5124" , 0x118008094a020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5125" , 0x118008094a028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5126" , 0x118008094a030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5127" , 0x118008094a038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5128" , 0x118008094a040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5129" , 0x118008094a048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5130" , 0x118008094a050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5131" , 0x118008094a058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5132" , 0x118008094a060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5133" , 0x118008094a068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5134" , 0x118008094a070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5135" , 0x118008094a078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5136" , 0x118008094a080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5137" , 0x118008094a088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5138" , 0x118008094a090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5139" , 0x118008094a098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5140" , 0x118008094a0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5141" , 0x118008094a0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5142" , 0x118008094a0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5143" , 0x118008094a0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5144" , 0x118008094a0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5145" , 0x118008094a0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5146" , 0x118008094a0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5147" , 0x118008094a0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5148" , 0x118008094a0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5149" , 0x118008094a0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5150" , 0x118008094a0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5151" , 0x118008094a0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5152" , 0x118008094a100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5153" , 0x118008094a108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5154" , 0x118008094a110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5155" , 0x118008094a118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5156" , 0x118008094a120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5157" , 0x118008094a128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5158" , 0x118008094a130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5159" , 0x118008094a138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5160" , 0x118008094a140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5161" , 0x118008094a148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5162" , 0x118008094a150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5163" , 0x118008094a158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5164" , 0x118008094a160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5165" , 0x118008094a168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5166" , 0x118008094a170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5167" , 0x118008094a178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5168" , 0x118008094a180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5169" , 0x118008094a188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5170" , 0x118008094a190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5171" , 0x118008094a198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5172" , 0x118008094a1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5173" , 0x118008094a1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5174" , 0x118008094a1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5175" , 0x118008094a1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5176" , 0x118008094a1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5177" , 0x118008094a1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5178" , 0x118008094a1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5179" , 0x118008094a1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5180" , 0x118008094a1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5181" , 0x118008094a1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5182" , 0x118008094a1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5183" , 0x118008094a1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5184" , 0x118008094a200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5185" , 0x118008094a208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5186" , 0x118008094a210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5187" , 0x118008094a218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5188" , 0x118008094a220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5189" , 0x118008094a228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5190" , 0x118008094a230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5191" , 0x118008094a238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5192" , 0x118008094a240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5193" , 0x118008094a248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5194" , 0x118008094a250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5195" , 0x118008094a258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5196" , 0x118008094a260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5197" , 0x118008094a268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5198" , 0x118008094a270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5199" , 0x118008094a278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5200" , 0x118008094a280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5201" , 0x118008094a288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5202" , 0x118008094a290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5203" , 0x118008094a298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5204" , 0x118008094a2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5205" , 0x118008094a2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5206" , 0x118008094a2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5207" , 0x118008094a2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5208" , 0x118008094a2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5209" , 0x118008094a2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5210" , 0x118008094a2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5211" , 0x118008094a2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5212" , 0x118008094a2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5213" , 0x118008094a2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5214" , 0x118008094a2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5215" , 0x118008094a2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5216" , 0x118008094a300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5217" , 0x118008094a308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5218" , 0x118008094a310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5219" , 0x118008094a318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5220" , 0x118008094a320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5221" , 0x118008094a328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5222" , 0x118008094a330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5223" , 0x118008094a338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5224" , 0x118008094a340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5225" , 0x118008094a348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5226" , 0x118008094a350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5227" , 0x118008094a358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5228" , 0x118008094a360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5229" , 0x118008094a368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5230" , 0x118008094a370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5231" , 0x118008094a378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5232" , 0x118008094a380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5233" , 0x118008094a388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5234" , 0x118008094a390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5235" , 0x118008094a398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5236" , 0x118008094a3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5237" , 0x118008094a3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5238" , 0x118008094a3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5239" , 0x118008094a3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5240" , 0x118008094a3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5241" , 0x118008094a3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5242" , 0x118008094a3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5243" , 0x118008094a3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5244" , 0x118008094a3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5245" , 0x118008094a3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5246" , 0x118008094a3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5247" , 0x118008094a3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5248" , 0x118008094a400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5249" , 0x118008094a408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5250" , 0x118008094a410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5251" , 0x118008094a418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5252" , 0x118008094a420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5253" , 0x118008094a428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5254" , 0x118008094a430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5255" , 0x118008094a438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5256" , 0x118008094a440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5257" , 0x118008094a448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5258" , 0x118008094a450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5259" , 0x118008094a458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5260" , 0x118008094a460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5261" , 0x118008094a468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5262" , 0x118008094a470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5263" , 0x118008094a478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5264" , 0x118008094a480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5265" , 0x118008094a488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5266" , 0x118008094a490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5267" , 0x118008094a498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5268" , 0x118008094a4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5269" , 0x118008094a4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5270" , 0x118008094a4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5271" , 0x118008094a4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5272" , 0x118008094a4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5273" , 0x118008094a4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5274" , 0x118008094a4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5275" , 0x118008094a4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5276" , 0x118008094a4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5277" , 0x118008094a4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5278" , 0x118008094a4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5279" , 0x118008094a4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5280" , 0x118008094a500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5281" , 0x118008094a508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5282" , 0x118008094a510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5283" , 0x118008094a518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5284" , 0x118008094a520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5285" , 0x118008094a528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5286" , 0x118008094a530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5287" , 0x118008094a538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5288" , 0x118008094a540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5289" , 0x118008094a548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5290" , 0x118008094a550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5291" , 0x118008094a558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5292" , 0x118008094a560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5293" , 0x118008094a568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5294" , 0x118008094a570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5295" , 0x118008094a578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5296" , 0x118008094a580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5297" , 0x118008094a588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5298" , 0x118008094a590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5299" , 0x118008094a598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5300" , 0x118008094a5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5301" , 0x118008094a5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5302" , 0x118008094a5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5303" , 0x118008094a5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5304" , 0x118008094a5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5305" , 0x118008094a5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5306" , 0x118008094a5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5307" , 0x118008094a5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5308" , 0x118008094a5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5309" , 0x118008094a5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5310" , 0x118008094a5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5311" , 0x118008094a5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5312" , 0x118008094a600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5313" , 0x118008094a608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5314" , 0x118008094a610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5315" , 0x118008094a618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5316" , 0x118008094a620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5317" , 0x118008094a628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5318" , 0x118008094a630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5319" , 0x118008094a638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5320" , 0x118008094a640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5321" , 0x118008094a648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5322" , 0x118008094a650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5323" , 0x118008094a658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5324" , 0x118008094a660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5325" , 0x118008094a668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5326" , 0x118008094a670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5327" , 0x118008094a678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5328" , 0x118008094a680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5329" , 0x118008094a688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5330" , 0x118008094a690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5331" , 0x118008094a698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5332" , 0x118008094a6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5333" , 0x118008094a6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5334" , 0x118008094a6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5335" , 0x118008094a6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5336" , 0x118008094a6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5337" , 0x118008094a6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5338" , 0x118008094a6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5339" , 0x118008094a6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5340" , 0x118008094a6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5341" , 0x118008094a6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5342" , 0x118008094a6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5343" , 0x118008094a6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5344" , 0x118008094a700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5345" , 0x118008094a708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5346" , 0x118008094a710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5347" , 0x118008094a718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5348" , 0x118008094a720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5349" , 0x118008094a728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5350" , 0x118008094a730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5351" , 0x118008094a738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5352" , 0x118008094a740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5353" , 0x118008094a748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5354" , 0x118008094a750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5355" , 0x118008094a758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5356" , 0x118008094a760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5357" , 0x118008094a768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5358" , 0x118008094a770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5359" , 0x118008094a778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5360" , 0x118008094a780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5361" , 0x118008094a788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5362" , 0x118008094a790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5363" , 0x118008094a798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5364" , 0x118008094a7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5365" , 0x118008094a7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5366" , 0x118008094a7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5367" , 0x118008094a7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5368" , 0x118008094a7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5369" , 0x118008094a7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5370" , 0x118008094a7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5371" , 0x118008094a7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5372" , 0x118008094a7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5373" , 0x118008094a7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5374" , 0x118008094a7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5375" , 0x118008094a7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5376" , 0x118008094a800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5377" , 0x118008094a808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5378" , 0x118008094a810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5379" , 0x118008094a818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5380" , 0x118008094a820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5381" , 0x118008094a828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5382" , 0x118008094a830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5383" , 0x118008094a838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5384" , 0x118008094a840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5385" , 0x118008094a848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5386" , 0x118008094a850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5387" , 0x118008094a858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5388" , 0x118008094a860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5389" , 0x118008094a868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5390" , 0x118008094a870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5391" , 0x118008094a878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5392" , 0x118008094a880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5393" , 0x118008094a888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5394" , 0x118008094a890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5395" , 0x118008094a898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5396" , 0x118008094a8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5397" , 0x118008094a8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5398" , 0x118008094a8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5399" , 0x118008094a8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5400" , 0x118008094a8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5401" , 0x118008094a8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5402" , 0x118008094a8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5403" , 0x118008094a8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5404" , 0x118008094a8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5405" , 0x118008094a8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5406" , 0x118008094a8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5407" , 0x118008094a8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5408" , 0x118008094a900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5409" , 0x118008094a908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5410" , 0x118008094a910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5411" , 0x118008094a918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5412" , 0x118008094a920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5413" , 0x118008094a928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5414" , 0x118008094a930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5415" , 0x118008094a938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5416" , 0x118008094a940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5417" , 0x118008094a948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5418" , 0x118008094a950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5419" , 0x118008094a958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5420" , 0x118008094a960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5421" , 0x118008094a968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5422" , 0x118008094a970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5423" , 0x118008094a978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5424" , 0x118008094a980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5425" , 0x118008094a988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5426" , 0x118008094a990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5427" , 0x118008094a998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5428" , 0x118008094a9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5429" , 0x118008094a9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5430" , 0x118008094a9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5431" , 0x118008094a9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5432" , 0x118008094a9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5433" , 0x118008094a9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5434" , 0x118008094a9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5435" , 0x118008094a9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5436" , 0x118008094a9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5437" , 0x118008094a9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5438" , 0x118008094a9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5439" , 0x118008094a9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5440" , 0x118008094aa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5441" , 0x118008094aa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5442" , 0x118008094aa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5443" , 0x118008094aa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5444" , 0x118008094aa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5445" , 0x118008094aa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5446" , 0x118008094aa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5447" , 0x118008094aa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5448" , 0x118008094aa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5449" , 0x118008094aa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5450" , 0x118008094aa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5451" , 0x118008094aa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5452" , 0x118008094aa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5453" , 0x118008094aa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5454" , 0x118008094aa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5455" , 0x118008094aa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5456" , 0x118008094aa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5457" , 0x118008094aa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5458" , 0x118008094aa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5459" , 0x118008094aa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5460" , 0x118008094aaa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5461" , 0x118008094aaa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5462" , 0x118008094aab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5463" , 0x118008094aab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5464" , 0x118008094aac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5465" , 0x118008094aac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5466" , 0x118008094aad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5467" , 0x118008094aad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5468" , 0x118008094aae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5469" , 0x118008094aae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5470" , 0x118008094aaf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5471" , 0x118008094aaf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5472" , 0x118008094ab00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5473" , 0x118008094ab08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5474" , 0x118008094ab10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5475" , 0x118008094ab18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5476" , 0x118008094ab20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5477" , 0x118008094ab28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5478" , 0x118008094ab30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5479" , 0x118008094ab38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5480" , 0x118008094ab40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5481" , 0x118008094ab48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5482" , 0x118008094ab50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5483" , 0x118008094ab58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5484" , 0x118008094ab60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5485" , 0x118008094ab68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5486" , 0x118008094ab70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5487" , 0x118008094ab78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5488" , 0x118008094ab80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5489" , 0x118008094ab88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5490" , 0x118008094ab90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5491" , 0x118008094ab98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5492" , 0x118008094aba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5493" , 0x118008094aba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5494" , 0x118008094abb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5495" , 0x118008094abb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5496" , 0x118008094abc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5497" , 0x118008094abc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5498" , 0x118008094abd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5499" , 0x118008094abd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5500" , 0x118008094abe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5501" , 0x118008094abe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5502" , 0x118008094abf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5503" , 0x118008094abf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5504" , 0x118008094ac00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5505" , 0x118008094ac08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5506" , 0x118008094ac10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5507" , 0x118008094ac18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5508" , 0x118008094ac20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5509" , 0x118008094ac28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5510" , 0x118008094ac30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5511" , 0x118008094ac38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5512" , 0x118008094ac40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5513" , 0x118008094ac48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5514" , 0x118008094ac50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5515" , 0x118008094ac58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5516" , 0x118008094ac60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5517" , 0x118008094ac68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5518" , 0x118008094ac70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5519" , 0x118008094ac78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5520" , 0x118008094ac80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5521" , 0x118008094ac88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5522" , 0x118008094ac90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5523" , 0x118008094ac98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5524" , 0x118008094aca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5525" , 0x118008094aca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5526" , 0x118008094acb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5527" , 0x118008094acb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5528" , 0x118008094acc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5529" , 0x118008094acc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5530" , 0x118008094acd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5531" , 0x118008094acd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5532" , 0x118008094ace0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5533" , 0x118008094ace8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5534" , 0x118008094acf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5535" , 0x118008094acf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5536" , 0x118008094ad00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5537" , 0x118008094ad08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5538" , 0x118008094ad10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5539" , 0x118008094ad18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5540" , 0x118008094ad20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5541" , 0x118008094ad28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5542" , 0x118008094ad30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5543" , 0x118008094ad38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5544" , 0x118008094ad40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5545" , 0x118008094ad48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5546" , 0x118008094ad50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5547" , 0x118008094ad58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5548" , 0x118008094ad60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5549" , 0x118008094ad68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5550" , 0x118008094ad70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5551" , 0x118008094ad78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5552" , 0x118008094ad80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5553" , 0x118008094ad88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5554" , 0x118008094ad90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5555" , 0x118008094ad98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5556" , 0x118008094ada0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5557" , 0x118008094ada8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5558" , 0x118008094adb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5559" , 0x118008094adb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5560" , 0x118008094adc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5561" , 0x118008094adc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5562" , 0x118008094add0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5563" , 0x118008094add8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5564" , 0x118008094ade0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5565" , 0x118008094ade8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5566" , 0x118008094adf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5567" , 0x118008094adf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5568" , 0x118008094ae00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5569" , 0x118008094ae08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5570" , 0x118008094ae10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5571" , 0x118008094ae18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5572" , 0x118008094ae20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5573" , 0x118008094ae28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5574" , 0x118008094ae30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5575" , 0x118008094ae38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5576" , 0x118008094ae40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5577" , 0x118008094ae48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5578" , 0x118008094ae50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5579" , 0x118008094ae58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5580" , 0x118008094ae60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5581" , 0x118008094ae68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5582" , 0x118008094ae70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5583" , 0x118008094ae78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5584" , 0x118008094ae80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5585" , 0x118008094ae88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5586" , 0x118008094ae90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5587" , 0x118008094ae98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5588" , 0x118008094aea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5589" , 0x118008094aea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5590" , 0x118008094aeb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5591" , 0x118008094aeb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5592" , 0x118008094aec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5593" , 0x118008094aec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5594" , 0x118008094aed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5595" , 0x118008094aed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5596" , 0x118008094aee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5597" , 0x118008094aee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5598" , 0x118008094aef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5599" , 0x118008094aef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5600" , 0x118008094af00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5601" , 0x118008094af08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5602" , 0x118008094af10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5603" , 0x118008094af18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5604" , 0x118008094af20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5605" , 0x118008094af28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5606" , 0x118008094af30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5607" , 0x118008094af38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5608" , 0x118008094af40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5609" , 0x118008094af48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5610" , 0x118008094af50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5611" , 0x118008094af58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5612" , 0x118008094af60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5613" , 0x118008094af68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5614" , 0x118008094af70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5615" , 0x118008094af78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5616" , 0x118008094af80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5617" , 0x118008094af88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5618" , 0x118008094af90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5619" , 0x118008094af98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5620" , 0x118008094afa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5621" , 0x118008094afa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5622" , 0x118008094afb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5623" , 0x118008094afb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5624" , 0x118008094afc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5625" , 0x118008094afc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5626" , 0x118008094afd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5627" , 0x118008094afd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5628" , 0x118008094afe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5629" , 0x118008094afe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5630" , 0x118008094aff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5631" , 0x118008094aff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5632" , 0x118008094b000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5633" , 0x118008094b008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5634" , 0x118008094b010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5635" , 0x118008094b018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5636" , 0x118008094b020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5637" , 0x118008094b028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5638" , 0x118008094b030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5639" , 0x118008094b038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5640" , 0x118008094b040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5641" , 0x118008094b048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5642" , 0x118008094b050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5643" , 0x118008094b058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5644" , 0x118008094b060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5645" , 0x118008094b068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5646" , 0x118008094b070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5647" , 0x118008094b078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5648" , 0x118008094b080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5649" , 0x118008094b088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5650" , 0x118008094b090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5651" , 0x118008094b098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5652" , 0x118008094b0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5653" , 0x118008094b0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5654" , 0x118008094b0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5655" , 0x118008094b0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5656" , 0x118008094b0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5657" , 0x118008094b0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5658" , 0x118008094b0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5659" , 0x118008094b0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5660" , 0x118008094b0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5661" , 0x118008094b0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5662" , 0x118008094b0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5663" , 0x118008094b0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5664" , 0x118008094b100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5665" , 0x118008094b108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5666" , 0x118008094b110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5667" , 0x118008094b118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5668" , 0x118008094b120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5669" , 0x118008094b128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5670" , 0x118008094b130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5671" , 0x118008094b138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5672" , 0x118008094b140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5673" , 0x118008094b148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5674" , 0x118008094b150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5675" , 0x118008094b158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5676" , 0x118008094b160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5677" , 0x118008094b168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5678" , 0x118008094b170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5679" , 0x118008094b178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5680" , 0x118008094b180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5681" , 0x118008094b188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5682" , 0x118008094b190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5683" , 0x118008094b198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5684" , 0x118008094b1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5685" , 0x118008094b1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5686" , 0x118008094b1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5687" , 0x118008094b1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5688" , 0x118008094b1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5689" , 0x118008094b1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5690" , 0x118008094b1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5691" , 0x118008094b1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5692" , 0x118008094b1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5693" , 0x118008094b1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5694" , 0x118008094b1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5695" , 0x118008094b1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5696" , 0x118008094b200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5697" , 0x118008094b208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5698" , 0x118008094b210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5699" , 0x118008094b218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5700" , 0x118008094b220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5701" , 0x118008094b228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5702" , 0x118008094b230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5703" , 0x118008094b238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5704" , 0x118008094b240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5705" , 0x118008094b248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5706" , 0x118008094b250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5707" , 0x118008094b258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5708" , 0x118008094b260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5709" , 0x118008094b268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5710" , 0x118008094b270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5711" , 0x118008094b278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5712" , 0x118008094b280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5713" , 0x118008094b288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5714" , 0x118008094b290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5715" , 0x118008094b298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5716" , 0x118008094b2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5717" , 0x118008094b2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5718" , 0x118008094b2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5719" , 0x118008094b2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5720" , 0x118008094b2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5721" , 0x118008094b2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5722" , 0x118008094b2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5723" , 0x118008094b2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5724" , 0x118008094b2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5725" , 0x118008094b2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5726" , 0x118008094b2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5727" , 0x118008094b2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5728" , 0x118008094b300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5729" , 0x118008094b308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5730" , 0x118008094b310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5731" , 0x118008094b318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5732" , 0x118008094b320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5733" , 0x118008094b328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5734" , 0x118008094b330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5735" , 0x118008094b338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5736" , 0x118008094b340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5737" , 0x118008094b348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5738" , 0x118008094b350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5739" , 0x118008094b358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5740" , 0x118008094b360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5741" , 0x118008094b368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5742" , 0x118008094b370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5743" , 0x118008094b378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5744" , 0x118008094b380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5745" , 0x118008094b388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5746" , 0x118008094b390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5747" , 0x118008094b398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5748" , 0x118008094b3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5749" , 0x118008094b3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5750" , 0x118008094b3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5751" , 0x118008094b3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5752" , 0x118008094b3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5753" , 0x118008094b3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5754" , 0x118008094b3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5755" , 0x118008094b3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5756" , 0x118008094b3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5757" , 0x118008094b3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5758" , 0x118008094b3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5759" , 0x118008094b3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5760" , 0x118008094b400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5761" , 0x118008094b408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5762" , 0x118008094b410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5763" , 0x118008094b418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5764" , 0x118008094b420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5765" , 0x118008094b428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5766" , 0x118008094b430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5767" , 0x118008094b438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5768" , 0x118008094b440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5769" , 0x118008094b448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5770" , 0x118008094b450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5771" , 0x118008094b458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5772" , 0x118008094b460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5773" , 0x118008094b468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5774" , 0x118008094b470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5775" , 0x118008094b478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5776" , 0x118008094b480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5777" , 0x118008094b488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5778" , 0x118008094b490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5779" , 0x118008094b498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5780" , 0x118008094b4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5781" , 0x118008094b4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5782" , 0x118008094b4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5783" , 0x118008094b4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5784" , 0x118008094b4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5785" , 0x118008094b4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5786" , 0x118008094b4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5787" , 0x118008094b4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5788" , 0x118008094b4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5789" , 0x118008094b4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5790" , 0x118008094b4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5791" , 0x118008094b4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5792" , 0x118008094b500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5793" , 0x118008094b508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5794" , 0x118008094b510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5795" , 0x118008094b518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5796" , 0x118008094b520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5797" , 0x118008094b528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5798" , 0x118008094b530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5799" , 0x118008094b538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5800" , 0x118008094b540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5801" , 0x118008094b548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5802" , 0x118008094b550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5803" , 0x118008094b558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5804" , 0x118008094b560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5805" , 0x118008094b568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5806" , 0x118008094b570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5807" , 0x118008094b578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5808" , 0x118008094b580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5809" , 0x118008094b588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5810" , 0x118008094b590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5811" , 0x118008094b598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5812" , 0x118008094b5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5813" , 0x118008094b5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5814" , 0x118008094b5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5815" , 0x118008094b5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5816" , 0x118008094b5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5817" , 0x118008094b5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5818" , 0x118008094b5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5819" , 0x118008094b5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5820" , 0x118008094b5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5821" , 0x118008094b5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5822" , 0x118008094b5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5823" , 0x118008094b5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5824" , 0x118008094b600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5825" , 0x118008094b608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5826" , 0x118008094b610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5827" , 0x118008094b618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5828" , 0x118008094b620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5829" , 0x118008094b628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5830" , 0x118008094b630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5831" , 0x118008094b638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5832" , 0x118008094b640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5833" , 0x118008094b648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5834" , 0x118008094b650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5835" , 0x118008094b658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5836" , 0x118008094b660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5837" , 0x118008094b668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5838" , 0x118008094b670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5839" , 0x118008094b678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5840" , 0x118008094b680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5841" , 0x118008094b688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5842" , 0x118008094b690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5843" , 0x118008094b698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5844" , 0x118008094b6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5845" , 0x118008094b6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5846" , 0x118008094b6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5847" , 0x118008094b6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5848" , 0x118008094b6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5849" , 0x118008094b6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5850" , 0x118008094b6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5851" , 0x118008094b6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5852" , 0x118008094b6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5853" , 0x118008094b6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5854" , 0x118008094b6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5855" , 0x118008094b6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5856" , 0x118008094b700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5857" , 0x118008094b708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5858" , 0x118008094b710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5859" , 0x118008094b718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5860" , 0x118008094b720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5861" , 0x118008094b728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5862" , 0x118008094b730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5863" , 0x118008094b738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5864" , 0x118008094b740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5865" , 0x118008094b748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5866" , 0x118008094b750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5867" , 0x118008094b758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5868" , 0x118008094b760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5869" , 0x118008094b768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5870" , 0x118008094b770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5871" , 0x118008094b778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5872" , 0x118008094b780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5873" , 0x118008094b788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5874" , 0x118008094b790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5875" , 0x118008094b798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5876" , 0x118008094b7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5877" , 0x118008094b7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5878" , 0x118008094b7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5879" , 0x118008094b7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5880" , 0x118008094b7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5881" , 0x118008094b7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5882" , 0x118008094b7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5883" , 0x118008094b7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5884" , 0x118008094b7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5885" , 0x118008094b7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5886" , 0x118008094b7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5887" , 0x118008094b7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5888" , 0x118008094b800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5889" , 0x118008094b808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5890" , 0x118008094b810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5891" , 0x118008094b818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5892" , 0x118008094b820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5893" , 0x118008094b828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5894" , 0x118008094b830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5895" , 0x118008094b838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5896" , 0x118008094b840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5897" , 0x118008094b848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5898" , 0x118008094b850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5899" , 0x118008094b858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5900" , 0x118008094b860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5901" , 0x118008094b868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5902" , 0x118008094b870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5903" , 0x118008094b878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5904" , 0x118008094b880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5905" , 0x118008094b888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5906" , 0x118008094b890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5907" , 0x118008094b898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5908" , 0x118008094b8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5909" , 0x118008094b8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5910" , 0x118008094b8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5911" , 0x118008094b8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5912" , 0x118008094b8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5913" , 0x118008094b8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5914" , 0x118008094b8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5915" , 0x118008094b8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5916" , 0x118008094b8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5917" , 0x118008094b8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5918" , 0x118008094b8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5919" , 0x118008094b8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5920" , 0x118008094b900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5921" , 0x118008094b908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5922" , 0x118008094b910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5923" , 0x118008094b918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5924" , 0x118008094b920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5925" , 0x118008094b928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5926" , 0x118008094b930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5927" , 0x118008094b938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5928" , 0x118008094b940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5929" , 0x118008094b948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5930" , 0x118008094b950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5931" , 0x118008094b958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5932" , 0x118008094b960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5933" , 0x118008094b968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5934" , 0x118008094b970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5935" , 0x118008094b978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5936" , 0x118008094b980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5937" , 0x118008094b988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5938" , 0x118008094b990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5939" , 0x118008094b998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5940" , 0x118008094b9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5941" , 0x118008094b9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5942" , 0x118008094b9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5943" , 0x118008094b9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5944" , 0x118008094b9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5945" , 0x118008094b9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5946" , 0x118008094b9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5947" , 0x118008094b9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5948" , 0x118008094b9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5949" , 0x118008094b9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5950" , 0x118008094b9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5951" , 0x118008094b9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5952" , 0x118008094ba00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5953" , 0x118008094ba08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5954" , 0x118008094ba10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5955" , 0x118008094ba18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5956" , 0x118008094ba20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5957" , 0x118008094ba28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5958" , 0x118008094ba30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5959" , 0x118008094ba38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5960" , 0x118008094ba40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5961" , 0x118008094ba48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5962" , 0x118008094ba50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5963" , 0x118008094ba58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5964" , 0x118008094ba60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5965" , 0x118008094ba68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5966" , 0x118008094ba70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5967" , 0x118008094ba78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5968" , 0x118008094ba80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5969" , 0x118008094ba88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5970" , 0x118008094ba90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5971" , 0x118008094ba98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5972" , 0x118008094baa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5973" , 0x118008094baa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5974" , 0x118008094bab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5975" , 0x118008094bab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5976" , 0x118008094bac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5977" , 0x118008094bac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5978" , 0x118008094bad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5979" , 0x118008094bad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5980" , 0x118008094bae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5981" , 0x118008094bae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5982" , 0x118008094baf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5983" , 0x118008094baf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5984" , 0x118008094bb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5985" , 0x118008094bb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5986" , 0x118008094bb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5987" , 0x118008094bb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5988" , 0x118008094bb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5989" , 0x118008094bb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5990" , 0x118008094bb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5991" , 0x118008094bb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5992" , 0x118008094bb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5993" , 0x118008094bb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5994" , 0x118008094bb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5995" , 0x118008094bb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5996" , 0x118008094bb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5997" , 0x118008094bb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5998" , 0x118008094bb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP5999" , 0x118008094bb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6000" , 0x118008094bb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6001" , 0x118008094bb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6002" , 0x118008094bb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6003" , 0x118008094bb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6004" , 0x118008094bba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6005" , 0x118008094bba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6006" , 0x118008094bbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6007" , 0x118008094bbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6008" , 0x118008094bbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6009" , 0x118008094bbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6010" , 0x118008094bbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6011" , 0x118008094bbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6012" , 0x118008094bbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6013" , 0x118008094bbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6014" , 0x118008094bbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6015" , 0x118008094bbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6016" , 0x118008094bc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6017" , 0x118008094bc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6018" , 0x118008094bc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6019" , 0x118008094bc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6020" , 0x118008094bc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6021" , 0x118008094bc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6022" , 0x118008094bc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6023" , 0x118008094bc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6024" , 0x118008094bc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6025" , 0x118008094bc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6026" , 0x118008094bc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6027" , 0x118008094bc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6028" , 0x118008094bc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6029" , 0x118008094bc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6030" , 0x118008094bc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6031" , 0x118008094bc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6032" , 0x118008094bc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6033" , 0x118008094bc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6034" , 0x118008094bc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6035" , 0x118008094bc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6036" , 0x118008094bca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6037" , 0x118008094bca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6038" , 0x118008094bcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6039" , 0x118008094bcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6040" , 0x118008094bcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6041" , 0x118008094bcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6042" , 0x118008094bcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6043" , 0x118008094bcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6044" , 0x118008094bce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6045" , 0x118008094bce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6046" , 0x118008094bcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6047" , 0x118008094bcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6048" , 0x118008094bd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6049" , 0x118008094bd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6050" , 0x118008094bd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6051" , 0x118008094bd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6052" , 0x118008094bd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6053" , 0x118008094bd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6054" , 0x118008094bd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6055" , 0x118008094bd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6056" , 0x118008094bd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6057" , 0x118008094bd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6058" , 0x118008094bd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6059" , 0x118008094bd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6060" , 0x118008094bd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6061" , 0x118008094bd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6062" , 0x118008094bd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6063" , 0x118008094bd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6064" , 0x118008094bd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6065" , 0x118008094bd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6066" , 0x118008094bd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6067" , 0x118008094bd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6068" , 0x118008094bda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6069" , 0x118008094bda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6070" , 0x118008094bdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6071" , 0x118008094bdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6072" , 0x118008094bdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6073" , 0x118008094bdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6074" , 0x118008094bdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6075" , 0x118008094bdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6076" , 0x118008094bde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6077" , 0x118008094bde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6078" , 0x118008094bdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6079" , 0x118008094bdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6080" , 0x118008094be00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6081" , 0x118008094be08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6082" , 0x118008094be10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6083" , 0x118008094be18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6084" , 0x118008094be20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6085" , 0x118008094be28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6086" , 0x118008094be30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6087" , 0x118008094be38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6088" , 0x118008094be40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6089" , 0x118008094be48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6090" , 0x118008094be50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6091" , 0x118008094be58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6092" , 0x118008094be60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6093" , 0x118008094be68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6094" , 0x118008094be70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6095" , 0x118008094be78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6096" , 0x118008094be80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6097" , 0x118008094be88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6098" , 0x118008094be90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6099" , 0x118008094be98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6100" , 0x118008094bea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6101" , 0x118008094bea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6102" , 0x118008094beb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6103" , 0x118008094beb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6104" , 0x118008094bec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6105" , 0x118008094bec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6106" , 0x118008094bed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6107" , 0x118008094bed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6108" , 0x118008094bee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6109" , 0x118008094bee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6110" , 0x118008094bef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6111" , 0x118008094bef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6112" , 0x118008094bf00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6113" , 0x118008094bf08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6114" , 0x118008094bf10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6115" , 0x118008094bf18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6116" , 0x118008094bf20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6117" , 0x118008094bf28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6118" , 0x118008094bf30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6119" , 0x118008094bf38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6120" , 0x118008094bf40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6121" , 0x118008094bf48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6122" , 0x118008094bf50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6123" , 0x118008094bf58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6124" , 0x118008094bf60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6125" , 0x118008094bf68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6126" , 0x118008094bf70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6127" , 0x118008094bf78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6128" , 0x118008094bf80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6129" , 0x118008094bf88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6130" , 0x118008094bf90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6131" , 0x118008094bf98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6132" , 0x118008094bfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6133" , 0x118008094bfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6134" , 0x118008094bfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6135" , 0x118008094bfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6136" , 0x118008094bfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6137" , 0x118008094bfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6138" , 0x118008094bfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6139" , 0x118008094bfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6140" , 0x118008094bfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6141" , 0x118008094bfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6142" , 0x118008094bff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6143" , 0x118008094bff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6144" , 0x118008094c000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6145" , 0x118008094c008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6146" , 0x118008094c010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6147" , 0x118008094c018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6148" , 0x118008094c020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6149" , 0x118008094c028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6150" , 0x118008094c030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6151" , 0x118008094c038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6152" , 0x118008094c040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6153" , 0x118008094c048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6154" , 0x118008094c050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6155" , 0x118008094c058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6156" , 0x118008094c060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6157" , 0x118008094c068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6158" , 0x118008094c070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6159" , 0x118008094c078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6160" , 0x118008094c080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6161" , 0x118008094c088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6162" , 0x118008094c090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6163" , 0x118008094c098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6164" , 0x118008094c0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6165" , 0x118008094c0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6166" , 0x118008094c0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6167" , 0x118008094c0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6168" , 0x118008094c0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6169" , 0x118008094c0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6170" , 0x118008094c0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6171" , 0x118008094c0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6172" , 0x118008094c0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6173" , 0x118008094c0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6174" , 0x118008094c0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6175" , 0x118008094c0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6176" , 0x118008094c100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6177" , 0x118008094c108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6178" , 0x118008094c110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6179" , 0x118008094c118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6180" , 0x118008094c120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6181" , 0x118008094c128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6182" , 0x118008094c130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6183" , 0x118008094c138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6184" , 0x118008094c140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6185" , 0x118008094c148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6186" , 0x118008094c150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6187" , 0x118008094c158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6188" , 0x118008094c160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6189" , 0x118008094c168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6190" , 0x118008094c170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6191" , 0x118008094c178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6192" , 0x118008094c180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6193" , 0x118008094c188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6194" , 0x118008094c190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6195" , 0x118008094c198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6196" , 0x118008094c1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6197" , 0x118008094c1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6198" , 0x118008094c1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6199" , 0x118008094c1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6200" , 0x118008094c1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6201" , 0x118008094c1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6202" , 0x118008094c1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6203" , 0x118008094c1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6204" , 0x118008094c1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6205" , 0x118008094c1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6206" , 0x118008094c1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6207" , 0x118008094c1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6208" , 0x118008094c200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6209" , 0x118008094c208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6210" , 0x118008094c210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6211" , 0x118008094c218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6212" , 0x118008094c220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6213" , 0x118008094c228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6214" , 0x118008094c230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6215" , 0x118008094c238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6216" , 0x118008094c240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6217" , 0x118008094c248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6218" , 0x118008094c250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6219" , 0x118008094c258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6220" , 0x118008094c260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6221" , 0x118008094c268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6222" , 0x118008094c270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6223" , 0x118008094c278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6224" , 0x118008094c280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6225" , 0x118008094c288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6226" , 0x118008094c290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6227" , 0x118008094c298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6228" , 0x118008094c2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6229" , 0x118008094c2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6230" , 0x118008094c2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6231" , 0x118008094c2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6232" , 0x118008094c2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6233" , 0x118008094c2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6234" , 0x118008094c2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6235" , 0x118008094c2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6236" , 0x118008094c2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6237" , 0x118008094c2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6238" , 0x118008094c2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6239" , 0x118008094c2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6240" , 0x118008094c300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6241" , 0x118008094c308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6242" , 0x118008094c310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6243" , 0x118008094c318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6244" , 0x118008094c320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6245" , 0x118008094c328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6246" , 0x118008094c330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6247" , 0x118008094c338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6248" , 0x118008094c340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6249" , 0x118008094c348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6250" , 0x118008094c350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6251" , 0x118008094c358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6252" , 0x118008094c360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6253" , 0x118008094c368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6254" , 0x118008094c370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6255" , 0x118008094c378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6256" , 0x118008094c380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6257" , 0x118008094c388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6258" , 0x118008094c390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6259" , 0x118008094c398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6260" , 0x118008094c3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6261" , 0x118008094c3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6262" , 0x118008094c3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6263" , 0x118008094c3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6264" , 0x118008094c3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6265" , 0x118008094c3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6266" , 0x118008094c3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6267" , 0x118008094c3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6268" , 0x118008094c3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6269" , 0x118008094c3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6270" , 0x118008094c3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6271" , 0x118008094c3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6272" , 0x118008094c400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6273" , 0x118008094c408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6274" , 0x118008094c410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6275" , 0x118008094c418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6276" , 0x118008094c420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6277" , 0x118008094c428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6278" , 0x118008094c430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6279" , 0x118008094c438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6280" , 0x118008094c440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6281" , 0x118008094c448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6282" , 0x118008094c450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6283" , 0x118008094c458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6284" , 0x118008094c460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6285" , 0x118008094c468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6286" , 0x118008094c470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6287" , 0x118008094c478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6288" , 0x118008094c480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6289" , 0x118008094c488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6290" , 0x118008094c490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6291" , 0x118008094c498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6292" , 0x118008094c4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6293" , 0x118008094c4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6294" , 0x118008094c4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6295" , 0x118008094c4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6296" , 0x118008094c4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6297" , 0x118008094c4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6298" , 0x118008094c4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6299" , 0x118008094c4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6300" , 0x118008094c4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6301" , 0x118008094c4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6302" , 0x118008094c4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6303" , 0x118008094c4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6304" , 0x118008094c500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6305" , 0x118008094c508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6306" , 0x118008094c510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6307" , 0x118008094c518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6308" , 0x118008094c520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6309" , 0x118008094c528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6310" , 0x118008094c530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6311" , 0x118008094c538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6312" , 0x118008094c540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6313" , 0x118008094c548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6314" , 0x118008094c550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6315" , 0x118008094c558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6316" , 0x118008094c560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6317" , 0x118008094c568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6318" , 0x118008094c570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6319" , 0x118008094c578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6320" , 0x118008094c580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6321" , 0x118008094c588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6322" , 0x118008094c590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6323" , 0x118008094c598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6324" , 0x118008094c5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6325" , 0x118008094c5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6326" , 0x118008094c5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6327" , 0x118008094c5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6328" , 0x118008094c5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6329" , 0x118008094c5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6330" , 0x118008094c5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6331" , 0x118008094c5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6332" , 0x118008094c5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6333" , 0x118008094c5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6334" , 0x118008094c5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6335" , 0x118008094c5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6336" , 0x118008094c600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6337" , 0x118008094c608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6338" , 0x118008094c610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6339" , 0x118008094c618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6340" , 0x118008094c620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6341" , 0x118008094c628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6342" , 0x118008094c630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6343" , 0x118008094c638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6344" , 0x118008094c640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6345" , 0x118008094c648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6346" , 0x118008094c650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6347" , 0x118008094c658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6348" , 0x118008094c660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6349" , 0x118008094c668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6350" , 0x118008094c670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6351" , 0x118008094c678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6352" , 0x118008094c680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6353" , 0x118008094c688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6354" , 0x118008094c690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6355" , 0x118008094c698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6356" , 0x118008094c6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6357" , 0x118008094c6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6358" , 0x118008094c6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6359" , 0x118008094c6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6360" , 0x118008094c6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6361" , 0x118008094c6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6362" , 0x118008094c6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6363" , 0x118008094c6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6364" , 0x118008094c6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6365" , 0x118008094c6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6366" , 0x118008094c6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6367" , 0x118008094c6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6368" , 0x118008094c700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6369" , 0x118008094c708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6370" , 0x118008094c710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6371" , 0x118008094c718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6372" , 0x118008094c720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6373" , 0x118008094c728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6374" , 0x118008094c730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6375" , 0x118008094c738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6376" , 0x118008094c740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6377" , 0x118008094c748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6378" , 0x118008094c750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6379" , 0x118008094c758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6380" , 0x118008094c760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6381" , 0x118008094c768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6382" , 0x118008094c770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6383" , 0x118008094c778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6384" , 0x118008094c780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6385" , 0x118008094c788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6386" , 0x118008094c790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6387" , 0x118008094c798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6388" , 0x118008094c7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6389" , 0x118008094c7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6390" , 0x118008094c7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6391" , 0x118008094c7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6392" , 0x118008094c7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6393" , 0x118008094c7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6394" , 0x118008094c7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6395" , 0x118008094c7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6396" , 0x118008094c7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6397" , 0x118008094c7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6398" , 0x118008094c7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6399" , 0x118008094c7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6400" , 0x118008094c800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6401" , 0x118008094c808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6402" , 0x118008094c810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6403" , 0x118008094c818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6404" , 0x118008094c820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6405" , 0x118008094c828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6406" , 0x118008094c830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6407" , 0x118008094c838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6408" , 0x118008094c840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6409" , 0x118008094c848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6410" , 0x118008094c850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6411" , 0x118008094c858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6412" , 0x118008094c860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6413" , 0x118008094c868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6414" , 0x118008094c870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6415" , 0x118008094c878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6416" , 0x118008094c880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6417" , 0x118008094c888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6418" , 0x118008094c890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6419" , 0x118008094c898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6420" , 0x118008094c8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6421" , 0x118008094c8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6422" , 0x118008094c8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6423" , 0x118008094c8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6424" , 0x118008094c8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6425" , 0x118008094c8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6426" , 0x118008094c8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6427" , 0x118008094c8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6428" , 0x118008094c8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6429" , 0x118008094c8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6430" , 0x118008094c8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6431" , 0x118008094c8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6432" , 0x118008094c900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6433" , 0x118008094c908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6434" , 0x118008094c910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6435" , 0x118008094c918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6436" , 0x118008094c920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6437" , 0x118008094c928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6438" , 0x118008094c930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6439" , 0x118008094c938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6440" , 0x118008094c940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6441" , 0x118008094c948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6442" , 0x118008094c950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6443" , 0x118008094c958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6444" , 0x118008094c960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6445" , 0x118008094c968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6446" , 0x118008094c970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6447" , 0x118008094c978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6448" , 0x118008094c980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6449" , 0x118008094c988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6450" , 0x118008094c990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6451" , 0x118008094c998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6452" , 0x118008094c9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6453" , 0x118008094c9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6454" , 0x118008094c9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6455" , 0x118008094c9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6456" , 0x118008094c9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6457" , 0x118008094c9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6458" , 0x118008094c9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6459" , 0x118008094c9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6460" , 0x118008094c9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6461" , 0x118008094c9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6462" , 0x118008094c9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6463" , 0x118008094c9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6464" , 0x118008094ca00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6465" , 0x118008094ca08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6466" , 0x118008094ca10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6467" , 0x118008094ca18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6468" , 0x118008094ca20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6469" , 0x118008094ca28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6470" , 0x118008094ca30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6471" , 0x118008094ca38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6472" , 0x118008094ca40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6473" , 0x118008094ca48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6474" , 0x118008094ca50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6475" , 0x118008094ca58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6476" , 0x118008094ca60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6477" , 0x118008094ca68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6478" , 0x118008094ca70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6479" , 0x118008094ca78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6480" , 0x118008094ca80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6481" , 0x118008094ca88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6482" , 0x118008094ca90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6483" , 0x118008094ca98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6484" , 0x118008094caa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6485" , 0x118008094caa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6486" , 0x118008094cab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6487" , 0x118008094cab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6488" , 0x118008094cac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6489" , 0x118008094cac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6490" , 0x118008094cad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6491" , 0x118008094cad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6492" , 0x118008094cae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6493" , 0x118008094cae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6494" , 0x118008094caf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6495" , 0x118008094caf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6496" , 0x118008094cb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6497" , 0x118008094cb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6498" , 0x118008094cb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6499" , 0x118008094cb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6500" , 0x118008094cb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6501" , 0x118008094cb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6502" , 0x118008094cb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6503" , 0x118008094cb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6504" , 0x118008094cb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6505" , 0x118008094cb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6506" , 0x118008094cb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6507" , 0x118008094cb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6508" , 0x118008094cb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6509" , 0x118008094cb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6510" , 0x118008094cb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6511" , 0x118008094cb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6512" , 0x118008094cb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6513" , 0x118008094cb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6514" , 0x118008094cb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6515" , 0x118008094cb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6516" , 0x118008094cba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6517" , 0x118008094cba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6518" , 0x118008094cbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6519" , 0x118008094cbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6520" , 0x118008094cbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6521" , 0x118008094cbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6522" , 0x118008094cbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6523" , 0x118008094cbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6524" , 0x118008094cbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6525" , 0x118008094cbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6526" , 0x118008094cbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6527" , 0x118008094cbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6528" , 0x118008094cc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6529" , 0x118008094cc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6530" , 0x118008094cc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6531" , 0x118008094cc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6532" , 0x118008094cc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6533" , 0x118008094cc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6534" , 0x118008094cc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6535" , 0x118008094cc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6536" , 0x118008094cc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6537" , 0x118008094cc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6538" , 0x118008094cc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6539" , 0x118008094cc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6540" , 0x118008094cc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6541" , 0x118008094cc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6542" , 0x118008094cc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6543" , 0x118008094cc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6544" , 0x118008094cc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6545" , 0x118008094cc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6546" , 0x118008094cc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6547" , 0x118008094cc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6548" , 0x118008094cca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6549" , 0x118008094cca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6550" , 0x118008094ccb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6551" , 0x118008094ccb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6552" , 0x118008094ccc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6553" , 0x118008094ccc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6554" , 0x118008094ccd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6555" , 0x118008094ccd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6556" , 0x118008094cce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6557" , 0x118008094cce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6558" , 0x118008094ccf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6559" , 0x118008094ccf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6560" , 0x118008094cd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6561" , 0x118008094cd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6562" , 0x118008094cd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6563" , 0x118008094cd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6564" , 0x118008094cd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6565" , 0x118008094cd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6566" , 0x118008094cd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6567" , 0x118008094cd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6568" , 0x118008094cd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6569" , 0x118008094cd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6570" , 0x118008094cd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6571" , 0x118008094cd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6572" , 0x118008094cd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6573" , 0x118008094cd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6574" , 0x118008094cd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6575" , 0x118008094cd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6576" , 0x118008094cd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6577" , 0x118008094cd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6578" , 0x118008094cd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6579" , 0x118008094cd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6580" , 0x118008094cda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6581" , 0x118008094cda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6582" , 0x118008094cdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6583" , 0x118008094cdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6584" , 0x118008094cdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6585" , 0x118008094cdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6586" , 0x118008094cdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6587" , 0x118008094cdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6588" , 0x118008094cde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6589" , 0x118008094cde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6590" , 0x118008094cdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6591" , 0x118008094cdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6592" , 0x118008094ce00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6593" , 0x118008094ce08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6594" , 0x118008094ce10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6595" , 0x118008094ce18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6596" , 0x118008094ce20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6597" , 0x118008094ce28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6598" , 0x118008094ce30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6599" , 0x118008094ce38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6600" , 0x118008094ce40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6601" , 0x118008094ce48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6602" , 0x118008094ce50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6603" , 0x118008094ce58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6604" , 0x118008094ce60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6605" , 0x118008094ce68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6606" , 0x118008094ce70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6607" , 0x118008094ce78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6608" , 0x118008094ce80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6609" , 0x118008094ce88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6610" , 0x118008094ce90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6611" , 0x118008094ce98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6612" , 0x118008094cea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6613" , 0x118008094cea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6614" , 0x118008094ceb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6615" , 0x118008094ceb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6616" , 0x118008094cec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6617" , 0x118008094cec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6618" , 0x118008094ced0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6619" , 0x118008094ced8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6620" , 0x118008094cee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6621" , 0x118008094cee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6622" , 0x118008094cef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6623" , 0x118008094cef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6624" , 0x118008094cf00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6625" , 0x118008094cf08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6626" , 0x118008094cf10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6627" , 0x118008094cf18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6628" , 0x118008094cf20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6629" , 0x118008094cf28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6630" , 0x118008094cf30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6631" , 0x118008094cf38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6632" , 0x118008094cf40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6633" , 0x118008094cf48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6634" , 0x118008094cf50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6635" , 0x118008094cf58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6636" , 0x118008094cf60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6637" , 0x118008094cf68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6638" , 0x118008094cf70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6639" , 0x118008094cf78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6640" , 0x118008094cf80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6641" , 0x118008094cf88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6642" , 0x118008094cf90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6643" , 0x118008094cf98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6644" , 0x118008094cfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6645" , 0x118008094cfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6646" , 0x118008094cfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6647" , 0x118008094cfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6648" , 0x118008094cfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6649" , 0x118008094cfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6650" , 0x118008094cfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6651" , 0x118008094cfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6652" , 0x118008094cfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6653" , 0x118008094cfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6654" , 0x118008094cff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6655" , 0x118008094cff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6656" , 0x118008094d000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6657" , 0x118008094d008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6658" , 0x118008094d010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6659" , 0x118008094d018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6660" , 0x118008094d020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6661" , 0x118008094d028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6662" , 0x118008094d030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6663" , 0x118008094d038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6664" , 0x118008094d040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6665" , 0x118008094d048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6666" , 0x118008094d050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6667" , 0x118008094d058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6668" , 0x118008094d060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6669" , 0x118008094d068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6670" , 0x118008094d070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6671" , 0x118008094d078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6672" , 0x118008094d080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6673" , 0x118008094d088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6674" , 0x118008094d090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6675" , 0x118008094d098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6676" , 0x118008094d0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6677" , 0x118008094d0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6678" , 0x118008094d0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6679" , 0x118008094d0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6680" , 0x118008094d0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6681" , 0x118008094d0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6682" , 0x118008094d0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6683" , 0x118008094d0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6684" , 0x118008094d0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6685" , 0x118008094d0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6686" , 0x118008094d0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6687" , 0x118008094d0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6688" , 0x118008094d100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6689" , 0x118008094d108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6690" , 0x118008094d110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6691" , 0x118008094d118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6692" , 0x118008094d120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6693" , 0x118008094d128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6694" , 0x118008094d130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6695" , 0x118008094d138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6696" , 0x118008094d140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6697" , 0x118008094d148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6698" , 0x118008094d150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6699" , 0x118008094d158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6700" , 0x118008094d160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6701" , 0x118008094d168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6702" , 0x118008094d170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6703" , 0x118008094d178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6704" , 0x118008094d180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6705" , 0x118008094d188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6706" , 0x118008094d190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6707" , 0x118008094d198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6708" , 0x118008094d1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6709" , 0x118008094d1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6710" , 0x118008094d1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6711" , 0x118008094d1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6712" , 0x118008094d1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6713" , 0x118008094d1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6714" , 0x118008094d1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6715" , 0x118008094d1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6716" , 0x118008094d1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6717" , 0x118008094d1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6718" , 0x118008094d1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6719" , 0x118008094d1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6720" , 0x118008094d200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6721" , 0x118008094d208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6722" , 0x118008094d210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6723" , 0x118008094d218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6724" , 0x118008094d220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6725" , 0x118008094d228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6726" , 0x118008094d230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6727" , 0x118008094d238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6728" , 0x118008094d240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6729" , 0x118008094d248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6730" , 0x118008094d250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6731" , 0x118008094d258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6732" , 0x118008094d260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6733" , 0x118008094d268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6734" , 0x118008094d270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6735" , 0x118008094d278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6736" , 0x118008094d280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6737" , 0x118008094d288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6738" , 0x118008094d290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6739" , 0x118008094d298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6740" , 0x118008094d2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6741" , 0x118008094d2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6742" , 0x118008094d2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6743" , 0x118008094d2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6744" , 0x118008094d2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6745" , 0x118008094d2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6746" , 0x118008094d2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6747" , 0x118008094d2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6748" , 0x118008094d2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6749" , 0x118008094d2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6750" , 0x118008094d2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6751" , 0x118008094d2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6752" , 0x118008094d300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6753" , 0x118008094d308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6754" , 0x118008094d310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6755" , 0x118008094d318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6756" , 0x118008094d320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6757" , 0x118008094d328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6758" , 0x118008094d330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6759" , 0x118008094d338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6760" , 0x118008094d340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6761" , 0x118008094d348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6762" , 0x118008094d350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6763" , 0x118008094d358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6764" , 0x118008094d360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6765" , 0x118008094d368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6766" , 0x118008094d370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6767" , 0x118008094d378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6768" , 0x118008094d380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6769" , 0x118008094d388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6770" , 0x118008094d390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6771" , 0x118008094d398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6772" , 0x118008094d3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6773" , 0x118008094d3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6774" , 0x118008094d3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6775" , 0x118008094d3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6776" , 0x118008094d3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6777" , 0x118008094d3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6778" , 0x118008094d3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6779" , 0x118008094d3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6780" , 0x118008094d3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6781" , 0x118008094d3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6782" , 0x118008094d3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6783" , 0x118008094d3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6784" , 0x118008094d400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6785" , 0x118008094d408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6786" , 0x118008094d410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6787" , 0x118008094d418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6788" , 0x118008094d420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6789" , 0x118008094d428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6790" , 0x118008094d430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6791" , 0x118008094d438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6792" , 0x118008094d440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6793" , 0x118008094d448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6794" , 0x118008094d450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6795" , 0x118008094d458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6796" , 0x118008094d460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6797" , 0x118008094d468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6798" , 0x118008094d470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6799" , 0x118008094d478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6800" , 0x118008094d480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6801" , 0x118008094d488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6802" , 0x118008094d490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6803" , 0x118008094d498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6804" , 0x118008094d4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6805" , 0x118008094d4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6806" , 0x118008094d4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6807" , 0x118008094d4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6808" , 0x118008094d4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6809" , 0x118008094d4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6810" , 0x118008094d4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6811" , 0x118008094d4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6812" , 0x118008094d4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6813" , 0x118008094d4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6814" , 0x118008094d4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6815" , 0x118008094d4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6816" , 0x118008094d500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6817" , 0x118008094d508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6818" , 0x118008094d510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6819" , 0x118008094d518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6820" , 0x118008094d520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6821" , 0x118008094d528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6822" , 0x118008094d530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6823" , 0x118008094d538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6824" , 0x118008094d540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6825" , 0x118008094d548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6826" , 0x118008094d550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6827" , 0x118008094d558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6828" , 0x118008094d560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6829" , 0x118008094d568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6830" , 0x118008094d570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6831" , 0x118008094d578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6832" , 0x118008094d580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6833" , 0x118008094d588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6834" , 0x118008094d590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6835" , 0x118008094d598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6836" , 0x118008094d5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6837" , 0x118008094d5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6838" , 0x118008094d5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6839" , 0x118008094d5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6840" , 0x118008094d5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6841" , 0x118008094d5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6842" , 0x118008094d5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6843" , 0x118008094d5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6844" , 0x118008094d5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6845" , 0x118008094d5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6846" , 0x118008094d5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6847" , 0x118008094d5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6848" , 0x118008094d600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6849" , 0x118008094d608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6850" , 0x118008094d610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6851" , 0x118008094d618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6852" , 0x118008094d620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6853" , 0x118008094d628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6854" , 0x118008094d630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6855" , 0x118008094d638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6856" , 0x118008094d640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6857" , 0x118008094d648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6858" , 0x118008094d650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6859" , 0x118008094d658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6860" , 0x118008094d660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6861" , 0x118008094d668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6862" , 0x118008094d670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6863" , 0x118008094d678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6864" , 0x118008094d680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6865" , 0x118008094d688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6866" , 0x118008094d690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6867" , 0x118008094d698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6868" , 0x118008094d6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6869" , 0x118008094d6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6870" , 0x118008094d6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6871" , 0x118008094d6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6872" , 0x118008094d6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6873" , 0x118008094d6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6874" , 0x118008094d6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6875" , 0x118008094d6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6876" , 0x118008094d6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6877" , 0x118008094d6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6878" , 0x118008094d6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6879" , 0x118008094d6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6880" , 0x118008094d700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6881" , 0x118008094d708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6882" , 0x118008094d710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6883" , 0x118008094d718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6884" , 0x118008094d720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6885" , 0x118008094d728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6886" , 0x118008094d730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6887" , 0x118008094d738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6888" , 0x118008094d740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6889" , 0x118008094d748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6890" , 0x118008094d750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6891" , 0x118008094d758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6892" , 0x118008094d760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6893" , 0x118008094d768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6894" , 0x118008094d770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6895" , 0x118008094d778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6896" , 0x118008094d780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6897" , 0x118008094d788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6898" , 0x118008094d790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6899" , 0x118008094d798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6900" , 0x118008094d7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6901" , 0x118008094d7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6902" , 0x118008094d7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6903" , 0x118008094d7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6904" , 0x118008094d7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6905" , 0x118008094d7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6906" , 0x118008094d7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6907" , 0x118008094d7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6908" , 0x118008094d7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6909" , 0x118008094d7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6910" , 0x118008094d7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6911" , 0x118008094d7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6912" , 0x118008094d800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6913" , 0x118008094d808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6914" , 0x118008094d810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6915" , 0x118008094d818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6916" , 0x118008094d820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6917" , 0x118008094d828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6918" , 0x118008094d830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6919" , 0x118008094d838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6920" , 0x118008094d840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6921" , 0x118008094d848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6922" , 0x118008094d850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6923" , 0x118008094d858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6924" , 0x118008094d860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6925" , 0x118008094d868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6926" , 0x118008094d870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6927" , 0x118008094d878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6928" , 0x118008094d880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6929" , 0x118008094d888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6930" , 0x118008094d890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6931" , 0x118008094d898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6932" , 0x118008094d8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6933" , 0x118008094d8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6934" , 0x118008094d8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6935" , 0x118008094d8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6936" , 0x118008094d8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6937" , 0x118008094d8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6938" , 0x118008094d8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6939" , 0x118008094d8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6940" , 0x118008094d8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6941" , 0x118008094d8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6942" , 0x118008094d8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6943" , 0x118008094d8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6944" , 0x118008094d900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6945" , 0x118008094d908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6946" , 0x118008094d910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6947" , 0x118008094d918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6948" , 0x118008094d920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6949" , 0x118008094d928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6950" , 0x118008094d930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6951" , 0x118008094d938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6952" , 0x118008094d940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6953" , 0x118008094d948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6954" , 0x118008094d950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6955" , 0x118008094d958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6956" , 0x118008094d960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6957" , 0x118008094d968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6958" , 0x118008094d970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6959" , 0x118008094d978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6960" , 0x118008094d980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6961" , 0x118008094d988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6962" , 0x118008094d990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6963" , 0x118008094d998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6964" , 0x118008094d9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6965" , 0x118008094d9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6966" , 0x118008094d9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6967" , 0x118008094d9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6968" , 0x118008094d9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6969" , 0x118008094d9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6970" , 0x118008094d9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6971" , 0x118008094d9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6972" , 0x118008094d9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6973" , 0x118008094d9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6974" , 0x118008094d9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6975" , 0x118008094d9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6976" , 0x118008094da00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6977" , 0x118008094da08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6978" , 0x118008094da10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6979" , 0x118008094da18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6980" , 0x118008094da20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6981" , 0x118008094da28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6982" , 0x118008094da30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6983" , 0x118008094da38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6984" , 0x118008094da40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6985" , 0x118008094da48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6986" , 0x118008094da50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6987" , 0x118008094da58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6988" , 0x118008094da60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6989" , 0x118008094da68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6990" , 0x118008094da70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6991" , 0x118008094da78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6992" , 0x118008094da80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6993" , 0x118008094da88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6994" , 0x118008094da90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6995" , 0x118008094da98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6996" , 0x118008094daa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6997" , 0x118008094daa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6998" , 0x118008094dab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP6999" , 0x118008094dab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7000" , 0x118008094dac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7001" , 0x118008094dac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7002" , 0x118008094dad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7003" , 0x118008094dad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7004" , 0x118008094dae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7005" , 0x118008094dae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7006" , 0x118008094daf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7007" , 0x118008094daf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7008" , 0x118008094db00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7009" , 0x118008094db08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7010" , 0x118008094db10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7011" , 0x118008094db18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7012" , 0x118008094db20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7013" , 0x118008094db28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7014" , 0x118008094db30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7015" , 0x118008094db38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7016" , 0x118008094db40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7017" , 0x118008094db48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7018" , 0x118008094db50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7019" , 0x118008094db58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7020" , 0x118008094db60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7021" , 0x118008094db68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7022" , 0x118008094db70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7023" , 0x118008094db78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7024" , 0x118008094db80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7025" , 0x118008094db88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7026" , 0x118008094db90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7027" , 0x118008094db98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7028" , 0x118008094dba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7029" , 0x118008094dba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7030" , 0x118008094dbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7031" , 0x118008094dbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7032" , 0x118008094dbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7033" , 0x118008094dbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7034" , 0x118008094dbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7035" , 0x118008094dbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7036" , 0x118008094dbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7037" , 0x118008094dbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7038" , 0x118008094dbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7039" , 0x118008094dbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7040" , 0x118008094dc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7041" , 0x118008094dc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7042" , 0x118008094dc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7043" , 0x118008094dc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7044" , 0x118008094dc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7045" , 0x118008094dc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7046" , 0x118008094dc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7047" , 0x118008094dc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7048" , 0x118008094dc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7049" , 0x118008094dc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7050" , 0x118008094dc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7051" , 0x118008094dc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7052" , 0x118008094dc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7053" , 0x118008094dc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7054" , 0x118008094dc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7055" , 0x118008094dc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7056" , 0x118008094dc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7057" , 0x118008094dc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7058" , 0x118008094dc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7059" , 0x118008094dc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7060" , 0x118008094dca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7061" , 0x118008094dca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7062" , 0x118008094dcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7063" , 0x118008094dcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7064" , 0x118008094dcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7065" , 0x118008094dcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7066" , 0x118008094dcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7067" , 0x118008094dcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7068" , 0x118008094dce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7069" , 0x118008094dce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7070" , 0x118008094dcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7071" , 0x118008094dcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7072" , 0x118008094dd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7073" , 0x118008094dd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7074" , 0x118008094dd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7075" , 0x118008094dd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7076" , 0x118008094dd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7077" , 0x118008094dd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7078" , 0x118008094dd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7079" , 0x118008094dd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7080" , 0x118008094dd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7081" , 0x118008094dd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7082" , 0x118008094dd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7083" , 0x118008094dd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7084" , 0x118008094dd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7085" , 0x118008094dd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7086" , 0x118008094dd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7087" , 0x118008094dd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7088" , 0x118008094dd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7089" , 0x118008094dd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7090" , 0x118008094dd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7091" , 0x118008094dd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7092" , 0x118008094dda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7093" , 0x118008094dda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7094" , 0x118008094ddb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7095" , 0x118008094ddb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7096" , 0x118008094ddc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7097" , 0x118008094ddc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7098" , 0x118008094ddd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7099" , 0x118008094ddd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7100" , 0x118008094dde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7101" , 0x118008094dde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7102" , 0x118008094ddf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7103" , 0x118008094ddf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7104" , 0x118008094de00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7105" , 0x118008094de08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7106" , 0x118008094de10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7107" , 0x118008094de18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7108" , 0x118008094de20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7109" , 0x118008094de28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7110" , 0x118008094de30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7111" , 0x118008094de38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7112" , 0x118008094de40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7113" , 0x118008094de48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7114" , 0x118008094de50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7115" , 0x118008094de58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7116" , 0x118008094de60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7117" , 0x118008094de68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7118" , 0x118008094de70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7119" , 0x118008094de78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7120" , 0x118008094de80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7121" , 0x118008094de88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7122" , 0x118008094de90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7123" , 0x118008094de98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7124" , 0x118008094dea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7125" , 0x118008094dea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7126" , 0x118008094deb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7127" , 0x118008094deb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7128" , 0x118008094dec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7129" , 0x118008094dec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7130" , 0x118008094ded0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7131" , 0x118008094ded8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7132" , 0x118008094dee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7133" , 0x118008094dee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7134" , 0x118008094def0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7135" , 0x118008094def8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7136" , 0x118008094df00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7137" , 0x118008094df08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7138" , 0x118008094df10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7139" , 0x118008094df18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7140" , 0x118008094df20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7141" , 0x118008094df28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7142" , 0x118008094df30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7143" , 0x118008094df38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7144" , 0x118008094df40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7145" , 0x118008094df48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7146" , 0x118008094df50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7147" , 0x118008094df58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7148" , 0x118008094df60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7149" , 0x118008094df68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7150" , 0x118008094df70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7151" , 0x118008094df78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7152" , 0x118008094df80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7153" , 0x118008094df88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7154" , 0x118008094df90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7155" , 0x118008094df98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7156" , 0x118008094dfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7157" , 0x118008094dfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7158" , 0x118008094dfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7159" , 0x118008094dfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7160" , 0x118008094dfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7161" , 0x118008094dfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7162" , 0x118008094dfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7163" , 0x118008094dfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7164" , 0x118008094dfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7165" , 0x118008094dfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7166" , 0x118008094dff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7167" , 0x118008094dff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7168" , 0x118008094e000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7169" , 0x118008094e008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7170" , 0x118008094e010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7171" , 0x118008094e018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7172" , 0x118008094e020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7173" , 0x118008094e028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7174" , 0x118008094e030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7175" , 0x118008094e038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7176" , 0x118008094e040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7177" , 0x118008094e048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7178" , 0x118008094e050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7179" , 0x118008094e058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7180" , 0x118008094e060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7181" , 0x118008094e068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7182" , 0x118008094e070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7183" , 0x118008094e078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7184" , 0x118008094e080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7185" , 0x118008094e088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7186" , 0x118008094e090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7187" , 0x118008094e098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7188" , 0x118008094e0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7189" , 0x118008094e0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7190" , 0x118008094e0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7191" , 0x118008094e0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7192" , 0x118008094e0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7193" , 0x118008094e0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7194" , 0x118008094e0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7195" , 0x118008094e0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7196" , 0x118008094e0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7197" , 0x118008094e0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7198" , 0x118008094e0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7199" , 0x118008094e0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7200" , 0x118008094e100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7201" , 0x118008094e108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7202" , 0x118008094e110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7203" , 0x118008094e118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7204" , 0x118008094e120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7205" , 0x118008094e128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7206" , 0x118008094e130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7207" , 0x118008094e138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7208" , 0x118008094e140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7209" , 0x118008094e148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7210" , 0x118008094e150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7211" , 0x118008094e158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7212" , 0x118008094e160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7213" , 0x118008094e168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7214" , 0x118008094e170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7215" , 0x118008094e178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7216" , 0x118008094e180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7217" , 0x118008094e188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7218" , 0x118008094e190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7219" , 0x118008094e198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7220" , 0x118008094e1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7221" , 0x118008094e1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7222" , 0x118008094e1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7223" , 0x118008094e1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7224" , 0x118008094e1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7225" , 0x118008094e1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7226" , 0x118008094e1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7227" , 0x118008094e1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7228" , 0x118008094e1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7229" , 0x118008094e1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7230" , 0x118008094e1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7231" , 0x118008094e1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7232" , 0x118008094e200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7233" , 0x118008094e208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7234" , 0x118008094e210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7235" , 0x118008094e218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7236" , 0x118008094e220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7237" , 0x118008094e228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7238" , 0x118008094e230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7239" , 0x118008094e238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7240" , 0x118008094e240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7241" , 0x118008094e248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7242" , 0x118008094e250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7243" , 0x118008094e258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7244" , 0x118008094e260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7245" , 0x118008094e268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7246" , 0x118008094e270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7247" , 0x118008094e278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7248" , 0x118008094e280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7249" , 0x118008094e288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7250" , 0x118008094e290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7251" , 0x118008094e298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7252" , 0x118008094e2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7253" , 0x118008094e2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7254" , 0x118008094e2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7255" , 0x118008094e2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7256" , 0x118008094e2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7257" , 0x118008094e2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7258" , 0x118008094e2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7259" , 0x118008094e2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7260" , 0x118008094e2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7261" , 0x118008094e2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7262" , 0x118008094e2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7263" , 0x118008094e2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7264" , 0x118008094e300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7265" , 0x118008094e308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7266" , 0x118008094e310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7267" , 0x118008094e318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7268" , 0x118008094e320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7269" , 0x118008094e328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7270" , 0x118008094e330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7271" , 0x118008094e338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7272" , 0x118008094e340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7273" , 0x118008094e348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7274" , 0x118008094e350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7275" , 0x118008094e358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7276" , 0x118008094e360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7277" , 0x118008094e368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7278" , 0x118008094e370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7279" , 0x118008094e378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7280" , 0x118008094e380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7281" , 0x118008094e388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7282" , 0x118008094e390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7283" , 0x118008094e398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7284" , 0x118008094e3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7285" , 0x118008094e3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7286" , 0x118008094e3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7287" , 0x118008094e3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7288" , 0x118008094e3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7289" , 0x118008094e3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7290" , 0x118008094e3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7291" , 0x118008094e3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7292" , 0x118008094e3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7293" , 0x118008094e3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7294" , 0x118008094e3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7295" , 0x118008094e3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7296" , 0x118008094e400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7297" , 0x118008094e408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7298" , 0x118008094e410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7299" , 0x118008094e418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7300" , 0x118008094e420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7301" , 0x118008094e428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7302" , 0x118008094e430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7303" , 0x118008094e438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7304" , 0x118008094e440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7305" , 0x118008094e448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7306" , 0x118008094e450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7307" , 0x118008094e458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7308" , 0x118008094e460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7309" , 0x118008094e468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7310" , 0x118008094e470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7311" , 0x118008094e478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7312" , 0x118008094e480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7313" , 0x118008094e488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7314" , 0x118008094e490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7315" , 0x118008094e498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7316" , 0x118008094e4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7317" , 0x118008094e4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7318" , 0x118008094e4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7319" , 0x118008094e4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7320" , 0x118008094e4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7321" , 0x118008094e4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7322" , 0x118008094e4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7323" , 0x118008094e4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7324" , 0x118008094e4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7325" , 0x118008094e4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7326" , 0x118008094e4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7327" , 0x118008094e4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7328" , 0x118008094e500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7329" , 0x118008094e508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7330" , 0x118008094e510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7331" , 0x118008094e518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7332" , 0x118008094e520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7333" , 0x118008094e528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7334" , 0x118008094e530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7335" , 0x118008094e538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7336" , 0x118008094e540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7337" , 0x118008094e548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7338" , 0x118008094e550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7339" , 0x118008094e558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7340" , 0x118008094e560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7341" , 0x118008094e568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7342" , 0x118008094e570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7343" , 0x118008094e578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7344" , 0x118008094e580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7345" , 0x118008094e588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7346" , 0x118008094e590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7347" , 0x118008094e598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7348" , 0x118008094e5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7349" , 0x118008094e5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7350" , 0x118008094e5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7351" , 0x118008094e5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7352" , 0x118008094e5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7353" , 0x118008094e5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7354" , 0x118008094e5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7355" , 0x118008094e5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7356" , 0x118008094e5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7357" , 0x118008094e5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7358" , 0x118008094e5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7359" , 0x118008094e5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7360" , 0x118008094e600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7361" , 0x118008094e608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7362" , 0x118008094e610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7363" , 0x118008094e618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7364" , 0x118008094e620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7365" , 0x118008094e628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7366" , 0x118008094e630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7367" , 0x118008094e638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7368" , 0x118008094e640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7369" , 0x118008094e648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7370" , 0x118008094e650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7371" , 0x118008094e658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7372" , 0x118008094e660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7373" , 0x118008094e668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7374" , 0x118008094e670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7375" , 0x118008094e678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7376" , 0x118008094e680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7377" , 0x118008094e688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7378" , 0x118008094e690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7379" , 0x118008094e698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7380" , 0x118008094e6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7381" , 0x118008094e6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7382" , 0x118008094e6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7383" , 0x118008094e6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7384" , 0x118008094e6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7385" , 0x118008094e6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7386" , 0x118008094e6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7387" , 0x118008094e6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7388" , 0x118008094e6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7389" , 0x118008094e6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7390" , 0x118008094e6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7391" , 0x118008094e6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7392" , 0x118008094e700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7393" , 0x118008094e708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7394" , 0x118008094e710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7395" , 0x118008094e718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7396" , 0x118008094e720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7397" , 0x118008094e728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7398" , 0x118008094e730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7399" , 0x118008094e738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7400" , 0x118008094e740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7401" , 0x118008094e748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7402" , 0x118008094e750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7403" , 0x118008094e758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7404" , 0x118008094e760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7405" , 0x118008094e768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7406" , 0x118008094e770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7407" , 0x118008094e778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7408" , 0x118008094e780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7409" , 0x118008094e788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7410" , 0x118008094e790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7411" , 0x118008094e798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7412" , 0x118008094e7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7413" , 0x118008094e7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7414" , 0x118008094e7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7415" , 0x118008094e7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7416" , 0x118008094e7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7417" , 0x118008094e7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7418" , 0x118008094e7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7419" , 0x118008094e7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7420" , 0x118008094e7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7421" , 0x118008094e7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7422" , 0x118008094e7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7423" , 0x118008094e7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7424" , 0x118008094e800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7425" , 0x118008094e808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7426" , 0x118008094e810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7427" , 0x118008094e818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7428" , 0x118008094e820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7429" , 0x118008094e828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7430" , 0x118008094e830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7431" , 0x118008094e838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7432" , 0x118008094e840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7433" , 0x118008094e848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7434" , 0x118008094e850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7435" , 0x118008094e858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7436" , 0x118008094e860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7437" , 0x118008094e868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7438" , 0x118008094e870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7439" , 0x118008094e878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7440" , 0x118008094e880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7441" , 0x118008094e888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7442" , 0x118008094e890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7443" , 0x118008094e898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7444" , 0x118008094e8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7445" , 0x118008094e8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7446" , 0x118008094e8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7447" , 0x118008094e8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7448" , 0x118008094e8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7449" , 0x118008094e8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7450" , 0x118008094e8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7451" , 0x118008094e8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7452" , 0x118008094e8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7453" , 0x118008094e8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7454" , 0x118008094e8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7455" , 0x118008094e8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7456" , 0x118008094e900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7457" , 0x118008094e908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7458" , 0x118008094e910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7459" , 0x118008094e918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7460" , 0x118008094e920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7461" , 0x118008094e928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7462" , 0x118008094e930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7463" , 0x118008094e938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7464" , 0x118008094e940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7465" , 0x118008094e948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7466" , 0x118008094e950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7467" , 0x118008094e958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7468" , 0x118008094e960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7469" , 0x118008094e968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7470" , 0x118008094e970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7471" , 0x118008094e978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7472" , 0x118008094e980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7473" , 0x118008094e988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7474" , 0x118008094e990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7475" , 0x118008094e998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7476" , 0x118008094e9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7477" , 0x118008094e9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7478" , 0x118008094e9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7479" , 0x118008094e9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7480" , 0x118008094e9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7481" , 0x118008094e9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7482" , 0x118008094e9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7483" , 0x118008094e9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7484" , 0x118008094e9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7485" , 0x118008094e9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7486" , 0x118008094e9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7487" , 0x118008094e9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7488" , 0x118008094ea00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7489" , 0x118008094ea08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7490" , 0x118008094ea10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7491" , 0x118008094ea18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7492" , 0x118008094ea20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7493" , 0x118008094ea28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7494" , 0x118008094ea30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7495" , 0x118008094ea38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7496" , 0x118008094ea40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7497" , 0x118008094ea48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7498" , 0x118008094ea50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7499" , 0x118008094ea58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7500" , 0x118008094ea60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7501" , 0x118008094ea68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7502" , 0x118008094ea70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7503" , 0x118008094ea78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7504" , 0x118008094ea80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7505" , 0x118008094ea88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7506" , 0x118008094ea90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7507" , 0x118008094ea98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7508" , 0x118008094eaa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7509" , 0x118008094eaa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7510" , 0x118008094eab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7511" , 0x118008094eab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7512" , 0x118008094eac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7513" , 0x118008094eac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7514" , 0x118008094ead0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7515" , 0x118008094ead8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7516" , 0x118008094eae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7517" , 0x118008094eae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7518" , 0x118008094eaf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7519" , 0x118008094eaf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7520" , 0x118008094eb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7521" , 0x118008094eb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7522" , 0x118008094eb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7523" , 0x118008094eb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7524" , 0x118008094eb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7525" , 0x118008094eb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7526" , 0x118008094eb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7527" , 0x118008094eb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7528" , 0x118008094eb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7529" , 0x118008094eb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7530" , 0x118008094eb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7531" , 0x118008094eb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7532" , 0x118008094eb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7533" , 0x118008094eb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7534" , 0x118008094eb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7535" , 0x118008094eb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7536" , 0x118008094eb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7537" , 0x118008094eb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7538" , 0x118008094eb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7539" , 0x118008094eb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7540" , 0x118008094eba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7541" , 0x118008094eba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7542" , 0x118008094ebb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7543" , 0x118008094ebb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7544" , 0x118008094ebc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7545" , 0x118008094ebc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7546" , 0x118008094ebd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7547" , 0x118008094ebd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7548" , 0x118008094ebe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7549" , 0x118008094ebe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7550" , 0x118008094ebf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7551" , 0x118008094ebf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7552" , 0x118008094ec00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7553" , 0x118008094ec08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7554" , 0x118008094ec10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7555" , 0x118008094ec18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7556" , 0x118008094ec20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7557" , 0x118008094ec28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7558" , 0x118008094ec30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7559" , 0x118008094ec38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7560" , 0x118008094ec40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7561" , 0x118008094ec48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7562" , 0x118008094ec50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7563" , 0x118008094ec58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7564" , 0x118008094ec60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7565" , 0x118008094ec68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7566" , 0x118008094ec70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7567" , 0x118008094ec78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7568" , 0x118008094ec80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7569" , 0x118008094ec88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7570" , 0x118008094ec90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7571" , 0x118008094ec98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7572" , 0x118008094eca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7573" , 0x118008094eca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7574" , 0x118008094ecb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7575" , 0x118008094ecb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7576" , 0x118008094ecc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7577" , 0x118008094ecc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7578" , 0x118008094ecd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7579" , 0x118008094ecd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7580" , 0x118008094ece0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7581" , 0x118008094ece8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7582" , 0x118008094ecf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7583" , 0x118008094ecf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7584" , 0x118008094ed00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7585" , 0x118008094ed08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7586" , 0x118008094ed10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7587" , 0x118008094ed18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7588" , 0x118008094ed20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7589" , 0x118008094ed28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7590" , 0x118008094ed30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7591" , 0x118008094ed38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7592" , 0x118008094ed40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7593" , 0x118008094ed48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7594" , 0x118008094ed50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7595" , 0x118008094ed58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7596" , 0x118008094ed60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7597" , 0x118008094ed68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7598" , 0x118008094ed70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7599" , 0x118008094ed78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7600" , 0x118008094ed80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7601" , 0x118008094ed88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7602" , 0x118008094ed90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7603" , 0x118008094ed98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7604" , 0x118008094eda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7605" , 0x118008094eda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7606" , 0x118008094edb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7607" , 0x118008094edb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7608" , 0x118008094edc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7609" , 0x118008094edc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7610" , 0x118008094edd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7611" , 0x118008094edd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7612" , 0x118008094ede0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7613" , 0x118008094ede8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7614" , 0x118008094edf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7615" , 0x118008094edf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7616" , 0x118008094ee00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7617" , 0x118008094ee08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7618" , 0x118008094ee10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7619" , 0x118008094ee18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7620" , 0x118008094ee20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7621" , 0x118008094ee28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7622" , 0x118008094ee30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7623" , 0x118008094ee38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7624" , 0x118008094ee40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7625" , 0x118008094ee48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7626" , 0x118008094ee50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7627" , 0x118008094ee58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7628" , 0x118008094ee60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7629" , 0x118008094ee68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7630" , 0x118008094ee70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7631" , 0x118008094ee78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7632" , 0x118008094ee80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7633" , 0x118008094ee88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7634" , 0x118008094ee90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7635" , 0x118008094ee98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7636" , 0x118008094eea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7637" , 0x118008094eea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7638" , 0x118008094eeb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7639" , 0x118008094eeb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7640" , 0x118008094eec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7641" , 0x118008094eec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7642" , 0x118008094eed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7643" , 0x118008094eed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7644" , 0x118008094eee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7645" , 0x118008094eee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7646" , 0x118008094eef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7647" , 0x118008094eef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7648" , 0x118008094ef00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7649" , 0x118008094ef08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7650" , 0x118008094ef10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7651" , 0x118008094ef18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7652" , 0x118008094ef20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7653" , 0x118008094ef28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7654" , 0x118008094ef30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7655" , 0x118008094ef38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7656" , 0x118008094ef40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7657" , 0x118008094ef48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7658" , 0x118008094ef50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7659" , 0x118008094ef58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7660" , 0x118008094ef60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7661" , 0x118008094ef68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7662" , 0x118008094ef70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7663" , 0x118008094ef78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7664" , 0x118008094ef80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7665" , 0x118008094ef88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7666" , 0x118008094ef90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7667" , 0x118008094ef98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7668" , 0x118008094efa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7669" , 0x118008094efa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7670" , 0x118008094efb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7671" , 0x118008094efb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7672" , 0x118008094efc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7673" , 0x118008094efc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7674" , 0x118008094efd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7675" , 0x118008094efd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7676" , 0x118008094efe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7677" , 0x118008094efe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7678" , 0x118008094eff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7679" , 0x118008094eff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7680" , 0x118008094f000ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7681" , 0x118008094f008ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7682" , 0x118008094f010ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7683" , 0x118008094f018ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7684" , 0x118008094f020ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7685" , 0x118008094f028ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7686" , 0x118008094f030ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7687" , 0x118008094f038ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7688" , 0x118008094f040ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7689" , 0x118008094f048ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7690" , 0x118008094f050ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7691" , 0x118008094f058ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7692" , 0x118008094f060ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7693" , 0x118008094f068ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7694" , 0x118008094f070ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7695" , 0x118008094f078ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7696" , 0x118008094f080ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7697" , 0x118008094f088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7698" , 0x118008094f090ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7699" , 0x118008094f098ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7700" , 0x118008094f0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7701" , 0x118008094f0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7702" , 0x118008094f0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7703" , 0x118008094f0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7704" , 0x118008094f0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7705" , 0x118008094f0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7706" , 0x118008094f0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7707" , 0x118008094f0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7708" , 0x118008094f0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7709" , 0x118008094f0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7710" , 0x118008094f0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7711" , 0x118008094f0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7712" , 0x118008094f100ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7713" , 0x118008094f108ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7714" , 0x118008094f110ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7715" , 0x118008094f118ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7716" , 0x118008094f120ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7717" , 0x118008094f128ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7718" , 0x118008094f130ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7719" , 0x118008094f138ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7720" , 0x118008094f140ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7721" , 0x118008094f148ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7722" , 0x118008094f150ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7723" , 0x118008094f158ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7724" , 0x118008094f160ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7725" , 0x118008094f168ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7726" , 0x118008094f170ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7727" , 0x118008094f178ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7728" , 0x118008094f180ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7729" , 0x118008094f188ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7730" , 0x118008094f190ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7731" , 0x118008094f198ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7732" , 0x118008094f1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7733" , 0x118008094f1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7734" , 0x118008094f1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7735" , 0x118008094f1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7736" , 0x118008094f1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7737" , 0x118008094f1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7738" , 0x118008094f1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7739" , 0x118008094f1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7740" , 0x118008094f1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7741" , 0x118008094f1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7742" , 0x118008094f1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7743" , 0x118008094f1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7744" , 0x118008094f200ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7745" , 0x118008094f208ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7746" , 0x118008094f210ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7747" , 0x118008094f218ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7748" , 0x118008094f220ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7749" , 0x118008094f228ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7750" , 0x118008094f230ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7751" , 0x118008094f238ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7752" , 0x118008094f240ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7753" , 0x118008094f248ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7754" , 0x118008094f250ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7755" , 0x118008094f258ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7756" , 0x118008094f260ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7757" , 0x118008094f268ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7758" , 0x118008094f270ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7759" , 0x118008094f278ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7760" , 0x118008094f280ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7761" , 0x118008094f288ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7762" , 0x118008094f290ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7763" , 0x118008094f298ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7764" , 0x118008094f2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7765" , 0x118008094f2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7766" , 0x118008094f2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7767" , 0x118008094f2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7768" , 0x118008094f2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7769" , 0x118008094f2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7770" , 0x118008094f2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7771" , 0x118008094f2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7772" , 0x118008094f2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7773" , 0x118008094f2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7774" , 0x118008094f2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7775" , 0x118008094f2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7776" , 0x118008094f300ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7777" , 0x118008094f308ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7778" , 0x118008094f310ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7779" , 0x118008094f318ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7780" , 0x118008094f320ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7781" , 0x118008094f328ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7782" , 0x118008094f330ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7783" , 0x118008094f338ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7784" , 0x118008094f340ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7785" , 0x118008094f348ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7786" , 0x118008094f350ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7787" , 0x118008094f358ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7788" , 0x118008094f360ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7789" , 0x118008094f368ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7790" , 0x118008094f370ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7791" , 0x118008094f378ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7792" , 0x118008094f380ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7793" , 0x118008094f388ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7794" , 0x118008094f390ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7795" , 0x118008094f398ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7796" , 0x118008094f3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7797" , 0x118008094f3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7798" , 0x118008094f3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7799" , 0x118008094f3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7800" , 0x118008094f3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7801" , 0x118008094f3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7802" , 0x118008094f3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7803" , 0x118008094f3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7804" , 0x118008094f3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7805" , 0x118008094f3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7806" , 0x118008094f3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7807" , 0x118008094f3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7808" , 0x118008094f400ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7809" , 0x118008094f408ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7810" , 0x118008094f410ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7811" , 0x118008094f418ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7812" , 0x118008094f420ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7813" , 0x118008094f428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7814" , 0x118008094f430ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7815" , 0x118008094f438ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7816" , 0x118008094f440ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7817" , 0x118008094f448ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7818" , 0x118008094f450ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7819" , 0x118008094f458ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7820" , 0x118008094f460ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7821" , 0x118008094f468ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7822" , 0x118008094f470ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7823" , 0x118008094f478ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7824" , 0x118008094f480ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7825" , 0x118008094f488ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7826" , 0x118008094f490ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7827" , 0x118008094f498ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7828" , 0x118008094f4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7829" , 0x118008094f4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7830" , 0x118008094f4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7831" , 0x118008094f4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7832" , 0x118008094f4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7833" , 0x118008094f4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7834" , 0x118008094f4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7835" , 0x118008094f4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7836" , 0x118008094f4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7837" , 0x118008094f4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7838" , 0x118008094f4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7839" , 0x118008094f4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7840" , 0x118008094f500ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7841" , 0x118008094f508ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7842" , 0x118008094f510ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7843" , 0x118008094f518ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7844" , 0x118008094f520ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7845" , 0x118008094f528ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7846" , 0x118008094f530ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7847" , 0x118008094f538ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7848" , 0x118008094f540ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7849" , 0x118008094f548ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7850" , 0x118008094f550ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7851" , 0x118008094f558ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7852" , 0x118008094f560ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7853" , 0x118008094f568ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7854" , 0x118008094f570ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7855" , 0x118008094f578ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7856" , 0x118008094f580ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7857" , 0x118008094f588ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7858" , 0x118008094f590ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7859" , 0x118008094f598ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7860" , 0x118008094f5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7861" , 0x118008094f5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7862" , 0x118008094f5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7863" , 0x118008094f5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7864" , 0x118008094f5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7865" , 0x118008094f5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7866" , 0x118008094f5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7867" , 0x118008094f5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7868" , 0x118008094f5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7869" , 0x118008094f5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7870" , 0x118008094f5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7871" , 0x118008094f5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7872" , 0x118008094f600ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7873" , 0x118008094f608ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7874" , 0x118008094f610ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7875" , 0x118008094f618ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7876" , 0x118008094f620ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7877" , 0x118008094f628ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7878" , 0x118008094f630ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7879" , 0x118008094f638ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7880" , 0x118008094f640ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7881" , 0x118008094f648ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7882" , 0x118008094f650ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7883" , 0x118008094f658ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7884" , 0x118008094f660ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7885" , 0x118008094f668ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7886" , 0x118008094f670ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7887" , 0x118008094f678ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7888" , 0x118008094f680ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7889" , 0x118008094f688ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7890" , 0x118008094f690ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7891" , 0x118008094f698ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7892" , 0x118008094f6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7893" , 0x118008094f6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7894" , 0x118008094f6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7895" , 0x118008094f6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7896" , 0x118008094f6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7897" , 0x118008094f6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7898" , 0x118008094f6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7899" , 0x118008094f6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7900" , 0x118008094f6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7901" , 0x118008094f6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7902" , 0x118008094f6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7903" , 0x118008094f6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7904" , 0x118008094f700ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7905" , 0x118008094f708ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7906" , 0x118008094f710ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7907" , 0x118008094f718ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7908" , 0x118008094f720ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7909" , 0x118008094f728ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7910" , 0x118008094f730ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7911" , 0x118008094f738ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7912" , 0x118008094f740ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7913" , 0x118008094f748ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7914" , 0x118008094f750ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7915" , 0x118008094f758ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7916" , 0x118008094f760ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7917" , 0x118008094f768ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7918" , 0x118008094f770ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7919" , 0x118008094f778ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7920" , 0x118008094f780ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7921" , 0x118008094f788ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7922" , 0x118008094f790ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7923" , 0x118008094f798ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7924" , 0x118008094f7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7925" , 0x118008094f7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7926" , 0x118008094f7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7927" , 0x118008094f7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7928" , 0x118008094f7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7929" , 0x118008094f7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7930" , 0x118008094f7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7931" , 0x118008094f7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7932" , 0x118008094f7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7933" , 0x118008094f7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7934" , 0x118008094f7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7935" , 0x118008094f7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7936" , 0x118008094f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7937" , 0x118008094f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7938" , 0x118008094f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7939" , 0x118008094f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7940" , 0x118008094f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7941" , 0x118008094f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7942" , 0x118008094f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7943" , 0x118008094f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7944" , 0x118008094f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7945" , 0x118008094f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7946" , 0x118008094f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7947" , 0x118008094f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7948" , 0x118008094f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7949" , 0x118008094f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7950" , 0x118008094f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7951" , 0x118008094f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7952" , 0x118008094f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7953" , 0x118008094f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7954" , 0x118008094f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7955" , 0x118008094f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7956" , 0x118008094f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7957" , 0x118008094f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7958" , 0x118008094f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7959" , 0x118008094f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7960" , 0x118008094f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7961" , 0x118008094f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7962" , 0x118008094f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7963" , 0x118008094f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7964" , 0x118008094f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7965" , 0x118008094f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7966" , 0x118008094f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7967" , 0x118008094f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7968" , 0x118008094f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7969" , 0x118008094f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7970" , 0x118008094f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7971" , 0x118008094f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7972" , 0x118008094f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7973" , 0x118008094f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7974" , 0x118008094f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7975" , 0x118008094f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7976" , 0x118008094f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7977" , 0x118008094f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7978" , 0x118008094f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7979" , 0x118008094f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7980" , 0x118008094f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7981" , 0x118008094f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7982" , 0x118008094f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7983" , 0x118008094f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7984" , 0x118008094f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7985" , 0x118008094f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7986" , 0x118008094f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7987" , 0x118008094f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7988" , 0x118008094f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7989" , 0x118008094f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7990" , 0x118008094f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7991" , 0x118008094f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7992" , 0x118008094f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7993" , 0x118008094f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7994" , 0x118008094f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7995" , 0x118008094f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7996" , 0x118008094f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7997" , 0x118008094f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7998" , 0x118008094f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP7999" , 0x118008094f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8000" , 0x118008094fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8001" , 0x118008094fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8002" , 0x118008094fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8003" , 0x118008094fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8004" , 0x118008094fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8005" , 0x118008094fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8006" , 0x118008094fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8007" , 0x118008094fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8008" , 0x118008094fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8009" , 0x118008094fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8010" , 0x118008094fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8011" , 0x118008094fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8012" , 0x118008094fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8013" , 0x118008094fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8014" , 0x118008094fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8015" , 0x118008094fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8016" , 0x118008094fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8017" , 0x118008094fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8018" , 0x118008094fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8019" , 0x118008094fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8020" , 0x118008094faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8021" , 0x118008094faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8022" , 0x118008094fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8023" , 0x118008094fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8024" , 0x118008094fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8025" , 0x118008094fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8026" , 0x118008094fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8027" , 0x118008094fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8028" , 0x118008094fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8029" , 0x118008094fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8030" , 0x118008094faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8031" , 0x118008094faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8032" , 0x118008094fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8033" , 0x118008094fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8034" , 0x118008094fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8035" , 0x118008094fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8036" , 0x118008094fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8037" , 0x118008094fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8038" , 0x118008094fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8039" , 0x118008094fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8040" , 0x118008094fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8041" , 0x118008094fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8042" , 0x118008094fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8043" , 0x118008094fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8044" , 0x118008094fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8045" , 0x118008094fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8046" , 0x118008094fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8047" , 0x118008094fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8048" , 0x118008094fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8049" , 0x118008094fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8050" , 0x118008094fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8051" , 0x118008094fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8052" , 0x118008094fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8053" , 0x118008094fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8054" , 0x118008094fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8055" , 0x118008094fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8056" , 0x118008094fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8057" , 0x118008094fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8058" , 0x118008094fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8059" , 0x118008094fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8060" , 0x118008094fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8061" , 0x118008094fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8062" , 0x118008094fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8063" , 0x118008094fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8064" , 0x118008094fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8065" , 0x118008094fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8066" , 0x118008094fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8067" , 0x118008094fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8068" , 0x118008094fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8069" , 0x118008094fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8070" , 0x118008094fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8071" , 0x118008094fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8072" , 0x118008094fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8073" , 0x118008094fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8074" , 0x118008094fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8075" , 0x118008094fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8076" , 0x118008094fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8077" , 0x118008094fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8078" , 0x118008094fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8079" , 0x118008094fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8080" , 0x118008094fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8081" , 0x118008094fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8082" , 0x118008094fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8083" , 0x118008094fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8084" , 0x118008094fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8085" , 0x118008094fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8086" , 0x118008094fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8087" , 0x118008094fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8088" , 0x118008094fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8089" , 0x118008094fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8090" , 0x118008094fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8091" , 0x118008094fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8092" , 0x118008094fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8093" , 0x118008094fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8094" , 0x118008094fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8095" , 0x118008094fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8096" , 0x118008094fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8097" , 0x118008094fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8098" , 0x118008094fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8099" , 0x118008094fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8100" , 0x118008094fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8101" , 0x118008094fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8102" , 0x118008094fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8103" , 0x118008094fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8104" , 0x118008094fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8105" , 0x118008094fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8106" , 0x118008094fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8107" , 0x118008094fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8108" , 0x118008094fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8109" , 0x118008094fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8110" , 0x118008094fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8111" , 0x118008094fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8112" , 0x118008094fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8113" , 0x118008094fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8114" , 0x118008094fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8115" , 0x118008094fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8116" , 0x118008094fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8117" , 0x118008094fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8118" , 0x118008094fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8119" , 0x118008094fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8120" , 0x118008094fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8121" , 0x118008094fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8122" , 0x118008094fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8123" , 0x118008094fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8124" , 0x118008094fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8125" , 0x118008094fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8126" , 0x118008094fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8127" , 0x118008094fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8128" , 0x118008094fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8129" , 0x118008094fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8130" , 0x118008094fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8131" , 0x118008094fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8132" , 0x118008094fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8133" , 0x118008094fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8134" , 0x118008094fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8135" , 0x118008094fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8136" , 0x118008094fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8137" , 0x118008094fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8138" , 0x118008094fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8139" , 0x118008094fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8140" , 0x118008094fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8141" , 0x118008094fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8142" , 0x118008094fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8143" , 0x118008094fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8144" , 0x118008094fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8145" , 0x118008094fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8146" , 0x118008094fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8147" , 0x118008094fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8148" , 0x118008094fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8149" , 0x118008094fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8150" , 0x118008094feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8151" , 0x118008094feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8152" , 0x118008094fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8153" , 0x118008094fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8154" , 0x118008094fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8155" , 0x118008094fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8156" , 0x118008094fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8157" , 0x118008094fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8158" , 0x118008094fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8159" , 0x118008094fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8160" , 0x118008094ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8161" , 0x118008094ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8162" , 0x118008094ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8163" , 0x118008094ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8164" , 0x118008094ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8165" , 0x118008094ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8166" , 0x118008094ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8167" , 0x118008094ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8168" , 0x118008094ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8169" , 0x118008094ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8170" , 0x118008094ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8171" , 0x118008094ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8172" , 0x118008094ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8173" , 0x118008094ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8174" , 0x118008094ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8175" , 0x118008094ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8176" , 0x118008094ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8177" , 0x118008094ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8178" , 0x118008094ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8179" , 0x118008094ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8180" , 0x118008094ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8181" , 0x118008094ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8182" , 0x118008094ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8183" , 0x118008094ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8184" , 0x118008094ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8185" , 0x118008094ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8186" , 0x118008094ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8187" , 0x118008094ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8188" , 0x118008094ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8189" , 0x118008094ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8190" , 0x118008094fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP8191" , 0x118008094fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16128" , 0x118008095f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16129" , 0x118008095f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16130" , 0x118008095f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16131" , 0x118008095f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16132" , 0x118008095f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16133" , 0x118008095f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16134" , 0x118008095f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16135" , 0x118008095f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16136" , 0x118008095f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16137" , 0x118008095f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16138" , 0x118008095f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16139" , 0x118008095f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16140" , 0x118008095f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16141" , 0x118008095f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16142" , 0x118008095f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16143" , 0x118008095f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16144" , 0x118008095f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16145" , 0x118008095f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16146" , 0x118008095f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16147" , 0x118008095f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16148" , 0x118008095f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16149" , 0x118008095f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16150" , 0x118008095f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16151" , 0x118008095f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16152" , 0x118008095f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16153" , 0x118008095f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16154" , 0x118008095f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16155" , 0x118008095f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16156" , 0x118008095f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16157" , 0x118008095f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16158" , 0x118008095f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16159" , 0x118008095f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16160" , 0x118008095f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16161" , 0x118008095f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16162" , 0x118008095f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16163" , 0x118008095f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16164" , 0x118008095f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16165" , 0x118008095f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16166" , 0x118008095f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16167" , 0x118008095f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16168" , 0x118008095f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16169" , 0x118008095f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16170" , 0x118008095f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16171" , 0x118008095f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16172" , 0x118008095f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16173" , 0x118008095f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16174" , 0x118008095f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16175" , 0x118008095f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16176" , 0x118008095f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16177" , 0x118008095f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16178" , 0x118008095f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16179" , 0x118008095f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16180" , 0x118008095f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16181" , 0x118008095f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16182" , 0x118008095f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16183" , 0x118008095f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16184" , 0x118008095f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16185" , 0x118008095f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16186" , 0x118008095f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16187" , 0x118008095f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16188" , 0x118008095f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16189" , 0x118008095f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16190" , 0x118008095f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16191" , 0x118008095f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16192" , 0x118008095fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16193" , 0x118008095fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16194" , 0x118008095fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16195" , 0x118008095fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16196" , 0x118008095fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16197" , 0x118008095fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16198" , 0x118008095fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16199" , 0x118008095fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16200" , 0x118008095fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16201" , 0x118008095fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16202" , 0x118008095fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16203" , 0x118008095fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16204" , 0x118008095fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16205" , 0x118008095fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16206" , 0x118008095fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16207" , 0x118008095fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16208" , 0x118008095fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16209" , 0x118008095fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16210" , 0x118008095fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16211" , 0x118008095fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16212" , 0x118008095faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16213" , 0x118008095faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16214" , 0x118008095fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16215" , 0x118008095fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16216" , 0x118008095fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16217" , 0x118008095fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16218" , 0x118008095fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16219" , 0x118008095fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16220" , 0x118008095fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16221" , 0x118008095fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16222" , 0x118008095faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16223" , 0x118008095faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16224" , 0x118008095fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16225" , 0x118008095fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16226" , 0x118008095fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16227" , 0x118008095fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16228" , 0x118008095fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16229" , 0x118008095fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16230" , 0x118008095fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16231" , 0x118008095fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16232" , 0x118008095fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16233" , 0x118008095fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16234" , 0x118008095fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16235" , 0x118008095fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16236" , 0x118008095fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16237" , 0x118008095fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16238" , 0x118008095fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16239" , 0x118008095fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16240" , 0x118008095fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16241" , 0x118008095fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16242" , 0x118008095fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16243" , 0x118008095fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16244" , 0x118008095fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16245" , 0x118008095fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16246" , 0x118008095fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16247" , 0x118008095fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16248" , 0x118008095fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16249" , 0x118008095fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16250" , 0x118008095fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16251" , 0x118008095fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16252" , 0x118008095fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16253" , 0x118008095fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16254" , 0x118008095fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16255" , 0x118008095fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16256" , 0x118008095fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16257" , 0x118008095fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16258" , 0x118008095fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16259" , 0x118008095fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16260" , 0x118008095fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16261" , 0x118008095fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16262" , 0x118008095fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16263" , 0x118008095fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16264" , 0x118008095fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16265" , 0x118008095fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16266" , 0x118008095fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16267" , 0x118008095fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16268" , 0x118008095fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16269" , 0x118008095fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16270" , 0x118008095fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16271" , 0x118008095fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16272" , 0x118008095fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16273" , 0x118008095fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16274" , 0x118008095fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16275" , 0x118008095fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16276" , 0x118008095fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16277" , 0x118008095fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16278" , 0x118008095fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16279" , 0x118008095fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16280" , 0x118008095fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16281" , 0x118008095fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16282" , 0x118008095fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16283" , 0x118008095fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16284" , 0x118008095fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16285" , 0x118008095fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16286" , 0x118008095fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16287" , 0x118008095fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16288" , 0x118008095fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16289" , 0x118008095fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16290" , 0x118008095fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16291" , 0x118008095fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16292" , 0x118008095fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16293" , 0x118008095fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16294" , 0x118008095fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16295" , 0x118008095fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16296" , 0x118008095fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16297" , 0x118008095fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16298" , 0x118008095fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16299" , 0x118008095fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16300" , 0x118008095fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16301" , 0x118008095fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16302" , 0x118008095fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16303" , 0x118008095fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16304" , 0x118008095fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16305" , 0x118008095fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16306" , 0x118008095fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16307" , 0x118008095fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16308" , 0x118008095fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16309" , 0x118008095fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16310" , 0x118008095fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16311" , 0x118008095fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16312" , 0x118008095fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16313" , 0x118008095fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16314" , 0x118008095fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16315" , 0x118008095fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16316" , 0x118008095fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16317" , 0x118008095fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16318" , 0x118008095fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16319" , 0x118008095fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16320" , 0x118008095fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16321" , 0x118008095fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16322" , 0x118008095fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16323" , 0x118008095fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16324" , 0x118008095fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16325" , 0x118008095fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16326" , 0x118008095fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16327" , 0x118008095fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16328" , 0x118008095fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16329" , 0x118008095fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16330" , 0x118008095fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16331" , 0x118008095fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16332" , 0x118008095fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16333" , 0x118008095fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16334" , 0x118008095fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16335" , 0x118008095fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16336" , 0x118008095fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16337" , 0x118008095fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16338" , 0x118008095fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16339" , 0x118008095fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16340" , 0x118008095fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16341" , 0x118008095fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16342" , 0x118008095feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16343" , 0x118008095feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16344" , 0x118008095fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16345" , 0x118008095fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16346" , 0x118008095fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16347" , 0x118008095fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16348" , 0x118008095fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16349" , 0x118008095fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16350" , 0x118008095fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16351" , 0x118008095fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16352" , 0x118008095ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16353" , 0x118008095ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16354" , 0x118008095ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16355" , 0x118008095ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16356" , 0x118008095ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16357" , 0x118008095ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16358" , 0x118008095ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16359" , 0x118008095ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16360" , 0x118008095ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16361" , 0x118008095ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16362" , 0x118008095ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16363" , 0x118008095ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16364" , 0x118008095ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16365" , 0x118008095ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16366" , 0x118008095ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16367" , 0x118008095ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16368" , 0x118008095ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16369" , 0x118008095ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16370" , 0x118008095ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16371" , 0x118008095ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16372" , 0x118008095ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16373" , 0x118008095ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16374" , 0x118008095ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16375" , 0x118008095ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16376" , 0x118008095ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16377" , 0x118008095ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16378" , 0x118008095ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16379" , 0x118008095ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16380" , 0x118008095ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16381" , 0x118008095ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16382" , 0x118008095fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_COP0_MAP16383" , 0x118008095fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"L2C_CTL" , 0x1180080800000ull, CVMX_CSR_DB_TYPE_RSL, 64, 612},
- {"L2C_DUT_MAP0" , 0x1180080e00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1" , 0x1180080e00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2" , 0x1180080e00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3" , 0x1180080e00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4" , 0x1180080e00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5" , 0x1180080e00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6" , 0x1180080e00030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7" , 0x1180080e00038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8" , 0x1180080e00040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP9" , 0x1180080e00048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP10" , 0x1180080e00050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP11" , 0x1180080e00058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP12" , 0x1180080e00060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP13" , 0x1180080e00068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP14" , 0x1180080e00070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP15" , 0x1180080e00078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP16" , 0x1180080e00080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP17" , 0x1180080e00088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP18" , 0x1180080e00090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP19" , 0x1180080e00098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP20" , 0x1180080e000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP21" , 0x1180080e000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP22" , 0x1180080e000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP23" , 0x1180080e000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP24" , 0x1180080e000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP25" , 0x1180080e000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP26" , 0x1180080e000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP27" , 0x1180080e000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP28" , 0x1180080e000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP29" , 0x1180080e000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP30" , 0x1180080e000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP31" , 0x1180080e000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP32" , 0x1180080e00100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP33" , 0x1180080e00108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP34" , 0x1180080e00110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP35" , 0x1180080e00118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP36" , 0x1180080e00120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP37" , 0x1180080e00128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP38" , 0x1180080e00130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP39" , 0x1180080e00138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP40" , 0x1180080e00140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP41" , 0x1180080e00148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP42" , 0x1180080e00150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP43" , 0x1180080e00158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP44" , 0x1180080e00160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP45" , 0x1180080e00168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP46" , 0x1180080e00170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP47" , 0x1180080e00178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP48" , 0x1180080e00180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP49" , 0x1180080e00188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP50" , 0x1180080e00190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP51" , 0x1180080e00198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP52" , 0x1180080e001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP53" , 0x1180080e001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP54" , 0x1180080e001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP55" , 0x1180080e001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP56" , 0x1180080e001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP57" , 0x1180080e001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP58" , 0x1180080e001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP59" , 0x1180080e001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP60" , 0x1180080e001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP61" , 0x1180080e001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP62" , 0x1180080e001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP63" , 0x1180080e001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP64" , 0x1180080e00200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP65" , 0x1180080e00208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP66" , 0x1180080e00210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP67" , 0x1180080e00218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP68" , 0x1180080e00220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP69" , 0x1180080e00228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP70" , 0x1180080e00230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP71" , 0x1180080e00238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP72" , 0x1180080e00240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP73" , 0x1180080e00248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP74" , 0x1180080e00250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP75" , 0x1180080e00258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP76" , 0x1180080e00260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP77" , 0x1180080e00268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP78" , 0x1180080e00270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP79" , 0x1180080e00278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP80" , 0x1180080e00280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP81" , 0x1180080e00288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP82" , 0x1180080e00290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP83" , 0x1180080e00298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP84" , 0x1180080e002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP85" , 0x1180080e002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP86" , 0x1180080e002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP87" , 0x1180080e002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP88" , 0x1180080e002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP89" , 0x1180080e002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP90" , 0x1180080e002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP91" , 0x1180080e002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP92" , 0x1180080e002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP93" , 0x1180080e002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP94" , 0x1180080e002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP95" , 0x1180080e002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP96" , 0x1180080e00300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP97" , 0x1180080e00308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP98" , 0x1180080e00310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP99" , 0x1180080e00318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP100" , 0x1180080e00320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP101" , 0x1180080e00328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP102" , 0x1180080e00330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP103" , 0x1180080e00338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP104" , 0x1180080e00340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP105" , 0x1180080e00348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP106" , 0x1180080e00350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP107" , 0x1180080e00358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP108" , 0x1180080e00360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP109" , 0x1180080e00368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP110" , 0x1180080e00370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP111" , 0x1180080e00378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP112" , 0x1180080e00380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP113" , 0x1180080e00388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP114" , 0x1180080e00390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP115" , 0x1180080e00398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP116" , 0x1180080e003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP117" , 0x1180080e003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP118" , 0x1180080e003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP119" , 0x1180080e003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP120" , 0x1180080e003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP121" , 0x1180080e003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP122" , 0x1180080e003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP123" , 0x1180080e003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP124" , 0x1180080e003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP125" , 0x1180080e003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP126" , 0x1180080e003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP127" , 0x1180080e003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP128" , 0x1180080e00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP129" , 0x1180080e00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP130" , 0x1180080e00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP131" , 0x1180080e00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP132" , 0x1180080e00420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP133" , 0x1180080e00428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP134" , 0x1180080e00430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP135" , 0x1180080e00438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP136" , 0x1180080e00440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP137" , 0x1180080e00448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP138" , 0x1180080e00450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP139" , 0x1180080e00458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP140" , 0x1180080e00460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP141" , 0x1180080e00468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP142" , 0x1180080e00470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP143" , 0x1180080e00478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP144" , 0x1180080e00480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP145" , 0x1180080e00488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP146" , 0x1180080e00490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP147" , 0x1180080e00498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP148" , 0x1180080e004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP149" , 0x1180080e004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP150" , 0x1180080e004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP151" , 0x1180080e004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP152" , 0x1180080e004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP153" , 0x1180080e004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP154" , 0x1180080e004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP155" , 0x1180080e004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP156" , 0x1180080e004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP157" , 0x1180080e004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP158" , 0x1180080e004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP159" , 0x1180080e004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP160" , 0x1180080e00500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP161" , 0x1180080e00508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP162" , 0x1180080e00510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP163" , 0x1180080e00518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP164" , 0x1180080e00520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP165" , 0x1180080e00528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP166" , 0x1180080e00530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP167" , 0x1180080e00538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP168" , 0x1180080e00540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP169" , 0x1180080e00548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP170" , 0x1180080e00550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP171" , 0x1180080e00558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP172" , 0x1180080e00560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP173" , 0x1180080e00568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP174" , 0x1180080e00570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP175" , 0x1180080e00578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP176" , 0x1180080e00580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP177" , 0x1180080e00588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP178" , 0x1180080e00590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP179" , 0x1180080e00598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP180" , 0x1180080e005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP181" , 0x1180080e005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP182" , 0x1180080e005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP183" , 0x1180080e005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP184" , 0x1180080e005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP185" , 0x1180080e005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP186" , 0x1180080e005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP187" , 0x1180080e005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP188" , 0x1180080e005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP189" , 0x1180080e005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP190" , 0x1180080e005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP191" , 0x1180080e005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP192" , 0x1180080e00600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP193" , 0x1180080e00608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP194" , 0x1180080e00610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP195" , 0x1180080e00618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP196" , 0x1180080e00620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP197" , 0x1180080e00628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP198" , 0x1180080e00630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP199" , 0x1180080e00638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP200" , 0x1180080e00640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP201" , 0x1180080e00648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP202" , 0x1180080e00650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP203" , 0x1180080e00658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP204" , 0x1180080e00660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP205" , 0x1180080e00668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP206" , 0x1180080e00670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP207" , 0x1180080e00678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP208" , 0x1180080e00680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP209" , 0x1180080e00688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP210" , 0x1180080e00690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP211" , 0x1180080e00698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP212" , 0x1180080e006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP213" , 0x1180080e006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP214" , 0x1180080e006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP215" , 0x1180080e006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP216" , 0x1180080e006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP217" , 0x1180080e006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP218" , 0x1180080e006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP219" , 0x1180080e006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP220" , 0x1180080e006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP221" , 0x1180080e006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP222" , 0x1180080e006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP223" , 0x1180080e006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP224" , 0x1180080e00700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP225" , 0x1180080e00708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP226" , 0x1180080e00710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP227" , 0x1180080e00718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP228" , 0x1180080e00720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP229" , 0x1180080e00728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP230" , 0x1180080e00730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP231" , 0x1180080e00738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP232" , 0x1180080e00740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP233" , 0x1180080e00748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP234" , 0x1180080e00750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP235" , 0x1180080e00758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP236" , 0x1180080e00760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP237" , 0x1180080e00768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP238" , 0x1180080e00770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP239" , 0x1180080e00778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP240" , 0x1180080e00780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP241" , 0x1180080e00788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP242" , 0x1180080e00790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP243" , 0x1180080e00798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP244" , 0x1180080e007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP245" , 0x1180080e007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP246" , 0x1180080e007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP247" , 0x1180080e007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP248" , 0x1180080e007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP249" , 0x1180080e007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP250" , 0x1180080e007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP251" , 0x1180080e007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP252" , 0x1180080e007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP253" , 0x1180080e007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP254" , 0x1180080e007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP255" , 0x1180080e007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP256" , 0x1180080e00800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP257" , 0x1180080e00808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP258" , 0x1180080e00810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP259" , 0x1180080e00818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP260" , 0x1180080e00820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP261" , 0x1180080e00828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP262" , 0x1180080e00830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP263" , 0x1180080e00838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP264" , 0x1180080e00840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP265" , 0x1180080e00848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP266" , 0x1180080e00850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP267" , 0x1180080e00858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP268" , 0x1180080e00860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP269" , 0x1180080e00868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP270" , 0x1180080e00870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP271" , 0x1180080e00878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP272" , 0x1180080e00880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP273" , 0x1180080e00888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP274" , 0x1180080e00890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP275" , 0x1180080e00898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP276" , 0x1180080e008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP277" , 0x1180080e008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP278" , 0x1180080e008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP279" , 0x1180080e008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP280" , 0x1180080e008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP281" , 0x1180080e008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP282" , 0x1180080e008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP283" , 0x1180080e008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP284" , 0x1180080e008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP285" , 0x1180080e008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP286" , 0x1180080e008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP287" , 0x1180080e008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP288" , 0x1180080e00900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP289" , 0x1180080e00908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP290" , 0x1180080e00910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP291" , 0x1180080e00918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP292" , 0x1180080e00920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP293" , 0x1180080e00928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP294" , 0x1180080e00930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP295" , 0x1180080e00938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP296" , 0x1180080e00940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP297" , 0x1180080e00948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP298" , 0x1180080e00950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP299" , 0x1180080e00958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP300" , 0x1180080e00960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP301" , 0x1180080e00968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP302" , 0x1180080e00970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP303" , 0x1180080e00978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP304" , 0x1180080e00980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP305" , 0x1180080e00988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP306" , 0x1180080e00990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP307" , 0x1180080e00998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP308" , 0x1180080e009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP309" , 0x1180080e009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP310" , 0x1180080e009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP311" , 0x1180080e009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP312" , 0x1180080e009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP313" , 0x1180080e009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP314" , 0x1180080e009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP315" , 0x1180080e009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP316" , 0x1180080e009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP317" , 0x1180080e009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP318" , 0x1180080e009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP319" , 0x1180080e009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP320" , 0x1180080e00a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP321" , 0x1180080e00a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP322" , 0x1180080e00a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP323" , 0x1180080e00a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP324" , 0x1180080e00a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP325" , 0x1180080e00a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP326" , 0x1180080e00a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP327" , 0x1180080e00a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP328" , 0x1180080e00a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP329" , 0x1180080e00a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP330" , 0x1180080e00a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP331" , 0x1180080e00a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP332" , 0x1180080e00a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP333" , 0x1180080e00a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP334" , 0x1180080e00a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP335" , 0x1180080e00a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP336" , 0x1180080e00a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP337" , 0x1180080e00a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP338" , 0x1180080e00a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP339" , 0x1180080e00a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP340" , 0x1180080e00aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP341" , 0x1180080e00aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP342" , 0x1180080e00ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP343" , 0x1180080e00ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP344" , 0x1180080e00ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP345" , 0x1180080e00ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP346" , 0x1180080e00ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP347" , 0x1180080e00ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP348" , 0x1180080e00ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP349" , 0x1180080e00ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP350" , 0x1180080e00af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP351" , 0x1180080e00af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP352" , 0x1180080e00b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP353" , 0x1180080e00b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP354" , 0x1180080e00b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP355" , 0x1180080e00b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP356" , 0x1180080e00b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP357" , 0x1180080e00b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP358" , 0x1180080e00b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP359" , 0x1180080e00b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP360" , 0x1180080e00b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP361" , 0x1180080e00b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP362" , 0x1180080e00b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP363" , 0x1180080e00b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP364" , 0x1180080e00b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP365" , 0x1180080e00b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP366" , 0x1180080e00b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP367" , 0x1180080e00b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP368" , 0x1180080e00b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP369" , 0x1180080e00b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP370" , 0x1180080e00b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP371" , 0x1180080e00b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP372" , 0x1180080e00ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP373" , 0x1180080e00ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP374" , 0x1180080e00bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP375" , 0x1180080e00bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP376" , 0x1180080e00bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP377" , 0x1180080e00bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP378" , 0x1180080e00bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP379" , 0x1180080e00bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP380" , 0x1180080e00be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP381" , 0x1180080e00be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP382" , 0x1180080e00bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP383" , 0x1180080e00bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP384" , 0x1180080e00c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP385" , 0x1180080e00c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP386" , 0x1180080e00c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP387" , 0x1180080e00c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP388" , 0x1180080e00c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP389" , 0x1180080e00c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP390" , 0x1180080e00c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP391" , 0x1180080e00c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP392" , 0x1180080e00c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP393" , 0x1180080e00c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP394" , 0x1180080e00c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP395" , 0x1180080e00c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP396" , 0x1180080e00c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP397" , 0x1180080e00c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP398" , 0x1180080e00c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP399" , 0x1180080e00c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP400" , 0x1180080e00c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP401" , 0x1180080e00c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP402" , 0x1180080e00c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP403" , 0x1180080e00c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP404" , 0x1180080e00ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP405" , 0x1180080e00ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP406" , 0x1180080e00cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP407" , 0x1180080e00cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP408" , 0x1180080e00cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP409" , 0x1180080e00cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP410" , 0x1180080e00cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP411" , 0x1180080e00cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP412" , 0x1180080e00ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP413" , 0x1180080e00ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP414" , 0x1180080e00cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP415" , 0x1180080e00cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP416" , 0x1180080e00d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP417" , 0x1180080e00d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP418" , 0x1180080e00d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP419" , 0x1180080e00d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP420" , 0x1180080e00d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP421" , 0x1180080e00d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP422" , 0x1180080e00d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP423" , 0x1180080e00d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP424" , 0x1180080e00d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP425" , 0x1180080e00d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP426" , 0x1180080e00d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP427" , 0x1180080e00d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP428" , 0x1180080e00d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP429" , 0x1180080e00d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP430" , 0x1180080e00d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP431" , 0x1180080e00d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP432" , 0x1180080e00d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP433" , 0x1180080e00d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP434" , 0x1180080e00d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP435" , 0x1180080e00d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP436" , 0x1180080e00da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP437" , 0x1180080e00da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP438" , 0x1180080e00db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP439" , 0x1180080e00db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP440" , 0x1180080e00dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP441" , 0x1180080e00dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP442" , 0x1180080e00dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP443" , 0x1180080e00dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP444" , 0x1180080e00de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP445" , 0x1180080e00de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP446" , 0x1180080e00df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP447" , 0x1180080e00df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP448" , 0x1180080e00e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP449" , 0x1180080e00e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP450" , 0x1180080e00e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP451" , 0x1180080e00e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP452" , 0x1180080e00e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP453" , 0x1180080e00e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP454" , 0x1180080e00e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP455" , 0x1180080e00e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP456" , 0x1180080e00e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP457" , 0x1180080e00e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP458" , 0x1180080e00e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP459" , 0x1180080e00e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP460" , 0x1180080e00e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP461" , 0x1180080e00e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP462" , 0x1180080e00e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP463" , 0x1180080e00e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP464" , 0x1180080e00e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP465" , 0x1180080e00e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP466" , 0x1180080e00e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP467" , 0x1180080e00e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP468" , 0x1180080e00ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP469" , 0x1180080e00ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP470" , 0x1180080e00eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP471" , 0x1180080e00eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP472" , 0x1180080e00ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP473" , 0x1180080e00ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP474" , 0x1180080e00ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP475" , 0x1180080e00ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP476" , 0x1180080e00ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP477" , 0x1180080e00ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP478" , 0x1180080e00ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP479" , 0x1180080e00ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP480" , 0x1180080e00f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP481" , 0x1180080e00f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP482" , 0x1180080e00f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP483" , 0x1180080e00f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP484" , 0x1180080e00f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP485" , 0x1180080e00f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP486" , 0x1180080e00f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP487" , 0x1180080e00f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP488" , 0x1180080e00f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP489" , 0x1180080e00f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP490" , 0x1180080e00f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP491" , 0x1180080e00f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP492" , 0x1180080e00f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP493" , 0x1180080e00f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP494" , 0x1180080e00f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP495" , 0x1180080e00f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP496" , 0x1180080e00f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP497" , 0x1180080e00f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP498" , 0x1180080e00f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP499" , 0x1180080e00f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP500" , 0x1180080e00fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP501" , 0x1180080e00fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP502" , 0x1180080e00fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP503" , 0x1180080e00fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP504" , 0x1180080e00fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP505" , 0x1180080e00fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP506" , 0x1180080e00fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP507" , 0x1180080e00fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP508" , 0x1180080e00fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP509" , 0x1180080e00fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP510" , 0x1180080e00ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP511" , 0x1180080e00ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP512" , 0x1180080e01000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP513" , 0x1180080e01008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP514" , 0x1180080e01010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP515" , 0x1180080e01018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP516" , 0x1180080e01020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP517" , 0x1180080e01028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP518" , 0x1180080e01030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP519" , 0x1180080e01038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP520" , 0x1180080e01040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP521" , 0x1180080e01048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP522" , 0x1180080e01050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP523" , 0x1180080e01058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP524" , 0x1180080e01060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP525" , 0x1180080e01068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP526" , 0x1180080e01070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP527" , 0x1180080e01078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP528" , 0x1180080e01080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP529" , 0x1180080e01088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP530" , 0x1180080e01090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP531" , 0x1180080e01098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP532" , 0x1180080e010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP533" , 0x1180080e010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP534" , 0x1180080e010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP535" , 0x1180080e010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP536" , 0x1180080e010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP537" , 0x1180080e010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP538" , 0x1180080e010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP539" , 0x1180080e010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP540" , 0x1180080e010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP541" , 0x1180080e010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP542" , 0x1180080e010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP543" , 0x1180080e010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP544" , 0x1180080e01100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP545" , 0x1180080e01108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP546" , 0x1180080e01110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP547" , 0x1180080e01118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP548" , 0x1180080e01120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP549" , 0x1180080e01128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP550" , 0x1180080e01130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP551" , 0x1180080e01138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP552" , 0x1180080e01140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP553" , 0x1180080e01148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP554" , 0x1180080e01150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP555" , 0x1180080e01158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP556" , 0x1180080e01160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP557" , 0x1180080e01168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP558" , 0x1180080e01170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP559" , 0x1180080e01178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP560" , 0x1180080e01180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP561" , 0x1180080e01188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP562" , 0x1180080e01190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP563" , 0x1180080e01198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP564" , 0x1180080e011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP565" , 0x1180080e011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP566" , 0x1180080e011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP567" , 0x1180080e011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP568" , 0x1180080e011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP569" , 0x1180080e011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP570" , 0x1180080e011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP571" , 0x1180080e011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP572" , 0x1180080e011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP573" , 0x1180080e011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP574" , 0x1180080e011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP575" , 0x1180080e011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP576" , 0x1180080e01200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP577" , 0x1180080e01208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP578" , 0x1180080e01210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP579" , 0x1180080e01218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP580" , 0x1180080e01220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP581" , 0x1180080e01228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP582" , 0x1180080e01230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP583" , 0x1180080e01238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP584" , 0x1180080e01240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP585" , 0x1180080e01248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP586" , 0x1180080e01250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP587" , 0x1180080e01258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP588" , 0x1180080e01260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP589" , 0x1180080e01268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP590" , 0x1180080e01270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP591" , 0x1180080e01278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP592" , 0x1180080e01280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP593" , 0x1180080e01288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP594" , 0x1180080e01290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP595" , 0x1180080e01298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP596" , 0x1180080e012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP597" , 0x1180080e012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP598" , 0x1180080e012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP599" , 0x1180080e012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP600" , 0x1180080e012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP601" , 0x1180080e012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP602" , 0x1180080e012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP603" , 0x1180080e012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP604" , 0x1180080e012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP605" , 0x1180080e012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP606" , 0x1180080e012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP607" , 0x1180080e012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP608" , 0x1180080e01300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP609" , 0x1180080e01308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP610" , 0x1180080e01310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP611" , 0x1180080e01318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP612" , 0x1180080e01320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP613" , 0x1180080e01328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP614" , 0x1180080e01330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP615" , 0x1180080e01338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP616" , 0x1180080e01340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP617" , 0x1180080e01348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP618" , 0x1180080e01350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP619" , 0x1180080e01358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP620" , 0x1180080e01360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP621" , 0x1180080e01368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP622" , 0x1180080e01370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP623" , 0x1180080e01378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP624" , 0x1180080e01380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP625" , 0x1180080e01388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP626" , 0x1180080e01390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP627" , 0x1180080e01398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP628" , 0x1180080e013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP629" , 0x1180080e013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP630" , 0x1180080e013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP631" , 0x1180080e013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP632" , 0x1180080e013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP633" , 0x1180080e013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP634" , 0x1180080e013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP635" , 0x1180080e013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP636" , 0x1180080e013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP637" , 0x1180080e013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP638" , 0x1180080e013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP639" , 0x1180080e013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP640" , 0x1180080e01400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP641" , 0x1180080e01408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP642" , 0x1180080e01410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP643" , 0x1180080e01418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP644" , 0x1180080e01420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP645" , 0x1180080e01428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP646" , 0x1180080e01430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP647" , 0x1180080e01438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP648" , 0x1180080e01440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP649" , 0x1180080e01448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP650" , 0x1180080e01450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP651" , 0x1180080e01458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP652" , 0x1180080e01460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP653" , 0x1180080e01468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP654" , 0x1180080e01470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP655" , 0x1180080e01478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP656" , 0x1180080e01480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP657" , 0x1180080e01488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP658" , 0x1180080e01490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP659" , 0x1180080e01498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP660" , 0x1180080e014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP661" , 0x1180080e014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP662" , 0x1180080e014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP663" , 0x1180080e014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP664" , 0x1180080e014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP665" , 0x1180080e014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP666" , 0x1180080e014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP667" , 0x1180080e014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP668" , 0x1180080e014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP669" , 0x1180080e014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP670" , 0x1180080e014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP671" , 0x1180080e014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP672" , 0x1180080e01500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP673" , 0x1180080e01508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP674" , 0x1180080e01510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP675" , 0x1180080e01518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP676" , 0x1180080e01520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP677" , 0x1180080e01528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP678" , 0x1180080e01530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP679" , 0x1180080e01538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP680" , 0x1180080e01540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP681" , 0x1180080e01548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP682" , 0x1180080e01550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP683" , 0x1180080e01558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP684" , 0x1180080e01560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP685" , 0x1180080e01568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP686" , 0x1180080e01570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP687" , 0x1180080e01578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP688" , 0x1180080e01580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP689" , 0x1180080e01588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP690" , 0x1180080e01590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP691" , 0x1180080e01598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP692" , 0x1180080e015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP693" , 0x1180080e015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP694" , 0x1180080e015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP695" , 0x1180080e015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP696" , 0x1180080e015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP697" , 0x1180080e015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP698" , 0x1180080e015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP699" , 0x1180080e015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP700" , 0x1180080e015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP701" , 0x1180080e015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP702" , 0x1180080e015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP703" , 0x1180080e015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP704" , 0x1180080e01600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP705" , 0x1180080e01608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP706" , 0x1180080e01610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP707" , 0x1180080e01618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP708" , 0x1180080e01620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP709" , 0x1180080e01628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP710" , 0x1180080e01630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP711" , 0x1180080e01638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP712" , 0x1180080e01640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP713" , 0x1180080e01648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP714" , 0x1180080e01650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP715" , 0x1180080e01658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP716" , 0x1180080e01660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP717" , 0x1180080e01668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP718" , 0x1180080e01670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP719" , 0x1180080e01678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP720" , 0x1180080e01680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP721" , 0x1180080e01688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP722" , 0x1180080e01690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP723" , 0x1180080e01698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP724" , 0x1180080e016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP725" , 0x1180080e016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP726" , 0x1180080e016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP727" , 0x1180080e016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP728" , 0x1180080e016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP729" , 0x1180080e016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP730" , 0x1180080e016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP731" , 0x1180080e016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP732" , 0x1180080e016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP733" , 0x1180080e016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP734" , 0x1180080e016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP735" , 0x1180080e016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP736" , 0x1180080e01700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP737" , 0x1180080e01708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP738" , 0x1180080e01710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP739" , 0x1180080e01718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP740" , 0x1180080e01720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP741" , 0x1180080e01728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP742" , 0x1180080e01730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP743" , 0x1180080e01738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP744" , 0x1180080e01740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP745" , 0x1180080e01748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP746" , 0x1180080e01750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP747" , 0x1180080e01758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP748" , 0x1180080e01760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP749" , 0x1180080e01768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP750" , 0x1180080e01770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP751" , 0x1180080e01778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP752" , 0x1180080e01780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP753" , 0x1180080e01788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP754" , 0x1180080e01790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP755" , 0x1180080e01798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP756" , 0x1180080e017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP757" , 0x1180080e017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP758" , 0x1180080e017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP759" , 0x1180080e017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP760" , 0x1180080e017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP761" , 0x1180080e017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP762" , 0x1180080e017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP763" , 0x1180080e017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP764" , 0x1180080e017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP765" , 0x1180080e017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP766" , 0x1180080e017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP767" , 0x1180080e017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP768" , 0x1180080e01800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP769" , 0x1180080e01808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP770" , 0x1180080e01810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP771" , 0x1180080e01818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP772" , 0x1180080e01820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP773" , 0x1180080e01828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP774" , 0x1180080e01830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP775" , 0x1180080e01838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP776" , 0x1180080e01840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP777" , 0x1180080e01848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP778" , 0x1180080e01850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP779" , 0x1180080e01858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP780" , 0x1180080e01860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP781" , 0x1180080e01868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP782" , 0x1180080e01870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP783" , 0x1180080e01878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP784" , 0x1180080e01880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP785" , 0x1180080e01888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP786" , 0x1180080e01890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP787" , 0x1180080e01898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP788" , 0x1180080e018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP789" , 0x1180080e018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP790" , 0x1180080e018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP791" , 0x1180080e018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP792" , 0x1180080e018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP793" , 0x1180080e018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP794" , 0x1180080e018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP795" , 0x1180080e018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP796" , 0x1180080e018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP797" , 0x1180080e018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP798" , 0x1180080e018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP799" , 0x1180080e018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP800" , 0x1180080e01900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP801" , 0x1180080e01908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP802" , 0x1180080e01910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP803" , 0x1180080e01918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP804" , 0x1180080e01920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP805" , 0x1180080e01928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP806" , 0x1180080e01930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP807" , 0x1180080e01938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP808" , 0x1180080e01940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP809" , 0x1180080e01948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP810" , 0x1180080e01950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP811" , 0x1180080e01958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP812" , 0x1180080e01960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP813" , 0x1180080e01968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP814" , 0x1180080e01970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP815" , 0x1180080e01978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP816" , 0x1180080e01980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP817" , 0x1180080e01988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP818" , 0x1180080e01990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP819" , 0x1180080e01998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP820" , 0x1180080e019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP821" , 0x1180080e019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP822" , 0x1180080e019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP823" , 0x1180080e019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP824" , 0x1180080e019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP825" , 0x1180080e019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP826" , 0x1180080e019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP827" , 0x1180080e019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP828" , 0x1180080e019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP829" , 0x1180080e019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP830" , 0x1180080e019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP831" , 0x1180080e019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP832" , 0x1180080e01a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP833" , 0x1180080e01a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP834" , 0x1180080e01a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP835" , 0x1180080e01a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP836" , 0x1180080e01a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP837" , 0x1180080e01a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP838" , 0x1180080e01a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP839" , 0x1180080e01a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP840" , 0x1180080e01a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP841" , 0x1180080e01a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP842" , 0x1180080e01a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP843" , 0x1180080e01a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP844" , 0x1180080e01a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP845" , 0x1180080e01a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP846" , 0x1180080e01a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP847" , 0x1180080e01a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP848" , 0x1180080e01a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP849" , 0x1180080e01a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP850" , 0x1180080e01a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP851" , 0x1180080e01a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP852" , 0x1180080e01aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP853" , 0x1180080e01aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP854" , 0x1180080e01ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP855" , 0x1180080e01ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP856" , 0x1180080e01ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP857" , 0x1180080e01ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP858" , 0x1180080e01ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP859" , 0x1180080e01ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP860" , 0x1180080e01ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP861" , 0x1180080e01ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP862" , 0x1180080e01af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP863" , 0x1180080e01af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP864" , 0x1180080e01b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP865" , 0x1180080e01b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP866" , 0x1180080e01b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP867" , 0x1180080e01b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP868" , 0x1180080e01b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP869" , 0x1180080e01b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP870" , 0x1180080e01b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP871" , 0x1180080e01b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP872" , 0x1180080e01b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP873" , 0x1180080e01b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP874" , 0x1180080e01b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP875" , 0x1180080e01b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP876" , 0x1180080e01b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP877" , 0x1180080e01b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP878" , 0x1180080e01b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP879" , 0x1180080e01b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP880" , 0x1180080e01b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP881" , 0x1180080e01b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP882" , 0x1180080e01b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP883" , 0x1180080e01b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP884" , 0x1180080e01ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP885" , 0x1180080e01ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP886" , 0x1180080e01bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP887" , 0x1180080e01bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP888" , 0x1180080e01bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP889" , 0x1180080e01bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP890" , 0x1180080e01bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP891" , 0x1180080e01bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP892" , 0x1180080e01be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP893" , 0x1180080e01be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP894" , 0x1180080e01bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP895" , 0x1180080e01bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP896" , 0x1180080e01c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP897" , 0x1180080e01c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP898" , 0x1180080e01c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP899" , 0x1180080e01c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP900" , 0x1180080e01c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP901" , 0x1180080e01c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP902" , 0x1180080e01c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP903" , 0x1180080e01c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP904" , 0x1180080e01c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP905" , 0x1180080e01c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP906" , 0x1180080e01c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP907" , 0x1180080e01c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP908" , 0x1180080e01c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP909" , 0x1180080e01c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP910" , 0x1180080e01c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP911" , 0x1180080e01c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP912" , 0x1180080e01c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP913" , 0x1180080e01c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP914" , 0x1180080e01c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP915" , 0x1180080e01c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP916" , 0x1180080e01ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP917" , 0x1180080e01ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP918" , 0x1180080e01cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP919" , 0x1180080e01cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP920" , 0x1180080e01cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP921" , 0x1180080e01cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP922" , 0x1180080e01cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP923" , 0x1180080e01cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP924" , 0x1180080e01ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP925" , 0x1180080e01ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP926" , 0x1180080e01cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP927" , 0x1180080e01cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP928" , 0x1180080e01d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP929" , 0x1180080e01d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP930" , 0x1180080e01d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP931" , 0x1180080e01d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP932" , 0x1180080e01d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP933" , 0x1180080e01d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP934" , 0x1180080e01d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP935" , 0x1180080e01d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP936" , 0x1180080e01d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP937" , 0x1180080e01d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP938" , 0x1180080e01d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP939" , 0x1180080e01d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP940" , 0x1180080e01d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP941" , 0x1180080e01d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP942" , 0x1180080e01d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP943" , 0x1180080e01d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP944" , 0x1180080e01d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP945" , 0x1180080e01d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP946" , 0x1180080e01d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP947" , 0x1180080e01d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP948" , 0x1180080e01da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP949" , 0x1180080e01da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP950" , 0x1180080e01db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP951" , 0x1180080e01db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP952" , 0x1180080e01dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP953" , 0x1180080e01dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP954" , 0x1180080e01dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP955" , 0x1180080e01dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP956" , 0x1180080e01de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP957" , 0x1180080e01de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP958" , 0x1180080e01df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP959" , 0x1180080e01df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP960" , 0x1180080e01e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP961" , 0x1180080e01e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP962" , 0x1180080e01e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP963" , 0x1180080e01e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP964" , 0x1180080e01e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP965" , 0x1180080e01e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP966" , 0x1180080e01e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP967" , 0x1180080e01e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP968" , 0x1180080e01e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP969" , 0x1180080e01e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP970" , 0x1180080e01e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP971" , 0x1180080e01e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP972" , 0x1180080e01e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP973" , 0x1180080e01e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP974" , 0x1180080e01e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP975" , 0x1180080e01e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP976" , 0x1180080e01e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP977" , 0x1180080e01e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP978" , 0x1180080e01e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP979" , 0x1180080e01e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP980" , 0x1180080e01ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP981" , 0x1180080e01ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP982" , 0x1180080e01eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP983" , 0x1180080e01eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP984" , 0x1180080e01ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP985" , 0x1180080e01ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP986" , 0x1180080e01ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP987" , 0x1180080e01ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP988" , 0x1180080e01ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP989" , 0x1180080e01ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP990" , 0x1180080e01ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP991" , 0x1180080e01ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP992" , 0x1180080e01f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP993" , 0x1180080e01f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP994" , 0x1180080e01f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP995" , 0x1180080e01f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP996" , 0x1180080e01f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP997" , 0x1180080e01f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP998" , 0x1180080e01f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP999" , 0x1180080e01f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1000" , 0x1180080e01f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1001" , 0x1180080e01f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1002" , 0x1180080e01f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1003" , 0x1180080e01f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1004" , 0x1180080e01f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1005" , 0x1180080e01f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1006" , 0x1180080e01f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1007" , 0x1180080e01f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1008" , 0x1180080e01f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1009" , 0x1180080e01f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1010" , 0x1180080e01f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1011" , 0x1180080e01f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1012" , 0x1180080e01fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1013" , 0x1180080e01fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1014" , 0x1180080e01fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1015" , 0x1180080e01fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1016" , 0x1180080e01fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1017" , 0x1180080e01fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1018" , 0x1180080e01fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1019" , 0x1180080e01fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1020" , 0x1180080e01fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1021" , 0x1180080e01fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1022" , 0x1180080e01ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1023" , 0x1180080e01ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1024" , 0x1180080e02000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1025" , 0x1180080e02008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1026" , 0x1180080e02010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1027" , 0x1180080e02018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1028" , 0x1180080e02020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1029" , 0x1180080e02028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1030" , 0x1180080e02030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1031" , 0x1180080e02038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1032" , 0x1180080e02040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1033" , 0x1180080e02048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1034" , 0x1180080e02050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1035" , 0x1180080e02058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1036" , 0x1180080e02060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1037" , 0x1180080e02068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1038" , 0x1180080e02070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1039" , 0x1180080e02078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1040" , 0x1180080e02080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1041" , 0x1180080e02088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1042" , 0x1180080e02090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1043" , 0x1180080e02098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1044" , 0x1180080e020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1045" , 0x1180080e020a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1046" , 0x1180080e020b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1047" , 0x1180080e020b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1048" , 0x1180080e020c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1049" , 0x1180080e020c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1050" , 0x1180080e020d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1051" , 0x1180080e020d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1052" , 0x1180080e020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1053" , 0x1180080e020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1054" , 0x1180080e020f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1055" , 0x1180080e020f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1056" , 0x1180080e02100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1057" , 0x1180080e02108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1058" , 0x1180080e02110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1059" , 0x1180080e02118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1060" , 0x1180080e02120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1061" , 0x1180080e02128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1062" , 0x1180080e02130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1063" , 0x1180080e02138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1064" , 0x1180080e02140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1065" , 0x1180080e02148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1066" , 0x1180080e02150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1067" , 0x1180080e02158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1068" , 0x1180080e02160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1069" , 0x1180080e02168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1070" , 0x1180080e02170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1071" , 0x1180080e02178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1072" , 0x1180080e02180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1073" , 0x1180080e02188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1074" , 0x1180080e02190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1075" , 0x1180080e02198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1076" , 0x1180080e021a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1077" , 0x1180080e021a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1078" , 0x1180080e021b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1079" , 0x1180080e021b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1080" , 0x1180080e021c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1081" , 0x1180080e021c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1082" , 0x1180080e021d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1083" , 0x1180080e021d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1084" , 0x1180080e021e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1085" , 0x1180080e021e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1086" , 0x1180080e021f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1087" , 0x1180080e021f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1088" , 0x1180080e02200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1089" , 0x1180080e02208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1090" , 0x1180080e02210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1091" , 0x1180080e02218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1092" , 0x1180080e02220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1093" , 0x1180080e02228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1094" , 0x1180080e02230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1095" , 0x1180080e02238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1096" , 0x1180080e02240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1097" , 0x1180080e02248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1098" , 0x1180080e02250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1099" , 0x1180080e02258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1100" , 0x1180080e02260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1101" , 0x1180080e02268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1102" , 0x1180080e02270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1103" , 0x1180080e02278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1104" , 0x1180080e02280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1105" , 0x1180080e02288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1106" , 0x1180080e02290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1107" , 0x1180080e02298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1108" , 0x1180080e022a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1109" , 0x1180080e022a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1110" , 0x1180080e022b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1111" , 0x1180080e022b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1112" , 0x1180080e022c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1113" , 0x1180080e022c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1114" , 0x1180080e022d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1115" , 0x1180080e022d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1116" , 0x1180080e022e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1117" , 0x1180080e022e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1118" , 0x1180080e022f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1119" , 0x1180080e022f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1120" , 0x1180080e02300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1121" , 0x1180080e02308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1122" , 0x1180080e02310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1123" , 0x1180080e02318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1124" , 0x1180080e02320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1125" , 0x1180080e02328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1126" , 0x1180080e02330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1127" , 0x1180080e02338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1128" , 0x1180080e02340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1129" , 0x1180080e02348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1130" , 0x1180080e02350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1131" , 0x1180080e02358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1132" , 0x1180080e02360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1133" , 0x1180080e02368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1134" , 0x1180080e02370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1135" , 0x1180080e02378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1136" , 0x1180080e02380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1137" , 0x1180080e02388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1138" , 0x1180080e02390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1139" , 0x1180080e02398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1140" , 0x1180080e023a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1141" , 0x1180080e023a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1142" , 0x1180080e023b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1143" , 0x1180080e023b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1144" , 0x1180080e023c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1145" , 0x1180080e023c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1146" , 0x1180080e023d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1147" , 0x1180080e023d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1148" , 0x1180080e023e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1149" , 0x1180080e023e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1150" , 0x1180080e023f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1151" , 0x1180080e023f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1152" , 0x1180080e02400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1153" , 0x1180080e02408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1154" , 0x1180080e02410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1155" , 0x1180080e02418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1156" , 0x1180080e02420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1157" , 0x1180080e02428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1158" , 0x1180080e02430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1159" , 0x1180080e02438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1160" , 0x1180080e02440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1161" , 0x1180080e02448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1162" , 0x1180080e02450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1163" , 0x1180080e02458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1164" , 0x1180080e02460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1165" , 0x1180080e02468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1166" , 0x1180080e02470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1167" , 0x1180080e02478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1168" , 0x1180080e02480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1169" , 0x1180080e02488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1170" , 0x1180080e02490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1171" , 0x1180080e02498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1172" , 0x1180080e024a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1173" , 0x1180080e024a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1174" , 0x1180080e024b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1175" , 0x1180080e024b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1176" , 0x1180080e024c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1177" , 0x1180080e024c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1178" , 0x1180080e024d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1179" , 0x1180080e024d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1180" , 0x1180080e024e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1181" , 0x1180080e024e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1182" , 0x1180080e024f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1183" , 0x1180080e024f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1184" , 0x1180080e02500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1185" , 0x1180080e02508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1186" , 0x1180080e02510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1187" , 0x1180080e02518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1188" , 0x1180080e02520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1189" , 0x1180080e02528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1190" , 0x1180080e02530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1191" , 0x1180080e02538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1192" , 0x1180080e02540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1193" , 0x1180080e02548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1194" , 0x1180080e02550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1195" , 0x1180080e02558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1196" , 0x1180080e02560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1197" , 0x1180080e02568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1198" , 0x1180080e02570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1199" , 0x1180080e02578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1200" , 0x1180080e02580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1201" , 0x1180080e02588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1202" , 0x1180080e02590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1203" , 0x1180080e02598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1204" , 0x1180080e025a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1205" , 0x1180080e025a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1206" , 0x1180080e025b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1207" , 0x1180080e025b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1208" , 0x1180080e025c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1209" , 0x1180080e025c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1210" , 0x1180080e025d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1211" , 0x1180080e025d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1212" , 0x1180080e025e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1213" , 0x1180080e025e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1214" , 0x1180080e025f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1215" , 0x1180080e025f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1216" , 0x1180080e02600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1217" , 0x1180080e02608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1218" , 0x1180080e02610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1219" , 0x1180080e02618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1220" , 0x1180080e02620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1221" , 0x1180080e02628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1222" , 0x1180080e02630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1223" , 0x1180080e02638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1224" , 0x1180080e02640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1225" , 0x1180080e02648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1226" , 0x1180080e02650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1227" , 0x1180080e02658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1228" , 0x1180080e02660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1229" , 0x1180080e02668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1230" , 0x1180080e02670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1231" , 0x1180080e02678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1232" , 0x1180080e02680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1233" , 0x1180080e02688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1234" , 0x1180080e02690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1235" , 0x1180080e02698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1236" , 0x1180080e026a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1237" , 0x1180080e026a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1238" , 0x1180080e026b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1239" , 0x1180080e026b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1240" , 0x1180080e026c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1241" , 0x1180080e026c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1242" , 0x1180080e026d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1243" , 0x1180080e026d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1244" , 0x1180080e026e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1245" , 0x1180080e026e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1246" , 0x1180080e026f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1247" , 0x1180080e026f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1248" , 0x1180080e02700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1249" , 0x1180080e02708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1250" , 0x1180080e02710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1251" , 0x1180080e02718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1252" , 0x1180080e02720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1253" , 0x1180080e02728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1254" , 0x1180080e02730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1255" , 0x1180080e02738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1256" , 0x1180080e02740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1257" , 0x1180080e02748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1258" , 0x1180080e02750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1259" , 0x1180080e02758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1260" , 0x1180080e02760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1261" , 0x1180080e02768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1262" , 0x1180080e02770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1263" , 0x1180080e02778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1264" , 0x1180080e02780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1265" , 0x1180080e02788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1266" , 0x1180080e02790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1267" , 0x1180080e02798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1268" , 0x1180080e027a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1269" , 0x1180080e027a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1270" , 0x1180080e027b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1271" , 0x1180080e027b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1272" , 0x1180080e027c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1273" , 0x1180080e027c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1274" , 0x1180080e027d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1275" , 0x1180080e027d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1276" , 0x1180080e027e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1277" , 0x1180080e027e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1278" , 0x1180080e027f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1279" , 0x1180080e027f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1280" , 0x1180080e02800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1281" , 0x1180080e02808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1282" , 0x1180080e02810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1283" , 0x1180080e02818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1284" , 0x1180080e02820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1285" , 0x1180080e02828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1286" , 0x1180080e02830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1287" , 0x1180080e02838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1288" , 0x1180080e02840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1289" , 0x1180080e02848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1290" , 0x1180080e02850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1291" , 0x1180080e02858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1292" , 0x1180080e02860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1293" , 0x1180080e02868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1294" , 0x1180080e02870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1295" , 0x1180080e02878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1296" , 0x1180080e02880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1297" , 0x1180080e02888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1298" , 0x1180080e02890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1299" , 0x1180080e02898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1300" , 0x1180080e028a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1301" , 0x1180080e028a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1302" , 0x1180080e028b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1303" , 0x1180080e028b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1304" , 0x1180080e028c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1305" , 0x1180080e028c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1306" , 0x1180080e028d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1307" , 0x1180080e028d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1308" , 0x1180080e028e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1309" , 0x1180080e028e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1310" , 0x1180080e028f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1311" , 0x1180080e028f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1312" , 0x1180080e02900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1313" , 0x1180080e02908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1314" , 0x1180080e02910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1315" , 0x1180080e02918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1316" , 0x1180080e02920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1317" , 0x1180080e02928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1318" , 0x1180080e02930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1319" , 0x1180080e02938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1320" , 0x1180080e02940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1321" , 0x1180080e02948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1322" , 0x1180080e02950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1323" , 0x1180080e02958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1324" , 0x1180080e02960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1325" , 0x1180080e02968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1326" , 0x1180080e02970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1327" , 0x1180080e02978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1328" , 0x1180080e02980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1329" , 0x1180080e02988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1330" , 0x1180080e02990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1331" , 0x1180080e02998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1332" , 0x1180080e029a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1333" , 0x1180080e029a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1334" , 0x1180080e029b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1335" , 0x1180080e029b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1336" , 0x1180080e029c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1337" , 0x1180080e029c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1338" , 0x1180080e029d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1339" , 0x1180080e029d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1340" , 0x1180080e029e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1341" , 0x1180080e029e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1342" , 0x1180080e029f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1343" , 0x1180080e029f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1344" , 0x1180080e02a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1345" , 0x1180080e02a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1346" , 0x1180080e02a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1347" , 0x1180080e02a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1348" , 0x1180080e02a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1349" , 0x1180080e02a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1350" , 0x1180080e02a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1351" , 0x1180080e02a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1352" , 0x1180080e02a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1353" , 0x1180080e02a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1354" , 0x1180080e02a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1355" , 0x1180080e02a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1356" , 0x1180080e02a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1357" , 0x1180080e02a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1358" , 0x1180080e02a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1359" , 0x1180080e02a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1360" , 0x1180080e02a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1361" , 0x1180080e02a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1362" , 0x1180080e02a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1363" , 0x1180080e02a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1364" , 0x1180080e02aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1365" , 0x1180080e02aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1366" , 0x1180080e02ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1367" , 0x1180080e02ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1368" , 0x1180080e02ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1369" , 0x1180080e02ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1370" , 0x1180080e02ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1371" , 0x1180080e02ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1372" , 0x1180080e02ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1373" , 0x1180080e02ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1374" , 0x1180080e02af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1375" , 0x1180080e02af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1376" , 0x1180080e02b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1377" , 0x1180080e02b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1378" , 0x1180080e02b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1379" , 0x1180080e02b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1380" , 0x1180080e02b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1381" , 0x1180080e02b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1382" , 0x1180080e02b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1383" , 0x1180080e02b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1384" , 0x1180080e02b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1385" , 0x1180080e02b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1386" , 0x1180080e02b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1387" , 0x1180080e02b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1388" , 0x1180080e02b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1389" , 0x1180080e02b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1390" , 0x1180080e02b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1391" , 0x1180080e02b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1392" , 0x1180080e02b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1393" , 0x1180080e02b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1394" , 0x1180080e02b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1395" , 0x1180080e02b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1396" , 0x1180080e02ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1397" , 0x1180080e02ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1398" , 0x1180080e02bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1399" , 0x1180080e02bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1400" , 0x1180080e02bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1401" , 0x1180080e02bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1402" , 0x1180080e02bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1403" , 0x1180080e02bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1404" , 0x1180080e02be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1405" , 0x1180080e02be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1406" , 0x1180080e02bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1407" , 0x1180080e02bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1408" , 0x1180080e02c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1409" , 0x1180080e02c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1410" , 0x1180080e02c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1411" , 0x1180080e02c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1412" , 0x1180080e02c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1413" , 0x1180080e02c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1414" , 0x1180080e02c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1415" , 0x1180080e02c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1416" , 0x1180080e02c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1417" , 0x1180080e02c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1418" , 0x1180080e02c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1419" , 0x1180080e02c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1420" , 0x1180080e02c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1421" , 0x1180080e02c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1422" , 0x1180080e02c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1423" , 0x1180080e02c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1424" , 0x1180080e02c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1425" , 0x1180080e02c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1426" , 0x1180080e02c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1427" , 0x1180080e02c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1428" , 0x1180080e02ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1429" , 0x1180080e02ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1430" , 0x1180080e02cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1431" , 0x1180080e02cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1432" , 0x1180080e02cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1433" , 0x1180080e02cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1434" , 0x1180080e02cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1435" , 0x1180080e02cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1436" , 0x1180080e02ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1437" , 0x1180080e02ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1438" , 0x1180080e02cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1439" , 0x1180080e02cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1440" , 0x1180080e02d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1441" , 0x1180080e02d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1442" , 0x1180080e02d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1443" , 0x1180080e02d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1444" , 0x1180080e02d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1445" , 0x1180080e02d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1446" , 0x1180080e02d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1447" , 0x1180080e02d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1448" , 0x1180080e02d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1449" , 0x1180080e02d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1450" , 0x1180080e02d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1451" , 0x1180080e02d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1452" , 0x1180080e02d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1453" , 0x1180080e02d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1454" , 0x1180080e02d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1455" , 0x1180080e02d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1456" , 0x1180080e02d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1457" , 0x1180080e02d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1458" , 0x1180080e02d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1459" , 0x1180080e02d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1460" , 0x1180080e02da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1461" , 0x1180080e02da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1462" , 0x1180080e02db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1463" , 0x1180080e02db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1464" , 0x1180080e02dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1465" , 0x1180080e02dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1466" , 0x1180080e02dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1467" , 0x1180080e02dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1468" , 0x1180080e02de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1469" , 0x1180080e02de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1470" , 0x1180080e02df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1471" , 0x1180080e02df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1472" , 0x1180080e02e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1473" , 0x1180080e02e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1474" , 0x1180080e02e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1475" , 0x1180080e02e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1476" , 0x1180080e02e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1477" , 0x1180080e02e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1478" , 0x1180080e02e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1479" , 0x1180080e02e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1480" , 0x1180080e02e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1481" , 0x1180080e02e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1482" , 0x1180080e02e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1483" , 0x1180080e02e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1484" , 0x1180080e02e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1485" , 0x1180080e02e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1486" , 0x1180080e02e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1487" , 0x1180080e02e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1488" , 0x1180080e02e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1489" , 0x1180080e02e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1490" , 0x1180080e02e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1491" , 0x1180080e02e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1492" , 0x1180080e02ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1493" , 0x1180080e02ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1494" , 0x1180080e02eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1495" , 0x1180080e02eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1496" , 0x1180080e02ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1497" , 0x1180080e02ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1498" , 0x1180080e02ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1499" , 0x1180080e02ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1500" , 0x1180080e02ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1501" , 0x1180080e02ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1502" , 0x1180080e02ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1503" , 0x1180080e02ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1504" , 0x1180080e02f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1505" , 0x1180080e02f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1506" , 0x1180080e02f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1507" , 0x1180080e02f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1508" , 0x1180080e02f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1509" , 0x1180080e02f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1510" , 0x1180080e02f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1511" , 0x1180080e02f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1512" , 0x1180080e02f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1513" , 0x1180080e02f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1514" , 0x1180080e02f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1515" , 0x1180080e02f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1516" , 0x1180080e02f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1517" , 0x1180080e02f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1518" , 0x1180080e02f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1519" , 0x1180080e02f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1520" , 0x1180080e02f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1521" , 0x1180080e02f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1522" , 0x1180080e02f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1523" , 0x1180080e02f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1524" , 0x1180080e02fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1525" , 0x1180080e02fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1526" , 0x1180080e02fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1527" , 0x1180080e02fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1528" , 0x1180080e02fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1529" , 0x1180080e02fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1530" , 0x1180080e02fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1531" , 0x1180080e02fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1532" , 0x1180080e02fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1533" , 0x1180080e02fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1534" , 0x1180080e02ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1535" , 0x1180080e02ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1536" , 0x1180080e03000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1537" , 0x1180080e03008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1538" , 0x1180080e03010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1539" , 0x1180080e03018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1540" , 0x1180080e03020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1541" , 0x1180080e03028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1542" , 0x1180080e03030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1543" , 0x1180080e03038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1544" , 0x1180080e03040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1545" , 0x1180080e03048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1546" , 0x1180080e03050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1547" , 0x1180080e03058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1548" , 0x1180080e03060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1549" , 0x1180080e03068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1550" , 0x1180080e03070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1551" , 0x1180080e03078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1552" , 0x1180080e03080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1553" , 0x1180080e03088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1554" , 0x1180080e03090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1555" , 0x1180080e03098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1556" , 0x1180080e030a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1557" , 0x1180080e030a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1558" , 0x1180080e030b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1559" , 0x1180080e030b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1560" , 0x1180080e030c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1561" , 0x1180080e030c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1562" , 0x1180080e030d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1563" , 0x1180080e030d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1564" , 0x1180080e030e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1565" , 0x1180080e030e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1566" , 0x1180080e030f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1567" , 0x1180080e030f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1568" , 0x1180080e03100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1569" , 0x1180080e03108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1570" , 0x1180080e03110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1571" , 0x1180080e03118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1572" , 0x1180080e03120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1573" , 0x1180080e03128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1574" , 0x1180080e03130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1575" , 0x1180080e03138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1576" , 0x1180080e03140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1577" , 0x1180080e03148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1578" , 0x1180080e03150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1579" , 0x1180080e03158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1580" , 0x1180080e03160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1581" , 0x1180080e03168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1582" , 0x1180080e03170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1583" , 0x1180080e03178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1584" , 0x1180080e03180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1585" , 0x1180080e03188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1586" , 0x1180080e03190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1587" , 0x1180080e03198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1588" , 0x1180080e031a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1589" , 0x1180080e031a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1590" , 0x1180080e031b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1591" , 0x1180080e031b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1592" , 0x1180080e031c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1593" , 0x1180080e031c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1594" , 0x1180080e031d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1595" , 0x1180080e031d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1596" , 0x1180080e031e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1597" , 0x1180080e031e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1598" , 0x1180080e031f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1599" , 0x1180080e031f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1600" , 0x1180080e03200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1601" , 0x1180080e03208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1602" , 0x1180080e03210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1603" , 0x1180080e03218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1604" , 0x1180080e03220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1605" , 0x1180080e03228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1606" , 0x1180080e03230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1607" , 0x1180080e03238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1608" , 0x1180080e03240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1609" , 0x1180080e03248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1610" , 0x1180080e03250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1611" , 0x1180080e03258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1612" , 0x1180080e03260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1613" , 0x1180080e03268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1614" , 0x1180080e03270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1615" , 0x1180080e03278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1616" , 0x1180080e03280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1617" , 0x1180080e03288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1618" , 0x1180080e03290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1619" , 0x1180080e03298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1620" , 0x1180080e032a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1621" , 0x1180080e032a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1622" , 0x1180080e032b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1623" , 0x1180080e032b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1624" , 0x1180080e032c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1625" , 0x1180080e032c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1626" , 0x1180080e032d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1627" , 0x1180080e032d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1628" , 0x1180080e032e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1629" , 0x1180080e032e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1630" , 0x1180080e032f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1631" , 0x1180080e032f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1632" , 0x1180080e03300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1633" , 0x1180080e03308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1634" , 0x1180080e03310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1635" , 0x1180080e03318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1636" , 0x1180080e03320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1637" , 0x1180080e03328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1638" , 0x1180080e03330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1639" , 0x1180080e03338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1640" , 0x1180080e03340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1641" , 0x1180080e03348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1642" , 0x1180080e03350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1643" , 0x1180080e03358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1644" , 0x1180080e03360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1645" , 0x1180080e03368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1646" , 0x1180080e03370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1647" , 0x1180080e03378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1648" , 0x1180080e03380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1649" , 0x1180080e03388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1650" , 0x1180080e03390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1651" , 0x1180080e03398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1652" , 0x1180080e033a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1653" , 0x1180080e033a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1654" , 0x1180080e033b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1655" , 0x1180080e033b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1656" , 0x1180080e033c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1657" , 0x1180080e033c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1658" , 0x1180080e033d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1659" , 0x1180080e033d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1660" , 0x1180080e033e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1661" , 0x1180080e033e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1662" , 0x1180080e033f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1663" , 0x1180080e033f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1664" , 0x1180080e03400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1665" , 0x1180080e03408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1666" , 0x1180080e03410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1667" , 0x1180080e03418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1668" , 0x1180080e03420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1669" , 0x1180080e03428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1670" , 0x1180080e03430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1671" , 0x1180080e03438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1672" , 0x1180080e03440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1673" , 0x1180080e03448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1674" , 0x1180080e03450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1675" , 0x1180080e03458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1676" , 0x1180080e03460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1677" , 0x1180080e03468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1678" , 0x1180080e03470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1679" , 0x1180080e03478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1680" , 0x1180080e03480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1681" , 0x1180080e03488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1682" , 0x1180080e03490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1683" , 0x1180080e03498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1684" , 0x1180080e034a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1685" , 0x1180080e034a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1686" , 0x1180080e034b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1687" , 0x1180080e034b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1688" , 0x1180080e034c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1689" , 0x1180080e034c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1690" , 0x1180080e034d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1691" , 0x1180080e034d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1692" , 0x1180080e034e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1693" , 0x1180080e034e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1694" , 0x1180080e034f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1695" , 0x1180080e034f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1696" , 0x1180080e03500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1697" , 0x1180080e03508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1698" , 0x1180080e03510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1699" , 0x1180080e03518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1700" , 0x1180080e03520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1701" , 0x1180080e03528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1702" , 0x1180080e03530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1703" , 0x1180080e03538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1704" , 0x1180080e03540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1705" , 0x1180080e03548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1706" , 0x1180080e03550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1707" , 0x1180080e03558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1708" , 0x1180080e03560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1709" , 0x1180080e03568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1710" , 0x1180080e03570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1711" , 0x1180080e03578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1712" , 0x1180080e03580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1713" , 0x1180080e03588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1714" , 0x1180080e03590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1715" , 0x1180080e03598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1716" , 0x1180080e035a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1717" , 0x1180080e035a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1718" , 0x1180080e035b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1719" , 0x1180080e035b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1720" , 0x1180080e035c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1721" , 0x1180080e035c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1722" , 0x1180080e035d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1723" , 0x1180080e035d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1724" , 0x1180080e035e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1725" , 0x1180080e035e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1726" , 0x1180080e035f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1727" , 0x1180080e035f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1728" , 0x1180080e03600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1729" , 0x1180080e03608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1730" , 0x1180080e03610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1731" , 0x1180080e03618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1732" , 0x1180080e03620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1733" , 0x1180080e03628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1734" , 0x1180080e03630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1735" , 0x1180080e03638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1736" , 0x1180080e03640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1737" , 0x1180080e03648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1738" , 0x1180080e03650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1739" , 0x1180080e03658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1740" , 0x1180080e03660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1741" , 0x1180080e03668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1742" , 0x1180080e03670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1743" , 0x1180080e03678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1744" , 0x1180080e03680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1745" , 0x1180080e03688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1746" , 0x1180080e03690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1747" , 0x1180080e03698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1748" , 0x1180080e036a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1749" , 0x1180080e036a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1750" , 0x1180080e036b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1751" , 0x1180080e036b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1752" , 0x1180080e036c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1753" , 0x1180080e036c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1754" , 0x1180080e036d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1755" , 0x1180080e036d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1756" , 0x1180080e036e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1757" , 0x1180080e036e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1758" , 0x1180080e036f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1759" , 0x1180080e036f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1760" , 0x1180080e03700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1761" , 0x1180080e03708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1762" , 0x1180080e03710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1763" , 0x1180080e03718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1764" , 0x1180080e03720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1765" , 0x1180080e03728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1766" , 0x1180080e03730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1767" , 0x1180080e03738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1768" , 0x1180080e03740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1769" , 0x1180080e03748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1770" , 0x1180080e03750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1771" , 0x1180080e03758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1772" , 0x1180080e03760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1773" , 0x1180080e03768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1774" , 0x1180080e03770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1775" , 0x1180080e03778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1776" , 0x1180080e03780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1777" , 0x1180080e03788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1778" , 0x1180080e03790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1779" , 0x1180080e03798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1780" , 0x1180080e037a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1781" , 0x1180080e037a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1782" , 0x1180080e037b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1783" , 0x1180080e037b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1784" , 0x1180080e037c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1785" , 0x1180080e037c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1786" , 0x1180080e037d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1787" , 0x1180080e037d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1788" , 0x1180080e037e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1789" , 0x1180080e037e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1790" , 0x1180080e037f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1791" , 0x1180080e037f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1792" , 0x1180080e03800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1793" , 0x1180080e03808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1794" , 0x1180080e03810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1795" , 0x1180080e03818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1796" , 0x1180080e03820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1797" , 0x1180080e03828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1798" , 0x1180080e03830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1799" , 0x1180080e03838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1800" , 0x1180080e03840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1801" , 0x1180080e03848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1802" , 0x1180080e03850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1803" , 0x1180080e03858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1804" , 0x1180080e03860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1805" , 0x1180080e03868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1806" , 0x1180080e03870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1807" , 0x1180080e03878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1808" , 0x1180080e03880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1809" , 0x1180080e03888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1810" , 0x1180080e03890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1811" , 0x1180080e03898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1812" , 0x1180080e038a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1813" , 0x1180080e038a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1814" , 0x1180080e038b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1815" , 0x1180080e038b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1816" , 0x1180080e038c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1817" , 0x1180080e038c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1818" , 0x1180080e038d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1819" , 0x1180080e038d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1820" , 0x1180080e038e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1821" , 0x1180080e038e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1822" , 0x1180080e038f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1823" , 0x1180080e038f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1824" , 0x1180080e03900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1825" , 0x1180080e03908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1826" , 0x1180080e03910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1827" , 0x1180080e03918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1828" , 0x1180080e03920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1829" , 0x1180080e03928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1830" , 0x1180080e03930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1831" , 0x1180080e03938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1832" , 0x1180080e03940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1833" , 0x1180080e03948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1834" , 0x1180080e03950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1835" , 0x1180080e03958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1836" , 0x1180080e03960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1837" , 0x1180080e03968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1838" , 0x1180080e03970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1839" , 0x1180080e03978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1840" , 0x1180080e03980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1841" , 0x1180080e03988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1842" , 0x1180080e03990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1843" , 0x1180080e03998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1844" , 0x1180080e039a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1845" , 0x1180080e039a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1846" , 0x1180080e039b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1847" , 0x1180080e039b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1848" , 0x1180080e039c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1849" , 0x1180080e039c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1850" , 0x1180080e039d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1851" , 0x1180080e039d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1852" , 0x1180080e039e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1853" , 0x1180080e039e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1854" , 0x1180080e039f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1855" , 0x1180080e039f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1856" , 0x1180080e03a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1857" , 0x1180080e03a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1858" , 0x1180080e03a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1859" , 0x1180080e03a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1860" , 0x1180080e03a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1861" , 0x1180080e03a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1862" , 0x1180080e03a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1863" , 0x1180080e03a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1864" , 0x1180080e03a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1865" , 0x1180080e03a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1866" , 0x1180080e03a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1867" , 0x1180080e03a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1868" , 0x1180080e03a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1869" , 0x1180080e03a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1870" , 0x1180080e03a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1871" , 0x1180080e03a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1872" , 0x1180080e03a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1873" , 0x1180080e03a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1874" , 0x1180080e03a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1875" , 0x1180080e03a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1876" , 0x1180080e03aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1877" , 0x1180080e03aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1878" , 0x1180080e03ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1879" , 0x1180080e03ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1880" , 0x1180080e03ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1881" , 0x1180080e03ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1882" , 0x1180080e03ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1883" , 0x1180080e03ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1884" , 0x1180080e03ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1885" , 0x1180080e03ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1886" , 0x1180080e03af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1887" , 0x1180080e03af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1888" , 0x1180080e03b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1889" , 0x1180080e03b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1890" , 0x1180080e03b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1891" , 0x1180080e03b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1892" , 0x1180080e03b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1893" , 0x1180080e03b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1894" , 0x1180080e03b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1895" , 0x1180080e03b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1896" , 0x1180080e03b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1897" , 0x1180080e03b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1898" , 0x1180080e03b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1899" , 0x1180080e03b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1900" , 0x1180080e03b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1901" , 0x1180080e03b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1902" , 0x1180080e03b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1903" , 0x1180080e03b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1904" , 0x1180080e03b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1905" , 0x1180080e03b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1906" , 0x1180080e03b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1907" , 0x1180080e03b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1908" , 0x1180080e03ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1909" , 0x1180080e03ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1910" , 0x1180080e03bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1911" , 0x1180080e03bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1912" , 0x1180080e03bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1913" , 0x1180080e03bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1914" , 0x1180080e03bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1915" , 0x1180080e03bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1916" , 0x1180080e03be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1917" , 0x1180080e03be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1918" , 0x1180080e03bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1919" , 0x1180080e03bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1920" , 0x1180080e03c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1921" , 0x1180080e03c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1922" , 0x1180080e03c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1923" , 0x1180080e03c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1924" , 0x1180080e03c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1925" , 0x1180080e03c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1926" , 0x1180080e03c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1927" , 0x1180080e03c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1928" , 0x1180080e03c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1929" , 0x1180080e03c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1930" , 0x1180080e03c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1931" , 0x1180080e03c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1932" , 0x1180080e03c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1933" , 0x1180080e03c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1934" , 0x1180080e03c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1935" , 0x1180080e03c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1936" , 0x1180080e03c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1937" , 0x1180080e03c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1938" , 0x1180080e03c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1939" , 0x1180080e03c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1940" , 0x1180080e03ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1941" , 0x1180080e03ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1942" , 0x1180080e03cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1943" , 0x1180080e03cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1944" , 0x1180080e03cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1945" , 0x1180080e03cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1946" , 0x1180080e03cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1947" , 0x1180080e03cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1948" , 0x1180080e03ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1949" , 0x1180080e03ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1950" , 0x1180080e03cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1951" , 0x1180080e03cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1952" , 0x1180080e03d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1953" , 0x1180080e03d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1954" , 0x1180080e03d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1955" , 0x1180080e03d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1956" , 0x1180080e03d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1957" , 0x1180080e03d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1958" , 0x1180080e03d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1959" , 0x1180080e03d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1960" , 0x1180080e03d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1961" , 0x1180080e03d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1962" , 0x1180080e03d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1963" , 0x1180080e03d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1964" , 0x1180080e03d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1965" , 0x1180080e03d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1966" , 0x1180080e03d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1967" , 0x1180080e03d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1968" , 0x1180080e03d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1969" , 0x1180080e03d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1970" , 0x1180080e03d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1971" , 0x1180080e03d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1972" , 0x1180080e03da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1973" , 0x1180080e03da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1974" , 0x1180080e03db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1975" , 0x1180080e03db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1976" , 0x1180080e03dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1977" , 0x1180080e03dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1978" , 0x1180080e03dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1979" , 0x1180080e03dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1980" , 0x1180080e03de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1981" , 0x1180080e03de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1982" , 0x1180080e03df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1983" , 0x1180080e03df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1984" , 0x1180080e03e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1985" , 0x1180080e03e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1986" , 0x1180080e03e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1987" , 0x1180080e03e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1988" , 0x1180080e03e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1989" , 0x1180080e03e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1990" , 0x1180080e03e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1991" , 0x1180080e03e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1992" , 0x1180080e03e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1993" , 0x1180080e03e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1994" , 0x1180080e03e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1995" , 0x1180080e03e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1996" , 0x1180080e03e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1997" , 0x1180080e03e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1998" , 0x1180080e03e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP1999" , 0x1180080e03e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2000" , 0x1180080e03e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2001" , 0x1180080e03e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2002" , 0x1180080e03e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2003" , 0x1180080e03e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2004" , 0x1180080e03ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2005" , 0x1180080e03ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2006" , 0x1180080e03eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2007" , 0x1180080e03eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2008" , 0x1180080e03ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2009" , 0x1180080e03ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2010" , 0x1180080e03ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2011" , 0x1180080e03ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2012" , 0x1180080e03ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2013" , 0x1180080e03ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2014" , 0x1180080e03ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2015" , 0x1180080e03ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2016" , 0x1180080e03f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2017" , 0x1180080e03f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2018" , 0x1180080e03f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2019" , 0x1180080e03f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2020" , 0x1180080e03f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2021" , 0x1180080e03f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2022" , 0x1180080e03f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2023" , 0x1180080e03f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2024" , 0x1180080e03f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2025" , 0x1180080e03f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2026" , 0x1180080e03f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2027" , 0x1180080e03f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2028" , 0x1180080e03f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2029" , 0x1180080e03f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2030" , 0x1180080e03f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2031" , 0x1180080e03f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2032" , 0x1180080e03f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2033" , 0x1180080e03f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2034" , 0x1180080e03f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2035" , 0x1180080e03f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2036" , 0x1180080e03fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2037" , 0x1180080e03fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2038" , 0x1180080e03fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2039" , 0x1180080e03fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2040" , 0x1180080e03fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2041" , 0x1180080e03fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2042" , 0x1180080e03fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2043" , 0x1180080e03fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2044" , 0x1180080e03fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2045" , 0x1180080e03fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2046" , 0x1180080e03ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2047" , 0x1180080e03ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2048" , 0x1180080e04000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2049" , 0x1180080e04008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2050" , 0x1180080e04010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2051" , 0x1180080e04018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2052" , 0x1180080e04020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2053" , 0x1180080e04028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2054" , 0x1180080e04030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2055" , 0x1180080e04038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2056" , 0x1180080e04040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2057" , 0x1180080e04048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2058" , 0x1180080e04050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2059" , 0x1180080e04058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2060" , 0x1180080e04060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2061" , 0x1180080e04068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2062" , 0x1180080e04070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2063" , 0x1180080e04078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2064" , 0x1180080e04080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2065" , 0x1180080e04088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2066" , 0x1180080e04090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2067" , 0x1180080e04098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2068" , 0x1180080e040a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2069" , 0x1180080e040a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2070" , 0x1180080e040b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2071" , 0x1180080e040b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2072" , 0x1180080e040c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2073" , 0x1180080e040c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2074" , 0x1180080e040d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2075" , 0x1180080e040d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2076" , 0x1180080e040e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2077" , 0x1180080e040e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2078" , 0x1180080e040f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2079" , 0x1180080e040f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2080" , 0x1180080e04100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2081" , 0x1180080e04108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2082" , 0x1180080e04110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2083" , 0x1180080e04118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2084" , 0x1180080e04120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2085" , 0x1180080e04128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2086" , 0x1180080e04130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2087" , 0x1180080e04138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2088" , 0x1180080e04140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2089" , 0x1180080e04148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2090" , 0x1180080e04150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2091" , 0x1180080e04158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2092" , 0x1180080e04160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2093" , 0x1180080e04168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2094" , 0x1180080e04170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2095" , 0x1180080e04178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2096" , 0x1180080e04180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2097" , 0x1180080e04188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2098" , 0x1180080e04190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2099" , 0x1180080e04198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2100" , 0x1180080e041a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2101" , 0x1180080e041a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2102" , 0x1180080e041b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2103" , 0x1180080e041b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2104" , 0x1180080e041c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2105" , 0x1180080e041c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2106" , 0x1180080e041d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2107" , 0x1180080e041d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2108" , 0x1180080e041e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2109" , 0x1180080e041e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2110" , 0x1180080e041f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2111" , 0x1180080e041f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2112" , 0x1180080e04200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2113" , 0x1180080e04208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2114" , 0x1180080e04210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2115" , 0x1180080e04218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2116" , 0x1180080e04220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2117" , 0x1180080e04228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2118" , 0x1180080e04230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2119" , 0x1180080e04238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2120" , 0x1180080e04240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2121" , 0x1180080e04248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2122" , 0x1180080e04250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2123" , 0x1180080e04258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2124" , 0x1180080e04260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2125" , 0x1180080e04268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2126" , 0x1180080e04270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2127" , 0x1180080e04278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2128" , 0x1180080e04280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2129" , 0x1180080e04288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2130" , 0x1180080e04290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2131" , 0x1180080e04298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2132" , 0x1180080e042a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2133" , 0x1180080e042a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2134" , 0x1180080e042b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2135" , 0x1180080e042b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2136" , 0x1180080e042c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2137" , 0x1180080e042c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2138" , 0x1180080e042d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2139" , 0x1180080e042d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2140" , 0x1180080e042e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2141" , 0x1180080e042e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2142" , 0x1180080e042f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2143" , 0x1180080e042f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2144" , 0x1180080e04300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2145" , 0x1180080e04308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2146" , 0x1180080e04310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2147" , 0x1180080e04318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2148" , 0x1180080e04320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2149" , 0x1180080e04328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2150" , 0x1180080e04330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2151" , 0x1180080e04338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2152" , 0x1180080e04340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2153" , 0x1180080e04348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2154" , 0x1180080e04350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2155" , 0x1180080e04358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2156" , 0x1180080e04360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2157" , 0x1180080e04368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2158" , 0x1180080e04370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2159" , 0x1180080e04378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2160" , 0x1180080e04380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2161" , 0x1180080e04388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2162" , 0x1180080e04390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2163" , 0x1180080e04398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2164" , 0x1180080e043a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2165" , 0x1180080e043a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2166" , 0x1180080e043b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2167" , 0x1180080e043b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2168" , 0x1180080e043c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2169" , 0x1180080e043c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2170" , 0x1180080e043d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2171" , 0x1180080e043d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2172" , 0x1180080e043e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2173" , 0x1180080e043e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2174" , 0x1180080e043f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2175" , 0x1180080e043f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2176" , 0x1180080e04400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2177" , 0x1180080e04408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2178" , 0x1180080e04410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2179" , 0x1180080e04418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2180" , 0x1180080e04420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2181" , 0x1180080e04428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2182" , 0x1180080e04430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2183" , 0x1180080e04438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2184" , 0x1180080e04440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2185" , 0x1180080e04448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2186" , 0x1180080e04450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2187" , 0x1180080e04458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2188" , 0x1180080e04460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2189" , 0x1180080e04468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2190" , 0x1180080e04470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2191" , 0x1180080e04478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2192" , 0x1180080e04480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2193" , 0x1180080e04488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2194" , 0x1180080e04490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2195" , 0x1180080e04498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2196" , 0x1180080e044a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2197" , 0x1180080e044a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2198" , 0x1180080e044b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2199" , 0x1180080e044b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2200" , 0x1180080e044c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2201" , 0x1180080e044c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2202" , 0x1180080e044d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2203" , 0x1180080e044d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2204" , 0x1180080e044e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2205" , 0x1180080e044e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2206" , 0x1180080e044f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2207" , 0x1180080e044f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2208" , 0x1180080e04500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2209" , 0x1180080e04508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2210" , 0x1180080e04510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2211" , 0x1180080e04518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2212" , 0x1180080e04520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2213" , 0x1180080e04528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2214" , 0x1180080e04530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2215" , 0x1180080e04538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2216" , 0x1180080e04540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2217" , 0x1180080e04548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2218" , 0x1180080e04550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2219" , 0x1180080e04558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2220" , 0x1180080e04560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2221" , 0x1180080e04568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2222" , 0x1180080e04570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2223" , 0x1180080e04578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2224" , 0x1180080e04580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2225" , 0x1180080e04588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2226" , 0x1180080e04590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2227" , 0x1180080e04598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2228" , 0x1180080e045a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2229" , 0x1180080e045a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2230" , 0x1180080e045b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2231" , 0x1180080e045b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2232" , 0x1180080e045c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2233" , 0x1180080e045c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2234" , 0x1180080e045d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2235" , 0x1180080e045d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2236" , 0x1180080e045e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2237" , 0x1180080e045e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2238" , 0x1180080e045f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2239" , 0x1180080e045f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2240" , 0x1180080e04600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2241" , 0x1180080e04608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2242" , 0x1180080e04610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2243" , 0x1180080e04618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2244" , 0x1180080e04620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2245" , 0x1180080e04628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2246" , 0x1180080e04630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2247" , 0x1180080e04638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2248" , 0x1180080e04640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2249" , 0x1180080e04648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2250" , 0x1180080e04650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2251" , 0x1180080e04658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2252" , 0x1180080e04660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2253" , 0x1180080e04668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2254" , 0x1180080e04670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2255" , 0x1180080e04678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2256" , 0x1180080e04680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2257" , 0x1180080e04688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2258" , 0x1180080e04690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2259" , 0x1180080e04698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2260" , 0x1180080e046a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2261" , 0x1180080e046a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2262" , 0x1180080e046b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2263" , 0x1180080e046b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2264" , 0x1180080e046c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2265" , 0x1180080e046c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2266" , 0x1180080e046d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2267" , 0x1180080e046d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2268" , 0x1180080e046e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2269" , 0x1180080e046e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2270" , 0x1180080e046f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2271" , 0x1180080e046f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2272" , 0x1180080e04700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2273" , 0x1180080e04708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2274" , 0x1180080e04710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2275" , 0x1180080e04718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2276" , 0x1180080e04720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2277" , 0x1180080e04728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2278" , 0x1180080e04730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2279" , 0x1180080e04738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2280" , 0x1180080e04740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2281" , 0x1180080e04748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2282" , 0x1180080e04750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2283" , 0x1180080e04758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2284" , 0x1180080e04760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2285" , 0x1180080e04768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2286" , 0x1180080e04770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2287" , 0x1180080e04778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2288" , 0x1180080e04780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2289" , 0x1180080e04788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2290" , 0x1180080e04790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2291" , 0x1180080e04798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2292" , 0x1180080e047a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2293" , 0x1180080e047a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2294" , 0x1180080e047b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2295" , 0x1180080e047b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2296" , 0x1180080e047c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2297" , 0x1180080e047c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2298" , 0x1180080e047d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2299" , 0x1180080e047d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2300" , 0x1180080e047e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2301" , 0x1180080e047e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2302" , 0x1180080e047f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2303" , 0x1180080e047f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2304" , 0x1180080e04800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2305" , 0x1180080e04808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2306" , 0x1180080e04810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2307" , 0x1180080e04818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2308" , 0x1180080e04820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2309" , 0x1180080e04828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2310" , 0x1180080e04830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2311" , 0x1180080e04838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2312" , 0x1180080e04840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2313" , 0x1180080e04848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2314" , 0x1180080e04850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2315" , 0x1180080e04858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2316" , 0x1180080e04860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2317" , 0x1180080e04868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2318" , 0x1180080e04870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2319" , 0x1180080e04878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2320" , 0x1180080e04880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2321" , 0x1180080e04888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2322" , 0x1180080e04890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2323" , 0x1180080e04898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2324" , 0x1180080e048a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2325" , 0x1180080e048a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2326" , 0x1180080e048b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2327" , 0x1180080e048b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2328" , 0x1180080e048c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2329" , 0x1180080e048c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2330" , 0x1180080e048d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2331" , 0x1180080e048d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2332" , 0x1180080e048e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2333" , 0x1180080e048e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2334" , 0x1180080e048f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2335" , 0x1180080e048f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2336" , 0x1180080e04900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2337" , 0x1180080e04908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2338" , 0x1180080e04910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2339" , 0x1180080e04918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2340" , 0x1180080e04920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2341" , 0x1180080e04928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2342" , 0x1180080e04930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2343" , 0x1180080e04938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2344" , 0x1180080e04940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2345" , 0x1180080e04948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2346" , 0x1180080e04950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2347" , 0x1180080e04958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2348" , 0x1180080e04960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2349" , 0x1180080e04968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2350" , 0x1180080e04970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2351" , 0x1180080e04978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2352" , 0x1180080e04980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2353" , 0x1180080e04988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2354" , 0x1180080e04990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2355" , 0x1180080e04998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2356" , 0x1180080e049a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2357" , 0x1180080e049a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2358" , 0x1180080e049b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2359" , 0x1180080e049b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2360" , 0x1180080e049c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2361" , 0x1180080e049c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2362" , 0x1180080e049d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2363" , 0x1180080e049d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2364" , 0x1180080e049e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2365" , 0x1180080e049e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2366" , 0x1180080e049f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2367" , 0x1180080e049f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2368" , 0x1180080e04a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2369" , 0x1180080e04a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2370" , 0x1180080e04a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2371" , 0x1180080e04a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2372" , 0x1180080e04a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2373" , 0x1180080e04a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2374" , 0x1180080e04a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2375" , 0x1180080e04a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2376" , 0x1180080e04a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2377" , 0x1180080e04a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2378" , 0x1180080e04a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2379" , 0x1180080e04a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2380" , 0x1180080e04a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2381" , 0x1180080e04a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2382" , 0x1180080e04a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2383" , 0x1180080e04a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2384" , 0x1180080e04a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2385" , 0x1180080e04a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2386" , 0x1180080e04a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2387" , 0x1180080e04a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2388" , 0x1180080e04aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2389" , 0x1180080e04aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2390" , 0x1180080e04ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2391" , 0x1180080e04ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2392" , 0x1180080e04ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2393" , 0x1180080e04ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2394" , 0x1180080e04ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2395" , 0x1180080e04ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2396" , 0x1180080e04ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2397" , 0x1180080e04ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2398" , 0x1180080e04af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2399" , 0x1180080e04af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2400" , 0x1180080e04b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2401" , 0x1180080e04b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2402" , 0x1180080e04b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2403" , 0x1180080e04b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2404" , 0x1180080e04b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2405" , 0x1180080e04b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2406" , 0x1180080e04b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2407" , 0x1180080e04b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2408" , 0x1180080e04b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2409" , 0x1180080e04b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2410" , 0x1180080e04b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2411" , 0x1180080e04b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2412" , 0x1180080e04b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2413" , 0x1180080e04b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2414" , 0x1180080e04b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2415" , 0x1180080e04b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2416" , 0x1180080e04b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2417" , 0x1180080e04b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2418" , 0x1180080e04b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2419" , 0x1180080e04b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2420" , 0x1180080e04ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2421" , 0x1180080e04ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2422" , 0x1180080e04bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2423" , 0x1180080e04bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2424" , 0x1180080e04bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2425" , 0x1180080e04bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2426" , 0x1180080e04bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2427" , 0x1180080e04bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2428" , 0x1180080e04be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2429" , 0x1180080e04be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2430" , 0x1180080e04bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2431" , 0x1180080e04bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2432" , 0x1180080e04c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2433" , 0x1180080e04c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2434" , 0x1180080e04c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2435" , 0x1180080e04c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2436" , 0x1180080e04c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2437" , 0x1180080e04c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2438" , 0x1180080e04c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2439" , 0x1180080e04c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2440" , 0x1180080e04c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2441" , 0x1180080e04c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2442" , 0x1180080e04c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2443" , 0x1180080e04c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2444" , 0x1180080e04c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2445" , 0x1180080e04c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2446" , 0x1180080e04c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2447" , 0x1180080e04c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2448" , 0x1180080e04c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2449" , 0x1180080e04c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2450" , 0x1180080e04c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2451" , 0x1180080e04c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2452" , 0x1180080e04ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2453" , 0x1180080e04ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2454" , 0x1180080e04cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2455" , 0x1180080e04cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2456" , 0x1180080e04cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2457" , 0x1180080e04cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2458" , 0x1180080e04cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2459" , 0x1180080e04cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2460" , 0x1180080e04ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2461" , 0x1180080e04ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2462" , 0x1180080e04cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2463" , 0x1180080e04cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2464" , 0x1180080e04d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2465" , 0x1180080e04d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2466" , 0x1180080e04d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2467" , 0x1180080e04d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2468" , 0x1180080e04d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2469" , 0x1180080e04d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2470" , 0x1180080e04d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2471" , 0x1180080e04d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2472" , 0x1180080e04d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2473" , 0x1180080e04d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2474" , 0x1180080e04d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2475" , 0x1180080e04d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2476" , 0x1180080e04d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2477" , 0x1180080e04d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2478" , 0x1180080e04d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2479" , 0x1180080e04d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2480" , 0x1180080e04d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2481" , 0x1180080e04d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2482" , 0x1180080e04d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2483" , 0x1180080e04d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2484" , 0x1180080e04da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2485" , 0x1180080e04da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2486" , 0x1180080e04db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2487" , 0x1180080e04db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2488" , 0x1180080e04dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2489" , 0x1180080e04dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2490" , 0x1180080e04dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2491" , 0x1180080e04dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2492" , 0x1180080e04de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2493" , 0x1180080e04de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2494" , 0x1180080e04df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2495" , 0x1180080e04df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2496" , 0x1180080e04e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2497" , 0x1180080e04e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2498" , 0x1180080e04e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2499" , 0x1180080e04e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2500" , 0x1180080e04e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2501" , 0x1180080e04e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2502" , 0x1180080e04e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2503" , 0x1180080e04e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2504" , 0x1180080e04e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2505" , 0x1180080e04e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2506" , 0x1180080e04e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2507" , 0x1180080e04e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2508" , 0x1180080e04e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2509" , 0x1180080e04e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2510" , 0x1180080e04e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2511" , 0x1180080e04e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2512" , 0x1180080e04e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2513" , 0x1180080e04e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2514" , 0x1180080e04e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2515" , 0x1180080e04e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2516" , 0x1180080e04ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2517" , 0x1180080e04ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2518" , 0x1180080e04eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2519" , 0x1180080e04eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2520" , 0x1180080e04ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2521" , 0x1180080e04ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2522" , 0x1180080e04ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2523" , 0x1180080e04ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2524" , 0x1180080e04ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2525" , 0x1180080e04ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2526" , 0x1180080e04ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2527" , 0x1180080e04ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2528" , 0x1180080e04f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2529" , 0x1180080e04f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2530" , 0x1180080e04f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2531" , 0x1180080e04f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2532" , 0x1180080e04f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2533" , 0x1180080e04f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2534" , 0x1180080e04f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2535" , 0x1180080e04f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2536" , 0x1180080e04f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2537" , 0x1180080e04f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2538" , 0x1180080e04f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2539" , 0x1180080e04f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2540" , 0x1180080e04f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2541" , 0x1180080e04f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2542" , 0x1180080e04f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2543" , 0x1180080e04f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2544" , 0x1180080e04f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2545" , 0x1180080e04f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2546" , 0x1180080e04f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2547" , 0x1180080e04f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2548" , 0x1180080e04fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2549" , 0x1180080e04fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2550" , 0x1180080e04fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2551" , 0x1180080e04fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2552" , 0x1180080e04fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2553" , 0x1180080e04fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2554" , 0x1180080e04fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2555" , 0x1180080e04fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2556" , 0x1180080e04fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2557" , 0x1180080e04fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2558" , 0x1180080e04ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2559" , 0x1180080e04ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2560" , 0x1180080e05000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2561" , 0x1180080e05008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2562" , 0x1180080e05010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2563" , 0x1180080e05018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2564" , 0x1180080e05020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2565" , 0x1180080e05028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2566" , 0x1180080e05030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2567" , 0x1180080e05038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2568" , 0x1180080e05040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2569" , 0x1180080e05048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2570" , 0x1180080e05050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2571" , 0x1180080e05058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2572" , 0x1180080e05060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2573" , 0x1180080e05068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2574" , 0x1180080e05070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2575" , 0x1180080e05078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2576" , 0x1180080e05080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2577" , 0x1180080e05088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2578" , 0x1180080e05090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2579" , 0x1180080e05098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2580" , 0x1180080e050a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2581" , 0x1180080e050a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2582" , 0x1180080e050b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2583" , 0x1180080e050b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2584" , 0x1180080e050c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2585" , 0x1180080e050c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2586" , 0x1180080e050d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2587" , 0x1180080e050d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2588" , 0x1180080e050e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2589" , 0x1180080e050e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2590" , 0x1180080e050f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2591" , 0x1180080e050f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2592" , 0x1180080e05100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2593" , 0x1180080e05108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2594" , 0x1180080e05110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2595" , 0x1180080e05118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2596" , 0x1180080e05120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2597" , 0x1180080e05128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2598" , 0x1180080e05130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2599" , 0x1180080e05138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2600" , 0x1180080e05140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2601" , 0x1180080e05148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2602" , 0x1180080e05150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2603" , 0x1180080e05158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2604" , 0x1180080e05160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2605" , 0x1180080e05168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2606" , 0x1180080e05170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2607" , 0x1180080e05178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2608" , 0x1180080e05180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2609" , 0x1180080e05188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2610" , 0x1180080e05190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2611" , 0x1180080e05198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2612" , 0x1180080e051a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2613" , 0x1180080e051a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2614" , 0x1180080e051b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2615" , 0x1180080e051b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2616" , 0x1180080e051c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2617" , 0x1180080e051c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2618" , 0x1180080e051d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2619" , 0x1180080e051d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2620" , 0x1180080e051e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2621" , 0x1180080e051e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2622" , 0x1180080e051f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2623" , 0x1180080e051f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2624" , 0x1180080e05200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2625" , 0x1180080e05208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2626" , 0x1180080e05210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2627" , 0x1180080e05218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2628" , 0x1180080e05220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2629" , 0x1180080e05228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2630" , 0x1180080e05230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2631" , 0x1180080e05238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2632" , 0x1180080e05240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2633" , 0x1180080e05248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2634" , 0x1180080e05250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2635" , 0x1180080e05258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2636" , 0x1180080e05260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2637" , 0x1180080e05268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2638" , 0x1180080e05270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2639" , 0x1180080e05278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2640" , 0x1180080e05280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2641" , 0x1180080e05288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2642" , 0x1180080e05290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2643" , 0x1180080e05298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2644" , 0x1180080e052a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2645" , 0x1180080e052a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2646" , 0x1180080e052b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2647" , 0x1180080e052b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2648" , 0x1180080e052c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2649" , 0x1180080e052c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2650" , 0x1180080e052d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2651" , 0x1180080e052d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2652" , 0x1180080e052e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2653" , 0x1180080e052e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2654" , 0x1180080e052f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2655" , 0x1180080e052f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2656" , 0x1180080e05300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2657" , 0x1180080e05308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2658" , 0x1180080e05310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2659" , 0x1180080e05318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2660" , 0x1180080e05320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2661" , 0x1180080e05328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2662" , 0x1180080e05330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2663" , 0x1180080e05338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2664" , 0x1180080e05340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2665" , 0x1180080e05348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2666" , 0x1180080e05350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2667" , 0x1180080e05358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2668" , 0x1180080e05360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2669" , 0x1180080e05368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2670" , 0x1180080e05370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2671" , 0x1180080e05378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2672" , 0x1180080e05380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2673" , 0x1180080e05388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2674" , 0x1180080e05390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2675" , 0x1180080e05398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2676" , 0x1180080e053a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2677" , 0x1180080e053a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2678" , 0x1180080e053b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2679" , 0x1180080e053b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2680" , 0x1180080e053c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2681" , 0x1180080e053c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2682" , 0x1180080e053d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2683" , 0x1180080e053d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2684" , 0x1180080e053e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2685" , 0x1180080e053e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2686" , 0x1180080e053f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2687" , 0x1180080e053f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2688" , 0x1180080e05400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2689" , 0x1180080e05408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2690" , 0x1180080e05410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2691" , 0x1180080e05418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2692" , 0x1180080e05420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2693" , 0x1180080e05428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2694" , 0x1180080e05430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2695" , 0x1180080e05438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2696" , 0x1180080e05440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2697" , 0x1180080e05448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2698" , 0x1180080e05450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2699" , 0x1180080e05458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2700" , 0x1180080e05460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2701" , 0x1180080e05468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2702" , 0x1180080e05470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2703" , 0x1180080e05478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2704" , 0x1180080e05480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2705" , 0x1180080e05488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2706" , 0x1180080e05490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2707" , 0x1180080e05498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2708" , 0x1180080e054a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2709" , 0x1180080e054a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2710" , 0x1180080e054b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2711" , 0x1180080e054b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2712" , 0x1180080e054c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2713" , 0x1180080e054c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2714" , 0x1180080e054d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2715" , 0x1180080e054d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2716" , 0x1180080e054e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2717" , 0x1180080e054e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2718" , 0x1180080e054f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2719" , 0x1180080e054f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2720" , 0x1180080e05500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2721" , 0x1180080e05508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2722" , 0x1180080e05510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2723" , 0x1180080e05518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2724" , 0x1180080e05520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2725" , 0x1180080e05528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2726" , 0x1180080e05530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2727" , 0x1180080e05538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2728" , 0x1180080e05540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2729" , 0x1180080e05548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2730" , 0x1180080e05550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2731" , 0x1180080e05558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2732" , 0x1180080e05560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2733" , 0x1180080e05568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2734" , 0x1180080e05570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2735" , 0x1180080e05578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2736" , 0x1180080e05580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2737" , 0x1180080e05588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2738" , 0x1180080e05590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2739" , 0x1180080e05598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2740" , 0x1180080e055a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2741" , 0x1180080e055a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2742" , 0x1180080e055b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2743" , 0x1180080e055b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2744" , 0x1180080e055c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2745" , 0x1180080e055c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2746" , 0x1180080e055d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2747" , 0x1180080e055d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2748" , 0x1180080e055e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2749" , 0x1180080e055e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2750" , 0x1180080e055f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2751" , 0x1180080e055f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2752" , 0x1180080e05600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2753" , 0x1180080e05608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2754" , 0x1180080e05610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2755" , 0x1180080e05618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2756" , 0x1180080e05620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2757" , 0x1180080e05628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2758" , 0x1180080e05630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2759" , 0x1180080e05638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2760" , 0x1180080e05640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2761" , 0x1180080e05648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2762" , 0x1180080e05650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2763" , 0x1180080e05658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2764" , 0x1180080e05660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2765" , 0x1180080e05668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2766" , 0x1180080e05670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2767" , 0x1180080e05678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2768" , 0x1180080e05680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2769" , 0x1180080e05688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2770" , 0x1180080e05690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2771" , 0x1180080e05698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2772" , 0x1180080e056a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2773" , 0x1180080e056a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2774" , 0x1180080e056b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2775" , 0x1180080e056b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2776" , 0x1180080e056c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2777" , 0x1180080e056c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2778" , 0x1180080e056d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2779" , 0x1180080e056d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2780" , 0x1180080e056e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2781" , 0x1180080e056e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2782" , 0x1180080e056f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2783" , 0x1180080e056f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2784" , 0x1180080e05700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2785" , 0x1180080e05708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2786" , 0x1180080e05710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2787" , 0x1180080e05718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2788" , 0x1180080e05720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2789" , 0x1180080e05728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2790" , 0x1180080e05730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2791" , 0x1180080e05738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2792" , 0x1180080e05740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2793" , 0x1180080e05748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2794" , 0x1180080e05750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2795" , 0x1180080e05758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2796" , 0x1180080e05760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2797" , 0x1180080e05768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2798" , 0x1180080e05770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2799" , 0x1180080e05778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2800" , 0x1180080e05780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2801" , 0x1180080e05788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2802" , 0x1180080e05790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2803" , 0x1180080e05798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2804" , 0x1180080e057a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2805" , 0x1180080e057a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2806" , 0x1180080e057b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2807" , 0x1180080e057b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2808" , 0x1180080e057c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2809" , 0x1180080e057c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2810" , 0x1180080e057d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2811" , 0x1180080e057d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2812" , 0x1180080e057e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2813" , 0x1180080e057e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2814" , 0x1180080e057f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2815" , 0x1180080e057f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2816" , 0x1180080e05800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2817" , 0x1180080e05808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2818" , 0x1180080e05810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2819" , 0x1180080e05818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2820" , 0x1180080e05820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2821" , 0x1180080e05828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2822" , 0x1180080e05830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2823" , 0x1180080e05838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2824" , 0x1180080e05840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2825" , 0x1180080e05848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2826" , 0x1180080e05850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2827" , 0x1180080e05858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2828" , 0x1180080e05860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2829" , 0x1180080e05868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2830" , 0x1180080e05870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2831" , 0x1180080e05878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2832" , 0x1180080e05880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2833" , 0x1180080e05888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2834" , 0x1180080e05890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2835" , 0x1180080e05898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2836" , 0x1180080e058a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2837" , 0x1180080e058a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2838" , 0x1180080e058b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2839" , 0x1180080e058b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2840" , 0x1180080e058c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2841" , 0x1180080e058c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2842" , 0x1180080e058d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2843" , 0x1180080e058d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2844" , 0x1180080e058e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2845" , 0x1180080e058e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2846" , 0x1180080e058f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2847" , 0x1180080e058f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2848" , 0x1180080e05900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2849" , 0x1180080e05908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2850" , 0x1180080e05910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2851" , 0x1180080e05918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2852" , 0x1180080e05920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2853" , 0x1180080e05928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2854" , 0x1180080e05930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2855" , 0x1180080e05938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2856" , 0x1180080e05940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2857" , 0x1180080e05948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2858" , 0x1180080e05950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2859" , 0x1180080e05958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2860" , 0x1180080e05960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2861" , 0x1180080e05968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2862" , 0x1180080e05970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2863" , 0x1180080e05978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2864" , 0x1180080e05980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2865" , 0x1180080e05988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2866" , 0x1180080e05990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2867" , 0x1180080e05998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2868" , 0x1180080e059a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2869" , 0x1180080e059a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2870" , 0x1180080e059b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2871" , 0x1180080e059b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2872" , 0x1180080e059c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2873" , 0x1180080e059c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2874" , 0x1180080e059d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2875" , 0x1180080e059d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2876" , 0x1180080e059e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2877" , 0x1180080e059e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2878" , 0x1180080e059f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2879" , 0x1180080e059f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2880" , 0x1180080e05a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2881" , 0x1180080e05a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2882" , 0x1180080e05a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2883" , 0x1180080e05a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2884" , 0x1180080e05a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2885" , 0x1180080e05a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2886" , 0x1180080e05a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2887" , 0x1180080e05a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2888" , 0x1180080e05a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2889" , 0x1180080e05a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2890" , 0x1180080e05a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2891" , 0x1180080e05a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2892" , 0x1180080e05a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2893" , 0x1180080e05a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2894" , 0x1180080e05a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2895" , 0x1180080e05a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2896" , 0x1180080e05a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2897" , 0x1180080e05a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2898" , 0x1180080e05a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2899" , 0x1180080e05a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2900" , 0x1180080e05aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2901" , 0x1180080e05aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2902" , 0x1180080e05ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2903" , 0x1180080e05ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2904" , 0x1180080e05ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2905" , 0x1180080e05ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2906" , 0x1180080e05ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2907" , 0x1180080e05ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2908" , 0x1180080e05ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2909" , 0x1180080e05ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2910" , 0x1180080e05af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2911" , 0x1180080e05af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2912" , 0x1180080e05b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2913" , 0x1180080e05b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2914" , 0x1180080e05b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2915" , 0x1180080e05b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2916" , 0x1180080e05b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2917" , 0x1180080e05b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2918" , 0x1180080e05b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2919" , 0x1180080e05b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2920" , 0x1180080e05b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2921" , 0x1180080e05b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2922" , 0x1180080e05b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2923" , 0x1180080e05b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2924" , 0x1180080e05b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2925" , 0x1180080e05b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2926" , 0x1180080e05b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2927" , 0x1180080e05b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2928" , 0x1180080e05b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2929" , 0x1180080e05b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2930" , 0x1180080e05b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2931" , 0x1180080e05b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2932" , 0x1180080e05ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2933" , 0x1180080e05ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2934" , 0x1180080e05bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2935" , 0x1180080e05bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2936" , 0x1180080e05bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2937" , 0x1180080e05bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2938" , 0x1180080e05bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2939" , 0x1180080e05bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2940" , 0x1180080e05be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2941" , 0x1180080e05be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2942" , 0x1180080e05bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2943" , 0x1180080e05bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2944" , 0x1180080e05c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2945" , 0x1180080e05c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2946" , 0x1180080e05c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2947" , 0x1180080e05c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2948" , 0x1180080e05c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2949" , 0x1180080e05c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2950" , 0x1180080e05c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2951" , 0x1180080e05c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2952" , 0x1180080e05c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2953" , 0x1180080e05c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2954" , 0x1180080e05c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2955" , 0x1180080e05c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2956" , 0x1180080e05c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2957" , 0x1180080e05c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2958" , 0x1180080e05c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2959" , 0x1180080e05c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2960" , 0x1180080e05c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2961" , 0x1180080e05c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2962" , 0x1180080e05c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2963" , 0x1180080e05c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2964" , 0x1180080e05ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2965" , 0x1180080e05ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2966" , 0x1180080e05cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2967" , 0x1180080e05cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2968" , 0x1180080e05cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2969" , 0x1180080e05cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2970" , 0x1180080e05cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2971" , 0x1180080e05cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2972" , 0x1180080e05ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2973" , 0x1180080e05ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2974" , 0x1180080e05cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2975" , 0x1180080e05cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2976" , 0x1180080e05d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2977" , 0x1180080e05d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2978" , 0x1180080e05d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2979" , 0x1180080e05d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2980" , 0x1180080e05d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2981" , 0x1180080e05d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2982" , 0x1180080e05d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2983" , 0x1180080e05d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2984" , 0x1180080e05d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2985" , 0x1180080e05d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2986" , 0x1180080e05d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2987" , 0x1180080e05d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2988" , 0x1180080e05d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2989" , 0x1180080e05d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2990" , 0x1180080e05d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2991" , 0x1180080e05d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2992" , 0x1180080e05d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2993" , 0x1180080e05d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2994" , 0x1180080e05d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2995" , 0x1180080e05d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2996" , 0x1180080e05da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2997" , 0x1180080e05da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2998" , 0x1180080e05db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP2999" , 0x1180080e05db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3000" , 0x1180080e05dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3001" , 0x1180080e05dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3002" , 0x1180080e05dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3003" , 0x1180080e05dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3004" , 0x1180080e05de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3005" , 0x1180080e05de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3006" , 0x1180080e05df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3007" , 0x1180080e05df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3008" , 0x1180080e05e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3009" , 0x1180080e05e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3010" , 0x1180080e05e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3011" , 0x1180080e05e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3012" , 0x1180080e05e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3013" , 0x1180080e05e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3014" , 0x1180080e05e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3015" , 0x1180080e05e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3016" , 0x1180080e05e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3017" , 0x1180080e05e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3018" , 0x1180080e05e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3019" , 0x1180080e05e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3020" , 0x1180080e05e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3021" , 0x1180080e05e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3022" , 0x1180080e05e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3023" , 0x1180080e05e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3024" , 0x1180080e05e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3025" , 0x1180080e05e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3026" , 0x1180080e05e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3027" , 0x1180080e05e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3028" , 0x1180080e05ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3029" , 0x1180080e05ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3030" , 0x1180080e05eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3031" , 0x1180080e05eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3032" , 0x1180080e05ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3033" , 0x1180080e05ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3034" , 0x1180080e05ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3035" , 0x1180080e05ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3036" , 0x1180080e05ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3037" , 0x1180080e05ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3038" , 0x1180080e05ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3039" , 0x1180080e05ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3040" , 0x1180080e05f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3041" , 0x1180080e05f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3042" , 0x1180080e05f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3043" , 0x1180080e05f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3044" , 0x1180080e05f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3045" , 0x1180080e05f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3046" , 0x1180080e05f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3047" , 0x1180080e05f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3048" , 0x1180080e05f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3049" , 0x1180080e05f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3050" , 0x1180080e05f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3051" , 0x1180080e05f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3052" , 0x1180080e05f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3053" , 0x1180080e05f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3054" , 0x1180080e05f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3055" , 0x1180080e05f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3056" , 0x1180080e05f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3057" , 0x1180080e05f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3058" , 0x1180080e05f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3059" , 0x1180080e05f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3060" , 0x1180080e05fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3061" , 0x1180080e05fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3062" , 0x1180080e05fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3063" , 0x1180080e05fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3064" , 0x1180080e05fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3065" , 0x1180080e05fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3066" , 0x1180080e05fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3067" , 0x1180080e05fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3068" , 0x1180080e05fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3069" , 0x1180080e05fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3070" , 0x1180080e05ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3071" , 0x1180080e05ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3072" , 0x1180080e06000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3073" , 0x1180080e06008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3074" , 0x1180080e06010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3075" , 0x1180080e06018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3076" , 0x1180080e06020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3077" , 0x1180080e06028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3078" , 0x1180080e06030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3079" , 0x1180080e06038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3080" , 0x1180080e06040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3081" , 0x1180080e06048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3082" , 0x1180080e06050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3083" , 0x1180080e06058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3084" , 0x1180080e06060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3085" , 0x1180080e06068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3086" , 0x1180080e06070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3087" , 0x1180080e06078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3088" , 0x1180080e06080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3089" , 0x1180080e06088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3090" , 0x1180080e06090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3091" , 0x1180080e06098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3092" , 0x1180080e060a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3093" , 0x1180080e060a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3094" , 0x1180080e060b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3095" , 0x1180080e060b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3096" , 0x1180080e060c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3097" , 0x1180080e060c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3098" , 0x1180080e060d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3099" , 0x1180080e060d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3100" , 0x1180080e060e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3101" , 0x1180080e060e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3102" , 0x1180080e060f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3103" , 0x1180080e060f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3104" , 0x1180080e06100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3105" , 0x1180080e06108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3106" , 0x1180080e06110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3107" , 0x1180080e06118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3108" , 0x1180080e06120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3109" , 0x1180080e06128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3110" , 0x1180080e06130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3111" , 0x1180080e06138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3112" , 0x1180080e06140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3113" , 0x1180080e06148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3114" , 0x1180080e06150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3115" , 0x1180080e06158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3116" , 0x1180080e06160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3117" , 0x1180080e06168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3118" , 0x1180080e06170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3119" , 0x1180080e06178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3120" , 0x1180080e06180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3121" , 0x1180080e06188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3122" , 0x1180080e06190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3123" , 0x1180080e06198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3124" , 0x1180080e061a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3125" , 0x1180080e061a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3126" , 0x1180080e061b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3127" , 0x1180080e061b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3128" , 0x1180080e061c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3129" , 0x1180080e061c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3130" , 0x1180080e061d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3131" , 0x1180080e061d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3132" , 0x1180080e061e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3133" , 0x1180080e061e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3134" , 0x1180080e061f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3135" , 0x1180080e061f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3136" , 0x1180080e06200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3137" , 0x1180080e06208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3138" , 0x1180080e06210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3139" , 0x1180080e06218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3140" , 0x1180080e06220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3141" , 0x1180080e06228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3142" , 0x1180080e06230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3143" , 0x1180080e06238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3144" , 0x1180080e06240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3145" , 0x1180080e06248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3146" , 0x1180080e06250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3147" , 0x1180080e06258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3148" , 0x1180080e06260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3149" , 0x1180080e06268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3150" , 0x1180080e06270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3151" , 0x1180080e06278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3152" , 0x1180080e06280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3153" , 0x1180080e06288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3154" , 0x1180080e06290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3155" , 0x1180080e06298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3156" , 0x1180080e062a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3157" , 0x1180080e062a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3158" , 0x1180080e062b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3159" , 0x1180080e062b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3160" , 0x1180080e062c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3161" , 0x1180080e062c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3162" , 0x1180080e062d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3163" , 0x1180080e062d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3164" , 0x1180080e062e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3165" , 0x1180080e062e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3166" , 0x1180080e062f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3167" , 0x1180080e062f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3168" , 0x1180080e06300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3169" , 0x1180080e06308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3170" , 0x1180080e06310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3171" , 0x1180080e06318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3172" , 0x1180080e06320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3173" , 0x1180080e06328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3174" , 0x1180080e06330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3175" , 0x1180080e06338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3176" , 0x1180080e06340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3177" , 0x1180080e06348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3178" , 0x1180080e06350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3179" , 0x1180080e06358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3180" , 0x1180080e06360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3181" , 0x1180080e06368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3182" , 0x1180080e06370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3183" , 0x1180080e06378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3184" , 0x1180080e06380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3185" , 0x1180080e06388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3186" , 0x1180080e06390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3187" , 0x1180080e06398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3188" , 0x1180080e063a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3189" , 0x1180080e063a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3190" , 0x1180080e063b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3191" , 0x1180080e063b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3192" , 0x1180080e063c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3193" , 0x1180080e063c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3194" , 0x1180080e063d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3195" , 0x1180080e063d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3196" , 0x1180080e063e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3197" , 0x1180080e063e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3198" , 0x1180080e063f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3199" , 0x1180080e063f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3200" , 0x1180080e06400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3201" , 0x1180080e06408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3202" , 0x1180080e06410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3203" , 0x1180080e06418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3204" , 0x1180080e06420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3205" , 0x1180080e06428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3206" , 0x1180080e06430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3207" , 0x1180080e06438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3208" , 0x1180080e06440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3209" , 0x1180080e06448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3210" , 0x1180080e06450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3211" , 0x1180080e06458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3212" , 0x1180080e06460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3213" , 0x1180080e06468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3214" , 0x1180080e06470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3215" , 0x1180080e06478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3216" , 0x1180080e06480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3217" , 0x1180080e06488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3218" , 0x1180080e06490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3219" , 0x1180080e06498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3220" , 0x1180080e064a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3221" , 0x1180080e064a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3222" , 0x1180080e064b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3223" , 0x1180080e064b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3224" , 0x1180080e064c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3225" , 0x1180080e064c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3226" , 0x1180080e064d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3227" , 0x1180080e064d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3228" , 0x1180080e064e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3229" , 0x1180080e064e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3230" , 0x1180080e064f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3231" , 0x1180080e064f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3232" , 0x1180080e06500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3233" , 0x1180080e06508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3234" , 0x1180080e06510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3235" , 0x1180080e06518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3236" , 0x1180080e06520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3237" , 0x1180080e06528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3238" , 0x1180080e06530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3239" , 0x1180080e06538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3240" , 0x1180080e06540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3241" , 0x1180080e06548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3242" , 0x1180080e06550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3243" , 0x1180080e06558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3244" , 0x1180080e06560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3245" , 0x1180080e06568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3246" , 0x1180080e06570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3247" , 0x1180080e06578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3248" , 0x1180080e06580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3249" , 0x1180080e06588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3250" , 0x1180080e06590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3251" , 0x1180080e06598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3252" , 0x1180080e065a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3253" , 0x1180080e065a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3254" , 0x1180080e065b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3255" , 0x1180080e065b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3256" , 0x1180080e065c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3257" , 0x1180080e065c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3258" , 0x1180080e065d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3259" , 0x1180080e065d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3260" , 0x1180080e065e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3261" , 0x1180080e065e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3262" , 0x1180080e065f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3263" , 0x1180080e065f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3264" , 0x1180080e06600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3265" , 0x1180080e06608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3266" , 0x1180080e06610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3267" , 0x1180080e06618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3268" , 0x1180080e06620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3269" , 0x1180080e06628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3270" , 0x1180080e06630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3271" , 0x1180080e06638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3272" , 0x1180080e06640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3273" , 0x1180080e06648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3274" , 0x1180080e06650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3275" , 0x1180080e06658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3276" , 0x1180080e06660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3277" , 0x1180080e06668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3278" , 0x1180080e06670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3279" , 0x1180080e06678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3280" , 0x1180080e06680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3281" , 0x1180080e06688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3282" , 0x1180080e06690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3283" , 0x1180080e06698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3284" , 0x1180080e066a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3285" , 0x1180080e066a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3286" , 0x1180080e066b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3287" , 0x1180080e066b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3288" , 0x1180080e066c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3289" , 0x1180080e066c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3290" , 0x1180080e066d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3291" , 0x1180080e066d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3292" , 0x1180080e066e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3293" , 0x1180080e066e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3294" , 0x1180080e066f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3295" , 0x1180080e066f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3296" , 0x1180080e06700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3297" , 0x1180080e06708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3298" , 0x1180080e06710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3299" , 0x1180080e06718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3300" , 0x1180080e06720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3301" , 0x1180080e06728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3302" , 0x1180080e06730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3303" , 0x1180080e06738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3304" , 0x1180080e06740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3305" , 0x1180080e06748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3306" , 0x1180080e06750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3307" , 0x1180080e06758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3308" , 0x1180080e06760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3309" , 0x1180080e06768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3310" , 0x1180080e06770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3311" , 0x1180080e06778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3312" , 0x1180080e06780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3313" , 0x1180080e06788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3314" , 0x1180080e06790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3315" , 0x1180080e06798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3316" , 0x1180080e067a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3317" , 0x1180080e067a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3318" , 0x1180080e067b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3319" , 0x1180080e067b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3320" , 0x1180080e067c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3321" , 0x1180080e067c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3322" , 0x1180080e067d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3323" , 0x1180080e067d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3324" , 0x1180080e067e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3325" , 0x1180080e067e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3326" , 0x1180080e067f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3327" , 0x1180080e067f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3328" , 0x1180080e06800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3329" , 0x1180080e06808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3330" , 0x1180080e06810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3331" , 0x1180080e06818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3332" , 0x1180080e06820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3333" , 0x1180080e06828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3334" , 0x1180080e06830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3335" , 0x1180080e06838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3336" , 0x1180080e06840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3337" , 0x1180080e06848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3338" , 0x1180080e06850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3339" , 0x1180080e06858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3340" , 0x1180080e06860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3341" , 0x1180080e06868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3342" , 0x1180080e06870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3343" , 0x1180080e06878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3344" , 0x1180080e06880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3345" , 0x1180080e06888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3346" , 0x1180080e06890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3347" , 0x1180080e06898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3348" , 0x1180080e068a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3349" , 0x1180080e068a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3350" , 0x1180080e068b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3351" , 0x1180080e068b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3352" , 0x1180080e068c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3353" , 0x1180080e068c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3354" , 0x1180080e068d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3355" , 0x1180080e068d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3356" , 0x1180080e068e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3357" , 0x1180080e068e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3358" , 0x1180080e068f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3359" , 0x1180080e068f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3360" , 0x1180080e06900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3361" , 0x1180080e06908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3362" , 0x1180080e06910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3363" , 0x1180080e06918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3364" , 0x1180080e06920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3365" , 0x1180080e06928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3366" , 0x1180080e06930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3367" , 0x1180080e06938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3368" , 0x1180080e06940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3369" , 0x1180080e06948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3370" , 0x1180080e06950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3371" , 0x1180080e06958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3372" , 0x1180080e06960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3373" , 0x1180080e06968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3374" , 0x1180080e06970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3375" , 0x1180080e06978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3376" , 0x1180080e06980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3377" , 0x1180080e06988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3378" , 0x1180080e06990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3379" , 0x1180080e06998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3380" , 0x1180080e069a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3381" , 0x1180080e069a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3382" , 0x1180080e069b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3383" , 0x1180080e069b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3384" , 0x1180080e069c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3385" , 0x1180080e069c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3386" , 0x1180080e069d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3387" , 0x1180080e069d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3388" , 0x1180080e069e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3389" , 0x1180080e069e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3390" , 0x1180080e069f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3391" , 0x1180080e069f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3392" , 0x1180080e06a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3393" , 0x1180080e06a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3394" , 0x1180080e06a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3395" , 0x1180080e06a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3396" , 0x1180080e06a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3397" , 0x1180080e06a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3398" , 0x1180080e06a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3399" , 0x1180080e06a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3400" , 0x1180080e06a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3401" , 0x1180080e06a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3402" , 0x1180080e06a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3403" , 0x1180080e06a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3404" , 0x1180080e06a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3405" , 0x1180080e06a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3406" , 0x1180080e06a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3407" , 0x1180080e06a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3408" , 0x1180080e06a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3409" , 0x1180080e06a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3410" , 0x1180080e06a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3411" , 0x1180080e06a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3412" , 0x1180080e06aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3413" , 0x1180080e06aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3414" , 0x1180080e06ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3415" , 0x1180080e06ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3416" , 0x1180080e06ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3417" , 0x1180080e06ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3418" , 0x1180080e06ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3419" , 0x1180080e06ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3420" , 0x1180080e06ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3421" , 0x1180080e06ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3422" , 0x1180080e06af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3423" , 0x1180080e06af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3424" , 0x1180080e06b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3425" , 0x1180080e06b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3426" , 0x1180080e06b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3427" , 0x1180080e06b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3428" , 0x1180080e06b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3429" , 0x1180080e06b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3430" , 0x1180080e06b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3431" , 0x1180080e06b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3432" , 0x1180080e06b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3433" , 0x1180080e06b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3434" , 0x1180080e06b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3435" , 0x1180080e06b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3436" , 0x1180080e06b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3437" , 0x1180080e06b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3438" , 0x1180080e06b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3439" , 0x1180080e06b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3440" , 0x1180080e06b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3441" , 0x1180080e06b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3442" , 0x1180080e06b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3443" , 0x1180080e06b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3444" , 0x1180080e06ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3445" , 0x1180080e06ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3446" , 0x1180080e06bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3447" , 0x1180080e06bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3448" , 0x1180080e06bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3449" , 0x1180080e06bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3450" , 0x1180080e06bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3451" , 0x1180080e06bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3452" , 0x1180080e06be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3453" , 0x1180080e06be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3454" , 0x1180080e06bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3455" , 0x1180080e06bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3456" , 0x1180080e06c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3457" , 0x1180080e06c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3458" , 0x1180080e06c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3459" , 0x1180080e06c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3460" , 0x1180080e06c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3461" , 0x1180080e06c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3462" , 0x1180080e06c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3463" , 0x1180080e06c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3464" , 0x1180080e06c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3465" , 0x1180080e06c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3466" , 0x1180080e06c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3467" , 0x1180080e06c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3468" , 0x1180080e06c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3469" , 0x1180080e06c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3470" , 0x1180080e06c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3471" , 0x1180080e06c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3472" , 0x1180080e06c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3473" , 0x1180080e06c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3474" , 0x1180080e06c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3475" , 0x1180080e06c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3476" , 0x1180080e06ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3477" , 0x1180080e06ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3478" , 0x1180080e06cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3479" , 0x1180080e06cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3480" , 0x1180080e06cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3481" , 0x1180080e06cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3482" , 0x1180080e06cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3483" , 0x1180080e06cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3484" , 0x1180080e06ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3485" , 0x1180080e06ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3486" , 0x1180080e06cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3487" , 0x1180080e06cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3488" , 0x1180080e06d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3489" , 0x1180080e06d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3490" , 0x1180080e06d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3491" , 0x1180080e06d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3492" , 0x1180080e06d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3493" , 0x1180080e06d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3494" , 0x1180080e06d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3495" , 0x1180080e06d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3496" , 0x1180080e06d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3497" , 0x1180080e06d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3498" , 0x1180080e06d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3499" , 0x1180080e06d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3500" , 0x1180080e06d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3501" , 0x1180080e06d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3502" , 0x1180080e06d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3503" , 0x1180080e06d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3504" , 0x1180080e06d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3505" , 0x1180080e06d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3506" , 0x1180080e06d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3507" , 0x1180080e06d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3508" , 0x1180080e06da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3509" , 0x1180080e06da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3510" , 0x1180080e06db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3511" , 0x1180080e06db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3512" , 0x1180080e06dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3513" , 0x1180080e06dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3514" , 0x1180080e06dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3515" , 0x1180080e06dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3516" , 0x1180080e06de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3517" , 0x1180080e06de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3518" , 0x1180080e06df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3519" , 0x1180080e06df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3520" , 0x1180080e06e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3521" , 0x1180080e06e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3522" , 0x1180080e06e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3523" , 0x1180080e06e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3524" , 0x1180080e06e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3525" , 0x1180080e06e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3526" , 0x1180080e06e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3527" , 0x1180080e06e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3528" , 0x1180080e06e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3529" , 0x1180080e06e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3530" , 0x1180080e06e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3531" , 0x1180080e06e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3532" , 0x1180080e06e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3533" , 0x1180080e06e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3534" , 0x1180080e06e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3535" , 0x1180080e06e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3536" , 0x1180080e06e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3537" , 0x1180080e06e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3538" , 0x1180080e06e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3539" , 0x1180080e06e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3540" , 0x1180080e06ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3541" , 0x1180080e06ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3542" , 0x1180080e06eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3543" , 0x1180080e06eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3544" , 0x1180080e06ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3545" , 0x1180080e06ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3546" , 0x1180080e06ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3547" , 0x1180080e06ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3548" , 0x1180080e06ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3549" , 0x1180080e06ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3550" , 0x1180080e06ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3551" , 0x1180080e06ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3552" , 0x1180080e06f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3553" , 0x1180080e06f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3554" , 0x1180080e06f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3555" , 0x1180080e06f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3556" , 0x1180080e06f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3557" , 0x1180080e06f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3558" , 0x1180080e06f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3559" , 0x1180080e06f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3560" , 0x1180080e06f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3561" , 0x1180080e06f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3562" , 0x1180080e06f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3563" , 0x1180080e06f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3564" , 0x1180080e06f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3565" , 0x1180080e06f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3566" , 0x1180080e06f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3567" , 0x1180080e06f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3568" , 0x1180080e06f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3569" , 0x1180080e06f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3570" , 0x1180080e06f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3571" , 0x1180080e06f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3572" , 0x1180080e06fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3573" , 0x1180080e06fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3574" , 0x1180080e06fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3575" , 0x1180080e06fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3576" , 0x1180080e06fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3577" , 0x1180080e06fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3578" , 0x1180080e06fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3579" , 0x1180080e06fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3580" , 0x1180080e06fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3581" , 0x1180080e06fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3582" , 0x1180080e06ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3583" , 0x1180080e06ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3584" , 0x1180080e07000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3585" , 0x1180080e07008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3586" , 0x1180080e07010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3587" , 0x1180080e07018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3588" , 0x1180080e07020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3589" , 0x1180080e07028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3590" , 0x1180080e07030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3591" , 0x1180080e07038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3592" , 0x1180080e07040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3593" , 0x1180080e07048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3594" , 0x1180080e07050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3595" , 0x1180080e07058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3596" , 0x1180080e07060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3597" , 0x1180080e07068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3598" , 0x1180080e07070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3599" , 0x1180080e07078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3600" , 0x1180080e07080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3601" , 0x1180080e07088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3602" , 0x1180080e07090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3603" , 0x1180080e07098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3604" , 0x1180080e070a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3605" , 0x1180080e070a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3606" , 0x1180080e070b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3607" , 0x1180080e070b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3608" , 0x1180080e070c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3609" , 0x1180080e070c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3610" , 0x1180080e070d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3611" , 0x1180080e070d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3612" , 0x1180080e070e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3613" , 0x1180080e070e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3614" , 0x1180080e070f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3615" , 0x1180080e070f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3616" , 0x1180080e07100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3617" , 0x1180080e07108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3618" , 0x1180080e07110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3619" , 0x1180080e07118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3620" , 0x1180080e07120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3621" , 0x1180080e07128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3622" , 0x1180080e07130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3623" , 0x1180080e07138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3624" , 0x1180080e07140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3625" , 0x1180080e07148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3626" , 0x1180080e07150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3627" , 0x1180080e07158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3628" , 0x1180080e07160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3629" , 0x1180080e07168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3630" , 0x1180080e07170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3631" , 0x1180080e07178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3632" , 0x1180080e07180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3633" , 0x1180080e07188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3634" , 0x1180080e07190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3635" , 0x1180080e07198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3636" , 0x1180080e071a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3637" , 0x1180080e071a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3638" , 0x1180080e071b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3639" , 0x1180080e071b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3640" , 0x1180080e071c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3641" , 0x1180080e071c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3642" , 0x1180080e071d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3643" , 0x1180080e071d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3644" , 0x1180080e071e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3645" , 0x1180080e071e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3646" , 0x1180080e071f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3647" , 0x1180080e071f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3648" , 0x1180080e07200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3649" , 0x1180080e07208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3650" , 0x1180080e07210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3651" , 0x1180080e07218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3652" , 0x1180080e07220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3653" , 0x1180080e07228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3654" , 0x1180080e07230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3655" , 0x1180080e07238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3656" , 0x1180080e07240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3657" , 0x1180080e07248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3658" , 0x1180080e07250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3659" , 0x1180080e07258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3660" , 0x1180080e07260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3661" , 0x1180080e07268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3662" , 0x1180080e07270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3663" , 0x1180080e07278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3664" , 0x1180080e07280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3665" , 0x1180080e07288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3666" , 0x1180080e07290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3667" , 0x1180080e07298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3668" , 0x1180080e072a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3669" , 0x1180080e072a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3670" , 0x1180080e072b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3671" , 0x1180080e072b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3672" , 0x1180080e072c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3673" , 0x1180080e072c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3674" , 0x1180080e072d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3675" , 0x1180080e072d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3676" , 0x1180080e072e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3677" , 0x1180080e072e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3678" , 0x1180080e072f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3679" , 0x1180080e072f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3680" , 0x1180080e07300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3681" , 0x1180080e07308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3682" , 0x1180080e07310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3683" , 0x1180080e07318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3684" , 0x1180080e07320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3685" , 0x1180080e07328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3686" , 0x1180080e07330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3687" , 0x1180080e07338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3688" , 0x1180080e07340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3689" , 0x1180080e07348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3690" , 0x1180080e07350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3691" , 0x1180080e07358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3692" , 0x1180080e07360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3693" , 0x1180080e07368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3694" , 0x1180080e07370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3695" , 0x1180080e07378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3696" , 0x1180080e07380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3697" , 0x1180080e07388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3698" , 0x1180080e07390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3699" , 0x1180080e07398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3700" , 0x1180080e073a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3701" , 0x1180080e073a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3702" , 0x1180080e073b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3703" , 0x1180080e073b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3704" , 0x1180080e073c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3705" , 0x1180080e073c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3706" , 0x1180080e073d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3707" , 0x1180080e073d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3708" , 0x1180080e073e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3709" , 0x1180080e073e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3710" , 0x1180080e073f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3711" , 0x1180080e073f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3712" , 0x1180080e07400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3713" , 0x1180080e07408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3714" , 0x1180080e07410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3715" , 0x1180080e07418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3716" , 0x1180080e07420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3717" , 0x1180080e07428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3718" , 0x1180080e07430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3719" , 0x1180080e07438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3720" , 0x1180080e07440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3721" , 0x1180080e07448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3722" , 0x1180080e07450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3723" , 0x1180080e07458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3724" , 0x1180080e07460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3725" , 0x1180080e07468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3726" , 0x1180080e07470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3727" , 0x1180080e07478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3728" , 0x1180080e07480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3729" , 0x1180080e07488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3730" , 0x1180080e07490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3731" , 0x1180080e07498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3732" , 0x1180080e074a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3733" , 0x1180080e074a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3734" , 0x1180080e074b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3735" , 0x1180080e074b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3736" , 0x1180080e074c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3737" , 0x1180080e074c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3738" , 0x1180080e074d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3739" , 0x1180080e074d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3740" , 0x1180080e074e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3741" , 0x1180080e074e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3742" , 0x1180080e074f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3743" , 0x1180080e074f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3744" , 0x1180080e07500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3745" , 0x1180080e07508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3746" , 0x1180080e07510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3747" , 0x1180080e07518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3748" , 0x1180080e07520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3749" , 0x1180080e07528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3750" , 0x1180080e07530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3751" , 0x1180080e07538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3752" , 0x1180080e07540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3753" , 0x1180080e07548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3754" , 0x1180080e07550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3755" , 0x1180080e07558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3756" , 0x1180080e07560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3757" , 0x1180080e07568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3758" , 0x1180080e07570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3759" , 0x1180080e07578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3760" , 0x1180080e07580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3761" , 0x1180080e07588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3762" , 0x1180080e07590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3763" , 0x1180080e07598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3764" , 0x1180080e075a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3765" , 0x1180080e075a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3766" , 0x1180080e075b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3767" , 0x1180080e075b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3768" , 0x1180080e075c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3769" , 0x1180080e075c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3770" , 0x1180080e075d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3771" , 0x1180080e075d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3772" , 0x1180080e075e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3773" , 0x1180080e075e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3774" , 0x1180080e075f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3775" , 0x1180080e075f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3776" , 0x1180080e07600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3777" , 0x1180080e07608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3778" , 0x1180080e07610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3779" , 0x1180080e07618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3780" , 0x1180080e07620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3781" , 0x1180080e07628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3782" , 0x1180080e07630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3783" , 0x1180080e07638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3784" , 0x1180080e07640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3785" , 0x1180080e07648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3786" , 0x1180080e07650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3787" , 0x1180080e07658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3788" , 0x1180080e07660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3789" , 0x1180080e07668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3790" , 0x1180080e07670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3791" , 0x1180080e07678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3792" , 0x1180080e07680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3793" , 0x1180080e07688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3794" , 0x1180080e07690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3795" , 0x1180080e07698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3796" , 0x1180080e076a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3797" , 0x1180080e076a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3798" , 0x1180080e076b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3799" , 0x1180080e076b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3800" , 0x1180080e076c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3801" , 0x1180080e076c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3802" , 0x1180080e076d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3803" , 0x1180080e076d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3804" , 0x1180080e076e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3805" , 0x1180080e076e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3806" , 0x1180080e076f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3807" , 0x1180080e076f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3808" , 0x1180080e07700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3809" , 0x1180080e07708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3810" , 0x1180080e07710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3811" , 0x1180080e07718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3812" , 0x1180080e07720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3813" , 0x1180080e07728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3814" , 0x1180080e07730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3815" , 0x1180080e07738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3816" , 0x1180080e07740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3817" , 0x1180080e07748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3818" , 0x1180080e07750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3819" , 0x1180080e07758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3820" , 0x1180080e07760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3821" , 0x1180080e07768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3822" , 0x1180080e07770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3823" , 0x1180080e07778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3824" , 0x1180080e07780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3825" , 0x1180080e07788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3826" , 0x1180080e07790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3827" , 0x1180080e07798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3828" , 0x1180080e077a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3829" , 0x1180080e077a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3830" , 0x1180080e077b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3831" , 0x1180080e077b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3832" , 0x1180080e077c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3833" , 0x1180080e077c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3834" , 0x1180080e077d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3835" , 0x1180080e077d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3836" , 0x1180080e077e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3837" , 0x1180080e077e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3838" , 0x1180080e077f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3839" , 0x1180080e077f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3840" , 0x1180080e07800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3841" , 0x1180080e07808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3842" , 0x1180080e07810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3843" , 0x1180080e07818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3844" , 0x1180080e07820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3845" , 0x1180080e07828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3846" , 0x1180080e07830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3847" , 0x1180080e07838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3848" , 0x1180080e07840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3849" , 0x1180080e07848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3850" , 0x1180080e07850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3851" , 0x1180080e07858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3852" , 0x1180080e07860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3853" , 0x1180080e07868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3854" , 0x1180080e07870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3855" , 0x1180080e07878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3856" , 0x1180080e07880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3857" , 0x1180080e07888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3858" , 0x1180080e07890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3859" , 0x1180080e07898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3860" , 0x1180080e078a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3861" , 0x1180080e078a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3862" , 0x1180080e078b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3863" , 0x1180080e078b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3864" , 0x1180080e078c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3865" , 0x1180080e078c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3866" , 0x1180080e078d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3867" , 0x1180080e078d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3868" , 0x1180080e078e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3869" , 0x1180080e078e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3870" , 0x1180080e078f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3871" , 0x1180080e078f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3872" , 0x1180080e07900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3873" , 0x1180080e07908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3874" , 0x1180080e07910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3875" , 0x1180080e07918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3876" , 0x1180080e07920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3877" , 0x1180080e07928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3878" , 0x1180080e07930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3879" , 0x1180080e07938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3880" , 0x1180080e07940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3881" , 0x1180080e07948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3882" , 0x1180080e07950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3883" , 0x1180080e07958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3884" , 0x1180080e07960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3885" , 0x1180080e07968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3886" , 0x1180080e07970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3887" , 0x1180080e07978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3888" , 0x1180080e07980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3889" , 0x1180080e07988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3890" , 0x1180080e07990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3891" , 0x1180080e07998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3892" , 0x1180080e079a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3893" , 0x1180080e079a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3894" , 0x1180080e079b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3895" , 0x1180080e079b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3896" , 0x1180080e079c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3897" , 0x1180080e079c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3898" , 0x1180080e079d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3899" , 0x1180080e079d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3900" , 0x1180080e079e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3901" , 0x1180080e079e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3902" , 0x1180080e079f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3903" , 0x1180080e079f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3904" , 0x1180080e07a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3905" , 0x1180080e07a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3906" , 0x1180080e07a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3907" , 0x1180080e07a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3908" , 0x1180080e07a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3909" , 0x1180080e07a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3910" , 0x1180080e07a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3911" , 0x1180080e07a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3912" , 0x1180080e07a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3913" , 0x1180080e07a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3914" , 0x1180080e07a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3915" , 0x1180080e07a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3916" , 0x1180080e07a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3917" , 0x1180080e07a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3918" , 0x1180080e07a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3919" , 0x1180080e07a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3920" , 0x1180080e07a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3921" , 0x1180080e07a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3922" , 0x1180080e07a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3923" , 0x1180080e07a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3924" , 0x1180080e07aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3925" , 0x1180080e07aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3926" , 0x1180080e07ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3927" , 0x1180080e07ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3928" , 0x1180080e07ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3929" , 0x1180080e07ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3930" , 0x1180080e07ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3931" , 0x1180080e07ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3932" , 0x1180080e07ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3933" , 0x1180080e07ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3934" , 0x1180080e07af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3935" , 0x1180080e07af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3936" , 0x1180080e07b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3937" , 0x1180080e07b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3938" , 0x1180080e07b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3939" , 0x1180080e07b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3940" , 0x1180080e07b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3941" , 0x1180080e07b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3942" , 0x1180080e07b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3943" , 0x1180080e07b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3944" , 0x1180080e07b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3945" , 0x1180080e07b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3946" , 0x1180080e07b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3947" , 0x1180080e07b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3948" , 0x1180080e07b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3949" , 0x1180080e07b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3950" , 0x1180080e07b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3951" , 0x1180080e07b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3952" , 0x1180080e07b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3953" , 0x1180080e07b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3954" , 0x1180080e07b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3955" , 0x1180080e07b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3956" , 0x1180080e07ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3957" , 0x1180080e07ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3958" , 0x1180080e07bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3959" , 0x1180080e07bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3960" , 0x1180080e07bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3961" , 0x1180080e07bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3962" , 0x1180080e07bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3963" , 0x1180080e07bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3964" , 0x1180080e07be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3965" , 0x1180080e07be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3966" , 0x1180080e07bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3967" , 0x1180080e07bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3968" , 0x1180080e07c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3969" , 0x1180080e07c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3970" , 0x1180080e07c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3971" , 0x1180080e07c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3972" , 0x1180080e07c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3973" , 0x1180080e07c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3974" , 0x1180080e07c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3975" , 0x1180080e07c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3976" , 0x1180080e07c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3977" , 0x1180080e07c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3978" , 0x1180080e07c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3979" , 0x1180080e07c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3980" , 0x1180080e07c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3981" , 0x1180080e07c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3982" , 0x1180080e07c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3983" , 0x1180080e07c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3984" , 0x1180080e07c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3985" , 0x1180080e07c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3986" , 0x1180080e07c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3987" , 0x1180080e07c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3988" , 0x1180080e07ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3989" , 0x1180080e07ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3990" , 0x1180080e07cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3991" , 0x1180080e07cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3992" , 0x1180080e07cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3993" , 0x1180080e07cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3994" , 0x1180080e07cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3995" , 0x1180080e07cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3996" , 0x1180080e07ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3997" , 0x1180080e07ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3998" , 0x1180080e07cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP3999" , 0x1180080e07cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4000" , 0x1180080e07d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4001" , 0x1180080e07d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4002" , 0x1180080e07d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4003" , 0x1180080e07d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4004" , 0x1180080e07d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4005" , 0x1180080e07d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4006" , 0x1180080e07d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4007" , 0x1180080e07d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4008" , 0x1180080e07d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4009" , 0x1180080e07d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4010" , 0x1180080e07d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4011" , 0x1180080e07d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4012" , 0x1180080e07d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4013" , 0x1180080e07d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4014" , 0x1180080e07d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4015" , 0x1180080e07d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4016" , 0x1180080e07d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4017" , 0x1180080e07d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4018" , 0x1180080e07d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4019" , 0x1180080e07d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4020" , 0x1180080e07da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4021" , 0x1180080e07da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4022" , 0x1180080e07db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4023" , 0x1180080e07db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4024" , 0x1180080e07dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4025" , 0x1180080e07dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4026" , 0x1180080e07dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4027" , 0x1180080e07dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4028" , 0x1180080e07de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4029" , 0x1180080e07de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4030" , 0x1180080e07df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4031" , 0x1180080e07df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4032" , 0x1180080e07e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4033" , 0x1180080e07e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4034" , 0x1180080e07e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4035" , 0x1180080e07e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4036" , 0x1180080e07e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4037" , 0x1180080e07e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4038" , 0x1180080e07e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4039" , 0x1180080e07e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4040" , 0x1180080e07e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4041" , 0x1180080e07e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4042" , 0x1180080e07e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4043" , 0x1180080e07e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4044" , 0x1180080e07e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4045" , 0x1180080e07e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4046" , 0x1180080e07e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4047" , 0x1180080e07e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4048" , 0x1180080e07e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4049" , 0x1180080e07e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4050" , 0x1180080e07e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4051" , 0x1180080e07e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4052" , 0x1180080e07ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4053" , 0x1180080e07ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4054" , 0x1180080e07eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4055" , 0x1180080e07eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4056" , 0x1180080e07ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4057" , 0x1180080e07ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4058" , 0x1180080e07ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4059" , 0x1180080e07ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4060" , 0x1180080e07ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4061" , 0x1180080e07ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4062" , 0x1180080e07ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4063" , 0x1180080e07ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4064" , 0x1180080e07f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4065" , 0x1180080e07f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4066" , 0x1180080e07f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4067" , 0x1180080e07f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4068" , 0x1180080e07f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4069" , 0x1180080e07f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4070" , 0x1180080e07f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4071" , 0x1180080e07f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4072" , 0x1180080e07f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4073" , 0x1180080e07f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4074" , 0x1180080e07f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4075" , 0x1180080e07f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4076" , 0x1180080e07f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4077" , 0x1180080e07f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4078" , 0x1180080e07f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4079" , 0x1180080e07f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4080" , 0x1180080e07f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4081" , 0x1180080e07f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4082" , 0x1180080e07f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4083" , 0x1180080e07f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4084" , 0x1180080e07fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4085" , 0x1180080e07fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4086" , 0x1180080e07fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4087" , 0x1180080e07fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4088" , 0x1180080e07fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4089" , 0x1180080e07fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4090" , 0x1180080e07fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4091" , 0x1180080e07fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4092" , 0x1180080e07fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4093" , 0x1180080e07fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4094" , 0x1180080e07ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4095" , 0x1180080e07ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4096" , 0x1180080e08000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4097" , 0x1180080e08008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4098" , 0x1180080e08010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4099" , 0x1180080e08018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4100" , 0x1180080e08020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4101" , 0x1180080e08028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4102" , 0x1180080e08030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4103" , 0x1180080e08038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4104" , 0x1180080e08040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4105" , 0x1180080e08048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4106" , 0x1180080e08050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4107" , 0x1180080e08058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4108" , 0x1180080e08060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4109" , 0x1180080e08068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4110" , 0x1180080e08070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4111" , 0x1180080e08078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4112" , 0x1180080e08080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4113" , 0x1180080e08088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4114" , 0x1180080e08090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4115" , 0x1180080e08098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4116" , 0x1180080e080a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4117" , 0x1180080e080a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4118" , 0x1180080e080b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4119" , 0x1180080e080b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4120" , 0x1180080e080c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4121" , 0x1180080e080c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4122" , 0x1180080e080d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4123" , 0x1180080e080d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4124" , 0x1180080e080e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4125" , 0x1180080e080e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4126" , 0x1180080e080f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4127" , 0x1180080e080f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4128" , 0x1180080e08100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4129" , 0x1180080e08108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4130" , 0x1180080e08110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4131" , 0x1180080e08118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4132" , 0x1180080e08120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4133" , 0x1180080e08128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4134" , 0x1180080e08130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4135" , 0x1180080e08138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4136" , 0x1180080e08140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4137" , 0x1180080e08148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4138" , 0x1180080e08150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4139" , 0x1180080e08158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4140" , 0x1180080e08160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4141" , 0x1180080e08168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4142" , 0x1180080e08170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4143" , 0x1180080e08178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4144" , 0x1180080e08180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4145" , 0x1180080e08188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4146" , 0x1180080e08190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4147" , 0x1180080e08198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4148" , 0x1180080e081a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4149" , 0x1180080e081a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4150" , 0x1180080e081b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4151" , 0x1180080e081b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4152" , 0x1180080e081c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4153" , 0x1180080e081c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4154" , 0x1180080e081d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4155" , 0x1180080e081d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4156" , 0x1180080e081e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4157" , 0x1180080e081e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4158" , 0x1180080e081f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4159" , 0x1180080e081f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4160" , 0x1180080e08200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4161" , 0x1180080e08208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4162" , 0x1180080e08210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4163" , 0x1180080e08218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4164" , 0x1180080e08220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4165" , 0x1180080e08228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4166" , 0x1180080e08230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4167" , 0x1180080e08238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4168" , 0x1180080e08240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4169" , 0x1180080e08248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4170" , 0x1180080e08250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4171" , 0x1180080e08258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4172" , 0x1180080e08260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4173" , 0x1180080e08268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4174" , 0x1180080e08270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4175" , 0x1180080e08278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4176" , 0x1180080e08280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4177" , 0x1180080e08288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4178" , 0x1180080e08290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4179" , 0x1180080e08298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4180" , 0x1180080e082a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4181" , 0x1180080e082a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4182" , 0x1180080e082b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4183" , 0x1180080e082b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4184" , 0x1180080e082c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4185" , 0x1180080e082c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4186" , 0x1180080e082d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4187" , 0x1180080e082d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4188" , 0x1180080e082e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4189" , 0x1180080e082e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4190" , 0x1180080e082f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4191" , 0x1180080e082f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4192" , 0x1180080e08300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4193" , 0x1180080e08308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4194" , 0x1180080e08310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4195" , 0x1180080e08318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4196" , 0x1180080e08320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4197" , 0x1180080e08328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4198" , 0x1180080e08330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4199" , 0x1180080e08338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4200" , 0x1180080e08340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4201" , 0x1180080e08348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4202" , 0x1180080e08350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4203" , 0x1180080e08358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4204" , 0x1180080e08360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4205" , 0x1180080e08368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4206" , 0x1180080e08370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4207" , 0x1180080e08378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4208" , 0x1180080e08380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4209" , 0x1180080e08388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4210" , 0x1180080e08390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4211" , 0x1180080e08398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4212" , 0x1180080e083a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4213" , 0x1180080e083a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4214" , 0x1180080e083b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4215" , 0x1180080e083b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4216" , 0x1180080e083c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4217" , 0x1180080e083c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4218" , 0x1180080e083d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4219" , 0x1180080e083d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4220" , 0x1180080e083e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4221" , 0x1180080e083e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4222" , 0x1180080e083f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4223" , 0x1180080e083f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4224" , 0x1180080e08400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4225" , 0x1180080e08408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4226" , 0x1180080e08410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4227" , 0x1180080e08418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4228" , 0x1180080e08420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4229" , 0x1180080e08428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4230" , 0x1180080e08430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4231" , 0x1180080e08438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4232" , 0x1180080e08440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4233" , 0x1180080e08448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4234" , 0x1180080e08450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4235" , 0x1180080e08458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4236" , 0x1180080e08460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4237" , 0x1180080e08468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4238" , 0x1180080e08470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4239" , 0x1180080e08478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4240" , 0x1180080e08480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4241" , 0x1180080e08488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4242" , 0x1180080e08490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4243" , 0x1180080e08498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4244" , 0x1180080e084a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4245" , 0x1180080e084a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4246" , 0x1180080e084b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4247" , 0x1180080e084b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4248" , 0x1180080e084c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4249" , 0x1180080e084c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4250" , 0x1180080e084d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4251" , 0x1180080e084d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4252" , 0x1180080e084e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4253" , 0x1180080e084e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4254" , 0x1180080e084f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4255" , 0x1180080e084f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4256" , 0x1180080e08500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4257" , 0x1180080e08508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4258" , 0x1180080e08510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4259" , 0x1180080e08518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4260" , 0x1180080e08520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4261" , 0x1180080e08528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4262" , 0x1180080e08530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4263" , 0x1180080e08538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4264" , 0x1180080e08540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4265" , 0x1180080e08548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4266" , 0x1180080e08550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4267" , 0x1180080e08558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4268" , 0x1180080e08560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4269" , 0x1180080e08568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4270" , 0x1180080e08570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4271" , 0x1180080e08578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4272" , 0x1180080e08580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4273" , 0x1180080e08588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4274" , 0x1180080e08590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4275" , 0x1180080e08598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4276" , 0x1180080e085a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4277" , 0x1180080e085a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4278" , 0x1180080e085b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4279" , 0x1180080e085b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4280" , 0x1180080e085c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4281" , 0x1180080e085c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4282" , 0x1180080e085d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4283" , 0x1180080e085d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4284" , 0x1180080e085e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4285" , 0x1180080e085e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4286" , 0x1180080e085f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4287" , 0x1180080e085f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4288" , 0x1180080e08600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4289" , 0x1180080e08608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4290" , 0x1180080e08610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4291" , 0x1180080e08618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4292" , 0x1180080e08620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4293" , 0x1180080e08628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4294" , 0x1180080e08630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4295" , 0x1180080e08638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4296" , 0x1180080e08640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4297" , 0x1180080e08648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4298" , 0x1180080e08650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4299" , 0x1180080e08658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4300" , 0x1180080e08660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4301" , 0x1180080e08668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4302" , 0x1180080e08670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4303" , 0x1180080e08678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4304" , 0x1180080e08680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4305" , 0x1180080e08688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4306" , 0x1180080e08690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4307" , 0x1180080e08698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4308" , 0x1180080e086a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4309" , 0x1180080e086a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4310" , 0x1180080e086b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4311" , 0x1180080e086b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4312" , 0x1180080e086c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4313" , 0x1180080e086c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4314" , 0x1180080e086d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4315" , 0x1180080e086d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4316" , 0x1180080e086e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4317" , 0x1180080e086e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4318" , 0x1180080e086f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4319" , 0x1180080e086f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4320" , 0x1180080e08700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4321" , 0x1180080e08708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4322" , 0x1180080e08710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4323" , 0x1180080e08718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4324" , 0x1180080e08720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4325" , 0x1180080e08728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4326" , 0x1180080e08730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4327" , 0x1180080e08738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4328" , 0x1180080e08740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4329" , 0x1180080e08748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4330" , 0x1180080e08750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4331" , 0x1180080e08758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4332" , 0x1180080e08760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4333" , 0x1180080e08768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4334" , 0x1180080e08770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4335" , 0x1180080e08778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4336" , 0x1180080e08780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4337" , 0x1180080e08788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4338" , 0x1180080e08790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4339" , 0x1180080e08798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4340" , 0x1180080e087a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4341" , 0x1180080e087a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4342" , 0x1180080e087b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4343" , 0x1180080e087b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4344" , 0x1180080e087c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4345" , 0x1180080e087c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4346" , 0x1180080e087d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4347" , 0x1180080e087d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4348" , 0x1180080e087e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4349" , 0x1180080e087e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4350" , 0x1180080e087f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4351" , 0x1180080e087f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4352" , 0x1180080e08800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4353" , 0x1180080e08808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4354" , 0x1180080e08810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4355" , 0x1180080e08818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4356" , 0x1180080e08820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4357" , 0x1180080e08828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4358" , 0x1180080e08830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4359" , 0x1180080e08838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4360" , 0x1180080e08840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4361" , 0x1180080e08848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4362" , 0x1180080e08850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4363" , 0x1180080e08858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4364" , 0x1180080e08860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4365" , 0x1180080e08868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4366" , 0x1180080e08870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4367" , 0x1180080e08878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4368" , 0x1180080e08880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4369" , 0x1180080e08888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4370" , 0x1180080e08890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4371" , 0x1180080e08898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4372" , 0x1180080e088a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4373" , 0x1180080e088a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4374" , 0x1180080e088b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4375" , 0x1180080e088b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4376" , 0x1180080e088c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4377" , 0x1180080e088c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4378" , 0x1180080e088d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4379" , 0x1180080e088d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4380" , 0x1180080e088e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4381" , 0x1180080e088e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4382" , 0x1180080e088f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4383" , 0x1180080e088f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4384" , 0x1180080e08900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4385" , 0x1180080e08908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4386" , 0x1180080e08910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4387" , 0x1180080e08918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4388" , 0x1180080e08920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4389" , 0x1180080e08928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4390" , 0x1180080e08930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4391" , 0x1180080e08938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4392" , 0x1180080e08940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4393" , 0x1180080e08948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4394" , 0x1180080e08950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4395" , 0x1180080e08958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4396" , 0x1180080e08960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4397" , 0x1180080e08968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4398" , 0x1180080e08970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4399" , 0x1180080e08978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4400" , 0x1180080e08980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4401" , 0x1180080e08988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4402" , 0x1180080e08990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4403" , 0x1180080e08998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4404" , 0x1180080e089a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4405" , 0x1180080e089a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4406" , 0x1180080e089b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4407" , 0x1180080e089b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4408" , 0x1180080e089c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4409" , 0x1180080e089c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4410" , 0x1180080e089d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4411" , 0x1180080e089d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4412" , 0x1180080e089e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4413" , 0x1180080e089e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4414" , 0x1180080e089f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4415" , 0x1180080e089f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4416" , 0x1180080e08a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4417" , 0x1180080e08a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4418" , 0x1180080e08a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4419" , 0x1180080e08a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4420" , 0x1180080e08a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4421" , 0x1180080e08a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4422" , 0x1180080e08a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4423" , 0x1180080e08a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4424" , 0x1180080e08a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4425" , 0x1180080e08a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4426" , 0x1180080e08a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4427" , 0x1180080e08a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4428" , 0x1180080e08a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4429" , 0x1180080e08a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4430" , 0x1180080e08a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4431" , 0x1180080e08a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4432" , 0x1180080e08a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4433" , 0x1180080e08a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4434" , 0x1180080e08a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4435" , 0x1180080e08a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4436" , 0x1180080e08aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4437" , 0x1180080e08aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4438" , 0x1180080e08ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4439" , 0x1180080e08ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4440" , 0x1180080e08ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4441" , 0x1180080e08ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4442" , 0x1180080e08ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4443" , 0x1180080e08ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4444" , 0x1180080e08ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4445" , 0x1180080e08ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4446" , 0x1180080e08af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4447" , 0x1180080e08af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4448" , 0x1180080e08b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4449" , 0x1180080e08b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4450" , 0x1180080e08b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4451" , 0x1180080e08b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4452" , 0x1180080e08b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4453" , 0x1180080e08b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4454" , 0x1180080e08b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4455" , 0x1180080e08b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4456" , 0x1180080e08b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4457" , 0x1180080e08b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4458" , 0x1180080e08b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4459" , 0x1180080e08b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4460" , 0x1180080e08b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4461" , 0x1180080e08b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4462" , 0x1180080e08b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4463" , 0x1180080e08b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4464" , 0x1180080e08b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4465" , 0x1180080e08b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4466" , 0x1180080e08b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4467" , 0x1180080e08b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4468" , 0x1180080e08ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4469" , 0x1180080e08ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4470" , 0x1180080e08bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4471" , 0x1180080e08bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4472" , 0x1180080e08bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4473" , 0x1180080e08bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4474" , 0x1180080e08bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4475" , 0x1180080e08bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4476" , 0x1180080e08be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4477" , 0x1180080e08be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4478" , 0x1180080e08bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4479" , 0x1180080e08bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4480" , 0x1180080e08c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4481" , 0x1180080e08c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4482" , 0x1180080e08c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4483" , 0x1180080e08c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4484" , 0x1180080e08c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4485" , 0x1180080e08c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4486" , 0x1180080e08c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4487" , 0x1180080e08c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4488" , 0x1180080e08c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4489" , 0x1180080e08c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4490" , 0x1180080e08c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4491" , 0x1180080e08c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4492" , 0x1180080e08c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4493" , 0x1180080e08c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4494" , 0x1180080e08c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4495" , 0x1180080e08c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4496" , 0x1180080e08c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4497" , 0x1180080e08c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4498" , 0x1180080e08c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4499" , 0x1180080e08c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4500" , 0x1180080e08ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4501" , 0x1180080e08ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4502" , 0x1180080e08cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4503" , 0x1180080e08cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4504" , 0x1180080e08cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4505" , 0x1180080e08cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4506" , 0x1180080e08cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4507" , 0x1180080e08cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4508" , 0x1180080e08ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4509" , 0x1180080e08ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4510" , 0x1180080e08cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4511" , 0x1180080e08cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4512" , 0x1180080e08d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4513" , 0x1180080e08d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4514" , 0x1180080e08d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4515" , 0x1180080e08d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4516" , 0x1180080e08d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4517" , 0x1180080e08d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4518" , 0x1180080e08d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4519" , 0x1180080e08d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4520" , 0x1180080e08d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4521" , 0x1180080e08d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4522" , 0x1180080e08d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4523" , 0x1180080e08d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4524" , 0x1180080e08d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4525" , 0x1180080e08d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4526" , 0x1180080e08d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4527" , 0x1180080e08d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4528" , 0x1180080e08d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4529" , 0x1180080e08d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4530" , 0x1180080e08d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4531" , 0x1180080e08d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4532" , 0x1180080e08da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4533" , 0x1180080e08da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4534" , 0x1180080e08db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4535" , 0x1180080e08db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4536" , 0x1180080e08dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4537" , 0x1180080e08dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4538" , 0x1180080e08dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4539" , 0x1180080e08dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4540" , 0x1180080e08de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4541" , 0x1180080e08de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4542" , 0x1180080e08df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4543" , 0x1180080e08df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4544" , 0x1180080e08e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4545" , 0x1180080e08e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4546" , 0x1180080e08e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4547" , 0x1180080e08e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4548" , 0x1180080e08e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4549" , 0x1180080e08e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4550" , 0x1180080e08e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4551" , 0x1180080e08e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4552" , 0x1180080e08e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4553" , 0x1180080e08e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4554" , 0x1180080e08e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4555" , 0x1180080e08e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4556" , 0x1180080e08e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4557" , 0x1180080e08e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4558" , 0x1180080e08e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4559" , 0x1180080e08e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4560" , 0x1180080e08e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4561" , 0x1180080e08e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4562" , 0x1180080e08e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4563" , 0x1180080e08e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4564" , 0x1180080e08ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4565" , 0x1180080e08ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4566" , 0x1180080e08eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4567" , 0x1180080e08eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4568" , 0x1180080e08ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4569" , 0x1180080e08ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4570" , 0x1180080e08ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4571" , 0x1180080e08ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4572" , 0x1180080e08ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4573" , 0x1180080e08ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4574" , 0x1180080e08ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4575" , 0x1180080e08ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4576" , 0x1180080e08f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4577" , 0x1180080e08f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4578" , 0x1180080e08f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4579" , 0x1180080e08f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4580" , 0x1180080e08f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4581" , 0x1180080e08f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4582" , 0x1180080e08f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4583" , 0x1180080e08f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4584" , 0x1180080e08f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4585" , 0x1180080e08f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4586" , 0x1180080e08f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4587" , 0x1180080e08f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4588" , 0x1180080e08f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4589" , 0x1180080e08f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4590" , 0x1180080e08f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4591" , 0x1180080e08f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4592" , 0x1180080e08f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4593" , 0x1180080e08f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4594" , 0x1180080e08f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4595" , 0x1180080e08f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4596" , 0x1180080e08fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4597" , 0x1180080e08fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4598" , 0x1180080e08fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4599" , 0x1180080e08fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4600" , 0x1180080e08fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4601" , 0x1180080e08fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4602" , 0x1180080e08fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4603" , 0x1180080e08fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4604" , 0x1180080e08fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4605" , 0x1180080e08fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4606" , 0x1180080e08ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4607" , 0x1180080e08ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4608" , 0x1180080e09000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4609" , 0x1180080e09008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4610" , 0x1180080e09010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4611" , 0x1180080e09018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4612" , 0x1180080e09020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4613" , 0x1180080e09028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4614" , 0x1180080e09030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4615" , 0x1180080e09038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4616" , 0x1180080e09040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4617" , 0x1180080e09048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4618" , 0x1180080e09050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4619" , 0x1180080e09058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4620" , 0x1180080e09060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4621" , 0x1180080e09068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4622" , 0x1180080e09070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4623" , 0x1180080e09078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4624" , 0x1180080e09080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4625" , 0x1180080e09088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4626" , 0x1180080e09090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4627" , 0x1180080e09098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4628" , 0x1180080e090a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4629" , 0x1180080e090a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4630" , 0x1180080e090b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4631" , 0x1180080e090b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4632" , 0x1180080e090c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4633" , 0x1180080e090c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4634" , 0x1180080e090d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4635" , 0x1180080e090d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4636" , 0x1180080e090e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4637" , 0x1180080e090e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4638" , 0x1180080e090f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4639" , 0x1180080e090f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4640" , 0x1180080e09100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4641" , 0x1180080e09108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4642" , 0x1180080e09110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4643" , 0x1180080e09118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4644" , 0x1180080e09120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4645" , 0x1180080e09128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4646" , 0x1180080e09130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4647" , 0x1180080e09138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4648" , 0x1180080e09140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4649" , 0x1180080e09148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4650" , 0x1180080e09150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4651" , 0x1180080e09158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4652" , 0x1180080e09160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4653" , 0x1180080e09168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4654" , 0x1180080e09170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4655" , 0x1180080e09178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4656" , 0x1180080e09180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4657" , 0x1180080e09188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4658" , 0x1180080e09190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4659" , 0x1180080e09198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4660" , 0x1180080e091a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4661" , 0x1180080e091a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4662" , 0x1180080e091b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4663" , 0x1180080e091b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4664" , 0x1180080e091c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4665" , 0x1180080e091c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4666" , 0x1180080e091d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4667" , 0x1180080e091d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4668" , 0x1180080e091e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4669" , 0x1180080e091e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4670" , 0x1180080e091f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4671" , 0x1180080e091f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4672" , 0x1180080e09200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4673" , 0x1180080e09208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4674" , 0x1180080e09210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4675" , 0x1180080e09218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4676" , 0x1180080e09220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4677" , 0x1180080e09228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4678" , 0x1180080e09230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4679" , 0x1180080e09238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4680" , 0x1180080e09240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4681" , 0x1180080e09248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4682" , 0x1180080e09250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4683" , 0x1180080e09258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4684" , 0x1180080e09260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4685" , 0x1180080e09268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4686" , 0x1180080e09270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4687" , 0x1180080e09278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4688" , 0x1180080e09280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4689" , 0x1180080e09288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4690" , 0x1180080e09290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4691" , 0x1180080e09298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4692" , 0x1180080e092a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4693" , 0x1180080e092a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4694" , 0x1180080e092b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4695" , 0x1180080e092b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4696" , 0x1180080e092c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4697" , 0x1180080e092c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4698" , 0x1180080e092d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4699" , 0x1180080e092d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4700" , 0x1180080e092e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4701" , 0x1180080e092e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4702" , 0x1180080e092f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4703" , 0x1180080e092f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4704" , 0x1180080e09300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4705" , 0x1180080e09308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4706" , 0x1180080e09310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4707" , 0x1180080e09318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4708" , 0x1180080e09320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4709" , 0x1180080e09328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4710" , 0x1180080e09330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4711" , 0x1180080e09338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4712" , 0x1180080e09340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4713" , 0x1180080e09348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4714" , 0x1180080e09350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4715" , 0x1180080e09358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4716" , 0x1180080e09360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4717" , 0x1180080e09368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4718" , 0x1180080e09370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4719" , 0x1180080e09378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4720" , 0x1180080e09380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4721" , 0x1180080e09388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4722" , 0x1180080e09390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4723" , 0x1180080e09398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4724" , 0x1180080e093a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4725" , 0x1180080e093a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4726" , 0x1180080e093b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4727" , 0x1180080e093b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4728" , 0x1180080e093c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4729" , 0x1180080e093c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4730" , 0x1180080e093d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4731" , 0x1180080e093d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4732" , 0x1180080e093e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4733" , 0x1180080e093e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4734" , 0x1180080e093f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4735" , 0x1180080e093f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4736" , 0x1180080e09400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4737" , 0x1180080e09408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4738" , 0x1180080e09410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4739" , 0x1180080e09418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4740" , 0x1180080e09420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4741" , 0x1180080e09428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4742" , 0x1180080e09430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4743" , 0x1180080e09438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4744" , 0x1180080e09440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4745" , 0x1180080e09448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4746" , 0x1180080e09450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4747" , 0x1180080e09458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4748" , 0x1180080e09460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4749" , 0x1180080e09468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4750" , 0x1180080e09470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4751" , 0x1180080e09478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4752" , 0x1180080e09480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4753" , 0x1180080e09488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4754" , 0x1180080e09490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4755" , 0x1180080e09498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4756" , 0x1180080e094a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4757" , 0x1180080e094a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4758" , 0x1180080e094b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4759" , 0x1180080e094b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4760" , 0x1180080e094c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4761" , 0x1180080e094c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4762" , 0x1180080e094d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4763" , 0x1180080e094d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4764" , 0x1180080e094e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4765" , 0x1180080e094e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4766" , 0x1180080e094f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4767" , 0x1180080e094f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4768" , 0x1180080e09500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4769" , 0x1180080e09508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4770" , 0x1180080e09510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4771" , 0x1180080e09518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4772" , 0x1180080e09520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4773" , 0x1180080e09528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4774" , 0x1180080e09530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4775" , 0x1180080e09538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4776" , 0x1180080e09540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4777" , 0x1180080e09548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4778" , 0x1180080e09550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4779" , 0x1180080e09558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4780" , 0x1180080e09560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4781" , 0x1180080e09568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4782" , 0x1180080e09570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4783" , 0x1180080e09578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4784" , 0x1180080e09580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4785" , 0x1180080e09588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4786" , 0x1180080e09590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4787" , 0x1180080e09598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4788" , 0x1180080e095a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4789" , 0x1180080e095a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4790" , 0x1180080e095b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4791" , 0x1180080e095b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4792" , 0x1180080e095c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4793" , 0x1180080e095c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4794" , 0x1180080e095d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4795" , 0x1180080e095d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4796" , 0x1180080e095e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4797" , 0x1180080e095e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4798" , 0x1180080e095f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4799" , 0x1180080e095f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4800" , 0x1180080e09600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4801" , 0x1180080e09608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4802" , 0x1180080e09610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4803" , 0x1180080e09618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4804" , 0x1180080e09620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4805" , 0x1180080e09628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4806" , 0x1180080e09630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4807" , 0x1180080e09638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4808" , 0x1180080e09640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4809" , 0x1180080e09648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4810" , 0x1180080e09650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4811" , 0x1180080e09658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4812" , 0x1180080e09660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4813" , 0x1180080e09668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4814" , 0x1180080e09670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4815" , 0x1180080e09678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4816" , 0x1180080e09680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4817" , 0x1180080e09688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4818" , 0x1180080e09690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4819" , 0x1180080e09698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4820" , 0x1180080e096a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4821" , 0x1180080e096a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4822" , 0x1180080e096b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4823" , 0x1180080e096b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4824" , 0x1180080e096c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4825" , 0x1180080e096c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4826" , 0x1180080e096d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4827" , 0x1180080e096d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4828" , 0x1180080e096e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4829" , 0x1180080e096e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4830" , 0x1180080e096f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4831" , 0x1180080e096f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4832" , 0x1180080e09700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4833" , 0x1180080e09708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4834" , 0x1180080e09710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4835" , 0x1180080e09718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4836" , 0x1180080e09720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4837" , 0x1180080e09728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4838" , 0x1180080e09730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4839" , 0x1180080e09738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4840" , 0x1180080e09740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4841" , 0x1180080e09748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4842" , 0x1180080e09750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4843" , 0x1180080e09758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4844" , 0x1180080e09760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4845" , 0x1180080e09768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4846" , 0x1180080e09770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4847" , 0x1180080e09778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4848" , 0x1180080e09780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4849" , 0x1180080e09788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4850" , 0x1180080e09790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4851" , 0x1180080e09798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4852" , 0x1180080e097a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4853" , 0x1180080e097a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4854" , 0x1180080e097b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4855" , 0x1180080e097b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4856" , 0x1180080e097c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4857" , 0x1180080e097c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4858" , 0x1180080e097d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4859" , 0x1180080e097d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4860" , 0x1180080e097e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4861" , 0x1180080e097e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4862" , 0x1180080e097f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4863" , 0x1180080e097f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4864" , 0x1180080e09800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4865" , 0x1180080e09808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4866" , 0x1180080e09810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4867" , 0x1180080e09818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4868" , 0x1180080e09820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4869" , 0x1180080e09828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4870" , 0x1180080e09830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4871" , 0x1180080e09838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4872" , 0x1180080e09840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4873" , 0x1180080e09848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4874" , 0x1180080e09850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4875" , 0x1180080e09858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4876" , 0x1180080e09860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4877" , 0x1180080e09868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4878" , 0x1180080e09870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4879" , 0x1180080e09878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4880" , 0x1180080e09880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4881" , 0x1180080e09888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4882" , 0x1180080e09890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4883" , 0x1180080e09898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4884" , 0x1180080e098a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4885" , 0x1180080e098a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4886" , 0x1180080e098b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4887" , 0x1180080e098b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4888" , 0x1180080e098c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4889" , 0x1180080e098c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4890" , 0x1180080e098d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4891" , 0x1180080e098d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4892" , 0x1180080e098e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4893" , 0x1180080e098e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4894" , 0x1180080e098f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4895" , 0x1180080e098f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4896" , 0x1180080e09900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4897" , 0x1180080e09908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4898" , 0x1180080e09910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4899" , 0x1180080e09918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4900" , 0x1180080e09920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4901" , 0x1180080e09928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4902" , 0x1180080e09930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4903" , 0x1180080e09938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4904" , 0x1180080e09940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4905" , 0x1180080e09948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4906" , 0x1180080e09950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4907" , 0x1180080e09958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4908" , 0x1180080e09960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4909" , 0x1180080e09968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4910" , 0x1180080e09970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4911" , 0x1180080e09978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4912" , 0x1180080e09980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4913" , 0x1180080e09988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4914" , 0x1180080e09990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4915" , 0x1180080e09998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4916" , 0x1180080e099a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4917" , 0x1180080e099a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4918" , 0x1180080e099b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4919" , 0x1180080e099b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4920" , 0x1180080e099c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4921" , 0x1180080e099c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4922" , 0x1180080e099d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4923" , 0x1180080e099d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4924" , 0x1180080e099e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4925" , 0x1180080e099e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4926" , 0x1180080e099f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4927" , 0x1180080e099f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4928" , 0x1180080e09a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4929" , 0x1180080e09a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4930" , 0x1180080e09a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4931" , 0x1180080e09a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4932" , 0x1180080e09a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4933" , 0x1180080e09a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4934" , 0x1180080e09a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4935" , 0x1180080e09a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4936" , 0x1180080e09a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4937" , 0x1180080e09a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4938" , 0x1180080e09a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4939" , 0x1180080e09a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4940" , 0x1180080e09a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4941" , 0x1180080e09a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4942" , 0x1180080e09a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4943" , 0x1180080e09a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4944" , 0x1180080e09a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4945" , 0x1180080e09a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4946" , 0x1180080e09a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4947" , 0x1180080e09a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4948" , 0x1180080e09aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4949" , 0x1180080e09aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4950" , 0x1180080e09ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4951" , 0x1180080e09ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4952" , 0x1180080e09ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4953" , 0x1180080e09ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4954" , 0x1180080e09ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4955" , 0x1180080e09ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4956" , 0x1180080e09ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4957" , 0x1180080e09ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4958" , 0x1180080e09af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4959" , 0x1180080e09af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4960" , 0x1180080e09b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4961" , 0x1180080e09b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4962" , 0x1180080e09b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4963" , 0x1180080e09b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4964" , 0x1180080e09b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4965" , 0x1180080e09b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4966" , 0x1180080e09b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4967" , 0x1180080e09b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4968" , 0x1180080e09b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4969" , 0x1180080e09b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4970" , 0x1180080e09b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4971" , 0x1180080e09b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4972" , 0x1180080e09b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4973" , 0x1180080e09b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4974" , 0x1180080e09b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4975" , 0x1180080e09b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4976" , 0x1180080e09b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4977" , 0x1180080e09b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4978" , 0x1180080e09b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4979" , 0x1180080e09b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4980" , 0x1180080e09ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4981" , 0x1180080e09ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4982" , 0x1180080e09bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4983" , 0x1180080e09bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4984" , 0x1180080e09bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4985" , 0x1180080e09bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4986" , 0x1180080e09bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4987" , 0x1180080e09bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4988" , 0x1180080e09be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4989" , 0x1180080e09be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4990" , 0x1180080e09bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4991" , 0x1180080e09bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4992" , 0x1180080e09c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4993" , 0x1180080e09c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4994" , 0x1180080e09c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4995" , 0x1180080e09c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4996" , 0x1180080e09c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4997" , 0x1180080e09c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4998" , 0x1180080e09c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP4999" , 0x1180080e09c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5000" , 0x1180080e09c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5001" , 0x1180080e09c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5002" , 0x1180080e09c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5003" , 0x1180080e09c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5004" , 0x1180080e09c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5005" , 0x1180080e09c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5006" , 0x1180080e09c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5007" , 0x1180080e09c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5008" , 0x1180080e09c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5009" , 0x1180080e09c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5010" , 0x1180080e09c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5011" , 0x1180080e09c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5012" , 0x1180080e09ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5013" , 0x1180080e09ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5014" , 0x1180080e09cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5015" , 0x1180080e09cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5016" , 0x1180080e09cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5017" , 0x1180080e09cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5018" , 0x1180080e09cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5019" , 0x1180080e09cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5020" , 0x1180080e09ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5021" , 0x1180080e09ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5022" , 0x1180080e09cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5023" , 0x1180080e09cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5024" , 0x1180080e09d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5025" , 0x1180080e09d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5026" , 0x1180080e09d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5027" , 0x1180080e09d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5028" , 0x1180080e09d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5029" , 0x1180080e09d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5030" , 0x1180080e09d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5031" , 0x1180080e09d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5032" , 0x1180080e09d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5033" , 0x1180080e09d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5034" , 0x1180080e09d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5035" , 0x1180080e09d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5036" , 0x1180080e09d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5037" , 0x1180080e09d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5038" , 0x1180080e09d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5039" , 0x1180080e09d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5040" , 0x1180080e09d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5041" , 0x1180080e09d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5042" , 0x1180080e09d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5043" , 0x1180080e09d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5044" , 0x1180080e09da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5045" , 0x1180080e09da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5046" , 0x1180080e09db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5047" , 0x1180080e09db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5048" , 0x1180080e09dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5049" , 0x1180080e09dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5050" , 0x1180080e09dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5051" , 0x1180080e09dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5052" , 0x1180080e09de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5053" , 0x1180080e09de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5054" , 0x1180080e09df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5055" , 0x1180080e09df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5056" , 0x1180080e09e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5057" , 0x1180080e09e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5058" , 0x1180080e09e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5059" , 0x1180080e09e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5060" , 0x1180080e09e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5061" , 0x1180080e09e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5062" , 0x1180080e09e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5063" , 0x1180080e09e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5064" , 0x1180080e09e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5065" , 0x1180080e09e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5066" , 0x1180080e09e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5067" , 0x1180080e09e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5068" , 0x1180080e09e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5069" , 0x1180080e09e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5070" , 0x1180080e09e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5071" , 0x1180080e09e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5072" , 0x1180080e09e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5073" , 0x1180080e09e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5074" , 0x1180080e09e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5075" , 0x1180080e09e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5076" , 0x1180080e09ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5077" , 0x1180080e09ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5078" , 0x1180080e09eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5079" , 0x1180080e09eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5080" , 0x1180080e09ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5081" , 0x1180080e09ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5082" , 0x1180080e09ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5083" , 0x1180080e09ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5084" , 0x1180080e09ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5085" , 0x1180080e09ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5086" , 0x1180080e09ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5087" , 0x1180080e09ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5088" , 0x1180080e09f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5089" , 0x1180080e09f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5090" , 0x1180080e09f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5091" , 0x1180080e09f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5092" , 0x1180080e09f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5093" , 0x1180080e09f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5094" , 0x1180080e09f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5095" , 0x1180080e09f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5096" , 0x1180080e09f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5097" , 0x1180080e09f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5098" , 0x1180080e09f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5099" , 0x1180080e09f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5100" , 0x1180080e09f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5101" , 0x1180080e09f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5102" , 0x1180080e09f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5103" , 0x1180080e09f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5104" , 0x1180080e09f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5105" , 0x1180080e09f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5106" , 0x1180080e09f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5107" , 0x1180080e09f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5108" , 0x1180080e09fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5109" , 0x1180080e09fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5110" , 0x1180080e09fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5111" , 0x1180080e09fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5112" , 0x1180080e09fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5113" , 0x1180080e09fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5114" , 0x1180080e09fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5115" , 0x1180080e09fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5116" , 0x1180080e09fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5117" , 0x1180080e09fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5118" , 0x1180080e09ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5119" , 0x1180080e09ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5120" , 0x1180080e0a000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5121" , 0x1180080e0a008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5122" , 0x1180080e0a010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5123" , 0x1180080e0a018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5124" , 0x1180080e0a020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5125" , 0x1180080e0a028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5126" , 0x1180080e0a030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5127" , 0x1180080e0a038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5128" , 0x1180080e0a040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5129" , 0x1180080e0a048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5130" , 0x1180080e0a050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5131" , 0x1180080e0a058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5132" , 0x1180080e0a060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5133" , 0x1180080e0a068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5134" , 0x1180080e0a070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5135" , 0x1180080e0a078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5136" , 0x1180080e0a080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5137" , 0x1180080e0a088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5138" , 0x1180080e0a090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5139" , 0x1180080e0a098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5140" , 0x1180080e0a0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5141" , 0x1180080e0a0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5142" , 0x1180080e0a0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5143" , 0x1180080e0a0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5144" , 0x1180080e0a0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5145" , 0x1180080e0a0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5146" , 0x1180080e0a0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5147" , 0x1180080e0a0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5148" , 0x1180080e0a0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5149" , 0x1180080e0a0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5150" , 0x1180080e0a0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5151" , 0x1180080e0a0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5152" , 0x1180080e0a100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5153" , 0x1180080e0a108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5154" , 0x1180080e0a110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5155" , 0x1180080e0a118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5156" , 0x1180080e0a120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5157" , 0x1180080e0a128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5158" , 0x1180080e0a130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5159" , 0x1180080e0a138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5160" , 0x1180080e0a140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5161" , 0x1180080e0a148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5162" , 0x1180080e0a150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5163" , 0x1180080e0a158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5164" , 0x1180080e0a160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5165" , 0x1180080e0a168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5166" , 0x1180080e0a170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5167" , 0x1180080e0a178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5168" , 0x1180080e0a180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5169" , 0x1180080e0a188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5170" , 0x1180080e0a190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5171" , 0x1180080e0a198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5172" , 0x1180080e0a1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5173" , 0x1180080e0a1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5174" , 0x1180080e0a1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5175" , 0x1180080e0a1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5176" , 0x1180080e0a1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5177" , 0x1180080e0a1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5178" , 0x1180080e0a1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5179" , 0x1180080e0a1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5180" , 0x1180080e0a1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5181" , 0x1180080e0a1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5182" , 0x1180080e0a1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5183" , 0x1180080e0a1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5184" , 0x1180080e0a200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5185" , 0x1180080e0a208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5186" , 0x1180080e0a210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5187" , 0x1180080e0a218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5188" , 0x1180080e0a220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5189" , 0x1180080e0a228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5190" , 0x1180080e0a230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5191" , 0x1180080e0a238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5192" , 0x1180080e0a240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5193" , 0x1180080e0a248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5194" , 0x1180080e0a250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5195" , 0x1180080e0a258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5196" , 0x1180080e0a260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5197" , 0x1180080e0a268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5198" , 0x1180080e0a270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5199" , 0x1180080e0a278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5200" , 0x1180080e0a280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5201" , 0x1180080e0a288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5202" , 0x1180080e0a290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5203" , 0x1180080e0a298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5204" , 0x1180080e0a2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5205" , 0x1180080e0a2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5206" , 0x1180080e0a2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5207" , 0x1180080e0a2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5208" , 0x1180080e0a2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5209" , 0x1180080e0a2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5210" , 0x1180080e0a2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5211" , 0x1180080e0a2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5212" , 0x1180080e0a2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5213" , 0x1180080e0a2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5214" , 0x1180080e0a2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5215" , 0x1180080e0a2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5216" , 0x1180080e0a300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5217" , 0x1180080e0a308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5218" , 0x1180080e0a310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5219" , 0x1180080e0a318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5220" , 0x1180080e0a320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5221" , 0x1180080e0a328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5222" , 0x1180080e0a330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5223" , 0x1180080e0a338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5224" , 0x1180080e0a340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5225" , 0x1180080e0a348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5226" , 0x1180080e0a350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5227" , 0x1180080e0a358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5228" , 0x1180080e0a360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5229" , 0x1180080e0a368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5230" , 0x1180080e0a370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5231" , 0x1180080e0a378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5232" , 0x1180080e0a380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5233" , 0x1180080e0a388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5234" , 0x1180080e0a390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5235" , 0x1180080e0a398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5236" , 0x1180080e0a3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5237" , 0x1180080e0a3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5238" , 0x1180080e0a3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5239" , 0x1180080e0a3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5240" , 0x1180080e0a3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5241" , 0x1180080e0a3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5242" , 0x1180080e0a3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5243" , 0x1180080e0a3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5244" , 0x1180080e0a3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5245" , 0x1180080e0a3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5246" , 0x1180080e0a3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5247" , 0x1180080e0a3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5248" , 0x1180080e0a400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5249" , 0x1180080e0a408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5250" , 0x1180080e0a410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5251" , 0x1180080e0a418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5252" , 0x1180080e0a420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5253" , 0x1180080e0a428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5254" , 0x1180080e0a430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5255" , 0x1180080e0a438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5256" , 0x1180080e0a440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5257" , 0x1180080e0a448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5258" , 0x1180080e0a450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5259" , 0x1180080e0a458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5260" , 0x1180080e0a460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5261" , 0x1180080e0a468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5262" , 0x1180080e0a470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5263" , 0x1180080e0a478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5264" , 0x1180080e0a480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5265" , 0x1180080e0a488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5266" , 0x1180080e0a490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5267" , 0x1180080e0a498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5268" , 0x1180080e0a4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5269" , 0x1180080e0a4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5270" , 0x1180080e0a4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5271" , 0x1180080e0a4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5272" , 0x1180080e0a4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5273" , 0x1180080e0a4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5274" , 0x1180080e0a4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5275" , 0x1180080e0a4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5276" , 0x1180080e0a4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5277" , 0x1180080e0a4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5278" , 0x1180080e0a4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5279" , 0x1180080e0a4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5280" , 0x1180080e0a500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5281" , 0x1180080e0a508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5282" , 0x1180080e0a510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5283" , 0x1180080e0a518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5284" , 0x1180080e0a520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5285" , 0x1180080e0a528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5286" , 0x1180080e0a530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5287" , 0x1180080e0a538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5288" , 0x1180080e0a540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5289" , 0x1180080e0a548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5290" , 0x1180080e0a550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5291" , 0x1180080e0a558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5292" , 0x1180080e0a560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5293" , 0x1180080e0a568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5294" , 0x1180080e0a570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5295" , 0x1180080e0a578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5296" , 0x1180080e0a580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5297" , 0x1180080e0a588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5298" , 0x1180080e0a590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5299" , 0x1180080e0a598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5300" , 0x1180080e0a5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5301" , 0x1180080e0a5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5302" , 0x1180080e0a5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5303" , 0x1180080e0a5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5304" , 0x1180080e0a5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5305" , 0x1180080e0a5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5306" , 0x1180080e0a5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5307" , 0x1180080e0a5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5308" , 0x1180080e0a5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5309" , 0x1180080e0a5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5310" , 0x1180080e0a5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5311" , 0x1180080e0a5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5312" , 0x1180080e0a600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5313" , 0x1180080e0a608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5314" , 0x1180080e0a610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5315" , 0x1180080e0a618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5316" , 0x1180080e0a620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5317" , 0x1180080e0a628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5318" , 0x1180080e0a630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5319" , 0x1180080e0a638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5320" , 0x1180080e0a640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5321" , 0x1180080e0a648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5322" , 0x1180080e0a650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5323" , 0x1180080e0a658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5324" , 0x1180080e0a660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5325" , 0x1180080e0a668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5326" , 0x1180080e0a670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5327" , 0x1180080e0a678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5328" , 0x1180080e0a680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5329" , 0x1180080e0a688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5330" , 0x1180080e0a690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5331" , 0x1180080e0a698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5332" , 0x1180080e0a6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5333" , 0x1180080e0a6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5334" , 0x1180080e0a6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5335" , 0x1180080e0a6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5336" , 0x1180080e0a6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5337" , 0x1180080e0a6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5338" , 0x1180080e0a6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5339" , 0x1180080e0a6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5340" , 0x1180080e0a6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5341" , 0x1180080e0a6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5342" , 0x1180080e0a6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5343" , 0x1180080e0a6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5344" , 0x1180080e0a700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5345" , 0x1180080e0a708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5346" , 0x1180080e0a710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5347" , 0x1180080e0a718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5348" , 0x1180080e0a720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5349" , 0x1180080e0a728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5350" , 0x1180080e0a730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5351" , 0x1180080e0a738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5352" , 0x1180080e0a740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5353" , 0x1180080e0a748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5354" , 0x1180080e0a750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5355" , 0x1180080e0a758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5356" , 0x1180080e0a760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5357" , 0x1180080e0a768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5358" , 0x1180080e0a770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5359" , 0x1180080e0a778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5360" , 0x1180080e0a780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5361" , 0x1180080e0a788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5362" , 0x1180080e0a790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5363" , 0x1180080e0a798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5364" , 0x1180080e0a7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5365" , 0x1180080e0a7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5366" , 0x1180080e0a7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5367" , 0x1180080e0a7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5368" , 0x1180080e0a7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5369" , 0x1180080e0a7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5370" , 0x1180080e0a7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5371" , 0x1180080e0a7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5372" , 0x1180080e0a7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5373" , 0x1180080e0a7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5374" , 0x1180080e0a7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5375" , 0x1180080e0a7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5376" , 0x1180080e0a800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5377" , 0x1180080e0a808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5378" , 0x1180080e0a810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5379" , 0x1180080e0a818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5380" , 0x1180080e0a820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5381" , 0x1180080e0a828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5382" , 0x1180080e0a830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5383" , 0x1180080e0a838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5384" , 0x1180080e0a840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5385" , 0x1180080e0a848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5386" , 0x1180080e0a850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5387" , 0x1180080e0a858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5388" , 0x1180080e0a860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5389" , 0x1180080e0a868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5390" , 0x1180080e0a870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5391" , 0x1180080e0a878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5392" , 0x1180080e0a880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5393" , 0x1180080e0a888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5394" , 0x1180080e0a890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5395" , 0x1180080e0a898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5396" , 0x1180080e0a8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5397" , 0x1180080e0a8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5398" , 0x1180080e0a8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5399" , 0x1180080e0a8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5400" , 0x1180080e0a8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5401" , 0x1180080e0a8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5402" , 0x1180080e0a8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5403" , 0x1180080e0a8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5404" , 0x1180080e0a8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5405" , 0x1180080e0a8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5406" , 0x1180080e0a8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5407" , 0x1180080e0a8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5408" , 0x1180080e0a900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5409" , 0x1180080e0a908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5410" , 0x1180080e0a910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5411" , 0x1180080e0a918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5412" , 0x1180080e0a920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5413" , 0x1180080e0a928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5414" , 0x1180080e0a930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5415" , 0x1180080e0a938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5416" , 0x1180080e0a940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5417" , 0x1180080e0a948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5418" , 0x1180080e0a950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5419" , 0x1180080e0a958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5420" , 0x1180080e0a960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5421" , 0x1180080e0a968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5422" , 0x1180080e0a970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5423" , 0x1180080e0a978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5424" , 0x1180080e0a980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5425" , 0x1180080e0a988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5426" , 0x1180080e0a990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5427" , 0x1180080e0a998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5428" , 0x1180080e0a9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5429" , 0x1180080e0a9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5430" , 0x1180080e0a9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5431" , 0x1180080e0a9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5432" , 0x1180080e0a9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5433" , 0x1180080e0a9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5434" , 0x1180080e0a9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5435" , 0x1180080e0a9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5436" , 0x1180080e0a9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5437" , 0x1180080e0a9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5438" , 0x1180080e0a9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5439" , 0x1180080e0a9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5440" , 0x1180080e0aa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5441" , 0x1180080e0aa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5442" , 0x1180080e0aa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5443" , 0x1180080e0aa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5444" , 0x1180080e0aa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5445" , 0x1180080e0aa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5446" , 0x1180080e0aa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5447" , 0x1180080e0aa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5448" , 0x1180080e0aa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5449" , 0x1180080e0aa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5450" , 0x1180080e0aa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5451" , 0x1180080e0aa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5452" , 0x1180080e0aa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5453" , 0x1180080e0aa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5454" , 0x1180080e0aa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5455" , 0x1180080e0aa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5456" , 0x1180080e0aa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5457" , 0x1180080e0aa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5458" , 0x1180080e0aa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5459" , 0x1180080e0aa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5460" , 0x1180080e0aaa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5461" , 0x1180080e0aaa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5462" , 0x1180080e0aab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5463" , 0x1180080e0aab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5464" , 0x1180080e0aac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5465" , 0x1180080e0aac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5466" , 0x1180080e0aad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5467" , 0x1180080e0aad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5468" , 0x1180080e0aae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5469" , 0x1180080e0aae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5470" , 0x1180080e0aaf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5471" , 0x1180080e0aaf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5472" , 0x1180080e0ab00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5473" , 0x1180080e0ab08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5474" , 0x1180080e0ab10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5475" , 0x1180080e0ab18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5476" , 0x1180080e0ab20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5477" , 0x1180080e0ab28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5478" , 0x1180080e0ab30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5479" , 0x1180080e0ab38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5480" , 0x1180080e0ab40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5481" , 0x1180080e0ab48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5482" , 0x1180080e0ab50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5483" , 0x1180080e0ab58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5484" , 0x1180080e0ab60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5485" , 0x1180080e0ab68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5486" , 0x1180080e0ab70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5487" , 0x1180080e0ab78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5488" , 0x1180080e0ab80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5489" , 0x1180080e0ab88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5490" , 0x1180080e0ab90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5491" , 0x1180080e0ab98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5492" , 0x1180080e0aba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5493" , 0x1180080e0aba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5494" , 0x1180080e0abb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5495" , 0x1180080e0abb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5496" , 0x1180080e0abc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5497" , 0x1180080e0abc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5498" , 0x1180080e0abd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5499" , 0x1180080e0abd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5500" , 0x1180080e0abe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5501" , 0x1180080e0abe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5502" , 0x1180080e0abf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5503" , 0x1180080e0abf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5504" , 0x1180080e0ac00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5505" , 0x1180080e0ac08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5506" , 0x1180080e0ac10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5507" , 0x1180080e0ac18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5508" , 0x1180080e0ac20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5509" , 0x1180080e0ac28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5510" , 0x1180080e0ac30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5511" , 0x1180080e0ac38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5512" , 0x1180080e0ac40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5513" , 0x1180080e0ac48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5514" , 0x1180080e0ac50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5515" , 0x1180080e0ac58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5516" , 0x1180080e0ac60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5517" , 0x1180080e0ac68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5518" , 0x1180080e0ac70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5519" , 0x1180080e0ac78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5520" , 0x1180080e0ac80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5521" , 0x1180080e0ac88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5522" , 0x1180080e0ac90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5523" , 0x1180080e0ac98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5524" , 0x1180080e0aca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5525" , 0x1180080e0aca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5526" , 0x1180080e0acb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5527" , 0x1180080e0acb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5528" , 0x1180080e0acc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5529" , 0x1180080e0acc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5530" , 0x1180080e0acd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5531" , 0x1180080e0acd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5532" , 0x1180080e0ace0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5533" , 0x1180080e0ace8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5534" , 0x1180080e0acf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5535" , 0x1180080e0acf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5536" , 0x1180080e0ad00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5537" , 0x1180080e0ad08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5538" , 0x1180080e0ad10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5539" , 0x1180080e0ad18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5540" , 0x1180080e0ad20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5541" , 0x1180080e0ad28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5542" , 0x1180080e0ad30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5543" , 0x1180080e0ad38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5544" , 0x1180080e0ad40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5545" , 0x1180080e0ad48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5546" , 0x1180080e0ad50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5547" , 0x1180080e0ad58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5548" , 0x1180080e0ad60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5549" , 0x1180080e0ad68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5550" , 0x1180080e0ad70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5551" , 0x1180080e0ad78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5552" , 0x1180080e0ad80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5553" , 0x1180080e0ad88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5554" , 0x1180080e0ad90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5555" , 0x1180080e0ad98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5556" , 0x1180080e0ada0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5557" , 0x1180080e0ada8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5558" , 0x1180080e0adb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5559" , 0x1180080e0adb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5560" , 0x1180080e0adc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5561" , 0x1180080e0adc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5562" , 0x1180080e0add0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5563" , 0x1180080e0add8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5564" , 0x1180080e0ade0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5565" , 0x1180080e0ade8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5566" , 0x1180080e0adf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5567" , 0x1180080e0adf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5568" , 0x1180080e0ae00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5569" , 0x1180080e0ae08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5570" , 0x1180080e0ae10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5571" , 0x1180080e0ae18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5572" , 0x1180080e0ae20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5573" , 0x1180080e0ae28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5574" , 0x1180080e0ae30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5575" , 0x1180080e0ae38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5576" , 0x1180080e0ae40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5577" , 0x1180080e0ae48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5578" , 0x1180080e0ae50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5579" , 0x1180080e0ae58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5580" , 0x1180080e0ae60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5581" , 0x1180080e0ae68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5582" , 0x1180080e0ae70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5583" , 0x1180080e0ae78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5584" , 0x1180080e0ae80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5585" , 0x1180080e0ae88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5586" , 0x1180080e0ae90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5587" , 0x1180080e0ae98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5588" , 0x1180080e0aea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5589" , 0x1180080e0aea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5590" , 0x1180080e0aeb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5591" , 0x1180080e0aeb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5592" , 0x1180080e0aec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5593" , 0x1180080e0aec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5594" , 0x1180080e0aed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5595" , 0x1180080e0aed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5596" , 0x1180080e0aee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5597" , 0x1180080e0aee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5598" , 0x1180080e0aef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5599" , 0x1180080e0aef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5600" , 0x1180080e0af00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5601" , 0x1180080e0af08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5602" , 0x1180080e0af10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5603" , 0x1180080e0af18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5604" , 0x1180080e0af20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5605" , 0x1180080e0af28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5606" , 0x1180080e0af30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5607" , 0x1180080e0af38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5608" , 0x1180080e0af40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5609" , 0x1180080e0af48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5610" , 0x1180080e0af50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5611" , 0x1180080e0af58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5612" , 0x1180080e0af60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5613" , 0x1180080e0af68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5614" , 0x1180080e0af70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5615" , 0x1180080e0af78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5616" , 0x1180080e0af80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5617" , 0x1180080e0af88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5618" , 0x1180080e0af90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5619" , 0x1180080e0af98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5620" , 0x1180080e0afa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5621" , 0x1180080e0afa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5622" , 0x1180080e0afb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5623" , 0x1180080e0afb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5624" , 0x1180080e0afc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5625" , 0x1180080e0afc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5626" , 0x1180080e0afd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5627" , 0x1180080e0afd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5628" , 0x1180080e0afe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5629" , 0x1180080e0afe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5630" , 0x1180080e0aff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5631" , 0x1180080e0aff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5632" , 0x1180080e0b000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5633" , 0x1180080e0b008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5634" , 0x1180080e0b010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5635" , 0x1180080e0b018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5636" , 0x1180080e0b020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5637" , 0x1180080e0b028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5638" , 0x1180080e0b030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5639" , 0x1180080e0b038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5640" , 0x1180080e0b040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5641" , 0x1180080e0b048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5642" , 0x1180080e0b050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5643" , 0x1180080e0b058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5644" , 0x1180080e0b060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5645" , 0x1180080e0b068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5646" , 0x1180080e0b070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5647" , 0x1180080e0b078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5648" , 0x1180080e0b080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5649" , 0x1180080e0b088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5650" , 0x1180080e0b090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5651" , 0x1180080e0b098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5652" , 0x1180080e0b0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5653" , 0x1180080e0b0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5654" , 0x1180080e0b0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5655" , 0x1180080e0b0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5656" , 0x1180080e0b0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5657" , 0x1180080e0b0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5658" , 0x1180080e0b0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5659" , 0x1180080e0b0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5660" , 0x1180080e0b0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5661" , 0x1180080e0b0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5662" , 0x1180080e0b0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5663" , 0x1180080e0b0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5664" , 0x1180080e0b100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5665" , 0x1180080e0b108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5666" , 0x1180080e0b110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5667" , 0x1180080e0b118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5668" , 0x1180080e0b120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5669" , 0x1180080e0b128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5670" , 0x1180080e0b130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5671" , 0x1180080e0b138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5672" , 0x1180080e0b140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5673" , 0x1180080e0b148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5674" , 0x1180080e0b150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5675" , 0x1180080e0b158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5676" , 0x1180080e0b160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5677" , 0x1180080e0b168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5678" , 0x1180080e0b170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5679" , 0x1180080e0b178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5680" , 0x1180080e0b180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5681" , 0x1180080e0b188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5682" , 0x1180080e0b190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5683" , 0x1180080e0b198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5684" , 0x1180080e0b1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5685" , 0x1180080e0b1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5686" , 0x1180080e0b1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5687" , 0x1180080e0b1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5688" , 0x1180080e0b1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5689" , 0x1180080e0b1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5690" , 0x1180080e0b1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5691" , 0x1180080e0b1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5692" , 0x1180080e0b1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5693" , 0x1180080e0b1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5694" , 0x1180080e0b1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5695" , 0x1180080e0b1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5696" , 0x1180080e0b200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5697" , 0x1180080e0b208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5698" , 0x1180080e0b210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5699" , 0x1180080e0b218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5700" , 0x1180080e0b220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5701" , 0x1180080e0b228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5702" , 0x1180080e0b230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5703" , 0x1180080e0b238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5704" , 0x1180080e0b240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5705" , 0x1180080e0b248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5706" , 0x1180080e0b250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5707" , 0x1180080e0b258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5708" , 0x1180080e0b260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5709" , 0x1180080e0b268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5710" , 0x1180080e0b270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5711" , 0x1180080e0b278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5712" , 0x1180080e0b280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5713" , 0x1180080e0b288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5714" , 0x1180080e0b290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5715" , 0x1180080e0b298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5716" , 0x1180080e0b2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5717" , 0x1180080e0b2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5718" , 0x1180080e0b2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5719" , 0x1180080e0b2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5720" , 0x1180080e0b2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5721" , 0x1180080e0b2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5722" , 0x1180080e0b2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5723" , 0x1180080e0b2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5724" , 0x1180080e0b2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5725" , 0x1180080e0b2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5726" , 0x1180080e0b2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5727" , 0x1180080e0b2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5728" , 0x1180080e0b300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5729" , 0x1180080e0b308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5730" , 0x1180080e0b310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5731" , 0x1180080e0b318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5732" , 0x1180080e0b320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5733" , 0x1180080e0b328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5734" , 0x1180080e0b330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5735" , 0x1180080e0b338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5736" , 0x1180080e0b340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5737" , 0x1180080e0b348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5738" , 0x1180080e0b350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5739" , 0x1180080e0b358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5740" , 0x1180080e0b360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5741" , 0x1180080e0b368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5742" , 0x1180080e0b370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5743" , 0x1180080e0b378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5744" , 0x1180080e0b380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5745" , 0x1180080e0b388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5746" , 0x1180080e0b390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5747" , 0x1180080e0b398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5748" , 0x1180080e0b3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5749" , 0x1180080e0b3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5750" , 0x1180080e0b3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5751" , 0x1180080e0b3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5752" , 0x1180080e0b3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5753" , 0x1180080e0b3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5754" , 0x1180080e0b3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5755" , 0x1180080e0b3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5756" , 0x1180080e0b3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5757" , 0x1180080e0b3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5758" , 0x1180080e0b3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5759" , 0x1180080e0b3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5760" , 0x1180080e0b400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5761" , 0x1180080e0b408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5762" , 0x1180080e0b410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5763" , 0x1180080e0b418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5764" , 0x1180080e0b420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5765" , 0x1180080e0b428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5766" , 0x1180080e0b430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5767" , 0x1180080e0b438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5768" , 0x1180080e0b440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5769" , 0x1180080e0b448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5770" , 0x1180080e0b450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5771" , 0x1180080e0b458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5772" , 0x1180080e0b460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5773" , 0x1180080e0b468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5774" , 0x1180080e0b470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5775" , 0x1180080e0b478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5776" , 0x1180080e0b480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5777" , 0x1180080e0b488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5778" , 0x1180080e0b490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5779" , 0x1180080e0b498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5780" , 0x1180080e0b4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5781" , 0x1180080e0b4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5782" , 0x1180080e0b4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5783" , 0x1180080e0b4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5784" , 0x1180080e0b4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5785" , 0x1180080e0b4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5786" , 0x1180080e0b4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5787" , 0x1180080e0b4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5788" , 0x1180080e0b4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5789" , 0x1180080e0b4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5790" , 0x1180080e0b4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5791" , 0x1180080e0b4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5792" , 0x1180080e0b500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5793" , 0x1180080e0b508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5794" , 0x1180080e0b510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5795" , 0x1180080e0b518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5796" , 0x1180080e0b520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5797" , 0x1180080e0b528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5798" , 0x1180080e0b530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5799" , 0x1180080e0b538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5800" , 0x1180080e0b540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5801" , 0x1180080e0b548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5802" , 0x1180080e0b550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5803" , 0x1180080e0b558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5804" , 0x1180080e0b560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5805" , 0x1180080e0b568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5806" , 0x1180080e0b570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5807" , 0x1180080e0b578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5808" , 0x1180080e0b580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5809" , 0x1180080e0b588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5810" , 0x1180080e0b590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5811" , 0x1180080e0b598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5812" , 0x1180080e0b5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5813" , 0x1180080e0b5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5814" , 0x1180080e0b5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5815" , 0x1180080e0b5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5816" , 0x1180080e0b5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5817" , 0x1180080e0b5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5818" , 0x1180080e0b5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5819" , 0x1180080e0b5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5820" , 0x1180080e0b5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5821" , 0x1180080e0b5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5822" , 0x1180080e0b5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5823" , 0x1180080e0b5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5824" , 0x1180080e0b600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5825" , 0x1180080e0b608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5826" , 0x1180080e0b610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5827" , 0x1180080e0b618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5828" , 0x1180080e0b620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5829" , 0x1180080e0b628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5830" , 0x1180080e0b630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5831" , 0x1180080e0b638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5832" , 0x1180080e0b640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5833" , 0x1180080e0b648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5834" , 0x1180080e0b650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5835" , 0x1180080e0b658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5836" , 0x1180080e0b660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5837" , 0x1180080e0b668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5838" , 0x1180080e0b670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5839" , 0x1180080e0b678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5840" , 0x1180080e0b680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5841" , 0x1180080e0b688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5842" , 0x1180080e0b690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5843" , 0x1180080e0b698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5844" , 0x1180080e0b6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5845" , 0x1180080e0b6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5846" , 0x1180080e0b6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5847" , 0x1180080e0b6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5848" , 0x1180080e0b6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5849" , 0x1180080e0b6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5850" , 0x1180080e0b6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5851" , 0x1180080e0b6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5852" , 0x1180080e0b6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5853" , 0x1180080e0b6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5854" , 0x1180080e0b6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5855" , 0x1180080e0b6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5856" , 0x1180080e0b700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5857" , 0x1180080e0b708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5858" , 0x1180080e0b710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5859" , 0x1180080e0b718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5860" , 0x1180080e0b720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5861" , 0x1180080e0b728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5862" , 0x1180080e0b730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5863" , 0x1180080e0b738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5864" , 0x1180080e0b740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5865" , 0x1180080e0b748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5866" , 0x1180080e0b750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5867" , 0x1180080e0b758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5868" , 0x1180080e0b760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5869" , 0x1180080e0b768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5870" , 0x1180080e0b770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5871" , 0x1180080e0b778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5872" , 0x1180080e0b780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5873" , 0x1180080e0b788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5874" , 0x1180080e0b790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5875" , 0x1180080e0b798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5876" , 0x1180080e0b7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5877" , 0x1180080e0b7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5878" , 0x1180080e0b7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5879" , 0x1180080e0b7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5880" , 0x1180080e0b7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5881" , 0x1180080e0b7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5882" , 0x1180080e0b7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5883" , 0x1180080e0b7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5884" , 0x1180080e0b7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5885" , 0x1180080e0b7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5886" , 0x1180080e0b7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5887" , 0x1180080e0b7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5888" , 0x1180080e0b800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5889" , 0x1180080e0b808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5890" , 0x1180080e0b810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5891" , 0x1180080e0b818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5892" , 0x1180080e0b820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5893" , 0x1180080e0b828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5894" , 0x1180080e0b830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5895" , 0x1180080e0b838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5896" , 0x1180080e0b840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5897" , 0x1180080e0b848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5898" , 0x1180080e0b850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5899" , 0x1180080e0b858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5900" , 0x1180080e0b860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5901" , 0x1180080e0b868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5902" , 0x1180080e0b870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5903" , 0x1180080e0b878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5904" , 0x1180080e0b880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5905" , 0x1180080e0b888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5906" , 0x1180080e0b890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5907" , 0x1180080e0b898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5908" , 0x1180080e0b8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5909" , 0x1180080e0b8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5910" , 0x1180080e0b8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5911" , 0x1180080e0b8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5912" , 0x1180080e0b8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5913" , 0x1180080e0b8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5914" , 0x1180080e0b8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5915" , 0x1180080e0b8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5916" , 0x1180080e0b8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5917" , 0x1180080e0b8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5918" , 0x1180080e0b8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5919" , 0x1180080e0b8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5920" , 0x1180080e0b900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5921" , 0x1180080e0b908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5922" , 0x1180080e0b910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5923" , 0x1180080e0b918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5924" , 0x1180080e0b920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5925" , 0x1180080e0b928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5926" , 0x1180080e0b930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5927" , 0x1180080e0b938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5928" , 0x1180080e0b940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5929" , 0x1180080e0b948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5930" , 0x1180080e0b950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5931" , 0x1180080e0b958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5932" , 0x1180080e0b960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5933" , 0x1180080e0b968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5934" , 0x1180080e0b970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5935" , 0x1180080e0b978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5936" , 0x1180080e0b980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5937" , 0x1180080e0b988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5938" , 0x1180080e0b990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5939" , 0x1180080e0b998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5940" , 0x1180080e0b9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5941" , 0x1180080e0b9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5942" , 0x1180080e0b9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5943" , 0x1180080e0b9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5944" , 0x1180080e0b9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5945" , 0x1180080e0b9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5946" , 0x1180080e0b9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5947" , 0x1180080e0b9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5948" , 0x1180080e0b9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5949" , 0x1180080e0b9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5950" , 0x1180080e0b9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5951" , 0x1180080e0b9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5952" , 0x1180080e0ba00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5953" , 0x1180080e0ba08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5954" , 0x1180080e0ba10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5955" , 0x1180080e0ba18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5956" , 0x1180080e0ba20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5957" , 0x1180080e0ba28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5958" , 0x1180080e0ba30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5959" , 0x1180080e0ba38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5960" , 0x1180080e0ba40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5961" , 0x1180080e0ba48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5962" , 0x1180080e0ba50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5963" , 0x1180080e0ba58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5964" , 0x1180080e0ba60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5965" , 0x1180080e0ba68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5966" , 0x1180080e0ba70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5967" , 0x1180080e0ba78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5968" , 0x1180080e0ba80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5969" , 0x1180080e0ba88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5970" , 0x1180080e0ba90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5971" , 0x1180080e0ba98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5972" , 0x1180080e0baa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5973" , 0x1180080e0baa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5974" , 0x1180080e0bab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5975" , 0x1180080e0bab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5976" , 0x1180080e0bac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5977" , 0x1180080e0bac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5978" , 0x1180080e0bad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5979" , 0x1180080e0bad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5980" , 0x1180080e0bae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5981" , 0x1180080e0bae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5982" , 0x1180080e0baf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5983" , 0x1180080e0baf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5984" , 0x1180080e0bb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5985" , 0x1180080e0bb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5986" , 0x1180080e0bb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5987" , 0x1180080e0bb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5988" , 0x1180080e0bb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5989" , 0x1180080e0bb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5990" , 0x1180080e0bb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5991" , 0x1180080e0bb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5992" , 0x1180080e0bb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5993" , 0x1180080e0bb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5994" , 0x1180080e0bb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5995" , 0x1180080e0bb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5996" , 0x1180080e0bb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5997" , 0x1180080e0bb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5998" , 0x1180080e0bb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP5999" , 0x1180080e0bb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6000" , 0x1180080e0bb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6001" , 0x1180080e0bb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6002" , 0x1180080e0bb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6003" , 0x1180080e0bb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6004" , 0x1180080e0bba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6005" , 0x1180080e0bba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6006" , 0x1180080e0bbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6007" , 0x1180080e0bbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6008" , 0x1180080e0bbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6009" , 0x1180080e0bbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6010" , 0x1180080e0bbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6011" , 0x1180080e0bbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6012" , 0x1180080e0bbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6013" , 0x1180080e0bbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6014" , 0x1180080e0bbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6015" , 0x1180080e0bbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6016" , 0x1180080e0bc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6017" , 0x1180080e0bc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6018" , 0x1180080e0bc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6019" , 0x1180080e0bc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6020" , 0x1180080e0bc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6021" , 0x1180080e0bc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6022" , 0x1180080e0bc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6023" , 0x1180080e0bc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6024" , 0x1180080e0bc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6025" , 0x1180080e0bc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6026" , 0x1180080e0bc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6027" , 0x1180080e0bc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6028" , 0x1180080e0bc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6029" , 0x1180080e0bc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6030" , 0x1180080e0bc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6031" , 0x1180080e0bc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6032" , 0x1180080e0bc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6033" , 0x1180080e0bc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6034" , 0x1180080e0bc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6035" , 0x1180080e0bc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6036" , 0x1180080e0bca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6037" , 0x1180080e0bca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6038" , 0x1180080e0bcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6039" , 0x1180080e0bcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6040" , 0x1180080e0bcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6041" , 0x1180080e0bcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6042" , 0x1180080e0bcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6043" , 0x1180080e0bcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6044" , 0x1180080e0bce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6045" , 0x1180080e0bce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6046" , 0x1180080e0bcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6047" , 0x1180080e0bcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6048" , 0x1180080e0bd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6049" , 0x1180080e0bd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6050" , 0x1180080e0bd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6051" , 0x1180080e0bd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6052" , 0x1180080e0bd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6053" , 0x1180080e0bd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6054" , 0x1180080e0bd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6055" , 0x1180080e0bd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6056" , 0x1180080e0bd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6057" , 0x1180080e0bd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6058" , 0x1180080e0bd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6059" , 0x1180080e0bd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6060" , 0x1180080e0bd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6061" , 0x1180080e0bd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6062" , 0x1180080e0bd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6063" , 0x1180080e0bd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6064" , 0x1180080e0bd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6065" , 0x1180080e0bd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6066" , 0x1180080e0bd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6067" , 0x1180080e0bd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6068" , 0x1180080e0bda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6069" , 0x1180080e0bda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6070" , 0x1180080e0bdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6071" , 0x1180080e0bdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6072" , 0x1180080e0bdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6073" , 0x1180080e0bdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6074" , 0x1180080e0bdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6075" , 0x1180080e0bdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6076" , 0x1180080e0bde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6077" , 0x1180080e0bde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6078" , 0x1180080e0bdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6079" , 0x1180080e0bdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6080" , 0x1180080e0be00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6081" , 0x1180080e0be08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6082" , 0x1180080e0be10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6083" , 0x1180080e0be18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6084" , 0x1180080e0be20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6085" , 0x1180080e0be28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6086" , 0x1180080e0be30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6087" , 0x1180080e0be38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6088" , 0x1180080e0be40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6089" , 0x1180080e0be48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6090" , 0x1180080e0be50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6091" , 0x1180080e0be58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6092" , 0x1180080e0be60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6093" , 0x1180080e0be68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6094" , 0x1180080e0be70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6095" , 0x1180080e0be78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6096" , 0x1180080e0be80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6097" , 0x1180080e0be88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6098" , 0x1180080e0be90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6099" , 0x1180080e0be98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6100" , 0x1180080e0bea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6101" , 0x1180080e0bea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6102" , 0x1180080e0beb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6103" , 0x1180080e0beb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6104" , 0x1180080e0bec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6105" , 0x1180080e0bec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6106" , 0x1180080e0bed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6107" , 0x1180080e0bed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6108" , 0x1180080e0bee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6109" , 0x1180080e0bee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6110" , 0x1180080e0bef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6111" , 0x1180080e0bef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6112" , 0x1180080e0bf00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6113" , 0x1180080e0bf08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6114" , 0x1180080e0bf10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6115" , 0x1180080e0bf18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6116" , 0x1180080e0bf20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6117" , 0x1180080e0bf28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6118" , 0x1180080e0bf30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6119" , 0x1180080e0bf38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6120" , 0x1180080e0bf40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6121" , 0x1180080e0bf48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6122" , 0x1180080e0bf50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6123" , 0x1180080e0bf58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6124" , 0x1180080e0bf60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6125" , 0x1180080e0bf68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6126" , 0x1180080e0bf70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6127" , 0x1180080e0bf78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6128" , 0x1180080e0bf80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6129" , 0x1180080e0bf88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6130" , 0x1180080e0bf90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6131" , 0x1180080e0bf98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6132" , 0x1180080e0bfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6133" , 0x1180080e0bfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6134" , 0x1180080e0bfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6135" , 0x1180080e0bfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6136" , 0x1180080e0bfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6137" , 0x1180080e0bfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6138" , 0x1180080e0bfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6139" , 0x1180080e0bfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6140" , 0x1180080e0bfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6141" , 0x1180080e0bfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6142" , 0x1180080e0bff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6143" , 0x1180080e0bff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6144" , 0x1180080e0c000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6145" , 0x1180080e0c008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6146" , 0x1180080e0c010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6147" , 0x1180080e0c018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6148" , 0x1180080e0c020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6149" , 0x1180080e0c028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6150" , 0x1180080e0c030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6151" , 0x1180080e0c038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6152" , 0x1180080e0c040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6153" , 0x1180080e0c048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6154" , 0x1180080e0c050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6155" , 0x1180080e0c058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6156" , 0x1180080e0c060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6157" , 0x1180080e0c068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6158" , 0x1180080e0c070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6159" , 0x1180080e0c078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6160" , 0x1180080e0c080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6161" , 0x1180080e0c088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6162" , 0x1180080e0c090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6163" , 0x1180080e0c098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6164" , 0x1180080e0c0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6165" , 0x1180080e0c0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6166" , 0x1180080e0c0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6167" , 0x1180080e0c0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6168" , 0x1180080e0c0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6169" , 0x1180080e0c0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6170" , 0x1180080e0c0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6171" , 0x1180080e0c0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6172" , 0x1180080e0c0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6173" , 0x1180080e0c0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6174" , 0x1180080e0c0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6175" , 0x1180080e0c0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6176" , 0x1180080e0c100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6177" , 0x1180080e0c108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6178" , 0x1180080e0c110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6179" , 0x1180080e0c118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6180" , 0x1180080e0c120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6181" , 0x1180080e0c128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6182" , 0x1180080e0c130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6183" , 0x1180080e0c138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6184" , 0x1180080e0c140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6185" , 0x1180080e0c148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6186" , 0x1180080e0c150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6187" , 0x1180080e0c158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6188" , 0x1180080e0c160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6189" , 0x1180080e0c168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6190" , 0x1180080e0c170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6191" , 0x1180080e0c178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6192" , 0x1180080e0c180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6193" , 0x1180080e0c188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6194" , 0x1180080e0c190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6195" , 0x1180080e0c198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6196" , 0x1180080e0c1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6197" , 0x1180080e0c1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6198" , 0x1180080e0c1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6199" , 0x1180080e0c1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6200" , 0x1180080e0c1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6201" , 0x1180080e0c1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6202" , 0x1180080e0c1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6203" , 0x1180080e0c1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6204" , 0x1180080e0c1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6205" , 0x1180080e0c1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6206" , 0x1180080e0c1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6207" , 0x1180080e0c1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6208" , 0x1180080e0c200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6209" , 0x1180080e0c208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6210" , 0x1180080e0c210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6211" , 0x1180080e0c218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6212" , 0x1180080e0c220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6213" , 0x1180080e0c228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6214" , 0x1180080e0c230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6215" , 0x1180080e0c238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6216" , 0x1180080e0c240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6217" , 0x1180080e0c248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6218" , 0x1180080e0c250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6219" , 0x1180080e0c258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6220" , 0x1180080e0c260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6221" , 0x1180080e0c268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6222" , 0x1180080e0c270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6223" , 0x1180080e0c278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6224" , 0x1180080e0c280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6225" , 0x1180080e0c288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6226" , 0x1180080e0c290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6227" , 0x1180080e0c298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6228" , 0x1180080e0c2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6229" , 0x1180080e0c2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6230" , 0x1180080e0c2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6231" , 0x1180080e0c2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6232" , 0x1180080e0c2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6233" , 0x1180080e0c2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6234" , 0x1180080e0c2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6235" , 0x1180080e0c2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6236" , 0x1180080e0c2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6237" , 0x1180080e0c2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6238" , 0x1180080e0c2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6239" , 0x1180080e0c2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6240" , 0x1180080e0c300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6241" , 0x1180080e0c308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6242" , 0x1180080e0c310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6243" , 0x1180080e0c318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6244" , 0x1180080e0c320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6245" , 0x1180080e0c328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6246" , 0x1180080e0c330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6247" , 0x1180080e0c338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6248" , 0x1180080e0c340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6249" , 0x1180080e0c348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6250" , 0x1180080e0c350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6251" , 0x1180080e0c358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6252" , 0x1180080e0c360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6253" , 0x1180080e0c368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6254" , 0x1180080e0c370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6255" , 0x1180080e0c378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6256" , 0x1180080e0c380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6257" , 0x1180080e0c388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6258" , 0x1180080e0c390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6259" , 0x1180080e0c398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6260" , 0x1180080e0c3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6261" , 0x1180080e0c3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6262" , 0x1180080e0c3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6263" , 0x1180080e0c3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6264" , 0x1180080e0c3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6265" , 0x1180080e0c3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6266" , 0x1180080e0c3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6267" , 0x1180080e0c3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6268" , 0x1180080e0c3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6269" , 0x1180080e0c3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6270" , 0x1180080e0c3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6271" , 0x1180080e0c3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6272" , 0x1180080e0c400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6273" , 0x1180080e0c408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6274" , 0x1180080e0c410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6275" , 0x1180080e0c418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6276" , 0x1180080e0c420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6277" , 0x1180080e0c428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6278" , 0x1180080e0c430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6279" , 0x1180080e0c438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6280" , 0x1180080e0c440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6281" , 0x1180080e0c448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6282" , 0x1180080e0c450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6283" , 0x1180080e0c458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6284" , 0x1180080e0c460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6285" , 0x1180080e0c468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6286" , 0x1180080e0c470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6287" , 0x1180080e0c478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6288" , 0x1180080e0c480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6289" , 0x1180080e0c488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6290" , 0x1180080e0c490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6291" , 0x1180080e0c498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6292" , 0x1180080e0c4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6293" , 0x1180080e0c4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6294" , 0x1180080e0c4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6295" , 0x1180080e0c4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6296" , 0x1180080e0c4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6297" , 0x1180080e0c4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6298" , 0x1180080e0c4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6299" , 0x1180080e0c4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6300" , 0x1180080e0c4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6301" , 0x1180080e0c4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6302" , 0x1180080e0c4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6303" , 0x1180080e0c4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6304" , 0x1180080e0c500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6305" , 0x1180080e0c508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6306" , 0x1180080e0c510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6307" , 0x1180080e0c518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6308" , 0x1180080e0c520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6309" , 0x1180080e0c528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6310" , 0x1180080e0c530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6311" , 0x1180080e0c538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6312" , 0x1180080e0c540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6313" , 0x1180080e0c548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6314" , 0x1180080e0c550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6315" , 0x1180080e0c558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6316" , 0x1180080e0c560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6317" , 0x1180080e0c568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6318" , 0x1180080e0c570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6319" , 0x1180080e0c578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6320" , 0x1180080e0c580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6321" , 0x1180080e0c588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6322" , 0x1180080e0c590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6323" , 0x1180080e0c598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6324" , 0x1180080e0c5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6325" , 0x1180080e0c5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6326" , 0x1180080e0c5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6327" , 0x1180080e0c5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6328" , 0x1180080e0c5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6329" , 0x1180080e0c5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6330" , 0x1180080e0c5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6331" , 0x1180080e0c5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6332" , 0x1180080e0c5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6333" , 0x1180080e0c5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6334" , 0x1180080e0c5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6335" , 0x1180080e0c5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6336" , 0x1180080e0c600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6337" , 0x1180080e0c608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6338" , 0x1180080e0c610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6339" , 0x1180080e0c618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6340" , 0x1180080e0c620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6341" , 0x1180080e0c628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6342" , 0x1180080e0c630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6343" , 0x1180080e0c638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6344" , 0x1180080e0c640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6345" , 0x1180080e0c648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6346" , 0x1180080e0c650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6347" , 0x1180080e0c658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6348" , 0x1180080e0c660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6349" , 0x1180080e0c668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6350" , 0x1180080e0c670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6351" , 0x1180080e0c678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6352" , 0x1180080e0c680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6353" , 0x1180080e0c688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6354" , 0x1180080e0c690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6355" , 0x1180080e0c698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6356" , 0x1180080e0c6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6357" , 0x1180080e0c6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6358" , 0x1180080e0c6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6359" , 0x1180080e0c6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6360" , 0x1180080e0c6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6361" , 0x1180080e0c6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6362" , 0x1180080e0c6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6363" , 0x1180080e0c6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6364" , 0x1180080e0c6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6365" , 0x1180080e0c6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6366" , 0x1180080e0c6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6367" , 0x1180080e0c6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6368" , 0x1180080e0c700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6369" , 0x1180080e0c708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6370" , 0x1180080e0c710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6371" , 0x1180080e0c718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6372" , 0x1180080e0c720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6373" , 0x1180080e0c728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6374" , 0x1180080e0c730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6375" , 0x1180080e0c738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6376" , 0x1180080e0c740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6377" , 0x1180080e0c748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6378" , 0x1180080e0c750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6379" , 0x1180080e0c758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6380" , 0x1180080e0c760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6381" , 0x1180080e0c768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6382" , 0x1180080e0c770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6383" , 0x1180080e0c778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6384" , 0x1180080e0c780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6385" , 0x1180080e0c788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6386" , 0x1180080e0c790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6387" , 0x1180080e0c798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6388" , 0x1180080e0c7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6389" , 0x1180080e0c7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6390" , 0x1180080e0c7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6391" , 0x1180080e0c7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6392" , 0x1180080e0c7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6393" , 0x1180080e0c7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6394" , 0x1180080e0c7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6395" , 0x1180080e0c7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6396" , 0x1180080e0c7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6397" , 0x1180080e0c7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6398" , 0x1180080e0c7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6399" , 0x1180080e0c7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6400" , 0x1180080e0c800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6401" , 0x1180080e0c808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6402" , 0x1180080e0c810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6403" , 0x1180080e0c818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6404" , 0x1180080e0c820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6405" , 0x1180080e0c828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6406" , 0x1180080e0c830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6407" , 0x1180080e0c838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6408" , 0x1180080e0c840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6409" , 0x1180080e0c848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6410" , 0x1180080e0c850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6411" , 0x1180080e0c858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6412" , 0x1180080e0c860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6413" , 0x1180080e0c868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6414" , 0x1180080e0c870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6415" , 0x1180080e0c878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6416" , 0x1180080e0c880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6417" , 0x1180080e0c888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6418" , 0x1180080e0c890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6419" , 0x1180080e0c898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6420" , 0x1180080e0c8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6421" , 0x1180080e0c8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6422" , 0x1180080e0c8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6423" , 0x1180080e0c8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6424" , 0x1180080e0c8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6425" , 0x1180080e0c8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6426" , 0x1180080e0c8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6427" , 0x1180080e0c8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6428" , 0x1180080e0c8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6429" , 0x1180080e0c8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6430" , 0x1180080e0c8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6431" , 0x1180080e0c8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6432" , 0x1180080e0c900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6433" , 0x1180080e0c908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6434" , 0x1180080e0c910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6435" , 0x1180080e0c918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6436" , 0x1180080e0c920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6437" , 0x1180080e0c928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6438" , 0x1180080e0c930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6439" , 0x1180080e0c938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6440" , 0x1180080e0c940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6441" , 0x1180080e0c948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6442" , 0x1180080e0c950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6443" , 0x1180080e0c958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6444" , 0x1180080e0c960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6445" , 0x1180080e0c968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6446" , 0x1180080e0c970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6447" , 0x1180080e0c978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6448" , 0x1180080e0c980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6449" , 0x1180080e0c988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6450" , 0x1180080e0c990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6451" , 0x1180080e0c998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6452" , 0x1180080e0c9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6453" , 0x1180080e0c9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6454" , 0x1180080e0c9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6455" , 0x1180080e0c9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6456" , 0x1180080e0c9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6457" , 0x1180080e0c9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6458" , 0x1180080e0c9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6459" , 0x1180080e0c9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6460" , 0x1180080e0c9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6461" , 0x1180080e0c9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6462" , 0x1180080e0c9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6463" , 0x1180080e0c9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6464" , 0x1180080e0ca00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6465" , 0x1180080e0ca08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6466" , 0x1180080e0ca10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6467" , 0x1180080e0ca18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6468" , 0x1180080e0ca20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6469" , 0x1180080e0ca28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6470" , 0x1180080e0ca30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6471" , 0x1180080e0ca38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6472" , 0x1180080e0ca40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6473" , 0x1180080e0ca48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6474" , 0x1180080e0ca50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6475" , 0x1180080e0ca58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6476" , 0x1180080e0ca60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6477" , 0x1180080e0ca68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6478" , 0x1180080e0ca70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6479" , 0x1180080e0ca78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6480" , 0x1180080e0ca80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6481" , 0x1180080e0ca88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6482" , 0x1180080e0ca90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6483" , 0x1180080e0ca98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6484" , 0x1180080e0caa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6485" , 0x1180080e0caa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6486" , 0x1180080e0cab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6487" , 0x1180080e0cab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6488" , 0x1180080e0cac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6489" , 0x1180080e0cac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6490" , 0x1180080e0cad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6491" , 0x1180080e0cad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6492" , 0x1180080e0cae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6493" , 0x1180080e0cae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6494" , 0x1180080e0caf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6495" , 0x1180080e0caf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6496" , 0x1180080e0cb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6497" , 0x1180080e0cb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6498" , 0x1180080e0cb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6499" , 0x1180080e0cb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6500" , 0x1180080e0cb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6501" , 0x1180080e0cb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6502" , 0x1180080e0cb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6503" , 0x1180080e0cb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6504" , 0x1180080e0cb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6505" , 0x1180080e0cb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6506" , 0x1180080e0cb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6507" , 0x1180080e0cb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6508" , 0x1180080e0cb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6509" , 0x1180080e0cb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6510" , 0x1180080e0cb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6511" , 0x1180080e0cb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6512" , 0x1180080e0cb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6513" , 0x1180080e0cb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6514" , 0x1180080e0cb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6515" , 0x1180080e0cb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6516" , 0x1180080e0cba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6517" , 0x1180080e0cba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6518" , 0x1180080e0cbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6519" , 0x1180080e0cbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6520" , 0x1180080e0cbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6521" , 0x1180080e0cbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6522" , 0x1180080e0cbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6523" , 0x1180080e0cbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6524" , 0x1180080e0cbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6525" , 0x1180080e0cbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6526" , 0x1180080e0cbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6527" , 0x1180080e0cbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6528" , 0x1180080e0cc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6529" , 0x1180080e0cc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6530" , 0x1180080e0cc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6531" , 0x1180080e0cc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6532" , 0x1180080e0cc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6533" , 0x1180080e0cc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6534" , 0x1180080e0cc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6535" , 0x1180080e0cc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6536" , 0x1180080e0cc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6537" , 0x1180080e0cc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6538" , 0x1180080e0cc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6539" , 0x1180080e0cc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6540" , 0x1180080e0cc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6541" , 0x1180080e0cc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6542" , 0x1180080e0cc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6543" , 0x1180080e0cc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6544" , 0x1180080e0cc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6545" , 0x1180080e0cc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6546" , 0x1180080e0cc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6547" , 0x1180080e0cc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6548" , 0x1180080e0cca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6549" , 0x1180080e0cca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6550" , 0x1180080e0ccb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6551" , 0x1180080e0ccb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6552" , 0x1180080e0ccc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6553" , 0x1180080e0ccc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6554" , 0x1180080e0ccd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6555" , 0x1180080e0ccd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6556" , 0x1180080e0cce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6557" , 0x1180080e0cce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6558" , 0x1180080e0ccf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6559" , 0x1180080e0ccf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6560" , 0x1180080e0cd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6561" , 0x1180080e0cd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6562" , 0x1180080e0cd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6563" , 0x1180080e0cd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6564" , 0x1180080e0cd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6565" , 0x1180080e0cd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6566" , 0x1180080e0cd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6567" , 0x1180080e0cd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6568" , 0x1180080e0cd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6569" , 0x1180080e0cd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6570" , 0x1180080e0cd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6571" , 0x1180080e0cd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6572" , 0x1180080e0cd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6573" , 0x1180080e0cd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6574" , 0x1180080e0cd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6575" , 0x1180080e0cd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6576" , 0x1180080e0cd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6577" , 0x1180080e0cd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6578" , 0x1180080e0cd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6579" , 0x1180080e0cd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6580" , 0x1180080e0cda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6581" , 0x1180080e0cda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6582" , 0x1180080e0cdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6583" , 0x1180080e0cdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6584" , 0x1180080e0cdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6585" , 0x1180080e0cdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6586" , 0x1180080e0cdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6587" , 0x1180080e0cdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6588" , 0x1180080e0cde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6589" , 0x1180080e0cde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6590" , 0x1180080e0cdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6591" , 0x1180080e0cdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6592" , 0x1180080e0ce00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6593" , 0x1180080e0ce08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6594" , 0x1180080e0ce10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6595" , 0x1180080e0ce18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6596" , 0x1180080e0ce20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6597" , 0x1180080e0ce28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6598" , 0x1180080e0ce30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6599" , 0x1180080e0ce38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6600" , 0x1180080e0ce40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6601" , 0x1180080e0ce48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6602" , 0x1180080e0ce50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6603" , 0x1180080e0ce58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6604" , 0x1180080e0ce60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6605" , 0x1180080e0ce68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6606" , 0x1180080e0ce70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6607" , 0x1180080e0ce78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6608" , 0x1180080e0ce80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6609" , 0x1180080e0ce88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6610" , 0x1180080e0ce90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6611" , 0x1180080e0ce98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6612" , 0x1180080e0cea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6613" , 0x1180080e0cea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6614" , 0x1180080e0ceb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6615" , 0x1180080e0ceb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6616" , 0x1180080e0cec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6617" , 0x1180080e0cec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6618" , 0x1180080e0ced0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6619" , 0x1180080e0ced8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6620" , 0x1180080e0cee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6621" , 0x1180080e0cee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6622" , 0x1180080e0cef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6623" , 0x1180080e0cef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6624" , 0x1180080e0cf00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6625" , 0x1180080e0cf08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6626" , 0x1180080e0cf10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6627" , 0x1180080e0cf18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6628" , 0x1180080e0cf20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6629" , 0x1180080e0cf28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6630" , 0x1180080e0cf30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6631" , 0x1180080e0cf38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6632" , 0x1180080e0cf40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6633" , 0x1180080e0cf48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6634" , 0x1180080e0cf50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6635" , 0x1180080e0cf58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6636" , 0x1180080e0cf60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6637" , 0x1180080e0cf68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6638" , 0x1180080e0cf70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6639" , 0x1180080e0cf78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6640" , 0x1180080e0cf80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6641" , 0x1180080e0cf88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6642" , 0x1180080e0cf90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6643" , 0x1180080e0cf98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6644" , 0x1180080e0cfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6645" , 0x1180080e0cfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6646" , 0x1180080e0cfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6647" , 0x1180080e0cfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6648" , 0x1180080e0cfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6649" , 0x1180080e0cfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6650" , 0x1180080e0cfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6651" , 0x1180080e0cfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6652" , 0x1180080e0cfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6653" , 0x1180080e0cfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6654" , 0x1180080e0cff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6655" , 0x1180080e0cff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6656" , 0x1180080e0d000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6657" , 0x1180080e0d008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6658" , 0x1180080e0d010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6659" , 0x1180080e0d018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6660" , 0x1180080e0d020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6661" , 0x1180080e0d028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6662" , 0x1180080e0d030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6663" , 0x1180080e0d038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6664" , 0x1180080e0d040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6665" , 0x1180080e0d048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6666" , 0x1180080e0d050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6667" , 0x1180080e0d058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6668" , 0x1180080e0d060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6669" , 0x1180080e0d068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6670" , 0x1180080e0d070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6671" , 0x1180080e0d078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6672" , 0x1180080e0d080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6673" , 0x1180080e0d088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6674" , 0x1180080e0d090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6675" , 0x1180080e0d098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6676" , 0x1180080e0d0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6677" , 0x1180080e0d0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6678" , 0x1180080e0d0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6679" , 0x1180080e0d0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6680" , 0x1180080e0d0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6681" , 0x1180080e0d0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6682" , 0x1180080e0d0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6683" , 0x1180080e0d0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6684" , 0x1180080e0d0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6685" , 0x1180080e0d0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6686" , 0x1180080e0d0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6687" , 0x1180080e0d0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6688" , 0x1180080e0d100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6689" , 0x1180080e0d108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6690" , 0x1180080e0d110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6691" , 0x1180080e0d118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6692" , 0x1180080e0d120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6693" , 0x1180080e0d128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6694" , 0x1180080e0d130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6695" , 0x1180080e0d138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6696" , 0x1180080e0d140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6697" , 0x1180080e0d148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6698" , 0x1180080e0d150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6699" , 0x1180080e0d158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6700" , 0x1180080e0d160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6701" , 0x1180080e0d168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6702" , 0x1180080e0d170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6703" , 0x1180080e0d178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6704" , 0x1180080e0d180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6705" , 0x1180080e0d188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6706" , 0x1180080e0d190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6707" , 0x1180080e0d198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6708" , 0x1180080e0d1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6709" , 0x1180080e0d1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6710" , 0x1180080e0d1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6711" , 0x1180080e0d1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6712" , 0x1180080e0d1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6713" , 0x1180080e0d1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6714" , 0x1180080e0d1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6715" , 0x1180080e0d1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6716" , 0x1180080e0d1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6717" , 0x1180080e0d1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6718" , 0x1180080e0d1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6719" , 0x1180080e0d1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6720" , 0x1180080e0d200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6721" , 0x1180080e0d208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6722" , 0x1180080e0d210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6723" , 0x1180080e0d218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6724" , 0x1180080e0d220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6725" , 0x1180080e0d228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6726" , 0x1180080e0d230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6727" , 0x1180080e0d238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6728" , 0x1180080e0d240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6729" , 0x1180080e0d248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6730" , 0x1180080e0d250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6731" , 0x1180080e0d258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6732" , 0x1180080e0d260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6733" , 0x1180080e0d268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6734" , 0x1180080e0d270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6735" , 0x1180080e0d278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6736" , 0x1180080e0d280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6737" , 0x1180080e0d288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6738" , 0x1180080e0d290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6739" , 0x1180080e0d298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6740" , 0x1180080e0d2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6741" , 0x1180080e0d2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6742" , 0x1180080e0d2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6743" , 0x1180080e0d2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6744" , 0x1180080e0d2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6745" , 0x1180080e0d2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6746" , 0x1180080e0d2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6747" , 0x1180080e0d2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6748" , 0x1180080e0d2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6749" , 0x1180080e0d2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6750" , 0x1180080e0d2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6751" , 0x1180080e0d2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6752" , 0x1180080e0d300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6753" , 0x1180080e0d308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6754" , 0x1180080e0d310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6755" , 0x1180080e0d318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6756" , 0x1180080e0d320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6757" , 0x1180080e0d328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6758" , 0x1180080e0d330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6759" , 0x1180080e0d338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6760" , 0x1180080e0d340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6761" , 0x1180080e0d348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6762" , 0x1180080e0d350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6763" , 0x1180080e0d358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6764" , 0x1180080e0d360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6765" , 0x1180080e0d368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6766" , 0x1180080e0d370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6767" , 0x1180080e0d378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6768" , 0x1180080e0d380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6769" , 0x1180080e0d388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6770" , 0x1180080e0d390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6771" , 0x1180080e0d398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6772" , 0x1180080e0d3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6773" , 0x1180080e0d3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6774" , 0x1180080e0d3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6775" , 0x1180080e0d3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6776" , 0x1180080e0d3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6777" , 0x1180080e0d3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6778" , 0x1180080e0d3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6779" , 0x1180080e0d3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6780" , 0x1180080e0d3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6781" , 0x1180080e0d3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6782" , 0x1180080e0d3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6783" , 0x1180080e0d3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6784" , 0x1180080e0d400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6785" , 0x1180080e0d408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6786" , 0x1180080e0d410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6787" , 0x1180080e0d418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6788" , 0x1180080e0d420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6789" , 0x1180080e0d428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6790" , 0x1180080e0d430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6791" , 0x1180080e0d438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6792" , 0x1180080e0d440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6793" , 0x1180080e0d448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6794" , 0x1180080e0d450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6795" , 0x1180080e0d458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6796" , 0x1180080e0d460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6797" , 0x1180080e0d468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6798" , 0x1180080e0d470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6799" , 0x1180080e0d478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6800" , 0x1180080e0d480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6801" , 0x1180080e0d488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6802" , 0x1180080e0d490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6803" , 0x1180080e0d498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6804" , 0x1180080e0d4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6805" , 0x1180080e0d4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6806" , 0x1180080e0d4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6807" , 0x1180080e0d4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6808" , 0x1180080e0d4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6809" , 0x1180080e0d4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6810" , 0x1180080e0d4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6811" , 0x1180080e0d4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6812" , 0x1180080e0d4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6813" , 0x1180080e0d4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6814" , 0x1180080e0d4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6815" , 0x1180080e0d4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6816" , 0x1180080e0d500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6817" , 0x1180080e0d508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6818" , 0x1180080e0d510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6819" , 0x1180080e0d518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6820" , 0x1180080e0d520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6821" , 0x1180080e0d528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6822" , 0x1180080e0d530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6823" , 0x1180080e0d538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6824" , 0x1180080e0d540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6825" , 0x1180080e0d548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6826" , 0x1180080e0d550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6827" , 0x1180080e0d558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6828" , 0x1180080e0d560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6829" , 0x1180080e0d568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6830" , 0x1180080e0d570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6831" , 0x1180080e0d578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6832" , 0x1180080e0d580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6833" , 0x1180080e0d588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6834" , 0x1180080e0d590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6835" , 0x1180080e0d598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6836" , 0x1180080e0d5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6837" , 0x1180080e0d5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6838" , 0x1180080e0d5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6839" , 0x1180080e0d5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6840" , 0x1180080e0d5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6841" , 0x1180080e0d5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6842" , 0x1180080e0d5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6843" , 0x1180080e0d5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6844" , 0x1180080e0d5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6845" , 0x1180080e0d5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6846" , 0x1180080e0d5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6847" , 0x1180080e0d5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6848" , 0x1180080e0d600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6849" , 0x1180080e0d608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6850" , 0x1180080e0d610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6851" , 0x1180080e0d618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6852" , 0x1180080e0d620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6853" , 0x1180080e0d628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6854" , 0x1180080e0d630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6855" , 0x1180080e0d638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6856" , 0x1180080e0d640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6857" , 0x1180080e0d648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6858" , 0x1180080e0d650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6859" , 0x1180080e0d658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6860" , 0x1180080e0d660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6861" , 0x1180080e0d668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6862" , 0x1180080e0d670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6863" , 0x1180080e0d678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6864" , 0x1180080e0d680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6865" , 0x1180080e0d688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6866" , 0x1180080e0d690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6867" , 0x1180080e0d698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6868" , 0x1180080e0d6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6869" , 0x1180080e0d6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6870" , 0x1180080e0d6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6871" , 0x1180080e0d6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6872" , 0x1180080e0d6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6873" , 0x1180080e0d6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6874" , 0x1180080e0d6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6875" , 0x1180080e0d6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6876" , 0x1180080e0d6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6877" , 0x1180080e0d6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6878" , 0x1180080e0d6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6879" , 0x1180080e0d6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6880" , 0x1180080e0d700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6881" , 0x1180080e0d708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6882" , 0x1180080e0d710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6883" , 0x1180080e0d718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6884" , 0x1180080e0d720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6885" , 0x1180080e0d728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6886" , 0x1180080e0d730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6887" , 0x1180080e0d738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6888" , 0x1180080e0d740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6889" , 0x1180080e0d748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6890" , 0x1180080e0d750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6891" , 0x1180080e0d758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6892" , 0x1180080e0d760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6893" , 0x1180080e0d768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6894" , 0x1180080e0d770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6895" , 0x1180080e0d778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6896" , 0x1180080e0d780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6897" , 0x1180080e0d788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6898" , 0x1180080e0d790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6899" , 0x1180080e0d798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6900" , 0x1180080e0d7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6901" , 0x1180080e0d7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6902" , 0x1180080e0d7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6903" , 0x1180080e0d7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6904" , 0x1180080e0d7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6905" , 0x1180080e0d7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6906" , 0x1180080e0d7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6907" , 0x1180080e0d7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6908" , 0x1180080e0d7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6909" , 0x1180080e0d7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6910" , 0x1180080e0d7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6911" , 0x1180080e0d7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6912" , 0x1180080e0d800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6913" , 0x1180080e0d808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6914" , 0x1180080e0d810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6915" , 0x1180080e0d818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6916" , 0x1180080e0d820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6917" , 0x1180080e0d828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6918" , 0x1180080e0d830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6919" , 0x1180080e0d838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6920" , 0x1180080e0d840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6921" , 0x1180080e0d848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6922" , 0x1180080e0d850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6923" , 0x1180080e0d858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6924" , 0x1180080e0d860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6925" , 0x1180080e0d868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6926" , 0x1180080e0d870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6927" , 0x1180080e0d878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6928" , 0x1180080e0d880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6929" , 0x1180080e0d888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6930" , 0x1180080e0d890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6931" , 0x1180080e0d898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6932" , 0x1180080e0d8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6933" , 0x1180080e0d8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6934" , 0x1180080e0d8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6935" , 0x1180080e0d8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6936" , 0x1180080e0d8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6937" , 0x1180080e0d8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6938" , 0x1180080e0d8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6939" , 0x1180080e0d8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6940" , 0x1180080e0d8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6941" , 0x1180080e0d8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6942" , 0x1180080e0d8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6943" , 0x1180080e0d8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6944" , 0x1180080e0d900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6945" , 0x1180080e0d908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6946" , 0x1180080e0d910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6947" , 0x1180080e0d918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6948" , 0x1180080e0d920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6949" , 0x1180080e0d928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6950" , 0x1180080e0d930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6951" , 0x1180080e0d938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6952" , 0x1180080e0d940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6953" , 0x1180080e0d948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6954" , 0x1180080e0d950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6955" , 0x1180080e0d958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6956" , 0x1180080e0d960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6957" , 0x1180080e0d968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6958" , 0x1180080e0d970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6959" , 0x1180080e0d978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6960" , 0x1180080e0d980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6961" , 0x1180080e0d988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6962" , 0x1180080e0d990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6963" , 0x1180080e0d998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6964" , 0x1180080e0d9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6965" , 0x1180080e0d9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6966" , 0x1180080e0d9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6967" , 0x1180080e0d9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6968" , 0x1180080e0d9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6969" , 0x1180080e0d9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6970" , 0x1180080e0d9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6971" , 0x1180080e0d9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6972" , 0x1180080e0d9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6973" , 0x1180080e0d9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6974" , 0x1180080e0d9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6975" , 0x1180080e0d9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6976" , 0x1180080e0da00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6977" , 0x1180080e0da08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6978" , 0x1180080e0da10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6979" , 0x1180080e0da18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6980" , 0x1180080e0da20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6981" , 0x1180080e0da28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6982" , 0x1180080e0da30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6983" , 0x1180080e0da38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6984" , 0x1180080e0da40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6985" , 0x1180080e0da48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6986" , 0x1180080e0da50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6987" , 0x1180080e0da58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6988" , 0x1180080e0da60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6989" , 0x1180080e0da68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6990" , 0x1180080e0da70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6991" , 0x1180080e0da78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6992" , 0x1180080e0da80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6993" , 0x1180080e0da88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6994" , 0x1180080e0da90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6995" , 0x1180080e0da98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6996" , 0x1180080e0daa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6997" , 0x1180080e0daa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6998" , 0x1180080e0dab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP6999" , 0x1180080e0dab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7000" , 0x1180080e0dac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7001" , 0x1180080e0dac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7002" , 0x1180080e0dad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7003" , 0x1180080e0dad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7004" , 0x1180080e0dae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7005" , 0x1180080e0dae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7006" , 0x1180080e0daf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7007" , 0x1180080e0daf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7008" , 0x1180080e0db00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7009" , 0x1180080e0db08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7010" , 0x1180080e0db10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7011" , 0x1180080e0db18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7012" , 0x1180080e0db20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7013" , 0x1180080e0db28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7014" , 0x1180080e0db30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7015" , 0x1180080e0db38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7016" , 0x1180080e0db40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7017" , 0x1180080e0db48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7018" , 0x1180080e0db50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7019" , 0x1180080e0db58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7020" , 0x1180080e0db60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7021" , 0x1180080e0db68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7022" , 0x1180080e0db70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7023" , 0x1180080e0db78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7024" , 0x1180080e0db80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7025" , 0x1180080e0db88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7026" , 0x1180080e0db90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7027" , 0x1180080e0db98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7028" , 0x1180080e0dba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7029" , 0x1180080e0dba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7030" , 0x1180080e0dbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7031" , 0x1180080e0dbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7032" , 0x1180080e0dbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7033" , 0x1180080e0dbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7034" , 0x1180080e0dbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7035" , 0x1180080e0dbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7036" , 0x1180080e0dbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7037" , 0x1180080e0dbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7038" , 0x1180080e0dbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7039" , 0x1180080e0dbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7040" , 0x1180080e0dc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7041" , 0x1180080e0dc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7042" , 0x1180080e0dc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7043" , 0x1180080e0dc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7044" , 0x1180080e0dc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7045" , 0x1180080e0dc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7046" , 0x1180080e0dc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7047" , 0x1180080e0dc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7048" , 0x1180080e0dc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7049" , 0x1180080e0dc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7050" , 0x1180080e0dc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7051" , 0x1180080e0dc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7052" , 0x1180080e0dc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7053" , 0x1180080e0dc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7054" , 0x1180080e0dc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7055" , 0x1180080e0dc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7056" , 0x1180080e0dc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7057" , 0x1180080e0dc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7058" , 0x1180080e0dc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7059" , 0x1180080e0dc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7060" , 0x1180080e0dca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7061" , 0x1180080e0dca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7062" , 0x1180080e0dcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7063" , 0x1180080e0dcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7064" , 0x1180080e0dcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7065" , 0x1180080e0dcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7066" , 0x1180080e0dcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7067" , 0x1180080e0dcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7068" , 0x1180080e0dce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7069" , 0x1180080e0dce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7070" , 0x1180080e0dcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7071" , 0x1180080e0dcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7072" , 0x1180080e0dd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7073" , 0x1180080e0dd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7074" , 0x1180080e0dd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7075" , 0x1180080e0dd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7076" , 0x1180080e0dd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7077" , 0x1180080e0dd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7078" , 0x1180080e0dd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7079" , 0x1180080e0dd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7080" , 0x1180080e0dd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7081" , 0x1180080e0dd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7082" , 0x1180080e0dd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7083" , 0x1180080e0dd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7084" , 0x1180080e0dd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7085" , 0x1180080e0dd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7086" , 0x1180080e0dd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7087" , 0x1180080e0dd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7088" , 0x1180080e0dd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7089" , 0x1180080e0dd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7090" , 0x1180080e0dd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7091" , 0x1180080e0dd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7092" , 0x1180080e0dda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7093" , 0x1180080e0dda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7094" , 0x1180080e0ddb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7095" , 0x1180080e0ddb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7096" , 0x1180080e0ddc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7097" , 0x1180080e0ddc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7098" , 0x1180080e0ddd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7099" , 0x1180080e0ddd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7100" , 0x1180080e0dde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7101" , 0x1180080e0dde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7102" , 0x1180080e0ddf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7103" , 0x1180080e0ddf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7104" , 0x1180080e0de00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7105" , 0x1180080e0de08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7106" , 0x1180080e0de10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7107" , 0x1180080e0de18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7108" , 0x1180080e0de20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7109" , 0x1180080e0de28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7110" , 0x1180080e0de30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7111" , 0x1180080e0de38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7112" , 0x1180080e0de40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7113" , 0x1180080e0de48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7114" , 0x1180080e0de50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7115" , 0x1180080e0de58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7116" , 0x1180080e0de60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7117" , 0x1180080e0de68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7118" , 0x1180080e0de70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7119" , 0x1180080e0de78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7120" , 0x1180080e0de80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7121" , 0x1180080e0de88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7122" , 0x1180080e0de90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7123" , 0x1180080e0de98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7124" , 0x1180080e0dea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7125" , 0x1180080e0dea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7126" , 0x1180080e0deb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7127" , 0x1180080e0deb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7128" , 0x1180080e0dec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7129" , 0x1180080e0dec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7130" , 0x1180080e0ded0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7131" , 0x1180080e0ded8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7132" , 0x1180080e0dee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7133" , 0x1180080e0dee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7134" , 0x1180080e0def0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7135" , 0x1180080e0def8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7136" , 0x1180080e0df00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7137" , 0x1180080e0df08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7138" , 0x1180080e0df10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7139" , 0x1180080e0df18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7140" , 0x1180080e0df20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7141" , 0x1180080e0df28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7142" , 0x1180080e0df30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7143" , 0x1180080e0df38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7144" , 0x1180080e0df40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7145" , 0x1180080e0df48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7146" , 0x1180080e0df50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7147" , 0x1180080e0df58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7148" , 0x1180080e0df60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7149" , 0x1180080e0df68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7150" , 0x1180080e0df70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7151" , 0x1180080e0df78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7152" , 0x1180080e0df80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7153" , 0x1180080e0df88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7154" , 0x1180080e0df90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7155" , 0x1180080e0df98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7156" , 0x1180080e0dfa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7157" , 0x1180080e0dfa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7158" , 0x1180080e0dfb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7159" , 0x1180080e0dfb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7160" , 0x1180080e0dfc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7161" , 0x1180080e0dfc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7162" , 0x1180080e0dfd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7163" , 0x1180080e0dfd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7164" , 0x1180080e0dfe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7165" , 0x1180080e0dfe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7166" , 0x1180080e0dff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7167" , 0x1180080e0dff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7168" , 0x1180080e0e000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7169" , 0x1180080e0e008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7170" , 0x1180080e0e010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7171" , 0x1180080e0e018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7172" , 0x1180080e0e020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7173" , 0x1180080e0e028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7174" , 0x1180080e0e030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7175" , 0x1180080e0e038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7176" , 0x1180080e0e040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7177" , 0x1180080e0e048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7178" , 0x1180080e0e050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7179" , 0x1180080e0e058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7180" , 0x1180080e0e060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7181" , 0x1180080e0e068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7182" , 0x1180080e0e070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7183" , 0x1180080e0e078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7184" , 0x1180080e0e080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7185" , 0x1180080e0e088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7186" , 0x1180080e0e090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7187" , 0x1180080e0e098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7188" , 0x1180080e0e0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7189" , 0x1180080e0e0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7190" , 0x1180080e0e0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7191" , 0x1180080e0e0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7192" , 0x1180080e0e0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7193" , 0x1180080e0e0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7194" , 0x1180080e0e0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7195" , 0x1180080e0e0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7196" , 0x1180080e0e0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7197" , 0x1180080e0e0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7198" , 0x1180080e0e0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7199" , 0x1180080e0e0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7200" , 0x1180080e0e100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7201" , 0x1180080e0e108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7202" , 0x1180080e0e110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7203" , 0x1180080e0e118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7204" , 0x1180080e0e120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7205" , 0x1180080e0e128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7206" , 0x1180080e0e130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7207" , 0x1180080e0e138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7208" , 0x1180080e0e140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7209" , 0x1180080e0e148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7210" , 0x1180080e0e150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7211" , 0x1180080e0e158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7212" , 0x1180080e0e160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7213" , 0x1180080e0e168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7214" , 0x1180080e0e170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7215" , 0x1180080e0e178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7216" , 0x1180080e0e180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7217" , 0x1180080e0e188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7218" , 0x1180080e0e190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7219" , 0x1180080e0e198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7220" , 0x1180080e0e1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7221" , 0x1180080e0e1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7222" , 0x1180080e0e1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7223" , 0x1180080e0e1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7224" , 0x1180080e0e1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7225" , 0x1180080e0e1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7226" , 0x1180080e0e1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7227" , 0x1180080e0e1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7228" , 0x1180080e0e1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7229" , 0x1180080e0e1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7230" , 0x1180080e0e1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7231" , 0x1180080e0e1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7232" , 0x1180080e0e200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7233" , 0x1180080e0e208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7234" , 0x1180080e0e210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7235" , 0x1180080e0e218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7236" , 0x1180080e0e220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7237" , 0x1180080e0e228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7238" , 0x1180080e0e230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7239" , 0x1180080e0e238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7240" , 0x1180080e0e240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7241" , 0x1180080e0e248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7242" , 0x1180080e0e250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7243" , 0x1180080e0e258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7244" , 0x1180080e0e260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7245" , 0x1180080e0e268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7246" , 0x1180080e0e270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7247" , 0x1180080e0e278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7248" , 0x1180080e0e280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7249" , 0x1180080e0e288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7250" , 0x1180080e0e290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7251" , 0x1180080e0e298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7252" , 0x1180080e0e2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7253" , 0x1180080e0e2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7254" , 0x1180080e0e2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7255" , 0x1180080e0e2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7256" , 0x1180080e0e2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7257" , 0x1180080e0e2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7258" , 0x1180080e0e2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7259" , 0x1180080e0e2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7260" , 0x1180080e0e2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7261" , 0x1180080e0e2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7262" , 0x1180080e0e2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7263" , 0x1180080e0e2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7264" , 0x1180080e0e300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7265" , 0x1180080e0e308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7266" , 0x1180080e0e310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7267" , 0x1180080e0e318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7268" , 0x1180080e0e320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7269" , 0x1180080e0e328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7270" , 0x1180080e0e330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7271" , 0x1180080e0e338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7272" , 0x1180080e0e340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7273" , 0x1180080e0e348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7274" , 0x1180080e0e350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7275" , 0x1180080e0e358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7276" , 0x1180080e0e360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7277" , 0x1180080e0e368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7278" , 0x1180080e0e370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7279" , 0x1180080e0e378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7280" , 0x1180080e0e380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7281" , 0x1180080e0e388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7282" , 0x1180080e0e390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7283" , 0x1180080e0e398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7284" , 0x1180080e0e3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7285" , 0x1180080e0e3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7286" , 0x1180080e0e3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7287" , 0x1180080e0e3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7288" , 0x1180080e0e3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7289" , 0x1180080e0e3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7290" , 0x1180080e0e3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7291" , 0x1180080e0e3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7292" , 0x1180080e0e3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7293" , 0x1180080e0e3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7294" , 0x1180080e0e3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7295" , 0x1180080e0e3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7296" , 0x1180080e0e400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7297" , 0x1180080e0e408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7298" , 0x1180080e0e410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7299" , 0x1180080e0e418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7300" , 0x1180080e0e420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7301" , 0x1180080e0e428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7302" , 0x1180080e0e430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7303" , 0x1180080e0e438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7304" , 0x1180080e0e440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7305" , 0x1180080e0e448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7306" , 0x1180080e0e450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7307" , 0x1180080e0e458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7308" , 0x1180080e0e460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7309" , 0x1180080e0e468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7310" , 0x1180080e0e470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7311" , 0x1180080e0e478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7312" , 0x1180080e0e480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7313" , 0x1180080e0e488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7314" , 0x1180080e0e490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7315" , 0x1180080e0e498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7316" , 0x1180080e0e4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7317" , 0x1180080e0e4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7318" , 0x1180080e0e4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7319" , 0x1180080e0e4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7320" , 0x1180080e0e4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7321" , 0x1180080e0e4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7322" , 0x1180080e0e4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7323" , 0x1180080e0e4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7324" , 0x1180080e0e4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7325" , 0x1180080e0e4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7326" , 0x1180080e0e4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7327" , 0x1180080e0e4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7328" , 0x1180080e0e500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7329" , 0x1180080e0e508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7330" , 0x1180080e0e510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7331" , 0x1180080e0e518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7332" , 0x1180080e0e520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7333" , 0x1180080e0e528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7334" , 0x1180080e0e530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7335" , 0x1180080e0e538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7336" , 0x1180080e0e540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7337" , 0x1180080e0e548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7338" , 0x1180080e0e550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7339" , 0x1180080e0e558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7340" , 0x1180080e0e560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7341" , 0x1180080e0e568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7342" , 0x1180080e0e570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7343" , 0x1180080e0e578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7344" , 0x1180080e0e580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7345" , 0x1180080e0e588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7346" , 0x1180080e0e590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7347" , 0x1180080e0e598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7348" , 0x1180080e0e5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7349" , 0x1180080e0e5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7350" , 0x1180080e0e5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7351" , 0x1180080e0e5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7352" , 0x1180080e0e5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7353" , 0x1180080e0e5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7354" , 0x1180080e0e5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7355" , 0x1180080e0e5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7356" , 0x1180080e0e5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7357" , 0x1180080e0e5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7358" , 0x1180080e0e5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7359" , 0x1180080e0e5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7360" , 0x1180080e0e600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7361" , 0x1180080e0e608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7362" , 0x1180080e0e610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7363" , 0x1180080e0e618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7364" , 0x1180080e0e620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7365" , 0x1180080e0e628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7366" , 0x1180080e0e630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7367" , 0x1180080e0e638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7368" , 0x1180080e0e640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7369" , 0x1180080e0e648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7370" , 0x1180080e0e650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7371" , 0x1180080e0e658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7372" , 0x1180080e0e660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7373" , 0x1180080e0e668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7374" , 0x1180080e0e670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7375" , 0x1180080e0e678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7376" , 0x1180080e0e680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7377" , 0x1180080e0e688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7378" , 0x1180080e0e690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7379" , 0x1180080e0e698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7380" , 0x1180080e0e6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7381" , 0x1180080e0e6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7382" , 0x1180080e0e6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7383" , 0x1180080e0e6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7384" , 0x1180080e0e6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7385" , 0x1180080e0e6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7386" , 0x1180080e0e6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7387" , 0x1180080e0e6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7388" , 0x1180080e0e6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7389" , 0x1180080e0e6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7390" , 0x1180080e0e6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7391" , 0x1180080e0e6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7392" , 0x1180080e0e700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7393" , 0x1180080e0e708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7394" , 0x1180080e0e710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7395" , 0x1180080e0e718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7396" , 0x1180080e0e720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7397" , 0x1180080e0e728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7398" , 0x1180080e0e730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7399" , 0x1180080e0e738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7400" , 0x1180080e0e740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7401" , 0x1180080e0e748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7402" , 0x1180080e0e750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7403" , 0x1180080e0e758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7404" , 0x1180080e0e760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7405" , 0x1180080e0e768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7406" , 0x1180080e0e770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7407" , 0x1180080e0e778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7408" , 0x1180080e0e780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7409" , 0x1180080e0e788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7410" , 0x1180080e0e790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7411" , 0x1180080e0e798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7412" , 0x1180080e0e7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7413" , 0x1180080e0e7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7414" , 0x1180080e0e7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7415" , 0x1180080e0e7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7416" , 0x1180080e0e7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7417" , 0x1180080e0e7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7418" , 0x1180080e0e7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7419" , 0x1180080e0e7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7420" , 0x1180080e0e7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7421" , 0x1180080e0e7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7422" , 0x1180080e0e7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7423" , 0x1180080e0e7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7424" , 0x1180080e0e800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7425" , 0x1180080e0e808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7426" , 0x1180080e0e810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7427" , 0x1180080e0e818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7428" , 0x1180080e0e820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7429" , 0x1180080e0e828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7430" , 0x1180080e0e830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7431" , 0x1180080e0e838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7432" , 0x1180080e0e840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7433" , 0x1180080e0e848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7434" , 0x1180080e0e850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7435" , 0x1180080e0e858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7436" , 0x1180080e0e860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7437" , 0x1180080e0e868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7438" , 0x1180080e0e870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7439" , 0x1180080e0e878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7440" , 0x1180080e0e880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7441" , 0x1180080e0e888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7442" , 0x1180080e0e890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7443" , 0x1180080e0e898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7444" , 0x1180080e0e8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7445" , 0x1180080e0e8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7446" , 0x1180080e0e8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7447" , 0x1180080e0e8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7448" , 0x1180080e0e8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7449" , 0x1180080e0e8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7450" , 0x1180080e0e8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7451" , 0x1180080e0e8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7452" , 0x1180080e0e8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7453" , 0x1180080e0e8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7454" , 0x1180080e0e8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7455" , 0x1180080e0e8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7456" , 0x1180080e0e900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7457" , 0x1180080e0e908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7458" , 0x1180080e0e910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7459" , 0x1180080e0e918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7460" , 0x1180080e0e920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7461" , 0x1180080e0e928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7462" , 0x1180080e0e930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7463" , 0x1180080e0e938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7464" , 0x1180080e0e940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7465" , 0x1180080e0e948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7466" , 0x1180080e0e950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7467" , 0x1180080e0e958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7468" , 0x1180080e0e960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7469" , 0x1180080e0e968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7470" , 0x1180080e0e970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7471" , 0x1180080e0e978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7472" , 0x1180080e0e980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7473" , 0x1180080e0e988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7474" , 0x1180080e0e990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7475" , 0x1180080e0e998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7476" , 0x1180080e0e9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7477" , 0x1180080e0e9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7478" , 0x1180080e0e9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7479" , 0x1180080e0e9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7480" , 0x1180080e0e9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7481" , 0x1180080e0e9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7482" , 0x1180080e0e9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7483" , 0x1180080e0e9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7484" , 0x1180080e0e9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7485" , 0x1180080e0e9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7486" , 0x1180080e0e9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7487" , 0x1180080e0e9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7488" , 0x1180080e0ea00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7489" , 0x1180080e0ea08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7490" , 0x1180080e0ea10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7491" , 0x1180080e0ea18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7492" , 0x1180080e0ea20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7493" , 0x1180080e0ea28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7494" , 0x1180080e0ea30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7495" , 0x1180080e0ea38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7496" , 0x1180080e0ea40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7497" , 0x1180080e0ea48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7498" , 0x1180080e0ea50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7499" , 0x1180080e0ea58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7500" , 0x1180080e0ea60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7501" , 0x1180080e0ea68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7502" , 0x1180080e0ea70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7503" , 0x1180080e0ea78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7504" , 0x1180080e0ea80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7505" , 0x1180080e0ea88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7506" , 0x1180080e0ea90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7507" , 0x1180080e0ea98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7508" , 0x1180080e0eaa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7509" , 0x1180080e0eaa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7510" , 0x1180080e0eab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7511" , 0x1180080e0eab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7512" , 0x1180080e0eac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7513" , 0x1180080e0eac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7514" , 0x1180080e0ead0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7515" , 0x1180080e0ead8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7516" , 0x1180080e0eae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7517" , 0x1180080e0eae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7518" , 0x1180080e0eaf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7519" , 0x1180080e0eaf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7520" , 0x1180080e0eb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7521" , 0x1180080e0eb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7522" , 0x1180080e0eb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7523" , 0x1180080e0eb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7524" , 0x1180080e0eb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7525" , 0x1180080e0eb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7526" , 0x1180080e0eb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7527" , 0x1180080e0eb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7528" , 0x1180080e0eb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7529" , 0x1180080e0eb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7530" , 0x1180080e0eb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7531" , 0x1180080e0eb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7532" , 0x1180080e0eb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7533" , 0x1180080e0eb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7534" , 0x1180080e0eb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7535" , 0x1180080e0eb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7536" , 0x1180080e0eb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7537" , 0x1180080e0eb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7538" , 0x1180080e0eb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7539" , 0x1180080e0eb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7540" , 0x1180080e0eba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7541" , 0x1180080e0eba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7542" , 0x1180080e0ebb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7543" , 0x1180080e0ebb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7544" , 0x1180080e0ebc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7545" , 0x1180080e0ebc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7546" , 0x1180080e0ebd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7547" , 0x1180080e0ebd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7548" , 0x1180080e0ebe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7549" , 0x1180080e0ebe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7550" , 0x1180080e0ebf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7551" , 0x1180080e0ebf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7552" , 0x1180080e0ec00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7553" , 0x1180080e0ec08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7554" , 0x1180080e0ec10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7555" , 0x1180080e0ec18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7556" , 0x1180080e0ec20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7557" , 0x1180080e0ec28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7558" , 0x1180080e0ec30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7559" , 0x1180080e0ec38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7560" , 0x1180080e0ec40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7561" , 0x1180080e0ec48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7562" , 0x1180080e0ec50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7563" , 0x1180080e0ec58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7564" , 0x1180080e0ec60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7565" , 0x1180080e0ec68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7566" , 0x1180080e0ec70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7567" , 0x1180080e0ec78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7568" , 0x1180080e0ec80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7569" , 0x1180080e0ec88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7570" , 0x1180080e0ec90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7571" , 0x1180080e0ec98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7572" , 0x1180080e0eca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7573" , 0x1180080e0eca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7574" , 0x1180080e0ecb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7575" , 0x1180080e0ecb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7576" , 0x1180080e0ecc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7577" , 0x1180080e0ecc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7578" , 0x1180080e0ecd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7579" , 0x1180080e0ecd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7580" , 0x1180080e0ece0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7581" , 0x1180080e0ece8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7582" , 0x1180080e0ecf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7583" , 0x1180080e0ecf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7584" , 0x1180080e0ed00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7585" , 0x1180080e0ed08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7586" , 0x1180080e0ed10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7587" , 0x1180080e0ed18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7588" , 0x1180080e0ed20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7589" , 0x1180080e0ed28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7590" , 0x1180080e0ed30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7591" , 0x1180080e0ed38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7592" , 0x1180080e0ed40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7593" , 0x1180080e0ed48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7594" , 0x1180080e0ed50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7595" , 0x1180080e0ed58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7596" , 0x1180080e0ed60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7597" , 0x1180080e0ed68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7598" , 0x1180080e0ed70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7599" , 0x1180080e0ed78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7600" , 0x1180080e0ed80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7601" , 0x1180080e0ed88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7602" , 0x1180080e0ed90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7603" , 0x1180080e0ed98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7604" , 0x1180080e0eda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7605" , 0x1180080e0eda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7606" , 0x1180080e0edb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7607" , 0x1180080e0edb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7608" , 0x1180080e0edc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7609" , 0x1180080e0edc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7610" , 0x1180080e0edd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7611" , 0x1180080e0edd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7612" , 0x1180080e0ede0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7613" , 0x1180080e0ede8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7614" , 0x1180080e0edf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7615" , 0x1180080e0edf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7616" , 0x1180080e0ee00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7617" , 0x1180080e0ee08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7618" , 0x1180080e0ee10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7619" , 0x1180080e0ee18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7620" , 0x1180080e0ee20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7621" , 0x1180080e0ee28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7622" , 0x1180080e0ee30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7623" , 0x1180080e0ee38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7624" , 0x1180080e0ee40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7625" , 0x1180080e0ee48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7626" , 0x1180080e0ee50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7627" , 0x1180080e0ee58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7628" , 0x1180080e0ee60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7629" , 0x1180080e0ee68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7630" , 0x1180080e0ee70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7631" , 0x1180080e0ee78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7632" , 0x1180080e0ee80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7633" , 0x1180080e0ee88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7634" , 0x1180080e0ee90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7635" , 0x1180080e0ee98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7636" , 0x1180080e0eea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7637" , 0x1180080e0eea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7638" , 0x1180080e0eeb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7639" , 0x1180080e0eeb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7640" , 0x1180080e0eec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7641" , 0x1180080e0eec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7642" , 0x1180080e0eed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7643" , 0x1180080e0eed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7644" , 0x1180080e0eee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7645" , 0x1180080e0eee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7646" , 0x1180080e0eef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7647" , 0x1180080e0eef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7648" , 0x1180080e0ef00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7649" , 0x1180080e0ef08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7650" , 0x1180080e0ef10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7651" , 0x1180080e0ef18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7652" , 0x1180080e0ef20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7653" , 0x1180080e0ef28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7654" , 0x1180080e0ef30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7655" , 0x1180080e0ef38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7656" , 0x1180080e0ef40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7657" , 0x1180080e0ef48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7658" , 0x1180080e0ef50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7659" , 0x1180080e0ef58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7660" , 0x1180080e0ef60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7661" , 0x1180080e0ef68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7662" , 0x1180080e0ef70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7663" , 0x1180080e0ef78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7664" , 0x1180080e0ef80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7665" , 0x1180080e0ef88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7666" , 0x1180080e0ef90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7667" , 0x1180080e0ef98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7668" , 0x1180080e0efa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7669" , 0x1180080e0efa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7670" , 0x1180080e0efb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7671" , 0x1180080e0efb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7672" , 0x1180080e0efc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7673" , 0x1180080e0efc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7674" , 0x1180080e0efd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7675" , 0x1180080e0efd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7676" , 0x1180080e0efe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7677" , 0x1180080e0efe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7678" , 0x1180080e0eff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7679" , 0x1180080e0eff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7680" , 0x1180080e0f000ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7681" , 0x1180080e0f008ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7682" , 0x1180080e0f010ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7683" , 0x1180080e0f018ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7684" , 0x1180080e0f020ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7685" , 0x1180080e0f028ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7686" , 0x1180080e0f030ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7687" , 0x1180080e0f038ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7688" , 0x1180080e0f040ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7689" , 0x1180080e0f048ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7690" , 0x1180080e0f050ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7691" , 0x1180080e0f058ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7692" , 0x1180080e0f060ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7693" , 0x1180080e0f068ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7694" , 0x1180080e0f070ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7695" , 0x1180080e0f078ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7696" , 0x1180080e0f080ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7697" , 0x1180080e0f088ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7698" , 0x1180080e0f090ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7699" , 0x1180080e0f098ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7700" , 0x1180080e0f0a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7701" , 0x1180080e0f0a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7702" , 0x1180080e0f0b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7703" , 0x1180080e0f0b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7704" , 0x1180080e0f0c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7705" , 0x1180080e0f0c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7706" , 0x1180080e0f0d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7707" , 0x1180080e0f0d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7708" , 0x1180080e0f0e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7709" , 0x1180080e0f0e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7710" , 0x1180080e0f0f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7711" , 0x1180080e0f0f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7712" , 0x1180080e0f100ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7713" , 0x1180080e0f108ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7714" , 0x1180080e0f110ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7715" , 0x1180080e0f118ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7716" , 0x1180080e0f120ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7717" , 0x1180080e0f128ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7718" , 0x1180080e0f130ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7719" , 0x1180080e0f138ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7720" , 0x1180080e0f140ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7721" , 0x1180080e0f148ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7722" , 0x1180080e0f150ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7723" , 0x1180080e0f158ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7724" , 0x1180080e0f160ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7725" , 0x1180080e0f168ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7726" , 0x1180080e0f170ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7727" , 0x1180080e0f178ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7728" , 0x1180080e0f180ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7729" , 0x1180080e0f188ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7730" , 0x1180080e0f190ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7731" , 0x1180080e0f198ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7732" , 0x1180080e0f1a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7733" , 0x1180080e0f1a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7734" , 0x1180080e0f1b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7735" , 0x1180080e0f1b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7736" , 0x1180080e0f1c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7737" , 0x1180080e0f1c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7738" , 0x1180080e0f1d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7739" , 0x1180080e0f1d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7740" , 0x1180080e0f1e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7741" , 0x1180080e0f1e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7742" , 0x1180080e0f1f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7743" , 0x1180080e0f1f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7744" , 0x1180080e0f200ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7745" , 0x1180080e0f208ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7746" , 0x1180080e0f210ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7747" , 0x1180080e0f218ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7748" , 0x1180080e0f220ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7749" , 0x1180080e0f228ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7750" , 0x1180080e0f230ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7751" , 0x1180080e0f238ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7752" , 0x1180080e0f240ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7753" , 0x1180080e0f248ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7754" , 0x1180080e0f250ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7755" , 0x1180080e0f258ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7756" , 0x1180080e0f260ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7757" , 0x1180080e0f268ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7758" , 0x1180080e0f270ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7759" , 0x1180080e0f278ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7760" , 0x1180080e0f280ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7761" , 0x1180080e0f288ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7762" , 0x1180080e0f290ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7763" , 0x1180080e0f298ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7764" , 0x1180080e0f2a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7765" , 0x1180080e0f2a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7766" , 0x1180080e0f2b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7767" , 0x1180080e0f2b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7768" , 0x1180080e0f2c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7769" , 0x1180080e0f2c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7770" , 0x1180080e0f2d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7771" , 0x1180080e0f2d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7772" , 0x1180080e0f2e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7773" , 0x1180080e0f2e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7774" , 0x1180080e0f2f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7775" , 0x1180080e0f2f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7776" , 0x1180080e0f300ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7777" , 0x1180080e0f308ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7778" , 0x1180080e0f310ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7779" , 0x1180080e0f318ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7780" , 0x1180080e0f320ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7781" , 0x1180080e0f328ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7782" , 0x1180080e0f330ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7783" , 0x1180080e0f338ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7784" , 0x1180080e0f340ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7785" , 0x1180080e0f348ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7786" , 0x1180080e0f350ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7787" , 0x1180080e0f358ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7788" , 0x1180080e0f360ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7789" , 0x1180080e0f368ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7790" , 0x1180080e0f370ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7791" , 0x1180080e0f378ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7792" , 0x1180080e0f380ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7793" , 0x1180080e0f388ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7794" , 0x1180080e0f390ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7795" , 0x1180080e0f398ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7796" , 0x1180080e0f3a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7797" , 0x1180080e0f3a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7798" , 0x1180080e0f3b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7799" , 0x1180080e0f3b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7800" , 0x1180080e0f3c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7801" , 0x1180080e0f3c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7802" , 0x1180080e0f3d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7803" , 0x1180080e0f3d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7804" , 0x1180080e0f3e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7805" , 0x1180080e0f3e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7806" , 0x1180080e0f3f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7807" , 0x1180080e0f3f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7808" , 0x1180080e0f400ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7809" , 0x1180080e0f408ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7810" , 0x1180080e0f410ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7811" , 0x1180080e0f418ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7812" , 0x1180080e0f420ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7813" , 0x1180080e0f428ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7814" , 0x1180080e0f430ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7815" , 0x1180080e0f438ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7816" , 0x1180080e0f440ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7817" , 0x1180080e0f448ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7818" , 0x1180080e0f450ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7819" , 0x1180080e0f458ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7820" , 0x1180080e0f460ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7821" , 0x1180080e0f468ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7822" , 0x1180080e0f470ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7823" , 0x1180080e0f478ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7824" , 0x1180080e0f480ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7825" , 0x1180080e0f488ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7826" , 0x1180080e0f490ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7827" , 0x1180080e0f498ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7828" , 0x1180080e0f4a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7829" , 0x1180080e0f4a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7830" , 0x1180080e0f4b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7831" , 0x1180080e0f4b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7832" , 0x1180080e0f4c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7833" , 0x1180080e0f4c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7834" , 0x1180080e0f4d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7835" , 0x1180080e0f4d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7836" , 0x1180080e0f4e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7837" , 0x1180080e0f4e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7838" , 0x1180080e0f4f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7839" , 0x1180080e0f4f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7840" , 0x1180080e0f500ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7841" , 0x1180080e0f508ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7842" , 0x1180080e0f510ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7843" , 0x1180080e0f518ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7844" , 0x1180080e0f520ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7845" , 0x1180080e0f528ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7846" , 0x1180080e0f530ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7847" , 0x1180080e0f538ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7848" , 0x1180080e0f540ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7849" , 0x1180080e0f548ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7850" , 0x1180080e0f550ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7851" , 0x1180080e0f558ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7852" , 0x1180080e0f560ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7853" , 0x1180080e0f568ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7854" , 0x1180080e0f570ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7855" , 0x1180080e0f578ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7856" , 0x1180080e0f580ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7857" , 0x1180080e0f588ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7858" , 0x1180080e0f590ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7859" , 0x1180080e0f598ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7860" , 0x1180080e0f5a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7861" , 0x1180080e0f5a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7862" , 0x1180080e0f5b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7863" , 0x1180080e0f5b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7864" , 0x1180080e0f5c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7865" , 0x1180080e0f5c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7866" , 0x1180080e0f5d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7867" , 0x1180080e0f5d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7868" , 0x1180080e0f5e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7869" , 0x1180080e0f5e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7870" , 0x1180080e0f5f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7871" , 0x1180080e0f5f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7872" , 0x1180080e0f600ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7873" , 0x1180080e0f608ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7874" , 0x1180080e0f610ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7875" , 0x1180080e0f618ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7876" , 0x1180080e0f620ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7877" , 0x1180080e0f628ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7878" , 0x1180080e0f630ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7879" , 0x1180080e0f638ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7880" , 0x1180080e0f640ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7881" , 0x1180080e0f648ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7882" , 0x1180080e0f650ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7883" , 0x1180080e0f658ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7884" , 0x1180080e0f660ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7885" , 0x1180080e0f668ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7886" , 0x1180080e0f670ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7887" , 0x1180080e0f678ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7888" , 0x1180080e0f680ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7889" , 0x1180080e0f688ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7890" , 0x1180080e0f690ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7891" , 0x1180080e0f698ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7892" , 0x1180080e0f6a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7893" , 0x1180080e0f6a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7894" , 0x1180080e0f6b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7895" , 0x1180080e0f6b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7896" , 0x1180080e0f6c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7897" , 0x1180080e0f6c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7898" , 0x1180080e0f6d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7899" , 0x1180080e0f6d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7900" , 0x1180080e0f6e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7901" , 0x1180080e0f6e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7902" , 0x1180080e0f6f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7903" , 0x1180080e0f6f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7904" , 0x1180080e0f700ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7905" , 0x1180080e0f708ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7906" , 0x1180080e0f710ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7907" , 0x1180080e0f718ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7908" , 0x1180080e0f720ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7909" , 0x1180080e0f728ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7910" , 0x1180080e0f730ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7911" , 0x1180080e0f738ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7912" , 0x1180080e0f740ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7913" , 0x1180080e0f748ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7914" , 0x1180080e0f750ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7915" , 0x1180080e0f758ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7916" , 0x1180080e0f760ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7917" , 0x1180080e0f768ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7918" , 0x1180080e0f770ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7919" , 0x1180080e0f778ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7920" , 0x1180080e0f780ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7921" , 0x1180080e0f788ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7922" , 0x1180080e0f790ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7923" , 0x1180080e0f798ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7924" , 0x1180080e0f7a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7925" , 0x1180080e0f7a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7926" , 0x1180080e0f7b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7927" , 0x1180080e0f7b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7928" , 0x1180080e0f7c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7929" , 0x1180080e0f7c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7930" , 0x1180080e0f7d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7931" , 0x1180080e0f7d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7932" , 0x1180080e0f7e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7933" , 0x1180080e0f7e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7934" , 0x1180080e0f7f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7935" , 0x1180080e0f7f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7936" , 0x1180080e0f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7937" , 0x1180080e0f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7938" , 0x1180080e0f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7939" , 0x1180080e0f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7940" , 0x1180080e0f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7941" , 0x1180080e0f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7942" , 0x1180080e0f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7943" , 0x1180080e0f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7944" , 0x1180080e0f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7945" , 0x1180080e0f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7946" , 0x1180080e0f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7947" , 0x1180080e0f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7948" , 0x1180080e0f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7949" , 0x1180080e0f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7950" , 0x1180080e0f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7951" , 0x1180080e0f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7952" , 0x1180080e0f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7953" , 0x1180080e0f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7954" , 0x1180080e0f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7955" , 0x1180080e0f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7956" , 0x1180080e0f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7957" , 0x1180080e0f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7958" , 0x1180080e0f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7959" , 0x1180080e0f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7960" , 0x1180080e0f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7961" , 0x1180080e0f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7962" , 0x1180080e0f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7963" , 0x1180080e0f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7964" , 0x1180080e0f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7965" , 0x1180080e0f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7966" , 0x1180080e0f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7967" , 0x1180080e0f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7968" , 0x1180080e0f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7969" , 0x1180080e0f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7970" , 0x1180080e0f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7971" , 0x1180080e0f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7972" , 0x1180080e0f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7973" , 0x1180080e0f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7974" , 0x1180080e0f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7975" , 0x1180080e0f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7976" , 0x1180080e0f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7977" , 0x1180080e0f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7978" , 0x1180080e0f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7979" , 0x1180080e0f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7980" , 0x1180080e0f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7981" , 0x1180080e0f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7982" , 0x1180080e0f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7983" , 0x1180080e0f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7984" , 0x1180080e0f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7985" , 0x1180080e0f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7986" , 0x1180080e0f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7987" , 0x1180080e0f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7988" , 0x1180080e0f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7989" , 0x1180080e0f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7990" , 0x1180080e0f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7991" , 0x1180080e0f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7992" , 0x1180080e0f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7993" , 0x1180080e0f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7994" , 0x1180080e0f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7995" , 0x1180080e0f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7996" , 0x1180080e0f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7997" , 0x1180080e0f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7998" , 0x1180080e0f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP7999" , 0x1180080e0f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8000" , 0x1180080e0fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8001" , 0x1180080e0fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8002" , 0x1180080e0fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8003" , 0x1180080e0fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8004" , 0x1180080e0fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8005" , 0x1180080e0fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8006" , 0x1180080e0fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8007" , 0x1180080e0fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8008" , 0x1180080e0fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8009" , 0x1180080e0fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8010" , 0x1180080e0fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8011" , 0x1180080e0fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8012" , 0x1180080e0fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8013" , 0x1180080e0fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8014" , 0x1180080e0fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8015" , 0x1180080e0fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8016" , 0x1180080e0fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8017" , 0x1180080e0fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8018" , 0x1180080e0fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8019" , 0x1180080e0fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8020" , 0x1180080e0faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8021" , 0x1180080e0faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8022" , 0x1180080e0fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8023" , 0x1180080e0fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8024" , 0x1180080e0fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8025" , 0x1180080e0fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8026" , 0x1180080e0fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8027" , 0x1180080e0fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8028" , 0x1180080e0fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8029" , 0x1180080e0fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8030" , 0x1180080e0faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8031" , 0x1180080e0faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8032" , 0x1180080e0fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8033" , 0x1180080e0fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8034" , 0x1180080e0fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8035" , 0x1180080e0fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8036" , 0x1180080e0fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8037" , 0x1180080e0fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8038" , 0x1180080e0fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8039" , 0x1180080e0fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8040" , 0x1180080e0fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8041" , 0x1180080e0fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8042" , 0x1180080e0fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8043" , 0x1180080e0fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8044" , 0x1180080e0fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8045" , 0x1180080e0fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8046" , 0x1180080e0fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8047" , 0x1180080e0fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8048" , 0x1180080e0fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8049" , 0x1180080e0fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8050" , 0x1180080e0fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8051" , 0x1180080e0fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8052" , 0x1180080e0fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8053" , 0x1180080e0fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8054" , 0x1180080e0fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8055" , 0x1180080e0fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8056" , 0x1180080e0fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8057" , 0x1180080e0fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8058" , 0x1180080e0fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8059" , 0x1180080e0fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8060" , 0x1180080e0fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8061" , 0x1180080e0fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8062" , 0x1180080e0fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8063" , 0x1180080e0fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8064" , 0x1180080e0fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8065" , 0x1180080e0fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8066" , 0x1180080e0fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8067" , 0x1180080e0fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8068" , 0x1180080e0fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8069" , 0x1180080e0fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8070" , 0x1180080e0fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8071" , 0x1180080e0fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8072" , 0x1180080e0fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8073" , 0x1180080e0fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8074" , 0x1180080e0fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8075" , 0x1180080e0fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8076" , 0x1180080e0fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8077" , 0x1180080e0fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8078" , 0x1180080e0fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8079" , 0x1180080e0fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8080" , 0x1180080e0fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8081" , 0x1180080e0fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8082" , 0x1180080e0fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8083" , 0x1180080e0fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8084" , 0x1180080e0fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8085" , 0x1180080e0fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8086" , 0x1180080e0fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8087" , 0x1180080e0fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8088" , 0x1180080e0fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8089" , 0x1180080e0fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8090" , 0x1180080e0fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8091" , 0x1180080e0fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8092" , 0x1180080e0fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8093" , 0x1180080e0fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8094" , 0x1180080e0fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8095" , 0x1180080e0fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8096" , 0x1180080e0fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8097" , 0x1180080e0fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8098" , 0x1180080e0fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8099" , 0x1180080e0fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8100" , 0x1180080e0fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8101" , 0x1180080e0fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8102" , 0x1180080e0fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8103" , 0x1180080e0fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8104" , 0x1180080e0fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8105" , 0x1180080e0fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8106" , 0x1180080e0fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8107" , 0x1180080e0fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8108" , 0x1180080e0fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8109" , 0x1180080e0fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8110" , 0x1180080e0fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8111" , 0x1180080e0fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8112" , 0x1180080e0fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8113" , 0x1180080e0fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8114" , 0x1180080e0fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8115" , 0x1180080e0fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8116" , 0x1180080e0fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8117" , 0x1180080e0fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8118" , 0x1180080e0fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8119" , 0x1180080e0fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8120" , 0x1180080e0fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8121" , 0x1180080e0fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8122" , 0x1180080e0fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8123" , 0x1180080e0fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8124" , 0x1180080e0fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8125" , 0x1180080e0fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8126" , 0x1180080e0fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8127" , 0x1180080e0fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8128" , 0x1180080e0fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8129" , 0x1180080e0fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8130" , 0x1180080e0fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8131" , 0x1180080e0fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8132" , 0x1180080e0fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8133" , 0x1180080e0fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8134" , 0x1180080e0fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8135" , 0x1180080e0fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8136" , 0x1180080e0fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8137" , 0x1180080e0fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8138" , 0x1180080e0fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8139" , 0x1180080e0fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8140" , 0x1180080e0fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8141" , 0x1180080e0fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8142" , 0x1180080e0fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8143" , 0x1180080e0fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8144" , 0x1180080e0fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8145" , 0x1180080e0fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8146" , 0x1180080e0fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8147" , 0x1180080e0fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8148" , 0x1180080e0fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8149" , 0x1180080e0fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8150" , 0x1180080e0feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8151" , 0x1180080e0feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8152" , 0x1180080e0fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8153" , 0x1180080e0fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8154" , 0x1180080e0fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8155" , 0x1180080e0fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8156" , 0x1180080e0fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8157" , 0x1180080e0fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8158" , 0x1180080e0fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8159" , 0x1180080e0fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8160" , 0x1180080e0ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8161" , 0x1180080e0ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8162" , 0x1180080e0ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8163" , 0x1180080e0ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8164" , 0x1180080e0ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8165" , 0x1180080e0ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8166" , 0x1180080e0ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8167" , 0x1180080e0ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8168" , 0x1180080e0ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8169" , 0x1180080e0ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8170" , 0x1180080e0ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8171" , 0x1180080e0ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8172" , 0x1180080e0ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8173" , 0x1180080e0ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8174" , 0x1180080e0ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8175" , 0x1180080e0ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8176" , 0x1180080e0ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8177" , 0x1180080e0ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8178" , 0x1180080e0ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8179" , 0x1180080e0ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8180" , 0x1180080e0ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8181" , 0x1180080e0ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8182" , 0x1180080e0ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8183" , 0x1180080e0ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8184" , 0x1180080e0ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8185" , 0x1180080e0ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8186" , 0x1180080e0ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8187" , 0x1180080e0ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8188" , 0x1180080e0ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8189" , 0x1180080e0ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8190" , 0x1180080e0fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_DUT_MAP8191" , 0x1180080e0fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"L2C_ERR_TDT0" , 0x1180080a007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 614},
- {"L2C_ERR_TDT1" , 0x1180080a407e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 614},
- {"L2C_ERR_TDT2" , 0x1180080a807e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 614},
- {"L2C_ERR_TDT3" , 0x1180080ac07e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 614},
- {"L2C_ERR_TTG0" , 0x1180080a007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 615},
- {"L2C_ERR_TTG1" , 0x1180080a407e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 615},
- {"L2C_ERR_TTG2" , 0x1180080a807e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 615},
- {"L2C_ERR_TTG3" , 0x1180080ac07e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 615},
- {"L2C_ERR_VBF0" , 0x1180080c007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"L2C_ERR_VBF1" , 0x1180080c407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"L2C_ERR_VBF2" , 0x1180080c807f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"L2C_ERR_VBF3" , 0x1180080cc07f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"L2C_ERR_XMC" , 0x11800808007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
- {"L2C_INT_ENA" , 0x1180080800020ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
- {"L2C_INT_REG" , 0x1180080800018ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
- {"L2C_IOC0_PFC" , 0x1180080800420ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
- {"L2C_IOR0_PFC" , 0x1180080800428ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
- {"L2C_QOS_IOB0" , 0x1180080880200ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"L2C_QOS_IOB1" , 0x1180080880208ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
- {"L2C_QOS_PP0" , 0x1180080880000ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP1" , 0x1180080880008ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP2" , 0x1180080880010ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP3" , 0x1180080880018ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP4" , 0x1180080880020ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP5" , 0x1180080880028ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP6" , 0x1180080880030ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP7" , 0x1180080880038ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP8" , 0x1180080880040ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP9" , 0x1180080880048ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP10" , 0x1180080880050ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP11" , 0x1180080880058ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP12" , 0x1180080880060ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP13" , 0x1180080880068ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP14" , 0x1180080880070ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP15" , 0x1180080880078ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP16" , 0x1180080880080ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP17" , 0x1180080880088ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP18" , 0x1180080880090ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP19" , 0x1180080880098ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP20" , 0x11800808800a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP21" , 0x11800808800a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP22" , 0x11800808800b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP23" , 0x11800808800b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP24" , 0x11800808800c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP25" , 0x11800808800c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP26" , 0x11800808800d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP27" , 0x11800808800d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP28" , 0x11800808800e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP29" , 0x11800808800e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP30" , 0x11800808800f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_PP31" , 0x11800808800f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
- {"L2C_QOS_WGT" , 0x1180080800008ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
- {"L2C_RSC0_PFC" , 0x1180080800410ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"L2C_RSC1_PFC" , 0x1180080800450ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"L2C_RSC2_PFC" , 0x1180080800490ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"L2C_RSC3_PFC" , 0x11800808004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
- {"L2C_RSD0_PFC" , 0x1180080800418ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"L2C_RSD1_PFC" , 0x1180080800458ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"L2C_RSD2_PFC" , 0x1180080800498ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"L2C_RSD3_PFC" , 0x11800808004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
- {"L2C_TAD0_ECC0" , 0x1180080a00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"L2C_TAD1_ECC0" , 0x1180080a40018ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"L2C_TAD2_ECC0" , 0x1180080a80018ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"L2C_TAD3_ECC0" , 0x1180080ac0018ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
- {"L2C_TAD0_ECC1" , 0x1180080a00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"L2C_TAD1_ECC1" , 0x1180080a40020ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"L2C_TAD2_ECC1" , 0x1180080a80020ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"L2C_TAD3_ECC1" , 0x1180080ac0020ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
- {"L2C_TAD0_IEN" , 0x1180080a00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"L2C_TAD1_IEN" , 0x1180080a40000ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"L2C_TAD2_IEN" , 0x1180080a80000ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"L2C_TAD3_IEN" , 0x1180080ac0000ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
- {"L2C_TAD0_INT" , 0x1180080a00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"L2C_TAD1_INT" , 0x1180080a40028ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"L2C_TAD2_INT" , 0x1180080a80028ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"L2C_TAD3_INT" , 0x1180080ac0028ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
- {"L2C_TAD0_PFC0" , 0x1180080a00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"L2C_TAD1_PFC0" , 0x1180080a40400ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"L2C_TAD2_PFC0" , 0x1180080a80400ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"L2C_TAD3_PFC0" , 0x1180080ac0400ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
- {"L2C_TAD0_PFC1" , 0x1180080a00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"L2C_TAD1_PFC1" , 0x1180080a40408ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"L2C_TAD2_PFC1" , 0x1180080a80408ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"L2C_TAD3_PFC1" , 0x1180080ac0408ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"L2C_TAD0_PFC2" , 0x1180080a00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"L2C_TAD1_PFC2" , 0x1180080a40410ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"L2C_TAD2_PFC2" , 0x1180080a80410ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"L2C_TAD3_PFC2" , 0x1180080ac0410ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"L2C_TAD0_PFC3" , 0x1180080a00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"L2C_TAD1_PFC3" , 0x1180080a40418ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"L2C_TAD2_PFC3" , 0x1180080a80418ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"L2C_TAD3_PFC3" , 0x1180080ac0418ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"L2C_TAD0_PRF" , 0x1180080a00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"L2C_TAD1_PRF" , 0x1180080a40008ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"L2C_TAD2_PRF" , 0x1180080a80008ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"L2C_TAD3_PRF" , 0x1180080ac0008ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"L2C_TAD0_TAG" , 0x1180080a00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_TAD1_TAG" , 0x1180080a40010ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_TAD2_TAG" , 0x1180080a80010ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_TAD3_TAG" , 0x1180080ac0010ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"L2C_VER_ID" , 0x11800808007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
- {"L2C_VER_IOB" , 0x11800808007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"L2C_VER_MSC" , 0x11800808007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
- {"L2C_VER_PP" , 0x11800808007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"L2C_VIRTID_IOB0" , 0x11800808c0200ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"L2C_VIRTID_IOB1" , 0x11800808c0208ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"L2C_VIRTID_PP0" , 0x11800808c0000ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP1" , 0x11800808c0008ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP2" , 0x11800808c0010ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP3" , 0x11800808c0018ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP4" , 0x11800808c0020ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP5" , 0x11800808c0028ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP6" , 0x11800808c0030ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP7" , 0x11800808c0038ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP8" , 0x11800808c0040ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP9" , 0x11800808c0048ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP10" , 0x11800808c0050ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP11" , 0x11800808c0058ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP12" , 0x11800808c0060ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP13" , 0x11800808c0068ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP14" , 0x11800808c0070ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP15" , 0x11800808c0078ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP16" , 0x11800808c0080ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP17" , 0x11800808c0088ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP18" , 0x11800808c0090ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP19" , 0x11800808c0098ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP20" , 0x11800808c00a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP21" , 0x11800808c00a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP22" , 0x11800808c00b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP23" , 0x11800808c00b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP24" , 0x11800808c00c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP25" , 0x11800808c00c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP26" , 0x11800808c00d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP27" , 0x11800808c00d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP28" , 0x11800808c00e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP29" , 0x11800808c00e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP30" , 0x11800808c00f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VIRTID_PP31" , 0x11800808c00f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"L2C_VRT_CTL" , 0x1180080800010ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
- {"L2C_VRT_MEM0" , 0x1180080900000ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1" , 0x1180080900008ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM2" , 0x1180080900010ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM3" , 0x1180080900018ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM4" , 0x1180080900020ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM5" , 0x1180080900028ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM6" , 0x1180080900030ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM7" , 0x1180080900038ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM8" , 0x1180080900040ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM9" , 0x1180080900048ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM10" , 0x1180080900050ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM11" , 0x1180080900058ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM12" , 0x1180080900060ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM13" , 0x1180080900068ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM14" , 0x1180080900070ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM15" , 0x1180080900078ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM16" , 0x1180080900080ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM17" , 0x1180080900088ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM18" , 0x1180080900090ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM19" , 0x1180080900098ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM20" , 0x11800809000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM21" , 0x11800809000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM22" , 0x11800809000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM23" , 0x11800809000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM24" , 0x11800809000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM25" , 0x11800809000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM26" , 0x11800809000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM27" , 0x11800809000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM28" , 0x11800809000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM29" , 0x11800809000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM30" , 0x11800809000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM31" , 0x11800809000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM32" , 0x1180080900100ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM33" , 0x1180080900108ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM34" , 0x1180080900110ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM35" , 0x1180080900118ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM36" , 0x1180080900120ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM37" , 0x1180080900128ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM38" , 0x1180080900130ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM39" , 0x1180080900138ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM40" , 0x1180080900140ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM41" , 0x1180080900148ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM42" , 0x1180080900150ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM43" , 0x1180080900158ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM44" , 0x1180080900160ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM45" , 0x1180080900168ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM46" , 0x1180080900170ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM47" , 0x1180080900178ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM48" , 0x1180080900180ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM49" , 0x1180080900188ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM50" , 0x1180080900190ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM51" , 0x1180080900198ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM52" , 0x11800809001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM53" , 0x11800809001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM54" , 0x11800809001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM55" , 0x11800809001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM56" , 0x11800809001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM57" , 0x11800809001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM58" , 0x11800809001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM59" , 0x11800809001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM60" , 0x11800809001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM61" , 0x11800809001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM62" , 0x11800809001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM63" , 0x11800809001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM64" , 0x1180080900200ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM65" , 0x1180080900208ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM66" , 0x1180080900210ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM67" , 0x1180080900218ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM68" , 0x1180080900220ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM69" , 0x1180080900228ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM70" , 0x1180080900230ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM71" , 0x1180080900238ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM72" , 0x1180080900240ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM73" , 0x1180080900248ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM74" , 0x1180080900250ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM75" , 0x1180080900258ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM76" , 0x1180080900260ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM77" , 0x1180080900268ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM78" , 0x1180080900270ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM79" , 0x1180080900278ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM80" , 0x1180080900280ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM81" , 0x1180080900288ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM82" , 0x1180080900290ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM83" , 0x1180080900298ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM84" , 0x11800809002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM85" , 0x11800809002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM86" , 0x11800809002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM87" , 0x11800809002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM88" , 0x11800809002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM89" , 0x11800809002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM90" , 0x11800809002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM91" , 0x11800809002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM92" , 0x11800809002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM93" , 0x11800809002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM94" , 0x11800809002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM95" , 0x11800809002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM96" , 0x1180080900300ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM97" , 0x1180080900308ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM98" , 0x1180080900310ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM99" , 0x1180080900318ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM100" , 0x1180080900320ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM101" , 0x1180080900328ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM102" , 0x1180080900330ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM103" , 0x1180080900338ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM104" , 0x1180080900340ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM105" , 0x1180080900348ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM106" , 0x1180080900350ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM107" , 0x1180080900358ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM108" , 0x1180080900360ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM109" , 0x1180080900368ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM110" , 0x1180080900370ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM111" , 0x1180080900378ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM112" , 0x1180080900380ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM113" , 0x1180080900388ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM114" , 0x1180080900390ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM115" , 0x1180080900398ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM116" , 0x11800809003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM117" , 0x11800809003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM118" , 0x11800809003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM119" , 0x11800809003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM120" , 0x11800809003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM121" , 0x11800809003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM122" , 0x11800809003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM123" , 0x11800809003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM124" , 0x11800809003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM125" , 0x11800809003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM126" , 0x11800809003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM127" , 0x11800809003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM128" , 0x1180080900400ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM129" , 0x1180080900408ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM130" , 0x1180080900410ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM131" , 0x1180080900418ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM132" , 0x1180080900420ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM133" , 0x1180080900428ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM134" , 0x1180080900430ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM135" , 0x1180080900438ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM136" , 0x1180080900440ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM137" , 0x1180080900448ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM138" , 0x1180080900450ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM139" , 0x1180080900458ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM140" , 0x1180080900460ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM141" , 0x1180080900468ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM142" , 0x1180080900470ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM143" , 0x1180080900478ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM144" , 0x1180080900480ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM145" , 0x1180080900488ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM146" , 0x1180080900490ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM147" , 0x1180080900498ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM148" , 0x11800809004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM149" , 0x11800809004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM150" , 0x11800809004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM151" , 0x11800809004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM152" , 0x11800809004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM153" , 0x11800809004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM154" , 0x11800809004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM155" , 0x11800809004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM156" , 0x11800809004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM157" , 0x11800809004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM158" , 0x11800809004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM159" , 0x11800809004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM160" , 0x1180080900500ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM161" , 0x1180080900508ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM162" , 0x1180080900510ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM163" , 0x1180080900518ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM164" , 0x1180080900520ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM165" , 0x1180080900528ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM166" , 0x1180080900530ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM167" , 0x1180080900538ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM168" , 0x1180080900540ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM169" , 0x1180080900548ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM170" , 0x1180080900550ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM171" , 0x1180080900558ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM172" , 0x1180080900560ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM173" , 0x1180080900568ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM174" , 0x1180080900570ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM175" , 0x1180080900578ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM176" , 0x1180080900580ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM177" , 0x1180080900588ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM178" , 0x1180080900590ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM179" , 0x1180080900598ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM180" , 0x11800809005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM181" , 0x11800809005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM182" , 0x11800809005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM183" , 0x11800809005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM184" , 0x11800809005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM185" , 0x11800809005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM186" , 0x11800809005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM187" , 0x11800809005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM188" , 0x11800809005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM189" , 0x11800809005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM190" , 0x11800809005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM191" , 0x11800809005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM192" , 0x1180080900600ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM193" , 0x1180080900608ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM194" , 0x1180080900610ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM195" , 0x1180080900618ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM196" , 0x1180080900620ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM197" , 0x1180080900628ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM198" , 0x1180080900630ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM199" , 0x1180080900638ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM200" , 0x1180080900640ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM201" , 0x1180080900648ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM202" , 0x1180080900650ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM203" , 0x1180080900658ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM204" , 0x1180080900660ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM205" , 0x1180080900668ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM206" , 0x1180080900670ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM207" , 0x1180080900678ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM208" , 0x1180080900680ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM209" , 0x1180080900688ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM210" , 0x1180080900690ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM211" , 0x1180080900698ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM212" , 0x11800809006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM213" , 0x11800809006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM214" , 0x11800809006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM215" , 0x11800809006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM216" , 0x11800809006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM217" , 0x11800809006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM218" , 0x11800809006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM219" , 0x11800809006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM220" , 0x11800809006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM221" , 0x11800809006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM222" , 0x11800809006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM223" , 0x11800809006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM224" , 0x1180080900700ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM225" , 0x1180080900708ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM226" , 0x1180080900710ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM227" , 0x1180080900718ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM228" , 0x1180080900720ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM229" , 0x1180080900728ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM230" , 0x1180080900730ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM231" , 0x1180080900738ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM232" , 0x1180080900740ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM233" , 0x1180080900748ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM234" , 0x1180080900750ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM235" , 0x1180080900758ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM236" , 0x1180080900760ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM237" , 0x1180080900768ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM238" , 0x1180080900770ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM239" , 0x1180080900778ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM240" , 0x1180080900780ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM241" , 0x1180080900788ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM242" , 0x1180080900790ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM243" , 0x1180080900798ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM244" , 0x11800809007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM245" , 0x11800809007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM246" , 0x11800809007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM247" , 0x11800809007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM248" , 0x11800809007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM249" , 0x11800809007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM250" , 0x11800809007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM251" , 0x11800809007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM252" , 0x11800809007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM253" , 0x11800809007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM254" , 0x11800809007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM255" , 0x11800809007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM256" , 0x1180080900800ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM257" , 0x1180080900808ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM258" , 0x1180080900810ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM259" , 0x1180080900818ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM260" , 0x1180080900820ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM261" , 0x1180080900828ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM262" , 0x1180080900830ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM263" , 0x1180080900838ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM264" , 0x1180080900840ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM265" , 0x1180080900848ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM266" , 0x1180080900850ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM267" , 0x1180080900858ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM268" , 0x1180080900860ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM269" , 0x1180080900868ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM270" , 0x1180080900870ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM271" , 0x1180080900878ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM272" , 0x1180080900880ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM273" , 0x1180080900888ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM274" , 0x1180080900890ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM275" , 0x1180080900898ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM276" , 0x11800809008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM277" , 0x11800809008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM278" , 0x11800809008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM279" , 0x11800809008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM280" , 0x11800809008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM281" , 0x11800809008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM282" , 0x11800809008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM283" , 0x11800809008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM284" , 0x11800809008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM285" , 0x11800809008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM286" , 0x11800809008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM287" , 0x11800809008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM288" , 0x1180080900900ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM289" , 0x1180080900908ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM290" , 0x1180080900910ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM291" , 0x1180080900918ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM292" , 0x1180080900920ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM293" , 0x1180080900928ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM294" , 0x1180080900930ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM295" , 0x1180080900938ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM296" , 0x1180080900940ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM297" , 0x1180080900948ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM298" , 0x1180080900950ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM299" , 0x1180080900958ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM300" , 0x1180080900960ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM301" , 0x1180080900968ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM302" , 0x1180080900970ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM303" , 0x1180080900978ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM304" , 0x1180080900980ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM305" , 0x1180080900988ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM306" , 0x1180080900990ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM307" , 0x1180080900998ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM308" , 0x11800809009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM309" , 0x11800809009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM310" , 0x11800809009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM311" , 0x11800809009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM312" , 0x11800809009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM313" , 0x11800809009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM314" , 0x11800809009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM315" , 0x11800809009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM316" , 0x11800809009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM317" , 0x11800809009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM318" , 0x11800809009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM319" , 0x11800809009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM320" , 0x1180080900a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM321" , 0x1180080900a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM322" , 0x1180080900a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM323" , 0x1180080900a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM324" , 0x1180080900a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM325" , 0x1180080900a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM326" , 0x1180080900a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM327" , 0x1180080900a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM328" , 0x1180080900a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM329" , 0x1180080900a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM330" , 0x1180080900a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM331" , 0x1180080900a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM332" , 0x1180080900a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM333" , 0x1180080900a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM334" , 0x1180080900a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM335" , 0x1180080900a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM336" , 0x1180080900a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM337" , 0x1180080900a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM338" , 0x1180080900a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM339" , 0x1180080900a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM340" , 0x1180080900aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM341" , 0x1180080900aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM342" , 0x1180080900ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM343" , 0x1180080900ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM344" , 0x1180080900ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM345" , 0x1180080900ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM346" , 0x1180080900ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM347" , 0x1180080900ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM348" , 0x1180080900ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM349" , 0x1180080900ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM350" , 0x1180080900af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM351" , 0x1180080900af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM352" , 0x1180080900b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM353" , 0x1180080900b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM354" , 0x1180080900b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM355" , 0x1180080900b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM356" , 0x1180080900b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM357" , 0x1180080900b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM358" , 0x1180080900b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM359" , 0x1180080900b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM360" , 0x1180080900b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM361" , 0x1180080900b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM362" , 0x1180080900b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM363" , 0x1180080900b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM364" , 0x1180080900b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM365" , 0x1180080900b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM366" , 0x1180080900b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM367" , 0x1180080900b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM368" , 0x1180080900b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM369" , 0x1180080900b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM370" , 0x1180080900b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM371" , 0x1180080900b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM372" , 0x1180080900ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM373" , 0x1180080900ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM374" , 0x1180080900bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM375" , 0x1180080900bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM376" , 0x1180080900bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM377" , 0x1180080900bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM378" , 0x1180080900bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM379" , 0x1180080900bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM380" , 0x1180080900be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM381" , 0x1180080900be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM382" , 0x1180080900bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM383" , 0x1180080900bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM384" , 0x1180080900c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM385" , 0x1180080900c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM386" , 0x1180080900c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM387" , 0x1180080900c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM388" , 0x1180080900c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM389" , 0x1180080900c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM390" , 0x1180080900c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM391" , 0x1180080900c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM392" , 0x1180080900c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM393" , 0x1180080900c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM394" , 0x1180080900c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM395" , 0x1180080900c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM396" , 0x1180080900c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM397" , 0x1180080900c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM398" , 0x1180080900c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM399" , 0x1180080900c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM400" , 0x1180080900c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM401" , 0x1180080900c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM402" , 0x1180080900c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM403" , 0x1180080900c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM404" , 0x1180080900ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM405" , 0x1180080900ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM406" , 0x1180080900cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM407" , 0x1180080900cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM408" , 0x1180080900cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM409" , 0x1180080900cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM410" , 0x1180080900cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM411" , 0x1180080900cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM412" , 0x1180080900ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM413" , 0x1180080900ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM414" , 0x1180080900cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM415" , 0x1180080900cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM416" , 0x1180080900d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM417" , 0x1180080900d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM418" , 0x1180080900d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM419" , 0x1180080900d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM420" , 0x1180080900d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM421" , 0x1180080900d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM422" , 0x1180080900d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM423" , 0x1180080900d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM424" , 0x1180080900d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM425" , 0x1180080900d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM426" , 0x1180080900d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM427" , 0x1180080900d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM428" , 0x1180080900d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM429" , 0x1180080900d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM430" , 0x1180080900d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM431" , 0x1180080900d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM432" , 0x1180080900d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM433" , 0x1180080900d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM434" , 0x1180080900d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM435" , 0x1180080900d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM436" , 0x1180080900da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM437" , 0x1180080900da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM438" , 0x1180080900db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM439" , 0x1180080900db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM440" , 0x1180080900dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM441" , 0x1180080900dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM442" , 0x1180080900dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM443" , 0x1180080900dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM444" , 0x1180080900de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM445" , 0x1180080900de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM446" , 0x1180080900df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM447" , 0x1180080900df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM448" , 0x1180080900e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM449" , 0x1180080900e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM450" , 0x1180080900e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM451" , 0x1180080900e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM452" , 0x1180080900e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM453" , 0x1180080900e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM454" , 0x1180080900e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM455" , 0x1180080900e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM456" , 0x1180080900e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM457" , 0x1180080900e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM458" , 0x1180080900e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM459" , 0x1180080900e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM460" , 0x1180080900e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM461" , 0x1180080900e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM462" , 0x1180080900e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM463" , 0x1180080900e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM464" , 0x1180080900e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM465" , 0x1180080900e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM466" , 0x1180080900e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM467" , 0x1180080900e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM468" , 0x1180080900ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM469" , 0x1180080900ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM470" , 0x1180080900eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM471" , 0x1180080900eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM472" , 0x1180080900ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM473" , 0x1180080900ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM474" , 0x1180080900ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM475" , 0x1180080900ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM476" , 0x1180080900ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM477" , 0x1180080900ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM478" , 0x1180080900ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM479" , 0x1180080900ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM480" , 0x1180080900f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM481" , 0x1180080900f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM482" , 0x1180080900f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM483" , 0x1180080900f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM484" , 0x1180080900f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM485" , 0x1180080900f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM486" , 0x1180080900f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM487" , 0x1180080900f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM488" , 0x1180080900f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM489" , 0x1180080900f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM490" , 0x1180080900f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM491" , 0x1180080900f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM492" , 0x1180080900f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM493" , 0x1180080900f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM494" , 0x1180080900f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM495" , 0x1180080900f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM496" , 0x1180080900f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM497" , 0x1180080900f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM498" , 0x1180080900f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM499" , 0x1180080900f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM500" , 0x1180080900fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM501" , 0x1180080900fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM502" , 0x1180080900fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM503" , 0x1180080900fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM504" , 0x1180080900fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM505" , 0x1180080900fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM506" , 0x1180080900fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM507" , 0x1180080900fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM508" , 0x1180080900fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM509" , 0x1180080900fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM510" , 0x1180080900ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM511" , 0x1180080900ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM512" , 0x1180080901000ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM513" , 0x1180080901008ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM514" , 0x1180080901010ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM515" , 0x1180080901018ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM516" , 0x1180080901020ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM517" , 0x1180080901028ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM518" , 0x1180080901030ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM519" , 0x1180080901038ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM520" , 0x1180080901040ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM521" , 0x1180080901048ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM522" , 0x1180080901050ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM523" , 0x1180080901058ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM524" , 0x1180080901060ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM525" , 0x1180080901068ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM526" , 0x1180080901070ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM527" , 0x1180080901078ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM528" , 0x1180080901080ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM529" , 0x1180080901088ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM530" , 0x1180080901090ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM531" , 0x1180080901098ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM532" , 0x11800809010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM533" , 0x11800809010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM534" , 0x11800809010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM535" , 0x11800809010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM536" , 0x11800809010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM537" , 0x11800809010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM538" , 0x11800809010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM539" , 0x11800809010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM540" , 0x11800809010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM541" , 0x11800809010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM542" , 0x11800809010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM543" , 0x11800809010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM544" , 0x1180080901100ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM545" , 0x1180080901108ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM546" , 0x1180080901110ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM547" , 0x1180080901118ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM548" , 0x1180080901120ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM549" , 0x1180080901128ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM550" , 0x1180080901130ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM551" , 0x1180080901138ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM552" , 0x1180080901140ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM553" , 0x1180080901148ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM554" , 0x1180080901150ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM555" , 0x1180080901158ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM556" , 0x1180080901160ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM557" , 0x1180080901168ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM558" , 0x1180080901170ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM559" , 0x1180080901178ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM560" , 0x1180080901180ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM561" , 0x1180080901188ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM562" , 0x1180080901190ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM563" , 0x1180080901198ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM564" , 0x11800809011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM565" , 0x11800809011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM566" , 0x11800809011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM567" , 0x11800809011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM568" , 0x11800809011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM569" , 0x11800809011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM570" , 0x11800809011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM571" , 0x11800809011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM572" , 0x11800809011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM573" , 0x11800809011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM574" , 0x11800809011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM575" , 0x11800809011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM576" , 0x1180080901200ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM577" , 0x1180080901208ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM578" , 0x1180080901210ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM579" , 0x1180080901218ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM580" , 0x1180080901220ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM581" , 0x1180080901228ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM582" , 0x1180080901230ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM583" , 0x1180080901238ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM584" , 0x1180080901240ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM585" , 0x1180080901248ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM586" , 0x1180080901250ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM587" , 0x1180080901258ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM588" , 0x1180080901260ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM589" , 0x1180080901268ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM590" , 0x1180080901270ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM591" , 0x1180080901278ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM592" , 0x1180080901280ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM593" , 0x1180080901288ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM594" , 0x1180080901290ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM595" , 0x1180080901298ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM596" , 0x11800809012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM597" , 0x11800809012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM598" , 0x11800809012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM599" , 0x11800809012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM600" , 0x11800809012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM601" , 0x11800809012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM602" , 0x11800809012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM603" , 0x11800809012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM604" , 0x11800809012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM605" , 0x11800809012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM606" , 0x11800809012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM607" , 0x11800809012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM608" , 0x1180080901300ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM609" , 0x1180080901308ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM610" , 0x1180080901310ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM611" , 0x1180080901318ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM612" , 0x1180080901320ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM613" , 0x1180080901328ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM614" , 0x1180080901330ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM615" , 0x1180080901338ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM616" , 0x1180080901340ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM617" , 0x1180080901348ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM618" , 0x1180080901350ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM619" , 0x1180080901358ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM620" , 0x1180080901360ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM621" , 0x1180080901368ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM622" , 0x1180080901370ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM623" , 0x1180080901378ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM624" , 0x1180080901380ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM625" , 0x1180080901388ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM626" , 0x1180080901390ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM627" , 0x1180080901398ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM628" , 0x11800809013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM629" , 0x11800809013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM630" , 0x11800809013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM631" , 0x11800809013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM632" , 0x11800809013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM633" , 0x11800809013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM634" , 0x11800809013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM635" , 0x11800809013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM636" , 0x11800809013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM637" , 0x11800809013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM638" , 0x11800809013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM639" , 0x11800809013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM640" , 0x1180080901400ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM641" , 0x1180080901408ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM642" , 0x1180080901410ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM643" , 0x1180080901418ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM644" , 0x1180080901420ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM645" , 0x1180080901428ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM646" , 0x1180080901430ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM647" , 0x1180080901438ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM648" , 0x1180080901440ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM649" , 0x1180080901448ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM650" , 0x1180080901450ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM651" , 0x1180080901458ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM652" , 0x1180080901460ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM653" , 0x1180080901468ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM654" , 0x1180080901470ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM655" , 0x1180080901478ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM656" , 0x1180080901480ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM657" , 0x1180080901488ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM658" , 0x1180080901490ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM659" , 0x1180080901498ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM660" , 0x11800809014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM661" , 0x11800809014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM662" , 0x11800809014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM663" , 0x11800809014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM664" , 0x11800809014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM665" , 0x11800809014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM666" , 0x11800809014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM667" , 0x11800809014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM668" , 0x11800809014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM669" , 0x11800809014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM670" , 0x11800809014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM671" , 0x11800809014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM672" , 0x1180080901500ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM673" , 0x1180080901508ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM674" , 0x1180080901510ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM675" , 0x1180080901518ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM676" , 0x1180080901520ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM677" , 0x1180080901528ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM678" , 0x1180080901530ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM679" , 0x1180080901538ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM680" , 0x1180080901540ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM681" , 0x1180080901548ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM682" , 0x1180080901550ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM683" , 0x1180080901558ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM684" , 0x1180080901560ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM685" , 0x1180080901568ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM686" , 0x1180080901570ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM687" , 0x1180080901578ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM688" , 0x1180080901580ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM689" , 0x1180080901588ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM690" , 0x1180080901590ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM691" , 0x1180080901598ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM692" , 0x11800809015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM693" , 0x11800809015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM694" , 0x11800809015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM695" , 0x11800809015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM696" , 0x11800809015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM697" , 0x11800809015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM698" , 0x11800809015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM699" , 0x11800809015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM700" , 0x11800809015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM701" , 0x11800809015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM702" , 0x11800809015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM703" , 0x11800809015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM704" , 0x1180080901600ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM705" , 0x1180080901608ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM706" , 0x1180080901610ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM707" , 0x1180080901618ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM708" , 0x1180080901620ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM709" , 0x1180080901628ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM710" , 0x1180080901630ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM711" , 0x1180080901638ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM712" , 0x1180080901640ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM713" , 0x1180080901648ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM714" , 0x1180080901650ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM715" , 0x1180080901658ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM716" , 0x1180080901660ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM717" , 0x1180080901668ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM718" , 0x1180080901670ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM719" , 0x1180080901678ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM720" , 0x1180080901680ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM721" , 0x1180080901688ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM722" , 0x1180080901690ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM723" , 0x1180080901698ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM724" , 0x11800809016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM725" , 0x11800809016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM726" , 0x11800809016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM727" , 0x11800809016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM728" , 0x11800809016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM729" , 0x11800809016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM730" , 0x11800809016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM731" , 0x11800809016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM732" , 0x11800809016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM733" , 0x11800809016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM734" , 0x11800809016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM735" , 0x11800809016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM736" , 0x1180080901700ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM737" , 0x1180080901708ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM738" , 0x1180080901710ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM739" , 0x1180080901718ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM740" , 0x1180080901720ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM741" , 0x1180080901728ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM742" , 0x1180080901730ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM743" , 0x1180080901738ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM744" , 0x1180080901740ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM745" , 0x1180080901748ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM746" , 0x1180080901750ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM747" , 0x1180080901758ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM748" , 0x1180080901760ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM749" , 0x1180080901768ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM750" , 0x1180080901770ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM751" , 0x1180080901778ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM752" , 0x1180080901780ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM753" , 0x1180080901788ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM754" , 0x1180080901790ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM755" , 0x1180080901798ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM756" , 0x11800809017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM757" , 0x11800809017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM758" , 0x11800809017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM759" , 0x11800809017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM760" , 0x11800809017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM761" , 0x11800809017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM762" , 0x11800809017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM763" , 0x11800809017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM764" , 0x11800809017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM765" , 0x11800809017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM766" , 0x11800809017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM767" , 0x11800809017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM768" , 0x1180080901800ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM769" , 0x1180080901808ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM770" , 0x1180080901810ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM771" , 0x1180080901818ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM772" , 0x1180080901820ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM773" , 0x1180080901828ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM774" , 0x1180080901830ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM775" , 0x1180080901838ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM776" , 0x1180080901840ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM777" , 0x1180080901848ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM778" , 0x1180080901850ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM779" , 0x1180080901858ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM780" , 0x1180080901860ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM781" , 0x1180080901868ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM782" , 0x1180080901870ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM783" , 0x1180080901878ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM784" , 0x1180080901880ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM785" , 0x1180080901888ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM786" , 0x1180080901890ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM787" , 0x1180080901898ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM788" , 0x11800809018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM789" , 0x11800809018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM790" , 0x11800809018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM791" , 0x11800809018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM792" , 0x11800809018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM793" , 0x11800809018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM794" , 0x11800809018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM795" , 0x11800809018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM796" , 0x11800809018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM797" , 0x11800809018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM798" , 0x11800809018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM799" , 0x11800809018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM800" , 0x1180080901900ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM801" , 0x1180080901908ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM802" , 0x1180080901910ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM803" , 0x1180080901918ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM804" , 0x1180080901920ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM805" , 0x1180080901928ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM806" , 0x1180080901930ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM807" , 0x1180080901938ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM808" , 0x1180080901940ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM809" , 0x1180080901948ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM810" , 0x1180080901950ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM811" , 0x1180080901958ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM812" , 0x1180080901960ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM813" , 0x1180080901968ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM814" , 0x1180080901970ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM815" , 0x1180080901978ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM816" , 0x1180080901980ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM817" , 0x1180080901988ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM818" , 0x1180080901990ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM819" , 0x1180080901998ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM820" , 0x11800809019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM821" , 0x11800809019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM822" , 0x11800809019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM823" , 0x11800809019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM824" , 0x11800809019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM825" , 0x11800809019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM826" , 0x11800809019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM827" , 0x11800809019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM828" , 0x11800809019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM829" , 0x11800809019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM830" , 0x11800809019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM831" , 0x11800809019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM832" , 0x1180080901a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM833" , 0x1180080901a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM834" , 0x1180080901a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM835" , 0x1180080901a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM836" , 0x1180080901a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM837" , 0x1180080901a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM838" , 0x1180080901a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM839" , 0x1180080901a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM840" , 0x1180080901a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM841" , 0x1180080901a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM842" , 0x1180080901a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM843" , 0x1180080901a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM844" , 0x1180080901a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM845" , 0x1180080901a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM846" , 0x1180080901a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM847" , 0x1180080901a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM848" , 0x1180080901a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM849" , 0x1180080901a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM850" , 0x1180080901a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM851" , 0x1180080901a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM852" , 0x1180080901aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM853" , 0x1180080901aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM854" , 0x1180080901ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM855" , 0x1180080901ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM856" , 0x1180080901ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM857" , 0x1180080901ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM858" , 0x1180080901ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM859" , 0x1180080901ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM860" , 0x1180080901ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM861" , 0x1180080901ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM862" , 0x1180080901af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM863" , 0x1180080901af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM864" , 0x1180080901b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM865" , 0x1180080901b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM866" , 0x1180080901b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM867" , 0x1180080901b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM868" , 0x1180080901b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM869" , 0x1180080901b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM870" , 0x1180080901b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM871" , 0x1180080901b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM872" , 0x1180080901b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM873" , 0x1180080901b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM874" , 0x1180080901b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM875" , 0x1180080901b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM876" , 0x1180080901b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM877" , 0x1180080901b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM878" , 0x1180080901b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM879" , 0x1180080901b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM880" , 0x1180080901b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM881" , 0x1180080901b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM882" , 0x1180080901b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM883" , 0x1180080901b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM884" , 0x1180080901ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM885" , 0x1180080901ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM886" , 0x1180080901bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM887" , 0x1180080901bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM888" , 0x1180080901bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM889" , 0x1180080901bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM890" , 0x1180080901bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM891" , 0x1180080901bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM892" , 0x1180080901be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM893" , 0x1180080901be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM894" , 0x1180080901bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM895" , 0x1180080901bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM896" , 0x1180080901c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM897" , 0x1180080901c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM898" , 0x1180080901c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM899" , 0x1180080901c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM900" , 0x1180080901c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM901" , 0x1180080901c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM902" , 0x1180080901c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM903" , 0x1180080901c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM904" , 0x1180080901c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM905" , 0x1180080901c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM906" , 0x1180080901c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM907" , 0x1180080901c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM908" , 0x1180080901c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM909" , 0x1180080901c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM910" , 0x1180080901c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM911" , 0x1180080901c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM912" , 0x1180080901c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM913" , 0x1180080901c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM914" , 0x1180080901c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM915" , 0x1180080901c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM916" , 0x1180080901ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM917" , 0x1180080901ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM918" , 0x1180080901cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM919" , 0x1180080901cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM920" , 0x1180080901cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM921" , 0x1180080901cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM922" , 0x1180080901cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM923" , 0x1180080901cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM924" , 0x1180080901ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM925" , 0x1180080901ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM926" , 0x1180080901cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM927" , 0x1180080901cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM928" , 0x1180080901d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM929" , 0x1180080901d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM930" , 0x1180080901d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM931" , 0x1180080901d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM932" , 0x1180080901d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM933" , 0x1180080901d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM934" , 0x1180080901d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM935" , 0x1180080901d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM936" , 0x1180080901d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM937" , 0x1180080901d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM938" , 0x1180080901d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM939" , 0x1180080901d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM940" , 0x1180080901d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM941" , 0x1180080901d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM942" , 0x1180080901d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM943" , 0x1180080901d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM944" , 0x1180080901d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM945" , 0x1180080901d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM946" , 0x1180080901d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM947" , 0x1180080901d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM948" , 0x1180080901da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM949" , 0x1180080901da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM950" , 0x1180080901db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM951" , 0x1180080901db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM952" , 0x1180080901dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM953" , 0x1180080901dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM954" , 0x1180080901dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM955" , 0x1180080901dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM956" , 0x1180080901de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM957" , 0x1180080901de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM958" , 0x1180080901df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM959" , 0x1180080901df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM960" , 0x1180080901e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM961" , 0x1180080901e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM962" , 0x1180080901e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM963" , 0x1180080901e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM964" , 0x1180080901e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM965" , 0x1180080901e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM966" , 0x1180080901e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM967" , 0x1180080901e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM968" , 0x1180080901e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM969" , 0x1180080901e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM970" , 0x1180080901e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM971" , 0x1180080901e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM972" , 0x1180080901e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM973" , 0x1180080901e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM974" , 0x1180080901e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM975" , 0x1180080901e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM976" , 0x1180080901e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM977" , 0x1180080901e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM978" , 0x1180080901e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM979" , 0x1180080901e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM980" , 0x1180080901ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM981" , 0x1180080901ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM982" , 0x1180080901eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM983" , 0x1180080901eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM984" , 0x1180080901ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM985" , 0x1180080901ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM986" , 0x1180080901ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM987" , 0x1180080901ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM988" , 0x1180080901ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM989" , 0x1180080901ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM990" , 0x1180080901ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM991" , 0x1180080901ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM992" , 0x1180080901f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM993" , 0x1180080901f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM994" , 0x1180080901f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM995" , 0x1180080901f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM996" , 0x1180080901f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM997" , 0x1180080901f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM998" , 0x1180080901f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM999" , 0x1180080901f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1000" , 0x1180080901f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1001" , 0x1180080901f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1002" , 0x1180080901f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1003" , 0x1180080901f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1004" , 0x1180080901f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1005" , 0x1180080901f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1006" , 0x1180080901f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1007" , 0x1180080901f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1008" , 0x1180080901f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1009" , 0x1180080901f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1010" , 0x1180080901f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1011" , 0x1180080901f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1012" , 0x1180080901fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1013" , 0x1180080901fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1014" , 0x1180080901fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1015" , 0x1180080901fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1016" , 0x1180080901fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1017" , 0x1180080901fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1018" , 0x1180080901fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1019" , 0x1180080901fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1020" , 0x1180080901fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1021" , 0x1180080901fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1022" , 0x1180080901ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_VRT_MEM1023" , 0x1180080901ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"L2C_WPAR_IOB0" , 0x1180080840200ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"L2C_WPAR_IOB1" , 0x1180080840208ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"L2C_WPAR_PP0" , 0x1180080840000ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP1" , 0x1180080840008ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP2" , 0x1180080840010ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP3" , 0x1180080840018ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP4" , 0x1180080840020ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP5" , 0x1180080840028ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP6" , 0x1180080840030ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP7" , 0x1180080840038ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP8" , 0x1180080840040ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP9" , 0x1180080840048ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP10" , 0x1180080840050ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP11" , 0x1180080840058ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP12" , 0x1180080840060ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP13" , 0x1180080840068ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP14" , 0x1180080840070ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP15" , 0x1180080840078ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP16" , 0x1180080840080ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP17" , 0x1180080840088ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP18" , 0x1180080840090ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP19" , 0x1180080840098ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP20" , 0x11800808400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP21" , 0x11800808400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP22" , 0x11800808400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP23" , 0x11800808400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP24" , 0x11800808400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP25" , 0x11800808400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP26" , 0x11800808400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP27" , 0x11800808400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP28" , 0x11800808400e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP29" , 0x11800808400e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP30" , 0x11800808400f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_WPAR_PP31" , 0x11800808400f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"L2C_XMC0_PFC" , 0x1180080800400ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"L2C_XMC1_PFC" , 0x1180080800440ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"L2C_XMC2_PFC" , 0x1180080800480ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"L2C_XMC3_PFC" , 0x11800808004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"L2C_XMC_CMD" , 0x1180080800028ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
- {"L2C_XMD0_PFC" , 0x1180080800408ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"L2C_XMD1_PFC" , 0x1180080800448ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"L2C_XMD2_PFC" , 0x1180080800488ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"L2C_XMD3_PFC" , 0x11800808004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"LMC0_CHAR_CTL" , 0x1180088000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"LMC1_CHAR_CTL" , 0x1180089000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"LMC2_CHAR_CTL" , 0x118008a000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"LMC3_CHAR_CTL" , 0x118008b000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"LMC0_CHAR_MASK0" , 0x1180088000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"LMC1_CHAR_MASK0" , 0x1180089000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"LMC2_CHAR_MASK0" , 0x118008a000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"LMC3_CHAR_MASK0" , 0x118008b000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"LMC0_CHAR_MASK1" , 0x1180088000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"LMC1_CHAR_MASK1" , 0x1180089000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"LMC2_CHAR_MASK1" , 0x118008a000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"LMC3_CHAR_MASK1" , 0x118008b000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"LMC0_CHAR_MASK2" , 0x1180088000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"LMC1_CHAR_MASK2" , 0x1180089000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"LMC2_CHAR_MASK2" , 0x118008a000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"LMC3_CHAR_MASK2" , 0x118008b000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"LMC0_CHAR_MASK3" , 0x1180088000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"LMC1_CHAR_MASK3" , 0x1180089000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"LMC2_CHAR_MASK3" , 0x118008a000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"LMC3_CHAR_MASK3" , 0x118008b000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"LMC0_CHAR_MASK4" , 0x1180088000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC1_CHAR_MASK4" , 0x1180089000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC2_CHAR_MASK4" , 0x118008a000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC3_CHAR_MASK4" , 0x118008b000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"LMC0_COMP_CTL2" , 0x11800880001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"LMC1_COMP_CTL2" , 0x11800890001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"LMC2_COMP_CTL2" , 0x118008a0001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"LMC3_COMP_CTL2" , 0x118008b0001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"LMC0_CONFIG" , 0x1180088000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"LMC1_CONFIG" , 0x1180089000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"LMC2_CONFIG" , 0x118008a000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"LMC3_CONFIG" , 0x118008b000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"LMC0_CONTROL" , 0x1180088000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"LMC1_CONTROL" , 0x1180089000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"LMC2_CONTROL" , 0x118008a000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"LMC3_CONTROL" , 0x118008b000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"LMC0_DCLK_CNT" , 0x11800880001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"LMC1_DCLK_CNT" , 0x11800890001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"LMC2_DCLK_CNT" , 0x118008a0001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"LMC3_DCLK_CNT" , 0x118008b0001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"LMC0_DDR_PLL_CTL" , 0x1180088000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"LMC1_DDR_PLL_CTL" , 0x1180089000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"LMC2_DDR_PLL_CTL" , 0x118008a000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"LMC3_DDR_PLL_CTL" , 0x118008b000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"LMC0_DIMM000_PARAMS" , 0x1180088000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC0_DIMM001_PARAMS" , 0x1180088000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC1_DIMM000_PARAMS" , 0x1180089000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC1_DIMM001_PARAMS" , 0x1180089000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC2_DIMM000_PARAMS" , 0x118008a000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC2_DIMM001_PARAMS" , 0x118008a000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC3_DIMM000_PARAMS" , 0x118008b000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC3_DIMM001_PARAMS" , 0x118008b000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"LMC0_DIMM_CTL" , 0x1180088000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"LMC1_DIMM_CTL" , 0x1180089000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"LMC2_DIMM_CTL" , 0x118008a000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"LMC3_DIMM_CTL" , 0x118008b000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"LMC0_DLL_CTL2" , 0x11800880001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"LMC1_DLL_CTL2" , 0x11800890001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"LMC2_DLL_CTL2" , 0x118008a0001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"LMC3_DLL_CTL2" , 0x118008b0001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"LMC0_DLL_CTL3" , 0x1180088000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"LMC1_DLL_CTL3" , 0x1180089000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"LMC2_DLL_CTL3" , 0x118008a000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"LMC3_DLL_CTL3" , 0x118008b000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"LMC1_DUAL_MEMCFG" , 0x1180089000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"LMC2_DUAL_MEMCFG" , 0x118008a000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"LMC3_DUAL_MEMCFG" , 0x118008b000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"LMC1_ECC_SYND" , 0x1180089000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"LMC2_ECC_SYND" , 0x118008a000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"LMC3_ECC_SYND" , 0x118008b000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"LMC1_FADR" , 0x1180089000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"LMC2_FADR" , 0x118008a000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"LMC3_FADR" , 0x118008b000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"LMC0_IFB_CNT" , 0x11800880001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"LMC1_IFB_CNT" , 0x11800890001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"LMC2_IFB_CNT" , 0x118008a0001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"LMC3_IFB_CNT" , 0x118008b0001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"LMC0_INT" , 0x11800880001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"LMC1_INT" , 0x11800890001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"LMC2_INT" , 0x118008a0001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"LMC3_INT" , 0x118008b0001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"LMC0_INT_EN" , 0x11800880001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"LMC1_INT_EN" , 0x11800890001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"LMC2_INT_EN" , 0x118008a0001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"LMC3_INT_EN" , 0x118008b0001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
- {"LMC0_MODEREG_PARAMS0" , 0x11800880001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
- {"LMC1_MODEREG_PARAMS0" , 0x11800890001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
- {"LMC2_MODEREG_PARAMS0" , 0x118008a0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
- {"LMC3_MODEREG_PARAMS0" , 0x118008b0001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
- {"LMC0_MODEREG_PARAMS1" , 0x1180088000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"LMC1_MODEREG_PARAMS1" , 0x1180089000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"LMC2_MODEREG_PARAMS1" , 0x118008a000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"LMC3_MODEREG_PARAMS1" , 0x118008b000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
- {"LMC0_NXM" , 0x11800880000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC1_NXM" , 0x11800890000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC2_NXM" , 0x118008a0000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC3_NXM" , 0x118008b0000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
- {"LMC0_OPS_CNT" , 0x11800880001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"LMC1_OPS_CNT" , 0x11800890001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"LMC2_OPS_CNT" , 0x118008a0001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"LMC3_OPS_CNT" , 0x118008b0001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
- {"LMC0_PHY_CTL" , 0x1180088000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"LMC1_PHY_CTL" , 0x1180089000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"LMC2_PHY_CTL" , 0x118008a000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"LMC3_PHY_CTL" , 0x118008b000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
- {"LMC0_RESET_CTL" , 0x1180088000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"LMC1_RESET_CTL" , 0x1180089000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"LMC2_RESET_CTL" , 0x118008a000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"LMC3_RESET_CTL" , 0x118008b000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
- {"LMC0_RLEVEL_CTL" , 0x11800880002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"LMC1_RLEVEL_CTL" , 0x11800890002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"LMC2_RLEVEL_CTL" , 0x118008a0002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"LMC3_RLEVEL_CTL" , 0x118008b0002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
- {"LMC0_RLEVEL_DBG" , 0x11800880002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
- {"LMC1_RLEVEL_DBG" , 0x11800890002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
- {"LMC2_RLEVEL_DBG" , 0x118008a0002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
- {"LMC3_RLEVEL_DBG" , 0x118008b0002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
- {"LMC0_RLEVEL_RANK000" , 0x1180088000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC0_RLEVEL_RANK001" , 0x1180088000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC0_RLEVEL_RANK002" , 0x1180088000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC0_RLEVEL_RANK003" , 0x1180088000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC1_RLEVEL_RANK000" , 0x1180089000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC1_RLEVEL_RANK001" , 0x1180089000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC1_RLEVEL_RANK002" , 0x1180089000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC1_RLEVEL_RANK003" , 0x1180089000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC2_RLEVEL_RANK000" , 0x118008a000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC2_RLEVEL_RANK001" , 0x118008a000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC2_RLEVEL_RANK002" , 0x118008a000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC2_RLEVEL_RANK003" , 0x118008a000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC3_RLEVEL_RANK000" , 0x118008b000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC3_RLEVEL_RANK001" , 0x118008b000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC3_RLEVEL_RANK002" , 0x118008b000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC3_RLEVEL_RANK003" , 0x118008b000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
- {"LMC0_RODT_MASK" , 0x1180088000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"LMC1_RODT_MASK" , 0x1180089000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"LMC2_RODT_MASK" , 0x118008a000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"LMC3_RODT_MASK" , 0x118008b000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
- {"LMC0_SLOT_CTL0" , 0x11800880001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"LMC1_SLOT_CTL0" , 0x11800890001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"LMC2_SLOT_CTL0" , 0x118008a0001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"LMC3_SLOT_CTL0" , 0x118008b0001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
- {"LMC0_SLOT_CTL1" , 0x1180088000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"LMC1_SLOT_CTL1" , 0x1180089000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"LMC2_SLOT_CTL1" , 0x118008a000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"LMC3_SLOT_CTL1" , 0x118008b000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
- {"LMC0_SLOT_CTL2" , 0x1180088000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"LMC1_SLOT_CTL2" , 0x1180089000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"LMC2_SLOT_CTL2" , 0x118008a000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"LMC3_SLOT_CTL2" , 0x118008b000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
- {"LMC0_TIMING_PARAMS0" , 0x1180088000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC1_TIMING_PARAMS0" , 0x1180089000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC2_TIMING_PARAMS0" , 0x118008a000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC3_TIMING_PARAMS0" , 0x118008b000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
- {"LMC0_TIMING_PARAMS1" , 0x11800880001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"LMC1_TIMING_PARAMS1" , 0x11800890001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"LMC2_TIMING_PARAMS1" , 0x118008a0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"LMC3_TIMING_PARAMS1" , 0x118008b0001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
- {"LMC0_TRO_CTL" , 0x1180088000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"LMC1_TRO_CTL" , 0x1180089000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"LMC2_TRO_CTL" , 0x118008a000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"LMC3_TRO_CTL" , 0x118008b000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
- {"LMC0_TRO_STAT" , 0x1180088000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"LMC1_TRO_STAT" , 0x1180089000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"LMC2_TRO_STAT" , 0x118008a000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"LMC3_TRO_STAT" , 0x118008b000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
- {"LMC0_WLEVEL_CTL" , 0x1180088000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"LMC1_WLEVEL_CTL" , 0x1180089000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"LMC2_WLEVEL_CTL" , 0x118008a000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"LMC3_WLEVEL_CTL" , 0x118008b000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
- {"LMC0_WLEVEL_DBG" , 0x1180088000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"LMC1_WLEVEL_DBG" , 0x1180089000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"LMC2_WLEVEL_DBG" , 0x118008a000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"LMC3_WLEVEL_DBG" , 0x118008b000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
- {"LMC0_WLEVEL_RANK000" , 0x11800880002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC0_WLEVEL_RANK001" , 0x11800880002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC0_WLEVEL_RANK002" , 0x11800880002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC0_WLEVEL_RANK003" , 0x11800880002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC1_WLEVEL_RANK000" , 0x11800890002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC1_WLEVEL_RANK001" , 0x11800890002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC1_WLEVEL_RANK002" , 0x11800890002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC1_WLEVEL_RANK003" , 0x11800890002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC2_WLEVEL_RANK000" , 0x118008a0002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC2_WLEVEL_RANK001" , 0x118008a0002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC2_WLEVEL_RANK002" , 0x118008a0002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC2_WLEVEL_RANK003" , 0x118008a0002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC3_WLEVEL_RANK000" , 0x118008b0002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC3_WLEVEL_RANK001" , 0x118008b0002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC3_WLEVEL_RANK002" , 0x118008b0002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC3_WLEVEL_RANK003" , 0x118008b0002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
- {"LMC0_WODT_MASK" , 0x11800880001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"LMC1_WODT_MASK" , 0x11800890001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"LMC2_WODT_MASK" , 0x118008a0001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"LMC3_WODT_MASK" , 0x118008b0001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
- {"MIO_BOOT_PIN_DEFS" , 0x11800000000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
- {"MIO_FUS_READ_TIMES" , 0x1180000001570ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
- {"MIO_FUS_REPAIR_RES0" , 0x1180000001558ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
- {"MIO_FUS_REPAIR_RES1" , 0x1180000001560ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
- {"MIO_FUS_REPAIR_RES2" , 0x1180000001568ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
- {"MIO_GPIO_COMP" , 0x11800000000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
- {"MIO_NDF_DMA_CFG" , 0x1180000000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
- {"MIO_NDF_DMA_INT" , 0x1180000000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
- {"MIO_NDF_DMA_INT_EN" , 0x1180000000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
- {"MIO_PTP_CKOUT_HI_INCR" , 0x1070000000f40ull, CVMX_CSR_DB_TYPE_NCB, 64, 729},
- {"MIO_PTP_CKOUT_LO_INCR" , 0x1070000000f48ull, CVMX_CSR_DB_TYPE_NCB, 64, 730},
- {"MIO_PTP_CKOUT_THRESH_HI" , 0x1070000000f38ull, CVMX_CSR_DB_TYPE_NCB, 64, 731},
- {"MIO_PTP_CKOUT_THRESH_LO" , 0x1070000000f30ull, CVMX_CSR_DB_TYPE_NCB, 64, 732},
- {"MIO_PTP_CLOCK_CFG" , 0x1070000000f00ull, CVMX_CSR_DB_TYPE_NCB, 64, 733},
- {"MIO_PTP_CLOCK_COMP" , 0x1070000000f18ull, CVMX_CSR_DB_TYPE_NCB, 64, 734},
- {"MIO_PTP_CLOCK_HI" , 0x1070000000f10ull, CVMX_CSR_DB_TYPE_NCB, 64, 735},
- {"MIO_PTP_CLOCK_LO" , 0x1070000000f08ull, CVMX_CSR_DB_TYPE_NCB, 64, 736},
- {"MIO_PTP_EVT_CNT" , 0x1070000000f28ull, CVMX_CSR_DB_TYPE_NCB, 64, 737},
- {"MIO_PTP_PPS_HI_INCR" , 0x1070000000f60ull, CVMX_CSR_DB_TYPE_NCB, 64, 738},
- {"MIO_PTP_PPS_LO_INCR" , 0x1070000000f68ull, CVMX_CSR_DB_TYPE_NCB, 64, 739},
- {"MIO_PTP_PPS_THRESH_HI" , 0x1070000000f58ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
- {"MIO_PTP_PPS_THRESH_LO" , 0x1070000000f50ull, CVMX_CSR_DB_TYPE_NCB, 64, 741},
- {"MIO_PTP_TIMESTAMP" , 0x1070000000f20ull, CVMX_CSR_DB_TYPE_NCB, 64, 742},
- {"MIO_QLM0_CFG" , 0x1180000001590ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"MIO_QLM1_CFG" , 0x1180000001598ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"MIO_QLM2_CFG" , 0x11800000015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"MIO_QLM3_CFG" , 0x11800000015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"MIO_QLM4_CFG" , 0x11800000015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
- {"MIO_RST_BOOT" , 0x1180000001600ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
- {"MIO_RST_CFG" , 0x1180000001610ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
- {"MIO_RST_CNTL0" , 0x1180000001648ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"MIO_RST_CNTL1" , 0x1180000001650ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
- {"MIO_RST_CTL0" , 0x1180000001618ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"MIO_RST_CTL1" , 0x1180000001620ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
- {"MIO_RST_DELAY" , 0x1180000001608ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
- {"MIO_RST_INT" , 0x1180000001628ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
- {"MIO_RST_INT_EN" , 0x1180000001630ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
- {"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 780},
- {"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 781},
- {"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 782},
- {"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 783},
- {"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 784},
- {"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 785},
- {"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 786},
- {"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 787},
- {"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 788},
- {"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 789},
- {"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 790},
- {"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 791},
- {"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 792},
- {"MIX0_TSCTL" , 0x1070000100068ull, CVMX_CSR_DB_TYPE_NCB, 64, 793},
- {"MIX0_TSTAMP" , 0x1070000100060ull, CVMX_CSR_DB_TYPE_NCB, 64, 794},
- {"NDF_BT_PG_INFO" , 0x1070001000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 795},
- {"NDF_CMD" , 0x1070001000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 796},
- {"NDF_DRBELL" , 0x1070001000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 797},
- {"NDF_ECC_CNT" , 0x1070001000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 798},
- {"NDF_INT" , 0x1070001000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 799},
- {"NDF_INT_EN" , 0x1070001000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 800},
- {"NDF_MISC" , 0x1070001000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 801},
- {"NDF_ST_REG" , 0x1070001000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 802},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 803},
- {"PCIEEP1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 803},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 804},
- {"PCIEEP1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 804},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 805},
- {"PCIEEP1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 805},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 806},
- {"PCIEEP1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 806},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 807},
- {"PCIEEP1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 807},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 808},
- {"PCIEEP1_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 808},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 809},
- {"PCIEEP1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 809},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 810},
- {"PCIEEP1_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 810},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 811},
- {"PCIEEP1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 811},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 812},
- {"PCIEEP1_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 812},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 813},
- {"PCIEEP1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 813},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 814},
- {"PCIEEP1_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 814},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 815},
- {"PCIEEP1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 815},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 816},
- {"PCIEEP1_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 816},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 817},
- {"PCIEEP1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 817},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 818},
- {"PCIEEP1_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 818},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 819},
- {"PCIEEP1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 819},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 820},
- {"PCIEEP1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 820},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 821},
- {"PCIEEP1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 821},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 822},
- {"PCIEEP1_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 822},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 823},
- {"PCIEEP1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 823},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 824},
- {"PCIEEP1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 824},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 825},
- {"PCIEEP1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 825},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 826},
- {"PCIEEP1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 826},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 827},
- {"PCIEEP1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 827},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 828},
- {"PCIEEP1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 828},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 829},
- {"PCIEEP1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 829},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 830},
- {"PCIEEP1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 830},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 831},
- {"PCIEEP1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 831},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 832},
- {"PCIEEP1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 832},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 833},
- {"PCIEEP1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 833},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 834},
- {"PCIEEP1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 834},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 835},
- {"PCIEEP1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 835},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 836},
- {"PCIEEP1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 836},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 837},
- {"PCIEEP1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 837},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 838},
- {"PCIEEP1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 838},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 839},
- {"PCIEEP1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 839},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 840},
- {"PCIEEP1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 840},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 841},
- {"PCIEEP1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 841},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 842},
- {"PCIEEP1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 842},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 843},
- {"PCIEEP1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 843},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 844},
- {"PCIEEP1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 844},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 845},
- {"PCIEEP1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 845},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 846},
- {"PCIEEP1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 846},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 847},
- {"PCIEEP1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 847},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 848},
- {"PCIEEP1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 848},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 849},
- {"PCIEEP1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 849},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 850},
- {"PCIEEP1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 850},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 851},
- {"PCIEEP1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 851},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 852},
- {"PCIEEP1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 852},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 853},
- {"PCIEEP1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 853},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 854},
- {"PCIEEP1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 854},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 855},
- {"PCIEEP1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 855},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 856},
- {"PCIEEP1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 856},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 857},
- {"PCIEEP1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 857},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 858},
- {"PCIEEP1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 858},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 859},
- {"PCIEEP1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 859},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 860},
- {"PCIEEP1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 860},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 861},
- {"PCIEEP1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 861},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 862},
- {"PCIEEP1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 862},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 863},
- {"PCIEEP1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 863},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 864},
- {"PCIEEP1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 864},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 865},
- {"PCIEEP1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 865},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 866},
- {"PCIEEP1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 866},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 867},
- {"PCIEEP1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 867},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 868},
- {"PCIEEP1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 868},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 869},
- {"PCIEEP1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 869},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 870},
- {"PCIEEP1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 870},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 871},
- {"PCIEEP1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 871},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 872},
- {"PCIEEP1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 872},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 873},
- {"PCIEEP1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 873},
- {"PCIEEP0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 874},
- {"PCIEEP1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 874},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 875},
- {"PCIEEP1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 875},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 876},
- {"PCIEEP1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 876},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 877},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 877},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 878},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 878},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 879},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 879},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 880},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 880},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 881},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 881},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 882},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 882},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 883},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 883},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 884},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 884},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 885},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 885},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 886},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 886},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 887},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 887},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 888},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 888},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 889},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 889},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 890},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 890},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 891},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 891},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 892},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 892},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 893},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 893},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 894},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 894},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 895},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 895},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 896},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 896},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 897},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 897},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 898},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 898},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 899},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 899},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 900},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 900},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 901},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 901},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 902},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 902},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 903},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 903},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 904},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 904},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 905},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 905},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 906},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 906},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 907},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 907},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 908},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 908},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 909},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 909},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 910},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 910},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 911},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 911},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 912},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 912},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 913},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 913},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 914},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 914},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 915},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 915},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 916},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 916},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 917},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 917},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 918},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 918},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 919},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 919},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 920},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 920},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 921},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 921},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 922},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 922},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 923},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 923},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 924},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 924},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 925},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 925},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 926},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 926},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 927},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 927},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 928},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 928},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 929},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 929},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 930},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 930},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 931},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 931},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 932},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 932},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 933},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 933},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 934},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 934},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 935},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 935},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 936},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 936},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 937},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 937},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 938},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 938},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 939},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 939},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 940},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 940},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 941},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 941},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 942},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 942},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 943},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 943},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 944},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 944},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 945},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 945},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 946},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 946},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 947},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 947},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 948},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 948},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 949},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 949},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 950},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 950},
- {"PCIERC0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 951},
- {"PCIERC1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 951},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 952},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 952},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 953},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 953},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS0_AN002_ADV_REG" , 0x11800b0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS0_AN003_ADV_REG" , 0x11800b0001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS1_AN000_ADV_REG" , 0x11800b1001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS1_AN001_ADV_REG" , 0x11800b1001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS1_AN002_ADV_REG" , 0x11800b1001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS1_AN003_ADV_REG" , 0x11800b1001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS2_AN000_ADV_REG" , 0x11800b2001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS2_AN001_ADV_REG" , 0x11800b2001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS2_AN002_ADV_REG" , 0x11800b2001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS2_AN003_ADV_REG" , 0x11800b2001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS3_AN000_ADV_REG" , 0x11800b3001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS3_AN001_ADV_REG" , 0x11800b3001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS3_AN002_ADV_REG" , 0x11800b3001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS3_AN003_ADV_REG" , 0x11800b3001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS4_AN000_ADV_REG" , 0x11800b4001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS4_AN001_ADV_REG" , 0x11800b4001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS4_AN002_ADV_REG" , 0x11800b4001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS4_AN003_ADV_REG" , 0x11800b4001c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS0_AN002_EXT_ST_REG" , 0x11800b0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS0_AN003_EXT_ST_REG" , 0x11800b0001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS1_AN000_EXT_ST_REG" , 0x11800b1001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS1_AN001_EXT_ST_REG" , 0x11800b1001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS1_AN002_EXT_ST_REG" , 0x11800b1001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS1_AN003_EXT_ST_REG" , 0x11800b1001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS2_AN000_EXT_ST_REG" , 0x11800b2001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS2_AN001_EXT_ST_REG" , 0x11800b2001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS2_AN002_EXT_ST_REG" , 0x11800b2001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS2_AN003_EXT_ST_REG" , 0x11800b2001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS3_AN000_EXT_ST_REG" , 0x11800b3001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS3_AN001_EXT_ST_REG" , 0x11800b3001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS3_AN002_EXT_ST_REG" , 0x11800b3001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS3_AN003_EXT_ST_REG" , 0x11800b3001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS4_AN000_EXT_ST_REG" , 0x11800b4001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS4_AN001_EXT_ST_REG" , 0x11800b4001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS4_AN002_EXT_ST_REG" , 0x11800b4001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS4_AN003_EXT_ST_REG" , 0x11800b4001c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS0_AN002_LP_ABIL_REG" , 0x11800b0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS0_AN003_LP_ABIL_REG" , 0x11800b0001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS1_AN000_LP_ABIL_REG" , 0x11800b1001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS1_AN001_LP_ABIL_REG" , 0x11800b1001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS1_AN002_LP_ABIL_REG" , 0x11800b1001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS1_AN003_LP_ABIL_REG" , 0x11800b1001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS2_AN000_LP_ABIL_REG" , 0x11800b2001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS2_AN001_LP_ABIL_REG" , 0x11800b2001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS2_AN002_LP_ABIL_REG" , 0x11800b2001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS2_AN003_LP_ABIL_REG" , 0x11800b2001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS3_AN000_LP_ABIL_REG" , 0x11800b3001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS3_AN001_LP_ABIL_REG" , 0x11800b3001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS3_AN002_LP_ABIL_REG" , 0x11800b3001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS3_AN003_LP_ABIL_REG" , 0x11800b3001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS4_AN000_LP_ABIL_REG" , 0x11800b4001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS4_AN001_LP_ABIL_REG" , 0x11800b4001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS4_AN002_LP_ABIL_REG" , 0x11800b4001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS4_AN003_LP_ABIL_REG" , 0x11800b4001c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS0_AN002_RESULTS_REG" , 0x11800b0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS0_AN003_RESULTS_REG" , 0x11800b0001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS1_AN000_RESULTS_REG" , 0x11800b1001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS1_AN001_RESULTS_REG" , 0x11800b1001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS1_AN002_RESULTS_REG" , 0x11800b1001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS1_AN003_RESULTS_REG" , 0x11800b1001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS2_AN000_RESULTS_REG" , 0x11800b2001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS2_AN001_RESULTS_REG" , 0x11800b2001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS2_AN002_RESULTS_REG" , 0x11800b2001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS2_AN003_RESULTS_REG" , 0x11800b2001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS3_AN000_RESULTS_REG" , 0x11800b3001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS3_AN001_RESULTS_REG" , 0x11800b3001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS3_AN002_RESULTS_REG" , 0x11800b3001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS3_AN003_RESULTS_REG" , 0x11800b3001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS4_AN000_RESULTS_REG" , 0x11800b4001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS4_AN001_RESULTS_REG" , 0x11800b4001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS4_AN002_RESULTS_REG" , 0x11800b4001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS4_AN003_RESULTS_REG" , 0x11800b4001c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS0_INT002_EN_REG" , 0x11800b0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS0_INT003_EN_REG" , 0x11800b0001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS1_INT000_EN_REG" , 0x11800b1001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS1_INT001_EN_REG" , 0x11800b1001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS1_INT002_EN_REG" , 0x11800b1001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS1_INT003_EN_REG" , 0x11800b1001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS2_INT000_EN_REG" , 0x11800b2001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS2_INT001_EN_REG" , 0x11800b2001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS2_INT002_EN_REG" , 0x11800b2001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS2_INT003_EN_REG" , 0x11800b2001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS3_INT000_EN_REG" , 0x11800b3001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS3_INT001_EN_REG" , 0x11800b3001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS3_INT002_EN_REG" , 0x11800b3001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS3_INT003_EN_REG" , 0x11800b3001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS4_INT000_EN_REG" , 0x11800b4001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS4_INT001_EN_REG" , 0x11800b4001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS4_INT002_EN_REG" , 0x11800b4001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS4_INT003_EN_REG" , 0x11800b4001c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS0_INT002_REG" , 0x11800b0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS0_INT003_REG" , 0x11800b0001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS1_INT000_REG" , 0x11800b1001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS1_INT001_REG" , 0x11800b1001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS1_INT002_REG" , 0x11800b1001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS1_INT003_REG" , 0x11800b1001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS2_INT000_REG" , 0x11800b2001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS2_INT001_REG" , 0x11800b2001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS2_INT002_REG" , 0x11800b2001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS2_INT003_REG" , 0x11800b2001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS3_INT000_REG" , 0x11800b3001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS3_INT001_REG" , 0x11800b3001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS3_INT002_REG" , 0x11800b3001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS3_INT003_REG" , 0x11800b3001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS4_INT000_REG" , 0x11800b4001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS4_INT001_REG" , 0x11800b4001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS4_INT002_REG" , 0x11800b4001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS4_INT003_REG" , 0x11800b4001c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS0_LINK002_TIMER_COUNT_REG", 0x11800b0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS0_LINK003_TIMER_COUNT_REG", 0x11800b0001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS1_LINK000_TIMER_COUNT_REG", 0x11800b1001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS1_LINK001_TIMER_COUNT_REG", 0x11800b1001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS1_LINK002_TIMER_COUNT_REG", 0x11800b1001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS1_LINK003_TIMER_COUNT_REG", 0x11800b1001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS2_LINK000_TIMER_COUNT_REG", 0x11800b2001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS2_LINK001_TIMER_COUNT_REG", 0x11800b2001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS2_LINK002_TIMER_COUNT_REG", 0x11800b2001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS2_LINK003_TIMER_COUNT_REG", 0x11800b2001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS3_LINK000_TIMER_COUNT_REG", 0x11800b3001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS3_LINK001_TIMER_COUNT_REG", 0x11800b3001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS3_LINK002_TIMER_COUNT_REG", 0x11800b3001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS3_LINK003_TIMER_COUNT_REG", 0x11800b3001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS4_LINK000_TIMER_COUNT_REG", 0x11800b4001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS4_LINK001_TIMER_COUNT_REG", 0x11800b4001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS4_LINK002_TIMER_COUNT_REG", 0x11800b4001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS4_LINK003_TIMER_COUNT_REG", 0x11800b4001c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS0_LOG_ANL002_REG" , 0x11800b0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS0_LOG_ANL003_REG" , 0x11800b0001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS1_LOG_ANL000_REG" , 0x11800b1001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS1_LOG_ANL001_REG" , 0x11800b1001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS1_LOG_ANL002_REG" , 0x11800b1001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS1_LOG_ANL003_REG" , 0x11800b1001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS2_LOG_ANL000_REG" , 0x11800b2001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS2_LOG_ANL001_REG" , 0x11800b2001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS2_LOG_ANL002_REG" , 0x11800b2001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS2_LOG_ANL003_REG" , 0x11800b2001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS3_LOG_ANL000_REG" , 0x11800b3001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS3_LOG_ANL001_REG" , 0x11800b3001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS3_LOG_ANL002_REG" , 0x11800b3001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS3_LOG_ANL003_REG" , 0x11800b3001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS4_LOG_ANL000_REG" , 0x11800b4001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS4_LOG_ANL001_REG" , 0x11800b4001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS4_LOG_ANL002_REG" , 0x11800b4001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS4_LOG_ANL003_REG" , 0x11800b4001c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS0_MISC002_CTL_REG" , 0x11800b0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS0_MISC003_CTL_REG" , 0x11800b0001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS1_MISC000_CTL_REG" , 0x11800b1001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS1_MISC001_CTL_REG" , 0x11800b1001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS1_MISC002_CTL_REG" , 0x11800b1001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS1_MISC003_CTL_REG" , 0x11800b1001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS2_MISC000_CTL_REG" , 0x11800b2001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS2_MISC001_CTL_REG" , 0x11800b2001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS2_MISC002_CTL_REG" , 0x11800b2001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS2_MISC003_CTL_REG" , 0x11800b2001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS3_MISC000_CTL_REG" , 0x11800b3001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS3_MISC001_CTL_REG" , 0x11800b3001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS3_MISC002_CTL_REG" , 0x11800b3001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS3_MISC003_CTL_REG" , 0x11800b3001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS4_MISC000_CTL_REG" , 0x11800b4001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS4_MISC001_CTL_REG" , 0x11800b4001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS4_MISC002_CTL_REG" , 0x11800b4001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS4_MISC003_CTL_REG" , 0x11800b4001c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS0_MR002_CONTROL_REG" , 0x11800b0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS0_MR003_CONTROL_REG" , 0x11800b0001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS1_MR000_CONTROL_REG" , 0x11800b1001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS1_MR001_CONTROL_REG" , 0x11800b1001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS1_MR002_CONTROL_REG" , 0x11800b1001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS1_MR003_CONTROL_REG" , 0x11800b1001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS2_MR000_CONTROL_REG" , 0x11800b2001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS2_MR001_CONTROL_REG" , 0x11800b2001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS2_MR002_CONTROL_REG" , 0x11800b2001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS2_MR003_CONTROL_REG" , 0x11800b2001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS3_MR000_CONTROL_REG" , 0x11800b3001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS3_MR001_CONTROL_REG" , 0x11800b3001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS3_MR002_CONTROL_REG" , 0x11800b3001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS3_MR003_CONTROL_REG" , 0x11800b3001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS4_MR000_CONTROL_REG" , 0x11800b4001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS4_MR001_CONTROL_REG" , 0x11800b4001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS4_MR002_CONTROL_REG" , 0x11800b4001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS4_MR003_CONTROL_REG" , 0x11800b4001c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS0_MR002_STATUS_REG" , 0x11800b0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS0_MR003_STATUS_REG" , 0x11800b0001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS1_MR000_STATUS_REG" , 0x11800b1001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS1_MR001_STATUS_REG" , 0x11800b1001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS1_MR002_STATUS_REG" , 0x11800b1001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS1_MR003_STATUS_REG" , 0x11800b1001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS2_MR000_STATUS_REG" , 0x11800b2001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS2_MR001_STATUS_REG" , 0x11800b2001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS2_MR002_STATUS_REG" , 0x11800b2001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS2_MR003_STATUS_REG" , 0x11800b2001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS3_MR000_STATUS_REG" , 0x11800b3001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS3_MR001_STATUS_REG" , 0x11800b3001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS3_MR002_STATUS_REG" , 0x11800b3001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS3_MR003_STATUS_REG" , 0x11800b3001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS4_MR000_STATUS_REG" , 0x11800b4001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS4_MR001_STATUS_REG" , 0x11800b4001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS4_MR002_STATUS_REG" , 0x11800b4001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS4_MR003_STATUS_REG" , 0x11800b4001c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS0_RX002_STATES_REG" , 0x11800b0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS0_RX003_STATES_REG" , 0x11800b0001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS1_RX000_STATES_REG" , 0x11800b1001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS1_RX001_STATES_REG" , 0x11800b1001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS1_RX002_STATES_REG" , 0x11800b1001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS1_RX003_STATES_REG" , 0x11800b1001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS2_RX000_STATES_REG" , 0x11800b2001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS2_RX001_STATES_REG" , 0x11800b2001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS2_RX002_STATES_REG" , 0x11800b2001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS2_RX003_STATES_REG" , 0x11800b2001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS3_RX000_STATES_REG" , 0x11800b3001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS3_RX001_STATES_REG" , 0x11800b3001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS3_RX002_STATES_REG" , 0x11800b3001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS3_RX003_STATES_REG" , 0x11800b3001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS4_RX000_STATES_REG" , 0x11800b4001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS4_RX001_STATES_REG" , 0x11800b4001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS4_RX002_STATES_REG" , 0x11800b4001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS4_RX003_STATES_REG" , 0x11800b4001c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS0_RX002_SYNC_REG" , 0x11800b0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS0_RX003_SYNC_REG" , 0x11800b0001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS1_RX000_SYNC_REG" , 0x11800b1001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS1_RX001_SYNC_REG" , 0x11800b1001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS1_RX002_SYNC_REG" , 0x11800b1001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS1_RX003_SYNC_REG" , 0x11800b1001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS2_RX000_SYNC_REG" , 0x11800b2001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS2_RX001_SYNC_REG" , 0x11800b2001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS2_RX002_SYNC_REG" , 0x11800b2001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS2_RX003_SYNC_REG" , 0x11800b2001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS3_RX000_SYNC_REG" , 0x11800b3001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS3_RX001_SYNC_REG" , 0x11800b3001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS3_RX002_SYNC_REG" , 0x11800b3001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS3_RX003_SYNC_REG" , 0x11800b3001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS4_RX000_SYNC_REG" , 0x11800b4001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS4_RX001_SYNC_REG" , 0x11800b4001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS4_RX002_SYNC_REG" , 0x11800b4001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS4_RX003_SYNC_REG" , 0x11800b4001c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS0_SGM002_AN_ADV_REG" , 0x11800b0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS0_SGM003_AN_ADV_REG" , 0x11800b0001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS1_SGM000_AN_ADV_REG" , 0x11800b1001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS1_SGM001_AN_ADV_REG" , 0x11800b1001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS1_SGM002_AN_ADV_REG" , 0x11800b1001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS1_SGM003_AN_ADV_REG" , 0x11800b1001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS2_SGM000_AN_ADV_REG" , 0x11800b2001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS2_SGM001_AN_ADV_REG" , 0x11800b2001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS2_SGM002_AN_ADV_REG" , 0x11800b2001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS2_SGM003_AN_ADV_REG" , 0x11800b2001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS3_SGM000_AN_ADV_REG" , 0x11800b3001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS3_SGM001_AN_ADV_REG" , 0x11800b3001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS3_SGM002_AN_ADV_REG" , 0x11800b3001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS3_SGM003_AN_ADV_REG" , 0x11800b3001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS4_SGM000_AN_ADV_REG" , 0x11800b4001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS4_SGM001_AN_ADV_REG" , 0x11800b4001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS4_SGM002_AN_ADV_REG" , 0x11800b4001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS4_SGM003_AN_ADV_REG" , 0x11800b4001c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS0_SGM002_LP_ADV_REG" , 0x11800b0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS0_SGM003_LP_ADV_REG" , 0x11800b0001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS1_SGM000_LP_ADV_REG" , 0x11800b1001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS1_SGM001_LP_ADV_REG" , 0x11800b1001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS1_SGM002_LP_ADV_REG" , 0x11800b1001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS1_SGM003_LP_ADV_REG" , 0x11800b1001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS2_SGM000_LP_ADV_REG" , 0x11800b2001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS2_SGM001_LP_ADV_REG" , 0x11800b2001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS2_SGM002_LP_ADV_REG" , 0x11800b2001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS2_SGM003_LP_ADV_REG" , 0x11800b2001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS3_SGM000_LP_ADV_REG" , 0x11800b3001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS3_SGM001_LP_ADV_REG" , 0x11800b3001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS3_SGM002_LP_ADV_REG" , 0x11800b3001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS3_SGM003_LP_ADV_REG" , 0x11800b3001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS4_SGM000_LP_ADV_REG" , 0x11800b4001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS4_SGM001_LP_ADV_REG" , 0x11800b4001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS4_SGM002_LP_ADV_REG" , 0x11800b4001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS4_SGM003_LP_ADV_REG" , 0x11800b4001c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS0_TX002_STATES_REG" , 0x11800b0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS0_TX003_STATES_REG" , 0x11800b0001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS1_TX000_STATES_REG" , 0x11800b1001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS1_TX001_STATES_REG" , 0x11800b1001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS1_TX002_STATES_REG" , 0x11800b1001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS1_TX003_STATES_REG" , 0x11800b1001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS2_TX000_STATES_REG" , 0x11800b2001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS2_TX001_STATES_REG" , 0x11800b2001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS2_TX002_STATES_REG" , 0x11800b2001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS2_TX003_STATES_REG" , 0x11800b2001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS3_TX000_STATES_REG" , 0x11800b3001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS3_TX001_STATES_REG" , 0x11800b3001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS3_TX002_STATES_REG" , 0x11800b3001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS3_TX003_STATES_REG" , 0x11800b3001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS4_TX000_STATES_REG" , 0x11800b4001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS4_TX001_STATES_REG" , 0x11800b4001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS4_TX002_STATES_REG" , 0x11800b4001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS4_TX003_STATES_REG" , 0x11800b4001c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS0_TX_RX002_POLARITY_REG" , 0x11800b0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS0_TX_RX003_POLARITY_REG" , 0x11800b0001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS1_TX_RX000_POLARITY_REG" , 0x11800b1001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS1_TX_RX001_POLARITY_REG" , 0x11800b1001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS1_TX_RX002_POLARITY_REG" , 0x11800b1001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS1_TX_RX003_POLARITY_REG" , 0x11800b1001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS2_TX_RX000_POLARITY_REG" , 0x11800b2001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS2_TX_RX001_POLARITY_REG" , 0x11800b2001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS2_TX_RX002_POLARITY_REG" , 0x11800b2001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS2_TX_RX003_POLARITY_REG" , 0x11800b2001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS3_TX_RX000_POLARITY_REG" , 0x11800b3001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS3_TX_RX001_POLARITY_REG" , 0x11800b3001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS3_TX_RX002_POLARITY_REG" , 0x11800b3001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS3_TX_RX003_POLARITY_REG" , 0x11800b3001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS4_TX_RX000_POLARITY_REG" , 0x11800b4001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS4_TX_RX001_POLARITY_REG" , 0x11800b4001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS4_TX_RX002_POLARITY_REG" , 0x11800b4001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCS4_TX_RX003_POLARITY_REG" , 0x11800b4001c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PCSX0_10GBX_STATUS_REG" , 0x11800b0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PCSX1_10GBX_STATUS_REG" , 0x11800b1000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PCSX2_10GBX_STATUS_REG" , 0x11800b2000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PCSX3_10GBX_STATUS_REG" , 0x11800b3000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PCSX4_10GBX_STATUS_REG" , 0x11800b4000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PCSX0_BIST_STATUS_REG" , 0x11800b0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
- {"PCSX1_BIST_STATUS_REG" , 0x11800b1000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
- {"PCSX2_BIST_STATUS_REG" , 0x11800b2000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
- {"PCSX3_BIST_STATUS_REG" , 0x11800b3000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
- {"PCSX4_BIST_STATUS_REG" , 0x11800b4000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
- {"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800b0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
- {"PCSX1_BIT_LOCK_STATUS_REG" , 0x11800b1000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
- {"PCSX2_BIT_LOCK_STATUS_REG" , 0x11800b2000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
- {"PCSX3_BIT_LOCK_STATUS_REG" , 0x11800b3000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
- {"PCSX4_BIT_LOCK_STATUS_REG" , 0x11800b4000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
- {"PCSX0_CONTROL1_REG" , 0x11800b0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
- {"PCSX1_CONTROL1_REG" , 0x11800b1000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
- {"PCSX2_CONTROL1_REG" , 0x11800b2000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
- {"PCSX3_CONTROL1_REG" , 0x11800b3000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
- {"PCSX4_CONTROL1_REG" , 0x11800b4000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
- {"PCSX0_CONTROL2_REG" , 0x11800b0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 975},
- {"PCSX1_CONTROL2_REG" , 0x11800b1000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 975},
- {"PCSX2_CONTROL2_REG" , 0x11800b2000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 975},
- {"PCSX3_CONTROL2_REG" , 0x11800b3000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 975},
- {"PCSX4_CONTROL2_REG" , 0x11800b4000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 975},
- {"PCSX0_INT_EN_REG" , 0x11800b0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 976},
- {"PCSX1_INT_EN_REG" , 0x11800b1000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 976},
- {"PCSX2_INT_EN_REG" , 0x11800b2000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 976},
- {"PCSX3_INT_EN_REG" , 0x11800b3000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 976},
- {"PCSX4_INT_EN_REG" , 0x11800b4000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 976},
- {"PCSX0_INT_REG" , 0x11800b0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 977},
- {"PCSX1_INT_REG" , 0x11800b1000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 977},
- {"PCSX2_INT_REG" , 0x11800b2000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 977},
- {"PCSX3_INT_REG" , 0x11800b3000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 977},
- {"PCSX4_INT_REG" , 0x11800b4000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 977},
- {"PCSX0_LOG_ANL_REG" , 0x11800b0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 978},
- {"PCSX1_LOG_ANL_REG" , 0x11800b1000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 978},
- {"PCSX2_LOG_ANL_REG" , 0x11800b2000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 978},
- {"PCSX3_LOG_ANL_REG" , 0x11800b3000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 978},
- {"PCSX4_LOG_ANL_REG" , 0x11800b4000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 978},
- {"PCSX0_MISC_CTL_REG" , 0x11800b0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 979},
- {"PCSX1_MISC_CTL_REG" , 0x11800b1000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 979},
- {"PCSX2_MISC_CTL_REG" , 0x11800b2000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 979},
- {"PCSX3_MISC_CTL_REG" , 0x11800b3000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 979},
- {"PCSX4_MISC_CTL_REG" , 0x11800b4000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 979},
- {"PCSX0_RX_SYNC_STATES_REG" , 0x11800b0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 980},
- {"PCSX1_RX_SYNC_STATES_REG" , 0x11800b1000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 980},
- {"PCSX2_RX_SYNC_STATES_REG" , 0x11800b2000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 980},
- {"PCSX3_RX_SYNC_STATES_REG" , 0x11800b3000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 980},
- {"PCSX4_RX_SYNC_STATES_REG" , 0x11800b4000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 980},
- {"PCSX0_SPD_ABIL_REG" , 0x11800b0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 981},
- {"PCSX1_SPD_ABIL_REG" , 0x11800b1000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 981},
- {"PCSX2_SPD_ABIL_REG" , 0x11800b2000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 981},
- {"PCSX3_SPD_ABIL_REG" , 0x11800b3000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 981},
- {"PCSX4_SPD_ABIL_REG" , 0x11800b4000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 981},
- {"PCSX0_STATUS1_REG" , 0x11800b0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 982},
- {"PCSX1_STATUS1_REG" , 0x11800b1000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 982},
- {"PCSX2_STATUS1_REG" , 0x11800b2000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 982},
- {"PCSX3_STATUS1_REG" , 0x11800b3000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 982},
- {"PCSX4_STATUS1_REG" , 0x11800b4000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 982},
- {"PCSX0_STATUS2_REG" , 0x11800b0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 983},
- {"PCSX1_STATUS2_REG" , 0x11800b1000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 983},
- {"PCSX2_STATUS2_REG" , 0x11800b2000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 983},
- {"PCSX3_STATUS2_REG" , 0x11800b3000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 983},
- {"PCSX4_STATUS2_REG" , 0x11800b4000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 983},
- {"PCSX0_TX_RX_POLARITY_REG" , 0x11800b0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 984},
- {"PCSX1_TX_RX_POLARITY_REG" , 0x11800b1000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 984},
- {"PCSX2_TX_RX_POLARITY_REG" , 0x11800b2000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 984},
- {"PCSX3_TX_RX_POLARITY_REG" , 0x11800b3000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 984},
- {"PCSX4_TX_RX_POLARITY_REG" , 0x11800b4000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 984},
- {"PCSX0_TX_RX_STATES_REG" , 0x11800b0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 985},
- {"PCSX1_TX_RX_STATES_REG" , 0x11800b1000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 985},
- {"PCSX2_TX_RX_STATES_REG" , 0x11800b2000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 985},
- {"PCSX3_TX_RX_STATES_REG" , 0x11800b3000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 985},
- {"PCSX4_TX_RX_STATES_REG" , 0x11800b4000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 985},
- {"PEM0_BAR1_INDEX000" , 0x11800c00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX001" , 0x11800c00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX002" , 0x11800c00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX003" , 0x11800c00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX004" , 0x11800c00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX005" , 0x11800c00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX006" , 0x11800c00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX007" , 0x11800c00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX008" , 0x11800c00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX009" , 0x11800c00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX010" , 0x11800c00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX011" , 0x11800c0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX012" , 0x11800c0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX013" , 0x11800c0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX014" , 0x11800c0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR1_INDEX015" , 0x11800c0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX000" , 0x11800c10000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX001" , 0x11800c10000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX002" , 0x11800c10000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX003" , 0x11800c10000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX004" , 0x11800c10000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX005" , 0x11800c10000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX006" , 0x11800c10000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX007" , 0x11800c10000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX008" , 0x11800c10000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX009" , 0x11800c10000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX010" , 0x11800c10000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX011" , 0x11800c1000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX012" , 0x11800c1000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX013" , 0x11800c1000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX014" , 0x11800c1000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM1_BAR1_INDEX015" , 0x11800c1000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 986},
- {"PEM0_BAR2_MASK" , 0x11800c0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 987},
- {"PEM1_BAR2_MASK" , 0x11800c1000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 987},
- {"PEM0_BAR_CTL" , 0x11800c0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 988},
- {"PEM1_BAR_CTL" , 0x11800c1000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 988},
- {"PEM0_BIST_STATUS" , 0x11800c0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"PEM1_BIST_STATUS" , 0x11800c1000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 989},
- {"PEM0_BIST_STATUS2" , 0x11800c0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"PEM1_BIST_STATUS2" , 0x11800c1000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 990},
- {"PEM0_CFG_RD" , 0x11800c0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 991},
- {"PEM1_CFG_RD" , 0x11800c1000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 991},
- {"PEM0_CFG_WR" , 0x11800c0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 992},
- {"PEM1_CFG_WR" , 0x11800c1000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 992},
- {"PEM0_CPL_LUT_VALID" , 0x11800c0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 993},
- {"PEM1_CPL_LUT_VALID" , 0x11800c1000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 993},
- {"PEM0_CTL_STATUS" , 0x11800c0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"PEM1_CTL_STATUS" , 0x11800c1000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 994},
- {"PEM0_DBG_INFO" , 0x11800c0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"PEM1_DBG_INFO" , 0x11800c1000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 995},
- {"PEM0_DBG_INFO_EN" , 0x11800c00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 996},
- {"PEM1_DBG_INFO_EN" , 0x11800c10000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 996},
- {"PEM0_DIAG_STATUS" , 0x11800c0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 997},
- {"PEM1_DIAG_STATUS" , 0x11800c1000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 997},
- {"PEM0_INB_READ_CREDITS" , 0x11800c0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 998},
- {"PEM1_INB_READ_CREDITS" , 0x11800c1000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 998},
- {"PEM0_INT_ENB" , 0x11800c0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 999},
- {"PEM1_INT_ENB" , 0x11800c1000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 999},
- {"PEM0_INT_ENB_INT" , 0x11800c0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1000},
- {"PEM1_INT_ENB_INT" , 0x11800c1000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1000},
- {"PEM0_INT_SUM" , 0x11800c0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1001},
- {"PEM1_INT_SUM" , 0x11800c1000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1001},
- {"PEM0_P2N_BAR0_START" , 0x11800c0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1002},
- {"PEM1_P2N_BAR0_START" , 0x11800c1000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1002},
- {"PEM0_P2N_BAR1_START" , 0x11800c0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1003},
- {"PEM1_P2N_BAR1_START" , 0x11800c1000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1003},
- {"PEM0_P2N_BAR2_START" , 0x11800c0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PEM1_P2N_BAR2_START" , 0x11800c1000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"PEM0_P2P_BAR000_END" , 0x11800c0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PEM0_P2P_BAR001_END" , 0x11800c0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PEM0_P2P_BAR002_END" , 0x11800c0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PEM0_P2P_BAR003_END" , 0x11800c0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PEM1_P2P_BAR000_END" , 0x11800c1000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PEM1_P2P_BAR001_END" , 0x11800c1000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PEM1_P2P_BAR002_END" , 0x11800c1000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PEM1_P2P_BAR003_END" , 0x11800c1000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"PEM0_P2P_BAR000_START" , 0x11800c0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PEM0_P2P_BAR001_START" , 0x11800c0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PEM0_P2P_BAR002_START" , 0x11800c0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PEM0_P2P_BAR003_START" , 0x11800c0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PEM1_P2P_BAR000_START" , 0x11800c1000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PEM1_P2P_BAR001_START" , 0x11800c1000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PEM1_P2P_BAR002_START" , 0x11800c1000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PEM1_P2P_BAR003_START" , 0x11800c1000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"PEM0_TLP_CREDITS" , 0x11800c0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PEM1_TLP_CREDITS" , 0x11800c1000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"PIP_ALT_SKIP_CFG0" , 0x11800a0002a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_ALT_SKIP_CFG1" , 0x11800a0002a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_ALT_SKIP_CFG2" , 0x11800a0002a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_ALT_SKIP_CFG3" , 0x11800a0002a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1009},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1010},
- {"PIP_BSEL_EXT_CFG0" , 0x11800a0002800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_BSEL_EXT_CFG1" , 0x11800a0002810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_BSEL_EXT_CFG2" , 0x11800a0002820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_BSEL_EXT_CFG3" , 0x11800a0002830ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"PIP_BSEL_EXT_POS0" , 0x11800a0002808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_BSEL_EXT_POS1" , 0x11800a0002818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_BSEL_EXT_POS2" , 0x11800a0002828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_BSEL_EXT_POS3" , 0x11800a0002838ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"PIP_BSEL_TBL_ENT0" , 0x11800a0003000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT1" , 0x11800a0003008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT2" , 0x11800a0003010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT3" , 0x11800a0003018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT4" , 0x11800a0003020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT5" , 0x11800a0003028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT6" , 0x11800a0003030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT7" , 0x11800a0003038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT8" , 0x11800a0003040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT9" , 0x11800a0003048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT10" , 0x11800a0003050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT11" , 0x11800a0003058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT12" , 0x11800a0003060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT13" , 0x11800a0003068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT14" , 0x11800a0003070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT15" , 0x11800a0003078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT16" , 0x11800a0003080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT17" , 0x11800a0003088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT18" , 0x11800a0003090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT19" , 0x11800a0003098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT20" , 0x11800a00030a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT21" , 0x11800a00030a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT22" , 0x11800a00030b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT23" , 0x11800a00030b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT24" , 0x11800a00030c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT25" , 0x11800a00030c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT26" , 0x11800a00030d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT27" , 0x11800a00030d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT28" , 0x11800a00030e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT29" , 0x11800a00030e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT30" , 0x11800a00030f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT31" , 0x11800a00030f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT32" , 0x11800a0003100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT33" , 0x11800a0003108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT34" , 0x11800a0003110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT35" , 0x11800a0003118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT36" , 0x11800a0003120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT37" , 0x11800a0003128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT38" , 0x11800a0003130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT39" , 0x11800a0003138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT40" , 0x11800a0003140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT41" , 0x11800a0003148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT42" , 0x11800a0003150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT43" , 0x11800a0003158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT44" , 0x11800a0003160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT45" , 0x11800a0003168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT46" , 0x11800a0003170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT47" , 0x11800a0003178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT48" , 0x11800a0003180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT49" , 0x11800a0003188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT50" , 0x11800a0003190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT51" , 0x11800a0003198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT52" , 0x11800a00031a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT53" , 0x11800a00031a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT54" , 0x11800a00031b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT55" , 0x11800a00031b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT56" , 0x11800a00031c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT57" , 0x11800a00031c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT58" , 0x11800a00031d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT59" , 0x11800a00031d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT60" , 0x11800a00031e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT61" , 0x11800a00031e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT62" , 0x11800a00031f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT63" , 0x11800a00031f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT64" , 0x11800a0003200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT65" , 0x11800a0003208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT66" , 0x11800a0003210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT67" , 0x11800a0003218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT68" , 0x11800a0003220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT69" , 0x11800a0003228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT70" , 0x11800a0003230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT71" , 0x11800a0003238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT72" , 0x11800a0003240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT73" , 0x11800a0003248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT74" , 0x11800a0003250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT75" , 0x11800a0003258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT76" , 0x11800a0003260ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT77" , 0x11800a0003268ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT78" , 0x11800a0003270ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT79" , 0x11800a0003278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT80" , 0x11800a0003280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT81" , 0x11800a0003288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT82" , 0x11800a0003290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT83" , 0x11800a0003298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT84" , 0x11800a00032a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT85" , 0x11800a00032a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT86" , 0x11800a00032b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT87" , 0x11800a00032b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT88" , 0x11800a00032c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT89" , 0x11800a00032c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT90" , 0x11800a00032d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT91" , 0x11800a00032d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT92" , 0x11800a00032e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT93" , 0x11800a00032e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT94" , 0x11800a00032f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT95" , 0x11800a00032f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT96" , 0x11800a0003300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT97" , 0x11800a0003308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT98" , 0x11800a0003310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT99" , 0x11800a0003318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT100" , 0x11800a0003320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT101" , 0x11800a0003328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT102" , 0x11800a0003330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT103" , 0x11800a0003338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT104" , 0x11800a0003340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT105" , 0x11800a0003348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT106" , 0x11800a0003350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT107" , 0x11800a0003358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT108" , 0x11800a0003360ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT109" , 0x11800a0003368ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT110" , 0x11800a0003370ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT111" , 0x11800a0003378ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT112" , 0x11800a0003380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT113" , 0x11800a0003388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT114" , 0x11800a0003390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT115" , 0x11800a0003398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT116" , 0x11800a00033a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT117" , 0x11800a00033a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT118" , 0x11800a00033b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT119" , 0x11800a00033b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT120" , 0x11800a00033c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT121" , 0x11800a00033c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT122" , 0x11800a00033d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT123" , 0x11800a00033d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT124" , 0x11800a00033e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT125" , 0x11800a00033e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT126" , 0x11800a00033f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT127" , 0x11800a00033f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT128" , 0x11800a0003400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT129" , 0x11800a0003408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT130" , 0x11800a0003410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT131" , 0x11800a0003418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT132" , 0x11800a0003420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT133" , 0x11800a0003428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT134" , 0x11800a0003430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT135" , 0x11800a0003438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT136" , 0x11800a0003440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT137" , 0x11800a0003448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT138" , 0x11800a0003450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT139" , 0x11800a0003458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT140" , 0x11800a0003460ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT141" , 0x11800a0003468ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT142" , 0x11800a0003470ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT143" , 0x11800a0003478ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT144" , 0x11800a0003480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT145" , 0x11800a0003488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT146" , 0x11800a0003490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT147" , 0x11800a0003498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT148" , 0x11800a00034a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT149" , 0x11800a00034a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT150" , 0x11800a00034b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT151" , 0x11800a00034b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT152" , 0x11800a00034c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT153" , 0x11800a00034c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT154" , 0x11800a00034d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT155" , 0x11800a00034d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT156" , 0x11800a00034e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT157" , 0x11800a00034e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT158" , 0x11800a00034f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT159" , 0x11800a00034f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT160" , 0x11800a0003500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT161" , 0x11800a0003508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT162" , 0x11800a0003510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT163" , 0x11800a0003518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT164" , 0x11800a0003520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT165" , 0x11800a0003528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT166" , 0x11800a0003530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT167" , 0x11800a0003538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT168" , 0x11800a0003540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT169" , 0x11800a0003548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT170" , 0x11800a0003550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT171" , 0x11800a0003558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT172" , 0x11800a0003560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT173" , 0x11800a0003568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT174" , 0x11800a0003570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT175" , 0x11800a0003578ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT176" , 0x11800a0003580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT177" , 0x11800a0003588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT178" , 0x11800a0003590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT179" , 0x11800a0003598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT180" , 0x11800a00035a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT181" , 0x11800a00035a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT182" , 0x11800a00035b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT183" , 0x11800a00035b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT184" , 0x11800a00035c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT185" , 0x11800a00035c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT186" , 0x11800a00035d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT187" , 0x11800a00035d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT188" , 0x11800a00035e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT189" , 0x11800a00035e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT190" , 0x11800a00035f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT191" , 0x11800a00035f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT192" , 0x11800a0003600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT193" , 0x11800a0003608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT194" , 0x11800a0003610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT195" , 0x11800a0003618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT196" , 0x11800a0003620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT197" , 0x11800a0003628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT198" , 0x11800a0003630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT199" , 0x11800a0003638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT200" , 0x11800a0003640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT201" , 0x11800a0003648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT202" , 0x11800a0003650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT203" , 0x11800a0003658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT204" , 0x11800a0003660ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT205" , 0x11800a0003668ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT206" , 0x11800a0003670ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT207" , 0x11800a0003678ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT208" , 0x11800a0003680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT209" , 0x11800a0003688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT210" , 0x11800a0003690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT211" , 0x11800a0003698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT212" , 0x11800a00036a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT213" , 0x11800a00036a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT214" , 0x11800a00036b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT215" , 0x11800a00036b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT216" , 0x11800a00036c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT217" , 0x11800a00036c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT218" , 0x11800a00036d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT219" , 0x11800a00036d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT220" , 0x11800a00036e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT221" , 0x11800a00036e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT222" , 0x11800a00036f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT223" , 0x11800a00036f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT224" , 0x11800a0003700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT225" , 0x11800a0003708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT226" , 0x11800a0003710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT227" , 0x11800a0003718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT228" , 0x11800a0003720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT229" , 0x11800a0003728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT230" , 0x11800a0003730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT231" , 0x11800a0003738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT232" , 0x11800a0003740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT233" , 0x11800a0003748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT234" , 0x11800a0003750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT235" , 0x11800a0003758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT236" , 0x11800a0003760ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT237" , 0x11800a0003768ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT238" , 0x11800a0003770ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT239" , 0x11800a0003778ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT240" , 0x11800a0003780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT241" , 0x11800a0003788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT242" , 0x11800a0003790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT243" , 0x11800a0003798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT244" , 0x11800a00037a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT245" , 0x11800a00037a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT246" , 0x11800a00037b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT247" , 0x11800a00037b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT248" , 0x11800a00037c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT249" , 0x11800a00037c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT250" , 0x11800a00037d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT251" , 0x11800a00037d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT252" , 0x11800a00037e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT253" , 0x11800a00037e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT254" , 0x11800a00037f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT255" , 0x11800a00037f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT256" , 0x11800a0003800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT257" , 0x11800a0003808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT258" , 0x11800a0003810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT259" , 0x11800a0003818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT260" , 0x11800a0003820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT261" , 0x11800a0003828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT262" , 0x11800a0003830ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT263" , 0x11800a0003838ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT264" , 0x11800a0003840ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT265" , 0x11800a0003848ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT266" , 0x11800a0003850ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT267" , 0x11800a0003858ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT268" , 0x11800a0003860ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT269" , 0x11800a0003868ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT270" , 0x11800a0003870ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT271" , 0x11800a0003878ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT272" , 0x11800a0003880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT273" , 0x11800a0003888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT274" , 0x11800a0003890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT275" , 0x11800a0003898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT276" , 0x11800a00038a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT277" , 0x11800a00038a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT278" , 0x11800a00038b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT279" , 0x11800a00038b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT280" , 0x11800a00038c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT281" , 0x11800a00038c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT282" , 0x11800a00038d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT283" , 0x11800a00038d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT284" , 0x11800a00038e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT285" , 0x11800a00038e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT286" , 0x11800a00038f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT287" , 0x11800a00038f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT288" , 0x11800a0003900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT289" , 0x11800a0003908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT290" , 0x11800a0003910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT291" , 0x11800a0003918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT292" , 0x11800a0003920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT293" , 0x11800a0003928ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT294" , 0x11800a0003930ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT295" , 0x11800a0003938ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT296" , 0x11800a0003940ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT297" , 0x11800a0003948ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT298" , 0x11800a0003950ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT299" , 0x11800a0003958ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT300" , 0x11800a0003960ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT301" , 0x11800a0003968ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT302" , 0x11800a0003970ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT303" , 0x11800a0003978ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT304" , 0x11800a0003980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT305" , 0x11800a0003988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT306" , 0x11800a0003990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT307" , 0x11800a0003998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT308" , 0x11800a00039a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT309" , 0x11800a00039a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT310" , 0x11800a00039b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT311" , 0x11800a00039b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT312" , 0x11800a00039c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT313" , 0x11800a00039c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT314" , 0x11800a00039d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT315" , 0x11800a00039d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT316" , 0x11800a00039e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT317" , 0x11800a00039e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT318" , 0x11800a00039f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT319" , 0x11800a00039f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT320" , 0x11800a0003a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT321" , 0x11800a0003a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT322" , 0x11800a0003a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT323" , 0x11800a0003a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT324" , 0x11800a0003a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT325" , 0x11800a0003a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT326" , 0x11800a0003a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT327" , 0x11800a0003a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT328" , 0x11800a0003a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT329" , 0x11800a0003a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT330" , 0x11800a0003a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT331" , 0x11800a0003a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT332" , 0x11800a0003a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT333" , 0x11800a0003a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT334" , 0x11800a0003a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT335" , 0x11800a0003a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT336" , 0x11800a0003a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT337" , 0x11800a0003a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT338" , 0x11800a0003a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT339" , 0x11800a0003a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT340" , 0x11800a0003aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT341" , 0x11800a0003aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT342" , 0x11800a0003ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT343" , 0x11800a0003ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT344" , 0x11800a0003ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT345" , 0x11800a0003ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT346" , 0x11800a0003ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT347" , 0x11800a0003ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT348" , 0x11800a0003ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT349" , 0x11800a0003ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT350" , 0x11800a0003af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT351" , 0x11800a0003af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT352" , 0x11800a0003b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT353" , 0x11800a0003b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT354" , 0x11800a0003b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT355" , 0x11800a0003b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT356" , 0x11800a0003b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT357" , 0x11800a0003b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT358" , 0x11800a0003b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT359" , 0x11800a0003b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT360" , 0x11800a0003b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT361" , 0x11800a0003b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT362" , 0x11800a0003b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT363" , 0x11800a0003b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT364" , 0x11800a0003b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT365" , 0x11800a0003b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT366" , 0x11800a0003b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT367" , 0x11800a0003b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT368" , 0x11800a0003b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT369" , 0x11800a0003b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT370" , 0x11800a0003b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT371" , 0x11800a0003b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT372" , 0x11800a0003ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT373" , 0x11800a0003ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT374" , 0x11800a0003bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT375" , 0x11800a0003bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT376" , 0x11800a0003bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT377" , 0x11800a0003bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT378" , 0x11800a0003bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT379" , 0x11800a0003bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT380" , 0x11800a0003be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT381" , 0x11800a0003be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT382" , 0x11800a0003bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT383" , 0x11800a0003bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT384" , 0x11800a0003c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT385" , 0x11800a0003c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT386" , 0x11800a0003c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT387" , 0x11800a0003c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT388" , 0x11800a0003c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT389" , 0x11800a0003c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT390" , 0x11800a0003c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT391" , 0x11800a0003c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT392" , 0x11800a0003c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT393" , 0x11800a0003c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT394" , 0x11800a0003c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT395" , 0x11800a0003c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT396" , 0x11800a0003c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT397" , 0x11800a0003c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT398" , 0x11800a0003c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT399" , 0x11800a0003c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT400" , 0x11800a0003c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT401" , 0x11800a0003c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT402" , 0x11800a0003c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT403" , 0x11800a0003c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT404" , 0x11800a0003ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT405" , 0x11800a0003ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT406" , 0x11800a0003cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT407" , 0x11800a0003cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT408" , 0x11800a0003cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT409" , 0x11800a0003cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT410" , 0x11800a0003cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT411" , 0x11800a0003cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT412" , 0x11800a0003ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT413" , 0x11800a0003ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT414" , 0x11800a0003cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT415" , 0x11800a0003cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT416" , 0x11800a0003d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT417" , 0x11800a0003d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT418" , 0x11800a0003d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT419" , 0x11800a0003d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT420" , 0x11800a0003d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT421" , 0x11800a0003d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT422" , 0x11800a0003d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT423" , 0x11800a0003d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT424" , 0x11800a0003d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT425" , 0x11800a0003d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT426" , 0x11800a0003d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT427" , 0x11800a0003d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT428" , 0x11800a0003d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT429" , 0x11800a0003d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT430" , 0x11800a0003d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT431" , 0x11800a0003d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT432" , 0x11800a0003d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT433" , 0x11800a0003d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT434" , 0x11800a0003d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT435" , 0x11800a0003d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT436" , 0x11800a0003da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT437" , 0x11800a0003da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT438" , 0x11800a0003db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT439" , 0x11800a0003db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT440" , 0x11800a0003dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT441" , 0x11800a0003dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT442" , 0x11800a0003dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT443" , 0x11800a0003dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT444" , 0x11800a0003de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT445" , 0x11800a0003de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT446" , 0x11800a0003df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT447" , 0x11800a0003df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT448" , 0x11800a0003e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT449" , 0x11800a0003e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT450" , 0x11800a0003e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT451" , 0x11800a0003e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT452" , 0x11800a0003e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT453" , 0x11800a0003e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT454" , 0x11800a0003e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT455" , 0x11800a0003e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT456" , 0x11800a0003e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT457" , 0x11800a0003e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT458" , 0x11800a0003e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT459" , 0x11800a0003e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT460" , 0x11800a0003e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT461" , 0x11800a0003e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT462" , 0x11800a0003e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT463" , 0x11800a0003e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT464" , 0x11800a0003e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT465" , 0x11800a0003e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT466" , 0x11800a0003e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT467" , 0x11800a0003e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT468" , 0x11800a0003ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT469" , 0x11800a0003ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT470" , 0x11800a0003eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT471" , 0x11800a0003eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT472" , 0x11800a0003ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT473" , 0x11800a0003ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT474" , 0x11800a0003ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT475" , 0x11800a0003ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT476" , 0x11800a0003ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT477" , 0x11800a0003ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT478" , 0x11800a0003ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT479" , 0x11800a0003ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT480" , 0x11800a0003f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT481" , 0x11800a0003f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT482" , 0x11800a0003f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT483" , 0x11800a0003f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT484" , 0x11800a0003f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT485" , 0x11800a0003f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT486" , 0x11800a0003f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT487" , 0x11800a0003f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT488" , 0x11800a0003f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT489" , 0x11800a0003f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT490" , 0x11800a0003f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT491" , 0x11800a0003f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT492" , 0x11800a0003f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT493" , 0x11800a0003f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT494" , 0x11800a0003f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT495" , 0x11800a0003f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT496" , 0x11800a0003f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT497" , 0x11800a0003f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT498" , 0x11800a0003f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT499" , 0x11800a0003f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT500" , 0x11800a0003fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT501" , 0x11800a0003fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT502" , 0x11800a0003fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT503" , 0x11800a0003fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT504" , 0x11800a0003fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT505" , 0x11800a0003fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT506" , 0x11800a0003fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT507" , 0x11800a0003fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT508" , 0x11800a0003fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT509" , 0x11800a0003fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT510" , 0x11800a0003ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_BSEL_TBL_ENT511" , 0x11800a0003ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"PIP_CLKEN" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"PIP_DSA_SRC_GRP" , 0x11800a0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"PIP_DSA_VID_GRP" , 0x11800a0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_FRM_LEN_CHK1" , 0x11800a0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1023},
- {"PIP_PRI_TBL0" , 0x11800a0004000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL1" , 0x11800a0004008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL2" , 0x11800a0004010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL3" , 0x11800a0004018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL4" , 0x11800a0004020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL5" , 0x11800a0004028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL6" , 0x11800a0004030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL7" , 0x11800a0004038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL8" , 0x11800a0004040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL9" , 0x11800a0004048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL10" , 0x11800a0004050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL11" , 0x11800a0004058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL12" , 0x11800a0004060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL13" , 0x11800a0004068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL14" , 0x11800a0004070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL15" , 0x11800a0004078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL16" , 0x11800a0004080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL17" , 0x11800a0004088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL18" , 0x11800a0004090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL19" , 0x11800a0004098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL20" , 0x11800a00040a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL21" , 0x11800a00040a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL22" , 0x11800a00040b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL23" , 0x11800a00040b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL24" , 0x11800a00040c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL25" , 0x11800a00040c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL26" , 0x11800a00040d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL27" , 0x11800a00040d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL28" , 0x11800a00040e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL29" , 0x11800a00040e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL30" , 0x11800a00040f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL31" , 0x11800a00040f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL32" , 0x11800a0004100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL33" , 0x11800a0004108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL34" , 0x11800a0004110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL35" , 0x11800a0004118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL36" , 0x11800a0004120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL37" , 0x11800a0004128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL38" , 0x11800a0004130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL39" , 0x11800a0004138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL40" , 0x11800a0004140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL41" , 0x11800a0004148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL42" , 0x11800a0004150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL43" , 0x11800a0004158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL44" , 0x11800a0004160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL45" , 0x11800a0004168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL46" , 0x11800a0004170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL47" , 0x11800a0004178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL48" , 0x11800a0004180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL49" , 0x11800a0004188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL50" , 0x11800a0004190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL51" , 0x11800a0004198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL52" , 0x11800a00041a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL53" , 0x11800a00041a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL54" , 0x11800a00041b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL55" , 0x11800a00041b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL56" , 0x11800a00041c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL57" , 0x11800a00041c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL58" , 0x11800a00041d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL59" , 0x11800a00041d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL60" , 0x11800a00041e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL61" , 0x11800a00041e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL62" , 0x11800a00041f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL63" , 0x11800a00041f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL64" , 0x11800a0004200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL65" , 0x11800a0004208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL66" , 0x11800a0004210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL67" , 0x11800a0004218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL68" , 0x11800a0004220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL69" , 0x11800a0004228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL70" , 0x11800a0004230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL71" , 0x11800a0004238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL72" , 0x11800a0004240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL73" , 0x11800a0004248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL74" , 0x11800a0004250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL75" , 0x11800a0004258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL76" , 0x11800a0004260ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL77" , 0x11800a0004268ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL78" , 0x11800a0004270ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL79" , 0x11800a0004278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL80" , 0x11800a0004280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL81" , 0x11800a0004288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL82" , 0x11800a0004290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL83" , 0x11800a0004298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL84" , 0x11800a00042a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL85" , 0x11800a00042a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL86" , 0x11800a00042b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL87" , 0x11800a00042b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL88" , 0x11800a00042c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL89" , 0x11800a00042c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL90" , 0x11800a00042d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL91" , 0x11800a00042d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL92" , 0x11800a00042e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL93" , 0x11800a00042e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL94" , 0x11800a00042f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL95" , 0x11800a00042f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL96" , 0x11800a0004300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL97" , 0x11800a0004308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL98" , 0x11800a0004310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL99" , 0x11800a0004318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL100" , 0x11800a0004320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL101" , 0x11800a0004328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL102" , 0x11800a0004330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL103" , 0x11800a0004338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL104" , 0x11800a0004340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL105" , 0x11800a0004348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL106" , 0x11800a0004350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL107" , 0x11800a0004358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL108" , 0x11800a0004360ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL109" , 0x11800a0004368ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL110" , 0x11800a0004370ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL111" , 0x11800a0004378ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL112" , 0x11800a0004380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL113" , 0x11800a0004388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL114" , 0x11800a0004390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL115" , 0x11800a0004398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL116" , 0x11800a00043a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL117" , 0x11800a00043a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL118" , 0x11800a00043b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL119" , 0x11800a00043b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL120" , 0x11800a00043c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL121" , 0x11800a00043c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL122" , 0x11800a00043d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL123" , 0x11800a00043d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL124" , 0x11800a00043e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL125" , 0x11800a00043e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL126" , 0x11800a00043f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL127" , 0x11800a00043f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL128" , 0x11800a0004400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL129" , 0x11800a0004408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL130" , 0x11800a0004410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL131" , 0x11800a0004418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL132" , 0x11800a0004420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL133" , 0x11800a0004428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL134" , 0x11800a0004430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL135" , 0x11800a0004438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL136" , 0x11800a0004440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL137" , 0x11800a0004448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL138" , 0x11800a0004450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL139" , 0x11800a0004458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL140" , 0x11800a0004460ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL141" , 0x11800a0004468ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL142" , 0x11800a0004470ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL143" , 0x11800a0004478ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL144" , 0x11800a0004480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL145" , 0x11800a0004488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL146" , 0x11800a0004490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL147" , 0x11800a0004498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL148" , 0x11800a00044a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL149" , 0x11800a00044a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL150" , 0x11800a00044b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL151" , 0x11800a00044b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL152" , 0x11800a00044c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL153" , 0x11800a00044c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL154" , 0x11800a00044d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL155" , 0x11800a00044d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL156" , 0x11800a00044e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL157" , 0x11800a00044e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL158" , 0x11800a00044f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL159" , 0x11800a00044f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL160" , 0x11800a0004500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL161" , 0x11800a0004508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL162" , 0x11800a0004510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL163" , 0x11800a0004518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL164" , 0x11800a0004520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL165" , 0x11800a0004528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL166" , 0x11800a0004530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL167" , 0x11800a0004538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL168" , 0x11800a0004540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL169" , 0x11800a0004548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL170" , 0x11800a0004550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL171" , 0x11800a0004558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL172" , 0x11800a0004560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL173" , 0x11800a0004568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL174" , 0x11800a0004570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL175" , 0x11800a0004578ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL176" , 0x11800a0004580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL177" , 0x11800a0004588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL178" , 0x11800a0004590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL179" , 0x11800a0004598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL180" , 0x11800a00045a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL181" , 0x11800a00045a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL182" , 0x11800a00045b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL183" , 0x11800a00045b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL184" , 0x11800a00045c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL185" , 0x11800a00045c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL186" , 0x11800a00045d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL187" , 0x11800a00045d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL188" , 0x11800a00045e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL189" , 0x11800a00045e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL190" , 0x11800a00045f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL191" , 0x11800a00045f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL192" , 0x11800a0004600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL193" , 0x11800a0004608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL194" , 0x11800a0004610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL195" , 0x11800a0004618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL196" , 0x11800a0004620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL197" , 0x11800a0004628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL198" , 0x11800a0004630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL199" , 0x11800a0004638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL200" , 0x11800a0004640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL201" , 0x11800a0004648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL202" , 0x11800a0004650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL203" , 0x11800a0004658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL204" , 0x11800a0004660ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL205" , 0x11800a0004668ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL206" , 0x11800a0004670ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL207" , 0x11800a0004678ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL208" , 0x11800a0004680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL209" , 0x11800a0004688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL210" , 0x11800a0004690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL211" , 0x11800a0004698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL212" , 0x11800a00046a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL213" , 0x11800a00046a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL214" , 0x11800a00046b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL215" , 0x11800a00046b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL216" , 0x11800a00046c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL217" , 0x11800a00046c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL218" , 0x11800a00046d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL219" , 0x11800a00046d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL220" , 0x11800a00046e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL221" , 0x11800a00046e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL222" , 0x11800a00046f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL223" , 0x11800a00046f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL224" , 0x11800a0004700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL225" , 0x11800a0004708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL226" , 0x11800a0004710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL227" , 0x11800a0004718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL228" , 0x11800a0004720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL229" , 0x11800a0004728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL230" , 0x11800a0004730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL231" , 0x11800a0004738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL232" , 0x11800a0004740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL233" , 0x11800a0004748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL234" , 0x11800a0004750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL235" , 0x11800a0004758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL236" , 0x11800a0004760ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL237" , 0x11800a0004768ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL238" , 0x11800a0004770ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL239" , 0x11800a0004778ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL240" , 0x11800a0004780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL241" , 0x11800a0004788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL242" , 0x11800a0004790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL243" , 0x11800a0004798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL244" , 0x11800a00047a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL245" , 0x11800a00047a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL246" , 0x11800a00047b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL247" , 0x11800a00047b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL248" , 0x11800a00047c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL249" , 0x11800a00047c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL250" , 0x11800a00047d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL251" , 0x11800a00047d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL252" , 0x11800a00047e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL253" , 0x11800a00047e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL254" , 0x11800a00047f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRI_TBL255" , 0x11800a00047f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG2" , 0x11800a0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG3" , 0x11800a0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG4" , 0x11800a0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG5" , 0x11800a0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG6" , 0x11800a0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG7" , 0x11800a0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG8" , 0x11800a0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG9" , 0x11800a0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG10" , 0x11800a0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG11" , 0x11800a0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG12" , 0x11800a0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG13" , 0x11800a0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG14" , 0x11800a0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG15" , 0x11800a0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG16" , 0x11800a0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG17" , 0x11800a0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG18" , 0x11800a0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG19" , 0x11800a0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG20" , 0x11800a00002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG21" , 0x11800a00002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG22" , 0x11800a00002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG23" , 0x11800a00002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG24" , 0x11800a00002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG25" , 0x11800a00002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG26" , 0x11800a00002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG27" , 0x11800a00002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG28" , 0x11800a00002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG29" , 0x11800a00002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG30" , 0x11800a00002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG31" , 0x11800a00002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG40" , 0x11800a0000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG41" , 0x11800a0000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG42" , 0x11800a0000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG43" , 0x11800a0000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG44" , 0x11800a0000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG45" , 0x11800a0000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG46" , 0x11800a0000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG47" , 0x11800a0000378ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG48" , 0x11800a0000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG49" , 0x11800a0000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG50" , 0x11800a0000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG51" , 0x11800a0000398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG52" , 0x11800a00003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG53" , 0x11800a00003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG54" , 0x11800a00003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG55" , 0x11800a00003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG56" , 0x11800a00003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG57" , 0x11800a00003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG58" , 0x11800a00003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG59" , 0x11800a00003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG60" , 0x11800a00003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG61" , 0x11800a00003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG62" , 0x11800a00003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFG63" , 0x11800a00003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"PIP_PRT_CFGB0" , 0x11800a0008000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB1" , 0x11800a0008008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB2" , 0x11800a0008010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB3" , 0x11800a0008018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB4" , 0x11800a0008020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB5" , 0x11800a0008028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB6" , 0x11800a0008030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB7" , 0x11800a0008038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB8" , 0x11800a0008040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB9" , 0x11800a0008048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB10" , 0x11800a0008050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB11" , 0x11800a0008058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB12" , 0x11800a0008060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB13" , 0x11800a0008068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB14" , 0x11800a0008070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB15" , 0x11800a0008078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB16" , 0x11800a0008080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB17" , 0x11800a0008088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB18" , 0x11800a0008090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB19" , 0x11800a0008098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB20" , 0x11800a00080a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB21" , 0x11800a00080a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB22" , 0x11800a00080b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB23" , 0x11800a00080b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB24" , 0x11800a00080c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB25" , 0x11800a00080c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB26" , 0x11800a00080d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB27" , 0x11800a00080d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB28" , 0x11800a00080e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB29" , 0x11800a00080e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB30" , 0x11800a00080f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB31" , 0x11800a00080f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB32" , 0x11800a0008100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB33" , 0x11800a0008108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB34" , 0x11800a0008110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB35" , 0x11800a0008118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB36" , 0x11800a0008120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB37" , 0x11800a0008128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB38" , 0x11800a0008130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB39" , 0x11800a0008138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB40" , 0x11800a0008140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB41" , 0x11800a0008148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB42" , 0x11800a0008150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB43" , 0x11800a0008158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB44" , 0x11800a0008160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB45" , 0x11800a0008168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB46" , 0x11800a0008170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB47" , 0x11800a0008178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB48" , 0x11800a0008180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB49" , 0x11800a0008188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB50" , 0x11800a0008190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB51" , 0x11800a0008198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB52" , 0x11800a00081a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB53" , 0x11800a00081a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB54" , 0x11800a00081b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB55" , 0x11800a00081b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB56" , 0x11800a00081c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB57" , 0x11800a00081c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB58" , 0x11800a00081d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB59" , 0x11800a00081d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB60" , 0x11800a00081e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB61" , 0x11800a00081e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB62" , 0x11800a00081f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_CFGB63" , 0x11800a00081f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG2" , 0x11800a0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG3" , 0x11800a0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG4" , 0x11800a0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG5" , 0x11800a0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG6" , 0x11800a0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG7" , 0x11800a0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG8" , 0x11800a0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG9" , 0x11800a0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG10" , 0x11800a0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG11" , 0x11800a0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG12" , 0x11800a0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG13" , 0x11800a0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG14" , 0x11800a0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG15" , 0x11800a0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG16" , 0x11800a0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG17" , 0x11800a0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG18" , 0x11800a0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG19" , 0x11800a0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG20" , 0x11800a00004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG21" , 0x11800a00004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG22" , 0x11800a00004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG23" , 0x11800a00004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG24" , 0x11800a00004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG25" , 0x11800a00004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG26" , 0x11800a00004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG27" , 0x11800a00004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG28" , 0x11800a00004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG29" , 0x11800a00004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG30" , 0x11800a00004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG31" , 0x11800a00004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG40" , 0x11800a0000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG41" , 0x11800a0000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG42" , 0x11800a0000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG43" , 0x11800a0000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG44" , 0x11800a0000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG45" , 0x11800a0000568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG46" , 0x11800a0000570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG47" , 0x11800a0000578ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG48" , 0x11800a0000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG49" , 0x11800a0000588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG50" , 0x11800a0000590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG51" , 0x11800a0000598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG52" , 0x11800a00005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG53" , 0x11800a00005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG54" , 0x11800a00005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG55" , 0x11800a00005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG56" , 0x11800a00005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG57" , 0x11800a00005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG58" , 0x11800a00005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG59" , 0x11800a00005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG60" , 0x11800a00005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG61" , 0x11800a00005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG62" , 0x11800a00005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_PRT_TAG63" , 0x11800a00005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1029},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1030},
- {"PIP_STAT0_0" , 0x11800a0040000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_1" , 0x11800a0040080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_2" , 0x11800a0040100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_3" , 0x11800a0040180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_4" , 0x11800a0040200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_5" , 0x11800a0040280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_6" , 0x11800a0040300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_7" , 0x11800a0040380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_8" , 0x11800a0040400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_9" , 0x11800a0040480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_10" , 0x11800a0040500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_11" , 0x11800a0040580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_12" , 0x11800a0040600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_13" , 0x11800a0040680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_14" , 0x11800a0040700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_15" , 0x11800a0040780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_16" , 0x11800a0040800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_17" , 0x11800a0040880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_18" , 0x11800a0040900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_19" , 0x11800a0040980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_20" , 0x11800a0040a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_21" , 0x11800a0040a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_22" , 0x11800a0040b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_23" , 0x11800a0040b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_24" , 0x11800a0040c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_25" , 0x11800a0040c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_26" , 0x11800a0040d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_27" , 0x11800a0040d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_28" , 0x11800a0040e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_29" , 0x11800a0040e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_30" , 0x11800a0040f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_31" , 0x11800a0040f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_32" , 0x11800a0041000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_33" , 0x11800a0041080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_34" , 0x11800a0041100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_35" , 0x11800a0041180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_36" , 0x11800a0041200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_37" , 0x11800a0041280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_38" , 0x11800a0041300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_39" , 0x11800a0041380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_40" , 0x11800a0041400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_41" , 0x11800a0041480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_42" , 0x11800a0041500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_43" , 0x11800a0041580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_44" , 0x11800a0041600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_45" , 0x11800a0041680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_46" , 0x11800a0041700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_47" , 0x11800a0041780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_48" , 0x11800a0041800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_49" , 0x11800a0041880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_50" , 0x11800a0041900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_51" , 0x11800a0041980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_52" , 0x11800a0041a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_53" , 0x11800a0041a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_54" , 0x11800a0041b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_55" , 0x11800a0041b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_56" , 0x11800a0041c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_57" , 0x11800a0041c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_58" , 0x11800a0041d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_59" , 0x11800a0041d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_60" , 0x11800a0041e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_61" , 0x11800a0041e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_62" , 0x11800a0041f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT0_63" , 0x11800a0041f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 1031},
- {"PIP_STAT10_0" , 0x11800a0040050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_1" , 0x11800a00400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_2" , 0x11800a0040150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_3" , 0x11800a00401d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_4" , 0x11800a0040250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_5" , 0x11800a00402d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_6" , 0x11800a0040350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_7" , 0x11800a00403d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_8" , 0x11800a0040450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_9" , 0x11800a00404d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_10" , 0x11800a0040550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_11" , 0x11800a00405d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_12" , 0x11800a0040650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_13" , 0x11800a00406d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_14" , 0x11800a0040750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_15" , 0x11800a00407d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_16" , 0x11800a0040850ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_17" , 0x11800a00408d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_18" , 0x11800a0040950ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_19" , 0x11800a00409d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_20" , 0x11800a0040a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_21" , 0x11800a0040ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_22" , 0x11800a0040b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_23" , 0x11800a0040bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_24" , 0x11800a0040c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_25" , 0x11800a0040cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_26" , 0x11800a0040d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_27" , 0x11800a0040dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_28" , 0x11800a0040e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_29" , 0x11800a0040ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_30" , 0x11800a0040f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_31" , 0x11800a0040fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_32" , 0x11800a0041050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_33" , 0x11800a00410d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_34" , 0x11800a0041150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_35" , 0x11800a00411d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_36" , 0x11800a0041250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_37" , 0x11800a00412d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_38" , 0x11800a0041350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_39" , 0x11800a00413d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_40" , 0x11800a0041450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_41" , 0x11800a00414d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_42" , 0x11800a0041550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_43" , 0x11800a00415d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_44" , 0x11800a0041650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_45" , 0x11800a00416d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_46" , 0x11800a0041750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_47" , 0x11800a00417d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_48" , 0x11800a0041850ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_49" , 0x11800a00418d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_50" , 0x11800a0041950ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_51" , 0x11800a00419d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_52" , 0x11800a0041a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_53" , 0x11800a0041ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_54" , 0x11800a0041b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_55" , 0x11800a0041bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_56" , 0x11800a0041c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_57" , 0x11800a0041cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_58" , 0x11800a0041d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_59" , 0x11800a0041dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_60" , 0x11800a0041e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_61" , 0x11800a0041ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_62" , 0x11800a0041f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT10_63" , 0x11800a0041fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1032},
- {"PIP_STAT11_0" , 0x11800a0040058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_1" , 0x11800a00400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_2" , 0x11800a0040158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_3" , 0x11800a00401d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_4" , 0x11800a0040258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_5" , 0x11800a00402d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_6" , 0x11800a0040358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_7" , 0x11800a00403d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_8" , 0x11800a0040458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_9" , 0x11800a00404d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_10" , 0x11800a0040558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_11" , 0x11800a00405d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_12" , 0x11800a0040658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_13" , 0x11800a00406d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_14" , 0x11800a0040758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_15" , 0x11800a00407d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_16" , 0x11800a0040858ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_17" , 0x11800a00408d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_18" , 0x11800a0040958ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_19" , 0x11800a00409d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_20" , 0x11800a0040a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_21" , 0x11800a0040ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_22" , 0x11800a0040b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_23" , 0x11800a0040bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_24" , 0x11800a0040c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_25" , 0x11800a0040cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_26" , 0x11800a0040d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_27" , 0x11800a0040dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_28" , 0x11800a0040e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_29" , 0x11800a0040ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_30" , 0x11800a0040f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_31" , 0x11800a0040fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_32" , 0x11800a0041058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_33" , 0x11800a00410d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_34" , 0x11800a0041158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_35" , 0x11800a00411d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_36" , 0x11800a0041258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_37" , 0x11800a00412d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_38" , 0x11800a0041358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_39" , 0x11800a00413d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_40" , 0x11800a0041458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_41" , 0x11800a00414d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_42" , 0x11800a0041558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_43" , 0x11800a00415d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_44" , 0x11800a0041658ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_45" , 0x11800a00416d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_46" , 0x11800a0041758ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_47" , 0x11800a00417d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_48" , 0x11800a0041858ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_49" , 0x11800a00418d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_50" , 0x11800a0041958ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_51" , 0x11800a00419d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_52" , 0x11800a0041a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_53" , 0x11800a0041ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_54" , 0x11800a0041b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_55" , 0x11800a0041bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_56" , 0x11800a0041c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_57" , 0x11800a0041cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_58" , 0x11800a0041d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_59" , 0x11800a0041dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_60" , 0x11800a0041e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_61" , 0x11800a0041ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_62" , 0x11800a0041f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT11_63" , 0x11800a0041fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1033},
- {"PIP_STAT1_0" , 0x11800a0040008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_1" , 0x11800a0040088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_2" , 0x11800a0040108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_3" , 0x11800a0040188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_4" , 0x11800a0040208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_5" , 0x11800a0040288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_6" , 0x11800a0040308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_7" , 0x11800a0040388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_8" , 0x11800a0040408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_9" , 0x11800a0040488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_10" , 0x11800a0040508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_11" , 0x11800a0040588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_12" , 0x11800a0040608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_13" , 0x11800a0040688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_14" , 0x11800a0040708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_15" , 0x11800a0040788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_16" , 0x11800a0040808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_17" , 0x11800a0040888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_18" , 0x11800a0040908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_19" , 0x11800a0040988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_20" , 0x11800a0040a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_21" , 0x11800a0040a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_22" , 0x11800a0040b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_23" , 0x11800a0040b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_24" , 0x11800a0040c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_25" , 0x11800a0040c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_26" , 0x11800a0040d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_27" , 0x11800a0040d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_28" , 0x11800a0040e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_29" , 0x11800a0040e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_30" , 0x11800a0040f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_31" , 0x11800a0040f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_32" , 0x11800a0041008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_33" , 0x11800a0041088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_34" , 0x11800a0041108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_35" , 0x11800a0041188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_36" , 0x11800a0041208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_37" , 0x11800a0041288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_38" , 0x11800a0041308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_39" , 0x11800a0041388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_40" , 0x11800a0041408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_41" , 0x11800a0041488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_42" , 0x11800a0041508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_43" , 0x11800a0041588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_44" , 0x11800a0041608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_45" , 0x11800a0041688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_46" , 0x11800a0041708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_47" , 0x11800a0041788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_48" , 0x11800a0041808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_49" , 0x11800a0041888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_50" , 0x11800a0041908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_51" , 0x11800a0041988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_52" , 0x11800a0041a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_53" , 0x11800a0041a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_54" , 0x11800a0041b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_55" , 0x11800a0041b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_56" , 0x11800a0041c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_57" , 0x11800a0041c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_58" , 0x11800a0041d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_59" , 0x11800a0041d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_60" , 0x11800a0041e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_61" , 0x11800a0041e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_62" , 0x11800a0041f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT1_63" , 0x11800a0041f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 1034},
- {"PIP_STAT2_0" , 0x11800a0040010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_1" , 0x11800a0040090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_2" , 0x11800a0040110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_3" , 0x11800a0040190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_4" , 0x11800a0040210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_5" , 0x11800a0040290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_6" , 0x11800a0040310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_7" , 0x11800a0040390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_8" , 0x11800a0040410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_9" , 0x11800a0040490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_10" , 0x11800a0040510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_11" , 0x11800a0040590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_12" , 0x11800a0040610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_13" , 0x11800a0040690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_14" , 0x11800a0040710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_15" , 0x11800a0040790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_16" , 0x11800a0040810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_17" , 0x11800a0040890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_18" , 0x11800a0040910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_19" , 0x11800a0040990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_20" , 0x11800a0040a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_21" , 0x11800a0040a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_22" , 0x11800a0040b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_23" , 0x11800a0040b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_24" , 0x11800a0040c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_25" , 0x11800a0040c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_26" , 0x11800a0040d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_27" , 0x11800a0040d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_28" , 0x11800a0040e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_29" , 0x11800a0040e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_30" , 0x11800a0040f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_31" , 0x11800a0040f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_32" , 0x11800a0041010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_33" , 0x11800a0041090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_34" , 0x11800a0041110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_35" , 0x11800a0041190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_36" , 0x11800a0041210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_37" , 0x11800a0041290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_38" , 0x11800a0041310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_39" , 0x11800a0041390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_40" , 0x11800a0041410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_41" , 0x11800a0041490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_42" , 0x11800a0041510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_43" , 0x11800a0041590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_44" , 0x11800a0041610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_45" , 0x11800a0041690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_46" , 0x11800a0041710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_47" , 0x11800a0041790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_48" , 0x11800a0041810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_49" , 0x11800a0041890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_50" , 0x11800a0041910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_51" , 0x11800a0041990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_52" , 0x11800a0041a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_53" , 0x11800a0041a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_54" , 0x11800a0041b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_55" , 0x11800a0041b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_56" , 0x11800a0041c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_57" , 0x11800a0041c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_58" , 0x11800a0041d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_59" , 0x11800a0041d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_60" , 0x11800a0041e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_61" , 0x11800a0041e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_62" , 0x11800a0041f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT2_63" , 0x11800a0041f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 1035},
- {"PIP_STAT3_0" , 0x11800a0040018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_1" , 0x11800a0040098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_2" , 0x11800a0040118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_3" , 0x11800a0040198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_4" , 0x11800a0040218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_5" , 0x11800a0040298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_6" , 0x11800a0040318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_7" , 0x11800a0040398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_8" , 0x11800a0040418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_9" , 0x11800a0040498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_10" , 0x11800a0040518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_11" , 0x11800a0040598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_12" , 0x11800a0040618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_13" , 0x11800a0040698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_14" , 0x11800a0040718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_15" , 0x11800a0040798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_16" , 0x11800a0040818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_17" , 0x11800a0040898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_18" , 0x11800a0040918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_19" , 0x11800a0040998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_20" , 0x11800a0040a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_21" , 0x11800a0040a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_22" , 0x11800a0040b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_23" , 0x11800a0040b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_24" , 0x11800a0040c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_25" , 0x11800a0040c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_26" , 0x11800a0040d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_27" , 0x11800a0040d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_28" , 0x11800a0040e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_29" , 0x11800a0040e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_30" , 0x11800a0040f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_31" , 0x11800a0040f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_32" , 0x11800a0041018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_33" , 0x11800a0041098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_34" , 0x11800a0041118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_35" , 0x11800a0041198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_36" , 0x11800a0041218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_37" , 0x11800a0041298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_38" , 0x11800a0041318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_39" , 0x11800a0041398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_40" , 0x11800a0041418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_41" , 0x11800a0041498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_42" , 0x11800a0041518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_43" , 0x11800a0041598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_44" , 0x11800a0041618ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_45" , 0x11800a0041698ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_46" , 0x11800a0041718ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_47" , 0x11800a0041798ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_48" , 0x11800a0041818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_49" , 0x11800a0041898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_50" , 0x11800a0041918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_51" , 0x11800a0041998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_52" , 0x11800a0041a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_53" , 0x11800a0041a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_54" , 0x11800a0041b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_55" , 0x11800a0041b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_56" , 0x11800a0041c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_57" , 0x11800a0041c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_58" , 0x11800a0041d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_59" , 0x11800a0041d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_60" , 0x11800a0041e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_61" , 0x11800a0041e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_62" , 0x11800a0041f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT3_63" , 0x11800a0041f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 1036},
- {"PIP_STAT4_0" , 0x11800a0040020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_1" , 0x11800a00400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_2" , 0x11800a0040120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_3" , 0x11800a00401a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_4" , 0x11800a0040220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_5" , 0x11800a00402a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_6" , 0x11800a0040320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_7" , 0x11800a00403a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_8" , 0x11800a0040420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_9" , 0x11800a00404a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_10" , 0x11800a0040520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_11" , 0x11800a00405a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_12" , 0x11800a0040620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_13" , 0x11800a00406a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_14" , 0x11800a0040720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_15" , 0x11800a00407a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_16" , 0x11800a0040820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_17" , 0x11800a00408a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_18" , 0x11800a0040920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_19" , 0x11800a00409a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_20" , 0x11800a0040a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_21" , 0x11800a0040aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_22" , 0x11800a0040b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_23" , 0x11800a0040ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_24" , 0x11800a0040c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_25" , 0x11800a0040ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_26" , 0x11800a0040d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_27" , 0x11800a0040da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_28" , 0x11800a0040e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_29" , 0x11800a0040ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_30" , 0x11800a0040f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_31" , 0x11800a0040fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_32" , 0x11800a0041020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_33" , 0x11800a00410a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_34" , 0x11800a0041120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_35" , 0x11800a00411a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_36" , 0x11800a0041220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_37" , 0x11800a00412a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_38" , 0x11800a0041320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_39" , 0x11800a00413a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_40" , 0x11800a0041420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_41" , 0x11800a00414a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_42" , 0x11800a0041520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_43" , 0x11800a00415a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_44" , 0x11800a0041620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_45" , 0x11800a00416a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_46" , 0x11800a0041720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_47" , 0x11800a00417a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_48" , 0x11800a0041820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_49" , 0x11800a00418a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_50" , 0x11800a0041920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_51" , 0x11800a00419a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_52" , 0x11800a0041a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_53" , 0x11800a0041aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_54" , 0x11800a0041b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_55" , 0x11800a0041ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_56" , 0x11800a0041c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_57" , 0x11800a0041ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_58" , 0x11800a0041d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_59" , 0x11800a0041da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_60" , 0x11800a0041e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_61" , 0x11800a0041ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_62" , 0x11800a0041f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT4_63" , 0x11800a0041fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1037},
- {"PIP_STAT5_0" , 0x11800a0040028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_1" , 0x11800a00400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_2" , 0x11800a0040128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_3" , 0x11800a00401a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_4" , 0x11800a0040228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_5" , 0x11800a00402a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_6" , 0x11800a0040328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_7" , 0x11800a00403a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_8" , 0x11800a0040428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_9" , 0x11800a00404a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_10" , 0x11800a0040528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_11" , 0x11800a00405a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_12" , 0x11800a0040628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_13" , 0x11800a00406a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_14" , 0x11800a0040728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_15" , 0x11800a00407a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_16" , 0x11800a0040828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_17" , 0x11800a00408a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_18" , 0x11800a0040928ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_19" , 0x11800a00409a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_20" , 0x11800a0040a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_21" , 0x11800a0040aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_22" , 0x11800a0040b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_23" , 0x11800a0040ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_24" , 0x11800a0040c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_25" , 0x11800a0040ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_26" , 0x11800a0040d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_27" , 0x11800a0040da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_28" , 0x11800a0040e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_29" , 0x11800a0040ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_30" , 0x11800a0040f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_31" , 0x11800a0040fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_32" , 0x11800a0041028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_33" , 0x11800a00410a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_34" , 0x11800a0041128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_35" , 0x11800a00411a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_36" , 0x11800a0041228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_37" , 0x11800a00412a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_38" , 0x11800a0041328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_39" , 0x11800a00413a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_40" , 0x11800a0041428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_41" , 0x11800a00414a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_42" , 0x11800a0041528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_43" , 0x11800a00415a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_44" , 0x11800a0041628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_45" , 0x11800a00416a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_46" , 0x11800a0041728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_47" , 0x11800a00417a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_48" , 0x11800a0041828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_49" , 0x11800a00418a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_50" , 0x11800a0041928ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_51" , 0x11800a00419a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_52" , 0x11800a0041a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_53" , 0x11800a0041aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_54" , 0x11800a0041b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_55" , 0x11800a0041ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_56" , 0x11800a0041c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_57" , 0x11800a0041ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_58" , 0x11800a0041d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_59" , 0x11800a0041da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_60" , 0x11800a0041e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_61" , 0x11800a0041ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_62" , 0x11800a0041f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT5_63" , 0x11800a0041fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1038},
- {"PIP_STAT6_0" , 0x11800a0040030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_1" , 0x11800a00400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_2" , 0x11800a0040130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_3" , 0x11800a00401b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_4" , 0x11800a0040230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_5" , 0x11800a00402b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_6" , 0x11800a0040330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_7" , 0x11800a00403b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_8" , 0x11800a0040430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_9" , 0x11800a00404b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_10" , 0x11800a0040530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_11" , 0x11800a00405b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_12" , 0x11800a0040630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_13" , 0x11800a00406b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_14" , 0x11800a0040730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_15" , 0x11800a00407b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_16" , 0x11800a0040830ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_17" , 0x11800a00408b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_18" , 0x11800a0040930ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_19" , 0x11800a00409b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_20" , 0x11800a0040a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_21" , 0x11800a0040ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_22" , 0x11800a0040b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_23" , 0x11800a0040bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_24" , 0x11800a0040c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_25" , 0x11800a0040cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_26" , 0x11800a0040d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_27" , 0x11800a0040db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_28" , 0x11800a0040e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_29" , 0x11800a0040eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_30" , 0x11800a0040f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_31" , 0x11800a0040fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_32" , 0x11800a0041030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_33" , 0x11800a00410b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_34" , 0x11800a0041130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_35" , 0x11800a00411b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_36" , 0x11800a0041230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_37" , 0x11800a00412b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_38" , 0x11800a0041330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_39" , 0x11800a00413b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_40" , 0x11800a0041430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_41" , 0x11800a00414b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_42" , 0x11800a0041530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_43" , 0x11800a00415b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_44" , 0x11800a0041630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_45" , 0x11800a00416b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_46" , 0x11800a0041730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_47" , 0x11800a00417b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_48" , 0x11800a0041830ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_49" , 0x11800a00418b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_50" , 0x11800a0041930ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_51" , 0x11800a00419b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_52" , 0x11800a0041a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_53" , 0x11800a0041ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_54" , 0x11800a0041b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_55" , 0x11800a0041bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_56" , 0x11800a0041c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_57" , 0x11800a0041cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_58" , 0x11800a0041d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_59" , 0x11800a0041db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_60" , 0x11800a0041e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_61" , 0x11800a0041eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_62" , 0x11800a0041f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT6_63" , 0x11800a0041fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1039},
- {"PIP_STAT7_0" , 0x11800a0040038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_1" , 0x11800a00400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_2" , 0x11800a0040138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_3" , 0x11800a00401b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_4" , 0x11800a0040238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_5" , 0x11800a00402b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_6" , 0x11800a0040338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_7" , 0x11800a00403b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_8" , 0x11800a0040438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_9" , 0x11800a00404b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_10" , 0x11800a0040538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_11" , 0x11800a00405b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_12" , 0x11800a0040638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_13" , 0x11800a00406b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_14" , 0x11800a0040738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_15" , 0x11800a00407b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_16" , 0x11800a0040838ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_17" , 0x11800a00408b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_18" , 0x11800a0040938ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_19" , 0x11800a00409b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_20" , 0x11800a0040a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_21" , 0x11800a0040ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_22" , 0x11800a0040b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_23" , 0x11800a0040bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_24" , 0x11800a0040c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_25" , 0x11800a0040cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_26" , 0x11800a0040d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_27" , 0x11800a0040db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_28" , 0x11800a0040e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_29" , 0x11800a0040eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_30" , 0x11800a0040f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_31" , 0x11800a0040fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_32" , 0x11800a0041038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_33" , 0x11800a00410b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_34" , 0x11800a0041138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_35" , 0x11800a00411b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_36" , 0x11800a0041238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_37" , 0x11800a00412b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_38" , 0x11800a0041338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_39" , 0x11800a00413b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_40" , 0x11800a0041438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_41" , 0x11800a00414b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_42" , 0x11800a0041538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_43" , 0x11800a00415b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_44" , 0x11800a0041638ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_45" , 0x11800a00416b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_46" , 0x11800a0041738ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_47" , 0x11800a00417b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_48" , 0x11800a0041838ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_49" , 0x11800a00418b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_50" , 0x11800a0041938ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_51" , 0x11800a00419b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_52" , 0x11800a0041a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_53" , 0x11800a0041ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_54" , 0x11800a0041b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_55" , 0x11800a0041bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_56" , 0x11800a0041c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_57" , 0x11800a0041cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_58" , 0x11800a0041d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_59" , 0x11800a0041db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_60" , 0x11800a0041e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_61" , 0x11800a0041eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_62" , 0x11800a0041f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT7_63" , 0x11800a0041fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1040},
- {"PIP_STAT8_0" , 0x11800a0040040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_1" , 0x11800a00400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_2" , 0x11800a0040140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_3" , 0x11800a00401c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_4" , 0x11800a0040240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_5" , 0x11800a00402c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_6" , 0x11800a0040340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_7" , 0x11800a00403c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_8" , 0x11800a0040440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_9" , 0x11800a00404c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_10" , 0x11800a0040540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_11" , 0x11800a00405c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_12" , 0x11800a0040640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_13" , 0x11800a00406c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_14" , 0x11800a0040740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_15" , 0x11800a00407c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_16" , 0x11800a0040840ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_17" , 0x11800a00408c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_18" , 0x11800a0040940ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_19" , 0x11800a00409c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_20" , 0x11800a0040a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_21" , 0x11800a0040ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_22" , 0x11800a0040b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_23" , 0x11800a0040bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_24" , 0x11800a0040c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_25" , 0x11800a0040cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_26" , 0x11800a0040d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_27" , 0x11800a0040dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_28" , 0x11800a0040e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_29" , 0x11800a0040ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_30" , 0x11800a0040f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_31" , 0x11800a0040fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_32" , 0x11800a0041040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_33" , 0x11800a00410c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_34" , 0x11800a0041140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_35" , 0x11800a00411c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_36" , 0x11800a0041240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_37" , 0x11800a00412c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_38" , 0x11800a0041340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_39" , 0x11800a00413c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_40" , 0x11800a0041440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_41" , 0x11800a00414c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_42" , 0x11800a0041540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_43" , 0x11800a00415c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_44" , 0x11800a0041640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_45" , 0x11800a00416c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_46" , 0x11800a0041740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_47" , 0x11800a00417c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_48" , 0x11800a0041840ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_49" , 0x11800a00418c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_50" , 0x11800a0041940ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_51" , 0x11800a00419c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_52" , 0x11800a0041a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_53" , 0x11800a0041ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_54" , 0x11800a0041b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_55" , 0x11800a0041bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_56" , 0x11800a0041c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_57" , 0x11800a0041cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_58" , 0x11800a0041d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_59" , 0x11800a0041dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_60" , 0x11800a0041e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_61" , 0x11800a0041ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_62" , 0x11800a0041f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT8_63" , 0x11800a0041fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1041},
- {"PIP_STAT9_0" , 0x11800a0040048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_1" , 0x11800a00400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_2" , 0x11800a0040148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_3" , 0x11800a00401c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_4" , 0x11800a0040248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_5" , 0x11800a00402c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_6" , 0x11800a0040348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_7" , 0x11800a00403c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_8" , 0x11800a0040448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_9" , 0x11800a00404c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_10" , 0x11800a0040548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_11" , 0x11800a00405c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_12" , 0x11800a0040648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_13" , 0x11800a00406c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_14" , 0x11800a0040748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_15" , 0x11800a00407c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_16" , 0x11800a0040848ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_17" , 0x11800a00408c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_18" , 0x11800a0040948ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_19" , 0x11800a00409c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_20" , 0x11800a0040a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_21" , 0x11800a0040ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_22" , 0x11800a0040b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_23" , 0x11800a0040bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_24" , 0x11800a0040c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_25" , 0x11800a0040cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_26" , 0x11800a0040d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_27" , 0x11800a0040dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_28" , 0x11800a0040e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_29" , 0x11800a0040ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_30" , 0x11800a0040f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_31" , 0x11800a0040fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_32" , 0x11800a0041048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_33" , 0x11800a00410c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_34" , 0x11800a0041148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_35" , 0x11800a00411c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_36" , 0x11800a0041248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_37" , 0x11800a00412c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_38" , 0x11800a0041348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_39" , 0x11800a00413c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_40" , 0x11800a0041448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_41" , 0x11800a00414c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_42" , 0x11800a0041548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_43" , 0x11800a00415c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_44" , 0x11800a0041648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_45" , 0x11800a00416c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_46" , 0x11800a0041748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_47" , 0x11800a00417c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_48" , 0x11800a0041848ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_49" , 0x11800a00418c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_50" , 0x11800a0041948ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_51" , 0x11800a00419c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_52" , 0x11800a0041a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_53" , 0x11800a0041ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_54" , 0x11800a0041b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_55" , 0x11800a0041bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_56" , 0x11800a0041c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_57" , 0x11800a0041cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_58" , 0x11800a0041d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_59" , 0x11800a0041dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_60" , 0x11800a0041e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_61" , 0x11800a0041ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_62" , 0x11800a0041f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT9_63" , 0x11800a0041fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1042},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1043},
- {"PIP_STAT_INB_ERRS_PKND0" , 0x11800a0020010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND1" , 0x11800a0020030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND2" , 0x11800a0020050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND3" , 0x11800a0020070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND4" , 0x11800a0020090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND5" , 0x11800a00200b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND6" , 0x11800a00200d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND7" , 0x11800a00200f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND8" , 0x11800a0020110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND9" , 0x11800a0020130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND10" , 0x11800a0020150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND11" , 0x11800a0020170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND12" , 0x11800a0020190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND13" , 0x11800a00201b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND14" , 0x11800a00201d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND15" , 0x11800a00201f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND16" , 0x11800a0020210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND17" , 0x11800a0020230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND18" , 0x11800a0020250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND19" , 0x11800a0020270ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND20" , 0x11800a0020290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND21" , 0x11800a00202b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND22" , 0x11800a00202d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND23" , 0x11800a00202f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND24" , 0x11800a0020310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND25" , 0x11800a0020330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND26" , 0x11800a0020350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND27" , 0x11800a0020370ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND28" , 0x11800a0020390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND29" , 0x11800a00203b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND30" , 0x11800a00203d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND31" , 0x11800a00203f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND32" , 0x11800a0020410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND33" , 0x11800a0020430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND34" , 0x11800a0020450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND35" , 0x11800a0020470ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND36" , 0x11800a0020490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND37" , 0x11800a00204b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND38" , 0x11800a00204d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND39" , 0x11800a00204f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND40" , 0x11800a0020510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND41" , 0x11800a0020530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND42" , 0x11800a0020550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND43" , 0x11800a0020570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND44" , 0x11800a0020590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND45" , 0x11800a00205b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND46" , 0x11800a00205d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND47" , 0x11800a00205f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND48" , 0x11800a0020610ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND49" , 0x11800a0020630ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND50" , 0x11800a0020650ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND51" , 0x11800a0020670ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND52" , 0x11800a0020690ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND53" , 0x11800a00206b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND54" , 0x11800a00206d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND55" , 0x11800a00206f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND56" , 0x11800a0020710ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND57" , 0x11800a0020730ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND58" , 0x11800a0020750ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND59" , 0x11800a0020770ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND60" , 0x11800a0020790ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND61" , 0x11800a00207b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND62" , 0x11800a00207d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_ERRS_PKND63" , 0x11800a00207f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1044},
- {"PIP_STAT_INB_OCTS_PKND0" , 0x11800a0020008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND1" , 0x11800a0020028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND2" , 0x11800a0020048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND3" , 0x11800a0020068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND4" , 0x11800a0020088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND5" , 0x11800a00200a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND6" , 0x11800a00200c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND7" , 0x11800a00200e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND8" , 0x11800a0020108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND9" , 0x11800a0020128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND10" , 0x11800a0020148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND11" , 0x11800a0020168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND12" , 0x11800a0020188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND13" , 0x11800a00201a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND14" , 0x11800a00201c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND15" , 0x11800a00201e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND16" , 0x11800a0020208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND17" , 0x11800a0020228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND18" , 0x11800a0020248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND19" , 0x11800a0020268ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND20" , 0x11800a0020288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND21" , 0x11800a00202a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND22" , 0x11800a00202c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND23" , 0x11800a00202e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND24" , 0x11800a0020308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND25" , 0x11800a0020328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND26" , 0x11800a0020348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND27" , 0x11800a0020368ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND28" , 0x11800a0020388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND29" , 0x11800a00203a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND30" , 0x11800a00203c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND31" , 0x11800a00203e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND32" , 0x11800a0020408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND33" , 0x11800a0020428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND34" , 0x11800a0020448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND35" , 0x11800a0020468ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND36" , 0x11800a0020488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND37" , 0x11800a00204a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND38" , 0x11800a00204c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND39" , 0x11800a00204e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND40" , 0x11800a0020508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND41" , 0x11800a0020528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND42" , 0x11800a0020548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND43" , 0x11800a0020568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND44" , 0x11800a0020588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND45" , 0x11800a00205a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND46" , 0x11800a00205c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND47" , 0x11800a00205e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND48" , 0x11800a0020608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND49" , 0x11800a0020628ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND50" , 0x11800a0020648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND51" , 0x11800a0020668ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND52" , 0x11800a0020688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND53" , 0x11800a00206a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND54" , 0x11800a00206c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND55" , 0x11800a00206e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND56" , 0x11800a0020708ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND57" , 0x11800a0020728ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND58" , 0x11800a0020748ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND59" , 0x11800a0020768ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND60" , 0x11800a0020788ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND61" , 0x11800a00207a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND62" , 0x11800a00207c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_OCTS_PKND63" , 0x11800a00207e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1045},
- {"PIP_STAT_INB_PKTS_PKND0" , 0x11800a0020000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND1" , 0x11800a0020020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND2" , 0x11800a0020040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND3" , 0x11800a0020060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND4" , 0x11800a0020080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND5" , 0x11800a00200a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND6" , 0x11800a00200c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND7" , 0x11800a00200e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND8" , 0x11800a0020100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND9" , 0x11800a0020120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND10" , 0x11800a0020140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND11" , 0x11800a0020160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND12" , 0x11800a0020180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND13" , 0x11800a00201a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND14" , 0x11800a00201c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND15" , 0x11800a00201e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND16" , 0x11800a0020200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND17" , 0x11800a0020220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND18" , 0x11800a0020240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND19" , 0x11800a0020260ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND20" , 0x11800a0020280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND21" , 0x11800a00202a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND22" , 0x11800a00202c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND23" , 0x11800a00202e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND24" , 0x11800a0020300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND25" , 0x11800a0020320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND26" , 0x11800a0020340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND27" , 0x11800a0020360ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND28" , 0x11800a0020380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND29" , 0x11800a00203a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND30" , 0x11800a00203c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND31" , 0x11800a00203e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND32" , 0x11800a0020400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND33" , 0x11800a0020420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND34" , 0x11800a0020440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND35" , 0x11800a0020460ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND36" , 0x11800a0020480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND37" , 0x11800a00204a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND38" , 0x11800a00204c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND39" , 0x11800a00204e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND40" , 0x11800a0020500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND41" , 0x11800a0020520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND42" , 0x11800a0020540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND43" , 0x11800a0020560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND44" , 0x11800a0020580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND45" , 0x11800a00205a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND46" , 0x11800a00205c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND47" , 0x11800a00205e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND48" , 0x11800a0020600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND49" , 0x11800a0020620ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND50" , 0x11800a0020640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND51" , 0x11800a0020660ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND52" , 0x11800a0020680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND53" , 0x11800a00206a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND54" , 0x11800a00206c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND55" , 0x11800a00206e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND56" , 0x11800a0020700ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND57" , 0x11800a0020720ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND58" , 0x11800a0020740ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND59" , 0x11800a0020760ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND60" , 0x11800a0020780ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND61" , 0x11800a00207a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND62" , 0x11800a00207c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_STAT_INB_PKTS_PKND63" , 0x11800a00207e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1046},
- {"PIP_SUB_PKIND_FCS0" , 0x11800a0080000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1047},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1048},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1049},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1050},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1051},
- {"PIP_VLAN_ETYPES0" , 0x11800a00001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1052},
- {"PIP_VLAN_ETYPES1" , 0x11800a00001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1052},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1053},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1054},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1055},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1056},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1057},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1058},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1059},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1060},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1061},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1062},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1063},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1064},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1065},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1066},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1067},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1068},
- {"PKO_MEM_IPORT_PTRS" , 0x1180050001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1069},
- {"PKO_MEM_IPORT_QOS" , 0x1180050001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1070},
- {"PKO_MEM_IQUEUE_PTRS" , 0x1180050001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1071},
- {"PKO_MEM_IQUEUE_QOS" , 0x1180050001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1072},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1073},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1074},
- {"PKO_MEM_THROTTLE_INT" , 0x1180050001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1075},
- {"PKO_MEM_THROTTLE_PIPE" , 0x1180050001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1076},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1077},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1078},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1079},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1080},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1081},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1082},
- {"PKO_REG_DEBUG4" , 0x11800500000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1083},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1084},
- {"PKO_REG_ENGINE_INFLIGHT1" , 0x1180050000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1085},
- {"PKO_REG_ENGINE_STORAGE0" , 0x1180050000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1086},
- {"PKO_REG_ENGINE_STORAGE1" , 0x1180050000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1086},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1087},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1088},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1089},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1090},
- {"PKO_REG_LOOPBACK_BPID" , 0x1180050000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1091},
- {"PKO_REG_LOOPBACK_PKIND" , 0x1180050000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1092},
- {"PKO_REG_MIN_PKT" , 0x1180050000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1093},
- {"PKO_REG_PREEMPT" , 0x1180050000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1094},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1095},
- {"PKO_REG_QUEUE_PREEMPT" , 0x1180050000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1096},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1097},
- {"PKO_REG_THROTTLE" , 0x1180050000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1098},
- {"PKO_REG_TIMESTAMP" , 0x1180050000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1099},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1100},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1101},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1102},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1103},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1104},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1105},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1106},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1107},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1108},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1109},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1110},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1111},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1112},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1113},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1114},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1115},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1116},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1117},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1118},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1119},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1120},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1121},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1122},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1123},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1124},
- {"RNM_EER_DBG" , 0x1180040000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1125},
- {"RNM_EER_KEY" , 0x1180040000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1126},
- {"RNM_SERIAL_NUM" , 0x1180040000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1127},
- {"SLI_BIST_STATUS" , 0x11f0000010580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1128},
- {"SLI_CTL_PORT0" , 0x11f0000010050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1129},
- {"SLI_CTL_PORT1" , 0x11f0000010060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1129},
- {"SLI_CTL_STATUS" , 0x11f0000010570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1130},
- {"SLI_DATA_OUT_CNT" , 0x11f00000105f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1131},
- {"SLI_DBG_DATA" , 0x11f0000010310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1132},
- {"SLI_DBG_SELECT" , 0x11f0000010300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1133},
- {"SLI_DMA0_CNT" , 0x11f0000010400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1134},
- {"SLI_DMA1_CNT" , 0x11f0000010410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1134},
- {"SLI_DMA0_INT_LEVEL" , 0x11f00000103e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1135},
- {"SLI_DMA1_INT_LEVEL" , 0x11f00000103f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1135},
- {"SLI_DMA0_TIM" , 0x11f0000010420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1136},
- {"SLI_DMA1_TIM" , 0x11f0000010430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1136},
- {"SLI_INT_ENB_CIU" , 0x11f0000013cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1137},
- {"SLI_INT_ENB_PORT0" , 0x11f0000010340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1138},
- {"SLI_INT_ENB_PORT1" , 0x11f0000010350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1138},
- {"SLI_INT_SUM" , 0x11f0000010330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1139},
- {"SLI_LAST_WIN_RDATA0" , 0x11f0000010600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1140},
- {"SLI_LAST_WIN_RDATA1" , 0x11f0000010610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1141},
- {"SLI_MAC_CREDIT_CNT" , 0x11f0000013d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1142},
- {"SLI_MAC_NUMBER" , 0x3e00ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1143},
- {"SLI_MEM_ACCESS_CTL" , 0x11f00000102f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1144},
- {"SLI_MEM_ACCESS_SUBID12" , 0x11f00000100e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID13" , 0x11f00000100f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID14" , 0x11f0000010100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID15" , 0x11f0000010110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID16" , 0x11f0000010120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID17" , 0x11f0000010130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID18" , 0x11f0000010140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID19" , 0x11f0000010150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID20" , 0x11f0000010160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID21" , 0x11f0000010170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID22" , 0x11f0000010180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID23" , 0x11f0000010190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID24" , 0x11f00000101a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID25" , 0x11f00000101b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID26" , 0x11f00000101c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MEM_ACCESS_SUBID27" , 0x11f00000101d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1145},
- {"SLI_MSI_ENB0" , 0x11f0000013c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1146},
- {"SLI_MSI_ENB1" , 0x11f0000013c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1147},
- {"SLI_MSI_ENB2" , 0x11f0000013c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1148},
- {"SLI_MSI_ENB3" , 0x11f0000013c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1149},
- {"SLI_MSI_RCV0" , 0x11f0000013c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1150},
- {"SLI_MSI_RCV1" , 0x11f0000013c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1151},
- {"SLI_MSI_RCV2" , 0x11f0000013c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1152},
- {"SLI_MSI_RCV3" , 0x11f0000013c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1153},
- {"SLI_MSI_RD_MAP" , 0x11f0000013ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1154},
- {"SLI_MSI_W1C_ENB0" , 0x11f0000013cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1155},
- {"SLI_MSI_W1C_ENB1" , 0x11f0000013d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1156},
- {"SLI_MSI_W1C_ENB2" , 0x11f0000013d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1157},
- {"SLI_MSI_W1C_ENB3" , 0x11f0000013d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1158},
- {"SLI_MSI_W1S_ENB0" , 0x11f0000013d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1159},
- {"SLI_MSI_W1S_ENB1" , 0x11f0000013d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1160},
- {"SLI_MSI_W1S_ENB2" , 0x11f0000013d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1161},
- {"SLI_MSI_W1S_ENB3" , 0x11f0000013d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1162},
- {"SLI_MSI_WR_MAP" , 0x11f0000013c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1163},
- {"SLI_PCIE_MSI_RCV" , 0x11f0000013cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1164},
- {"SLI_PCIE_MSI_RCV_B1" , 0x11f0000010650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1165},
- {"SLI_PCIE_MSI_RCV_B2" , 0x11f0000010660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1166},
- {"SLI_PCIE_MSI_RCV_B3" , 0x11f0000010670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1167},
- {"SLI_PKT0_CNTS" , 0x11f0000012400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT1_CNTS" , 0x11f0000012410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT2_CNTS" , 0x11f0000012420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT3_CNTS" , 0x11f0000012430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT4_CNTS" , 0x11f0000012440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT5_CNTS" , 0x11f0000012450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT6_CNTS" , 0x11f0000012460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT7_CNTS" , 0x11f0000012470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT8_CNTS" , 0x11f0000012480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT9_CNTS" , 0x11f0000012490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT10_CNTS" , 0x11f00000124a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT11_CNTS" , 0x11f00000124b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT12_CNTS" , 0x11f00000124c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT13_CNTS" , 0x11f00000124d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT14_CNTS" , 0x11f00000124e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT15_CNTS" , 0x11f00000124f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT16_CNTS" , 0x11f0000012500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT17_CNTS" , 0x11f0000012510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT18_CNTS" , 0x11f0000012520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT19_CNTS" , 0x11f0000012530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT20_CNTS" , 0x11f0000012540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT21_CNTS" , 0x11f0000012550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT22_CNTS" , 0x11f0000012560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT23_CNTS" , 0x11f0000012570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT24_CNTS" , 0x11f0000012580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT25_CNTS" , 0x11f0000012590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT26_CNTS" , 0x11f00000125a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT27_CNTS" , 0x11f00000125b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT28_CNTS" , 0x11f00000125c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT29_CNTS" , 0x11f00000125d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT30_CNTS" , 0x11f00000125e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT31_CNTS" , 0x11f00000125f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1168},
- {"SLI_PKT0_INSTR_BADDR" , 0x11f0000012800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT1_INSTR_BADDR" , 0x11f0000012810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT2_INSTR_BADDR" , 0x11f0000012820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT3_INSTR_BADDR" , 0x11f0000012830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT4_INSTR_BADDR" , 0x11f0000012840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT5_INSTR_BADDR" , 0x11f0000012850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT6_INSTR_BADDR" , 0x11f0000012860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT7_INSTR_BADDR" , 0x11f0000012870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT8_INSTR_BADDR" , 0x11f0000012880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT9_INSTR_BADDR" , 0x11f0000012890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT10_INSTR_BADDR" , 0x11f00000128a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT11_INSTR_BADDR" , 0x11f00000128b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT12_INSTR_BADDR" , 0x11f00000128c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT13_INSTR_BADDR" , 0x11f00000128d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT14_INSTR_BADDR" , 0x11f00000128e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT15_INSTR_BADDR" , 0x11f00000128f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT16_INSTR_BADDR" , 0x11f0000012900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT17_INSTR_BADDR" , 0x11f0000012910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT18_INSTR_BADDR" , 0x11f0000012920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT19_INSTR_BADDR" , 0x11f0000012930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT20_INSTR_BADDR" , 0x11f0000012940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT21_INSTR_BADDR" , 0x11f0000012950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT22_INSTR_BADDR" , 0x11f0000012960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT23_INSTR_BADDR" , 0x11f0000012970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT24_INSTR_BADDR" , 0x11f0000012980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT25_INSTR_BADDR" , 0x11f0000012990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT26_INSTR_BADDR" , 0x11f00000129a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT27_INSTR_BADDR" , 0x11f00000129b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT28_INSTR_BADDR" , 0x11f00000129c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT29_INSTR_BADDR" , 0x11f00000129d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT30_INSTR_BADDR" , 0x11f00000129e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT31_INSTR_BADDR" , 0x11f00000129f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1169},
- {"SLI_PKT0_INSTR_BAOFF_DBELL" , 0x11f0000012c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT1_INSTR_BAOFF_DBELL" , 0x11f0000012c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT2_INSTR_BAOFF_DBELL" , 0x11f0000012c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT3_INSTR_BAOFF_DBELL" , 0x11f0000012c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT4_INSTR_BAOFF_DBELL" , 0x11f0000012c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT5_INSTR_BAOFF_DBELL" , 0x11f0000012c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT6_INSTR_BAOFF_DBELL" , 0x11f0000012c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT7_INSTR_BAOFF_DBELL" , 0x11f0000012c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT8_INSTR_BAOFF_DBELL" , 0x11f0000012c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT9_INSTR_BAOFF_DBELL" , 0x11f0000012c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT10_INSTR_BAOFF_DBELL" , 0x11f0000012ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT11_INSTR_BAOFF_DBELL" , 0x11f0000012cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT12_INSTR_BAOFF_DBELL" , 0x11f0000012cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT13_INSTR_BAOFF_DBELL" , 0x11f0000012cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT14_INSTR_BAOFF_DBELL" , 0x11f0000012ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT15_INSTR_BAOFF_DBELL" , 0x11f0000012cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT16_INSTR_BAOFF_DBELL" , 0x11f0000012d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT17_INSTR_BAOFF_DBELL" , 0x11f0000012d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT18_INSTR_BAOFF_DBELL" , 0x11f0000012d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT19_INSTR_BAOFF_DBELL" , 0x11f0000012d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT20_INSTR_BAOFF_DBELL" , 0x11f0000012d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT21_INSTR_BAOFF_DBELL" , 0x11f0000012d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT22_INSTR_BAOFF_DBELL" , 0x11f0000012d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT23_INSTR_BAOFF_DBELL" , 0x11f0000012d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT24_INSTR_BAOFF_DBELL" , 0x11f0000012d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT25_INSTR_BAOFF_DBELL" , 0x11f0000012d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT26_INSTR_BAOFF_DBELL" , 0x11f0000012da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT27_INSTR_BAOFF_DBELL" , 0x11f0000012db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT28_INSTR_BAOFF_DBELL" , 0x11f0000012dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT29_INSTR_BAOFF_DBELL" , 0x11f0000012dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT30_INSTR_BAOFF_DBELL" , 0x11f0000012de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT31_INSTR_BAOFF_DBELL" , 0x11f0000012df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1170},
- {"SLI_PKT0_INSTR_FIFO_RSIZE" , 0x11f0000013000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT1_INSTR_FIFO_RSIZE" , 0x11f0000013010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT2_INSTR_FIFO_RSIZE" , 0x11f0000013020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT3_INSTR_FIFO_RSIZE" , 0x11f0000013030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT4_INSTR_FIFO_RSIZE" , 0x11f0000013040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT5_INSTR_FIFO_RSIZE" , 0x11f0000013050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT6_INSTR_FIFO_RSIZE" , 0x11f0000013060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT7_INSTR_FIFO_RSIZE" , 0x11f0000013070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT8_INSTR_FIFO_RSIZE" , 0x11f0000013080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT9_INSTR_FIFO_RSIZE" , 0x11f0000013090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT10_INSTR_FIFO_RSIZE" , 0x11f00000130a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT11_INSTR_FIFO_RSIZE" , 0x11f00000130b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT12_INSTR_FIFO_RSIZE" , 0x11f00000130c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT13_INSTR_FIFO_RSIZE" , 0x11f00000130d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT14_INSTR_FIFO_RSIZE" , 0x11f00000130e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT15_INSTR_FIFO_RSIZE" , 0x11f00000130f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT16_INSTR_FIFO_RSIZE" , 0x11f0000013100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT17_INSTR_FIFO_RSIZE" , 0x11f0000013110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT18_INSTR_FIFO_RSIZE" , 0x11f0000013120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT19_INSTR_FIFO_RSIZE" , 0x11f0000013130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT20_INSTR_FIFO_RSIZE" , 0x11f0000013140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT21_INSTR_FIFO_RSIZE" , 0x11f0000013150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT22_INSTR_FIFO_RSIZE" , 0x11f0000013160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT23_INSTR_FIFO_RSIZE" , 0x11f0000013170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT24_INSTR_FIFO_RSIZE" , 0x11f0000013180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT25_INSTR_FIFO_RSIZE" , 0x11f0000013190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT26_INSTR_FIFO_RSIZE" , 0x11f00000131a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT27_INSTR_FIFO_RSIZE" , 0x11f00000131b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT28_INSTR_FIFO_RSIZE" , 0x11f00000131c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT29_INSTR_FIFO_RSIZE" , 0x11f00000131d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT30_INSTR_FIFO_RSIZE" , 0x11f00000131e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT31_INSTR_FIFO_RSIZE" , 0x11f00000131f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1171},
- {"SLI_PKT0_INSTR_HEADER" , 0x11f0000013400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT1_INSTR_HEADER" , 0x11f0000013410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT2_INSTR_HEADER" , 0x11f0000013420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT3_INSTR_HEADER" , 0x11f0000013430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT4_INSTR_HEADER" , 0x11f0000013440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT5_INSTR_HEADER" , 0x11f0000013450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT6_INSTR_HEADER" , 0x11f0000013460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT7_INSTR_HEADER" , 0x11f0000013470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT8_INSTR_HEADER" , 0x11f0000013480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT9_INSTR_HEADER" , 0x11f0000013490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT10_INSTR_HEADER" , 0x11f00000134a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT11_INSTR_HEADER" , 0x11f00000134b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT12_INSTR_HEADER" , 0x11f00000134c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT13_INSTR_HEADER" , 0x11f00000134d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT14_INSTR_HEADER" , 0x11f00000134e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT15_INSTR_HEADER" , 0x11f00000134f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT16_INSTR_HEADER" , 0x11f0000013500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT17_INSTR_HEADER" , 0x11f0000013510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT18_INSTR_HEADER" , 0x11f0000013520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT19_INSTR_HEADER" , 0x11f0000013530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT20_INSTR_HEADER" , 0x11f0000013540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT21_INSTR_HEADER" , 0x11f0000013550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT22_INSTR_HEADER" , 0x11f0000013560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT23_INSTR_HEADER" , 0x11f0000013570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT24_INSTR_HEADER" , 0x11f0000013580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT25_INSTR_HEADER" , 0x11f0000013590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT26_INSTR_HEADER" , 0x11f00000135a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT27_INSTR_HEADER" , 0x11f00000135b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT28_INSTR_HEADER" , 0x11f00000135c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT29_INSTR_HEADER" , 0x11f00000135d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT30_INSTR_HEADER" , 0x11f00000135e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT31_INSTR_HEADER" , 0x11f00000135f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1172},
- {"SLI_PKT0_OUT_SIZE" , 0x11f0000010c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT1_OUT_SIZE" , 0x11f0000010c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT2_OUT_SIZE" , 0x11f0000010c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT3_OUT_SIZE" , 0x11f0000010c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT4_OUT_SIZE" , 0x11f0000010c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT5_OUT_SIZE" , 0x11f0000010c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT6_OUT_SIZE" , 0x11f0000010c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT7_OUT_SIZE" , 0x11f0000010c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT8_OUT_SIZE" , 0x11f0000010c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT9_OUT_SIZE" , 0x11f0000010c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT10_OUT_SIZE" , 0x11f0000010ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT11_OUT_SIZE" , 0x11f0000010cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT12_OUT_SIZE" , 0x11f0000010cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT13_OUT_SIZE" , 0x11f0000010cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT14_OUT_SIZE" , 0x11f0000010ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT15_OUT_SIZE" , 0x11f0000010cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT16_OUT_SIZE" , 0x11f0000010d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT17_OUT_SIZE" , 0x11f0000010d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT18_OUT_SIZE" , 0x11f0000010d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT19_OUT_SIZE" , 0x11f0000010d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT20_OUT_SIZE" , 0x11f0000010d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT21_OUT_SIZE" , 0x11f0000010d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT22_OUT_SIZE" , 0x11f0000010d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT23_OUT_SIZE" , 0x11f0000010d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT24_OUT_SIZE" , 0x11f0000010d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT25_OUT_SIZE" , 0x11f0000010d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT26_OUT_SIZE" , 0x11f0000010da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT27_OUT_SIZE" , 0x11f0000010db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT28_OUT_SIZE" , 0x11f0000010dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT29_OUT_SIZE" , 0x11f0000010dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT30_OUT_SIZE" , 0x11f0000010de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT31_OUT_SIZE" , 0x11f0000010df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1173},
- {"SLI_PKT0_SLIST_BADDR" , 0x11f0000011400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT1_SLIST_BADDR" , 0x11f0000011410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT2_SLIST_BADDR" , 0x11f0000011420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT3_SLIST_BADDR" , 0x11f0000011430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT4_SLIST_BADDR" , 0x11f0000011440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT5_SLIST_BADDR" , 0x11f0000011450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT6_SLIST_BADDR" , 0x11f0000011460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT7_SLIST_BADDR" , 0x11f0000011470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT8_SLIST_BADDR" , 0x11f0000011480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT9_SLIST_BADDR" , 0x11f0000011490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT10_SLIST_BADDR" , 0x11f00000114a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT11_SLIST_BADDR" , 0x11f00000114b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT12_SLIST_BADDR" , 0x11f00000114c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT13_SLIST_BADDR" , 0x11f00000114d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT14_SLIST_BADDR" , 0x11f00000114e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT15_SLIST_BADDR" , 0x11f00000114f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT16_SLIST_BADDR" , 0x11f0000011500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT17_SLIST_BADDR" , 0x11f0000011510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT18_SLIST_BADDR" , 0x11f0000011520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT19_SLIST_BADDR" , 0x11f0000011530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT20_SLIST_BADDR" , 0x11f0000011540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT21_SLIST_BADDR" , 0x11f0000011550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT22_SLIST_BADDR" , 0x11f0000011560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT23_SLIST_BADDR" , 0x11f0000011570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT24_SLIST_BADDR" , 0x11f0000011580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT25_SLIST_BADDR" , 0x11f0000011590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT26_SLIST_BADDR" , 0x11f00000115a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT27_SLIST_BADDR" , 0x11f00000115b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT28_SLIST_BADDR" , 0x11f00000115c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT29_SLIST_BADDR" , 0x11f00000115d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT30_SLIST_BADDR" , 0x11f00000115e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT31_SLIST_BADDR" , 0x11f00000115f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1174},
- {"SLI_PKT0_SLIST_BAOFF_DBELL" , 0x11f0000011800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT1_SLIST_BAOFF_DBELL" , 0x11f0000011810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT2_SLIST_BAOFF_DBELL" , 0x11f0000011820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT3_SLIST_BAOFF_DBELL" , 0x11f0000011830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT4_SLIST_BAOFF_DBELL" , 0x11f0000011840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT5_SLIST_BAOFF_DBELL" , 0x11f0000011850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT6_SLIST_BAOFF_DBELL" , 0x11f0000011860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT7_SLIST_BAOFF_DBELL" , 0x11f0000011870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT8_SLIST_BAOFF_DBELL" , 0x11f0000011880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT9_SLIST_BAOFF_DBELL" , 0x11f0000011890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT10_SLIST_BAOFF_DBELL" , 0x11f00000118a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT11_SLIST_BAOFF_DBELL" , 0x11f00000118b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT12_SLIST_BAOFF_DBELL" , 0x11f00000118c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT13_SLIST_BAOFF_DBELL" , 0x11f00000118d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT14_SLIST_BAOFF_DBELL" , 0x11f00000118e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT15_SLIST_BAOFF_DBELL" , 0x11f00000118f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT16_SLIST_BAOFF_DBELL" , 0x11f0000011900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT17_SLIST_BAOFF_DBELL" , 0x11f0000011910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT18_SLIST_BAOFF_DBELL" , 0x11f0000011920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT19_SLIST_BAOFF_DBELL" , 0x11f0000011930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT20_SLIST_BAOFF_DBELL" , 0x11f0000011940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT21_SLIST_BAOFF_DBELL" , 0x11f0000011950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT22_SLIST_BAOFF_DBELL" , 0x11f0000011960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT23_SLIST_BAOFF_DBELL" , 0x11f0000011970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT24_SLIST_BAOFF_DBELL" , 0x11f0000011980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT25_SLIST_BAOFF_DBELL" , 0x11f0000011990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT26_SLIST_BAOFF_DBELL" , 0x11f00000119a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT27_SLIST_BAOFF_DBELL" , 0x11f00000119b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT28_SLIST_BAOFF_DBELL" , 0x11f00000119c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT29_SLIST_BAOFF_DBELL" , 0x11f00000119d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT30_SLIST_BAOFF_DBELL" , 0x11f00000119e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT31_SLIST_BAOFF_DBELL" , 0x11f00000119f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1175},
- {"SLI_PKT0_SLIST_FIFO_RSIZE" , 0x11f0000011c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT1_SLIST_FIFO_RSIZE" , 0x11f0000011c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT2_SLIST_FIFO_RSIZE" , 0x11f0000011c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT3_SLIST_FIFO_RSIZE" , 0x11f0000011c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT4_SLIST_FIFO_RSIZE" , 0x11f0000011c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT5_SLIST_FIFO_RSIZE" , 0x11f0000011c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT6_SLIST_FIFO_RSIZE" , 0x11f0000011c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT7_SLIST_FIFO_RSIZE" , 0x11f0000011c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT8_SLIST_FIFO_RSIZE" , 0x11f0000011c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT9_SLIST_FIFO_RSIZE" , 0x11f0000011c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT10_SLIST_FIFO_RSIZE" , 0x11f0000011ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT11_SLIST_FIFO_RSIZE" , 0x11f0000011cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT12_SLIST_FIFO_RSIZE" , 0x11f0000011cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT13_SLIST_FIFO_RSIZE" , 0x11f0000011cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT14_SLIST_FIFO_RSIZE" , 0x11f0000011ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT15_SLIST_FIFO_RSIZE" , 0x11f0000011cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT16_SLIST_FIFO_RSIZE" , 0x11f0000011d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT17_SLIST_FIFO_RSIZE" , 0x11f0000011d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT18_SLIST_FIFO_RSIZE" , 0x11f0000011d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT19_SLIST_FIFO_RSIZE" , 0x11f0000011d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT20_SLIST_FIFO_RSIZE" , 0x11f0000011d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT21_SLIST_FIFO_RSIZE" , 0x11f0000011d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT22_SLIST_FIFO_RSIZE" , 0x11f0000011d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT23_SLIST_FIFO_RSIZE" , 0x11f0000011d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT24_SLIST_FIFO_RSIZE" , 0x11f0000011d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT25_SLIST_FIFO_RSIZE" , 0x11f0000011d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT26_SLIST_FIFO_RSIZE" , 0x11f0000011da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT27_SLIST_FIFO_RSIZE" , 0x11f0000011db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT28_SLIST_FIFO_RSIZE" , 0x11f0000011dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT29_SLIST_FIFO_RSIZE" , 0x11f0000011dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT30_SLIST_FIFO_RSIZE" , 0x11f0000011de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT31_SLIST_FIFO_RSIZE" , 0x11f0000011df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1176},
- {"SLI_PKT_CNT_INT" , 0x11f0000011130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1177},
- {"SLI_PKT_CNT_INT_ENB" , 0x11f0000011150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1178},
- {"SLI_PKT_CTL" , 0x11f0000011220ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1179},
- {"SLI_PKT_DATA_OUT_ES" , 0x11f00000110b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1180},
- {"SLI_PKT_DATA_OUT_NS" , 0x11f00000110a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1181},
- {"SLI_PKT_DATA_OUT_ROR" , 0x11f0000011090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1182},
- {"SLI_PKT_DPADDR" , 0x11f0000011080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1183},
- {"SLI_PKT_IN_DONE0_CNTS" , 0x11f0000012000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE1_CNTS" , 0x11f0000012010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE2_CNTS" , 0x11f0000012020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE3_CNTS" , 0x11f0000012030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE4_CNTS" , 0x11f0000012040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE5_CNTS" , 0x11f0000012050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE6_CNTS" , 0x11f0000012060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE7_CNTS" , 0x11f0000012070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE8_CNTS" , 0x11f0000012080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE9_CNTS" , 0x11f0000012090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE10_CNTS" , 0x11f00000120a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE11_CNTS" , 0x11f00000120b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE12_CNTS" , 0x11f00000120c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE13_CNTS" , 0x11f00000120d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE14_CNTS" , 0x11f00000120e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE15_CNTS" , 0x11f00000120f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE16_CNTS" , 0x11f0000012100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE17_CNTS" , 0x11f0000012110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE18_CNTS" , 0x11f0000012120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE19_CNTS" , 0x11f0000012130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE20_CNTS" , 0x11f0000012140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE21_CNTS" , 0x11f0000012150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE22_CNTS" , 0x11f0000012160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE23_CNTS" , 0x11f0000012170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE24_CNTS" , 0x11f0000012180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE25_CNTS" , 0x11f0000012190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE26_CNTS" , 0x11f00000121a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE27_CNTS" , 0x11f00000121b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE28_CNTS" , 0x11f00000121c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE29_CNTS" , 0x11f00000121d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE30_CNTS" , 0x11f00000121e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_DONE31_CNTS" , 0x11f00000121f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1184},
- {"SLI_PKT_IN_INSTR_COUNTS" , 0x11f0000011200ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1185},
- {"SLI_PKT_IN_PCIE_PORT" , 0x11f00000111b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1186},
- {"SLI_PKT_INPUT_CONTROL" , 0x11f0000011170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1187},
- {"SLI_PKT_INSTR_ENB" , 0x11f0000011000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1188},
- {"SLI_PKT_INSTR_RD_SIZE" , 0x11f00000111a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1189},
- {"SLI_PKT_INSTR_SIZE" , 0x11f0000011020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1190},
- {"SLI_PKT_INT_LEVELS" , 0x11f0000011120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1191},
- {"SLI_PKT_IPTR" , 0x11f0000011070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1192},
- {"SLI_PKT_OUT_BMODE" , 0x11f00000110d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1193},
- {"SLI_PKT_OUT_BP_EN" , 0x11f0000011240ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1194},
- {"SLI_PKT_OUT_ENB" , 0x11f0000011010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1195},
- {"SLI_PKT_OUTPUT_WMARK" , 0x11f0000011180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1196},
- {"SLI_PKT_PCIE_PORT" , 0x11f00000110e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1197},
- {"SLI_PKT_PORT_IN_RST" , 0x11f00000111f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1198},
- {"SLI_PKT_SLIST_ES" , 0x11f0000011050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1199},
- {"SLI_PKT_SLIST_NS" , 0x11f0000011040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1200},
- {"SLI_PKT_SLIST_ROR" , 0x11f0000011030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1201},
- {"SLI_PKT_TIME_INT" , 0x11f0000011140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1202},
- {"SLI_PKT_TIME_INT_ENB" , 0x11f0000011160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1203},
- {"SLI_PORT0_PKIND" , 0x11f0000010800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT1_PKIND" , 0x11f0000010810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT2_PKIND" , 0x11f0000010820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT3_PKIND" , 0x11f0000010830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT4_PKIND" , 0x11f0000010840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT5_PKIND" , 0x11f0000010850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT6_PKIND" , 0x11f0000010860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT7_PKIND" , 0x11f0000010870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT8_PKIND" , 0x11f0000010880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT9_PKIND" , 0x11f0000010890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT10_PKIND" , 0x11f00000108a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT11_PKIND" , 0x11f00000108b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT12_PKIND" , 0x11f00000108c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT13_PKIND" , 0x11f00000108d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT14_PKIND" , 0x11f00000108e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT15_PKIND" , 0x11f00000108f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT16_PKIND" , 0x11f0000010900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT17_PKIND" , 0x11f0000010910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT18_PKIND" , 0x11f0000010920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT19_PKIND" , 0x11f0000010930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT20_PKIND" , 0x11f0000010940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT21_PKIND" , 0x11f0000010950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT22_PKIND" , 0x11f0000010960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT23_PKIND" , 0x11f0000010970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT24_PKIND" , 0x11f0000010980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT25_PKIND" , 0x11f0000010990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT26_PKIND" , 0x11f00000109a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT27_PKIND" , 0x11f00000109b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT28_PKIND" , 0x11f00000109c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT29_PKIND" , 0x11f00000109d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT30_PKIND" , 0x11f00000109e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_PORT31_PKIND" , 0x11f00000109f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1204},
- {"SLI_S2M_PORT0_CTL" , 0x11f0000013d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1205},
- {"SLI_S2M_PORT1_CTL" , 0x11f0000013d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1205},
- {"SLI_SCRATCH_1" , 0x11f00000103c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1206},
- {"SLI_SCRATCH_2" , 0x11f00000103d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1207},
- {"SLI_STATE1" , 0x11f0000010620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1208},
- {"SLI_STATE2" , 0x11f0000010630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1209},
- {"SLI_STATE3" , 0x11f0000010640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1210},
- {"SLI_TX_PIPE" , 0x11f0000011230ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1211},
- {"SLI_WIN_RD_ADDR" , 0x10ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1212},
- {"SLI_WIN_RD_DATA" , 0x40ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1213},
- {"SLI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1214},
- {"SLI_WIN_WR_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1215},
- {"SLI_WIN_WR_MASK" , 0x30ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1216},
- {"SLI_WINDOW_CTL" , 0x11f00000102e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1217},
- {"SMI0_CLK" , 0x1180000003818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1218},
- {"SMI1_CLK" , 0x1180000003898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1218},
- {"SMI2_CLK" , 0x1180000003918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1218},
- {"SMI3_CLK" , 0x1180000003998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1218},
- {"SMI0_CMD" , 0x1180000003800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1219},
- {"SMI1_CMD" , 0x1180000003880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1219},
- {"SMI2_CMD" , 0x1180000003900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1219},
- {"SMI3_CMD" , 0x1180000003980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1219},
- {"SMI0_EN" , 0x1180000003820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1220},
- {"SMI1_EN" , 0x11800000038a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1220},
- {"SMI2_EN" , 0x1180000003920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1220},
- {"SMI3_EN" , 0x11800000039a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1220},
- {"SMI0_RD_DAT" , 0x1180000003810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1221},
- {"SMI1_RD_DAT" , 0x1180000003890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1221},
- {"SMI2_RD_DAT" , 0x1180000003910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1221},
- {"SMI3_RD_DAT" , 0x1180000003990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1221},
- {"SMI0_WR_DAT" , 0x1180000003808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1222},
- {"SMI1_WR_DAT" , 0x1180000003888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1222},
- {"SMI2_WR_DAT" , 0x1180000003908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1222},
- {"SMI3_WR_DAT" , 0x1180000003988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1222},
- {"SMI_DRV_CTL" , 0x1180000001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1223},
- {"SSO_ACTIVE_CYCLES" , 0x16700000010e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1224},
- {"SSO_BIST_STAT" , 0x1670000001078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1225},
- {"SSO_CFG" , 0x1670000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1226},
- {"SSO_DS_PC" , 0x1670000001070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1227},
- {"SSO_ERR" , 0x1670000001038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1228},
- {"SSO_ERR_ENB" , 0x1670000001030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1229},
- {"SSO_FIDX_ECC_CTL" , 0x16700000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1230},
- {"SSO_FIDX_ECC_ST" , 0x16700000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1231},
- {"SSO_FPAGE_CNT" , 0x1670000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1232},
- {"SSO_GWE_CFG" , 0x1670000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1233},
- {"SSO_IDX_ECC_CTL" , 0x16700000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1234},
- {"SSO_IDX_ECC_ST" , 0x16700000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1235},
- {"SSO_IQ_CNT0" , 0x1670000009000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1236},
- {"SSO_IQ_CNT1" , 0x1670000009008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1236},
- {"SSO_IQ_CNT2" , 0x1670000009010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1236},
- {"SSO_IQ_CNT3" , 0x1670000009018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1236},
- {"SSO_IQ_CNT4" , 0x1670000009020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1236},
- {"SSO_IQ_CNT5" , 0x1670000009028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1236},
- {"SSO_IQ_CNT6" , 0x1670000009030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1236},
- {"SSO_IQ_CNT7" , 0x1670000009038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1236},
- {"SSO_IQ_COM_CNT" , 0x1670000001058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1237},
- {"SSO_IQ_INT" , 0x1670000001048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1238},
- {"SSO_IQ_INT_EN" , 0x1670000001050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1239},
- {"SSO_IQ_THR0" , 0x167000000a000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1240},
- {"SSO_IQ_THR1" , 0x167000000a008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1240},
- {"SSO_IQ_THR2" , 0x167000000a010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1240},
- {"SSO_IQ_THR3" , 0x167000000a018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1240},
- {"SSO_IQ_THR4" , 0x167000000a020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1240},
- {"SSO_IQ_THR5" , 0x167000000a028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1240},
- {"SSO_IQ_THR6" , 0x167000000a030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1240},
- {"SSO_IQ_THR7" , 0x167000000a038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1240},
- {"SSO_NOS_CNT" , 0x1670000001040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1241},
- {"SSO_NW_TIM" , 0x1670000001028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1242},
- {"SSO_OTH_ECC_CTL" , 0x16700000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1243},
- {"SSO_OTH_ECC_ST" , 0x16700000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1244},
- {"SSO_PND_ECC_CTL" , 0x16700000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1245},
- {"SSO_PND_ECC_ST" , 0x16700000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1246},
- {"SSO_PP0_GRP_MSK" , 0x1670000006000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP1_GRP_MSK" , 0x1670000006008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP2_GRP_MSK" , 0x1670000006010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP3_GRP_MSK" , 0x1670000006018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP4_GRP_MSK" , 0x1670000006020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP5_GRP_MSK" , 0x1670000006028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP6_GRP_MSK" , 0x1670000006030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP7_GRP_MSK" , 0x1670000006038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP8_GRP_MSK" , 0x1670000006040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP9_GRP_MSK" , 0x1670000006048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP10_GRP_MSK" , 0x1670000006050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP11_GRP_MSK" , 0x1670000006058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP12_GRP_MSK" , 0x1670000006060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP13_GRP_MSK" , 0x1670000006068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP14_GRP_MSK" , 0x1670000006070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP15_GRP_MSK" , 0x1670000006078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP16_GRP_MSK" , 0x1670000006080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP17_GRP_MSK" , 0x1670000006088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP18_GRP_MSK" , 0x1670000006090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP19_GRP_MSK" , 0x1670000006098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP20_GRP_MSK" , 0x16700000060a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP21_GRP_MSK" , 0x16700000060a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP22_GRP_MSK" , 0x16700000060b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP23_GRP_MSK" , 0x16700000060b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP24_GRP_MSK" , 0x16700000060c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP25_GRP_MSK" , 0x16700000060c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP26_GRP_MSK" , 0x16700000060d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP27_GRP_MSK" , 0x16700000060d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP28_GRP_MSK" , 0x16700000060e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP29_GRP_MSK" , 0x16700000060e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP30_GRP_MSK" , 0x16700000060f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP31_GRP_MSK" , 0x16700000060f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1247},
- {"SSO_PP0_QOS_PRI" , 0x1670000003000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP1_QOS_PRI" , 0x1670000003008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP2_QOS_PRI" , 0x1670000003010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP3_QOS_PRI" , 0x1670000003018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP4_QOS_PRI" , 0x1670000003020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP5_QOS_PRI" , 0x1670000003028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP6_QOS_PRI" , 0x1670000003030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP7_QOS_PRI" , 0x1670000003038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP8_QOS_PRI" , 0x1670000003040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP9_QOS_PRI" , 0x1670000003048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP10_QOS_PRI" , 0x1670000003050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP11_QOS_PRI" , 0x1670000003058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP12_QOS_PRI" , 0x1670000003060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP13_QOS_PRI" , 0x1670000003068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP14_QOS_PRI" , 0x1670000003070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP15_QOS_PRI" , 0x1670000003078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP16_QOS_PRI" , 0x1670000003080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP17_QOS_PRI" , 0x1670000003088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP18_QOS_PRI" , 0x1670000003090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP19_QOS_PRI" , 0x1670000003098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP20_QOS_PRI" , 0x16700000030a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP21_QOS_PRI" , 0x16700000030a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP22_QOS_PRI" , 0x16700000030b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP23_QOS_PRI" , 0x16700000030b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP24_QOS_PRI" , 0x16700000030c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP25_QOS_PRI" , 0x16700000030c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP26_QOS_PRI" , 0x16700000030d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP27_QOS_PRI" , 0x16700000030d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP28_QOS_PRI" , 0x16700000030e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP29_QOS_PRI" , 0x16700000030e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP30_QOS_PRI" , 0x16700000030f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP31_QOS_PRI" , 0x16700000030f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1248},
- {"SSO_PP_STRICT" , 0x16700000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1249},
- {"SSO_QOS0_RND" , 0x1670000002000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1250},
- {"SSO_QOS1_RND" , 0x1670000002008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1250},
- {"SSO_QOS2_RND" , 0x1670000002010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1250},
- {"SSO_QOS3_RND" , 0x1670000002018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1250},
- {"SSO_QOS4_RND" , 0x1670000002020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1250},
- {"SSO_QOS5_RND" , 0x1670000002028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1250},
- {"SSO_QOS6_RND" , 0x1670000002030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1250},
- {"SSO_QOS7_RND" , 0x1670000002038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1250},
- {"SSO_QOS_THR0" , 0x167000000b000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1251},
- {"SSO_QOS_THR1" , 0x167000000b008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1251},
- {"SSO_QOS_THR2" , 0x167000000b010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1251},
- {"SSO_QOS_THR3" , 0x167000000b018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1251},
- {"SSO_QOS_THR4" , 0x167000000b020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1251},
- {"SSO_QOS_THR5" , 0x167000000b028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1251},
- {"SSO_QOS_THR6" , 0x167000000b030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1251},
- {"SSO_QOS_THR7" , 0x167000000b038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1251},
- {"SSO_QOS_WE" , 0x1670000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1252},
- {"SSO_RESET" , 0x16700000010f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1253},
- {"SSO_RWQ_HEAD_PTR0" , 0x167000000c000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1254},
- {"SSO_RWQ_HEAD_PTR1" , 0x167000000c008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1254},
- {"SSO_RWQ_HEAD_PTR2" , 0x167000000c010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1254},
- {"SSO_RWQ_HEAD_PTR3" , 0x167000000c018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1254},
- {"SSO_RWQ_HEAD_PTR4" , 0x167000000c020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1254},
- {"SSO_RWQ_HEAD_PTR5" , 0x167000000c028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1254},
- {"SSO_RWQ_HEAD_PTR6" , 0x167000000c030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1254},
- {"SSO_RWQ_HEAD_PTR7" , 0x167000000c038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1254},
- {"SSO_RWQ_POP_FPTR" , 0x167000000c408ull, CVMX_CSR_DB_TYPE_NCB, 64, 1255},
- {"SSO_RWQ_PSH_FPTR" , 0x167000000c400ull, CVMX_CSR_DB_TYPE_NCB, 64, 1256},
- {"SSO_RWQ_TAIL_PTR0" , 0x167000000c200ull, CVMX_CSR_DB_TYPE_NCB, 64, 1257},
- {"SSO_RWQ_TAIL_PTR1" , 0x167000000c208ull, CVMX_CSR_DB_TYPE_NCB, 64, 1257},
- {"SSO_RWQ_TAIL_PTR2" , 0x167000000c210ull, CVMX_CSR_DB_TYPE_NCB, 64, 1257},
- {"SSO_RWQ_TAIL_PTR3" , 0x167000000c218ull, CVMX_CSR_DB_TYPE_NCB, 64, 1257},
- {"SSO_RWQ_TAIL_PTR4" , 0x167000000c220ull, CVMX_CSR_DB_TYPE_NCB, 64, 1257},
- {"SSO_RWQ_TAIL_PTR5" , 0x167000000c228ull, CVMX_CSR_DB_TYPE_NCB, 64, 1257},
- {"SSO_RWQ_TAIL_PTR6" , 0x167000000c230ull, CVMX_CSR_DB_TYPE_NCB, 64, 1257},
- {"SSO_RWQ_TAIL_PTR7" , 0x167000000c238ull, CVMX_CSR_DB_TYPE_NCB, 64, 1257},
- {"SSO_TS_PC" , 0x1670000001068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1258},
- {"SSO_WA_COM_PC" , 0x1670000001060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1259},
- {"SSO_WA_PC0" , 0x1670000005000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1260},
- {"SSO_WA_PC1" , 0x1670000005008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1260},
- {"SSO_WA_PC2" , 0x1670000005010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1260},
- {"SSO_WA_PC3" , 0x1670000005018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1260},
- {"SSO_WA_PC4" , 0x1670000005020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1260},
- {"SSO_WA_PC5" , 0x1670000005028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1260},
- {"SSO_WA_PC6" , 0x1670000005030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1260},
- {"SSO_WA_PC7" , 0x1670000005038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1260},
- {"SSO_WQ_INT" , 0x1670000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1261},
- {"SSO_WQ_INT_CNT0" , 0x1670000008000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT1" , 0x1670000008008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT2" , 0x1670000008010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT3" , 0x1670000008018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT4" , 0x1670000008020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT5" , 0x1670000008028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT6" , 0x1670000008030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT7" , 0x1670000008038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT8" , 0x1670000008040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT9" , 0x1670000008048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT10" , 0x1670000008050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT11" , 0x1670000008058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT12" , 0x1670000008060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT13" , 0x1670000008068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT14" , 0x1670000008070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT15" , 0x1670000008078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT16" , 0x1670000008080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT17" , 0x1670000008088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT18" , 0x1670000008090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT19" , 0x1670000008098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT20" , 0x16700000080a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT21" , 0x16700000080a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT22" , 0x16700000080b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT23" , 0x16700000080b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT24" , 0x16700000080c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT25" , 0x16700000080c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT26" , 0x16700000080d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT27" , 0x16700000080d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT28" , 0x16700000080e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT29" , 0x16700000080e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT30" , 0x16700000080f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT31" , 0x16700000080f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT32" , 0x1670000008100ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT33" , 0x1670000008108ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT34" , 0x1670000008110ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT35" , 0x1670000008118ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT36" , 0x1670000008120ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT37" , 0x1670000008128ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT38" , 0x1670000008130ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT39" , 0x1670000008138ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT40" , 0x1670000008140ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT41" , 0x1670000008148ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT42" , 0x1670000008150ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT43" , 0x1670000008158ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT44" , 0x1670000008160ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT45" , 0x1670000008168ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT46" , 0x1670000008170ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT47" , 0x1670000008178ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT48" , 0x1670000008180ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT49" , 0x1670000008188ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT50" , 0x1670000008190ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT51" , 0x1670000008198ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT52" , 0x16700000081a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT53" , 0x16700000081a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT54" , 0x16700000081b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT55" , 0x16700000081b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT56" , 0x16700000081c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT57" , 0x16700000081c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT58" , 0x16700000081d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT59" , 0x16700000081d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT60" , 0x16700000081e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT61" , 0x16700000081e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT62" , 0x16700000081f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_CNT63" , 0x16700000081f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1262},
- {"SSO_WQ_INT_PC" , 0x1670000001020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1263},
- {"SSO_WQ_INT_THR0" , 0x1670000007000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR1" , 0x1670000007008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR2" , 0x1670000007010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR3" , 0x1670000007018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR4" , 0x1670000007020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR5" , 0x1670000007028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR6" , 0x1670000007030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR7" , 0x1670000007038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR8" , 0x1670000007040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR9" , 0x1670000007048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR10" , 0x1670000007050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR11" , 0x1670000007058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR12" , 0x1670000007060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR13" , 0x1670000007068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR14" , 0x1670000007070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR15" , 0x1670000007078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR16" , 0x1670000007080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR17" , 0x1670000007088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR18" , 0x1670000007090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR19" , 0x1670000007098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR20" , 0x16700000070a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR21" , 0x16700000070a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR22" , 0x16700000070b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR23" , 0x16700000070b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR24" , 0x16700000070c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR25" , 0x16700000070c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR26" , 0x16700000070d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR27" , 0x16700000070d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR28" , 0x16700000070e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR29" , 0x16700000070e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR30" , 0x16700000070f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR31" , 0x16700000070f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR32" , 0x1670000007100ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR33" , 0x1670000007108ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR34" , 0x1670000007110ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR35" , 0x1670000007118ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR36" , 0x1670000007120ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR37" , 0x1670000007128ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR38" , 0x1670000007130ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR39" , 0x1670000007138ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR40" , 0x1670000007140ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR41" , 0x1670000007148ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR42" , 0x1670000007150ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR43" , 0x1670000007158ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR44" , 0x1670000007160ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR45" , 0x1670000007168ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR46" , 0x1670000007170ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR47" , 0x1670000007178ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR48" , 0x1670000007180ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR49" , 0x1670000007188ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR50" , 0x1670000007190ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR51" , 0x1670000007198ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR52" , 0x16700000071a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR53" , 0x16700000071a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR54" , 0x16700000071b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR55" , 0x16700000071b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR56" , 0x16700000071c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR57" , 0x16700000071c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR58" , 0x16700000071d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR59" , 0x16700000071d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR60" , 0x16700000071e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR61" , 0x16700000071e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR62" , 0x16700000071f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_INT_THR63" , 0x16700000071f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1264},
- {"SSO_WQ_IQ_DIS" , 0x1670000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1265},
- {"SSO_WS_PC0" , 0x1670000004000ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC1" , 0x1670000004008ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC2" , 0x1670000004010ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC3" , 0x1670000004018ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC4" , 0x1670000004020ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC5" , 0x1670000004028ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC6" , 0x1670000004030ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC7" , 0x1670000004038ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC8" , 0x1670000004040ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC9" , 0x1670000004048ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC10" , 0x1670000004050ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC11" , 0x1670000004058ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC12" , 0x1670000004060ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC13" , 0x1670000004068ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC14" , 0x1670000004070ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC15" , 0x1670000004078ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC16" , 0x1670000004080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC17" , 0x1670000004088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC18" , 0x1670000004090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC19" , 0x1670000004098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC20" , 0x16700000040a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC21" , 0x16700000040a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC22" , 0x16700000040b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC23" , 0x16700000040b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC24" , 0x16700000040c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC25" , 0x16700000040c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC26" , 0x16700000040d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC27" , 0x16700000040d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC28" , 0x16700000040e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC29" , 0x16700000040e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC30" , 0x16700000040f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC31" , 0x16700000040f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC32" , 0x1670000004100ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC33" , 0x1670000004108ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC34" , 0x1670000004110ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC35" , 0x1670000004118ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC36" , 0x1670000004120ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC37" , 0x1670000004128ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC38" , 0x1670000004130ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC39" , 0x1670000004138ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC40" , 0x1670000004140ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC41" , 0x1670000004148ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC42" , 0x1670000004150ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC43" , 0x1670000004158ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC44" , 0x1670000004160ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC45" , 0x1670000004168ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC46" , 0x1670000004170ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC47" , 0x1670000004178ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC48" , 0x1670000004180ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC49" , 0x1670000004188ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC50" , 0x1670000004190ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC51" , 0x1670000004198ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC52" , 0x16700000041a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC53" , 0x16700000041a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC54" , 0x16700000041b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC55" , 0x16700000041b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC56" , 0x16700000041c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC57" , 0x16700000041c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC58" , 0x16700000041d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC59" , 0x16700000041d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC60" , 0x16700000041e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC61" , 0x16700000041e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC62" , 0x16700000041f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"SSO_WS_PC63" , 0x16700000041f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1266},
- {"TIM_BIST_RESULT" , 0x1180058000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1267},
- {"TIM_DBG2" , 0x11800580000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1268},
- {"TIM_DBG3" , 0x11800580000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1269},
- {"TIM_ECC_CFG" , 0x1180058000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1270},
- {"TIM_FR_RN_TT" , 0x1180058000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1271},
- {"TIM_GPIO_EN" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1272},
- {"TIM_INT0" , 0x1180058000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1273},
- {"TIM_INT0_EN" , 0x1180058000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1274},
- {"TIM_INT0_EVENT" , 0x1180058000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1275},
- {"TIM_INT_ECCERR" , 0x1180058000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1276},
- {"TIM_INT_ECCERR_EN" , 0x1180058000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1277},
- {"TIM_INT_ECCERR_EVENT0" , 0x1180058000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1278},
- {"TIM_INT_ECCERR_EVENT1" , 0x1180058000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1279},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1280},
- {"TIM_RING0_CTL0" , 0x1180058002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING1_CTL0" , 0x1180058002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING2_CTL0" , 0x1180058002010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING3_CTL0" , 0x1180058002018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING4_CTL0" , 0x1180058002020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING5_CTL0" , 0x1180058002028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING6_CTL0" , 0x1180058002030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING7_CTL0" , 0x1180058002038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING8_CTL0" , 0x1180058002040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING9_CTL0" , 0x1180058002048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING10_CTL0" , 0x1180058002050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING11_CTL0" , 0x1180058002058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING12_CTL0" , 0x1180058002060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING13_CTL0" , 0x1180058002068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING14_CTL0" , 0x1180058002070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING15_CTL0" , 0x1180058002078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING16_CTL0" , 0x1180058002080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING17_CTL0" , 0x1180058002088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING18_CTL0" , 0x1180058002090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING19_CTL0" , 0x1180058002098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING20_CTL0" , 0x11800580020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING21_CTL0" , 0x11800580020a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING22_CTL0" , 0x11800580020b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING23_CTL0" , 0x11800580020b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING24_CTL0" , 0x11800580020c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING25_CTL0" , 0x11800580020c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING26_CTL0" , 0x11800580020d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING27_CTL0" , 0x11800580020d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING28_CTL0" , 0x11800580020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING29_CTL0" , 0x11800580020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING30_CTL0" , 0x11800580020f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING31_CTL0" , 0x11800580020f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING32_CTL0" , 0x1180058002100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING33_CTL0" , 0x1180058002108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING34_CTL0" , 0x1180058002110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING35_CTL0" , 0x1180058002118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING36_CTL0" , 0x1180058002120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING37_CTL0" , 0x1180058002128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING38_CTL0" , 0x1180058002130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING39_CTL0" , 0x1180058002138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING40_CTL0" , 0x1180058002140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING41_CTL0" , 0x1180058002148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING42_CTL0" , 0x1180058002150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING43_CTL0" , 0x1180058002158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING44_CTL0" , 0x1180058002160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING45_CTL0" , 0x1180058002168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING46_CTL0" , 0x1180058002170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING47_CTL0" , 0x1180058002178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING48_CTL0" , 0x1180058002180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING49_CTL0" , 0x1180058002188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING50_CTL0" , 0x1180058002190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING51_CTL0" , 0x1180058002198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING52_CTL0" , 0x11800580021a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING53_CTL0" , 0x11800580021a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING54_CTL0" , 0x11800580021b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING55_CTL0" , 0x11800580021b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING56_CTL0" , 0x11800580021c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING57_CTL0" , 0x11800580021c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING58_CTL0" , 0x11800580021d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING59_CTL0" , 0x11800580021d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING60_CTL0" , 0x11800580021e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING61_CTL0" , 0x11800580021e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING62_CTL0" , 0x11800580021f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING63_CTL0" , 0x11800580021f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1281},
- {"TIM_RING0_CTL1" , 0x1180058002400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING1_CTL1" , 0x1180058002408ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING2_CTL1" , 0x1180058002410ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING3_CTL1" , 0x1180058002418ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING4_CTL1" , 0x1180058002420ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING5_CTL1" , 0x1180058002428ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING6_CTL1" , 0x1180058002430ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING7_CTL1" , 0x1180058002438ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING8_CTL1" , 0x1180058002440ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING9_CTL1" , 0x1180058002448ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING10_CTL1" , 0x1180058002450ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING11_CTL1" , 0x1180058002458ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING12_CTL1" , 0x1180058002460ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING13_CTL1" , 0x1180058002468ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING14_CTL1" , 0x1180058002470ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING15_CTL1" , 0x1180058002478ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING16_CTL1" , 0x1180058002480ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING17_CTL1" , 0x1180058002488ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING18_CTL1" , 0x1180058002490ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING19_CTL1" , 0x1180058002498ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING20_CTL1" , 0x11800580024a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING21_CTL1" , 0x11800580024a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING22_CTL1" , 0x11800580024b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING23_CTL1" , 0x11800580024b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING24_CTL1" , 0x11800580024c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING25_CTL1" , 0x11800580024c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING26_CTL1" , 0x11800580024d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING27_CTL1" , 0x11800580024d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING28_CTL1" , 0x11800580024e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING29_CTL1" , 0x11800580024e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING30_CTL1" , 0x11800580024f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING31_CTL1" , 0x11800580024f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING32_CTL1" , 0x1180058002500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING33_CTL1" , 0x1180058002508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING34_CTL1" , 0x1180058002510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING35_CTL1" , 0x1180058002518ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING36_CTL1" , 0x1180058002520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING37_CTL1" , 0x1180058002528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING38_CTL1" , 0x1180058002530ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING39_CTL1" , 0x1180058002538ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING40_CTL1" , 0x1180058002540ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING41_CTL1" , 0x1180058002548ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING42_CTL1" , 0x1180058002550ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING43_CTL1" , 0x1180058002558ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING44_CTL1" , 0x1180058002560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING45_CTL1" , 0x1180058002568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING46_CTL1" , 0x1180058002570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING47_CTL1" , 0x1180058002578ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING48_CTL1" , 0x1180058002580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING49_CTL1" , 0x1180058002588ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING50_CTL1" , 0x1180058002590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING51_CTL1" , 0x1180058002598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING52_CTL1" , 0x11800580025a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING53_CTL1" , 0x11800580025a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING54_CTL1" , 0x11800580025b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING55_CTL1" , 0x11800580025b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING56_CTL1" , 0x11800580025c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING57_CTL1" , 0x11800580025c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING58_CTL1" , 0x11800580025d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING59_CTL1" , 0x11800580025d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING60_CTL1" , 0x11800580025e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING61_CTL1" , 0x11800580025e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING62_CTL1" , 0x11800580025f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING63_CTL1" , 0x11800580025f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1282},
- {"TIM_RING0_CTL2" , 0x1180058002800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING1_CTL2" , 0x1180058002808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING2_CTL2" , 0x1180058002810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING3_CTL2" , 0x1180058002818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING4_CTL2" , 0x1180058002820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING5_CTL2" , 0x1180058002828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING6_CTL2" , 0x1180058002830ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING7_CTL2" , 0x1180058002838ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING8_CTL2" , 0x1180058002840ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING9_CTL2" , 0x1180058002848ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING10_CTL2" , 0x1180058002850ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING11_CTL2" , 0x1180058002858ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING12_CTL2" , 0x1180058002860ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING13_CTL2" , 0x1180058002868ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING14_CTL2" , 0x1180058002870ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING15_CTL2" , 0x1180058002878ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING16_CTL2" , 0x1180058002880ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING17_CTL2" , 0x1180058002888ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING18_CTL2" , 0x1180058002890ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING19_CTL2" , 0x1180058002898ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING20_CTL2" , 0x11800580028a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING21_CTL2" , 0x11800580028a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING22_CTL2" , 0x11800580028b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING23_CTL2" , 0x11800580028b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING24_CTL2" , 0x11800580028c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING25_CTL2" , 0x11800580028c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING26_CTL2" , 0x11800580028d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING27_CTL2" , 0x11800580028d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING28_CTL2" , 0x11800580028e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING29_CTL2" , 0x11800580028e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING30_CTL2" , 0x11800580028f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING31_CTL2" , 0x11800580028f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING32_CTL2" , 0x1180058002900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING33_CTL2" , 0x1180058002908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING34_CTL2" , 0x1180058002910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING35_CTL2" , 0x1180058002918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING36_CTL2" , 0x1180058002920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING37_CTL2" , 0x1180058002928ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING38_CTL2" , 0x1180058002930ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING39_CTL2" , 0x1180058002938ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING40_CTL2" , 0x1180058002940ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING41_CTL2" , 0x1180058002948ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING42_CTL2" , 0x1180058002950ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING43_CTL2" , 0x1180058002958ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING44_CTL2" , 0x1180058002960ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING45_CTL2" , 0x1180058002968ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING46_CTL2" , 0x1180058002970ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING47_CTL2" , 0x1180058002978ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING48_CTL2" , 0x1180058002980ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING49_CTL2" , 0x1180058002988ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING50_CTL2" , 0x1180058002990ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING51_CTL2" , 0x1180058002998ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING52_CTL2" , 0x11800580029a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING53_CTL2" , 0x11800580029a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING54_CTL2" , 0x11800580029b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING55_CTL2" , 0x11800580029b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING56_CTL2" , 0x11800580029c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING57_CTL2" , 0x11800580029c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING58_CTL2" , 0x11800580029d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING59_CTL2" , 0x11800580029d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING60_CTL2" , 0x11800580029e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING61_CTL2" , 0x11800580029e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING62_CTL2" , 0x11800580029f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING63_CTL2" , 0x11800580029f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1283},
- {"TIM_RING0_DBG0" , 0x1180058003000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING1_DBG0" , 0x1180058003008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING2_DBG0" , 0x1180058003010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING3_DBG0" , 0x1180058003018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING4_DBG0" , 0x1180058003020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING5_DBG0" , 0x1180058003028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING6_DBG0" , 0x1180058003030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING7_DBG0" , 0x1180058003038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING8_DBG0" , 0x1180058003040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING9_DBG0" , 0x1180058003048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING10_DBG0" , 0x1180058003050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING11_DBG0" , 0x1180058003058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING12_DBG0" , 0x1180058003060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING13_DBG0" , 0x1180058003068ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING14_DBG0" , 0x1180058003070ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING15_DBG0" , 0x1180058003078ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING16_DBG0" , 0x1180058003080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING17_DBG0" , 0x1180058003088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING18_DBG0" , 0x1180058003090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING19_DBG0" , 0x1180058003098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING20_DBG0" , 0x11800580030a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING21_DBG0" , 0x11800580030a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING22_DBG0" , 0x11800580030b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING23_DBG0" , 0x11800580030b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING24_DBG0" , 0x11800580030c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING25_DBG0" , 0x11800580030c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING26_DBG0" , 0x11800580030d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING27_DBG0" , 0x11800580030d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING28_DBG0" , 0x11800580030e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING29_DBG0" , 0x11800580030e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING30_DBG0" , 0x11800580030f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING31_DBG0" , 0x11800580030f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING32_DBG0" , 0x1180058003100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING33_DBG0" , 0x1180058003108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING34_DBG0" , 0x1180058003110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING35_DBG0" , 0x1180058003118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING36_DBG0" , 0x1180058003120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING37_DBG0" , 0x1180058003128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING38_DBG0" , 0x1180058003130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING39_DBG0" , 0x1180058003138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING40_DBG0" , 0x1180058003140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING41_DBG0" , 0x1180058003148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING42_DBG0" , 0x1180058003150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING43_DBG0" , 0x1180058003158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING44_DBG0" , 0x1180058003160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING45_DBG0" , 0x1180058003168ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING46_DBG0" , 0x1180058003170ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING47_DBG0" , 0x1180058003178ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING48_DBG0" , 0x1180058003180ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING49_DBG0" , 0x1180058003188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING50_DBG0" , 0x1180058003190ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING51_DBG0" , 0x1180058003198ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING52_DBG0" , 0x11800580031a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING53_DBG0" , 0x11800580031a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING54_DBG0" , 0x11800580031b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING55_DBG0" , 0x11800580031b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING56_DBG0" , 0x11800580031c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING57_DBG0" , 0x11800580031c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING58_DBG0" , 0x11800580031d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING59_DBG0" , 0x11800580031d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING60_DBG0" , 0x11800580031e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING61_DBG0" , 0x11800580031e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING62_DBG0" , 0x11800580031f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING63_DBG0" , 0x11800580031f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1284},
- {"TIM_RING0_DBG1" , 0x1180058001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING1_DBG1" , 0x1180058001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING2_DBG1" , 0x1180058001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING3_DBG1" , 0x1180058001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING4_DBG1" , 0x1180058001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING5_DBG1" , 0x1180058001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING6_DBG1" , 0x1180058001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING7_DBG1" , 0x1180058001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING8_DBG1" , 0x1180058001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING9_DBG1" , 0x1180058001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING10_DBG1" , 0x1180058001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING11_DBG1" , 0x1180058001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING12_DBG1" , 0x1180058001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING13_DBG1" , 0x1180058001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING14_DBG1" , 0x1180058001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING15_DBG1" , 0x1180058001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING16_DBG1" , 0x1180058001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING17_DBG1" , 0x1180058001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING18_DBG1" , 0x1180058001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING19_DBG1" , 0x1180058001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING20_DBG1" , 0x11800580012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING21_DBG1" , 0x11800580012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING22_DBG1" , 0x11800580012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING23_DBG1" , 0x11800580012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING24_DBG1" , 0x11800580012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING25_DBG1" , 0x11800580012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING26_DBG1" , 0x11800580012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING27_DBG1" , 0x11800580012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING28_DBG1" , 0x11800580012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING29_DBG1" , 0x11800580012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING30_DBG1" , 0x11800580012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING31_DBG1" , 0x11800580012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING32_DBG1" , 0x1180058001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING33_DBG1" , 0x1180058001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING34_DBG1" , 0x1180058001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING35_DBG1" , 0x1180058001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING36_DBG1" , 0x1180058001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING37_DBG1" , 0x1180058001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING38_DBG1" , 0x1180058001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING39_DBG1" , 0x1180058001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING40_DBG1" , 0x1180058001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING41_DBG1" , 0x1180058001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING42_DBG1" , 0x1180058001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING43_DBG1" , 0x1180058001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING44_DBG1" , 0x1180058001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING45_DBG1" , 0x1180058001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING46_DBG1" , 0x1180058001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING47_DBG1" , 0x1180058001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING48_DBG1" , 0x1180058001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING49_DBG1" , 0x1180058001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING50_DBG1" , 0x1180058001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING51_DBG1" , 0x1180058001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING52_DBG1" , 0x11800580013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING53_DBG1" , 0x11800580013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING54_DBG1" , 0x11800580013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING55_DBG1" , 0x11800580013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING56_DBG1" , 0x11800580013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING57_DBG1" , 0x11800580013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING58_DBG1" , 0x11800580013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING59_DBG1" , 0x11800580013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING60_DBG1" , 0x11800580013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING61_DBG1" , 0x11800580013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING62_DBG1" , 0x11800580013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TIM_RING63_DBG1" , 0x11800580013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1285},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1286},
- {"TRA1_BIST_STATUS" , 0x11800a8100010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1286},
- {"TRA2_BIST_STATUS" , 0x11800a8200010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1286},
- {"TRA3_BIST_STATUS" , 0x11800a8300010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1286},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1287},
- {"TRA1_CTL" , 0x11800a8100000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1287},
- {"TRA2_CTL" , 0x11800a8200000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1287},
- {"TRA3_CTL" , 0x11800a8300000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1287},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1288},
- {"TRA1_CYCLES_SINCE" , 0x11800a8100018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1288},
- {"TRA2_CYCLES_SINCE" , 0x11800a8200018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1288},
- {"TRA3_CYCLES_SINCE" , 0x11800a8300018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1288},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1289},
- {"TRA1_CYCLES_SINCE1" , 0x11800a8100028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1289},
- {"TRA2_CYCLES_SINCE1" , 0x11800a8200028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1289},
- {"TRA3_CYCLES_SINCE1" , 0x11800a8300028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1289},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1290},
- {"TRA1_FILT_ADR_ADR" , 0x11800a8100058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1290},
- {"TRA2_FILT_ADR_ADR" , 0x11800a8200058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1290},
- {"TRA3_FILT_ADR_ADR" , 0x11800a8300058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1290},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1291},
- {"TRA1_FILT_ADR_MSK" , 0x11800a8100060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1291},
- {"TRA2_FILT_ADR_MSK" , 0x11800a8200060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1291},
- {"TRA3_FILT_ADR_MSK" , 0x11800a8300060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1291},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1292},
- {"TRA1_FILT_CMD" , 0x11800a8100040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1292},
- {"TRA2_FILT_CMD" , 0x11800a8200040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1292},
- {"TRA3_FILT_CMD" , 0x11800a8300040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1292},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1293},
- {"TRA1_FILT_DID" , 0x11800a8100050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1293},
- {"TRA2_FILT_DID" , 0x11800a8200050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1293},
- {"TRA3_FILT_DID" , 0x11800a8300050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1293},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1294},
- {"TRA1_FILT_SID" , 0x11800a8100048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1294},
- {"TRA2_FILT_SID" , 0x11800a8200048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1294},
- {"TRA3_FILT_SID" , 0x11800a8300048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1294},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1295},
- {"TRA1_INT_STATUS" , 0x11800a8100008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1295},
- {"TRA2_INT_STATUS" , 0x11800a8200008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1295},
- {"TRA3_INT_STATUS" , 0x11800a8300008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1295},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1296},
- {"TRA1_READ_DAT" , 0x11800a8100020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1296},
- {"TRA2_READ_DAT" , 0x11800a8200020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1296},
- {"TRA3_READ_DAT" , 0x11800a8300020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1296},
- {"TRA0_READ_DAT_HI" , 0x11800a8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1297},
- {"TRA1_READ_DAT_HI" , 0x11800a8100030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1297},
- {"TRA2_READ_DAT_HI" , 0x11800a8200030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1297},
- {"TRA3_READ_DAT_HI" , 0x11800a8300030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1297},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1298},
- {"TRA1_TRIG0_ADR_ADR" , 0x11800a8100098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1298},
- {"TRA2_TRIG0_ADR_ADR" , 0x11800a8200098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1298},
- {"TRA3_TRIG0_ADR_ADR" , 0x11800a8300098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1298},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1299},
- {"TRA1_TRIG0_ADR_MSK" , 0x11800a81000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1299},
- {"TRA2_TRIG0_ADR_MSK" , 0x11800a82000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1299},
- {"TRA3_TRIG0_ADR_MSK" , 0x11800a83000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1299},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1300},
- {"TRA1_TRIG0_CMD" , 0x11800a8100080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1300},
- {"TRA2_TRIG0_CMD" , 0x11800a8200080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1300},
- {"TRA3_TRIG0_CMD" , 0x11800a8300080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1300},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1301},
- {"TRA1_TRIG0_DID" , 0x11800a8100090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1301},
- {"TRA2_TRIG0_DID" , 0x11800a8200090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1301},
- {"TRA3_TRIG0_DID" , 0x11800a8300090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1301},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1302},
- {"TRA1_TRIG0_SID" , 0x11800a8100088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1302},
- {"TRA2_TRIG0_SID" , 0x11800a8200088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1302},
- {"TRA3_TRIG0_SID" , 0x11800a8300088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1302},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1303},
- {"TRA1_TRIG1_ADR_ADR" , 0x11800a81000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1303},
- {"TRA2_TRIG1_ADR_ADR" , 0x11800a82000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1303},
- {"TRA3_TRIG1_ADR_ADR" , 0x11800a83000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1303},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1304},
- {"TRA1_TRIG1_ADR_MSK" , 0x11800a81000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1304},
- {"TRA2_TRIG1_ADR_MSK" , 0x11800a82000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1304},
- {"TRA3_TRIG1_ADR_MSK" , 0x11800a83000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1304},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1305},
- {"TRA1_TRIG1_CMD" , 0x11800a81000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1305},
- {"TRA2_TRIG1_CMD" , 0x11800a82000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1305},
- {"TRA3_TRIG1_CMD" , 0x11800a83000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1305},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1306},
- {"TRA1_TRIG1_DID" , 0x11800a81000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1306},
- {"TRA2_TRIG1_DID" , 0x11800a82000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1306},
- {"TRA3_TRIG1_DID" , 0x11800a83000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1306},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1307},
- {"TRA1_TRIG1_SID" , 0x11800a81000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1307},
- {"TRA2_TRIG1_SID" , 0x11800a82000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1307},
- {"TRA3_TRIG1_SID" , 0x11800a83000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1307},
- {"UAHC0_EHCI_ASYNCLISTADDR" , 0x16f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 1308},
- {"UAHC0_EHCI_CONFIGFLAG" , 0x16f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 1309},
- {"UAHC0_EHCI_CTRLDSSEGMENT" , 0x16f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 1310},
- {"UAHC0_EHCI_FRINDEX" , 0x16f000000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 1311},
- {"UAHC0_EHCI_HCCAPBASE" , 0x16f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 1312},
- {"UAHC0_EHCI_HCCPARAMS" , 0x16f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 1313},
- {"UAHC0_EHCI_HCSPARAMS" , 0x16f0000000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 1314},
- {"UAHC0_EHCI_INSNREG00" , 0x16f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 32, 1315},
- {"UAHC0_EHCI_INSNREG03" , 0x16f000000009cull, CVMX_CSR_DB_TYPE_NCB, 32, 1316},
- {"UAHC0_EHCI_INSNREG04" , 0x16f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 1317},
- {"UAHC0_EHCI_INSNREG06" , 0x16f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 1318},
- {"UAHC0_EHCI_INSNREG07" , 0x16f00000000ecull, CVMX_CSR_DB_TYPE_NCB, 32, 1319},
- {"UAHC0_EHCI_PERIODICLISTBASE" , 0x16f0000000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 1320},
- {"UAHC0_EHCI_PORTSC001" , 0x16f0000000054ull, CVMX_CSR_DB_TYPE_NCB, 32, 1321},
- {"UAHC0_EHCI_PORTSC002" , 0x16f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 32, 1321},
- {"UAHC0_EHCI_USBCMD" , 0x16f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 1322},
- {"UAHC0_EHCI_USBINTR" , 0x16f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 1323},
- {"UAHC0_EHCI_USBSTS" , 0x16f0000000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 1324},
- {"UAHC0_OHCI0_HCBULKCURRENTED" , 0x16f000000042cull, CVMX_CSR_DB_TYPE_NCB, 32, 1325},
- {"UAHC0_OHCI0_HCBULKHEADED" , 0x16f0000000428ull, CVMX_CSR_DB_TYPE_NCB, 32, 1326},
- {"UAHC0_OHCI0_HCCOMMANDSTATUS" , 0x16f0000000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 1327},
- {"UAHC0_OHCI0_HCCONTROL" , 0x16f0000000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 1328},
- {"UAHC0_OHCI0_HCCONTROLCURRENTED", 0x16f0000000424ull, CVMX_CSR_DB_TYPE_NCB, 32, 1329},
- {"UAHC0_OHCI0_HCCONTROLHEADED" , 0x16f0000000420ull, CVMX_CSR_DB_TYPE_NCB, 32, 1330},
- {"UAHC0_OHCI0_HCDONEHEAD" , 0x16f0000000430ull, CVMX_CSR_DB_TYPE_NCB, 32, 1331},
- {"UAHC0_OHCI0_HCFMINTERVAL" , 0x16f0000000434ull, CVMX_CSR_DB_TYPE_NCB, 32, 1332},
- {"UAHC0_OHCI0_HCFMNUMBER" , 0x16f000000043cull, CVMX_CSR_DB_TYPE_NCB, 32, 1333},
- {"UAHC0_OHCI0_HCFMREMAINING" , 0x16f0000000438ull, CVMX_CSR_DB_TYPE_NCB, 32, 1334},
- {"UAHC0_OHCI0_HCHCCA" , 0x16f0000000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 1335},
- {"UAHC0_OHCI0_HCINTERRUPTDISABLE", 0x16f0000000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 1336},
- {"UAHC0_OHCI0_HCINTERRUPTENABLE", 0x16f0000000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 1337},
- {"UAHC0_OHCI0_HCINTERRUPTSTATUS", 0x16f000000040cull, CVMX_CSR_DB_TYPE_NCB, 32, 1338},
- {"UAHC0_OHCI0_HCLSTHRESHOLD" , 0x16f0000000444ull, CVMX_CSR_DB_TYPE_NCB, 32, 1339},
- {"UAHC0_OHCI0_HCPERIODCURRENTED", 0x16f000000041cull, CVMX_CSR_DB_TYPE_NCB, 32, 1340},
- {"UAHC0_OHCI0_HCPERIODICSTART" , 0x16f0000000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 1341},
- {"UAHC0_OHCI0_HCREVISION" , 0x16f0000000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 1342},
- {"UAHC0_OHCI0_HCRHDESCRIPTORA" , 0x16f0000000448ull, CVMX_CSR_DB_TYPE_NCB, 32, 1343},
- {"UAHC0_OHCI0_HCRHDESCRIPTORB" , 0x16f000000044cull, CVMX_CSR_DB_TYPE_NCB, 32, 1344},
- {"UAHC0_OHCI0_HCRHPORTSTATUS001", 0x16f0000000454ull, CVMX_CSR_DB_TYPE_NCB, 32, 1345},
- {"UAHC0_OHCI0_HCRHPORTSTATUS002", 0x16f0000000458ull, CVMX_CSR_DB_TYPE_NCB, 32, 1345},
- {"UAHC0_OHCI0_HCRHSTATUS" , 0x16f0000000450ull, CVMX_CSR_DB_TYPE_NCB, 32, 1346},
- {"UAHC0_OHCI0_INSNREG06" , 0x16f0000000498ull, CVMX_CSR_DB_TYPE_NCB, 32, 1347},
- {"UAHC0_OHCI0_INSNREG07" , 0x16f000000049cull, CVMX_CSR_DB_TYPE_NCB, 32, 1348},
- {"UCTL0_BIST_STATUS" , 0x118006f0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1349},
- {"UCTL0_CLK_RST_CTL" , 0x118006f000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1350},
- {"UCTL0_EHCI_CTL" , 0x118006f000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1351},
- {"UCTL0_EHCI_FLA" , 0x118006f0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1352},
- {"UCTL0_ERTO_CTL" , 0x118006f000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1353},
- {"UCTL0_IF_ENA" , 0x118006f000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1354},
- {"UCTL0_INT_ENA" , 0x118006f000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1355},
- {"UCTL0_INT_REG" , 0x118006f000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1356},
- {"UCTL0_OHCI_CTL" , 0x118006f000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1357},
- {"UCTL0_ORTO_CTL" , 0x118006f000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1358},
- {"UCTL0_UPHY_CTL_STATUS" , 0x118006f000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1359},
- {"UCTL0_UPHY_PORT000_CTL_STATUS", 0x118006f000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1360},
- {"UCTL0_UPHY_PORT001_CTL_STATUS", 0x118006f000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1360},
- {"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1361},
- {"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1362},
- {"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1363},
- {"ZIP_CONSTANTS" , 0x11800380000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1364},
- {"ZIP_CORE0_BIST_STATUS" , 0x1180038000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 1365},
- {"ZIP_CORE1_BIST_STATUS" , 0x1180038000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 1365},
- {"ZIP_CTL_BIST_STATUS" , 0x1180038000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 1366},
- {"ZIP_CTL_CFG" , 0x1180038000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 1367},
- {"ZIP_DBG_CORE0_INST" , 0x1180038000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 1368},
- {"ZIP_DBG_CORE1_INST" , 0x1180038000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 1368},
- {"ZIP_DBG_CORE0_STA" , 0x1180038000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 1369},
- {"ZIP_DBG_CORE1_STA" , 0x1180038000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 1369},
- {"ZIP_DBG_QUE0_STA" , 0x1180038000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 1370},
- {"ZIP_DBG_QUE1_STA" , 0x1180038000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 1370},
- {"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1371},
- {"ZIP_ECC_CTL" , 0x1180038000568ull, CVMX_CSR_DB_TYPE_RSL, 64, 1372},
- {"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1373},
- {"ZIP_INT_ENA" , 0x1180038000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 1374},
- {"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1375},
- {"ZIP_INT_REG" , 0x1180038000570ull, CVMX_CSR_DB_TYPE_RSL, 64, 1376},
- {"ZIP_QUE0_BUF" , 0x1180038000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1377},
- {"ZIP_QUE1_BUF" , 0x1180038000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1377},
- {"ZIP_QUE0_ECC_ERR_STA" , 0x1180038000590ull, CVMX_CSR_DB_TYPE_RSL, 64, 1378},
- {"ZIP_QUE1_ECC_ERR_STA" , 0x1180038000598ull, CVMX_CSR_DB_TYPE_RSL, 64, 1378},
- {"ZIP_QUE0_MAP" , 0x1180038000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 1379},
- {"ZIP_QUE1_MAP" , 0x1180038000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 1379},
- {"ZIP_QUE_ENA" , 0x1180038000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 1380},
- {"ZIP_QUE_PRI" , 0x1180038000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 1381},
- {"ZIP_THROTTLE" , 0x1180038000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1382},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn68xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"OUT_OVR" , 2, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_21" , 4, 18, 0, "RAZ", 0, 0, 0ull, 0ull},
- {"LOSTSTAT" , 22, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_24_25" , 24, 2, 0, "RAZ", 1, 1, 0, 0},
- {"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_27_31" , 27, 5, 0, "RAZ", 1, 1, 0, 0},
- {"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRFLW1" , 35, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPOP1" , 36, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXPSH1" , 37, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 0, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 2, "R/W", 0, 1, 1ull, 0},
- {"RX_EN" , 4, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"TX_EN" , 5, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"BURST" , 6, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 2, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 2, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 2, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 2, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 2, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 3, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 4, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 8, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 9, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 10, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 10, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 10, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 10, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 11, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR" , 2, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"JABBER" , 3, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"ALNERR" , 5, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR" , 6, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RCVERR" , 7, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"NIBERR" , 9, 1, 12, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_10_63" , 10, 54, 12, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 13, "RO", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 7, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 8, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_ALIGN" , 9, 1, 13, "R/W", 0, 0, 1ull, 1ull},
- {"NULL_DIS" , 10, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 13, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 13, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 13, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 14, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_16_63" , 16, 48, 14, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 16, 15, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_16_63" , 16, 48, 15, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 16, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 16, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 17, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 2, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"JABBER" , 3, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALNERR" , 5, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 6, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCVERR" , 7, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"NIBERR" , 9, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"OVRERR" , 10, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_LINK" , 16, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_SPD" , 17, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PHY_DUPX" , 18, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PAUSE_DRP" , 19, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 18, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 19, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 19, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 20, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 20, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 1, 21, "RO", 0, 1, 0ull, 0},
- {"SPEED" , 1, 2, 21, "RO", 0, 1, 0ull, 0},
- {"DUPLEX" , 3, 1, 21, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 22, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 22, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 23, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 23, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 27, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 27, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 32, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 32, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 32, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 33, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 33, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 34, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 35, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 35, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 36, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 2, 36, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 36, "RAZ", 1, 1, 0, 0},
- {"RX" , 0, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 37, "RAZ", 1, 1, 0, 0},
- {"TX" , 4, 2, 37, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 37, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 38, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 38, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 39, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 39, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 39, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 40, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 40, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 6, 41, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_63" , 6, 58, 41, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 6, 60, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 2, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 61, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 64, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 64, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 64, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 64, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 64, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 64, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 64, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 65, "RAZ", 1, 1, 0, 0},
- {"UNDFLW" , 2, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 65, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 65, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 65, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 65, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 65, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 68, "RAZ", 1, 1, 0, 0},
- {"BP" , 4, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 68, "RAZ", 1, 1, 0, 0},
- {"EN" , 8, 2, 68, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 68, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 1, 71, "R/W", 0, 0, 0ull, 0ull},
- {"CLKRST" , 1, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"ENABLE" , 2, 1, 71, "R/W", 0, 0, 1ull, 1ull},
- {"COMP" , 3, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"DLLRST" , 4, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_SET" , 8, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_14" , 13, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKTX_BYP" , 15, 1, 71, "R/W", 0, 1, 1ull, 0},
- {"CLKRX_SET" , 16, 5, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_22" , 21, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CLKRX_BYP" , 23, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"CLK_SET" , 24, 5, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_NCTL" , 32, 6, 71, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_38_39" , 38, 2, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_PCTL" , 40, 6, 71, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_46_47" , 46, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_NCTL" , 48, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_54_55" , 54, 2, 71, "RAZ", 1, 1, 0, 0},
- {"CMP_PCTL" , 56, 6, 71, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 71, "RAZ", 1, 1, 0, 0},
- {"DRV_BYP" , 63, 1, 71, "R/W", 0, 0, 1ull, 0ull},
- {"ACK" , 0, 1, 72, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 72, "RAZ", 1, 1, 0, 0},
- {"ACK" , 0, 1, 73, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 73, "RAZ", 1, 1, 0, 0},
- {"ACK" , 0, 1, 74, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 74, "RAZ", 1, 1, 0, 0},
- {"ACK" , 0, 1, 75, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 75, "RAZ", 1, 1, 0, 0},
- {"GPIO" , 0, 16, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 76, "RAZ", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 77, "RAZ", 1, 0, 0, 0ull},
- {"GPIO" , 0, 16, 78, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 78, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 79, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 79, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 79, "R/W", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 79, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 79, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 79, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 79, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 79, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 79, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 80, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 80, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 80, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 80, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 81, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 81, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 81, "R/W1", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 81, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 81, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 81, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 81, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 81, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 81, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 82, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 82, "RAZ", 0, 0, 0ull, 0ull},
- {"MBOX" , 0, 4, 83, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 83, "RAZ", 1, 0, 0, 0ull},
- {"MBOX" , 0, 4, 84, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 84, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 85, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 85, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 86, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 86, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 87, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 87, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 88, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 88, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 88, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 88, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 88, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 88, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 88, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 88, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 88, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 89, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 89, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 89, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 89, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 89, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 89, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 89, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 89, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 89, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 90, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 90, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 90, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 90, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 90, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 90, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 90, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 90, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 90, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 91, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 91, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 91, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 91, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 91, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 91, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 91, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 92, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 92, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 92, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 92, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 92, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 92, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 92, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 93, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 93, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 93, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 93, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 93, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 93, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 93, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 94, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 94, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 94, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 94, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 94, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 94, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 94, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 94, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 94, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 94, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 95, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 95, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 95, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 95, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 95, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 95, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 95, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 95, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 95, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 95, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 95, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 96, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 96, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 96, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 96, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 96, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 96, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 96, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 96, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 96, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 96, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 96, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 97, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 98, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 98, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 99, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 99, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 100, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 101, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 102, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 103, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 103, "RAZ", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 104, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 104, "RAZ", 1, 0, 0, 0ull},
- {"GPIO" , 0, 16, 105, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 105, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 106, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 106, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 106, "R/W", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 106, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 106, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 106, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 106, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 106, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 106, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 107, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 107, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 107, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 107, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 107, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 107, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 107, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 107, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 107, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 108, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 108, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 108, "R/W1", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 108, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 108, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 108, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 108, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 108, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 108, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 109, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 109, "RAZ", 0, 0, 0ull, 0ull},
- {"MBOX" , 0, 4, 110, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 110, "RAZ", 1, 0, 0, 0ull},
- {"MBOX" , 0, 4, 111, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 111, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 112, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 113, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 113, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 114, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 114, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 115, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 115, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 115, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 115, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 115, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 115, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 115, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 115, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 115, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 116, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 116, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 116, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 116, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 116, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 116, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 116, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 116, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 117, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 117, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 117, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 117, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 117, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 117, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 117, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 117, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 117, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 118, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 118, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 118, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 118, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 118, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 118, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 119, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 119, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 119, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 119, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 119, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 119, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 120, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 120, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 120, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 120, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 120, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 120, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 120, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 121, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 121, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 121, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 121, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 121, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 121, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 121, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 121, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 121, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 121, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 122, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 122, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 122, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 122, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 122, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 122, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 122, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 122, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 122, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 122, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 122, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 123, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 123, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 123, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 123, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 123, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 123, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 123, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 123, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 123, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 123, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 123, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 124, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 124, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 125, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 125, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 126, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 126, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 127, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 128, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 129, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 130, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 130, "RAZ", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 131, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 131, "RAZ", 1, 0, 0, 0ull},
- {"GPIO" , 0, 16, 132, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 132, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 133, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 133, "R/W", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 133, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 133, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 133, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 133, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 134, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 134, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 134, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 134, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 135, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 135, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 135, "R/W1", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 135, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 135, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 135, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 135, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 135, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 135, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 136, "RAZ", 0, 0, 0ull, 0ull},
- {"MBOX" , 0, 4, 137, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 137, "RAZ", 1, 0, 0, 0ull},
- {"MBOX" , 0, 4, 138, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 138, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 139, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 139, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 140, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 140, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 141, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 141, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 142, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 142, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 142, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 142, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 142, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 142, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 142, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 142, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 143, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 143, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 143, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 143, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 143, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 143, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 143, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 143, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 143, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 144, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 144, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 144, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 144, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 144, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 144, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 144, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 144, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 144, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 145, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 145, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 145, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 145, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 145, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 145, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 146, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 146, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 146, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 146, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 146, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 146, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 146, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 147, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 147, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 147, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 147, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 147, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 147, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 147, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 148, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 148, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 148, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 148, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 148, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 148, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 148, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 148, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 148, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 148, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 148, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 149, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 149, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 149, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 149, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 149, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 149, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 149, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 149, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 149, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 149, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 150, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 150, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 150, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 150, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 150, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 150, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 150, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 150, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 150, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 150, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 150, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 151, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 152, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 152, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 153, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 153, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 154, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 155, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 156, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 157, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 157, "RAZ", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 158, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 158, "RAZ", 1, 0, 0, 0ull},
- {"GPIO" , 0, 16, 159, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 159, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 160, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 160, "R/W", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 160, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 160, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 160, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 161, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 161, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 161, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 161, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 161, "RAZ", 1, 1, 0, 0},
- {"PCI_INTR" , 0, 4, 162, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 162, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 162, "R/W1", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 162, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 162, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 162, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 162, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 162, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 162, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 163, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 163, "RAZ", 0, 0, 0ull, 0ull},
- {"MBOX" , 0, 4, 164, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 164, "RAZ", 1, 0, 0, 0ull},
- {"MBOX" , 0, 4, 165, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 165, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 166, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 166, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 167, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 167, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 168, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 168, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 169, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 169, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 169, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 169, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 169, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 169, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 169, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 169, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 169, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 170, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 170, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 170, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 170, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 170, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 170, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 170, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 170, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 170, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 0, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 171, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 171, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 171, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 171, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 171, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 171, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 171, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 171, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 171, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 172, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 172, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 172, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 172, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 172, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 172, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 172, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 173, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 173, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 173, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 173, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 173, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 173, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 173, "RAZ", 1, 1, 0, 0},
- {"AGX" , 0, 5, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 174, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 174, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 174, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 174, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 174, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 174, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 174, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 175, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 175, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 175, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 175, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 175, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 175, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 175, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 175, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 175, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 175, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 175, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 176, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 176, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 176, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 176, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 176, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 176, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 176, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 176, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 176, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 176, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 177, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 177, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 177, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 177, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 177, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 177, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 177, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 177, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 177, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 177, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 177, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 178, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 178, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 179, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 179, "RAZ", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 32, 180, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 180, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 181, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 182, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 183, "R/W1", 0, 0, 0ull, 0ull},
- {"READY" , 0, 1, 184, "RO", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 184, "RAZ", 1, 1, 0, 0},
- {"ECC_ENA" , 0, 1, 185, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND" , 1, 2, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 185, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 186, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 186, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 186, "RAZ", 1, 1, 0, 0},
- {"SYNDROM" , 4, 9, 186, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 186, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 16, 7, 186, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 186, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 3, 187, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_3_63" , 3, 61, 187, "RAZ", 1, 1, 0, 0},
- {"MSI_RCV" , 0, 1, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 188, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 189, "RAZ", 1, 1, 0, 0},
- {"IP_NUM" , 4, 2, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 189, "RAZ", 1, 1, 0, 0},
- {"PP_NUM" , 8, 5, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 189, "RAZ", 1, 1, 0, 0},
- {"MSI_NUM" , 0, 8, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 190, "RAZ", 1, 1, 0, 0},
- {"NEWINT" , 16, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 190, "RAZ", 1, 1, 0, 0},
- {"INTR" , 20, 1, 190, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 190, "RAZ", 1, 1, 0, 0},
- {"MSI_NUM" , 0, 8, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 191, "RAZ", 1, 1, 0, 0},
- {"NEWINT" , 16, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 191, "RAZ", 1, 1, 0, 0},
- {"INTR" , 20, 1, 191, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 191, "RAZ", 1, 1, 0, 0},
- {"MSI_NUM" , 0, 8, 192, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 192, "RAZ", 1, 1, 0, 0},
- {"NEWINT" , 16, 1, 192, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 192, "RAZ", 1, 1, 0, 0},
- {"INTR" , 20, 1, 192, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 192, "RAZ", 1, 1, 0, 0},
- {"GPIO" , 0, 16, 193, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 193, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 194, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 194, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 194, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 194, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 194, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 194, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 195, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 195, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 196, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 196, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 196, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 196, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 196, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 196, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 196, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 196, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 196, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 197, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 197, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 197, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 197, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 197, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 197, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 197, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 197, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 198, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 198, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 198, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 198, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 198, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 198, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 198, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 198, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 198, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 198, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 199, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 199, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 200, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 201, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 201, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 202, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 202, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 202, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 202, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 202, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 202, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 202, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 202, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 202, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 203, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 203, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 204, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 204, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 204, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 204, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 204, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 204, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 204, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 204, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 204, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 205, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 205, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 205, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 205, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 205, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 205, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 205, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 206, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 206, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 206, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 206, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 206, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 206, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 206, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 206, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 206, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 206, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 206, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 207, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 207, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 208, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 209, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 209, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 210, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 210, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 210, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 210, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 210, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 210, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 211, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 211, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 212, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 212, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 212, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 212, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 212, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 212, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 212, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 212, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 212, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 212, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 212, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 212, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 213, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 213, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 213, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 213, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 213, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 213, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 213, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 213, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 213, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 214, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 214, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 214, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 214, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 214, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 214, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 214, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 214, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 214, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 214, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 214, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 215, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 215, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 216, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 217, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 218, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 218, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 218, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 218, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 218, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 218, "RAZ", 1, 1, 0, 0},
- {"LMC" , 0, 4, 219, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 219, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 220, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 220, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 220, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 220, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 220, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 220, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 220, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 220, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 220, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 220, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 220, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 220, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 221, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 221, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 221, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 221, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 221, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 221, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 221, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 221, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 221, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 222, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 222, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 222, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 222, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 222, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 222, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 222, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 222, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 222, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 222, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 222, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 223, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 223, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 224, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 225, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 226, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 226, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 226, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 226, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 226, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 226, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 227, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 227, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 228, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 228, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 229, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 229, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 229, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 229, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 229, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 229, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 229, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 229, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 229, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 230, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 230, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 230, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 230, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 230, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 230, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 230, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 231, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 231, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 231, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 231, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 231, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 231, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 231, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 231, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 231, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 231, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 232, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 232, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 233, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 234, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 234, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 235, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 235, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 235, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 235, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 235, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 236, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 236, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 237, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 237, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 238, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 238, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 238, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 238, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 238, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 238, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 238, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 238, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 238, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 239, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 239, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 239, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 239, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 239, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 239, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 239, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 240, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 240, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 240, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 240, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 240, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 240, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 240, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 240, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 240, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 240, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 241, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 241, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 242, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 243, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 243, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 244, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 244, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 244, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 244, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 244, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 245, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 245, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 246, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 246, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 247, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 247, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 247, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 247, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 247, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 247, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 247, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 247, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 247, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 248, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 248, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 248, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 248, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 248, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 248, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 248, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 249, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 249, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 249, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 249, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 249, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 249, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 249, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 249, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 249, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 249, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 250, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 250, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 251, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 0, 16, 252, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 252, "RAZ", 0, 0, 0ull, 0ull},
- {"PCI_INTR" , 0, 4, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 253, "RAZ", 1, 1, 0, 0},
- {"PCI_MSI" , 8, 4, 253, "RO", 0, 0, 0ull, 0ull},
- {"MSIRED" , 12, 1, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 253, "RAZ", 1, 1, 0, 0},
- {"PCI_INTA" , 16, 2, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 253, "RAZ", 1, 1, 0, 0},
- {"PEM" , 32, 2, 253, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 253, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 0, 4, 254, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 254, "RAZ", 0, 0, 0ull, 0ull},
- {"LMC" , 0, 4, 255, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 255, "RAZ", 1, 1, 0, 0},
- {"IPDPPTHR" , 0, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"SSOIQ" , 1, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"IPD_DRP" , 2, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 256, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 8, 4, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 256, "RAZ", 1, 1, 0, 0},
- {"NAND" , 16, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 17, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"BOOTDMA" , 18, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_31" , 19, 13, 256, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 32, 2, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 256, "RAZ", 1, 1, 0, 0},
- {"UART" , 36, 2, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 256, "RAZ", 1, 1, 0, 0},
- {"USB_UCTL" , 40, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_43" , 41, 3, 256, "RAZ", 1, 1, 0, 0},
- {"USB_HCI" , 44, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 256, "RAZ", 1, 1, 0, 0},
- {"PTP" , 48, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_62" , 49, 14, 256, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 256, "RO", 0, 0, 0ull, 0ull},
- {"AGX" , 0, 5, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 257, "RAZ", 1, 1, 0, 0},
- {"GMX_DRP" , 8, 5, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 257, "RAZ", 1, 1, 0, 0},
- {"AGL" , 32, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_33_39" , 33, 7, 257, "RAZ", 1, 1, 0, 0},
- {"MII" , 40, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 257, "RAZ", 1, 1, 0, 0},
- {"ILK" , 48, 1, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 257, "RAZ", 1, 1, 0, 0},
- {"ILK_DRP" , 52, 2, 257, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 257, "RAZ", 1, 1, 0, 0},
- {"IOB" , 0, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 258, "RAZ", 1, 1, 0, 0},
- {"FPA" , 4, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 5, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 6, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 7, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 258, "RAZ", 1, 1, 0, 0},
- {"SSO" , 16, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 258, "RAZ", 1, 1, 0, 0},
- {"ZIP" , 24, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_27" , 25, 3, 258, "RAZ", 1, 1, 0, 0},
- {"TIM" , 28, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 29, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 30, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 258, "RAZ", 1, 1, 0, 0},
- {"SLI" , 32, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 33, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_34_35" , 34, 2, 258, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 36, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 258, "RAZ", 1, 1, 0, 0},
- {"DFA" , 40, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_47" , 41, 7, 258, "RAZ", 1, 1, 0, 0},
- {"L2C" , 48, 1, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_49_51" , 49, 3, 258, "RAZ", 1, 1, 0, 0},
- {"TRACE" , 52, 4, 258, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 258, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 32, 259, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 259, "RAZ", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 64, 260, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 1, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 2, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 3, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"IO" , 4, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"MEM" , 5, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"PKT" , 6, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 7, 1, 261, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_59" , 8, 52, 261, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 60, 4, 261, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 1, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 2, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 3, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"IO" , 4, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"MEM" , 5, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"PKT" , 6, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 7, 1, 262, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_59" , 8, 52, 262, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 60, 4, 262, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 1, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 2, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 3, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"IO" , 4, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"MEM" , 5, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"PKT" , 6, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 7, 1, 263, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_59" , 8, 52, 263, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 60, 4, 263, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 1, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 2, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 3, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"IO" , 4, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"MEM" , 5, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"PKT" , 6, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 7, 1, 264, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_59" , 8, 52, 264, "RAZ", 1, 1, 0, 0},
- {"MBOX" , 60, 4, 264, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 7, 265, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 265, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 32, 266, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 266, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 32, 267, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 267, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 268, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 268, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 5, 269, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 269, "RAZ", 1, 1, 0, 0},
- {"IRQ" , 8, 2, 269, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 269, "RAZ", 1, 1, 0, 0},
- {"SEL" , 16, 3, 269, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_19_63" , 19, 45, 269, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 270, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 271, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 271, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 32, 272, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 272, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 273, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 273, "RAZ", 1, 1, 0, 0},
- {"PP_BIST" , 0, 32, 274, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 274, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 32, 275, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 276, "R/W", 1, 1, 0, 0},
- {"RST0" , 0, 1, 277, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 31, 277, "R/W", 0, 0, 2147483647ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 277, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 278, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 278, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 278, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 278, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 278, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 278, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 278, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 278, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 279, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 279, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 279, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 279, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 279, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 279, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 279, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 279, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 279, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 280, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 280, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 280, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 280, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 280, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 280, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 280, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 280, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 280, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 281, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 281, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 281, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 281, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 281, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 281, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 281, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 281, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 281, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 282, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 282, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 282, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 282, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 282, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 282, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 282, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 282, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 282, "R/W", 0, 1, 0ull, 0},
- {"BYPASS" , 0, 4, 283, "R/W", 0, 1, 0ull, 0},
- {"MUX_SEL" , 4, 3, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 283, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_15" , 11, 5, 283, "RAZ", 1, 1, 0, 0},
- {"BYPASS_EXT" , 16, 1, 283, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 283, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 284, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 284, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_39" , 37, 3, 284, "RAZ", 1, 1, 0, 0},
- {"SELECT" , 40, 5, 284, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_60" , 45, 16, 284, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 284, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 284, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 284, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 285, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 285, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 286, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 286, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 287, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 287, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 288, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 288, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 289, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 289, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 289, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 290, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 290, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 290, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 290, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 290, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 290, "RAZ", 1, 1, 0, 0},
- {"PDB" , 0, 3, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"RDF" , 4, 3, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"DTX" , 8, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"DTX1" , 10, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"DTX2" , 12, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"STX" , 16, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"STX1" , 18, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"STX2" , 20, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"GFB" , 24, 3, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_27" , 27, 1, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"MRP" , 28, 2, 291, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 291, "RAZ", 0, 0, 0ull, 0ull},
- {"GFU" , 0, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"GIB" , 1, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"GIF" , 2, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"NCD" , 3, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"GUTP" , 4, 3, 292, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"GUTV" , 8, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"CRQ" , 9, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"RAM1" , 10, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"RAM2" , 11, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"RAM3" , 12, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC1RAM1" , 13, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC1RAM2" , 14, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC1RAM3" , 15, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC2RAM1" , 16, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC2RAM2" , 17, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DC2RAM3" , 18, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DLC0RAM" , 19, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"DLC1RAM" , 20, 1, 292, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 292, "RAZ", 0, 0, 0ull, 0ull},
- {"DTECLKDIS" , 0, 1, 293, "R/W", 0, 0, 1ull, 0ull},
- {"CLDTECRIP" , 1, 3, 293, "R/W", 0, 0, 0ull, 0ull},
- {"CLMSKCRIP" , 4, 4, 293, "R/W", 0, 0, 0ull, 0ull},
- {"REPL_ENA" , 8, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"DLCSTART_BIST" , 9, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"DLCCLEAR_BIST" , 10, 1, 293, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 293, "RAZ", 1, 1, 0, 0},
- {"IMODE" , 0, 1, 294, "R/W", 0, 0, 1ull, 1ull},
- {"QMODE" , 1, 1, 294, "R/W", 0, 0, 1ull, 1ull},
- {"PMODE" , 2, 1, 294, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_4" , 3, 2, 294, "RAZ", 1, 1, 0, 0},
- {"SBDLCK" , 5, 1, 294, "R/W", 0, 0, 0ull, 0ull},
- {"SBDNUM" , 6, 6, 294, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 294, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 20, 295, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 295, "RAZ", 1, 1, 0, 0},
- {"SBD0" , 0, 64, 296, "RO", 1, 1, 0, 0},
- {"SBD1" , 0, 64, 297, "RO", 1, 1, 0, 0},
- {"SBD2" , 0, 64, 298, "RO", 1, 1, 0, 0},
- {"SBD3" , 0, 64, 299, "RO", 1, 1, 0, 0},
- {"SIZE" , 0, 9, 300, "R/W", 0, 1, 3ull, 0},
- {"POOL" , 9, 3, 300, "R/W", 0, 1, 0ull, 0},
- {"DWBCNT" , 12, 8, 300, "R/W", 0, 1, 1ull, 0},
- {"MSEGBASE" , 20, 6, 300, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 300, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 301, "RAZ", 1, 1, 0, 0},
- {"RDPTR" , 5, 35, 301, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 301, "RAZ", 1, 1, 0, 0},
- {"RAM1FADR" , 0, 14, 302, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 302, "RAZ", 1, 1, 0, 0},
- {"RAM2FADR" , 16, 9, 302, "RO", 1, 1, 0, 0},
- {"RESERVED_25_31" , 25, 7, 302, "RAZ", 1, 1, 0, 0},
- {"RAM3FADR" , 32, 12, 302, "RO", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 302, "RAZ", 1, 1, 0, 0},
- {"DBLOVF" , 0, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC0PERR" , 1, 3, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC1PERR" , 4, 3, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC2PERR" , 7, 3, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_12" , 10, 3, 303, "RAZ", 1, 1, 0, 0},
- {"DLC0_OVFERR" , 13, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"DLC1_OVFERR" , 14, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 303, "RAZ", 1, 1, 0, 0},
- {"CNDRD" , 16, 1, 303, "RO", 0, 0, 0ull, 0ull},
- {"DFANXM" , 17, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"REPLERR" , 18, 1, 303, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 303, "RAZ", 1, 1, 0, 0},
- {"DBLINA" , 0, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"DC0PENA" , 1, 3, 304, "R/W", 0, 0, 0ull, 0ull},
- {"DC1PENA" , 4, 3, 304, "R/W", 0, 0, 0ull, 0ull},
- {"DC2PENA" , 7, 3, 304, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_12" , 10, 3, 304, "RAZ", 1, 1, 0, 0},
- {"DLC0_OVFENA" , 13, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"DLC1_OVFENA" , 14, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_15_16" , 15, 2, 304, "RAZ", 1, 1, 0, 0},
- {"DFANXMENA" , 17, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"REPLERRENA" , 18, 1, 304, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 304, "RAZ", 1, 1, 0, 0},
- {"HIDAT" , 0, 64, 305, "R/W", 1, 1, 0, 0},
- {"PFCNT0" , 0, 64, 306, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 307, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 307, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 307, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 307, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 307, "RAZ", 1, 1, 0, 0},
- {"PFCNT1" , 0, 64, 308, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 309, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 309, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 309, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 309, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 309, "RAZ", 1, 1, 0, 0},
- {"PFCNT2" , 0, 64, 310, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 311, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 311, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 311, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 311, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 311, "RAZ", 1, 1, 0, 0},
- {"PFCNT3" , 0, 64, 312, "R/W", 0, 1, 0ull, 0},
- {"CLNUM" , 0, 2, 313, "R/W", 0, 0, 0ull, 0ull},
- {"CLDTE" , 2, 4, 313, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 313, "RAZ", 1, 1, 0, 0},
- {"EVSEL" , 8, 6, 313, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_63" , 14, 50, 313, "RAZ", 1, 1, 0, 0},
- {"CNT0ENA" , 0, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1ENA" , 1, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2ENA" , 2, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3ENA" , 3, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0WCLR" , 4, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1WCLR" , 5, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2WCLR" , 6, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3WCLR" , 7, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT0RCLR" , 8, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT1RCLR" , 9, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT2RCLR" , 10, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"CNT3RCLR" , 11, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"SNODE" , 12, 3, 314, "R/W", 0, 0, 0ull, 0ull},
- {"ENODE" , 15, 3, 314, "R/W", 0, 0, 0ull, 0ull},
- {"EDNODE" , 18, 2, 314, "R/W", 0, 0, 0ull, 0ull},
- {"PMODE" , 20, 1, 314, "R/W", 0, 0, 0ull, 0ull},
- {"VGID" , 21, 8, 314, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 314, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 45, 315, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_63" , 45, 19, 315, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 316, "R/W", 0, 0, 0ull, 1ull},
- {"CLK" , 1, 1, 316, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 316, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 317, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 317, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 317, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 318, "WO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 318, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 319, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 319, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 320, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 33, 320, "R/W", 0, 1, 0ull, 0},
- {"IDLE" , 40, 1, 320, "RO", 0, 1, 1ull, 0},
- {"RESERVED_41_47" , 41, 7, 320, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 48, 14, 320, "R/W", 0, 1, 64ull, 0},
- {"RESERVED_62_63" , 62, 2, 320, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 3, 321, "R/W", 0, 0, 6ull, 6ull},
- {"RESERVED_3_63" , 3, 61, 321, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 40, 322, "RO", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 322, "RAZ", 1, 1, 0, 0},
- {"STATE" , 0, 64, 323, "RO", 0, 1, 0ull, 0},
- {"STATE" , 0, 64, 324, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_13" , 0, 14, 325, "RAZ", 1, 1, 0, 0},
- {"O_MODE" , 14, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 325, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 325, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 325, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 325, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_47" , 34, 14, 325, "RAZ", 1, 1, 0, 0},
- {"DMA_ENB" , 48, 6, 325, "R/W", 0, 0, 0ull, 63ull},
- {"RESERVED_54_55" , 54, 2, 325, "RAZ", 1, 1, 0, 0},
- {"PKT_EN" , 56, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"PKT_HP" , 57, 1, 325, "RO", 0, 0, 0ull, 0ull},
- {"COMMIT_MODE" , 58, 1, 325, "R/W", 0, 0, 0ull, 1ull},
- {"FFP_DIS" , 59, 1, 325, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_EN1" , 60, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"DICI_MODE" , 61, 1, 325, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 325, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 326, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 326, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 327, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 327, "RAZ", 1, 1, 0, 0},
- {"BLKS" , 0, 4, 328, "R/W", 0, 1, 2ull, 0},
- {"BASE" , 4, 5, 328, "RO", 1, 1, 0, 0},
- {"RESERVED_9_31" , 9, 23, 328, "RAZ", 1, 1, 0, 0},
- {"COMPBLKS" , 32, 5, 328, "RO", 1, 1, 0, 0},
- {"RESERVED_37_63" , 37, 27, 328, "RAZ", 1, 1, 0, 0},
- {"RSL" , 0, 1, 329, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB" , 1, 1, 329, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 329, "RAZ", 1, 1, 0, 0},
- {"FFP" , 4, 4, 329, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 329, "RAZ", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 330, "R/W", 0, 0, 0ull, 0ull},
- {"DMADBO" , 8, 8, 330, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 330, "R/W", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 330, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 330, "R/W", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 331, "RAZ", 1, 1, 0, 0},
- {"DMADBO" , 8, 8, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 331, "RAZ", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 331, "RAZ", 1, 1, 0, 0},
- {"MOLR" , 0, 6, 332, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 332, "RAZ", 1, 1, 0, 0},
- {"SINFO" , 0, 6, 333, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 333, "RAZ", 1, 1, 0, 0},
- {"IINFO" , 8, 6, 333, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 333, "RAZ", 1, 1, 0, 0},
- {"PKTERR" , 0, 1, 334, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 334, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 335, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 335, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 336, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 336, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 337, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 337, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 338, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 338, "RAZ", 1, 1, 0, 0},
- {"EN_RSP" , 0, 8, 339, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 339, "RAZ", 1, 1, 0, 0},
- {"EN_RST" , 16, 8, 339, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 339, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 340, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 340, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 2, 341, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 341, "RAZ", 1, 1, 0, 0},
- {"MRRS_LIM" , 3, 1, 341, "R/W", 0, 0, 0ull, 0ull},
- {"MPS" , 4, 1, 341, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 341, "RAZ", 1, 1, 0, 0},
- {"MPS_LIM" , 7, 1, 341, "R/W", 0, 0, 0ull, 0ull},
- {"MOLR" , 8, 6, 341, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_14_15" , 14, 2, 341, "RAZ", 1, 1, 0, 0},
- {"RD_MODE" , 16, 1, 341, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 341, "RAZ", 1, 1, 0, 0},
- {"QLM_CFG" , 20, 1, 341, "RO", 1, 1, 0, 0},
- {"RESERVED_21_23" , 21, 3, 341, "RAZ", 1, 1, 0, 0},
- {"HALT" , 24, 1, 341, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 341, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 342, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 342, "RO", 0, 1, 0ull, 0},
- {"REQQ" , 0, 3, 343, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 343, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 4, 1, 343, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 343, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 8, 1, 343, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 343, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 344, "RO", 0, 1, 0ull, 0},
- {"POOL" , 33, 5, 344, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 344, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 345, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 345, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 345, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 345, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 345, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 345, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 346, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 346, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 346, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 346, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 346, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 346, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OFF" , 18, 1, 346, "R/W", 0, 0, 0ull, 0ull},
- {"RET_OFF" , 19, 1, 346, "R/W", 0, 0, 0ull, 0ull},
- {"FREE_EN" , 20, 1, 346, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 346, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 347, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 347, "R/W", 0, 0, 164ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 347, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 348, "R/W", 0, 0, 224ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 348, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 349, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 349, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 349, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 350, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 350, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 351, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 351, "R/W", 0, 0, 164ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 351, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 352, "R/W", 0, 0, 224ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 352, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"FREE8" , 44, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q8_UND" , 45, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q8_COFF" , 46, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"Q8_PERR" , 47, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"POOL8TH" , 48, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"PADDR_E" , 49, 1, 353, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_63" , 50, 14, 353, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE8" , 44, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q8_UND" , 45, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q8_COFF" , 46, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q8_PERR" , 47, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL8TH" , 48, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"PADDR_E" , 49, 1, 354, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_50_63" , 50, 14, 354, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 32, 355, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 355, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 356, "R/W", 0, 1, 8589934591ull, 0},
- {"RESERVED_33_63" , 33, 31, 356, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 357, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 357, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 32, 358, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 358, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 32, 359, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 359, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 360, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 360, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 361, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 361, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 362, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 362, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 362, "RO", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 363, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 363, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 363, "RO", 0, 0, 0ull, 7ull},
- {"THRESH" , 0, 32, 364, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 364, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 365, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 365, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 365, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 365, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 366, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 366, "RAZ", 1, 1, 0, 0},
- {"BPID" , 0, 6, 367, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 367, "RAZ", 1, 1, 0, 0},
- {"VAL" , 8, 1, 367, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 367, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 16, 1, 367, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 367, "RAZ", 1, 1, 0, 0},
- {"MSK_AND" , 0, 16, 368, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 368, "RAZ", 1, 1, 0, 0},
- {"MSK_OR" , 32, 16, 368, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 368, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 369, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 369, "RAZ", 1, 1, 0, 0},
- {"DIS" , 0, 16, 370, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 370, "RAZ", 1, 1, 0, 0},
- {"MSK" , 0, 16, 371, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 371, "RAZ", 1, 1, 0, 0},
- {"LOGL_EN" , 0, 16, 372, "R/W", 0, 1, 65535ull, 0},
- {"PHYS_EN" , 16, 1, 372, "R/W", 0, 1, 1ull, 0},
- {"HG2RX_EN" , 17, 1, 372, "R/W", 0, 0, 0ull, 0ull},
- {"HG2TX_EN" , 18, 1, 372, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 372, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 373, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 373, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 373, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 3, 373, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 373, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 4, 373, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 373, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 374, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_15" , 6, 10, 374, "RAZ", 1, 1, 0, 0},
- {"PIPE" , 16, 7, 374, "RO", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 374, "RAZ", 1, 1, 0, 0},
- {"STOP" , 0, 4, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 375, "RAZ", 1, 1, 0, 0},
- {"BP" , 8, 4, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 375, "RAZ", 1, 1, 0, 0},
- {"OVR" , 16, 4, 375, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 375, "RAZ", 1, 1, 0, 0},
- {"RX_EN" , 0, 1, 376, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EN" , 1, 1, 376, "R/W", 0, 0, 0ull, 0ull},
- {"DRP_EN" , 2, 1, 376, "R/W", 0, 0, 0ull, 0ull},
- {"BCK_EN" , 3, 1, 376, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 376, "RAZ", 1, 1, 0, 0},
- {"PHYS_BP" , 16, 16, 376, "R/W", 0, 1, 65535ull, 0},
- {"LOGL_EN" , 32, 16, 376, "R/W", 0, 0, 255ull, 255ull},
- {"PHYS_EN" , 48, 16, 376, "R/W", 0, 0, 255ull, 255ull},
- {"EN" , 0, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 377, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 377, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 377, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 377, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 377, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 377, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 377, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 377, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_15" , 14, 2, 377, "RAZ", 1, 1, 0, 0},
- {"PKND" , 16, 6, 377, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 377, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 378, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 379, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 380, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 381, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 382, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 383, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 32, 384, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 384, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 385, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 385, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 386, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 386, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 386, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 386, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 387, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 387, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 388, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 388, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 388, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 388, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 388, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 388, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 388, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 388, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 388, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 389, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 389, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 389, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 389, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 389, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 389, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 389, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 389, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 389, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 389, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 390, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 390, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 391, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 391, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 391, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 391, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 391, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 391, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 392, "R/W1C", 0, 1, 0ull, 0},
- {"CAREXT" , 1, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 392, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 392, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 392, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 392, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 392, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 393, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 393, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 394, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 394, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 395, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 395, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 396, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 396, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 397, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 397, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 398, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 398, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 399, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 399, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 400, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 400, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 401, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 401, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 402, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 402, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 403, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 403, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 404, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 404, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 405, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 405, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 405, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 405, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 406, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 406, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 407, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 407, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 11, 408, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_11_63" , 11, 53, 408, "RAZ", 1, 1, 0, 0},
- {"LGTIM2GO" , 0, 16, 409, "RO", 0, 1, 0ull, 0},
- {"XOF" , 16, 16, 409, "RO", 0, 0, 0ull, 0ull},
- {"PHTIM2GO" , 32, 16, 409, "RO", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 409, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 4, 410, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 410, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 4, 410, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 410, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 411, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 411, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 412, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 412, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 412, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 412, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 412, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 413, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 413, "RAZ", 1, 1, 0, 0},
- {"DISPARITY" , 0, 1, 414, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 414, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 415, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 415, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 0, 1, 416, "R/W", 0, 1, 0ull, 0},
- {"START_BIST" , 1, 1, 416, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 416, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 417, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 417, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 417, "RAZ", 1, 1, 0, 0},
- {"WR_MAGIC" , 0, 1, 418, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 418, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 419, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 419, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 419, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 419, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 419, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 420, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 420, "RAZ", 1, 1, 0, 0},
- {"XOFF" , 0, 16, 421, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 421, "RAZ", 1, 1, 0, 0},
- {"XON" , 0, 16, 422, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 422, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 423, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 423, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 423, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 424, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 424, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 425, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 425, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 426, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 426, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 427, "RO", 1, 1, 0, 0},
- {"MSG_TIME" , 16, 16, 427, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 427, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 428, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 428, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 7, 429, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 429, "RAZ", 1, 1, 0, 0},
- {"NUMP" , 16, 5, 429, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_31" , 21, 11, 429, "RAZ", 1, 1, 0, 0},
- {"IGN_BP" , 32, 1, 429, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 429, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 430, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 430, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 431, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 431, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 432, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 432, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 433, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 433, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 434, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 434, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 435, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 435, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 436, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 436, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 437, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 437, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 438, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 438, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 439, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 439, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 440, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 440, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 441, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 441, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 442, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 442, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 443, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 443, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 10, 444, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_10_63" , 10, 54, 444, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 4, 445, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 445, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 446, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 446, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 4, 447, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_4_63" , 4, 60, 447, "RAZ", 1, 1, 0, 0},
- {"TX_XOF" , 0, 16, 448, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 448, "RAZ", 1, 1, 0, 0},
- {"TX_XON" , 0, 16, 449, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 449, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 450, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 450, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 450, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"PKO_NXP" , 1, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 451, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 451, "R/W", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 451, "R/W", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 451, "R/W", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 451, "R/W", 0, 0, 0ull, 0ull},
- {"XCHANGE" , 24, 1, 451, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 451, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 452, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO_NXP" , 1, 1, 452, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 4, 452, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 452, "RAZ", 0, 0, 0ull, 0ull},
- {"XSCOL" , 8, 4, 452, "R/W1C", 0, 0, 0ull, 0ull},
- {"XSDEF" , 12, 4, 452, "R/W1C", 0, 0, 0ull, 0ull},
- {"LATE_COL" , 16, 4, 452, "R/W1C", 0, 0, 0ull, 0ull},
- {"PTP_LOST" , 20, 4, 452, "R/W1C", 0, 0, 0ull, 0ull},
- {"XCHANGE" , 24, 1, 452, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 452, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 453, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 453, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 454, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 454, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 4, 455, "R/W", 0, 0, 0ull, 0ull},
- {"BP" , 4, 4, 455, "R/W", 0, 0, 0ull, 0ull},
- {"EN" , 8, 4, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 455, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 455, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 455, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 456, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 456, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 457, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 457, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 458, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_5_63" , 5, 59, 458, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 459, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 459, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 459, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 459, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 459, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 459, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 459, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 459, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 459, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 460, "R/W", 0, 0, 6ull, 6ull},
- {"EN" , 4, 1, 460, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 460, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 461, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 461, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 461, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 461, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 461, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 461, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 461, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 461, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCE_SEL" , 15, 2, 461, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 461, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 462, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 462, "RAZ", 1, 1, 0, 0},
- {"LANE_SEL" , 0, 2, 463, "R/W", 0, 0, 0ull, 0ull},
- {"DIV" , 2, 1, 463, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 463, "RAZ", 1, 1, 0, 0},
- {"QLM_SEL" , 8, 3, 463, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 463, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 464, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 464, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 465, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 465, "RAZ", 1, 1, 0, 0},
- {"SEL" , 0, 4, 466, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 466, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 16, 467, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 467, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 16, 468, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 468, "RAZ", 1, 1, 0, 0},
- {"TLK0_TXF0" , 0, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK0_TXF1" , 1, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK0_TXF2" , 2, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK0_STAT0" , 3, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK0_FWC" , 4, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK0_STAT1" , 5, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK1_TXF0" , 6, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK1_TXF1" , 7, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK1_TXF2" , 8, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK1_STAT0" , 9, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK1_FWC" , 10, 1, 469, "RO", 0, 1, 0ull, 0},
- {"TLK1_STAT1" , 11, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLK0_STAT" , 12, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLK0_FWC" , 13, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLK0_STAT1" , 14, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 469, "RAZ", 0, 1, 0ull, 0},
- {"RLK1_STAT" , 16, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLK1_FWC" , 17, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLK1_STAT1" , 18, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RESERVED_19_19" , 19, 1, 469, "RAZ", 0, 1, 0ull, 0},
- {"RLE0_DSK0" , 20, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE0_DSK1" , 21, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE1_DSK0" , 22, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE1_DSK1" , 23, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE2_DSK0" , 24, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE2_DSK1" , 25, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE3_DSK0" , 26, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE3_DSK1" , 27, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE4_DSK0" , 28, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE4_DSK1" , 29, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE5_DSK0" , 30, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE5_DSK1" , 31, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE6_DSK0" , 32, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE6_DSK1" , 33, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE7_DSK0" , 34, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RLE7_DSK1" , 35, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_51" , 36, 16, 469, "RAZ", 0, 1, 0ull, 0},
- {"RXF_MEM0" , 52, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RXF_MEM1" , 53, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RXF_MEM2" , 54, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RXF_PMAP" , 55, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RXF_X2P0" , 56, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RXF_X2P1" , 57, 1, 469, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 469, "RAZ", 0, 1, 0ull, 0},
- {"RXF_XLINK" , 0, 1, 470, "R/W", 0, 1, 0ull, 0},
- {"CCLK_DIS" , 1, 1, 470, "R/W", 0, 1, 0ull, 0},
- {"RESET" , 2, 1, 470, "R/W", 0, 1, 0ull, 0},
- {"RID_RSTDIS" , 3, 1, 470, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 470, "RAZ", 0, 1, 0ull, 0},
- {"RXF_LNK0_PERR" , 0, 1, 471, "R/W1C", 0, 1, 0ull, 0},
- {"RXF_LNK1_PERR" , 1, 1, 471, "R/W1C", 0, 1, 0ull, 0},
- {"RXF_CTL_PERR" , 2, 1, 471, "R/W1C", 0, 1, 0ull, 0},
- {"RXF_POP_EMPTY" , 3, 1, 471, "R/W1C", 0, 1, 0ull, 0},
- {"RXF_PUSH_FULL" , 4, 1, 471, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 471, "RAZ", 0, 1, 0ull, 0},
- {"RXF_LNK0_PERR" , 0, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"RXF_LNK1_PERR" , 1, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"RXF_CTL_PERR" , 2, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"RXF_POP_EMPTY" , 3, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"RXF_PUSH_FULL" , 4, 1, 472, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 472, "RAZ", 0, 1, 0ull, 0},
- {"GBL_INT" , 0, 1, 473, "RO", 0, 1, 0ull, 0},
- {"TLK0_INT" , 1, 1, 473, "RO", 0, 1, 0ull, 0},
- {"TLK1_INT" , 2, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RLK0_INT" , 3, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RLK1_INT" , 4, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RLE0_INT" , 5, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RLE1_INT" , 6, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RLE2_INT" , 7, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RLE3_INT" , 8, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RLE4_INT" , 9, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RLE5_INT" , 10, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RLE6_INT" , 11, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RLE7_INT" , 12, 1, 473, "RO", 0, 1, 0ull, 0},
- {"RESERVED_13_63" , 13, 51, 473, "RAZ", 0, 1, 0ull, 0},
- {"TX_DIS_SCRAM" , 0, 8, 474, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 474, "RAZ", 0, 1, 0ull, 0},
- {"TX_DIS_DISPR" , 16, 8, 474, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_31" , 24, 8, 474, "RAZ", 0, 1, 0ull, 0},
- {"TX_BAD_LANE_SEL" , 32, 8, 474, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_47" , 40, 8, 474, "RAZ", 0, 1, 0ull, 0},
- {"TX_BAD_SCRAM_CNT" , 48, 3, 474, "R/W", 0, 1, 0ull, 0},
- {"TX_BAD_SYNC_CNT" , 51, 3, 474, "R/W", 0, 1, 0ull, 0},
- {"TX_BAD_6467_CNT" , 54, 5, 474, "R/W", 0, 1, 0ull, 0},
- {"TX_BAD_CRC32" , 59, 1, 474, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 474, "RAZ", 0, 1, 0ull, 0},
- {"TX_LNE_STAT" , 0, 8, 475, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_8_15" , 8, 8, 475, "RAZ", 0, 1, 0ull, 0},
- {"TX_LNK_STAT" , 16, 8, 475, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_24_31" , 24, 8, 475, "RAZ", 0, 1, 0ull, 0},
- {"RX_LNE_STAT" , 32, 8, 475, "RO", 0, 1, 0ull, 0},
- {"RESERVED_40_47" , 40, 8, 475, "RAZ", 0, 1, 0ull, 0},
- {"RX_LNK_STAT" , 48, 8, 475, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 475, "RAZ", 0, 1, 0ull, 0},
- {"LANE_ENA" , 0, 8, 476, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 476, "RAZ", 0, 1, 0ull, 0},
- {"CAL_DEPTH" , 16, 9, 476, "R/W", 0, 1, 144ull, 0},
- {"RESERVED_25_25" , 25, 1, 476, "RAZ", 0, 1, 0ull, 0},
- {"BRST_MAX" , 26, 5, 476, "R/W", 0, 1, 4ull, 0},
- {"LANE_REV" , 31, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"BRST_SHRT" , 32, 7, 476, "R/W", 0, 1, 4ull, 0},
- {"MFRM_LEN" , 39, 13, 476, "R/W", 0, 1, 1024ull, 0},
- {"CAL_ENA" , 52, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"MLTUSE_FC_ENA" , 53, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"LNK_STATS_ENA" , 54, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"LNK_STATS_RDCLR" , 55, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"PTRN_MODE" , 56, 1, 476, "RAZ", 0, 1, 0ull, 0},
- {"MPROTO_IGN" , 57, 1, 476, "R/W", 0, 0, 0ull, 0ull},
- {"BCW_PUSH" , 58, 1, 476, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_STATS_WRAP" , 59, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_61" , 60, 2, 476, "RAZ", 0, 1, 0ull, 0},
- {"EXT_LPBK" , 62, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"EXT_LPBK_FC" , 63, 1, 476, "R/W", 0, 1, 0ull, 0},
- {"RX_BDRY_LOCK_ENA" , 0, 8, 477, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 477, "RAZ", 0, 1, 0ull, 0},
- {"RX_ALIGN_ENA" , 16, 1, 477, "R/W", 0, 1, 0ull, 0},
- {"RX_LINK_FC" , 17, 1, 477, "RO", 0, 1, 0ull, 0},
- {"TX_LINK_FC" , 18, 1, 477, "RO", 0, 1, 0ull, 0},
- {"LA_MODE" , 19, 1, 477, "R/W", 0, 1, 0ull, 0},
- {"PKT_ENA" , 20, 1, 477, "R/W", 0, 1, 0ull, 0},
- {"PKT_FLUSH" , 21, 1, 477, "WR0", 0, 1, 0ull, 0},
- {"RX_FIFO_MAX" , 22, 12, 477, "R/W", 0, 1, 1024ull, 0},
- {"RESERVED_34_35" , 34, 2, 477, "RAZ", 0, 1, 0ull, 0},
- {"RX_FIFO_HWM" , 36, 12, 477, "R/W", 0, 1, 512ull, 0},
- {"RESERVED_48_49" , 48, 2, 477, "RAZ", 0, 1, 0ull, 0},
- {"RX_FIFO_CNT" , 50, 12, 477, "RO", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 477, "RAZ", 0, 1, 0ull, 0},
- {"STATUS" , 0, 64, 478, "RO", 0, 1, 0ull, 0},
- {"STATUS" , 0, 64, 479, "RO", 0, 1, 0ull, 0},
- {"INDEX" , 0, 6, 480, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 480, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 8, 6, 480, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 480, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 8, 481, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 481, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 8, 481, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_30" , 24, 7, 481, "RAZ", 0, 1, 0ull, 0},
- {"CLR" , 31, 1, 481, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 481, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 8, 482, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 482, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 8, 482, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_30" , 24, 7, 482, "RAZ", 0, 1, 0ull, 0},
- {"CLR" , 31, 1, 482, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 482, "RAZ", 0, 1, 0ull, 0},
- {"LANE_ALIGN_FAIL" , 0, 1, 483, "R/W1C", 0, 1, 0ull, 0},
- {"CRC24_ERR" , 1, 1, 483, "R/W1C", 0, 1, 0ull, 0},
- {"WORD_SYNC_DONE" , 2, 1, 483, "R/W1C", 0, 1, 0ull, 0},
- {"LANE_ALIGN_DONE" , 3, 1, 483, "R/W1C", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 4, 1, 483, "R/W1C", 0, 1, 0ull, 0},
- {"LANE_BAD_WORD" , 5, 1, 483, "R/W1C", 0, 1, 0ull, 0},
- {"PKT_DROP_RXF" , 6, 1, 483, "R/W1C", 0, 1, 0ull, 0},
- {"PKT_DROP_RID" , 7, 1, 483, "R/W1C", 0, 1, 0ull, 0},
- {"PKT_DROP_SOP" , 8, 1, 483, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 483, "RAZ", 0, 1, 0ull, 0},
- {"LANE_ALIGN_FAIL" , 0, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"CRC24_ERR" , 1, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"WORD_SYNC_DONE" , 2, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"LANE_ALIGN_DONE" , 3, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 4, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"LANE_BAD_WORD" , 5, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"PKT_DROP_RXF" , 6, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"PKT_DROP_RID" , 7, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"PKT_DROP_SOP" , 8, 1, 484, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 484, "RAZ", 0, 1, 0ull, 0},
- {"CNT" , 0, 16, 485, "R/W", 0, 1, 10240ull, 0},
- {"RESERVED_16_63" , 16, 48, 485, "RAZ", 0, 1, 0ull, 0},
- {"PORT_PIPE0" , 0, 7, 486, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL0" , 7, 2, 486, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE1" , 9, 7, 486, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL1" , 16, 2, 486, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE2" , 18, 7, 486, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL2" , 25, 2, 486, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE3" , 27, 7, 486, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL3" , 34, 2, 486, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 486, "RAZ", 0, 1, 0ull, 0},
- {"PORT_PIPE4" , 0, 7, 487, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL4" , 7, 2, 487, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE5" , 9, 7, 487, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL5" , 16, 2, 487, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE6" , 18, 7, 487, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL6" , 25, 2, 487, "R/W", 0, 1, 0ull, 0},
- {"PORT_PIPE7" , 27, 7, 487, "R/W", 0, 1, 0ull, 0},
- {"ENTRY_CTL7" , 34, 2, 487, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 487, "RAZ", 0, 1, 0ull, 0},
- {"RX_PKT" , 0, 28, 488, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 488, "RAZ", 0, 1, 0ull, 0},
- {"RX_BYTES" , 0, 36, 489, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 489, "RAZ", 0, 1, 0ull, 0},
- {"MAX_CNT" , 0, 6, 490, "R/W", 0, 1, 45ull, 0},
- {"RESERVED_6_63" , 6, 58, 490, "RAZ", 0, 1, 0ull, 0},
- {"CRC24_MATCH_CNT" , 0, 33, 491, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 491, "RAZ", 0, 1, 0ull, 0},
- {"CRC24_ERR_CNT" , 0, 18, 492, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 492, "RAZ", 0, 1, 0ull, 0},
- {"BRST_CNT" , 0, 28, 493, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 493, "RAZ", 0, 1, 0ull, 0},
- {"BRST_NOT_FULL_CNT" , 32, 16, 493, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 493, "RAZ", 0, 1, 0ull, 0},
- {"BRST_MAX_ERR_CNT" , 0, 16, 494, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 494, "RAZ", 0, 1, 0ull, 0},
- {"BRST_SHRT_ERR_CNT" , 0, 16, 495, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 495, "RAZ", 0, 1, 0ull, 0},
- {"ALIGN_CNT" , 0, 23, 496, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 496, "RAZ", 0, 1, 0ull, 0},
- {"ALIGN_ERR_CNT" , 0, 16, 497, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 497, "RAZ", 0, 1, 0ull, 0},
- {"BAD_64B67B_CNT" , 0, 16, 498, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 498, "RAZ", 0, 1, 0ull, 0},
- {"PKT_DROP_RXF_CNT" , 0, 16, 499, "R/W", 0, 1, 0ull, 0},
- {"PKT_DROP_RID_CNT" , 16, 16, 499, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 499, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_0_63" , 0, 64, 500, "RAZ", 0, 1, 0ull, 0},
- {"STAT_ENA" , 0, 1, 501, "R/W", 0, 1, 0ull, 0},
- {"STAT_RDCLR" , 1, 1, 501, "R/W", 0, 1, 0ull, 0},
- {"RX_DIS_SCRAM" , 2, 1, 501, "R/W", 0, 0, 0ull, 0ull},
- {"RX_DIS_UKWN" , 3, 1, 501, "R/W", 0, 0, 0ull, 0ull},
- {"RX_BDRY_SYNC" , 4, 1, 501, "RO", 0, 1, 0ull, 0},
- {"RX_SCRM_SYNC" , 5, 1, 501, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 501, "RAZ", 0, 1, 0ull, 0},
- {"RX_DIS_PSH_SKIP" , 8, 1, 501, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 501, "RAZ", 0, 1, 0ull, 0},
- {"SERDES_LOCK_LOSS" , 0, 1, 502, "R/W1C", 0, 1, 0ull, 0},
- {"BDRY_SYNC_LOSS" , 1, 1, 502, "R/W1C", 0, 1, 0ull, 0},
- {"CRC32_ERR" , 2, 1, 502, "R/W1C", 0, 1, 0ull, 0},
- {"UKWN_CNTL_WORD" , 3, 1, 502, "R/W1C", 0, 1, 0ull, 0},
- {"SCRM_SYNC_LOSS" , 4, 1, 502, "R/W1C", 0, 1, 0ull, 0},
- {"DSKEW_FIFO_OVFL" , 5, 1, 502, "R/W1C", 0, 1, 0ull, 0},
- {"STAT_MSG" , 6, 1, 502, "R/W1C", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 7, 1, 502, "R/W1C", 0, 1, 0ull, 0},
- {"BAD_64B67B" , 8, 1, 502, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 502, "RAZ", 0, 1, 0ull, 0},
- {"SERDES_LOCK_LOSS" , 0, 1, 503, "R/W", 0, 1, 0ull, 0},
- {"BDRY_SYNC_LOSS" , 1, 1, 503, "R/W", 0, 1, 0ull, 0},
- {"CRC32_ERR" , 2, 1, 503, "R/W", 0, 1, 0ull, 0},
- {"UKWN_CNTL_WORD" , 3, 1, 503, "R/W", 0, 1, 0ull, 0},
- {"SCRM_SYNC_LOSS" , 4, 1, 503, "R/W", 0, 1, 0ull, 0},
- {"DSKEW_FIFO_OVFL" , 5, 1, 503, "R/W", 0, 1, 0ull, 0},
- {"STAT_MSG" , 6, 1, 503, "R/W", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 7, 1, 503, "R/W", 0, 1, 0ull, 0},
- {"BAD_64B67B" , 8, 1, 503, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 503, "RAZ", 0, 1, 0ull, 0},
- {"SER_LOCK_LOSS_CNT" , 0, 18, 504, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 504, "RAZ", 0, 1, 0ull, 0},
- {"BDRY_SYNC_LOSS_CNT" , 0, 18, 505, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 505, "RAZ", 0, 1, 0ull, 0},
- {"SYNCW_BAD_CNT" , 0, 18, 506, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_31" , 18, 14, 506, "RAZ", 0, 1, 0ull, 0},
- {"SYNCW_GOOD_CNT" , 32, 18, 506, "RO", 0, 1, 0ull, 0},
- {"RESERVED_50_63" , 50, 14, 506, "RAZ", 0, 1, 0ull, 0},
- {"BAD_64B67B_CNT" , 0, 18, 507, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 507, "RAZ", 0, 1, 0ull, 0},
- {"DATA_WORD_CNT" , 0, 27, 508, "RO", 0, 1, 0ull, 0},
- {"RESERVED_27_31" , 27, 5, 508, "RAZ", 0, 1, 0ull, 0},
- {"CNTL_WORD_CNT" , 32, 27, 508, "RO", 0, 1, 0ull, 0},
- {"RESERVED_59_63" , 59, 5, 508, "RAZ", 0, 1, 0ull, 0},
- {"UNKWN_WORD_CNT" , 0, 18, 509, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 509, "RAZ", 0, 1, 0ull, 0},
- {"SCRM_SYNC_LOSS_CNT" , 0, 18, 510, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 510, "RAZ", 0, 1, 0ull, 0},
- {"SCRM_MATCH_CNT" , 0, 18, 511, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 511, "RAZ", 0, 1, 0ull, 0},
- {"SKIPW_GOOD_CNT" , 0, 18, 512, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 512, "RAZ", 0, 1, 0ull, 0},
- {"CRC32_MATCH_CNT" , 0, 27, 513, "RO", 0, 1, 0ull, 0},
- {"RESERVED_27_31" , 27, 5, 513, "RAZ", 0, 1, 0ull, 0},
- {"CRC32_ERR_CNT" , 32, 18, 513, "RO", 0, 1, 0ull, 0},
- {"RESERVED_50_63" , 50, 14, 513, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 9, 514, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_15" , 9, 7, 514, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 9, 514, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 514, "RAZ", 0, 1, 0ull, 0},
- {"PORT_KIND" , 0, 6, 515, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 515, "RAZ", 0, 1, 0ull, 0},
- {"SER_HAUL" , 0, 2, 516, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 516, "RAZ", 0, 1, 0ull, 0},
- {"SER_PWRUP" , 4, 2, 516, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 516, "RAZ", 0, 1, 0ull, 0},
- {"SER_RESET_N" , 8, 8, 516, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_23" , 16, 8, 516, "RAZ", 0, 1, 0ull, 0},
- {"SER_TXPOL" , 24, 8, 516, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 516, "RAZ", 0, 1, 0ull, 0},
- {"SER_RXPOL" , 40, 8, 516, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_55" , 48, 8, 516, "RAZ", 0, 1, 0ull, 0},
- {"SER_RXPOL_AUTO" , 56, 1, 516, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_57_63" , 57, 7, 516, "RAZ", 0, 1, 0ull, 0},
- {"LANE_ENA" , 0, 8, 517, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 517, "RAZ", 0, 1, 0ull, 0},
- {"CAL_DEPTH" , 16, 9, 517, "R/W", 0, 1, 72ull, 0},
- {"RESERVED_25_25" , 25, 1, 517, "RAZ", 0, 1, 0ull, 0},
- {"BRST_MAX" , 26, 5, 517, "R/W", 0, 1, 4ull, 0},
- {"LANE_REV" , 31, 1, 517, "R/W", 0, 1, 0ull, 0},
- {"BRST_SHRT" , 32, 7, 517, "R/W", 0, 1, 4ull, 0},
- {"MFRM_LEN" , 39, 13, 517, "R/W", 0, 1, 1024ull, 0},
- {"CAL_ENA" , 52, 1, 517, "R/W", 0, 1, 0ull, 0},
- {"MLTUSE_FC_ENA" , 53, 1, 517, "R/W", 0, 1, 0ull, 0},
- {"LNK_STATS_ENA" , 54, 1, 517, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_55_55" , 55, 1, 517, "RAZ", 0, 1, 0ull, 0},
- {"PTRN_MODE" , 56, 1, 517, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_57_60" , 57, 4, 517, "RAZ", 0, 1, 0ull, 0},
- {"INT_LPBK" , 61, 1, 517, "R/W", 0, 1, 0ull, 0},
- {"EXT_LPBK" , 62, 1, 517, "R/W", 0, 1, 0ull, 0},
- {"EXT_LPBK_FC" , 63, 1, 517, "R/W", 0, 1, 0ull, 0},
- {"TX_MLTUSE" , 0, 8, 518, "R/W", 0, 1, 0ull, 0},
- {"RMATCH" , 8, 1, 518, "R/W", 0, 1, 0ull, 0},
- {"RX_LINK_FC_IGN" , 9, 1, 518, "R/W", 0, 1, 0ull, 0},
- {"RX_LINK_FC_PKT" , 10, 1, 518, "R/W", 0, 1, 0ull, 0},
- {"TX_LINK_FC_JAM" , 11, 1, 518, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_16" , 12, 5, 518, "RAZ", 0, 1, 0ull, 0},
- {"RX_LINK_FC" , 17, 1, 518, "RO", 0, 1, 0ull, 0},
- {"TX_LINK_FC" , 18, 1, 518, "RO", 0, 1, 0ull, 0},
- {"LA_MODE" , 19, 1, 518, "R/W", 0, 1, 0ull, 0},
- {"PKT_ENA" , 20, 1, 518, "R/W", 0, 1, 1ull, 0},
- {"PKT_FLUSH" , 21, 1, 518, "R/W", 0, 1, 0ull, 0},
- {"SKIP_CNT" , 22, 4, 518, "R/W", 0, 1, 1ull, 0},
- {"PTP_DELAY" , 26, 5, 518, "R/W", 0, 1, 26ull, 0},
- {"PIPE_CRD_DIS" , 31, 1, 518, "R/W", 0, 1, 0ull, 0},
- {"PKT_BUSY" , 32, 1, 518, "RO", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 518, "RAZ", 0, 1, 0ull, 0},
- {"TX_BAD_CTLW1" , 0, 1, 519, "R/W", 0, 1, 0ull, 0},
- {"TX_BAD_CTLW2" , 1, 1, 519, "R/W", 0, 1, 0ull, 0},
- {"TX_BAD_CRC24" , 2, 1, 519, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 519, "RAZ", 0, 1, 0ull, 0},
- {"STATUS" , 0, 64, 520, "RO", 0, 1, 18446744073709551615ull, 0},
- {"RESERVED_0_63" , 0, 64, 521, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 6, 522, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 522, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 8, 6, 522, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 522, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 7, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 523, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 7, 523, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 523, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 8, 524, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 524, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 8, 524, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_30" , 24, 7, 524, "RAZ", 0, 1, 0ull, 0},
- {"CLR" , 31, 1, 524, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 524, "RAZ", 0, 1, 0ull, 0},
- {"INDEX" , 0, 8, 525, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 525, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 8, 525, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_30" , 24, 7, 525, "RAZ", 0, 1, 0ull, 0},
- {"CLR" , 31, 1, 525, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 525, "RAZ", 0, 1, 0ull, 0},
- {"TXF_ERR" , 0, 1, 526, "R/W1C", 0, 1, 0ull, 0},
- {"BAD_SEQ" , 1, 1, 526, "R/W1C", 0, 1, 0ull, 0},
- {"BAD_PIPE" , 2, 1, 526, "R/W1C", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 3, 1, 526, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 526, "RAZ", 0, 1, 0ull, 0},
- {"TXF_ERR" , 0, 1, 527, "R/W", 0, 1, 0ull, 0},
- {"BAD_SEQ" , 1, 1, 527, "R/W", 0, 1, 0ull, 0},
- {"BAD_PIPE" , 2, 1, 527, "R/W", 0, 1, 0ull, 0},
- {"STAT_CNT_OVFL" , 3, 1, 527, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 527, "RAZ", 0, 1, 0ull, 0},
- {"BPID0" , 0, 6, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_6" , 6, 1, 528, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL0" , 7, 2, 528, "R/W", 0, 1, 0ull, 0},
- {"BPID1" , 9, 6, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 528, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL1" , 16, 2, 528, "R/W", 0, 1, 0ull, 0},
- {"BPID2" , 18, 6, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_24" , 24, 1, 528, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL2" , 25, 2, 528, "R/W", 0, 1, 0ull, 0},
- {"BPID3" , 27, 6, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_33" , 33, 1, 528, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL3" , 34, 2, 528, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 528, "RAZ", 0, 1, 0ull, 0},
- {"BPID4" , 0, 6, 529, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_6" , 6, 1, 529, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL4" , 7, 2, 529, "R/W", 0, 1, 0ull, 0},
- {"BPID5" , 9, 6, 529, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 529, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL5" , 16, 2, 529, "R/W", 0, 1, 0ull, 0},
- {"BPID6" , 18, 6, 529, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_24" , 24, 1, 529, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL6" , 25, 2, 529, "R/W", 0, 1, 0ull, 0},
- {"BPID7" , 27, 6, 529, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_33" , 33, 1, 529, "RAZ", 0, 1, 0ull, 0},
- {"ENTRY_CTL7" , 34, 2, 529, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 529, "RAZ", 0, 1, 0ull, 0},
- {"CHANNEL" , 0, 8, 530, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 530, "RAZ", 0, 1, 0ull, 0},
- {"REMAP" , 16, 1, 530, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 530, "RAZ", 0, 1, 0ull, 0},
- {"TX_PKT" , 0, 28, 531, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 531, "RAZ", 0, 1, 0ull, 0},
- {"TX_BYTES" , 0, 36, 532, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 532, "RAZ", 0, 1, 0ull, 0},
- {"BASE" , 0, 7, 533, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 533, "RAZ", 0, 1, 0ull, 0},
- {"NUMP" , 16, 8, 533, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 533, "RAZ", 0, 1, 0ull, 0},
- {"RATE_LIMIT" , 0, 16, 534, "R/W", 0, 1, 1024ull, 0},
- {"TIME_LIMIT" , 16, 16, 534, "R/W", 0, 1, 256ull, 0},
- {"BRST_LIMIT" , 32, 16, 534, "R/W", 0, 1, 1024ull, 0},
- {"GRNLRTY" , 48, 2, 534, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_50_63" , 50, 14, 534, "RAZ", 0, 1, 0ull, 0},
- {"ICRP1" , 0, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 1, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 535, "RAZ", 1, 1, 0, 0},
- {"IOCFIF" , 4, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"RSDFIF" , 5, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"IORFIF" , 6, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"XMCFIF" , 7, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"XMDFIF" , 8, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 535, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_5" , 0, 6, 536, "RAZ", 0, 0, 0ull, 0ull},
- {"XMC_PER" , 6, 4, 536, "R/W", 0, 0, 0ull, 0ull},
- {"FIF_DLY" , 10, 1, 536, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 536, "RAZ", 1, 1, 0, 0},
- {"NCB_WR" , 0, 3, 537, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_5" , 3, 3, 537, "R/W", 0, 0, 0ull, 0ull},
- {"PKO_RD" , 6, 4, 537, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 537, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 2, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 3, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 4, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 5, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 6, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 7, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 8, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 9, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 10, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 11, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 12, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"IOCFIF" , 13, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"RSDFIF" , 14, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"IORFIF" , 15, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"XMCFIF" , 16, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"XMDFIF" , 17, 1, 538, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 538, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 539, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 539, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 539, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVR5" , 5, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"XMC_PER" , 6, 4, 539, "R/W", 0, 0, 0ull, 0ull},
- {"FIF_DLY" , 10, 1, 539, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 539, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 540, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 540, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 540, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 541, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 541, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 541, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 541, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 541, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 542, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 542, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 542, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 542, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 542, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 543, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 544, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_63" , 0, 64, 545, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_63" , 0, 64, 546, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 547, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 547, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 547, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 548, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 548, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 548, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 548, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 548, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 549, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 549, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 549, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 549, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 549, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 550, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 551, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 552, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 552, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 552, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 553, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 553, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 553, "RAZ", 1, 1, 0, 0},
- {"NCB_WR" , 0, 3, 554, "R/W", 0, 1, 0ull, 0},
- {"NCB_RD" , 3, 3, 554, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 6, 3, 554, "R/W", 0, 1, 2ull, 0},
- {"RESERVED_9_63" , 9, 55, 554, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 555, "R/W", 0, 1, 13ull, 0},
- {"RESERVED_7_63" , 7, 57, 555, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 556, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_7_63" , 7, 57, 556, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 557, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_7_63" , 7, 57, 557, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 558, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_7_63" , 7, 57, 558, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 559, "R/W", 0, 1, 12ull, 0},
- {"RESERVED_7_63" , 7, 57, 559, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 560, "R/W", 0, 1, 40ull, 0},
- {"RESERVED_7_63" , 7, 57, 560, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 561, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_7_63" , 7, 57, 561, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 562, "R/W", 0, 1, 8ull, 0},
- {"RESERVED_7_63" , 7, 57, 562, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 563, "R/W", 0, 1, 8ull, 0},
- {"RESERVED_7_63" , 7, 57, 563, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 564, "R/W", 0, 1, 24ull, 0},
- {"RESERVED_7_63" , 7, 57, 564, "RAZ", 1, 1, 0, 0},
- {"CRD" , 0, 7, 565, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_7_63" , 7, 57, 565, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 566, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 566, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 567, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 567, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 568, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 568, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"PBM4" , 18, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"IIO0" , 19, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"IIO1" , 20, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"IIWO0" , 21, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"IIWO1" , 22, 1, 569, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 569, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 570, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 570, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 570, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 571, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 571, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 572, "RO", 0, 0, 0ull, 0ull},
- {"IOB_WR" , 0, 8, 573, "R/W", 0, 0, 8ull, 8ull},
- {"IOB_WRC" , 8, 8, 573, "RO", 0, 1, 8ull, 0},
- {"RESERVED_16_63" , 16, 48, 573, "RAZ", 1, 1, 0, 0},
- {"IPD_EN" , 0, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 574, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"CLKEN" , 15, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"RST_DONE" , 16, 1, 574, "RO", 0, 0, 1ull, 0ull},
- {"USE_SOP" , 17, 1, 574, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 574, "RAZ", 1, 1, 0, 0},
- {"PM0_SYN" , 0, 2, 575, "R/W", 0, 0, 0ull, 0ull},
- {"PM1_SYN" , 2, 2, 575, "R/W", 0, 0, 0ull, 0ull},
- {"PM2_SYN" , 4, 2, 575, "R/W", 0, 0, 0ull, 0ull},
- {"PM3_SYN" , 6, 2, 575, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 575, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 576, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 576, "R/W", 0, 0, 1ull, 1ull},
- {"PRADDR" , 9, 8, 576, "RO", 1, 1, 0, 0},
- {"WRADDR" , 17, 8, 576, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 25, 7, 576, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_32_63" , 32, 32, 576, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 577, "RO", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 577, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 3, 578, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 578, "R/W", 0, 0, 1ull, 1ull},
- {"PRADDR" , 4, 3, 578, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 7, 3, 578, "RO", 0, 0, 5ull, 5ull},
- {"PTR" , 10, 33, 578, "RO", 1, 1, 0, 0},
- {"RESERVED_43_63" , 43, 21, 578, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"SOP" , 12, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"EOP" , 13, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"DAT" , 14, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PW0_SBE" , 15, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PW0_DBE" , 16, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PW1_SBE" , 17, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PW1_DBE" , 18, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PW2_SBE" , 19, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PW2_DBE" , 20, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PW3_SBE" , 21, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"PW3_DBE" , 22, 1, 579, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 579, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"SOP" , 12, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"EOP" , 13, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"DAT" , 14, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW0_SBE" , 15, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW0_DBE" , 16, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW1_SBE" , 17, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW1_DBE" , 18, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW2_SBE" , 19, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW2_DBE" , 20, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW3_SBE" , 21, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"PW3_DBE" , 22, 1, 580, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 580, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 581, "RO", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 581, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 582, "RO", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 582, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 583, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 583, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 64, 584, "R/W", 0, 0, 0ull, 0ull},
- {"MB_SIZE" , 0, 12, 585, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 585, "RAZ", 1, 1, 0, 0},
- {"REASM" , 0, 6, 586, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 586, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 587, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 587, "R/W", 0, 0, 1ull, 1ull},
- {"MAX_PKT" , 8, 7, 587, "RO", 0, 0, 64ull, 64ull},
- {"PTR" , 15, 33, 587, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 587, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 588, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 588, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 589, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 590, "R/W", 0, 0, 0ull, 1ull},
- {"SOP" , 0, 64, 591, "RO", 0, 1, 0ull, 0},
- {"WQE_PCNT" , 0, 7, 592, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 592, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 592, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 592, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 592, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 592, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 593, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 593, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 594, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 594, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 64, 595, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 0, 14, 596, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 14, 14, 596, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 596, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 597, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 597, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 597, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 597, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 597, "RAZ", 1, 1, 0, 0},
- {"WGT0" , 0, 8, 598, "R/W", 0, 0, 255ull, 255ull},
- {"WGT1" , 8, 8, 598, "R/W", 0, 0, 255ull, 255ull},
- {"WGT2" , 16, 8, 598, "R/W", 0, 0, 255ull, 255ull},
- {"WGT3" , 24, 8, 598, "R/W", 0, 0, 255ull, 255ull},
- {"WGT4" , 32, 8, 598, "R/W", 0, 0, 255ull, 255ull},
- {"WGT5" , 40, 8, 598, "R/W", 0, 0, 255ull, 255ull},
- {"WGT6" , 48, 8, 598, "R/W", 0, 0, 255ull, 255ull},
- {"WGT7" , 56, 8, 598, "R/W", 0, 0, 255ull, 255ull},
- {"PAGE_CNT" , 0, 25, 599, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 599, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 599, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 600, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 600, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 600, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 601, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 601, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 602, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 602, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 602, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 602, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 603, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 603, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 603, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 604, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 605, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 605, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 605, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 605, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 605, "RAZ", 1, 1, 0, 0},
- {"DISABLE" , 0, 1, 606, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 606, "RAZ", 1, 1, 0, 0},
- {"MAXDRAM" , 4, 4, 606, "R/W", 0, 0, 9ull, 9ull},
- {"RESERVED_8_63" , 8, 56, 606, "RAZ", 1, 1, 0, 0},
- {"TDFFL" , 0, 4, 607, "RO", 1, 0, 0, 0ull},
- {"VRTFL" , 4, 4, 607, "RO", 1, 0, 0, 0ull},
- {"DUTRESFL" , 8, 4, 607, "RO", 1, 0, 0, 0ull},
- {"IOCDATFL" , 12, 4, 607, "RO", 1, 0, 0, 0ull},
- {"IOCCMDFL" , 16, 4, 607, "RO", 1, 0, 0, 0ull},
- {"TDPFL" , 20, 4, 607, "RO", 1, 0, 0, 0ull},
- {"XBFFL" , 24, 4, 607, "RO", 1, 0, 0, 0ull},
- {"RBFFL" , 28, 4, 607, "RO", 1, 0, 0, 0ull},
- {"DUTFL" , 32, 32, 607, "RO", 1, 0, 0, 0ull},
- {"VBFFL" , 0, 4, 608, "RO", 1, 0, 0, 0ull},
- {"RDFFL" , 4, 1, 608, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_61" , 5, 57, 608, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 62, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 63, 1, 608, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFL" , 0, 8, 609, "RO", 1, 0, 0, 0ull},
- {"FBFFL" , 8, 8, 609, "RO", 1, 0, 0, 0ull},
- {"SBFFL" , 16, 8, 609, "RO", 1, 0, 0, 0ull},
- {"FBFRSPFL" , 24, 8, 609, "RO", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 609, "RAZ", 1, 1, 0, 0},
- {"TAGFL" , 0, 16, 610, "RO", 1, 0, 0, 0ull},
- {"LRUFL" , 16, 1, 610, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 610, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 611, "R/W", 1, 1, 0, 0},
- {"DISIDXALIAS" , 0, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"DISECC" , 1, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"VAB_THRESH" , 2, 4, 612, "R/W", 0, 0, 0ull, 0ull},
- {"EF_CNT" , 6, 7, 612, "R/W", 0, 0, 0ull, 4ull},
- {"EF_ENA" , 13, 1, 612, "R/W", 0, 0, 0ull, 1ull},
- {"XMC_ARB_MODE" , 14, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"RSP_ARB_MODE" , 15, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"MAXLFB" , 16, 4, 612, "R/W", 0, 0, 0ull, 0ull},
- {"MAXVAB" , 20, 4, 612, "R/W", 0, 0, 0ull, 0ull},
- {"DISCCLK" , 24, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFDBE" , 25, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFSBE" , 26, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"DISSTGL2I" , 27, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"RDF_FAST" , 28, 1, 612, "R/W", 0, 0, 0ull, 1ull},
- {"SEPCMT" , 29, 1, 612, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 612, "RAZ", 1, 1, 0, 0},
- {"VALID" , 0, 1, 613, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_9" , 1, 9, 613, "RAZ", 1, 1, 0, 0},
- {"TAG" , 10, 28, 613, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 613, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 614, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 614, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 4, 18, 614, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_49" , 22, 28, 614, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 10, 614, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 614, "R/W1C", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 614, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 614, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 614, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 615, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_6" , 2, 5, 615, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 7, 15, 615, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_49" , 22, 28, 615, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 6, 615, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_60" , 56, 5, 615, "RAZ", 1, 1, 0, 0},
- {"NOWAY" , 61, 1, 615, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 615, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 615, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 616, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_49" , 2, 48, 616, "RAZ", 1, 1, 0, 0},
- {"VSYN" , 50, 10, 616, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 616, "RO", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 616, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 616, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 38, 617, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_47" , 38, 10, 617, "RAZ", 1, 1, 0, 0},
- {"SID" , 48, 6, 617, "RO", 0, 1, 0ull, 0},
- {"RESERVED_54_57" , 54, 4, 617, "RAZ", 1, 1, 0, 0},
- {"CMD" , 58, 6, 617, "RO", 0, 1, 0ull, 0},
- {"HOLERD" , 0, 1, 618, "R/W", 0, 0, 0ull, 1ull},
- {"HOLEWR" , 1, 1, 618, "R/W", 0, 0, 0ull, 1ull},
- {"VRTWR" , 2, 1, 618, "R/W", 0, 0, 0ull, 1ull},
- {"VRTIDRNG" , 3, 1, 618, "R/W", 0, 0, 0ull, 1ull},
- {"VRTADRNG" , 4, 1, 618, "R/W", 0, 0, 0ull, 1ull},
- {"VRTPE" , 5, 1, 618, "R/W", 0, 0, 0ull, 1ull},
- {"BIGWR" , 6, 1, 618, "R/W", 0, 0, 0ull, 1ull},
- {"BIGRD" , 7, 1, 618, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 618, "RAZ", 1, 1, 0, 0},
- {"HOLERD" , 0, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"HOLEWR" , 1, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTWR" , 2, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTIDRNG" , 3, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTADRNG" , 4, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTPE" , 5, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGWR" , 6, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGRD" , 7, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 619, "RAZ", 1, 1, 0, 0},
- {"TAD0" , 16, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"TAD1" , 17, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"TAD2" , 18, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"TAD3" , 19, 1, 619, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 619, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 620, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 621, "R/W", 0, 1, 0ull, 0},
- {"LVL" , 0, 3, 622, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 622, "RAZ", 1, 1, 0, 0},
- {"DWBLVL" , 4, 3, 622, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 622, "RAZ", 1, 1, 0, 0},
- {"LVL" , 0, 3, 623, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 623, "RAZ", 1, 1, 0, 0},
- {"WGT0" , 0, 8, 624, "R/W", 0, 0, 255ull, 255ull},
- {"WGT1" , 8, 8, 624, "R/W", 0, 0, 255ull, 255ull},
- {"WGT2" , 16, 8, 624, "R/W", 0, 0, 255ull, 255ull},
- {"WGT3" , 24, 8, 624, "R/W", 0, 0, 255ull, 255ull},
- {"WGT4" , 32, 8, 624, "R/W", 0, 0, 255ull, 255ull},
- {"WGT5" , 40, 8, 624, "R/W", 0, 0, 255ull, 255ull},
- {"WGT6" , 48, 8, 624, "R/W", 0, 0, 255ull, 255ull},
- {"WGT7" , 56, 8, 624, "R/W", 0, 0, 255ull, 255ull},
- {"COUNT" , 0, 64, 625, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 626, "R/W", 0, 1, 0ull, 0},
- {"OW0ECC" , 0, 10, 627, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 627, "RAZ", 1, 1, 0, 0},
- {"OW1ECC" , 16, 10, 627, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 627, "RAZ", 1, 1, 0, 0},
- {"OW2ECC" , 32, 10, 627, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 627, "RAZ", 1, 1, 0, 0},
- {"OW3ECC" , 48, 10, 627, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 627, "RAZ", 1, 1, 0, 0},
- {"OW4ECC" , 0, 10, 628, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 628, "RAZ", 1, 1, 0, 0},
- {"OW5ECC" , 16, 10, 628, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 628, "RAZ", 1, 1, 0, 0},
- {"OW6ECC" , 32, 10, 628, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 628, "RAZ", 1, 1, 0, 0},
- {"OW7ECC" , 48, 10, 628, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 628, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 629, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 629, "R/W", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 629, "R/W", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 629, "R/W", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 629, "R/W", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 629, "R/W", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 629, "R/W", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 629, "R/W", 0, 0, 0ull, 1ull},
- {"WRDISLMC" , 8, 1, 629, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 629, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 630, "R/W1C", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 630, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 630, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 630, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 630, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 630, "R/W1C", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
- {"WRDISLMC" , 8, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 630, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 631, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 632, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 633, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 634, "R/W", 0, 1, 0ull, 0},
- {"CNT0SEL" , 0, 8, 635, "R/W", 0, 0, 0ull, 1ull},
- {"CNT1SEL" , 8, 8, 635, "R/W", 0, 0, 0ull, 1ull},
- {"CNT2SEL" , 16, 8, 635, "R/W", 0, 0, 0ull, 1ull},
- {"CNT3SEL" , 24, 8, 635, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 635, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 0, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"DIRTY" , 1, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"VALID" , 2, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"USE" , 3, 1, 636, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_16" , 4, 13, 636, "RAZ", 1, 1, 0, 0},
- {"TAG" , 17, 19, 636, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_39" , 36, 4, 636, "RAZ", 1, 1, 0, 0},
- {"ECC" , 40, 6, 636, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_63" , 46, 18, 636, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 637, "R/W1C", 0, 0, 0ull, 0ull},
- {"MASK" , 0, 2, 638, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 638, "RAZ", 1, 1, 0, 0},
- {"DWB" , 0, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
- {"INVL2" , 1, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 639, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 32, 640, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 640, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 641, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 641, "RAZ", 1, 1, 0, 0},
- {"DWBID" , 8, 6, 641, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 641, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 642, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 642, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 643, "R/W", 0, 0, 0ull, 1ull},
- {"NUMID" , 1, 3, 643, "R/W", 0, 0, 5ull, 5ull},
- {"MEMSZ" , 4, 3, 643, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_7_7" , 7, 1, 643, "RAZ", 1, 1, 0, 0},
- {"OOBERR" , 8, 1, 643, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 643, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 32, 644, "R/W", 0, 0, 0ull, 0ull},
- {"PARITY" , 32, 4, 644, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 644, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 645, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 645, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 646, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 646, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 647, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 38, 648, "R/W", 1, 1, 0, 0},
- {"RESERVED_38_56" , 38, 19, 648, "RAZ", 1, 1, 0, 0},
- {"CMD" , 57, 6, 648, "R/W", 1, 1, 0, 0},
- {"INUSE" , 63, 1, 648, "RO", 0, 0, 0ull, 0ull},
- {"COUNT" , 0, 64, 649, "R/W", 0, 1, 0ull, 0},
- {"PRBS" , 0, 32, 650, "R/W", 1, 1, 0, 0},
- {"PROG" , 32, 8, 650, "R/W", 1, 1, 0, 0},
- {"SEL" , 40, 1, 650, "R/W", 1, 1, 0, 0},
- {"EN" , 41, 1, 650, "R/W", 1, 1, 0, 0},
- {"SKEW_ON" , 42, 1, 650, "R/W", 1, 1, 0, 0},
- {"DR" , 43, 1, 650, "R/W", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 650, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 651, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 652, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 652, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 653, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 654, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 654, "R/W", 1, 1, 0, 0},
- {"CKE_MASK" , 0, 2, 655, "R/W", 1, 1, 0, 0},
- {"CS0_N_MASK" , 2, 2, 655, "R/W", 1, 1, 0, 0},
- {"CS1_N_MASK" , 4, 2, 655, "R/W", 1, 1, 0, 0},
- {"ODT0_MASK" , 6, 2, 655, "R/W", 1, 1, 0, 0},
- {"ODT1_MASK" , 8, 2, 655, "R/W", 1, 1, 0, 0},
- {"RAS_N_MASK" , 10, 1, 655, "R/W", 1, 1, 0, 0},
- {"CAS_N_MASK" , 11, 1, 655, "R/W", 1, 1, 0, 0},
- {"WE_N_MASK" , 12, 1, 655, "R/W", 1, 1, 0, 0},
- {"BA_MASK" , 13, 3, 655, "R/W", 1, 1, 0, 0},
- {"A_MASK" , 16, 16, 655, "R/W", 1, 1, 0, 0},
- {"RESET_N_MASK" , 32, 1, 655, "R/W", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 655, "R/W", 1, 1, 0, 0},
- {"DQX_CTL" , 0, 4, 656, "R/W", 0, 1, 4ull, 0},
- {"CK_CTL" , 4, 4, 656, "R/W", 0, 1, 4ull, 0},
- {"CMD_CTL" , 8, 4, 656, "R/W", 0, 1, 4ull, 0},
- {"RODT_CTL" , 12, 4, 656, "R/W", 0, 1, 0ull, 0},
- {"NTUNE" , 16, 4, 656, "R/W", 0, 1, 0ull, 0},
- {"PTUNE" , 20, 4, 656, "R/W", 0, 1, 0ull, 0},
- {"BYP" , 24, 1, 656, "R/W", 0, 1, 0ull, 0},
- {"M180" , 25, 1, 656, "R/W", 0, 1, 0ull, 0},
- {"DDR__NTUNE" , 26, 4, 656, "RO", 1, 1, 0, 0},
- {"DDR__PTUNE" , 30, 4, 656, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 656, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 657, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 657, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 657, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 657, "R/W", 0, 1, 5ull, 0},
- {"IDLEPOWER" , 9, 3, 657, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 12, 4, 657, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 16, 1, 657, "R/W", 0, 0, 0ull, 1ull},
- {"RESET" , 17, 1, 657, "R/W", 0, 1, 0ull, 0},
- {"REF_ZQCS_INT" , 18, 19, 657, "R/W", 1, 1, 0, 0},
- {"SEQUENCE" , 37, 3, 657, "R/W", 0, 0, 0ull, 0ull},
- {"EARLY_DQX" , 40, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"SREF_WITH_DLL" , 41, 1, 657, "R/W", 0, 0, 0ull, 0ull},
- {"RANK_ENA" , 42, 1, 657, "R/W", 0, 1, 0ull, 0},
- {"RANKMASK" , 43, 4, 657, "R/W", 0, 1, 0ull, 0},
- {"MIRRMASK" , 47, 4, 657, "R/W", 0, 1, 0ull, 0},
- {"INIT_STATUS" , 51, 4, 657, "R/W1", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R0" , 55, 1, 657, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R1" , 56, 1, 657, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R0" , 57, 1, 657, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R1" , 58, 1, 657, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_59_63" , 59, 5, 657, "RAZ", 1, 1, 0, 0},
- {"RDIMM_ENA" , 0, 1, 658, "R/W", 0, 1, 0ull, 0},
- {"BWCNT" , 1, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 2, 1, 658, "R/W", 0, 0, 0ull, 1ull},
- {"POCAS" , 3, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH2" , 4, 2, 658, "R/W", 0, 0, 0ull, 1ull},
- {"THROTTLE_RD" , 6, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"THROTTLE_WR" , 7, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_RD" , 8, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_WR" , 9, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"ELEV_PRIO_DIS" , 10, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"NXM_WRITE_EN" , 11, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 12, 4, 658, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 16, 1, 658, "R/W", 0, 0, 0ull, 1ull},
- {"AUTO_DCLKDIS" , 17, 1, 658, "R/W", 0, 0, 0ull, 1ull},
- {"INT_ZQCS_DIS" , 18, 1, 658, "R/W", 0, 0, 1ull, 0ull},
- {"EXT_ZQCS_DIS" , 19, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 20, 2, 658, "R/W", 0, 0, 0ull, 0ull},
- {"WODT_BPRCH" , 22, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_BPRCH" , 23, 1, 658, "R/W", 0, 0, 0ull, 0ull},
- {"CRM_MAX" , 24, 5, 658, "R/W", 0, 0, 31ull, 31ull},
- {"CRM_THR" , 29, 5, 658, "R/W", 0, 0, 0ull, 8ull},
- {"CRM_CNT" , 34, 5, 658, "RO", 0, 0, 0ull, 0ull},
- {"THRMAX" , 39, 4, 658, "R/W", 0, 0, 15ull, 2ull},
- {"PERSUB" , 43, 8, 658, "R/W", 0, 0, 0ull, 0ull},
- {"THRCNT" , 51, 12, 658, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_63_63" , 63, 1, 658, "RAZ", 1, 1, 0, 0},
- {"DCLKCNT" , 0, 64, 659, "RO", 0, 1, 0ull, 0},
- {"CLKF" , 0, 7, 660, "R/W", 0, 1, 48ull, 0},
- {"RESET_N" , 7, 1, 660, "R/W", 0, 0, 0ull, 1ull},
- {"CPB" , 8, 3, 660, "R/W", 0, 0, 0ull, 1ull},
- {"CPS" , 11, 3, 660, "R/W", 0, 0, 0ull, 1ull},
- {"DIFFAMP" , 14, 4, 660, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_PS_EN" , 18, 3, 660, "R/W", 0, 1, 2ull, 0},
- {"DDR_DIV_RESET" , 21, 1, 660, "R/W", 0, 0, 1ull, 0ull},
- {"DFM_PS_EN" , 22, 3, 660, "R/W", 0, 1, 2ull, 0},
- {"DFM_DIV_RESET" , 25, 1, 660, "R/W", 0, 0, 1ull, 0ull},
- {"JTG_TEST_MODE" , 26, 1, 660, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 660, "RAZ", 1, 1, 0, 0},
- {"RC0" , 0, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC1" , 4, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC2" , 8, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC3" , 12, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC4" , 16, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC5" , 20, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC6" , 24, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC7" , 28, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC8" , 32, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC9" , 36, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC10" , 40, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC11" , 44, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC12" , 48, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC13" , 52, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC14" , 56, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"RC15" , 60, 4, 661, "R/W", 0, 0, 0ull, 0ull},
- {"DIMM0_WMASK" , 0, 16, 662, "R/W", 0, 0, 65535ull, 65535ull},
- {"DIMM1_WMASK" , 16, 16, 662, "R/W", 0, 0, 65535ull, 65535ull},
- {"TCWS" , 32, 13, 662, "R/W", 0, 0, 1248ull, 1248ull},
- {"PARITY" , 45, 1, 662, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 662, "RAZ", 1, 1, 0, 0},
- {"BYP_SETTING" , 0, 8, 663, "R/W", 0, 0, 0ull, 0ull},
- {"BYP_SEL" , 8, 4, 663, "R/W", 0, 0, 0ull, 0ull},
- {"QUAD_DLL_ENA" , 12, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 13, 1, 663, "R/W", 0, 0, 1ull, 0ull},
- {"DLL_BRINGUP" , 14, 1, 663, "R/W", 0, 0, 0ull, 0ull},
- {"INTF_EN" , 15, 1, 663, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 663, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 664, "R/W", 0, 0, 0ull, 0ull},
- {"BYTE_SEL" , 6, 4, 664, "R/W", 0, 0, 0ull, 0ull},
- {"MODE_SEL" , 10, 2, 664, "R/W", 0, 0, 0ull, 0ull},
- {"LOAD_OFFSET" , 12, 1, 664, "WR0", 0, 0, 0ull, 0ull},
- {"OFFSET_ENA" , 13, 1, 664, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYTE_SEL" , 14, 4, 664, "R/W", 0, 0, 1ull, 1ull},
- {"DLL_MODE" , 18, 1, 664, "R/W", 0, 0, 0ull, 0ull},
- {"FINE_TUNE_MODE" , 19, 1, 664, "R/W", 0, 0, 0ull, 1ull},
- {"DLL90_SETTING" , 20, 8, 664, "RO", 1, 1, 0, 0},
- {"DLL_FAST" , 28, 1, 664, "RO", 1, 1, 0, 0},
- {"DCLK90_BYP_SETTING" , 29, 8, 664, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_BYP_SEL" , 37, 1, 664, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_RECAL_DIS" , 38, 1, 664, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_90_DLY_BYP" , 39, 1, 664, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_FWD" , 40, 1, 664, "WR0", 0, 0, 0ull, 0ull},
- {"RESERVED_41_63" , 41, 23, 664, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 665, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 665, "RAZ", 1, 1, 0, 0},
- {"ROW_LSB" , 16, 3, 665, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_19_63" , 19, 45, 665, "RAZ", 1, 1, 0, 0},
- {"MRDSYN0" , 0, 8, 666, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 666, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 666, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 666, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 666, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 14, 667, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 14, 16, 667, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 30, 3, 667, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 33, 1, 667, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 34, 2, 667, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 667, "RAZ", 1, 1, 0, 0},
- {"IFBCNT" , 0, 64, 668, "RO", 0, 1, 1ull, 0},
- {"NXM_WR_ERR" , 0, 1, 669, "R/W1C", 0, 0, 0ull, 0ull},
- {"SEC_ERR" , 1, 4, 669, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 5, 4, 669, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 669, "RAZ", 1, 1, 0, 0},
- {"INTR_NXM_WR_ENA" , 0, 1, 670, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_SEC_ENA" , 1, 1, 670, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 2, 1, 670, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 670, "RAZ", 1, 1, 0, 0},
- {"CWL" , 0, 3, 671, "R/W", 0, 0, 0ull, 0ull},
- {"MPRLOC" , 3, 2, 671, "R/W", 0, 0, 0ull, 0ull},
- {"MPR" , 5, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"DLL" , 6, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"AL" , 7, 2, 671, "R/W", 0, 0, 0ull, 0ull},
- {"WLEV" , 9, 1, 671, "RO", 0, 0, 0ull, 0ull},
- {"TDQS" , 10, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"QOFF" , 11, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"BL" , 12, 2, 671, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 14, 4, 671, "R/W", 0, 0, 2ull, 2ull},
- {"RBT" , 18, 1, 671, "RO", 0, 0, 1ull, 1ull},
- {"TM" , 19, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"DLLR" , 20, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"WRP" , 21, 3, 671, "R/W", 0, 0, 0ull, 0ull},
- {"PPD" , 24, 1, 671, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 671, "RAZ", 1, 1, 0, 0},
- {"PASR_00" , 0, 3, 672, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_00" , 3, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_00" , 4, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_00" , 5, 2, 672, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_00" , 7, 2, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_00" , 9, 3, 672, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_01" , 12, 3, 672, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_01" , 15, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_01" , 16, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_01" , 17, 2, 672, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_01" , 19, 2, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_01" , 21, 3, 672, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_10" , 24, 3, 672, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_10" , 27, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_10" , 28, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_10" , 29, 2, 672, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_10" , 31, 2, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_10" , 33, 3, 672, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_11" , 36, 3, 672, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_11" , 39, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_11" , 40, 1, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_11" , 41, 2, 672, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_11" , 43, 2, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_11" , 45, 3, 672, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 672, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 673, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R0" , 8, 4, 673, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R1" , 12, 4, 673, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R0" , 16, 4, 673, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R1" , 20, 4, 673, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R0" , 24, 4, 673, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R1" , 28, 4, 673, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R0" , 32, 4, 673, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R1" , 36, 4, 673, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 673, "RAZ", 1, 1, 0, 0},
- {"OPSCNT" , 0, 64, 674, "RO", 0, 1, 1ull, 0},
- {"TS_STAGGER" , 0, 1, 675, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK_POS" , 1, 1, 675, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK" , 2, 1, 675, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT0" , 3, 4, 675, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE0" , 7, 1, 675, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT1" , 8, 4, 675, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE1" , 12, 1, 675, "R/W", 0, 1, 0ull, 0},
- {"LV_MODE" , 13, 1, 675, "R/W", 0, 1, 0ull, 0},
- {"RX_ALWAYS_ON" , 14, 1, 675, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 675, "RAZ", 1, 1, 0, 0},
- {"DDR3RST" , 0, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PWARM" , 1, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSOFT" , 2, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSV" , 3, 1, 676, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 676, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 677, "R/W", 0, 1, 0ull, 0},
- {"OFFSET" , 4, 4, 677, "R/W", 0, 0, 2ull, 2ull},
- {"OFFSET_EN" , 8, 1, 677, "R/W", 0, 0, 1ull, 1ull},
- {"OR_DIS" , 9, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 10, 8, 677, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_0" , 18, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_1" , 19, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_2" , 20, 1, 677, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_3" , 21, 1, 677, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 677, "RAZ", 1, 1, 0, 0},
- {"BITMASK" , 0, 64, 678, "RO", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 6, 679, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 6, 6, 679, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 12, 6, 679, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 18, 6, 679, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 24, 6, 679, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 30, 6, 679, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 36, 6, 679, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 42, 6, 679, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 48, 6, 679, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 54, 2, 679, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 679, "RAZ", 1, 1, 0, 0},
- {"RODT_D0_R0" , 0, 8, 680, "R/W", 0, 1, 0ull, 0},
- {"RODT_D0_R1" , 8, 8, 680, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R0" , 16, 8, 680, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R1" , 24, 8, 680, "R/W", 0, 1, 0ull, 0},
- {"RODT_D2_R0" , 32, 8, 680, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R1" , 40, 8, 680, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R0" , 48, 8, 680, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R1" , 56, 8, 680, "R/W", 0, 0, 0ull, 0ull},
- {"R2R_INIT" , 0, 6, 681, "R/W", 0, 1, 1ull, 0},
- {"R2W_INIT" , 6, 6, 681, "R/W", 0, 1, 6ull, 0},
- {"W2R_INIT" , 12, 6, 681, "R/W", 0, 1, 9ull, 0},
- {"W2W_INIT" , 18, 6, 681, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_24_63" , 24, 40, 681, "RAZ", 1, 1, 0, 0},
- {"R2R_XRANK_INIT" , 0, 6, 682, "R/W", 0, 1, 3ull, 0},
- {"R2W_XRANK_INIT" , 6, 6, 682, "R/W", 0, 1, 6ull, 0},
- {"W2R_XRANK_INIT" , 12, 6, 682, "R/W", 0, 1, 4ull, 0},
- {"W2W_XRANK_INIT" , 18, 6, 682, "R/W", 0, 1, 5ull, 0},
- {"RESERVED_24_63" , 24, 40, 682, "RAZ", 1, 1, 0, 0},
- {"R2R_XDIMM_INIT" , 0, 6, 683, "R/W", 0, 1, 4ull, 0},
- {"R2W_XDIMM_INIT" , 6, 6, 683, "R/W", 0, 1, 7ull, 0},
- {"W2R_XDIMM_INIT" , 12, 6, 683, "R/W", 0, 1, 4ull, 0},
- {"W2W_XDIMM_INIT" , 18, 6, 683, "R/W", 0, 1, 6ull, 0},
- {"RESERVED_24_63" , 24, 40, 683, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_9" , 0, 10, 684, "RAZ", 1, 1, 0, 0},
- {"TZQCS" , 10, 4, 684, "R/W", 0, 0, 4ull, 4ull},
- {"TCKE" , 14, 4, 684, "R/W", 0, 0, 3ull, 3ull},
- {"TXPR" , 18, 4, 684, "R/W", 0, 0, 5ull, 5ull},
- {"TMRD" , 22, 4, 684, "R/W", 0, 0, 4ull, 4ull},
- {"TMOD" , 26, 4, 684, "R/W", 0, 0, 12ull, 12ull},
- {"TDLLK" , 30, 4, 684, "R/W", 0, 0, 2ull, 2ull},
- {"TZQINIT" , 34, 4, 684, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 38, 4, 684, "R/W", 0, 0, 6ull, 6ull},
- {"TCKSRE" , 42, 4, 684, "R/W", 0, 0, 5ull, 5ull},
- {"TRP_EXT" , 46, 1, 684, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 684, "RAZ", 1, 1, 0, 0},
- {"TMPRR" , 0, 4, 685, "R/W", 0, 0, 1ull, 1ull},
- {"TRAS" , 4, 5, 685, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 9, 4, 685, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 13, 4, 685, "R/W", 0, 0, 2ull, 3ull},
- {"TRFC" , 17, 5, 685, "R/W", 0, 0, 6ull, 7ull},
- {"TRRD" , 22, 3, 685, "R/W", 0, 0, 2ull, 2ull},
- {"TXP" , 25, 3, 685, "R/W", 0, 0, 3ull, 3ull},
- {"TWLMRD" , 28, 4, 685, "R/W", 0, 0, 10ull, 10ull},
- {"TWLDQSEN" , 32, 4, 685, "R/W", 0, 0, 7ull, 7ull},
- {"TFAW" , 36, 5, 685, "R/W", 0, 0, 0ull, 9ull},
- {"TXPDLL" , 41, 5, 685, "R/W", 0, 0, 0ull, 10ull},
- {"TRAS_EXT" , 46, 1, 685, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 685, "RAZ", 1, 1, 0, 0},
- {"TRESET" , 0, 1, 686, "R/W", 0, 1, 1ull, 0},
- {"RCLK_CNT" , 1, 32, 686, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 686, "RAZ", 1, 1, 0, 0},
- {"RING_CNT" , 0, 32, 687, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 687, "RAZ", 1, 1, 0, 0},
- {"LANEMASK" , 0, 9, 688, "R/W", 0, 1, 0ull, 0},
- {"SSET" , 9, 1, 688, "R/W", 0, 1, 0ull, 0},
- {"OR_DIS" , 10, 1, 688, "R/W", 0, 1, 0ull, 0},
- {"BITMASK" , 11, 8, 688, "R/W", 0, 1, 0ull, 0},
- {"RTT_NOM" , 19, 3, 688, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 688, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 689, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 4, 8, 689, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 689, "RAZ", 1, 1, 0, 0},
- {"BYTE0" , 0, 5, 690, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 5, 5, 690, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 10, 5, 690, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 15, 5, 690, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 20, 5, 690, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 25, 5, 690, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 30, 5, 690, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 35, 5, 690, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 40, 5, 690, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 45, 2, 690, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_63" , 47, 17, 690, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 691, "R/W", 0, 1, 255ull, 0},
- {"WODT_D0_R1" , 8, 8, 691, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R0" , 16, 8, 691, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R1" , 24, 8, 691, "R/W", 0, 1, 255ull, 0},
- {"WODT_D2_R0" , 32, 8, 691, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D2_R1" , 40, 8, 691, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R0" , 48, 8, 691, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R1" , 56, 8, 691, "R/W", 0, 0, 255ull, 0ull},
- {"STAT" , 0, 10, 692, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 692, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 693, "R/W", 1, 1, 0, 0},
- {"PCTL" , 6, 6, 693, "R/W", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 693, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 694, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 694, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 694, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 694, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 694, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 694, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 694, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 694, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 694, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 694, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 695, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 695, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 695, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 696, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 696, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 696, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 697, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 697, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 697, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 697, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 697, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 697, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 697, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 697, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 697, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 697, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 697, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 697, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 697, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 697, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 697, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 698, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 698, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 698, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 699, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 699, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 699, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 700, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 700, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 700, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 701, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 701, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 701, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 701, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 701, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 702, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 703, "RAZ", 1, 1, 0, 0},
- {"NAND" , 8, 1, 703, "RO", 1, 1, 0, 0},
- {"TERM" , 9, 2, 703, "RO", 1, 1, 0, 0},
- {"DMACK_P0" , 11, 1, 703, "RO", 1, 1, 0, 0},
- {"DMACK_P1" , 12, 1, 703, "RO", 1, 1, 0, 0},
- {"RESERVED_13_13" , 13, 1, 703, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 14, 1, 703, "RO", 1, 1, 0, 0},
- {"ALE" , 15, 1, 703, "RO", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 703, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 16, 704, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 704, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 704, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 704, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 704, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 704, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 704, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 704, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 704, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 704, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 704, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 704, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 704, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 705, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 705, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 705, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 705, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 705, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 705, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 705, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 705, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 705, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 705, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 705, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 705, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 705, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 706, "R/W", 0, 0, 25ull, 25ull},
- {"RESERVED_6_7" , 6, 2, 706, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 706, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 706, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 706, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 706, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 707, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 708, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 708, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 709, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 709, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 710, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 710, "RO", 1, 1, 0, 0},
- {"RESERVED_24_25" , 24, 2, 710, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 710, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 710, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 710, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 710, "RO", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 710, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 710, "RO", 1, 1, 0, 0},
- {"DORM_CRYPTO" , 34, 1, 710, "RO", 1, 1, 0, 0},
- {"POWER_LIMIT" , 35, 2, 710, "RO", 1, 1, 0, 0},
- {"RESERVED_37_63" , 37, 27, 710, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 711, "RAZ", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 711, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 711, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 711, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 711, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 711, "RO", 1, 1, 0, 0},
- {"ZIP_INFO" , 29, 2, 711, "RO", 1, 1, 0, 0},
- {"RESERVED_31_31" , 31, 1, 711, "RAZ", 1, 1, 0, 0},
- {"L2C_CRIP" , 32, 3, 711, "RO", 1, 1, 0, 0},
- {"PLL_HALF_DIS" , 35, 1, 711, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_MAN" , 36, 1, 711, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_RSV" , 37, 1, 711, "RO", 1, 1, 0, 0},
- {"EMA" , 38, 2, 711, "RO", 1, 1, 0, 0},
- {"RESERVED_40_40" , 40, 1, 711, "RAZ", 1, 1, 0, 0},
- {"DFA_INFO_CLM" , 41, 4, 711, "RO", 1, 1, 0, 0},
- {"DFA_INFO_DTE" , 45, 3, 711, "RO", 1, 1, 0, 0},
- {"PLL_CTL" , 48, 10, 711, "RO", 1, 1, 0, 0},
- {"RESERVED_58_63" , 58, 6, 711, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 712, "RAZ", 1, 1, 0, 0},
- {"RESERVED_3_3" , 3, 1, 712, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 712, "RAZ", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 712, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 713, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 714, "RAZ", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 714, "RAZ", 0, 1, 0ull, 0},
- {"PNR_COUT_SEL" , 2, 2, 714, "R/W", 0, 1, 0ull, 0},
- {"PNR_COUT_RST" , 4, 1, 714, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_SEL" , 5, 2, 714, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_RST" , 7, 1, 714, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_31" , 8, 24, 714, "RAZ", 1, 1, 0, 0},
- {"RCLK_ALIGN_L" , 32, 8, 714, "RO", 1, 1, 0, 0},
- {"RCLK_ALIGN_R" , 40, 8, 714, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 714, "RO", 1, 1, 0, 0},
- {"PROG" , 0, 1, 715, "R/W", 1, 1, 0, 0},
- {"SOFT" , 1, 1, 715, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 715, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 6, 716, "R/W", 0, 1, 1ull, 0},
- {"SCLK_HI" , 6, 15, 716, "R/W", 0, 1, 5000ull, 0},
- {"SCLK_LO" , 21, 4, 716, "R/W", 0, 1, 1ull, 0},
- {"OUT" , 25, 7, 716, "R/W", 0, 1, 1ull, 0},
- {"PROG_PIN" , 32, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"FSRC_PIN" , 33, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"VGATE_PIN" , 34, 1, 716, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 716, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 717, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 717, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 717, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 717, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 717, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 717, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 717, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 10, 718, "R/W", 0, 1, 999ull, 0},
- {"SDH" , 10, 4, 718, "R/W", 0, 1, 0ull, 0},
- {"PRH" , 14, 4, 718, "R/W", 0, 1, 6ull, 0},
- {"FSH" , 18, 4, 718, "R/W", 0, 1, 15ull, 0},
- {"SCH" , 22, 4, 718, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_26_63" , 26, 38, 718, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 18, 719, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 18, 18, 719, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 36, 18, 719, "RO", 0, 0, 0ull, 0ull},
- {"TOO_MANY" , 54, 1, 719, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 719, "RAZ", 1, 1, 0, 0},
- {"REPAIR3" , 0, 18, 720, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR4" , 18, 18, 720, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR5" , 36, 18, 720, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 720, "RAZ", 1, 1, 0, 0},
- {"REPAIR6" , 0, 18, 721, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 721, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 722, "RAZ", 1, 1, 0, 0},
- {"REPAIR1" , 14, 14, 722, "RAZ", 1, 1, 0, 0},
- {"REPAIR2" , 28, 14, 722, "RAZ", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 722, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 723, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 723, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 4, 724, "R/W", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 724, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 725, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 6, 6, 725, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_12_63" , 12, 52, 725, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 726, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 726, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 726, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 726, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 726, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 726, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 726, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 726, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 726, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 726, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 727, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 727, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 728, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 728, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 729, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 729, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 730, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 730, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 731, "R/W", 0, 0, 18446744073709551615ull, 0ull},
- {"FRNANOSEC" , 0, 32, 732, "R/W", 0, 0, 4294967295ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 732, "RAZ", 1, 1, 0, 0},
- {"PTP_EN" , 0, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EN" , 1, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_IN" , 2, 6, 733, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EN" , 8, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EDGE" , 9, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_IN" , 10, 6, 733, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EN" , 16, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EDGE" , 17, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_IN" , 18, 6, 733, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_EN" , 24, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_INV" , 25, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_OUT" , 26, 4, 733, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_EN" , 30, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_INV" , 31, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_OUT" , 32, 5, 733, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_OUT4" , 37, 1, 733, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EDGE" , 38, 2, 733, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT" , 40, 1, 733, "RO", 1, 0, 0, 0ull},
- {"PPS" , 41, 1, 733, "RO", 1, 0, 0, 0ull},
- {"RESERVED_42_63" , 42, 22, 733, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 734, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 734, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 735, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 736, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 736, "RAZ", 1, 1, 0, 0},
- {"CNTR" , 0, 64, 737, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 738, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 738, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 739, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 739, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 740, "R/W", 0, 0, 18446744073709551615ull, 0ull},
- {"FRNANOSEC" , 0, 32, 741, "R/W", 0, 0, 4294967295ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 741, "RAZ", 1, 1, 0, 0},
- {"NANOSEC" , 0, 64, 742, "R/W", 0, 0, 0ull, 0ull},
- {"QLM_CFG" , 0, 3, 743, "RO", 1, 1, 0, 0},
- {"RESERVED_3_7" , 3, 5, 743, "RAZ", 1, 1, 0, 0},
- {"QLM_SPD" , 8, 4, 743, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 743, "RAZ", 1, 1, 0, 0},
- {"RBOOT_PIN" , 0, 1, 744, "RO", 1, 1, 0, 0},
- {"RBOOT" , 1, 1, 744, "R/W", 1, 1, 0, 0},
- {"LBOOT" , 2, 10, 744, "R/W1C", 1, 1, 0, 0},
- {"QLM0_SPD" , 12, 4, 744, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 16, 4, 744, "RO", 1, 1, 0, 0},
- {"QLM2_SPD" , 20, 4, 744, "RO", 1, 1, 0, 0},
- {"PNR_MUL" , 24, 6, 744, "RO", 1, 1, 0, 0},
- {"C_MUL" , 30, 6, 744, "RO", 1, 1, 0, 0},
- {"QLM3_SPD" , 36, 4, 744, "RO", 1, 1, 0, 0},
- {"QLM4_SPD" , 40, 4, 744, "RO", 1, 1, 0, 0},
- {"RESERVED_44_57" , 44, 14, 744, "RAZ", 1, 1, 0, 0},
- {"JT_TSTMODE" , 58, 1, 744, "RO", 1, 1, 0, 0},
- {"RESERVED_59_63" , 59, 5, 744, "RAZ", 1, 1, 0, 0},
- {"SOFT_CLR_BIST" , 0, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"WARM_CLR_BIST" , 1, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"CNTL_CLR_BIST" , 2, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 745, "RAZ", 1, 1, 0, 0},
- {"BIST_DELAY" , 8, 56, 745, "RO", 1, 1, 0, 0},
- {"RST_VAL" , 0, 1, 746, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 746, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 746, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 746, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 746, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 746, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 746, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 746, "RO", 1, 1, 0, 0},
- {"PRST_LINK" , 9, 1, 746, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 746, "RAZ", 1, 1, 0, 0},
- {"RST_VAL" , 0, 1, 747, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 747, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 747, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 747, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 747, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 747, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 747, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 747, "RO", 1, 1, 0, 0},
- {"PRST_LINK" , 9, 1, 747, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 747, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST_DLY" , 0, 16, 748, "R/W", 0, 1, 2047ull, 0},
- {"WARM_RST_DLY" , 16, 16, 748, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_32_63" , 32, 32, 748, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 749, "R/W1C", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 749, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 749, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 749, "R/W1C", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 749, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 749, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 750, "R/W", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 750, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 750, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 750, "R/W", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 750, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 750, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 751, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 751, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 751, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 751, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 751, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 751, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 751, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 751, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 751, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 751, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 751, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 751, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 751, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 752, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 752, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 752, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 752, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 752, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 752, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 752, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 752, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 752, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 752, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 752, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 752, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 753, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 753, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 753, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 754, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 754, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 754, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 755, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 755, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 756, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 756, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 757, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 757, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 758, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 758, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 758, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 758, "RAZ", 1, 1, 0, 0},
- {"TXTRIG" , 4, 2, 758, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 758, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 758, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 759, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 759, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 760, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 760, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 760, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 760, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 760, "RAZ", 1, 1, 0, 0},
- {"PTIME" , 7, 1, 760, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 760, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 761, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 761, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 761, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 761, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 762, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 762, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 762, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 762, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 762, "RAZ", 1, 1, 0, 0},
- {"BRK" , 6, 1, 762, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 762, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 762, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 763, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 763, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 763, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 763, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 763, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 763, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 763, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 763, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 763, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 764, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 764, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 764, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 764, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 764, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 764, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 764, "RAZ", 1, 1, 0, 0},
- {"DCTS" , 0, 1, 765, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 765, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 765, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 765, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 765, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 765, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 765, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 765, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 765, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 766, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 766, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 767, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 767, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 768, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 768, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 768, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 768, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 769, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 769, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 770, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 770, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 771, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 771, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 772, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 772, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 772, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 772, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 773, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 773, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 774, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 774, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 775, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 775, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 776, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 776, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 777, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 777, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 778, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 778, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 779, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 779, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 779, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 779, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 779, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 779, "RAZ", 1, 1, 0, 0},
- {"ORFDAT" , 0, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"IRFDAT" , 1, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"IPFDAT" , 2, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"MRQDAT" , 3, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"MRGDAT" , 4, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"OPFDAT" , 5, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 780, "RAZ", 0, 0, 0ull, 0ull},
- {"MRQ_HWM" , 0, 2, 781, "R/W", 0, 0, 0ull, 1ull},
- {"NBTARB" , 2, 1, 781, "R/W", 0, 0, 0ull, 0ull},
- {"LENDIAN" , 3, 1, 781, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 4, 1, 781, "R/W", 0, 0, 1ull, 0ull},
- {"EN" , 5, 1, 781, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 6, 1, 781, "RO", 0, 0, 0ull, 0ull},
- {"CRC_STRIP" , 7, 1, 781, "R/W", 0, 0, 0ull, 0ull},
- {"TS_THRESH" , 8, 4, 781, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 781, "RAZ", 1, 1, 0, 0},
- {"OVFENA" , 0, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"IVFENA" , 1, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"OTHENA" , 2, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"ITHENA" , 3, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_DRPENA" , 4, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"IRUNENA" , 5, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"ORUNENA" , 6, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"TSENA" , 7, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 782, "RAZ", 1, 1, 0, 0},
- {"IRCNT" , 0, 20, 783, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 783, "RAZ", 1, 1, 0, 0},
- {"IRHWM" , 0, 20, 784, "R/W", 0, 0, 0ull, 0ull},
- {"IBPLWM" , 20, 20, 784, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 784, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 785, "RAZ", 1, 1, 0, 0},
- {"IBASE" , 3, 37, 785, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 40, 20, 785, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 785, "RAZ", 1, 1, 0, 0},
- {"IDBELL" , 0, 20, 786, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 786, "RAZ", 1, 1, 0, 0},
- {"ITLPTR" , 32, 20, 786, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 786, "RAZ", 1, 1, 0, 0},
- {"ODBLOVF" , 0, 1, 787, "R/W1C", 0, 0, 0ull, 0ull},
- {"IDBLOVF" , 1, 1, 787, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORTHRESH" , 2, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"IRTHRESH" , 3, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"DATA_DRP" , 4, 1, 787, "R/W1C", 0, 0, 0ull, 0ull},
- {"IRUN" , 5, 1, 787, "R/W1C", 0, 0, 0ull, 0ull},
- {"ORUN" , 6, 1, 787, "R/W1C", 0, 0, 0ull, 0ull},
- {"TS" , 7, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 787, "RAZ", 1, 1, 0, 0},
- {"ORCNT" , 0, 20, 788, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 788, "RAZ", 1, 1, 0, 0},
- {"ORHWM" , 0, 20, 789, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 789, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 790, "RAZ", 1, 1, 0, 0},
- {"OBASE" , 3, 37, 790, "R/W", 0, 1, 0ull, 0},
- {"OSIZE" , 40, 20, 790, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 790, "RAZ", 1, 1, 0, 0},
- {"ODBELL" , 0, 20, 791, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 791, "RAZ", 1, 1, 0, 0},
- {"OTLPTR" , 32, 20, 791, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_63" , 52, 12, 791, "RAZ", 1, 1, 0, 0},
- {"OREMCNT" , 0, 20, 792, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 792, "RAZ", 1, 1, 0, 0},
- {"IREMCNT" , 32, 20, 792, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_52_63" , 52, 12, 792, "RAZ", 1, 1, 0, 0},
- {"TSCNT" , 0, 5, 793, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 793, "RAZ", 1, 1, 0, 0},
- {"TSTOT" , 8, 5, 793, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 793, "RAZ", 1, 1, 0, 0},
- {"TSAVL" , 16, 5, 793, "RO", 0, 0, 4ull, 4ull},
- {"RESERVED_21_63" , 21, 43, 793, "RAZ", 1, 1, 0, 0},
- {"TSTAMP" , 0, 64, 794, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 3, 795, "R/W", 0, 1, 0ull, 0},
- {"ADR_CYC" , 3, 4, 795, "R/W", 0, 1, 8ull, 0},
- {"T_MULT" , 7, 4, 795, "R/W", 0, 1, 9ull, 0},
- {"RESERVED_11_63" , 11, 53, 795, "RAZ", 1, 1, 0, 0},
- {"NF_CMD" , 0, 64, 796, "R/W", 0, 1, 0ull, 0},
- {"CNT" , 0, 8, 797, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 797, "RAZ", 1, 1, 0, 0},
- {"ECC_ERR" , 0, 8, 798, "RO", 0, 1, 0ull, 0},
- {"XOR_ECC" , 8, 24, 798, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 798, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 799, "R/W1C", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 799, "R/W1C", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 799, "R/W1C", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 799, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 799, "R/W1C", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 799, "R/W1C", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 799, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 799, "RAZ", 1, 1, 0, 0},
- {"EMPTY" , 0, 1, 800, "R/W", 0, 1, 0ull, 0},
- {"FULL" , 1, 1, 800, "R/W", 0, 1, 0ull, 0},
- {"WDOG" , 2, 1, 800, "R/W", 0, 1, 0ull, 0},
- {"SM_BAD" , 3, 1, 800, "R/W", 0, 1, 0ull, 0},
- {"ECC_1BIT" , 4, 1, 800, "R/W", 0, 1, 0ull, 0},
- {"ECC_MULT" , 5, 1, 800, "R/W", 0, 1, 0ull, 0},
- {"OVRF" , 6, 1, 800, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 800, "RAZ", 1, 1, 0, 0},
- {"RST_FF" , 0, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"EX_DIS" , 1, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"BT_DIS" , 2, 1, 801, "R/W", 0, 0, 0ull, 1ull},
- {"BT_DMA" , 3, 1, 801, "R/W", 0, 1, 0ull, 0},
- {"RD_CMD" , 4, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RD_VAL" , 5, 1, 801, "RO", 0, 1, 0ull, 0},
- {"RD_DONE" , 6, 1, 801, "R/W1C", 0, 0, 0ull, 0ull},
- {"FR_BYT" , 7, 11, 801, "RO", 0, 1, 0ull, 0},
- {"WAIT_CNT" , 18, 6, 801, "R/W", 0, 1, 20ull, 0},
- {"NBR_HWM" , 24, 3, 801, "R/W", 0, 0, 3ull, 3ull},
- {"MB_DIS" , 27, 1, 801, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 801, "RAZ", 1, 1, 0, 0},
- {"MAIN_SM" , 0, 3, 802, "RO", 0, 1, 0ull, 0},
- {"MAIN_BAD" , 3, 1, 802, "RO", 0, 1, 0ull, 0},
- {"RD_FF" , 4, 2, 802, "RO", 0, 1, 0ull, 0},
- {"RD_FF_BAD" , 6, 1, 802, "RO", 0, 1, 0ull, 0},
- {"BT_SM" , 7, 4, 802, "RO", 0, 1, 0ull, 0},
- {"EXE_SM" , 11, 4, 802, "RO", 0, 1, 0ull, 0},
- {"EXE_IDLE" , 15, 1, 802, "RO", 0, 1, 1ull, 0},
- {"RESERVED_16_63" , 16, 48, 802, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 803, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 803, "RO/WRSL", 0, 0, 145ull, 145ull},
- {"ISAE" , 0, 1, 804, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 804, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 804, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 804, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 804, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 804, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 804, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 804, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 804, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 804, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 804, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 804, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 804, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 804, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 804, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 804, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 804, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 804, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 805, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PI" , 8, 8, 805, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 805, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 805, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 806, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 806, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 806, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 806, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 806, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 807, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 807, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 807, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 807, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 807, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 808, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 808, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 809, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 810, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 811, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 811, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 811, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 811, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 811, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 812, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 812, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 813, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 814, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 815, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 815, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 815, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 815, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 816, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 816, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_8" , 0, 9, 817, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 9, 23, 817, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 818, "WORSL", 0, 0, 511ull, 511ull},
- {"CISP" , 0, 32, 819, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 820, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 820, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 821, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 821, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 821, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 822, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 822, "WORSL", 0, 0, 32767ull, 32767ull},
- {"CP" , 0, 8, 823, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 823, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 824, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 824, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 824, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 824, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 825, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 825, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 825, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 825, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 825, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 825, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 825, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 825, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 825, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 825, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 826, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 826, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 826, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 826, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 826, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 826, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 826, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 826, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 826, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 826, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 826, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 826, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 827, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 827, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 827, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 827, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 827, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 827, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PVM" , 24, 1, 827, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 827, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 828, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 828, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 829, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 830, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 830, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 831, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 831, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 831, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 831, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 831, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 831, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 831, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 832, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 832, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 832, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 832, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 832, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 832, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 832, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 832, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 832, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 832, "RO", 0, 0, 0ull, 0ull},
- {"FLR" , 28, 1, 832, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 832, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 833, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 833, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 833, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 833, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 833, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 833, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 833, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 833, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 833, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 833, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 833, "R/W", 0, 0, 2ull, 2ull},
- {"I_FLR" , 15, 1, 833, "RO", 0, 0, 0ull, 0ull},
- {"CE_D" , 16, 1, 833, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 833, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 833, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 833, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 833, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 833, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 833, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 834, "RO/WRSL", 1, 1, 0, 0},
- {"MLW" , 4, 6, 834, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"ASLPMS" , 10, 2, 834, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 834, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 834, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 834, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 834, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 834, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 834, "RO", 0, 0, 0ull, 0ull},
- {"ASPM" , 22, 1, 834, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 834, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 834, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 835, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 835, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 835, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 835, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 835, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 835, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 835, "RO", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 835, "RO", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 835, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 835, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 835, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 835, "RO", 0, 0, 0ull, 8ull},
- {"RESERVED_26_26" , 26, 1, 835, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 835, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 835, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 835, "RO", 0, 0, 0ull, 0ull},
- {"LBM" , 30, 1, 835, "RO", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 835, "RO", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 836, "RO", 0, 0, 15ull, 15ull},
- {"CTDS" , 4, 1, 836, "RO", 0, 0, 1ull, 1ull},
- {"ARI" , 5, 1, 836, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OPS" , 6, 1, 836, "RO", 0, 0, 0ull, 0ull},
- {"ATOM32S" , 7, 1, 836, "RO", 0, 0, 0ull, 0ull},
- {"ATOM64S" , 8, 1, 836, "RO", 0, 0, 0ull, 0ull},
- {"ATOM128S" , 9, 1, 836, "RO", 0, 0, 0ull, 0ull},
- {"NOROPRPR" , 10, 1, 836, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 836, "RAZ", 1, 1, 0, 0},
- {"TPH" , 12, 2, 836, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 836, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 837, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 837, "R/W", 0, 0, 0ull, 0ull},
- {"ARI" , 5, 1, 837, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP" , 6, 1, 837, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP_EB" , 7, 1, 837, "RO", 0, 0, 0ull, 0ull},
- {"ID0_RQ" , 8, 1, 837, "RO", 0, 0, 0ull, 0ull},
- {"ID0_CP" , 9, 1, 837, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 837, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 838, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 838, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 838, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 838, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 839, "R/W", 1, 0, 0, 2ull},
- {"EC" , 4, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 839, "RO", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 839, "RO", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 839, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 839, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 839, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 839, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 840, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 840, "RO", 0, 0, 2ull, 2ull},
- {"NCO" , 20, 12, 840, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 841, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 841, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 841, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 841, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 841, "RAZ", 1, 1, 0, 0},
- {"UATOMBS" , 24, 1, 841, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 841, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 842, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 842, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 842, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 842, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 842, "RAZ", 1, 1, 0, 0},
- {"UATOMBM" , 24, 1, 842, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 842, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 843, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 843, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 843, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 843, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 843, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 843, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 843, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 843, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 843, "RO", 0, 0, 2ull, 2ull},
- {"UATOMBS" , 24, 1, 843, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 843, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 844, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 844, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 844, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 845, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 845, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 845, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 845, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 845, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 845, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 845, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 845, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 845, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 846, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 846, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 846, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 846, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 846, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 846, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 847, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 848, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 849, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 850, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 851, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 851, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 852, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 853, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 853, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 853, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 853, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 853, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 853, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 854, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 854, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 854, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 854, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 854, "R/W", 0, 0, 3ull, 3ull},
- {"EASPML1" , 30, 1, 854, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 854, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 855, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 855, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 855, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 855, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 855, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 855, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 855, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 855, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 855, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 855, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_22_31" , 22, 10, 855, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 856, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 856, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 856, "R/W", 0, 0, 0ull, 0ull},
- {"MFUNCN" , 0, 8, 857, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_13" , 8, 6, 857, "RO", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 857, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 857, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 857, "R/W", 0, 0, 0ull, 0ull},
- {"CX_NFUNC" , 29, 3, 857, "R/W", 0, 0, 0ull, 0ull},
- {"SKPIV" , 0, 11, 858, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 858, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 858, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 858, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"M_DABORT_4UCPL" , 2, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"M_HANDLE_FLUSH" , 3, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 859, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 860, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 861, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 862, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 862, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 862, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 863, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 863, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 863, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 864, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 864, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 864, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 865, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 866, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 866, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 866, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 866, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 867, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 867, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 867, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 867, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 868, "RO/WRSL", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 868, "RO/WRSL", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 868, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 868, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 868, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 868, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 868, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 869, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"HEADER_CREDITS" , 12, 8, 869, "RO/WRSL", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 869, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 869, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 869, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 870, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 870, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 870, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 870, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 870, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 871, "RO/WRSL", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 871, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 871, "RO/WRSL", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 871, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 872, "RO/WRSL", 0, 0, 136ull, 136ull},
- {"RESERVED_14_15" , 14, 2, 872, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 872, "RO/WRSL", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 872, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 873, "RO/WRSL", 0, 0, 679ull, 679ull},
- {"RESERVED_14_15" , 14, 2, 873, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 873, "RO/WRSL", 0, 0, 133ull, 133ull},
- {"RESERVED_26_31" , 26, 6, 873, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 874, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 874, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 874, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 874, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 874, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 874, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 874, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 875, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 876, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 877, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 877, "R/W", 0, 0, 145ull, 145ull},
- {"ISAE" , 0, 1, 878, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 878, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 878, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 878, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 878, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 878, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 878, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 878, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 878, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 878, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 878, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 878, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 878, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 878, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 878, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 878, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 878, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 878, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 878, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 878, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 878, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 878, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 878, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 878, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 879, "R/W", 0, 0, 0ull, 0ull},
- {"PI" , 8, 8, 879, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 879, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 879, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 880, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 880, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 880, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 880, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 881, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 882, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 883, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 883, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 883, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 883, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 884, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 884, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 884, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 884, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 884, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 884, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 884, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 884, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 884, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 884, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 884, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 884, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 884, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 884, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 884, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 884, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 884, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 885, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 885, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 885, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 885, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 886, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 886, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 886, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 886, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 886, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 886, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 887, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 888, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 889, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 889, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 890, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 890, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 891, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 892, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 892, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 892, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 892, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 892, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 892, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 892, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 892, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 892, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 892, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 893, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 893, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 893, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 893, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 893, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 893, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 893, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 893, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 893, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 894, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 894, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 894, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 894, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 894, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 894, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 894, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 894, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 894, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 894, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 895, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 895, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 895, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 895, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 895, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 895, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_24_31" , 24, 8, 895, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 896, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 896, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 897, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 898, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 898, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 899, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 899, "R/W", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 899, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 899, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 899, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 899, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 899, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 900, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 900, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 900, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 900, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 900, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 900, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 900, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 900, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 900, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 900, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 900, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 901, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 901, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 901, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 901, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 901, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 901, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 901, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 901, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 901, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 901, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 901, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 901, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 901, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 902, "R/W", 1, 1, 0, 0},
- {"MLW" , 4, 6, 902, "R/W", 0, 0, 8ull, 8ull},
- {"ASLPMS" , 10, 2, 902, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 902, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 902, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 902, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 902, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 902, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 902, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ASPM" , 22, 1, 902, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 902, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 902, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 903, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 903, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 903, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 903, "RO", 1, 1, 0, 0},
- {"NLW" , 20, 6, 903, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 903, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 903, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 903, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 903, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 903, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 903, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 904, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 904, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 904, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 905, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 905, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 905, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 905, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 905, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 905, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 905, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 905, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 906, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 906, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 906, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 906, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 907, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 907, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 907, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 908, "RO", 0, 0, 15ull, 15ull},
- {"CTDS" , 4, 1, 908, "RO", 0, 0, 1ull, 1ull},
- {"ARI" , 5, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OPS" , 6, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"ATOM32S" , 7, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"ATOM64S" , 8, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"ATOM128S" , 9, 1, 908, "RO", 0, 0, 0ull, 0ull},
- {"NOROPRPR" , 10, 1, 908, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_11_11" , 11, 1, 908, "RAZ", 1, 1, 0, 0},
- {"TPH" , 12, 2, 908, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 908, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 909, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"ARI" , 5, 1, 909, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP" , 6, 1, 909, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP_EB" , 7, 1, 909, "RO", 0, 0, 0ull, 0ull},
- {"ID0_RQ" , 8, 1, 909, "RO", 0, 0, 0ull, 0ull},
- {"ID0_CP" , 9, 1, 909, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 909, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 910, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 910, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 910, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 910, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 911, "R/W", 1, 1, 0, 0},
- {"EC" , 4, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 911, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 911, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 911, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 911, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 912, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 913, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 914, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 914, "RO", 0, 0, 2ull, 2ull},
- {"NCO" , 20, 12, 914, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 915, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 915, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 915, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 915, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 915, "RAZ", 1, 1, 0, 0},
- {"UATOMBS" , 24, 1, 915, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 915, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 916, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 916, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 916, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 916, "RAZ", 1, 1, 0, 0},
- {"UATOMBM" , 24, 1, 916, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 916, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 917, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 917, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 917, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 917, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 917, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 917, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 917, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 917, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 917, "RO", 0, 0, 2ull, 2ull},
- {"UATOMBS" , 24, 1, 917, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 917, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 918, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 918, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 918, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 918, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 918, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 918, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 918, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 918, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 918, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 919, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 919, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 919, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 919, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 919, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 919, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 919, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 919, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_14_31" , 14, 18, 919, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 920, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 920, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 920, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 920, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 920, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 921, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 922, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 923, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 924, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 925, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 925, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 925, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 925, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 926, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 926, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 926, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 926, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 926, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 926, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 926, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 926, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 926, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 927, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 927, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 928, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 928, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 929, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 930, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 930, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 930, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 930, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 930, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 930, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 931, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 931, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 931, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 931, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 931, "R/W", 0, 0, 3ull, 3ull},
- {"EASPML1" , 30, 1, 931, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 931, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 932, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 932, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 932, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 932, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 932, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 932, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 932, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 932, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 932, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 932, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_22_31" , 22, 10, 932, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 933, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 933, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 933, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 933, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 933, "R/W", 0, 0, 0ull, 0ull},
- {"MFUNCN" , 0, 8, 934, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_13" , 8, 6, 934, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 934, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 934, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 934, "R/W", 0, 0, 0ull, 0ull},
- {"CX_NFUNC" , 29, 3, 934, "R/W", 0, 0, 0ull, 0ull},
- {"SKPIV" , 0, 11, 935, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 935, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 935, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 935, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 936, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 936, "R/W", 0, 0, 0ull, 0ull},
- {"M_DABORT_4UCPL" , 2, 1, 936, "R/W", 0, 0, 0ull, 0ull},
- {"M_HANDLE_FLUSH" , 3, 1, 936, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 936, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 937, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 938, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 939, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 939, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 939, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 940, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 940, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 940, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 941, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 941, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 941, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 942, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 942, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 942, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 942, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 943, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 943, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 943, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 943, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 944, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 944, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 944, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 944, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 945, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 945, "R/W", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 945, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 945, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 945, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 945, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 945, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 946, "R/W", 0, 0, 32ull, 32ull},
- {"HEADER_CREDITS" , 12, 8, 946, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_20" , 20, 1, 946, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 946, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 946, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 947, "R/W", 0, 0, 256ull, 256ull},
- {"HEADER_CREDITS" , 12, 8, 947, "R/W", 0, 0, 127ull, 127ull},
- {"RESERVED_20_20" , 20, 1, 947, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 947, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 947, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 948, "R/W", 0, 0, 392ull, 392ull},
- {"RESERVED_14_15" , 14, 2, 948, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 948, "R/W", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 948, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 949, "R/W", 0, 0, 136ull, 136ull},
- {"RESERVED_14_15" , 14, 2, 949, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 949, "R/W", 0, 0, 38ull, 38ull},
- {"RESERVED_26_31" , 26, 6, 949, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 950, "R/W", 0, 0, 679ull, 679ull},
- {"RESERVED_14_15" , 14, 2, 950, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 950, "R/W", 0, 0, 133ull, 133ull},
- {"RESERVED_26_31" , 26, 6, 950, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 951, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 951, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 951, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 951, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 951, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 951, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 951, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 952, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 953, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 954, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 954, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 954, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 954, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 954, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 954, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 954, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 954, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 954, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 955, "RO", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 955, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 955, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 955, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 955, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 955, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 956, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 956, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 956, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 956, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 956, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 956, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 956, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 956, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 956, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 957, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 957, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 957, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 957, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 957, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 958, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 12, 1, 958, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 958, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 12, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 959, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 960, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 960, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 961, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 961, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 961, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 961, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 962, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 962, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 962, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 962, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 962, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 962, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 962, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 962, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 963, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 963, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 963, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 963, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 963, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 963, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 963, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 963, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 963, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 963, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 963, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 963, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 963, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 964, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 964, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 964, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 964, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 964, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 964, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 964, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 964, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 965, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 965, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 965, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 965, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 965, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 965, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 965, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 966, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 966, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 966, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 967, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 967, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 967, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 967, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 967, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 967, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 967, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 967, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 968, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 968, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 968, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 968, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 968, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 968, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 968, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 969, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 969, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 969, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 969, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 970, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 970, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 970, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 970, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 970, "RAZ", 1, 1, 0, 0},
- {"L0SYNC" , 0, 1, 971, "RO", 0, 0, 0ull, 1ull},
- {"L1SYNC" , 1, 1, 971, "RO", 0, 0, 0ull, 1ull},
- {"L2SYNC" , 2, 1, 971, "RO", 0, 0, 0ull, 1ull},
- {"L3SYNC" , 3, 1, 971, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_4_10" , 4, 7, 971, "RAZ", 1, 1, 0, 0},
- {"PATTST" , 11, 1, 971, "RO", 0, 0, 0ull, 0ull},
- {"ALIGND" , 12, 1, 971, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_63" , 13, 51, 971, "RAZ", 1, 1, 0, 0},
- {"BIST_STATUS" , 0, 1, 972, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 972, "RAZ", 1, 1, 0, 0},
- {"BITLCK0" , 0, 1, 973, "RO", 0, 1, 0ull, 0},
- {"BITLCK1" , 1, 1, 973, "RO", 0, 1, 0ull, 0},
- {"BITLCK2" , 2, 1, 973, "RO", 0, 1, 0ull, 0},
- {"BITLCK3" , 3, 1, 973, "RO", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 973, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 974, "RAZ", 1, 1, 0, 0},
- {"SPD" , 2, 4, 974, "RO", 0, 0, 0ull, 0ull},
- {"SPDSEL0" , 6, 1, 974, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_10" , 7, 4, 974, "RAZ", 1, 1, 0, 0},
- {"LO_PWR" , 11, 1, 974, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_12_12" , 12, 1, 974, "RAZ", 1, 1, 0, 0},
- {"SPDSEL1" , 13, 1, 974, "RO", 0, 0, 1ull, 1ull},
- {"LOOPBCK1" , 14, 1, 974, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 974, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 974, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 975, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 975, "RAZ", 1, 1, 0, 0},
- {"TXFLT_EN" , 0, 1, 976, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 1, 1, 976, "R/W", 0, 0, 0ull, 1ull},
- {"RXSYNBAD_EN" , 2, 1, 976, "R/W", 0, 0, 0ull, 1ull},
- {"BITLCKLS_EN" , 3, 1, 976, "R/W", 0, 0, 0ull, 1ull},
- {"SYNLOS_EN" , 4, 1, 976, "R/W", 0, 0, 0ull, 1ull},
- {"ALGNLOS_EN" , 5, 1, 976, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 6, 1, 976, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 976, "RAZ", 1, 1, 0, 0},
- {"TXFLT" , 0, 1, 977, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 1, 1, 977, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXSYNBAD" , 2, 1, 977, "R/W1C", 0, 0, 0ull, 0ull},
- {"BITLCKLS" , 3, 1, 977, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNLOS" , 4, 1, 977, "R/W1C", 0, 0, 0ull, 0ull},
- {"ALGNLOS" , 5, 1, 977, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 6, 1, 977, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 977, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 978, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 978, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 978, "R/W1C", 0, 0, 0ull, 0ull},
- {"DROP_LN" , 4, 2, 978, "R/W", 0, 0, 0ull, 0ull},
- {"ENC_MODE" , 6, 1, 978, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 978, "RAZ", 1, 1, 0, 0},
- {"GMXENO" , 0, 1, 979, "R/W", 0, 0, 0ull, 0ull},
- {"XAUI" , 1, 1, 979, "RO", 1, 1, 0, 0},
- {"RX_SWAP" , 2, 1, 979, "R/W", 0, 1, 0ull, 0},
- {"TX_SWAP" , 3, 1, 979, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 979, "RAZ", 1, 1, 0, 0},
- {"SYNC0ST" , 0, 4, 980, "RO", 0, 1, 0ull, 0},
- {"SYNC1ST" , 4, 4, 980, "RO", 0, 1, 0ull, 0},
- {"SYNC2ST" , 8, 4, 980, "RO", 0, 1, 0ull, 0},
- {"SYNC3ST" , 12, 4, 980, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 980, "RAZ", 1, 1, 0, 0},
- {"TENGB" , 0, 1, 981, "RO", 0, 0, 1ull, 1ull},
- {"TENPASST" , 1, 1, 981, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 981, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 982, "RAZ", 1, 1, 0, 0},
- {"LPABLE" , 1, 1, 982, "RO", 0, 0, 1ull, 1ull},
- {"RCV_LNK" , 2, 1, 982, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_3_6" , 3, 4, 982, "RAZ", 1, 1, 0, 0},
- {"FLT" , 7, 1, 982, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 982, "RAZ", 1, 1, 0, 0},
- {"TENGB_R" , 0, 1, 983, "RO", 0, 0, 0ull, 0ull},
- {"TENGB_X" , 1, 1, 983, "RO", 0, 0, 1ull, 1ull},
- {"TENGB_W" , 2, 1, 983, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_9" , 3, 7, 983, "RAZ", 1, 1, 0, 0},
- {"RCVFLT" , 10, 1, 983, "RC", 0, 0, 0ull, 0ull},
- {"XMTFLT" , 11, 1, 983, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_12_13" , 12, 2, 983, "RAZ", 1, 1, 0, 0},
- {"DEV" , 14, 2, 983, "RO", 0, 0, 2ull, 2ull},
- {"RESERVED_16_63" , 16, 48, 983, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 984, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 984, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_TXPLRT" , 2, 4, 984, "R/W", 0, 0, 0ull, 0ull},
- {"XOR_RXPLRT" , 6, 4, 984, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 984, "RAZ", 1, 1, 0, 0},
- {"TX_ST" , 0, 3, 985, "RO", 0, 1, 0ull, 0},
- {"RX_ST" , 3, 2, 985, "RO", 0, 1, 0ull, 0},
- {"ALGN_ST" , 5, 3, 985, "RO", 0, 1, 0ull, 0},
- {"RXBAD" , 8, 1, 985, "RO", 0, 0, 0ull, 0ull},
- {"SYN0BAD" , 9, 1, 985, "RO", 0, 0, 0ull, 0ull},
- {"SYN1BAD" , 10, 1, 985, "RO", 0, 0, 0ull, 0ull},
- {"SYN2BAD" , 11, 1, 985, "RO", 0, 0, 0ull, 0ull},
- {"SYN3BAD" , 12, 1, 985, "RO", 0, 0, 0ull, 0ull},
- {"TERM_ERR" , 13, 1, 985, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 985, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 986, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 986, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 986, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 16, 986, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 986, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 987, "RAZ", 1, 1, 0, 0},
- {"MASK" , 3, 35, 987, "R/W", 0, 0, 34359738367ull, 34359738367ull},
- {"RESERVED_38_63" , 38, 26, 987, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 988, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 988, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 988, "R/W", 0, 0, 0ull, 1ull},
- {"BAR1_SIZ" , 4, 3, 988, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_7_63" , 7, 57, 988, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 989, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 989, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 989, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 3, 1, 989, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 4, 1, 989, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 5, 1, 989, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 6, 1, 989, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 7, 1, 989, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 989, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 990, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 990, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 990, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 990, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 990, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 990, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 6, 1, 990, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 7, 1, 990, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 8, 1, 990, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 9, 1, 990, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 990, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 991, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 991, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 992, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 992, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 993, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 993, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"FAST_LM" , 2, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 994, "R/W", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 994, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 994, "RAZ", 0, 0, 0ull, 0ull},
- {"CFG_RTRY" , 16, 16, 994, "R/W", 0, 0, 0ull, 32ull},
- {"RESERVED_32_33" , 32, 2, 994, "RAZ", 1, 1, 0, 0},
- {"PBUS" , 34, 8, 994, "RO", 1, 1, 0, 0},
- {"DNUM" , 42, 5, 994, "RO", 1, 1, 0, 0},
- {"AUTO_SD" , 47, 1, 994, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 994, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 995, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 995, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 996, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 996, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 997, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 997, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 997, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 997, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 997, "RO", 1, 1, 0, 0},
- {"NUM" , 0, 6, 998, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 998, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 999, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 999, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 1000, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 1000, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 1001, "RO", 0, 0, 0ull, 0ull},
- {"SE" , 1, 1, 1001, "R/W1C", 0, 0, 0ull, 0ull},
- {"PMEI" , 2, 1, 1001, "RO", 0, 0, 0ull, 0ull},
- {"PMEM" , 3, 1, 1001, "RO", 0, 0, 0ull, 0ull},
- {"UP_B1" , 4, 1, 1001, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_B2" , 5, 1, 1001, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_BX" , 6, 1, 1001, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B1" , 7, 1, 1001, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B2" , 8, 1, 1001, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_BX" , 9, 1, 1001, "R/W1C", 0, 0, 0ull, 0ull},
- {"EXC" , 10, 1, 1001, "RO", 0, 0, 0ull, 0ull},
- {"RDLK" , 11, 1, 1001, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_ER" , 12, 1, 1001, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_DR" , 13, 1, 1001, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 1001, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 1002, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 1002, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 1003, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 1003, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_40" , 0, 41, 1004, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 41, 23, 1004, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 1005, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 1005, "R/W", 0, 1, 4503599627370495ull, 0},
- {"RESERVED_0_11" , 0, 12, 1006, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 12, 52, 1006, "R/W", 0, 1, 4503599627370495ull, 0},
- {"SLI_P" , 0, 8, 1007, "R/W", 0, 0, 128ull, 128ull},
- {"SLI_NP" , 8, 8, 1007, "R/W", 0, 0, 16ull, 16ull},
- {"SLI_CPL" , 16, 8, 1007, "R/W", 0, 0, 128ull, 128ull},
- {"PEM_P" , 24, 8, 1007, "R/W", 0, 0, 128ull, 128ull},
- {"PEM_NP" , 32, 8, 1007, "R/W", 0, 0, 16ull, 16ull},
- {"PEM_CPL" , 40, 8, 1007, "R/W", 0, 0, 128ull, 128ull},
- {"PEAI_PPF" , 48, 8, 1007, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_56_63" , 56, 8, 1007, "RAZ", 1, 1, 0, 0},
- {"SKIP1" , 0, 7, 1008, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 1008, "RAZ", 1, 1, 0, 0},
- {"SKIP2" , 8, 7, 1008, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 1008, "RAZ", 1, 1, 0, 0},
- {"SKIP3" , 16, 7, 1008, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_31" , 23, 9, 1008, "RAZ", 1, 1, 0, 0},
- {"BIT0" , 32, 6, 1008, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_39" , 38, 2, 1008, "RAZ", 1, 1, 0, 0},
- {"BIT1" , 40, 6, 1008, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_55" , 46, 10, 1008, "RAZ", 1, 1, 0, 0},
- {"LEN" , 56, 1, 1008, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_57_63" , 57, 7, 1008, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 1009, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 1009, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 1009, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 1009, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 1009, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 22, 1010, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 1010, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 1011, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 1011, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 16, 9, 1011, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_25_31" , 25, 7, 1011, "RAZ", 1, 1, 0, 0},
- {"TAG" , 32, 8, 1011, "R/W", 0, 1, 0ull, 0},
- {"UPPER_TAG" , 40, 16, 1011, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 1011, "RAZ", 1, 1, 0, 0},
- {"POS0" , 0, 7, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS0_VAL" , 7, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS1" , 8, 7, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS1_VAL" , 15, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS2" , 16, 7, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS2_VAL" , 23, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS3" , 24, 7, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS3_VAL" , 31, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS4" , 32, 7, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS4_VAL" , 39, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS5" , 40, 7, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS5_VAL" , 47, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS6" , 48, 7, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS6_VAL" , 55, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS7" , 56, 7, 1012, "R/W", 0, 1, 0ull, 0},
- {"POS7_VAL" , 63, 1, 1012, "R/W", 0, 1, 0ull, 0},
- {"QOS" , 0, 3, 1013, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_7" , 3, 5, 1013, "RAZ", 1, 1, 0, 0},
- {"TT" , 8, 2, 1013, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 1013, "RAZ", 1, 1, 0, 0},
- {"GRP" , 16, 6, 1013, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_31" , 22, 10, 1013, "RAZ", 1, 1, 0, 0},
- {"TAG" , 32, 8, 1013, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_59" , 40, 20, 1013, "RAZ", 1, 1, 0, 0},
- {"QOS_EN" , 60, 1, 1013, "R/W", 0, 1, 0ull, 0},
- {"TT_EN" , 61, 1, 1013, "R/W", 0, 1, 0ull, 0},
- {"GRP_EN" , 62, 1, 1013, "R/W", 0, 1, 0ull, 0},
- {"TAG_EN" , 63, 1, 1013, "R/W", 0, 1, 0ull, 0},
- {"CLKEN" , 0, 1, 1014, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1014, "RAZ", 0, 1, 0ull, 0},
- {"DPRT" , 0, 16, 1015, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 1015, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 1015, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 1015, "RAZ", 1, 1, 0, 0},
- {"MAP0" , 0, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 1016, "R/W", 0, 0, 0ull, 0ull},
- {"MAP0" , 0, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 1017, "R/W", 0, 0, 0ull, 0ull},
- {"MINLEN" , 0, 16, 1018, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 1018, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 1018, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 1019, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 1019, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 1019, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 1019, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 1019, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 1019, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 1019, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1019, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 1020, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 1020, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 1020, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 1020, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 1020, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 1020, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 1020, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 1020, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 1020, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 1020, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 1020, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 1020, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_23" , 17, 7, 1020, "RAZ", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SID" , 24, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SCMD" , 25, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_TVID" , 26, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"IHMSK_DIS" , 27, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"EGRP_DIS" , 28, 1, 1020, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 1020, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 1021, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 1021, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 1022, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 1022, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 1023, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1023, "RAZ", 1, 1, 0, 0},
- {"VLAN2_QOS" , 0, 3, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1024, "RAZ", 1, 1, 0, 0},
- {"HG2_QOS" , 4, 3, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 1024, "RAZ", 1, 1, 0, 0},
- {"DIFF2_QOS" , 8, 3, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 1024, "RAZ", 1, 1, 0, 0},
- {"VLAN2_BPID" , 16, 6, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1024, "RAZ", 1, 1, 0, 0},
- {"HG2_BPID" , 24, 6, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 1024, "RAZ", 1, 1, 0, 0},
- {"DIFF2_BPID" , 32, 6, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_39" , 38, 2, 1024, "RAZ", 1, 1, 0, 0},
- {"VLAN2_PADD" , 40, 8, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"HG2_PADD" , 48, 8, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"DIFF2_PADD" , 56, 8, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"SKIP" , 0, 7, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 1025, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_EN" , 10, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"HIGIG_EN" , 11, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"CRC_EN" , 12, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 1025, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 1025, "RAZ", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"HG_QOS" , 27, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT" , 28, 4, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 1025, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 1025, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 1025, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 1025, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_CHK_SEL" , 53, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"IH_PRI" , 54, 1, 1025, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 1025, "RAZ", 1, 1, 0, 0},
- {"BPID" , 0, 6, 1026, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_15" , 6, 10, 1026, "RAZ", 1, 1, 0, 0},
- {"BASE" , 16, 8, 1026, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1026, "RAZ", 1, 1, 0, 0},
- {"BSEL_EN" , 32, 1, 1026, "R/W", 0, 0, 0ull, 0ull},
- {"BSEL_NUM" , 33, 2, 1026, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_35_35" , 35, 1, 1026, "RAZ", 1, 1, 0, 0},
- {"ALT_SKP_EN" , 36, 1, 1026, "R/W", 0, 1, 0ull, 0},
- {"ALT_SKP_SEL" , 37, 2, 1026, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_39_63" , 39, 25, 1026, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_MSB" , 40, 2, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_42_43" , 42, 2, 1027, "RAZ", 1, 1, 0, 0},
- {"GRPTAGMASK_MSB" , 44, 2, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_47" , 46, 2, 1027, "RAZ", 1, 1, 0, 0},
- {"GRPTAGBASE_MSB" , 48, 2, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 1027, "RAZ", 1, 1, 0, 0},
- {"INC_HWCHK" , 52, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"PORTADD_EN" , 53, 1, 1027, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 1027, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 1028, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 1028, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 1028, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 1028, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 1028, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 6, 1028, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 1028, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 1028, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1028, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 1029, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 1029, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 1030, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1030, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 1031, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 1031, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 1032, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 1032, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 1033, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 1033, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 1034, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 1034, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 1035, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 1035, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 1036, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 1036, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 1037, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 1037, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 1038, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 1038, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 1039, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 1039, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 1040, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 1040, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 1041, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 1041, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 1042, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 1042, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 1043, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_7" , 1, 7, 1043, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 1, 1043, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 1043, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 1044, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1044, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 1045, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 1045, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 1046, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1046, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 64, 1047, "R/W", 0, 0, 18446744073709551615ull, 18446744073709551615ull},
- {"EN" , 0, 8, 1048, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1048, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1049, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1049, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 1050, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 1050, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1050, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 1051, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 1051, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 1051, "RO", 1, 1, 0, 0},
- {"TYPE0" , 0, 16, 1052, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE1" , 16, 16, 1052, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE2" , 32, 16, 1052, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE3" , 48, 16, 1052, "R/W", 0, 0, 33024ull, 33024ull},
- {"COUNT" , 0, 32, 1053, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 1053, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 1054, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 1054, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 1055, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 1055, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 1055, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 1055, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 1056, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 1056, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 1056, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 1056, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 1056, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 1057, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 1057, "RO", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 1057, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 1057, "RO", 1, 1, 0, 0},
- {"MOD" , 0, 3, 1058, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 1058, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 1058, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 1058, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 1058, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 1058, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 1058, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 1058, "RO", 1, 1, 0, 0},
- {"STATE" , 0, 64, 1059, "RO", 1, 1, 0, 0},
- {"STATE" , 0, 64, 1060, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1061, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 1061, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 1061, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 1061, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 1061, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 1062, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 1063, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 1063, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 1063, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 1063, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 1063, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 1063, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 1063, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 1063, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 1063, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 1063, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 1063, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 1063, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 1063, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 1064, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 1064, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 1064, "RO", 1, 0, 0, 0ull},
- {"MAJOR_3" , 54, 1, 1064, "RO", 1, 0, 0, 0ull},
- {"PTP" , 55, 1, 1064, "RO", 1, 0, 0, 0ull},
- {"UID_2" , 56, 1, 1064, "RO", 1, 0, 0, 0ull},
- {"RESERVED_57_63" , 57, 7, 1064, "RO", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 1065, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 1065, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 1065, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 1065, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 1065, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 1065, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 1065, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 1065, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 1065, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 1065, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 1065, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 1065, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 1065, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 7, 1066, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 7, 7, 1066, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 14, 33, 1066, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 47, 13, 1066, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 60, 1, 1066, "RO", 1, 0, 0, 0ull},
- {"QOS" , 61, 3, 1066, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 5, 1067, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 5, 1, 1067, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 6, 1, 1067, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 7, 1, 1067, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 8, 1, 1067, "RO", 1, 0, 0, 0ull},
- {"RESERVED_9_15" , 9, 7, 1067, "RO", 1, 1, 0, 0},
- {"DOORBELL" , 16, 20, 1067, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 36, 1, 1067, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 1067, "RO", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 1068, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 1068, "RO", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 1068, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 1068, "RO", 1, 1, 0, 0},
- {"IPID" , 0, 7, 1069, "R/W", 1, 1, 0, 0},
- {"RESERVED_7_7" , 7, 1, 1069, "RAZ", 1, 1, 0, 0},
- {"EID" , 8, 5, 1069, "R/W", 1, 1, 0, 0},
- {"RESERVED_13_15" , 13, 3, 1069, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 5, 1069, "R/W", 1, 1, 0, 0},
- {"RESERVED_21_23" , 21, 3, 1069, "RAZ", 1, 1, 0, 0},
- {"PIPE" , 24, 7, 1069, "R/W", 1, 1, 0, 0},
- {"RESERVED_31_49" , 31, 19, 1069, "RAZ", 1, 1, 0, 0},
- {"MIN_PKT" , 50, 3, 1069, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 1069, "R/W", 1, 1, 0, 0},
- {"STATIC_P" , 61, 1, 1069, "R/W", 1, 0, 0, 0ull},
- {"CRC" , 62, 1, 1069, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_63_63" , 63, 1, 1069, "R/W", 1, 0, 0, 0ull},
- {"IPID" , 0, 7, 1070, "R/W", 1, 1, 0, 0},
- {"RESERVED_7_7" , 7, 1, 1070, "RAZ", 1, 1, 0, 0},
- {"EID" , 8, 5, 1070, "R/W", 1, 1, 0, 0},
- {"RESERVED_13_52" , 13, 40, 1070, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 1070, "R/W", 1, 1, 0, 0},
- {"RESERVED_61_63" , 61, 3, 1070, "RAZ", 1, 1, 0, 0},
- {"QID" , 0, 8, 1071, "R/W", 1, 0, 0, 0ull},
- {"IPID" , 8, 7, 1071, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_15_15" , 15, 1, 1071, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 16, 5, 1071, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 21, 1, 1071, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 22, 31, 1071, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 1071, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 1071, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 1071, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 1071, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 8, 1072, "R/W", 1, 0, 0, 0ull},
- {"IPID" , 8, 7, 1072, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_15_52" , 15, 38, 1072, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 1072, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 1072, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 7, 1073, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1073, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 1073, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 1073, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 1073, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 7, 1074, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1074, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 1074, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 1074, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 5, 1075, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_5_7" , 5, 3, 1075, "RAZ", 1, 1, 0, 0},
- {"PACKET" , 8, 6, 1075, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_14_31" , 14, 18, 1075, "RAZ", 1, 1, 0, 0},
- {"WORD" , 32, 15, 1075, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_47_63" , 47, 17, 1075, "RAZ", 1, 1, 0, 0},
- {"PIPE" , 0, 7, 1076, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1076, "RAZ", 1, 1, 0, 0},
- {"PACKET" , 8, 6, 1076, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_14_31" , 14, 18, 1076, "RAZ", 1, 1, 0, 0},
- {"WORD" , 32, 15, 1076, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_47_63" , 47, 17, 1076, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 1077, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 1077, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 1077, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 1077, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 1077, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 1077, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 6, 1077, "RO", 1, 0, 0, 0ull},
- {"RESERVED_21_21" , 21, 1, 1077, "RAZ", 1, 1, 0, 0},
- {"PRT_PSB7" , 22, 1, 1077, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 1077, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 1077, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 1077, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 1077, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 2, 1077, "RO", 1, 0, 0, 0ull},
- {"RESERVED_31_31" , 31, 1, 1077, "RAZ", 1, 1, 0, 0},
- {"OUT_DAT" , 32, 1, 1077, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 1077, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 1077, "RO", 1, 0, 0, 0ull},
- {"CRC" , 35, 1, 1077, "RO", 1, 0, 0, 0ull},
- {"RESERVED_36_63" , 36, 28, 1077, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 1078, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 1078, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 1079, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 1080, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 1081, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 1082, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 1083, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE1" , 4, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE2" , 8, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE3" , 12, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE4" , 16, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE5" , 20, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE6" , 24, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE7" , 28, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE8" , 32, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE9" , 36, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE10" , 40, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE11" , 44, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE12" , 48, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE13" , 52, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE14" , 56, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE15" , 60, 4, 1084, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE16" , 0, 4, 1085, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE17" , 4, 4, 1085, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE18" , 8, 4, 1085, "R/W", 0, 0, 8ull, 8ull},
- {"ENGINE19" , 12, 4, 1085, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_16_63" , 16, 48, 1085, "RAZ", 1, 1, 0, 0},
- {"ENGINE0" , 0, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE1" , 4, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE2" , 8, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE3" , 12, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE4" , 16, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE5" , 20, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE6" , 24, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE7" , 28, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE8" , 32, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE9" , 36, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE10" , 40, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE11" , 44, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE12" , 48, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE13" , 52, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE14" , 56, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"ENGINE15" , 60, 4, 1086, "R/W", 0, 0, 1ull, 1ull},
- {"MASK" , 0, 20, 1087, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1087, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 1088, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 1088, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 1088, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOOPBACK" , 3, 1, 1088, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1088, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 1089, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA_THROTTLE" , 4, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_PERF0" , 5, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_PERF1" , 6, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_PERF2" , 7, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_PERF3" , 8, 1, 1089, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 1089, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 1090, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 1090, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 1090, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBACK" , 3, 1, 1090, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1090, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1091, "RAZ", 1, 1, 0, 0},
- {"BPID0" , 4, 6, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1091, "RAZ", 1, 1, 0, 0},
- {"BPID1" , 11, 6, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_17" , 17, 1, 1091, "RAZ", 1, 1, 0, 0},
- {"BPID2" , 18, 6, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_24" , 24, 1, 1091, "RAZ", 1, 1, 0, 0},
- {"BPID3" , 25, 6, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1091, "RAZ", 1, 1, 0, 0},
- {"BPID4" , 32, 6, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_38" , 38, 1, 1091, "RAZ", 1, 1, 0, 0},
- {"BPID5" , 39, 6, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_45" , 45, 1, 1091, "RAZ", 1, 1, 0, 0},
- {"BPID6" , 46, 6, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_52_52" , 52, 1, 1091, "RAZ", 1, 1, 0, 0},
- {"BPID7" , 53, 6, 1091, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 1091, "RAZ", 1, 1, 0, 0},
- {"NUM_PORTS" , 0, 4, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"PKIND0" , 4, 6, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1092, "RAZ", 1, 1, 0, 0},
- {"PKIND1" , 11, 6, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_17" , 17, 1, 1092, "RAZ", 1, 1, 0, 0},
- {"PKIND2" , 18, 6, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_24" , 24, 1, 1092, "RAZ", 1, 1, 0, 0},
- {"PKIND3" , 25, 6, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1092, "RAZ", 1, 1, 0, 0},
- {"PKIND4" , 32, 6, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_38" , 38, 1, 1092, "RAZ", 1, 1, 0, 0},
- {"PKIND5" , 39, 6, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_45_45" , 45, 1, 1092, "RAZ", 1, 1, 0, 0},
- {"PKIND6" , 46, 6, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_52_52" , 52, 1, 1092, "RAZ", 1, 1, 0, 0},
- {"PKIND7" , 53, 6, 1092, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 1092, "RAZ", 1, 1, 0, 0},
- {"SIZE0" , 0, 8, 1093, "RO", 0, 0, 0ull, 0ull},
- {"SIZE1" , 8, 8, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE2" , 16, 8, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE3" , 24, 8, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE4" , 32, 8, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE5" , 40, 8, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE6" , 48, 8, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE7" , 56, 8, 1093, "R/W", 0, 0, 0ull, 0ull},
- {"MIN_SIZE" , 0, 16, 1094, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1094, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 1095, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1095, "RAZ", 1, 1, 0, 0},
- {"PREEMPTER" , 0, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"PREEMPTEE" , 1, 1, 1096, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1096, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1097, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 1097, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1097, "RAZ", 1, 1, 0, 0},
- {"INT_MASK" , 0, 32, 1098, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1098, "RAZ", 0, 0, 0ull, 0ull},
- {"WQE_WORD" , 0, 4, 1099, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_4_63" , 4, 60, 1099, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 1100, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 1101, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 1102, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 1103, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 1103, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 1103, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 1103, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 1103, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1104, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 1104, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 1104, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 1104, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 1104, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 1105, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 1105, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 1105, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 1105, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 1106, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 1106, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 1106, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 1106, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 1106, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 1106, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 1106, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 1106, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 1106, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 1106, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 1107, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1108, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 1108, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 1108, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1109, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 1109, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 1109, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 1109, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 1109, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 1109, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 1109, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 1110, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 1110, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 1111, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 1112, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 1113, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 1114, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 1114, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 1114, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 1114, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 1114, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 1114, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 1114, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 1114, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 1114, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 1114, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 1114, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 1114, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 1114, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 1114, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 1114, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 1114, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 1114, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 1114, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1115, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 1115, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 1115, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 1116, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 1116, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1117, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 1117, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 1117, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1118, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 1118, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 1118, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 1118, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 1118, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 1118, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 1118, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1119, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1119, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1120, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1120, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 1121, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 1121, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1122, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 1123, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 1123, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1123, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 1124, "R/W", 0, 0, 0ull, 0ull},
- {"EER_VAL" , 9, 1, 1124, "RO", 0, 0, 0ull, 0ull},
- {"EER_LCK" , 10, 1, 1124, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 1124, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 1125, "RO", 1, 1, 0, 0},
- {"KEY" , 0, 64, 1126, "WO", 0, 0, 0ull, 0ull},
- {"DAT" , 0, 64, 1127, "RO", 1, 1, 0, 0},
- {"NCB_CMD" , 0, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_0" , 2, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_1" , 3, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_0" , 4, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_1" , 5, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 1128, "RAZ", 1, 1, 0, 0},
- {"P2N1_P1" , 9, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_24" , 19, 6, 1128, "RAZ", 1, 1, 0, 0},
- {"CPL_P1" , 25, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_O" , 27, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"N2P1_C" , 28, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_O" , 29, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"NCB_REQ" , 31, 1, 1128, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1128, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_4" , 1, 4, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"PTLP_RO" , 5, 1, 1129, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 1129, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 1129, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 1129, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 1129, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 1129, "R/W", 0, 0, 3ull, 3ull},
- {"WAITL_COM" , 16, 1, 1129, "R/W", 0, 1, 0ull, 0},
- {"DIS_PORT" , 17, 1, 1129, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTA" , 18, 1, 1129, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 19, 1, 1129, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 20, 1, 1129, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 21, 1, 1129, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 1129, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 1130, "RO", 1, 1, 0, 0},
- {"P0_NTAGS" , 8, 6, 1130, "R/W", 0, 0, 32ull, 32ull},
- {"P1_NTAGS" , 14, 6, 1130, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_20_63" , 20, 44, 1130, "RAZ", 1, 1, 0, 0},
- {"P0_FCNT" , 0, 6, 1131, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 1131, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 1131, "RO", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 1131, "RO", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 1131, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 1132, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 1132, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 1132, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 32, 1133, "R/W", 0, 1, 0ull, 0},
- {"ADBG_SEL" , 32, 1, 1133, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 1133, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1134, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1134, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1135, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 1135, "R/W", 0, 1, 0ull, 0},
- {"TIM" , 0, 32, 1136, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1136, "RAZ", 1, 1, 0, 0},
- {"RML_TO" , 0, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 1137, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"PIPE_ERR" , 61, 1, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT1" , 17, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"MAC0_INT" , 18, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"MAC1_INT" , 19, 1, 1138, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_20_31" , 20, 12, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"PIPE_ERR" , 61, 1, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 1138, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT" , 4, 1, 1139, "RO", 0, 0, 0ull, 0ull},
- {"PTIME" , 5, 1, 1139, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_WI" , 9, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_B0" , 10, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_WI" , 11, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_B0" , 12, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_WI" , 13, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_B0" , 14, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_WI" , 15, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO_INT0" , 16, 1, 1139, "RO", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 1139, "RO", 0, 0, 0ull, 0ull},
- {"MAC0_INT" , 18, 1, 1139, "RO", 0, 0, 0ull, 0ull},
- {"MAC1_INT" , 19, 1, 1139, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 1139, "RAZ", 1, 1, 0, 0},
- {"DMAFI" , 32, 2, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 1139, "RO", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 1139, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 1139, "RAZ", 1, 1, 0, 0},
- {"PIDBOF" , 48, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 1139, "RAZ", 1, 1, 0, 0},
- {"PGL_ERR" , 52, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_58_59" , 58, 2, 1139, "RAZ", 1, 1, 0, 0},
- {"ILL_PAD" , 60, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIPE_ERR" , 61, 1, 1139, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 1139, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 1140, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 1141, "RO", 0, 1, 0ull, 0},
- {"P0_PCNT" , 0, 8, 1142, "R/W", 0, 0, 128ull, 128ull},
- {"P0_NCNT" , 8, 8, 1142, "R/W", 0, 0, 16ull, 16ull},
- {"P0_CCNT" , 16, 8, 1142, "R/W", 0, 0, 128ull, 128ull},
- {"P1_PCNT" , 24, 8, 1142, "R/W", 0, 0, 128ull, 128ull},
- {"P1_NCNT" , 32, 8, 1142, "R/W", 0, 0, 16ull, 16ull},
- {"P1_CCNT" , 40, 8, 1142, "R/W", 0, 0, 128ull, 128ull},
- {"P0_P_D" , 48, 1, 1142, "R/W", 0, 0, 1ull, 1ull},
- {"P0_N_D" , 49, 1, 1142, "R/W", 0, 0, 1ull, 1ull},
- {"P0_C_D" , 50, 1, 1142, "R/W", 0, 0, 1ull, 1ull},
- {"P1_P_D" , 51, 1, 1142, "R/W", 0, 0, 1ull, 1ull},
- {"P1_N_D" , 52, 1, 1142, "R/W", 0, 0, 1ull, 1ull},
- {"P1_C_D" , 53, 1, 1142, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_54_63" , 54, 10, 1142, "RAZ", 1, 1, 0, 0},
- {"NUM" , 0, 8, 1143, "RO", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 1143, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 1144, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 1144, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"BA" , 2, 28, 1145, "R/W", 0, 1, 0ull, 0},
- {"RTYPE" , 30, 2, 1145, "R/W", 0, 1, 0ull, 0},
- {"WTYPE" , 32, 2, 1145, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 1145, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 1145, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 3, 1145, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 42, 1, 1145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 1145, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 1146, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 1147, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 1148, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 1149, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 1150, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 1151, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 1152, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 1153, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 1154, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 1154, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1154, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 64, 1155, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 1156, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 1157, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 1158, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1160, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1161, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1162, "R/W", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 1163, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 1163, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1163, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 1164, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 1164, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1165, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 1165, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1165, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 1166, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 1166, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 1166, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 1167, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 1167, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1167, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 32, 22, 1168, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 1168, "RO", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 1169, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 1169, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 1170, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 1171, "R/W", 0, 1, 0ull, 0},
- {"FCNT" , 32, 5, 1171, "RO", 0, 1, 0ull, 0},
- {"WRP" , 37, 9, 1171, "RO", 0, 1, 0ull, 0},
- {"RRP" , 46, 9, 1171, "RO", 0, 1, 0ull, 0},
- {"MAX" , 55, 9, 1171, "RO", 0, 1, 16ull, 0},
- {"NTAG" , 0, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"NTT" , 1, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"NGRP" , 2, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"NQOS" , 3, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"NGRPEXT" , 4, 2, 1172, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 1172, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_13" , 13, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 1172, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_20" , 16, 5, 1172, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"RNTAG" , 22, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"RNTT" , 23, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"RNGRP" , 24, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"RNQOS" , 25, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"RNGRPEXT" , 26, 2, 1172, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 1172, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_35" , 35, 1, 1172, "RAZ", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 1172, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_42" , 38, 5, 1172, "RAZ", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 1172, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 1172, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 1173, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 16, 7, 1173, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 1173, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1174, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 4, 60, 1174, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 1175, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 1175, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 1176, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1176, "RO", 0, 1, 0ull, 0},
- {"PORT" , 0, 32, 1177, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1177, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1178, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1178, "RAZ", 1, 1, 0, 0},
- {"PKT_BP" , 0, 4, 1179, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 4, 1, 1179, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1179, "RAZ", 1, 1, 0, 0},
- {"ES" , 0, 64, 1180, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 1181, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1181, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 1182, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1182, "RAZ", 1, 1, 0, 0},
- {"DPTR" , 0, 32, 1183, "R/W", 0, 0, 0ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 1183, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1184, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1184, "RO", 0, 1, 0ull, 0},
- {"RD_CNT" , 0, 32, 1185, "RO", 0, 1, 0ull, 0},
- {"WR_CNT" , 32, 32, 1185, "RO", 0, 1, 0ull, 0},
- {"PP" , 0, 64, 1186, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 0, 1, 1187, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 1187, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 1187, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 1187, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 1187, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 1187, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 1187, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 22, 1, 1187, "R/W", 0, 0, 0ull, 1ull},
- {"PIN_RST" , 23, 1, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_39" , 24, 16, 1187, "RAZ", 1, 1, 0, 0},
- {"PRC_IDLE" , 40, 1, 1187, "RO", 0, 1, 0ull, 0},
- {"RESERVED_41_47" , 41, 7, 1187, "RAZ", 1, 1, 0, 0},
- {"GII_RDS" , 48, 7, 1187, "RO", 0, 1, 0ull, 0},
- {"GII_ERST" , 55, 1, 1187, "RO", 0, 1, 0ull, 0},
- {"PRD_RDS" , 56, 7, 1187, "RO", 0, 1, 0ull, 0},
- {"PRD_ERST" , 63, 1, 1187, "RO", 0, 1, 0ull, 0},
- {"ENB" , 0, 32, 1188, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1188, "RAZ", 1, 1, 0, 0},
- {"RDSIZE" , 0, 64, 1189, "R/W", 0, 1, 0ull, 0},
- {"IS_64B" , 0, 32, 1190, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1190, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1191, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 22, 1191, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_63" , 54, 10, 1191, "RAZ", 1, 1, 0, 0},
- {"IPTR" , 0, 32, 1192, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1192, "RAZ", 1, 1, 0, 0},
- {"BMODE" , 0, 32, 1193, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1193, "RAZ", 1, 1, 0, 0},
- {"BP_EN" , 0, 32, 1194, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 1194, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 1195, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1195, "RAZ", 1, 1, 0, 0},
- {"WMARK" , 0, 32, 1196, "R/W", 0, 0, 0ull, 14ull},
- {"RESERVED_32_63" , 32, 32, 1196, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 64, 1197, "R/W", 0, 1, 0ull, 0},
- {"OUT_RST" , 0, 32, 1198, "RO", 0, 1, 0ull, 0},
- {"IN_RST" , 32, 32, 1198, "RO", 0, 1, 0ull, 0},
- {"ES" , 0, 64, 1199, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 1200, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1200, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 1201, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1201, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1202, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1202, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1203, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1203, "RAZ", 1, 1, 0, 0},
- {"PKIND" , 0, 6, 1204, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 1204, "RAZ", 1, 1, 0, 0},
- {"BPKIND" , 8, 6, 1204, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 1204, "RAZ", 1, 1, 0, 0},
- {"PKINDR" , 16, 6, 1204, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_23" , 22, 2, 1204, "RAZ", 1, 1, 0, 0},
- {"RPK_ENB" , 24, 1, 1204, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 1204, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 3, 1205, "R/W", 0, 0, 2ull, 2ull},
- {"BAR0_D" , 3, 1, 1205, "R/W", 0, 0, 0ull, 0ull},
- {"WIND_D" , 4, 1, 1205, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1205, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 1206, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 1207, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 1208, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 1208, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 1208, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 1208, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 1209, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 1209, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 1209, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 1209, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 1209, "RO", 0, 1, 1ull, 0},
- {"RESERVED_47_47" , 47, 1, 1209, "RAZ", 1, 1, 0, 0},
- {"NNP1" , 48, 8, 1209, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 1209, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 1210, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 1210, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 1210, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 1210, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 1210, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 7, 1211, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 1211, "RAZ", 1, 1, 0, 0},
- {"NUMP" , 16, 8, 1211, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 1211, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 1212, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 1212, "R/W", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 1212, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_51_63" , 51, 13, 1212, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 1213, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 1214, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 1214, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 1214, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 1214, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 1215, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 1216, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1216, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 1217, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 1217, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 1218, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 1218, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 1218, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 1218, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 1218, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 1218, "R/W", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 1218, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 1218, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 1218, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1218, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 1219, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1219, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 1219, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 1219, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 1219, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1219, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1220, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1220, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 1221, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 1221, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 1221, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1221, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 1222, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 1222, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 1222, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1222, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 1223, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_6_7" , 6, 2, 1223, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 6, 1223, "R/W", 0, 0, 19ull, 19ull},
- {"RESERVED_14_63" , 14, 50, 1223, "RAZ", 1, 1, 0, 0},
- {"ACT_CYC" , 0, 64, 1224, "RO", 0, 1, 0ull, 0},
- {"OTH" , 0, 2, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 1225, "RAZ", 1, 1, 0, 0},
- {"PEND" , 8, 2, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 1225, "RAZ", 1, 1, 0, 0},
- {"FIDX" , 16, 1, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 1225, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 20, 1, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 1225, "RAZ", 1, 1, 0, 0},
- {"NCBO" , 24, 4, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_30" , 28, 3, 1225, "RAZ", 1, 1, 0, 0},
- {"SOC" , 31, 1, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_33" , 32, 2, 1225, "RAZ", 1, 1, 0, 0},
- {"RWI_DAT" , 34, 1, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_41" , 35, 7, 1225, "RAZ", 1, 1, 0, 0},
- {"RWO" , 42, 2, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RWO_DAT" , 44, 1, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_51" , 45, 7, 1225, "RAZ", 1, 1, 0, 0},
- {"FPTR" , 52, 2, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_59" , 54, 6, 1225, "RAZ", 1, 1, 0, 0},
- {"ODU_PREF" , 60, 2, 1225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 1225, "RAZ", 1, 1, 0, 0},
- {"RWEN" , 0, 1, 1226, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 1, 1, 1226, "R/W", 0, 0, 0ull, 0ull},
- {"LDT" , 2, 1, 1226, "R/W", 0, 0, 1ull, 1ull},
- {"STT" , 3, 1, 1226, "R/W", 0, 0, 1ull, 1ull},
- {"RWQ_BYP_DIS" , 4, 1, 1226, "R/W", 0, 0, 0ull, 0ull},
- {"RWIO_BYP_DIS" , 5, 1, 1226, "R/W", 0, 0, 0ull, 0ull},
- {"WFE_THR" , 6, 1, 1226, "R/W", 0, 0, 0ull, 0ull},
- {"RWO_FLUSH" , 7, 1, 1226, "WR0", 0, 0, 0ull, 0ull},
- {"SSO_CCLK_DIS" , 8, 1, 1226, "R/W", 0, 0, 0ull, 0ull},
- {"SOC_CCAM_DIS" , 9, 1, 1226, "R/W", 0, 0, 0ull, 0ull},
- {"RWQ_ALLOC_DIS" , 10, 1, 1226, "R/W", 0, 0, 0ull, 0ull},
- {"QCK_SW_DIS" , 11, 1, 1226, "R/W", 0, 0, 0ull, 0ull},
- {"QCK_GW_RSP_DIS" , 12, 1, 1226, "R/W", 0, 0, 0ull, 0ull},
- {"QCK_GW_RSP_ADJ" , 13, 3, 1226, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1226, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 64, 1227, "R/W", 0, 1, 0ull, 0},
- {"FIDX_SBE" , 0, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"FIDX_DBE" , 1, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"IDX_SBE" , 2, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"IDX_DBE" , 3, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"OTH_SBE1" , 4, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"OTH_DBE1" , 5, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"OTH_SBE0" , 6, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"OTH_DBE0" , 7, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"PND_SBE1" , 8, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"PND_DBE1" , 9, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"PND_SBE0" , 10, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"PND_DBE0" , 11, 1, 1228, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_12_31" , 12, 20, 1228, "RAZ", 1, 1, 0, 0},
- {"IOP" , 32, 11, 1228, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_43_44" , 43, 2, 1228, "RAZ", 1, 1, 0, 0},
- {"FPE" , 45, 1, 1228, "R/W1C", 0, 0, 0ull, 0ull},
- {"AWE" , 46, 1, 1228, "R/W1C", 0, 0, 0ull, 0ull},
- {"BFP" , 47, 1, 1228, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 1228, "RAZ", 1, 1, 0, 0},
- {"FIDX_SBE_IE" , 0, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"FIDX_DBE_IE" , 1, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"IDX_SBE_IE" , 2, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"IDX_DBE_IE" , 3, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"OTH_SBE1_IE" , 4, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"OTH_DBE1_IE" , 5, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"OTH_SBE0_IE" , 6, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"OTH_DBE0_IE" , 7, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"PND_SBE1_IE" , 8, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"PND_DBE1_IE" , 9, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"PND_SBE0_IE" , 10, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"PND_DBE0_IE" , 11, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_31" , 12, 20, 1229, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 11, 1229, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_44" , 43, 2, 1229, "RAZ", 1, 1, 0, 0},
- {"FPE_IE" , 45, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"AWE_IE" , 46, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"BFP_IE" , 47, 1, 1229, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 1229, "RAZ", 1, 1, 0, 0},
- {"ECC_ENA" , 0, 1, 1230, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND" , 1, 2, 1230, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1230, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1231, "RAZ", 1, 1, 0, 0},
- {"SYNDROM" , 4, 5, 1231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 1231, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 16, 11, 1231, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 1231, "RAZ", 1, 1, 0, 0},
- {"FPAGE_CNT" , 0, 32, 1232, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1232, "RAZ", 1, 1, 0, 0},
- {"GWE_DIS" , 0, 1, 1233, "R/W", 0, 0, 0ull, 0ull},
- {"GWE_RAH" , 1, 1, 1233, "R/W", 0, 0, 0ull, 0ull},
- {"GWE_FPOR" , 2, 1, 1233, "R/W", 0, 0, 0ull, 0ull},
- {"GWE_POE" , 3, 1, 1233, "R/W", 0, 0, 0ull, 0ull},
- {"GWE_HVY_DIS" , 4, 1, 1233, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_7" , 5, 3, 1233, "RAZ", 1, 1, 0, 0},
- {"ODU_BMP_DIS" , 8, 1, 1233, "R/W", 0, 0, 0ull, 0ull},
- {"ODU_PRF_DIS" , 9, 1, 1233, "R/W", 0, 0, 0ull, 0ull},
- {"GWE_RFPGW_DIS" , 10, 1, 1233, "R/W", 0, 0, 0ull, 0ull},
- {"ODU_FFPGW_DIS" , 11, 1, 1233, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 1233, "RAZ", 1, 1, 0, 0},
- {"ECC_ENA" , 0, 1, 1234, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND" , 1, 2, 1234, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1234, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1235, "RAZ", 1, 1, 0, 0},
- {"SYNDROM" , 4, 5, 1235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_15" , 9, 7, 1235, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 16, 11, 1235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 1235, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 1236, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1236, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 1237, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1237, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 1238, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 1238, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 1239, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 1239, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 1240, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 1240, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 12, 1241, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 1241, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 1242, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_10_63" , 10, 54, 1242, "RAZ", 1, 1, 0, 0},
- {"ECC_ENA0" , 0, 1, 1243, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND0" , 1, 2, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA1" , 3, 1, 1243, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND1" , 4, 2, 1243, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1243, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1244, "RAZ", 1, 1, 0, 0},
- {"SYNDROM0" , 4, 7, 1244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 1244, "RAZ", 1, 1, 0, 0},
- {"ADDR0" , 16, 11, 1244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_35" , 27, 9, 1244, "RAZ", 1, 1, 0, 0},
- {"SYNDROM1" , 36, 7, 1244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_43_47" , 43, 5, 1244, "RAZ", 1, 1, 0, 0},
- {"ADDR1" , 48, 11, 1244, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 1244, "RAZ", 1, 1, 0, 0},
- {"ECC_ENA0" , 0, 1, 1245, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND0" , 1, 2, 1245, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ENA1" , 3, 1, 1245, "R/W", 0, 0, 1ull, 1ull},
- {"FLIP_SYND1" , 4, 2, 1245, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1245, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1246, "RAZ", 1, 1, 0, 0},
- {"SYNDROM0" , 4, 7, 1246, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 1246, "RAZ", 1, 1, 0, 0},
- {"ADDR0" , 16, 11, 1246, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_35" , 27, 9, 1246, "RAZ", 1, 1, 0, 0},
- {"SYNDROM1" , 36, 7, 1246, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_43_47" , 43, 5, 1246, "RAZ", 1, 1, 0, 0},
- {"ADDR1" , 48, 11, 1246, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_59_63" , 59, 5, 1246, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 64, 1247, "R/W", 0, 0, 18446744073709551615ull, 18446744073709551615ull},
- {"QOS0_PRI" , 0, 4, 1248, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_7" , 4, 4, 1248, "RAZ", 1, 1, 0, 0},
- {"QOS1_PRI" , 8, 4, 1248, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_15" , 12, 4, 1248, "RAZ", 1, 1, 0, 0},
- {"QOS2_PRI" , 16, 4, 1248, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_23" , 20, 4, 1248, "RAZ", 1, 1, 0, 0},
- {"QOS3_PRI" , 24, 4, 1248, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 1248, "RAZ", 1, 1, 0, 0},
- {"QOS4_PRI" , 32, 4, 1248, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 1248, "RAZ", 1, 1, 0, 0},
- {"QOS5_PRI" , 40, 4, 1248, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_47" , 44, 4, 1248, "RAZ", 1, 1, 0, 0},
- {"QOS6_PRI" , 48, 4, 1248, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_52_55" , 52, 4, 1248, "RAZ", 1, 1, 0, 0},
- {"QOS7_PRI" , 56, 4, 1248, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 1248, "RAZ", 1, 1, 0, 0},
- {"PP_STRICT" , 0, 32, 1249, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1249, "RAZ", 1, 1, 0, 0},
- {"RNDS_QOS" , 0, 8, 1250, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_8_63" , 8, 56, 1250, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 12, 1251, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_13" , 12, 2, 1251, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 14, 12, 1251, "R/W", 0, 1, 241ull, 0},
- {"RESERVED_26_27" , 26, 2, 1251, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 28, 12, 1251, "RO", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 1251, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 0, 12, 1252, "RO", 0, 1, 2000ull, 0},
- {"RESERVED_12_13" , 12, 2, 1252, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 14, 12, 1252, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 1252, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 1253, "WR0", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1253, "RAZ", 1, 1, 0, 0},
- {"RCTR" , 0, 5, 1254, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_6" , 5, 2, 1254, "RAZ", 1, 1, 0, 0},
- {"PTR" , 7, 31, 1254, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1254, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 1255, "RAZ", 1, 1, 0, 0},
- {"FPTR" , 7, 31, 1255, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_56" , 38, 19, 1255, "RAZ", 1, 1, 0, 0},
- {"CNT" , 57, 6, 1255, "RO", 0, 1, 0ull, 0},
- {"VAL" , 63, 1, 1255, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_6" , 0, 7, 1256, "RAZ", 1, 1, 0, 0},
- {"FPTR" , 7, 31, 1256, "WO", 0, 1, 0ull, 0},
- {"RESERVED_38_58" , 38, 21, 1256, "RAZ", 1, 1, 0, 0},
- {"CNT" , 59, 4, 1256, "RO", 0, 1, 0ull, 0},
- {"FULL" , 63, 1, 1256, "RO", 0, 1, 0ull, 0},
- {"RCTR" , 0, 5, 1257, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_6" , 5, 2, 1257, "RAZ", 1, 1, 0, 0},
- {"PTR" , 7, 31, 1257, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1257, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 64, 1258, "R/W", 0, 1, 0ull, 0},
- {"WA_PC" , 0, 64, 1259, "R/W", 0, 1, 0ull, 0},
- {"WA_PC" , 0, 64, 1260, "R/W", 0, 1, 0ull, 0},
- {"WQ_INT" , 0, 64, 1261, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_CNT" , 0, 12, 1262, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_13" , 12, 2, 1262, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 14, 12, 1262, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_27" , 26, 2, 1262, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 28, 4, 1262, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1262, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1263, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 1263, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 1263, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 1263, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 1263, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 12, 1264, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_12_13" , 12, 2, 1264, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 14, 12, 1264, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_27" , 26, 2, 1264, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 28, 4, 1264, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 32, 1, 1264, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 1264, "RAZ", 1, 1, 0, 0},
- {"IQ_DIS" , 0, 64, 1265, "R/W1", 0, 1, 0ull, 0},
- {"WS_PC" , 0, 64, 1266, "R/W", 0, 1, 0ull, 0},
- {"RDS_MEM" , 0, 1, 1267, "RO", 1, 0, 0, 0ull},
- {"LSLR_FIFO" , 1, 1, 1267, "RO", 1, 0, 0, 0ull},
- {"WQE_FIFO" , 2, 1, 1267, "RO", 1, 0, 0, 0ull},
- {"RESERVED_3_63" , 3, 61, 1267, "RAZ", 1, 1, 0, 0},
- {"FSM0_STATE" , 0, 4, 1268, "RO", 0, 0, 0ull, 0ull},
- {"FSM1_STATE" , 4, 4, 1268, "RO", 0, 0, 0ull, 0ull},
- {"FSM2_STATE" , 8, 4, 1268, "RO", 0, 0, 0ull, 0ull},
- {"FSM3_STATE" , 12, 4, 1268, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1268, "RAZ", 1, 1, 0, 0},
- {"WQE_FIFO_LEVEL" , 32, 8, 1268, "RO", 0, 0, 0ull, 0ull},
- {"RWF_FIFO_LEVEL" , 40, 5, 1268, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_45_47" , 45, 3, 1268, "RAZ", 1, 1, 0, 0},
- {"GNT_FIFO_LEVEL" , 48, 3, 1268, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_51_55" , 51, 5, 1268, "RAZ", 1, 1, 0, 0},
- {"MEM_ALLOC_REG" , 56, 8, 1268, "RO", 0, 0, 0ull, 0ull},
- {"RINGS_PENDING_VEC" , 0, 64, 1269, "RO", 0, 0, 0ull, 0ull},
- {"ECC_EN" , 0, 1, 1270, "R/W", 0, 0, 1ull, 1ull},
- {"ECC_FLP_SYN" , 1, 2, 1270, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1270, "RAZ", 1, 1, 0, 0},
- {"FR_RN_TT" , 0, 22, 1271, "R/W", 0, 0, 1024ull, 1024ull},
- {"RESERVED_22_31" , 22, 10, 1271, "RAZ", 1, 1, 0, 0},
- {"THLD_GP" , 32, 22, 1271, "R/W", 0, 0, 1024ull, 1024ull},
- {"RESERVED_54_63" , 54, 10, 1271, "RAZ", 1, 1, 0, 0},
- {"GPIO_EN" , 0, 64, 1272, "RO", 0, 0, 0ull, 0ull},
- {"INT0" , 0, 64, 1273, "R/W1C", 0, 0, 0ull, 0ull},
- {"INT0_EN" , 0, 64, 1274, "R/W", 0, 0, 0ull, 0ull},
- {"RING_ID" , 0, 6, 1275, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1275, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 1276, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 1276, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1276, "RAZ", 1, 1, 0, 0},
- {"SBE_EN" , 0, 1, 1277, "R/W", 0, 0, 0ull, 0ull},
- {"DBE_EN" , 1, 1, 1277, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1277, "RAZ", 1, 1, 0, 0},
- {"ADD" , 0, 8, 1278, "RO", 0, 0, 0ull, 0ull},
- {"SYND" , 8, 7, 1278, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 1278, "RAZ", 1, 1, 0, 0},
- {"ORG_RDS_DAT" , 0, 48, 1279, "RO", 0, 0, 0ull, 0ull},
- {"ORG_ECC" , 48, 7, 1279, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 1279, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 1280, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 1280, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 1280, "WO", 0, 0, 0ull, 0ull},
- {"ENA_DFB" , 3, 1, 1280, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_GPIO" , 4, 1, 1280, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO_EDGE" , 5, 2, 1280, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 1280, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 1281, "R/W", 1, 0, 0, 0ull},
- {"TIMERCOUNT" , 22, 22, 1281, "R/W", 1, 0, 0, 0ull},
- {"INTC" , 44, 2, 1281, "R/W", 1, 0, 0, 0ull},
- {"ENA" , 46, 1, 1281, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_47_63" , 47, 17, 1281, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 1282, "R/W", 1, 0, 0, 0ull},
- {"BUCKET" , 20, 20, 1282, "R/W", 1, 0, 0, 0ull},
- {"CPOOL" , 40, 3, 1282, "R/W", 1, 0, 0, 0ull},
- {"ENA_DFB" , 43, 1, 1282, "R/W", 1, 0, 0, 0ull},
- {"ENA_DWB" , 44, 1, 1282, "R/W", 1, 0, 0, 0ull},
- {"ENA_PRD" , 45, 1, 1282, "R/W", 1, 0, 0, 0ull},
- {"ENA_GPIO" , 46, 1, 1282, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_47_63" , 47, 17, 1282, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 31, 1283, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_33" , 31, 3, 1283, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 34, 13, 1283, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_47_63" , 47, 17, 1283, "RAZ", 1, 1, 0, 0},
- {"CUR_BUCKET" , 0, 20, 1284, "RO", 0, 0, 0ull, 0ull},
- {"TIMERCOUNT" , 20, 22, 1284, "RO", 0, 0, 4096ull, 0ull},
- {"FR_RN_HT" , 42, 22, 1284, "RO", 0, 0, 0ull, 0ull},
- {"RING_ESR" , 0, 2, 1285, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1285, "RAZ", 1, 1, 0, 0},
- {"TDF" , 0, 1, 1286, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1286, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"CLKALWAYS" , 15, 1, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"RDAT_MD" , 16, 1, 1287, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1287, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 1288, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 1288, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 1288, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 1289, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 1289, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 1289, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1289, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 1289, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1290, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1290, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1291, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1291, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1292, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1292, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1292, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1292, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1292, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1292, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1293, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1293, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1293, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1293, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1293, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 8, 1294, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1294, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1294, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1294, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1294, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1294, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1294, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 1295, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 1295, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 1295, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 1295, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1295, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 1296, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 5, 1297, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1297, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1298, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1298, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1299, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1299, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1300, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1300, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1300, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1300, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1300, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1300, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1301, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1301, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1301, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1301, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1301, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 8, 1302, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1302, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1302, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1302, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1302, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1302, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1302, "R/W", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1303, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1303, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1304, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1304, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1305, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1305, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1305, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1305, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1305, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1305, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1306, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1306, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1306, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1306, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1306, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 8, 1307, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 1307, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1307, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1307, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1307, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1307, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1307, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 1308, "R/W", 0, 1, 0ull, 0},
- {"LPL" , 5, 27, 1308, "R/W", 0, 1, 0ull, 0},
- {"CF" , 0, 1, 1309, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_31" , 1, 31, 1309, "R/W", 0, 0, 0ull, 0ull},
- {"CTRLDSSEG" , 0, 32, 1310, "R/W", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1311, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_31" , 14, 18, 1311, "RO", 0, 0, 0ull, 0ull},
- {"CAPLENGTH" , 0, 8, 1312, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_15" , 8, 8, 1312, "RO", 0, 0, 0ull, 0ull},
- {"HCIVERSION" , 16, 16, 1312, "RO", 0, 0, 256ull, 256ull},
- {"AC64" , 0, 1, 1313, "RO", 0, 0, 1ull, 1ull},
- {"PFLF" , 1, 1, 1313, "RO", 0, 0, 0ull, 0ull},
- {"ASPC" , 2, 1, 1313, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1313, "RO", 0, 0, 0ull, 0ull},
- {"IST" , 4, 4, 1313, "RO", 0, 0, 2ull, 2ull},
- {"EECP" , 8, 8, 1313, "RO", 0, 0, 160ull, 160ull},
- {"RESERVED_16_31" , 16, 16, 1313, "RO", 0, 0, 0ull, 0ull},
- {"N_PORTS" , 0, 4, 1314, "RO", 0, 0, 2ull, 2ull},
- {"PPC" , 4, 1, 1314, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 1314, "RO", 0, 0, 0ull, 0ull},
- {"PRR" , 7, 1, 1314, "RO", 0, 0, 0ull, 0ull},
- {"N_PCC" , 8, 4, 1314, "RO", 0, 0, 2ull, 2ull},
- {"N_CC" , 12, 4, 1314, "RO", 0, 0, 1ull, 1ull},
- {"P_INDICATOR" , 16, 1, 1314, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 1314, "RO", 0, 0, 0ull, 0ull},
- {"DPN" , 20, 4, 1314, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1314, "RO", 0, 0, 0ull, 0ull},
- {"EN" , 0, 1, 1315, "R/W", 0, 0, 0ull, 0ull},
- {"MFMC" , 1, 13, 1315, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 1315, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_0" , 0, 1, 1316, "R/W", 0, 0, 0ull, 0ull},
- {"TA_OFF" , 1, 8, 1316, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1316, "R/W", 0, 0, 0ull, 0ull},
- {"TXTX_TADAO" , 10, 3, 1316, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 1316, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_RW" , 0, 1, 1317, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_FW" , 1, 1, 1317, "R/W", 0, 0, 0ull, 0ull},
- {"PESD" , 2, 1, 1317, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1317, "RAZ", 0, 0, 0ull, 0ull},
- {"NAKRF_DIS" , 4, 1, 1317, "R/W", 0, 0, 0ull, 0ull},
- {"AUTO_DIS" , 5, 1, 1317, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 1317, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_30" , 0, 31, 1318, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1318, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1319, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 1320, "R/W", 0, 1, 0ull, 0},
- {"BADDR" , 12, 20, 1320, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1321, "RO", 0, 0, 0ull, 0ull},
- {"CSC" , 1, 1, 1321, "R/W1C", 0, 0, 0ull, 0ull},
- {"PED" , 2, 1, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"PEDC" , 3, 1, 1321, "R/W1C", 0, 0, 0ull, 0ull},
- {"OCA" , 4, 1, 1321, "RO", 0, 0, 0ull, 0ull},
- {"OCC" , 5, 1, 1321, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPR" , 6, 1, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"SPD" , 7, 1, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"PRST" , 8, 1, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1321, "RO", 0, 0, 0ull, 0ull},
- {"LSTS" , 10, 2, 1321, "RO", 0, 1, 0ull, 0},
- {"PP" , 12, 1, 1321, "RO", 0, 0, 1ull, 1ull},
- {"PO" , 13, 1, 1321, "R/W", 0, 0, 1ull, 0ull},
- {"PIC" , 14, 2, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"PTC" , 16, 4, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"WKCNNT_E" , 20, 1, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"WKDSCNNT_E" , 21, 1, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"WKOC_E" , 22, 1, 1321, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 1321, "RO", 0, 0, 0ull, 0ull},
- {"RS" , 0, 1, 1322, "R/W", 0, 0, 0ull, 1ull},
- {"HCRESET" , 1, 1, 1322, "R/W", 0, 0, 0ull, 0ull},
- {"FLS" , 2, 2, 1322, "RO", 0, 0, 0ull, 0ull},
- {"PS_EN" , 4, 1, 1322, "R/W", 0, 0, 0ull, 0ull},
- {"AS_EN" , 5, 1, 1322, "R/W", 0, 0, 0ull, 0ull},
- {"IAA_DB" , 6, 1, 1322, "R/W", 0, 0, 0ull, 0ull},
- {"LHCR" , 7, 1, 1322, "R/W", 0, 0, 0ull, 0ull},
- {"ASPMC" , 8, 2, 1322, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1322, "RO", 0, 0, 0ull, 0ull},
- {"ASPM_EN" , 11, 1, 1322, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 1322, "RO", 0, 0, 0ull, 0ull},
- {"ITC" , 16, 8, 1322, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_24_31" , 24, 8, 1322, "RO", 0, 0, 0ull, 0ull},
- {"USBINT_EN" , 0, 1, 1323, "R/W", 0, 1, 0ull, 0},
- {"USBERRINT_EN" , 1, 1, 1323, "R/W", 0, 1, 0ull, 0},
- {"PCI_EN" , 2, 1, 1323, "R/W", 0, 1, 0ull, 0},
- {"FLRO_EN" , 3, 1, 1323, "R/W", 0, 1, 0ull, 0},
- {"HSERR_EN" , 4, 1, 1323, "R/W", 0, 1, 0ull, 0},
- {"IOAA_EN" , 5, 1, 1323, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 1323, "RO", 0, 0, 0ull, 0ull},
- {"USBINT" , 0, 1, 1324, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBERRINT" , 1, 1, 1324, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCD" , 2, 1, 1324, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLRO" , 3, 1, 1324, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSYSERR" , 4, 1, 1324, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOAA" , 5, 1, 1324, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 1324, "RO", 0, 0, 0ull, 0ull},
- {"HCHTD" , 12, 1, 1324, "RO", 0, 0, 1ull, 0ull},
- {"RECLM" , 13, 1, 1324, "RO", 0, 0, 0ull, 0ull},
- {"PSS" , 14, 1, 1324, "RO", 0, 0, 0ull, 0ull},
- {"ASS" , 15, 1, 1324, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1324, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1325, "R/W", 0, 0, 0ull, 0ull},
- {"BCED" , 4, 28, 1325, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1326, "R/W", 0, 0, 0ull, 0ull},
- {"BHED" , 4, 28, 1326, "R/W", 0, 1, 0ull, 0},
- {"HCR" , 0, 1, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"CLF" , 1, 1, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"BLF" , 2, 1, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"OCR" , 3, 1, 1327, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1327, "RO", 0, 0, 0ull, 0ull},
- {"SOC" , 16, 2, 1327, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 1327, "RO", 0, 0, 0ull, 0ull},
- {"CBSR" , 0, 2, 1328, "R/W", 0, 1, 0ull, 0},
- {"PLE" , 2, 1, 1328, "R/W", 0, 0, 0ull, 0ull},
- {"IE" , 3, 1, 1328, "R/W", 0, 0, 0ull, 0ull},
- {"CLE" , 4, 1, 1328, "R/W", 0, 0, 0ull, 0ull},
- {"BLE" , 5, 1, 1328, "R/W", 0, 0, 0ull, 0ull},
- {"HCFS" , 6, 2, 1328, "R/W", 0, 0, 0ull, 0ull},
- {"IR" , 8, 1, 1328, "R/W", 0, 0, 0ull, 0ull},
- {"RWC" , 9, 1, 1328, "R/W", 0, 0, 0ull, 0ull},
- {"RWE" , 10, 1, 1328, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 1328, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1329, "R/W", 0, 0, 0ull, 0ull},
- {"CCED" , 4, 28, 1329, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1330, "R/W", 0, 0, 0ull, 0ull},
- {"CHED" , 4, 28, 1330, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1331, "RO", 0, 0, 0ull, 0ull},
- {"DH" , 4, 28, 1331, "RO", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1332, "R/W", 0, 1, 11999ull, 0},
- {"RESERVED_14_15" , 14, 2, 1332, "R/W", 0, 0, 0ull, 0ull},
- {"FSMPS" , 16, 15, 1332, "R/W", 0, 1, 0ull, 0},
- {"FIT" , 31, 1, 1332, "R/W", 0, 0, 0ull, 0ull},
- {"FN" , 0, 16, 1333, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 1333, "RO", 0, 0, 0ull, 0ull},
- {"FR" , 0, 14, 1334, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_30" , 14, 17, 1334, "RO", 0, 0, 0ull, 0ull},
- {"FRT" , 31, 1, 1334, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1335, "R/W", 0, 0, 0ull, 0ull},
- {"HCCA" , 8, 24, 1335, "R/W", 0, 1, 0ull, 0},
- {"SO" , 0, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1336, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1336, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1337, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1337, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1337, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1337, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1337, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1337, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1337, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1337, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1337, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1337, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1338, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1338, "R/W1C", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1338, "R/W1C", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1338, "R/W1C", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1338, "R/W1C", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1338, "R/W1C", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1338, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1338, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1338, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1338, "RO", 0, 0, 0ull, 0ull},
- {"LST" , 0, 12, 1339, "R/W", 0, 1, 1576ull, 0},
- {"RESERVED_12_31" , 12, 20, 1339, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1340, "RO", 0, 0, 0ull, 0ull},
- {"PCED" , 4, 28, 1340, "RO", 0, 1, 0ull, 0},
- {"PS" , 0, 14, 1341, "R/W", 0, 0, 0ull, 15975ull},
- {"RESERVED_14_31" , 14, 18, 1341, "R/W", 0, 0, 0ull, 0ull},
- {"REV" , 0, 8, 1342, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_31" , 8, 24, 1342, "RO", 0, 0, 0ull, 0ull},
- {"NDP" , 0, 8, 1343, "RO", 0, 0, 2ull, 2ull},
- {"NPS" , 8, 1, 1343, "R/W", 0, 0, 0ull, 0ull},
- {"PSM" , 9, 1, 1343, "R/W", 0, 0, 1ull, 1ull},
- {"DT" , 10, 1, 1343, "RO", 0, 0, 0ull, 0ull},
- {"OCPM" , 11, 1, 1343, "R/W", 1, 1, 0, 0},
- {"NOCP" , 12, 1, 1343, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_23" , 13, 11, 1343, "RO", 0, 0, 0ull, 0ull},
- {"POTPGT" , 24, 8, 1343, "R/W", 0, 0, 1ull, 1ull},
- {"DR" , 0, 16, 1344, "R/W", 0, 0, 0ull, 0ull},
- {"PPCM" , 16, 16, 1344, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"PES" , 1, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"PSS" , 2, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"POCI" , 3, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"PRS" , 4, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1345, "R/W", 0, 0, 0ull, 0ull},
- {"PPS" , 8, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"LSDA" , 9, 1, 1345, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_15" , 10, 6, 1345, "R/W", 0, 0, 0ull, 0ull},
- {"CSC" , 16, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"PESC" , 17, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"PSSC" , 18, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"OCIC" , 19, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"PRSC" , 20, 1, 1345, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_31" , 21, 11, 1345, "R/W", 0, 0, 0ull, 0ull},
- {"LPS" , 0, 1, 1346, "R/W", 0, 0, 0ull, 0ull},
- {"OCI" , 1, 1, 1346, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_14" , 2, 13, 1346, "RO", 0, 0, 0ull, 0ull},
- {"DRWE" , 15, 1, 1346, "R/W", 0, 1, 0ull, 0},
- {"LPSC" , 16, 1, 1346, "R/W", 0, 1, 0ull, 0},
- {"CCIC" , 17, 1, 1346, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_18_30" , 18, 13, 1346, "RO", 0, 0, 0ull, 0ull},
- {"CRWE" , 31, 1, 1346, "WO", 1, 1, 0, 0},
- {"RESERVED_0_30" , 0, 31, 1347, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1347, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1348, "RO", 0, 0, 0ull, 0ull},
- {"PPAF_BIS" , 0, 1, 1349, "RO", 0, 0, 0ull, 0ull},
- {"WRBM_BIS" , 1, 1, 1349, "RO", 0, 0, 0ull, 0ull},
- {"ORBM_BIS" , 2, 1, 1349, "RO", 0, 0, 0ull, 0ull},
- {"ERBM_BIS" , 3, 1, 1349, "RO", 0, 0, 0ull, 0ull},
- {"DESC_BIS" , 4, 1, 1349, "RO", 0, 0, 0ull, 0ull},
- {"DATA_BIS" , 5, 1, 1349, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1349, "RO", 1, 1, 0, 0},
- {"HRST" , 0, 1, 1350, "R/W", 0, 0, 0ull, 1ull},
- {"P_PRST" , 1, 1, 1350, "R/W", 0, 0, 0ull, 1ull},
- {"P_POR" , 2, 1, 1350, "R/W", 0, 0, 1ull, 0ull},
- {"P_COM_ON" , 3, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 1350, "R/W", 0, 1, 0ull, 0},
- {"P_REFCLK_DIV" , 5, 2, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"P_REFCLK_SEL" , 7, 2, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"H_DIV" , 9, 4, 1350, "R/W", 0, 0, 6ull, 6ull},
- {"O_CLKDIV_EN" , 13, 1, 1350, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_EN" , 14, 1, 1350, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_RST" , 15, 1, 1350, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_BYP" , 16, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"O_CLKDIV_RST" , 17, 1, 1350, "R/W", 0, 0, 0ull, 1ull},
- {"APP_START_CLK" , 18, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_SUSP_LGCY" , 19, 1, 1350, "R/W", 0, 0, 1ull, 1ull},
- {"OHCI_SM" , 20, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_CLKCKTRST" , 21, 1, 1350, "R/W", 0, 0, 1ull, 1ull},
- {"EHCI_SM" , 22, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 23, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 24, 1, 1350, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1350, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1351, "R/W", 0, 1, 0ull, 0},
- {"EHCI_64B_ADDR_EN" , 8, 1, 1351, "R/W", 0, 0, 1ull, 1ull},
- {"INV_REG_A2" , 9, 1, 1351, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1351, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1351, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1351, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1351, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1351, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1351, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1351, "R/W", 0, 0, 0ull, 0ull},
- {"DESC_RBM" , 19, 1, 1351, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1351, "RAZ", 1, 1, 0, 0},
- {"FLA" , 0, 6, 1352, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 1352, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 1353, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 5, 27, 1353, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1353, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1354, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1354, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1355, "R/W", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1355, "R/W", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1355, "R/W", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1355, "R/W", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1355, "R/W", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1355, "R/W", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1355, "R/W", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1355, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1355, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1356, "R/W1C", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1356, "R/W1C", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1356, "R/W1C", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1356, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1356, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1356, "R/W1C", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1356, "R/W1C", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1356, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1356, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1357, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_8" , 8, 1, 1357, "RAZ", 1, 1, 0, 0},
- {"INV_REG_A2" , 9, 1, 1357, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1357, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1357, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1357, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1357, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1357, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1357, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1357, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1357, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1358, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 8, 24, 1358, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1358, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 1359, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_EN" , 1, 1, 1359, "R/W", 0, 0, 0ull, 0ull},
- {"UPHY_BIST" , 2, 1, 1359, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_EN" , 3, 1, 1359, "R/W", 0, 0, 0ull, 0ull},
- {"SIDDQ" , 4, 1, 1359, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 5, 1, 1359, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 6, 1, 1359, "R/W", 0, 0, 0ull, 0ull},
- {"HSBIST" , 7, 1, 1359, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ERR" , 8, 1, 1359, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 9, 1, 1359, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1359, "RAZ", 1, 1, 0, 0},
- {"TDATA_IN" , 0, 8, 1360, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 8, 4, 1360, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 12, 1, 1360, "R/W", 0, 0, 1ull, 0ull},
- {"TCLK" , 13, 1, 1360, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_EN" , 14, 1, 1360, "R/W", 0, 0, 0ull, 0ull},
- {"COMPDISTUNE" , 15, 3, 1360, "R/W", 0, 0, 4ull, 4ull},
- {"SQRXTUNE" , 18, 3, 1360, "R/W", 0, 0, 4ull, 4ull},
- {"TXFSLSTUNE" , 21, 4, 1360, "R/W", 0, 0, 3ull, 3ull},
- {"TXPREEMPHASISTUNE" , 25, 1, 1360, "R/W", 0, 0, 0ull, 1ull},
- {"TXRISETUNE" , 26, 1, 1360, "R/W", 0, 0, 0ull, 1ull},
- {"TXVREFTUNE" , 27, 4, 1360, "R/W", 0, 0, 5ull, 15ull},
- {"TXHSVXTUNE" , 31, 2, 1360, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 33, 1, 1360, "R/W", 0, 0, 0ull, 0ull},
- {"VBUSVLDEXT" , 34, 1, 1360, "R/W", 0, 0, 0ull, 0ull},
- {"DPPULLDOWN" , 35, 1, 1360, "R/W", 0, 0, 1ull, 1ull},
- {"DMPULLDOWN" , 36, 1, 1360, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFEN" , 37, 1, 1360, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFENH" , 38, 1, 1360, "R/W", 0, 0, 1ull, 1ull},
- {"TDATA_OUT" , 39, 4, 1360, "RO", 1, 1, 0, 0},
- {"RESERVED_43_63" , 43, 21, 1360, "RAZ", 1, 1, 0, 0},
- {"ZIP_CTL" , 0, 4, 1361, "RO", 1, 0, 0, 0ull},
- {"ZIP_CORE" , 4, 53, 1361, "RO", 1, 0, 0, 0ull},
- {"RESERVED_57_63" , 57, 7, 1361, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1362, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 1362, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 1362, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 1362, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 1362, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 1363, "RAZ", 0, 0, 0ull, 0ull},
- {"FORCECLK" , 1, 1, 1363, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1363, "RAZ", 1, 1, 0, 0},
- {"DISABLED" , 0, 1, 1364, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 1364, "RAZ", 1, 1, 0, 0},
- {"CTXSIZE" , 8, 12, 1364, "RO", 0, 0, 1536ull, 1536ull},
- {"ONFSIZE" , 20, 12, 1364, "RO", 0, 0, 512ull, 512ull},
- {"DEPTH" , 32, 16, 1364, "RO", 0, 0, 31744ull, 31744ull},
- {"SYNCFLUSH_CAPABLE" , 48, 1, 1364, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_49_55" , 49, 7, 1364, "RAZ", 1, 1, 0, 0},
- {"NEXEC" , 56, 8, 1364, "RO", 0, 0, 2ull, 2ull},
- {"BSTATUS" , 0, 53, 1365, "RO", 1, 0, 0, 0ull},
- {"RESERVED_53_63" , 53, 11, 1365, "RAZ", 1, 1, 0, 0},
- {"BSTATUS" , 0, 7, 1366, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_63" , 7, 57, 1366, "RAZ", 1, 1, 0, 0},
- {"LMOD" , 0, 1, 1367, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 1, 1, 1367, "RO", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 1367, "RAZ", 1, 0, 0, 0ull},
- {"WKQF" , 4, 2, 1367, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_7" , 6, 2, 1367, "RAZ", 1, 0, 0, 0ull},
- {"LDF" , 8, 3, 1367, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_11_11" , 11, 1, 1367, "RAZ", 1, 0, 0, 0ull},
- {"STCF" , 12, 3, 1367, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_15_15" , 15, 1, 1367, "RAZ", 1, 0, 0, 0ull},
- {"GSTF" , 16, 3, 1367, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_19_19" , 19, 1, 1367, "RAZ", 1, 0, 0, 0ull},
- {"IPRF" , 20, 2, 1367, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_22_23" , 22, 2, 1367, "RAZ", 1, 0, 0, 0ull},
- {"ILDF" , 24, 3, 1367, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_27_63" , 27, 37, 1367, "RAZ", 1, 0, 0, 0ull},
- {"IID" , 0, 32, 1368, "RO", 0, 1, 0ull, 0},
- {"QID" , 32, 1, 1368, "RO", 0, 1, 0ull, 0},
- {"RESERVED_33_62" , 33, 30, 1368, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 63, 1, 1368, "RO", 0, 1, 0ull, 0},
- {"NIE" , 0, 32, 1369, "RO", 0, 1, 0ull, 0},
- {"IST" , 32, 5, 1369, "RO", 0, 1, 0ull, 0},
- {"RESERVED_37_62" , 37, 26, 1369, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 63, 1, 1369, "RO", 0, 1, 0ull, 0},
- {"NII" , 0, 32, 1370, "RO", 0, 1, 0ull, 0},
- {"CDBC" , 32, 20, 1370, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_62" , 52, 11, 1370, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 63, 1, 1370, "RO", 0, 1, 0ull, 0},
- {"ASSERTS" , 0, 30, 1371, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_30_63" , 30, 34, 1371, "RAZ", 1, 1, 0, 0},
- {"IBEN" , 0, 1, 1372, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_31" , 1, 31, 1372, "RAZ", 1, 1, 0, 0},
- {"IBGE" , 32, 2, 1372, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_63" , 34, 30, 1372, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1373, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1373, "RAZ", 1, 1, 0, 0},
- {"FIFE" , 0, 1, 1374, "R/W", 0, 0, 0ull, 0ull},
- {"IBSBE" , 1, 1, 1374, "R/W", 0, 0, 0ull, 0ull},
- {"IBDBE" , 2, 1, 1374, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 1374, "RAZ", 1, 0, 0, 0ull},
- {"DOORBELL0" , 8, 1, 1374, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL1" , 9, 1, 1374, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1374, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1375, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1375, "RAZ", 1, 1, 0, 0},
- {"FIFE" , 0, 1, 1376, "RO", 0, 0, 0ull, 0ull},
- {"IBSBE" , 1, 1, 1376, "R/W1C", 0, 0, 0ull, 0ull},
- {"IBDBE" , 2, 1, 1376, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 1376, "RAZ", 1, 0, 0, 0ull},
- {"DOORBELL0" , 8, 1, 1376, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL1" , 9, 1, 1376, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1376, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1377, "R/W", 0, 0, 0ull, 0ull},
- {"SIZE" , 33, 13, 1377, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 46, 3, 1377, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 49, 9, 1377, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_58_63" , 58, 6, 1377, "RAZ", 1, 1, 0, 0},
- {"INUM" , 0, 32, 1378, "RO", 0, 0, 0ull, 0ull},
- {"WNUM" , 32, 3, 1378, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 1378, "RAZ", 1, 1, 0, 0},
- {"ZCE" , 0, 2, 1379, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_2_63" , 2, 62, 1379, "RAZ", 1, 1, 0, 0},
- {"ENA" , 0, 2, 1380, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_2_63" , 2, 62, 1380, "RAZ", 1, 1, 0, 0},
- {"PRI" , 0, 2, 1381, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1381, "RAZ", 1, 1, 0, 0},
- {"MAX_INFL" , 0, 5, 1382, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 1382, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_TYPE cvmx_csr_db_cnf71xx[] = {
- /* name , ---------------type, bits, off, #field, fld of */
- {"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 0, 2, 0},
- {"cvmx_ciu_block_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1, 29, 2},
- {"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 2, 2, 31},
- {"cvmx_ciu_en2_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 3, 6, 33},
- {"cvmx_ciu_en2_io#_int_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 5, 6, 39},
- {"cvmx_ciu_en2_io#_int_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 7, 6, 45},
- {"cvmx_ciu_en2_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 9, 6, 51},
- {"cvmx_ciu_en2_pp#_ip2_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 13, 6, 57},
- {"cvmx_ciu_en2_pp#_ip2_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 17, 6, 63},
- {"cvmx_ciu_en2_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 21, 6, 69},
- {"cvmx_ciu_en2_pp#_ip3_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 25, 6, 75},
- {"cvmx_ciu_en2_pp#_ip3_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 29, 6, 81},
- {"cvmx_ciu_en2_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 33, 6, 87},
- {"cvmx_ciu_en2_pp#_ip4_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 37, 6, 93},
- {"cvmx_ciu_en2_pp#_ip4_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 41, 6, 99},
- {"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 45, 2, 105},
- {"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 46, 2, 107},
- {"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 47, 23, 109},
- {"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 57, 23, 132},
- {"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 67, 23, 155},
- {"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 77, 30, 178},
- {"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 87, 30, 208},
- {"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 97, 30, 238},
- {"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 107, 23, 268},
- {"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 111, 23, 291},
- {"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 115, 23, 314},
- {"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 119, 30, 337},
- {"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 123, 30, 367},
- {"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 127, 30, 397},
- {"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 131, 23, 427},
- {"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 140, 23, 450},
- {"cvmx_ciu_int33_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 144, 23, 473},
- {"cvmx_ciu_int_dbg_sel" , CVMX_CSR_DB_TYPE_NCB, 64, 145, 6, 496},
- {"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 146, 28, 502},
- {"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 147, 2, 530},
- {"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 151, 2, 532},
- {"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 155, 2, 534},
- {"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 156, 2, 536},
- {"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 157, 2, 538},
- {"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 158, 1, 540},
- {"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 162, 3, 541},
- {"cvmx_ciu_qlm0" , CVMX_CSR_DB_TYPE_NCB, 64, 163, 13, 544},
- {"cvmx_ciu_qlm1" , CVMX_CSR_DB_TYPE_NCB, 64, 164, 13, 557},
- {"cvmx_ciu_qlm2" , CVMX_CSR_DB_TYPE_NCB, 64, 165, 8, 570},
- {"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 166, 6, 578},
- {"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 167, 8, 584},
- {"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 168, 2, 592},
- {"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 169, 2, 594},
- {"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 170, 2, 596},
- {"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 171, 2, 598},
- {"cvmx_ciu_sum1_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 172, 30, 600},
- {"cvmx_ciu_sum1_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 174, 30, 630},
- {"cvmx_ciu_sum1_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 178, 30, 660},
- {"cvmx_ciu_sum1_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 182, 30, 690},
- {"cvmx_ciu_sum2_io#_int" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 6, 720},
- {"cvmx_ciu_sum2_pp#_ip2" , CVMX_CSR_DB_TYPE_NCB, 64, 188, 6, 726},
- {"cvmx_ciu_sum2_pp#_ip3" , CVMX_CSR_DB_TYPE_NCB, 64, 192, 6, 732},
- {"cvmx_ciu_sum2_pp#_ip4" , CVMX_CSR_DB_TYPE_NCB, 64, 196, 6, 738},
- {"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 200, 3, 744},
- {"cvmx_ciu_tim_multi_cast" , CVMX_CSR_DB_TYPE_NCB, 64, 210, 2, 747},
- {"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 211, 7, 749},
- {"cvmx_dpi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 215, 2, 756},
- {"cvmx_dpi_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 216, 2, 758},
- {"cvmx_dpi_dma#_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 217, 3, 760},
- {"cvmx_dpi_dma#_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 2, 763},
- {"cvmx_dpi_dma#_err_rsp_status", CVMX_CSR_DB_TYPE_NCB, 64, 233, 2, 765},
- {"cvmx_dpi_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 241, 7, 767},
- {"cvmx_dpi_dma#_iflight" , CVMX_CSR_DB_TYPE_NCB, 64, 249, 2, 774},
- {"cvmx_dpi_dma#_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 257, 2, 776},
- {"cvmx_dpi_dma#_reqbnk0" , CVMX_CSR_DB_TYPE_NCB, 64, 265, 1, 778},
- {"cvmx_dpi_dma#_reqbnk1" , CVMX_CSR_DB_TYPE_NCB, 64, 273, 1, 779},
- {"cvmx_dpi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 281, 20, 780},
- {"cvmx_dpi_dma_eng#_en" , CVMX_CSR_DB_TYPE_NCB, 64, 282, 2, 800},
- {"cvmx_dpi_dma_pp#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 288, 2, 802},
- {"cvmx_dpi_eng#_buf" , CVMX_CSR_DB_TYPE_NCB, 64, 292, 5, 804},
- {"cvmx_dpi_info_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 298, 5, 809},
- {"cvmx_dpi_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 299, 17, 814},
- {"cvmx_dpi_int_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 300, 17, 831},
- {"cvmx_dpi_ncb#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 301, 2, 848},
- {"cvmx_dpi_pint_info" , CVMX_CSR_DB_TYPE_NCB, 64, 302, 4, 850},
- {"cvmx_dpi_pkt_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 303, 2, 854},
- {"cvmx_dpi_req_err_rsp" , CVMX_CSR_DB_TYPE_NCB, 64, 304, 2, 856},
- {"cvmx_dpi_req_err_rsp_en" , CVMX_CSR_DB_TYPE_NCB, 64, 305, 2, 858},
- {"cvmx_dpi_req_err_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 306, 2, 860},
- {"cvmx_dpi_req_err_rst_en" , CVMX_CSR_DB_TYPE_NCB, 64, 307, 2, 862},
- {"cvmx_dpi_req_err_skip_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 308, 4, 864},
- {"cvmx_dpi_req_gbl_en" , CVMX_CSR_DB_TYPE_NCB, 64, 309, 2, 868},
- {"cvmx_dpi_sli_prt#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 310, 13, 870},
- {"cvmx_dpi_sli_prt#_err" , CVMX_CSR_DB_TYPE_NCB, 64, 312, 2, 883},
- {"cvmx_dpi_sli_prt#_err_info" , CVMX_CSR_DB_TYPE_NCB, 64, 314, 6, 885},
- {"cvmx_endor_adma_auto_clk_gate", CVMX_CSR_DB_TYPE_NCB, 32, 316, 2, 891},
- {"cvmx_endor_adma_axi_rspcode" , CVMX_CSR_DB_TYPE_NCB, 32, 317, 9, 893},
- {"cvmx_endor_adma_axi_signal" , CVMX_CSR_DB_TYPE_NCB, 32, 318, 6, 902},
- {"cvmx_endor_adma_axierr_intr" , CVMX_CSR_DB_TYPE_NCB, 32, 319, 2, 908},
- {"cvmx_endor_adma_dma#_addr_hi", CVMX_CSR_DB_TYPE_NCB, 32, 320, 2, 910},
- {"cvmx_endor_adma_dma#_addr_lo", CVMX_CSR_DB_TYPE_NCB, 32, 328, 1, 912},
- {"cvmx_endor_adma_dma#_cfg" , CVMX_CSR_DB_TYPE_NCB, 32, 336, 12, 913},
- {"cvmx_endor_adma_dma#_size" , CVMX_CSR_DB_TYPE_NCB, 32, 344, 2, 925},
- {"cvmx_endor_adma_dma_priority", CVMX_CSR_DB_TYPE_NCB, 32, 352, 4, 927},
- {"cvmx_endor_adma_dma_reset" , CVMX_CSR_DB_TYPE_NCB, 32, 353, 2, 931},
- {"cvmx_endor_adma_dmadone_intr", CVMX_CSR_DB_TYPE_NCB, 32, 354, 2, 933},
- {"cvmx_endor_adma_intr_dis" , CVMX_CSR_DB_TYPE_NCB, 32, 355, 3, 935},
- {"cvmx_endor_adma_intr_enb" , CVMX_CSR_DB_TYPE_NCB, 32, 356, 3, 938},
- {"cvmx_endor_adma_module_status", CVMX_CSR_DB_TYPE_NCB, 32, 357, 4, 941},
- {"cvmx_endor_intc_cntl_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 358, 2, 945},
- {"cvmx_endor_intc_cntl_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 360, 2, 947},
- {"cvmx_endor_intc_index_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 362, 2, 949},
- {"cvmx_endor_intc_index_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 364, 2, 951},
- {"cvmx_endor_intc_misc_idx_hi#", CVMX_CSR_DB_TYPE_NCB, 32, 366, 2, 953},
- {"cvmx_endor_intc_misc_idx_lo#", CVMX_CSR_DB_TYPE_NCB, 32, 368, 2, 955},
- {"cvmx_endor_intc_misc_mask_hi#", CVMX_CSR_DB_TYPE_NCB, 32, 370, 25, 957},
- {"cvmx_endor_intc_misc_mask_lo#", CVMX_CSR_DB_TYPE_NCB, 32, 372, 25, 982},
- {"cvmx_endor_intc_misc_rint" , CVMX_CSR_DB_TYPE_NCB, 32, 374, 25, 1007},
- {"cvmx_endor_intc_misc_status_hi#", CVMX_CSR_DB_TYPE_NCB, 32, 375, 25, 1032},
- {"cvmx_endor_intc_misc_status_lo#", CVMX_CSR_DB_TYPE_NCB, 32, 377, 25, 1057},
- {"cvmx_endor_intc_rd_idx_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 379, 2, 1082},
- {"cvmx_endor_intc_rd_idx_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 381, 2, 1084},
- {"cvmx_endor_intc_rd_mask_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 383, 25, 1086},
- {"cvmx_endor_intc_rd_mask_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 385, 25, 1111},
- {"cvmx_endor_intc_rd_rint" , CVMX_CSR_DB_TYPE_NCB, 32, 387, 25, 1136},
- {"cvmx_endor_intc_rd_status_hi#", CVMX_CSR_DB_TYPE_NCB, 32, 388, 25, 1161},
- {"cvmx_endor_intc_rd_status_lo#", CVMX_CSR_DB_TYPE_NCB, 32, 390, 25, 1186},
- {"cvmx_endor_intc_rdq_idx_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 392, 2, 1211},
- {"cvmx_endor_intc_rdq_idx_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 394, 2, 1213},
- {"cvmx_endor_intc_rdq_mask_hi#", CVMX_CSR_DB_TYPE_NCB, 32, 396, 25, 1215},
- {"cvmx_endor_intc_rdq_mask_lo#", CVMX_CSR_DB_TYPE_NCB, 32, 398, 25, 1240},
- {"cvmx_endor_intc_rdq_rint" , CVMX_CSR_DB_TYPE_NCB, 32, 400, 25, 1265},
- {"cvmx_endor_intc_rdq_status_hi#", CVMX_CSR_DB_TYPE_NCB, 32, 401, 25, 1290},
- {"cvmx_endor_intc_rdq_status_lo#", CVMX_CSR_DB_TYPE_NCB, 32, 403, 25, 1315},
- {"cvmx_endor_intc_stat_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 405, 7, 1340},
- {"cvmx_endor_intc_stat_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 407, 7, 1347},
- {"cvmx_endor_intc_sw_idx_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 409, 2, 1354},
- {"cvmx_endor_intc_sw_idx_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 411, 2, 1356},
- {"cvmx_endor_intc_sw_mask_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 413, 1, 1358},
- {"cvmx_endor_intc_sw_mask_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 415, 1, 1359},
- {"cvmx_endor_intc_sw_rint" , CVMX_CSR_DB_TYPE_NCB, 32, 417, 1, 1360},
- {"cvmx_endor_intc_sw_status_hi#", CVMX_CSR_DB_TYPE_NCB, 32, 418, 1, 1361},
- {"cvmx_endor_intc_sw_status_lo#", CVMX_CSR_DB_TYPE_NCB, 32, 420, 1, 1362},
- {"cvmx_endor_intc_swclr" , CVMX_CSR_DB_TYPE_NCB, 32, 422, 1, 1363},
- {"cvmx_endor_intc_swset" , CVMX_CSR_DB_TYPE_NCB, 32, 423, 1, 1364},
- {"cvmx_endor_intc_wr_idx_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 424, 2, 1365},
- {"cvmx_endor_intc_wr_idx_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 426, 2, 1367},
- {"cvmx_endor_intc_wr_mask_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 428, 30, 1369},
- {"cvmx_endor_intc_wr_mask_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 430, 30, 1399},
- {"cvmx_endor_intc_wr_rint" , CVMX_CSR_DB_TYPE_NCB, 32, 432, 30, 1429},
- {"cvmx_endor_intc_wr_status_hi#", CVMX_CSR_DB_TYPE_NCB, 32, 433, 30, 1459},
- {"cvmx_endor_intc_wr_status_lo#", CVMX_CSR_DB_TYPE_NCB, 32, 435, 30, 1489},
- {"cvmx_endor_intc_wrq_idx_hi#" , CVMX_CSR_DB_TYPE_NCB, 32, 437, 2, 1519},
- {"cvmx_endor_intc_wrq_idx_lo#" , CVMX_CSR_DB_TYPE_NCB, 32, 439, 2, 1521},
- {"cvmx_endor_intc_wrq_mask_hi#", CVMX_CSR_DB_TYPE_NCB, 32, 441, 24, 1523},
- {"cvmx_endor_intc_wrq_mask_lo#", CVMX_CSR_DB_TYPE_NCB, 32, 443, 24, 1547},
- {"cvmx_endor_intc_wrq_rint" , CVMX_CSR_DB_TYPE_NCB, 32, 445, 24, 1571},
- {"cvmx_endor_intc_wrq_status_hi#", CVMX_CSR_DB_TYPE_NCB, 32, 446, 24, 1595},
- {"cvmx_endor_intc_wrq_status_lo#", CVMX_CSR_DB_TYPE_NCB, 32, 448, 24, 1619},
- {"cvmx_endor_ofs_hmm_cbuf_end_addr0", CVMX_CSR_DB_TYPE_NCB, 32, 450, 2, 1643},
- {"cvmx_endor_ofs_hmm_cbuf_end_addr1", CVMX_CSR_DB_TYPE_NCB, 32, 451, 2, 1645},
- {"cvmx_endor_ofs_hmm_cbuf_end_addr2", CVMX_CSR_DB_TYPE_NCB, 32, 452, 2, 1647},
- {"cvmx_endor_ofs_hmm_cbuf_end_addr3", CVMX_CSR_DB_TYPE_NCB, 32, 453, 2, 1649},
- {"cvmx_endor_ofs_hmm_cbuf_start_addr0", CVMX_CSR_DB_TYPE_NCB, 32, 454, 2, 1651},
- {"cvmx_endor_ofs_hmm_cbuf_start_addr1", CVMX_CSR_DB_TYPE_NCB, 32, 455, 2, 1653},
- {"cvmx_endor_ofs_hmm_cbuf_start_addr2", CVMX_CSR_DB_TYPE_NCB, 32, 456, 2, 1655},
- {"cvmx_endor_ofs_hmm_cbuf_start_addr3", CVMX_CSR_DB_TYPE_NCB, 32, 457, 2, 1657},
- {"cvmx_endor_ofs_hmm_intr_clear", CVMX_CSR_DB_TYPE_NCB, 32, 458, 3, 1659},
- {"cvmx_endor_ofs_hmm_intr_enb" , CVMX_CSR_DB_TYPE_NCB, 32, 459, 3, 1662},
- {"cvmx_endor_ofs_hmm_intr_rstatus", CVMX_CSR_DB_TYPE_NCB, 32, 460, 3, 1665},
- {"cvmx_endor_ofs_hmm_intr_status", CVMX_CSR_DB_TYPE_NCB, 32, 461, 3, 1668},
- {"cvmx_endor_ofs_hmm_intr_test", CVMX_CSR_DB_TYPE_NCB, 32, 462, 3, 1671},
- {"cvmx_endor_ofs_hmm_mode" , CVMX_CSR_DB_TYPE_NCB, 32, 463, 5, 1674},
- {"cvmx_endor_ofs_hmm_start_addr0", CVMX_CSR_DB_TYPE_NCB, 32, 464, 2, 1679},
- {"cvmx_endor_ofs_hmm_start_addr1", CVMX_CSR_DB_TYPE_NCB, 32, 465, 2, 1681},
- {"cvmx_endor_ofs_hmm_start_addr2", CVMX_CSR_DB_TYPE_NCB, 32, 466, 2, 1683},
- {"cvmx_endor_ofs_hmm_start_addr3", CVMX_CSR_DB_TYPE_NCB, 32, 467, 2, 1685},
- {"cvmx_endor_ofs_hmm_status" , CVMX_CSR_DB_TYPE_NCB, 32, 468, 1, 1687},
- {"cvmx_endor_ofs_hmm_xfer_cnt" , CVMX_CSR_DB_TYPE_NCB, 32, 469, 5, 1688},
- {"cvmx_endor_ofs_hmm_xfer_q_status", CVMX_CSR_DB_TYPE_NCB, 32, 470, 1, 1693},
- {"cvmx_endor_ofs_hmm_xfer_start", CVMX_CSR_DB_TYPE_NCB, 32, 471, 2, 1694},
- {"cvmx_endor_rfif_1pps_gen_cfg", CVMX_CSR_DB_TYPE_NCB, 32, 472, 2, 1696},
- {"cvmx_endor_rfif_1pps_sample_cnt_offset", CVMX_CSR_DB_TYPE_NCB, 32, 473, 2, 1698},
- {"cvmx_endor_rfif_1pps_verif_gen_en", CVMX_CSR_DB_TYPE_NCB, 32, 474, 2, 1700},
- {"cvmx_endor_rfif_1pps_verif_scnt", CVMX_CSR_DB_TYPE_NCB, 32, 475, 2, 1702},
- {"cvmx_endor_rfif_conf" , CVMX_CSR_DB_TYPE_NCB, 32, 476, 19, 1704},
- {"cvmx_endor_rfif_conf2" , CVMX_CSR_DB_TYPE_NCB, 32, 477, 4, 1723},
- {"cvmx_endor_rfif_dsp1_gpio" , CVMX_CSR_DB_TYPE_NCB, 32, 478, 2, 1727},
- {"cvmx_endor_rfif_dsp_rx_his" , CVMX_CSR_DB_TYPE_NCB, 32, 479, 1, 1729},
- {"cvmx_endor_rfif_dsp_rx_ism" , CVMX_CSR_DB_TYPE_NCB, 32, 480, 3, 1730},
- {"cvmx_endor_rfif_firs_enable" , CVMX_CSR_DB_TYPE_NCB, 32, 481, 5, 1733},
- {"cvmx_endor_rfif_frame_cnt" , CVMX_CSR_DB_TYPE_NCB, 32, 482, 2, 1738},
- {"cvmx_endor_rfif_frame_l" , CVMX_CSR_DB_TYPE_NCB, 32, 483, 2, 1740},
- {"cvmx_endor_rfif_gpio_#" , CVMX_CSR_DB_TYPE_NCB, 32, 484, 4, 1742},
- {"cvmx_endor_rfif_max_sample_adj", CVMX_CSR_DB_TYPE_NCB, 32, 488, 2, 1746},
- {"cvmx_endor_rfif_min_sample_adj", CVMX_CSR_DB_TYPE_NCB, 32, 489, 2, 1748},
- {"cvmx_endor_rfif_num_rx_win" , CVMX_CSR_DB_TYPE_NCB, 32, 490, 2, 1750},
- {"cvmx_endor_rfif_pwm_enable" , CVMX_CSR_DB_TYPE_NCB, 32, 491, 2, 1752},
- {"cvmx_endor_rfif_pwm_high_time", CVMX_CSR_DB_TYPE_NCB, 32, 492, 2, 1754},
- {"cvmx_endor_rfif_pwm_low_time", CVMX_CSR_DB_TYPE_NCB, 32, 493, 2, 1756},
- {"cvmx_endor_rfif_rd_timer64_lsb", CVMX_CSR_DB_TYPE_NCB, 32, 494, 1, 1758},
- {"cvmx_endor_rfif_rd_timer64_msb", CVMX_CSR_DB_TYPE_NCB, 32, 495, 1, 1759},
- {"cvmx_endor_rfif_real_time_timer", CVMX_CSR_DB_TYPE_NCB, 32, 496, 1, 1760},
- {"cvmx_endor_rfif_rf_clk_timer", CVMX_CSR_DB_TYPE_NCB, 32, 497, 1, 1761},
- {"cvmx_endor_rfif_rf_clk_timer_en", CVMX_CSR_DB_TYPE_NCB, 32, 498, 2, 1762},
- {"cvmx_endor_rfif_rx_correct_adj", CVMX_CSR_DB_TYPE_NCB, 32, 499, 2, 1764},
- {"cvmx_endor_rfif_rx_div_status", CVMX_CSR_DB_TYPE_NCB, 32, 500, 11, 1766},
- {"cvmx_endor_rfif_rx_fifo_cnt" , CVMX_CSR_DB_TYPE_NCB, 32, 501, 2, 1777},
- {"cvmx_endor_rfif_rx_if_cfg" , CVMX_CSR_DB_TYPE_NCB, 32, 502, 4, 1779},
- {"cvmx_endor_rfif_rx_lead_lag" , CVMX_CSR_DB_TYPE_NCB, 32, 503, 3, 1783},
- {"cvmx_endor_rfif_rx_load_cfg" , CVMX_CSR_DB_TYPE_NCB, 32, 504, 8, 1786},
- {"cvmx_endor_rfif_rx_offset" , CVMX_CSR_DB_TYPE_NCB, 32, 505, 2, 1794},
- {"cvmx_endor_rfif_rx_offset_adj_scnt", CVMX_CSR_DB_TYPE_NCB, 32, 506, 2, 1796},
- {"cvmx_endor_rfif_rx_status" , CVMX_CSR_DB_TYPE_NCB, 32, 507, 11, 1798},
- {"cvmx_endor_rfif_rx_sync_scnt", CVMX_CSR_DB_TYPE_NCB, 32, 508, 2, 1809},
- {"cvmx_endor_rfif_rx_sync_value", CVMX_CSR_DB_TYPE_NCB, 32, 509, 2, 1811},
- {"cvmx_endor_rfif_rx_th" , CVMX_CSR_DB_TYPE_NCB, 32, 510, 2, 1813},
- {"cvmx_endor_rfif_rx_transfer_size", CVMX_CSR_DB_TYPE_NCB, 32, 511, 2, 1815},
- {"cvmx_endor_rfif_rx_w_e#" , CVMX_CSR_DB_TYPE_NCB, 32, 512, 2, 1817},
- {"cvmx_endor_rfif_rx_w_s#" , CVMX_CSR_DB_TYPE_NCB, 32, 516, 2, 1819},
- {"cvmx_endor_rfif_sample_adj_cfg", CVMX_CSR_DB_TYPE_NCB, 32, 520, 2, 1821},
- {"cvmx_endor_rfif_sample_adj_error", CVMX_CSR_DB_TYPE_NCB, 32, 521, 1, 1823},
- {"cvmx_endor_rfif_sample_cnt" , CVMX_CSR_DB_TYPE_NCB, 32, 522, 2, 1824},
- {"cvmx_endor_rfif_skip_frm_cnt_bits", CVMX_CSR_DB_TYPE_NCB, 32, 523, 2, 1826},
- {"cvmx_endor_rfif_spi_#_ll" , CVMX_CSR_DB_TYPE_NCB, 32, 524, 2, 1828},
- {"cvmx_endor_rfif_spi_cmd_attr#", CVMX_CSR_DB_TYPE_NCB, 32, 528, 5, 1830},
- {"cvmx_endor_rfif_spi_cmds#" , CVMX_CSR_DB_TYPE_NCB, 32, 592, 2, 1835},
- {"cvmx_endor_rfif_spi_conf0" , CVMX_CSR_DB_TYPE_NCB, 32, 656, 5, 1837},
- {"cvmx_endor_rfif_spi_conf1" , CVMX_CSR_DB_TYPE_NCB, 32, 657, 5, 1842},
- {"cvmx_endor_rfif_spi_ctrl" , CVMX_CSR_DB_TYPE_NCB, 32, 658, 1, 1847},
- {"cvmx_endor_rfif_spi_din#" , CVMX_CSR_DB_TYPE_NCB, 32, 659, 2, 1848},
- {"cvmx_endor_rfif_spi_rx_data" , CVMX_CSR_DB_TYPE_NCB, 32, 723, 1, 1850},
- {"cvmx_endor_rfif_spi_status" , CVMX_CSR_DB_TYPE_NCB, 32, 724, 4, 1851},
- {"cvmx_endor_rfif_spi_tx_data" , CVMX_CSR_DB_TYPE_NCB, 32, 725, 5, 1855},
- {"cvmx_endor_rfif_timer64_cfg" , CVMX_CSR_DB_TYPE_NCB, 32, 726, 2, 1860},
- {"cvmx_endor_rfif_timer64_en" , CVMX_CSR_DB_TYPE_NCB, 32, 727, 2, 1862},
- {"cvmx_endor_rfif_tti_scnt_int#", CVMX_CSR_DB_TYPE_NCB, 32, 728, 2, 1864},
- {"cvmx_endor_rfif_tti_scnt_int_clr", CVMX_CSR_DB_TYPE_NCB, 32, 736, 2, 1866},
- {"cvmx_endor_rfif_tti_scnt_int_en", CVMX_CSR_DB_TYPE_NCB, 32, 737, 2, 1868},
- {"cvmx_endor_rfif_tti_scnt_int_map", CVMX_CSR_DB_TYPE_NCB, 32, 738, 2, 1870},
- {"cvmx_endor_rfif_tti_scnt_int_stat", CVMX_CSR_DB_TYPE_NCB, 32, 739, 2, 1872},
- {"cvmx_endor_rfif_tx_div_status", CVMX_CSR_DB_TYPE_NCB, 32, 740, 11, 1874},
- {"cvmx_endor_rfif_tx_if_cfg" , CVMX_CSR_DB_TYPE_NCB, 32, 741, 4, 1885},
- {"cvmx_endor_rfif_tx_lead_lag" , CVMX_CSR_DB_TYPE_NCB, 32, 742, 3, 1889},
- {"cvmx_endor_rfif_tx_offset" , CVMX_CSR_DB_TYPE_NCB, 32, 743, 2, 1892},
- {"cvmx_endor_rfif_tx_offset_adj_scnt", CVMX_CSR_DB_TYPE_NCB, 32, 744, 2, 1894},
- {"cvmx_endor_rfif_tx_status" , CVMX_CSR_DB_TYPE_NCB, 32, 745, 11, 1896},
- {"cvmx_endor_rfif_tx_th" , CVMX_CSR_DB_TYPE_NCB, 32, 746, 2, 1907},
- {"cvmx_endor_rfif_win_en" , CVMX_CSR_DB_TYPE_NCB, 32, 747, 2, 1909},
- {"cvmx_endor_rfif_win_upd_scnt", CVMX_CSR_DB_TYPE_NCB, 32, 748, 2, 1911},
- {"cvmx_endor_rfif_wr_timer64_lsb", CVMX_CSR_DB_TYPE_NCB, 32, 749, 1, 1913},
- {"cvmx_endor_rfif_wr_timer64_msb", CVMX_CSR_DB_TYPE_NCB, 32, 750, 1, 1914},
- {"cvmx_endor_rstclk_clkenb0_clr", CVMX_CSR_DB_TYPE_NCB, 32, 751, 14, 1915},
- {"cvmx_endor_rstclk_clkenb0_set", CVMX_CSR_DB_TYPE_NCB, 32, 752, 14, 1929},
- {"cvmx_endor_rstclk_clkenb0_state", CVMX_CSR_DB_TYPE_NCB, 32, 753, 14, 1943},
- {"cvmx_endor_rstclk_clkenb1_clr", CVMX_CSR_DB_TYPE_NCB, 32, 754, 8, 1957},
- {"cvmx_endor_rstclk_clkenb1_set", CVMX_CSR_DB_TYPE_NCB, 32, 755, 8, 1965},
- {"cvmx_endor_rstclk_clkenb1_state", CVMX_CSR_DB_TYPE_NCB, 32, 756, 8, 1973},
- {"cvmx_endor_rstclk_dspstall_clr", CVMX_CSR_DB_TYPE_NCB, 32, 757, 7, 1981},
- {"cvmx_endor_rstclk_dspstall_set", CVMX_CSR_DB_TYPE_NCB, 32, 758, 7, 1988},
- {"cvmx_endor_rstclk_dspstall_state", CVMX_CSR_DB_TYPE_NCB, 32, 759, 7, 1995},
- {"cvmx_endor_rstclk_intr0_clrmask", CVMX_CSR_DB_TYPE_NCB, 32, 760, 2, 2002},
- {"cvmx_endor_rstclk_intr0_mask", CVMX_CSR_DB_TYPE_NCB, 32, 761, 2, 2004},
- {"cvmx_endor_rstclk_intr0_setmask", CVMX_CSR_DB_TYPE_NCB, 32, 762, 2, 2006},
- {"cvmx_endor_rstclk_intr0_status", CVMX_CSR_DB_TYPE_NCB, 32, 763, 1, 2008},
- {"cvmx_endor_rstclk_intr1_clrmask", CVMX_CSR_DB_TYPE_NCB, 32, 764, 1, 2009},
- {"cvmx_endor_rstclk_intr1_mask", CVMX_CSR_DB_TYPE_NCB, 32, 765, 1, 2010},
- {"cvmx_endor_rstclk_intr1_setmask", CVMX_CSR_DB_TYPE_NCB, 32, 766, 1, 2011},
- {"cvmx_endor_rstclk_intr1_status", CVMX_CSR_DB_TYPE_NCB, 32, 767, 1, 2012},
- {"cvmx_endor_rstclk_phy_config", CVMX_CSR_DB_TYPE_NCB, 32, 768, 7, 2013},
- {"cvmx_endor_rstclk_proc_mon" , CVMX_CSR_DB_TYPE_NCB, 32, 769, 3, 2020},
- {"cvmx_endor_rstclk_proc_mon_count", CVMX_CSR_DB_TYPE_NCB, 32, 770, 2, 2023},
- {"cvmx_endor_rstclk_reset0_clr", CVMX_CSR_DB_TYPE_NCB, 32, 771, 14, 2025},
- {"cvmx_endor_rstclk_reset0_set", CVMX_CSR_DB_TYPE_NCB, 32, 772, 14, 2039},
- {"cvmx_endor_rstclk_reset0_state", CVMX_CSR_DB_TYPE_NCB, 32, 773, 14, 2053},
- {"cvmx_endor_rstclk_reset1_clr", CVMX_CSR_DB_TYPE_NCB, 32, 774, 8, 2067},
- {"cvmx_endor_rstclk_reset1_set", CVMX_CSR_DB_TYPE_NCB, 32, 775, 8, 2075},
- {"cvmx_endor_rstclk_reset1_state", CVMX_CSR_DB_TYPE_NCB, 32, 776, 8, 2083},
- {"cvmx_endor_rstclk_sw_intr_clr", CVMX_CSR_DB_TYPE_NCB, 32, 777, 2, 2091},
- {"cvmx_endor_rstclk_sw_intr_set", CVMX_CSR_DB_TYPE_NCB, 32, 778, 2, 2093},
- {"cvmx_endor_rstclk_sw_intr_status", CVMX_CSR_DB_TYPE_NCB, 32, 779, 2, 2095},
- {"cvmx_endor_rstclk_time#_thrd", CVMX_CSR_DB_TYPE_NCB, 32, 780, 2, 2097},
- {"cvmx_endor_rstclk_timer_ctl" , CVMX_CSR_DB_TYPE_NCB, 32, 788, 6, 2099},
- {"cvmx_endor_rstclk_timer_intr_clr", CVMX_CSR_DB_TYPE_NCB, 32, 789, 2, 2105},
- {"cvmx_endor_rstclk_timer_intr_status", CVMX_CSR_DB_TYPE_NCB, 32, 790, 2, 2107},
- {"cvmx_endor_rstclk_timer_max" , CVMX_CSR_DB_TYPE_NCB, 32, 791, 1, 2109},
- {"cvmx_endor_rstclk_timer_value", CVMX_CSR_DB_TYPE_NCB, 32, 792, 1, 2110},
- {"cvmx_endor_rstclk_version" , CVMX_CSR_DB_TYPE_NCB, 32, 793, 3, 2111},
- {"cvmx_eoi_bist_ctl_sta" , CVMX_CSR_DB_TYPE_RSL, 64, 794, 7, 2114},
- {"cvmx_eoi_ctl_sta" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 7, 2121},
- {"cvmx_eoi_def_sta0" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 4, 2128},
- {"cvmx_eoi_def_sta1" , CVMX_CSR_DB_TYPE_RSL, 64, 797, 4, 2132},
- {"cvmx_eoi_def_sta2" , CVMX_CSR_DB_TYPE_RSL, 64, 798, 4, 2136},
- {"cvmx_eoi_ecc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 799, 3, 2140},
- {"cvmx_eoi_endor_bistr_ctl_sta", CVMX_CSR_DB_TYPE_RSL, 64, 800, 7, 2143},
- {"cvmx_eoi_endor_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 801, 12, 2150},
- {"cvmx_eoi_endor_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 9, 2162},
- {"cvmx_eoi_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 3, 2171},
- {"cvmx_eoi_int_sta" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 3, 2174},
- {"cvmx_eoi_io_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 805, 5, 2177},
- {"cvmx_eoi_throttle_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 6, 2182},
- {"cvmx_fpa_addr_range_error" , CVMX_CSR_DB_TYPE_RSL, 64, 807, 3, 2188},
- {"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 6, 2191},
- {"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 809, 10, 2197},
- {"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 3, 2207},
- {"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 817, 2, 2210},
- {"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 3, 2212},
- {"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 825, 2, 2215},
- {"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 47, 2217},
- {"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 827, 47, 2264},
- {"cvmx_fpa_packet_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 2, 2311},
- {"cvmx_fpa_pool#_end_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 829, 2, 2313},
- {"cvmx_fpa_pool#_start_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 837, 2, 2315},
- {"cvmx_fpa_pool#_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 845, 2, 2317},
- {"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 853, 2, 2319},
- {"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 861, 2, 2321},
- {"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 869, 3, 2323},
- {"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 870, 3, 2326},
- {"cvmx_fpa_wqe_threshold" , CVMX_CSR_DB_TYPE_RSL, 64, 871, 2, 2329},
- {"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 872, 7, 2331},
- {"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 873, 2, 2338},
- {"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 874, 2, 2340},
- {"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 5, 2342},
- {"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 876, 7, 2347},
- {"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 877, 2, 2354},
- {"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 878, 8, 2356},
- {"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 879, 10, 2364},
- {"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 881, 1, 2374},
- {"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 885, 1, 2375},
- {"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 889, 1, 2376},
- {"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 893, 1, 2377},
- {"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 897, 1, 2378},
- {"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 901, 1, 2379},
- {"cvmx_gmx#_rx#_adr_cam_all_en", CVMX_CSR_DB_TYPE_RSL, 64, 905, 2, 2380},
- {"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 907, 2, 2382},
- {"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 909, 4, 2384},
- {"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 911, 2, 2388},
- {"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 913, 9, 2390},
- {"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 915, 13, 2399},
- {"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 917, 2, 2412},
- {"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 919, 27, 2414},
- {"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 921, 27, 2441},
- {"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 2, 2468},
- {"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 925, 2, 2470},
- {"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 927, 2, 2472},
- {"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 929, 2, 2474},
- {"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 931, 2, 2476},
- {"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 933, 2, 2478},
- {"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 935, 2, 2480},
- {"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 937, 2, 2482},
- {"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 939, 2, 2484},
- {"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 941, 2, 2486},
- {"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 943, 2, 2488},
- {"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 945, 2, 2490},
- {"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 947, 4, 2492},
- {"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 949, 2, 2496},
- {"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 951, 2, 2498},
- {"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 953, 2, 2500},
- {"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 955, 4, 2502},
- {"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 956, 4, 2506},
- {"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 957, 2, 2510},
- {"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 958, 5, 2512},
- {"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 959, 2, 2517},
- {"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 960, 2, 2519},
- {"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 962, 3, 2521},
- {"cvmx_gmx#_tb_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 963, 2, 2524},
- {"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 964, 5, 2526},
- {"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 966, 2, 2531},
- {"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 968, 2, 2533},
- {"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 969, 2, 2535},
- {"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 970, 3, 2537},
- {"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 972, 2, 2540},
- {"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 974, 2, 2542},
- {"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 976, 2, 2544},
- {"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 978, 3, 2546},
- {"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 980, 2, 2549},
- {"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 982, 2, 2551},
- {"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 984, 2, 2553},
- {"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 986, 2, 2555},
- {"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 988, 2, 2557},
- {"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 2, 2559},
- {"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 2, 2561},
- {"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 994, 2, 2563},
- {"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 996, 2, 2565},
- {"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 2, 2567},
- {"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 1000, 2, 2569},
- {"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 1002, 2, 2571},
- {"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 2, 2573},
- {"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 2, 2575},
- {"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1008, 2, 2577},
- {"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 1010, 2, 2579},
- {"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1012, 2, 2581},
- {"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 1013, 2, 2583},
- {"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 1014, 2, 2585},
- {"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1015, 2, 2587},
- {"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 1016, 2, 2589},
- {"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 1017, 3, 2591},
- {"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1018, 14, 2594},
- {"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 14, 2608},
- {"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 1020, 2, 2622},
- {"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1021, 2, 2624},
- {"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1022, 8, 2626},
- {"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 2, 2634},
- {"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 2, 2636},
- {"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 2, 2638},
- {"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 9, 2640},
- {"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 3, 2649},
- {"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 1028, 10, 2652},
- {"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 1044, 2, 2662},
- {"cvmx_gpio_clk_qlm#" , CVMX_CSR_DB_TYPE_NCB, 64, 1048, 5, 2664},
- {"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 1050, 2, 2669},
- {"cvmx_gpio_multi_cast" , CVMX_CSR_DB_TYPE_NCB, 64, 1051, 2, 2671},
- {"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 1052, 2, 2673},
- {"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 1053, 2, 2675},
- {"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 1054, 2, 2677},
- {"cvmx_gpio_xbit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 1055, 10, 2679},
- {"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 24, 2689},
- {"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1060, 9, 2713},
- {"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 3, 2722},
- {"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 1062, 3, 2725},
- {"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1063, 3, 2728},
- {"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1064, 5, 2731},
- {"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1065, 5, 2736},
- {"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1066, 1, 2741},
- {"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1067, 1, 2742},
- {"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1068, 7, 2743},
- {"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1069, 7, 2750},
- {"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1070, 3, 2757},
- {"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1071, 3, 2760},
- {"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1072, 3, 2763},
- {"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1073, 5, 2766},
- {"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1074, 5, 2771},
- {"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1075, 1, 2776},
- {"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1076, 1, 2777},
- {"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1077, 3, 2778},
- {"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1078, 3, 2781},
- {"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1079, 3, 2784},
- {"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1080, 3, 2787},
- {"cvmx_iob_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 1081, 4, 2790},
- {"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1082, 2, 2794},
- {"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 1083, 2, 2796},
- {"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 1084, 2, 2798},
- {"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1085, 19, 2800},
- {"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 1086, 2, 2819},
- {"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1087, 1, 2821},
- {"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1088, 18, 2822},
- {"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1089, 13, 2840},
- {"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1090, 13, 2853},
- {"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1091, 2, 2866},
- {"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1092, 2, 2868},
- {"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1093, 2, 2870},
- {"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1094, 3, 2872},
- {"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 1106, 3, 2875},
- {"cvmx_ipd_port#_bp_page_cnt3" , CVMX_CSR_DB_TYPE_NCB, 64, 1110, 3, 2878},
- {"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1118, 2, 2881},
- {"cvmx_ipd_port_bp_counters3_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1122, 2, 2883},
- {"cvmx_ipd_port_bp_counters4_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1126, 2, 2885},
- {"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1130, 2, 2887},
- {"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1142, 2, 2889},
- {"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 1334, 1, 2891},
- {"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 1338, 1, 2892},
- {"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1342, 6, 2893},
- {"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1343, 5, 2899},
- {"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1344, 6, 2904},
- {"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1345, 7, 2910},
- {"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 1346, 2, 2917},
- {"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1354, 2, 2919},
- {"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 1355, 3, 2921},
- {"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 1356, 2, 2924},
- {"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 1357, 5, 2926},
- {"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 1365, 3, 2931},
- {"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 1366, 4, 2934},
- {"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1367, 3, 2938},
- {"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 1368, 2, 2941},
- {"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1369, 2, 2943},
- {"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1370, 4, 2945},
- {"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1371, 3, 2949},
- {"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1372, 5, 2952},
- {"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1373, 5, 2957},
- {"cvmx_l2c_big_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1374, 4, 2962},
- {"cvmx_l2c_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 1375, 12, 2966},
- {"cvmx_l2c_bst_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 1376, 5, 2978},
- {"cvmx_l2c_bst_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1377, 5, 2983},
- {"cvmx_l2c_bst_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1378, 3, 2988},
- {"cvmx_l2c_cop0_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 1379, 1, 2991},
- {"cvmx_l2c_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2659, 15, 2992},
- {"cvmx_l2c_dut_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 2660, 4, 3007},
- {"cvmx_l2c_err_tdt#" , CVMX_CSR_DB_TYPE_RSL, 64, 3684, 9, 3011},
- {"cvmx_l2c_err_ttg#" , CVMX_CSR_DB_TYPE_RSL, 64, 3685, 9, 3020},
- {"cvmx_l2c_err_vbf#" , CVMX_CSR_DB_TYPE_RSL, 64, 3686, 6, 3029},
- {"cvmx_l2c_err_xmc" , CVMX_CSR_DB_TYPE_RSL, 64, 3687, 5, 3035},
- {"cvmx_l2c_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 3688, 9, 3040},
- {"cvmx_l2c_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 3689, 11, 3049},
- {"cvmx_l2c_ioc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 3690, 1, 3060},
- {"cvmx_l2c_ior#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 3691, 1, 3061},
- {"cvmx_l2c_qos_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 3692, 4, 3062},
- {"cvmx_l2c_qos_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 3693, 2, 3066},
- {"cvmx_l2c_qos_wgt" , CVMX_CSR_DB_TYPE_RSL, 64, 3697, 5, 3068},
- {"cvmx_l2c_rsc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 3698, 1, 3073},
- {"cvmx_l2c_rsd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 3699, 1, 3074},
- {"cvmx_l2c_tad#_ecc0" , CVMX_CSR_DB_TYPE_RSL, 64, 3700, 8, 3075},
- {"cvmx_l2c_tad#_ecc1" , CVMX_CSR_DB_TYPE_RSL, 64, 3701, 8, 3083},
- {"cvmx_l2c_tad#_ien" , CVMX_CSR_DB_TYPE_RSL, 64, 3702, 10, 3091},
- {"cvmx_l2c_tad#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 3703, 10, 3101},
- {"cvmx_l2c_tad#_pfc0" , CVMX_CSR_DB_TYPE_RSL, 64, 3704, 1, 3111},
- {"cvmx_l2c_tad#_pfc1" , CVMX_CSR_DB_TYPE_RSL, 64, 3705, 1, 3112},
- {"cvmx_l2c_tad#_pfc2" , CVMX_CSR_DB_TYPE_RSL, 64, 3706, 1, 3113},
- {"cvmx_l2c_tad#_pfc3" , CVMX_CSR_DB_TYPE_RSL, 64, 3707, 1, 3114},
- {"cvmx_l2c_tad#_prf" , CVMX_CSR_DB_TYPE_RSL, 64, 3708, 5, 3115},
- {"cvmx_l2c_tad#_tag" , CVMX_CSR_DB_TYPE_RSL, 64, 3709, 9, 3120},
- {"cvmx_l2c_ver_id" , CVMX_CSR_DB_TYPE_RSL, 64, 3710, 1, 3129},
- {"cvmx_l2c_ver_iob" , CVMX_CSR_DB_TYPE_RSL, 64, 3711, 2, 3130},
- {"cvmx_l2c_ver_msc" , CVMX_CSR_DB_TYPE_RSL, 64, 3712, 3, 3132},
- {"cvmx_l2c_ver_pp" , CVMX_CSR_DB_TYPE_RSL, 64, 3713, 2, 3135},
- {"cvmx_l2c_virtid_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 3714, 4, 3137},
- {"cvmx_l2c_virtid_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 3715, 2, 3141},
- {"cvmx_l2c_vrt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 3719, 6, 3143},
- {"cvmx_l2c_vrt_mem#" , CVMX_CSR_DB_TYPE_RSL, 64, 3720, 3, 3149},
- {"cvmx_l2c_wpar_iob#" , CVMX_CSR_DB_TYPE_RSL, 64, 4744, 2, 3152},
- {"cvmx_l2c_wpar_pp#" , CVMX_CSR_DB_TYPE_RSL, 64, 4745, 2, 3154},
- {"cvmx_l2c_xmc#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4749, 1, 3156},
- {"cvmx_l2c_xmc_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 4750, 4, 3157},
- {"cvmx_l2c_xmd#_pfc" , CVMX_CSR_DB_TYPE_RSL, 64, 4751, 1, 3161},
- {"cvmx_lmc#_char_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4752, 7, 3162},
- {"cvmx_lmc#_char_mask0" , CVMX_CSR_DB_TYPE_RSL, 64, 4753, 1, 3169},
- {"cvmx_lmc#_char_mask1" , CVMX_CSR_DB_TYPE_RSL, 64, 4754, 2, 3170},
- {"cvmx_lmc#_char_mask2" , CVMX_CSR_DB_TYPE_RSL, 64, 4755, 1, 3172},
- {"cvmx_lmc#_char_mask3" , CVMX_CSR_DB_TYPE_RSL, 64, 4756, 2, 3173},
- {"cvmx_lmc#_char_mask4" , CVMX_CSR_DB_TYPE_RSL, 64, 4757, 12, 3175},
- {"cvmx_lmc#_comp_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 4758, 11, 3187},
- {"cvmx_lmc#_config" , CVMX_CSR_DB_TYPE_RSL, 64, 4759, 23, 3198},
- {"cvmx_lmc#_control" , CVMX_CSR_DB_TYPE_RSL, 64, 4760, 21, 3221},
- {"cvmx_lmc#_dclk_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 4761, 1, 3242},
- {"cvmx_lmc#_ddr_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4762, 11, 3243},
- {"cvmx_lmc#_dimm#_params" , CVMX_CSR_DB_TYPE_RSL, 64, 4763, 16, 3254},
- {"cvmx_lmc#_dimm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4765, 5, 3270},
- {"cvmx_lmc#_dll_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 4766, 7, 3275},
- {"cvmx_lmc#_dll_ctl3" , CVMX_CSR_DB_TYPE_RSL, 64, 4767, 16, 3282},
- {"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4768, 4, 3298},
- {"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 4769, 5, 3302},
- {"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 4770, 6, 3307},
- {"cvmx_lmc#_ifb_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 4771, 1, 3313},
- {"cvmx_lmc#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4772, 4, 3314},
- {"cvmx_lmc#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 4773, 4, 3318},
- {"cvmx_lmc#_modereg_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 4774, 16, 3322},
- {"cvmx_lmc#_modereg_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 4775, 25, 3338},
- {"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 4776, 10, 3363},
- {"cvmx_lmc#_ops_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 4777, 1, 3373},
- {"cvmx_lmc#_phy_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4778, 10, 3374},
- {"cvmx_lmc#_reset_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4779, 5, 3384},
- {"cvmx_lmc#_rlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4780, 10, 3389},
- {"cvmx_lmc#_rlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 4781, 1, 3399},
- {"cvmx_lmc#_rlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 4782, 11, 3400},
- {"cvmx_lmc#_rodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 4786, 8, 3411},
- {"cvmx_lmc#_scramble_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 4787, 1, 3419},
- {"cvmx_lmc#_scramble_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 4788, 1, 3420},
- {"cvmx_lmc#_scrambled_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 4789, 6, 3421},
- {"cvmx_lmc#_slot_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 4790, 5, 3427},
- {"cvmx_lmc#_slot_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 4791, 5, 3432},
- {"cvmx_lmc#_slot_ctl2" , CVMX_CSR_DB_TYPE_RSL, 64, 4792, 5, 3437},
- {"cvmx_lmc#_timing_params0" , CVMX_CSR_DB_TYPE_RSL, 64, 4793, 12, 3442},
- {"cvmx_lmc#_timing_params1" , CVMX_CSR_DB_TYPE_RSL, 64, 4794, 13, 3454},
- {"cvmx_lmc#_tro_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4795, 3, 3467},
- {"cvmx_lmc#_tro_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 4796, 2, 3470},
- {"cvmx_lmc#_wlevel_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 4797, 6, 3472},
- {"cvmx_lmc#_wlevel_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 4798, 3, 3478},
- {"cvmx_lmc#_wlevel_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 4799, 11, 3481},
- {"cvmx_lmc#_wodt_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 4803, 8, 3492},
- {"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 4804, 2, 3500},
- {"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 4805, 3, 3502},
- {"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 4806, 10, 3505},
- {"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 4808, 3, 3515},
- {"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 4810, 3, 3518},
- {"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 4812, 15, 3521},
- {"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 4814, 3, 3536},
- {"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4815, 3, 3539},
- {"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 4816, 3, 3542},
- {"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 4817, 5, 3545},
- {"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 4819, 1, 3550},
- {"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 4820, 10, 3551},
- {"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 4821, 13, 3561},
- {"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 4829, 13, 3574},
- {"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 4837, 6, 3587},
- {"cvmx_mio_emm_buf_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 4838, 1, 3593},
- {"cvmx_mio_emm_buf_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 4839, 5, 3594},
- {"cvmx_mio_emm_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4840, 4, 3599},
- {"cvmx_mio_emm_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 4841, 11, 3603},
- {"cvmx_mio_emm_dma" , CVMX_CSR_DB_TYPE_RSL, 64, 4842, 11, 3614},
- {"cvmx_mio_emm_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4843, 8, 3625},
- {"cvmx_mio_emm_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 4844, 8, 3633},
- {"cvmx_mio_emm_mode#" , CVMX_CSR_DB_TYPE_RSL, 64, 4845, 8, 3641},
- {"cvmx_mio_emm_rca" , CVMX_CSR_DB_TYPE_RSL, 64, 4849, 2, 3649},
- {"cvmx_mio_emm_rsp_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 4850, 1, 3651},
- {"cvmx_mio_emm_rsp_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 4851, 1, 3652},
- {"cvmx_mio_emm_rsp_sts" , CVMX_CSR_DB_TYPE_RSL, 64, 4852, 25, 3653},
- {"cvmx_mio_emm_sample" , CVMX_CSR_DB_TYPE_RSL, 64, 4853, 4, 3678},
- {"cvmx_mio_emm_sts_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 4854, 2, 3682},
- {"cvmx_mio_emm_switch" , CVMX_CSR_DB_TYPE_RSL, 64, 4855, 14, 3684},
- {"cvmx_mio_emm_wdog" , CVMX_CSR_DB_TYPE_RSL, 64, 4856, 2, 3698},
- {"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 4857, 1, 3700},
- {"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 4859, 2, 3701},
- {"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 4860, 2, 3703},
- {"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 4861, 15, 3705},
- {"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 4862, 18, 3720},
- {"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 4863, 4, 3738},
- {"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 4864, 1, 3742},
- {"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 4865, 7, 3743},
- {"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 4866, 3, 3750},
- {"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 4867, 8, 3753},
- {"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 4868, 7, 3761},
- {"cvmx_mio_fus_read_times" , CVMX_CSR_DB_TYPE_RSL, 64, 4869, 6, 3768},
- {"cvmx_mio_fus_repair_res0" , CVMX_CSR_DB_TYPE_RSL, 64, 4870, 5, 3774},
- {"cvmx_mio_fus_repair_res1" , CVMX_CSR_DB_TYPE_RSL, 64, 4871, 4, 3779},
- {"cvmx_mio_fus_repair_res2" , CVMX_CSR_DB_TYPE_RSL, 64, 4872, 2, 3783},
- {"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 4873, 4, 3785},
- {"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 4874, 2, 3789},
- {"cvmx_mio_fus_tgg" , CVMX_CSR_DB_TYPE_RSL, 64, 4875, 2, 3791},
- {"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 4876, 2, 3793},
- {"cvmx_mio_gpio_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 4877, 3, 3795},
- {"cvmx_mio_ndf_dma_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4878, 10, 3798},
- {"cvmx_mio_ndf_dma_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4879, 2, 3808},
- {"cvmx_mio_ndf_dma_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 4880, 2, 3810},
- {"cvmx_mio_ptp_ckout_hi_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 4881, 2, 3812},
- {"cvmx_mio_ptp_ckout_lo_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 4882, 2, 3814},
- {"cvmx_mio_ptp_ckout_thresh_hi", CVMX_CSR_DB_TYPE_NCB, 64, 4883, 1, 3816},
- {"cvmx_mio_ptp_ckout_thresh_lo", CVMX_CSR_DB_TYPE_NCB, 64, 4884, 2, 3817},
- {"cvmx_mio_ptp_clock_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 4885, 20, 3819},
- {"cvmx_mio_ptp_clock_comp" , CVMX_CSR_DB_TYPE_NCB, 64, 4886, 2, 3839},
- {"cvmx_mio_ptp_clock_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 4887, 1, 3841},
- {"cvmx_mio_ptp_clock_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 4888, 2, 3842},
- {"cvmx_mio_ptp_evt_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 4889, 1, 3844},
- {"cvmx_mio_ptp_phy_1pps_in" , CVMX_CSR_DB_TYPE_NCB, 64, 4890, 2, 3845},
- {"cvmx_mio_ptp_pps_hi_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 4891, 2, 3847},
- {"cvmx_mio_ptp_pps_lo_incr" , CVMX_CSR_DB_TYPE_NCB, 64, 4892, 2, 3849},
- {"cvmx_mio_ptp_pps_thresh_hi" , CVMX_CSR_DB_TYPE_NCB, 64, 4893, 1, 3851},
- {"cvmx_mio_ptp_pps_thresh_lo" , CVMX_CSR_DB_TYPE_NCB, 64, 4894, 2, 3852},
- {"cvmx_mio_ptp_timestamp" , CVMX_CSR_DB_TYPE_NCB, 64, 4895, 1, 3854},
- {"cvmx_mio_qlm#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4896, 6, 3855},
- {"cvmx_mio_rst_boot" , CVMX_CSR_DB_TYPE_RSL, 64, 4898, 17, 3861},
- {"cvmx_mio_rst_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4899, 5, 3878},
- {"cvmx_mio_rst_ckill" , CVMX_CSR_DB_TYPE_RSL, 64, 4900, 2, 3883},
- {"cvmx_mio_rst_cntl#" , CVMX_CSR_DB_TYPE_RSL, 64, 4901, 13, 3885},
- {"cvmx_mio_rst_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 4903, 13, 3898},
- {"cvmx_mio_rst_delay" , CVMX_CSR_DB_TYPE_RSL, 64, 4905, 3, 3911},
- {"cvmx_mio_rst_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4906, 6, 3914},
- {"cvmx_mio_rst_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 4907, 6, 3920},
- {"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 4908, 13, 3926},
- {"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 4910, 12, 3939},
- {"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 4912, 3, 3951},
- {"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 4914, 3, 3954},
- {"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 4916, 2, 3957},
- {"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 4918, 2, 3959},
- {"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 4920, 2, 3961},
- {"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 4922, 7, 3963},
- {"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 4924, 2, 3970},
- {"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 4926, 7, 3972},
- {"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 4928, 4, 3979},
- {"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 4930, 8, 3983},
- {"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 4932, 9, 3991},
- {"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 4934, 7, 4000},
- {"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 4936, 9, 4007},
- {"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 4938, 2, 4016},
- {"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 4940, 2, 4018},
- {"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 4942, 4, 4020},
- {"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 4944, 2, 4024},
- {"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 4946, 2, 4026},
- {"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 4948, 2, 4028},
- {"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 4950, 4, 4030},
- {"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 4952, 2, 4034},
- {"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 4954, 2, 4036},
- {"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 4956, 2, 4038},
- {"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 4958, 2, 4040},
- {"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 4960, 2, 4042},
- {"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 4962, 2, 4044},
- {"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 4964, 6, 4046},
- {"cvmx_mpi_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 4966, 16, 4052},
- {"cvmx_mpi_dat#" , CVMX_CSR_DB_TYPE_NCB, 64, 4967, 2, 4068},
- {"cvmx_mpi_sts" , CVMX_CSR_DB_TYPE_NCB, 64, 4976, 4, 4070},
- {"cvmx_mpi_tx" , CVMX_CSR_DB_TYPE_NCB, 64, 4977, 8, 4074},
- {"cvmx_pcieep#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4978, 2, 4082},
- {"cvmx_pcieep#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4980, 24, 4084},
- {"cvmx_pcieep#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4982, 4, 4108},
- {"cvmx_pcieep#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4984, 5, 4112},
- {"cvmx_pcieep#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4986, 5, 4117},
- {"cvmx_pcieep#_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4988, 2, 4122},
- {"cvmx_pcieep#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4990, 1, 4124},
- {"cvmx_pcieep#_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4992, 1, 4125},
- {"cvmx_pcieep#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4994, 5, 4126},
- {"cvmx_pcieep#_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4996, 2, 4131},
- {"cvmx_pcieep#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 4998, 1, 4133},
- {"cvmx_pcieep#_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5000, 1, 4134},
- {"cvmx_pcieep#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5002, 4, 4135},
- {"cvmx_pcieep#_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5004, 2, 4139},
- {"cvmx_pcieep#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5006, 2, 4141},
- {"cvmx_pcieep#_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5008, 1, 4143},
- {"cvmx_pcieep#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5010, 1, 4144},
- {"cvmx_pcieep#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5012, 2, 4145},
- {"cvmx_pcieep#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5014, 3, 4147},
- {"cvmx_pcieep#_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5016, 2, 4150},
- {"cvmx_pcieep#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5018, 2, 4152},
- {"cvmx_pcieep#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5020, 4, 4154},
- {"cvmx_pcieep#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5022, 10, 4158},
- {"cvmx_pcieep#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5024, 12, 4168},
- {"cvmx_pcieep#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5026, 8, 4180},
- {"cvmx_pcieep#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5028, 2, 4188},
- {"cvmx_pcieep#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5030, 1, 4190},
- {"cvmx_pcieep#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5032, 2, 4191},
- {"cvmx_pcieep#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5034, 7, 4193},
- {"cvmx_pcieep#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5036, 12, 4200},
- {"cvmx_pcieep#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5038, 19, 4212},
- {"cvmx_pcieep#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5040, 12, 4231},
- {"cvmx_pcieep#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5042, 20, 4243},
- {"cvmx_pcieep#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5044, 13, 4263},
- {"cvmx_pcieep#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5046, 11, 4276},
- {"cvmx_pcieep#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5048, 4, 4287},
- {"cvmx_pcieep#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5050, 11, 4291},
- {"cvmx_pcieep#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5052, 3, 4302},
- {"cvmx_pcieep#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5054, 17, 4305},
- {"cvmx_pcieep#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5056, 17, 4322},
- {"cvmx_pcieep#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5058, 17, 4339},
- {"cvmx_pcieep#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5060, 10, 4356},
- {"cvmx_pcieep#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5062, 10, 4366},
- {"cvmx_pcieep#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5064, 6, 4376},
- {"cvmx_pcieep#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5066, 1, 4382},
- {"cvmx_pcieep#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5068, 1, 4383},
- {"cvmx_pcieep#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5070, 1, 4384},
- {"cvmx_pcieep#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5072, 1, 4385},
- {"cvmx_pcieep#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5074, 2, 4386},
- {"cvmx_pcieep#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5076, 1, 4388},
- {"cvmx_pcieep#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5078, 6, 4389},
- {"cvmx_pcieep#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5080, 7, 4395},
- {"cvmx_pcieep#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5082, 11, 4402},
- {"cvmx_pcieep#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5084, 5, 4413},
- {"cvmx_pcieep#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5086, 6, 4418},
- {"cvmx_pcieep#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5088, 19, 4424},
- {"cvmx_pcieep#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5090, 5, 4443},
- {"cvmx_pcieep#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5092, 1, 4448},
- {"cvmx_pcieep#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5094, 1, 4449},
- {"cvmx_pcieep#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5096, 3, 4450},
- {"cvmx_pcieep#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5098, 3, 4453},
- {"cvmx_pcieep#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5100, 3, 4456},
- {"cvmx_pcieep#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5102, 4, 4459},
- {"cvmx_pcieep#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5104, 4, 4463},
- {"cvmx_pcieep#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5106, 4, 4467},
- {"cvmx_pcieep#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5108, 7, 4471},
- {"cvmx_pcieep#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5110, 5, 4478},
- {"cvmx_pcieep#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5112, 5, 4483},
- {"cvmx_pcieep#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5114, 4, 4488},
- {"cvmx_pcieep#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5116, 4, 4492},
- {"cvmx_pcieep#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5118, 4, 4496},
- {"cvmx_pcieep#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5120, 7, 4500},
- {"cvmx_pcieep#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5122, 1, 4507},
- {"cvmx_pcieep#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 5124, 1, 4508},
- {"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5126, 2, 4509},
- {"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5128, 24, 4511},
- {"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5130, 4, 4535},
- {"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5132, 5, 4539},
- {"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5134, 1, 4544},
- {"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5136, 1, 4545},
- {"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5138, 4, 4546},
- {"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5140, 17, 4550},
- {"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5142, 4, 4567},
- {"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5144, 6, 4571},
- {"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5146, 1, 4577},
- {"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5148, 1, 4578},
- {"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5150, 2, 4579},
- {"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5152, 2, 4581},
- {"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5154, 1, 4583},
- {"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5156, 15, 4584},
- {"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5158, 10, 4599},
- {"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5160, 12, 4609},
- {"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5162, 8, 4621},
- {"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5164, 2, 4629},
- {"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5166, 1, 4631},
- {"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5168, 2, 4632},
- {"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5170, 7, 4634},
- {"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5172, 11, 4641},
- {"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5174, 19, 4652},
- {"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5176, 12, 4671},
- {"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5178, 20, 4683},
- {"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5180, 12, 4703},
- {"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5182, 22, 4715},
- {"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5184, 8, 4737},
- {"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5186, 4, 4745},
- {"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5188, 13, 4749},
- {"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5190, 11, 4762},
- {"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5192, 4, 4773},
- {"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5194, 11, 4777},
- {"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5196, 1, 4788},
- {"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5198, 1, 4789},
- {"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5200, 3, 4790},
- {"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5202, 18, 4793},
- {"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5204, 18, 4811},
- {"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5206, 18, 4829},
- {"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5208, 10, 4847},
- {"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5210, 10, 4857},
- {"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5212, 6, 4867},
- {"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5214, 1, 4873},
- {"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5216, 1, 4874},
- {"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5218, 1, 4875},
- {"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5220, 1, 4876},
- {"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5222, 4, 4877},
- {"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5224, 9, 4881},
- {"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5226, 2, 4890},
- {"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5228, 2, 4892},
- {"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5230, 1, 4894},
- {"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5232, 6, 4895},
- {"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5234, 7, 4901},
- {"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5236, 11, 4908},
- {"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5238, 5, 4919},
- {"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5240, 6, 4924},
- {"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5242, 19, 4930},
- {"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5244, 5, 4949},
- {"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5246, 1, 4954},
- {"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5248, 1, 4955},
- {"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5250, 3, 4956},
- {"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5252, 3, 4959},
- {"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5254, 3, 4962},
- {"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5256, 4, 4965},
- {"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5258, 4, 4969},
- {"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5260, 4, 4973},
- {"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5262, 7, 4977},
- {"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5264, 5, 4984},
- {"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5266, 5, 4989},
- {"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5268, 4, 4994},
- {"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5270, 4, 4998},
- {"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5272, 4, 5002},
- {"cvmx_pcierc#_cfg515" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5274, 7, 5006},
- {"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5276, 1, 5013},
- {"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 5278, 1, 5014},
- {"cvmx_pcm#_dma_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5280, 12, 5015},
- {"cvmx_pcm#_int_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 5284, 9, 5027},
- {"cvmx_pcm#_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 5288, 9, 5036},
- {"cvmx_pcm#_rxaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 5292, 2, 5045},
- {"cvmx_pcm#_rxcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5296, 2, 5047},
- {"cvmx_pcm#_rxmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 5300, 1, 5049},
- {"cvmx_pcm#_rxmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 5304, 1, 5050},
- {"cvmx_pcm#_rxmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 5308, 1, 5051},
- {"cvmx_pcm#_rxmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 5312, 1, 5052},
- {"cvmx_pcm#_rxmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 5316, 1, 5053},
- {"cvmx_pcm#_rxmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 5320, 1, 5054},
- {"cvmx_pcm#_rxmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 5324, 1, 5055},
- {"cvmx_pcm#_rxmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 5328, 1, 5056},
- {"cvmx_pcm#_rxstart" , CVMX_CSR_DB_TYPE_NCB, 64, 5332, 3, 5057},
- {"cvmx_pcm#_tdm_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5336, 6, 5060},
- {"cvmx_pcm#_tdm_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 5340, 1, 5066},
- {"cvmx_pcm#_txaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 5344, 3, 5067},
- {"cvmx_pcm#_txcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 5348, 2, 5070},
- {"cvmx_pcm#_txmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 5352, 1, 5072},
- {"cvmx_pcm#_txmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 5356, 1, 5073},
- {"cvmx_pcm#_txmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 5360, 1, 5074},
- {"cvmx_pcm#_txmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 5364, 1, 5075},
- {"cvmx_pcm#_txmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 5368, 1, 5076},
- {"cvmx_pcm#_txmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 5372, 1, 5077},
- {"cvmx_pcm#_txmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 5376, 1, 5078},
- {"cvmx_pcm#_txmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 5380, 1, 5079},
- {"cvmx_pcm#_txstart" , CVMX_CSR_DB_TYPE_NCB, 64, 5384, 3, 5080},
- {"cvmx_pcm_clk#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 5388, 12, 5083},
- {"cvmx_pcm_clk#_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 5390, 1, 5095},
- {"cvmx_pcm_clk#_gen" , CVMX_CSR_DB_TYPE_NCB, 64, 5392, 3, 5096},
- {"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5394, 9, 5099},
- {"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5396, 6, 5108},
- {"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5398, 9, 5114},
- {"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5400, 6, 5123},
- {"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5402, 14, 5129},
- {"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5404, 14, 5143},
- {"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 5406, 2, 5157},
- {"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5408, 4, 5159},
- {"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5410, 8, 5163},
- {"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5412, 13, 5171},
- {"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5414, 17, 5184},
- {"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5416, 7, 5201},
- {"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5418, 3, 5208},
- {"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5420, 8, 5211},
- {"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5422, 7, 5219},
- {"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 5424, 4, 5226},
- {"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 5426, 5, 5230},
- {"cvmx_pem#_bar1_index#" , CVMX_CSR_DB_TYPE_RSL, 64, 5428, 5, 5235},
- {"cvmx_pem#_bar2_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 5460, 3, 5240},
- {"cvmx_pem#_bar_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 5462, 5, 5243},
- {"cvmx_pem#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5464, 9, 5248},
- {"cvmx_pem#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 5466, 11, 5257},
- {"cvmx_pem#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 5468, 2, 5268},
- {"cvmx_pem#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 5470, 2, 5270},
- {"cvmx_pem#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 5472, 2, 5272},
- {"cvmx_pem#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5474, 18, 5274},
- {"cvmx_pem#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 5476, 32, 5292},
- {"cvmx_pem#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 5478, 32, 5324},
- {"cvmx_pem#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5480, 5, 5356},
- {"cvmx_pem#_inb_read_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 5482, 2, 5361},
- {"cvmx_pem#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 5484, 15, 5363},
- {"cvmx_pem#_int_enb_int" , CVMX_CSR_DB_TYPE_RSL, 64, 5486, 15, 5378},
- {"cvmx_pem#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 5488, 15, 5393},
- {"cvmx_pem#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 5490, 2, 5408},
- {"cvmx_pem#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 5492, 2, 5410},
- {"cvmx_pem#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 5494, 2, 5412},
- {"cvmx_pem#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 5496, 6, 5414},
- {"cvmx_pip_alt_skip_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 5498, 12, 5420},
- {"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 5502, 5, 5432},
- {"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 5503, 2, 5437},
- {"cvmx_pip_bsel_ext_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 5504, 7, 5439},
- {"cvmx_pip_bsel_ext_pos#" , CVMX_CSR_DB_TYPE_RSL, 64, 5508, 16, 5446},
- {"cvmx_pip_bsel_tbl_ent#" , CVMX_CSR_DB_TYPE_RSL, 64, 5512, 12, 5462},
- {"cvmx_pip_clken" , CVMX_CSR_DB_TYPE_RSL, 64, 6024, 2, 5474},
- {"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 6025, 4, 5476},
- {"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 6029, 16, 5480},
- {"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 6030, 16, 5496},
- {"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 6031, 3, 5512},
- {"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 6032, 8, 5515},
- {"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6033, 23, 5523},
- {"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6034, 6, 5546},
- {"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 6035, 14, 5552},
- {"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 6036, 14, 5566},
- {"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 6037, 2, 5580},
- {"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 6038, 28, 5582},
- {"cvmx_pip_prt_cfgb#" , CVMX_CSR_DB_TYPE_RSL, 64, 6048, 7, 5610},
- {"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 6064, 25, 5617},
- {"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 6074, 2, 5642},
- {"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 6138, 4, 5644},
- {"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 6146, 9, 5648},
- {"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 6154, 2, 5657},
- {"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 6155, 2, 5659},
- {"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6156, 2, 5661},
- {"cvmx_pip_stat10_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6166, 2, 5663},
- {"cvmx_pip_stat11_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6176, 2, 5665},
- {"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6186, 2, 5667},
- {"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6196, 2, 5669},
- {"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6206, 2, 5671},
- {"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6216, 2, 5673},
- {"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6226, 2, 5675},
- {"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6236, 2, 5677},
- {"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6246, 2, 5679},
- {"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6256, 2, 5681},
- {"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 6266, 2, 5683},
- {"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6276, 2, 5685},
- {"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 6277, 2, 5687},
- {"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 6287, 2, 5689},
- {"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 6297, 2, 5691},
- {"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 6307, 2, 5693},
- {"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6371, 2, 5695},
- {"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 6372, 3, 5697},
- {"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 6373, 3, 5700},
- {"cvmx_pip_vlan_etypes#" , CVMX_CSR_DB_TYPE_RSL, 64, 6374, 4, 5703},
- {"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 6376, 2, 5707},
- {"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 6377, 2, 5709},
- {"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6378, 4, 5711},
- {"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6379, 5, 5715},
- {"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 6380, 4, 5720},
- {"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 6381, 8, 5724},
- {"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 6382, 4, 5732},
- {"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 6383, 5, 5736},
- {"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 6384, 1, 5741},
- {"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6385, 5, 5742},
- {"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6386, 1, 5747},
- {"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 6387, 13, 5748},
- {"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 6388, 6, 5761},
- {"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 6389, 13, 5767},
- {"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 6390, 6, 5780},
- {"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 6391, 12, 5786},
- {"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 6392, 4, 5798},
- {"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 6393, 7, 5802},
- {"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6394, 5, 5809},
- {"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 6395, 5, 5814},
- {"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 6396, 4, 5819},
- {"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 6397, 9, 5823},
- {"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 6398, 5, 5832},
- {"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 6399, 16, 5837},
- {"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 6400, 4, 5853},
- {"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6401, 1, 5857},
- {"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6402, 1, 5858},
- {"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6403, 1, 5859},
- {"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6404, 1, 5860},
- {"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 6405, 15, 5861},
- {"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 6406, 2, 5876},
- {"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 6407, 4, 5878},
- {"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 6408, 8, 5882},
- {"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 6409, 3, 5890},
- {"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6410, 4, 5893},
- {"cvmx_pko_reg_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 6411, 2, 5897},
- {"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 6412, 2, 5899},
- {"cvmx_pko_reg_queue_preempt" , CVMX_CSR_DB_TYPE_RSL, 64, 6413, 3, 5901},
- {"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 6414, 3, 5904},
- {"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 6415, 3, 5907},
- {"cvmx_pko_reg_timestamp" , CVMX_CSR_DB_TYPE_RSL, 64, 6416, 2, 5910},
- {"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 6417, 10, 5912},
- {"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6418, 2, 5922},
- {"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 6419, 13, 5924},
- {"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 6420, 3, 5937},
- {"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 6421, 2, 5940},
- {"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 6429, 2, 5942},
- {"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 6430, 2, 5944},
- {"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 6431, 2, 5946},
- {"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6432, 2, 5948},
- {"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 6440, 2, 5950},
- {"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 6441, 2, 5952},
- {"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 6442, 2, 5954},
- {"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 6443, 10, 5956},
- {"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 6447, 5, 5966},
- {"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6455, 10, 5971},
- {"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6463, 2, 5981},
- {"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6464, 2, 5983},
- {"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 6465, 2, 5985},
- {"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 6473, 3, 5987},
- {"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 6474, 6, 5990},
- {"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 6490, 5, 5996},
- {"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 6491, 7, 6001},
- {"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 6507, 2, 6008},
- {"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6523, 1, 6010},
- {"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6524, 1, 6011},
- {"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6525, 1, 6012},
- {"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 6526, 5, 6013},
- {"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 6527, 5, 6018},
- {"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 6528, 4, 6023},
- {"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 6529, 10, 6027},
- {"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 6530, 1, 6037},
- {"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 6531, 3, 6038},
- {"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 6532, 7, 6041},
- {"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 6533, 2, 6048},
- {"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 6534, 1, 6050},
- {"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 6535, 1, 6051},
- {"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 6536, 1, 6052},
- {"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 6537, 18, 6053},
- {"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 6538, 3, 6071},
- {"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 6539, 2, 6074},
- {"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 6540, 3, 6076},
- {"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 6541, 7, 6079},
- {"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 6542, 2, 6086},
- {"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 6543, 2, 6088},
- {"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 6544, 2, 6090},
- {"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 6545, 3, 6092},
- {"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6546, 3, 6095},
- {"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 6547, 10, 6098},
- {"cvmx_rnm_eer_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 6548, 1, 6108},
- {"cvmx_rnm_eer_key" , CVMX_CSR_DB_TYPE_RSL, 64, 6549, 1, 6109},
- {"cvmx_rnm_serial_num" , CVMX_CSR_DB_TYPE_RSL, 64, 6550, 1, 6110},
- {"cvmx_sli_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6551, 24, 6111},
- {"cvmx_sli_ctl_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6552, 16, 6135},
- {"cvmx_sli_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6554, 3, 6151},
- {"cvmx_sli_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6555, 5, 6154},
- {"cvmx_sli_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6556, 3, 6159},
- {"cvmx_sli_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6557, 3, 6162},
- {"cvmx_sli_dma#_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6558, 2, 6165},
- {"cvmx_sli_dma#_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6560, 2, 6167},
- {"cvmx_sli_dma#_tim" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6562, 2, 6169},
- {"cvmx_sli_int_enb_ciu" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6564, 45, 6171},
- {"cvmx_sli_int_enb_port#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6565, 46, 6216},
- {"cvmx_sli_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6567, 46, 6262},
- {"cvmx_sli_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6568, 1, 6308},
- {"cvmx_sli_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6569, 1, 6309},
- {"cvmx_sli_last_win_rdata2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6570, 1, 6310},
- {"cvmx_sli_last_win_rdata3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6571, 1, 6311},
- {"cvmx_sli_mac_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6572, 13, 6312},
- {"cvmx_sli_mac_credit_cnt2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6573, 13, 6325},
- {"cvmx_sli_mac_number" , CVMX_CSR_DB_TYPE_PEXP, 64, 6574, 3, 6338},
- {"cvmx_sli_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6575, 3, 6341},
- {"cvmx_sli_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6576, 9, 6344},
- {"cvmx_sli_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6592, 1, 6353},
- {"cvmx_sli_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6593, 1, 6354},
- {"cvmx_sli_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6594, 1, 6355},
- {"cvmx_sli_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6595, 1, 6356},
- {"cvmx_sli_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6596, 1, 6357},
- {"cvmx_sli_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6597, 1, 6358},
- {"cvmx_sli_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6598, 1, 6359},
- {"cvmx_sli_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6599, 1, 6360},
- {"cvmx_sli_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6600, 3, 6361},
- {"cvmx_sli_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6601, 1, 6364},
- {"cvmx_sli_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6602, 1, 6365},
- {"cvmx_sli_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6603, 1, 6366},
- {"cvmx_sli_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6604, 1, 6367},
- {"cvmx_sli_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6605, 1, 6368},
- {"cvmx_sli_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6606, 1, 6369},
- {"cvmx_sli_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6607, 1, 6370},
- {"cvmx_sli_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6608, 1, 6371},
- {"cvmx_sli_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6609, 3, 6372},
- {"cvmx_sli_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6610, 2, 6375},
- {"cvmx_sli_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6611, 3, 6377},
- {"cvmx_sli_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6612, 3, 6380},
- {"cvmx_sli_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6613, 3, 6383},
- {"cvmx_sli_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6614, 3, 6386},
- {"cvmx_sli_pkt#_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6646, 2, 6389},
- {"cvmx_sli_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6678, 2, 6391},
- {"cvmx_sli_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6710, 2, 6393},
- {"cvmx_sli_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6742, 5, 6395},
- {"cvmx_sli_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6774, 21, 6400},
- {"cvmx_sli_pkt#_out_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6806, 3, 6421},
- {"cvmx_sli_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6838, 2, 6424},
- {"cvmx_sli_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6870, 2, 6426},
- {"cvmx_sli_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6902, 2, 6428},
- {"cvmx_sli_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6934, 2, 6430},
- {"cvmx_sli_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6935, 2, 6432},
- {"cvmx_sli_pkt_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6936, 3, 6434},
- {"cvmx_sli_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6937, 1, 6437},
- {"cvmx_sli_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6938, 2, 6438},
- {"cvmx_sli_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6939, 2, 6440},
- {"cvmx_sli_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6940, 2, 6442},
- {"cvmx_sli_pkt_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6941, 2, 6444},
- {"cvmx_sli_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6942, 2, 6446},
- {"cvmx_sli_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6974, 2, 6448},
- {"cvmx_sli_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6975, 1, 6450},
- {"cvmx_sli_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6976, 17, 6451},
- {"cvmx_sli_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6977, 2, 6468},
- {"cvmx_sli_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6978, 1, 6470},
- {"cvmx_sli_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6979, 2, 6471},
- {"cvmx_sli_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6980, 3, 6473},
- {"cvmx_sli_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6981, 2, 6476},
- {"cvmx_sli_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6982, 2, 6478},
- {"cvmx_sli_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6983, 2, 6480},
- {"cvmx_sli_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6984, 2, 6482},
- {"cvmx_sli_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6985, 1, 6484},
- {"cvmx_sli_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6986, 2, 6485},
- {"cvmx_sli_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6987, 1, 6487},
- {"cvmx_sli_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6988, 2, 6488},
- {"cvmx_sli_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6989, 2, 6490},
- {"cvmx_sli_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6990, 2, 6492},
- {"cvmx_sli_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6991, 2, 6494},
- {"cvmx_sli_s2m_port#_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6992, 4, 6496},
- {"cvmx_sli_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6994, 1, 6500},
- {"cvmx_sli_scratch_2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6995, 1, 6501},
- {"cvmx_sli_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6996, 4, 6502},
- {"cvmx_sli_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6997, 8, 6506},
- {"cvmx_sli_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 6998, 5, 6514},
- {"cvmx_sli_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 6999, 4, 6519},
- {"cvmx_sli_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 7000, 1, 6523},
- {"cvmx_sli_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 7001, 4, 6524},
- {"cvmx_sli_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 7002, 1, 6528},
- {"cvmx_sli_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 7003, 2, 6529},
- {"cvmx_sli_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 7004, 2, 6531},
- {"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 7005, 10, 6533},
- {"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7007, 6, 6543},
- {"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 7009, 2, 6549},
- {"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7011, 4, 6551},
- {"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7013, 4, 6555},
- {"cvmx_smi_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7015, 4, 6559},
- {"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 7016, 6, 6563},
- {"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 7017, 3, 6569},
- {"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 7018, 5, 6572},
- {"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 7019, 4, 6577},
- {"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 7020, 6, 6581},
- {"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 7021, 4, 6587},
- {"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 7022, 2, 6591},
- {"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 7023, 4, 6593},
- {"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 7024, 2, 6597},
- {"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 7025, 3, 6599},
- {"cvmx_tra#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7026, 2, 6602},
- {"cvmx_tra#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7027, 14, 6604},
- {"cvmx_tra#_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 7028, 3, 6618},
- {"cvmx_tra#_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 7029, 5, 6621},
- {"cvmx_tra#_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7030, 2, 6626},
- {"cvmx_tra#_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7031, 2, 6628},
- {"cvmx_tra#_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7032, 57, 6630},
- {"cvmx_tra#_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7033, 20, 6687},
- {"cvmx_tra#_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7034, 7, 6707},
- {"cvmx_tra#_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7035, 5, 6714},
- {"cvmx_tra#_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 7036, 1, 6719},
- {"cvmx_tra#_read_dat_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 7037, 2, 6720},
- {"cvmx_tra#_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7038, 2, 6722},
- {"cvmx_tra#_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7039, 2, 6724},
- {"cvmx_tra#_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7040, 57, 6726},
- {"cvmx_tra#_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7041, 20, 6783},
- {"cvmx_tra#_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7042, 7, 6803},
- {"cvmx_tra#_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 7043, 2, 6810},
- {"cvmx_tra#_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 7044, 2, 6812},
- {"cvmx_tra#_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 7045, 57, 6814},
- {"cvmx_tra#_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 7046, 20, 6871},
- {"cvmx_tra#_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 7047, 7, 6891},
- {"cvmx_uahc#_ehci_asynclistaddr", CVMX_CSR_DB_TYPE_NCB, 32, 7048, 2, 6898},
- {"cvmx_uahc#_ehci_configflag" , CVMX_CSR_DB_TYPE_NCB, 32, 7049, 2, 6900},
- {"cvmx_uahc#_ehci_ctrldssegment", CVMX_CSR_DB_TYPE_NCB, 32, 7050, 1, 6902},
- {"cvmx_uahc#_ehci_frindex" , CVMX_CSR_DB_TYPE_NCB, 32, 7051, 2, 6903},
- {"cvmx_uahc#_ehci_hccapbase" , CVMX_CSR_DB_TYPE_NCB, 32, 7052, 3, 6905},
- {"cvmx_uahc#_ehci_hccparams" , CVMX_CSR_DB_TYPE_NCB, 32, 7053, 7, 6908},
- {"cvmx_uahc#_ehci_hcsparams" , CVMX_CSR_DB_TYPE_NCB, 32, 7054, 10, 6915},
- {"cvmx_uahc#_ehci_insnreg00" , CVMX_CSR_DB_TYPE_NCB, 32, 7055, 3, 6925},
- {"cvmx_uahc#_ehci_insnreg03" , CVMX_CSR_DB_TYPE_NCB, 32, 7056, 5, 6928},
- {"cvmx_uahc#_ehci_insnreg04" , CVMX_CSR_DB_TYPE_NCB, 32, 7057, 7, 6933},
- {"cvmx_uahc#_ehci_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 7058, 2, 6940},
- {"cvmx_uahc#_ehci_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 7059, 1, 6942},
- {"cvmx_uahc#_ehci_periodiclistbase", CVMX_CSR_DB_TYPE_NCB, 32, 7060, 2, 6943},
- {"cvmx_uahc#_ehci_portsc#" , CVMX_CSR_DB_TYPE_NCB, 32, 7061, 19, 6945},
- {"cvmx_uahc#_ehci_usbcmd" , CVMX_CSR_DB_TYPE_NCB, 32, 7063, 13, 6964},
- {"cvmx_uahc#_ehci_usbintr" , CVMX_CSR_DB_TYPE_NCB, 32, 7064, 7, 6977},
- {"cvmx_uahc#_ehci_usbsts" , CVMX_CSR_DB_TYPE_NCB, 32, 7065, 12, 6984},
- {"cvmx_uahc#_ohci0_hcbulkcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7066, 2, 6996},
- {"cvmx_uahc#_ohci0_hcbulkheaded", CVMX_CSR_DB_TYPE_NCB, 32, 7067, 2, 6998},
- {"cvmx_uahc#_ohci0_hccommandstatus", CVMX_CSR_DB_TYPE_NCB, 32, 7068, 7, 7000},
- {"cvmx_uahc#_ohci0_hccontrol" , CVMX_CSR_DB_TYPE_NCB, 32, 7069, 10, 7007},
- {"cvmx_uahc#_ohci0_hccontrolcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7070, 2, 7017},
- {"cvmx_uahc#_ohci0_hccontrolheaded", CVMX_CSR_DB_TYPE_NCB, 32, 7071, 2, 7019},
- {"cvmx_uahc#_ohci0_hcdonehead" , CVMX_CSR_DB_TYPE_NCB, 32, 7072, 2, 7021},
- {"cvmx_uahc#_ohci0_hcfminterval", CVMX_CSR_DB_TYPE_NCB, 32, 7073, 4, 7023},
- {"cvmx_uahc#_ohci0_hcfmnumber" , CVMX_CSR_DB_TYPE_NCB, 32, 7074, 2, 7027},
- {"cvmx_uahc#_ohci0_hcfmremaining", CVMX_CSR_DB_TYPE_NCB, 32, 7075, 3, 7029},
- {"cvmx_uahc#_ohci0_hchcca" , CVMX_CSR_DB_TYPE_NCB, 32, 7076, 2, 7032},
- {"cvmx_uahc#_ohci0_hcinterruptdisable", CVMX_CSR_DB_TYPE_NCB, 32, 7077, 10, 7034},
- {"cvmx_uahc#_ohci0_hcinterruptenable", CVMX_CSR_DB_TYPE_NCB, 32, 7078, 10, 7044},
- {"cvmx_uahc#_ohci0_hcinterruptstatus", CVMX_CSR_DB_TYPE_NCB, 32, 7079, 10, 7054},
- {"cvmx_uahc#_ohci0_hclsthreshold", CVMX_CSR_DB_TYPE_NCB, 32, 7080, 2, 7064},
- {"cvmx_uahc#_ohci0_hcperiodcurrented", CVMX_CSR_DB_TYPE_NCB, 32, 7081, 2, 7066},
- {"cvmx_uahc#_ohci0_hcperiodicstart", CVMX_CSR_DB_TYPE_NCB, 32, 7082, 2, 7068},
- {"cvmx_uahc#_ohci0_hcrevision" , CVMX_CSR_DB_TYPE_NCB, 32, 7083, 2, 7070},
- {"cvmx_uahc#_ohci0_hcrhdescriptora", CVMX_CSR_DB_TYPE_NCB, 32, 7084, 8, 7072},
- {"cvmx_uahc#_ohci0_hcrhdescriptorb", CVMX_CSR_DB_TYPE_NCB, 32, 7085, 2, 7080},
- {"cvmx_uahc#_ohci0_hcrhportstatus#", CVMX_CSR_DB_TYPE_NCB, 32, 7086, 15, 7082},
- {"cvmx_uahc#_ohci0_hcrhstatus" , CVMX_CSR_DB_TYPE_NCB, 32, 7088, 8, 7097},
- {"cvmx_uahc#_ohci0_insnreg06" , CVMX_CSR_DB_TYPE_NCB, 32, 7089, 2, 7105},
- {"cvmx_uahc#_ohci0_insnreg07" , CVMX_CSR_DB_TYPE_NCB, 32, 7090, 1, 7107},
- {"cvmx_uctl#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7091, 7, 7108},
- {"cvmx_uctl#_clk_rst_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7092, 21, 7115},
- {"cvmx_uctl#_ehci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7093, 12, 7136},
- {"cvmx_uctl#_ehci_fla" , CVMX_CSR_DB_TYPE_RSL, 64, 7094, 2, 7148},
- {"cvmx_uctl#_erto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7095, 3, 7150},
- {"cvmx_uctl#_if_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 7096, 2, 7153},
- {"cvmx_uctl#_int_ena" , CVMX_CSR_DB_TYPE_RSL, 64, 7097, 9, 7155},
- {"cvmx_uctl#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 7098, 9, 7164},
- {"cvmx_uctl#_ohci_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7099, 11, 7173},
- {"cvmx_uctl#_orto_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 7100, 3, 7184},
- {"cvmx_uctl#_ppaf_wm" , CVMX_CSR_DB_TYPE_RSL, 64, 7101, 2, 7187},
- {"cvmx_uctl#_uphy_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 7102, 11, 7189},
- {"cvmx_uctl#_uphy_port#_ctl_status", CVMX_CSR_DB_TYPE_RSL, 64, 7103, 20, 7200},
- {NULL,0,0,0,0,0}
-};
-static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cnf71xx[] = {
- /* name , --------------address, ---------------type, bits, csr offset */
- {"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 0},
- {"CIU_BLOCK_INT" , 0x10700000007c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1},
- {"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 2},
- {"CIU_EN2_IO0_INT" , 0x107000000a600ull, CVMX_CSR_DB_TYPE_NCB, 64, 3},
- {"CIU_EN2_IO1_INT" , 0x107000000a608ull, CVMX_CSR_DB_TYPE_NCB, 64, 3},
- {"CIU_EN2_IO0_INT_W1C" , 0x107000000ce00ull, CVMX_CSR_DB_TYPE_NCB, 64, 4},
- {"CIU_EN2_IO1_INT_W1C" , 0x107000000ce08ull, CVMX_CSR_DB_TYPE_NCB, 64, 4},
- {"CIU_EN2_IO0_INT_W1S" , 0x107000000ae00ull, CVMX_CSR_DB_TYPE_NCB, 64, 5},
- {"CIU_EN2_IO1_INT_W1S" , 0x107000000ae08ull, CVMX_CSR_DB_TYPE_NCB, 64, 5},
- {"CIU_EN2_PP0_IP2" , 0x107000000a000ull, CVMX_CSR_DB_TYPE_NCB, 64, 6},
- {"CIU_EN2_PP1_IP2" , 0x107000000a008ull, CVMX_CSR_DB_TYPE_NCB, 64, 6},
- {"CIU_EN2_PP2_IP2" , 0x107000000a010ull, CVMX_CSR_DB_TYPE_NCB, 64, 6},
- {"CIU_EN2_PP3_IP2" , 0x107000000a018ull, CVMX_CSR_DB_TYPE_NCB, 64, 6},
- {"CIU_EN2_PP0_IP2_W1C" , 0x107000000c800ull, CVMX_CSR_DB_TYPE_NCB, 64, 7},
- {"CIU_EN2_PP1_IP2_W1C" , 0x107000000c808ull, CVMX_CSR_DB_TYPE_NCB, 64, 7},
- {"CIU_EN2_PP2_IP2_W1C" , 0x107000000c810ull, CVMX_CSR_DB_TYPE_NCB, 64, 7},
- {"CIU_EN2_PP3_IP2_W1C" , 0x107000000c818ull, CVMX_CSR_DB_TYPE_NCB, 64, 7},
- {"CIU_EN2_PP0_IP2_W1S" , 0x107000000a800ull, CVMX_CSR_DB_TYPE_NCB, 64, 8},
- {"CIU_EN2_PP1_IP2_W1S" , 0x107000000a808ull, CVMX_CSR_DB_TYPE_NCB, 64, 8},
- {"CIU_EN2_PP2_IP2_W1S" , 0x107000000a810ull, CVMX_CSR_DB_TYPE_NCB, 64, 8},
- {"CIU_EN2_PP3_IP2_W1S" , 0x107000000a818ull, CVMX_CSR_DB_TYPE_NCB, 64, 8},
- {"CIU_EN2_PP0_IP3" , 0x107000000a200ull, CVMX_CSR_DB_TYPE_NCB, 64, 9},
- {"CIU_EN2_PP1_IP3" , 0x107000000a208ull, CVMX_CSR_DB_TYPE_NCB, 64, 9},
- {"CIU_EN2_PP2_IP3" , 0x107000000a210ull, CVMX_CSR_DB_TYPE_NCB, 64, 9},
- {"CIU_EN2_PP3_IP3" , 0x107000000a218ull, CVMX_CSR_DB_TYPE_NCB, 64, 9},
- {"CIU_EN2_PP0_IP3_W1C" , 0x107000000ca00ull, CVMX_CSR_DB_TYPE_NCB, 64, 10},
- {"CIU_EN2_PP1_IP3_W1C" , 0x107000000ca08ull, CVMX_CSR_DB_TYPE_NCB, 64, 10},
- {"CIU_EN2_PP2_IP3_W1C" , 0x107000000ca10ull, CVMX_CSR_DB_TYPE_NCB, 64, 10},
- {"CIU_EN2_PP3_IP3_W1C" , 0x107000000ca18ull, CVMX_CSR_DB_TYPE_NCB, 64, 10},
- {"CIU_EN2_PP0_IP3_W1S" , 0x107000000aa00ull, CVMX_CSR_DB_TYPE_NCB, 64, 11},
- {"CIU_EN2_PP1_IP3_W1S" , 0x107000000aa08ull, CVMX_CSR_DB_TYPE_NCB, 64, 11},
- {"CIU_EN2_PP2_IP3_W1S" , 0x107000000aa10ull, CVMX_CSR_DB_TYPE_NCB, 64, 11},
- {"CIU_EN2_PP3_IP3_W1S" , 0x107000000aa18ull, CVMX_CSR_DB_TYPE_NCB, 64, 11},
- {"CIU_EN2_PP0_IP4" , 0x107000000a400ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
- {"CIU_EN2_PP1_IP4" , 0x107000000a408ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
- {"CIU_EN2_PP2_IP4" , 0x107000000a410ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
- {"CIU_EN2_PP3_IP4" , 0x107000000a418ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
- {"CIU_EN2_PP0_IP4_W1C" , 0x107000000cc00ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
- {"CIU_EN2_PP1_IP4_W1C" , 0x107000000cc08ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
- {"CIU_EN2_PP2_IP4_W1C" , 0x107000000cc10ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
- {"CIU_EN2_PP3_IP4_W1C" , 0x107000000cc18ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
- {"CIU_EN2_PP0_IP4_W1S" , 0x107000000ac00ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
- {"CIU_EN2_PP1_IP4_W1S" , 0x107000000ac08ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
- {"CIU_EN2_PP2_IP4_W1S" , 0x107000000ac10ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
- {"CIU_EN2_PP3_IP4_W1S" , 0x107000000ac18ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
- {"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
- {"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
- {"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT33_EN0" , 0x1070000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
- {"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT33_EN0_W1C" , 0x1070000002410ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
- {"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT33_EN0_W1S" , 0x1070000006410ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
- {"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT33_EN1" , 0x1070000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
- {"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT33_EN1_W1C" , 0x1070000002418ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
- {"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_INT33_EN1_W1S" , 0x1070000006418ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
- {"CIU_INT0_EN4_0" , 0x1070000000c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
- {"CIU_INT1_EN4_0" , 0x1070000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
- {"CIU_INT2_EN4_0" , 0x1070000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
- {"CIU_INT3_EN4_0" , 0x1070000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
- {"CIU_INT0_EN4_0_W1C" , 0x1070000002c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT1_EN4_0_W1C" , 0x1070000002c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT2_EN4_0_W1C" , 0x1070000002ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT3_EN4_0_W1C" , 0x1070000002cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
- {"CIU_INT0_EN4_0_W1S" , 0x1070000006c80ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT1_EN4_0_W1S" , 0x1070000006c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT2_EN4_0_W1S" , 0x1070000006ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT3_EN4_0_W1S" , 0x1070000006cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
- {"CIU_INT0_EN4_1" , 0x1070000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT1_EN4_1" , 0x1070000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT2_EN4_1" , 0x1070000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT3_EN4_1" , 0x1070000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
- {"CIU_INT0_EN4_1_W1C" , 0x1070000002c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT1_EN4_1_W1C" , 0x1070000002c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT2_EN4_1_W1C" , 0x1070000002ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT3_EN4_1_W1C" , 0x1070000002cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
- {"CIU_INT0_EN4_1_W1S" , 0x1070000006c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT1_EN4_1_W1S" , 0x1070000006c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT2_EN4_1_W1S" , 0x1070000006ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT3_EN4_1_W1S" , 0x1070000006cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
- {"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
- {"CIU_INT0_SUM4" , 0x1070000000c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT1_SUM4" , 0x1070000000c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT2_SUM4" , 0x1070000000c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT3_SUM4" , 0x1070000000c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
- {"CIU_INT33_SUM0" , 0x1070000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
- {"CIU_INT_DBG_SEL" , 0x10700000007d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
- {"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
- {"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
- {"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
- {"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
- {"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
- {"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
- {"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
- {"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
- {"CIU_QLM0" , 0x1070000000780ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
- {"CIU_QLM1" , 0x1070000000788ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
- {"CIU_QLM2" , 0x1070000000790ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
- {"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
- {"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
- {"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 46},
- {"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 47},
- {"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 48},
- {"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
- {"CIU_SUM1_IO0_INT" , 0x1070000008600ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_SUM1_IO1_INT" , 0x1070000008608ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
- {"CIU_SUM1_PP0_IP2" , 0x1070000008000ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
- {"CIU_SUM1_PP1_IP2" , 0x1070000008008ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
- {"CIU_SUM1_PP2_IP2" , 0x1070000008010ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
- {"CIU_SUM1_PP3_IP2" , 0x1070000008018ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
- {"CIU_SUM1_PP0_IP3" , 0x1070000008200ull, CVMX_CSR_DB_TYPE_NCB, 64, 52},
- {"CIU_SUM1_PP1_IP3" , 0x1070000008208ull, CVMX_CSR_DB_TYPE_NCB, 64, 52},
- {"CIU_SUM1_PP2_IP3" , 0x1070000008210ull, CVMX_CSR_DB_TYPE_NCB, 64, 52},
- {"CIU_SUM1_PP3_IP3" , 0x1070000008218ull, CVMX_CSR_DB_TYPE_NCB, 64, 52},
- {"CIU_SUM1_PP0_IP4" , 0x1070000008400ull, CVMX_CSR_DB_TYPE_NCB, 64, 53},
- {"CIU_SUM1_PP1_IP4" , 0x1070000008408ull, CVMX_CSR_DB_TYPE_NCB, 64, 53},
- {"CIU_SUM1_PP2_IP4" , 0x1070000008410ull, CVMX_CSR_DB_TYPE_NCB, 64, 53},
- {"CIU_SUM1_PP3_IP4" , 0x1070000008418ull, CVMX_CSR_DB_TYPE_NCB, 64, 53},
- {"CIU_SUM2_IO0_INT" , 0x1070000008e00ull, CVMX_CSR_DB_TYPE_NCB, 64, 54},
- {"CIU_SUM2_IO1_INT" , 0x1070000008e08ull, CVMX_CSR_DB_TYPE_NCB, 64, 54},
- {"CIU_SUM2_PP0_IP2" , 0x1070000008800ull, CVMX_CSR_DB_TYPE_NCB, 64, 55},
- {"CIU_SUM2_PP1_IP2" , 0x1070000008808ull, CVMX_CSR_DB_TYPE_NCB, 64, 55},
- {"CIU_SUM2_PP2_IP2" , 0x1070000008810ull, CVMX_CSR_DB_TYPE_NCB, 64, 55},
- {"CIU_SUM2_PP3_IP2" , 0x1070000008818ull, CVMX_CSR_DB_TYPE_NCB, 64, 55},
- {"CIU_SUM2_PP0_IP3" , 0x1070000008a00ull, CVMX_CSR_DB_TYPE_NCB, 64, 56},
- {"CIU_SUM2_PP1_IP3" , 0x1070000008a08ull, CVMX_CSR_DB_TYPE_NCB, 64, 56},
- {"CIU_SUM2_PP2_IP3" , 0x1070000008a10ull, CVMX_CSR_DB_TYPE_NCB, 64, 56},
- {"CIU_SUM2_PP3_IP3" , 0x1070000008a18ull, CVMX_CSR_DB_TYPE_NCB, 64, 56},
- {"CIU_SUM2_PP0_IP4" , 0x1070000008c00ull, CVMX_CSR_DB_TYPE_NCB, 64, 57},
- {"CIU_SUM2_PP1_IP4" , 0x1070000008c08ull, CVMX_CSR_DB_TYPE_NCB, 64, 57},
- {"CIU_SUM2_PP2_IP4" , 0x1070000008c10ull, CVMX_CSR_DB_TYPE_NCB, 64, 57},
- {"CIU_SUM2_PP3_IP4" , 0x1070000008c18ull, CVMX_CSR_DB_TYPE_NCB, 64, 57},
- {"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 58},
- {"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 58},
- {"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 58},
- {"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 58},
- {"CIU_TIM4" , 0x10700000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 58},
- {"CIU_TIM5" , 0x10700000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 58},
- {"CIU_TIM6" , 0x10700000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 58},
- {"CIU_TIM7" , 0x10700000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 58},
- {"CIU_TIM8" , 0x10700000004c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 58},
- {"CIU_TIM9" , 0x10700000004c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 58},
- {"CIU_TIM_MULTI_CAST" , 0x107000000c200ull, CVMX_CSR_DB_TYPE_NCB, 64, 59},
- {"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 60},
- {"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 60},
- {"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 60},
- {"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 60},
- {"DPI_BIST_STATUS" , 0x1df0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 61},
- {"DPI_CTL" , 0x1df0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 62},
- {"DPI_DMA0_COUNTS" , 0x1df0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 63},
- {"DPI_DMA1_COUNTS" , 0x1df0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 63},
- {"DPI_DMA2_COUNTS" , 0x1df0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 63},
- {"DPI_DMA3_COUNTS" , 0x1df0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 63},
- {"DPI_DMA4_COUNTS" , 0x1df0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 63},
- {"DPI_DMA5_COUNTS" , 0x1df0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 63},
- {"DPI_DMA6_COUNTS" , 0x1df0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 63},
- {"DPI_DMA7_COUNTS" , 0x1df0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 63},
- {"DPI_DMA0_DBELL" , 0x1df0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 64},
- {"DPI_DMA1_DBELL" , 0x1df0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 64},
- {"DPI_DMA2_DBELL" , 0x1df0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 64},
- {"DPI_DMA3_DBELL" , 0x1df0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 64},
- {"DPI_DMA4_DBELL" , 0x1df0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 64},
- {"DPI_DMA5_DBELL" , 0x1df0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 64},
- {"DPI_DMA6_DBELL" , 0x1df0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 64},
- {"DPI_DMA7_DBELL" , 0x1df0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 64},
- {"DPI_DMA0_ERR_RSP_STATUS" , 0x1df0000000a80ull, CVMX_CSR_DB_TYPE_NCB, 64, 65},
- {"DPI_DMA1_ERR_RSP_STATUS" , 0x1df0000000a88ull, CVMX_CSR_DB_TYPE_NCB, 64, 65},
- {"DPI_DMA2_ERR_RSP_STATUS" , 0x1df0000000a90ull, CVMX_CSR_DB_TYPE_NCB, 64, 65},
- {"DPI_DMA3_ERR_RSP_STATUS" , 0x1df0000000a98ull, CVMX_CSR_DB_TYPE_NCB, 64, 65},
- {"DPI_DMA4_ERR_RSP_STATUS" , 0x1df0000000aa0ull, CVMX_CSR_DB_TYPE_NCB, 64, 65},
- {"DPI_DMA5_ERR_RSP_STATUS" , 0x1df0000000aa8ull, CVMX_CSR_DB_TYPE_NCB, 64, 65},
- {"DPI_DMA6_ERR_RSP_STATUS" , 0x1df0000000ab0ull, CVMX_CSR_DB_TYPE_NCB, 64, 65},
- {"DPI_DMA7_ERR_RSP_STATUS" , 0x1df0000000ab8ull, CVMX_CSR_DB_TYPE_NCB, 64, 65},
- {"DPI_DMA0_IBUFF_SADDR" , 0x1df0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 66},
- {"DPI_DMA1_IBUFF_SADDR" , 0x1df0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 66},
- {"DPI_DMA2_IBUFF_SADDR" , 0x1df0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 66},
- {"DPI_DMA3_IBUFF_SADDR" , 0x1df0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 66},
- {"DPI_DMA4_IBUFF_SADDR" , 0x1df00000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 66},
- {"DPI_DMA5_IBUFF_SADDR" , 0x1df00000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 66},
- {"DPI_DMA6_IBUFF_SADDR" , 0x1df00000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 66},
- {"DPI_DMA7_IBUFF_SADDR" , 0x1df00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 66},
- {"DPI_DMA0_IFLIGHT" , 0x1df0000000a00ull, CVMX_CSR_DB_TYPE_NCB, 64, 67},
- {"DPI_DMA1_IFLIGHT" , 0x1df0000000a08ull, CVMX_CSR_DB_TYPE_NCB, 64, 67},
- {"DPI_DMA2_IFLIGHT" , 0x1df0000000a10ull, CVMX_CSR_DB_TYPE_NCB, 64, 67},
- {"DPI_DMA3_IFLIGHT" , 0x1df0000000a18ull, CVMX_CSR_DB_TYPE_NCB, 64, 67},
- {"DPI_DMA4_IFLIGHT" , 0x1df0000000a20ull, CVMX_CSR_DB_TYPE_NCB, 64, 67},
- {"DPI_DMA5_IFLIGHT" , 0x1df0000000a28ull, CVMX_CSR_DB_TYPE_NCB, 64, 67},
- {"DPI_DMA6_IFLIGHT" , 0x1df0000000a30ull, CVMX_CSR_DB_TYPE_NCB, 64, 67},
- {"DPI_DMA7_IFLIGHT" , 0x1df0000000a38ull, CVMX_CSR_DB_TYPE_NCB, 64, 67},
- {"DPI_DMA0_NADDR" , 0x1df0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 68},
- {"DPI_DMA1_NADDR" , 0x1df0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 68},
- {"DPI_DMA2_NADDR" , 0x1df0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 68},
- {"DPI_DMA3_NADDR" , 0x1df0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 68},
- {"DPI_DMA4_NADDR" , 0x1df00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 68},
- {"DPI_DMA5_NADDR" , 0x1df00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 68},
- {"DPI_DMA6_NADDR" , 0x1df00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 68},
- {"DPI_DMA7_NADDR" , 0x1df00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 68},
- {"DPI_DMA0_REQBNK0" , 0x1df0000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 69},
- {"DPI_DMA1_REQBNK0" , 0x1df0000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 69},
- {"DPI_DMA2_REQBNK0" , 0x1df0000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 69},
- {"DPI_DMA3_REQBNK0" , 0x1df0000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 69},
- {"DPI_DMA4_REQBNK0" , 0x1df0000000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 69},
- {"DPI_DMA5_REQBNK0" , 0x1df0000000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 69},
- {"DPI_DMA6_REQBNK0" , 0x1df0000000430ull, CVMX_CSR_DB_TYPE_NCB, 64, 69},
- {"DPI_DMA7_REQBNK0" , 0x1df0000000438ull, CVMX_CSR_DB_TYPE_NCB, 64, 69},
- {"DPI_DMA0_REQBNK1" , 0x1df0000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 70},
- {"DPI_DMA1_REQBNK1" , 0x1df0000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 70},
- {"DPI_DMA2_REQBNK1" , 0x1df0000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 70},
- {"DPI_DMA3_REQBNK1" , 0x1df0000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 70},
- {"DPI_DMA4_REQBNK1" , 0x1df00000004a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 70},
- {"DPI_DMA5_REQBNK1" , 0x1df00000004a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 70},
- {"DPI_DMA6_REQBNK1" , 0x1df00000004b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 70},
- {"DPI_DMA7_REQBNK1" , 0x1df00000004b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 70},
- {"DPI_DMA_CONTROL" , 0x1df0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 71},
- {"DPI_DMA_ENG0_EN" , 0x1df0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"DPI_DMA_ENG1_EN" , 0x1df0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"DPI_DMA_ENG2_EN" , 0x1df0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"DPI_DMA_ENG3_EN" , 0x1df0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"DPI_DMA_ENG4_EN" , 0x1df00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"DPI_DMA_ENG5_EN" , 0x1df00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
- {"DPI_DMA_PP0_CNT" , 0x1df0000000b00ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"DPI_DMA_PP1_CNT" , 0x1df0000000b08ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"DPI_DMA_PP2_CNT" , 0x1df0000000b10ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"DPI_DMA_PP3_CNT" , 0x1df0000000b18ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
- {"DPI_ENG0_BUF" , 0x1df0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"DPI_ENG1_BUF" , 0x1df0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"DPI_ENG2_BUF" , 0x1df0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"DPI_ENG3_BUF" , 0x1df0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"DPI_ENG4_BUF" , 0x1df00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"DPI_ENG5_BUF" , 0x1df00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
- {"DPI_INFO_REG" , 0x1df0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
- {"DPI_INT_EN" , 0x1df0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
- {"DPI_INT_REG" , 0x1df0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
- {"DPI_NCB0_CFG" , 0x1df0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
- {"DPI_PINT_INFO" , 0x1df0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
- {"DPI_PKT_ERR_RSP" , 0x1df0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
- {"DPI_REQ_ERR_RSP" , 0x1df0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
- {"DPI_REQ_ERR_RSP_EN" , 0x1df0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
- {"DPI_REQ_ERR_RST" , 0x1df0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
- {"DPI_REQ_ERR_RST_EN" , 0x1df0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
- {"DPI_REQ_ERR_SKIP_COMP" , 0x1df0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
- {"DPI_REQ_GBL_EN" , 0x1df0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
- {"DPI_SLI_PRT0_CFG" , 0x1df0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"DPI_SLI_PRT1_CFG" , 0x1df0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
- {"DPI_SLI_PRT0_ERR" , 0x1df0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"DPI_SLI_PRT1_ERR" , 0x1df0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
- {"DPI_SLI_PRT0_ERR_INFO" , 0x1df0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"DPI_SLI_PRT1_ERR_INFO" , 0x1df0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
- {"ENDOR_ADMA_AUTO_CLK_GATE" , 0x10f0000844004ull, CVMX_CSR_DB_TYPE_NCB, 32, 90},
- {"ENDOR_ADMA_AXI_RSPCODE" , 0x10f0000844050ull, CVMX_CSR_DB_TYPE_NCB, 32, 91},
- {"ENDOR_ADMA_AXI_SIGNAL" , 0x10f0000844084ull, CVMX_CSR_DB_TYPE_NCB, 32, 92},
- {"ENDOR_ADMA_AXIERR_INTR" , 0x10f0000844044ull, CVMX_CSR_DB_TYPE_NCB, 32, 93},
- {"ENDOR_ADMA_DMA0_ADDR_HI" , 0x10f000084410cull, CVMX_CSR_DB_TYPE_NCB, 32, 94},
- {"ENDOR_ADMA_DMA1_ADDR_HI" , 0x10f000084411cull, CVMX_CSR_DB_TYPE_NCB, 32, 94},
- {"ENDOR_ADMA_DMA2_ADDR_HI" , 0x10f000084412cull, CVMX_CSR_DB_TYPE_NCB, 32, 94},
- {"ENDOR_ADMA_DMA3_ADDR_HI" , 0x10f000084413cull, CVMX_CSR_DB_TYPE_NCB, 32, 94},
- {"ENDOR_ADMA_DMA4_ADDR_HI" , 0x10f000084414cull, CVMX_CSR_DB_TYPE_NCB, 32, 94},
- {"ENDOR_ADMA_DMA5_ADDR_HI" , 0x10f000084415cull, CVMX_CSR_DB_TYPE_NCB, 32, 94},
- {"ENDOR_ADMA_DMA6_ADDR_HI" , 0x10f000084416cull, CVMX_CSR_DB_TYPE_NCB, 32, 94},
- {"ENDOR_ADMA_DMA7_ADDR_HI" , 0x10f000084417cull, CVMX_CSR_DB_TYPE_NCB, 32, 94},
- {"ENDOR_ADMA_DMA0_ADDR_LO" , 0x10f0000844108ull, CVMX_CSR_DB_TYPE_NCB, 32, 95},
- {"ENDOR_ADMA_DMA1_ADDR_LO" , 0x10f0000844118ull, CVMX_CSR_DB_TYPE_NCB, 32, 95},
- {"ENDOR_ADMA_DMA2_ADDR_LO" , 0x10f0000844128ull, CVMX_CSR_DB_TYPE_NCB, 32, 95},
- {"ENDOR_ADMA_DMA3_ADDR_LO" , 0x10f0000844138ull, CVMX_CSR_DB_TYPE_NCB, 32, 95},
- {"ENDOR_ADMA_DMA4_ADDR_LO" , 0x10f0000844148ull, CVMX_CSR_DB_TYPE_NCB, 32, 95},
- {"ENDOR_ADMA_DMA5_ADDR_LO" , 0x10f0000844158ull, CVMX_CSR_DB_TYPE_NCB, 32, 95},
- {"ENDOR_ADMA_DMA6_ADDR_LO" , 0x10f0000844168ull, CVMX_CSR_DB_TYPE_NCB, 32, 95},
- {"ENDOR_ADMA_DMA7_ADDR_LO" , 0x10f0000844178ull, CVMX_CSR_DB_TYPE_NCB, 32, 95},
- {"ENDOR_ADMA_DMA0_CFG" , 0x10f0000844100ull, CVMX_CSR_DB_TYPE_NCB, 32, 96},
- {"ENDOR_ADMA_DMA1_CFG" , 0x10f0000844110ull, CVMX_CSR_DB_TYPE_NCB, 32, 96},
- {"ENDOR_ADMA_DMA2_CFG" , 0x10f0000844120ull, CVMX_CSR_DB_TYPE_NCB, 32, 96},
- {"ENDOR_ADMA_DMA3_CFG" , 0x10f0000844130ull, CVMX_CSR_DB_TYPE_NCB, 32, 96},
- {"ENDOR_ADMA_DMA4_CFG" , 0x10f0000844140ull, CVMX_CSR_DB_TYPE_NCB, 32, 96},
- {"ENDOR_ADMA_DMA5_CFG" , 0x10f0000844150ull, CVMX_CSR_DB_TYPE_NCB, 32, 96},
- {"ENDOR_ADMA_DMA6_CFG" , 0x10f0000844160ull, CVMX_CSR_DB_TYPE_NCB, 32, 96},
- {"ENDOR_ADMA_DMA7_CFG" , 0x10f0000844170ull, CVMX_CSR_DB_TYPE_NCB, 32, 96},
- {"ENDOR_ADMA_DMA0_SIZE" , 0x10f0000844104ull, CVMX_CSR_DB_TYPE_NCB, 32, 97},
- {"ENDOR_ADMA_DMA1_SIZE" , 0x10f0000844114ull, CVMX_CSR_DB_TYPE_NCB, 32, 97},
- {"ENDOR_ADMA_DMA2_SIZE" , 0x10f0000844124ull, CVMX_CSR_DB_TYPE_NCB, 32, 97},
- {"ENDOR_ADMA_DMA3_SIZE" , 0x10f0000844134ull, CVMX_CSR_DB_TYPE_NCB, 32, 97},
- {"ENDOR_ADMA_DMA4_SIZE" , 0x10f0000844144ull, CVMX_CSR_DB_TYPE_NCB, 32, 97},
- {"ENDOR_ADMA_DMA5_SIZE" , 0x10f0000844154ull, CVMX_CSR_DB_TYPE_NCB, 32, 97},
- {"ENDOR_ADMA_DMA6_SIZE" , 0x10f0000844164ull, CVMX_CSR_DB_TYPE_NCB, 32, 97},
- {"ENDOR_ADMA_DMA7_SIZE" , 0x10f0000844174ull, CVMX_CSR_DB_TYPE_NCB, 32, 97},
- {"ENDOR_ADMA_DMA_PRIORITY" , 0x10f0000844080ull, CVMX_CSR_DB_TYPE_NCB, 32, 98},
- {"ENDOR_ADMA_DMA_RESET" , 0x10f0000844008ull, CVMX_CSR_DB_TYPE_NCB, 32, 99},
- {"ENDOR_ADMA_DMADONE_INTR" , 0x10f0000844040ull, CVMX_CSR_DB_TYPE_NCB, 32, 100},
- {"ENDOR_ADMA_INTR_DIS" , 0x10f000084404cull, CVMX_CSR_DB_TYPE_NCB, 32, 101},
- {"ENDOR_ADMA_INTR_ENB" , 0x10f0000844048ull, CVMX_CSR_DB_TYPE_NCB, 32, 102},
- {"ENDOR_ADMA_MODULE_STATUS" , 0x10f0000844000ull, CVMX_CSR_DB_TYPE_NCB, 32, 103},
- {"ENDOR_INTC_CNTL_HI0" , 0x10f00008201e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 104},
- {"ENDOR_INTC_CNTL_HI1" , 0x10f00008201ecull, CVMX_CSR_DB_TYPE_NCB, 32, 104},
- {"ENDOR_INTC_CNTL_LO0" , 0x10f00008201e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 105},
- {"ENDOR_INTC_CNTL_LO1" , 0x10f00008201e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 105},
- {"ENDOR_INTC_INDEX_HI0" , 0x10f00008201a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 106},
- {"ENDOR_INTC_INDEX_HI1" , 0x10f00008201acull, CVMX_CSR_DB_TYPE_NCB, 32, 106},
- {"ENDOR_INTC_INDEX_LO0" , 0x10f00008201a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 107},
- {"ENDOR_INTC_INDEX_LO1" , 0x10f00008201a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 107},
- {"ENDOR_INTC_MISC_IDX_HI0" , 0x10f0000820134ull, CVMX_CSR_DB_TYPE_NCB, 32, 108},
- {"ENDOR_INTC_MISC_IDX_HI1" , 0x10f0000820174ull, CVMX_CSR_DB_TYPE_NCB, 32, 108},
- {"ENDOR_INTC_MISC_IDX_LO0" , 0x10f0000820114ull, CVMX_CSR_DB_TYPE_NCB, 32, 109},
- {"ENDOR_INTC_MISC_IDX_LO1" , 0x10f0000820154ull, CVMX_CSR_DB_TYPE_NCB, 32, 109},
- {"ENDOR_INTC_MISC_MASK_HI0" , 0x10f0000820034ull, CVMX_CSR_DB_TYPE_NCB, 32, 110},
- {"ENDOR_INTC_MISC_MASK_HI1" , 0x10f0000820074ull, CVMX_CSR_DB_TYPE_NCB, 32, 110},
- {"ENDOR_INTC_MISC_MASK_LO0" , 0x10f0000820014ull, CVMX_CSR_DB_TYPE_NCB, 32, 111},
- {"ENDOR_INTC_MISC_MASK_LO1" , 0x10f0000820054ull, CVMX_CSR_DB_TYPE_NCB, 32, 111},
- {"ENDOR_INTC_MISC_RINT" , 0x10f0000820194ull, CVMX_CSR_DB_TYPE_NCB, 32, 112},
- {"ENDOR_INTC_MISC_STATUS_HI0" , 0x10f00008200b4ull, CVMX_CSR_DB_TYPE_NCB, 32, 113},
- {"ENDOR_INTC_MISC_STATUS_HI1" , 0x10f00008200f4ull, CVMX_CSR_DB_TYPE_NCB, 32, 113},
- {"ENDOR_INTC_MISC_STATUS_LO0" , 0x10f0000820094ull, CVMX_CSR_DB_TYPE_NCB, 32, 114},
- {"ENDOR_INTC_MISC_STATUS_LO1" , 0x10f00008200d4ull, CVMX_CSR_DB_TYPE_NCB, 32, 114},
- {"ENDOR_INTC_RD_IDX_HI0" , 0x10f0000820124ull, CVMX_CSR_DB_TYPE_NCB, 32, 115},
- {"ENDOR_INTC_RD_IDX_HI1" , 0x10f0000820164ull, CVMX_CSR_DB_TYPE_NCB, 32, 115},
- {"ENDOR_INTC_RD_IDX_LO0" , 0x10f0000820104ull, CVMX_CSR_DB_TYPE_NCB, 32, 116},
- {"ENDOR_INTC_RD_IDX_LO1" , 0x10f0000820144ull, CVMX_CSR_DB_TYPE_NCB, 32, 116},
- {"ENDOR_INTC_RD_MASK_HI0" , 0x10f0000820024ull, CVMX_CSR_DB_TYPE_NCB, 32, 117},
- {"ENDOR_INTC_RD_MASK_HI1" , 0x10f0000820064ull, CVMX_CSR_DB_TYPE_NCB, 32, 117},
- {"ENDOR_INTC_RD_MASK_LO0" , 0x10f0000820004ull, CVMX_CSR_DB_TYPE_NCB, 32, 118},
- {"ENDOR_INTC_RD_MASK_LO1" , 0x10f0000820044ull, CVMX_CSR_DB_TYPE_NCB, 32, 118},
- {"ENDOR_INTC_RD_RINT" , 0x10f0000820184ull, CVMX_CSR_DB_TYPE_NCB, 32, 119},
- {"ENDOR_INTC_RD_STATUS_HI0" , 0x10f00008200a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 120},
- {"ENDOR_INTC_RD_STATUS_HI1" , 0x10f00008200e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 120},
- {"ENDOR_INTC_RD_STATUS_LO0" , 0x10f0000820084ull, CVMX_CSR_DB_TYPE_NCB, 32, 121},
- {"ENDOR_INTC_RD_STATUS_LO1" , 0x10f00008200c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 121},
- {"ENDOR_INTC_RDQ_IDX_HI0" , 0x10f000082012cull, CVMX_CSR_DB_TYPE_NCB, 32, 122},
- {"ENDOR_INTC_RDQ_IDX_HI1" , 0x10f000082016cull, CVMX_CSR_DB_TYPE_NCB, 32, 122},
- {"ENDOR_INTC_RDQ_IDX_LO0" , 0x10f000082010cull, CVMX_CSR_DB_TYPE_NCB, 32, 123},
- {"ENDOR_INTC_RDQ_IDX_LO1" , 0x10f000082014cull, CVMX_CSR_DB_TYPE_NCB, 32, 123},
- {"ENDOR_INTC_RDQ_MASK_HI0" , 0x10f000082002cull, CVMX_CSR_DB_TYPE_NCB, 32, 124},
- {"ENDOR_INTC_RDQ_MASK_HI1" , 0x10f000082006cull, CVMX_CSR_DB_TYPE_NCB, 32, 124},
- {"ENDOR_INTC_RDQ_MASK_LO0" , 0x10f000082000cull, CVMX_CSR_DB_TYPE_NCB, 32, 125},
- {"ENDOR_INTC_RDQ_MASK_LO1" , 0x10f000082004cull, CVMX_CSR_DB_TYPE_NCB, 32, 125},
- {"ENDOR_INTC_RDQ_RINT" , 0x10f000082018cull, CVMX_CSR_DB_TYPE_NCB, 32, 126},
- {"ENDOR_INTC_RDQ_STATUS_HI0" , 0x10f00008200acull, CVMX_CSR_DB_TYPE_NCB, 32, 127},
- {"ENDOR_INTC_RDQ_STATUS_HI1" , 0x10f00008200ecull, CVMX_CSR_DB_TYPE_NCB, 32, 127},
- {"ENDOR_INTC_RDQ_STATUS_LO0" , 0x10f000082008cull, CVMX_CSR_DB_TYPE_NCB, 32, 128},
- {"ENDOR_INTC_RDQ_STATUS_LO1" , 0x10f00008200ccull, CVMX_CSR_DB_TYPE_NCB, 32, 128},
- {"ENDOR_INTC_STAT_HI0" , 0x10f00008201c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 129},
- {"ENDOR_INTC_STAT_HI1" , 0x10f00008201ccull, CVMX_CSR_DB_TYPE_NCB, 32, 129},
- {"ENDOR_INTC_STAT_LO0" , 0x10f00008201c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 130},
- {"ENDOR_INTC_STAT_LO1" , 0x10f00008201c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 130},
- {"ENDOR_INTC_SW_IDX_HI0" , 0x10f0000820130ull, CVMX_CSR_DB_TYPE_NCB, 32, 131},
- {"ENDOR_INTC_SW_IDX_HI1" , 0x10f0000820170ull, CVMX_CSR_DB_TYPE_NCB, 32, 131},
- {"ENDOR_INTC_SW_IDX_LO0" , 0x10f0000820110ull, CVMX_CSR_DB_TYPE_NCB, 32, 132},
- {"ENDOR_INTC_SW_IDX_LO1" , 0x10f0000820150ull, CVMX_CSR_DB_TYPE_NCB, 32, 132},
- {"ENDOR_INTC_SW_MASK_HI0" , 0x10f0000820030ull, CVMX_CSR_DB_TYPE_NCB, 32, 133},
- {"ENDOR_INTC_SW_MASK_HI1" , 0x10f0000820070ull, CVMX_CSR_DB_TYPE_NCB, 32, 133},
- {"ENDOR_INTC_SW_MASK_LO0" , 0x10f0000820010ull, CVMX_CSR_DB_TYPE_NCB, 32, 134},
- {"ENDOR_INTC_SW_MASK_LO1" , 0x10f0000820050ull, CVMX_CSR_DB_TYPE_NCB, 32, 134},
- {"ENDOR_INTC_SW_RINT" , 0x10f0000820190ull, CVMX_CSR_DB_TYPE_NCB, 32, 135},
- {"ENDOR_INTC_SW_STATUS_HI0" , 0x10f00008200b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 136},
- {"ENDOR_INTC_SW_STATUS_HI1" , 0x10f00008200f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 136},
- {"ENDOR_INTC_SW_STATUS_LO0" , 0x10f0000820090ull, CVMX_CSR_DB_TYPE_NCB, 32, 137},
- {"ENDOR_INTC_SW_STATUS_LO1" , 0x10f00008200d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 137},
- {"ENDOR_INTC_SWCLR" , 0x10f0000820204ull, CVMX_CSR_DB_TYPE_NCB, 32, 138},
- {"ENDOR_INTC_SWSET" , 0x10f0000820200ull, CVMX_CSR_DB_TYPE_NCB, 32, 139},
- {"ENDOR_INTC_WR_IDX_HI0" , 0x10f0000820120ull, CVMX_CSR_DB_TYPE_NCB, 32, 140},
- {"ENDOR_INTC_WR_IDX_HI1" , 0x10f0000820160ull, CVMX_CSR_DB_TYPE_NCB, 32, 140},
- {"ENDOR_INTC_WR_IDX_LO0" , 0x10f0000820100ull, CVMX_CSR_DB_TYPE_NCB, 32, 141},
- {"ENDOR_INTC_WR_IDX_LO1" , 0x10f0000820140ull, CVMX_CSR_DB_TYPE_NCB, 32, 141},
- {"ENDOR_INTC_WR_MASK_HI0" , 0x10f0000820020ull, CVMX_CSR_DB_TYPE_NCB, 32, 142},
- {"ENDOR_INTC_WR_MASK_HI1" , 0x10f0000820060ull, CVMX_CSR_DB_TYPE_NCB, 32, 142},
- {"ENDOR_INTC_WR_MASK_LO0" , 0x10f0000820000ull, CVMX_CSR_DB_TYPE_NCB, 32, 143},
- {"ENDOR_INTC_WR_MASK_LO1" , 0x10f0000820040ull, CVMX_CSR_DB_TYPE_NCB, 32, 143},
- {"ENDOR_INTC_WR_RINT" , 0x10f0000820180ull, CVMX_CSR_DB_TYPE_NCB, 32, 144},
- {"ENDOR_INTC_WR_STATUS_HI0" , 0x10f00008200a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 145},
- {"ENDOR_INTC_WR_STATUS_HI1" , 0x10f00008200e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 145},
- {"ENDOR_INTC_WR_STATUS_LO0" , 0x10f0000820080ull, CVMX_CSR_DB_TYPE_NCB, 32, 146},
- {"ENDOR_INTC_WR_STATUS_LO1" , 0x10f00008200c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 146},
- {"ENDOR_INTC_WRQ_IDX_HI0" , 0x10f0000820128ull, CVMX_CSR_DB_TYPE_NCB, 32, 147},
- {"ENDOR_INTC_WRQ_IDX_HI1" , 0x10f0000820168ull, CVMX_CSR_DB_TYPE_NCB, 32, 147},
- {"ENDOR_INTC_WRQ_IDX_LO0" , 0x10f0000820108ull, CVMX_CSR_DB_TYPE_NCB, 32, 148},
- {"ENDOR_INTC_WRQ_IDX_LO1" , 0x10f0000820148ull, CVMX_CSR_DB_TYPE_NCB, 32, 148},
- {"ENDOR_INTC_WRQ_MASK_HI0" , 0x10f0000820028ull, CVMX_CSR_DB_TYPE_NCB, 32, 149},
- {"ENDOR_INTC_WRQ_MASK_HI1" , 0x10f0000820068ull, CVMX_CSR_DB_TYPE_NCB, 32, 149},
- {"ENDOR_INTC_WRQ_MASK_LO0" , 0x10f0000820008ull, CVMX_CSR_DB_TYPE_NCB, 32, 150},
- {"ENDOR_INTC_WRQ_MASK_LO1" , 0x10f0000820048ull, CVMX_CSR_DB_TYPE_NCB, 32, 150},
- {"ENDOR_INTC_WRQ_RINT" , 0x10f0000820188ull, CVMX_CSR_DB_TYPE_NCB, 32, 151},
- {"ENDOR_INTC_WRQ_STATUS_HI0" , 0x10f00008200a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 152},
- {"ENDOR_INTC_WRQ_STATUS_HI1" , 0x10f00008200e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 152},
- {"ENDOR_INTC_WRQ_STATUS_LO0" , 0x10f0000820088ull, CVMX_CSR_DB_TYPE_NCB, 32, 153},
- {"ENDOR_INTC_WRQ_STATUS_LO1" , 0x10f00008200c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 153},
- {"ENDOR_OFS_HMM_CBUF_END_ADDR0", 0x10f0000832054ull, CVMX_CSR_DB_TYPE_NCB, 32, 154},
- {"ENDOR_OFS_HMM_CBUF_END_ADDR1", 0x10f000083205cull, CVMX_CSR_DB_TYPE_NCB, 32, 155},
- {"ENDOR_OFS_HMM_CBUF_END_ADDR2", 0x10f0000832064ull, CVMX_CSR_DB_TYPE_NCB, 32, 156},
- {"ENDOR_OFS_HMM_CBUF_END_ADDR3", 0x10f000083206cull, CVMX_CSR_DB_TYPE_NCB, 32, 157},
- {"ENDOR_OFS_HMM_CBUF_START_ADDR0", 0x10f0000832050ull, CVMX_CSR_DB_TYPE_NCB, 32, 158},
- {"ENDOR_OFS_HMM_CBUF_START_ADDR1", 0x10f0000832058ull, CVMX_CSR_DB_TYPE_NCB, 32, 159},
- {"ENDOR_OFS_HMM_CBUF_START_ADDR2", 0x10f0000832060ull, CVMX_CSR_DB_TYPE_NCB, 32, 160},
- {"ENDOR_OFS_HMM_CBUF_START_ADDR3", 0x10f0000832068ull, CVMX_CSR_DB_TYPE_NCB, 32, 161},
- {"ENDOR_OFS_HMM_INTR_CLEAR" , 0x10f0000832018ull, CVMX_CSR_DB_TYPE_NCB, 32, 162},
- {"ENDOR_OFS_HMM_INTR_ENB" , 0x10f000083201cull, CVMX_CSR_DB_TYPE_NCB, 32, 163},
- {"ENDOR_OFS_HMM_INTR_RSTATUS" , 0x10f0000832014ull, CVMX_CSR_DB_TYPE_NCB, 32, 164},
- {"ENDOR_OFS_HMM_INTR_STATUS" , 0x10f0000832010ull, CVMX_CSR_DB_TYPE_NCB, 32, 165},
- {"ENDOR_OFS_HMM_INTR_TEST" , 0x10f0000832020ull, CVMX_CSR_DB_TYPE_NCB, 32, 166},
- {"ENDOR_OFS_HMM_MODE" , 0x10f0000832004ull, CVMX_CSR_DB_TYPE_NCB, 32, 167},
- {"ENDOR_OFS_HMM_START_ADDR0" , 0x10f0000832030ull, CVMX_CSR_DB_TYPE_NCB, 32, 168},
- {"ENDOR_OFS_HMM_START_ADDR1" , 0x10f0000832034ull, CVMX_CSR_DB_TYPE_NCB, 32, 169},
- {"ENDOR_OFS_HMM_START_ADDR2" , 0x10f0000832038ull, CVMX_CSR_DB_TYPE_NCB, 32, 170},
- {"ENDOR_OFS_HMM_START_ADDR3" , 0x10f000083203cull, CVMX_CSR_DB_TYPE_NCB, 32, 171},
- {"ENDOR_OFS_HMM_STATUS" , 0x10f0000832000ull, CVMX_CSR_DB_TYPE_NCB, 32, 172},
- {"ENDOR_OFS_HMM_XFER_CNT" , 0x10f000083202cull, CVMX_CSR_DB_TYPE_NCB, 32, 173},
- {"ENDOR_OFS_HMM_XFER_Q_STATUS" , 0x10f000083200cull, CVMX_CSR_DB_TYPE_NCB, 32, 174},
- {"ENDOR_OFS_HMM_XFER_START" , 0x10f0000832028ull, CVMX_CSR_DB_TYPE_NCB, 32, 175},
- {"ENDOR_RFIF_1PPS_GEN_CFG" , 0x10f00008680ccull, CVMX_CSR_DB_TYPE_NCB, 32, 176},
- {"ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET", 0x10f0000868104ull, CVMX_CSR_DB_TYPE_NCB, 32, 177},
- {"ENDOR_RFIF_1PPS_VERIF_GEN_EN", 0x10f0000868110ull, CVMX_CSR_DB_TYPE_NCB, 32, 178},
- {"ENDOR_RFIF_1PPS_VERIF_SCNT" , 0x10f0000868114ull, CVMX_CSR_DB_TYPE_NCB, 32, 179},
- {"ENDOR_RFIF_CONF" , 0x10f0000868010ull, CVMX_CSR_DB_TYPE_NCB, 32, 180},
- {"ENDOR_RFIF_CONF2" , 0x10f000086801cull, CVMX_CSR_DB_TYPE_NCB, 32, 181},
- {"ENDOR_RFIF_DSP1_GPIO" , 0x10f00008684c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 182},
- {"ENDOR_RFIF_DSP_RX_HIS" , 0x10f000086840cull, CVMX_CSR_DB_TYPE_NCB, 32, 183},
- {"ENDOR_RFIF_DSP_RX_ISM" , 0x10f0000868400ull, CVMX_CSR_DB_TYPE_NCB, 32, 184},
- {"ENDOR_RFIF_FIRS_ENABLE" , 0x10f00008684c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 185},
- {"ENDOR_RFIF_FRAME_CNT" , 0x10f0000868030ull, CVMX_CSR_DB_TYPE_NCB, 32, 186},
- {"ENDOR_RFIF_FRAME_L" , 0x10f0000868014ull, CVMX_CSR_DB_TYPE_NCB, 32, 187},
- {"ENDOR_RFIF_GPIO_0" , 0x10f0000868418ull, CVMX_CSR_DB_TYPE_NCB, 32, 188},
- {"ENDOR_RFIF_GPIO_1" , 0x10f000086841cull, CVMX_CSR_DB_TYPE_NCB, 32, 188},
- {"ENDOR_RFIF_GPIO_2" , 0x10f0000868420ull, CVMX_CSR_DB_TYPE_NCB, 32, 188},
- {"ENDOR_RFIF_GPIO_3" , 0x10f0000868424ull, CVMX_CSR_DB_TYPE_NCB, 32, 188},
- {"ENDOR_RFIF_MAX_SAMPLE_ADJ" , 0x10f00008680dcull, CVMX_CSR_DB_TYPE_NCB, 32, 189},
- {"ENDOR_RFIF_MIN_SAMPLE_ADJ" , 0x10f00008680e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 190},
- {"ENDOR_RFIF_NUM_RX_WIN" , 0x10f0000868018ull, CVMX_CSR_DB_TYPE_NCB, 32, 191},
- {"ENDOR_RFIF_PWM_ENABLE" , 0x10f0000868180ull, CVMX_CSR_DB_TYPE_NCB, 32, 192},
- {"ENDOR_RFIF_PWM_HIGH_TIME" , 0x10f0000868184ull, CVMX_CSR_DB_TYPE_NCB, 32, 193},
- {"ENDOR_RFIF_PWM_LOW_TIME" , 0x10f0000868188ull, CVMX_CSR_DB_TYPE_NCB, 32, 194},
- {"ENDOR_RFIF_RD_TIMER64_LSB" , 0x10f00008681acull, CVMX_CSR_DB_TYPE_NCB, 32, 195},
- {"ENDOR_RFIF_RD_TIMER64_MSB" , 0x10f00008681b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 196},
- {"ENDOR_RFIF_REAL_TIME_TIMER" , 0x10f00008680c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 197},
- {"ENDOR_RFIF_RF_CLK_TIMER" , 0x10f0000868194ull, CVMX_CSR_DB_TYPE_NCB, 32, 198},
- {"ENDOR_RFIF_RF_CLK_TIMER_EN" , 0x10f0000868198ull, CVMX_CSR_DB_TYPE_NCB, 32, 199},
- {"ENDOR_RFIF_RX_CORRECT_ADJ" , 0x10f00008680e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 200},
- {"ENDOR_RFIF_RX_DIV_STATUS" , 0x10f0000868004ull, CVMX_CSR_DB_TYPE_NCB, 32, 201},
- {"ENDOR_RFIF_RX_FIFO_CNT" , 0x10f0000868500ull, CVMX_CSR_DB_TYPE_NCB, 32, 202},
- {"ENDOR_RFIF_RX_IF_CFG" , 0x10f0000868038ull, CVMX_CSR_DB_TYPE_NCB, 32, 203},
- {"ENDOR_RFIF_RX_LEAD_LAG" , 0x10f0000868020ull, CVMX_CSR_DB_TYPE_NCB, 32, 204},
- {"ENDOR_RFIF_RX_LOAD_CFG" , 0x10f0000868508ull, CVMX_CSR_DB_TYPE_NCB, 32, 205},
- {"ENDOR_RFIF_RX_OFFSET" , 0x10f00008680d4ull, CVMX_CSR_DB_TYPE_NCB, 32, 206},
- {"ENDOR_RFIF_RX_OFFSET_ADJ_SCNT", 0x10f0000868108ull, CVMX_CSR_DB_TYPE_NCB, 32, 207},
- {"ENDOR_RFIF_RX_STATUS" , 0x10f0000868000ull, CVMX_CSR_DB_TYPE_NCB, 32, 208},
- {"ENDOR_RFIF_RX_SYNC_SCNT" , 0x10f00008680c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 209},
- {"ENDOR_RFIF_RX_SYNC_VALUE" , 0x10f00008680c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 210},
- {"ENDOR_RFIF_RX_TH" , 0x10f0000868410ull, CVMX_CSR_DB_TYPE_NCB, 32, 211},
- {"ENDOR_RFIF_RX_TRANSFER_SIZE" , 0x10f000086850cull, CVMX_CSR_DB_TYPE_NCB, 32, 212},
- {"ENDOR_RFIF_RX_W_E0" , 0x10f0000868084ull, CVMX_CSR_DB_TYPE_NCB, 32, 213},
- {"ENDOR_RFIF_RX_W_E1" , 0x10f0000868088ull, CVMX_CSR_DB_TYPE_NCB, 32, 213},
- {"ENDOR_RFIF_RX_W_E2" , 0x10f000086808cull, CVMX_CSR_DB_TYPE_NCB, 32, 213},
- {"ENDOR_RFIF_RX_W_E3" , 0x10f0000868090ull, CVMX_CSR_DB_TYPE_NCB, 32, 213},
- {"ENDOR_RFIF_RX_W_S0" , 0x10f0000868044ull, CVMX_CSR_DB_TYPE_NCB, 32, 214},
- {"ENDOR_RFIF_RX_W_S1" , 0x10f0000868048ull, CVMX_CSR_DB_TYPE_NCB, 32, 214},
- {"ENDOR_RFIF_RX_W_S2" , 0x10f000086804cull, CVMX_CSR_DB_TYPE_NCB, 32, 214},
- {"ENDOR_RFIF_RX_W_S3" , 0x10f0000868050ull, CVMX_CSR_DB_TYPE_NCB, 32, 214},
- {"ENDOR_RFIF_SAMPLE_ADJ_CFG" , 0x10f00008680e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 215},
- {"ENDOR_RFIF_SAMPLE_ADJ_ERROR" , 0x10f0000868100ull, CVMX_CSR_DB_TYPE_NCB, 32, 216},
- {"ENDOR_RFIF_SAMPLE_CNT" , 0x10f0000868028ull, CVMX_CSR_DB_TYPE_NCB, 32, 217},
- {"ENDOR_RFIF_SKIP_FRM_CNT_BITS", 0x10f0000868444ull, CVMX_CSR_DB_TYPE_NCB, 32, 218},
- {"ENDOR_RFIF_SPI_0_LL" , 0x10f0000868430ull, CVMX_CSR_DB_TYPE_NCB, 32, 219},
- {"ENDOR_RFIF_SPI_1_LL" , 0x10f0000868434ull, CVMX_CSR_DB_TYPE_NCB, 32, 219},
- {"ENDOR_RFIF_SPI_2_LL" , 0x10f0000868438ull, CVMX_CSR_DB_TYPE_NCB, 32, 219},
- {"ENDOR_RFIF_SPI_3_LL" , 0x10f000086843cull, CVMX_CSR_DB_TYPE_NCB, 32, 219},
- {"ENDOR_RFIF_SPI_CMD_ATTR0" , 0x10f0000868a00ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR1" , 0x10f0000868a04ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR2" , 0x10f0000868a08ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR3" , 0x10f0000868a0cull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR4" , 0x10f0000868a10ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR5" , 0x10f0000868a14ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR6" , 0x10f0000868a18ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR7" , 0x10f0000868a1cull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR8" , 0x10f0000868a20ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR9" , 0x10f0000868a24ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR10" , 0x10f0000868a28ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR11" , 0x10f0000868a2cull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR12" , 0x10f0000868a30ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR13" , 0x10f0000868a34ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR14" , 0x10f0000868a38ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR15" , 0x10f0000868a3cull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR16" , 0x10f0000868a40ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR17" , 0x10f0000868a44ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR18" , 0x10f0000868a48ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR19" , 0x10f0000868a4cull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR20" , 0x10f0000868a50ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR21" , 0x10f0000868a54ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR22" , 0x10f0000868a58ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR23" , 0x10f0000868a5cull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR24" , 0x10f0000868a60ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR25" , 0x10f0000868a64ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR26" , 0x10f0000868a68ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR27" , 0x10f0000868a6cull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR28" , 0x10f0000868a70ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR29" , 0x10f0000868a74ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR30" , 0x10f0000868a78ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR31" , 0x10f0000868a7cull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR32" , 0x10f0000868a80ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR33" , 0x10f0000868a84ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR34" , 0x10f0000868a88ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR35" , 0x10f0000868a8cull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR36" , 0x10f0000868a90ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR37" , 0x10f0000868a94ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR38" , 0x10f0000868a98ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR39" , 0x10f0000868a9cull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR40" , 0x10f0000868aa0ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR41" , 0x10f0000868aa4ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR42" , 0x10f0000868aa8ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR43" , 0x10f0000868aacull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR44" , 0x10f0000868ab0ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR45" , 0x10f0000868ab4ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR46" , 0x10f0000868ab8ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR47" , 0x10f0000868abcull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR48" , 0x10f0000868ac0ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR49" , 0x10f0000868ac4ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR50" , 0x10f0000868ac8ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR51" , 0x10f0000868accull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR52" , 0x10f0000868ad0ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR53" , 0x10f0000868ad4ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR54" , 0x10f0000868ad8ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR55" , 0x10f0000868adcull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR56" , 0x10f0000868ae0ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR57" , 0x10f0000868ae4ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR58" , 0x10f0000868ae8ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR59" , 0x10f0000868aecull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR60" , 0x10f0000868af0ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR61" , 0x10f0000868af4ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR62" , 0x10f0000868af8ull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMD_ATTR63" , 0x10f0000868afcull, CVMX_CSR_DB_TYPE_NCB, 32, 220},
- {"ENDOR_RFIF_SPI_CMDS0" , 0x10f0000868800ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS1" , 0x10f0000868804ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS2" , 0x10f0000868808ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS3" , 0x10f000086880cull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS4" , 0x10f0000868810ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS5" , 0x10f0000868814ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS6" , 0x10f0000868818ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS7" , 0x10f000086881cull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS8" , 0x10f0000868820ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS9" , 0x10f0000868824ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS10" , 0x10f0000868828ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS11" , 0x10f000086882cull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS12" , 0x10f0000868830ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS13" , 0x10f0000868834ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS14" , 0x10f0000868838ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS15" , 0x10f000086883cull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS16" , 0x10f0000868840ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS17" , 0x10f0000868844ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS18" , 0x10f0000868848ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS19" , 0x10f000086884cull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS20" , 0x10f0000868850ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS21" , 0x10f0000868854ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS22" , 0x10f0000868858ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS23" , 0x10f000086885cull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS24" , 0x10f0000868860ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS25" , 0x10f0000868864ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS26" , 0x10f0000868868ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS27" , 0x10f000086886cull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS28" , 0x10f0000868870ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS29" , 0x10f0000868874ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS30" , 0x10f0000868878ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS31" , 0x10f000086887cull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS32" , 0x10f0000868880ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS33" , 0x10f0000868884ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS34" , 0x10f0000868888ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS35" , 0x10f000086888cull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS36" , 0x10f0000868890ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS37" , 0x10f0000868894ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS38" , 0x10f0000868898ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS39" , 0x10f000086889cull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS40" , 0x10f00008688a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS41" , 0x10f00008688a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS42" , 0x10f00008688a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS43" , 0x10f00008688acull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS44" , 0x10f00008688b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS45" , 0x10f00008688b4ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS46" , 0x10f00008688b8ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS47" , 0x10f00008688bcull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS48" , 0x10f00008688c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS49" , 0x10f00008688c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS50" , 0x10f00008688c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS51" , 0x10f00008688ccull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS52" , 0x10f00008688d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS53" , 0x10f00008688d4ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS54" , 0x10f00008688d8ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS55" , 0x10f00008688dcull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS56" , 0x10f00008688e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS57" , 0x10f00008688e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS58" , 0x10f00008688e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS59" , 0x10f00008688ecull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS60" , 0x10f00008688f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS61" , 0x10f00008688f4ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS62" , 0x10f00008688f8ull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CMDS63" , 0x10f00008688fcull, CVMX_CSR_DB_TYPE_NCB, 32, 221},
- {"ENDOR_RFIF_SPI_CONF0" , 0x10f0000868428ull, CVMX_CSR_DB_TYPE_NCB, 32, 222},
- {"ENDOR_RFIF_SPI_CONF1" , 0x10f000086842cull, CVMX_CSR_DB_TYPE_NCB, 32, 223},
- {"ENDOR_RFIF_SPI_CTRL" , 0x10f0000866008ull, CVMX_CSR_DB_TYPE_NCB, 32, 224},
- {"ENDOR_RFIF_SPI_DIN0" , 0x10f0000868900ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN1" , 0x10f0000868904ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN2" , 0x10f0000868908ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN3" , 0x10f000086890cull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN4" , 0x10f0000868910ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN5" , 0x10f0000868914ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN6" , 0x10f0000868918ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN7" , 0x10f000086891cull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN8" , 0x10f0000868920ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN9" , 0x10f0000868924ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN10" , 0x10f0000868928ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN11" , 0x10f000086892cull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN12" , 0x10f0000868930ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN13" , 0x10f0000868934ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN14" , 0x10f0000868938ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN15" , 0x10f000086893cull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN16" , 0x10f0000868940ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN17" , 0x10f0000868944ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN18" , 0x10f0000868948ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN19" , 0x10f000086894cull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN20" , 0x10f0000868950ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN21" , 0x10f0000868954ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN22" , 0x10f0000868958ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN23" , 0x10f000086895cull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN24" , 0x10f0000868960ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN25" , 0x10f0000868964ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN26" , 0x10f0000868968ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN27" , 0x10f000086896cull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN28" , 0x10f0000868970ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN29" , 0x10f0000868974ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN30" , 0x10f0000868978ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN31" , 0x10f000086897cull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN32" , 0x10f0000868980ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN33" , 0x10f0000868984ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN34" , 0x10f0000868988ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN35" , 0x10f000086898cull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN36" , 0x10f0000868990ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN37" , 0x10f0000868994ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN38" , 0x10f0000868998ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN39" , 0x10f000086899cull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN40" , 0x10f00008689a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN41" , 0x10f00008689a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN42" , 0x10f00008689a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN43" , 0x10f00008689acull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN44" , 0x10f00008689b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN45" , 0x10f00008689b4ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN46" , 0x10f00008689b8ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN47" , 0x10f00008689bcull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN48" , 0x10f00008689c0ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN49" , 0x10f00008689c4ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN50" , 0x10f00008689c8ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN51" , 0x10f00008689ccull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN52" , 0x10f00008689d0ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN53" , 0x10f00008689d4ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN54" , 0x10f00008689d8ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN55" , 0x10f00008689dcull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN56" , 0x10f00008689e0ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN57" , 0x10f00008689e4ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN58" , 0x10f00008689e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN59" , 0x10f00008689ecull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN60" , 0x10f00008689f0ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN61" , 0x10f00008689f4ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN62" , 0x10f00008689f8ull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_DIN63" , 0x10f00008689fcull, CVMX_CSR_DB_TYPE_NCB, 32, 225},
- {"ENDOR_RFIF_SPI_RX_DATA" , 0x10f0000866000ull, CVMX_CSR_DB_TYPE_NCB, 32, 226},
- {"ENDOR_RFIF_SPI_STATUS" , 0x10f0000866010ull, CVMX_CSR_DB_TYPE_NCB, 32, 227},
- {"ENDOR_RFIF_SPI_TX_DATA" , 0x10f0000866004ull, CVMX_CSR_DB_TYPE_NCB, 32, 228},
- {"ENDOR_RFIF_TIMER64_CFG" , 0x10f00008681a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 229},
- {"ENDOR_RFIF_TIMER64_EN" , 0x10f000086819cull, CVMX_CSR_DB_TYPE_NCB, 32, 230},
- {"ENDOR_RFIF_TTI_SCNT_INT0" , 0x10f0000868140ull, CVMX_CSR_DB_TYPE_NCB, 32, 231},
- {"ENDOR_RFIF_TTI_SCNT_INT1" , 0x10f0000868144ull, CVMX_CSR_DB_TYPE_NCB, 32, 231},
- {"ENDOR_RFIF_TTI_SCNT_INT2" , 0x10f0000868148ull, CVMX_CSR_DB_TYPE_NCB, 32, 231},
- {"ENDOR_RFIF_TTI_SCNT_INT3" , 0x10f000086814cull, CVMX_CSR_DB_TYPE_NCB, 32, 231},
- {"ENDOR_RFIF_TTI_SCNT_INT4" , 0x10f0000868150ull, CVMX_CSR_DB_TYPE_NCB, 32, 231},
- {"ENDOR_RFIF_TTI_SCNT_INT5" , 0x10f0000868154ull, CVMX_CSR_DB_TYPE_NCB, 32, 231},
- {"ENDOR_RFIF_TTI_SCNT_INT6" , 0x10f0000868158ull, CVMX_CSR_DB_TYPE_NCB, 32, 231},
- {"ENDOR_RFIF_TTI_SCNT_INT7" , 0x10f000086815cull, CVMX_CSR_DB_TYPE_NCB, 32, 231},
- {"ENDOR_RFIF_TTI_SCNT_INT_CLR" , 0x10f0000868118ull, CVMX_CSR_DB_TYPE_NCB, 32, 232},
- {"ENDOR_RFIF_TTI_SCNT_INT_EN" , 0x10f0000868124ull, CVMX_CSR_DB_TYPE_NCB, 32, 233},
- {"ENDOR_RFIF_TTI_SCNT_INT_MAP" , 0x10f0000868120ull, CVMX_CSR_DB_TYPE_NCB, 32, 234},
- {"ENDOR_RFIF_TTI_SCNT_INT_STAT", 0x10f000086811cull, CVMX_CSR_DB_TYPE_NCB, 32, 235},
- {"ENDOR_RFIF_TX_DIV_STATUS" , 0x10f000086800cull, CVMX_CSR_DB_TYPE_NCB, 32, 236},
- {"ENDOR_RFIF_TX_IF_CFG" , 0x10f0000868034ull, CVMX_CSR_DB_TYPE_NCB, 32, 237},
- {"ENDOR_RFIF_TX_LEAD_LAG" , 0x10f0000868024ull, CVMX_CSR_DB_TYPE_NCB, 32, 238},
- {"ENDOR_RFIF_TX_OFFSET" , 0x10f00008680d8ull, CVMX_CSR_DB_TYPE_NCB, 32, 239},
- {"ENDOR_RFIF_TX_OFFSET_ADJ_SCNT", 0x10f000086810cull, CVMX_CSR_DB_TYPE_NCB, 32, 240},
- {"ENDOR_RFIF_TX_STATUS" , 0x10f0000868008ull, CVMX_CSR_DB_TYPE_NCB, 32, 241},
- {"ENDOR_RFIF_TX_TH" , 0x10f0000868414ull, CVMX_CSR_DB_TYPE_NCB, 32, 242},
- {"ENDOR_RFIF_WIN_EN" , 0x10f0000868040ull, CVMX_CSR_DB_TYPE_NCB, 32, 243},
- {"ENDOR_RFIF_WIN_UPD_SCNT" , 0x10f000086803cull, CVMX_CSR_DB_TYPE_NCB, 32, 244},
- {"ENDOR_RFIF_WR_TIMER64_LSB" , 0x10f00008681a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 245},
- {"ENDOR_RFIF_WR_TIMER64_MSB" , 0x10f00008681a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 246},
- {"ENDOR_RSTCLK_CLKENB0_CLR" , 0x10f0000844428ull, CVMX_CSR_DB_TYPE_NCB, 32, 247},
- {"ENDOR_RSTCLK_CLKENB0_SET" , 0x10f0000844424ull, CVMX_CSR_DB_TYPE_NCB, 32, 248},
- {"ENDOR_RSTCLK_CLKENB0_STATE" , 0x10f0000844420ull, CVMX_CSR_DB_TYPE_NCB, 32, 249},
- {"ENDOR_RSTCLK_CLKENB1_CLR" , 0x10f0000844438ull, CVMX_CSR_DB_TYPE_NCB, 32, 250},
- {"ENDOR_RSTCLK_CLKENB1_SET" , 0x10f0000844434ull, CVMX_CSR_DB_TYPE_NCB, 32, 251},
- {"ENDOR_RSTCLK_CLKENB1_STATE" , 0x10f0000844430ull, CVMX_CSR_DB_TYPE_NCB, 32, 252},
- {"ENDOR_RSTCLK_DSPSTALL_CLR" , 0x10f0000844448ull, CVMX_CSR_DB_TYPE_NCB, 32, 253},
- {"ENDOR_RSTCLK_DSPSTALL_SET" , 0x10f0000844444ull, CVMX_CSR_DB_TYPE_NCB, 32, 254},
- {"ENDOR_RSTCLK_DSPSTALL_STATE" , 0x10f0000844440ull, CVMX_CSR_DB_TYPE_NCB, 32, 255},
- {"ENDOR_RSTCLK_INTR0_CLRMASK" , 0x10f0000844598ull, CVMX_CSR_DB_TYPE_NCB, 32, 256},
- {"ENDOR_RSTCLK_INTR0_MASK" , 0x10f0000844590ull, CVMX_CSR_DB_TYPE_NCB, 32, 257},
- {"ENDOR_RSTCLK_INTR0_SETMASK" , 0x10f0000844594ull, CVMX_CSR_DB_TYPE_NCB, 32, 258},
- {"ENDOR_RSTCLK_INTR0_STATUS" , 0x10f000084459cull, CVMX_CSR_DB_TYPE_NCB, 32, 259},
- {"ENDOR_RSTCLK_INTR1_CLRMASK" , 0x10f00008445a8ull, CVMX_CSR_DB_TYPE_NCB, 32, 260},
- {"ENDOR_RSTCLK_INTR1_MASK" , 0x10f00008445a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 261},
- {"ENDOR_RSTCLK_INTR1_SETMASK" , 0x10f00008445a4ull, CVMX_CSR_DB_TYPE_NCB, 32, 262},
- {"ENDOR_RSTCLK_INTR1_STATUS" , 0x10f00008445acull, CVMX_CSR_DB_TYPE_NCB, 32, 263},
- {"ENDOR_RSTCLK_PHY_CONFIG" , 0x10f0000844450ull, CVMX_CSR_DB_TYPE_NCB, 32, 264},
- {"ENDOR_RSTCLK_PROC_MON" , 0x10f00008445b0ull, CVMX_CSR_DB_TYPE_NCB, 32, 265},
- {"ENDOR_RSTCLK_PROC_MON_COUNT" , 0x10f00008445b4ull, CVMX_CSR_DB_TYPE_NCB, 32, 266},
- {"ENDOR_RSTCLK_RESET0_CLR" , 0x10f0000844408ull, CVMX_CSR_DB_TYPE_NCB, 32, 267},
- {"ENDOR_RSTCLK_RESET0_SET" , 0x10f0000844404ull, CVMX_CSR_DB_TYPE_NCB, 32, 268},
- {"ENDOR_RSTCLK_RESET0_STATE" , 0x10f0000844400ull, CVMX_CSR_DB_TYPE_NCB, 32, 269},
- {"ENDOR_RSTCLK_RESET1_CLR" , 0x10f0000844418ull, CVMX_CSR_DB_TYPE_NCB, 32, 270},
- {"ENDOR_RSTCLK_RESET1_SET" , 0x10f0000844414ull, CVMX_CSR_DB_TYPE_NCB, 32, 271},
- {"ENDOR_RSTCLK_RESET1_STATE" , 0x10f0000844410ull, CVMX_CSR_DB_TYPE_NCB, 32, 272},
- {"ENDOR_RSTCLK_SW_INTR_CLR" , 0x10f0000844588ull, CVMX_CSR_DB_TYPE_NCB, 32, 273},
- {"ENDOR_RSTCLK_SW_INTR_SET" , 0x10f0000844584ull, CVMX_CSR_DB_TYPE_NCB, 32, 274},
- {"ENDOR_RSTCLK_SW_INTR_STATUS" , 0x10f0000844580ull, CVMX_CSR_DB_TYPE_NCB, 32, 275},
- {"ENDOR_RSTCLK_TIME0_THRD" , 0x10f0000844510ull, CVMX_CSR_DB_TYPE_NCB, 32, 276},
- {"ENDOR_RSTCLK_TIME1_THRD" , 0x10f0000844514ull, CVMX_CSR_DB_TYPE_NCB, 32, 276},
- {"ENDOR_RSTCLK_TIME2_THRD" , 0x10f0000844518ull, CVMX_CSR_DB_TYPE_NCB, 32, 276},
- {"ENDOR_RSTCLK_TIME3_THRD" , 0x10f000084451cull, CVMX_CSR_DB_TYPE_NCB, 32, 276},
- {"ENDOR_RSTCLK_TIME4_THRD" , 0x10f0000844520ull, CVMX_CSR_DB_TYPE_NCB, 32, 276},
- {"ENDOR_RSTCLK_TIME5_THRD" , 0x10f0000844524ull, CVMX_CSR_DB_TYPE_NCB, 32, 276},
- {"ENDOR_RSTCLK_TIME6_THRD" , 0x10f0000844528ull, CVMX_CSR_DB_TYPE_NCB, 32, 276},
- {"ENDOR_RSTCLK_TIME7_THRD" , 0x10f000084452cull, CVMX_CSR_DB_TYPE_NCB, 32, 276},
- {"ENDOR_RSTCLK_TIMER_CTL" , 0x10f0000844500ull, CVMX_CSR_DB_TYPE_NCB, 32, 277},
- {"ENDOR_RSTCLK_TIMER_INTR_CLR" , 0x10f0000844534ull, CVMX_CSR_DB_TYPE_NCB, 32, 278},
- {"ENDOR_RSTCLK_TIMER_INTR_STATUS", 0x10f0000844530ull, CVMX_CSR_DB_TYPE_NCB, 32, 279},
- {"ENDOR_RSTCLK_TIMER_MAX" , 0x10f0000844508ull, CVMX_CSR_DB_TYPE_NCB, 32, 280},
- {"ENDOR_RSTCLK_TIMER_VALUE" , 0x10f0000844504ull, CVMX_CSR_DB_TYPE_NCB, 32, 281},
- {"ENDOR_RSTCLK_VERSION" , 0x10f0000844570ull, CVMX_CSR_DB_TYPE_NCB, 32, 282},
- {"EOI_BIST_CTL_STA" , 0x1180013000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
- {"EOI_CTL_STA" , 0x1180013000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
- {"EOI_DEF_STA0" , 0x1180013000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
- {"EOI_DEF_STA1" , 0x1180013000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
- {"EOI_DEF_STA2" , 0x1180013000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
- {"EOI_ECC_CTL" , 0x1180013000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
- {"EOI_ENDOR_BISTR_CTL_STA" , 0x1180013000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
- {"EOI_ENDOR_CLK_CTL" , 0x1180013000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
- {"EOI_ENDOR_CTL" , 0x1180013000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
- {"EOI_INT_ENA" , 0x1180013000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
- {"EOI_INT_STA" , 0x1180013000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
- {"EOI_IO_DRV" , 0x1180013000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
- {"EOI_THROTTLE_CTL" , 0x1180013000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
- {"FPA_ADDR_RANGE_ERROR" , 0x1180028000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
- {"FPA_BIST_STATUS" , 0x11800280000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
- {"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
- {"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
- {"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
- {"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
- {"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
- {"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
- {"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
- {"FPA_PACKET_THRESHOLD" , 0x1180028000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
- {"FPA_POOL0_END_ADDR" , 0x1180028000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"FPA_POOL1_END_ADDR" , 0x1180028000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"FPA_POOL2_END_ADDR" , 0x1180028000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"FPA_POOL3_END_ADDR" , 0x1180028000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"FPA_POOL4_END_ADDR" , 0x1180028000378ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"FPA_POOL5_END_ADDR" , 0x1180028000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"FPA_POOL6_END_ADDR" , 0x1180028000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"FPA_POOL7_END_ADDR" , 0x1180028000390ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
- {"FPA_POOL0_START_ADDR" , 0x1180028000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"FPA_POOL1_START_ADDR" , 0x1180028000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"FPA_POOL2_START_ADDR" , 0x1180028000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"FPA_POOL3_START_ADDR" , 0x1180028000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"FPA_POOL4_START_ADDR" , 0x1180028000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"FPA_POOL5_START_ADDR" , 0x1180028000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"FPA_POOL6_START_ADDR" , 0x1180028000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"FPA_POOL7_START_ADDR" , 0x1180028000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
- {"FPA_POOL0_THRESHOLD" , 0x1180028000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"FPA_POOL1_THRESHOLD" , 0x1180028000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"FPA_POOL2_THRESHOLD" , 0x1180028000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"FPA_POOL3_THRESHOLD" , 0x1180028000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"FPA_POOL4_THRESHOLD" , 0x1180028000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"FPA_POOL5_THRESHOLD" , 0x1180028000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"FPA_POOL6_THRESHOLD" , 0x1180028000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"FPA_POOL7_THRESHOLD" , 0x1180028000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
- {"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"FPA_QUE1_AVAILABLE" , 0x11800280000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"FPA_QUE2_AVAILABLE" , 0x11800280000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"FPA_QUE3_AVAILABLE" , 0x11800280000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"FPA_QUE4_AVAILABLE" , 0x11800280000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"FPA_QUE5_AVAILABLE" , 0x11800280000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"FPA_QUE6_AVAILABLE" , 0x11800280000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"FPA_QUE7_AVAILABLE" , 0x11800280000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
- {"FPA_QUE0_PAGE_INDEX" , 0x11800280000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"FPA_QUE1_PAGE_INDEX" , 0x11800280000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
- {"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
- {"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
- {"FPA_WQE_THRESHOLD" , 0x1180028000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
- {"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
- {"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
- {"GMX0_CLK_EN" , 0x11800080007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
- {"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
- {"GMX0_INF_MODE" , 0x11800080007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
- {"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
- {"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
- {"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
- {"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
- {"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
- {"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
- {"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
- {"GMX0_RX000_ADR_CAM4" , 0x11800080001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"GMX0_RX001_ADR_CAM4" , 0x11800080009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"GMX0_RX002_ADR_CAM4" , 0x11800080011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"GMX0_RX003_ADR_CAM4" , 0x11800080019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
- {"GMX0_RX000_ADR_CAM5" , 0x11800080001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"GMX0_RX001_ADR_CAM5" , 0x11800080009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"GMX0_RX002_ADR_CAM5" , 0x11800080011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"GMX0_RX003_ADR_CAM5" , 0x11800080019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
- {"GMX0_RX000_ADR_CAM_ALL_EN" , 0x1180008000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"GMX0_RX001_ADR_CAM_ALL_EN" , 0x1180008000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
- {"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
- {"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
- {"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
- {"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
- {"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
- {"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
- {"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
- {"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
- {"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
- {"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
- {"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
- {"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
- {"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
- {"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
- {"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
- {"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
- {"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
- {"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
- {"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
- {"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
- {"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
- {"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
- {"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
- {"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
- {"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
- {"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
- {"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
- {"GMX0_RX_PRT_INFO" , 0x11800080004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
- {"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
- {"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
- {"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
- {"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"GMX0_SMAC001" , 0x1180008000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
- {"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
- {"GMX0_TB_REG" , 0x11800080007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
- {"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"GMX0_TX001_APPEND" , 0x1180008000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
- {"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"GMX0_TX001_BURST" , 0x1180008000a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
- {"GMX0_TX000_CBFC_XOFF" , 0x11800080005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
- {"GMX0_TX000_CBFC_XON" , 0x11800080005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
- {"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_TX001_CTL" , 0x1180008000a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
- {"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX0_TX001_MIN_PKT" , 0x1180008000a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
- {"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
- {"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
- {"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX0_TX001_PAUSE_TOGO" , 0x1180008000a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
- {"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX0_TX001_PAUSE_ZERO" , 0x1180008000a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
- {"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX0_TX001_SGMII_CTL" , 0x1180008000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
- {"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX0_TX001_SLOT" , 0x1180008000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
- {"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX0_TX001_SOFT_PAUSE" , 0x1180008000a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
- {"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX0_TX001_STAT0" , 0x1180008000a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
- {"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX0_TX001_STAT1" , 0x1180008000a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
- {"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX0_TX001_STAT2" , 0x1180008000a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
- {"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX0_TX001_STAT3" , 0x1180008000a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
- {"GMX0_TX000_STAT4" , 0x11800080002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX0_TX001_STAT4" , 0x1180008000aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
- {"GMX0_TX000_STAT5" , 0x11800080002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX0_TX001_STAT5" , 0x1180008000aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
- {"GMX0_TX000_STAT6" , 0x11800080002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX0_TX001_STAT6" , 0x1180008000ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
- {"GMX0_TX000_STAT7" , 0x11800080002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX0_TX001_STAT7" , 0x1180008000ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
- {"GMX0_TX000_STAT8" , 0x11800080002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX0_TX001_STAT8" , 0x1180008000ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
- {"GMX0_TX000_STAT9" , 0x11800080002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX0_TX001_STAT9" , 0x1180008000ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
- {"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX0_TX001_STATS_CTL" , 0x1180008000a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
- {"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX0_TX001_THRESH" , 0x1180008000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
- {"GMX0_TX_BP" , 0x11800080004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
- {"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
- {"GMX0_TX_CORRUPT" , 0x11800080004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
- {"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
- {"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
- {"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
- {"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
- {"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
- {"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
- {"GMX0_TX_LFSR" , 0x11800080004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
- {"GMX0_TX_OVR_BP" , 0x11800080004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
- {"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
- {"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
- {"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
- {"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
- {"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
- {"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
- {"GPIO_CLK_GEN0" , 0x10700000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"GPIO_CLK_GEN1" , 0x10700000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"GPIO_CLK_GEN2" , 0x10700000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"GPIO_CLK_GEN3" , 0x10700000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
- {"GPIO_CLK_QLM0" , 0x10700000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"GPIO_CLK_QLM1" , 0x10700000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
- {"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
- {"GPIO_MULTI_CAST" , 0x10700000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
- {"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
- {"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
- {"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
- {"GPIO_XBIT_CFG16" , 0x1070000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
- {"GPIO_XBIT_CFG17" , 0x1070000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
- {"GPIO_XBIT_CFG18" , 0x1070000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
- {"GPIO_XBIT_CFG19" , 0x1070000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
- {"IOB_BIST_STATUS" , 0x11800f00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
- {"IOB_CTL_STATUS" , 0x11800f0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
- {"IOB_DWB_PRI_CNT" , 0x11800f0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
- {"IOB_FAU_TIMEOUT" , 0x11800f0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
- {"IOB_I2C_PRI_CNT" , 0x11800f0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
- {"IOB_INB_CONTROL_MATCH" , 0x11800f0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
- {"IOB_INB_CONTROL_MATCH_ENB" , 0x11800f0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
- {"IOB_INB_DATA_MATCH" , 0x11800f0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
- {"IOB_INB_DATA_MATCH_ENB" , 0x11800f0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
- {"IOB_INT_ENB" , 0x11800f0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
- {"IOB_INT_SUM" , 0x11800f0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
- {"IOB_N2C_L2C_PRI_CNT" , 0x11800f0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
- {"IOB_N2C_RSP_PRI_CNT" , 0x11800f0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
- {"IOB_OUTB_COM_PRI_CNT" , 0x11800f0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
- {"IOB_OUTB_CONTROL_MATCH" , 0x11800f0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
- {"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800f00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
- {"IOB_OUTB_DATA_MATCH" , 0x11800f0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
- {"IOB_OUTB_DATA_MATCH_ENB" , 0x11800f00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
- {"IOB_OUTB_FPA_PRI_CNT" , 0x11800f0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
- {"IOB_OUTB_REQ_PRI_CNT" , 0x11800f0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
- {"IOB_P2C_REQ_PRI_CNT" , 0x11800f0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
- {"IOB_PKT_ERR" , 0x11800f0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
- {"IOB_TO_CMB_CREDITS" , 0x11800f00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
- {"IPD_1ST_MBUFF_SKIP" , 0x14f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 434},
- {"IPD_1ST_NEXT_PTR_BACK" , 0x14f0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 435},
- {"IPD_2ND_NEXT_PTR_BACK" , 0x14f0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 436},
- {"IPD_BIST_STATUS" , 0x14f00000007f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 437},
- {"IPD_BP_PRT_RED_END" , 0x14f0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 438},
- {"IPD_CLK_COUNT" , 0x14f0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 439},
- {"IPD_CTL_STATUS" , 0x14f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 440},
- {"IPD_INT_ENB" , 0x14f0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 441},
- {"IPD_INT_SUM" , 0x14f0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 442},
- {"IPD_NOT_1ST_MBUFF_SKIP" , 0x14f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 443},
- {"IPD_PACKET_MBUFF_SIZE" , 0x14f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 444},
- {"IPD_PKT_PTR_VALID" , 0x14f0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 445},
- {"IPD_PORT0_BP_PAGE_CNT" , 0x14f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT1_BP_PAGE_CNT" , 0x14f0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT2_BP_PAGE_CNT" , 0x14f0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT3_BP_PAGE_CNT" , 0x14f0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT16_BP_PAGE_CNT" , 0x14f00000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT17_BP_PAGE_CNT" , 0x14f00000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT18_BP_PAGE_CNT" , 0x14f00000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT19_BP_PAGE_CNT" , 0x14f00000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT32_BP_PAGE_CNT" , 0x14f0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT33_BP_PAGE_CNT" , 0x14f0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT34_BP_PAGE_CNT" , 0x14f0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT35_BP_PAGE_CNT" , 0x14f0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 446},
- {"IPD_PORT36_BP_PAGE_CNT2" , 0x14f0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 447},
- {"IPD_PORT37_BP_PAGE_CNT2" , 0x14f0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 447},
- {"IPD_PORT38_BP_PAGE_CNT2" , 0x14f0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 447},
- {"IPD_PORT39_BP_PAGE_CNT2" , 0x14f0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 447},
- {"IPD_PORT40_BP_PAGE_CNT3" , 0x14f00000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 448},
- {"IPD_PORT41_BP_PAGE_CNT3" , 0x14f00000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 448},
- {"IPD_PORT42_BP_PAGE_CNT3" , 0x14f00000003e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 448},
- {"IPD_PORT43_BP_PAGE_CNT3" , 0x14f00000003e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 448},
- {"IPD_PORT44_BP_PAGE_CNT3" , 0x14f00000003f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 448},
- {"IPD_PORT45_BP_PAGE_CNT3" , 0x14f00000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 448},
- {"IPD_PORT46_BP_PAGE_CNT3" , 0x14f0000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 448},
- {"IPD_PORT47_BP_PAGE_CNT3" , 0x14f0000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 448},
- {"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14f0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 449},
- {"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14f0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 449},
- {"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14f0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 449},
- {"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14f00000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 449},
- {"IPD_PORT_BP_COUNTERS3_PAIR40", 0x14f00000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 450},
- {"IPD_PORT_BP_COUNTERS3_PAIR41", 0x14f00000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 450},
- {"IPD_PORT_BP_COUNTERS3_PAIR42", 0x14f00000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 450},
- {"IPD_PORT_BP_COUNTERS3_PAIR43", 0x14f00000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 450},
- {"IPD_PORT_BP_COUNTERS4_PAIR44", 0x14f0000000410ull, CVMX_CSR_DB_TYPE_NCB, 64, 451},
- {"IPD_PORT_BP_COUNTERS4_PAIR45", 0x14f0000000418ull, CVMX_CSR_DB_TYPE_NCB, 64, 451},
- {"IPD_PORT_BP_COUNTERS4_PAIR46", 0x14f0000000420ull, CVMX_CSR_DB_TYPE_NCB, 64, 451},
- {"IPD_PORT_BP_COUNTERS4_PAIR47", 0x14f0000000428ull, CVMX_CSR_DB_TYPE_NCB, 64, 451},
- {"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14f00000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14f00000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14f00000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14f00000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14f0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14f0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14f0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14f0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14f00000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14f00000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14f00000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14f00000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
- {"IPD_PORT_QOS_0_CNT" , 0x14f0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_1_CNT" , 0x14f0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_2_CNT" , 0x14f0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_3_CNT" , 0x14f00000008a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_4_CNT" , 0x14f00000008a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_5_CNT" , 0x14f00000008b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_6_CNT" , 0x14f00000008b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_7_CNT" , 0x14f00000008c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_8_CNT" , 0x14f00000008c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_9_CNT" , 0x14f00000008d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_10_CNT" , 0x14f00000008d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_11_CNT" , 0x14f00000008e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_12_CNT" , 0x14f00000008e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_13_CNT" , 0x14f00000008f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_14_CNT" , 0x14f00000008f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_15_CNT" , 0x14f0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_16_CNT" , 0x14f0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_17_CNT" , 0x14f0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_18_CNT" , 0x14f0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_19_CNT" , 0x14f0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_20_CNT" , 0x14f0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_21_CNT" , 0x14f0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_22_CNT" , 0x14f0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_23_CNT" , 0x14f0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_24_CNT" , 0x14f0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_25_CNT" , 0x14f0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_26_CNT" , 0x14f0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_27_CNT" , 0x14f0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_28_CNT" , 0x14f0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_29_CNT" , 0x14f0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_30_CNT" , 0x14f0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_31_CNT" , 0x14f0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_128_CNT" , 0x14f0000000c88ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_129_CNT" , 0x14f0000000c90ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_130_CNT" , 0x14f0000000c98ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_131_CNT" , 0x14f0000000ca0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_132_CNT" , 0x14f0000000ca8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_133_CNT" , 0x14f0000000cb0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_134_CNT" , 0x14f0000000cb8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_135_CNT" , 0x14f0000000cc0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_136_CNT" , 0x14f0000000cc8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_137_CNT" , 0x14f0000000cd0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_138_CNT" , 0x14f0000000cd8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_139_CNT" , 0x14f0000000ce0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_140_CNT" , 0x14f0000000ce8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_141_CNT" , 0x14f0000000cf0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_142_CNT" , 0x14f0000000cf8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_143_CNT" , 0x14f0000000d00ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_144_CNT" , 0x14f0000000d08ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_145_CNT" , 0x14f0000000d10ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_146_CNT" , 0x14f0000000d18ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_147_CNT" , 0x14f0000000d20ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_148_CNT" , 0x14f0000000d28ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_149_CNT" , 0x14f0000000d30ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_150_CNT" , 0x14f0000000d38ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_151_CNT" , 0x14f0000000d40ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_152_CNT" , 0x14f0000000d48ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_153_CNT" , 0x14f0000000d50ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_154_CNT" , 0x14f0000000d58ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_155_CNT" , 0x14f0000000d60ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_156_CNT" , 0x14f0000000d68ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_157_CNT" , 0x14f0000000d70ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_158_CNT" , 0x14f0000000d78ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_159_CNT" , 0x14f0000000d80ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_256_CNT" , 0x14f0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_257_CNT" , 0x14f0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_258_CNT" , 0x14f0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_259_CNT" , 0x14f00000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_260_CNT" , 0x14f00000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_261_CNT" , 0x14f00000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_262_CNT" , 0x14f00000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_263_CNT" , 0x14f00000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_264_CNT" , 0x14f00000010c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_265_CNT" , 0x14f00000010d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_266_CNT" , 0x14f00000010d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_267_CNT" , 0x14f00000010e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_268_CNT" , 0x14f00000010e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_269_CNT" , 0x14f00000010f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_270_CNT" , 0x14f00000010f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_271_CNT" , 0x14f0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_272_CNT" , 0x14f0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_273_CNT" , 0x14f0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_274_CNT" , 0x14f0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_275_CNT" , 0x14f0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_276_CNT" , 0x14f0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_277_CNT" , 0x14f0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_278_CNT" , 0x14f0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_279_CNT" , 0x14f0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_280_CNT" , 0x14f0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_281_CNT" , 0x14f0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_282_CNT" , 0x14f0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_283_CNT" , 0x14f0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_284_CNT" , 0x14f0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_285_CNT" , 0x14f0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_286_CNT" , 0x14f0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_287_CNT" , 0x14f0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_288_CNT" , 0x14f0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_289_CNT" , 0x14f0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_290_CNT" , 0x14f0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_291_CNT" , 0x14f00000011a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_292_CNT" , 0x14f00000011a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_293_CNT" , 0x14f00000011b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_294_CNT" , 0x14f00000011b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_295_CNT" , 0x14f00000011c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_296_CNT" , 0x14f00000011c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_297_CNT" , 0x14f00000011d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_298_CNT" , 0x14f00000011d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_299_CNT" , 0x14f00000011e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_300_CNT" , 0x14f00000011e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_301_CNT" , 0x14f00000011f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_302_CNT" , 0x14f00000011f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_303_CNT" , 0x14f0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_304_CNT" , 0x14f0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_305_CNT" , 0x14f0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_306_CNT" , 0x14f0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_307_CNT" , 0x14f0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_308_CNT" , 0x14f0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_309_CNT" , 0x14f0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_310_CNT" , 0x14f0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_311_CNT" , 0x14f0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_312_CNT" , 0x14f0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_313_CNT" , 0x14f0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_314_CNT" , 0x14f0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_315_CNT" , 0x14f0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_316_CNT" , 0x14f0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_317_CNT" , 0x14f0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_318_CNT" , 0x14f0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_319_CNT" , 0x14f0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_320_CNT" , 0x14f0000001288ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_321_CNT" , 0x14f0000001290ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_322_CNT" , 0x14f0000001298ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_323_CNT" , 0x14f00000012a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_324_CNT" , 0x14f00000012a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_325_CNT" , 0x14f00000012b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_326_CNT" , 0x14f00000012b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_327_CNT" , 0x14f00000012c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_328_CNT" , 0x14f00000012c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_329_CNT" , 0x14f00000012d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_330_CNT" , 0x14f00000012d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_331_CNT" , 0x14f00000012e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_332_CNT" , 0x14f00000012e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_333_CNT" , 0x14f00000012f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_334_CNT" , 0x14f00000012f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_335_CNT" , 0x14f0000001300ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_336_CNT" , 0x14f0000001308ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_337_CNT" , 0x14f0000001310ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_338_CNT" , 0x14f0000001318ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_339_CNT" , 0x14f0000001320ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_340_CNT" , 0x14f0000001328ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_341_CNT" , 0x14f0000001330ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_342_CNT" , 0x14f0000001338ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_343_CNT" , 0x14f0000001340ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_344_CNT" , 0x14f0000001348ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_345_CNT" , 0x14f0000001350ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_346_CNT" , 0x14f0000001358ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_347_CNT" , 0x14f0000001360ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_348_CNT" , 0x14f0000001368ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_349_CNT" , 0x14f0000001370ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_350_CNT" , 0x14f0000001378ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_351_CNT" , 0x14f0000001380ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_352_CNT" , 0x14f0000001388ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_353_CNT" , 0x14f0000001390ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_354_CNT" , 0x14f0000001398ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_355_CNT" , 0x14f00000013a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_356_CNT" , 0x14f00000013a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_357_CNT" , 0x14f00000013b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_358_CNT" , 0x14f00000013b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_359_CNT" , 0x14f00000013c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_360_CNT" , 0x14f00000013c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_361_CNT" , 0x14f00000013d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_362_CNT" , 0x14f00000013d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_363_CNT" , 0x14f00000013e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_364_CNT" , 0x14f00000013e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_365_CNT" , 0x14f00000013f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_366_CNT" , 0x14f00000013f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_367_CNT" , 0x14f0000001400ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_368_CNT" , 0x14f0000001408ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_369_CNT" , 0x14f0000001410ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_370_CNT" , 0x14f0000001418ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_371_CNT" , 0x14f0000001420ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_372_CNT" , 0x14f0000001428ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_373_CNT" , 0x14f0000001430ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_374_CNT" , 0x14f0000001438ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_375_CNT" , 0x14f0000001440ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_376_CNT" , 0x14f0000001448ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_377_CNT" , 0x14f0000001450ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_378_CNT" , 0x14f0000001458ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_379_CNT" , 0x14f0000001460ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_380_CNT" , 0x14f0000001468ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_381_CNT" , 0x14f0000001470ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_382_CNT" , 0x14f0000001478ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_383_CNT" , 0x14f0000001480ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
- {"IPD_PORT_QOS_INT0" , 0x14f0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 454},
- {"IPD_PORT_QOS_INT2" , 0x14f0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 454},
- {"IPD_PORT_QOS_INT4" , 0x14f0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 454},
- {"IPD_PORT_QOS_INT5" , 0x14f0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 454},
- {"IPD_PORT_QOS_INT_ENB0" , 0x14f0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 455},
- {"IPD_PORT_QOS_INT_ENB2" , 0x14f0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 455},
- {"IPD_PORT_QOS_INT_ENB4" , 0x14f0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 455},
- {"IPD_PORT_QOS_INT_ENB5" , 0x14f0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 455},
- {"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14f0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
- {"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14f0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
- {"IPD_PTR_COUNT" , 0x14f0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 458},
- {"IPD_PWP_PTR_FIFO_CTL" , 0x14f0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 459},
- {"IPD_QOS0_RED_MARKS" , 0x14f0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
- {"IPD_QOS1_RED_MARKS" , 0x14f0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
- {"IPD_QOS2_RED_MARKS" , 0x14f0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
- {"IPD_QOS3_RED_MARKS" , 0x14f0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
- {"IPD_QOS4_RED_MARKS" , 0x14f0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
- {"IPD_QOS5_RED_MARKS" , 0x14f00000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
- {"IPD_QOS6_RED_MARKS" , 0x14f00000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
- {"IPD_QOS7_RED_MARKS" , 0x14f00000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
- {"IPD_QUE0_FREE_PAGE_CNT" , 0x14f0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
- {"IPD_RED_PORT_ENABLE" , 0x14f00000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
- {"IPD_RED_PORT_ENABLE2" , 0x14f00000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 463},
- {"IPD_RED_QUE0_PARAM" , 0x14f00000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"IPD_RED_QUE1_PARAM" , 0x14f00000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"IPD_RED_QUE2_PARAM" , 0x14f00000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"IPD_RED_QUE3_PARAM" , 0x14f00000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"IPD_RED_QUE4_PARAM" , 0x14f0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"IPD_RED_QUE5_PARAM" , 0x14f0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"IPD_RED_QUE6_PARAM" , 0x14f0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"IPD_RED_QUE7_PARAM" , 0x14f0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
- {"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14f0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
- {"IPD_SUB_PORT_FCS" , 0x14f0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 466},
- {"IPD_SUB_PORT_QOS_CNT" , 0x14f0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
- {"IPD_WQE_FPA_QUEUE" , 0x14f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 468},
- {"IPD_WQE_PTR_VALID" , 0x14f0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
- {"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
- {"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
- {"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
- {"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
- {"L2C_BIG_CTL" , 0x1180080800030ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
- {"L2C_BST" , 0x11800808007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
- {"L2C_BST_MEM0" , 0x1180080c007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
- {"L2C_BST_TDT0" , 0x1180080a007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
- {"L2C_BST_TTG0" , 0x1180080a007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
- {"L2C_COP0_MAP0" , 0x1180080940000ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1" , 0x1180080940008ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP2" , 0x1180080940010ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP3" , 0x1180080940018ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP4" , 0x1180080940020ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP5" , 0x1180080940028ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP6" , 0x1180080940030ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP7" , 0x1180080940038ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP8" , 0x1180080940040ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP9" , 0x1180080940048ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP10" , 0x1180080940050ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP11" , 0x1180080940058ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP12" , 0x1180080940060ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP13" , 0x1180080940068ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP14" , 0x1180080940070ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP15" , 0x1180080940078ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16" , 0x1180080940080ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP17" , 0x1180080940088ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP18" , 0x1180080940090ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP19" , 0x1180080940098ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP20" , 0x11800809400a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP21" , 0x11800809400a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP22" , 0x11800809400b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP23" , 0x11800809400b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP24" , 0x11800809400c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP25" , 0x11800809400c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP26" , 0x11800809400d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP27" , 0x11800809400d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP28" , 0x11800809400e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP29" , 0x11800809400e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP30" , 0x11800809400f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP31" , 0x11800809400f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP32" , 0x1180080940100ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP33" , 0x1180080940108ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP34" , 0x1180080940110ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP35" , 0x1180080940118ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP36" , 0x1180080940120ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP37" , 0x1180080940128ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP38" , 0x1180080940130ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP39" , 0x1180080940138ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP40" , 0x1180080940140ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP41" , 0x1180080940148ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP42" , 0x1180080940150ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP43" , 0x1180080940158ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP44" , 0x1180080940160ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP45" , 0x1180080940168ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP46" , 0x1180080940170ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP47" , 0x1180080940178ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP48" , 0x1180080940180ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP49" , 0x1180080940188ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP50" , 0x1180080940190ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP51" , 0x1180080940198ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP52" , 0x11800809401a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP53" , 0x11800809401a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP54" , 0x11800809401b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP55" , 0x11800809401b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP56" , 0x11800809401c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP57" , 0x11800809401c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP58" , 0x11800809401d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP59" , 0x11800809401d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP60" , 0x11800809401e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP61" , 0x11800809401e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP62" , 0x11800809401f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP63" , 0x11800809401f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP64" , 0x1180080940200ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP65" , 0x1180080940208ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP66" , 0x1180080940210ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP67" , 0x1180080940218ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP68" , 0x1180080940220ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP69" , 0x1180080940228ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP70" , 0x1180080940230ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP71" , 0x1180080940238ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP72" , 0x1180080940240ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP73" , 0x1180080940248ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP74" , 0x1180080940250ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP75" , 0x1180080940258ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP76" , 0x1180080940260ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP77" , 0x1180080940268ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP78" , 0x1180080940270ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP79" , 0x1180080940278ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP80" , 0x1180080940280ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP81" , 0x1180080940288ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP82" , 0x1180080940290ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP83" , 0x1180080940298ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP84" , 0x11800809402a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP85" , 0x11800809402a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP86" , 0x11800809402b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP87" , 0x11800809402b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP88" , 0x11800809402c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP89" , 0x11800809402c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP90" , 0x11800809402d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP91" , 0x11800809402d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP92" , 0x11800809402e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP93" , 0x11800809402e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP94" , 0x11800809402f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP95" , 0x11800809402f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP96" , 0x1180080940300ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP97" , 0x1180080940308ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP98" , 0x1180080940310ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP99" , 0x1180080940318ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP100" , 0x1180080940320ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP101" , 0x1180080940328ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP102" , 0x1180080940330ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP103" , 0x1180080940338ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP104" , 0x1180080940340ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP105" , 0x1180080940348ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP106" , 0x1180080940350ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP107" , 0x1180080940358ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP108" , 0x1180080940360ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP109" , 0x1180080940368ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP110" , 0x1180080940370ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP111" , 0x1180080940378ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP112" , 0x1180080940380ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP113" , 0x1180080940388ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP114" , 0x1180080940390ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP115" , 0x1180080940398ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP116" , 0x11800809403a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP117" , 0x11800809403a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP118" , 0x11800809403b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP119" , 0x11800809403b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP120" , 0x11800809403c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP121" , 0x11800809403c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP122" , 0x11800809403d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP123" , 0x11800809403d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP124" , 0x11800809403e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP125" , 0x11800809403e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP126" , 0x11800809403f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP127" , 0x11800809403f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP128" , 0x1180080940400ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP129" , 0x1180080940408ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP130" , 0x1180080940410ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP131" , 0x1180080940418ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP132" , 0x1180080940420ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP133" , 0x1180080940428ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP134" , 0x1180080940430ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP135" , 0x1180080940438ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP136" , 0x1180080940440ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP137" , 0x1180080940448ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP138" , 0x1180080940450ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP139" , 0x1180080940458ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP140" , 0x1180080940460ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP141" , 0x1180080940468ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP142" , 0x1180080940470ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP143" , 0x1180080940478ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP144" , 0x1180080940480ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP145" , 0x1180080940488ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP146" , 0x1180080940490ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP147" , 0x1180080940498ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP148" , 0x11800809404a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP149" , 0x11800809404a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP150" , 0x11800809404b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP151" , 0x11800809404b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP152" , 0x11800809404c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP153" , 0x11800809404c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP154" , 0x11800809404d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP155" , 0x11800809404d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP156" , 0x11800809404e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP157" , 0x11800809404e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP158" , 0x11800809404f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP159" , 0x11800809404f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP160" , 0x1180080940500ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP161" , 0x1180080940508ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP162" , 0x1180080940510ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP163" , 0x1180080940518ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP164" , 0x1180080940520ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP165" , 0x1180080940528ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP166" , 0x1180080940530ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP167" , 0x1180080940538ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP168" , 0x1180080940540ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP169" , 0x1180080940548ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP170" , 0x1180080940550ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP171" , 0x1180080940558ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP172" , 0x1180080940560ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP173" , 0x1180080940568ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP174" , 0x1180080940570ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP175" , 0x1180080940578ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP176" , 0x1180080940580ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP177" , 0x1180080940588ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP178" , 0x1180080940590ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP179" , 0x1180080940598ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP180" , 0x11800809405a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP181" , 0x11800809405a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP182" , 0x11800809405b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP183" , 0x11800809405b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP184" , 0x11800809405c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP185" , 0x11800809405c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP186" , 0x11800809405d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP187" , 0x11800809405d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP188" , 0x11800809405e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP189" , 0x11800809405e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP190" , 0x11800809405f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP191" , 0x11800809405f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP192" , 0x1180080940600ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP193" , 0x1180080940608ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP194" , 0x1180080940610ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP195" , 0x1180080940618ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP196" , 0x1180080940620ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP197" , 0x1180080940628ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP198" , 0x1180080940630ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP199" , 0x1180080940638ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP200" , 0x1180080940640ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP201" , 0x1180080940648ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP202" , 0x1180080940650ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP203" , 0x1180080940658ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP204" , 0x1180080940660ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP205" , 0x1180080940668ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP206" , 0x1180080940670ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP207" , 0x1180080940678ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP208" , 0x1180080940680ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP209" , 0x1180080940688ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP210" , 0x1180080940690ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP211" , 0x1180080940698ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP212" , 0x11800809406a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP213" , 0x11800809406a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP214" , 0x11800809406b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP215" , 0x11800809406b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP216" , 0x11800809406c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP217" , 0x11800809406c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP218" , 0x11800809406d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP219" , 0x11800809406d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP220" , 0x11800809406e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP221" , 0x11800809406e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP222" , 0x11800809406f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP223" , 0x11800809406f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP224" , 0x1180080940700ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP225" , 0x1180080940708ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP226" , 0x1180080940710ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP227" , 0x1180080940718ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP228" , 0x1180080940720ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP229" , 0x1180080940728ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP230" , 0x1180080940730ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP231" , 0x1180080940738ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP232" , 0x1180080940740ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP233" , 0x1180080940748ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP234" , 0x1180080940750ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP235" , 0x1180080940758ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP236" , 0x1180080940760ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP237" , 0x1180080940768ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP238" , 0x1180080940770ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP239" , 0x1180080940778ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP240" , 0x1180080940780ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP241" , 0x1180080940788ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP242" , 0x1180080940790ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP243" , 0x1180080940798ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP244" , 0x11800809407a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP245" , 0x11800809407a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP246" , 0x11800809407b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP247" , 0x11800809407b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP248" , 0x11800809407c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP249" , 0x11800809407c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP250" , 0x11800809407d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP251" , 0x11800809407d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP252" , 0x11800809407e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP253" , 0x11800809407e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP254" , 0x11800809407f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP255" , 0x11800809407f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP256" , 0x1180080940800ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP257" , 0x1180080940808ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP258" , 0x1180080940810ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP259" , 0x1180080940818ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP260" , 0x1180080940820ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP261" , 0x1180080940828ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP262" , 0x1180080940830ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP263" , 0x1180080940838ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP264" , 0x1180080940840ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP265" , 0x1180080940848ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP266" , 0x1180080940850ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP267" , 0x1180080940858ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP268" , 0x1180080940860ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP269" , 0x1180080940868ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP270" , 0x1180080940870ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP271" , 0x1180080940878ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP272" , 0x1180080940880ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP273" , 0x1180080940888ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP274" , 0x1180080940890ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP275" , 0x1180080940898ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP276" , 0x11800809408a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP277" , 0x11800809408a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP278" , 0x11800809408b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP279" , 0x11800809408b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP280" , 0x11800809408c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP281" , 0x11800809408c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP282" , 0x11800809408d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP283" , 0x11800809408d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP284" , 0x11800809408e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP285" , 0x11800809408e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP286" , 0x11800809408f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP287" , 0x11800809408f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP288" , 0x1180080940900ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP289" , 0x1180080940908ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP290" , 0x1180080940910ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP291" , 0x1180080940918ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP292" , 0x1180080940920ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP293" , 0x1180080940928ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP294" , 0x1180080940930ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP295" , 0x1180080940938ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP296" , 0x1180080940940ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP297" , 0x1180080940948ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP298" , 0x1180080940950ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP299" , 0x1180080940958ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP300" , 0x1180080940960ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP301" , 0x1180080940968ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP302" , 0x1180080940970ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP303" , 0x1180080940978ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP304" , 0x1180080940980ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP305" , 0x1180080940988ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP306" , 0x1180080940990ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP307" , 0x1180080940998ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP308" , 0x11800809409a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP309" , 0x11800809409a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP310" , 0x11800809409b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP311" , 0x11800809409b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP312" , 0x11800809409c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP313" , 0x11800809409c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP314" , 0x11800809409d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP315" , 0x11800809409d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP316" , 0x11800809409e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP317" , 0x11800809409e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP318" , 0x11800809409f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP319" , 0x11800809409f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP320" , 0x1180080940a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP321" , 0x1180080940a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP322" , 0x1180080940a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP323" , 0x1180080940a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP324" , 0x1180080940a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP325" , 0x1180080940a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP326" , 0x1180080940a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP327" , 0x1180080940a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP328" , 0x1180080940a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP329" , 0x1180080940a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP330" , 0x1180080940a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP331" , 0x1180080940a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP332" , 0x1180080940a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP333" , 0x1180080940a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP334" , 0x1180080940a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP335" , 0x1180080940a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP336" , 0x1180080940a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP337" , 0x1180080940a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP338" , 0x1180080940a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP339" , 0x1180080940a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP340" , 0x1180080940aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP341" , 0x1180080940aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP342" , 0x1180080940ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP343" , 0x1180080940ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP344" , 0x1180080940ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP345" , 0x1180080940ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP346" , 0x1180080940ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP347" , 0x1180080940ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP348" , 0x1180080940ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP349" , 0x1180080940ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP350" , 0x1180080940af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP351" , 0x1180080940af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP352" , 0x1180080940b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP353" , 0x1180080940b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP354" , 0x1180080940b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP355" , 0x1180080940b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP356" , 0x1180080940b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP357" , 0x1180080940b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP358" , 0x1180080940b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP359" , 0x1180080940b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP360" , 0x1180080940b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP361" , 0x1180080940b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP362" , 0x1180080940b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP363" , 0x1180080940b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP364" , 0x1180080940b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP365" , 0x1180080940b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP366" , 0x1180080940b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP367" , 0x1180080940b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP368" , 0x1180080940b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP369" , 0x1180080940b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP370" , 0x1180080940b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP371" , 0x1180080940b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP372" , 0x1180080940ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP373" , 0x1180080940ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP374" , 0x1180080940bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP375" , 0x1180080940bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP376" , 0x1180080940bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP377" , 0x1180080940bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP378" , 0x1180080940bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP379" , 0x1180080940bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP380" , 0x1180080940be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP381" , 0x1180080940be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP382" , 0x1180080940bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP383" , 0x1180080940bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP384" , 0x1180080940c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP385" , 0x1180080940c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP386" , 0x1180080940c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP387" , 0x1180080940c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP388" , 0x1180080940c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP389" , 0x1180080940c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP390" , 0x1180080940c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP391" , 0x1180080940c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP392" , 0x1180080940c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP393" , 0x1180080940c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP394" , 0x1180080940c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP395" , 0x1180080940c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP396" , 0x1180080940c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP397" , 0x1180080940c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP398" , 0x1180080940c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP399" , 0x1180080940c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP400" , 0x1180080940c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP401" , 0x1180080940c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP402" , 0x1180080940c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP403" , 0x1180080940c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP404" , 0x1180080940ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP405" , 0x1180080940ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP406" , 0x1180080940cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP407" , 0x1180080940cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP408" , 0x1180080940cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP409" , 0x1180080940cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP410" , 0x1180080940cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP411" , 0x1180080940cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP412" , 0x1180080940ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP413" , 0x1180080940ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP414" , 0x1180080940cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP415" , 0x1180080940cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP416" , 0x1180080940d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP417" , 0x1180080940d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP418" , 0x1180080940d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP419" , 0x1180080940d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP420" , 0x1180080940d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP421" , 0x1180080940d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP422" , 0x1180080940d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP423" , 0x1180080940d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP424" , 0x1180080940d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP425" , 0x1180080940d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP426" , 0x1180080940d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP427" , 0x1180080940d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP428" , 0x1180080940d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP429" , 0x1180080940d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP430" , 0x1180080940d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP431" , 0x1180080940d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP432" , 0x1180080940d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP433" , 0x1180080940d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP434" , 0x1180080940d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP435" , 0x1180080940d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP436" , 0x1180080940da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP437" , 0x1180080940da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP438" , 0x1180080940db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP439" , 0x1180080940db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP440" , 0x1180080940dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP441" , 0x1180080940dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP442" , 0x1180080940dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP443" , 0x1180080940dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP444" , 0x1180080940de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP445" , 0x1180080940de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP446" , 0x1180080940df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP447" , 0x1180080940df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP448" , 0x1180080940e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP449" , 0x1180080940e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP450" , 0x1180080940e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP451" , 0x1180080940e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP452" , 0x1180080940e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP453" , 0x1180080940e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP454" , 0x1180080940e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP455" , 0x1180080940e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP456" , 0x1180080940e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP457" , 0x1180080940e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP458" , 0x1180080940e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP459" , 0x1180080940e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP460" , 0x1180080940e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP461" , 0x1180080940e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP462" , 0x1180080940e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP463" , 0x1180080940e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP464" , 0x1180080940e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP465" , 0x1180080940e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP466" , 0x1180080940e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP467" , 0x1180080940e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP468" , 0x1180080940ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP469" , 0x1180080940ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP470" , 0x1180080940eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP471" , 0x1180080940eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP472" , 0x1180080940ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP473" , 0x1180080940ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP474" , 0x1180080940ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP475" , 0x1180080940ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP476" , 0x1180080940ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP477" , 0x1180080940ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP478" , 0x1180080940ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP479" , 0x1180080940ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP480" , 0x1180080940f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP481" , 0x1180080940f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP482" , 0x1180080940f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP483" , 0x1180080940f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP484" , 0x1180080940f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP485" , 0x1180080940f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP486" , 0x1180080940f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP487" , 0x1180080940f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP488" , 0x1180080940f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP489" , 0x1180080940f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP490" , 0x1180080940f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP491" , 0x1180080940f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP492" , 0x1180080940f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP493" , 0x1180080940f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP494" , 0x1180080940f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP495" , 0x1180080940f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP496" , 0x1180080940f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP497" , 0x1180080940f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP498" , 0x1180080940f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP499" , 0x1180080940f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP500" , 0x1180080940fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP501" , 0x1180080940fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP502" , 0x1180080940fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP503" , 0x1180080940fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP504" , 0x1180080940fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP505" , 0x1180080940fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP506" , 0x1180080940fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP507" , 0x1180080940fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP508" , 0x1180080940fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP509" , 0x1180080940fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP510" , 0x1180080940ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP511" , 0x1180080940ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP512" , 0x1180080941000ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP513" , 0x1180080941008ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP514" , 0x1180080941010ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP515" , 0x1180080941018ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP516" , 0x1180080941020ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP517" , 0x1180080941028ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP518" , 0x1180080941030ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP519" , 0x1180080941038ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP520" , 0x1180080941040ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP521" , 0x1180080941048ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP522" , 0x1180080941050ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP523" , 0x1180080941058ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP524" , 0x1180080941060ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP525" , 0x1180080941068ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP526" , 0x1180080941070ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP527" , 0x1180080941078ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP528" , 0x1180080941080ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP529" , 0x1180080941088ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP530" , 0x1180080941090ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP531" , 0x1180080941098ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP532" , 0x11800809410a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP533" , 0x11800809410a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP534" , 0x11800809410b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP535" , 0x11800809410b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP536" , 0x11800809410c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP537" , 0x11800809410c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP538" , 0x11800809410d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP539" , 0x11800809410d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP540" , 0x11800809410e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP541" , 0x11800809410e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP542" , 0x11800809410f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP543" , 0x11800809410f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP544" , 0x1180080941100ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP545" , 0x1180080941108ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP546" , 0x1180080941110ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP547" , 0x1180080941118ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP548" , 0x1180080941120ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP549" , 0x1180080941128ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP550" , 0x1180080941130ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP551" , 0x1180080941138ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP552" , 0x1180080941140ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP553" , 0x1180080941148ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP554" , 0x1180080941150ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP555" , 0x1180080941158ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP556" , 0x1180080941160ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP557" , 0x1180080941168ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP558" , 0x1180080941170ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP559" , 0x1180080941178ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP560" , 0x1180080941180ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP561" , 0x1180080941188ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP562" , 0x1180080941190ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP563" , 0x1180080941198ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP564" , 0x11800809411a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP565" , 0x11800809411a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP566" , 0x11800809411b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP567" , 0x11800809411b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP568" , 0x11800809411c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP569" , 0x11800809411c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP570" , 0x11800809411d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP571" , 0x11800809411d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP572" , 0x11800809411e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP573" , 0x11800809411e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP574" , 0x11800809411f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP575" , 0x11800809411f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP576" , 0x1180080941200ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP577" , 0x1180080941208ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP578" , 0x1180080941210ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP579" , 0x1180080941218ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP580" , 0x1180080941220ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP581" , 0x1180080941228ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP582" , 0x1180080941230ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP583" , 0x1180080941238ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP584" , 0x1180080941240ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP585" , 0x1180080941248ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP586" , 0x1180080941250ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP587" , 0x1180080941258ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP588" , 0x1180080941260ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP589" , 0x1180080941268ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP590" , 0x1180080941270ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP591" , 0x1180080941278ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP592" , 0x1180080941280ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP593" , 0x1180080941288ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP594" , 0x1180080941290ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP595" , 0x1180080941298ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP596" , 0x11800809412a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP597" , 0x11800809412a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP598" , 0x11800809412b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP599" , 0x11800809412b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP600" , 0x11800809412c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP601" , 0x11800809412c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP602" , 0x11800809412d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP603" , 0x11800809412d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP604" , 0x11800809412e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP605" , 0x11800809412e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP606" , 0x11800809412f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP607" , 0x11800809412f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP608" , 0x1180080941300ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP609" , 0x1180080941308ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP610" , 0x1180080941310ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP611" , 0x1180080941318ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP612" , 0x1180080941320ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP613" , 0x1180080941328ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP614" , 0x1180080941330ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP615" , 0x1180080941338ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP616" , 0x1180080941340ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP617" , 0x1180080941348ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP618" , 0x1180080941350ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP619" , 0x1180080941358ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP620" , 0x1180080941360ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP621" , 0x1180080941368ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP622" , 0x1180080941370ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP623" , 0x1180080941378ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP624" , 0x1180080941380ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP625" , 0x1180080941388ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP626" , 0x1180080941390ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP627" , 0x1180080941398ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP628" , 0x11800809413a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP629" , 0x11800809413a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP630" , 0x11800809413b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP631" , 0x11800809413b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP632" , 0x11800809413c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP633" , 0x11800809413c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP634" , 0x11800809413d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP635" , 0x11800809413d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP636" , 0x11800809413e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP637" , 0x11800809413e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP638" , 0x11800809413f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP639" , 0x11800809413f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP640" , 0x1180080941400ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP641" , 0x1180080941408ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP642" , 0x1180080941410ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP643" , 0x1180080941418ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP644" , 0x1180080941420ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP645" , 0x1180080941428ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP646" , 0x1180080941430ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP647" , 0x1180080941438ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP648" , 0x1180080941440ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP649" , 0x1180080941448ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP650" , 0x1180080941450ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP651" , 0x1180080941458ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP652" , 0x1180080941460ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP653" , 0x1180080941468ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP654" , 0x1180080941470ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP655" , 0x1180080941478ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP656" , 0x1180080941480ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP657" , 0x1180080941488ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP658" , 0x1180080941490ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP659" , 0x1180080941498ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP660" , 0x11800809414a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP661" , 0x11800809414a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP662" , 0x11800809414b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP663" , 0x11800809414b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP664" , 0x11800809414c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP665" , 0x11800809414c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP666" , 0x11800809414d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP667" , 0x11800809414d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP668" , 0x11800809414e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP669" , 0x11800809414e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP670" , 0x11800809414f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP671" , 0x11800809414f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP672" , 0x1180080941500ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP673" , 0x1180080941508ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP674" , 0x1180080941510ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP675" , 0x1180080941518ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP676" , 0x1180080941520ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP677" , 0x1180080941528ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP678" , 0x1180080941530ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP679" , 0x1180080941538ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP680" , 0x1180080941540ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP681" , 0x1180080941548ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP682" , 0x1180080941550ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP683" , 0x1180080941558ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP684" , 0x1180080941560ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP685" , 0x1180080941568ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP686" , 0x1180080941570ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP687" , 0x1180080941578ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP688" , 0x1180080941580ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP689" , 0x1180080941588ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP690" , 0x1180080941590ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP691" , 0x1180080941598ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP692" , 0x11800809415a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP693" , 0x11800809415a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP694" , 0x11800809415b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP695" , 0x11800809415b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP696" , 0x11800809415c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP697" , 0x11800809415c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP698" , 0x11800809415d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP699" , 0x11800809415d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP700" , 0x11800809415e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP701" , 0x11800809415e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP702" , 0x11800809415f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP703" , 0x11800809415f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP704" , 0x1180080941600ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP705" , 0x1180080941608ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP706" , 0x1180080941610ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP707" , 0x1180080941618ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP708" , 0x1180080941620ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP709" , 0x1180080941628ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP710" , 0x1180080941630ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP711" , 0x1180080941638ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP712" , 0x1180080941640ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP713" , 0x1180080941648ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP714" , 0x1180080941650ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP715" , 0x1180080941658ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP716" , 0x1180080941660ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP717" , 0x1180080941668ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP718" , 0x1180080941670ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP719" , 0x1180080941678ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP720" , 0x1180080941680ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP721" , 0x1180080941688ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP722" , 0x1180080941690ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP723" , 0x1180080941698ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP724" , 0x11800809416a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP725" , 0x11800809416a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP726" , 0x11800809416b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP727" , 0x11800809416b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP728" , 0x11800809416c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP729" , 0x11800809416c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP730" , 0x11800809416d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP731" , 0x11800809416d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP732" , 0x11800809416e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP733" , 0x11800809416e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP734" , 0x11800809416f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP735" , 0x11800809416f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP736" , 0x1180080941700ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP737" , 0x1180080941708ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP738" , 0x1180080941710ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP739" , 0x1180080941718ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP740" , 0x1180080941720ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP741" , 0x1180080941728ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP742" , 0x1180080941730ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP743" , 0x1180080941738ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP744" , 0x1180080941740ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP745" , 0x1180080941748ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP746" , 0x1180080941750ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP747" , 0x1180080941758ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP748" , 0x1180080941760ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP749" , 0x1180080941768ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP750" , 0x1180080941770ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP751" , 0x1180080941778ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP752" , 0x1180080941780ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP753" , 0x1180080941788ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP754" , 0x1180080941790ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP755" , 0x1180080941798ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP756" , 0x11800809417a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP757" , 0x11800809417a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP758" , 0x11800809417b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP759" , 0x11800809417b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP760" , 0x11800809417c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP761" , 0x11800809417c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP762" , 0x11800809417d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP763" , 0x11800809417d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP764" , 0x11800809417e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP765" , 0x11800809417e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP766" , 0x11800809417f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP767" , 0x11800809417f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP768" , 0x1180080941800ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP769" , 0x1180080941808ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP770" , 0x1180080941810ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP771" , 0x1180080941818ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP772" , 0x1180080941820ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP773" , 0x1180080941828ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP774" , 0x1180080941830ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP775" , 0x1180080941838ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP776" , 0x1180080941840ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP777" , 0x1180080941848ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP778" , 0x1180080941850ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP779" , 0x1180080941858ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP780" , 0x1180080941860ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP781" , 0x1180080941868ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP782" , 0x1180080941870ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP783" , 0x1180080941878ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP784" , 0x1180080941880ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP785" , 0x1180080941888ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP786" , 0x1180080941890ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP787" , 0x1180080941898ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP788" , 0x11800809418a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP789" , 0x11800809418a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP790" , 0x11800809418b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP791" , 0x11800809418b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP792" , 0x11800809418c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP793" , 0x11800809418c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP794" , 0x11800809418d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP795" , 0x11800809418d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP796" , 0x11800809418e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP797" , 0x11800809418e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP798" , 0x11800809418f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP799" , 0x11800809418f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP800" , 0x1180080941900ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP801" , 0x1180080941908ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP802" , 0x1180080941910ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP803" , 0x1180080941918ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP804" , 0x1180080941920ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP805" , 0x1180080941928ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP806" , 0x1180080941930ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP807" , 0x1180080941938ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP808" , 0x1180080941940ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP809" , 0x1180080941948ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP810" , 0x1180080941950ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP811" , 0x1180080941958ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP812" , 0x1180080941960ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP813" , 0x1180080941968ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP814" , 0x1180080941970ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP815" , 0x1180080941978ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP816" , 0x1180080941980ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP817" , 0x1180080941988ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP818" , 0x1180080941990ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP819" , 0x1180080941998ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP820" , 0x11800809419a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP821" , 0x11800809419a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP822" , 0x11800809419b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP823" , 0x11800809419b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP824" , 0x11800809419c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP825" , 0x11800809419c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP826" , 0x11800809419d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP827" , 0x11800809419d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP828" , 0x11800809419e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP829" , 0x11800809419e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP830" , 0x11800809419f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP831" , 0x11800809419f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP832" , 0x1180080941a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP833" , 0x1180080941a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP834" , 0x1180080941a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP835" , 0x1180080941a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP836" , 0x1180080941a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP837" , 0x1180080941a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP838" , 0x1180080941a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP839" , 0x1180080941a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP840" , 0x1180080941a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP841" , 0x1180080941a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP842" , 0x1180080941a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP843" , 0x1180080941a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP844" , 0x1180080941a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP845" , 0x1180080941a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP846" , 0x1180080941a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP847" , 0x1180080941a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP848" , 0x1180080941a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP849" , 0x1180080941a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP850" , 0x1180080941a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP851" , 0x1180080941a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP852" , 0x1180080941aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP853" , 0x1180080941aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP854" , 0x1180080941ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP855" , 0x1180080941ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP856" , 0x1180080941ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP857" , 0x1180080941ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP858" , 0x1180080941ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP859" , 0x1180080941ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP860" , 0x1180080941ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP861" , 0x1180080941ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP862" , 0x1180080941af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP863" , 0x1180080941af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP864" , 0x1180080941b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP865" , 0x1180080941b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP866" , 0x1180080941b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP867" , 0x1180080941b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP868" , 0x1180080941b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP869" , 0x1180080941b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP870" , 0x1180080941b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP871" , 0x1180080941b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP872" , 0x1180080941b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP873" , 0x1180080941b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP874" , 0x1180080941b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP875" , 0x1180080941b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP876" , 0x1180080941b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP877" , 0x1180080941b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP878" , 0x1180080941b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP879" , 0x1180080941b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP880" , 0x1180080941b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP881" , 0x1180080941b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP882" , 0x1180080941b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP883" , 0x1180080941b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP884" , 0x1180080941ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP885" , 0x1180080941ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP886" , 0x1180080941bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP887" , 0x1180080941bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP888" , 0x1180080941bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP889" , 0x1180080941bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP890" , 0x1180080941bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP891" , 0x1180080941bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP892" , 0x1180080941be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP893" , 0x1180080941be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP894" , 0x1180080941bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP895" , 0x1180080941bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP896" , 0x1180080941c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP897" , 0x1180080941c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP898" , 0x1180080941c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP899" , 0x1180080941c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP900" , 0x1180080941c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP901" , 0x1180080941c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP902" , 0x1180080941c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP903" , 0x1180080941c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP904" , 0x1180080941c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP905" , 0x1180080941c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP906" , 0x1180080941c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP907" , 0x1180080941c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP908" , 0x1180080941c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP909" , 0x1180080941c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP910" , 0x1180080941c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP911" , 0x1180080941c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP912" , 0x1180080941c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP913" , 0x1180080941c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP914" , 0x1180080941c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP915" , 0x1180080941c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP916" , 0x1180080941ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP917" , 0x1180080941ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP918" , 0x1180080941cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP919" , 0x1180080941cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP920" , 0x1180080941cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP921" , 0x1180080941cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP922" , 0x1180080941cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP923" , 0x1180080941cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP924" , 0x1180080941ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP925" , 0x1180080941ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP926" , 0x1180080941cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP927" , 0x1180080941cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP928" , 0x1180080941d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP929" , 0x1180080941d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP930" , 0x1180080941d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP931" , 0x1180080941d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP932" , 0x1180080941d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP933" , 0x1180080941d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP934" , 0x1180080941d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP935" , 0x1180080941d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP936" , 0x1180080941d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP937" , 0x1180080941d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP938" , 0x1180080941d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP939" , 0x1180080941d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP940" , 0x1180080941d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP941" , 0x1180080941d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP942" , 0x1180080941d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP943" , 0x1180080941d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP944" , 0x1180080941d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP945" , 0x1180080941d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP946" , 0x1180080941d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP947" , 0x1180080941d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP948" , 0x1180080941da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP949" , 0x1180080941da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP950" , 0x1180080941db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP951" , 0x1180080941db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP952" , 0x1180080941dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP953" , 0x1180080941dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP954" , 0x1180080941dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP955" , 0x1180080941dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP956" , 0x1180080941de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP957" , 0x1180080941de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP958" , 0x1180080941df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP959" , 0x1180080941df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP960" , 0x1180080941e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP961" , 0x1180080941e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP962" , 0x1180080941e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP963" , 0x1180080941e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP964" , 0x1180080941e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP965" , 0x1180080941e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP966" , 0x1180080941e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP967" , 0x1180080941e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP968" , 0x1180080941e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP969" , 0x1180080941e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP970" , 0x1180080941e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP971" , 0x1180080941e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP972" , 0x1180080941e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP973" , 0x1180080941e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP974" , 0x1180080941e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP975" , 0x1180080941e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP976" , 0x1180080941e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP977" , 0x1180080941e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP978" , 0x1180080941e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP979" , 0x1180080941e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP980" , 0x1180080941ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP981" , 0x1180080941ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP982" , 0x1180080941eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP983" , 0x1180080941eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP984" , 0x1180080941ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP985" , 0x1180080941ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP986" , 0x1180080941ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP987" , 0x1180080941ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP988" , 0x1180080941ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP989" , 0x1180080941ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP990" , 0x1180080941ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP991" , 0x1180080941ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP992" , 0x1180080941f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP993" , 0x1180080941f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP994" , 0x1180080941f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP995" , 0x1180080941f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP996" , 0x1180080941f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP997" , 0x1180080941f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP998" , 0x1180080941f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP999" , 0x1180080941f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1000" , 0x1180080941f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1001" , 0x1180080941f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1002" , 0x1180080941f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1003" , 0x1180080941f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1004" , 0x1180080941f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1005" , 0x1180080941f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1006" , 0x1180080941f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1007" , 0x1180080941f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1008" , 0x1180080941f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1009" , 0x1180080941f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1010" , 0x1180080941f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1011" , 0x1180080941f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1012" , 0x1180080941fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1013" , 0x1180080941fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1014" , 0x1180080941fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1015" , 0x1180080941fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1016" , 0x1180080941fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1017" , 0x1180080941fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1018" , 0x1180080941fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1019" , 0x1180080941fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1020" , 0x1180080941fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1021" , 0x1180080941fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1022" , 0x1180080941ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP1023" , 0x1180080941ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16128" , 0x118008095f800ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16129" , 0x118008095f808ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16130" , 0x118008095f810ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16131" , 0x118008095f818ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16132" , 0x118008095f820ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16133" , 0x118008095f828ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16134" , 0x118008095f830ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16135" , 0x118008095f838ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16136" , 0x118008095f840ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16137" , 0x118008095f848ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16138" , 0x118008095f850ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16139" , 0x118008095f858ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16140" , 0x118008095f860ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16141" , 0x118008095f868ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16142" , 0x118008095f870ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16143" , 0x118008095f878ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16144" , 0x118008095f880ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16145" , 0x118008095f888ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16146" , 0x118008095f890ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16147" , 0x118008095f898ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16148" , 0x118008095f8a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16149" , 0x118008095f8a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16150" , 0x118008095f8b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16151" , 0x118008095f8b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16152" , 0x118008095f8c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16153" , 0x118008095f8c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16154" , 0x118008095f8d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16155" , 0x118008095f8d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16156" , 0x118008095f8e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16157" , 0x118008095f8e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16158" , 0x118008095f8f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16159" , 0x118008095f8f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16160" , 0x118008095f900ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16161" , 0x118008095f908ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16162" , 0x118008095f910ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16163" , 0x118008095f918ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16164" , 0x118008095f920ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16165" , 0x118008095f928ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16166" , 0x118008095f930ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16167" , 0x118008095f938ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16168" , 0x118008095f940ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16169" , 0x118008095f948ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16170" , 0x118008095f950ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16171" , 0x118008095f958ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16172" , 0x118008095f960ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16173" , 0x118008095f968ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16174" , 0x118008095f970ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16175" , 0x118008095f978ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16176" , 0x118008095f980ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16177" , 0x118008095f988ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16178" , 0x118008095f990ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16179" , 0x118008095f998ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16180" , 0x118008095f9a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16181" , 0x118008095f9a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16182" , 0x118008095f9b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16183" , 0x118008095f9b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16184" , 0x118008095f9c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16185" , 0x118008095f9c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16186" , 0x118008095f9d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16187" , 0x118008095f9d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16188" , 0x118008095f9e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16189" , 0x118008095f9e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16190" , 0x118008095f9f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16191" , 0x118008095f9f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16192" , 0x118008095fa00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16193" , 0x118008095fa08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16194" , 0x118008095fa10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16195" , 0x118008095fa18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16196" , 0x118008095fa20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16197" , 0x118008095fa28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16198" , 0x118008095fa30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16199" , 0x118008095fa38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16200" , 0x118008095fa40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16201" , 0x118008095fa48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16202" , 0x118008095fa50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16203" , 0x118008095fa58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16204" , 0x118008095fa60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16205" , 0x118008095fa68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16206" , 0x118008095fa70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16207" , 0x118008095fa78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16208" , 0x118008095fa80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16209" , 0x118008095fa88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16210" , 0x118008095fa90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16211" , 0x118008095fa98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16212" , 0x118008095faa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16213" , 0x118008095faa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16214" , 0x118008095fab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16215" , 0x118008095fab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16216" , 0x118008095fac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16217" , 0x118008095fac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16218" , 0x118008095fad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16219" , 0x118008095fad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16220" , 0x118008095fae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16221" , 0x118008095fae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16222" , 0x118008095faf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16223" , 0x118008095faf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16224" , 0x118008095fb00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16225" , 0x118008095fb08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16226" , 0x118008095fb10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16227" , 0x118008095fb18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16228" , 0x118008095fb20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16229" , 0x118008095fb28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16230" , 0x118008095fb30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16231" , 0x118008095fb38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16232" , 0x118008095fb40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16233" , 0x118008095fb48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16234" , 0x118008095fb50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16235" , 0x118008095fb58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16236" , 0x118008095fb60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16237" , 0x118008095fb68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16238" , 0x118008095fb70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16239" , 0x118008095fb78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16240" , 0x118008095fb80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16241" , 0x118008095fb88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16242" , 0x118008095fb90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16243" , 0x118008095fb98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16244" , 0x118008095fba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16245" , 0x118008095fba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16246" , 0x118008095fbb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16247" , 0x118008095fbb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16248" , 0x118008095fbc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16249" , 0x118008095fbc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16250" , 0x118008095fbd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16251" , 0x118008095fbd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16252" , 0x118008095fbe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16253" , 0x118008095fbe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16254" , 0x118008095fbf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16255" , 0x118008095fbf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16256" , 0x118008095fc00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16257" , 0x118008095fc08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16258" , 0x118008095fc10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16259" , 0x118008095fc18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16260" , 0x118008095fc20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16261" , 0x118008095fc28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16262" , 0x118008095fc30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16263" , 0x118008095fc38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16264" , 0x118008095fc40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16265" , 0x118008095fc48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16266" , 0x118008095fc50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16267" , 0x118008095fc58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16268" , 0x118008095fc60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16269" , 0x118008095fc68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16270" , 0x118008095fc70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16271" , 0x118008095fc78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16272" , 0x118008095fc80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16273" , 0x118008095fc88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16274" , 0x118008095fc90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16275" , 0x118008095fc98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16276" , 0x118008095fca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16277" , 0x118008095fca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16278" , 0x118008095fcb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16279" , 0x118008095fcb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16280" , 0x118008095fcc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16281" , 0x118008095fcc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16282" , 0x118008095fcd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16283" , 0x118008095fcd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16284" , 0x118008095fce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16285" , 0x118008095fce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16286" , 0x118008095fcf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16287" , 0x118008095fcf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16288" , 0x118008095fd00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16289" , 0x118008095fd08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16290" , 0x118008095fd10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16291" , 0x118008095fd18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16292" , 0x118008095fd20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16293" , 0x118008095fd28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16294" , 0x118008095fd30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16295" , 0x118008095fd38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16296" , 0x118008095fd40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16297" , 0x118008095fd48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16298" , 0x118008095fd50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16299" , 0x118008095fd58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16300" , 0x118008095fd60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16301" , 0x118008095fd68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16302" , 0x118008095fd70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16303" , 0x118008095fd78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16304" , 0x118008095fd80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16305" , 0x118008095fd88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16306" , 0x118008095fd90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16307" , 0x118008095fd98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16308" , 0x118008095fda0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16309" , 0x118008095fda8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16310" , 0x118008095fdb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16311" , 0x118008095fdb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16312" , 0x118008095fdc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16313" , 0x118008095fdc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16314" , 0x118008095fdd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16315" , 0x118008095fdd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16316" , 0x118008095fde0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16317" , 0x118008095fde8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16318" , 0x118008095fdf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16319" , 0x118008095fdf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16320" , 0x118008095fe00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16321" , 0x118008095fe08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16322" , 0x118008095fe10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16323" , 0x118008095fe18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16324" , 0x118008095fe20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16325" , 0x118008095fe28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16326" , 0x118008095fe30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16327" , 0x118008095fe38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16328" , 0x118008095fe40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16329" , 0x118008095fe48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16330" , 0x118008095fe50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16331" , 0x118008095fe58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16332" , 0x118008095fe60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16333" , 0x118008095fe68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16334" , 0x118008095fe70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16335" , 0x118008095fe78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16336" , 0x118008095fe80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16337" , 0x118008095fe88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16338" , 0x118008095fe90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16339" , 0x118008095fe98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16340" , 0x118008095fea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16341" , 0x118008095fea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16342" , 0x118008095feb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16343" , 0x118008095feb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16344" , 0x118008095fec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16345" , 0x118008095fec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16346" , 0x118008095fed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16347" , 0x118008095fed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16348" , 0x118008095fee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16349" , 0x118008095fee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16350" , 0x118008095fef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16351" , 0x118008095fef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16352" , 0x118008095ff00ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16353" , 0x118008095ff08ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16354" , 0x118008095ff10ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16355" , 0x118008095ff18ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16356" , 0x118008095ff20ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16357" , 0x118008095ff28ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16358" , 0x118008095ff30ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16359" , 0x118008095ff38ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16360" , 0x118008095ff40ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16361" , 0x118008095ff48ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16362" , 0x118008095ff50ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16363" , 0x118008095ff58ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16364" , 0x118008095ff60ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16365" , 0x118008095ff68ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16366" , 0x118008095ff70ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16367" , 0x118008095ff78ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16368" , 0x118008095ff80ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16369" , 0x118008095ff88ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16370" , 0x118008095ff90ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16371" , 0x118008095ff98ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16372" , 0x118008095ffa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16373" , 0x118008095ffa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16374" , 0x118008095ffb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16375" , 0x118008095ffb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16376" , 0x118008095ffc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16377" , 0x118008095ffc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16378" , 0x118008095ffd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16379" , 0x118008095ffd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16380" , 0x118008095ffe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16381" , 0x118008095ffe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16382" , 0x118008095fff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_COP0_MAP16383" , 0x118008095fff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
- {"L2C_CTL" , 0x1180080800000ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
- {"L2C_DUT_MAP0" , 0x1180080e00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1" , 0x1180080e00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP2" , 0x1180080e00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP3" , 0x1180080e00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP4" , 0x1180080e00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP5" , 0x1180080e00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP6" , 0x1180080e00030ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP7" , 0x1180080e00038ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP8" , 0x1180080e00040ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP9" , 0x1180080e00048ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP10" , 0x1180080e00050ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP11" , 0x1180080e00058ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP12" , 0x1180080e00060ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP13" , 0x1180080e00068ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP14" , 0x1180080e00070ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP15" , 0x1180080e00078ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP16" , 0x1180080e00080ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP17" , 0x1180080e00088ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP18" , 0x1180080e00090ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP19" , 0x1180080e00098ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP20" , 0x1180080e000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP21" , 0x1180080e000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP22" , 0x1180080e000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP23" , 0x1180080e000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP24" , 0x1180080e000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP25" , 0x1180080e000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP26" , 0x1180080e000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP27" , 0x1180080e000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP28" , 0x1180080e000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP29" , 0x1180080e000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP30" , 0x1180080e000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP31" , 0x1180080e000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP32" , 0x1180080e00100ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP33" , 0x1180080e00108ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP34" , 0x1180080e00110ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP35" , 0x1180080e00118ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP36" , 0x1180080e00120ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP37" , 0x1180080e00128ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP38" , 0x1180080e00130ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP39" , 0x1180080e00138ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP40" , 0x1180080e00140ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP41" , 0x1180080e00148ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP42" , 0x1180080e00150ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP43" , 0x1180080e00158ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP44" , 0x1180080e00160ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP45" , 0x1180080e00168ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP46" , 0x1180080e00170ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP47" , 0x1180080e00178ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP48" , 0x1180080e00180ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP49" , 0x1180080e00188ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP50" , 0x1180080e00190ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP51" , 0x1180080e00198ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP52" , 0x1180080e001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP53" , 0x1180080e001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP54" , 0x1180080e001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP55" , 0x1180080e001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP56" , 0x1180080e001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP57" , 0x1180080e001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP58" , 0x1180080e001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP59" , 0x1180080e001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP60" , 0x1180080e001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP61" , 0x1180080e001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP62" , 0x1180080e001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP63" , 0x1180080e001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP64" , 0x1180080e00200ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP65" , 0x1180080e00208ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP66" , 0x1180080e00210ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP67" , 0x1180080e00218ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP68" , 0x1180080e00220ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP69" , 0x1180080e00228ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP70" , 0x1180080e00230ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP71" , 0x1180080e00238ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP72" , 0x1180080e00240ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP73" , 0x1180080e00248ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP74" , 0x1180080e00250ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP75" , 0x1180080e00258ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP76" , 0x1180080e00260ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP77" , 0x1180080e00268ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP78" , 0x1180080e00270ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP79" , 0x1180080e00278ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP80" , 0x1180080e00280ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP81" , 0x1180080e00288ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP82" , 0x1180080e00290ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP83" , 0x1180080e00298ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP84" , 0x1180080e002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP85" , 0x1180080e002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP86" , 0x1180080e002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP87" , 0x1180080e002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP88" , 0x1180080e002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP89" , 0x1180080e002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP90" , 0x1180080e002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP91" , 0x1180080e002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP92" , 0x1180080e002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP93" , 0x1180080e002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP94" , 0x1180080e002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP95" , 0x1180080e002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP96" , 0x1180080e00300ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP97" , 0x1180080e00308ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP98" , 0x1180080e00310ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP99" , 0x1180080e00318ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP100" , 0x1180080e00320ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP101" , 0x1180080e00328ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP102" , 0x1180080e00330ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP103" , 0x1180080e00338ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP104" , 0x1180080e00340ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP105" , 0x1180080e00348ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP106" , 0x1180080e00350ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP107" , 0x1180080e00358ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP108" , 0x1180080e00360ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP109" , 0x1180080e00368ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP110" , 0x1180080e00370ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP111" , 0x1180080e00378ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP112" , 0x1180080e00380ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP113" , 0x1180080e00388ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP114" , 0x1180080e00390ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP115" , 0x1180080e00398ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP116" , 0x1180080e003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP117" , 0x1180080e003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP118" , 0x1180080e003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP119" , 0x1180080e003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP120" , 0x1180080e003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP121" , 0x1180080e003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP122" , 0x1180080e003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP123" , 0x1180080e003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP124" , 0x1180080e003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP125" , 0x1180080e003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP126" , 0x1180080e003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP127" , 0x1180080e003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP128" , 0x1180080e00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP129" , 0x1180080e00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP130" , 0x1180080e00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP131" , 0x1180080e00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP132" , 0x1180080e00420ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP133" , 0x1180080e00428ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP134" , 0x1180080e00430ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP135" , 0x1180080e00438ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP136" , 0x1180080e00440ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP137" , 0x1180080e00448ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP138" , 0x1180080e00450ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP139" , 0x1180080e00458ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP140" , 0x1180080e00460ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP141" , 0x1180080e00468ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP142" , 0x1180080e00470ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP143" , 0x1180080e00478ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP144" , 0x1180080e00480ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP145" , 0x1180080e00488ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP146" , 0x1180080e00490ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP147" , 0x1180080e00498ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP148" , 0x1180080e004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP149" , 0x1180080e004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP150" , 0x1180080e004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP151" , 0x1180080e004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP152" , 0x1180080e004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP153" , 0x1180080e004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP154" , 0x1180080e004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP155" , 0x1180080e004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP156" , 0x1180080e004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP157" , 0x1180080e004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP158" , 0x1180080e004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP159" , 0x1180080e004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP160" , 0x1180080e00500ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP161" , 0x1180080e00508ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP162" , 0x1180080e00510ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP163" , 0x1180080e00518ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP164" , 0x1180080e00520ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP165" , 0x1180080e00528ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP166" , 0x1180080e00530ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP167" , 0x1180080e00538ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP168" , 0x1180080e00540ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP169" , 0x1180080e00548ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP170" , 0x1180080e00550ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP171" , 0x1180080e00558ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP172" , 0x1180080e00560ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP173" , 0x1180080e00568ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP174" , 0x1180080e00570ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP175" , 0x1180080e00578ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP176" , 0x1180080e00580ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP177" , 0x1180080e00588ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP178" , 0x1180080e00590ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP179" , 0x1180080e00598ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP180" , 0x1180080e005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP181" , 0x1180080e005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP182" , 0x1180080e005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP183" , 0x1180080e005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP184" , 0x1180080e005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP185" , 0x1180080e005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP186" , 0x1180080e005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP187" , 0x1180080e005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP188" , 0x1180080e005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP189" , 0x1180080e005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP190" , 0x1180080e005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP191" , 0x1180080e005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP192" , 0x1180080e00600ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP193" , 0x1180080e00608ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP194" , 0x1180080e00610ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP195" , 0x1180080e00618ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP196" , 0x1180080e00620ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP197" , 0x1180080e00628ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP198" , 0x1180080e00630ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP199" , 0x1180080e00638ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP200" , 0x1180080e00640ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP201" , 0x1180080e00648ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP202" , 0x1180080e00650ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP203" , 0x1180080e00658ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP204" , 0x1180080e00660ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP205" , 0x1180080e00668ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP206" , 0x1180080e00670ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP207" , 0x1180080e00678ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP208" , 0x1180080e00680ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP209" , 0x1180080e00688ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP210" , 0x1180080e00690ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP211" , 0x1180080e00698ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP212" , 0x1180080e006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP213" , 0x1180080e006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP214" , 0x1180080e006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP215" , 0x1180080e006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP216" , 0x1180080e006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP217" , 0x1180080e006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP218" , 0x1180080e006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP219" , 0x1180080e006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP220" , 0x1180080e006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP221" , 0x1180080e006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP222" , 0x1180080e006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP223" , 0x1180080e006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP224" , 0x1180080e00700ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP225" , 0x1180080e00708ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP226" , 0x1180080e00710ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP227" , 0x1180080e00718ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP228" , 0x1180080e00720ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP229" , 0x1180080e00728ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP230" , 0x1180080e00730ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP231" , 0x1180080e00738ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP232" , 0x1180080e00740ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP233" , 0x1180080e00748ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP234" , 0x1180080e00750ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP235" , 0x1180080e00758ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP236" , 0x1180080e00760ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP237" , 0x1180080e00768ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP238" , 0x1180080e00770ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP239" , 0x1180080e00778ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP240" , 0x1180080e00780ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP241" , 0x1180080e00788ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP242" , 0x1180080e00790ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP243" , 0x1180080e00798ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP244" , 0x1180080e007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP245" , 0x1180080e007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP246" , 0x1180080e007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP247" , 0x1180080e007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP248" , 0x1180080e007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP249" , 0x1180080e007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP250" , 0x1180080e007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP251" , 0x1180080e007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP252" , 0x1180080e007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP253" , 0x1180080e007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP254" , 0x1180080e007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP255" , 0x1180080e007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP256" , 0x1180080e00800ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP257" , 0x1180080e00808ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP258" , 0x1180080e00810ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP259" , 0x1180080e00818ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP260" , 0x1180080e00820ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP261" , 0x1180080e00828ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP262" , 0x1180080e00830ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP263" , 0x1180080e00838ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP264" , 0x1180080e00840ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP265" , 0x1180080e00848ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP266" , 0x1180080e00850ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP267" , 0x1180080e00858ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP268" , 0x1180080e00860ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP269" , 0x1180080e00868ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP270" , 0x1180080e00870ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP271" , 0x1180080e00878ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP272" , 0x1180080e00880ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP273" , 0x1180080e00888ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP274" , 0x1180080e00890ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP275" , 0x1180080e00898ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP276" , 0x1180080e008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP277" , 0x1180080e008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP278" , 0x1180080e008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP279" , 0x1180080e008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP280" , 0x1180080e008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP281" , 0x1180080e008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP282" , 0x1180080e008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP283" , 0x1180080e008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP284" , 0x1180080e008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP285" , 0x1180080e008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP286" , 0x1180080e008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP287" , 0x1180080e008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP288" , 0x1180080e00900ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP289" , 0x1180080e00908ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP290" , 0x1180080e00910ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP291" , 0x1180080e00918ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP292" , 0x1180080e00920ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP293" , 0x1180080e00928ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP294" , 0x1180080e00930ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP295" , 0x1180080e00938ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP296" , 0x1180080e00940ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP297" , 0x1180080e00948ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP298" , 0x1180080e00950ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP299" , 0x1180080e00958ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP300" , 0x1180080e00960ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP301" , 0x1180080e00968ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP302" , 0x1180080e00970ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP303" , 0x1180080e00978ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP304" , 0x1180080e00980ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP305" , 0x1180080e00988ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP306" , 0x1180080e00990ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP307" , 0x1180080e00998ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP308" , 0x1180080e009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP309" , 0x1180080e009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP310" , 0x1180080e009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP311" , 0x1180080e009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP312" , 0x1180080e009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP313" , 0x1180080e009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP314" , 0x1180080e009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP315" , 0x1180080e009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP316" , 0x1180080e009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP317" , 0x1180080e009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP318" , 0x1180080e009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP319" , 0x1180080e009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP320" , 0x1180080e00a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP321" , 0x1180080e00a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP322" , 0x1180080e00a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP323" , 0x1180080e00a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP324" , 0x1180080e00a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP325" , 0x1180080e00a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP326" , 0x1180080e00a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP327" , 0x1180080e00a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP328" , 0x1180080e00a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP329" , 0x1180080e00a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP330" , 0x1180080e00a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP331" , 0x1180080e00a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP332" , 0x1180080e00a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP333" , 0x1180080e00a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP334" , 0x1180080e00a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP335" , 0x1180080e00a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP336" , 0x1180080e00a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP337" , 0x1180080e00a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP338" , 0x1180080e00a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP339" , 0x1180080e00a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP340" , 0x1180080e00aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP341" , 0x1180080e00aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP342" , 0x1180080e00ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP343" , 0x1180080e00ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP344" , 0x1180080e00ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP345" , 0x1180080e00ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP346" , 0x1180080e00ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP347" , 0x1180080e00ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP348" , 0x1180080e00ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP349" , 0x1180080e00ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP350" , 0x1180080e00af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP351" , 0x1180080e00af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP352" , 0x1180080e00b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP353" , 0x1180080e00b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP354" , 0x1180080e00b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP355" , 0x1180080e00b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP356" , 0x1180080e00b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP357" , 0x1180080e00b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP358" , 0x1180080e00b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP359" , 0x1180080e00b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP360" , 0x1180080e00b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP361" , 0x1180080e00b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP362" , 0x1180080e00b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP363" , 0x1180080e00b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP364" , 0x1180080e00b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP365" , 0x1180080e00b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP366" , 0x1180080e00b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP367" , 0x1180080e00b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP368" , 0x1180080e00b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP369" , 0x1180080e00b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP370" , 0x1180080e00b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP371" , 0x1180080e00b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP372" , 0x1180080e00ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP373" , 0x1180080e00ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP374" , 0x1180080e00bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP375" , 0x1180080e00bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP376" , 0x1180080e00bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP377" , 0x1180080e00bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP378" , 0x1180080e00bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP379" , 0x1180080e00bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP380" , 0x1180080e00be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP381" , 0x1180080e00be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP382" , 0x1180080e00bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP383" , 0x1180080e00bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP384" , 0x1180080e00c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP385" , 0x1180080e00c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP386" , 0x1180080e00c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP387" , 0x1180080e00c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP388" , 0x1180080e00c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP389" , 0x1180080e00c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP390" , 0x1180080e00c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP391" , 0x1180080e00c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP392" , 0x1180080e00c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP393" , 0x1180080e00c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP394" , 0x1180080e00c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP395" , 0x1180080e00c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP396" , 0x1180080e00c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP397" , 0x1180080e00c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP398" , 0x1180080e00c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP399" , 0x1180080e00c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP400" , 0x1180080e00c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP401" , 0x1180080e00c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP402" , 0x1180080e00c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP403" , 0x1180080e00c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP404" , 0x1180080e00ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP405" , 0x1180080e00ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP406" , 0x1180080e00cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP407" , 0x1180080e00cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP408" , 0x1180080e00cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP409" , 0x1180080e00cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP410" , 0x1180080e00cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP411" , 0x1180080e00cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP412" , 0x1180080e00ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP413" , 0x1180080e00ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP414" , 0x1180080e00cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP415" , 0x1180080e00cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP416" , 0x1180080e00d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP417" , 0x1180080e00d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP418" , 0x1180080e00d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP419" , 0x1180080e00d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP420" , 0x1180080e00d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP421" , 0x1180080e00d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP422" , 0x1180080e00d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP423" , 0x1180080e00d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP424" , 0x1180080e00d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP425" , 0x1180080e00d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP426" , 0x1180080e00d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP427" , 0x1180080e00d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP428" , 0x1180080e00d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP429" , 0x1180080e00d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP430" , 0x1180080e00d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP431" , 0x1180080e00d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP432" , 0x1180080e00d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP433" , 0x1180080e00d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP434" , 0x1180080e00d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP435" , 0x1180080e00d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP436" , 0x1180080e00da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP437" , 0x1180080e00da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP438" , 0x1180080e00db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP439" , 0x1180080e00db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP440" , 0x1180080e00dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP441" , 0x1180080e00dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP442" , 0x1180080e00dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP443" , 0x1180080e00dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP444" , 0x1180080e00de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP445" , 0x1180080e00de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP446" , 0x1180080e00df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP447" , 0x1180080e00df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP448" , 0x1180080e00e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP449" , 0x1180080e00e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP450" , 0x1180080e00e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP451" , 0x1180080e00e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP452" , 0x1180080e00e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP453" , 0x1180080e00e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP454" , 0x1180080e00e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP455" , 0x1180080e00e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP456" , 0x1180080e00e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP457" , 0x1180080e00e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP458" , 0x1180080e00e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP459" , 0x1180080e00e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP460" , 0x1180080e00e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP461" , 0x1180080e00e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP462" , 0x1180080e00e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP463" , 0x1180080e00e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP464" , 0x1180080e00e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP465" , 0x1180080e00e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP466" , 0x1180080e00e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP467" , 0x1180080e00e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP468" , 0x1180080e00ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP469" , 0x1180080e00ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP470" , 0x1180080e00eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP471" , 0x1180080e00eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP472" , 0x1180080e00ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP473" , 0x1180080e00ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP474" , 0x1180080e00ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP475" , 0x1180080e00ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP476" , 0x1180080e00ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP477" , 0x1180080e00ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP478" , 0x1180080e00ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP479" , 0x1180080e00ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP480" , 0x1180080e00f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP481" , 0x1180080e00f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP482" , 0x1180080e00f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP483" , 0x1180080e00f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP484" , 0x1180080e00f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP485" , 0x1180080e00f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP486" , 0x1180080e00f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP487" , 0x1180080e00f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP488" , 0x1180080e00f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP489" , 0x1180080e00f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP490" , 0x1180080e00f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP491" , 0x1180080e00f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP492" , 0x1180080e00f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP493" , 0x1180080e00f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP494" , 0x1180080e00f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP495" , 0x1180080e00f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP496" , 0x1180080e00f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP497" , 0x1180080e00f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP498" , 0x1180080e00f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP499" , 0x1180080e00f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP500" , 0x1180080e00fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP501" , 0x1180080e00fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP502" , 0x1180080e00fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP503" , 0x1180080e00fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP504" , 0x1180080e00fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP505" , 0x1180080e00fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP506" , 0x1180080e00fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP507" , 0x1180080e00fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP508" , 0x1180080e00fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP509" , 0x1180080e00fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP510" , 0x1180080e00ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP511" , 0x1180080e00ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP512" , 0x1180080e01000ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP513" , 0x1180080e01008ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP514" , 0x1180080e01010ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP515" , 0x1180080e01018ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP516" , 0x1180080e01020ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP517" , 0x1180080e01028ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP518" , 0x1180080e01030ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP519" , 0x1180080e01038ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP520" , 0x1180080e01040ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP521" , 0x1180080e01048ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP522" , 0x1180080e01050ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP523" , 0x1180080e01058ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP524" , 0x1180080e01060ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP525" , 0x1180080e01068ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP526" , 0x1180080e01070ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP527" , 0x1180080e01078ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP528" , 0x1180080e01080ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP529" , 0x1180080e01088ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP530" , 0x1180080e01090ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP531" , 0x1180080e01098ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP532" , 0x1180080e010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP533" , 0x1180080e010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP534" , 0x1180080e010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP535" , 0x1180080e010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP536" , 0x1180080e010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP537" , 0x1180080e010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP538" , 0x1180080e010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP539" , 0x1180080e010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP540" , 0x1180080e010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP541" , 0x1180080e010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP542" , 0x1180080e010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP543" , 0x1180080e010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP544" , 0x1180080e01100ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP545" , 0x1180080e01108ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP546" , 0x1180080e01110ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP547" , 0x1180080e01118ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP548" , 0x1180080e01120ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP549" , 0x1180080e01128ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP550" , 0x1180080e01130ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP551" , 0x1180080e01138ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP552" , 0x1180080e01140ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP553" , 0x1180080e01148ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP554" , 0x1180080e01150ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP555" , 0x1180080e01158ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP556" , 0x1180080e01160ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP557" , 0x1180080e01168ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP558" , 0x1180080e01170ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP559" , 0x1180080e01178ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP560" , 0x1180080e01180ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP561" , 0x1180080e01188ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP562" , 0x1180080e01190ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP563" , 0x1180080e01198ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP564" , 0x1180080e011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP565" , 0x1180080e011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP566" , 0x1180080e011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP567" , 0x1180080e011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP568" , 0x1180080e011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP569" , 0x1180080e011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP570" , 0x1180080e011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP571" , 0x1180080e011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP572" , 0x1180080e011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP573" , 0x1180080e011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP574" , 0x1180080e011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP575" , 0x1180080e011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP576" , 0x1180080e01200ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP577" , 0x1180080e01208ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP578" , 0x1180080e01210ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP579" , 0x1180080e01218ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP580" , 0x1180080e01220ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP581" , 0x1180080e01228ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP582" , 0x1180080e01230ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP583" , 0x1180080e01238ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP584" , 0x1180080e01240ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP585" , 0x1180080e01248ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP586" , 0x1180080e01250ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP587" , 0x1180080e01258ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP588" , 0x1180080e01260ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP589" , 0x1180080e01268ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP590" , 0x1180080e01270ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP591" , 0x1180080e01278ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP592" , 0x1180080e01280ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP593" , 0x1180080e01288ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP594" , 0x1180080e01290ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP595" , 0x1180080e01298ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP596" , 0x1180080e012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP597" , 0x1180080e012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP598" , 0x1180080e012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP599" , 0x1180080e012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP600" , 0x1180080e012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP601" , 0x1180080e012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP602" , 0x1180080e012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP603" , 0x1180080e012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP604" , 0x1180080e012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP605" , 0x1180080e012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP606" , 0x1180080e012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP607" , 0x1180080e012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP608" , 0x1180080e01300ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP609" , 0x1180080e01308ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP610" , 0x1180080e01310ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP611" , 0x1180080e01318ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP612" , 0x1180080e01320ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP613" , 0x1180080e01328ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP614" , 0x1180080e01330ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP615" , 0x1180080e01338ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP616" , 0x1180080e01340ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP617" , 0x1180080e01348ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP618" , 0x1180080e01350ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP619" , 0x1180080e01358ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP620" , 0x1180080e01360ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP621" , 0x1180080e01368ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP622" , 0x1180080e01370ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP623" , 0x1180080e01378ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP624" , 0x1180080e01380ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP625" , 0x1180080e01388ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP626" , 0x1180080e01390ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP627" , 0x1180080e01398ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP628" , 0x1180080e013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP629" , 0x1180080e013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP630" , 0x1180080e013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP631" , 0x1180080e013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP632" , 0x1180080e013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP633" , 0x1180080e013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP634" , 0x1180080e013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP635" , 0x1180080e013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP636" , 0x1180080e013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP637" , 0x1180080e013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP638" , 0x1180080e013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP639" , 0x1180080e013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP640" , 0x1180080e01400ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP641" , 0x1180080e01408ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP642" , 0x1180080e01410ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP643" , 0x1180080e01418ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP644" , 0x1180080e01420ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP645" , 0x1180080e01428ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP646" , 0x1180080e01430ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP647" , 0x1180080e01438ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP648" , 0x1180080e01440ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP649" , 0x1180080e01448ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP650" , 0x1180080e01450ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP651" , 0x1180080e01458ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP652" , 0x1180080e01460ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP653" , 0x1180080e01468ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP654" , 0x1180080e01470ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP655" , 0x1180080e01478ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP656" , 0x1180080e01480ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP657" , 0x1180080e01488ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP658" , 0x1180080e01490ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP659" , 0x1180080e01498ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP660" , 0x1180080e014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP661" , 0x1180080e014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP662" , 0x1180080e014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP663" , 0x1180080e014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP664" , 0x1180080e014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP665" , 0x1180080e014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP666" , 0x1180080e014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP667" , 0x1180080e014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP668" , 0x1180080e014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP669" , 0x1180080e014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP670" , 0x1180080e014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP671" , 0x1180080e014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP672" , 0x1180080e01500ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP673" , 0x1180080e01508ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP674" , 0x1180080e01510ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP675" , 0x1180080e01518ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP676" , 0x1180080e01520ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP677" , 0x1180080e01528ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP678" , 0x1180080e01530ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP679" , 0x1180080e01538ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP680" , 0x1180080e01540ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP681" , 0x1180080e01548ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP682" , 0x1180080e01550ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP683" , 0x1180080e01558ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP684" , 0x1180080e01560ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP685" , 0x1180080e01568ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP686" , 0x1180080e01570ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP687" , 0x1180080e01578ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP688" , 0x1180080e01580ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP689" , 0x1180080e01588ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP690" , 0x1180080e01590ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP691" , 0x1180080e01598ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP692" , 0x1180080e015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP693" , 0x1180080e015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP694" , 0x1180080e015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP695" , 0x1180080e015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP696" , 0x1180080e015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP697" , 0x1180080e015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP698" , 0x1180080e015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP699" , 0x1180080e015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP700" , 0x1180080e015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP701" , 0x1180080e015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP702" , 0x1180080e015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP703" , 0x1180080e015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP704" , 0x1180080e01600ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP705" , 0x1180080e01608ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP706" , 0x1180080e01610ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP707" , 0x1180080e01618ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP708" , 0x1180080e01620ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP709" , 0x1180080e01628ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP710" , 0x1180080e01630ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP711" , 0x1180080e01638ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP712" , 0x1180080e01640ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP713" , 0x1180080e01648ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP714" , 0x1180080e01650ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP715" , 0x1180080e01658ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP716" , 0x1180080e01660ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP717" , 0x1180080e01668ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP718" , 0x1180080e01670ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP719" , 0x1180080e01678ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP720" , 0x1180080e01680ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP721" , 0x1180080e01688ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP722" , 0x1180080e01690ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP723" , 0x1180080e01698ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP724" , 0x1180080e016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP725" , 0x1180080e016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP726" , 0x1180080e016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP727" , 0x1180080e016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP728" , 0x1180080e016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP729" , 0x1180080e016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP730" , 0x1180080e016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP731" , 0x1180080e016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP732" , 0x1180080e016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP733" , 0x1180080e016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP734" , 0x1180080e016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP735" , 0x1180080e016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP736" , 0x1180080e01700ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP737" , 0x1180080e01708ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP738" , 0x1180080e01710ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP739" , 0x1180080e01718ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP740" , 0x1180080e01720ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP741" , 0x1180080e01728ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP742" , 0x1180080e01730ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP743" , 0x1180080e01738ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP744" , 0x1180080e01740ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP745" , 0x1180080e01748ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP746" , 0x1180080e01750ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP747" , 0x1180080e01758ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP748" , 0x1180080e01760ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP749" , 0x1180080e01768ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP750" , 0x1180080e01770ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP751" , 0x1180080e01778ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP752" , 0x1180080e01780ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP753" , 0x1180080e01788ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP754" , 0x1180080e01790ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP755" , 0x1180080e01798ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP756" , 0x1180080e017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP757" , 0x1180080e017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP758" , 0x1180080e017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP759" , 0x1180080e017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP760" , 0x1180080e017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP761" , 0x1180080e017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP762" , 0x1180080e017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP763" , 0x1180080e017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP764" , 0x1180080e017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP765" , 0x1180080e017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP766" , 0x1180080e017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP767" , 0x1180080e017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP768" , 0x1180080e01800ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP769" , 0x1180080e01808ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP770" , 0x1180080e01810ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP771" , 0x1180080e01818ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP772" , 0x1180080e01820ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP773" , 0x1180080e01828ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP774" , 0x1180080e01830ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP775" , 0x1180080e01838ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP776" , 0x1180080e01840ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP777" , 0x1180080e01848ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP778" , 0x1180080e01850ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP779" , 0x1180080e01858ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP780" , 0x1180080e01860ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP781" , 0x1180080e01868ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP782" , 0x1180080e01870ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP783" , 0x1180080e01878ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP784" , 0x1180080e01880ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP785" , 0x1180080e01888ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP786" , 0x1180080e01890ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP787" , 0x1180080e01898ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP788" , 0x1180080e018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP789" , 0x1180080e018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP790" , 0x1180080e018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP791" , 0x1180080e018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP792" , 0x1180080e018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP793" , 0x1180080e018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP794" , 0x1180080e018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP795" , 0x1180080e018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP796" , 0x1180080e018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP797" , 0x1180080e018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP798" , 0x1180080e018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP799" , 0x1180080e018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP800" , 0x1180080e01900ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP801" , 0x1180080e01908ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP802" , 0x1180080e01910ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP803" , 0x1180080e01918ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP804" , 0x1180080e01920ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP805" , 0x1180080e01928ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP806" , 0x1180080e01930ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP807" , 0x1180080e01938ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP808" , 0x1180080e01940ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP809" , 0x1180080e01948ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP810" , 0x1180080e01950ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP811" , 0x1180080e01958ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP812" , 0x1180080e01960ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP813" , 0x1180080e01968ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP814" , 0x1180080e01970ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP815" , 0x1180080e01978ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP816" , 0x1180080e01980ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP817" , 0x1180080e01988ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP818" , 0x1180080e01990ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP819" , 0x1180080e01998ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP820" , 0x1180080e019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP821" , 0x1180080e019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP822" , 0x1180080e019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP823" , 0x1180080e019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP824" , 0x1180080e019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP825" , 0x1180080e019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP826" , 0x1180080e019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP827" , 0x1180080e019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP828" , 0x1180080e019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP829" , 0x1180080e019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP830" , 0x1180080e019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP831" , 0x1180080e019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP832" , 0x1180080e01a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP833" , 0x1180080e01a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP834" , 0x1180080e01a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP835" , 0x1180080e01a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP836" , 0x1180080e01a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP837" , 0x1180080e01a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP838" , 0x1180080e01a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP839" , 0x1180080e01a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP840" , 0x1180080e01a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP841" , 0x1180080e01a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP842" , 0x1180080e01a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP843" , 0x1180080e01a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP844" , 0x1180080e01a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP845" , 0x1180080e01a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP846" , 0x1180080e01a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP847" , 0x1180080e01a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP848" , 0x1180080e01a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP849" , 0x1180080e01a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP850" , 0x1180080e01a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP851" , 0x1180080e01a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP852" , 0x1180080e01aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP853" , 0x1180080e01aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP854" , 0x1180080e01ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP855" , 0x1180080e01ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP856" , 0x1180080e01ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP857" , 0x1180080e01ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP858" , 0x1180080e01ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP859" , 0x1180080e01ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP860" , 0x1180080e01ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP861" , 0x1180080e01ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP862" , 0x1180080e01af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP863" , 0x1180080e01af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP864" , 0x1180080e01b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP865" , 0x1180080e01b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP866" , 0x1180080e01b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP867" , 0x1180080e01b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP868" , 0x1180080e01b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP869" , 0x1180080e01b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP870" , 0x1180080e01b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP871" , 0x1180080e01b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP872" , 0x1180080e01b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP873" , 0x1180080e01b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP874" , 0x1180080e01b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP875" , 0x1180080e01b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP876" , 0x1180080e01b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP877" , 0x1180080e01b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP878" , 0x1180080e01b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP879" , 0x1180080e01b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP880" , 0x1180080e01b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP881" , 0x1180080e01b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP882" , 0x1180080e01b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP883" , 0x1180080e01b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP884" , 0x1180080e01ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP885" , 0x1180080e01ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP886" , 0x1180080e01bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP887" , 0x1180080e01bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP888" , 0x1180080e01bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP889" , 0x1180080e01bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP890" , 0x1180080e01bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP891" , 0x1180080e01bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP892" , 0x1180080e01be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP893" , 0x1180080e01be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP894" , 0x1180080e01bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP895" , 0x1180080e01bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP896" , 0x1180080e01c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP897" , 0x1180080e01c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP898" , 0x1180080e01c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP899" , 0x1180080e01c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP900" , 0x1180080e01c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP901" , 0x1180080e01c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP902" , 0x1180080e01c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP903" , 0x1180080e01c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP904" , 0x1180080e01c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP905" , 0x1180080e01c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP906" , 0x1180080e01c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP907" , 0x1180080e01c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP908" , 0x1180080e01c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP909" , 0x1180080e01c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP910" , 0x1180080e01c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP911" , 0x1180080e01c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP912" , 0x1180080e01c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP913" , 0x1180080e01c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP914" , 0x1180080e01c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP915" , 0x1180080e01c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP916" , 0x1180080e01ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP917" , 0x1180080e01ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP918" , 0x1180080e01cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP919" , 0x1180080e01cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP920" , 0x1180080e01cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP921" , 0x1180080e01cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP922" , 0x1180080e01cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP923" , 0x1180080e01cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP924" , 0x1180080e01ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP925" , 0x1180080e01ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP926" , 0x1180080e01cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP927" , 0x1180080e01cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP928" , 0x1180080e01d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP929" , 0x1180080e01d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP930" , 0x1180080e01d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP931" , 0x1180080e01d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP932" , 0x1180080e01d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP933" , 0x1180080e01d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP934" , 0x1180080e01d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP935" , 0x1180080e01d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP936" , 0x1180080e01d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP937" , 0x1180080e01d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP938" , 0x1180080e01d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP939" , 0x1180080e01d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP940" , 0x1180080e01d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP941" , 0x1180080e01d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP942" , 0x1180080e01d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP943" , 0x1180080e01d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP944" , 0x1180080e01d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP945" , 0x1180080e01d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP946" , 0x1180080e01d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP947" , 0x1180080e01d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP948" , 0x1180080e01da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP949" , 0x1180080e01da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP950" , 0x1180080e01db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP951" , 0x1180080e01db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP952" , 0x1180080e01dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP953" , 0x1180080e01dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP954" , 0x1180080e01dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP955" , 0x1180080e01dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP956" , 0x1180080e01de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP957" , 0x1180080e01de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP958" , 0x1180080e01df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP959" , 0x1180080e01df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP960" , 0x1180080e01e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP961" , 0x1180080e01e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP962" , 0x1180080e01e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP963" , 0x1180080e01e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP964" , 0x1180080e01e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP965" , 0x1180080e01e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP966" , 0x1180080e01e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP967" , 0x1180080e01e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP968" , 0x1180080e01e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP969" , 0x1180080e01e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP970" , 0x1180080e01e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP971" , 0x1180080e01e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP972" , 0x1180080e01e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP973" , 0x1180080e01e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP974" , 0x1180080e01e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP975" , 0x1180080e01e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP976" , 0x1180080e01e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP977" , 0x1180080e01e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP978" , 0x1180080e01e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP979" , 0x1180080e01e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP980" , 0x1180080e01ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP981" , 0x1180080e01ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP982" , 0x1180080e01eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP983" , 0x1180080e01eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP984" , 0x1180080e01ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP985" , 0x1180080e01ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP986" , 0x1180080e01ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP987" , 0x1180080e01ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP988" , 0x1180080e01ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP989" , 0x1180080e01ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP990" , 0x1180080e01ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP991" , 0x1180080e01ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP992" , 0x1180080e01f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP993" , 0x1180080e01f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP994" , 0x1180080e01f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP995" , 0x1180080e01f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP996" , 0x1180080e01f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP997" , 0x1180080e01f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP998" , 0x1180080e01f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP999" , 0x1180080e01f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1000" , 0x1180080e01f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1001" , 0x1180080e01f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1002" , 0x1180080e01f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1003" , 0x1180080e01f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1004" , 0x1180080e01f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1005" , 0x1180080e01f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1006" , 0x1180080e01f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1007" , 0x1180080e01f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1008" , 0x1180080e01f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1009" , 0x1180080e01f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1010" , 0x1180080e01f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1011" , 0x1180080e01f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1012" , 0x1180080e01fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1013" , 0x1180080e01fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1014" , 0x1180080e01fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1015" , 0x1180080e01fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1016" , 0x1180080e01fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1017" , 0x1180080e01fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1018" , 0x1180080e01fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1019" , 0x1180080e01fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1020" , 0x1180080e01fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1021" , 0x1180080e01fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1022" , 0x1180080e01ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_DUT_MAP1023" , 0x1180080e01ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
- {"L2C_ERR_TDT0" , 0x1180080a007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
- {"L2C_ERR_TTG0" , 0x1180080a007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
- {"L2C_ERR_VBF0" , 0x1180080c007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
- {"L2C_ERR_XMC" , 0x11800808007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
- {"L2C_INT_ENA" , 0x1180080800020ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
- {"L2C_INT_REG" , 0x1180080800018ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
- {"L2C_IOC0_PFC" , 0x1180080800420ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
- {"L2C_IOR0_PFC" , 0x1180080800428ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
- {"L2C_QOS_IOB0" , 0x1180080880200ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
- {"L2C_QOS_PP0" , 0x1180080880000ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"L2C_QOS_PP1" , 0x1180080880008ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"L2C_QOS_PP2" , 0x1180080880010ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"L2C_QOS_PP3" , 0x1180080880018ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
- {"L2C_QOS_WGT" , 0x1180080800008ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
- {"L2C_RSC0_PFC" , 0x1180080800410ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
- {"L2C_RSD0_PFC" , 0x1180080800418ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
- {"L2C_TAD0_ECC0" , 0x1180080a00018ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
- {"L2C_TAD0_ECC1" , 0x1180080a00020ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
- {"L2C_TAD0_IEN" , 0x1180080a00000ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
- {"L2C_TAD0_INT" , 0x1180080a00028ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
- {"L2C_TAD0_PFC0" , 0x1180080a00400ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
- {"L2C_TAD0_PFC1" , 0x1180080a00408ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
- {"L2C_TAD0_PFC2" , 0x1180080a00410ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
- {"L2C_TAD0_PFC3" , 0x1180080a00418ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
- {"L2C_TAD0_PRF" , 0x1180080a00008ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
- {"L2C_TAD0_TAG" , 0x1180080a00010ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
- {"L2C_VER_ID" , 0x11800808007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
- {"L2C_VER_IOB" , 0x11800808007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
- {"L2C_VER_MSC" , 0x11800808007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
- {"L2C_VER_PP" , 0x11800808007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
- {"L2C_VIRTID_IOB0" , 0x11800808c0200ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
- {"L2C_VIRTID_PP0" , 0x11800808c0000ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"L2C_VIRTID_PP1" , 0x11800808c0008ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"L2C_VIRTID_PP2" , 0x11800808c0010ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"L2C_VIRTID_PP3" , 0x11800808c0018ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
- {"L2C_VRT_CTL" , 0x1180080800010ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
- {"L2C_VRT_MEM0" , 0x1180080900000ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1" , 0x1180080900008ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM2" , 0x1180080900010ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM3" , 0x1180080900018ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM4" , 0x1180080900020ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM5" , 0x1180080900028ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM6" , 0x1180080900030ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM7" , 0x1180080900038ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM8" , 0x1180080900040ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM9" , 0x1180080900048ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM10" , 0x1180080900050ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM11" , 0x1180080900058ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM12" , 0x1180080900060ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM13" , 0x1180080900068ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM14" , 0x1180080900070ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM15" , 0x1180080900078ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM16" , 0x1180080900080ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM17" , 0x1180080900088ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM18" , 0x1180080900090ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM19" , 0x1180080900098ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM20" , 0x11800809000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM21" , 0x11800809000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM22" , 0x11800809000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM23" , 0x11800809000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM24" , 0x11800809000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM25" , 0x11800809000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM26" , 0x11800809000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM27" , 0x11800809000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM28" , 0x11800809000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM29" , 0x11800809000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM30" , 0x11800809000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM31" , 0x11800809000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM32" , 0x1180080900100ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM33" , 0x1180080900108ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM34" , 0x1180080900110ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM35" , 0x1180080900118ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM36" , 0x1180080900120ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM37" , 0x1180080900128ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM38" , 0x1180080900130ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM39" , 0x1180080900138ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM40" , 0x1180080900140ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM41" , 0x1180080900148ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM42" , 0x1180080900150ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM43" , 0x1180080900158ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM44" , 0x1180080900160ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM45" , 0x1180080900168ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM46" , 0x1180080900170ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM47" , 0x1180080900178ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM48" , 0x1180080900180ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM49" , 0x1180080900188ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM50" , 0x1180080900190ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM51" , 0x1180080900198ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM52" , 0x11800809001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM53" , 0x11800809001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM54" , 0x11800809001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM55" , 0x11800809001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM56" , 0x11800809001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM57" , 0x11800809001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM58" , 0x11800809001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM59" , 0x11800809001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM60" , 0x11800809001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM61" , 0x11800809001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM62" , 0x11800809001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM63" , 0x11800809001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM64" , 0x1180080900200ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM65" , 0x1180080900208ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM66" , 0x1180080900210ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM67" , 0x1180080900218ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM68" , 0x1180080900220ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM69" , 0x1180080900228ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM70" , 0x1180080900230ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM71" , 0x1180080900238ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM72" , 0x1180080900240ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM73" , 0x1180080900248ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM74" , 0x1180080900250ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM75" , 0x1180080900258ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM76" , 0x1180080900260ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM77" , 0x1180080900268ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM78" , 0x1180080900270ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM79" , 0x1180080900278ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM80" , 0x1180080900280ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM81" , 0x1180080900288ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM82" , 0x1180080900290ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM83" , 0x1180080900298ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM84" , 0x11800809002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM85" , 0x11800809002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM86" , 0x11800809002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM87" , 0x11800809002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM88" , 0x11800809002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM89" , 0x11800809002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM90" , 0x11800809002d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM91" , 0x11800809002d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM92" , 0x11800809002e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM93" , 0x11800809002e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM94" , 0x11800809002f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM95" , 0x11800809002f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM96" , 0x1180080900300ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM97" , 0x1180080900308ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM98" , 0x1180080900310ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM99" , 0x1180080900318ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM100" , 0x1180080900320ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM101" , 0x1180080900328ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM102" , 0x1180080900330ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM103" , 0x1180080900338ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM104" , 0x1180080900340ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM105" , 0x1180080900348ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM106" , 0x1180080900350ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM107" , 0x1180080900358ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM108" , 0x1180080900360ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM109" , 0x1180080900368ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM110" , 0x1180080900370ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM111" , 0x1180080900378ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM112" , 0x1180080900380ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM113" , 0x1180080900388ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM114" , 0x1180080900390ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM115" , 0x1180080900398ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM116" , 0x11800809003a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM117" , 0x11800809003a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM118" , 0x11800809003b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM119" , 0x11800809003b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM120" , 0x11800809003c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM121" , 0x11800809003c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM122" , 0x11800809003d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM123" , 0x11800809003d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM124" , 0x11800809003e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM125" , 0x11800809003e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM126" , 0x11800809003f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM127" , 0x11800809003f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM128" , 0x1180080900400ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM129" , 0x1180080900408ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM130" , 0x1180080900410ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM131" , 0x1180080900418ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM132" , 0x1180080900420ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM133" , 0x1180080900428ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM134" , 0x1180080900430ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM135" , 0x1180080900438ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM136" , 0x1180080900440ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM137" , 0x1180080900448ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM138" , 0x1180080900450ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM139" , 0x1180080900458ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM140" , 0x1180080900460ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM141" , 0x1180080900468ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM142" , 0x1180080900470ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM143" , 0x1180080900478ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM144" , 0x1180080900480ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM145" , 0x1180080900488ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM146" , 0x1180080900490ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM147" , 0x1180080900498ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM148" , 0x11800809004a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM149" , 0x11800809004a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM150" , 0x11800809004b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM151" , 0x11800809004b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM152" , 0x11800809004c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM153" , 0x11800809004c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM154" , 0x11800809004d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM155" , 0x11800809004d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM156" , 0x11800809004e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM157" , 0x11800809004e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM158" , 0x11800809004f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM159" , 0x11800809004f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM160" , 0x1180080900500ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM161" , 0x1180080900508ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM162" , 0x1180080900510ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM163" , 0x1180080900518ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM164" , 0x1180080900520ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM165" , 0x1180080900528ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM166" , 0x1180080900530ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM167" , 0x1180080900538ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM168" , 0x1180080900540ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM169" , 0x1180080900548ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM170" , 0x1180080900550ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM171" , 0x1180080900558ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM172" , 0x1180080900560ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM173" , 0x1180080900568ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM174" , 0x1180080900570ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM175" , 0x1180080900578ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM176" , 0x1180080900580ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM177" , 0x1180080900588ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM178" , 0x1180080900590ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM179" , 0x1180080900598ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM180" , 0x11800809005a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM181" , 0x11800809005a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM182" , 0x11800809005b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM183" , 0x11800809005b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM184" , 0x11800809005c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM185" , 0x11800809005c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM186" , 0x11800809005d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM187" , 0x11800809005d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM188" , 0x11800809005e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM189" , 0x11800809005e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM190" , 0x11800809005f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM191" , 0x11800809005f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM192" , 0x1180080900600ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM193" , 0x1180080900608ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM194" , 0x1180080900610ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM195" , 0x1180080900618ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM196" , 0x1180080900620ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM197" , 0x1180080900628ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM198" , 0x1180080900630ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM199" , 0x1180080900638ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM200" , 0x1180080900640ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM201" , 0x1180080900648ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM202" , 0x1180080900650ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM203" , 0x1180080900658ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM204" , 0x1180080900660ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM205" , 0x1180080900668ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM206" , 0x1180080900670ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM207" , 0x1180080900678ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM208" , 0x1180080900680ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM209" , 0x1180080900688ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM210" , 0x1180080900690ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM211" , 0x1180080900698ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM212" , 0x11800809006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM213" , 0x11800809006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM214" , 0x11800809006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM215" , 0x11800809006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM216" , 0x11800809006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM217" , 0x11800809006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM218" , 0x11800809006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM219" , 0x11800809006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM220" , 0x11800809006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM221" , 0x11800809006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM222" , 0x11800809006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM223" , 0x11800809006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM224" , 0x1180080900700ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM225" , 0x1180080900708ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM226" , 0x1180080900710ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM227" , 0x1180080900718ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM228" , 0x1180080900720ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM229" , 0x1180080900728ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM230" , 0x1180080900730ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM231" , 0x1180080900738ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM232" , 0x1180080900740ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM233" , 0x1180080900748ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM234" , 0x1180080900750ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM235" , 0x1180080900758ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM236" , 0x1180080900760ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM237" , 0x1180080900768ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM238" , 0x1180080900770ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM239" , 0x1180080900778ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM240" , 0x1180080900780ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM241" , 0x1180080900788ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM242" , 0x1180080900790ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM243" , 0x1180080900798ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM244" , 0x11800809007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM245" , 0x11800809007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM246" , 0x11800809007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM247" , 0x11800809007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM248" , 0x11800809007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM249" , 0x11800809007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM250" , 0x11800809007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM251" , 0x11800809007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM252" , 0x11800809007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM253" , 0x11800809007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM254" , 0x11800809007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM255" , 0x11800809007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM256" , 0x1180080900800ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM257" , 0x1180080900808ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM258" , 0x1180080900810ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM259" , 0x1180080900818ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM260" , 0x1180080900820ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM261" , 0x1180080900828ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM262" , 0x1180080900830ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM263" , 0x1180080900838ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM264" , 0x1180080900840ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM265" , 0x1180080900848ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM266" , 0x1180080900850ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM267" , 0x1180080900858ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM268" , 0x1180080900860ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM269" , 0x1180080900868ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM270" , 0x1180080900870ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM271" , 0x1180080900878ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM272" , 0x1180080900880ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM273" , 0x1180080900888ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM274" , 0x1180080900890ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM275" , 0x1180080900898ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM276" , 0x11800809008a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM277" , 0x11800809008a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM278" , 0x11800809008b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM279" , 0x11800809008b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM280" , 0x11800809008c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM281" , 0x11800809008c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM282" , 0x11800809008d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM283" , 0x11800809008d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM284" , 0x11800809008e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM285" , 0x11800809008e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM286" , 0x11800809008f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM287" , 0x11800809008f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM288" , 0x1180080900900ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM289" , 0x1180080900908ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM290" , 0x1180080900910ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM291" , 0x1180080900918ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM292" , 0x1180080900920ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM293" , 0x1180080900928ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM294" , 0x1180080900930ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM295" , 0x1180080900938ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM296" , 0x1180080900940ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM297" , 0x1180080900948ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM298" , 0x1180080900950ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM299" , 0x1180080900958ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM300" , 0x1180080900960ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM301" , 0x1180080900968ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM302" , 0x1180080900970ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM303" , 0x1180080900978ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM304" , 0x1180080900980ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM305" , 0x1180080900988ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM306" , 0x1180080900990ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM307" , 0x1180080900998ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM308" , 0x11800809009a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM309" , 0x11800809009a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM310" , 0x11800809009b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM311" , 0x11800809009b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM312" , 0x11800809009c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM313" , 0x11800809009c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM314" , 0x11800809009d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM315" , 0x11800809009d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM316" , 0x11800809009e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM317" , 0x11800809009e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM318" , 0x11800809009f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM319" , 0x11800809009f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM320" , 0x1180080900a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM321" , 0x1180080900a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM322" , 0x1180080900a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM323" , 0x1180080900a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM324" , 0x1180080900a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM325" , 0x1180080900a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM326" , 0x1180080900a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM327" , 0x1180080900a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM328" , 0x1180080900a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM329" , 0x1180080900a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM330" , 0x1180080900a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM331" , 0x1180080900a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM332" , 0x1180080900a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM333" , 0x1180080900a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM334" , 0x1180080900a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM335" , 0x1180080900a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM336" , 0x1180080900a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM337" , 0x1180080900a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM338" , 0x1180080900a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM339" , 0x1180080900a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM340" , 0x1180080900aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM341" , 0x1180080900aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM342" , 0x1180080900ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM343" , 0x1180080900ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM344" , 0x1180080900ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM345" , 0x1180080900ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM346" , 0x1180080900ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM347" , 0x1180080900ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM348" , 0x1180080900ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM349" , 0x1180080900ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM350" , 0x1180080900af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM351" , 0x1180080900af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM352" , 0x1180080900b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM353" , 0x1180080900b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM354" , 0x1180080900b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM355" , 0x1180080900b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM356" , 0x1180080900b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM357" , 0x1180080900b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM358" , 0x1180080900b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM359" , 0x1180080900b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM360" , 0x1180080900b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM361" , 0x1180080900b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM362" , 0x1180080900b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM363" , 0x1180080900b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM364" , 0x1180080900b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM365" , 0x1180080900b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM366" , 0x1180080900b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM367" , 0x1180080900b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM368" , 0x1180080900b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM369" , 0x1180080900b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM370" , 0x1180080900b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM371" , 0x1180080900b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM372" , 0x1180080900ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM373" , 0x1180080900ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM374" , 0x1180080900bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM375" , 0x1180080900bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM376" , 0x1180080900bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM377" , 0x1180080900bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM378" , 0x1180080900bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM379" , 0x1180080900bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM380" , 0x1180080900be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM381" , 0x1180080900be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM382" , 0x1180080900bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM383" , 0x1180080900bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM384" , 0x1180080900c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM385" , 0x1180080900c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM386" , 0x1180080900c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM387" , 0x1180080900c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM388" , 0x1180080900c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM389" , 0x1180080900c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM390" , 0x1180080900c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM391" , 0x1180080900c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM392" , 0x1180080900c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM393" , 0x1180080900c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM394" , 0x1180080900c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM395" , 0x1180080900c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM396" , 0x1180080900c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM397" , 0x1180080900c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM398" , 0x1180080900c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM399" , 0x1180080900c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM400" , 0x1180080900c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM401" , 0x1180080900c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM402" , 0x1180080900c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM403" , 0x1180080900c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM404" , 0x1180080900ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM405" , 0x1180080900ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM406" , 0x1180080900cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM407" , 0x1180080900cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM408" , 0x1180080900cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM409" , 0x1180080900cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM410" , 0x1180080900cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM411" , 0x1180080900cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM412" , 0x1180080900ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM413" , 0x1180080900ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM414" , 0x1180080900cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM415" , 0x1180080900cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM416" , 0x1180080900d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM417" , 0x1180080900d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM418" , 0x1180080900d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM419" , 0x1180080900d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM420" , 0x1180080900d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM421" , 0x1180080900d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM422" , 0x1180080900d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM423" , 0x1180080900d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM424" , 0x1180080900d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM425" , 0x1180080900d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM426" , 0x1180080900d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM427" , 0x1180080900d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM428" , 0x1180080900d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM429" , 0x1180080900d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM430" , 0x1180080900d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM431" , 0x1180080900d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM432" , 0x1180080900d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM433" , 0x1180080900d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM434" , 0x1180080900d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM435" , 0x1180080900d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM436" , 0x1180080900da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM437" , 0x1180080900da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM438" , 0x1180080900db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM439" , 0x1180080900db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM440" , 0x1180080900dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM441" , 0x1180080900dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM442" , 0x1180080900dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM443" , 0x1180080900dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM444" , 0x1180080900de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM445" , 0x1180080900de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM446" , 0x1180080900df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM447" , 0x1180080900df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM448" , 0x1180080900e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM449" , 0x1180080900e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM450" , 0x1180080900e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM451" , 0x1180080900e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM452" , 0x1180080900e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM453" , 0x1180080900e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM454" , 0x1180080900e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM455" , 0x1180080900e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM456" , 0x1180080900e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM457" , 0x1180080900e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM458" , 0x1180080900e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM459" , 0x1180080900e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM460" , 0x1180080900e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM461" , 0x1180080900e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM462" , 0x1180080900e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM463" , 0x1180080900e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM464" , 0x1180080900e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM465" , 0x1180080900e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM466" , 0x1180080900e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM467" , 0x1180080900e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM468" , 0x1180080900ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM469" , 0x1180080900ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM470" , 0x1180080900eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM471" , 0x1180080900eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM472" , 0x1180080900ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM473" , 0x1180080900ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM474" , 0x1180080900ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM475" , 0x1180080900ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM476" , 0x1180080900ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM477" , 0x1180080900ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM478" , 0x1180080900ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM479" , 0x1180080900ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM480" , 0x1180080900f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM481" , 0x1180080900f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM482" , 0x1180080900f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM483" , 0x1180080900f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM484" , 0x1180080900f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM485" , 0x1180080900f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM486" , 0x1180080900f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM487" , 0x1180080900f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM488" , 0x1180080900f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM489" , 0x1180080900f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM490" , 0x1180080900f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM491" , 0x1180080900f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM492" , 0x1180080900f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM493" , 0x1180080900f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM494" , 0x1180080900f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM495" , 0x1180080900f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM496" , 0x1180080900f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM497" , 0x1180080900f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM498" , 0x1180080900f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM499" , 0x1180080900f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM500" , 0x1180080900fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM501" , 0x1180080900fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM502" , 0x1180080900fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM503" , 0x1180080900fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM504" , 0x1180080900fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM505" , 0x1180080900fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM506" , 0x1180080900fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM507" , 0x1180080900fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM508" , 0x1180080900fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM509" , 0x1180080900fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM510" , 0x1180080900ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM511" , 0x1180080900ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM512" , 0x1180080901000ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM513" , 0x1180080901008ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM514" , 0x1180080901010ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM515" , 0x1180080901018ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM516" , 0x1180080901020ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM517" , 0x1180080901028ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM518" , 0x1180080901030ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM519" , 0x1180080901038ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM520" , 0x1180080901040ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM521" , 0x1180080901048ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM522" , 0x1180080901050ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM523" , 0x1180080901058ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM524" , 0x1180080901060ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM525" , 0x1180080901068ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM526" , 0x1180080901070ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM527" , 0x1180080901078ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM528" , 0x1180080901080ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM529" , 0x1180080901088ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM530" , 0x1180080901090ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM531" , 0x1180080901098ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM532" , 0x11800809010a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM533" , 0x11800809010a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM534" , 0x11800809010b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM535" , 0x11800809010b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM536" , 0x11800809010c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM537" , 0x11800809010c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM538" , 0x11800809010d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM539" , 0x11800809010d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM540" , 0x11800809010e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM541" , 0x11800809010e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM542" , 0x11800809010f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM543" , 0x11800809010f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM544" , 0x1180080901100ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM545" , 0x1180080901108ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM546" , 0x1180080901110ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM547" , 0x1180080901118ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM548" , 0x1180080901120ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM549" , 0x1180080901128ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM550" , 0x1180080901130ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM551" , 0x1180080901138ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM552" , 0x1180080901140ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM553" , 0x1180080901148ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM554" , 0x1180080901150ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM555" , 0x1180080901158ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM556" , 0x1180080901160ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM557" , 0x1180080901168ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM558" , 0x1180080901170ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM559" , 0x1180080901178ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM560" , 0x1180080901180ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM561" , 0x1180080901188ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM562" , 0x1180080901190ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM563" , 0x1180080901198ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM564" , 0x11800809011a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM565" , 0x11800809011a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM566" , 0x11800809011b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM567" , 0x11800809011b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM568" , 0x11800809011c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM569" , 0x11800809011c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM570" , 0x11800809011d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM571" , 0x11800809011d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM572" , 0x11800809011e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM573" , 0x11800809011e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM574" , 0x11800809011f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM575" , 0x11800809011f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM576" , 0x1180080901200ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM577" , 0x1180080901208ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM578" , 0x1180080901210ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM579" , 0x1180080901218ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM580" , 0x1180080901220ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM581" , 0x1180080901228ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM582" , 0x1180080901230ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM583" , 0x1180080901238ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM584" , 0x1180080901240ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM585" , 0x1180080901248ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM586" , 0x1180080901250ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM587" , 0x1180080901258ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM588" , 0x1180080901260ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM589" , 0x1180080901268ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM590" , 0x1180080901270ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM591" , 0x1180080901278ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM592" , 0x1180080901280ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM593" , 0x1180080901288ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM594" , 0x1180080901290ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM595" , 0x1180080901298ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM596" , 0x11800809012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM597" , 0x11800809012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM598" , 0x11800809012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM599" , 0x11800809012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM600" , 0x11800809012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM601" , 0x11800809012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM602" , 0x11800809012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM603" , 0x11800809012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM604" , 0x11800809012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM605" , 0x11800809012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM606" , 0x11800809012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM607" , 0x11800809012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM608" , 0x1180080901300ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM609" , 0x1180080901308ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM610" , 0x1180080901310ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM611" , 0x1180080901318ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM612" , 0x1180080901320ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM613" , 0x1180080901328ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM614" , 0x1180080901330ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM615" , 0x1180080901338ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM616" , 0x1180080901340ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM617" , 0x1180080901348ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM618" , 0x1180080901350ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM619" , 0x1180080901358ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM620" , 0x1180080901360ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM621" , 0x1180080901368ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM622" , 0x1180080901370ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM623" , 0x1180080901378ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM624" , 0x1180080901380ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM625" , 0x1180080901388ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM626" , 0x1180080901390ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM627" , 0x1180080901398ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM628" , 0x11800809013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM629" , 0x11800809013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM630" , 0x11800809013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM631" , 0x11800809013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM632" , 0x11800809013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM633" , 0x11800809013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM634" , 0x11800809013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM635" , 0x11800809013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM636" , 0x11800809013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM637" , 0x11800809013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM638" , 0x11800809013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM639" , 0x11800809013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM640" , 0x1180080901400ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM641" , 0x1180080901408ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM642" , 0x1180080901410ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM643" , 0x1180080901418ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM644" , 0x1180080901420ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM645" , 0x1180080901428ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM646" , 0x1180080901430ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM647" , 0x1180080901438ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM648" , 0x1180080901440ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM649" , 0x1180080901448ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM650" , 0x1180080901450ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM651" , 0x1180080901458ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM652" , 0x1180080901460ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM653" , 0x1180080901468ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM654" , 0x1180080901470ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM655" , 0x1180080901478ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM656" , 0x1180080901480ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM657" , 0x1180080901488ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM658" , 0x1180080901490ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM659" , 0x1180080901498ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM660" , 0x11800809014a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM661" , 0x11800809014a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM662" , 0x11800809014b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM663" , 0x11800809014b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM664" , 0x11800809014c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM665" , 0x11800809014c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM666" , 0x11800809014d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM667" , 0x11800809014d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM668" , 0x11800809014e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM669" , 0x11800809014e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM670" , 0x11800809014f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM671" , 0x11800809014f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM672" , 0x1180080901500ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM673" , 0x1180080901508ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM674" , 0x1180080901510ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM675" , 0x1180080901518ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM676" , 0x1180080901520ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM677" , 0x1180080901528ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM678" , 0x1180080901530ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM679" , 0x1180080901538ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM680" , 0x1180080901540ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM681" , 0x1180080901548ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM682" , 0x1180080901550ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM683" , 0x1180080901558ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM684" , 0x1180080901560ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM685" , 0x1180080901568ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM686" , 0x1180080901570ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM687" , 0x1180080901578ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM688" , 0x1180080901580ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM689" , 0x1180080901588ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM690" , 0x1180080901590ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM691" , 0x1180080901598ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM692" , 0x11800809015a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM693" , 0x11800809015a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM694" , 0x11800809015b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM695" , 0x11800809015b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM696" , 0x11800809015c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM697" , 0x11800809015c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM698" , 0x11800809015d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM699" , 0x11800809015d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM700" , 0x11800809015e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM701" , 0x11800809015e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM702" , 0x11800809015f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM703" , 0x11800809015f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM704" , 0x1180080901600ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM705" , 0x1180080901608ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM706" , 0x1180080901610ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM707" , 0x1180080901618ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM708" , 0x1180080901620ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM709" , 0x1180080901628ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM710" , 0x1180080901630ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM711" , 0x1180080901638ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM712" , 0x1180080901640ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM713" , 0x1180080901648ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM714" , 0x1180080901650ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM715" , 0x1180080901658ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM716" , 0x1180080901660ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM717" , 0x1180080901668ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM718" , 0x1180080901670ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM719" , 0x1180080901678ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM720" , 0x1180080901680ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM721" , 0x1180080901688ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM722" , 0x1180080901690ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM723" , 0x1180080901698ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM724" , 0x11800809016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM725" , 0x11800809016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM726" , 0x11800809016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM727" , 0x11800809016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM728" , 0x11800809016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM729" , 0x11800809016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM730" , 0x11800809016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM731" , 0x11800809016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM732" , 0x11800809016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM733" , 0x11800809016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM734" , 0x11800809016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM735" , 0x11800809016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM736" , 0x1180080901700ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM737" , 0x1180080901708ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM738" , 0x1180080901710ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM739" , 0x1180080901718ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM740" , 0x1180080901720ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM741" , 0x1180080901728ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM742" , 0x1180080901730ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM743" , 0x1180080901738ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM744" , 0x1180080901740ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM745" , 0x1180080901748ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM746" , 0x1180080901750ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM747" , 0x1180080901758ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM748" , 0x1180080901760ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM749" , 0x1180080901768ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM750" , 0x1180080901770ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM751" , 0x1180080901778ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM752" , 0x1180080901780ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM753" , 0x1180080901788ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM754" , 0x1180080901790ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM755" , 0x1180080901798ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM756" , 0x11800809017a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM757" , 0x11800809017a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM758" , 0x11800809017b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM759" , 0x11800809017b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM760" , 0x11800809017c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM761" , 0x11800809017c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM762" , 0x11800809017d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM763" , 0x11800809017d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM764" , 0x11800809017e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM765" , 0x11800809017e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM766" , 0x11800809017f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM767" , 0x11800809017f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM768" , 0x1180080901800ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM769" , 0x1180080901808ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM770" , 0x1180080901810ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM771" , 0x1180080901818ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM772" , 0x1180080901820ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM773" , 0x1180080901828ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM774" , 0x1180080901830ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM775" , 0x1180080901838ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM776" , 0x1180080901840ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM777" , 0x1180080901848ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM778" , 0x1180080901850ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM779" , 0x1180080901858ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM780" , 0x1180080901860ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM781" , 0x1180080901868ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM782" , 0x1180080901870ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM783" , 0x1180080901878ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM784" , 0x1180080901880ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM785" , 0x1180080901888ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM786" , 0x1180080901890ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM787" , 0x1180080901898ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM788" , 0x11800809018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM789" , 0x11800809018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM790" , 0x11800809018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM791" , 0x11800809018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM792" , 0x11800809018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM793" , 0x11800809018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM794" , 0x11800809018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM795" , 0x11800809018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM796" , 0x11800809018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM797" , 0x11800809018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM798" , 0x11800809018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM799" , 0x11800809018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM800" , 0x1180080901900ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM801" , 0x1180080901908ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM802" , 0x1180080901910ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM803" , 0x1180080901918ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM804" , 0x1180080901920ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM805" , 0x1180080901928ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM806" , 0x1180080901930ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM807" , 0x1180080901938ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM808" , 0x1180080901940ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM809" , 0x1180080901948ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM810" , 0x1180080901950ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM811" , 0x1180080901958ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM812" , 0x1180080901960ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM813" , 0x1180080901968ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM814" , 0x1180080901970ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM815" , 0x1180080901978ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM816" , 0x1180080901980ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM817" , 0x1180080901988ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM818" , 0x1180080901990ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM819" , 0x1180080901998ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM820" , 0x11800809019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM821" , 0x11800809019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM822" , 0x11800809019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM823" , 0x11800809019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM824" , 0x11800809019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM825" , 0x11800809019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM826" , 0x11800809019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM827" , 0x11800809019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM828" , 0x11800809019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM829" , 0x11800809019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM830" , 0x11800809019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM831" , 0x11800809019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM832" , 0x1180080901a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM833" , 0x1180080901a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM834" , 0x1180080901a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM835" , 0x1180080901a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM836" , 0x1180080901a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM837" , 0x1180080901a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM838" , 0x1180080901a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM839" , 0x1180080901a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM840" , 0x1180080901a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM841" , 0x1180080901a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM842" , 0x1180080901a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM843" , 0x1180080901a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM844" , 0x1180080901a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM845" , 0x1180080901a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM846" , 0x1180080901a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM847" , 0x1180080901a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM848" , 0x1180080901a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM849" , 0x1180080901a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM850" , 0x1180080901a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM851" , 0x1180080901a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM852" , 0x1180080901aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM853" , 0x1180080901aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM854" , 0x1180080901ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM855" , 0x1180080901ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM856" , 0x1180080901ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM857" , 0x1180080901ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM858" , 0x1180080901ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM859" , 0x1180080901ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM860" , 0x1180080901ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM861" , 0x1180080901ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM862" , 0x1180080901af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM863" , 0x1180080901af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM864" , 0x1180080901b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM865" , 0x1180080901b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM866" , 0x1180080901b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM867" , 0x1180080901b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM868" , 0x1180080901b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM869" , 0x1180080901b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM870" , 0x1180080901b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM871" , 0x1180080901b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM872" , 0x1180080901b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM873" , 0x1180080901b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM874" , 0x1180080901b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM875" , 0x1180080901b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM876" , 0x1180080901b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM877" , 0x1180080901b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM878" , 0x1180080901b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM879" , 0x1180080901b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM880" , 0x1180080901b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM881" , 0x1180080901b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM882" , 0x1180080901b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM883" , 0x1180080901b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM884" , 0x1180080901ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM885" , 0x1180080901ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM886" , 0x1180080901bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM887" , 0x1180080901bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM888" , 0x1180080901bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM889" , 0x1180080901bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM890" , 0x1180080901bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM891" , 0x1180080901bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM892" , 0x1180080901be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM893" , 0x1180080901be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM894" , 0x1180080901bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM895" , 0x1180080901bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM896" , 0x1180080901c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM897" , 0x1180080901c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM898" , 0x1180080901c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM899" , 0x1180080901c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM900" , 0x1180080901c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM901" , 0x1180080901c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM902" , 0x1180080901c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM903" , 0x1180080901c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM904" , 0x1180080901c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM905" , 0x1180080901c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM906" , 0x1180080901c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM907" , 0x1180080901c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM908" , 0x1180080901c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM909" , 0x1180080901c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM910" , 0x1180080901c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM911" , 0x1180080901c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM912" , 0x1180080901c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM913" , 0x1180080901c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM914" , 0x1180080901c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM915" , 0x1180080901c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM916" , 0x1180080901ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM917" , 0x1180080901ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM918" , 0x1180080901cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM919" , 0x1180080901cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM920" , 0x1180080901cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM921" , 0x1180080901cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM922" , 0x1180080901cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM923" , 0x1180080901cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM924" , 0x1180080901ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM925" , 0x1180080901ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM926" , 0x1180080901cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM927" , 0x1180080901cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM928" , 0x1180080901d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM929" , 0x1180080901d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM930" , 0x1180080901d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM931" , 0x1180080901d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM932" , 0x1180080901d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM933" , 0x1180080901d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM934" , 0x1180080901d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM935" , 0x1180080901d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM936" , 0x1180080901d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM937" , 0x1180080901d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM938" , 0x1180080901d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM939" , 0x1180080901d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM940" , 0x1180080901d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM941" , 0x1180080901d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM942" , 0x1180080901d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM943" , 0x1180080901d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM944" , 0x1180080901d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM945" , 0x1180080901d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM946" , 0x1180080901d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM947" , 0x1180080901d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM948" , 0x1180080901da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM949" , 0x1180080901da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM950" , 0x1180080901db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM951" , 0x1180080901db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM952" , 0x1180080901dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM953" , 0x1180080901dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM954" , 0x1180080901dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM955" , 0x1180080901dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM956" , 0x1180080901de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM957" , 0x1180080901de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM958" , 0x1180080901df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM959" , 0x1180080901df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM960" , 0x1180080901e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM961" , 0x1180080901e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM962" , 0x1180080901e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM963" , 0x1180080901e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM964" , 0x1180080901e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM965" , 0x1180080901e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM966" , 0x1180080901e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM967" , 0x1180080901e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM968" , 0x1180080901e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM969" , 0x1180080901e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM970" , 0x1180080901e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM971" , 0x1180080901e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM972" , 0x1180080901e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM973" , 0x1180080901e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM974" , 0x1180080901e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM975" , 0x1180080901e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM976" , 0x1180080901e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM977" , 0x1180080901e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM978" , 0x1180080901e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM979" , 0x1180080901e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM980" , 0x1180080901ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM981" , 0x1180080901ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM982" , 0x1180080901eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM983" , 0x1180080901eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM984" , 0x1180080901ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM985" , 0x1180080901ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM986" , 0x1180080901ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM987" , 0x1180080901ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM988" , 0x1180080901ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM989" , 0x1180080901ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM990" , 0x1180080901ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM991" , 0x1180080901ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM992" , 0x1180080901f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM993" , 0x1180080901f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM994" , 0x1180080901f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM995" , 0x1180080901f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM996" , 0x1180080901f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM997" , 0x1180080901f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM998" , 0x1180080901f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM999" , 0x1180080901f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1000" , 0x1180080901f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1001" , 0x1180080901f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1002" , 0x1180080901f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1003" , 0x1180080901f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1004" , 0x1180080901f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1005" , 0x1180080901f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1006" , 0x1180080901f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1007" , 0x1180080901f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1008" , 0x1180080901f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1009" , 0x1180080901f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1010" , 0x1180080901f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1011" , 0x1180080901f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1012" , 0x1180080901fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1013" , 0x1180080901fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1014" , 0x1180080901fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1015" , 0x1180080901fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1016" , 0x1180080901fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1017" , 0x1180080901fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1018" , 0x1180080901fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1019" , 0x1180080901fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1020" , 0x1180080901fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1021" , 0x1180080901fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1022" , 0x1180080901ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_VRT_MEM1023" , 0x1180080901ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
- {"L2C_WPAR_IOB0" , 0x1180080840200ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
- {"L2C_WPAR_PP0" , 0x1180080840000ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"L2C_WPAR_PP1" , 0x1180080840008ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"L2C_WPAR_PP2" , 0x1180080840010ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"L2C_WPAR_PP3" , 0x1180080840018ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
- {"L2C_XMC0_PFC" , 0x1180080800400ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
- {"L2C_XMC_CMD" , 0x1180080800028ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
- {"L2C_XMD0_PFC" , 0x1180080800408ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
- {"LMC0_CHAR_CTL" , 0x1180088000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
- {"LMC0_CHAR_MASK0" , 0x1180088000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
- {"LMC0_CHAR_MASK1" , 0x1180088000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
- {"LMC0_CHAR_MASK2" , 0x1180088000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
- {"LMC0_CHAR_MASK3" , 0x1180088000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
- {"LMC0_CHAR_MASK4" , 0x1180088000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
- {"LMC0_COMP_CTL2" , 0x11800880001b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
- {"LMC0_CONFIG" , 0x1180088000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
- {"LMC0_CONTROL" , 0x1180088000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
- {"LMC0_DCLK_CNT" , 0x11800880001e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
- {"LMC0_DDR_PLL_CTL" , 0x1180088000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
- {"LMC0_DIMM000_PARAMS" , 0x1180088000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"LMC0_DIMM001_PARAMS" , 0x1180088000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
- {"LMC0_DIMM_CTL" , 0x1180088000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
- {"LMC0_DLL_CTL2" , 0x11800880001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
- {"LMC0_DLL_CTL3" , 0x1180088000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
- {"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
- {"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
- {"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
- {"LMC0_IFB_CNT" , 0x11800880001d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
- {"LMC0_INT" , 0x11800880001f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
- {"LMC0_INT_EN" , 0x11800880001e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
- {"LMC0_MODEREG_PARAMS0" , 0x11800880001a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
- {"LMC0_MODEREG_PARAMS1" , 0x1180088000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
- {"LMC0_NXM" , 0x11800880000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
- {"LMC0_OPS_CNT" , 0x11800880001d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
- {"LMC0_PHY_CTL" , 0x1180088000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
- {"LMC0_RESET_CTL" , 0x1180088000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
- {"LMC0_RLEVEL_CTL" , 0x11800880002a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
- {"LMC0_RLEVEL_DBG" , 0x11800880002a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
- {"LMC0_RLEVEL_RANK000" , 0x1180088000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"LMC0_RLEVEL_RANK001" , 0x1180088000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"LMC0_RLEVEL_RANK002" , 0x1180088000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"LMC0_RLEVEL_RANK003" , 0x1180088000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
- {"LMC0_RODT_MASK" , 0x1180088000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
- {"LMC0_SCRAMBLE_CFG0" , 0x1180088000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
- {"LMC0_SCRAMBLE_CFG1" , 0x1180088000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
- {"LMC0_SCRAMBLED_FADR" , 0x1180088000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
- {"LMC0_SLOT_CTL0" , 0x11800880001f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
- {"LMC0_SLOT_CTL1" , 0x1180088000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
- {"LMC0_SLOT_CTL2" , 0x1180088000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
- {"LMC0_TIMING_PARAMS0" , 0x1180088000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
- {"LMC0_TIMING_PARAMS1" , 0x11800880001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
- {"LMC0_TRO_CTL" , 0x1180088000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
- {"LMC0_TRO_STAT" , 0x1180088000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
- {"LMC0_WLEVEL_CTL" , 0x1180088000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
- {"LMC0_WLEVEL_DBG" , 0x1180088000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
- {"LMC0_WLEVEL_RANK000" , 0x11800880002b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"LMC0_WLEVEL_RANK001" , 0x11800880002b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"LMC0_WLEVEL_RANK002" , 0x11800880002c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"LMC0_WLEVEL_RANK003" , 0x11800880002c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
- {"LMC0_WODT_MASK" , 0x11800880001b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
- {"MIO_BOOT_BIST_STAT" , 0x11800000000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
- {"MIO_BOOT_COMP" , 0x11800000000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
- {"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
- {"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
- {"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
- {"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
- {"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
- {"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
- {"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
- {"MIO_BOOT_ERR" , 0x11800000000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
- {"MIO_BOOT_INT" , 0x11800000000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
- {"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
- {"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
- {"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
- {"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
- {"MIO_BOOT_PIN_DEFS" , 0x11800000000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
- {"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
- {"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
- {"MIO_BOOT_THR" , 0x11800000000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 577},
- {"MIO_EMM_BUF_DAT" , 0x11800000020e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 578},
- {"MIO_EMM_BUF_IDX" , 0x11800000020e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
- {"MIO_EMM_CFG" , 0x1180000002000ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
- {"MIO_EMM_CMD" , 0x1180000002058ull, CVMX_CSR_DB_TYPE_RSL, 64, 581},
- {"MIO_EMM_DMA" , 0x1180000002050ull, CVMX_CSR_DB_TYPE_RSL, 64, 582},
- {"MIO_EMM_INT" , 0x1180000002078ull, CVMX_CSR_DB_TYPE_RSL, 64, 583},
- {"MIO_EMM_INT_EN" , 0x1180000002080ull, CVMX_CSR_DB_TYPE_RSL, 64, 584},
- {"MIO_EMM_MODE0" , 0x1180000002008ull, CVMX_CSR_DB_TYPE_RSL, 64, 585},
- {"MIO_EMM_MODE1" , 0x1180000002010ull, CVMX_CSR_DB_TYPE_RSL, 64, 585},
- {"MIO_EMM_MODE2" , 0x1180000002018ull, CVMX_CSR_DB_TYPE_RSL, 64, 585},
- {"MIO_EMM_MODE3" , 0x1180000002020ull, CVMX_CSR_DB_TYPE_RSL, 64, 585},
- {"MIO_EMM_RCA" , 0x11800000020a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 586},
- {"MIO_EMM_RSP_HI" , 0x1180000002070ull, CVMX_CSR_DB_TYPE_RSL, 64, 587},
- {"MIO_EMM_RSP_LO" , 0x1180000002068ull, CVMX_CSR_DB_TYPE_RSL, 64, 588},
- {"MIO_EMM_RSP_STS" , 0x1180000002060ull, CVMX_CSR_DB_TYPE_RSL, 64, 589},
- {"MIO_EMM_SAMPLE" , 0x1180000002090ull, CVMX_CSR_DB_TYPE_RSL, 64, 590},
- {"MIO_EMM_STS_MASK" , 0x1180000002098ull, CVMX_CSR_DB_TYPE_RSL, 64, 591},
- {"MIO_EMM_SWITCH" , 0x1180000002048ull, CVMX_CSR_DB_TYPE_RSL, 64, 592},
- {"MIO_EMM_WDOG" , 0x1180000002088ull, CVMX_CSR_DB_TYPE_RSL, 64, 593},
- {"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 594},
- {"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 594},
- {"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 595},
- {"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 596},
- {"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 597},
- {"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 598},
- {"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 599},
- {"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 600},
- {"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 601},
- {"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
- {"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
- {"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
- {"MIO_FUS_READ_TIMES" , 0x1180000001570ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
- {"MIO_FUS_REPAIR_RES0" , 0x1180000001558ull, CVMX_CSR_DB_TYPE_RSL, 64, 606},
- {"MIO_FUS_REPAIR_RES1" , 0x1180000001560ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
- {"MIO_FUS_REPAIR_RES2" , 0x1180000001568ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
- {"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
- {"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
- {"MIO_FUS_TGG" , 0x1180000001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
- {"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 612},
- {"MIO_GPIO_COMP" , 0x11800000000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 613},
- {"MIO_NDF_DMA_CFG" , 0x1180000000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 614},
- {"MIO_NDF_DMA_INT" , 0x1180000000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 615},
- {"MIO_NDF_DMA_INT_EN" , 0x1180000000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
- {"MIO_PTP_CKOUT_HI_INCR" , 0x1070000000f40ull, CVMX_CSR_DB_TYPE_NCB, 64, 617},
- {"MIO_PTP_CKOUT_LO_INCR" , 0x1070000000f48ull, CVMX_CSR_DB_TYPE_NCB, 64, 618},
- {"MIO_PTP_CKOUT_THRESH_HI" , 0x1070000000f38ull, CVMX_CSR_DB_TYPE_NCB, 64, 619},
- {"MIO_PTP_CKOUT_THRESH_LO" , 0x1070000000f30ull, CVMX_CSR_DB_TYPE_NCB, 64, 620},
- {"MIO_PTP_CLOCK_CFG" , 0x1070000000f00ull, CVMX_CSR_DB_TYPE_NCB, 64, 621},
- {"MIO_PTP_CLOCK_COMP" , 0x1070000000f18ull, CVMX_CSR_DB_TYPE_NCB, 64, 622},
- {"MIO_PTP_CLOCK_HI" , 0x1070000000f10ull, CVMX_CSR_DB_TYPE_NCB, 64, 623},
- {"MIO_PTP_CLOCK_LO" , 0x1070000000f08ull, CVMX_CSR_DB_TYPE_NCB, 64, 624},
- {"MIO_PTP_EVT_CNT" , 0x1070000000f28ull, CVMX_CSR_DB_TYPE_NCB, 64, 625},
- {"MIO_PTP_PHY_1PPS_IN" , 0x1070000000f70ull, CVMX_CSR_DB_TYPE_NCB, 64, 626},
- {"MIO_PTP_PPS_HI_INCR" , 0x1070000000f60ull, CVMX_CSR_DB_TYPE_NCB, 64, 627},
- {"MIO_PTP_PPS_LO_INCR" , 0x1070000000f68ull, CVMX_CSR_DB_TYPE_NCB, 64, 628},
- {"MIO_PTP_PPS_THRESH_HI" , 0x1070000000f58ull, CVMX_CSR_DB_TYPE_NCB, 64, 629},
- {"MIO_PTP_PPS_THRESH_LO" , 0x1070000000f50ull, CVMX_CSR_DB_TYPE_NCB, 64, 630},
- {"MIO_PTP_TIMESTAMP" , 0x1070000000f20ull, CVMX_CSR_DB_TYPE_NCB, 64, 631},
- {"MIO_QLM0_CFG" , 0x1180000001590ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"MIO_QLM1_CFG" , 0x1180000001598ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
- {"MIO_RST_BOOT" , 0x1180000001600ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
- {"MIO_RST_CFG" , 0x1180000001610ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
- {"MIO_RST_CKILL" , 0x1180000001638ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
- {"MIO_RST_CNTL0" , 0x1180000001648ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"MIO_RST_CNTL1" , 0x1180000001650ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
- {"MIO_RST_CTL0" , 0x1180000001618ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
- {"MIO_RST_CTL1" , 0x1180000001620ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
- {"MIO_RST_DELAY" , 0x1180000001608ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
- {"MIO_RST_INT" , 0x1180000001628ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
- {"MIO_RST_INT_EN" , 0x1180000001630ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
- {"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
- {"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
- {"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
- {"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
- {"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
- {"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"MIO_UART1_DLH" , 0x1180000000c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
- {"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"MIO_UART1_DLL" , 0x1180000000c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
- {"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"MIO_UART1_FAR" , 0x1180000000d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
- {"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
- {"MIO_UART1_FCR" , 0x1180000000c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
- {"MIO_UART0_HTX" , 0x1180000000b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"MIO_UART1_HTX" , 0x1180000000f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
- {"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"MIO_UART1_IER" , 0x1180000000c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
- {"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"MIO_UART1_IIR" , 0x1180000000c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
- {"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"MIO_UART1_LCR" , 0x1180000000c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
- {"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"MIO_UART1_LSR" , 0x1180000000c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
- {"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"MIO_UART1_MCR" , 0x1180000000c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
- {"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"MIO_UART1_MSR" , 0x1180000000c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
- {"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"MIO_UART1_RBR" , 0x1180000000c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
- {"MIO_UART0_RFL" , 0x1180000000a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"MIO_UART1_RFL" , 0x1180000000e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
- {"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"MIO_UART1_RFW" , 0x1180000000d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
- {"MIO_UART0_SBCR" , 0x1180000000a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"MIO_UART1_SBCR" , 0x1180000000e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
- {"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"MIO_UART1_SCR" , 0x1180000000c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
- {"MIO_UART0_SFE" , 0x1180000000a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"MIO_UART1_SFE" , 0x1180000000e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
- {"MIO_UART0_SRR" , 0x1180000000a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"MIO_UART1_SRR" , 0x1180000000e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
- {"MIO_UART0_SRT" , 0x1180000000a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"MIO_UART1_SRT" , 0x1180000000e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
- {"MIO_UART0_SRTS" , 0x1180000000a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"MIO_UART1_SRTS" , 0x1180000000e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
- {"MIO_UART0_STT" , 0x1180000000b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"MIO_UART1_STT" , 0x1180000000f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
- {"MIO_UART0_TFL" , 0x1180000000a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"MIO_UART1_TFL" , 0x1180000000e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
- {"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"MIO_UART1_TFR" , 0x1180000000d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
- {"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"MIO_UART1_THR" , 0x1180000000c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
- {"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"MIO_UART1_USR" , 0x1180000000d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
- {"MPI_CFG" , 0x1070000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 670},
- {"MPI_DAT0" , 0x1070000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 671},
- {"MPI_DAT1" , 0x1070000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 671},
- {"MPI_DAT2" , 0x1070000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 671},
- {"MPI_DAT3" , 0x1070000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 671},
- {"MPI_DAT4" , 0x10700000010a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 671},
- {"MPI_DAT5" , 0x10700000010a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 671},
- {"MPI_DAT6" , 0x10700000010b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 671},
- {"MPI_DAT7" , 0x10700000010b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 671},
- {"MPI_DAT8" , 0x10700000010c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 671},
- {"MPI_STS" , 0x1070000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 672},
- {"MPI_TX" , 0x1070000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 673},
- {"PCIEEP0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 674},
- {"PCIEEP1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 674},
- {"PCIEEP0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 675},
- {"PCIEEP1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 675},
- {"PCIEEP0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 676},
- {"PCIEEP1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 676},
- {"PCIEEP0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 677},
- {"PCIEEP1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 677},
- {"PCIEEP0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 678},
- {"PCIEEP1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 678},
- {"PCIEEP0_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 679},
- {"PCIEEP1_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 679},
- {"PCIEEP0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 680},
- {"PCIEEP1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 680},
- {"PCIEEP0_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 681},
- {"PCIEEP1_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 681},
- {"PCIEEP0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 682},
- {"PCIEEP1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 682},
- {"PCIEEP0_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 683},
- {"PCIEEP1_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 683},
- {"PCIEEP0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 684},
- {"PCIEEP1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 684},
- {"PCIEEP0_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 685},
- {"PCIEEP1_CFG007_MASK" , 0x8000001cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 685},
- {"PCIEEP0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 686},
- {"PCIEEP1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 686},
- {"PCIEEP0_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 687},
- {"PCIEEP1_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 687},
- {"PCIEEP0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 688},
- {"PCIEEP1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 688},
- {"PCIEEP0_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 689},
- {"PCIEEP1_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 689},
- {"PCIEEP0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 690},
- {"PCIEEP1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 690},
- {"PCIEEP0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 691},
- {"PCIEEP1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 691},
- {"PCIEEP0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 692},
- {"PCIEEP1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 692},
- {"PCIEEP0_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 693},
- {"PCIEEP1_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 693},
- {"PCIEEP0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 694},
- {"PCIEEP1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 694},
- {"PCIEEP0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 695},
- {"PCIEEP1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 695},
- {"PCIEEP0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 696},
- {"PCIEEP1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 696},
- {"PCIEEP0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 697},
- {"PCIEEP1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 697},
- {"PCIEEP0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 698},
- {"PCIEEP1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 698},
- {"PCIEEP0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 699},
- {"PCIEEP1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 699},
- {"PCIEEP0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 700},
- {"PCIEEP1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 700},
- {"PCIEEP0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 701},
- {"PCIEEP1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 701},
- {"PCIEEP0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 702},
- {"PCIEEP1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 702},
- {"PCIEEP0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 703},
- {"PCIEEP1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 703},
- {"PCIEEP0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 704},
- {"PCIEEP1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 704},
- {"PCIEEP0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 705},
- {"PCIEEP1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 705},
- {"PCIEEP0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 706},
- {"PCIEEP1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 706},
- {"PCIEEP0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 707},
- {"PCIEEP1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 707},
- {"PCIEEP0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 708},
- {"PCIEEP1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 708},
- {"PCIEEP0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 709},
- {"PCIEEP1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 709},
- {"PCIEEP0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 710},
- {"PCIEEP1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 710},
- {"PCIEEP0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 711},
- {"PCIEEP1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 711},
- {"PCIEEP0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 712},
- {"PCIEEP1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 712},
- {"PCIEEP0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 713},
- {"PCIEEP1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 713},
- {"PCIEEP0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 714},
- {"PCIEEP1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 714},
- {"PCIEEP0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 715},
- {"PCIEEP1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 715},
- {"PCIEEP0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 716},
- {"PCIEEP1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 716},
- {"PCIEEP0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 717},
- {"PCIEEP1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 717},
- {"PCIEEP0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 718},
- {"PCIEEP1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 718},
- {"PCIEEP0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 719},
- {"PCIEEP1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 719},
- {"PCIEEP0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 720},
- {"PCIEEP1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 720},
- {"PCIEEP0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 721},
- {"PCIEEP1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 721},
- {"PCIEEP0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 722},
- {"PCIEEP1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 722},
- {"PCIEEP0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 723},
- {"PCIEEP1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 723},
- {"PCIEEP0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 724},
- {"PCIEEP1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 724},
- {"PCIEEP0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 725},
- {"PCIEEP1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 725},
- {"PCIEEP0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 726},
- {"PCIEEP1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 726},
- {"PCIEEP0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 727},
- {"PCIEEP1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 727},
- {"PCIEEP0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 728},
- {"PCIEEP1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 728},
- {"PCIEEP0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 729},
- {"PCIEEP1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 729},
- {"PCIEEP0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 730},
- {"PCIEEP1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 730},
- {"PCIEEP0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 731},
- {"PCIEEP1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 731},
- {"PCIEEP0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 732},
- {"PCIEEP1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 732},
- {"PCIEEP0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 733},
- {"PCIEEP1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 733},
- {"PCIEEP0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 734},
- {"PCIEEP1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 734},
- {"PCIEEP0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 735},
- {"PCIEEP1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 735},
- {"PCIEEP0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 736},
- {"PCIEEP1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 736},
- {"PCIEEP0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 737},
- {"PCIEEP1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 737},
- {"PCIEEP0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 738},
- {"PCIEEP1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 738},
- {"PCIEEP0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 739},
- {"PCIEEP1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 739},
- {"PCIEEP0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 740},
- {"PCIEEP1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 740},
- {"PCIEEP0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 741},
- {"PCIEEP1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 741},
- {"PCIEEP0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 742},
- {"PCIEEP1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 742},
- {"PCIEEP0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 743},
- {"PCIEEP1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 743},
- {"PCIEEP0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 744},
- {"PCIEEP1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 744},
- {"PCIEEP0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 745},
- {"PCIEEP1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 745},
- {"PCIEEP0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 746},
- {"PCIEEP1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 746},
- {"PCIEEP0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 747},
- {"PCIEEP1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 747},
- {"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 748},
- {"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 748},
- {"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 749},
- {"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 749},
- {"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 750},
- {"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 750},
- {"PCIERC0_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 751},
- {"PCIERC1_CFG003" , 0xcull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 751},
- {"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 752},
- {"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 752},
- {"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 753},
- {"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 753},
- {"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 754},
- {"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 754},
- {"PCIERC0_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 755},
- {"PCIERC1_CFG007" , 0x1cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 755},
- {"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 756},
- {"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 756},
- {"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 757},
- {"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 757},
- {"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 758},
- {"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 758},
- {"PCIERC0_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 759},
- {"PCIERC1_CFG011" , 0x2cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 759},
- {"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 760},
- {"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 760},
- {"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 761},
- {"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 761},
- {"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 762},
- {"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 762},
- {"PCIERC0_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 763},
- {"PCIERC1_CFG015" , 0x3cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 763},
- {"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 764},
- {"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 764},
- {"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 765},
- {"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 765},
- {"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 766},
- {"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 766},
- {"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 767},
- {"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 767},
- {"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 768},
- {"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 768},
- {"PCIERC0_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 769},
- {"PCIERC1_CFG023" , 0x5cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 769},
- {"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 770},
- {"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 770},
- {"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 771},
- {"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 771},
- {"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 772},
- {"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 772},
- {"PCIERC0_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 773},
- {"PCIERC1_CFG031" , 0x7cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 773},
- {"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 774},
- {"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 774},
- {"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 775},
- {"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 775},
- {"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 776},
- {"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 776},
- {"PCIERC0_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 777},
- {"PCIERC1_CFG035" , 0x8cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 777},
- {"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 778},
- {"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 778},
- {"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 779},
- {"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 779},
- {"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 780},
- {"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 780},
- {"PCIERC0_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 781},
- {"PCIERC1_CFG039" , 0x9cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 781},
- {"PCIERC0_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 782},
- {"PCIERC1_CFG040" , 0xa0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 782},
- {"PCIERC0_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 783},
- {"PCIERC1_CFG041" , 0xa4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 783},
- {"PCIERC0_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 784},
- {"PCIERC1_CFG042" , 0xa8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 784},
- {"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 785},
- {"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 785},
- {"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 786},
- {"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 786},
- {"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 787},
- {"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 787},
- {"PCIERC0_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 788},
- {"PCIERC1_CFG067" , 0x10cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 788},
- {"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 789},
- {"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 789},
- {"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 790},
- {"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 790},
- {"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 791},
- {"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 791},
- {"PCIERC0_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 792},
- {"PCIERC1_CFG071" , 0x11cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 792},
- {"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 793},
- {"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 793},
- {"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 794},
- {"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 794},
- {"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 795},
- {"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 795},
- {"PCIERC0_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 796},
- {"PCIERC1_CFG075" , 0x12cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 796},
- {"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 797},
- {"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 797},
- {"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 798},
- {"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 798},
- {"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 799},
- {"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 799},
- {"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 800},
- {"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 800},
- {"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 801},
- {"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 801},
- {"PCIERC0_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 802},
- {"PCIERC1_CFG451" , 0x70cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 802},
- {"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 803},
- {"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 803},
- {"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 804},
- {"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 804},
- {"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 805},
- {"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 805},
- {"PCIERC0_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 806},
- {"PCIERC1_CFG455" , 0x71cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 806},
- {"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 807},
- {"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 807},
- {"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 808},
- {"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 808},
- {"PCIERC0_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 809},
- {"PCIERC1_CFG459" , 0x72cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 809},
- {"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 810},
- {"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 810},
- {"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 811},
- {"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 811},
- {"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 812},
- {"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 812},
- {"PCIERC0_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 813},
- {"PCIERC1_CFG463" , 0x73cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 813},
- {"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 814},
- {"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 814},
- {"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 815},
- {"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 815},
- {"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 816},
- {"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 816},
- {"PCIERC0_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 817},
- {"PCIERC1_CFG467" , 0x74cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 817},
- {"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 818},
- {"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 818},
- {"PCIERC0_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 819},
- {"PCIERC1_CFG490" , 0x7a8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 819},
- {"PCIERC0_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 820},
- {"PCIERC1_CFG491" , 0x7acull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 820},
- {"PCIERC0_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 821},
- {"PCIERC1_CFG492" , 0x7b0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 821},
- {"PCIERC0_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 822},
- {"PCIERC1_CFG515" , 0x80cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 822},
- {"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 823},
- {"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 823},
- {"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 824},
- {"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 824},
- {"PCM0_DMA_CFG" , 0x1070000010018ull, CVMX_CSR_DB_TYPE_NCB, 64, 825},
- {"PCM1_DMA_CFG" , 0x1070000014018ull, CVMX_CSR_DB_TYPE_NCB, 64, 825},
- {"PCM2_DMA_CFG" , 0x1070000018018ull, CVMX_CSR_DB_TYPE_NCB, 64, 825},
- {"PCM3_DMA_CFG" , 0x107000001c018ull, CVMX_CSR_DB_TYPE_NCB, 64, 825},
- {"PCM0_INT_ENA" , 0x1070000010020ull, CVMX_CSR_DB_TYPE_NCB, 64, 826},
- {"PCM1_INT_ENA" , 0x1070000014020ull, CVMX_CSR_DB_TYPE_NCB, 64, 826},
- {"PCM2_INT_ENA" , 0x1070000018020ull, CVMX_CSR_DB_TYPE_NCB, 64, 826},
- {"PCM3_INT_ENA" , 0x107000001c020ull, CVMX_CSR_DB_TYPE_NCB, 64, 826},
- {"PCM0_INT_SUM" , 0x1070000010028ull, CVMX_CSR_DB_TYPE_NCB, 64, 827},
- {"PCM1_INT_SUM" , 0x1070000014028ull, CVMX_CSR_DB_TYPE_NCB, 64, 827},
- {"PCM2_INT_SUM" , 0x1070000018028ull, CVMX_CSR_DB_TYPE_NCB, 64, 827},
- {"PCM3_INT_SUM" , 0x107000001c028ull, CVMX_CSR_DB_TYPE_NCB, 64, 827},
- {"PCM0_RXADDR" , 0x1070000010068ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
- {"PCM1_RXADDR" , 0x1070000014068ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
- {"PCM2_RXADDR" , 0x1070000018068ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
- {"PCM3_RXADDR" , 0x107000001c068ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
- {"PCM0_RXCNT" , 0x1070000010060ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"PCM1_RXCNT" , 0x1070000014060ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"PCM2_RXCNT" , 0x1070000018060ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"PCM3_RXCNT" , 0x107000001c060ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
- {"PCM0_RXMSK0" , 0x10700000100c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"PCM1_RXMSK0" , 0x10700000140c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"PCM2_RXMSK0" , 0x10700000180c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"PCM3_RXMSK0" , 0x107000001c0c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
- {"PCM0_RXMSK1" , 0x10700000100c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 831},
- {"PCM1_RXMSK1" , 0x10700000140c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 831},
- {"PCM2_RXMSK1" , 0x10700000180c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 831},
- {"PCM3_RXMSK1" , 0x107000001c0c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 831},
- {"PCM0_RXMSK2" , 0x10700000100d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 832},
- {"PCM1_RXMSK2" , 0x10700000140d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 832},
- {"PCM2_RXMSK2" , 0x10700000180d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 832},
- {"PCM3_RXMSK2" , 0x107000001c0d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 832},
- {"PCM0_RXMSK3" , 0x10700000100d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"PCM1_RXMSK3" , 0x10700000140d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"PCM2_RXMSK3" , 0x10700000180d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"PCM3_RXMSK3" , 0x107000001c0d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
- {"PCM0_RXMSK4" , 0x10700000100e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 834},
- {"PCM1_RXMSK4" , 0x10700000140e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 834},
- {"PCM2_RXMSK4" , 0x10700000180e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 834},
- {"PCM3_RXMSK4" , 0x107000001c0e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 834},
- {"PCM0_RXMSK5" , 0x10700000100e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"PCM1_RXMSK5" , 0x10700000140e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"PCM2_RXMSK5" , 0x10700000180e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"PCM3_RXMSK5" , 0x107000001c0e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
- {"PCM0_RXMSK6" , 0x10700000100f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 836},
- {"PCM1_RXMSK6" , 0x10700000140f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 836},
- {"PCM2_RXMSK6" , 0x10700000180f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 836},
- {"PCM3_RXMSK6" , 0x107000001c0f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 836},
- {"PCM0_RXMSK7" , 0x10700000100f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"PCM1_RXMSK7" , 0x10700000140f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"PCM2_RXMSK7" , 0x10700000180f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"PCM3_RXMSK7" , 0x107000001c0f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
- {"PCM0_RXSTART" , 0x1070000010058ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"PCM1_RXSTART" , 0x1070000014058ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"PCM2_RXSTART" , 0x1070000018058ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"PCM3_RXSTART" , 0x107000001c058ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
- {"PCM0_TDM_CFG" , 0x1070000010010ull, CVMX_CSR_DB_TYPE_NCB, 64, 839},
- {"PCM1_TDM_CFG" , 0x1070000014010ull, CVMX_CSR_DB_TYPE_NCB, 64, 839},
- {"PCM2_TDM_CFG" , 0x1070000018010ull, CVMX_CSR_DB_TYPE_NCB, 64, 839},
- {"PCM3_TDM_CFG" , 0x107000001c010ull, CVMX_CSR_DB_TYPE_NCB, 64, 839},
- {"PCM0_TDM_DBG" , 0x1070000010030ull, CVMX_CSR_DB_TYPE_NCB, 64, 840},
- {"PCM1_TDM_DBG" , 0x1070000014030ull, CVMX_CSR_DB_TYPE_NCB, 64, 840},
- {"PCM2_TDM_DBG" , 0x1070000018030ull, CVMX_CSR_DB_TYPE_NCB, 64, 840},
- {"PCM3_TDM_DBG" , 0x107000001c030ull, CVMX_CSR_DB_TYPE_NCB, 64, 840},
- {"PCM0_TXADDR" , 0x1070000010050ull, CVMX_CSR_DB_TYPE_NCB, 64, 841},
- {"PCM1_TXADDR" , 0x1070000014050ull, CVMX_CSR_DB_TYPE_NCB, 64, 841},
- {"PCM2_TXADDR" , 0x1070000018050ull, CVMX_CSR_DB_TYPE_NCB, 64, 841},
- {"PCM3_TXADDR" , 0x107000001c050ull, CVMX_CSR_DB_TYPE_NCB, 64, 841},
- {"PCM0_TXCNT" , 0x1070000010048ull, CVMX_CSR_DB_TYPE_NCB, 64, 842},
- {"PCM1_TXCNT" , 0x1070000014048ull, CVMX_CSR_DB_TYPE_NCB, 64, 842},
- {"PCM2_TXCNT" , 0x1070000018048ull, CVMX_CSR_DB_TYPE_NCB, 64, 842},
- {"PCM3_TXCNT" , 0x107000001c048ull, CVMX_CSR_DB_TYPE_NCB, 64, 842},
- {"PCM0_TXMSK0" , 0x1070000010080ull, CVMX_CSR_DB_TYPE_NCB, 64, 843},
- {"PCM1_TXMSK0" , 0x1070000014080ull, CVMX_CSR_DB_TYPE_NCB, 64, 843},
- {"PCM2_TXMSK0" , 0x1070000018080ull, CVMX_CSR_DB_TYPE_NCB, 64, 843},
- {"PCM3_TXMSK0" , 0x107000001c080ull, CVMX_CSR_DB_TYPE_NCB, 64, 843},
- {"PCM0_TXMSK1" , 0x1070000010088ull, CVMX_CSR_DB_TYPE_NCB, 64, 844},
- {"PCM1_TXMSK1" , 0x1070000014088ull, CVMX_CSR_DB_TYPE_NCB, 64, 844},
- {"PCM2_TXMSK1" , 0x1070000018088ull, CVMX_CSR_DB_TYPE_NCB, 64, 844},
- {"PCM3_TXMSK1" , 0x107000001c088ull, CVMX_CSR_DB_TYPE_NCB, 64, 844},
- {"PCM0_TXMSK2" , 0x1070000010090ull, CVMX_CSR_DB_TYPE_NCB, 64, 845},
- {"PCM1_TXMSK2" , 0x1070000014090ull, CVMX_CSR_DB_TYPE_NCB, 64, 845},
- {"PCM2_TXMSK2" , 0x1070000018090ull, CVMX_CSR_DB_TYPE_NCB, 64, 845},
- {"PCM3_TXMSK2" , 0x107000001c090ull, CVMX_CSR_DB_TYPE_NCB, 64, 845},
- {"PCM0_TXMSK3" , 0x1070000010098ull, CVMX_CSR_DB_TYPE_NCB, 64, 846},
- {"PCM1_TXMSK3" , 0x1070000014098ull, CVMX_CSR_DB_TYPE_NCB, 64, 846},
- {"PCM2_TXMSK3" , 0x1070000018098ull, CVMX_CSR_DB_TYPE_NCB, 64, 846},
- {"PCM3_TXMSK3" , 0x107000001c098ull, CVMX_CSR_DB_TYPE_NCB, 64, 846},
- {"PCM0_TXMSK4" , 0x10700000100a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"PCM1_TXMSK4" , 0x10700000140a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"PCM2_TXMSK4" , 0x10700000180a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"PCM3_TXMSK4" , 0x107000001c0a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 847},
- {"PCM0_TXMSK5" , 0x10700000100a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 848},
- {"PCM1_TXMSK5" , 0x10700000140a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 848},
- {"PCM2_TXMSK5" , 0x10700000180a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 848},
- {"PCM3_TXMSK5" , 0x107000001c0a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 848},
- {"PCM0_TXMSK6" , 0x10700000100b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 849},
- {"PCM1_TXMSK6" , 0x10700000140b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 849},
- {"PCM2_TXMSK6" , 0x10700000180b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 849},
- {"PCM3_TXMSK6" , 0x107000001c0b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 849},
- {"PCM0_TXMSK7" , 0x10700000100b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 850},
- {"PCM1_TXMSK7" , 0x10700000140b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 850},
- {"PCM2_TXMSK7" , 0x10700000180b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 850},
- {"PCM3_TXMSK7" , 0x107000001c0b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 850},
- {"PCM0_TXSTART" , 0x1070000010040ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"PCM1_TXSTART" , 0x1070000014040ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"PCM2_TXSTART" , 0x1070000018040ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"PCM3_TXSTART" , 0x107000001c040ull, CVMX_CSR_DB_TYPE_NCB, 64, 851},
- {"PCM_CLK0_CFG" , 0x1070000010000ull, CVMX_CSR_DB_TYPE_NCB, 64, 852},
- {"PCM_CLK1_CFG" , 0x1070000014000ull, CVMX_CSR_DB_TYPE_NCB, 64, 852},
- {"PCM_CLK0_DBG" , 0x1070000010038ull, CVMX_CSR_DB_TYPE_NCB, 64, 853},
- {"PCM_CLK1_DBG" , 0x1070000014038ull, CVMX_CSR_DB_TYPE_NCB, 64, 853},
- {"PCM_CLK0_GEN" , 0x1070000010008ull, CVMX_CSR_DB_TYPE_NCB, 64, 854},
- {"PCM_CLK1_GEN" , 0x1070000014008ull, CVMX_CSR_DB_TYPE_NCB, 64, 854},
- {"PCS0_AN000_ADV_REG" , 0x11800b0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"PCS0_AN001_ADV_REG" , 0x11800b0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
- {"PCS0_AN000_EXT_ST_REG" , 0x11800b0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"PCS0_AN001_EXT_ST_REG" , 0x11800b0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
- {"PCS0_AN000_LP_ABIL_REG" , 0x11800b0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"PCS0_AN001_LP_ABIL_REG" , 0x11800b0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
- {"PCS0_AN000_RESULTS_REG" , 0x11800b0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"PCS0_AN001_RESULTS_REG" , 0x11800b0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
- {"PCS0_INT000_EN_REG" , 0x11800b0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"PCS0_INT001_EN_REG" , 0x11800b0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
- {"PCS0_INT000_REG" , 0x11800b0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"PCS0_INT001_REG" , 0x11800b0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
- {"PCS0_LINK000_TIMER_COUNT_REG", 0x11800b0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"PCS0_LINK001_TIMER_COUNT_REG", 0x11800b0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
- {"PCS0_LOG_ANL000_REG" , 0x11800b0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"PCS0_LOG_ANL001_REG" , 0x11800b0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
- {"PCS0_MISC000_CTL_REG" , 0x11800b0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"PCS0_MISC001_CTL_REG" , 0x11800b0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
- {"PCS0_MR000_CONTROL_REG" , 0x11800b0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"PCS0_MR001_CONTROL_REG" , 0x11800b0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
- {"PCS0_MR000_STATUS_REG" , 0x11800b0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 865},
- {"PCS0_MR001_STATUS_REG" , 0x11800b0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 865},
- {"PCS0_RX000_STATES_REG" , 0x11800b0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
- {"PCS0_RX001_STATES_REG" , 0x11800b0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
- {"PCS0_RX000_SYNC_REG" , 0x11800b0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
- {"PCS0_RX001_SYNC_REG" , 0x11800b0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
- {"PCS0_SGM000_AN_ADV_REG" , 0x11800b0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
- {"PCS0_SGM001_AN_ADV_REG" , 0x11800b0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
- {"PCS0_SGM000_LP_ADV_REG" , 0x11800b0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 869},
- {"PCS0_SGM001_LP_ADV_REG" , 0x11800b0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 869},
- {"PCS0_TX000_STATES_REG" , 0x11800b0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 870},
- {"PCS0_TX001_STATES_REG" , 0x11800b0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 870},
- {"PCS0_TX_RX000_POLARITY_REG" , 0x11800b0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 871},
- {"PCS0_TX_RX001_POLARITY_REG" , 0x11800b0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 871},
- {"PEM0_BAR1_INDEX000" , 0x11800c00000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX001" , 0x11800c00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX002" , 0x11800c00000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX003" , 0x11800c00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX004" , 0x11800c00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX005" , 0x11800c00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX006" , 0x11800c00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX007" , 0x11800c00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX008" , 0x11800c00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX009" , 0x11800c00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX010" , 0x11800c00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX011" , 0x11800c0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX012" , 0x11800c0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX013" , 0x11800c0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX014" , 0x11800c0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR1_INDEX015" , 0x11800c0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX000" , 0x11800c10000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX001" , 0x11800c10000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX002" , 0x11800c10000b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX003" , 0x11800c10000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX004" , 0x11800c10000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX005" , 0x11800c10000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX006" , 0x11800c10000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX007" , 0x11800c10000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX008" , 0x11800c10000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX009" , 0x11800c10000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX010" , 0x11800c10000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX011" , 0x11800c1000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX012" , 0x11800c1000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX013" , 0x11800c1000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX014" , 0x11800c1000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM1_BAR1_INDEX015" , 0x11800c1000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
- {"PEM0_BAR2_MASK" , 0x11800c0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
- {"PEM1_BAR2_MASK" , 0x11800c1000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
- {"PEM0_BAR_CTL" , 0x11800c0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 874},
- {"PEM1_BAR_CTL" , 0x11800c1000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 874},
- {"PEM0_BIST_STATUS" , 0x11800c0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 875},
- {"PEM1_BIST_STATUS" , 0x11800c1000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 875},
- {"PEM0_BIST_STATUS2" , 0x11800c0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 876},
- {"PEM1_BIST_STATUS2" , 0x11800c1000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 876},
- {"PEM0_CFG_RD" , 0x11800c0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 877},
- {"PEM1_CFG_RD" , 0x11800c1000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 877},
- {"PEM0_CFG_WR" , 0x11800c0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 878},
- {"PEM1_CFG_WR" , 0x11800c1000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 878},
- {"PEM0_CPL_LUT_VALID" , 0x11800c0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 879},
- {"PEM1_CPL_LUT_VALID" , 0x11800c1000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 879},
- {"PEM0_CTL_STATUS" , 0x11800c0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 880},
- {"PEM1_CTL_STATUS" , 0x11800c1000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 880},
- {"PEM0_DBG_INFO" , 0x11800c0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
- {"PEM1_DBG_INFO" , 0x11800c1000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
- {"PEM0_DBG_INFO_EN" , 0x11800c00000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
- {"PEM1_DBG_INFO_EN" , 0x11800c10000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
- {"PEM0_DIAG_STATUS" , 0x11800c0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 883},
- {"PEM1_DIAG_STATUS" , 0x11800c1000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 883},
- {"PEM0_INB_READ_CREDITS" , 0x11800c0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 884},
- {"PEM1_INB_READ_CREDITS" , 0x11800c1000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 884},
- {"PEM0_INT_ENB" , 0x11800c0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 885},
- {"PEM1_INT_ENB" , 0x11800c1000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 885},
- {"PEM0_INT_ENB_INT" , 0x11800c0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 886},
- {"PEM1_INT_ENB_INT" , 0x11800c1000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 886},
- {"PEM0_INT_SUM" , 0x11800c0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 887},
- {"PEM1_INT_SUM" , 0x11800c1000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 887},
- {"PEM0_P2N_BAR0_START" , 0x11800c0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 888},
- {"PEM1_P2N_BAR0_START" , 0x11800c1000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 888},
- {"PEM0_P2N_BAR1_START" , 0x11800c0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 889},
- {"PEM1_P2N_BAR1_START" , 0x11800c1000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 889},
- {"PEM0_P2N_BAR2_START" , 0x11800c0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 890},
- {"PEM1_P2N_BAR2_START" , 0x11800c1000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 890},
- {"PEM0_TLP_CREDITS" , 0x11800c0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 891},
- {"PEM1_TLP_CREDITS" , 0x11800c1000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 891},
- {"PIP_ALT_SKIP_CFG0" , 0x11800a0002a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
- {"PIP_ALT_SKIP_CFG1" , 0x11800a0002a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
- {"PIP_ALT_SKIP_CFG2" , 0x11800a0002a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
- {"PIP_ALT_SKIP_CFG3" , 0x11800a0002a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
- {"PIP_BCK_PRS" , 0x11800a0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 893},
- {"PIP_BIST_STATUS" , 0x11800a0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 894},
- {"PIP_BSEL_EXT_CFG0" , 0x11800a0002800ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
- {"PIP_BSEL_EXT_CFG1" , 0x11800a0002810ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
- {"PIP_BSEL_EXT_CFG2" , 0x11800a0002820ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
- {"PIP_BSEL_EXT_CFG3" , 0x11800a0002830ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
- {"PIP_BSEL_EXT_POS0" , 0x11800a0002808ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
- {"PIP_BSEL_EXT_POS1" , 0x11800a0002818ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
- {"PIP_BSEL_EXT_POS2" , 0x11800a0002828ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
- {"PIP_BSEL_EXT_POS3" , 0x11800a0002838ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
- {"PIP_BSEL_TBL_ENT0" , 0x11800a0003000ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT1" , 0x11800a0003008ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT2" , 0x11800a0003010ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT3" , 0x11800a0003018ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT4" , 0x11800a0003020ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT5" , 0x11800a0003028ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT6" , 0x11800a0003030ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT7" , 0x11800a0003038ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT8" , 0x11800a0003040ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT9" , 0x11800a0003048ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT10" , 0x11800a0003050ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT11" , 0x11800a0003058ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT12" , 0x11800a0003060ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT13" , 0x11800a0003068ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT14" , 0x11800a0003070ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT15" , 0x11800a0003078ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT16" , 0x11800a0003080ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT17" , 0x11800a0003088ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT18" , 0x11800a0003090ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT19" , 0x11800a0003098ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT20" , 0x11800a00030a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT21" , 0x11800a00030a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT22" , 0x11800a00030b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT23" , 0x11800a00030b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT24" , 0x11800a00030c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT25" , 0x11800a00030c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT26" , 0x11800a00030d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT27" , 0x11800a00030d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT28" , 0x11800a00030e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT29" , 0x11800a00030e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT30" , 0x11800a00030f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT31" , 0x11800a00030f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT32" , 0x11800a0003100ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT33" , 0x11800a0003108ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT34" , 0x11800a0003110ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT35" , 0x11800a0003118ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT36" , 0x11800a0003120ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT37" , 0x11800a0003128ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT38" , 0x11800a0003130ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT39" , 0x11800a0003138ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT40" , 0x11800a0003140ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT41" , 0x11800a0003148ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT42" , 0x11800a0003150ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT43" , 0x11800a0003158ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT44" , 0x11800a0003160ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT45" , 0x11800a0003168ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT46" , 0x11800a0003170ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT47" , 0x11800a0003178ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT48" , 0x11800a0003180ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT49" , 0x11800a0003188ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT50" , 0x11800a0003190ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT51" , 0x11800a0003198ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT52" , 0x11800a00031a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT53" , 0x11800a00031a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT54" , 0x11800a00031b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT55" , 0x11800a00031b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT56" , 0x11800a00031c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT57" , 0x11800a00031c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT58" , 0x11800a00031d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT59" , 0x11800a00031d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT60" , 0x11800a00031e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT61" , 0x11800a00031e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT62" , 0x11800a00031f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT63" , 0x11800a00031f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT64" , 0x11800a0003200ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT65" , 0x11800a0003208ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT66" , 0x11800a0003210ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT67" , 0x11800a0003218ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT68" , 0x11800a0003220ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT69" , 0x11800a0003228ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT70" , 0x11800a0003230ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT71" , 0x11800a0003238ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT72" , 0x11800a0003240ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT73" , 0x11800a0003248ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT74" , 0x11800a0003250ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT75" , 0x11800a0003258ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT76" , 0x11800a0003260ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT77" , 0x11800a0003268ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT78" , 0x11800a0003270ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT79" , 0x11800a0003278ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT80" , 0x11800a0003280ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT81" , 0x11800a0003288ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT82" , 0x11800a0003290ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT83" , 0x11800a0003298ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT84" , 0x11800a00032a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT85" , 0x11800a00032a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT86" , 0x11800a00032b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT87" , 0x11800a00032b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT88" , 0x11800a00032c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT89" , 0x11800a00032c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT90" , 0x11800a00032d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT91" , 0x11800a00032d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT92" , 0x11800a00032e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT93" , 0x11800a00032e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT94" , 0x11800a00032f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT95" , 0x11800a00032f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT96" , 0x11800a0003300ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT97" , 0x11800a0003308ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT98" , 0x11800a0003310ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT99" , 0x11800a0003318ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT100" , 0x11800a0003320ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT101" , 0x11800a0003328ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT102" , 0x11800a0003330ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT103" , 0x11800a0003338ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT104" , 0x11800a0003340ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT105" , 0x11800a0003348ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT106" , 0x11800a0003350ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT107" , 0x11800a0003358ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT108" , 0x11800a0003360ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT109" , 0x11800a0003368ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT110" , 0x11800a0003370ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT111" , 0x11800a0003378ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT112" , 0x11800a0003380ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT113" , 0x11800a0003388ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT114" , 0x11800a0003390ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT115" , 0x11800a0003398ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT116" , 0x11800a00033a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT117" , 0x11800a00033a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT118" , 0x11800a00033b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT119" , 0x11800a00033b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT120" , 0x11800a00033c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT121" , 0x11800a00033c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT122" , 0x11800a00033d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT123" , 0x11800a00033d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT124" , 0x11800a00033e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT125" , 0x11800a00033e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT126" , 0x11800a00033f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT127" , 0x11800a00033f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT128" , 0x11800a0003400ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT129" , 0x11800a0003408ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT130" , 0x11800a0003410ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT131" , 0x11800a0003418ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT132" , 0x11800a0003420ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT133" , 0x11800a0003428ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT134" , 0x11800a0003430ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT135" , 0x11800a0003438ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT136" , 0x11800a0003440ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT137" , 0x11800a0003448ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT138" , 0x11800a0003450ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT139" , 0x11800a0003458ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT140" , 0x11800a0003460ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT141" , 0x11800a0003468ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT142" , 0x11800a0003470ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT143" , 0x11800a0003478ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT144" , 0x11800a0003480ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT145" , 0x11800a0003488ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT146" , 0x11800a0003490ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT147" , 0x11800a0003498ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT148" , 0x11800a00034a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT149" , 0x11800a00034a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT150" , 0x11800a00034b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT151" , 0x11800a00034b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT152" , 0x11800a00034c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT153" , 0x11800a00034c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT154" , 0x11800a00034d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT155" , 0x11800a00034d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT156" , 0x11800a00034e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT157" , 0x11800a00034e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT158" , 0x11800a00034f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT159" , 0x11800a00034f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT160" , 0x11800a0003500ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT161" , 0x11800a0003508ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT162" , 0x11800a0003510ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT163" , 0x11800a0003518ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT164" , 0x11800a0003520ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT165" , 0x11800a0003528ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT166" , 0x11800a0003530ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT167" , 0x11800a0003538ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT168" , 0x11800a0003540ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT169" , 0x11800a0003548ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT170" , 0x11800a0003550ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT171" , 0x11800a0003558ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT172" , 0x11800a0003560ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT173" , 0x11800a0003568ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT174" , 0x11800a0003570ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT175" , 0x11800a0003578ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT176" , 0x11800a0003580ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT177" , 0x11800a0003588ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT178" , 0x11800a0003590ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT179" , 0x11800a0003598ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT180" , 0x11800a00035a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT181" , 0x11800a00035a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT182" , 0x11800a00035b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT183" , 0x11800a00035b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT184" , 0x11800a00035c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT185" , 0x11800a00035c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT186" , 0x11800a00035d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT187" , 0x11800a00035d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT188" , 0x11800a00035e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT189" , 0x11800a00035e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT190" , 0x11800a00035f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT191" , 0x11800a00035f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT192" , 0x11800a0003600ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT193" , 0x11800a0003608ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT194" , 0x11800a0003610ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT195" , 0x11800a0003618ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT196" , 0x11800a0003620ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT197" , 0x11800a0003628ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT198" , 0x11800a0003630ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT199" , 0x11800a0003638ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT200" , 0x11800a0003640ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT201" , 0x11800a0003648ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT202" , 0x11800a0003650ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT203" , 0x11800a0003658ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT204" , 0x11800a0003660ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT205" , 0x11800a0003668ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT206" , 0x11800a0003670ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT207" , 0x11800a0003678ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT208" , 0x11800a0003680ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT209" , 0x11800a0003688ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT210" , 0x11800a0003690ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT211" , 0x11800a0003698ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT212" , 0x11800a00036a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT213" , 0x11800a00036a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT214" , 0x11800a00036b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT215" , 0x11800a00036b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT216" , 0x11800a00036c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT217" , 0x11800a00036c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT218" , 0x11800a00036d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT219" , 0x11800a00036d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT220" , 0x11800a00036e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT221" , 0x11800a00036e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT222" , 0x11800a00036f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT223" , 0x11800a00036f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT224" , 0x11800a0003700ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT225" , 0x11800a0003708ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT226" , 0x11800a0003710ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT227" , 0x11800a0003718ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT228" , 0x11800a0003720ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT229" , 0x11800a0003728ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT230" , 0x11800a0003730ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT231" , 0x11800a0003738ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT232" , 0x11800a0003740ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT233" , 0x11800a0003748ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT234" , 0x11800a0003750ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT235" , 0x11800a0003758ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT236" , 0x11800a0003760ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT237" , 0x11800a0003768ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT238" , 0x11800a0003770ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT239" , 0x11800a0003778ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT240" , 0x11800a0003780ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT241" , 0x11800a0003788ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT242" , 0x11800a0003790ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT243" , 0x11800a0003798ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT244" , 0x11800a00037a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT245" , 0x11800a00037a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT246" , 0x11800a00037b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT247" , 0x11800a00037b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT248" , 0x11800a00037c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT249" , 0x11800a00037c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT250" , 0x11800a00037d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT251" , 0x11800a00037d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT252" , 0x11800a00037e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT253" , 0x11800a00037e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT254" , 0x11800a00037f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT255" , 0x11800a00037f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT256" , 0x11800a0003800ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT257" , 0x11800a0003808ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT258" , 0x11800a0003810ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT259" , 0x11800a0003818ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT260" , 0x11800a0003820ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT261" , 0x11800a0003828ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT262" , 0x11800a0003830ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT263" , 0x11800a0003838ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT264" , 0x11800a0003840ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT265" , 0x11800a0003848ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT266" , 0x11800a0003850ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT267" , 0x11800a0003858ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT268" , 0x11800a0003860ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT269" , 0x11800a0003868ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT270" , 0x11800a0003870ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT271" , 0x11800a0003878ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT272" , 0x11800a0003880ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT273" , 0x11800a0003888ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT274" , 0x11800a0003890ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT275" , 0x11800a0003898ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT276" , 0x11800a00038a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT277" , 0x11800a00038a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT278" , 0x11800a00038b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT279" , 0x11800a00038b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT280" , 0x11800a00038c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT281" , 0x11800a00038c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT282" , 0x11800a00038d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT283" , 0x11800a00038d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT284" , 0x11800a00038e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT285" , 0x11800a00038e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT286" , 0x11800a00038f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT287" , 0x11800a00038f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT288" , 0x11800a0003900ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT289" , 0x11800a0003908ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT290" , 0x11800a0003910ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT291" , 0x11800a0003918ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT292" , 0x11800a0003920ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT293" , 0x11800a0003928ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT294" , 0x11800a0003930ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT295" , 0x11800a0003938ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT296" , 0x11800a0003940ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT297" , 0x11800a0003948ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT298" , 0x11800a0003950ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT299" , 0x11800a0003958ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT300" , 0x11800a0003960ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT301" , 0x11800a0003968ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT302" , 0x11800a0003970ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT303" , 0x11800a0003978ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT304" , 0x11800a0003980ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT305" , 0x11800a0003988ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT306" , 0x11800a0003990ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT307" , 0x11800a0003998ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT308" , 0x11800a00039a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT309" , 0x11800a00039a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT310" , 0x11800a00039b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT311" , 0x11800a00039b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT312" , 0x11800a00039c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT313" , 0x11800a00039c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT314" , 0x11800a00039d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT315" , 0x11800a00039d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT316" , 0x11800a00039e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT317" , 0x11800a00039e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT318" , 0x11800a00039f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT319" , 0x11800a00039f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT320" , 0x11800a0003a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT321" , 0x11800a0003a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT322" , 0x11800a0003a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT323" , 0x11800a0003a18ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT324" , 0x11800a0003a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT325" , 0x11800a0003a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT326" , 0x11800a0003a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT327" , 0x11800a0003a38ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT328" , 0x11800a0003a40ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT329" , 0x11800a0003a48ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT330" , 0x11800a0003a50ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT331" , 0x11800a0003a58ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT332" , 0x11800a0003a60ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT333" , 0x11800a0003a68ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT334" , 0x11800a0003a70ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT335" , 0x11800a0003a78ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT336" , 0x11800a0003a80ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT337" , 0x11800a0003a88ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT338" , 0x11800a0003a90ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT339" , 0x11800a0003a98ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT340" , 0x11800a0003aa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT341" , 0x11800a0003aa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT342" , 0x11800a0003ab0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT343" , 0x11800a0003ab8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT344" , 0x11800a0003ac0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT345" , 0x11800a0003ac8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT346" , 0x11800a0003ad0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT347" , 0x11800a0003ad8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT348" , 0x11800a0003ae0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT349" , 0x11800a0003ae8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT350" , 0x11800a0003af0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT351" , 0x11800a0003af8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT352" , 0x11800a0003b00ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT353" , 0x11800a0003b08ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT354" , 0x11800a0003b10ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT355" , 0x11800a0003b18ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT356" , 0x11800a0003b20ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT357" , 0x11800a0003b28ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT358" , 0x11800a0003b30ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT359" , 0x11800a0003b38ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT360" , 0x11800a0003b40ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT361" , 0x11800a0003b48ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT362" , 0x11800a0003b50ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT363" , 0x11800a0003b58ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT364" , 0x11800a0003b60ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT365" , 0x11800a0003b68ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT366" , 0x11800a0003b70ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT367" , 0x11800a0003b78ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT368" , 0x11800a0003b80ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT369" , 0x11800a0003b88ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT370" , 0x11800a0003b90ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT371" , 0x11800a0003b98ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT372" , 0x11800a0003ba0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT373" , 0x11800a0003ba8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT374" , 0x11800a0003bb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT375" , 0x11800a0003bb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT376" , 0x11800a0003bc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT377" , 0x11800a0003bc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT378" , 0x11800a0003bd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT379" , 0x11800a0003bd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT380" , 0x11800a0003be0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT381" , 0x11800a0003be8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT382" , 0x11800a0003bf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT383" , 0x11800a0003bf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT384" , 0x11800a0003c00ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT385" , 0x11800a0003c08ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT386" , 0x11800a0003c10ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT387" , 0x11800a0003c18ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT388" , 0x11800a0003c20ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT389" , 0x11800a0003c28ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT390" , 0x11800a0003c30ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT391" , 0x11800a0003c38ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT392" , 0x11800a0003c40ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT393" , 0x11800a0003c48ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT394" , 0x11800a0003c50ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT395" , 0x11800a0003c58ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT396" , 0x11800a0003c60ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT397" , 0x11800a0003c68ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT398" , 0x11800a0003c70ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT399" , 0x11800a0003c78ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT400" , 0x11800a0003c80ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT401" , 0x11800a0003c88ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT402" , 0x11800a0003c90ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT403" , 0x11800a0003c98ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT404" , 0x11800a0003ca0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT405" , 0x11800a0003ca8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT406" , 0x11800a0003cb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT407" , 0x11800a0003cb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT408" , 0x11800a0003cc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT409" , 0x11800a0003cc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT410" , 0x11800a0003cd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT411" , 0x11800a0003cd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT412" , 0x11800a0003ce0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT413" , 0x11800a0003ce8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT414" , 0x11800a0003cf0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT415" , 0x11800a0003cf8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT416" , 0x11800a0003d00ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT417" , 0x11800a0003d08ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT418" , 0x11800a0003d10ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT419" , 0x11800a0003d18ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT420" , 0x11800a0003d20ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT421" , 0x11800a0003d28ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT422" , 0x11800a0003d30ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT423" , 0x11800a0003d38ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT424" , 0x11800a0003d40ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT425" , 0x11800a0003d48ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT426" , 0x11800a0003d50ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT427" , 0x11800a0003d58ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT428" , 0x11800a0003d60ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT429" , 0x11800a0003d68ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT430" , 0x11800a0003d70ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT431" , 0x11800a0003d78ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT432" , 0x11800a0003d80ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT433" , 0x11800a0003d88ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT434" , 0x11800a0003d90ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT435" , 0x11800a0003d98ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT436" , 0x11800a0003da0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT437" , 0x11800a0003da8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT438" , 0x11800a0003db0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT439" , 0x11800a0003db8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT440" , 0x11800a0003dc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT441" , 0x11800a0003dc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT442" , 0x11800a0003dd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT443" , 0x11800a0003dd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT444" , 0x11800a0003de0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT445" , 0x11800a0003de8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT446" , 0x11800a0003df0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT447" , 0x11800a0003df8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT448" , 0x11800a0003e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT449" , 0x11800a0003e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT450" , 0x11800a0003e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT451" , 0x11800a0003e18ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT452" , 0x11800a0003e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT453" , 0x11800a0003e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT454" , 0x11800a0003e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT455" , 0x11800a0003e38ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT456" , 0x11800a0003e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT457" , 0x11800a0003e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT458" , 0x11800a0003e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT459" , 0x11800a0003e58ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT460" , 0x11800a0003e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT461" , 0x11800a0003e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT462" , 0x11800a0003e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT463" , 0x11800a0003e78ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT464" , 0x11800a0003e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT465" , 0x11800a0003e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT466" , 0x11800a0003e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT467" , 0x11800a0003e98ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT468" , 0x11800a0003ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT469" , 0x11800a0003ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT470" , 0x11800a0003eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT471" , 0x11800a0003eb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT472" , 0x11800a0003ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT473" , 0x11800a0003ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT474" , 0x11800a0003ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT475" , 0x11800a0003ed8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT476" , 0x11800a0003ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT477" , 0x11800a0003ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT478" , 0x11800a0003ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT479" , 0x11800a0003ef8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT480" , 0x11800a0003f00ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT481" , 0x11800a0003f08ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT482" , 0x11800a0003f10ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT483" , 0x11800a0003f18ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT484" , 0x11800a0003f20ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT485" , 0x11800a0003f28ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT486" , 0x11800a0003f30ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT487" , 0x11800a0003f38ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT488" , 0x11800a0003f40ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT489" , 0x11800a0003f48ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT490" , 0x11800a0003f50ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT491" , 0x11800a0003f58ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT492" , 0x11800a0003f60ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT493" , 0x11800a0003f68ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT494" , 0x11800a0003f70ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT495" , 0x11800a0003f78ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT496" , 0x11800a0003f80ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT497" , 0x11800a0003f88ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT498" , 0x11800a0003f90ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT499" , 0x11800a0003f98ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT500" , 0x11800a0003fa0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT501" , 0x11800a0003fa8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT502" , 0x11800a0003fb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT503" , 0x11800a0003fb8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT504" , 0x11800a0003fc0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT505" , 0x11800a0003fc8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT506" , 0x11800a0003fd0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT507" , 0x11800a0003fd8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT508" , 0x11800a0003fe0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT509" , 0x11800a0003fe8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT510" , 0x11800a0003ff0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_BSEL_TBL_ENT511" , 0x11800a0003ff8ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
- {"PIP_CLKEN" , 0x11800a0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 898},
- {"PIP_DEC_IPSEC0" , 0x11800a0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 899},
- {"PIP_DEC_IPSEC1" , 0x11800a0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 899},
- {"PIP_DEC_IPSEC2" , 0x11800a0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 899},
- {"PIP_DEC_IPSEC3" , 0x11800a0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 899},
- {"PIP_DSA_SRC_GRP" , 0x11800a0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 900},
- {"PIP_DSA_VID_GRP" , 0x11800a0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 901},
- {"PIP_FRM_LEN_CHK0" , 0x11800a0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 902},
- {"PIP_GBL_CFG" , 0x11800a0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 903},
- {"PIP_GBL_CTL" , 0x11800a0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 904},
- {"PIP_HG_PRI_QOS" , 0x11800a00001a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 905},
- {"PIP_INT_EN" , 0x11800a0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 906},
- {"PIP_INT_REG" , 0x11800a0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 907},
- {"PIP_IP_OFFSET" , 0x11800a0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 908},
- {"PIP_PRT_CFG0" , 0x11800a0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 909},
- {"PIP_PRT_CFG1" , 0x11800a0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 909},
- {"PIP_PRT_CFG32" , 0x11800a0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 909},
- {"PIP_PRT_CFG33" , 0x11800a0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 909},
- {"PIP_PRT_CFG34" , 0x11800a0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 909},
- {"PIP_PRT_CFG35" , 0x11800a0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 909},
- {"PIP_PRT_CFG36" , 0x11800a0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 909},
- {"PIP_PRT_CFG37" , 0x11800a0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 909},
- {"PIP_PRT_CFG38" , 0x11800a0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 909},
- {"PIP_PRT_CFG39" , 0x11800a0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 909},
- {"PIP_PRT_CFGB0" , 0x11800a0008000ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB1" , 0x11800a0008008ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB2" , 0x11800a0008010ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB3" , 0x11800a0008018ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB16" , 0x11800a0008080ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB17" , 0x11800a0008088ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB18" , 0x11800a0008090ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB19" , 0x11800a0008098ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB32" , 0x11800a0008100ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB33" , 0x11800a0008108ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB34" , 0x11800a0008110ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB35" , 0x11800a0008118ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB36" , 0x11800a0008120ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB37" , 0x11800a0008128ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB38" , 0x11800a0008130ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_CFGB39" , 0x11800a0008138ull, CVMX_CSR_DB_TYPE_RSL, 64, 910},
- {"PIP_PRT_TAG0" , 0x11800a0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 911},
- {"PIP_PRT_TAG1" , 0x11800a0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 911},
- {"PIP_PRT_TAG32" , 0x11800a0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 911},
- {"PIP_PRT_TAG33" , 0x11800a0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 911},
- {"PIP_PRT_TAG34" , 0x11800a0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 911},
- {"PIP_PRT_TAG35" , 0x11800a0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 911},
- {"PIP_PRT_TAG36" , 0x11800a0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 911},
- {"PIP_PRT_TAG37" , 0x11800a0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 911},
- {"PIP_PRT_TAG38" , 0x11800a0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 911},
- {"PIP_PRT_TAG39" , 0x11800a0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 911},
- {"PIP_QOS_DIFF0" , 0x11800a0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF1" , 0x11800a0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF2" , 0x11800a0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF3" , 0x11800a0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF4" , 0x11800a0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF5" , 0x11800a0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF6" , 0x11800a0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF7" , 0x11800a0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF8" , 0x11800a0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF9" , 0x11800a0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF10" , 0x11800a0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF11" , 0x11800a0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF12" , 0x11800a0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF13" , 0x11800a0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF14" , 0x11800a0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF15" , 0x11800a0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF16" , 0x11800a0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF17" , 0x11800a0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF18" , 0x11800a0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF19" , 0x11800a0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF20" , 0x11800a00006a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF21" , 0x11800a00006a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF22" , 0x11800a00006b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF23" , 0x11800a00006b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF24" , 0x11800a00006c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF25" , 0x11800a00006c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF26" , 0x11800a00006d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF27" , 0x11800a00006d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF28" , 0x11800a00006e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF29" , 0x11800a00006e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF30" , 0x11800a00006f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF31" , 0x11800a00006f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF32" , 0x11800a0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF33" , 0x11800a0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF34" , 0x11800a0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF35" , 0x11800a0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF36" , 0x11800a0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF37" , 0x11800a0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF38" , 0x11800a0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF39" , 0x11800a0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF40" , 0x11800a0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF41" , 0x11800a0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF42" , 0x11800a0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF43" , 0x11800a0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF44" , 0x11800a0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF45" , 0x11800a0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF46" , 0x11800a0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF47" , 0x11800a0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF48" , 0x11800a0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF49" , 0x11800a0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF50" , 0x11800a0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF51" , 0x11800a0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF52" , 0x11800a00007a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF53" , 0x11800a00007a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF54" , 0x11800a00007b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF55" , 0x11800a00007b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF56" , 0x11800a00007c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF57" , 0x11800a00007c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF58" , 0x11800a00007d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF59" , 0x11800a00007d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF60" , 0x11800a00007e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF61" , 0x11800a00007e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF62" , 0x11800a00007f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_DIFF63" , 0x11800a00007f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 912},
- {"PIP_QOS_VLAN0" , 0x11800a00000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 913},
- {"PIP_QOS_VLAN1" , 0x11800a00000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 913},
- {"PIP_QOS_VLAN2" , 0x11800a00000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 913},
- {"PIP_QOS_VLAN3" , 0x11800a00000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 913},
- {"PIP_QOS_VLAN4" , 0x11800a00000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 913},
- {"PIP_QOS_VLAN5" , 0x11800a00000e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 913},
- {"PIP_QOS_VLAN6" , 0x11800a00000f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 913},
- {"PIP_QOS_VLAN7" , 0x11800a00000f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 913},
- {"PIP_QOS_WATCH0" , 0x11800a0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 914},
- {"PIP_QOS_WATCH1" , 0x11800a0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 914},
- {"PIP_QOS_WATCH2" , 0x11800a0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 914},
- {"PIP_QOS_WATCH3" , 0x11800a0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 914},
- {"PIP_QOS_WATCH4" , 0x11800a0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 914},
- {"PIP_QOS_WATCH5" , 0x11800a0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 914},
- {"PIP_QOS_WATCH6" , 0x11800a0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 914},
- {"PIP_QOS_WATCH7" , 0x11800a0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 914},
- {"PIP_RAW_WORD" , 0x11800a00000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 915},
- {"PIP_SFT_RST" , 0x11800a0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 916},
- {"PIP_STAT0_PRT0" , 0x11800a0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 917},
- {"PIP_STAT0_PRT1" , 0x11800a0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 917},
- {"PIP_STAT0_PRT32" , 0x11800a0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 917},
- {"PIP_STAT0_PRT33" , 0x11800a0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 917},
- {"PIP_STAT0_PRT34" , 0x11800a00012a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 917},
- {"PIP_STAT0_PRT35" , 0x11800a00012f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 917},
- {"PIP_STAT0_PRT36" , 0x11800a0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 917},
- {"PIP_STAT0_PRT37" , 0x11800a0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 917},
- {"PIP_STAT0_PRT38" , 0x11800a00013e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 917},
- {"PIP_STAT0_PRT39" , 0x11800a0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 917},
- {"PIP_STAT10_PRT0" , 0x11800a0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 918},
- {"PIP_STAT10_PRT1" , 0x11800a0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 918},
- {"PIP_STAT10_PRT32" , 0x11800a0001680ull, CVMX_CSR_DB_TYPE_RSL, 64, 918},
- {"PIP_STAT10_PRT33" , 0x11800a0001690ull, CVMX_CSR_DB_TYPE_RSL, 64, 918},
- {"PIP_STAT10_PRT34" , 0x11800a00016a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 918},
- {"PIP_STAT10_PRT35" , 0x11800a00016b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 918},
- {"PIP_STAT10_PRT36" , 0x11800a00016c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 918},
- {"PIP_STAT10_PRT37" , 0x11800a00016d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 918},
- {"PIP_STAT10_PRT38" , 0x11800a00016e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 918},
- {"PIP_STAT10_PRT39" , 0x11800a00016f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 918},
- {"PIP_STAT11_PRT0" , 0x11800a0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 919},
- {"PIP_STAT11_PRT1" , 0x11800a0001498ull, CVMX_CSR_DB_TYPE_RSL, 64, 919},
- {"PIP_STAT11_PRT32" , 0x11800a0001688ull, CVMX_CSR_DB_TYPE_RSL, 64, 919},
- {"PIP_STAT11_PRT33" , 0x11800a0001698ull, CVMX_CSR_DB_TYPE_RSL, 64, 919},
- {"PIP_STAT11_PRT34" , 0x11800a00016a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 919},
- {"PIP_STAT11_PRT35" , 0x11800a00016b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 919},
- {"PIP_STAT11_PRT36" , 0x11800a00016c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 919},
- {"PIP_STAT11_PRT37" , 0x11800a00016d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 919},
- {"PIP_STAT11_PRT38" , 0x11800a00016e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 919},
- {"PIP_STAT11_PRT39" , 0x11800a00016f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 919},
- {"PIP_STAT1_PRT0" , 0x11800a0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 920},
- {"PIP_STAT1_PRT1" , 0x11800a0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 920},
- {"PIP_STAT1_PRT32" , 0x11800a0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 920},
- {"PIP_STAT1_PRT33" , 0x11800a0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 920},
- {"PIP_STAT1_PRT34" , 0x11800a00012a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 920},
- {"PIP_STAT1_PRT35" , 0x11800a00012f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 920},
- {"PIP_STAT1_PRT36" , 0x11800a0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 920},
- {"PIP_STAT1_PRT37" , 0x11800a0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 920},
- {"PIP_STAT1_PRT38" , 0x11800a00013e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 920},
- {"PIP_STAT1_PRT39" , 0x11800a0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 920},
- {"PIP_STAT2_PRT0" , 0x11800a0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"PIP_STAT2_PRT1" , 0x11800a0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"PIP_STAT2_PRT32" , 0x11800a0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"PIP_STAT2_PRT33" , 0x11800a0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"PIP_STAT2_PRT34" , 0x11800a00012b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"PIP_STAT2_PRT35" , 0x11800a0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"PIP_STAT2_PRT36" , 0x11800a0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"PIP_STAT2_PRT37" , 0x11800a00013a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"PIP_STAT2_PRT38" , 0x11800a00013f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"PIP_STAT2_PRT39" , 0x11800a0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 921},
- {"PIP_STAT3_PRT0" , 0x11800a0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"PIP_STAT3_PRT1" , 0x11800a0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"PIP_STAT3_PRT32" , 0x11800a0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"PIP_STAT3_PRT33" , 0x11800a0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"PIP_STAT3_PRT34" , 0x11800a00012b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"PIP_STAT3_PRT35" , 0x11800a0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"PIP_STAT3_PRT36" , 0x11800a0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"PIP_STAT3_PRT37" , 0x11800a00013a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"PIP_STAT3_PRT38" , 0x11800a00013f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"PIP_STAT3_PRT39" , 0x11800a0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 922},
- {"PIP_STAT4_PRT0" , 0x11800a0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"PIP_STAT4_PRT1" , 0x11800a0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"PIP_STAT4_PRT32" , 0x11800a0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"PIP_STAT4_PRT33" , 0x11800a0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"PIP_STAT4_PRT34" , 0x11800a00012c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"PIP_STAT4_PRT35" , 0x11800a0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"PIP_STAT4_PRT36" , 0x11800a0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"PIP_STAT4_PRT37" , 0x11800a00013b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"PIP_STAT4_PRT38" , 0x11800a0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"PIP_STAT4_PRT39" , 0x11800a0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 923},
- {"PIP_STAT5_PRT0" , 0x11800a0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"PIP_STAT5_PRT1" , 0x11800a0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"PIP_STAT5_PRT32" , 0x11800a0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"PIP_STAT5_PRT33" , 0x11800a0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"PIP_STAT5_PRT34" , 0x11800a00012c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"PIP_STAT5_PRT35" , 0x11800a0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"PIP_STAT5_PRT36" , 0x11800a0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"PIP_STAT5_PRT37" , 0x11800a00013b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"PIP_STAT5_PRT38" , 0x11800a0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"PIP_STAT5_PRT39" , 0x11800a0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 924},
- {"PIP_STAT6_PRT0" , 0x11800a0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"PIP_STAT6_PRT1" , 0x11800a0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"PIP_STAT6_PRT32" , 0x11800a0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"PIP_STAT6_PRT33" , 0x11800a0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"PIP_STAT6_PRT34" , 0x11800a00012d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"PIP_STAT6_PRT35" , 0x11800a0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"PIP_STAT6_PRT36" , 0x11800a0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"PIP_STAT6_PRT37" , 0x11800a00013c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"PIP_STAT6_PRT38" , 0x11800a0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"PIP_STAT6_PRT39" , 0x11800a0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 925},
- {"PIP_STAT7_PRT0" , 0x11800a0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"PIP_STAT7_PRT1" , 0x11800a0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"PIP_STAT7_PRT32" , 0x11800a0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"PIP_STAT7_PRT33" , 0x11800a0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"PIP_STAT7_PRT34" , 0x11800a00012d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"PIP_STAT7_PRT35" , 0x11800a0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"PIP_STAT7_PRT36" , 0x11800a0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"PIP_STAT7_PRT37" , 0x11800a00013c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"PIP_STAT7_PRT38" , 0x11800a0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"PIP_STAT7_PRT39" , 0x11800a0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 926},
- {"PIP_STAT8_PRT0" , 0x11800a0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"PIP_STAT8_PRT1" , 0x11800a0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"PIP_STAT8_PRT32" , 0x11800a0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"PIP_STAT8_PRT33" , 0x11800a0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"PIP_STAT8_PRT34" , 0x11800a00012e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"PIP_STAT8_PRT35" , 0x11800a0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"PIP_STAT8_PRT36" , 0x11800a0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"PIP_STAT8_PRT37" , 0x11800a00013d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"PIP_STAT8_PRT38" , 0x11800a0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"PIP_STAT8_PRT39" , 0x11800a0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 927},
- {"PIP_STAT9_PRT0" , 0x11800a0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"PIP_STAT9_PRT1" , 0x11800a0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"PIP_STAT9_PRT32" , 0x11800a0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"PIP_STAT9_PRT33" , 0x11800a0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"PIP_STAT9_PRT34" , 0x11800a00012e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"PIP_STAT9_PRT35" , 0x11800a0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"PIP_STAT9_PRT36" , 0x11800a0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"PIP_STAT9_PRT37" , 0x11800a00013d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"PIP_STAT9_PRT38" , 0x11800a0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"PIP_STAT9_PRT39" , 0x11800a0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 928},
- {"PIP_STAT_CTL" , 0x11800a0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 929},
- {"PIP_STAT_INB_ERRS0" , 0x11800a0001a10ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"PIP_STAT_INB_ERRS1" , 0x11800a0001a30ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"PIP_STAT_INB_ERRS32" , 0x11800a0001e10ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"PIP_STAT_INB_ERRS33" , 0x11800a0001e30ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"PIP_STAT_INB_ERRS34" , 0x11800a0001e50ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"PIP_STAT_INB_ERRS35" , 0x11800a0001e70ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"PIP_STAT_INB_ERRS36" , 0x11800a0001e90ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"PIP_STAT_INB_ERRS37" , 0x11800a0001eb0ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"PIP_STAT_INB_ERRS38" , 0x11800a0001ed0ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"PIP_STAT_INB_ERRS39" , 0x11800a0001ef0ull, CVMX_CSR_DB_TYPE_RSL, 64, 930},
- {"PIP_STAT_INB_OCTS0" , 0x11800a0001a08ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"PIP_STAT_INB_OCTS1" , 0x11800a0001a28ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"PIP_STAT_INB_OCTS32" , 0x11800a0001e08ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"PIP_STAT_INB_OCTS33" , 0x11800a0001e28ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"PIP_STAT_INB_OCTS34" , 0x11800a0001e48ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"PIP_STAT_INB_OCTS35" , 0x11800a0001e68ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"PIP_STAT_INB_OCTS36" , 0x11800a0001e88ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"PIP_STAT_INB_OCTS37" , 0x11800a0001ea8ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"PIP_STAT_INB_OCTS38" , 0x11800a0001ec8ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"PIP_STAT_INB_OCTS39" , 0x11800a0001ee8ull, CVMX_CSR_DB_TYPE_RSL, 64, 931},
- {"PIP_STAT_INB_PKTS0" , 0x11800a0001a00ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"PIP_STAT_INB_PKTS1" , 0x11800a0001a20ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"PIP_STAT_INB_PKTS32" , 0x11800a0001e00ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"PIP_STAT_INB_PKTS33" , 0x11800a0001e20ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"PIP_STAT_INB_PKTS34" , 0x11800a0001e40ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"PIP_STAT_INB_PKTS35" , 0x11800a0001e60ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"PIP_STAT_INB_PKTS36" , 0x11800a0001e80ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"PIP_STAT_INB_PKTS37" , 0x11800a0001ea0ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"PIP_STAT_INB_PKTS38" , 0x11800a0001ec0ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"PIP_STAT_INB_PKTS39" , 0x11800a0001ee0ull, CVMX_CSR_DB_TYPE_RSL, 64, 932},
- {"PIP_TAG_INC0" , 0x11800a0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC1" , 0x11800a0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC2" , 0x11800a0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC3" , 0x11800a0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC4" , 0x11800a0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC5" , 0x11800a0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC6" , 0x11800a0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC7" , 0x11800a0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC8" , 0x11800a0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC9" , 0x11800a0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC10" , 0x11800a0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC11" , 0x11800a0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC12" , 0x11800a0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC13" , 0x11800a0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC14" , 0x11800a0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC15" , 0x11800a0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC16" , 0x11800a0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC17" , 0x11800a0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC18" , 0x11800a0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC19" , 0x11800a0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC20" , 0x11800a00018a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC21" , 0x11800a00018a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC22" , 0x11800a00018b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC23" , 0x11800a00018b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC24" , 0x11800a00018c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC25" , 0x11800a00018c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC26" , 0x11800a00018d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC27" , 0x11800a00018d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC28" , 0x11800a00018e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC29" , 0x11800a00018e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC30" , 0x11800a00018f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC31" , 0x11800a00018f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC32" , 0x11800a0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC33" , 0x11800a0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC34" , 0x11800a0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC35" , 0x11800a0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC36" , 0x11800a0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC37" , 0x11800a0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC38" , 0x11800a0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC39" , 0x11800a0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC40" , 0x11800a0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC41" , 0x11800a0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC42" , 0x11800a0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC43" , 0x11800a0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC44" , 0x11800a0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC45" , 0x11800a0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC46" , 0x11800a0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC47" , 0x11800a0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC48" , 0x11800a0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC49" , 0x11800a0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC50" , 0x11800a0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC51" , 0x11800a0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC52" , 0x11800a00019a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC53" , 0x11800a00019a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC54" , 0x11800a00019b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC55" , 0x11800a00019b8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC56" , 0x11800a00019c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC57" , 0x11800a00019c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC58" , 0x11800a00019d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC59" , 0x11800a00019d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC60" , 0x11800a00019e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC61" , 0x11800a00019e8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC62" , 0x11800a00019f0ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_INC63" , 0x11800a00019f8ull, CVMX_CSR_DB_TYPE_RSL, 64, 933},
- {"PIP_TAG_MASK" , 0x11800a0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 934},
- {"PIP_TAG_SECRET" , 0x11800a0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 935},
- {"PIP_TODO_ENTRY" , 0x11800a0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 936},
- {"PIP_VLAN_ETYPES0" , 0x11800a00001c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 937},
- {"PIP_VLAN_ETYPES1" , 0x11800a00001c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 937},
- {"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 938},
- {"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
- {"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 940},
- {"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 941},
- {"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 942},
- {"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 943},
- {"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 944},
- {"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 945},
- {"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 946},
- {"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 947},
- {"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 948},
- {"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 949},
- {"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 950},
- {"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 951},
- {"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
- {"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
- {"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 954},
- {"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 955},
- {"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 956},
- {"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 957},
- {"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
- {"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
- {"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
- {"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
- {"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
- {"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
- {"PKO_REG_DEBUG1" , 0x11800500000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
- {"PKO_REG_DEBUG2" , 0x11800500000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
- {"PKO_REG_DEBUG3" , 0x11800500000b0ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
- {"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
- {"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 968},
- {"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 969},
- {"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 970},
- {"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 971},
- {"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
- {"PKO_REG_PREEMPT" , 0x1180050000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
- {"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
- {"PKO_REG_QUEUE_PREEMPT" , 0x1180050000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 975},
- {"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 976},
- {"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 977},
- {"PKO_REG_TIMESTAMP" , 0x1180050000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 978},
- {"POW_BIST_STAT" , 0x16700000003f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 979},
- {"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 980},
- {"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 981},
- {"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 982},
- {"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 983},
- {"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 983},
- {"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 983},
- {"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 983},
- {"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 983},
- {"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 983},
- {"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 983},
- {"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 983},
- {"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 984},
- {"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 985},
- {"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 986},
- {"POW_IQ_THR0" , 0x16700000003a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 987},
- {"POW_IQ_THR1" , 0x16700000003a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 987},
- {"POW_IQ_THR2" , 0x16700000003b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 987},
- {"POW_IQ_THR3" , 0x16700000003b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 987},
- {"POW_IQ_THR4" , 0x16700000003c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 987},
- {"POW_IQ_THR5" , 0x16700000003c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 987},
- {"POW_IQ_THR6" , 0x16700000003d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 987},
- {"POW_IQ_THR7" , 0x16700000003d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 987},
- {"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 988},
- {"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 989},
- {"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 990},
- {"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 991},
- {"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 991},
- {"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 991},
- {"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 991},
- {"POW_QOS_RND0" , 0x16700000001c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 992},
- {"POW_QOS_RND1" , 0x16700000001c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 992},
- {"POW_QOS_RND2" , 0x16700000001d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 992},
- {"POW_QOS_RND3" , 0x16700000001d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 992},
- {"POW_QOS_RND4" , 0x16700000001e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 992},
- {"POW_QOS_RND5" , 0x16700000001e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 992},
- {"POW_QOS_RND6" , 0x16700000001f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 992},
- {"POW_QOS_RND7" , 0x16700000001f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 992},
- {"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 993},
- {"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 993},
- {"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 993},
- {"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 993},
- {"POW_QOS_THR4" , 0x16700000001a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 993},
- {"POW_QOS_THR5" , 0x16700000001a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 993},
- {"POW_QOS_THR6" , 0x16700000001b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 993},
- {"POW_QOS_THR7" , 0x16700000001b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 993},
- {"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 994},
- {"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 995},
- {"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 996},
- {"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 996},
- {"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 996},
- {"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 996},
- {"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 996},
- {"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 996},
- {"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 996},
- {"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 996},
- {"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 997},
- {"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 998},
- {"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 999},
- {"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR4" , 0x16700000000a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR5" , 0x16700000000a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR6" , 0x16700000000b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR7" , 0x16700000000b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR8" , 0x16700000000c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR9" , 0x16700000000c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR10" , 0x16700000000d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR11" , 0x16700000000d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR12" , 0x16700000000e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR13" , 0x16700000000e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR14" , 0x16700000000f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WQ_INT_THR15" , 0x16700000000f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1000},
- {"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC4" , 0x16700000002a0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC5" , 0x16700000002a8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC6" , 0x16700000002b0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC7" , 0x16700000002b8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC8" , 0x16700000002c0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC9" , 0x16700000002c8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC10" , 0x16700000002d0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC11" , 0x16700000002d8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC12" , 0x16700000002e0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC13" , 0x16700000002e8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC14" , 0x16700000002f0ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"POW_WS_PC15" , 0x16700000002f8ull, CVMX_CSR_DB_TYPE_NCB, 64, 1001},
- {"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1002},
- {"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1003},
- {"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1004},
- {"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1005},
- {"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1006},
- {"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1007},
- {"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1008},
- {"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1009},
- {"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 1010},
- {"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 1011},
- {"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 1012},
- {"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1013},
- {"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 1014},
- {"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 1015},
- {"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 1016},
- {"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 1017},
- {"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 1018},
- {"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 1019},
- {"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 1020},
- {"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1021},
- {"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1022},
- {"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1023},
- {"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1024},
- {"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1025},
- {"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1026},
- {"RNM_EER_DBG" , 0x1180040000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1027},
- {"RNM_EER_KEY" , 0x1180040000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1028},
- {"RNM_SERIAL_NUM" , 0x1180040000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1029},
- {"SLI_BIST_STATUS" , 0x11f0000010580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1030},
- {"SLI_CTL_PORT0" , 0x11f0000010050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1031},
- {"SLI_CTL_PORT1" , 0x11f0000010060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1031},
- {"SLI_CTL_STATUS" , 0x11f0000010570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1032},
- {"SLI_DATA_OUT_CNT" , 0x11f00000105f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1033},
- {"SLI_DBG_DATA" , 0x11f0000010310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1034},
- {"SLI_DBG_SELECT" , 0x11f0000010300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1035},
- {"SLI_DMA0_CNT" , 0x11f0000010400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1036},
- {"SLI_DMA1_CNT" , 0x11f0000010410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1036},
- {"SLI_DMA0_INT_LEVEL" , 0x11f00000103e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1037},
- {"SLI_DMA1_INT_LEVEL" , 0x11f00000103f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1037},
- {"SLI_DMA0_TIM" , 0x11f0000010420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1038},
- {"SLI_DMA1_TIM" , 0x11f0000010430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1038},
- {"SLI_INT_ENB_CIU" , 0x11f0000013cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1039},
- {"SLI_INT_ENB_PORT0" , 0x11f0000010340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1040},
- {"SLI_INT_ENB_PORT1" , 0x11f0000010350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1040},
- {"SLI_INT_SUM" , 0x11f0000010330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1041},
- {"SLI_LAST_WIN_RDATA0" , 0x11f0000010600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1042},
- {"SLI_LAST_WIN_RDATA1" , 0x11f0000010610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1043},
- {"SLI_LAST_WIN_RDATA2" , 0x11f00000106c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1044},
- {"SLI_LAST_WIN_RDATA3" , 0x11f00000106d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1045},
- {"SLI_MAC_CREDIT_CNT" , 0x11f0000013d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1046},
- {"SLI_MAC_CREDIT_CNT2" , 0x11f0000013e10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1047},
- {"SLI_MAC_NUMBER" , 0x3e00ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1048},
- {"SLI_MEM_ACCESS_CTL" , 0x11f00000102f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1049},
- {"SLI_MEM_ACCESS_SUBID12" , 0x11f00000100e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID13" , 0x11f00000100f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID14" , 0x11f0000010100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID15" , 0x11f0000010110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID16" , 0x11f0000010120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID17" , 0x11f0000010130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID18" , 0x11f0000010140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID19" , 0x11f0000010150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID20" , 0x11f0000010160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID21" , 0x11f0000010170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID22" , 0x11f0000010180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID23" , 0x11f0000010190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID24" , 0x11f00000101a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID25" , 0x11f00000101b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID26" , 0x11f00000101c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MEM_ACCESS_SUBID27" , 0x11f00000101d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050},
- {"SLI_MSI_ENB0" , 0x11f0000013c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1051},
- {"SLI_MSI_ENB1" , 0x11f0000013c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1052},
- {"SLI_MSI_ENB2" , 0x11f0000013c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1053},
- {"SLI_MSI_ENB3" , 0x11f0000013c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1054},
- {"SLI_MSI_RCV0" , 0x11f0000013c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1055},
- {"SLI_MSI_RCV1" , 0x11f0000013c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1056},
- {"SLI_MSI_RCV2" , 0x11f0000013c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1057},
- {"SLI_MSI_RCV3" , 0x11f0000013c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1058},
- {"SLI_MSI_RD_MAP" , 0x11f0000013ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1059},
- {"SLI_MSI_W1C_ENB0" , 0x11f0000013cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1060},
- {"SLI_MSI_W1C_ENB1" , 0x11f0000013d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1061},
- {"SLI_MSI_W1C_ENB2" , 0x11f0000013d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1062},
- {"SLI_MSI_W1C_ENB3" , 0x11f0000013d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1063},
- {"SLI_MSI_W1S_ENB0" , 0x11f0000013d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1064},
- {"SLI_MSI_W1S_ENB1" , 0x11f0000013d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1065},
- {"SLI_MSI_W1S_ENB2" , 0x11f0000013d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1066},
- {"SLI_MSI_W1S_ENB3" , 0x11f0000013d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1067},
- {"SLI_MSI_WR_MAP" , 0x11f0000013c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1068},
- {"SLI_PCIE_MSI_RCV" , 0x11f0000013cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1069},
- {"SLI_PCIE_MSI_RCV_B1" , 0x11f0000010650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1070},
- {"SLI_PCIE_MSI_RCV_B2" , 0x11f0000010660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1071},
- {"SLI_PCIE_MSI_RCV_B3" , 0x11f0000010670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1072},
- {"SLI_PKT0_CNTS" , 0x11f0000012400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT1_CNTS" , 0x11f0000012410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT2_CNTS" , 0x11f0000012420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT3_CNTS" , 0x11f0000012430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT4_CNTS" , 0x11f0000012440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT5_CNTS" , 0x11f0000012450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT6_CNTS" , 0x11f0000012460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT7_CNTS" , 0x11f0000012470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT8_CNTS" , 0x11f0000012480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT9_CNTS" , 0x11f0000012490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT10_CNTS" , 0x11f00000124a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT11_CNTS" , 0x11f00000124b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT12_CNTS" , 0x11f00000124c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT13_CNTS" , 0x11f00000124d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT14_CNTS" , 0x11f00000124e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT15_CNTS" , 0x11f00000124f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT16_CNTS" , 0x11f0000012500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT17_CNTS" , 0x11f0000012510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT18_CNTS" , 0x11f0000012520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT19_CNTS" , 0x11f0000012530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT20_CNTS" , 0x11f0000012540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT21_CNTS" , 0x11f0000012550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT22_CNTS" , 0x11f0000012560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT23_CNTS" , 0x11f0000012570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT24_CNTS" , 0x11f0000012580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT25_CNTS" , 0x11f0000012590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT26_CNTS" , 0x11f00000125a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT27_CNTS" , 0x11f00000125b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT28_CNTS" , 0x11f00000125c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT29_CNTS" , 0x11f00000125d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT30_CNTS" , 0x11f00000125e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT31_CNTS" , 0x11f00000125f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1073},
- {"SLI_PKT0_IN_BP" , 0x11f0000013800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT1_IN_BP" , 0x11f0000013810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT2_IN_BP" , 0x11f0000013820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT3_IN_BP" , 0x11f0000013830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT4_IN_BP" , 0x11f0000013840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT5_IN_BP" , 0x11f0000013850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT6_IN_BP" , 0x11f0000013860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT7_IN_BP" , 0x11f0000013870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT8_IN_BP" , 0x11f0000013880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT9_IN_BP" , 0x11f0000013890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT10_IN_BP" , 0x11f00000138a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT11_IN_BP" , 0x11f00000138b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT12_IN_BP" , 0x11f00000138c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT13_IN_BP" , 0x11f00000138d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT14_IN_BP" , 0x11f00000138e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT15_IN_BP" , 0x11f00000138f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT16_IN_BP" , 0x11f0000013900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT17_IN_BP" , 0x11f0000013910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT18_IN_BP" , 0x11f0000013920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT19_IN_BP" , 0x11f0000013930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT20_IN_BP" , 0x11f0000013940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT21_IN_BP" , 0x11f0000013950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT22_IN_BP" , 0x11f0000013960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT23_IN_BP" , 0x11f0000013970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT24_IN_BP" , 0x11f0000013980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT25_IN_BP" , 0x11f0000013990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT26_IN_BP" , 0x11f00000139a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT27_IN_BP" , 0x11f00000139b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT28_IN_BP" , 0x11f00000139c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT29_IN_BP" , 0x11f00000139d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT30_IN_BP" , 0x11f00000139e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT31_IN_BP" , 0x11f00000139f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1074},
- {"SLI_PKT0_INSTR_BADDR" , 0x11f0000012800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT1_INSTR_BADDR" , 0x11f0000012810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT2_INSTR_BADDR" , 0x11f0000012820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT3_INSTR_BADDR" , 0x11f0000012830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT4_INSTR_BADDR" , 0x11f0000012840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT5_INSTR_BADDR" , 0x11f0000012850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT6_INSTR_BADDR" , 0x11f0000012860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT7_INSTR_BADDR" , 0x11f0000012870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT8_INSTR_BADDR" , 0x11f0000012880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT9_INSTR_BADDR" , 0x11f0000012890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT10_INSTR_BADDR" , 0x11f00000128a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT11_INSTR_BADDR" , 0x11f00000128b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT12_INSTR_BADDR" , 0x11f00000128c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT13_INSTR_BADDR" , 0x11f00000128d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT14_INSTR_BADDR" , 0x11f00000128e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT15_INSTR_BADDR" , 0x11f00000128f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT16_INSTR_BADDR" , 0x11f0000012900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT17_INSTR_BADDR" , 0x11f0000012910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT18_INSTR_BADDR" , 0x11f0000012920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT19_INSTR_BADDR" , 0x11f0000012930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT20_INSTR_BADDR" , 0x11f0000012940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT21_INSTR_BADDR" , 0x11f0000012950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT22_INSTR_BADDR" , 0x11f0000012960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT23_INSTR_BADDR" , 0x11f0000012970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT24_INSTR_BADDR" , 0x11f0000012980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT25_INSTR_BADDR" , 0x11f0000012990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT26_INSTR_BADDR" , 0x11f00000129a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT27_INSTR_BADDR" , 0x11f00000129b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT28_INSTR_BADDR" , 0x11f00000129c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT29_INSTR_BADDR" , 0x11f00000129d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT30_INSTR_BADDR" , 0x11f00000129e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT31_INSTR_BADDR" , 0x11f00000129f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1075},
- {"SLI_PKT0_INSTR_BAOFF_DBELL" , 0x11f0000012c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT1_INSTR_BAOFF_DBELL" , 0x11f0000012c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT2_INSTR_BAOFF_DBELL" , 0x11f0000012c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT3_INSTR_BAOFF_DBELL" , 0x11f0000012c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT4_INSTR_BAOFF_DBELL" , 0x11f0000012c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT5_INSTR_BAOFF_DBELL" , 0x11f0000012c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT6_INSTR_BAOFF_DBELL" , 0x11f0000012c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT7_INSTR_BAOFF_DBELL" , 0x11f0000012c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT8_INSTR_BAOFF_DBELL" , 0x11f0000012c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT9_INSTR_BAOFF_DBELL" , 0x11f0000012c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT10_INSTR_BAOFF_DBELL" , 0x11f0000012ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT11_INSTR_BAOFF_DBELL" , 0x11f0000012cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT12_INSTR_BAOFF_DBELL" , 0x11f0000012cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT13_INSTR_BAOFF_DBELL" , 0x11f0000012cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT14_INSTR_BAOFF_DBELL" , 0x11f0000012ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT15_INSTR_BAOFF_DBELL" , 0x11f0000012cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT16_INSTR_BAOFF_DBELL" , 0x11f0000012d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT17_INSTR_BAOFF_DBELL" , 0x11f0000012d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT18_INSTR_BAOFF_DBELL" , 0x11f0000012d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT19_INSTR_BAOFF_DBELL" , 0x11f0000012d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT20_INSTR_BAOFF_DBELL" , 0x11f0000012d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT21_INSTR_BAOFF_DBELL" , 0x11f0000012d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT22_INSTR_BAOFF_DBELL" , 0x11f0000012d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT23_INSTR_BAOFF_DBELL" , 0x11f0000012d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT24_INSTR_BAOFF_DBELL" , 0x11f0000012d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT25_INSTR_BAOFF_DBELL" , 0x11f0000012d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT26_INSTR_BAOFF_DBELL" , 0x11f0000012da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT27_INSTR_BAOFF_DBELL" , 0x11f0000012db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT28_INSTR_BAOFF_DBELL" , 0x11f0000012dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT29_INSTR_BAOFF_DBELL" , 0x11f0000012dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT30_INSTR_BAOFF_DBELL" , 0x11f0000012de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT31_INSTR_BAOFF_DBELL" , 0x11f0000012df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1076},
- {"SLI_PKT0_INSTR_FIFO_RSIZE" , 0x11f0000013000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT1_INSTR_FIFO_RSIZE" , 0x11f0000013010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT2_INSTR_FIFO_RSIZE" , 0x11f0000013020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT3_INSTR_FIFO_RSIZE" , 0x11f0000013030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT4_INSTR_FIFO_RSIZE" , 0x11f0000013040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT5_INSTR_FIFO_RSIZE" , 0x11f0000013050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT6_INSTR_FIFO_RSIZE" , 0x11f0000013060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT7_INSTR_FIFO_RSIZE" , 0x11f0000013070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT8_INSTR_FIFO_RSIZE" , 0x11f0000013080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT9_INSTR_FIFO_RSIZE" , 0x11f0000013090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT10_INSTR_FIFO_RSIZE" , 0x11f00000130a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT11_INSTR_FIFO_RSIZE" , 0x11f00000130b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT12_INSTR_FIFO_RSIZE" , 0x11f00000130c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT13_INSTR_FIFO_RSIZE" , 0x11f00000130d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT14_INSTR_FIFO_RSIZE" , 0x11f00000130e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT15_INSTR_FIFO_RSIZE" , 0x11f00000130f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT16_INSTR_FIFO_RSIZE" , 0x11f0000013100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT17_INSTR_FIFO_RSIZE" , 0x11f0000013110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT18_INSTR_FIFO_RSIZE" , 0x11f0000013120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT19_INSTR_FIFO_RSIZE" , 0x11f0000013130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT20_INSTR_FIFO_RSIZE" , 0x11f0000013140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT21_INSTR_FIFO_RSIZE" , 0x11f0000013150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT22_INSTR_FIFO_RSIZE" , 0x11f0000013160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT23_INSTR_FIFO_RSIZE" , 0x11f0000013170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT24_INSTR_FIFO_RSIZE" , 0x11f0000013180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT25_INSTR_FIFO_RSIZE" , 0x11f0000013190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT26_INSTR_FIFO_RSIZE" , 0x11f00000131a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT27_INSTR_FIFO_RSIZE" , 0x11f00000131b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT28_INSTR_FIFO_RSIZE" , 0x11f00000131c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT29_INSTR_FIFO_RSIZE" , 0x11f00000131d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT30_INSTR_FIFO_RSIZE" , 0x11f00000131e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT31_INSTR_FIFO_RSIZE" , 0x11f00000131f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077},
- {"SLI_PKT0_INSTR_HEADER" , 0x11f0000013400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT1_INSTR_HEADER" , 0x11f0000013410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT2_INSTR_HEADER" , 0x11f0000013420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT3_INSTR_HEADER" , 0x11f0000013430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT4_INSTR_HEADER" , 0x11f0000013440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT5_INSTR_HEADER" , 0x11f0000013450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT6_INSTR_HEADER" , 0x11f0000013460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT7_INSTR_HEADER" , 0x11f0000013470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT8_INSTR_HEADER" , 0x11f0000013480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT9_INSTR_HEADER" , 0x11f0000013490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT10_INSTR_HEADER" , 0x11f00000134a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT11_INSTR_HEADER" , 0x11f00000134b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT12_INSTR_HEADER" , 0x11f00000134c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT13_INSTR_HEADER" , 0x11f00000134d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT14_INSTR_HEADER" , 0x11f00000134e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT15_INSTR_HEADER" , 0x11f00000134f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT16_INSTR_HEADER" , 0x11f0000013500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT17_INSTR_HEADER" , 0x11f0000013510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT18_INSTR_HEADER" , 0x11f0000013520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT19_INSTR_HEADER" , 0x11f0000013530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT20_INSTR_HEADER" , 0x11f0000013540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT21_INSTR_HEADER" , 0x11f0000013550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT22_INSTR_HEADER" , 0x11f0000013560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT23_INSTR_HEADER" , 0x11f0000013570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT24_INSTR_HEADER" , 0x11f0000013580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT25_INSTR_HEADER" , 0x11f0000013590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT26_INSTR_HEADER" , 0x11f00000135a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT27_INSTR_HEADER" , 0x11f00000135b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT28_INSTR_HEADER" , 0x11f00000135c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT29_INSTR_HEADER" , 0x11f00000135d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT30_INSTR_HEADER" , 0x11f00000135e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT31_INSTR_HEADER" , 0x11f00000135f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078},
- {"SLI_PKT0_OUT_SIZE" , 0x11f0000010c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT1_OUT_SIZE" , 0x11f0000010c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT2_OUT_SIZE" , 0x11f0000010c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT3_OUT_SIZE" , 0x11f0000010c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT4_OUT_SIZE" , 0x11f0000010c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT5_OUT_SIZE" , 0x11f0000010c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT6_OUT_SIZE" , 0x11f0000010c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT7_OUT_SIZE" , 0x11f0000010c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT8_OUT_SIZE" , 0x11f0000010c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT9_OUT_SIZE" , 0x11f0000010c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT10_OUT_SIZE" , 0x11f0000010ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT11_OUT_SIZE" , 0x11f0000010cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT12_OUT_SIZE" , 0x11f0000010cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT13_OUT_SIZE" , 0x11f0000010cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT14_OUT_SIZE" , 0x11f0000010ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT15_OUT_SIZE" , 0x11f0000010cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT16_OUT_SIZE" , 0x11f0000010d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT17_OUT_SIZE" , 0x11f0000010d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT18_OUT_SIZE" , 0x11f0000010d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT19_OUT_SIZE" , 0x11f0000010d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT20_OUT_SIZE" , 0x11f0000010d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT21_OUT_SIZE" , 0x11f0000010d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT22_OUT_SIZE" , 0x11f0000010d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT23_OUT_SIZE" , 0x11f0000010d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT24_OUT_SIZE" , 0x11f0000010d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT25_OUT_SIZE" , 0x11f0000010d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT26_OUT_SIZE" , 0x11f0000010da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT27_OUT_SIZE" , 0x11f0000010db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT28_OUT_SIZE" , 0x11f0000010dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT29_OUT_SIZE" , 0x11f0000010dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT30_OUT_SIZE" , 0x11f0000010de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT31_OUT_SIZE" , 0x11f0000010df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079},
- {"SLI_PKT0_SLIST_BADDR" , 0x11f0000011400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT1_SLIST_BADDR" , 0x11f0000011410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT2_SLIST_BADDR" , 0x11f0000011420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT3_SLIST_BADDR" , 0x11f0000011430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT4_SLIST_BADDR" , 0x11f0000011440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT5_SLIST_BADDR" , 0x11f0000011450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT6_SLIST_BADDR" , 0x11f0000011460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT7_SLIST_BADDR" , 0x11f0000011470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT8_SLIST_BADDR" , 0x11f0000011480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT9_SLIST_BADDR" , 0x11f0000011490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT10_SLIST_BADDR" , 0x11f00000114a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT11_SLIST_BADDR" , 0x11f00000114b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT12_SLIST_BADDR" , 0x11f00000114c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT13_SLIST_BADDR" , 0x11f00000114d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT14_SLIST_BADDR" , 0x11f00000114e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT15_SLIST_BADDR" , 0x11f00000114f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT16_SLIST_BADDR" , 0x11f0000011500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT17_SLIST_BADDR" , 0x11f0000011510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT18_SLIST_BADDR" , 0x11f0000011520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT19_SLIST_BADDR" , 0x11f0000011530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT20_SLIST_BADDR" , 0x11f0000011540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT21_SLIST_BADDR" , 0x11f0000011550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT22_SLIST_BADDR" , 0x11f0000011560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT23_SLIST_BADDR" , 0x11f0000011570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT24_SLIST_BADDR" , 0x11f0000011580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT25_SLIST_BADDR" , 0x11f0000011590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT26_SLIST_BADDR" , 0x11f00000115a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT27_SLIST_BADDR" , 0x11f00000115b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT28_SLIST_BADDR" , 0x11f00000115c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT29_SLIST_BADDR" , 0x11f00000115d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT30_SLIST_BADDR" , 0x11f00000115e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT31_SLIST_BADDR" , 0x11f00000115f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080},
- {"SLI_PKT0_SLIST_BAOFF_DBELL" , 0x11f0000011800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT1_SLIST_BAOFF_DBELL" , 0x11f0000011810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT2_SLIST_BAOFF_DBELL" , 0x11f0000011820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT3_SLIST_BAOFF_DBELL" , 0x11f0000011830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT4_SLIST_BAOFF_DBELL" , 0x11f0000011840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT5_SLIST_BAOFF_DBELL" , 0x11f0000011850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT6_SLIST_BAOFF_DBELL" , 0x11f0000011860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT7_SLIST_BAOFF_DBELL" , 0x11f0000011870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT8_SLIST_BAOFF_DBELL" , 0x11f0000011880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT9_SLIST_BAOFF_DBELL" , 0x11f0000011890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT10_SLIST_BAOFF_DBELL" , 0x11f00000118a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT11_SLIST_BAOFF_DBELL" , 0x11f00000118b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT12_SLIST_BAOFF_DBELL" , 0x11f00000118c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT13_SLIST_BAOFF_DBELL" , 0x11f00000118d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT14_SLIST_BAOFF_DBELL" , 0x11f00000118e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT15_SLIST_BAOFF_DBELL" , 0x11f00000118f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT16_SLIST_BAOFF_DBELL" , 0x11f0000011900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT17_SLIST_BAOFF_DBELL" , 0x11f0000011910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT18_SLIST_BAOFF_DBELL" , 0x11f0000011920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT19_SLIST_BAOFF_DBELL" , 0x11f0000011930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT20_SLIST_BAOFF_DBELL" , 0x11f0000011940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT21_SLIST_BAOFF_DBELL" , 0x11f0000011950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT22_SLIST_BAOFF_DBELL" , 0x11f0000011960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT23_SLIST_BAOFF_DBELL" , 0x11f0000011970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT24_SLIST_BAOFF_DBELL" , 0x11f0000011980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT25_SLIST_BAOFF_DBELL" , 0x11f0000011990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT26_SLIST_BAOFF_DBELL" , 0x11f00000119a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT27_SLIST_BAOFF_DBELL" , 0x11f00000119b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT28_SLIST_BAOFF_DBELL" , 0x11f00000119c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT29_SLIST_BAOFF_DBELL" , 0x11f00000119d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT30_SLIST_BAOFF_DBELL" , 0x11f00000119e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT31_SLIST_BAOFF_DBELL" , 0x11f00000119f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081},
- {"SLI_PKT0_SLIST_FIFO_RSIZE" , 0x11f0000011c00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT1_SLIST_FIFO_RSIZE" , 0x11f0000011c10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT2_SLIST_FIFO_RSIZE" , 0x11f0000011c20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT3_SLIST_FIFO_RSIZE" , 0x11f0000011c30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT4_SLIST_FIFO_RSIZE" , 0x11f0000011c40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT5_SLIST_FIFO_RSIZE" , 0x11f0000011c50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT6_SLIST_FIFO_RSIZE" , 0x11f0000011c60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT7_SLIST_FIFO_RSIZE" , 0x11f0000011c70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT8_SLIST_FIFO_RSIZE" , 0x11f0000011c80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT9_SLIST_FIFO_RSIZE" , 0x11f0000011c90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT10_SLIST_FIFO_RSIZE" , 0x11f0000011ca0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT11_SLIST_FIFO_RSIZE" , 0x11f0000011cb0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT12_SLIST_FIFO_RSIZE" , 0x11f0000011cc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT13_SLIST_FIFO_RSIZE" , 0x11f0000011cd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT14_SLIST_FIFO_RSIZE" , 0x11f0000011ce0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT15_SLIST_FIFO_RSIZE" , 0x11f0000011cf0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT16_SLIST_FIFO_RSIZE" , 0x11f0000011d00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT17_SLIST_FIFO_RSIZE" , 0x11f0000011d10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT18_SLIST_FIFO_RSIZE" , 0x11f0000011d20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT19_SLIST_FIFO_RSIZE" , 0x11f0000011d30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT20_SLIST_FIFO_RSIZE" , 0x11f0000011d40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT21_SLIST_FIFO_RSIZE" , 0x11f0000011d50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT22_SLIST_FIFO_RSIZE" , 0x11f0000011d60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT23_SLIST_FIFO_RSIZE" , 0x11f0000011d70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT24_SLIST_FIFO_RSIZE" , 0x11f0000011d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT25_SLIST_FIFO_RSIZE" , 0x11f0000011d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT26_SLIST_FIFO_RSIZE" , 0x11f0000011da0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT27_SLIST_FIFO_RSIZE" , 0x11f0000011db0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT28_SLIST_FIFO_RSIZE" , 0x11f0000011dc0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT29_SLIST_FIFO_RSIZE" , 0x11f0000011dd0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT30_SLIST_FIFO_RSIZE" , 0x11f0000011de0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT31_SLIST_FIFO_RSIZE" , 0x11f0000011df0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082},
- {"SLI_PKT_CNT_INT" , 0x11f0000011130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1083},
- {"SLI_PKT_CNT_INT_ENB" , 0x11f0000011150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1084},
- {"SLI_PKT_CTL" , 0x11f0000011220ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1085},
- {"SLI_PKT_DATA_OUT_ES" , 0x11f00000110b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1086},
- {"SLI_PKT_DATA_OUT_NS" , 0x11f00000110a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1087},
- {"SLI_PKT_DATA_OUT_ROR" , 0x11f0000011090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1088},
- {"SLI_PKT_DPADDR" , 0x11f0000011080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1089},
- {"SLI_PKT_IN_BP" , 0x11f0000011210ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1090},
- {"SLI_PKT_IN_DONE0_CNTS" , 0x11f0000012000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE1_CNTS" , 0x11f0000012010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE2_CNTS" , 0x11f0000012020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE3_CNTS" , 0x11f0000012030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE4_CNTS" , 0x11f0000012040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE5_CNTS" , 0x11f0000012050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE6_CNTS" , 0x11f0000012060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE7_CNTS" , 0x11f0000012070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE8_CNTS" , 0x11f0000012080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE9_CNTS" , 0x11f0000012090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE10_CNTS" , 0x11f00000120a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE11_CNTS" , 0x11f00000120b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE12_CNTS" , 0x11f00000120c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE13_CNTS" , 0x11f00000120d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE14_CNTS" , 0x11f00000120e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE15_CNTS" , 0x11f00000120f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE16_CNTS" , 0x11f0000012100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE17_CNTS" , 0x11f0000012110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE18_CNTS" , 0x11f0000012120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE19_CNTS" , 0x11f0000012130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE20_CNTS" , 0x11f0000012140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE21_CNTS" , 0x11f0000012150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE22_CNTS" , 0x11f0000012160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE23_CNTS" , 0x11f0000012170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE24_CNTS" , 0x11f0000012180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE25_CNTS" , 0x11f0000012190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE26_CNTS" , 0x11f00000121a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE27_CNTS" , 0x11f00000121b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE28_CNTS" , 0x11f00000121c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE29_CNTS" , 0x11f00000121d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE30_CNTS" , 0x11f00000121e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_DONE31_CNTS" , 0x11f00000121f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091},
- {"SLI_PKT_IN_INSTR_COUNTS" , 0x11f0000011200ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1092},
- {"SLI_PKT_IN_PCIE_PORT" , 0x11f00000111b0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1093},
- {"SLI_PKT_INPUT_CONTROL" , 0x11f0000011170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1094},
- {"SLI_PKT_INSTR_ENB" , 0x11f0000011000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1095},
- {"SLI_PKT_INSTR_RD_SIZE" , 0x11f00000111a0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1096},
- {"SLI_PKT_INSTR_SIZE" , 0x11f0000011020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1097},
- {"SLI_PKT_INT_LEVELS" , 0x11f0000011120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1098},
- {"SLI_PKT_IPTR" , 0x11f0000011070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1099},
- {"SLI_PKT_OUT_BMODE" , 0x11f00000110d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1100},
- {"SLI_PKT_OUT_ENB" , 0x11f0000011010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1101},
- {"SLI_PKT_OUTPUT_WMARK" , 0x11f0000011180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1102},
- {"SLI_PKT_PCIE_PORT" , 0x11f00000110e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1103},
- {"SLI_PKT_PORT_IN_RST" , 0x11f00000111f0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1104},
- {"SLI_PKT_SLIST_ES" , 0x11f0000011050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1105},
- {"SLI_PKT_SLIST_NS" , 0x11f0000011040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1106},
- {"SLI_PKT_SLIST_ROR" , 0x11f0000011030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1107},
- {"SLI_PKT_TIME_INT" , 0x11f0000011140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1108},
- {"SLI_PKT_TIME_INT_ENB" , 0x11f0000011160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1109},
- {"SLI_S2M_PORT0_CTL" , 0x11f0000013d80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1110},
- {"SLI_S2M_PORT1_CTL" , 0x11f0000013d90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1110},
- {"SLI_SCRATCH_1" , 0x11f00000103c0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1111},
- {"SLI_SCRATCH_2" , 0x11f00000103d0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1112},
- {"SLI_STATE1" , 0x11f0000010620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1113},
- {"SLI_STATE2" , 0x11f0000010630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1114},
- {"SLI_STATE3" , 0x11f0000010640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1115},
- {"SLI_WIN_RD_ADDR" , 0x10ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1116},
- {"SLI_WIN_RD_DATA" , 0x40ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1117},
- {"SLI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1118},
- {"SLI_WIN_WR_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1119},
- {"SLI_WIN_WR_MASK" , 0x30ull, CVMX_CSR_DB_TYPE_PEXP, 64, 1120},
- {"SLI_WINDOW_CTL" , 0x11f00000102e0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1121},
- {"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 1122},
- {"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 1122},
- {"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 1123},
- {"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 1123},
- {"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 1124},
- {"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 1124},
- {"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 1125},
- {"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 1125},
- {"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 1126},
- {"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 1126},
- {"SMI_DRV_CTL" , 0x1180000001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 1127},
- {"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 1128},
- {"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 1129},
- {"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 1130},
- {"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1131},
- {"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1132},
- {"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1133},
- {"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1134},
- {"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1135},
- {"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1136},
- {"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1137},
- {"TRA0_BIST_STATUS" , 0x11800a8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1138},
- {"TRA0_CTL" , 0x11800a8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1139},
- {"TRA0_CYCLES_SINCE" , 0x11800a8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1140},
- {"TRA0_CYCLES_SINCE1" , 0x11800a8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1141},
- {"TRA0_FILT_ADR_ADR" , 0x11800a8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 1142},
- {"TRA0_FILT_ADR_MSK" , 0x11800a8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 1143},
- {"TRA0_FILT_CMD" , 0x11800a8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 1144},
- {"TRA0_FILT_DID" , 0x11800a8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 1145},
- {"TRA0_FILT_SID" , 0x11800a8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 1146},
- {"TRA0_INT_STATUS" , 0x11800a8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1147},
- {"TRA0_READ_DAT" , 0x11800a8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1148},
- {"TRA0_READ_DAT_HI" , 0x11800a8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1149},
- {"TRA0_TRIG0_ADR_ADR" , 0x11800a8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1150},
- {"TRA0_TRIG0_ADR_MSK" , 0x11800a80000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1151},
- {"TRA0_TRIG0_CMD" , 0x11800a8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1152},
- {"TRA0_TRIG0_DID" , 0x11800a8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1153},
- {"TRA0_TRIG0_SID" , 0x11800a8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1154},
- {"TRA0_TRIG1_ADR_ADR" , 0x11800a80000d8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1155},
- {"TRA0_TRIG1_ADR_MSK" , 0x11800a80000e0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1156},
- {"TRA0_TRIG1_CMD" , 0x11800a80000c0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1157},
- {"TRA0_TRIG1_DID" , 0x11800a80000d0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1158},
- {"TRA0_TRIG1_SID" , 0x11800a80000c8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1159},
- {"UAHC0_EHCI_ASYNCLISTADDR" , 0x16f0000000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 1160},
- {"UAHC0_EHCI_CONFIGFLAG" , 0x16f0000000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 1161},
- {"UAHC0_EHCI_CTRLDSSEGMENT" , 0x16f0000000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 1162},
- {"UAHC0_EHCI_FRINDEX" , 0x16f000000001cull, CVMX_CSR_DB_TYPE_NCB, 32, 1163},
- {"UAHC0_EHCI_HCCAPBASE" , 0x16f0000000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 1164},
- {"UAHC0_EHCI_HCCPARAMS" , 0x16f0000000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 1165},
- {"UAHC0_EHCI_HCSPARAMS" , 0x16f0000000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 1166},
- {"UAHC0_EHCI_INSNREG00" , 0x16f0000000090ull, CVMX_CSR_DB_TYPE_NCB, 32, 1167},
- {"UAHC0_EHCI_INSNREG03" , 0x16f000000009cull, CVMX_CSR_DB_TYPE_NCB, 32, 1168},
- {"UAHC0_EHCI_INSNREG04" , 0x16f00000000a0ull, CVMX_CSR_DB_TYPE_NCB, 32, 1169},
- {"UAHC0_EHCI_INSNREG06" , 0x16f00000000e8ull, CVMX_CSR_DB_TYPE_NCB, 32, 1170},
- {"UAHC0_EHCI_INSNREG07" , 0x16f00000000ecull, CVMX_CSR_DB_TYPE_NCB, 32, 1171},
- {"UAHC0_EHCI_PERIODICLISTBASE" , 0x16f0000000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 1172},
- {"UAHC0_EHCI_PORTSC001" , 0x16f0000000054ull, CVMX_CSR_DB_TYPE_NCB, 32, 1173},
- {"UAHC0_EHCI_PORTSC002" , 0x16f0000000058ull, CVMX_CSR_DB_TYPE_NCB, 32, 1173},
- {"UAHC0_EHCI_USBCMD" , 0x16f0000000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 1174},
- {"UAHC0_EHCI_USBINTR" , 0x16f0000000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 1175},
- {"UAHC0_EHCI_USBSTS" , 0x16f0000000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 1176},
- {"UAHC0_OHCI0_HCBULKCURRENTED" , 0x16f000000042cull, CVMX_CSR_DB_TYPE_NCB, 32, 1177},
- {"UAHC0_OHCI0_HCBULKHEADED" , 0x16f0000000428ull, CVMX_CSR_DB_TYPE_NCB, 32, 1178},
- {"UAHC0_OHCI0_HCCOMMANDSTATUS" , 0x16f0000000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 1179},
- {"UAHC0_OHCI0_HCCONTROL" , 0x16f0000000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 1180},
- {"UAHC0_OHCI0_HCCONTROLCURRENTED", 0x16f0000000424ull, CVMX_CSR_DB_TYPE_NCB, 32, 1181},
- {"UAHC0_OHCI0_HCCONTROLHEADED" , 0x16f0000000420ull, CVMX_CSR_DB_TYPE_NCB, 32, 1182},
- {"UAHC0_OHCI0_HCDONEHEAD" , 0x16f0000000430ull, CVMX_CSR_DB_TYPE_NCB, 32, 1183},
- {"UAHC0_OHCI0_HCFMINTERVAL" , 0x16f0000000434ull, CVMX_CSR_DB_TYPE_NCB, 32, 1184},
- {"UAHC0_OHCI0_HCFMNUMBER" , 0x16f000000043cull, CVMX_CSR_DB_TYPE_NCB, 32, 1185},
- {"UAHC0_OHCI0_HCFMREMAINING" , 0x16f0000000438ull, CVMX_CSR_DB_TYPE_NCB, 32, 1186},
- {"UAHC0_OHCI0_HCHCCA" , 0x16f0000000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 1187},
- {"UAHC0_OHCI0_HCINTERRUPTDISABLE", 0x16f0000000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 1188},
- {"UAHC0_OHCI0_HCINTERRUPTENABLE", 0x16f0000000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 1189},
- {"UAHC0_OHCI0_HCINTERRUPTSTATUS", 0x16f000000040cull, CVMX_CSR_DB_TYPE_NCB, 32, 1190},
- {"UAHC0_OHCI0_HCLSTHRESHOLD" , 0x16f0000000444ull, CVMX_CSR_DB_TYPE_NCB, 32, 1191},
- {"UAHC0_OHCI0_HCPERIODCURRENTED", 0x16f000000041cull, CVMX_CSR_DB_TYPE_NCB, 32, 1192},
- {"UAHC0_OHCI0_HCPERIODICSTART" , 0x16f0000000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 1193},
- {"UAHC0_OHCI0_HCREVISION" , 0x16f0000000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 1194},
- {"UAHC0_OHCI0_HCRHDESCRIPTORA" , 0x16f0000000448ull, CVMX_CSR_DB_TYPE_NCB, 32, 1195},
- {"UAHC0_OHCI0_HCRHDESCRIPTORB" , 0x16f000000044cull, CVMX_CSR_DB_TYPE_NCB, 32, 1196},
- {"UAHC0_OHCI0_HCRHPORTSTATUS001", 0x16f0000000454ull, CVMX_CSR_DB_TYPE_NCB, 32, 1197},
- {"UAHC0_OHCI0_HCRHPORTSTATUS002", 0x16f0000000458ull, CVMX_CSR_DB_TYPE_NCB, 32, 1197},
- {"UAHC0_OHCI0_HCRHSTATUS" , 0x16f0000000450ull, CVMX_CSR_DB_TYPE_NCB, 32, 1198},
- {"UAHC0_OHCI0_INSNREG06" , 0x16f0000000498ull, CVMX_CSR_DB_TYPE_NCB, 32, 1199},
- {"UAHC0_OHCI0_INSNREG07" , 0x16f000000049cull, CVMX_CSR_DB_TYPE_NCB, 32, 1200},
- {"UCTL0_BIST_STATUS" , 0x118006f0000a0ull, CVMX_CSR_DB_TYPE_RSL, 64, 1201},
- {"UCTL0_CLK_RST_CTL" , 0x118006f000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 1202},
- {"UCTL0_EHCI_CTL" , 0x118006f000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 1203},
- {"UCTL0_EHCI_FLA" , 0x118006f0000a8ull, CVMX_CSR_DB_TYPE_RSL, 64, 1204},
- {"UCTL0_ERTO_CTL" , 0x118006f000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 1205},
- {"UCTL0_IF_ENA" , 0x118006f000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 1206},
- {"UCTL0_INT_ENA" , 0x118006f000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 1207},
- {"UCTL0_INT_REG" , 0x118006f000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 1208},
- {"UCTL0_OHCI_CTL" , 0x118006f000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 1209},
- {"UCTL0_ORTO_CTL" , 0x118006f000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 1210},
- {"UCTL0_PPAF_WM" , 0x118006f000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 1211},
- {"UCTL0_UPHY_CTL_STATUS" , 0x118006f000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 1212},
- {"UCTL0_UPHY_PORT000_CTL_STATUS", 0x118006f000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1213},
- {"UCTL0_UPHY_PORT001_CTL_STATUS", 0x118006f000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 1213},
- {NULL,0,0,0,0}
-};
-static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cnf71xx[] = {
- /* name , bit, width, csr, type, rst un, typ un, reset, typical */
- {"BIST" , 0, 6, 0, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 0, "RAZ", 1, 1, 0, 0},
- {"MIO" , 0, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"GMX0" , 1, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 1, "RAZ", 1, 1, 0, 0},
- {"SLI" , 3, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 4, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 5, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 1, "RAZ", 1, 1, 0, 0},
- {"IPD" , 9, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 10, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"TIM" , 11, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 12, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"USB" , 13, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 14, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_15" , 15, 1, 1, "RAZ", 1, 1, 0, 0},
- {"L2C" , 16, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"LMC0" , 17, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 1, "RAZ", 1, 1, 0, 0},
- {"PIP" , 20, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 1, "RAZ", 1, 1, 0, 0},
- {"ASXPCS0" , 22, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_24" , 23, 2, 1, "RAZ", 1, 1, 0, 0},
- {"PEM0" , 25, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 26, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_29" , 27, 3, 1, "RAZ", 1, 1, 0, 0},
- {"IOB" , 30, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_40" , 31, 10, 1, "RAZ", 1, 1, 0, 0},
- {"DPI" , 41, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"PTP" , 42, 1, 1, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 1, "RAZ", 1, 1, 0, 0},
- {"DINT" , 0, 4, 2, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 2, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 3, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 3, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 3, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 3, "R/W", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 3, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 3, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 4, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 4, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 4, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 4, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 4, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 4, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 5, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 5, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 5, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 5, "R/W1", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 5, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 5, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 6, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 6, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 6, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 6, "R/W", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 6, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 6, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 7, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 7, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 7, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 7, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 7, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 7, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 8, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 8, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 8, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 8, "R/W1", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 8, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 8, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 9, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 9, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 9, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 9, "R/W", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 9, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 9, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 10, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 10, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 10, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 10, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 10, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 10, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 11, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 11, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 11, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 11, "R/W1", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 11, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 11, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 12, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 12, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 12, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 12, "R/W", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 12, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 12, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 13, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 13, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 13, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 13, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 13, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 13, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 14, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 14, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 14, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 14, "R/W1", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 14, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 14, "RAZ", 1, 1, 0, 0},
- {"FUSE" , 0, 4, 15, "RO", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 15, "RAZ", 1, 1, 0, 0},
- {"GSTOP" , 0, 1, 16, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 16, "RAZ", 1, 1, 0, 0},
- {"WORKQ" , 0, 16, 17, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 17, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 17, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 17, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 17, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 17, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 52, 4, 17, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 17, "RAZ", 1, 1, 0, 0},
- {"BOOTDMA" , 63, 1, 17, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 18, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 18, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 18, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 52, 4, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 18, "RAZ", 1, 1, 0, 0},
- {"BOOTDMA" , 63, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 19, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 19, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 19, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 52, 4, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 19, "RAZ", 1, 1, 0, 0},
- {"BOOTDMA" , 63, 1, 19, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 20, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 20, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 20, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 20, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 20, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_46" , 41, 6, 20, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 20, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 20, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 20, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 21, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 21, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 21, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 21, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_46" , 41, 6, 21, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 21, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 21, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 22, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 22, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 22, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 22, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_46" , 41, 6, 22, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 22, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 22, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 22, "R/W1", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 23, "R/W", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 23, "R/W", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 23, "R/W", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 23, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 23, "R/W", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 23, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 23, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 23, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 52, 4, 23, "R/W", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 23, "RAZ", 1, 1, 0, 0},
- {"BOOTDMA" , 63, 1, 23, "R/W", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 24, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 24, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 24, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 52, 4, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 24, "RAZ", 1, 1, 0, 0},
- {"BOOTDMA" , 63, 1, 24, "R/W1C", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_44_44" , 44, 1, 25, "RAZ", 1, 1, 0, 0},
- {"TWSI" , 45, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 25, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_51_51" , 51, 1, 25, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 52, 4, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 25, "RAZ", 1, 1, 0, 0},
- {"BOOTDMA" , 63, 1, 25, "R/W1", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 26, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 26, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 26, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 26, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_41_46" , 41, 6, 26, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 26, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 26, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 26, "R/W", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 27, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 27, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 27, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 27, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_41_46" , 41, 6, 27, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 27, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 27, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 27, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 28, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 28, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 28, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 28, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_41_46" , 41, 6, 28, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 28, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 28, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 28, "R/W1", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 29, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 29, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 29, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 29, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 29, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 29, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 29, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 29, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 29, "R/W1C", 0, 0, 0ull, 0ull},
- {"SUM2" , 51, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 29, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 29, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 29, "RAZ", 1, 1, 0, 0},
- {"BOOTDMA" , 63, 1, 29, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 30, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 30, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 30, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 30, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 30, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 30, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 30, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 30, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 30, "R/W1C", 0, 0, 0ull, 0ull},
- {"SUM2" , 51, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 30, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 30, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 30, "RO", 1, 1, 0, 0},
- {"BOOTDMA" , 63, 1, 30, "RO", 0, 0, 0ull, 0ull},
- {"WORKQ" , 0, 16, 31, "RO", 0, 0, 0ull, 0ull},
- {"GPIO" , 16, 16, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"MBOX" , 32, 2, 31, "RO", 0, 0, 0ull, 0ull},
- {"UART" , 34, 2, 31, "RO", 0, 0, 0ull, 0ull},
- {"PCI_INT" , 36, 4, 31, "RO", 0, 0, 0ull, 0ull},
- {"PCI_MSI" , 40, 4, 31, "RO", 0, 0, 0ull, 0ull},
- {"WDOG_SUM" , 44, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"TWSI" , 45, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"RML" , 46, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"TRACE" , 47, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"GMX_DRP" , 48, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_49_49" , 49, 1, 31, "RAZ", 1, 1, 0, 0},
- {"IPD_DRP" , 50, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"SUM2" , 51, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 52, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"USB" , 56, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"PCM" , 57, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"MPI" , 58, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
- {"TWSI2" , 59, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"POWIQ" , 60, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"IPDPPTHR" , 61, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_62" , 62, 1, 31, "RAZ", 1, 1, 0, 0},
- {"BOOTDMA" , 63, 1, 31, "RO", 0, 0, 0ull, 0ull},
- {"PP" , 0, 4, 32, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_7" , 4, 4, 32, "RAZ", 1, 1, 0, 0},
- {"IRQ" , 8, 2, 32, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 32, "RAZ", 1, 1, 0, 0},
- {"SEL" , 16, 3, 32, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_19_63" , 19, 45, 32, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 4, 33, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 33, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 33, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 33, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_46" , 37, 10, 33, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 33, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 33, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 33, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 33, "RO", 0, 0, 0ull, 0ull},
- {"BITS" , 0, 32, 34, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 34, "RAZ", 1, 1, 0, 0},
- {"BITS" , 0, 32, 35, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 35, "RAZ", 1, 1, 0, 0},
- {"NMI" , 0, 4, 36, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 36, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 2, 37, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 37, "RAZ", 1, 1, 0, 0},
- {"PPDBG" , 0, 4, 38, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 38, "RAZ", 1, 1, 0, 0},
- {"POKE" , 0, 64, 39, "RAZ", 1, 1, 0, 0},
- {"RST0" , 0, 1, 40, "R/W", 1, 1, 0, 0},
- {"RST" , 1, 3, 40, "R/W", 0, 0, 7ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 40, "RAZ", 1, 1, 0, 0},
- {"LANE_EN" , 0, 4, 41, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 41, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 41, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 41, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 41, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 41, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 41, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 41, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 41, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 41, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 41, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 41, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 41, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 42, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 42, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 42, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 42, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 42, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 42, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 42, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_39" , 32, 8, 42, "RAZ", 1, 1, 0, 0},
- {"G2MARGIN" , 40, 5, 42, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_47" , 45, 3, 42, "RAZ", 1, 1, 0, 0},
- {"G2DEEMPH" , 48, 5, 42, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_53_62" , 53, 10, 42, "RAZ", 1, 1, 0, 0},
- {"G2BYPASS" , 63, 1, 42, "R/W", 0, 1, 0ull, 0},
- {"LANE_EN" , 0, 4, 43, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_4_7" , 4, 4, 43, "RAZ", 1, 1, 0, 0},
- {"TXMARGIN" , 8, 5, 43, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 43, "RAZ", 1, 1, 0, 0},
- {"TXDEEMPH" , 16, 5, 43, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_30" , 21, 10, 43, "RAZ", 1, 1, 0, 0},
- {"TXBYPASS" , 31, 1, 43, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 43, "RAZ", 1, 1, 0, 0},
- {"BYPASS" , 0, 3, 44, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 44, "RAZ", 1, 1, 0, 0},
- {"MUX_SEL" , 4, 2, 44, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 44, "RAZ", 1, 1, 0, 0},
- {"CLK_DIV" , 8, 3, 44, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_63" , 11, 53, 44, "RAZ", 1, 1, 0, 0},
- {"SHFT_REG" , 0, 32, 45, "R/W", 0, 1, 0ull, 0},
- {"SHFT_CNT" , 32, 5, 45, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_37_39" , 37, 3, 45, "RAZ", 1, 1, 0, 0},
- {"SELECT" , 40, 3, 45, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_60" , 43, 18, 45, "RAZ", 1, 1, 0, 0},
- {"UPDATE" , 61, 1, 45, "R/W", 0, 1, 0ull, 0},
- {"SHIFT" , 62, 1, 45, "R/W", 0, 1, 0ull, 0},
- {"CAPTURE" , 63, 1, 45, "R/W", 0, 1, 0ull, 0},
- {"SOFT_BIST" , 0, 1, 46, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 46, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 47, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
- {"SOFT_PRST" , 0, 1, 48, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 48, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST" , 0, 1, 49, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 49, "RAZ", 1, 1, 0, 0},
- {"WDOG" , 0, 4, 50, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 50, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 50, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 50, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 50, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_46" , 41, 6, 50, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 50, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 50, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 50, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 51, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 51, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 51, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 51, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 51, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_46" , 41, 6, 51, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 51, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 51, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 51, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 51, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 52, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 52, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 52, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 52, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 52, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_46" , 41, 6, 52, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 52, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 52, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 52, "RO", 0, 0, 0ull, 0ull},
- {"WDOG" , 0, 4, 53, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_18" , 4, 15, 53, "RAZ", 1, 1, 0, 0},
- {"NAND" , 19, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"MIO" , 20, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"IOB" , 21, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"FPA" , 22, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"POW" , 23, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"L2C" , 24, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"IPD" , 25, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"PIP" , 26, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"PKO" , 27, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_28" , 28, 1, 53, "RAZ", 1, 1, 0, 0},
- {"TIM" , 29, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"RAD" , 30, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"KEY" , 31, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_32" , 32, 1, 53, "RAZ", 1, 1, 0, 0},
- {"USB" , 33, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"SLI" , 34, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"DPI" , 35, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"AGX0" , 36, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 53, "RAZ", 1, 1, 0, 0},
- {"DPI_DMA" , 40, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_41_46" , 41, 6, 53, "RAZ", 1, 1, 0, 0},
- {"PTP" , 47, 1, 53, "R/W1C", 0, 0, 0ull, 0ull},
- {"PEM0" , 48, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"PEM1" , 49, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_50_51" , 50, 2, 53, "RAZ", 1, 1, 0, 0},
- {"LMC0" , 52, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_53_62" , 53, 10, 53, "RAZ", 1, 1, 0, 0},
- {"RST" , 63, 1, 53, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 54, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 54, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 54, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 54, "RO", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 54, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 54, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 55, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 55, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 55, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 55, "RO", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 55, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 55, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 56, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 56, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 56, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 56, "RO", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 56, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 56, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 57, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 4, 6, 57, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 57, "RAZ", 1, 1, 0, 0},
- {"EOI" , 12, 1, 57, "RO", 0, 0, 0ull, 0ull},
- {"ENDOR" , 13, 2, 57, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_63" , 15, 49, 57, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 36, 58, "R/W", 0, 0, 0ull, 0ull},
- {"ONE_SHOT" , 36, 1, 58, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_63" , 37, 27, 58, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 60, "R/W", 0, 0, 0ull, 0ull},
- {"STATE" , 2, 2, 60, "RO", 0, 0, 0ull, 0ull},
- {"LEN" , 4, 16, 60, "R/W", 0, 0, 0ull, 0ull},
- {"CNT" , 20, 24, 60, "RO", 0, 0, 0ull, 0ull},
- {"DSTOP" , 44, 1, 60, "R/W", 0, 0, 0ull, 0ull},
- {"GSTOPEN" , 45, 1, 60, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 60, "RAZ", 1, 1, 0, 0},
- {"BIST" , 0, 47, 61, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 61, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 62, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 62, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 32, 63, "RO", 0, 0, 0ull, 0ull},
- {"FCNT" , 32, 7, 63, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_39_63" , 39, 25, 63, "RAZ", 1, 1, 0, 0},
- {"DBELL" , 0, 16, 64, "WO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 64, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 6, 65, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 65, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_6" , 0, 7, 66, "RAZ", 1, 1, 0, 0},
- {"SADDR" , 7, 29, 66, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 66, "RAZ", 1, 1, 0, 0},
- {"IDLE" , 40, 1, 66, "RO", 0, 1, 1ull, 0},
- {"RESERVED_41_47" , 41, 7, 66, "RAZ", 1, 1, 0, 0},
- {"CSIZE" , 48, 14, 66, "R/W", 0, 1, 64ull, 0},
- {"RESERVED_62_63" , 62, 2, 66, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 3, 67, "R/W", 0, 0, 6ull, 6ull},
- {"RESERVED_3_63" , 3, 61, 67, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 68, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_63" , 36, 28, 68, "RAZ", 1, 1, 0, 0},
- {"STATE" , 0, 64, 69, "RO", 0, 1, 0ull, 0},
- {"STATE" , 0, 64, 70, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_13" , 0, 14, 71, "RAZ", 1, 1, 0, 0},
- {"O_MODE" , 14, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"O_ES" , 15, 2, 71, "R/W", 0, 1, 0ull, 0},
- {"O_NS" , 17, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"O_RO" , 18, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"O_ADD1" , 19, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"FPA_QUE" , 20, 3, 71, "R/W", 0, 1, 0ull, 0},
- {"DWB_ICHK" , 23, 9, 71, "R/W", 0, 1, 0ull, 0},
- {"DWB_DENB" , 32, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"B0_LEND" , 33, 1, 71, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_34_47" , 34, 14, 71, "RAZ", 1, 1, 0, 0},
- {"DMA_ENB" , 48, 6, 71, "R/W", 0, 0, 0ull, 63ull},
- {"RESERVED_54_55" , 54, 2, 71, "RAZ", 1, 1, 0, 0},
- {"PKT_EN" , 56, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"PKT_HP" , 57, 1, 71, "RO", 0, 0, 0ull, 0ull},
- {"COMMIT_MODE" , 58, 1, 71, "R/W", 0, 0, 0ull, 1ull},
- {"FFP_DIS" , 59, 1, 71, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_EN1" , 60, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"DICI_MODE" , 61, 1, 71, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 71, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 72, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 72, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 73, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 73, "RAZ", 1, 1, 0, 0},
- {"BLKS" , 0, 4, 74, "R/W", 0, 1, 2ull, 0},
- {"BASE" , 4, 5, 74, "RO", 1, 1, 0, 0},
- {"RESERVED_9_31" , 9, 23, 74, "RAZ", 1, 1, 0, 0},
- {"COMPBLKS" , 32, 5, 74, "RO", 1, 1, 0, 0},
- {"RESERVED_37_63" , 37, 27, 74, "RAZ", 1, 1, 0, 0},
- {"RSL" , 0, 1, 75, "R/W1C", 0, 0, 0ull, 0ull},
- {"NCB" , 1, 1, 75, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 75, "RAZ", 1, 1, 0, 0},
- {"FFP" , 4, 4, 75, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 75, "RAZ", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 76, "R/W", 0, 0, 0ull, 0ull},
- {"DMADBO" , 8, 8, 76, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 76, "R/W", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT2_RST" , 26, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT3_RST" , 27, 1, 76, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 76, "RAZ", 1, 1, 0, 0},
- {"NDERR" , 0, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFOVR" , 1, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 77, "RAZ", 1, 1, 0, 0},
- {"DMADBO" , 8, 8, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADADR" , 16, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADLEN" , 17, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_OVRFLW" , 18, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_UNDFLW" , 19, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_ANULL" , 20, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_INULL" , 21, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"REQ_BADFIL" , 22, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 77, "RAZ", 1, 1, 0, 0},
- {"SPRT0_RST" , 24, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_RST" , 25, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT2_RST" , 26, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT3_RST" , 27, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 77, "RAZ", 1, 1, 0, 0},
- {"MOLR" , 0, 6, 78, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 78, "RAZ", 1, 1, 0, 0},
- {"SINFO" , 0, 6, 79, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 79, "RAZ", 1, 1, 0, 0},
- {"IINFO" , 8, 6, 79, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_63" , 14, 50, 79, "RAZ", 1, 1, 0, 0},
- {"PKTERR" , 0, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 80, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 81, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 81, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 82, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 82, "RAZ", 1, 1, 0, 0},
- {"QERR" , 0, 8, 83, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 83, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 84, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 84, "RAZ", 1, 1, 0, 0},
- {"EN_RSP" , 0, 8, 85, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 85, "RAZ", 1, 1, 0, 0},
- {"EN_RST" , 16, 8, 85, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 85, "RAZ", 1, 1, 0, 0},
- {"QEN" , 0, 8, 86, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_8_63" , 8, 56, 86, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 2, 87, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 87, "RAZ", 1, 1, 0, 0},
- {"MRRS_LIM" , 3, 1, 87, "R/W", 0, 0, 0ull, 0ull},
- {"MPS" , 4, 1, 87, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 87, "RAZ", 1, 1, 0, 0},
- {"MPS_LIM" , 7, 1, 87, "R/W", 0, 0, 0ull, 0ull},
- {"MOLR" , 8, 6, 87, "R/W", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 87, "RAZ", 1, 1, 0, 0},
- {"RD_MODE" , 16, 1, 87, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 87, "RAZ", 1, 1, 0, 0},
- {"QLM_CFG" , 20, 4, 87, "RO", 1, 1, 0, 0},
- {"HALT" , 24, 1, 87, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 87, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 88, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 88, "RO", 0, 1, 0ull, 0},
- {"REQQ" , 0, 3, 89, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 89, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 4, 1, 89, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 89, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 8, 1, 89, "RO", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 89, "RAZ", 1, 1, 0, 0},
- {"AUTO_GATE" , 0, 1, 90, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 90, "RO", 0, 0, 0ull, 0ull},
- {"CH0_AXI_RSPCODE" , 0, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"CH1_AXI_RSPCODE" , 2, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"CH2_AXI_RSPCODE" , 4, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"CH3_AXI_RSPCODE" , 6, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"CH4_AXI_RSPCODE" , 8, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"CH5_AXI_RSPCODE" , 10, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"CH6_AXI_RSPCODE" , 12, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"CH7_AXI_RSPCODE" , 14, 2, 91, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 91, "RO", 0, 0, 0ull, 0ull},
- {"ARLOCK" , 0, 2, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_7" , 2, 6, 92, "RO", 0, 0, 0ull, 0ull},
- {"AWLOCK" , 8, 2, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_23" , 10, 14, 92, "RO", 0, 0, 0ull, 0ull},
- {"AWCOBUF" , 24, 1, 92, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 92, "RO", 0, 0, 0ull, 0ull},
- {"AXI_ERR_INT" , 0, 1, 93, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_31" , 1, 31, 93, "RO", 0, 0, 0ull, 0ull},
- {"HI_ADDR" , 0, 8, 94, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_31" , 8, 24, 94, "RO", 0, 0, 0ull, 0ull},
- {"LO_ADDR" , 0, 32, 95, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 96, "RO", 0, 0, 0ull, 0ull},
- {"MAX_BSTLEN" , 4, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"BST_BOUND" , 5, 1, 96, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 96, "RO", 0, 0, 0ull, 0ull},
- {"AWCACHE" , 8, 4, 96, "R/W", 0, 0, 0ull, 0ull},
- {"AWCACHE_LBM" , 12, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 96, "RO", 0, 0, 0ull, 0ull},
- {"HMM_OFS" , 16, 2, 96, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_23" , 18, 6, 96, "RO", 0, 0, 0ull, 0ull},
- {"ENDIAN" , 24, 1, 96, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 96, "RO", 0, 0, 0ull, 0ull},
- {"DMA_SIZE" , 0, 18, 97, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 97, "RO", 0, 0, 0ull, 0ull},
- {"WDMA_FIX_PRTY" , 0, 4, 98, "R/W", 0, 0, 0ull, 0ull},
- {"WDMA_RR_PRTY" , 4, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RDMA_RR_PRTY" , 5, 1, 98, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 98, "RO", 0, 0, 0ull, 0ull},
- {"DMA_CH_RESET" , 0, 8, 99, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_31" , 8, 24, 99, "RO", 0, 0, 0ull, 0ull},
- {"DMA_CH_DONE" , 0, 8, 100, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_31" , 8, 24, 100, "RO", 0, 0, 0ull, 0ull},
- {"DMADONE_INTR_DIS" , 0, 16, 101, "R/W", 0, 0, 0ull, 0ull},
- {"AXIERR_INTR_DIS" , 16, 1, 101, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 101, "RO", 0, 0, 0ull, 0ull},
- {"DMADONE_INTR_ENB" , 0, 16, 102, "R/W", 0, 0, 0ull, 0ull},
- {"AXIERR_INTR_ENB" , 16, 1, 102, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 102, "RO", 0, 0, 0ull, 0ull},
- {"DMA_CH_STT" , 0, 14, 103, "RO", 0, 0, 0ull, 0ull},
- {"NON_DMAWRCH_STT" , 14, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"NON_DMARDCH_STT" , 15, 1, 103, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 103, "RO", 0, 0, 0ull, 0ull},
- {"ENAB" , 0, 1, 104, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 104, "RAZ", 0, 0, 0ull, 0ull},
- {"ENAB" , 0, 1, 105, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 105, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 9, 106, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 106, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 9, 107, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 107, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPIDX" , 0, 6, 108, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 108, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPIDX" , 0, 6, 109, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 109, "RAZ", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RACH" , 1, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDMP" , 2, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_DONE" , 4, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_RDDONE" , 5, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"VDEC" , 6, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC" , 7, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"H3GENC" , 8, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RFSPI" , 10, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_BERR" , 11, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"TTI_TIMER" , 12, 8, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_FFTHRESH" , 20, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_FFFLAG" , 21, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RXD_FFTHRESH" , 22, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RXD_FFFLAG" , 23, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_STFRAME" , 24, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_STRX" , 25, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI0" , 26, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI1" , 27, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI2" , 28, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI3" , 29, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_SPISKIP" , 30, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_PPSSYNC" , 31, 1, 110, "R/W", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RACH" , 1, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDMP" , 2, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_DONE" , 4, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_RDDONE" , 5, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"VDEC" , 6, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC" , 7, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"H3GENC" , 8, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RFSPI" , 10, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_BERR" , 11, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"TTI_TIMER" , 12, 8, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_FFTHRESH" , 20, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_FFFLAG" , 21, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RXD_FFTHRESH" , 22, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RXD_FFFLAG" , 23, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_STFRAME" , 24, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_STRX" , 25, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI0" , 26, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI1" , 27, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI2" , 28, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI3" , 29, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_SPISKIP" , 30, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_PPSSYNC" , 31, 1, 111, "R/W", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RACH" , 1, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDMP" , 2, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_DONE" , 4, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_RDDONE" , 5, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"VDEC" , 6, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC" , 7, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"H3GENC" , 8, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RFSPI" , 10, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_BERR" , 11, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"TTI_TIMER" , 12, 8, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_FFTHRESH" , 20, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_FFFLAG" , 21, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RXD_FFTHRESH" , 22, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RXD_FFFLAG" , 23, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_STFRAME" , 24, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_STRX" , 25, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI0" , 26, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI1" , 27, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI2" , 28, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI3" , 29, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_SPISKIP" , 30, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_PPSSYNC" , 31, 1, 112, "R/W", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RACH" , 1, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDMP" , 2, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_DONE" , 4, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_RDDONE" , 5, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"VDEC" , 6, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC" , 7, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"H3GENC" , 8, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RFSPI" , 10, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_BERR" , 11, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"TTI_TIMER" , 12, 8, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_FFTHRESH" , 20, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_FFFLAG" , 21, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RXD_FFTHRESH" , 22, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RXD_FFFLAG" , 23, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_STFRAME" , 24, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_STRX" , 25, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI0" , 26, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI1" , 27, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI2" , 28, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI3" , 29, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_SPISKIP" , 30, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_PPSSYNC" , 31, 1, 113, "R/W", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RACH" , 1, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDMP" , 2, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_DONE" , 4, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_RDDONE" , 5, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"VDEC" , 6, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC" , 7, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"H3GENC" , 8, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RFSPI" , 10, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_BERR" , 11, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"TTI_TIMER" , 12, 8, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_FFTHRESH" , 20, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_FFFLAG" , 21, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RXD_FFTHRESH" , 22, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RXD_FFFLAG" , 23, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_STFRAME" , 24, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_STRX" , 25, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI0" , 26, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI1" , 27, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI2" , 28, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_SPI3" , 29, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_SPISKIP" , 30, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"RF_RX_PPSSYNC" , 31, 1, 114, "R/W", 0, 0, 0ull, 0ull},
- {"GRPIDX" , 0, 6, 115, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 115, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPIDX" , 0, 6, 116, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 116, "RAZ", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF" , 1, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 2, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 4, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 5, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 6, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 7, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 8, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 9, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_RM" , 10, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 11, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 12, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 13, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 14, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 15, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 16, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 17, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 18, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 19, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 20, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 21, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_0" , 22, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_1" , 23, 1, 117, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 117, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF" , 1, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 2, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 4, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 5, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 6, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 7, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 8, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 9, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_RM" , 10, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 11, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 12, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 13, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 14, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 15, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 16, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 17, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 18, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 19, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 20, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 21, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_0" , 22, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_1" , 23, 1, 118, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 118, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF" , 1, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 2, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 4, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 5, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 6, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 7, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 8, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 9, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_RM" , 10, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 11, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 12, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 13, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 14, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 15, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 16, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 17, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 18, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 19, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 20, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 21, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_0" , 22, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_1" , 23, 1, 119, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 119, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF" , 1, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 2, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 4, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 5, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 6, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 7, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 8, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 9, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_RM" , 10, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 11, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 12, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 13, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 14, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 15, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 16, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 17, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 18, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 19, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 20, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 21, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_0" , 22, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_1" , 23, 1, 120, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 120, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF" , 1, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 2, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 4, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 5, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 6, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 7, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 8, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 9, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_RM" , 10, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 11, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 12, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 13, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 14, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 15, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 16, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 17, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 18, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 19, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 20, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 21, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_0" , 22, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_1" , 23, 1, 121, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 121, "RAZ", 1, 1, 0, 0},
- {"GRPIDX" , 0, 6, 122, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 122, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPIDX" , 0, 6, 123, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 123, "RAZ", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF" , 1, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 2, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 4, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 5, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 6, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 7, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 8, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 9, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_RM" , 10, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 11, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 12, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 13, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 14, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 15, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 16, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 17, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 18, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 19, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 20, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 21, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_0" , 22, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_1" , 23, 1, 124, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 124, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF" , 1, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 2, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 4, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 5, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 6, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 7, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 8, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 9, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_RM" , 10, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 11, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 12, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 13, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 14, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 15, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 16, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 17, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 18, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 19, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 20, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 21, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_0" , 22, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_1" , 23, 1, 125, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 125, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF" , 1, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 2, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 4, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 5, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 6, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 7, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 8, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 9, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_RM" , 10, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 11, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 12, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 13, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 14, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 15, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 16, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 17, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 18, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 19, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 20, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 21, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_0" , 22, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_1" , 23, 1, 126, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 126, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF" , 1, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 2, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 4, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 5, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 6, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 7, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 8, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 9, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_RM" , 10, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 11, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 12, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 13, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 14, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 15, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 16, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 17, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 18, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 19, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 20, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 21, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_0" , 22, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_1" , 23, 1, 127, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 127, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF" , 1, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 2, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 3, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 4, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 5, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 6, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 7, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 8, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 9, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_RM" , 10, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 11, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 12, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 13, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 14, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 15, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 16, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 17, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 18, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 19, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 20, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 21, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_0" , 22, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"T3_RFIF_1" , 23, 1, 128, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 128, "RAZ", 1, 1, 0, 0},
- {"WRDONE" , 0, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"RDDONE" , 1, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"RDQDONE" , 2, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"WRQDONE" , 3, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"SW" , 4, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"MISC" , 5, 1, 129, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 129, "RAZ", 0, 0, 0ull, 0ull},
- {"WRDONE" , 0, 1, 130, "RO", 0, 0, 0ull, 0ull},
- {"RDDONE" , 1, 1, 130, "RO", 0, 0, 0ull, 0ull},
- {"RDQDONE" , 2, 1, 130, "RO", 0, 0, 0ull, 0ull},
- {"WRQDONE" , 3, 1, 130, "RO", 0, 0, 0ull, 0ull},
- {"SW" , 4, 1, 130, "RO", 0, 0, 0ull, 0ull},
- {"MISC" , 5, 1, 130, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 130, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPIDX" , 0, 6, 131, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 131, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPIDX" , 0, 6, 132, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 132, "RAZ", 0, 0, 0ull, 0ull},
- {"SWINT" , 0, 32, 133, "R/W", 0, 0, 0ull, 0ull},
- {"SWINT" , 0, 32, 134, "R/W", 0, 0, 0ull, 0ull},
- {"SWINT" , 0, 32, 135, "R/W", 0, 0, 0ull, 0ull},
- {"SWINT" , 0, 32, 136, "R/W", 0, 0, 0ull, 0ull},
- {"SWINT" , 0, 32, 137, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 32, 138, "R/W1C", 0, 0, 0ull, 0ull},
- {"SET" , 0, 32, 139, "R/W1", 0, 0, 0ull, 0ull},
- {"GRPIDX" , 0, 6, 140, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 140, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPIDX" , 0, 6, 141, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 141, "RAZ", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_0" , 1, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_1" , 2, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 3, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 4, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_SB" , 5, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 6, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 7, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 8, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 9, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_CCH" , 10, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 11, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 12, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 13, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 14, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INSTR" , 15, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 16, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 17, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 18, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INSTR" , 19, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 20, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 21, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INSTR" , 22, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 23, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 24, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 25, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 26, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T1_RFIF_0" , 27, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"T1_RFIF_1" , 28, 1, 142, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 142, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_0" , 1, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_1" , 2, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 3, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 4, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_SB" , 5, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 6, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 7, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 8, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 9, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_CCH" , 10, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 11, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 12, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 13, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 14, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INSTR" , 15, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 16, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 17, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 18, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INSTR" , 19, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 20, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 21, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INSTR" , 22, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 23, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 24, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 25, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 26, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T1_RFIF_0" , 27, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"T1_RFIF_1" , 28, 1, 143, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 143, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_0" , 1, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_1" , 2, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 3, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 4, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_SB" , 5, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 6, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 7, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 8, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 9, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_CCH" , 10, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 11, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 12, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 13, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 14, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INSTR" , 15, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 16, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 17, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 18, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INSTR" , 19, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 20, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 21, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INSTR" , 22, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 23, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 24, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 25, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 26, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T1_RFIF_0" , 27, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"T1_RFIF_1" , 28, 1, 144, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 144, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_0" , 1, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_1" , 2, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 3, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 4, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_SB" , 5, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 6, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 7, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 8, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 9, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_CCH" , 10, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 11, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 12, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 13, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 14, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INSTR" , 15, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 16, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 17, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 18, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INSTR" , 19, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 20, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 21, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INSTR" , 22, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 23, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 24, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 25, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 26, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T1_RFIF_0" , 27, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"T1_RFIF_1" , 28, 1, 145, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 145, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_0" , 1, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_1" , 2, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 3, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 4, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_SB" , 5, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 6, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 7, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 8, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 9, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_CCH" , 10, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 11, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 12, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 13, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 14, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INSTR" , 15, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 16, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 17, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 18, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INSTR" , 19, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 20, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 21, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INSTR" , 22, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_TX" , 23, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX0" , 24, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1" , 25, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"AXI_RX1_HARQ" , 26, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T1_RFIF_0" , 27, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"T1_RFIF_1" , 28, 1, 146, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 146, "RAZ", 1, 1, 0, 0},
- {"GRPIDX" , 0, 6, 147, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 147, "RAZ", 0, 0, 0ull, 0ull},
- {"GRPIDX" , 0, 6, 148, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 148, "RAZ", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_0" , 1, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_1" , 2, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 3, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 4, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_SB" , 5, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 6, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 7, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 8, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 9, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_CCH" , 10, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 11, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 12, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 13, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 14, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INSTR" , 15, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 16, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 17, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 18, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INSTR" , 19, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 20, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 21, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INSTR" , 22, 1, 149, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 149, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_0" , 1, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_1" , 2, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 3, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 4, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_SB" , 5, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 6, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 7, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 8, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 9, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_CCH" , 10, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 11, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 12, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 13, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 14, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INSTR" , 15, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 16, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 17, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 18, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INSTR" , 19, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 20, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 21, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INSTR" , 22, 1, 150, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 150, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_0" , 1, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_1" , 2, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 3, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 4, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_SB" , 5, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 6, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 7, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 8, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 9, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_CCH" , 10, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 11, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 12, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 13, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 14, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INSTR" , 15, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 16, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 17, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 18, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INSTR" , 19, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 20, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 21, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INSTR" , 22, 1, 151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 151, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_0" , 1, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_1" , 2, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 3, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 4, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_SB" , 5, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 6, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 7, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 8, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 9, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_CCH" , 10, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 11, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 12, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 13, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 14, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INSTR" , 15, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 16, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 17, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 18, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INSTR" , 19, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 20, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 21, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INSTR" , 22, 1, 152, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 152, "RAZ", 1, 1, 0, 0},
- {"ULFE" , 0, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_0" , 1, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RACHSNIF_1" , 2, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"DFTDM" , 3, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO" , 4, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_SB" , 5, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"TURBO_HQ" , 6, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"VITBDEC" , 7, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB0" , 8, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_TB1" , 9, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"LTEENC_CCH" , 10, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_0" , 11, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"IFFTPAPR_1" , 12, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"T1_EXT" , 13, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INT" , 14, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"T1_INSTR" , 15, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"T2_EXT" , 16, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INT" , 17, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"T2_HARQ" , 18, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"T2_INSTR" , 19, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"T3_EXT" , 20, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INT" , 21, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"T3_INSTR" , 22, 1, 153, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 153, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 24, 154, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 154, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 155, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 155, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 156, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 156, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 157, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 157, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 158, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 158, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 159, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 159, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 160, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 160, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 161, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 161, "RO", 0, 0, 0ull, 0ull},
- {"XFER_COMPLETE" , 0, 1, 162, "WO", 0, 0, 0ull, 0ull},
- {"XFER_Q_EMPTY" , 1, 1, 162, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 162, "RO", 0, 0, 0ull, 0ull},
- {"XFER_COMPLETE" , 0, 1, 163, "R/W", 0, 0, 0ull, 0ull},
- {"XFER_Q_EMPTY" , 1, 1, 163, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 163, "RO", 0, 0, 0ull, 0ull},
- {"XFER_COMPLETE" , 0, 1, 164, "RO", 0, 0, 0ull, 0ull},
- {"XFER_Q_EMPTY" , 1, 1, 164, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 164, "RO", 0, 0, 0ull, 0ull},
- {"XFER_COMPLETE" , 0, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"XFER_Q_EMPTY" , 1, 1, 165, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 165, "RO", 0, 0, 0ull, 0ull},
- {"XFER_COMPLETE" , 0, 1, 166, "WO", 0, 0, 0ull, 0ull},
- {"XFER_Q_EMPTY" , 1, 1, 166, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 166, "RO", 0, 0, 0ull, 0ull},
- {"AUTO_CLK_ENB" , 0, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"MEM_CLR_ENB" , 1, 1, 167, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 167, "RO", 0, 0, 0ull, 0ull},
- {"ITLV_BUFMODE" , 4, 2, 167, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 167, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 168, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 168, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 169, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 170, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 170, "RO", 0, 0, 0ull, 0ull},
- {"ADDR" , 0, 24, 171, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 171, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 172, "RO", 0, 0, 0ull, 0ull},
- {"WORDCNT" , 0, 16, 173, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_28" , 16, 13, 173, "RO", 0, 0, 0ull, 0ull},
- {"CBUF_MODE" , 29, 1, 173, "R/W", 0, 0, 0ull, 0ull},
- {"SLICE_MODE" , 30, 1, 173, "R/W", 0, 0, 0ull, 0ull},
- {"XFER_COMP_INTR" , 31, 1, 173, "R/W", 0, 0, 0ull, 0ull},
- {"STATUS" , 0, 32, 174, "RO", 0, 0, 0ull, 0ull},
- {"START" , 0, 1, 175, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 175, "RO", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 176, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 176, "RO", 0, 0, 0ull, 0ull},
- {"OFFSET" , 0, 20, 177, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 177, "RO", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 178, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 178, "RO", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 20, 179, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 179, "RO", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 1, 180, "R/W", 0, 0, 0ull, 1ull},
- {"MODE" , 1, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"INV" , 2, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"FLUSH" , 3, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"WAVESAT_MODE" , 4, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"CLR_FIFO_UR" , 5, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"CLR_FIFO_OF" , 6, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"ADI_EN" , 7, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"DSP_RX_INT_EN" , 8, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"MAN_CTRL" , 9, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_CTRL" , 10, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"TXNRX_CTRL" , 11, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"PROD_TYPE" , 12, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"DUPLEX" , 13, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"DIVERSITY" , 14, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"UPD_STYLE" , 15, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"MOL" , 16, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBACK" , 17, 1, 180, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 180, "RO", 0, 0, 0ull, 0ull},
- {"BEHAVIOR" , 0, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"IQ_CFG" , 1, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"LATENCY" , 2, 1, 181, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 181, "RO", 0, 0, 0ull, 0ull},
- {"VAL" , 0, 4, 182, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 182, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 183, "RC", 0, 0, 0ull, 0ull},
- {"RESERVED_0_15" , 0, 16, 184, "RO", 0, 0, 0ull, 0ull},
- {"ENA" , 16, 8, 184, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 184, "RO", 0, 0, 0ull, 0ull},
- {"RX_FIL" , 0, 1, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RX_DIF_FIL" , 1, 1, 185, "R/W", 0, 0, 0ull, 0ull},
- {"TX_FIL" , 2, 1, 185, "R/W", 0, 0, 0ull, 0ull},
- {"TX_DIV_FIL" , 3, 1, 185, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 185, "RO", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 20, 186, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 186, "RO", 0, 0, 0ull, 0ull},
- {"LENGTH" , 0, 20, 187, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 187, "RO", 0, 0, 0ull, 0ull},
- {"SRC" , 0, 2, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RISE_VAL" , 2, 11, 188, "R/W", 0, 0, 0ull, 0ull},
- {"FALL_VAL" , 13, 11, 188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 188, "RO", 0, 0, 0ull, 0ull},
- {"NUM" , 0, 10, 189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 189, "RO", 0, 0, 0ull, 0ull},
- {"NUM" , 0, 10, 190, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 190, "RO", 0, 0, 0ull, 0ull},
- {"NUM" , 0, 3, 191, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 191, "RO", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 192, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 192, "RO", 0, 0, 0ull, 0ull},
- {"HI_TIME" , 0, 24, 193, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 193, "RO", 0, 0, 0ull, 0ull},
- {"LO_TIME" , 0, 24, 194, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 194, "RO", 0, 0, 0ull, 0ull},
- {"VAL" , 0, 32, 195, "RO", 0, 0, 0ull, 0ull},
- {"VAL" , 0, 32, 196, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 0, 32, 197, "RO", 0, 0, 0ull, 0ull},
- {"TIMER" , 0, 32, 198, "RO", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 199, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 199, "RO", 0, 0, 0ull, 0ull},
- {"OFFSET" , 0, 4, 200, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 200, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 201, "RO", 0, 0, 0ull, 0ull},
- {"HAB_REQ_SM" , 8, 4, 201, "RO", 0, 0, 0ull, 0ull},
- {"RX_SM" , 12, 2, 201, "RO", 0, 0, 0ull, 0ull},
- {"TX_SM" , 14, 2, 201, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_UR" , 16, 1, 201, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_OF" , 17, 1, 201, "RO", 0, 0, 0ull, 0ull},
- {"THRESH_RCH" , 18, 1, 201, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_20" , 19, 2, 201, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_LATE" , 21, 1, 201, "RO", 0, 0, 0ull, 0ull},
- {"RFIC_ENA" , 22, 1, 201, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 201, "RO", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 13, 202, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 202, "RO", 0, 0, 0ull, 0ull},
- {"CAP_LAT" , 0, 4, 203, "R/W", 0, 0, 0ull, 0ull},
- {"HALF_LAT" , 4, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"EORL" , 5, 1, 203, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 203, "RO", 0, 0, 0ull, 0ull},
- {"LEAD" , 0, 12, 204, "R/W", 0, 0, 0ull, 0ull},
- {"LAG" , 12, 12, 204, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 204, "RO", 0, 0, 0ull, 0ull},
- {"EXE1" , 0, 1, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"EXE2" , 1, 1, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"EXE3" , 2, 1, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 205, "RO", 0, 0, 0ull, 0ull},
- {"ALT_ANT" , 8, 1, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 205, "RO", 0, 0, 0ull, 0ull},
- {"HIDDEN" , 12, 1, 205, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 205, "RO", 0, 0, 0ull, 0ull},
- {"OFFSET" , 0, 20, 206, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 206, "RO", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 20, 207, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 207, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 208, "RO", 0, 0, 0ull, 0ull},
- {"HAB_REQ_SM" , 8, 4, 208, "RO", 0, 0, 0ull, 0ull},
- {"RX_SM" , 12, 2, 208, "RO", 0, 0, 0ull, 0ull},
- {"TX_SM" , 14, 2, 208, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_UR" , 16, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_OF" , 17, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"THRESH_RCH" , 18, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_20" , 19, 2, 208, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_LATE" , 21, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"RFIC_ENA" , 22, 1, 208, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 208, "RO", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 20, 209, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 209, "RO", 0, 0, 0ull, 0ull},
- {"VAL" , 0, 20, 210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 210, "RO", 0, 0, 0ull, 0ull},
- {"THR" , 0, 12, 211, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 211, "RO", 0, 0, 0ull, 0ull},
- {"SIZE" , 0, 13, 212, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 212, "RO", 0, 0, 0ull, 0ull},
- {"END_CNT" , 0, 20, 213, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 213, "RO", 0, 0, 0ull, 0ull},
- {"START_PNT" , 0, 20, 214, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 214, "RO", 0, 0, 0ull, 0ull},
- {"ADJ" , 0, 1, 215, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 215, "RO", 0, 0, 0ull, 0ull},
- {"OFFSET" , 0, 32, 216, "RC", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 20, 217, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 217, "RO", 0, 0, 0ull, 0ull},
- {"BITS" , 0, 2, 218, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_31" , 2, 30, 218, "RO", 0, 0, 0ull, 0ull},
- {"NUM" , 0, 20, 219, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 219, "RO", 0, 0, 0ull, 0ull},
- {"RW" , 0, 1, 220, "R/W", 0, 0, 0ull, 0ull},
- {"GEN_INT" , 1, 1, 220, "R/W", 0, 0, 0ull, 0ull},
- {"BYTES" , 2, 1, 220, "R/W", 0, 0, 0ull, 0ull},
- {"SLAVE" , 3, 1, 220, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 220, "RO", 0, 0, 0ull, 0ull},
- {"WORD" , 0, 24, 221, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 221, "RO", 0, 0, 0ull, 0ull},
- {"NUM_CMDS0" , 0, 6, 222, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_CMDS1" , 6, 6, 222, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_CMDS2" , 12, 6, 222, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_CMDS3" , 18, 6, 222, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 222, "RO", 0, 0, 0ull, 0ull},
- {"START0" , 0, 6, 223, "R/W", 0, 0, 0ull, 0ull},
- {"START1" , 6, 6, 223, "R/W", 0, 0, 0ull, 0ull},
- {"START2" , 12, 6, 223, "R/W", 0, 0, 0ull, 0ull},
- {"START3" , 18, 6, 223, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 223, "RO", 0, 0, 0ull, 0ull},
- {"CTRL" , 0, 32, 224, "R/W", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 16, 225, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 225, "RO", 0, 0, 0ull, 0ull},
- {"RD_DATA" , 0, 32, 226, "RO", 0, 0, 0ull, 0ull},
- {"TX_FIFO_LVL" , 0, 4, 227, "RO", 0, 0, 0ull, 0ull},
- {"RX_FIFO_LVL" , 4, 4, 227, "RO", 0, 0, 0ull, 0ull},
- {"SR_STATE" , 8, 4, 227, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 227, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 228, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 8, 8, 228, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR" , 16, 9, 228, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_30" , 25, 6, 228, "RO", 0, 0, 0ull, 0ull},
- {"WRITE" , 31, 1, 228, "R/W", 0, 0, 0ull, 0ull},
- {"CLKS" , 0, 8, 229, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_31" , 8, 24, 229, "RO", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 230, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_31" , 1, 31, 230, "RO", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 20, 231, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 231, "RO", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 8, 232, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_31" , 8, 24, 232, "RO", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 8, 233, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_31" , 8, 24, 233, "RO", 0, 0, 0ull, 0ull},
- {"MAP" , 0, 8, 234, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_31" , 8, 24, 234, "RO", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 8, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_31" , 8, 24, 235, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 236, "RO", 0, 0, 0ull, 0ull},
- {"HAB_REQ_SM" , 8, 4, 236, "RO", 0, 0, 0ull, 0ull},
- {"RX_SM" , 12, 2, 236, "RO", 0, 0, 0ull, 0ull},
- {"TX_SM" , 14, 2, 236, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_UR" , 16, 1, 236, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_OF" , 17, 1, 236, "RO", 0, 0, 0ull, 0ull},
- {"THRESH_RCH" , 18, 1, 236, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_20" , 19, 2, 236, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_LATE" , 21, 1, 236, "RO", 0, 0, 0ull, 0ull},
- {"RFIC_ENA" , 22, 1, 236, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 236, "RO", 0, 0, 0ull, 0ull},
- {"ANTENNA" , 0, 2, 237, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_SCH" , 2, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 3, 1, 237, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 237, "RO", 0, 0, 0ull, 0ull},
- {"LEAD" , 0, 12, 238, "R/W", 0, 0, 0ull, 0ull},
- {"LAG" , 12, 12, 238, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 238, "RO", 0, 0, 0ull, 0ull},
- {"OFFSET" , 0, 20, 239, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 239, "RO", 0, 0, 0ull, 0ull},
- {"CNT" , 0, 20, 240, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 240, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 241, "RO", 0, 0, 0ull, 0ull},
- {"HAB_REQ_SM" , 8, 4, 241, "RO", 0, 0, 0ull, 0ull},
- {"RX_SM" , 12, 2, 241, "RO", 0, 0, 0ull, 0ull},
- {"TX_SM" , 14, 2, 241, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_UR" , 16, 1, 241, "RO", 0, 0, 0ull, 0ull},
- {"FIFO_OF" , 17, 1, 241, "RO", 0, 0, 0ull, 0ull},
- {"THRESH_RCH" , 18, 1, 241, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_20" , 19, 2, 241, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_LATE" , 21, 1, 241, "RO", 0, 0, 0ull, 0ull},
- {"RFIC_ENA" , 22, 1, 241, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 241, "RO", 0, 0, 0ull, 0ull},
- {"THR" , 0, 12, 242, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_31" , 12, 20, 242, "RO", 0, 0, 0ull, 0ull},
- {"ENABLE" , 0, 4, 243, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 243, "RO", 0, 0, 0ull, 0ull},
- {"SCNT" , 0, 20, 244, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 244, "RO", 0, 0, 0ull, 0ull},
- {"VAL" , 0, 32, 245, "WO", 0, 0, 0ull, 0ull},
- {"VAL" , 0, 32, 246, "WO", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"RACHFE" , 1, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"RX0SEQ" , 2, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"DFTDMAP" , 3, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"RX1SEQ" , 4, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"TURBOPHY" , 5, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"TURBODSP" , 6, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"VDEC" , 7, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"LTEENC" , 8, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"V3GENC" , 10, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"TXSEQ" , 11, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"AXIDMA" , 12, 1, 247, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 247, "RO", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"RACHFE" , 1, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"RX0SEQ" , 2, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"DFTDMAP" , 3, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"RX1SEQ" , 4, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"TURBOPHY" , 5, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"TURBODSP" , 6, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"VDEC" , 7, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"LTEENC" , 8, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"V3GENC" , 10, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"TXSEQ" , 11, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"AXIDMA" , 12, 1, 248, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 248, "RO", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RACHFE" , 1, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RX0SEQ" , 2, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"DFTDMAP" , 3, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RX1SEQ" , 4, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"TURBOPHY" , 5, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"TURBODSP" , 6, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"VDEC" , 7, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"LTEENC" , 8, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"V3GENC" , 10, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"TXSEQ" , 11, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"AXIDMA" , 12, 1, 249, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 249, "RO", 0, 0, 0ull, 0ull},
- {"RFIF_RF" , 0, 1, 250, "WO", 0, 0, 0ull, 0ull},
- {"RFIF_HAB" , 1, 1, 250, "WO", 0, 0, 0ull, 0ull},
- {"RFSPI" , 2, 1, 250, "WO", 0, 0, 0ull, 0ull},
- {"TILE1DSP" , 3, 1, 250, "WO", 0, 0, 0ull, 0ull},
- {"TILE2DSP" , 4, 1, 250, "WO", 0, 0, 0ull, 0ull},
- {"TILE3DSP" , 5, 1, 250, "WO", 0, 0, 0ull, 0ull},
- {"TOKEN" , 6, 1, 250, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 250, "RO", 0, 0, 0ull, 0ull},
- {"RFIF_RF" , 0, 1, 251, "WO", 0, 0, 0ull, 0ull},
- {"RFIF_HAB" , 1, 1, 251, "WO", 0, 0, 0ull, 0ull},
- {"RFSPI" , 2, 1, 251, "WO", 0, 0, 0ull, 0ull},
- {"TILE1DSP" , 3, 1, 251, "WO", 0, 0, 0ull, 0ull},
- {"TILE2DSP" , 4, 1, 251, "WO", 0, 0, 0ull, 0ull},
- {"TILE3DSP" , 5, 1, 251, "WO", 0, 0, 0ull, 0ull},
- {"TOKEN" , 6, 1, 251, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 251, "RO", 0, 0, 0ull, 0ull},
- {"RFIF_RF" , 0, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"RFIF_HAB" , 1, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"RFSPI" , 2, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"TILE1DSP" , 3, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"TILE2DSP" , 4, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"TILE3DSP" , 5, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"TOKEN" , 6, 1, 252, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 252, "RO", 0, 0, 0ull, 0ull},
- {"RX0DSP0" , 0, 1, 253, "WO", 0, 0, 0ull, 0ull},
- {"RX0DSP1" , 1, 1, 253, "WO", 0, 0, 0ull, 0ull},
- {"RX1DSP0" , 2, 1, 253, "WO", 0, 0, 0ull, 0ull},
- {"RX1DSP1" , 3, 1, 253, "WO", 0, 0, 0ull, 0ull},
- {"TXDSP0" , 4, 1, 253, "WO", 0, 0, 0ull, 0ull},
- {"TXDSP1" , 5, 1, 253, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 253, "RO", 0, 0, 0ull, 0ull},
- {"RX0DSP0" , 0, 1, 254, "WO", 0, 0, 0ull, 0ull},
- {"RX0DSP1" , 1, 1, 254, "WO", 0, 0, 0ull, 0ull},
- {"RX1DSP0" , 2, 1, 254, "WO", 0, 0, 0ull, 0ull},
- {"RX1DSP1" , 3, 1, 254, "WO", 0, 0, 0ull, 0ull},
- {"TXDSP0" , 4, 1, 254, "WO", 0, 0, 0ull, 0ull},
- {"TXDSP1" , 5, 1, 254, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 254, "RO", 0, 0, 0ull, 0ull},
- {"RX0DSP0" , 0, 1, 255, "RO", 0, 0, 0ull, 0ull},
- {"RX0DSP1" , 1, 1, 255, "RO", 0, 0, 0ull, 0ull},
- {"RX1DSP0" , 2, 1, 255, "RO", 0, 0, 0ull, 0ull},
- {"RX1DSP1" , 3, 1, 255, "RO", 0, 0, 0ull, 0ull},
- {"TXDSP0" , 4, 1, 255, "RO", 0, 0, 0ull, 0ull},
- {"TXDSP1" , 5, 1, 255, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 255, "RO", 0, 0, 0ull, 0ull},
- {"SW_INTR" , 0, 24, 256, "RO", 0, 0, 0ull, 0ull},
- {"TIMER_INTR" , 24, 8, 256, "RO", 0, 0, 0ull, 0ull},
- {"SW_INTR" , 0, 24, 257, "RO", 0, 0, 0ull, 0ull},
- {"TIMER_INTR" , 24, 8, 257, "RO", 0, 0, 0ull, 0ull},
- {"SW_INTR" , 0, 24, 258, "RO", 0, 0, 0ull, 0ull},
- {"TIMER_INTR" , 24, 8, 258, "RO", 0, 0, 0ull, 0ull},
- {"VALUE" , 0, 32, 259, "RO", 0, 0, 0ull, 0ull},
- {"VALUE" , 0, 32, 260, "RO", 0, 0, 0ull, 0ull},
- {"VALUE" , 0, 32, 261, "RO", 0, 0, 0ull, 0ull},
- {"VALUE" , 0, 32, 262, "RO", 0, 0, 0ull, 0ull},
- {"VALUE" , 0, 32, 263, "RO", 0, 0, 0ull, 0ull},
- {"T1IMEM_INITENB" , 0, 1, 264, "R/W", 0, 0, 0ull, 0ull},
- {"T1SMEM_INITENB" , 1, 1, 264, "R/W", 0, 0, 0ull, 0ull},
- {"T2IMEM_INITENB" , 2, 1, 264, "R/W", 0, 0, 0ull, 0ull},
- {"T2SMEM_INITENB" , 3, 1, 264, "R/W", 0, 0, 0ull, 0ull},
- {"T3IMEM_INITENB" , 4, 1, 264, "R/W", 0, 0, 0ull, 0ull},
- {"T3SMEM_INITENB" , 5, 1, 264, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 264, "RO", 0, 0, 0ull, 0ull},
- {"RINGOSC_COUNT" , 0, 16, 265, "RO", 0, 0, 0ull, 0ull},
- {"TRANSISTOR_SEL" , 16, 2, 265, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 265, "RO", 0, 0, 0ull, 0ull},
- {"COUNT" , 0, 24, 266, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 266, "RO", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"RACHFE" , 1, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"RX0SEQ" , 2, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"DFTDMAP" , 3, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"RX1SEQ" , 4, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"TURBOPHY" , 5, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"TURBODSP" , 6, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"VDEC" , 7, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"LTEENC" , 8, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"V3GENC" , 10, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"TXSEQ" , 11, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"AXIDMA" , 12, 1, 267, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 267, "RO", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"RACHFE" , 1, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"RX0SEQ" , 2, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"DFTDMAP" , 3, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"RX1SEQ" , 4, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"TURBOPHY" , 5, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"TURBODSP" , 6, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"VDEC" , 7, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"LTEENC" , 8, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"V3GENC" , 10, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"TXSEQ" , 11, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"AXIDMA" , 12, 1, 268, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 268, "RO", 0, 0, 0ull, 0ull},
- {"ULFE" , 0, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"RACHFE" , 1, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"RX0SEQ" , 2, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"DFTDMAP" , 3, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"RX1SEQ" , 4, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"TURBOPHY" , 5, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"TURBODSP" , 6, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"VDEC" , 7, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"LTEENC" , 8, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"IFFTPAPR" , 9, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"V3GENC" , 10, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"TXSEQ" , 11, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"AXIDMA" , 12, 1, 269, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 269, "RO", 0, 0, 0ull, 0ull},
- {"RFIF_RF" , 0, 1, 270, "WO", 0, 0, 0ull, 0ull},
- {"RFIF_HAB" , 1, 1, 270, "WO", 0, 0, 0ull, 0ull},
- {"RFSPI" , 2, 1, 270, "WO", 0, 0, 0ull, 0ull},
- {"TILE1DSP" , 3, 1, 270, "WO", 0, 0, 0ull, 0ull},
- {"TILE2DSP" , 4, 1, 270, "WO", 0, 0, 0ull, 0ull},
- {"TILE3DSP" , 5, 1, 270, "WO", 0, 0, 0ull, 0ull},
- {"TOKEN" , 6, 1, 270, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 270, "RO", 0, 0, 0ull, 0ull},
- {"RFIF_RF" , 0, 1, 271, "WO", 0, 0, 0ull, 0ull},
- {"RFIF_HAB" , 1, 1, 271, "WO", 0, 0, 0ull, 0ull},
- {"RFSPI" , 2, 1, 271, "WO", 0, 0, 0ull, 0ull},
- {"TILE1DSP" , 3, 1, 271, "WO", 0, 0, 0ull, 0ull},
- {"TILE2DSP" , 4, 1, 271, "WO", 0, 0, 0ull, 0ull},
- {"TILE3DSP" , 5, 1, 271, "WO", 0, 0, 0ull, 0ull},
- {"TOKEN" , 6, 1, 271, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 271, "RO", 0, 0, 0ull, 0ull},
- {"RFIF_RF" , 0, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"RFIF_HAB" , 1, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"RFSPI" , 2, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"TILE1DSP" , 3, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"TILE2DSP" , 4, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"TILE3DSP" , 5, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"TOKEN" , 6, 1, 272, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_31" , 7, 25, 272, "RO", 0, 0, 0ull, 0ull},
- {"SW_INTR" , 0, 24, 273, "RO", 0, 0, 0ull, 0ull},
- {"TIMER_INTR" , 24, 8, 273, "RO", 0, 0, 0ull, 0ull},
- {"SW_INTR" , 0, 24, 274, "RO", 0, 0, 0ull, 0ull},
- {"TIMER_INTR" , 24, 8, 274, "RO", 0, 0, 0ull, 0ull},
- {"SW_INTR" , 0, 24, 275, "RO", 0, 0, 0ull, 0ull},
- {"TIMER_INTR" , 24, 8, 275, "RO", 0, 0, 0ull, 0ull},
- {"VALUE" , 0, 24, 276, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 276, "RO", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"CONT" , 1, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 2, 1, 277, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 277, "RO", 0, 0, 0ull, 0ull},
- {"INTR_ENB" , 8, 8, 277, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 277, "RO", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 8, 278, "WO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_31" , 8, 24, 278, "RO", 0, 0, 0ull, 0ull},
- {"STATUS" , 0, 8, 279, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_31" , 8, 24, 279, "RO", 0, 0, 0ull, 0ull},
- {"VALUE" , 0, 32, 280, "RO", 0, 0, 0ull, 0ull},
- {"VALUE" , 0, 32, 281, "RO", 0, 0, 0ull, 0ull},
- {"MINOR" , 0, 8, 282, "RO", 0, 0, 0ull, 0ull},
- {"MAJOR" , 8, 8, 282, "RO", 0, 0, 0ull, 16ull},
- {"RESERVED_16_31" , 16, 16, 282, "RO", 0, 0, 0ull, 0ull},
- {"LDDF" , 0, 1, 283, "RO", 1, 0, 0, 0ull},
- {"PPAF" , 1, 1, 283, "RO", 1, 0, 0, 0ull},
- {"STDF" , 2, 1, 283, "RO", 1, 0, 0, 0ull},
- {"RESERVED_3_15" , 3, 13, 283, "RAZ", 1, 1, 0, 0},
- {"START_BIST" , 16, 1, 283, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 17, 1, 283, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 283, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 284, "R/W", 0, 0, 1ull, 0ull},
- {"ENA" , 1, 1, 284, "R/W", 0, 0, 1ull, 1ull},
- {"RWAM" , 2, 2, 284, "R/W", 0, 0, 0ull, 0ull},
- {"BUSY" , 4, 1, 284, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 284, "RAZ", 1, 1, 0, 0},
- {"PPAF_WM" , 8, 5, 284, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_13_63" , 13, 51, 284, "RAZ", 1, 1, 0, 0},
- {"ROUT0" , 0, 18, 285, "RO", 1, 0, 0, 0ull},
- {"ROUT1" , 18, 18, 285, "RO", 1, 0, 0, 0ull},
- {"ROUT2" , 36, 18, 285, "RO", 1, 0, 0, 0ull},
- {"RESERVED_54_63" , 54, 10, 285, "RAZ", 1, 1, 0, 0},
- {"ROUT3" , 0, 18, 286, "RO", 1, 0, 0, 0ull},
- {"ROUT4" , 18, 18, 286, "RO", 1, 0, 0, 0ull},
- {"ROUT5" , 36, 18, 286, "RO", 1, 0, 0, 0ull},
- {"RESERVED_54_63" , 54, 10, 286, "RAZ", 1, 1, 0, 0},
- {"ROUT6" , 0, 18, 287, "RO", 1, 0, 0, 0ull},
- {"RESERVED_18_23" , 18, 6, 287, "RAZ", 1, 1, 0, 0},
- {"TOOMANY" , 24, 1, 287, "RO", 1, 0, 0, 0ull},
- {"RESERVED_25_63" , 25, 39, 287, "RAZ", 1, 1, 0, 0},
- {"RBSF" , 0, 2, 288, "R/W", 0, 0, 0ull, 0ull},
- {"RBEN" , 2, 1, 288, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 288, "RAZ", 1, 1, 0, 0},
- {"START_BIST" , 0, 1, 289, "R/W", 0, 0, 0ull, 0ull},
- {"BISR_DIR" , 1, 1, 289, "R/W", 0, 0, 0ull, 0ull},
- {"BISR_HR" , 2, 1, 289, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 289, "RAZ", 1, 1, 0, 0},
- {"FAILED" , 8, 1, 289, "RO", 1, 0, 0, 0ull},
- {"BISR_DONE" , 9, 1, 289, "RO", 1, 0, 0, 0ull},
- {"RESERVED_10_63" , 10, 54, 289, "RAZ", 1, 1, 0, 0},
- {"CLKF" , 0, 7, 290, "R/W", 0, 1, 32ull, 0},
- {"RESET_N" , 7, 1, 290, "R/W", 0, 0, 0ull, 1ull},
- {"CPB" , 8, 3, 290, "R/W", 0, 0, 0ull, 1ull},
- {"CPS" , 11, 3, 290, "R/W", 0, 0, 0ull, 1ull},
- {"DIFFAMP" , 14, 4, 290, "R/W", 0, 0, 0ull, 1ull},
- {"HAB_PS_EN" , 18, 3, 290, "R/W", 0, 1, 5ull, 0},
- {"HAB_DIV_RESET" , 21, 1, 290, "R/W", 0, 0, 1ull, 0ull},
- {"DSP_PS_EN" , 22, 3, 290, "R/W", 0, 1, 4ull, 0},
- {"DSP_DIV_RESET" , 25, 1, 290, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_26_26" , 26, 1, 290, "RAZ", 1, 1, 0, 0},
- {"HABCLK_SEL" , 27, 1, 290, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 290, "RAZ", 1, 1, 0, 0},
- {"RESET" , 0, 1, 291, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 291, "RAZ", 1, 1, 0, 0},
- {"INV_PP_WA2" , 4, 1, 291, "R/W", 0, 0, 0ull, 0ull},
- {"INV_PP_RA2" , 5, 1, 291, "R/W", 0, 0, 0ull, 0ull},
- {"INV_RSL_WA2" , 6, 1, 291, "R/W", 0, 0, 0ull, 0ull},
- {"INV_RSL_RA2" , 7, 1, 291, "R/W", 0, 0, 0ull, 0ull},
- {"W_EMOD" , 8, 2, 291, "R/W", 0, 0, 0ull, 0ull},
- {"R_EMOD" , 10, 2, 291, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 291, "RAZ", 1, 1, 0, 0},
- {"RB_SBE" , 0, 1, 292, "R/W", 0, 0, 1ull, 1ull},
- {"RB_DBE" , 1, 1, 292, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 292, "RAZ", 1, 1, 0, 0},
- {"RB_SBE" , 0, 1, 293, "R/W1C", 0, 0, 0ull, 0ull},
- {"RB_DBE" , 1, 1, 293, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 293, "RAZ", 1, 1, 0, 0},
- {"GPO_N" , 0, 6, 294, "R/W", 0, 0, 24ull, 24ull},
- {"GPO_P" , 6, 6, 294, "R/W", 0, 0, 27ull, 27ull},
- {"RFIF_N" , 12, 6, 294, "R/W", 0, 0, 24ull, 24ull},
- {"RFIF_P" , 18, 6, 294, "R/W", 0, 0, 27ull, 27ull},
- {"RESERVED_24_63" , 24, 40, 294, "RAZ", 1, 1, 0, 0},
- {"LDC" , 0, 4, 295, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_7" , 4, 4, 295, "RAZ", 1, 1, 0, 0},
- {"STC" , 8, 2, 295, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_10_15" , 10, 6, 295, "RAZ", 1, 1, 0, 0},
- {"STD" , 16, 5, 295, "R/W", 0, 0, 31ull, 31ull},
- {"RESERVED_21_63" , 21, 43, 295, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 296, "RO", 0, 1, 0ull, 0},
- {"POOL" , 33, 5, 296, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 296, "RAZ", 1, 1, 0, 0},
- {"FDR" , 0, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"FFR" , 1, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"FPF1" , 2, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"FPF0" , 3, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"FRD" , 4, 1, 297, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 297, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 298, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 298, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 14, 1, 298, "R/W", 0, 0, 0ull, 0ull},
- {"USE_STT" , 15, 1, 298, "R/W", 0, 0, 0ull, 0ull},
- {"USE_LDT" , 16, 1, 298, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 17, 1, 298, "R/W", 0, 0, 0ull, 0ull},
- {"REQ_OFF" , 18, 1, 298, "R/W", 0, 0, 0ull, 0ull},
- {"RET_OFF" , 19, 1, 298, "R/W", 0, 0, 0ull, 0ull},
- {"FREE_EN" , 20, 1, 298, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_63" , 21, 43, 298, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 11, 299, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 11, 11, 299, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 299, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 11, 300, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 300, "RAZ", 1, 1, 0, 0},
- {"FPF_RD" , 0, 12, 301, "R/W", 0, 0, 64ull, 0ull},
- {"FPF_WR" , 12, 12, 301, "R/W", 0, 0, 196ull, 0ull},
- {"RESERVED_24_63" , 24, 40, 301, "RAZ", 1, 1, 0, 0},
- {"FPF_SIZ" , 0, 12, 302, "R/W", 0, 0, 256ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 302, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"RES_44" , 44, 5, 303, "R/W", 0, 0, 0ull, 0ull},
- {"PADDR_E" , 49, 1, 303, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_50_63" , 50, 14, 303, "RAZ", 1, 1, 0, 0},
- {"FED0_SBE" , 0, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED0_DBE" , 1, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_SBE" , 2, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FED1_DBE" , 3, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_UND" , 4, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_COFF" , 5, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q0_PERR" , 6, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_UND" , 7, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_COFF" , 8, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q1_PERR" , 9, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_UND" , 10, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_COFF" , 11, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q2_PERR" , 12, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_UND" , 13, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_COFF" , 14, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q3_PERR" , 15, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_UND" , 16, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_COFF" , 17, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q4_PERR" , 18, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_UND" , 19, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_COFF" , 20, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q5_PERR" , 21, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_UND" , 22, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_COFF" , 23, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q6_PERR" , 24, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_UND" , 25, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_COFF" , 26, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"Q7_PERR" , 27, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL0TH" , 28, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL1TH" , 29, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL2TH" , 30, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL3TH" , 31, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL4TH" , 32, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL5TH" , 33, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL6TH" , 34, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"POOL7TH" , 35, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE0" , 36, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE1" , 37, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE2" , 38, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE3" , 39, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE4" , 40, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE5" , 41, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE6" , 42, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"FREE7" , 43, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_44_48" , 44, 5, 304, "RAZ", 1, 1, 0, 0},
- {"PADDR_E" , 49, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_50_63" , 50, 14, 304, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 32, 305, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 305, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 306, "R/W", 0, 1, 8589934591ull, 0},
- {"RESERVED_33_63" , 33, 31, 306, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 33, 307, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 307, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 29, 308, "R/W", 0, 0, 536870911ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 308, "RAZ", 1, 1, 0, 0},
- {"QUE_SIZ" , 0, 29, 309, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 309, "RAZ", 1, 1, 0, 0},
- {"PG_NUM" , 0, 25, 310, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 310, "RAZ", 1, 1, 0, 0},
- {"ACT_INDX" , 0, 26, 311, "RO", 0, 1, 0ull, 0},
- {"ACT_QUE" , 26, 3, 311, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 311, "RO", 0, 0, 0ull, 7ull},
- {"EXP_INDX" , 0, 26, 312, "RO", 0, 1, 0ull, 0},
- {"EXP_QUE" , 26, 3, 312, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 312, "RO", 0, 0, 0ull, 7ull},
- {"THRESH" , 0, 32, 313, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 313, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 314, "RAZ", 1, 1, 0, 0},
- {"OUT_OVR" , 2, 4, 314, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_21" , 6, 16, 314, "RAZ", 1, 1, 0, 0},
- {"LOSTSTAT" , 22, 4, 314, "R/W1C", 0, 0, 0ull, 0ull},
- {"STATOVR" , 26, 1, 314, "R/W1C", 0, 0, 0ull, 0ull},
- {"INB_NXA" , 27, 4, 314, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 314, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 25, 315, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 315, "RAZ", 1, 1, 0, 0},
- {"CLK_EN" , 0, 1, 316, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 316, "RAZ", 1, 1, 0, 0},
- {"LOGL_EN" , 0, 16, 317, "R/W", 0, 1, 65535ull, 0},
- {"PHYS_EN" , 16, 1, 317, "R/W", 0, 1, 1ull, 0},
- {"HG2RX_EN" , 17, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"HG2TX_EN" , 18, 1, 317, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 317, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 1, 318, "RO", 0, 1, 0ull, 0},
- {"EN" , 1, 1, 318, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_3" , 2, 2, 318, "RAZ", 1, 1, 0, 0},
- {"MODE" , 4, 1, 318, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 318, "RAZ", 1, 1, 0, 0},
- {"SPEED" , 8, 4, 318, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 318, "RAZ", 1, 1, 0, 0},
- {"PRT" , 0, 6, 319, "RO", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 319, "RAZ", 1, 1, 0, 0},
- {"RX_EN" , 0, 1, 320, "R/W", 0, 0, 0ull, 0ull},
- {"TX_EN" , 1, 1, 320, "R/W", 0, 0, 0ull, 0ull},
- {"DRP_EN" , 2, 1, 320, "R/W", 0, 0, 0ull, 0ull},
- {"BCK_EN" , 3, 1, 320, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 320, "RAZ", 1, 1, 0, 0},
- {"PHYS_BP" , 16, 16, 320, "R/W", 0, 1, 65535ull, 0},
- {"LOGL_EN" , 32, 16, 320, "R/W", 0, 0, 255ull, 255ull},
- {"PHYS_EN" , 48, 16, 320, "R/W", 0, 0, 255ull, 255ull},
- {"EN" , 0, 1, 321, "R/W", 0, 1, 0ull, 0},
- {"SPEED" , 1, 1, 321, "R/W", 0, 1, 1ull, 0},
- {"DUPLEX" , 2, 1, 321, "R/W", 0, 1, 1ull, 0},
- {"SLOTTIME" , 3, 1, 321, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_4_7" , 4, 4, 321, "RAZ", 1, 1, 0, 0},
- {"SPEED_MSB" , 8, 1, 321, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 321, "RAZ", 1, 1, 0, 0},
- {"RX_IDLE" , 12, 1, 321, "RO", 0, 1, 1ull, 0},
- {"TX_IDLE" , 13, 1, 321, "RO", 0, 1, 1ull, 0},
- {"RESERVED_14_63" , 14, 50, 321, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 64, 322, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 323, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 324, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 325, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 326, "R/W", 0, 1, 0ull, 0},
- {"ADR" , 0, 64, 327, "R/W", 0, 1, 0ull, 0},
- {"EN" , 0, 32, 328, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 328, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 329, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 329, "RAZ", 1, 1, 0, 0},
- {"BCST" , 0, 1, 330, "R/W", 0, 1, 1ull, 0},
- {"MCST" , 1, 2, 330, "R/W", 0, 1, 0ull, 0},
- {"CAM_MODE" , 3, 1, 330, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_63" , 4, 60, 330, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 5, 331, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_5_63" , 5, 59, 331, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 332, "R/W", 0, 0, 1ull, 1ull},
- {"CAREXT" , 1, 1, 332, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_2" , 2, 1, 332, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 332, "R/W", 0, 0, 1ull, 1ull},
- {"FCSERR" , 4, 1, 332, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_6" , 5, 2, 332, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 332, "R/W", 0, 0, 1ull, 1ull},
- {"SKPERR" , 8, 1, 332, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 332, "RAZ", 1, 1, 0, 0},
- {"PRE_CHK" , 0, 1, 333, "R/W", 0, 0, 1ull, 1ull},
- {"PRE_STRP" , 1, 1, 333, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_DRP" , 2, 1, 333, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_BCK" , 3, 1, 333, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_MCST" , 4, 1, 333, "R/W", 0, 0, 1ull, 1ull},
- {"CTL_SMAC" , 5, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"PRE_FREE" , 6, 1, 333, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_8" , 7, 2, 333, "RAZ", 1, 1, 0, 0},
- {"PRE_ALIGN" , 9, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"NULL_DIS" , 10, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_11" , 11, 1, 333, "RAZ", 1, 1, 0, 0},
- {"PTP_MODE" , 12, 1, 333, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 333, "RAZ", 1, 1, 0, 0},
- {"IFG" , 0, 4, 334, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_4_63" , 4, 60, 334, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"CAREXT" , 1, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 335, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 335, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 335, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 335, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 335, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 335, "RAZ", 1, 1, 0, 0},
- {"MINERR" , 0, 1, 336, "R/W1C", 0, 1, 0ull, 0},
- {"CAREXT" , 1, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 336, "RAZ", 1, 1, 0, 0},
- {"JABBER" , 3, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCSERR" , 4, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 336, "RAZ", 1, 1, 0, 0},
- {"RCVERR" , 7, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPERR" , 8, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 336, "RAZ", 1, 1, 0, 0},
- {"OVRERR" , 10, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCTERR" , 11, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"RSVERR" , 12, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"FALERR" , 13, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"COLDET" , 14, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"IFGERR" , 15, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_18" , 16, 3, 336, "RAZ", 1, 1, 0, 0},
- {"PAUSE_DRP" , 19, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"LOC_FAULT" , 20, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"REM_FAULT" , 21, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_SEQ" , 22, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAD_TERM" , 23, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNSOP" , 24, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNEOP" , 25, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"UNDAT" , 26, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2FLD" , 27, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"HG2CC" , 28, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 336, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 337, "R/W", 0, 0, 10240ull, 10240ull},
- {"RESERVED_16_63" , 16, 48, 337, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 16, 338, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 338, "RAZ", 1, 1, 0, 0},
- {"RD_CLR" , 0, 1, 339, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 339, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 340, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 340, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 341, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 341, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 342, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 342, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 48, 343, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 343, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 344, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 344, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 345, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 345, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 346, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 346, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 347, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 347, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 348, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 348, "RAZ", 1, 1, 0, 0},
- {"LEN" , 0, 7, 349, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 349, "RAZ", 1, 1, 0, 0},
- {"FCSSEL" , 8, 1, 349, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 349, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 350, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_6_63" , 6, 58, 350, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 6, 351, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_6_63" , 6, 58, 351, "RAZ", 1, 1, 0, 0},
- {"MARK" , 0, 9, 352, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_9_63" , 9, 55, 352, "RAZ", 1, 1, 0, 0},
- {"LGTIM2GO" , 0, 16, 353, "RO", 0, 1, 0ull, 0},
- {"XOF" , 16, 16, 353, "RO", 0, 0, 0ull, 0ull},
- {"PHTIM2GO" , 32, 16, 353, "RO", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 353, "RAZ", 1, 1, 0, 0},
- {"COMMIT" , 0, 2, 354, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_15" , 2, 14, 354, "RAZ", 1, 1, 0, 0},
- {"DROP" , 16, 2, 354, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 354, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 3, 355, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_3_63" , 3, 61, 355, "RAZ", 1, 1, 0, 0},
- {"LANE_RXD" , 0, 32, 356, "RO", 0, 1, 0ull, 0},
- {"LANE_RXC" , 32, 4, 356, "RO", 0, 1, 0ull, 0},
- {"STATE" , 36, 3, 356, "RO", 0, 1, 0ull, 0},
- {"VAL" , 39, 1, 356, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 356, "RAZ", 1, 1, 0, 0},
- {"STATUS" , 0, 2, 357, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 357, "RAZ", 1, 1, 0, 0},
- {"SMAC" , 0, 48, 358, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 358, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 359, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP" , 16, 1, 359, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 359, "RAZ", 1, 1, 0, 0},
- {"WR_MAGIC" , 0, 1, 360, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 360, "RAZ", 1, 1, 0, 0},
- {"PREAMBLE" , 0, 1, 361, "R/W", 0, 0, 1ull, 1ull},
- {"PAD" , 1, 1, 361, "R/W", 0, 0, 1ull, 1ull},
- {"FCS" , 2, 1, 361, "R/W", 0, 0, 1ull, 1ull},
- {"FORCE_FCS" , 3, 1, 361, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_4_63" , 4, 60, 361, "RAZ", 1, 1, 0, 0},
- {"BURST" , 0, 16, 362, "R/W", 0, 0, 8192ull, 8192ull},
- {"RESERVED_16_63" , 16, 48, 362, "RAZ", 1, 1, 0, 0},
- {"XOFF" , 0, 16, 363, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 363, "RAZ", 1, 1, 0, 0},
- {"XON" , 0, 16, 364, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 364, "RAZ", 1, 1, 0, 0},
- {"XSCOL_EN" , 0, 1, 365, "R/W", 0, 0, 1ull, 1ull},
- {"XSDEF_EN" , 1, 1, 365, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_2_63" , 2, 62, 365, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 8, 366, "R/W", 0, 0, 59ull, 59ull},
- {"RESERVED_8_63" , 8, 56, 366, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 16, 367, "R/W", 0, 1, 16ull, 0},
- {"RESERVED_16_63" , 16, 48, 367, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 368, "R/W", 0, 1, 96ull, 0},
- {"RESERVED_16_63" , 16, 48, 368, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 369, "RO", 1, 1, 0, 0},
- {"MSG_TIME" , 16, 16, 369, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 369, "RAZ", 1, 1, 0, 0},
- {"SEND" , 0, 1, 370, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 370, "RAZ", 1, 1, 0, 0},
- {"ALIGN" , 0, 1, 371, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 371, "RAZ", 1, 1, 0, 0},
- {"SLOT" , 0, 10, 372, "R/W", 0, 0, 512ull, 512ull},
- {"RESERVED_10_63" , 10, 54, 372, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 16, 373, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 373, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 0, 32, 374, "RC/W", 0, 1, 0ull, 0},
- {"XSDEF" , 32, 32, 374, "RC/W", 0, 1, 0ull, 0},
- {"MCOL" , 0, 32, 375, "RC/W", 0, 1, 0ull, 0},
- {"SCOL" , 32, 32, 375, "RC/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 376, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 376, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 377, "RC/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 377, "RAZ", 1, 1, 0, 0},
- {"HIST0" , 0, 32, 378, "RC/W", 0, 1, 0ull, 0},
- {"HIST1" , 32, 32, 378, "RC/W", 0, 1, 0ull, 0},
- {"HIST2" , 0, 32, 379, "RC/W", 0, 1, 0ull, 0},
- {"HIST3" , 32, 32, 379, "RC/W", 0, 1, 0ull, 0},
- {"HIST4" , 0, 32, 380, "RC/W", 0, 1, 0ull, 0},
- {"HIST5" , 32, 32, 380, "RC/W", 0, 1, 0ull, 0},
- {"HIST6" , 0, 32, 381, "RC/W", 0, 1, 0ull, 0},
- {"HIST7" , 32, 32, 381, "RC/W", 0, 1, 0ull, 0},
- {"BCST" , 0, 32, 382, "RC/W", 0, 1, 0ull, 0},
- {"MCST" , 32, 32, 382, "RC/W", 0, 1, 0ull, 0},
- {"CTL" , 0, 32, 383, "RC/W", 0, 1, 0ull, 0},
- {"UNDFLW" , 32, 32, 383, "RC/W", 0, 1, 0ull, 0},
- {"RD_CLR" , 0, 1, 384, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 384, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 9, 385, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_9_63" , 9, 55, 385, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 2, 386, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 386, "RAZ", 1, 1, 0, 0},
- {"LIMIT" , 0, 5, 387, "R/W", 0, 0, 16ull, 16ull},
- {"RESERVED_5_63" , 5, 59, 387, "RAZ", 1, 1, 0, 0},
- {"CORRUPT" , 0, 2, 388, "R/W", 0, 0, 3ull, 3ull},
- {"RESERVED_2_63" , 2, 62, 388, "RAZ", 1, 1, 0, 0},
- {"TX_XOF" , 0, 16, 389, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 389, "RAZ", 1, 1, 0, 0},
- {"TX_XON" , 0, 16, 390, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 390, "RAZ", 1, 1, 0, 0},
- {"IFG1" , 0, 4, 391, "R/W", 0, 1, 8ull, 0},
- {"IFG2" , 4, 4, 391, "R/W", 0, 1, 4ull, 0},
- {"RESERVED_8_63" , 8, 56, 391, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 392, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 392, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 2, 392, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 392, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 392, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 392, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 392, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 392, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 392, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 392, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 392, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 392, "RAZ", 1, 1, 0, 0},
- {"XCHANGE" , 24, 1, 392, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 392, "RAZ", 1, 1, 0, 0},
- {"PKO_NXA" , 0, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 393, "RAZ", 0, 0, 0ull, 0ull},
- {"UNDFLW" , 2, 2, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 393, "RAZ", 1, 1, 0, 0},
- {"XSCOL" , 8, 2, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 393, "RAZ", 1, 1, 0, 0},
- {"XSDEF" , 12, 2, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 393, "RAZ", 1, 1, 0, 0},
- {"LATE_COL" , 16, 2, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 393, "RAZ", 1, 1, 0, 0},
- {"PTP_LOST" , 20, 2, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 393, "RAZ", 1, 1, 0, 0},
- {"XCHANGE" , 24, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 393, "RAZ", 1, 1, 0, 0},
- {"JAM" , 0, 8, 394, "R/W", 0, 1, 238ull, 0},
- {"RESERVED_8_63" , 8, 56, 394, "RAZ", 1, 1, 0, 0},
- {"LFSR" , 0, 16, 395, "R/W", 0, 1, 65535ull, 0},
- {"RESERVED_16_63" , 16, 48, 395, "RAZ", 1, 1, 0, 0},
- {"IGN_FULL" , 0, 2, 396, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 396, "RAZ", 1, 1, 0, 0},
- {"BP" , 4, 2, 396, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 396, "RAZ", 1, 1, 0, 0},
- {"EN" , 8, 2, 396, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_31" , 10, 22, 396, "RAZ", 1, 1, 0, 0},
- {"TX_PRT_BP" , 32, 16, 396, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 396, "RAZ", 1, 1, 0, 0},
- {"DMAC" , 0, 48, 397, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
- {"RESERVED_48_63" , 48, 16, 397, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 398, "R/W", 0, 0, 34824ull, 34824ull},
- {"RESERVED_16_63" , 16, 48, 398, "RAZ", 1, 1, 0, 0},
- {"PRTS" , 0, 5, 399, "R/W", 0, 1, 2ull, 0},
- {"RESERVED_5_63" , 5, 59, 399, "RAZ", 1, 1, 0, 0},
- {"DIC_EN" , 0, 1, 400, "R/W", 0, 0, 0ull, 1ull},
- {"UNI_EN" , 1, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 400, "RAZ", 1, 1, 0, 0},
- {"LS" , 4, 2, 400, "R/W", 0, 0, 0ull, 0ull},
- {"LS_BYP" , 6, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 400, "RAZ", 1, 1, 0, 0},
- {"HG_EN" , 8, 1, 400, "R/W", 0, 0, 0ull, 0ull},
- {"HG_PAUSE_HGI" , 9, 2, 400, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_11_63" , 11, 53, 400, "RAZ", 1, 1, 0, 0},
- {"THRESH" , 0, 4, 401, "R/W", 0, 0, 6ull, 6ull},
- {"EN" , 4, 1, 401, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 401, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 402, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 402, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 402, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 402, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCE_SEL" , 15, 2, 402, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 402, "RAZ", 1, 1, 0, 0},
- {"N" , 0, 32, 403, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 403, "RAZ", 1, 1, 0, 0},
- {"LANE_SEL" , 0, 2, 404, "R/W", 0, 0, 0ull, 0ull},
- {"DIV" , 2, 1, 404, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 404, "RAZ", 1, 1, 0, 0},
- {"QLM_SEL" , 8, 2, 404, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 404, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 16, 405, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 405, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 406, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 406, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 20, 407, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 407, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 20, 408, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 408, "RAZ", 1, 1, 0, 0},
- {"SET" , 0, 20, 409, "R/W1", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 409, "RAZ", 1, 1, 0, 0},
- {"TX_OE" , 0, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"RX_XOR" , 1, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"INT_EN" , 2, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"INT_TYPE" , 3, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_CNT" , 4, 4, 410, "R/W", 0, 0, 0ull, 0ull},
- {"FIL_SEL" , 8, 4, 410, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_SEL" , 12, 2, 410, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_GEN" , 14, 1, 410, "R/W", 0, 0, 0ull, 0ull},
- {"SYNCE_SEL" , 15, 2, 410, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 410, "RAZ", 1, 1, 0, 0},
- {"ICD" , 0, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"IBD" , 1, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"ICRP1" , 2, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"ICRP0" , 3, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"ICRN1" , 4, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"ICRN0" , 5, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ1" , 6, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"IBRQ0" , 7, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"ICNRT" , 8, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"IBR1" , 9, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"IBR0" , 10, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"IBDR1" , 11, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"IBDR0" , 12, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"ICNR0" , 13, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"ICNR1" , 14, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"ICR1" , 15, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"ICR0" , 16, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"ICNRCB" , 17, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"IOCFIF" , 18, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"RSDFIF" , 19, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"IORFIF" , 20, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"XMCFIF" , 21, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"XMDFIF" , 22, 1, 411, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 411, "RAZ", 1, 1, 0, 0},
- {"FAU_END" , 0, 1, 412, "R/W", 0, 0, 0ull, 0ull},
- {"DWB_ENB" , 1, 1, 412, "R/W", 0, 0, 1ull, 1ull},
- {"PKO_ENB" , 2, 1, 412, "R/W", 0, 0, 0ull, 0ull},
- {"INB_MAT" , 3, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"OUTB_MAT" , 4, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
- {"RR_MODE" , 5, 1, 412, "R/W", 0, 0, 0ull, 0ull},
- {"XMC_PER" , 6, 4, 412, "R/W", 0, 0, 0ull, 0ull},
- {"FIF_DLY" , 10, 1, 412, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_11_63" , 11, 53, 412, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 413, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 413, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 413, "RAZ", 1, 1, 0, 0},
- {"TOUT_VAL" , 0, 12, 414, "R/W", 0, 0, 4ull, 4ull},
- {"TOUT_ENB" , 12, 1, 414, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 414, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 415, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 415, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 415, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 416, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 416, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 416, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 416, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 416, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 8, 417, "R/W", 0, 1, 0ull, 0},
- {"DST" , 8, 9, 417, "R/W", 0, 1, 0ull, 0},
- {"OPC" , 17, 4, 417, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 21, 8, 417, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 417, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 418, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 419, "R/W", 0, 1, 0ull, 0},
- {"NP_SOP" , 0, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 420, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 420, "RAZ", 1, 1, 0, 0},
- {"NP_SOP" , 0, 1, 421, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_EOP" , 1, 1, 421, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_SOP" , 2, 1, 421, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_EOP" , 3, 1, 421, "R/W1C", 0, 0, 0ull, 0ull},
- {"NP_DAT" , 4, 1, 421, "R/W1C", 0, 0, 0ull, 0ull},
- {"P_DAT" , 5, 1, 421, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 421, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 422, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 422, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 422, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 423, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 423, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 423, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 424, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 424, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 424, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 425, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 425, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 425, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 425, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 425, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 9, 426, "R/W", 0, 1, 0ull, 0},
- {"DST" , 9, 8, 426, "R/W", 0, 1, 0ull, 0},
- {"EOT" , 17, 1, 426, "R/W", 0, 1, 0ull, 0},
- {"MASK" , 18, 8, 426, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_63" , 26, 38, 426, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 427, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 428, "R/W", 0, 1, 0ull, 0},
- {"CNT_VAL" , 0, 15, 429, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 429, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 429, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 430, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 430, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 430, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 15, 431, "R/W", 0, 0, 0ull, 0ull},
- {"CNT_ENB" , 15, 1, 431, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 431, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 6, 432, "RO", 0, 1, 0ull, 0},
- {"VPORT" , 6, 6, 432, "RO", 0, 1, 0ull, 0},
- {"RESERVED_12_63" , 12, 52, 432, "RAZ", 1, 1, 0, 0},
- {"NCB_WR" , 0, 3, 433, "R/W", 0, 1, 0ull, 0},
- {"NCB_RD" , 3, 3, 433, "R/W", 0, 1, 0ull, 0},
- {"PKO_RD" , 6, 3, 433, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_63" , 9, 55, 433, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 434, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 434, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 435, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 435, "RAZ", 1, 1, 0, 0},
- {"BACK" , 0, 4, 436, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 436, "RAZ", 1, 1, 0, 0},
- {"PWP" , 0, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"IPD_NEW" , 1, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"IPD_OLD" , 2, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PRC_OFF" , 3, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PWQ0" , 4, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PWQ1" , 5, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PBM_WORD" , 6, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PBM0" , 7, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PBM1" , 8, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PBM2" , 9, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PBM3" , 10, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE0" , 11, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"IPQ_PBE1" , 12, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_POW" , 13, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WP1" , 14, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"PWQ_WQED" , 15, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"CSR_NCMD" , 16, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"CSR_MEM" , 17, 1, 437, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 437, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 48, 438, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 438, "RAZ", 1, 1, 0, 0},
- {"CLK_CNT" , 0, 64, 439, "RO", 0, 0, 0ull, 0ull},
- {"IPD_EN" , 0, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"OPC_MODE" , 1, 2, 440, "R/W", 0, 0, 0ull, 0ull},
- {"PBP_EN" , 3, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"WQE_LEND" , 4, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_LEND" , 5, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"NADDBUF" , 6, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"ADDPKT" , 7, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 8, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"LEN_M8" , 9, 1, 440, "R/W", 0, 0, 0ull, 1ull},
- {"PKT_OFF" , 10, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"IPD_FULL" , 11, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_NABUF" , 12, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_APKT" , 13, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"NO_WPTR" , 14, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"CLKEN" , 15, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"RST_DONE" , 16, 1, 440, "RO", 0, 0, 1ull, 0ull},
- {"USE_SOP" , 17, 1, 440, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 440, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 441, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 441, "RAZ", 1, 1, 0, 0},
- {"PRC_PAR0" , 0, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR1" , 1, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR2" , 2, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRC_PAR3" , 3, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"BP_SUB" , 4, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"DC_OVR" , 5, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"CC_OVR" , 6, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"C_COLL" , 7, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"D_COLL" , 8, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"BC_OVR" , 9, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_ADD" , 10, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"PQ_SUB" , 11, 1, 442, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 442, "RAZ", 1, 1, 0, 0},
- {"SKIP_SZ" , 0, 6, 443, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 443, "RAZ", 1, 1, 0, 0},
- {"MB_SIZE" , 0, 12, 444, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_12_63" , 12, 52, 444, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 445, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 445, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 446, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 446, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 446, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 447, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 447, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 447, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 17, 448, "R/W", 0, 0, 0ull, 0ull},
- {"BP_ENB" , 17, 1, 448, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 448, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 449, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 449, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 450, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 450, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 451, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 451, "RAZ", 1, 1, 0, 0},
- {"CNT_VAL" , 0, 25, 452, "RO", 0, 1, 0ull, 0},
- {"RESERVED_25_63" , 25, 39, 452, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 453, "RO", 0, 1, 0ull, 0},
- {"WMARK" , 32, 32, 453, "R/W", 0, 1, 4294967295ull, 0},
- {"INTR" , 0, 64, 454, "R/W1C", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 64, 455, "R/W", 0, 0, 0ull, 1ull},
- {"RADDR" , 0, 3, 456, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 3, 1, 456, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 4, 29, 456, "RO", 1, 1, 0, 0},
- {"PRADDR" , 33, 3, 456, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 36, 3, 456, "RO", 0, 0, 5ull, 5ull},
- {"RESERVED_39_63" , 39, 25, 456, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 7, 457, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 7, 1, 457, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 8, 29, 457, "RO", 1, 1, 0, 0},
- {"MAX_PKT" , 37, 7, 457, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_44_63" , 44, 20, 457, "RAZ", 1, 1, 0, 0},
- {"WQE_PCNT" , 0, 7, 458, "RO", 0, 0, 0ull, 0ull},
- {"PKT_PCNT" , 7, 7, 458, "RO", 0, 0, 0ull, 0ull},
- {"PFIF_CNT" , 14, 3, 458, "RO", 0, 0, 0ull, 0ull},
- {"WQEV_CNT" , 17, 1, 458, "RO", 0, 0, 0ull, 0ull},
- {"PKTV_CNT" , 18, 1, 458, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 458, "RAZ", 1, 1, 0, 0},
- {"RADDR" , 0, 8, 459, "R/W", 0, 0, 0ull, 0ull},
- {"CENA" , 8, 1, 459, "R/W", 0, 0, 1ull, 1ull},
- {"PTR" , 9, 29, 459, "RO", 1, 1, 0, 0},
- {"PRADDR" , 38, 8, 459, "RO", 1, 1, 0, 0},
- {"WRADDR" , 46, 8, 459, "RO", 1, 1, 0, 0},
- {"MAX_CNTS" , 54, 7, 459, "RO", 0, 0, 64ull, 64ull},
- {"RESERVED_61_63" , 61, 3, 459, "RAZ", 1, 1, 0, 0},
- {"PASS" , 0, 32, 460, "R/W", 0, 1, 0ull, 0},
- {"DROP" , 32, 32, 460, "R/W", 0, 1, 0ull, 0},
- {"Q0_PCNT" , 0, 32, 461, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 461, "RAZ", 1, 1, 0, 0},
- {"PRT_ENB" , 0, 36, 462, "R/W", 0, 0, 0ull, 0ull},
- {"AVG_DLY" , 36, 14, 462, "R/W", 0, 1, 0ull, 0},
- {"PRB_DLY" , 50, 14, 462, "R/W", 0, 0, 0ull, 0ull},
- {"PRT_ENB" , 0, 12, 463, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 463, "RAZ", 1, 1, 0, 0},
- {"PRB_CON" , 0, 32, 464, "R/W", 0, 1, 0ull, 0},
- {"AVG_CON" , 32, 8, 464, "R/W", 0, 1, 0ull, 0},
- {"NEW_CON" , 40, 8, 464, "R/W", 0, 1, 0ull, 0},
- {"USE_PCNT" , 48, 1, 464, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 464, "RAZ", 1, 1, 0, 0},
- {"PAGE_CNT" , 0, 25, 465, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 25, 6, 465, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_31_63" , 31, 33, 465, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT" , 0, 32, 466, "R/W", 0, 0, 4294967295ull, 4294967295ull},
- {"RESERVED_32_35" , 32, 4, 466, "RAZ", 1, 1, 0, 0},
- {"PORT_BIT2" , 36, 4, 466, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_40_63" , 40, 24, 466, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 467, "R/W", 1, 0, 0, 0ull},
- {"PORT_QOS" , 32, 9, 467, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_41_63" , 41, 23, 467, "RAZ", 1, 1, 0, 0},
- {"WQE_POOL" , 0, 3, 468, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 468, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 29, 469, "RO", 1, 1, 0, 0},
- {"RESERVED_29_63" , 29, 35, 469, "RAZ", 1, 1, 0, 0},
- {"MEM0" , 0, 1, 470, "RO", 0, 0, 0ull, 0ull},
- {"MEM1" , 1, 1, 470, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 2, 1, 470, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 470, "RAZ", 1, 1, 0, 0},
- {"MEM0_ERR" , 0, 7, 471, "R/W", 0, 0, 0ull, 0ull},
- {"MEM1_ERR" , 7, 7, 471, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 471, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 472, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 472, "RAZ", 1, 1, 0, 0},
- {"KED0_SBE" , 0, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED0_DBE" , 1, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_SBE" , 2, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
- {"KED1_DBE" , 3, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 473, "RAZ", 1, 1, 0, 0},
- {"DISABLE" , 0, 1, 474, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_3" , 1, 3, 474, "RAZ", 1, 1, 0, 0},
- {"MAXDRAM" , 4, 4, 474, "R/W", 0, 0, 7ull, 7ull},
- {"RESERVED_8_63" , 8, 56, 474, "RAZ", 1, 1, 0, 0},
- {"TDFFL" , 0, 1, 475, "RO", 1, 0, 0, 0ull},
- {"RESERVED_1_3" , 1, 3, 475, "RAZ", 1, 1, 0, 0},
- {"VRTFL" , 4, 1, 475, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_7" , 5, 3, 475, "RAZ", 1, 1, 0, 0},
- {"DUTRESFL" , 8, 1, 475, "RO", 1, 0, 0, 0ull},
- {"RESERVED_9_11" , 9, 3, 475, "RAZ", 1, 1, 0, 0},
- {"IOCDATFL" , 12, 1, 475, "RO", 1, 0, 0, 0ull},
- {"RESERVED_13_15" , 13, 3, 475, "RAZ", 1, 1, 0, 0},
- {"IOCCMDFL" , 16, 1, 475, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 475, "RAZ", 1, 1, 0, 0},
- {"DUTFL" , 32, 4, 475, "RO", 1, 0, 0, 0ull},
- {"RESERVED_36_63" , 36, 28, 475, "RAZ", 1, 1, 0, 0},
- {"VBFFL" , 0, 4, 476, "RO", 1, 0, 0, 0ull},
- {"RDFFL" , 4, 1, 476, "RO", 1, 0, 0, 0ull},
- {"RESERVED_5_61" , 5, 57, 476, "RAZ", 1, 1, 0, 0},
- {"CLEAR_BIST" , 62, 1, 476, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 63, 1, 476, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFL" , 0, 8, 477, "RO", 1, 0, 0, 0ull},
- {"FBFFL" , 8, 8, 477, "RO", 1, 0, 0, 0ull},
- {"SBFFL" , 16, 8, 477, "RO", 1, 0, 0, 0ull},
- {"FBFRSPFL" , 24, 8, 477, "RO", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 477, "RAZ", 1, 1, 0, 0},
- {"TAGFL" , 0, 16, 478, "RO", 1, 0, 0, 0ull},
- {"LRUFL" , 16, 1, 478, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_63" , 17, 47, 478, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 479, "R/W", 1, 1, 0, 0},
- {"DISIDXALIAS" , 0, 1, 480, "R/W", 0, 0, 0ull, 0ull},
- {"DISECC" , 1, 1, 480, "R/W", 0, 0, 0ull, 0ull},
- {"VAB_THRESH" , 2, 4, 480, "R/W", 0, 0, 0ull, 0ull},
- {"EF_CNT" , 6, 7, 480, "R/W", 0, 0, 0ull, 4ull},
- {"EF_ENA" , 13, 1, 480, "R/W", 0, 0, 0ull, 1ull},
- {"XMC_ARB_MODE" , 14, 1, 480, "R/W", 0, 0, 0ull, 0ull},
- {"RSP_ARB_MODE" , 15, 1, 480, "R/W", 0, 0, 0ull, 0ull},
- {"MAXLFB" , 16, 4, 480, "R/W", 0, 0, 0ull, 0ull},
- {"MAXVAB" , 20, 4, 480, "R/W", 0, 0, 0ull, 0ull},
- {"DISCCLK" , 24, 1, 480, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFDBE" , 25, 1, 480, "R/W", 0, 0, 0ull, 0ull},
- {"L2DFSBE" , 26, 1, 480, "R/W", 0, 0, 0ull, 0ull},
- {"DISSTGL2I" , 27, 1, 480, "R/W", 0, 0, 0ull, 0ull},
- {"RDF_FAST" , 28, 1, 480, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_29_63" , 29, 35, 480, "RAZ", 1, 1, 0, 0},
- {"VALID" , 0, 1, 481, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_9" , 1, 9, 481, "RAZ", 1, 1, 0, 0},
- {"TAG" , 10, 28, 481, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 481, "RAZ", 1, 1, 0, 0},
- {"TYPE" , 0, 2, 482, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 482, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 4, 16, 482, "RO", 1, 0, 0, 0ull},
- {"RESERVED_20_49" , 20, 30, 482, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 10, 482, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 482, "R/W1C", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 482, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 482, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 482, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 483, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_6" , 2, 5, 483, "RAZ", 1, 1, 0, 0},
- {"WAYIDX" , 7, 13, 483, "RO", 1, 0, 0, 0ull},
- {"RESERVED_20_49" , 20, 30, 483, "RAZ", 1, 1, 0, 0},
- {"SYN" , 50, 6, 483, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_56_60" , 56, 5, 483, "RAZ", 1, 1, 0, 0},
- {"NOWAY" , 61, 1, 483, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE" , 62, 1, 483, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 63, 1, 483, "R/W1C", 0, 0, 0ull, 0ull},
- {"TYPE" , 0, 2, 484, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_49" , 2, 48, 484, "RAZ", 1, 1, 0, 0},
- {"VSYN" , 50, 10, 484, "RO", 0, 0, 0ull, 0ull},
- {"VSBE" , 60, 1, 484, "RO", 0, 0, 0ull, 0ull},
- {"VDBE" , 61, 1, 484, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_62_63" , 62, 2, 484, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 38, 485, "RO", 0, 1, 0ull, 0},
- {"RESERVED_38_47" , 38, 10, 485, "RAZ", 1, 1, 0, 0},
- {"SID" , 48, 4, 485, "RO", 0, 1, 0ull, 0},
- {"RESERVED_52_57" , 52, 6, 485, "RAZ", 1, 1, 0, 0},
- {"CMD" , 58, 6, 485, "RO", 0, 1, 0ull, 0},
- {"HOLERD" , 0, 1, 486, "R/W", 0, 0, 0ull, 1ull},
- {"HOLEWR" , 1, 1, 486, "R/W", 0, 0, 0ull, 1ull},
- {"VRTWR" , 2, 1, 486, "R/W", 0, 0, 0ull, 1ull},
- {"VRTIDRNG" , 3, 1, 486, "R/W", 0, 0, 0ull, 1ull},
- {"VRTADRNG" , 4, 1, 486, "R/W", 0, 0, 0ull, 1ull},
- {"VRTPE" , 5, 1, 486, "R/W", 0, 0, 0ull, 1ull},
- {"BIGWR" , 6, 1, 486, "R/W", 0, 0, 0ull, 1ull},
- {"BIGRD" , 7, 1, 486, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 486, "RAZ", 1, 1, 0, 0},
- {"HOLERD" , 0, 1, 487, "R/W1C", 0, 0, 0ull, 0ull},
- {"HOLEWR" , 1, 1, 487, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTWR" , 2, 1, 487, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTIDRNG" , 3, 1, 487, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTADRNG" , 4, 1, 487, "R/W1C", 0, 0, 0ull, 0ull},
- {"VRTPE" , 5, 1, 487, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGWR" , 6, 1, 487, "R/W1C", 0, 0, 0ull, 0ull},
- {"BIGRD" , 7, 1, 487, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 487, "RAZ", 1, 1, 0, 0},
- {"TAD0" , 16, 1, 487, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 487, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 488, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 489, "R/W", 0, 1, 0ull, 0},
- {"LVL" , 0, 2, 490, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_3" , 2, 2, 490, "RAZ", 1, 1, 0, 0},
- {"DWBLVL" , 4, 2, 490, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 490, "RAZ", 1, 1, 0, 0},
- {"LVL" , 0, 2, 491, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 491, "RAZ", 1, 1, 0, 0},
- {"WGT0" , 0, 8, 492, "R/W", 0, 0, 255ull, 255ull},
- {"WGT1" , 8, 8, 492, "R/W", 0, 0, 255ull, 255ull},
- {"WGT2" , 16, 8, 492, "R/W", 0, 0, 255ull, 255ull},
- {"WGT3" , 24, 8, 492, "R/W", 0, 0, 255ull, 255ull},
- {"RESERVED_32_63" , 32, 32, 492, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 493, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 494, "R/W", 0, 1, 0ull, 0},
- {"OW0ECC" , 0, 10, 495, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 495, "RAZ", 1, 1, 0, 0},
- {"OW1ECC" , 16, 10, 495, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 495, "RAZ", 1, 1, 0, 0},
- {"OW2ECC" , 32, 10, 495, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 495, "RAZ", 1, 1, 0, 0},
- {"OW3ECC" , 48, 10, 495, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 495, "RAZ", 1, 1, 0, 0},
- {"OW4ECC" , 0, 10, 496, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 496, "RAZ", 1, 1, 0, 0},
- {"OW5ECC" , 16, 10, 496, "RO", 0, 1, 0ull, 0},
- {"RESERVED_26_31" , 26, 6, 496, "RAZ", 1, 1, 0, 0},
- {"OW6ECC" , 32, 10, 496, "RO", 0, 1, 0ull, 0},
- {"RESERVED_42_47" , 42, 6, 496, "RAZ", 1, 1, 0, 0},
- {"OW7ECC" , 48, 10, 496, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 496, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 497, "R/W", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 497, "R/W", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 497, "R/W", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 497, "R/W", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 497, "R/W", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 497, "R/W", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 497, "R/W", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 497, "R/W", 0, 0, 0ull, 1ull},
- {"WRDISLMC" , 8, 1, 497, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_9_63" , 9, 55, 497, "RAZ", 1, 1, 0, 0},
- {"L2DSBE" , 0, 1, 498, "R/W1C", 0, 0, 0ull, 1ull},
- {"L2DDBE" , 1, 1, 498, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGSBE" , 2, 1, 498, "R/W1C", 0, 0, 0ull, 1ull},
- {"TAGDBE" , 3, 1, 498, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFSBE" , 4, 1, 498, "R/W1C", 0, 0, 0ull, 1ull},
- {"VBFDBE" , 5, 1, 498, "R/W1C", 0, 0, 0ull, 1ull},
- {"NOWAY" , 6, 1, 498, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDDISLMC" , 7, 1, 498, "R/W1C", 0, 0, 0ull, 0ull},
- {"WRDISLMC" , 8, 1, 498, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 498, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 499, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 500, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 501, "R/W", 0, 1, 0ull, 0},
- {"COUNT" , 0, 64, 502, "R/W", 0, 1, 0ull, 0},
- {"CNT0SEL" , 0, 8, 503, "R/W", 0, 0, 0ull, 1ull},
- {"CNT1SEL" , 8, 8, 503, "R/W", 0, 0, 0ull, 1ull},
- {"CNT2SEL" , 16, 8, 503, "R/W", 0, 0, 0ull, 1ull},
- {"CNT3SEL" , 24, 8, 503, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 503, "RAZ", 1, 1, 0, 0},
- {"LOCK" , 0, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"DIRTY" , 1, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"VALID" , 2, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"USE" , 3, 1, 504, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_16" , 4, 13, 504, "RAZ", 1, 1, 0, 0},
- {"TAG" , 17, 19, 504, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_39" , 36, 4, 504, "RAZ", 1, 1, 0, 0},
- {"ECC" , 40, 6, 504, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_63" , 46, 18, 504, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 505, "R/W1C", 0, 0, 0ull, 0ull},
- {"MASK" , 0, 1, 506, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 506, "RAZ", 1, 1, 0, 0},
- {"DWB" , 0, 1, 507, "R/W1C", 0, 0, 0ull, 0ull},
- {"INVL2" , 1, 1, 507, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 507, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 4, 508, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 508, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 509, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 509, "RAZ", 1, 1, 0, 0},
- {"DWBID" , 8, 6, 509, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 509, "RAZ", 1, 1, 0, 0},
- {"ID" , 0, 6, 510, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 510, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 511, "R/W", 0, 0, 0ull, 1ull},
- {"NUMID" , 1, 3, 511, "R/W", 0, 0, 5ull, 5ull},
- {"MEMSZ" , 4, 3, 511, "R/W", 0, 0, 5ull, 5ull},
- {"RESERVED_7_7" , 7, 1, 511, "RAZ", 1, 1, 0, 0},
- {"OOBERR" , 8, 1, 511, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 511, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 32, 512, "R/W", 0, 0, 0ull, 0ull},
- {"PARITY" , 32, 4, 512, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 512, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 513, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 513, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 514, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 514, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 64, 515, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 38, 516, "R/W", 1, 1, 0, 0},
- {"RESERVED_38_56" , 38, 19, 516, "RAZ", 1, 1, 0, 0},
- {"CMD" , 57, 6, 516, "R/W", 1, 1, 0, 0},
- {"INUSE" , 63, 1, 516, "RO", 0, 0, 0ull, 0ull},
- {"COUNT" , 0, 64, 517, "R/W", 0, 1, 0ull, 0},
- {"PRBS" , 0, 32, 518, "R/W", 1, 1, 0, 0},
- {"PROG" , 32, 8, 518, "R/W", 1, 1, 0, 0},
- {"SEL" , 40, 1, 518, "R/W", 1, 1, 0, 0},
- {"EN" , 41, 1, 518, "R/W", 1, 1, 0, 0},
- {"SKEW_ON" , 42, 1, 518, "R/W", 1, 1, 0, 0},
- {"DR" , 43, 1, 518, "R/W", 1, 1, 0, 0},
- {"RESERVED_44_63" , 44, 20, 518, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 519, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 520, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 520, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 521, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 8, 522, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 522, "R/W", 1, 1, 0, 0},
- {"CKE_MASK" , 0, 2, 523, "R/W", 1, 1, 0, 0},
- {"CS0_N_MASK" , 2, 2, 523, "R/W", 1, 1, 0, 0},
- {"CS1_N_MASK" , 4, 2, 523, "R/W", 1, 1, 0, 0},
- {"ODT0_MASK" , 6, 2, 523, "R/W", 1, 1, 0, 0},
- {"ODT1_MASK" , 8, 2, 523, "R/W", 1, 1, 0, 0},
- {"RAS_N_MASK" , 10, 1, 523, "R/W", 1, 1, 0, 0},
- {"CAS_N_MASK" , 11, 1, 523, "R/W", 1, 1, 0, 0},
- {"WE_N_MASK" , 12, 1, 523, "R/W", 1, 1, 0, 0},
- {"BA_MASK" , 13, 3, 523, "R/W", 1, 1, 0, 0},
- {"A_MASK" , 16, 16, 523, "R/W", 1, 1, 0, 0},
- {"RESET_N_MASK" , 32, 1, 523, "R/W", 1, 1, 0, 0},
- {"RESERVED_33_63" , 33, 31, 523, "R/W", 1, 1, 0, 0},
- {"DQX_CTL" , 0, 4, 524, "R/W", 0, 1, 4ull, 0},
- {"CK_CTL" , 4, 4, 524, "R/W", 0, 1, 4ull, 0},
- {"CMD_CTL" , 8, 4, 524, "R/W", 0, 1, 4ull, 0},
- {"RODT_CTL" , 12, 4, 524, "R/W", 0, 1, 0ull, 0},
- {"NTUNE" , 16, 4, 524, "R/W", 0, 1, 0ull, 0},
- {"PTUNE" , 20, 4, 524, "R/W", 0, 1, 0ull, 0},
- {"BYP" , 24, 1, 524, "R/W", 0, 1, 0ull, 0},
- {"M180" , 25, 1, 524, "R/W", 0, 1, 0ull, 0},
- {"DDR__NTUNE" , 26, 4, 524, "RO", 1, 1, 0, 0},
- {"DDR__PTUNE" , 30, 4, 524, "RO", 1, 1, 0, 0},
- {"RESERVED_34_63" , 34, 30, 524, "RAZ", 1, 1, 0, 0},
- {"INIT_START" , 0, 1, 525, "WR0", 0, 0, 0ull, 0ull},
- {"ECC_ENA" , 1, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"ROW_LSB" , 2, 3, 525, "R/W", 0, 1, 3ull, 0},
- {"PBANK_LSB" , 5, 4, 525, "R/W", 0, 1, 5ull, 0},
- {"IDLEPOWER" , 9, 3, 525, "R/W", 0, 0, 0ull, 6ull},
- {"FORCEWRITE" , 12, 4, 525, "R/W", 0, 0, 0ull, 0ull},
- {"ECC_ADR" , 16, 1, 525, "R/W", 0, 0, 0ull, 1ull},
- {"RESET" , 17, 1, 525, "R/W", 0, 1, 0ull, 0},
- {"REF_ZQCS_INT" , 18, 19, 525, "R/W", 1, 1, 0, 0},
- {"SEQUENCE" , 37, 3, 525, "R/W", 0, 0, 0ull, 0ull},
- {"EARLY_DQX" , 40, 1, 525, "R/W", 0, 0, 0ull, 0ull},
- {"SREF_WITH_DLL" , 41, 1, 525, "R/W", 0, 0, 0ull, 0ull},
- {"RANK_ENA" , 42, 1, 525, "R/W", 0, 1, 0ull, 0},
- {"RANKMASK" , 43, 4, 525, "R/W", 0, 1, 0ull, 0},
- {"MIRRMASK" , 47, 4, 525, "R/W", 0, 1, 0ull, 0},
- {"INIT_STATUS" , 51, 4, 525, "R/W1", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R0" , 55, 1, 525, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D0_R1" , 56, 1, 525, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R0" , 57, 1, 525, "R/W", 0, 1, 0ull, 0},
- {"EARLY_UNLOAD_D1_R1" , 58, 1, 525, "R/W", 0, 1, 0ull, 0},
- {"SCRZ" , 59, 1, 525, "R/W1", 0, 1, 0ull, 0},
- {"MODE32B" , 60, 1, 525, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 525, "RAZ", 1, 1, 0, 0},
- {"RDIMM_ENA" , 0, 1, 526, "R/W", 0, 1, 0ull, 0},
- {"BWCNT" , 1, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"DDR2T" , 2, 1, 526, "R/W", 0, 0, 0ull, 1ull},
- {"POCAS" , 3, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"FPRCH2" , 4, 2, 526, "R/W", 0, 0, 0ull, 1ull},
- {"THROTTLE_RD" , 6, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"THROTTLE_WR" , 7, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_RD" , 8, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"INORDER_WR" , 9, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"ELEV_PRIO_DIS" , 10, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"NXM_WRITE_EN" , 11, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_WRITE_BATCH" , 12, 4, 526, "R/W", 0, 0, 8ull, 8ull},
- {"XOR_BANK" , 16, 1, 526, "R/W", 0, 0, 0ull, 1ull},
- {"AUTO_DCLKDIS" , 17, 1, 526, "R/W", 0, 0, 0ull, 1ull},
- {"INT_ZQCS_DIS" , 18, 1, 526, "R/W", 0, 0, 1ull, 0ull},
- {"EXT_ZQCS_DIS" , 19, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"BPRCH" , 20, 2, 526, "R/W", 0, 0, 0ull, 0ull},
- {"WODT_BPRCH" , 22, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_BPRCH" , 23, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_62" , 24, 39, 526, "RAZ", 1, 1, 0, 0},
- {"SCRAMBLE_ENA" , 63, 1, 526, "R/W", 0, 0, 0ull, 0ull},
- {"DCLKCNT" , 0, 64, 527, "RO", 0, 1, 0ull, 0},
- {"CLKF" , 0, 7, 528, "R/W", 0, 1, 48ull, 0},
- {"RESET_N" , 7, 1, 528, "R/W", 0, 0, 0ull, 1ull},
- {"CPB" , 8, 3, 528, "R/W", 0, 0, 0ull, 1ull},
- {"CPS" , 11, 3, 528, "R/W", 0, 0, 0ull, 1ull},
- {"DIFFAMP" , 14, 4, 528, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_PS_EN" , 18, 3, 528, "R/W", 0, 1, 2ull, 0},
- {"DDR_DIV_RESET" , 21, 1, 528, "R/W", 0, 0, 1ull, 0ull},
- {"DFM_PS_EN" , 22, 3, 528, "R/W", 0, 1, 2ull, 0},
- {"DFM_DIV_RESET" , 25, 1, 528, "R/W", 0, 0, 1ull, 0ull},
- {"JTG_TEST_MODE" , 26, 1, 528, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_27_63" , 27, 37, 528, "RAZ", 1, 1, 0, 0},
- {"RC0" , 0, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC1" , 4, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC2" , 8, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC3" , 12, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC4" , 16, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC5" , 20, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC6" , 24, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC7" , 28, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC8" , 32, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC9" , 36, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC10" , 40, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC11" , 44, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC12" , 48, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC13" , 52, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC14" , 56, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"RC15" , 60, 4, 529, "R/W", 0, 0, 0ull, 0ull},
- {"DIMM0_WMASK" , 0, 16, 530, "R/W", 0, 0, 65535ull, 65535ull},
- {"DIMM1_WMASK" , 16, 16, 530, "R/W", 0, 0, 65535ull, 65535ull},
- {"TCWS" , 32, 13, 530, "R/W", 0, 0, 1248ull, 1248ull},
- {"PARITY" , 45, 1, 530, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_46_63" , 46, 18, 530, "RAZ", 1, 1, 0, 0},
- {"BYP_SETTING" , 0, 8, 531, "R/W", 0, 0, 0ull, 0ull},
- {"BYP_SEL" , 8, 4, 531, "R/W", 0, 0, 0ull, 0ull},
- {"QUAD_DLL_ENA" , 12, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"DRESET" , 13, 1, 531, "R/W", 0, 0, 1ull, 0ull},
- {"DLL_BRINGUP" , 14, 1, 531, "R/W", 0, 0, 0ull, 0ull},
- {"INTF_EN" , 15, 1, 531, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 531, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 532, "R/W", 0, 0, 0ull, 0ull},
- {"BYTE_SEL" , 6, 4, 532, "R/W", 0, 0, 0ull, 0ull},
- {"MODE_SEL" , 10, 2, 532, "R/W", 0, 0, 0ull, 0ull},
- {"LOAD_OFFSET" , 12, 1, 532, "WR0", 0, 0, 0ull, 0ull},
- {"OFFSET_ENA" , 13, 1, 532, "R/W", 0, 0, 0ull, 0ull},
- {"DLL90_BYTE_SEL" , 14, 4, 532, "R/W", 0, 0, 1ull, 1ull},
- {"DLL_MODE" , 18, 1, 532, "R/W", 0, 0, 0ull, 0ull},
- {"FINE_TUNE_MODE" , 19, 1, 532, "R/W", 0, 0, 0ull, 1ull},
- {"DLL90_SETTING" , 20, 8, 532, "RO", 1, 1, 0, 0},
- {"DLL_FAST" , 28, 1, 532, "RO", 1, 1, 0, 0},
- {"DCLK90_BYP_SETTING" , 29, 8, 532, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_BYP_SEL" , 37, 1, 532, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_RECAL_DIS" , 38, 1, 532, "R/W", 0, 0, 0ull, 1ull},
- {"DDR_90_DLY_BYP" , 39, 1, 532, "R/W", 0, 0, 0ull, 0ull},
- {"DCLK90_FWD" , 40, 1, 532, "WR0", 0, 0, 0ull, 0ull},
- {"RESERVED_41_63" , 41, 23, 532, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 533, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_15" , 8, 8, 533, "RAZ", 1, 1, 0, 0},
- {"ROW_LSB" , 16, 3, 533, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_19_63" , 19, 45, 533, "RAZ", 1, 1, 0, 0},
- {"MRDSYN0" , 0, 8, 534, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN1" , 8, 8, 534, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN2" , 16, 8, 534, "RO", 0, 0, 0ull, 0ull},
- {"MRDSYN3" , 24, 8, 534, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 534, "RAZ", 1, 1, 0, 0},
- {"FCOL" , 0, 14, 535, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 14, 16, 535, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 30, 3, 535, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 33, 1, 535, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 34, 2, 535, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 535, "RAZ", 1, 1, 0, 0},
- {"IFBCNT" , 0, 64, 536, "RO", 0, 1, 1ull, 0},
- {"NXM_WR_ERR" , 0, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"SEC_ERR" , 1, 4, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"DED_ERR" , 5, 4, 537, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 537, "RAZ", 1, 1, 0, 0},
- {"INTR_NXM_WR_ENA" , 0, 1, 538, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_SEC_ENA" , 1, 1, 538, "R/W", 0, 0, 0ull, 1ull},
- {"INTR_DED_ENA" , 2, 1, 538, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_3_63" , 3, 61, 538, "RAZ", 1, 1, 0, 0},
- {"CWL" , 0, 3, 539, "R/W", 0, 0, 0ull, 0ull},
- {"MPRLOC" , 3, 2, 539, "R/W", 0, 0, 0ull, 0ull},
- {"MPR" , 5, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"DLL" , 6, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"AL" , 7, 2, 539, "R/W", 0, 0, 0ull, 0ull},
- {"WLEV" , 9, 1, 539, "RO", 0, 0, 0ull, 0ull},
- {"TDQS" , 10, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"QOFF" , 11, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"BL" , 12, 2, 539, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 14, 4, 539, "R/W", 0, 0, 2ull, 2ull},
- {"RBT" , 18, 1, 539, "RO", 0, 0, 1ull, 1ull},
- {"TM" , 19, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"DLLR" , 20, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"WRP" , 21, 3, 539, "R/W", 0, 0, 0ull, 0ull},
- {"PPD" , 24, 1, 539, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 539, "RAZ", 1, 1, 0, 0},
- {"PASR_00" , 0, 3, 540, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_00" , 3, 1, 540, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_00" , 4, 1, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_00" , 5, 2, 540, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_00" , 7, 2, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_00" , 9, 3, 540, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_01" , 12, 3, 540, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_01" , 15, 1, 540, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_01" , 16, 1, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_01" , 17, 2, 540, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_01" , 19, 2, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_01" , 21, 3, 540, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_10" , 24, 3, 540, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_10" , 27, 1, 540, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_10" , 28, 1, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_10" , 29, 2, 540, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_10" , 31, 2, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_10" , 33, 3, 540, "R/W", 0, 0, 0ull, 0ull},
- {"PASR_11" , 36, 3, 540, "R/W", 0, 0, 0ull, 0ull},
- {"ASR_11" , 39, 1, 540, "R/W", 0, 0, 0ull, 0ull},
- {"SRT_11" , 40, 1, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_WR_11" , 41, 2, 540, "R/W", 0, 0, 0ull, 0ull},
- {"DIC_11" , 43, 2, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RTT_NOM_11" , 45, 3, 540, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 540, "RAZ", 1, 1, 0, 0},
- {"CS_MASK" , 0, 8, 541, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R0" , 8, 4, 541, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D0_R1" , 12, 4, 541, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R0" , 16, 4, 541, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D1_R1" , 20, 4, 541, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R0" , 24, 4, 541, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D2_R1" , 28, 4, 541, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R0" , 32, 4, 541, "R/W", 0, 1, 0ull, 0},
- {"MEM_MSB_D3_R1" , 36, 4, 541, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 541, "RAZ", 1, 1, 0, 0},
- {"OPSCNT" , 0, 64, 542, "RO", 0, 1, 1ull, 0},
- {"TS_STAGGER" , 0, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK_POS" , 1, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"LOOPBACK" , 2, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT0" , 3, 4, 543, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE0" , 7, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"CK_DLYOUT1" , 8, 4, 543, "R/W", 0, 1, 0ull, 0},
- {"CK_TUNE1" , 12, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"LV_MODE" , 13, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"RX_ALWAYS_ON" , 14, 1, 543, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_63" , 15, 49, 543, "RAZ", 1, 1, 0, 0},
- {"DDR3RST" , 0, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PWARM" , 1, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSOFT" , 2, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"DDR3PSV" , 3, 1, 544, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 544, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 545, "R/W", 0, 1, 0ull, 0},
- {"OFFSET" , 4, 4, 545, "R/W", 0, 0, 2ull, 2ull},
- {"OFFSET_EN" , 8, 1, 545, "R/W", 0, 0, 1ull, 1ull},
- {"OR_DIS" , 9, 1, 545, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 10, 8, 545, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_0" , 18, 1, 545, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_1" , 19, 1, 545, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_2" , 20, 1, 545, "R/W", 0, 0, 0ull, 0ull},
- {"DELAY_UNLOAD_3" , 21, 1, 545, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 545, "RAZ", 1, 1, 0, 0},
- {"BITMASK" , 0, 64, 546, "RO", 0, 0, 0ull, 0ull},
- {"BYTE0" , 0, 6, 547, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 6, 6, 547, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 12, 6, 547, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 18, 6, 547, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 24, 6, 547, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 30, 6, 547, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 36, 6, 547, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 42, 6, 547, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 48, 6, 547, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 54, 2, 547, "RO", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 547, "RAZ", 1, 1, 0, 0},
- {"RODT_D0_R0" , 0, 8, 548, "R/W", 0, 1, 0ull, 0},
- {"RODT_D0_R1" , 8, 8, 548, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R0" , 16, 8, 548, "R/W", 0, 1, 0ull, 0},
- {"RODT_D1_R1" , 24, 8, 548, "R/W", 0, 1, 0ull, 0},
- {"RODT_D2_R0" , 32, 8, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D2_R1" , 40, 8, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R0" , 48, 8, 548, "R/W", 0, 0, 0ull, 0ull},
- {"RODT_D3_R1" , 56, 8, 548, "R/W", 0, 0, 0ull, 0ull},
- {"KEY" , 0, 64, 549, "R/W", 0, 1, 0ull, 0},
- {"KEY" , 0, 64, 550, "R/W", 0, 1, 0ull, 0},
- {"FCOL" , 0, 14, 551, "RO", 0, 0, 0ull, 0ull},
- {"FROW" , 14, 16, 551, "RO", 0, 0, 0ull, 0ull},
- {"FBANK" , 30, 3, 551, "RO", 0, 0, 0ull, 0ull},
- {"FBUNK" , 33, 1, 551, "RO", 0, 0, 0ull, 0ull},
- {"FDIMM" , 34, 2, 551, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_36_63" , 36, 28, 551, "RAZ", 1, 1, 0, 0},
- {"R2R_INIT" , 0, 6, 552, "R/W", 0, 1, 1ull, 0},
- {"R2W_INIT" , 6, 6, 552, "R/W", 0, 1, 6ull, 0},
- {"W2R_INIT" , 12, 6, 552, "R/W", 0, 1, 9ull, 0},
- {"W2W_INIT" , 18, 6, 552, "R/W", 0, 1, 1ull, 0},
- {"RESERVED_24_63" , 24, 40, 552, "RAZ", 1, 1, 0, 0},
- {"R2R_XRANK_INIT" , 0, 6, 553, "R/W", 0, 1, 3ull, 0},
- {"R2W_XRANK_INIT" , 6, 6, 553, "R/W", 0, 1, 6ull, 0},
- {"W2R_XRANK_INIT" , 12, 6, 553, "R/W", 0, 1, 4ull, 0},
- {"W2W_XRANK_INIT" , 18, 6, 553, "R/W", 0, 1, 5ull, 0},
- {"RESERVED_24_63" , 24, 40, 553, "RAZ", 1, 1, 0, 0},
- {"R2R_XDIMM_INIT" , 0, 6, 554, "R/W", 0, 1, 4ull, 0},
- {"R2W_XDIMM_INIT" , 6, 6, 554, "R/W", 0, 1, 7ull, 0},
- {"W2R_XDIMM_INIT" , 12, 6, 554, "R/W", 0, 1, 4ull, 0},
- {"W2W_XDIMM_INIT" , 18, 6, 554, "R/W", 0, 1, 6ull, 0},
- {"RESERVED_24_63" , 24, 40, 554, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_9" , 0, 10, 555, "RAZ", 1, 1, 0, 0},
- {"TZQCS" , 10, 4, 555, "R/W", 0, 0, 4ull, 4ull},
- {"TCKE" , 14, 4, 555, "R/W", 0, 0, 3ull, 3ull},
- {"TXPR" , 18, 4, 555, "R/W", 0, 0, 5ull, 5ull},
- {"TMRD" , 22, 4, 555, "R/W", 0, 0, 4ull, 4ull},
- {"TMOD" , 26, 4, 555, "R/W", 0, 0, 12ull, 12ull},
- {"TDLLK" , 30, 4, 555, "R/W", 0, 0, 2ull, 2ull},
- {"TZQINIT" , 34, 4, 555, "R/W", 0, 0, 2ull, 2ull},
- {"TRP" , 38, 4, 555, "R/W", 0, 0, 6ull, 6ull},
- {"TCKSRE" , 42, 4, 555, "R/W", 0, 0, 5ull, 5ull},
- {"TRP_EXT" , 46, 1, 555, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 555, "RAZ", 1, 1, 0, 0},
- {"TMPRR" , 0, 4, 556, "R/W", 0, 0, 1ull, 1ull},
- {"TRAS" , 4, 5, 556, "R/W", 0, 0, 12ull, 12ull},
- {"TRCD" , 9, 4, 556, "R/W", 0, 0, 4ull, 4ull},
- {"TWTR" , 13, 4, 556, "R/W", 0, 0, 2ull, 3ull},
- {"TRFC" , 17, 5, 556, "R/W", 0, 0, 6ull, 7ull},
- {"TRRD" , 22, 3, 556, "R/W", 0, 0, 2ull, 2ull},
- {"TXP" , 25, 3, 556, "R/W", 0, 0, 3ull, 3ull},
- {"TWLMRD" , 28, 4, 556, "R/W", 0, 0, 10ull, 10ull},
- {"TWLDQSEN" , 32, 4, 556, "R/W", 0, 0, 7ull, 7ull},
- {"TFAW" , 36, 5, 556, "R/W", 0, 0, 0ull, 9ull},
- {"TXPDLL" , 41, 5, 556, "R/W", 0, 0, 0ull, 10ull},
- {"TRAS_EXT" , 46, 1, 556, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_47_63" , 47, 17, 556, "RAZ", 1, 1, 0, 0},
- {"TRESET" , 0, 1, 557, "R/W", 0, 1, 1ull, 0},
- {"RCLK_CNT" , 1, 32, 557, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 557, "RAZ", 1, 1, 0, 0},
- {"RING_CNT" , 0, 32, 558, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 558, "RAZ", 1, 1, 0, 0},
- {"LANEMASK" , 0, 9, 559, "R/W", 0, 1, 0ull, 0},
- {"SSET" , 9, 1, 559, "R/W", 0, 1, 0ull, 0},
- {"OR_DIS" , 10, 1, 559, "R/W", 0, 1, 0ull, 0},
- {"BITMASK" , 11, 8, 559, "R/W", 0, 1, 0ull, 0},
- {"RTT_NOM" , 19, 3, 559, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_63" , 22, 42, 559, "RAZ", 1, 1, 0, 0},
- {"BYTE" , 0, 4, 560, "R/W", 0, 0, 0ull, 0ull},
- {"BITMASK" , 4, 8, 560, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 560, "RAZ", 1, 1, 0, 0},
- {"BYTE0" , 0, 5, 561, "R/W", 0, 1, 0ull, 0},
- {"BYTE1" , 5, 5, 561, "R/W", 0, 1, 0ull, 0},
- {"BYTE2" , 10, 5, 561, "R/W", 0, 1, 0ull, 0},
- {"BYTE3" , 15, 5, 561, "R/W", 0, 1, 0ull, 0},
- {"BYTE4" , 20, 5, 561, "R/W", 0, 1, 0ull, 0},
- {"BYTE5" , 25, 5, 561, "R/W", 0, 1, 0ull, 0},
- {"BYTE6" , 30, 5, 561, "R/W", 0, 1, 0ull, 0},
- {"BYTE7" , 35, 5, 561, "R/W", 0, 1, 0ull, 0},
- {"BYTE8" , 40, 5, 561, "R/W", 0, 1, 0ull, 0},
- {"STATUS" , 45, 2, 561, "RO", 0, 1, 0ull, 0},
- {"RESERVED_47_63" , 47, 17, 561, "RAZ", 1, 1, 0, 0},
- {"WODT_D0_R0" , 0, 8, 562, "R/W", 0, 1, 255ull, 0},
- {"WODT_D0_R1" , 8, 8, 562, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R0" , 16, 8, 562, "R/W", 0, 1, 255ull, 0},
- {"WODT_D1_R1" , 24, 8, 562, "R/W", 0, 1, 255ull, 0},
- {"WODT_D2_R0" , 32, 8, 562, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D2_R1" , 40, 8, 562, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R0" , 48, 8, 562, "R/W", 0, 0, 255ull, 0ull},
- {"WODT_D3_R1" , 56, 8, 562, "R/W", 0, 0, 255ull, 0ull},
- {"STAT" , 0, 12, 563, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_63" , 12, 52, 563, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 564, "R/W", 1, 1, 0, 0},
- {"PCTL" , 6, 6, 564, "R/W", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 564, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 565, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 565, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 565, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 565, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 565, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 565, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 565, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 565, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 565, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 565, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 566, "R/W1C", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 566, "RO", 1, 1, 0, 0},
- {"RESERVED_2_63" , 2, 62, 566, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 567, "R/W", 0, 1, 0ull, 0},
- {"DMARQ" , 1, 1, 567, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 567, "RAZ", 1, 1, 0, 0},
- {"DMARQ" , 0, 6, 568, "R/W", 0, 1, 63ull, 0},
- {"DMACK_S" , 6, 6, 568, "R/W", 0, 1, 63ull, 0},
- {"OE_A" , 12, 6, 568, "R/W", 0, 1, 63ull, 0},
- {"OE_N" , 18, 6, 568, "R/W", 0, 1, 63ull, 0},
- {"WE_A" , 24, 6, 568, "R/W", 0, 1, 63ull, 0},
- {"WE_N" , 30, 6, 568, "R/W", 0, 1, 63ull, 0},
- {"DMACK_H" , 36, 6, 568, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 42, 6, 568, "R/W", 0, 1, 63ull, 0},
- {"RESERVED_48_54" , 48, 7, 568, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 55, 1, 568, "R/W", 0, 1, 0ull, 0},
- {"DDR" , 56, 1, 568, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 57, 3, 568, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 60, 2, 568, "R/W", 0, 1, 0ull, 0},
- {"DMARQ_PI" , 62, 1, 568, "R/W", 0, 1, 0ull, 0},
- {"DMACK_PI" , 63, 1, 568, "R/W", 0, 1, 0ull, 0},
- {"ADR_ERR" , 0, 1, 569, "R/W1C", 0, 0, 0ull, 0ull},
- {"WAIT_ERR" , 1, 1, 569, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 569, "RAZ", 1, 1, 0, 0},
- {"ADR_INT" , 0, 1, 570, "R/W", 0, 1, 0ull, 0},
- {"WAIT_INT" , 1, 1, 570, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 570, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 571, "RAZ", 1, 1, 0, 0},
- {"ADR" , 3, 5, 571, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 571, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 572, "RAZ", 1, 1, 0, 0},
- {"BASE" , 3, 25, 572, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_30" , 28, 3, 572, "RAZ", 1, 1, 0, 0},
- {"EN" , 31, 1, 572, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 572, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 573, "R/W", 1, 1, 0, 0},
- {"USER0" , 0, 8, 574, "RO", 1, 1, 0, 0},
- {"NAND" , 8, 1, 574, "RO", 1, 1, 0, 0},
- {"TERM" , 9, 2, 574, "RO", 1, 1, 0, 0},
- {"DMACK_P0" , 11, 1, 574, "RO", 1, 1, 0, 0},
- {"DMACK_P1" , 12, 1, 574, "RO", 1, 1, 0, 0},
- {"RESERVED_13_13" , 13, 1, 574, "RAZ", 1, 1, 0, 0},
- {"WIDTH" , 14, 1, 574, "RO", 1, 1, 0, 0},
- {"ALE" , 15, 1, 574, "RO", 1, 1, 0, 0},
- {"USER1" , 16, 16, 574, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 574, "RAZ", 1, 1, 0, 0},
- {"BASE" , 0, 16, 575, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 16, 12, 575, "R/W", 0, 1, 0ull, 0},
- {"WIDTH" , 28, 1, 575, "R/W", 0, 1, 0ull, 0},
- {"ALE" , 29, 1, 575, "R/W", 0, 1, 0ull, 0},
- {"ORBIT" , 30, 1, 575, "R/W", 0, 1, 0ull, 0},
- {"EN" , 31, 1, 575, "R/W", 0, 1, 0ull, 0},
- {"OE_EXT" , 32, 2, 575, "R/W", 0, 1, 0ull, 0},
- {"WE_EXT" , 34, 2, 575, "R/W", 0, 1, 0ull, 0},
- {"SAM" , 36, 1, 575, "R/W", 0, 1, 0ull, 0},
- {"RD_DLY" , 37, 3, 575, "R/W", 0, 1, 0ull, 0},
- {"TIM_MULT" , 40, 2, 575, "R/W", 0, 1, 0ull, 0},
- {"DMACK" , 42, 2, 575, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 575, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 6, 576, "R/W", 0, 1, 63ull, 0},
- {"CE" , 6, 6, 576, "R/W", 0, 1, 63ull, 0},
- {"OE" , 12, 6, 576, "R/W", 0, 1, 63ull, 0},
- {"WE" , 18, 6, 576, "R/W", 0, 1, 63ull, 0},
- {"RD_HLD" , 24, 6, 576, "R/W", 0, 1, 63ull, 0},
- {"WR_HLD" , 30, 6, 576, "R/W", 0, 1, 63ull, 0},
- {"PAUSE" , 36, 6, 576, "R/W", 0, 1, 63ull, 0},
- {"WAIT" , 42, 6, 576, "R/W", 0, 1, 63ull, 0},
- {"PAGE" , 48, 6, 576, "R/W", 0, 1, 63ull, 0},
- {"ALE" , 54, 6, 576, "R/W", 0, 1, 63ull, 0},
- {"PAGES" , 60, 2, 576, "R/W", 0, 1, 0ull, 0},
- {"WAITM" , 62, 1, 576, "R/W", 0, 1, 0ull, 0},
- {"PAGEM" , 63, 1, 576, "R/W", 0, 1, 0ull, 0},
- {"FIF_THR" , 0, 6, 577, "R/W", 0, 0, 25ull, 25ull},
- {"RESERVED_6_7" , 6, 2, 577, "RAZ", 1, 1, 0, 0},
- {"FIF_CNT" , 8, 6, 577, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 577, "RAZ", 1, 1, 0, 0},
- {"DMA_THR" , 16, 6, 577, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_22_63" , 22, 42, 577, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 578, "R/W", 1, 1, 0, 0},
- {"OFFSET" , 0, 6, 579, "R/W", 0, 1, 0ull, 0},
- {"BUF_NUM" , 6, 1, 579, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 579, "RAZ", 0, 1, 0ull, 0},
- {"INC" , 16, 1, 579, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 579, "RAZ", 0, 1, 0ull, 0},
- {"BUS_ENA" , 0, 4, 580, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_15" , 4, 12, 580, "RAZ", 0, 1, 0ull, 0},
- {"BOOT_FAIL" , 16, 1, 580, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_17_63" , 17, 47, 580, "RAZ", 0, 1, 0ull, 0},
- {"ARG" , 0, 32, 581, "R/W", 0, 1, 0ull, 0},
- {"CMD_IDX" , 32, 6, 581, "R/W", 0, 1, 0ull, 0},
- {"RTYPE_XOR" , 38, 3, 581, "R/W", 0, 1, 0ull, 0},
- {"CTYPE_XOR" , 41, 2, 581, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_48" , 43, 6, 581, "RAZ", 0, 1, 0ull, 0},
- {"OFFSET" , 49, 6, 581, "R/W", 0, 1, 0ull, 0},
- {"DBUF" , 55, 1, 581, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_56_58" , 56, 3, 581, "RAZ", 0, 1, 0ull, 0},
- {"CMD_VAL" , 59, 1, 581, "R/W", 1, 1, 0, 0},
- {"BUS_ID" , 60, 2, 581, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 581, "RAZ", 0, 1, 0ull, 0},
- {"CARD_ADDR" , 0, 32, 582, "R/W", 0, 1, 0ull, 0},
- {"BLOCK_CNT" , 32, 16, 582, "R/W", 0, 1, 0ull, 0},
- {"MULTI" , 48, 1, 582, "R/W", 0, 1, 0ull, 0},
- {"RW" , 49, 1, 582, "R/W", 0, 1, 0ull, 0},
- {"REL_WR" , 50, 1, 582, "R/W", 0, 1, 0ull, 0},
- {"THRES" , 51, 6, 582, "R/W", 0, 1, 0ull, 0},
- {"DAT_NULL" , 57, 1, 582, "R/W", 0, 1, 0ull, 0},
- {"SECTOR" , 58, 1, 582, "R/W", 0, 1, 0ull, 0},
- {"DMA_VAL" , 59, 1, 582, "R/W", 0, 1, 0ull, 0},
- {"BUS_ID" , 60, 2, 582, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 582, "RAZ", 0, 1, 0ull, 0},
- {"BUF_DONE" , 0, 1, 583, "R/W1C", 1, 1, 0, 0},
- {"CMD_DONE" , 1, 1, 583, "R/W1C", 1, 1, 0, 0},
- {"DMA_DONE" , 2, 1, 583, "R/W1C", 1, 1, 0, 0},
- {"CMD_ERR" , 3, 1, 583, "R/W1C", 1, 1, 0, 0},
- {"DMA_ERR" , 4, 1, 583, "R/W1C", 1, 1, 0, 0},
- {"SWITCH_DONE" , 5, 1, 583, "R/W1C", 1, 1, 0, 0},
- {"SWITCH_ERR" , 6, 1, 583, "R/W1C", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 583, "RAZ", 0, 1, 0ull, 0},
- {"BUF_DONE" , 0, 1, 584, "R/W", 1, 1, 0, 0},
- {"CMD_DONE" , 1, 1, 584, "R/W", 1, 1, 0, 0},
- {"DMA_DONE" , 2, 1, 584, "R/W", 1, 1, 0, 0},
- {"CMD_ERR" , 3, 1, 584, "R/W", 1, 1, 0, 0},
- {"DMA_ERR" , 4, 1, 584, "R/W", 1, 1, 0, 0},
- {"SWITCH_DONE" , 5, 1, 584, "R/W", 1, 1, 0, 0},
- {"SWITCH_ERR" , 6, 1, 584, "R/W", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 584, "RAZ", 0, 1, 0ull, 0},
- {"CLK_LO" , 0, 16, 585, "RO", 0, 1, 2500ull, 0},
- {"CLK_HI" , 16, 16, 585, "RO", 0, 1, 2500ull, 0},
- {"POWER_CLASS" , 32, 4, 585, "RO", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 585, "RAZ", 0, 1, 0ull, 0},
- {"BUS_WIDTH" , 40, 3, 585, "RO", 0, 1, 0ull, 0},
- {"RESERVED_43_47" , 43, 5, 585, "RAZ", 0, 1, 0ull, 0},
- {"HS_TIMING" , 48, 1, 585, "RO", 0, 1, 0ull, 0},
- {"RESERVED_49_63" , 49, 15, 585, "RAZ", 0, 1, 0ull, 0},
- {"CARD_RCA" , 0, 16, 586, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 586, "RAZ", 0, 1, 0ull, 0},
- {"DAT" , 0, 64, 587, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 64, 588, "RO", 1, 1, 0, 0},
- {"CMD_DONE" , 0, 1, 589, "RO", 0, 1, 0ull, 0},
- {"CMD_IDX" , 1, 6, 589, "RO", 0, 1, 0ull, 0},
- {"CMD_TYPE" , 7, 2, 589, "RO", 0, 1, 0ull, 0},
- {"RSP_TYPE" , 9, 3, 589, "RO", 0, 1, 0ull, 0},
- {"RSP_VAL" , 12, 1, 589, "RO", 0, 1, 0ull, 0},
- {"RSP_BAD_STS" , 13, 1, 589, "RO", 0, 1, 0ull, 0},
- {"RSP_CRC_ERR" , 14, 1, 589, "RO", 0, 1, 0ull, 0},
- {"RSP_TIMEOUT" , 15, 1, 589, "RO", 0, 1, 0ull, 0},
- {"STP_VAL" , 16, 1, 589, "RO", 0, 1, 0ull, 0},
- {"STP_BAD_STS" , 17, 1, 589, "RO", 0, 1, 0ull, 0},
- {"STP_CRC_ERR" , 18, 1, 589, "RO", 0, 1, 0ull, 0},
- {"STP_TIMEOUT" , 19, 1, 589, "RO", 0, 1, 0ull, 0},
- {"RSP_BUSYBIT" , 20, 1, 589, "RO", 0, 1, 0ull, 0},
- {"BLK_CRC_ERR" , 21, 1, 589, "RO", 0, 1, 0ull, 0},
- {"BLK_TIMEOUT" , 22, 1, 589, "RO", 0, 1, 0ull, 0},
- {"DBUF" , 23, 1, 589, "RO", 0, 1, 0ull, 0},
- {"RESERVED_24_27" , 24, 4, 589, "RAZ", 0, 1, 0ull, 0},
- {"DBUF_ERR" , 28, 1, 589, "RO", 0, 1, 0ull, 0},
- {"RESERVED_29_55" , 29, 27, 589, "RAZ", 0, 1, 0ull, 0},
- {"DMA_PEND" , 56, 1, 589, "RO", 0, 1, 0ull, 0},
- {"DMA_VAL" , 57, 1, 589, "RO", 0, 1, 0ull, 0},
- {"SWITCH_VAL" , 58, 1, 589, "RO", 0, 1, 0ull, 0},
- {"CMD_VAL" , 59, 1, 589, "RO", 0, 1, 0ull, 0},
- {"BUS_ID" , 60, 2, 589, "RO", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 589, "RAZ", 0, 1, 0ull, 0},
- {"DAT_CNT" , 0, 10, 590, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_15" , 10, 6, 590, "RAZ", 0, 1, 0ull, 0},
- {"CMD_CNT" , 16, 10, 590, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_63" , 26, 38, 590, "RAZ", 0, 1, 0ull, 0},
- {"STS_MSK" , 0, 32, 591, "R/W", 0, 1, 3828940928ull, 0},
- {"RESERVED_32_63" , 32, 32, 591, "RAZ", 0, 1, 0ull, 0},
- {"CLK_LO" , 0, 16, 592, "R/W", 0, 1, 2500ull, 0},
- {"CLK_HI" , 16, 16, 592, "R/W", 0, 1, 2500ull, 0},
- {"POWER_CLASS" , 32, 4, 592, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_36_39" , 36, 4, 592, "RAZ", 0, 1, 0ull, 0},
- {"BUS_WIDTH" , 40, 3, 592, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_43_47" , 43, 5, 592, "RAZ", 0, 1, 0ull, 0},
- {"HS_TIMING" , 48, 1, 592, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_49_55" , 49, 7, 592, "RAZ", 0, 1, 0ull, 0},
- {"SWITCH_ERR2" , 56, 1, 592, "RO", 0, 1, 0ull, 0},
- {"SWITCH_ERR1" , 57, 1, 592, "RO", 0, 1, 0ull, 0},
- {"SWITCH_ERR0" , 58, 1, 592, "RO", 0, 1, 0ull, 0},
- {"SWITCH_EXE" , 59, 1, 592, "R/W", 0, 1, 0ull, 0},
- {"BUS_ID" , 60, 2, 592, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_62_63" , 62, 2, 592, "RAZ", 0, 1, 0ull, 0},
- {"CLK_CNT" , 0, 26, 593, "R/W", 0, 1, 41855000ull, 0},
- {"RESERVED_26_63" , 26, 38, 593, "RAZ", 0, 1, 0ull, 0},
- {"DAT" , 0, 64, 594, "R/W", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 595, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 595, "RAZ", 1, 1, 0, 0},
- {"MAN_INFO" , 0, 32, 596, "RO", 1, 1, 0, 0},
- {"RESERVED_32_63" , 32, 32, 596, "RAZ", 1, 1, 0, 0},
- {"PP_DIS" , 0, 4, 597, "RO", 1, 1, 0, 0},
- {"RESERVED_4_15" , 4, 12, 597, "RO", 1, 1, 0, 0},
- {"CHIP_ID" , 16, 8, 597, "RO", 1, 1, 0, 0},
- {"RESERVED_24_25" , 24, 2, 597, "RO", 1, 1, 0, 0},
- {"NOCRYPTO" , 26, 1, 597, "RO", 1, 1, 0, 0},
- {"NOMUL" , 27, 1, 597, "RO", 1, 1, 0, 0},
- {"NODFA_CP2" , 28, 1, 597, "RO", 1, 1, 0, 0},
- {"RESERVED_29_31" , 29, 3, 597, "RO", 1, 1, 0, 0},
- {"RAID_EN" , 32, 1, 597, "RO", 1, 1, 0, 0},
- {"FUS318" , 33, 1, 597, "RO", 1, 1, 0, 0},
- {"DORM_CRYPTO" , 34, 1, 597, "RO", 1, 1, 0, 0},
- {"POWER_LIMIT" , 35, 2, 597, "RO", 1, 1, 0, 0},
- {"ROM_INFO" , 37, 10, 597, "RO", 1, 1, 0, 0},
- {"FUS118" , 47, 1, 597, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 597, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 598, "RAZ", 1, 1, 0, 0},
- {"NODFA_DTE" , 24, 1, 598, "RO", 1, 1, 0, 0},
- {"NOZIP" , 25, 1, 598, "RO", 1, 1, 0, 0},
- {"EFUS_IGN" , 26, 1, 598, "RO", 1, 1, 0, 0},
- {"EFUS_LCK" , 27, 1, 598, "RO", 1, 1, 0, 0},
- {"BAR2_EN" , 28, 1, 598, "RO", 1, 1, 0, 0},
- {"ZIP_INFO" , 29, 2, 598, "RO", 1, 1, 0, 0},
- {"RESERVED_31_31" , 31, 1, 598, "RAZ", 1, 1, 0, 0},
- {"L2C_CRIP" , 32, 3, 598, "RO", 1, 1, 0, 0},
- {"PLL_HALF_DIS" , 35, 1, 598, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_MAN" , 36, 1, 598, "RO", 1, 1, 0, 0},
- {"EFUS_LCK_RSV" , 37, 1, 598, "RO", 1, 1, 0, 0},
- {"EMA" , 38, 2, 598, "RO", 1, 1, 0, 0},
- {"RESERVED_40_40" , 40, 1, 598, "RAZ", 1, 1, 0, 0},
- {"DFA_INFO_CLM" , 41, 4, 598, "RO", 1, 1, 0, 0},
- {"DFA_INFO_DTE" , 45, 3, 598, "RO", 1, 1, 0, 0},
- {"PLL_CTL" , 48, 10, 598, "RO", 1, 1, 0, 0},
- {"RESERVED_58_63" , 58, 6, 598, "RAZ", 1, 1, 0, 0},
- {"EMA" , 0, 3, 599, "RAZ", 1, 1, 0, 0},
- {"RESERVED_3_3" , 3, 1, 599, "RAZ", 1, 1, 0, 0},
- {"EFF_EMA" , 4, 3, 599, "RAZ", 1, 1, 0, 0},
- {"RESERVED_7_63" , 7, 57, 599, "RAZ", 1, 1, 0, 0},
- {"PDF" , 0, 64, 600, "RO", 1, 1, 0, 0},
- {"FBSLIP" , 0, 1, 601, "RAZ", 0, 1, 0ull, 0},
- {"RFSLIP" , 1, 1, 601, "RAZ", 0, 1, 0ull, 0},
- {"PNR_COUT_SEL" , 2, 2, 601, "R/W", 0, 1, 0ull, 0},
- {"PNR_COUT_RST" , 4, 1, 601, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_SEL" , 5, 2, 601, "R/W", 0, 1, 0ull, 0},
- {"C_COUT_RST" , 7, 1, 601, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 601, "RAZ", 1, 1, 0, 0},
- {"PROG" , 0, 1, 602, "R/W", 1, 1, 0, 0},
- {"SOFT" , 1, 1, 602, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 602, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 6, 603, "R/W", 0, 1, 1ull, 0},
- {"SCLK_HI" , 6, 15, 603, "R/W", 0, 1, 5000ull, 0},
- {"SCLK_LO" , 21, 4, 603, "R/W", 0, 1, 1ull, 0},
- {"OUT" , 25, 7, 603, "R/W", 0, 1, 1ull, 0},
- {"PROG_PIN" , 32, 1, 603, "RO", 0, 0, 0ull, 0ull},
- {"FSRC_PIN" , 33, 1, 603, "RO", 0, 0, 0ull, 0ull},
- {"VGATE_PIN" , 34, 1, 603, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_35_63" , 35, 29, 603, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 8, 604, "R/W", 0, 0, 0ull, 0ull},
- {"EFUSE" , 8, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 604, "RAZ", 1, 1, 0, 0},
- {"PEND" , 12, 1, 604, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 604, "RAZ", 1, 1, 0, 0},
- {"DAT" , 16, 8, 604, "RO", 1, 1, 0, 0},
- {"RESERVED_24_63" , 24, 40, 604, "RAZ", 1, 1, 0, 0},
- {"SETUP" , 0, 10, 605, "R/W", 0, 1, 999ull, 0},
- {"SDH" , 10, 4, 605, "R/W", 0, 1, 0ull, 0},
- {"PRH" , 14, 4, 605, "R/W", 0, 1, 6ull, 0},
- {"FSH" , 18, 4, 605, "R/W", 0, 1, 15ull, 0},
- {"SCH" , 22, 4, 605, "R/W", 0, 1, 15ull, 0},
- {"RESERVED_26_63" , 26, 38, 605, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 18, 606, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR1" , 18, 18, 606, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR2" , 36, 18, 606, "RO", 0, 0, 0ull, 0ull},
- {"TOO_MANY" , 54, 1, 606, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 606, "RAZ", 1, 1, 0, 0},
- {"REPAIR3" , 0, 18, 607, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR4" , 18, 18, 607, "RO", 0, 0, 0ull, 0ull},
- {"REPAIR5" , 36, 18, 607, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 607, "RAZ", 1, 1, 0, 0},
- {"REPAIR6" , 0, 18, 608, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 608, "RAZ", 1, 1, 0, 0},
- {"REPAIR0" , 0, 14, 609, "RAZ", 1, 1, 0, 0},
- {"REPAIR1" , 14, 14, 609, "RAZ", 1, 1, 0, 0},
- {"REPAIR2" , 28, 14, 609, "RAZ", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 609, "RAZ", 1, 1, 0, 0},
- {"TOO_MANY" , 0, 1, 610, "RAZ", 1, 1, 0, 0},
- {"RESERVED_1_63" , 1, 63, 610, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 63, 611, "RO", 1, 1, 0, 0},
- {"VAL" , 63, 1, 611, "R/W", 1, 1, 0, 0},
- {"ADDR" , 0, 4, 612, "R/W", 1, 1, 0, 0},
- {"RESERVED_4_63" , 4, 60, 612, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 613, "R/W", 0, 1, 15ull, 0},
- {"PCTL" , 6, 6, 613, "R/W", 0, 1, 19ull, 0},
- {"RESERVED_12_63" , 12, 52, 613, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 36, 614, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 36, 20, 614, "R/W", 0, 1, 0ull, 0},
- {"ENDIAN" , 56, 1, 614, "R/W", 0, 1, 0ull, 0},
- {"SWAP8" , 57, 1, 614, "R/W", 0, 1, 0ull, 0},
- {"SWAP16" , 58, 1, 614, "R/W", 0, 1, 0ull, 0},
- {"SWAP32" , 59, 1, 614, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_60_60" , 60, 1, 614, "RAZ", 1, 1, 0, 0},
- {"CLR" , 61, 1, 614, "R/W", 0, 1, 0ull, 0},
- {"RW" , 62, 1, 614, "R/W", 0, 1, 0ull, 0},
- {"EN" , 63, 1, 614, "R/W", 0, 1, 0ull, 0},
- {"DONE" , 0, 1, 615, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 615, "RAZ", 1, 1, 0, 0},
- {"DONE" , 0, 1, 616, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 616, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 617, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 617, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 618, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 618, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 619, "R/W", 0, 0, 18446744073709551615ull, 0ull},
- {"FRNANOSEC" , 0, 32, 620, "R/W", 0, 0, 4294967295ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 620, "RAZ", 1, 1, 0, 0},
- {"PTP_EN" , 0, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EN" , 1, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_IN" , 2, 6, 621, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EN" , 8, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_EDGE" , 9, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"TSTMP_IN" , 10, 6, 621, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EN" , 16, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_EDGE" , 17, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"EVCNT_IN" , 18, 6, 621, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_EN" , 24, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_INV" , 25, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_OUT" , 26, 4, 621, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_EN" , 30, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_INV" , 31, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"PPS_OUT" , 32, 5, 621, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT_OUT4" , 37, 1, 621, "R/W", 0, 0, 0ull, 0ull},
- {"EXT_CLK_EDGE" , 38, 2, 621, "R/W", 0, 0, 0ull, 0ull},
- {"CKOUT" , 40, 1, 621, "RO", 1, 0, 0, 0ull},
- {"PPS" , 41, 1, 621, "RO", 1, 0, 0, 0ull},
- {"RESERVED_42_63" , 42, 22, 621, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 622, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 622, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 623, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 624, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 624, "RAZ", 1, 1, 0, 0},
- {"CNTR" , 0, 64, 625, "R/W", 0, 0, 0ull, 0ull},
- {"SEL" , 0, 5, 626, "R/W", 0, 0, 31ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 626, "RAZ", 1, 1, 0, 0},
- {"FRNANOSEC" , 0, 32, 627, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 627, "R/W", 0, 0, 0ull, 0ull},
- {"FRNANOSEC" , 0, 32, 628, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 32, 32, 628, "R/W", 0, 0, 0ull, 0ull},
- {"NANOSEC" , 0, 64, 629, "R/W", 0, 0, 18446744073709551615ull, 0ull},
- {"FRNANOSEC" , 0, 32, 630, "R/W", 0, 0, 4294967295ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 630, "RAZ", 1, 1, 0, 0},
- {"NANOSEC" , 0, 64, 631, "R/W", 0, 0, 0ull, 0ull},
- {"QLM_CFG" , 0, 2, 632, "R/W", 1, 1, 0, 0},
- {"RESERVED_2_7" , 2, 6, 632, "RAZ", 1, 1, 0, 0},
- {"QLM_SPD" , 8, 4, 632, "R/W", 1, 1, 0, 0},
- {"RESERVED_12_13" , 12, 2, 632, "RAZ", 1, 1, 0, 0},
- {"PRTMODE" , 14, 1, 632, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 632, "RAZ", 1, 1, 0, 0},
- {"RBOOT_PIN" , 0, 1, 633, "RO", 1, 1, 0, 0},
- {"RBOOT" , 1, 1, 633, "R/W", 1, 1, 0, 0},
- {"LBOOT" , 2, 10, 633, "R/W1C", 1, 1, 0, 0},
- {"QLM0_SPD" , 12, 4, 633, "RO", 1, 1, 0, 0},
- {"QLM1_SPD" , 16, 4, 633, "RO", 1, 1, 0, 0},
- {"QLM2_SPD" , 20, 4, 633, "RO", 1, 1, 0, 0},
- {"PNR_MUL" , 24, 6, 633, "RO", 1, 1, 0, 0},
- {"C_MUL" , 30, 6, 633, "RO", 1, 1, 0, 0},
- {"RESERVED_36_47" , 36, 12, 633, "RAZ", 1, 1, 0, 0},
- {"LBOOT_EXT" , 48, 2, 633, "R/W1C", 1, 1, 0, 0},
- {"RESERVED_50_57" , 50, 8, 633, "RAZ", 1, 1, 0, 0},
- {"JT_TSTMODE" , 58, 1, 633, "RO", 1, 1, 0, 0},
- {"CKILL_PPDIS" , 59, 1, 633, "R/W", 0, 1, 1ull, 0},
- {"ROMEN" , 60, 1, 633, "R/W", 1, 1, 0, 0},
- {"EJTAGDIS" , 61, 1, 633, "R/W", 1, 1, 0, 0},
- {"JTCSRDIS" , 62, 1, 633, "R/W", 1, 1, 0, 0},
- {"CHIPKILL" , 63, 1, 633, "R/W1", 0, 0, 0ull, 0ull},
- {"SOFT_CLR_BIST" , 0, 1, 634, "R/W", 0, 0, 0ull, 0ull},
- {"WARM_CLR_BIST" , 1, 1, 634, "R/W", 0, 0, 0ull, 0ull},
- {"CNTL_CLR_BIST" , 2, 1, 634, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_5" , 3, 3, 634, "RAZ", 1, 1, 0, 0},
- {"BIST_DELAY" , 6, 58, 634, "RO", 1, 1, 0, 0},
- {"TIMER" , 0, 47, 635, "R/W", 0, 1, 17179869183ull, 0},
- {"RESERVED_47_63" , 47, 17, 635, "RAZ", 0, 0, 0ull, 0ull},
- {"RST_VAL" , 0, 1, 636, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 636, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 636, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 636, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 636, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 636, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 636, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 636, "RO", 1, 1, 0, 0},
- {"PRST_LINK" , 9, 1, 636, "R/W", 0, 1, 0ull, 0},
- {"GEN1_ONLY" , 10, 1, 636, "RO", 0, 1, 0ull, 0},
- {"REV_LANES" , 11, 1, 636, "R/W", 1, 1, 0, 0},
- {"IN_REV_LN" , 12, 1, 636, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 636, "RAZ", 1, 1, 0, 0},
- {"RST_VAL" , 0, 1, 637, "RO", 1, 1, 0, 0},
- {"RST_CHIP" , 1, 1, 637, "R/W", 0, 1, 0ull, 0},
- {"RST_RCV" , 2, 1, 637, "R/W", 1, 1, 0, 0},
- {"RST_DRV" , 3, 1, 637, "R/W", 1, 1, 0, 0},
- {"PRTMODE" , 4, 2, 637, "R/W", 1, 1, 0, 0},
- {"HOST_MODE" , 6, 1, 637, "RO", 1, 1, 0, 0},
- {"RST_LINK" , 7, 1, 637, "R/W", 1, 1, 0, 0},
- {"RST_DONE" , 8, 1, 637, "RO", 1, 1, 0, 0},
- {"PRST_LINK" , 9, 1, 637, "R/W", 0, 1, 0ull, 0},
- {"GEN1_ONLY" , 10, 1, 637, "RO", 0, 1, 0ull, 0},
- {"REV_LANES" , 11, 1, 637, "R/W", 1, 1, 0, 0},
- {"IN_REV_LN" , 12, 1, 637, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 637, "RAZ", 1, 1, 0, 0},
- {"SOFT_RST_DLY" , 0, 16, 638, "R/W", 0, 1, 2047ull, 0},
- {"WARM_RST_DLY" , 16, 16, 638, "R/W", 0, 1, 2047ull, 0},
- {"RESERVED_32_63" , 32, 32, 638, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 639, "R/W1C", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 639, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 639, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 639, "R/W1C", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 639, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 639, "RAZ", 1, 1, 0, 0},
- {"RST_LINK0" , 0, 1, 640, "R/W", 0, 1, 0ull, 0},
- {"RST_LINK1" , 1, 1, 640, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_7" , 2, 6, 640, "RAZ", 1, 1, 0, 0},
- {"PERST0" , 8, 1, 640, "R/W", 0, 1, 0ull, 0},
- {"PERST1" , 9, 1, 640, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 640, "RAZ", 1, 1, 0, 0},
- {"ST_INT" , 0, 1, 641, "R/W1C", 0, 1, 0ull, 0},
- {"TS_INT" , 1, 1, 641, "R/W1C", 0, 1, 0ull, 0},
- {"CORE_INT" , 2, 1, 641, "RO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 641, "RAZ", 1, 1, 0, 0},
- {"ST_EN" , 4, 1, 641, "R/W", 0, 1, 0ull, 0},
- {"TS_EN" , 5, 1, 641, "R/W", 0, 1, 0ull, 0},
- {"CORE_EN" , 6, 1, 641, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 641, "RAZ", 1, 1, 0, 0},
- {"SDA_OVR" , 8, 1, 641, "R/W", 0, 1, 0ull, 0},
- {"SCL_OVR" , 9, 1, 641, "R/W", 0, 1, 0ull, 0},
- {"SDA" , 10, 1, 641, "RO", 1, 1, 0, 0},
- {"SCL" , 11, 1, 641, "RO", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 641, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 642, "R/W", 0, 1, 0ull, 0},
- {"EOP_IA" , 32, 3, 642, "R/W", 0, 1, 0ull, 0},
- {"IA" , 35, 5, 642, "R/W", 0, 1, 0ull, 0},
- {"A" , 40, 10, 642, "R/W", 0, 1, 0ull, 0},
- {"SCR" , 50, 2, 642, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 52, 3, 642, "R/W", 0, 1, 0ull, 0},
- {"SOVR" , 55, 1, 642, "R/W", 0, 1, 0ull, 0},
- {"R" , 56, 1, 642, "R/W", 0, 1, 0ull, 0},
- {"OP" , 57, 4, 642, "R/W", 0, 1, 0ull, 0},
- {"EIA" , 61, 1, 642, "R/W", 0, 1, 0ull, 0},
- {"SLONLY" , 62, 1, 642, "R/W", 0, 1, 0ull, 0},
- {"V" , 63, 1, 642, "RC/W", 0, 1, 0ull, 0},
- {"D" , 0, 32, 643, "R/W", 0, 1, 0ull, 0},
- {"IA" , 32, 8, 643, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_63" , 40, 24, 643, "RAZ", 1, 1, 0, 0},
- {"D" , 0, 32, 644, "R/W", 1, 1, 0, 0},
- {"RESERVED_32_61" , 32, 30, 644, "RAZ", 1, 1, 0, 0},
- {"V" , 62, 2, 644, "RC/W", 0, 1, 0ull, 0},
- {"DLH" , 0, 8, 645, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 645, "RAZ", 1, 1, 0, 0},
- {"DLL" , 0, 8, 646, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 646, "RAZ", 1, 1, 0, 0},
- {"FAR" , 0, 1, 647, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 647, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 648, "WO", 0, 1, 0ull, 0},
- {"RXFR" , 1, 1, 648, "WO", 0, 1, 0ull, 0},
- {"TXFR" , 2, 1, 648, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_3" , 3, 1, 648, "RAZ", 1, 1, 0, 0},
- {"TXTRIG" , 4, 2, 648, "WO", 0, 1, 0ull, 0},
- {"RXTRIG" , 6, 2, 648, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 648, "RAZ", 1, 1, 0, 0},
- {"HTX" , 0, 1, 649, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 649, "RAZ", 1, 1, 0, 0},
- {"ERBFI" , 0, 1, 650, "R/W", 0, 1, 0ull, 0},
- {"ETBEI" , 1, 1, 650, "R/W", 0, 1, 0ull, 0},
- {"ELSI" , 2, 1, 650, "R/W", 0, 1, 0ull, 0},
- {"EDSSI" , 3, 1, 650, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_6" , 4, 3, 650, "RAZ", 1, 1, 0, 0},
- {"PTIME" , 7, 1, 650, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 650, "RAZ", 1, 1, 0, 0},
- {"IID" , 0, 4, 651, "RO", 0, 1, 1ull, 0},
- {"RESERVED_4_5" , 4, 2, 651, "RAZ", 0, 1, 0ull, 0},
- {"FEN" , 6, 2, 651, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 651, "RAZ", 1, 1, 0, 0},
- {"CLS" , 0, 2, 652, "R/W", 0, 1, 0ull, 0},
- {"STOP" , 2, 1, 652, "R/W", 0, 1, 0ull, 0},
- {"PEN" , 3, 1, 652, "R/W", 0, 1, 0ull, 0},
- {"EPS" , 4, 1, 652, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_5" , 5, 1, 652, "RAZ", 1, 1, 0, 0},
- {"BRK" , 6, 1, 652, "R/W", 0, 1, 0ull, 0},
- {"DLAB" , 7, 1, 652, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 652, "RAZ", 1, 1, 0, 0},
- {"DR" , 0, 1, 653, "RO", 0, 1, 0ull, 0},
- {"OE" , 1, 1, 653, "RC", 0, 1, 0ull, 0},
- {"PE" , 2, 1, 653, "RC", 0, 1, 0ull, 0},
- {"FE" , 3, 1, 653, "RC", 0, 1, 0ull, 0},
- {"BI" , 4, 1, 653, "RC", 0, 1, 0ull, 0},
- {"THRE" , 5, 1, 653, "RO", 0, 1, 1ull, 0},
- {"TEMT" , 6, 1, 653, "RO", 0, 1, 1ull, 0},
- {"FERR" , 7, 1, 653, "RC", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 653, "RAZ", 1, 1, 0, 0},
- {"DTR" , 0, 1, 654, "R/W", 0, 1, 0ull, 0},
- {"RTS" , 1, 1, 654, "R/W", 0, 1, 0ull, 0},
- {"OUT1" , 2, 1, 654, "R/W", 0, 1, 0ull, 0},
- {"OUT2" , 3, 1, 654, "R/W", 0, 1, 0ull, 0},
- {"LOOP" , 4, 1, 654, "R/W", 0, 1, 0ull, 0},
- {"AFCE" , 5, 1, 654, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_63" , 6, 58, 654, "RAZ", 1, 1, 0, 0},
- {"DCTS" , 0, 1, 655, "RC", 0, 1, 0ull, 0},
- {"DDSR" , 1, 1, 655, "RC", 0, 1, 0ull, 0},
- {"TERI" , 2, 1, 655, "RC", 0, 1, 0ull, 0},
- {"DDCD" , 3, 1, 655, "RC", 0, 1, 0ull, 0},
- {"CTS" , 4, 1, 655, "RO", 1, 1, 0, 0},
- {"DSR" , 5, 1, 655, "RO", 0, 1, 0ull, 0},
- {"RI" , 6, 1, 655, "RO", 0, 1, 0ull, 0},
- {"DCD" , 7, 1, 655, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 655, "RAZ", 1, 1, 0, 0},
- {"RBR" , 0, 8, 656, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 656, "RAZ", 1, 1, 0, 0},
- {"RFL" , 0, 7, 657, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 657, "RAZ", 1, 1, 0, 0},
- {"RFWD" , 0, 8, 658, "WO", 0, 1, 0ull, 0},
- {"RFPE" , 8, 1, 658, "WO", 0, 1, 0ull, 0},
- {"RFFE" , 9, 1, 658, "WO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 658, "RAZ", 1, 1, 0, 0},
- {"SBCR" , 0, 1, 659, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 659, "RAZ", 1, 1, 0, 0},
- {"SCR" , 0, 8, 660, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 660, "RAZ", 1, 1, 0, 0},
- {"SFE" , 0, 1, 661, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 661, "RAZ", 1, 1, 0, 0},
- {"USR" , 0, 1, 662, "WO", 0, 1, 0ull, 0},
- {"SRFR" , 1, 1, 662, "WO", 0, 1, 0ull, 0},
- {"STFR" , 2, 1, 662, "WO", 0, 1, 0ull, 0},
- {"RESERVED_3_63" , 3, 61, 662, "RAZ", 1, 1, 0, 0},
- {"SRT" , 0, 2, 663, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 663, "RAZ", 1, 1, 0, 0},
- {"SRTS" , 0, 1, 664, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_1_63" , 1, 63, 664, "RAZ", 1, 1, 0, 0},
- {"STT" , 0, 2, 665, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_2_63" , 2, 62, 665, "RAZ", 1, 1, 0, 0},
- {"TFL" , 0, 7, 666, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 666, "RAZ", 1, 1, 0, 0},
- {"TFR" , 0, 8, 667, "RO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 667, "RAZ", 1, 1, 0, 0},
- {"THR" , 0, 8, 668, "WO", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 668, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 669, "RO", 0, 1, 0ull, 0},
- {"TFNF" , 1, 1, 669, "RO", 0, 1, 1ull, 0},
- {"TFE" , 2, 1, 669, "RO", 0, 1, 1ull, 0},
- {"RFNE" , 3, 1, 669, "RO", 0, 1, 0ull, 0},
- {"RFF" , 4, 1, 669, "RO", 0, 1, 0ull, 0},
- {"RESERVED_5_63" , 5, 59, 669, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"IDLELO" , 1, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"CLK_CONT" , 2, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"WIREOR" , 3, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 4, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"INT_ENA" , 5, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_6" , 6, 1, 670, "RAZ", 1, 1, 0, 0},
- {"CSHI" , 7, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"IDLECLKS" , 8, 2, 670, "R/W", 0, 0, 0ull, 0ull},
- {"TRITX" , 10, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"CSLATE" , 11, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"CSENA0" , 12, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"CSENA1" , 13, 1, 670, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_15" , 14, 2, 670, "RAZ", 1, 1, 0, 0},
- {"CLKDIV" , 16, 13, 670, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_29_63" , 29, 35, 670, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 8, 671, "R/W", 1, 1, 0, 0},
- {"RESERVED_8_63" , 8, 56, 671, "RAZ", 1, 1, 0, 0},
- {"BUSY" , 0, 1, 672, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_7" , 1, 7, 672, "RAZ", 1, 1, 0, 0},
- {"RXNUM" , 8, 5, 672, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 672, "RAZ", 1, 1, 0, 0},
- {"TOTNUM" , 0, 5, 673, "WO", 1, 0, 0, 2ull},
- {"RESERVED_5_7" , 5, 3, 673, "RAZ", 1, 1, 0, 0},
- {"TXNUM" , 8, 5, 673, "WO", 1, 0, 0, 1ull},
- {"RESERVED_13_15" , 13, 3, 673, "RAZ", 1, 1, 0, 0},
- {"LEAVECS" , 16, 1, 673, "WO", 1, 0, 0, 0ull},
- {"RESERVED_17_19" , 17, 3, 673, "RAZ", 1, 1, 0, 0},
- {"CSID" , 20, 1, 673, "WO", 1, 0, 0, 0ull},
- {"RESERVED_21_63" , 21, 43, 673, "RAZ", 1, 1, 0, 0},
- {"VENDID" , 0, 16, 674, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 674, "RO/WRSL", 0, 0, 148ull, 148ull},
- {"ISAE" , 0, 1, 675, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 675, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 675, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 675, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 675, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 675, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 675, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 675, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 675, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 675, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 675, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 675, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 675, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 675, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 675, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 675, "RAZ", 1, 1, 0, 0},
- {"FBB" , 23, 1, 675, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 675, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 675, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 675, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 675, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 675, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 675, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 675, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 676, "RO/WRSL", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 676, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 676, "RO/WRSL", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 676, "RO/WRSL", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 677, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 677, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 677, "RO", 0, 0, 0ull, 0ull},
- {"MFD" , 23, 1, 677, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 677, "RO", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 678, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 678, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 678, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_13" , 4, 10, 678, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 14, 18, 678, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 679, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 679, "WORSL", 0, 0, 8191ull, 8191ull},
- {"UBAB" , 0, 32, 680, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 681, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 682, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 682, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 682, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_25" , 4, 22, 682, "RAZ", 1, 1, 0, 0},
- {"LBAB" , 26, 6, 682, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 683, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 683, "WORSL", 0, 0, 33554431ull, 33554431ull},
- {"UBAB" , 0, 32, 684, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 685, "WORSL", 0, 0, 0ull, 0ull},
- {"MSPC" , 0, 1, 686, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"TYP" , 1, 2, 686, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"PF" , 3, 1, 686, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_4_31" , 4, 28, 686, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 1, 687, "WORSL", 0, 0, 1ull, 1ull},
- {"LMASK" , 1, 31, 687, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
- {"RESERVED_0_8" , 0, 9, 688, "RAZ", 1, 1, 0, 0},
- {"UBAB" , 9, 23, 688, "R/W", 0, 0, 0ull, 0ull},
- {"UMASK" , 0, 32, 689, "WORSL", 0, 0, 511ull, 511ull},
- {"CISP" , 0, 32, 690, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SSVID" , 0, 16, 691, "RO/WRSL", 0, 0, 6013ull, 6013ull},
- {"SSID" , 16, 16, 691, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ER_EN" , 0, 1, 692, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_15" , 1, 15, 692, "RAZ", 1, 1, 0, 0},
- {"ERADDR" , 16, 16, 692, "R/W", 0, 0, 0ull, 0ull},
- {"ENB" , 0, 1, 693, "WORSL", 0, 0, 1ull, 1ull},
- {"MASK" , 1, 31, 693, "WORSL", 0, 0, 32767ull, 32767ull},
- {"CP" , 0, 8, 694, "RO/WRSL", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 694, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 695, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 695, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"MG" , 16, 8, 695, "RO", 0, 0, 0ull, 0ull},
- {"ML" , 24, 8, 695, "RO", 0, 0, 0ull, 0ull},
- {"PMCID" , 0, 8, 696, "RO", 0, 0, 1ull, 0ull},
- {"NCP" , 8, 8, 696, "RO/WRSL", 0, 0, 80ull, 0ull},
- {"PMSV" , 16, 3, 696, "RO/WRSL", 0, 0, 3ull, 0ull},
- {"PME_CLOCK" , 19, 1, 696, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 696, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 696, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 696, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 696, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 696, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 696, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 697, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 697, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 697, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 697, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 697, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 697, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 697, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 697, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 697, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 697, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 697, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 697, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 698, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 698, "RO/WRSL", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 698, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 698, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 698, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 698, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PVM" , 24, 1, 698, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 698, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 699, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 699, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 700, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 701, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 701, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 702, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 702, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 702, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 702, "RO", 0, 0, 0ull, 0ull},
- {"SI" , 24, 1, 702, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 702, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 702, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 703, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 703, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 703, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 703, "RO/WRSL", 0, 0, 4ull, 4ull},
- {"EL1AL" , 9, 3, 703, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"RESERVED_12_14" , 12, 3, 703, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 703, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 703, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 703, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 703, "RO", 0, 0, 0ull, 0ull},
- {"FLR_CAP" , 28, 1, 703, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 703, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 704, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 704, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 704, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 704, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 704, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 704, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 704, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 704, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 704, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 704, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 704, "R/W", 0, 0, 2ull, 2ull},
- {"I_FLR" , 15, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"CE_D" , 16, 1, 704, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 704, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 704, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 704, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 704, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 704, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 705, "RO/WRSL", 1, 1, 0, 0},
- {"MLW" , 4, 6, 705, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ASLPMS" , 10, 2, 705, "RO/WRSL", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 705, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 705, "RO/WRSL", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 705, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 705, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 705, "RO", 0, 0, 0ull, 0ull},
- {"LBNC" , 21, 1, 705, "RO", 0, 0, 0ull, 0ull},
- {"ASPM" , 22, 1, 705, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 705, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 705, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 706, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 706, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"LD" , 4, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 706, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 706, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 706, "RO", 0, 0, 1ull, 1ull},
- {"NLW" , 20, 6, 706, "RO", 0, 0, 1ull, 4ull},
- {"RESERVED_26_26" , 26, 1, 706, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 706, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"DLLA" , 29, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"LBM" , 30, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 706, "RO", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 707, "RO", 0, 0, 15ull, 15ull},
- {"CTDS" , 4, 1, 707, "RO", 0, 0, 1ull, 1ull},
- {"ARI" , 5, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OPS" , 6, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"ATOM32S" , 7, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"ATOM64S" , 8, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"ATOM128S" , 9, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"NOROPRPR" , 10, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"LTRS" , 11, 1, 707, "RO", 0, 0, 0ull, 0ull},
- {"TPHS" , 12, 2, 707, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_17" , 14, 4, 707, "RAZ", 1, 1, 0, 0},
- {"OBFFS" , 18, 2, 707, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 707, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 708, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 708, "R/W", 0, 0, 0ull, 0ull},
- {"ARI" , 5, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP" , 6, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP_EB" , 7, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"ID0_RQ" , 8, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"ID0_CP" , 9, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"LTRE" , 10, 1, 708, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_12" , 11, 2, 708, "RAZ", 1, 1, 0, 0},
- {"OBFFE" , 13, 2, 708, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_31" , 15, 17, 708, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 709, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 709, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 709, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 709, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 710, "R/W", 1, 0, 0, 2ull},
- {"EC" , 4, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 710, "RO", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 710, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 710, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 710, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 710, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_31" , 17, 15, 710, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 711, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 711, "RO", 0, 0, 2ull, 2ull},
- {"NCO" , 20, 12, 711, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 712, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_5_11" , 5, 7, 712, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 712, "RAZ", 1, 1, 0, 0},
- {"UCIES" , 22, 1, 712, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 712, "RAZ", 1, 1, 0, 0},
- {"UATOMBS" , 24, 1, 712, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 712, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 713, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_11" , 5, 7, 713, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 713, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 713, "RAZ", 1, 1, 0, 0},
- {"UCIEM" , 22, 1, 713, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 713, "RAZ", 1, 1, 0, 0},
- {"UATOMBM" , 24, 1, 713, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 713, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 714, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 714, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_5_11" , 5, 7, 714, "RO", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 714, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 714, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 714, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 714, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 714, "RO", 0, 0, 0ull, 0ull},
- {"UCIES" , 22, 1, 714, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 714, "RO", 0, 0, 0ull, 0ull},
- {"UATOMBS" , 24, 1, 714, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 714, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 715, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 715, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 715, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 715, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 715, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 715, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 715, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 715, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIES" , 14, 1, 715, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_31" , 15, 17, 715, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 716, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 716, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 716, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 716, "R/W", 0, 0, 1ull, 1ull},
- {"CIEM" , 14, 1, 716, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_15_31" , 15, 17, 716, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 717, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 717, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 717, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 717, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 717, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 717, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 718, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 719, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 720, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 721, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 722, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 722, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 723, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 724, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_14" , 8, 7, 724, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 724, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 724, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 724, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 724, "R/W", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 725, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 725, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 725, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 725, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 725, "R/W", 0, 0, 3ull, 3ull},
- {"EASPML1" , 30, 1, 725, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 725, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 726, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 726, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 726, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 726, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 726, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 726, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 726, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 726, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 726, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 726, "R/W", 0, 0, 15ull, 1ull},
- {"RESERVED_22_31" , 22, 10, 726, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 727, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 727, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 727, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 727, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 727, "R/W", 0, 0, 0ull, 0ull},
- {"MFUNCN" , 0, 8, 728, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_13" , 8, 6, 728, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 728, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 728, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 728, "R/W", 0, 0, 0ull, 0ull},
- {"CX_NFUNC" , 29, 3, 728, "R/W", 0, 0, 0ull, 0ull},
- {"SKPIV" , 0, 11, 729, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 729, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 729, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 729, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 730, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 730, "R/W", 0, 0, 0ull, 0ull},
- {"M_DABORT_4UCPL" , 2, 1, 730, "R/W", 0, 0, 0ull, 0ull},
- {"M_HANDLE_FLUSH" , 3, 1, 730, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 730, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 731, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 732, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 733, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 733, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 733, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 734, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 734, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 734, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 735, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 735, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 735, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 736, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 736, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 737, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 737, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 737, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 737, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 738, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 738, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 738, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 738, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 739, "RO/WRSL", 0, 0, 56ull, 56ull},
- {"HEADER_CREDITS" , 12, 8, 739, "RO/WRSL", 0, 0, 31ull, 31ull},
- {"RESERVED_20_20" , 20, 1, 739, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 739, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 739, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 739, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 739, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 740, "RO/WRSL", 0, 0, 13ull, 13ull},
- {"HEADER_CREDITS" , 12, 8, 740, "RO/WRSL", 0, 0, 31ull, 31ull},
- {"RESERVED_20_20" , 20, 1, 740, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 740, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 740, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 741, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"HEADER_CREDITS" , 12, 8, 741, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 741, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 741, "RO/WRSL", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 741, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 742, "RO/WRSL", 0, 0, 183ull, 183ull},
- {"RESERVED_14_15" , 14, 2, 742, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 742, "RO/WRSL", 0, 0, 37ull, 37ull},
- {"RESERVED_26_31" , 26, 6, 742, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 743, "RO/WRSL", 0, 0, 97ull, 97ull},
- {"RESERVED_14_15" , 14, 2, 743, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 743, "RO/WRSL", 0, 0, 37ull, 37ull},
- {"RESERVED_26_31" , 26, 6, 743, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 744, "RO/WRSL", 0, 0, 398ull, 398ull},
- {"RESERVED_14_15" , 14, 2, 744, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 744, "RO/WRSL", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 744, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 745, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 745, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 745, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 745, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 746, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 747, "R/W", 0, 0, 0ull, 0ull},
- {"VENDID" , 0, 16, 748, "R/W", 0, 0, 6013ull, 6013ull},
- {"DEVID" , 16, 16, 748, "R/W", 0, 0, 148ull, 148ull},
- {"ISAE" , 0, 1, 749, "R/W", 0, 0, 0ull, 0ull},
- {"MSAE" , 1, 1, 749, "R/W", 0, 0, 0ull, 0ull},
- {"ME" , 2, 1, 749, "R/W", 0, 0, 0ull, 0ull},
- {"SCSE" , 3, 1, 749, "RO", 0, 0, 0ull, 0ull},
- {"MWICE" , 4, 1, 749, "RO", 0, 0, 0ull, 0ull},
- {"VPS" , 5, 1, 749, "RO", 0, 0, 0ull, 0ull},
- {"PER" , 6, 1, 749, "R/W", 0, 0, 0ull, 0ull},
- {"IDS_WCC" , 7, 1, 749, "RO", 0, 0, 0ull, 0ull},
- {"SEE" , 8, 1, 749, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 9, 1, 749, "RO", 0, 0, 0ull, 0ull},
- {"I_DIS" , 10, 1, 749, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_18" , 11, 8, 749, "RAZ", 1, 1, 0, 0},
- {"I_STAT" , 19, 1, 749, "RO", 0, 0, 0ull, 0ull},
- {"CL" , 20, 1, 749, "RO", 0, 0, 1ull, 1ull},
- {"M66" , 21, 1, 749, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 749, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 749, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 749, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 749, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 749, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 749, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 749, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 749, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 749, "R/W1C", 0, 0, 0ull, 0ull},
- {"RID" , 0, 8, 750, "R/W", 0, 0, 8ull, 8ull},
- {"PI" , 8, 8, 750, "R/W", 0, 0, 0ull, 0ull},
- {"SC" , 16, 8, 750, "R/W", 0, 0, 48ull, 48ull},
- {"BCC" , 24, 8, 750, "R/W", 0, 0, 11ull, 11ull},
- {"CLS" , 0, 8, 751, "R/W", 0, 0, 0ull, 0ull},
- {"LT" , 8, 8, 751, "RO", 0, 0, 0ull, 0ull},
- {"CHF" , 16, 7, 751, "RO", 0, 0, 1ull, 1ull},
- {"MFD" , 23, 1, 751, "R/W", 0, 0, 0ull, 0ull},
- {"BIST" , 24, 8, 751, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_31" , 0, 32, 752, "RO", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 753, "RO", 1, 1, 0, 0},
- {"PBNUM" , 0, 8, 754, "R/W", 0, 0, 0ull, 0ull},
- {"SBNUM" , 8, 8, 754, "R/W", 0, 0, 0ull, 0ull},
- {"SUBBNUM" , 16, 8, 754, "R/W", 0, 0, 0ull, 0ull},
- {"SLT" , 24, 8, 754, "RO", 0, 0, 0ull, 0ull},
- {"IO32A" , 0, 1, 755, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 755, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_BASE" , 4, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"IO32B" , 8, 1, 755, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_9_11" , 9, 3, 755, "RAZ", 0, 0, 0ull, 0ull},
- {"LIO_LIMI" , 12, 4, 755, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_20" , 16, 5, 755, "RAZ", 1, 1, 0, 0},
- {"M66" , 21, 1, 755, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_22" , 22, 1, 755, "RO", 1, 1, 0, 0},
- {"FBB" , 23, 1, 755, "RO", 0, 0, 0ull, 0ull},
- {"MDPE" , 24, 1, 755, "R/W1C", 0, 0, 0ull, 0ull},
- {"DEVT" , 25, 2, 755, "RO", 0, 0, 0ull, 0ull},
- {"STA" , 27, 1, 755, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTA" , 28, 1, 755, "R/W1C", 0, 0, 0ull, 0ull},
- {"RMA" , 29, 1, 755, "R/W1C", 0, 0, 0ull, 0ull},
- {"SSE" , 30, 1, 755, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPE" , 31, 1, 755, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 756, "RO", 1, 1, 0, 0},
- {"MB_ADDR" , 4, 12, 756, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_19" , 16, 4, 756, "RO", 1, 1, 0, 0},
- {"ML_ADDR" , 20, 12, 756, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64A" , 0, 1, 757, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_3" , 1, 3, 757, "RO", 1, 1, 0, 0},
- {"LMEM_BASE" , 4, 12, 757, "R/W", 0, 0, 0ull, 0ull},
- {"MEM64B" , 16, 1, 757, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_19" , 17, 3, 757, "RO", 1, 1, 0, 0},
- {"LMEM_LIMIT" , 20, 12, 757, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_BASE" , 0, 32, 758, "R/W", 0, 0, 0ull, 0ull},
- {"UMEM_LIMIT" , 0, 32, 759, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_BASE" , 0, 16, 760, "R/W", 0, 0, 0ull, 0ull},
- {"UIO_LIMIT" , 16, 16, 760, "R/W", 0, 0, 0ull, 0ull},
- {"CP" , 0, 8, 761, "R/W", 0, 0, 64ull, 64ull},
- {"RESERVED_8_31" , 8, 24, 761, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 762, "RAZ", 1, 1, 0, 0},
- {"IL" , 0, 8, 763, "R/W", 0, 0, 255ull, 255ull},
- {"INTA" , 8, 8, 763, "R/W", 0, 0, 1ull, 1ull},
- {"PERE" , 16, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"SEE" , 17, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"ISAE" , 18, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"VGAE" , 19, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"VGA16D" , 20, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"MAM" , 21, 1, 763, "RO", 0, 0, 0ull, 0ull},
- {"SBRST" , 22, 1, 763, "R/W", 0, 0, 0ull, 0ull},
- {"FBBE" , 23, 1, 763, "RO", 0, 0, 0ull, 0ull},
- {"PDT" , 24, 1, 763, "RO", 0, 0, 0ull, 0ull},
- {"SDT" , 25, 1, 763, "RO", 0, 0, 0ull, 0ull},
- {"DTS" , 26, 1, 763, "RO", 0, 0, 0ull, 0ull},
- {"DTSEES" , 27, 1, 763, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 763, "RO", 1, 1, 0, 0},
- {"PMCID" , 0, 8, 764, "RO", 0, 0, 1ull, 1ull},
- {"NCP" , 8, 8, 764, "R/W", 0, 0, 80ull, 80ull},
- {"PMSV" , 16, 3, 764, "R/W", 0, 0, 3ull, 3ull},
- {"PME_CLOCK" , 19, 1, 764, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_20" , 20, 1, 764, "RAZ", 1, 1, 0, 0},
- {"DSI" , 21, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"AUXC" , 22, 3, 764, "R/W", 0, 0, 0ull, 0ull},
- {"D1S" , 25, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"D2S" , 26, 1, 764, "R/W", 0, 0, 0ull, 0ull},
- {"PMES" , 27, 5, 764, "R/W", 0, 0, 0ull, 0ull},
- {"PS" , 0, 2, 765, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 765, "RAZ", 1, 1, 0, 0},
- {"NSR" , 3, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_7" , 4, 4, 765, "RAZ", 1, 1, 0, 0},
- {"PMEENS" , 8, 1, 765, "R/W", 0, 0, 0ull, 0ull},
- {"PMDS" , 9, 4, 765, "RO", 0, 0, 0ull, 0ull},
- {"PMEDSIA" , 13, 2, 765, "RO", 0, 0, 0ull, 0ull},
- {"PMESS" , 15, 1, 765, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_21" , 16, 6, 765, "RAZ", 1, 1, 0, 0},
- {"BD3H" , 22, 1, 765, "RO", 0, 0, 0ull, 0ull},
- {"BPCCEE" , 23, 1, 765, "RO", 0, 0, 0ull, 0ull},
- {"PMDIA" , 24, 8, 765, "RO", 0, 0, 0ull, 0ull},
- {"MSICID" , 0, 8, 766, "RO", 0, 0, 5ull, 5ull},
- {"NCP" , 8, 8, 766, "R/W", 0, 0, 112ull, 112ull},
- {"MSIEN" , 16, 1, 766, "R/W", 0, 0, 0ull, 0ull},
- {"MMC" , 17, 3, 766, "R/W", 0, 0, 0ull, 0ull},
- {"MME" , 20, 3, 766, "R/W", 0, 0, 0ull, 0ull},
- {"M64" , 23, 1, 766, "R/W", 0, 0, 1ull, 1ull},
- {"PVM" , 24, 1, 766, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 766, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_1" , 0, 2, 767, "RAZ", 1, 1, 0, 0},
- {"LMSI" , 2, 30, 767, "R/W", 0, 0, 0ull, 0ull},
- {"UMSI" , 0, 32, 768, "R/W", 0, 0, 0ull, 0ull},
- {"MSIMD" , 0, 16, 769, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 769, "RAZ", 1, 1, 0, 0},
- {"PCIEID" , 0, 8, 770, "RO", 0, 0, 16ull, 16ull},
- {"NCP" , 8, 8, 770, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"PCIECV" , 16, 4, 770, "RO", 0, 0, 2ull, 2ull},
- {"DPT" , 20, 4, 770, "RO", 0, 0, 4ull, 4ull},
- {"SI" , 24, 1, 770, "R/W", 0, 0, 0ull, 0ull},
- {"IMN" , 25, 5, 770, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_30_31" , 30, 2, 770, "RAZ", 1, 1, 0, 0},
- {"MPSS" , 0, 3, 771, "R/W", 0, 0, 1ull, 1ull},
- {"PFS" , 3, 2, 771, "R/W", 0, 0, 0ull, 0ull},
- {"ETFS" , 5, 1, 771, "R/W", 0, 0, 0ull, 0ull},
- {"EL0AL" , 6, 3, 771, "R/W", 0, 0, 0ull, 0ull},
- {"EL1AL" , 9, 3, 771, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_14" , 12, 3, 771, "RAZ", 1, 1, 0, 0},
- {"RBER" , 15, 1, 771, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_16_17" , 16, 2, 771, "RAZ", 1, 1, 0, 0},
- {"CSPLV" , 18, 8, 771, "RO", 0, 0, 0ull, 0ull},
- {"CSPLS" , 26, 2, 771, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 771, "RAZ", 1, 1, 0, 0},
- {"CE_EN" , 0, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"NFE_EN" , 1, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"FE_EN" , 2, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"UR_EN" , 3, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"RO_EN" , 4, 1, 772, "R/W", 0, 0, 1ull, 1ull},
- {"MPS" , 5, 3, 772, "R/W", 0, 0, 0ull, 0ull},
- {"ETF_EN" , 8, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 9, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"AP_EN" , 10, 1, 772, "R/W", 0, 0, 0ull, 0ull},
- {"NS_EN" , 11, 1, 772, "R/W", 0, 0, 1ull, 1ull},
- {"MRRS" , 12, 3, 772, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_15_15" , 15, 1, 772, "RAZ", 1, 1, 0, 0},
- {"CE_D" , 16, 1, 772, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFE_D" , 17, 1, 772, "R/W1C", 0, 0, 0ull, 0ull},
- {"FE_D" , 18, 1, 772, "R/W1C", 0, 0, 0ull, 0ull},
- {"UR_D" , 19, 1, 772, "R/W1C", 0, 0, 0ull, 0ull},
- {"AP_D" , 20, 1, 772, "RO", 0, 0, 0ull, 0ull},
- {"TP" , 21, 1, 772, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_31" , 22, 10, 772, "RAZ", 1, 1, 0, 0},
- {"MLS" , 0, 4, 773, "R/W", 1, 1, 0, 0},
- {"MLW" , 4, 6, 773, "R/W", 1, 1, 0, 0},
- {"ASLPMS" , 10, 2, 773, "R/W", 0, 0, 3ull, 3ull},
- {"L0EL" , 12, 3, 773, "R/W", 0, 0, 6ull, 6ull},
- {"L1EL" , 15, 3, 773, "R/W", 0, 0, 6ull, 6ull},
- {"CPM" , 18, 1, 773, "R/W", 0, 0, 0ull, 0ull},
- {"SDERC" , 19, 1, 773, "RO", 0, 0, 0ull, 0ull},
- {"DLLARC" , 20, 1, 773, "RO", 0, 0, 1ull, 1ull},
- {"LBNC" , 21, 1, 773, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"ASPM" , 22, 1, 773, "RO/WRSL", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 773, "RAZ", 1, 1, 0, 0},
- {"PNUM" , 24, 8, 773, "RO/WRSL", 0, 0, 0ull, 0ull},
- {"ASLPC" , 0, 2, 774, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_2" , 2, 1, 774, "RAZ", 1, 1, 0, 0},
- {"RCB" , 3, 1, 774, "R/W", 0, 0, 1ull, 1ull},
- {"LD" , 4, 1, 774, "R/W", 0, 0, 0ull, 0ull},
- {"RL" , 5, 1, 774, "R/W", 0, 0, 0ull, 0ull},
- {"CCC" , 6, 1, 774, "R/W", 0, 0, 0ull, 0ull},
- {"ES" , 7, 1, 774, "R/W", 0, 0, 0ull, 0ull},
- {"ECPM" , 8, 1, 774, "R/W", 0, 0, 0ull, 0ull},
- {"HAWD" , 9, 1, 774, "R/W", 0, 0, 0ull, 0ull},
- {"LBM_INT_ENB" , 10, 1, 774, "R/W", 0, 0, 0ull, 0ull},
- {"LAB_INT_ENB" , 11, 1, 774, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 774, "RAZ", 1, 1, 0, 0},
- {"LS" , 16, 4, 774, "RO", 1, 1, 0, 0},
- {"NLW" , 20, 6, 774, "RO", 0, 0, 1ull, 4ull},
- {"RESERVED_26_26" , 26, 1, 774, "RAZ", 1, 1, 0, 0},
- {"LT" , 27, 1, 774, "RO", 0, 0, 0ull, 0ull},
- {"SCC" , 28, 1, 774, "R/W", 0, 0, 1ull, 0ull},
- {"DLLA" , 29, 1, 774, "RO", 0, 0, 0ull, 1ull},
- {"LBM" , 30, 1, 774, "R/W1C", 0, 0, 0ull, 0ull},
- {"LAB" , 31, 1, 774, "R/W1C", 0, 0, 0ull, 0ull},
- {"ABP" , 0, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"PCP" , 1, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"MRLSP" , 2, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"AIP" , 3, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"PIP" , 4, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"HP_S" , 5, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"HP_C" , 6, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LV" , 7, 8, 775, "R/W", 0, 0, 0ull, 0ull},
- {"SP_LS" , 15, 2, 775, "R/W", 0, 0, 0ull, 0ull},
- {"EMIP" , 17, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"NCCS" , 18, 1, 775, "R/W", 0, 0, 0ull, 0ull},
- {"PS_NUM" , 19, 13, 775, "R/W", 0, 0, 0ull, 0ull},
- {"ABP_EN" , 0, 1, 776, "R/W", 0, 0, 0ull, 0ull},
- {"PF_EN" , 1, 1, 776, "R/W", 0, 0, 0ull, 0ull},
- {"MRLS_EN" , 2, 1, 776, "R/W", 0, 0, 0ull, 0ull},
- {"PD_EN" , 3, 1, 776, "R/W", 0, 0, 0ull, 0ull},
- {"CCINT_EN" , 4, 1, 776, "R/W", 0, 0, 0ull, 0ull},
- {"HPINT_EN" , 5, 1, 776, "R/W", 0, 0, 0ull, 0ull},
- {"AIC" , 6, 2, 776, "R/W", 0, 0, 3ull, 3ull},
- {"PIC" , 8, 2, 776, "R/W", 0, 0, 3ull, 3ull},
- {"PCC" , 10, 1, 776, "R/W", 0, 0, 0ull, 0ull},
- {"EMIC" , 11, 1, 776, "R/W", 0, 0, 0ull, 0ull},
- {"DLLS_EN" , 12, 1, 776, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 776, "RAZ", 1, 1, 0, 0},
- {"ABP_D" , 16, 1, 776, "R/W1C", 0, 0, 0ull, 0ull},
- {"PF_D" , 17, 1, 776, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLS_C" , 18, 1, 776, "R/W1C", 0, 0, 0ull, 0ull},
- {"PD_C" , 19, 1, 776, "R/W1C", 0, 0, 0ull, 0ull},
- {"CCINT_D" , 20, 1, 776, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRLSS" , 21, 1, 776, "RO", 0, 0, 0ull, 0ull},
- {"PDS" , 22, 1, 776, "RO", 0, 0, 1ull, 1ull},
- {"EMIS" , 23, 1, 776, "RO", 0, 0, 0ull, 0ull},
- {"DLLS_C" , 24, 1, 776, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 776, "RAZ", 1, 1, 0, 0},
- {"SECEE" , 0, 1, 777, "R/W", 0, 0, 0ull, 0ull},
- {"SENFEE" , 1, 1, 777, "R/W", 0, 0, 0ull, 0ull},
- {"SEFEE" , 2, 1, 777, "R/W", 0, 0, 0ull, 0ull},
- {"PMEIE" , 3, 1, 777, "R/W", 0, 0, 0ull, 0ull},
- {"CRSSVE" , 4, 1, 777, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_15" , 5, 11, 777, "RAZ", 1, 1, 0, 0},
- {"CRSSV" , 16, 1, 777, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_31" , 17, 15, 777, "RAZ", 1, 1, 0, 0},
- {"PME_RID" , 0, 16, 778, "RO", 0, 0, 0ull, 0ull},
- {"PME_STAT" , 16, 1, 778, "R/W1C", 0, 0, 0ull, 0ull},
- {"PME_PEND" , 17, 1, 778, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 778, "RAZ", 0, 0, 0ull, 0ull},
- {"CTRS" , 0, 4, 779, "RO", 0, 0, 15ull, 15ull},
- {"CTDS" , 4, 1, 779, "RO", 0, 0, 1ull, 1ull},
- {"ARI_FW" , 5, 1, 779, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OPS" , 6, 1, 779, "RO", 0, 0, 0ull, 0ull},
- {"ATOM32S" , 7, 1, 779, "RO", 0, 0, 0ull, 0ull},
- {"ATOM64S" , 8, 1, 779, "RO", 0, 0, 0ull, 0ull},
- {"ATOM128S" , 9, 1, 779, "RO", 0, 0, 0ull, 0ull},
- {"NOROPRPR" , 10, 1, 779, "RO", 0, 0, 1ull, 1ull},
- {"LTRS" , 11, 1, 779, "RO", 0, 0, 0ull, 0ull},
- {"TPHS" , 12, 2, 779, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_14_17" , 14, 4, 779, "RAZ", 1, 1, 0, 0},
- {"OBFFS" , 18, 2, 779, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 779, "RAZ", 1, 1, 0, 0},
- {"CTV" , 0, 4, 780, "RO", 0, 0, 0ull, 0ull},
- {"CTD" , 4, 1, 780, "R/W", 0, 0, 0ull, 0ull},
- {"ARI" , 5, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP" , 6, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"ATOM_OP_EB" , 7, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"ID0_RQ" , 8, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"ID0_CP" , 9, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"LTRE" , 10, 1, 780, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_11_12" , 11, 2, 780, "RAZ", 1, 1, 0, 0},
- {"OBFFE" , 13, 2, 780, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_15_31" , 15, 17, 780, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_0" , 0, 1, 781, "RAZ", 1, 1, 0, 0},
- {"SLSV" , 1, 7, 781, "RO/WRSL", 1, 1, 0, 0},
- {"CLS" , 8, 1, 781, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 781, "RAZ", 1, 1, 0, 0},
- {"TLS" , 0, 4, 782, "R/W", 1, 1, 0, 0},
- {"EC" , 4, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"HASD" , 5, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"SDE" , 6, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"TM" , 7, 3, 782, "R/W", 0, 0, 0ull, 0ull},
- {"EMC" , 10, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"CSOS" , 11, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"CDE" , 12, 1, 782, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 782, "RAZ", 1, 1, 0, 0},
- {"CDL" , 16, 1, 782, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_17_31" , 17, 15, 782, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 783, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 784, "RAZ", 1, 1, 0, 0},
- {"PCIEEC" , 0, 16, 785, "RO", 0, 0, 1ull, 1ull},
- {"CV" , 16, 4, 785, "RO", 0, 0, 2ull, 2ull},
- {"NCO" , 20, 12, 785, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 786, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"SDES" , 5, 1, 786, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 786, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"CTS" , 14, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"MTLPS" , 18, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRCES" , 19, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 786, "RAZ", 1, 1, 0, 0},
- {"UCIES" , 22, 1, 786, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 786, "RAZ", 1, 1, 0, 0},
- {"UATOMBS" , 24, 1, 786, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 786, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 787, "RAZ", 1, 1, 0, 0},
- {"DLPEM" , 4, 1, 787, "R/W", 0, 0, 0ull, 0ull},
- {"SDEM" , 5, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 787, "RAZ", 1, 1, 0, 0},
- {"PTLPM" , 12, 1, 787, "R/W", 0, 0, 0ull, 0ull},
- {"FCPEM" , 13, 1, 787, "R/W", 0, 0, 0ull, 0ull},
- {"CTM" , 14, 1, 787, "R/W", 0, 0, 0ull, 0ull},
- {"CAM" , 15, 1, 787, "R/W", 0, 0, 0ull, 0ull},
- {"UCM" , 16, 1, 787, "R/W", 0, 0, 0ull, 0ull},
- {"ROM" , 17, 1, 787, "R/W", 0, 0, 0ull, 0ull},
- {"MTLPM" , 18, 1, 787, "R/W", 0, 0, 0ull, 0ull},
- {"ECRCEM" , 19, 1, 787, "R/W", 0, 0, 0ull, 0ull},
- {"UREM" , 20, 1, 787, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 787, "RAZ", 1, 1, 0, 0},
- {"UCIEM" , 22, 1, 787, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 787, "RAZ", 1, 1, 0, 0},
- {"UATOMBM" , 24, 1, 787, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 787, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 788, "RAZ", 1, 1, 0, 0},
- {"DLPES" , 4, 1, 788, "R/W", 0, 0, 1ull, 1ull},
- {"SDES" , 5, 1, 788, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_6_11" , 6, 6, 788, "RAZ", 1, 1, 0, 0},
- {"PTLPS" , 12, 1, 788, "R/W", 0, 0, 0ull, 0ull},
- {"FCPES" , 13, 1, 788, "R/W", 0, 0, 1ull, 1ull},
- {"CTS" , 14, 1, 788, "R/W", 0, 0, 0ull, 0ull},
- {"CAS" , 15, 1, 788, "R/W", 0, 0, 0ull, 0ull},
- {"UCS" , 16, 1, 788, "R/W", 0, 0, 0ull, 0ull},
- {"ROS" , 17, 1, 788, "R/W", 0, 0, 1ull, 1ull},
- {"MTLPS" , 18, 1, 788, "R/W", 0, 0, 1ull, 1ull},
- {"ECRCES" , 19, 1, 788, "R/W", 0, 0, 0ull, 0ull},
- {"URES" , 20, 1, 788, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_21" , 21, 1, 788, "RO", 0, 0, 0ull, 0ull},
- {"UCIES" , 22, 1, 788, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_23_23" , 23, 1, 788, "RO", 0, 0, 0ull, 0ull},
- {"UATOMBS" , 24, 1, 788, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_25_31" , 25, 7, 788, "RAZ", 1, 1, 0, 0},
- {"RES" , 0, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 789, "RAZ", 1, 1, 0, 0},
- {"BTLPS" , 6, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"BDLLPS" , 7, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNRS" , 8, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 789, "RAZ", 1, 1, 0, 0},
- {"RTTS" , 12, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"ANFES" , 13, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIES" , 14, 1, 789, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_15_31" , 15, 17, 789, "RAZ", 1, 1, 0, 0},
- {"REM" , 0, 1, 790, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_5" , 1, 5, 790, "RAZ", 1, 1, 0, 0},
- {"BTLPM" , 6, 1, 790, "R/W", 0, 0, 0ull, 0ull},
- {"BDLLPM" , 7, 1, 790, "R/W", 0, 0, 0ull, 0ull},
- {"RNRM" , 8, 1, 790, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 790, "RAZ", 1, 1, 0, 0},
- {"RTTM" , 12, 1, 790, "R/W", 0, 0, 0ull, 0ull},
- {"ANFEM" , 13, 1, 790, "R/W", 0, 0, 1ull, 1ull},
- {"CIEM" , 14, 1, 790, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_15_31" , 15, 17, 790, "RAZ", 1, 1, 0, 0},
- {"FEP" , 0, 5, 791, "RO", 0, 0, 0ull, 0ull},
- {"GC" , 5, 1, 791, "RO", 0, 0, 1ull, 1ull},
- {"GE" , 6, 1, 791, "R/W", 0, 0, 0ull, 0ull},
- {"CC" , 7, 1, 791, "RO", 0, 0, 1ull, 1ull},
- {"CE" , 8, 1, 791, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_31" , 9, 23, 791, "RAZ", 1, 1, 0, 0},
- {"DWORD1" , 0, 32, 792, "RO", 0, 0, 0ull, 0ull},
- {"DWORD2" , 0, 32, 793, "RO", 0, 0, 0ull, 0ull},
- {"DWORD3" , 0, 32, 794, "RO", 0, 0, 0ull, 0ull},
- {"DWORD4" , 0, 32, 795, "RO", 0, 0, 0ull, 0ull},
- {"CERE" , 0, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"NFERE" , 1, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"FERE" , 2, 1, 796, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 796, "RAZ", 1, 1, 0, 0},
- {"ECR" , 0, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_ECR" , 1, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"EFNFR" , 2, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"MULTI_EFNFR" , 3, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"FUF" , 4, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"NFEMR" , 5, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEMR" , 6, 1, 797, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_26" , 7, 20, 797, "RAZ", 1, 1, 0, 0},
- {"AEIMN" , 27, 5, 797, "R/W", 0, 0, 0ull, 0ull},
- {"ECSI" , 0, 16, 798, "RO", 0, 0, 0ull, 0ull},
- {"EFNFSI" , 16, 16, 798, "RO", 0, 0, 0ull, 0ull},
- {"RTLTL" , 0, 16, 799, "R/W", 0, 1, 4143ull, 0},
- {"RTL" , 16, 16, 799, "R/W", 0, 1, 12429ull, 0},
- {"OMR" , 0, 32, 800, "R/W", 0, 1, 4294967295ull, 0},
- {"LINK_NUM" , 0, 8, 801, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_8_14" , 8, 7, 801, "RAZ", 1, 1, 0, 0},
- {"FORCE_LINK" , 15, 1, 801, "R/W", 0, 0, 0ull, 0ull},
- {"LINK_STATE" , 16, 6, 801, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 801, "RAZ", 1, 1, 0, 0},
- {"LPEC" , 24, 8, 801, "RO", 0, 0, 7ull, 7ull},
- {"ACK_FREQ" , 0, 8, 802, "R/W", 0, 0, 0ull, 0ull},
- {"N_FTS" , 8, 8, 802, "R/W", 0, 0, 128ull, 128ull},
- {"N_FTS_CC" , 16, 8, 802, "R/W", 0, 0, 128ull, 128ull},
- {"L0EL" , 24, 3, 802, "R/W", 0, 0, 3ull, 3ull},
- {"L1EL" , 27, 3, 802, "R/W", 0, 0, 3ull, 3ull},
- {"EASPML1" , 30, 1, 802, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 802, "RAZ", 1, 1, 0, 0},
- {"OMR" , 0, 1, 803, "R/W", 0, 0, 0ull, 0ull},
- {"SD" , 1, 1, 803, "R/W", 0, 0, 0ull, 0ull},
- {"LE" , 2, 1, 803, "R/W", 0, 0, 0ull, 0ull},
- {"RA" , 3, 1, 803, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 803, "RAZ", 1, 1, 0, 0},
- {"DLLLE" , 5, 1, 803, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 803, "RAZ", 1, 1, 0, 0},
- {"FLM" , 7, 1, 803, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_15" , 8, 8, 803, "RO", 0, 0, 1ull, 1ull},
- {"LME" , 16, 6, 803, "R/W", 0, 0, 15ull, 3ull},
- {"RESERVED_22_31" , 22, 10, 803, "RAZ", 1, 1, 0, 0},
- {"ILST" , 0, 24, 804, "R/W", 0, 0, 0ull, 0ull},
- {"FCD" , 24, 1, 804, "R/W", 0, 0, 0ull, 0ull},
- {"ACK_NAK" , 25, 1, 804, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_26_30" , 26, 5, 804, "RAZ", 1, 1, 0, 0},
- {"DLLD" , 31, 1, 804, "R/W", 0, 0, 0ull, 0ull},
- {"MFUNCN" , 0, 8, 805, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_13" , 8, 6, 805, "RAZ", 1, 1, 0, 0},
- {"TMRT" , 14, 5, 805, "R/W", 0, 0, 8ull, 8ull},
- {"TMANLT" , 19, 5, 805, "R/W", 0, 0, 0ull, 0ull},
- {"TMFCWT" , 24, 5, 805, "R/W", 0, 0, 0ull, 0ull},
- {"CX_NFUNC" , 29, 3, 805, "R/W", 0, 0, 0ull, 0ull},
- {"SKPIV" , 0, 11, 806, "R/W", 0, 0, 1280ull, 1280ull},
- {"RESERVED_11_14" , 11, 4, 806, "RAZ", 1, 1, 0, 0},
- {"DFCWT" , 15, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_FUN" , 16, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_POIS_FILT" , 17, 1, 806, "R/W", 0, 0, 1ull, 1ull},
- {"M_BAR_MATCH" , 18, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG1_FILT" , 19, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_LK_FILT" , 20, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TAG_ERR" , 21, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_RID_ERR" , 22, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_FUN_ERR" , 23, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_TC_ERR" , 24, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ATTR_ERR" , 25, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_LEN_ERR" , 26, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_ECRC_FILT" , 27, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_CPL_ECRC_FILT" , 28, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"MSG_CTRL" , 29, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_IO_FILT" , 30, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_CFG0_FILT" , 31, 1, 806, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND0_DRP" , 0, 1, 807, "R/W", 0, 0, 0ull, 0ull},
- {"M_VEND1_DRP" , 1, 1, 807, "R/W", 0, 0, 0ull, 0ull},
- {"M_DABORT_4UCPL" , 2, 1, 807, "R/W", 0, 0, 0ull, 0ull},
- {"M_HANDLE_FLUSH" , 3, 1, 807, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_31" , 4, 28, 807, "RAZ", 1, 1, 0, 0},
- {"DBG_INFO_L32" , 0, 32, 808, "RO", 0, 0, 0ull, 0ull},
- {"DBG_INFO_U32" , 0, 32, 809, "RO", 0, 0, 0ull, 0ull},
- {"TPDFCC" , 0, 12, 810, "RO", 0, 0, 0ull, 0ull},
- {"TPHFCC" , 12, 8, 810, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 810, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 811, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 811, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 811, "RAZ", 1, 1, 0, 0},
- {"TCDFCC" , 0, 12, 812, "RO", 0, 0, 0ull, 0ull},
- {"TCHFCC" , 12, 8, 812, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_31" , 20, 12, 812, "RAZ", 1, 1, 0, 0},
- {"RTLPFCCNR" , 0, 1, 813, "RO", 0, 0, 0ull, 0ull},
- {"TRBNE" , 1, 1, 813, "RO", 0, 0, 0ull, 0ull},
- {"RQNE" , 2, 1, 813, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 813, "RAZ", 1, 1, 0, 0},
- {"WRR_VC0" , 0, 8, 814, "RO", 0, 0, 15ull, 15ull},
- {"WRR_VC1" , 8, 8, 814, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC2" , 16, 8, 814, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC3" , 24, 8, 814, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC4" , 0, 8, 815, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC5" , 8, 8, 815, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC6" , 16, 8, 815, "RO", 0, 0, 0ull, 0ull},
- {"WRR_VC7" , 24, 8, 815, "RO", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 816, "R/W", 0, 0, 56ull, 56ull},
- {"HEADER_CREDITS" , 12, 8, 816, "R/W", 0, 0, 31ull, 31ull},
- {"RESERVED_20_20" , 20, 1, 816, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 816, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_29" , 24, 6, 816, "RAZ", 1, 1, 0, 0},
- {"TYPE_ORDERING" , 30, 1, 816, "R/W", 0, 0, 1ull, 1ull},
- {"RX_QUEUE_ORDER" , 31, 1, 816, "R/W", 0, 0, 0ull, 0ull},
- {"DATA_CREDITS" , 0, 12, 817, "R/W", 0, 0, 13ull, 13ull},
- {"HEADER_CREDITS" , 12, 8, 817, "R/W", 0, 0, 31ull, 31ull},
- {"RESERVED_20_20" , 20, 1, 817, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 817, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 817, "RAZ", 1, 1, 0, 0},
- {"DATA_CREDITS" , 0, 12, 818, "R/W", 0, 0, 128ull, 128ull},
- {"HEADER_CREDITS" , 12, 8, 818, "R/W", 0, 0, 96ull, 96ull},
- {"RESERVED_20_20" , 20, 1, 818, "RAZ", 1, 1, 0, 0},
- {"QUEUE_MODE" , 21, 3, 818, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_24_31" , 24, 8, 818, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 819, "R/W", 0, 0, 183ull, 183ull},
- {"RESERVED_14_15" , 14, 2, 819, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 819, "R/W", 0, 0, 37ull, 37ull},
- {"RESERVED_26_31" , 26, 6, 819, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 820, "R/W", 0, 0, 97ull, 97ull},
- {"RESERVED_14_15" , 14, 2, 820, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 820, "R/W", 0, 0, 37ull, 37ull},
- {"RESERVED_26_31" , 26, 6, 820, "RAZ", 1, 1, 0, 0},
- {"DATA_DEPTH" , 0, 14, 821, "R/W", 0, 0, 398ull, 398ull},
- {"RESERVED_14_15" , 14, 2, 821, "RAZ", 1, 1, 0, 0},
- {"HEADER_DEPTH" , 16, 10, 821, "R/W", 0, 0, 102ull, 102ull},
- {"RESERVED_26_31" , 26, 6, 821, "RAZ", 1, 1, 0, 0},
- {"N_FTS" , 0, 8, 822, "R/W", 0, 0, 128ull, 128ull},
- {"LE" , 8, 9, 822, "R/W", 0, 0, 8ull, 8ull},
- {"DSC" , 17, 1, 822, "R/W", 0, 0, 0ull, 0ull},
- {"CPYTS" , 18, 1, 822, "R/W", 0, 0, 0ull, 0ull},
- {"CTCRB" , 19, 1, 822, "R/W", 0, 0, 0ull, 0ull},
- {"S_D_E" , 20, 1, 822, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_31" , 21, 11, 822, "RAZ", 1, 1, 0, 0},
- {"PHY_STAT" , 0, 32, 823, "RO", 0, 0, 0ull, 0ull},
- {"PHY_CTRL" , 0, 32, 824, "R/W", 0, 0, 0ull, 0ull},
- {"THRESH" , 0, 4, 825, "R/W", 0, 0, 0ull, 8ull},
- {"FETCHSIZ" , 4, 4, 825, "R/W", 0, 0, 0ull, 7ull},
- {"TXRD" , 8, 10, 825, "R/W", 0, 0, 0ull, 1ull},
- {"USELDT" , 18, 1, 825, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 825, "RAZ", 1, 1, 0, 0},
- {"RXST" , 20, 10, 825, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_30_31" , 30, 2, 825, "RAZ", 1, 1, 0, 0},
- {"TXSLOTS" , 32, 10, 825, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_42_43" , 42, 2, 825, "RAZ", 1, 1, 0, 0},
- {"RXSLOTS" , 44, 10, 825, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_62" , 54, 9, 825, "RAZ", 1, 1, 0, 0},
- {"RDPEND" , 63, 1, 825, "RO", 0, 0, 0ull, 0ull},
- {"FSYNCMISSED" , 0, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"FSYNCEXTRA" , 1, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"RXWRAP" , 2, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"RXST" , 3, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"TXWRAP" , 4, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"TXRD" , 5, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"TXEMPTY" , 6, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"RXOVF" , 7, 1, 826, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_8_63" , 8, 56, 826, "RAZ", 1, 1, 0, 0},
- {"FSYNCMISSED" , 0, 1, 827, "R/W1C", 0, 0, 0ull, 0ull},
- {"FSYNCEXTRA" , 1, 1, 827, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXWRAP" , 2, 1, 827, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXST" , 3, 1, 827, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXWRAP" , 4, 1, 827, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXRD" , 5, 1, 827, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXEMPTY" , 6, 1, 827, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXOVF" , 7, 1, 827, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 827, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 36, 828, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 828, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 829, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 829, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 830, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 831, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 832, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 833, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 834, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 835, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 836, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 837, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 838, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 838, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 838, "RAZ", 1, 1, 0, 0},
- {"ENABLE" , 0, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"USECLK1" , 1, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"LSBFIRST" , 2, 1, 839, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_31" , 3, 29, 839, "RAZ", 1, 1, 0, 0},
- {"SAMPPT" , 32, 16, 839, "R/W", 0, 1, 0ull, 0},
- {"DRVTIM" , 48, 16, 839, "R/W", 0, 1, 0ull, 0},
- {"DEBUGINFO" , 0, 64, 840, "RO", 1, 1, 0, 0},
- {"FRAM" , 0, 3, 841, "R/W", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 841, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 841, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 16, 842, "R/W", 1, 1, 0, 0},
- {"RESERVED_16_63" , 16, 48, 842, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 64, 843, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 844, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 845, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 846, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 847, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 848, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 849, "R/W", 1, 1, 0, 0},
- {"MASK" , 0, 64, 850, "R/W", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 851, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 33, 851, "R/W", 1, 1, 0, 0},
- {"RESERVED_36_63" , 36, 28, 851, "RAZ", 1, 1, 0, 0},
- {"ENA" , 0, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"FSYNCPOL" , 1, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"BCLKPOL" , 2, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"BITLEN" , 3, 2, 852, "R/W", 0, 0, 0ull, 0ull},
- {"EXTRABIT" , 5, 1, 852, "R/W", 0, 0, 0ull, 0ull},
- {"NUMSLOTS" , 6, 10, 852, "R/W", 0, 1, 0ull, 0},
- {"FSYNCLOC" , 16, 5, 852, "R/W", 0, 0, 0ull, 0ull},
- {"FSYNCLEN" , 21, 5, 852, "R/W", 0, 0, 0ull, 2ull},
- {"RESERVED_26_31" , 26, 6, 852, "RAZ", 1, 1, 0, 0},
- {"FSYNCSAMP" , 32, 16, 852, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_62" , 48, 15, 852, "RAZ", 1, 1, 0, 0},
- {"FSYNCGOOD" , 63, 1, 852, "RO", 0, 0, 0ull, 1ull},
- {"DEBUGINFO" , 0, 64, 853, "RO", 1, 1, 0, 0},
- {"N" , 0, 32, 854, "R/W", 0, 1, 0ull, 0},
- {"NUMSAMP" , 32, 16, 854, "R/W", 0, 1, 0ull, 0},
- {"DELTASAMP" , 48, 16, 854, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 855, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 855, "R/W", 0, 0, 1ull, 1ull},
- {"HFD" , 6, 1, 855, "R/W", 0, 0, 1ull, 1ull},
- {"PAUSE" , 7, 2, 855, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 855, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 855, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 855, "RAZ", 0, 0, 0ull, 0ull},
- {"NP" , 15, 1, 855, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 855, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_11" , 0, 12, 856, "RO", 0, 0, 0ull, 0ull},
- {"THOU_THD" , 12, 1, 856, "RO", 0, 0, 0ull, 0ull},
- {"THOU_TFD" , 13, 1, 856, "RO", 0, 0, 0ull, 0ull},
- {"THOU_XHD" , 14, 1, 856, "RO", 0, 0, 1ull, 1ull},
- {"THOU_XFD" , 15, 1, 856, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 856, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 857, "RAZ", 0, 0, 0ull, 0ull},
- {"FD" , 5, 1, 857, "RO", 0, 0, 0ull, 0ull},
- {"HFD" , 6, 1, 857, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 7, 2, 857, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_9_11" , 9, 3, 857, "RAZ", 0, 0, 0ull, 0ull},
- {"REM_FLT" , 12, 2, 857, "RO", 0, 0, 0ull, 0ull},
- {"ACK" , 14, 1, 857, "RO", 0, 1, 0ull, 0},
- {"NP" , 15, 1, 857, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 857, "RAZ", 1, 1, 0, 0},
- {"LINK_OK" , 0, 1, 858, "RO", 0, 0, 0ull, 0ull},
- {"DUP" , 1, 1, 858, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 2, 1, 858, "RO", 0, 0, 0ull, 1ull},
- {"SPD" , 3, 2, 858, "RO", 0, 0, 0ull, 0ull},
- {"PAUSE" , 5, 2, 858, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 858, "RAZ", 1, 1, 0, 0},
- {"LNKSPD_EN" , 0, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"XMIT_EN" , 1, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"AN_ERR_EN" , 2, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFU_EN" , 3, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"TXFIFO_EN" , 4, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"TXBAD_EN" , 5, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"RXERR_EN" , 6, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"RXBAD_EN" , 7, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"RXLOCK_EN" , 8, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"AN_BAD_EN" , 9, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"SYNC_BAD_EN" , 10, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"DUP" , 11, 1, 859, "R/W", 0, 0, 0ull, 1ull},
- {"DBG_SYNC_EN" , 12, 1, 859, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 859, "RAZ", 1, 1, 0, 0},
- {"LNKSPD" , 0, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"XMIT" , 1, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_ERR" , 2, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFU" , 3, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXFIFO" , 4, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"TXBAD" , 5, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXERR" , 6, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXBAD" , 7, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"RXLOCK" , 8, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 9, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 10, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"DUP" , 11, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBG_SYNC" , 12, 1, 860, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 860, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 16, 861, "R/W", 0, 1, 1094ull, 0},
- {"RESERVED_16_63" , 16, 48, 861, "RAZ", 1, 1, 0, 0},
- {"PKT_SZ" , 0, 2, 862, "R/W", 0, 0, 0ull, 0ull},
- {"LA_EN" , 2, 1, 862, "R/W", 0, 0, 0ull, 0ull},
- {"LAFIFOVFL" , 3, 1, 862, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 862, "RAZ", 1, 1, 0, 0},
- {"SAMP_PT" , 0, 7, 863, "R/W", 0, 1, 1ull, 0},
- {"AN_OVRD" , 7, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"MODE" , 8, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"MAC_PHY" , 9, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK2" , 10, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"GMXENO" , 11, 1, 863, "R/W", 0, 0, 0ull, 0ull},
- {"SGMII" , 12, 1, 863, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 863, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 864, "RAZ", 1, 1, 0, 0},
- {"UNI" , 5, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"SPDMSB" , 6, 1, 864, "R/W", 0, 0, 1ull, 1ull},
- {"COLTST" , 7, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"DUP" , 8, 1, 864, "R/W", 0, 0, 1ull, 1ull},
- {"RST_AN" , 9, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 864, "RAZ", 1, 1, 0, 0},
- {"PWR_DN" , 11, 1, 864, "R/W", 0, 0, 1ull, 0ull},
- {"AN_EN" , 12, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"SPDLSB" , 13, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"LOOPBCK1" , 14, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 15, 1, 864, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 864, "RAZ", 1, 1, 0, 0},
- {"EXTND" , 0, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 865, "RAZ", 0, 0, 0ull, 0ull},
- {"LNK_ST" , 2, 1, 865, "RO", 0, 0, 0ull, 1ull},
- {"AN_ABIL" , 3, 1, 865, "RO", 0, 0, 1ull, 1ull},
- {"RM_FLT" , 4, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"AN_CPT" , 5, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"PRB_SUP" , 6, 1, 865, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_7_7" , 7, 1, 865, "RAZ", 0, 0, 0ull, 0ull},
- {"EXT_ST" , 8, 1, 865, "RO", 0, 0, 1ull, 1ull},
- {"HUN_T2HD" , 9, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T2FD" , 10, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"TEN_HD" , 11, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"TEN_FD" , 12, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XHD" , 13, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"HUN_XFD" , 14, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"HUN_T4" , 15, 1, 865, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 865, "RAZ", 1, 1, 0, 0},
- {"AN_ST" , 0, 4, 866, "RO", 0, 0, 0ull, 0ull},
- {"AN_BAD" , 4, 1, 866, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 5, 4, 866, "RO", 0, 0, 0ull, 0ull},
- {"SYNC_BAD" , 9, 1, 866, "RO", 0, 0, 0ull, 0ull},
- {"RX_ST" , 10, 5, 866, "RO", 0, 0, 0ull, 0ull},
- {"RX_BAD" , 15, 1, 866, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 866, "RAZ", 1, 1, 0, 0},
- {"BIT_LOCK" , 0, 1, 867, "RO", 0, 0, 0ull, 0ull},
- {"SYNC" , 1, 1, 867, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 867, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 868, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 868, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 868, "R/W", 0, 0, 2ull, 2ull},
- {"DUP" , 12, 1, 868, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_13" , 13, 1, 868, "RAZ", 0, 1, 0ull, 0},
- {"ACK" , 14, 1, 868, "RO", 0, 0, 0ull, 0ull},
- {"LINK" , 15, 1, 868, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 868, "RAZ", 1, 1, 0, 0},
- {"ONE" , 0, 1, 869, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_1_9" , 1, 9, 869, "RAZ", 0, 1, 0ull, 0},
- {"SPEED" , 10, 2, 869, "RO", 0, 0, 0ull, 2ull},
- {"DUP" , 12, 1, 869, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_13_14" , 13, 2, 869, "RAZ", 0, 1, 0ull, 0},
- {"LINK" , 15, 1, 869, "RO", 0, 0, 0ull, 1ull},
- {"RESERVED_16_63" , 16, 48, 869, "RAZ", 1, 1, 0, 0},
- {"ORD_ST" , 0, 4, 870, "RO", 0, 0, 0ull, 0ull},
- {"TX_BAD" , 4, 1, 870, "RO", 0, 0, 0ull, 0ull},
- {"XMIT" , 5, 2, 870, "RO", 0, 1, 0ull, 0},
- {"RESERVED_7_63" , 7, 57, 870, "RAZ", 1, 1, 0, 0},
- {"TXPLRT" , 0, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"RXPLRT" , 1, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"AUTORXPL" , 2, 1, 871, "RO", 0, 0, 0ull, 0ull},
- {"RXOVRD" , 3, 1, 871, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 871, "RAZ", 1, 1, 0, 0},
- {"ADDR_V" , 0, 1, 872, "R/W", 0, 1, 0ull, 0},
- {"END_SWP" , 1, 2, 872, "R/W", 0, 1, 0ull, 0},
- {"CA" , 3, 1, 872, "R/W", 0, 0, 0ull, 0ull},
- {"ADDR_IDX" , 4, 16, 872, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_63" , 20, 44, 872, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_2" , 0, 3, 873, "RAZ", 1, 1, 0, 0},
- {"MASK" , 3, 35, 873, "R/W", 0, 0, 34359738367ull, 34359738367ull},
- {"RESERVED_38_63" , 38, 26, 873, "RAZ", 1, 1, 0, 0},
- {"BAR2_CAX" , 0, 1, 874, "R/W", 0, 0, 0ull, 0ull},
- {"BAR2_ESX" , 1, 2, 874, "R/W", 0, 1, 0ull, 0},
- {"BAR2_ENB" , 3, 1, 874, "R/W", 0, 0, 0ull, 1ull},
- {"BAR1_SIZ" , 4, 3, 874, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_7_63" , 7, 57, 874, "RAZ", 1, 1, 0, 0},
- {"SOT" , 0, 1, 875, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR0" , 1, 1, 875, "RO", 0, 0, 0ull, 0ull},
- {"RQHDR1" , 2, 1, 875, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA3" , 3, 1, 875, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA2" , 4, 1, 875, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA1" , 5, 1, 875, "RO", 0, 0, 0ull, 0ull},
- {"RQDATA0" , 6, 1, 875, "RO", 0, 0, 0ull, 0ull},
- {"RETRY" , 7, 1, 875, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 875, "RAZ", 1, 1, 0, 0},
- {"PPF" , 0, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TC0" , 1, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TCF1" , 2, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TNF" , 3, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF0" , 4, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"PEF_TPF1" , 5, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"PEAI_P2E" , 6, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"E2P_P" , 7, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"E2P_N" , 8, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"E2P_CPL" , 9, 1, 876, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 876, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 0, 32, 877, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 877, "R/W", 0, 1, 0ull, 0},
- {"ADDR" , 0, 32, 878, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 32, 32, 878, "R/W", 0, 1, 0ull, 0},
- {"TAG" , 0, 32, 879, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 879, "RAZ", 1, 1, 0, 0},
- {"INV_LCRC" , 0, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"INV_ECRC" , 1, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"FAST_LM" , 2, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"RO_CTLP" , 3, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"LNK_ENB" , 4, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"DLY_ONE" , 5, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"NF_ECRC" , 6, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_8" , 7, 2, 880, "R/W", 0, 0, 0ull, 0ull},
- {"OB_P_CMD" , 9, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XPME" , 10, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"PM_XTOFF" , 11, 1, 880, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 880, "RAZ", 0, 0, 0ull, 0ull},
- {"CFG_RTRY" , 16, 16, 880, "R/W", 0, 0, 0ull, 32ull},
- {"RESERVED_32_33" , 32, 2, 880, "RAZ", 1, 1, 0, 0},
- {"PBUS" , 34, 8, 880, "RO", 1, 1, 0, 0},
- {"DNUM" , 42, 5, 880, "RO", 1, 1, 0, 0},
- {"AUTO_SD" , 47, 1, 880, "RO", 1, 1, 0, 0},
- {"RESERVED_48_63" , 48, 16, 880, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 881, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 881, "RAZ", 1, 1, 0, 0},
- {"SPOISON" , 0, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPMAL" , 1, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RTLPLLE" , 2, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RECRCE" , 3, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RPOISON" , 4, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RCEMRC" , 5, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RNFEMRC" , 6, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RFEMRC" , 7, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RPMERC" , 8, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RPTAMRC" , 9, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RUMEP" , 10, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RVDM" , 11, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"ACTO" , 12, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RTE" , 13, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"MRE" , 14, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RDWDLE" , 15, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RTWDLE" , 16, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"DPEOOSD" , 17, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"FCPVWT" , 18, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RPE" , 19, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"FCUV" , 20, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RQO" , 21, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RAUC" , 22, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RACUR" , 23, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RACCA" , 24, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"CAAR" , 25, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RARWDNS" , 26, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RAMTLP" , 27, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RACPP" , 28, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RAWWPP" , 29, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"ECRC_E" , 30, 1, 882, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 882, "RAZ", 1, 1, 0, 0},
- {"AUX_EN" , 0, 1, 883, "RO", 0, 0, 0ull, 0ull},
- {"PM_EN" , 1, 1, 883, "RO", 0, 0, 0ull, 0ull},
- {"PM_STAT" , 2, 1, 883, "RO", 0, 0, 0ull, 0ull},
- {"PM_DST" , 3, 1, 883, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 883, "RO", 1, 1, 0, 0},
- {"NUM" , 0, 6, 884, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 884, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 885, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 885, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"SE" , 1, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"PMEI" , 2, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"PMEM" , 3, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B1" , 4, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"UP_B2" , 5, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"UP_BX" , 6, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B1" , 7, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"UN_B2" , 8, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"UN_BX" , 9, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"EXC" , 10, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"RDLK" , 11, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_ER" , 12, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"CRS_DR" , 13, 1, 886, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_14_63" , 14, 50, 886, "RAZ", 1, 1, 0, 0},
- {"AERI" , 0, 1, 887, "RO", 0, 0, 0ull, 0ull},
- {"SE" , 1, 1, 887, "R/W1C", 0, 0, 0ull, 0ull},
- {"PMEI" , 2, 1, 887, "RO", 0, 0, 0ull, 0ull},
- {"PMEM" , 3, 1, 887, "RO", 0, 0, 0ull, 0ull},
- {"UP_B1" , 4, 1, 887, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_B2" , 5, 1, 887, "R/W1C", 0, 0, 0ull, 0ull},
- {"UP_BX" , 6, 1, 887, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B1" , 7, 1, 887, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_B2" , 8, 1, 887, "R/W1C", 0, 0, 0ull, 0ull},
- {"UN_BX" , 9, 1, 887, "R/W1C", 0, 0, 0ull, 0ull},
- {"EXC" , 10, 1, 887, "RO", 0, 0, 0ull, 0ull},
- {"RDLK" , 11, 1, 887, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_ER" , 12, 1, 887, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRS_DR" , 13, 1, 887, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 887, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_13" , 0, 14, 888, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 14, 50, 888, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_25" , 0, 26, 889, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 26, 38, 889, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_40" , 0, 41, 890, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 41, 23, 890, "R/W", 0, 0, 0ull, 0ull},
- {"SLI_P" , 0, 8, 891, "R/W", 0, 0, 128ull, 128ull},
- {"SLI_NP" , 8, 8, 891, "R/W", 0, 0, 16ull, 16ull},
- {"SLI_CPL" , 16, 8, 891, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_24_47" , 24, 24, 891, "RAZ", 1, 1, 0, 0},
- {"PEAI_PPF" , 48, 8, 891, "R/W", 0, 0, 128ull, 128ull},
- {"RESERVED_56_63" , 56, 8, 891, "RAZ", 1, 1, 0, 0},
- {"SKIP1" , 0, 7, 892, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_7" , 7, 1, 892, "RAZ", 1, 1, 0, 0},
- {"SKIP2" , 8, 7, 892, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_15_15" , 15, 1, 892, "RAZ", 1, 1, 0, 0},
- {"SKIP3" , 16, 7, 892, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_31" , 23, 9, 892, "RAZ", 1, 1, 0, 0},
- {"BIT0" , 32, 6, 892, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_39" , 38, 2, 892, "RAZ", 1, 1, 0, 0},
- {"BIT1" , 40, 6, 892, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_46_55" , 46, 10, 892, "RAZ", 1, 1, 0, 0},
- {"LEN" , 56, 1, 892, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_57_63" , 57, 7, 892, "RAZ", 1, 1, 0, 0},
- {"LOWATER" , 0, 5, 893, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_5_7" , 5, 3, 893, "RAZ", 0, 1, 0ull, 0},
- {"HIWATER" , 8, 5, 893, "R/W", 0, 0, 24ull, 24ull},
- {"RESERVED_13_62" , 13, 50, 893, "RAZ", 0, 1, 0ull, 0},
- {"BCKPRS" , 63, 1, 893, "RO", 0, 0, 0ull, 0ull},
- {"BIST" , 0, 20, 894, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 894, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 895, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_7_15" , 7, 9, 895, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 16, 9, 895, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_25_31" , 25, 7, 895, "RAZ", 1, 1, 0, 0},
- {"TAG" , 32, 8, 895, "R/W", 0, 1, 0ull, 0},
- {"UPPER_TAG" , 40, 16, 895, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 895, "RAZ", 1, 1, 0, 0},
- {"POS0" , 0, 7, 896, "R/W", 0, 1, 0ull, 0},
- {"POS0_VAL" , 7, 1, 896, "R/W", 0, 1, 0ull, 0},
- {"POS1" , 8, 7, 896, "R/W", 0, 1, 0ull, 0},
- {"POS1_VAL" , 15, 1, 896, "R/W", 0, 1, 0ull, 0},
- {"POS2" , 16, 7, 896, "R/W", 0, 1, 0ull, 0},
- {"POS2_VAL" , 23, 1, 896, "R/W", 0, 1, 0ull, 0},
- {"POS3" , 24, 7, 896, "R/W", 0, 1, 0ull, 0},
- {"POS3_VAL" , 31, 1, 896, "R/W", 0, 1, 0ull, 0},
- {"POS4" , 32, 7, 896, "R/W", 0, 1, 0ull, 0},
- {"POS4_VAL" , 39, 1, 896, "R/W", 0, 1, 0ull, 0},
- {"POS5" , 40, 7, 896, "R/W", 0, 1, 0ull, 0},
- {"POS5_VAL" , 47, 1, 896, "R/W", 0, 1, 0ull, 0},
- {"POS6" , 48, 7, 896, "R/W", 0, 1, 0ull, 0},
- {"POS6_VAL" , 55, 1, 896, "R/W", 0, 1, 0ull, 0},
- {"POS7" , 56, 7, 896, "R/W", 0, 1, 0ull, 0},
- {"POS7_VAL" , 63, 1, 896, "R/W", 0, 1, 0ull, 0},
- {"QOS" , 0, 3, 897, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_3_7" , 3, 5, 897, "RAZ", 1, 1, 0, 0},
- {"TT" , 8, 2, 897, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_10_15" , 10, 6, 897, "RAZ", 1, 1, 0, 0},
- {"GRP" , 16, 4, 897, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_20_31" , 20, 12, 897, "RAZ", 1, 1, 0, 0},
- {"TAG" , 32, 8, 897, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_40_59" , 40, 20, 897, "RAZ", 1, 1, 0, 0},
- {"QOS_EN" , 60, 1, 897, "R/W", 0, 1, 0ull, 0},
- {"TT_EN" , 61, 1, 897, "R/W", 0, 1, 0ull, 0},
- {"GRP_EN" , 62, 1, 897, "R/W", 0, 1, 0ull, 0},
- {"TAG_EN" , 63, 1, 897, "R/W", 0, 1, 0ull, 0},
- {"CLKEN" , 0, 1, 898, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 898, "RAZ", 0, 1, 0ull, 0},
- {"DPRT" , 0, 16, 899, "R/W", 0, 0, 0ull, 0ull},
- {"UDP" , 16, 1, 899, "R/W", 0, 0, 0ull, 0ull},
- {"TCP" , 17, 1, 899, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 899, "RAZ", 1, 1, 0, 0},
- {"MAP0" , 0, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 900, "R/W", 0, 0, 0ull, 0ull},
- {"MAP0" , 0, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP1" , 4, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP2" , 8, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP3" , 12, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP4" , 16, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP5" , 20, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP6" , 24, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP7" , 28, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP8" , 32, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP9" , 36, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP10" , 40, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP11" , 44, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP12" , 48, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP13" , 52, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP14" , 56, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MAP15" , 60, 4, 901, "R/W", 0, 0, 0ull, 0ull},
- {"MINLEN" , 0, 16, 902, "R/W", 0, 0, 64ull, 64ull},
- {"MAXLEN" , 16, 16, 902, "R/W", 0, 0, 1536ull, 1536ull},
- {"RESERVED_32_63" , 32, 32, 902, "RAZ", 1, 1, 0, 0},
- {"NIP_SHF" , 0, 3, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_7" , 3, 5, 903, "RAZ", 1, 1, 0, 0},
- {"RAW_SHF" , 8, 3, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_15" , 11, 5, 903, "RAZ", 1, 1, 0, 0},
- {"MAX_L2" , 16, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_UDP" , 17, 1, 903, "R/W", 0, 0, 1ull, 1ull},
- {"TAG_SYN" , 18, 1, 903, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 903, "RAZ", 1, 1, 0, 0},
- {"IP_CHK" , 0, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"IP_MAL" , 1, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"IP_HOP" , 2, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"IP4_OPTS" , 3, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"IP6_EEXT" , 4, 2, 904, "R/W", 0, 0, 1ull, 3ull},
- {"RESERVED_6_7" , 6, 2, 904, "RAZ", 1, 1, 0, 0},
- {"L4_MAL" , 8, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"L4_PRT" , 9, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"L4_CHK" , 10, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"L4_LEN" , 11, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"TCP_FLAG" , 12, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"L2_MAL" , 13, 1, 904, "R/W", 0, 0, 1ull, 1ull},
- {"VS_QOS" , 14, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"VS_WQE" , 15, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"IGNRS" , 16, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 904, "RAZ", 0, 0, 0ull, 0ull},
- {"RING_EN" , 20, 1, 904, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_21_23" , 21, 3, 904, "RAZ", 1, 1, 0, 0},
- {"DSA_GRP_SID" , 24, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_SCMD" , 25, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_GRP_TVID" , 26, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"IHMSK_DIS" , 27, 1, 904, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_63" , 28, 36, 904, "RAZ", 1, 1, 0, 0},
- {"PRI" , 0, 6, 905, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_7" , 6, 2, 905, "RAZ", 1, 1, 0, 0},
- {"QOS" , 8, 3, 905, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_11_11" , 11, 1, 905, "RAZ", 1, 1, 0, 0},
- {"UP_QOS" , 12, 1, 905, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_13_63" , 13, 51, 905, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 906, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 906, "RAZ", 1, 1, 0, 0},
- {"PKTDRP" , 0, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"CRCERR" , 1, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"BCKPRS" , 2, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"PRTNXA" , 3, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"BADTAG" , 4, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"SKPRUNT" , 5, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"TODOOVR" , 6, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"FEPERR" , 7, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"BEPERR" , 8, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"MINERR" , 9, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"MAXERR" , 10, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"LENERR" , 11, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"PUNYERR" , 12, 1, 907, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_13_63" , 13, 51, 907, "RAZ", 1, 1, 0, 0},
- {"OFFSET" , 0, 3, 908, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 908, "RAZ", 1, 1, 0, 0},
- {"SKIP" , 0, 7, 909, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_7" , 7, 1, 909, "RAZ", 1, 1, 0, 0},
- {"MODE" , 8, 2, 909, "R/W", 0, 0, 0ull, 0ull},
- {"DSA_EN" , 10, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"HIGIG_EN" , 11, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"CRC_EN" , 12, 1, 909, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_13_15" , 13, 3, 909, "RAZ", 1, 1, 0, 0},
- {"QOS_VLAN" , 16, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_DIFF" , 17, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VOD" , 18, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_VSEL" , 19, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"QOS_WAT" , 20, 4, 909, "R/W", 0, 0, 0ull, 0ull},
- {"QOS" , 24, 3, 909, "R/W", 0, 0, 0ull, 0ull},
- {"HG_QOS" , 27, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT" , 28, 4, 909, "R/W", 0, 0, 0ull, 0ull},
- {"INST_HDR" , 32, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"DYN_RS" , 33, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_INC" , 34, 2, 909, "R/W", 0, 0, 0ull, 0ull},
- {"RAWDRP" , 36, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_37_39" , 37, 3, 909, "RAZ", 1, 1, 0, 0},
- {"QOS_WAT_47" , 40, 4, 909, "R/W", 0, 0, 0ull, 0ull},
- {"GRP_WAT_47" , 44, 4, 909, "R/W", 0, 0, 0ull, 0ull},
- {"MINERR_EN" , 48, 1, 909, "R/W", 0, 0, 1ull, 1ull},
- {"MAXERR_EN" , 49, 1, 909, "R/W", 0, 0, 1ull, 1ull},
- {"LENERR_EN" , 50, 1, 909, "R/W", 0, 0, 1ull, 1ull},
- {"VLAN_LEN" , 51, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"PAD_LEN" , 52, 1, 909, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_53_63" , 53, 11, 909, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_31" , 0, 32, 910, "RAZ", 1, 1, 0, 0},
- {"BSEL_EN" , 32, 1, 910, "R/W", 0, 0, 0ull, 0ull},
- {"BSEL_NUM" , 33, 2, 910, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_35_35" , 35, 1, 910, "RAZ", 1, 1, 0, 0},
- {"ALT_SKP_EN" , 36, 1, 910, "R/W", 0, 1, 0ull, 0},
- {"ALT_SKP_SEL" , 37, 2, 910, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_39_63" , 39, 25, 910, "RAZ", 1, 1, 0, 0},
- {"GRP" , 0, 4, 911, "R/W", 0, 0, 0ull, 0ull},
- {"NON_TAG_TYPE" , 4, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_TAG_TYPE" , 6, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_TAG_TYPE" , 8, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"TCP4_TAG_TYPE" , 10, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"TCP6_TAG_TYPE" , 12, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SRC_FLAG" , 14, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SRC_FLAG" , 15, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DST_FLAG" , 16, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DST_FLAG" , 17, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_PCTL_FLAG" , 18, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_NXTH_FLAG" , 19, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_SPRT_FLAG" , 20, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_SPRT_FLAG" , 21, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP4_DPRT_FLAG" , 22, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"IP6_DPRT_FLAG" , 23, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"INC_PRT_FLAG" , 24, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VLAN" , 25, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"INC_VS" , 26, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"TAG_MODE" , 28, 2, 911, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG_MSKIP" , 30, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAG" , 31, 1, 911, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGMASK" , 32, 4, 911, "R/W", 0, 0, 0ull, 0ull},
- {"GRPTAGBASE" , 36, 4, 911, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_40_63" , 40, 24, 911, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 912, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 912, "RAZ", 1, 1, 0, 0},
- {"QOS" , 0, 3, 913, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 913, "RAZ", 1, 1, 0, 0},
- {"QOS1" , 4, 3, 913, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_63" , 7, 57, 913, "RAZ", 1, 1, 0, 0},
- {"MATCH_VALUE" , 0, 16, 914, "R/W", 0, 0, 0ull, 0ull},
- {"MATCH_TYPE" , 16, 3, 914, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_19" , 19, 1, 914, "RAZ", 1, 1, 0, 0},
- {"QOS" , 20, 3, 914, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_23" , 23, 1, 914, "RAZ", 1, 1, 0, 0},
- {"GRP" , 24, 4, 914, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 914, "RAZ", 1, 1, 0, 0},
- {"MASK" , 32, 16, 914, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_48_63" , 48, 16, 914, "RAZ", 1, 1, 0, 0},
- {"WORD" , 0, 56, 915, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_56_63" , 56, 8, 915, "RAZ", 1, 1, 0, 0},
- {"RST" , 0, 1, 916, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 916, "RAZ", 1, 1, 0, 0},
- {"DRP_OCTS" , 0, 32, 917, "R/W", 0, 1, 0ull, 0},
- {"DRP_PKTS" , 32, 32, 917, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 918, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 918, "R/W", 0, 1, 0ull, 0},
- {"MCAST" , 0, 32, 919, "R/W", 0, 1, 0ull, 0},
- {"BCAST" , 32, 32, 919, "R/W", 0, 1, 0ull, 0},
- {"OCTS" , 0, 48, 920, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 920, "RAZ", 1, 1, 0, 0},
- {"RAW" , 0, 32, 921, "R/W", 0, 1, 0ull, 0},
- {"PKTS" , 32, 32, 921, "R/W", 0, 1, 0ull, 0},
- {"MCST" , 0, 32, 922, "R/W", 0, 1, 0ull, 0},
- {"BCST" , 32, 32, 922, "R/W", 0, 1, 0ull, 0},
- {"H64" , 0, 32, 923, "R/W", 0, 1, 0ull, 0},
- {"H65TO127" , 32, 32, 923, "R/W", 0, 1, 0ull, 0},
- {"H128TO255" , 0, 32, 924, "R/W", 0, 1, 0ull, 0},
- {"H256TO511" , 32, 32, 924, "R/W", 0, 1, 0ull, 0},
- {"H512TO1023" , 0, 32, 925, "R/W", 0, 1, 0ull, 0},
- {"H1024TO1518" , 32, 32, 925, "R/W", 0, 1, 0ull, 0},
- {"H1519" , 0, 32, 926, "R/W", 0, 1, 0ull, 0},
- {"FCS" , 32, 32, 926, "R/W", 0, 1, 0ull, 0},
- {"UNDERSZ" , 0, 32, 927, "R/W", 0, 1, 0ull, 0},
- {"FRAG" , 32, 32, 927, "R/W", 0, 1, 0ull, 0},
- {"OVERSZ" , 0, 32, 928, "R/W", 0, 1, 0ull, 0},
- {"JABBER" , 32, 32, 928, "R/W", 0, 1, 0ull, 0},
- {"RDCLR" , 0, 1, 929, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 929, "RAZ", 1, 1, 0, 0},
- {"ERRS" , 0, 16, 930, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 930, "RAZ", 1, 1, 0, 0},
- {"OCTS" , 0, 48, 931, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 931, "RAZ", 1, 1, 0, 0},
- {"PKTS" , 0, 32, 932, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 932, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 8, 933, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 933, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 934, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 934, "RAZ", 1, 1, 0, 0},
- {"SRC" , 0, 16, 935, "R/W", 0, 0, 0ull, 0ull},
- {"DST" , 16, 16, 935, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 935, "RAZ", 1, 1, 0, 0},
- {"ENTRY" , 0, 62, 936, "RO", 1, 1, 0, 0},
- {"RESERVED_62_62" , 62, 1, 936, "RAZ", 1, 1, 0, 0},
- {"VAL" , 63, 1, 936, "RO", 1, 1, 0, 0},
- {"TYPE0" , 0, 16, 937, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE1" , 16, 16, 937, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE2" , 32, 16, 937, "R/W", 0, 0, 33024ull, 33024ull},
- {"TYPE3" , 48, 16, 937, "R/W", 0, 0, 33024ull, 33024ull},
- {"COUNT" , 0, 32, 938, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 938, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 0, 48, 939, "R/W1C", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 939, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 940, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 940, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 940, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 940, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 941, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 941, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 941, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 941, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 941, "RO", 1, 0, 0, 0ull},
- {"PTRS2" , 0, 17, 942, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 942, "RAZ", 1, 1, 0, 0},
- {"PTRS1" , 32, 17, 942, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 942, "RAZ", 1, 1, 0, 0},
- {"MOD" , 0, 3, 943, "RO", 1, 0, 0, 0ull},
- {"CNT" , 3, 13, 943, "RO", 1, 0, 0, 0ull},
- {"CHK" , 16, 1, 943, "RO", 1, 0, 0, 0ull},
- {"LEN" , 17, 1, 943, "RO", 1, 0, 0, 0ull},
- {"SOP" , 18, 1, 943, "RO", 1, 0, 0, 0ull},
- {"UID" , 19, 3, 943, "RO", 1, 0, 0, 0ull},
- {"MAJ" , 22, 1, 943, "RO", 1, 0, 0, 0ull},
- {"RESERVED_23_63" , 23, 41, 943, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 16, 944, "RO", 1, 0, 0, 0ull},
- {"SEGS" , 16, 6, 944, "RO", 1, 0, 0, 0ull},
- {"CMD" , 22, 14, 944, "RO", 1, 0, 0, 0ull},
- {"FAU" , 36, 28, 944, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 945, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 945, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 945, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 945, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 945, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 946, "RO", 1, 0, 0, 0ull},
- {"PTR" , 0, 40, 947, "RO", 1, 0, 0, 0ull},
- {"SIZE" , 40, 16, 947, "RO", 1, 0, 0, 0ull},
- {"POOL" , 56, 3, 947, "RO", 1, 0, 0, 0ull},
- {"BACK" , 59, 4, 947, "RO", 1, 0, 0, 0ull},
- {"I" , 63, 1, 947, "RO", 1, 0, 0, 0ull},
- {"DATA" , 0, 64, 948, "RO", 1, 0, 0, 0ull},
- {"MAJOR" , 0, 3, 949, "RO", 1, 0, 0, 0ull},
- {"MINOR" , 3, 2, 949, "RO", 1, 0, 0, 0ull},
- {"WAIT" , 5, 1, 949, "RO", 1, 0, 0, 0ull},
- {"CHK_MODE" , 6, 1, 949, "RO", 1, 0, 0, 0ull},
- {"CHK_ONCE" , 7, 1, 949, "RO", 1, 0, 0, 0ull},
- {"INIT_DWRITE" , 8, 1, 949, "RO", 1, 0, 0, 0ull},
- {"DREAD_SOP" , 9, 1, 949, "RO", 1, 0, 0, 0ull},
- {"UID" , 10, 2, 949, "RO", 1, 0, 0, 0ull},
- {"CMND_OFF" , 12, 6, 949, "RO", 1, 0, 0, 0ull},
- {"CMND_SIZ" , 18, 16, 949, "RO", 1, 0, 0, 0ull},
- {"CMND_SEGS" , 34, 6, 949, "RO", 1, 0, 0, 0ull},
- {"CURR_OFF" , 40, 16, 949, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 56, 8, 949, "RO", 1, 0, 0, 0ull},
- {"CURR_SIZ" , 0, 8, 950, "RO", 1, 0, 0, 0ull},
- {"CURR_PTR" , 8, 40, 950, "RO", 1, 0, 0, 0ull},
- {"NXT_INFLT" , 48, 6, 950, "RO", 1, 0, 0, 0ull},
- {"MAJOR_3" , 54, 1, 950, "RO", 1, 0, 0, 0ull},
- {"PTP" , 55, 1, 950, "RO", 1, 0, 0, 0ull},
- {"RESERVED_56_63" , 56, 8, 950, "RAZ", 1, 1, 0, 0},
- {"QID_BASE" , 0, 8, 951, "RO", 1, 0, 0, 0ull},
- {"QID_OFF" , 8, 4, 951, "RO", 1, 0, 0, 0ull},
- {"QID_OFFMAX" , 12, 4, 951, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 16, 5, 951, "RO", 1, 0, 0, 0ull},
- {"QOS" , 21, 3, 951, "RO", 1, 0, 0, 0ull},
- {"STATC" , 24, 1, 951, "RO", 1, 0, 0, 0ull},
- {"ACTIVE" , 25, 1, 951, "RO", 1, 0, 0, 0ull},
- {"PREEMPTED" , 26, 1, 951, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 27, 1, 951, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 951, "RO", 1, 0, 0, 0ull},
- {"QID_OFFTHS" , 29, 4, 951, "RO", 1, 0, 0, 0ull},
- {"QID_OFFRES" , 33, 4, 951, "RO", 1, 0, 0, 0ull},
- {"RESERVED_37_63" , 37, 27, 951, "RO", 1, 0, 0, 0ull},
- {"QCB_RIDX" , 0, 6, 952, "RO", 1, 0, 0, 0ull},
- {"QCB_WIDX" , 6, 6, 952, "RO", 1, 0, 0, 0ull},
- {"BUF_PTR" , 12, 33, 952, "RO", 1, 0, 0, 0ull},
- {"BUF_SIZ" , 45, 13, 952, "RO", 1, 0, 0, 0ull},
- {"TAIL" , 58, 1, 952, "RO", 1, 0, 0, 0ull},
- {"QOS" , 59, 5, 952, "RO", 1, 0, 0, 0ull},
- {"QOS" , 0, 3, 953, "RO", 1, 0, 0, 0ull},
- {"STATIC_Q" , 3, 1, 953, "RO", 1, 0, 0, 0ull},
- {"S_TAIL" , 4, 1, 953, "RO", 1, 0, 0, 0ull},
- {"STATIC_P" , 5, 1, 953, "RO", 1, 0, 0, 0ull},
- {"PREEMPTEE" , 6, 1, 953, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 953, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 8, 20, 953, "RO", 1, 0, 0, 0ull},
- {"PREEMPTER" , 28, 1, 953, "RO", 1, 0, 0, 0ull},
- {"QID_IDX" , 29, 4, 953, "RO", 1, 1, 0, 0},
- {"RESERVED_33_33" , 33, 1, 953, "RAZ", 1, 1, 0, 0},
- {"QID_QQOS" , 34, 8, 953, "RO", 1, 1, 0, 0},
- {"RESERVED_42_63" , 42, 22, 953, "RAZ", 1, 1, 0, 0},
- {"PTRS3" , 0, 17, 954, "RO", 1, 0, 0, 0ull},
- {"RESERVED_17_31" , 17, 15, 954, "RAZ", 1, 1, 0, 0},
- {"PTRS0" , 32, 17, 954, "RO", 1, 0, 0, 0ull},
- {"RESERVED_49_63" , 49, 15, 954, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 955, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 955, "R/W", 1, 0, 0, 0ull},
- {"BP_PORT" , 10, 6, 955, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_16_52" , 16, 37, 955, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 955, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 61, 1, 955, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_62_63" , 62, 2, 955, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 956, "R/W", 1, 0, 0, 0ull},
- {"EID" , 6, 4, 956, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_10_52" , 10, 43, 956, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 956, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 956, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 957, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 957, "RAZ", 1, 1, 0, 0},
- {"RATE_PKT" , 8, 24, 957, "R/W", 1, 0, 0, 0ull},
- {"RATE_WORD" , 32, 19, 957, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_51_63" , 51, 13, 957, "RAZ", 1, 1, 0, 0},
- {"PID" , 0, 6, 958, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_6_7" , 6, 2, 958, "RAZ", 1, 1, 0, 0},
- {"RATE_LIM" , 8, 24, 958, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_32_63" , 32, 32, 958, "RAZ", 1, 1, 0, 0},
- {"QUEUE" , 0, 7, 959, "R/W", 1, 0, 0, 0ull},
- {"PORT" , 7, 6, 959, "WR0", 1, 0, 0, 0ull},
- {"INDEX" , 13, 3, 959, "WR0", 1, 0, 0, 0ull},
- {"TAIL" , 16, 1, 959, "R/W", 1, 0, 0, 0ull},
- {"BUF_PTR" , 17, 36, 959, "R/W", 1, 0, 0, 0ull},
- {"QOS_MASK" , 53, 8, 959, "R/W", 1, 0, 0, 0ull},
- {"STATIC_Q" , 61, 1, 959, "R/W", 1, 0, 0, 0ull},
- {"STATIC_P" , 62, 1, 959, "R/W", 1, 0, 0, 0ull},
- {"S_TAIL" , 63, 1, 959, "R/W", 1, 0, 0, 0ull},
- {"QID" , 0, 7, 960, "R/W", 1, 0, 0, 0ull},
- {"PID" , 7, 6, 960, "WR0", 1, 0, 0, 0ull},
- {"RESERVED_13_52" , 13, 40, 960, "RAZ", 1, 1, 0, 0},
- {"QOS_MASK" , 53, 8, 960, "R/W", 1, 0, 0, 0ull},
- {"RESERVED_61_63" , 61, 3, 960, "RAZ", 1, 1, 0, 0},
- {"DAT_PTR" , 0, 4, 961, "RO", 1, 0, 0, 0ull},
- {"DAT_DAT" , 4, 2, 961, "RO", 1, 0, 0, 0ull},
- {"PRT_CTL" , 6, 2, 961, "RO", 1, 0, 0, 0ull},
- {"PRT_QSB" , 8, 3, 961, "RO", 1, 0, 0, 0ull},
- {"PRT_QCB" , 11, 2, 961, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 13, 2, 961, "RO", 1, 0, 0, 0ull},
- {"PRT_PSB" , 15, 8, 961, "RO", 1, 0, 0, 0ull},
- {"PRT_NXT" , 23, 1, 961, "RO", 1, 0, 0, 0ull},
- {"PRT_CHK" , 24, 3, 961, "RO", 1, 0, 0, 0ull},
- {"OUT_WIF" , 27, 1, 961, "RO", 1, 0, 0, 0ull},
- {"OUT_STA" , 28, 1, 961, "RO", 1, 0, 0, 0ull},
- {"OUT_CTL" , 29, 3, 961, "RO", 1, 0, 0, 0ull},
- {"OUT_DAT" , 32, 1, 961, "RO", 1, 0, 0, 0ull},
- {"IOB" , 33, 1, 961, "RO", 1, 0, 0, 0ull},
- {"CSR" , 34, 1, 961, "RO", 1, 0, 0, 0ull},
- {"RESERVED_35_63" , 35, 29, 961, "RAZ", 1, 1, 0, 0},
- {"SIZE" , 0, 13, 962, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_19" , 13, 7, 962, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 20, 3, 962, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_63" , 23, 41, 962, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 64, 963, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 964, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 965, "RO", 0, 0, 0ull, 0ull},
- {"ASSERTS" , 0, 64, 966, "RO", 0, 0, 0ull, 0ull},
- {"ENGINE0" , 0, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE1" , 4, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE2" , 8, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE3" , 12, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE4" , 16, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE5" , 20, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE6" , 24, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE7" , 28, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE8" , 32, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE9" , 36, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE10" , 40, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE11" , 44, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE12" , 48, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"ENGINE13" , 52, 4, 967, "R/W", 0, 0, 4ull, 4ull},
- {"RESERVED_56_63" , 56, 8, 967, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 14, 968, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 968, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 969, "R/W1C", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 969, "R/W1C", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 969, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 969, "RAZ", 1, 1, 0, 0},
- {"ENA_PKO" , 0, 1, 970, "R/W", 0, 0, 0ull, 0ull},
- {"ENA_DWB" , 1, 1, 970, "R/W", 0, 0, 0ull, 0ull},
- {"STORE_BE" , 2, 1, 970, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 3, 1, 970, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_4_6" , 4, 3, 970, "RAZ", 1, 1, 0, 0},
- {"DIS_PERF2" , 7, 1, 970, "R/W", 0, 0, 0ull, 0ull},
- {"DIS_PERF3" , 8, 1, 970, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_63" , 9, 55, 970, "RAZ", 1, 1, 0, 0},
- {"MODE0" , 0, 3, 971, "R/W", 0, 0, 0ull, 0ull},
- {"MODE1" , 3, 3, 971, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 971, "RAZ", 1, 1, 0, 0},
- {"PARITY" , 0, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"DOORBELL" , 1, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"CURRZERO" , 2, 1, 972, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 972, "RAZ", 1, 1, 0, 0},
- {"MIN_SIZE" , 0, 16, 973, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 973, "RAZ", 1, 1, 0, 0},
- {"MODE" , 0, 2, 974, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 974, "RAZ", 1, 1, 0, 0},
- {"PREEMPTER" , 0, 1, 975, "R/W", 0, 0, 0ull, 0ull},
- {"PREEMPTEE" , 1, 1, 975, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 975, "RAZ", 1, 1, 0, 0},
- {"QID7" , 0, 1, 976, "R/W", 0, 0, 0ull, 0ull},
- {"IDX3" , 1, 1, 976, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 976, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 977, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 977, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 977, "RAZ", 1, 1, 0, 0},
- {"WQE_WORD" , 0, 4, 978, "R/W", 0, 0, 2ull, 2ull},
- {"RESERVED_4_63" , 4, 60, 978, "RAZ", 1, 1, 0, 0},
- {"ADR" , 0, 1, 979, "RO", 0, 0, 0ull, 0ull},
- {"PEND" , 1, 1, 979, "RO", 0, 0, 0ull, 0ull},
- {"FIDX" , 2, 1, 979, "RO", 0, 0, 0ull, 0ull},
- {"INDEX" , 3, 1, 979, "RO", 0, 0, 0ull, 0ull},
- {"NBT" , 4, 4, 979, "RO", 0, 0, 0ull, 0ull},
- {"NBR" , 8, 3, 979, "RO", 0, 0, 0ull, 0ull},
- {"CAM" , 11, 1, 979, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 979, "RAZ", 1, 1, 0, 0},
- {"PP" , 16, 4, 979, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 979, "RAZ", 1, 1, 0, 0},
- {"DS_PC" , 0, 32, 980, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 980, "RAZ", 1, 1, 0, 0},
- {"SBE" , 0, 1, 981, "R/W1C", 0, 0, 0ull, 0ull},
- {"DBE" , 1, 1, 981, "R/W1C", 0, 0, 0ull, 0ull},
- {"SBE_IE" , 2, 1, 981, "R/W", 0, 1, 0ull, 0},
- {"DBE_IE" , 3, 1, 981, "R/W", 0, 1, 0ull, 0},
- {"SYN" , 4, 5, 981, "RO", 1, 1, 0, 0},
- {"RESERVED_9_11" , 9, 3, 981, "RAZ", 1, 1, 0, 0},
- {"RPE" , 12, 1, 981, "R/W1C", 0, 0, 0ull, 0ull},
- {"RPE_IE" , 13, 1, 981, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_15" , 14, 2, 981, "RAZ", 1, 1, 0, 0},
- {"IOP" , 16, 13, 981, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_29_31" , 29, 3, 981, "RAZ", 1, 1, 0, 0},
- {"IOP_IE" , 32, 13, 981, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_45_63" , 45, 19, 981, "RAZ", 1, 1, 0, 0},
- {"NBR_THR" , 0, 5, 982, "R/W", 0, 0, 2ull, 2ull},
- {"PFR_DIS" , 5, 1, 982, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 982, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 983, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 983, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 32, 984, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 984, "RAZ", 1, 1, 0, 0},
- {"IQ_INT" , 0, 8, 985, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 985, "RAZ", 1, 1, 0, 0},
- {"INT_EN" , 0, 8, 986, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 986, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 32, 987, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_32_63" , 32, 32, 987, "RAZ", 1, 1, 0, 0},
- {"NOS_CNT" , 0, 10, 988, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_63" , 10, 54, 988, "RAZ", 1, 1, 0, 0},
- {"NW_TIM" , 0, 10, 989, "R/W", 0, 0, 0ull, 4ull},
- {"RESERVED_10_63" , 10, 54, 989, "RAZ", 1, 1, 0, 0},
- {"RST_MSK" , 0, 8, 990, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 990, "RAZ", 1, 1, 0, 0},
- {"GRP_MSK" , 0, 16, 991, "R/W", 0, 0, 65535ull, 65535ull},
- {"QOS0_PRI" , 16, 4, 991, "R/W", 0, 1, 0ull, 0},
- {"QOS1_PRI" , 20, 4, 991, "R/W", 0, 1, 0ull, 0},
- {"QOS2_PRI" , 24, 4, 991, "R/W", 0, 1, 0ull, 0},
- {"QOS3_PRI" , 28, 4, 991, "R/W", 0, 1, 0ull, 0},
- {"QOS4_PRI" , 32, 4, 991, "R/W", 0, 1, 0ull, 0},
- {"QOS5_PRI" , 36, 4, 991, "R/W", 0, 1, 0ull, 0},
- {"QOS6_PRI" , 40, 4, 991, "R/W", 0, 1, 0ull, 0},
- {"QOS7_PRI" , 44, 4, 991, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_48_63" , 48, 16, 991, "RAZ", 1, 1, 0, 0},
- {"RND" , 0, 8, 992, "R/W", 0, 1, 255ull, 0},
- {"RND_P1" , 8, 8, 992, "R/W", 0, 1, 255ull, 0},
- {"RND_P2" , 16, 8, 992, "R/W", 0, 1, 255ull, 0},
- {"RND_P3" , 24, 8, 992, "R/W", 0, 1, 255ull, 0},
- {"RESERVED_32_63" , 32, 32, 992, "RAZ", 1, 1, 0, 0},
- {"MIN_THR" , 0, 9, 993, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 993, "RAZ", 1, 1, 0, 0},
- {"MAX_THR" , 12, 9, 993, "R/W", 0, 1, 511ull, 0},
- {"RESERVED_21_23" , 21, 3, 993, "RAZ", 1, 1, 0, 0},
- {"FREE_CNT" , 24, 10, 993, "RO", 0, 1, 503ull, 0},
- {"RESERVED_34_35" , 34, 2, 993, "RAZ", 1, 1, 0, 0},
- {"BUF_CNT" , 36, 10, 993, "RO", 0, 1, 0ull, 0},
- {"RESERVED_46_47" , 46, 2, 993, "RAZ", 1, 1, 0, 0},
- {"DES_CNT" , 48, 10, 993, "RO", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 993, "RAZ", 1, 1, 0, 0},
- {"TS_PC" , 0, 32, 994, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 994, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 995, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 995, "RAZ", 1, 1, 0, 0},
- {"WA_PC" , 0, 32, 996, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 996, "RAZ", 1, 1, 0, 0},
- {"WQ_INT" , 0, 16, 997, "R/W1C", 0, 1, 0ull, 0},
- {"IQ_DIS" , 16, 16, 997, "R/W1", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 997, "RAZ", 1, 1, 0, 0},
- {"IQ_CNT" , 0, 10, 998, "RO", 0, 1, 0ull, 0},
- {"RESERVED_10_11" , 10, 2, 998, "RAZ", 1, 1, 0, 0},
- {"DS_CNT" , 12, 10, 998, "RO", 0, 1, 0ull, 0},
- {"RESERVED_22_23" , 22, 2, 998, "RAZ", 1, 1, 0, 0},
- {"TC_CNT" , 24, 4, 998, "RO", 0, 1, 0ull, 0},
- {"RESERVED_28_63" , 28, 36, 998, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 999, "RAZ", 1, 1, 0, 0},
- {"PC_THR" , 8, 20, 999, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_28_31" , 28, 4, 999, "RAZ", 1, 1, 0, 0},
- {"PC" , 32, 28, 999, "RO", 0, 1, 0ull, 0},
- {"RESERVED_60_63" , 60, 4, 999, "RAZ", 1, 1, 0, 0},
- {"IQ_THR" , 0, 9, 1000, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_9_11" , 9, 3, 1000, "RAZ", 1, 1, 0, 0},
- {"DS_THR" , 12, 9, 1000, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_23" , 21, 3, 1000, "RAZ", 1, 1, 0, 0},
- {"TC_THR" , 24, 4, 1000, "R/W", 0, 1, 0ull, 0},
- {"TC_EN" , 28, 1, 1000, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_29_63" , 29, 35, 1000, "RAZ", 1, 1, 0, 0},
- {"WS_PC" , 0, 32, 1001, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1001, "RAZ", 1, 1, 0, 0},
- {"IWORD" , 0, 64, 1002, "RO", 1, 1, 0, 0},
- {"P_DAT" , 0, 64, 1003, "RO", 1, 1, 0, 0},
- {"Q_DAT" , 0, 64, 1004, "RO", 1, 1, 0, 0},
- {"DAT" , 0, 2, 1005, "RO", 1, 0, 0, 0ull},
- {"NCB_INB" , 2, 2, 1005, "RO", 1, 0, 0, 0ull},
- {"NCB_OUB" , 4, 1, 1005, "RO", 1, 0, 0, 0ull},
- {"STA" , 5, 1, 1005, "RO", 1, 0, 0, 0ull},
- {"RESERVED_6_63" , 6, 58, 1005, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 33, 1006, "R/W", 0, 1, 0ull, 0},
- {"SIZE" , 33, 13, 1006, "R/W", 0, 1, 0ull, 0},
- {"POOL" , 46, 3, 1006, "R/W", 0, 1, 0ull, 0},
- {"DWB" , 49, 9, 1006, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_58_63" , 58, 6, 1006, "RAZ", 0, 0, 0ull, 0ull},
- {"RESET" , 0, 1, 1007, "RAZ", 0, 0, 0ull, 0ull},
- {"STORE_LE" , 1, 1, 1007, "R/W", 0, 0, 0ull, 0ull},
- {"MAX_READ" , 2, 4, 1007, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_6_63" , 6, 58, 1007, "RAZ", 0, 0, 0ull, 0ull},
- {"STATE" , 0, 5, 1008, "RO", 1, 1, 0, 0},
- {"COMMIT" , 5, 1, 1008, "RO", 1, 1, 0, 0},
- {"OWORDPV" , 6, 1, 1008, "RO", 1, 1, 0, 0},
- {"OWORDQV" , 7, 1, 1008, "RO", 1, 1, 0, 0},
- {"IWIDX" , 8, 6, 1008, "RO", 1, 1, 0, 0},
- {"RESERVED_14_15" , 14, 2, 1008, "RO", 1, 1, 0, 0},
- {"IRIDX" , 16, 6, 1008, "RO", 1, 1, 0, 0},
- {"RESERVED_22_31" , 22, 10, 1008, "RO", 1, 1, 0, 0},
- {"LOOP" , 32, 25, 1008, "RO", 1, 1, 0, 0},
- {"RESERVED_57_63" , 57, 7, 1008, "RO", 1, 1, 0, 0},
- {"CWORD" , 0, 64, 1009, "RO", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1010, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 1010, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 1010, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1011, "RO", 1, 1, 0, 0},
- {"SOD" , 8, 1, 1011, "RO", 1, 1, 0, 0},
- {"EOD" , 9, 1, 1011, "RO", 1, 1, 0, 0},
- {"WC" , 10, 1, 1011, "RO", 1, 1, 0, 0},
- {"P" , 11, 1, 1011, "RO", 1, 1, 0, 0},
- {"Q" , 12, 1, 1011, "RO", 1, 1, 0, 0},
- {"RESERVED_13_63" , 13, 51, 1011, "RAZ", 1, 1, 0, 0},
- {"ASSERTS" , 0, 15, 1012, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 1012, "RAZ", 1, 1, 0, 0},
- {"OWORDP" , 0, 64, 1013, "RO", 1, 1, 0, 0},
- {"OWORDQ" , 0, 64, 1014, "RO", 1, 1, 0, 0},
- {"RWORD" , 0, 64, 1015, "RO", 1, 1, 0, 0},
- {"N0CREDS" , 0, 4, 1016, "RO", 0, 0, 8ull, 0ull},
- {"N1CREDS" , 4, 4, 1016, "RO", 0, 0, 8ull, 0ull},
- {"POWCREDS" , 8, 2, 1016, "RO", 0, 0, 2ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 1016, "RAZ", 1, 1, 0, 0},
- {"FPACREDS" , 12, 2, 1016, "RO", 0, 0, 1ull, 0ull},
- {"WCCREDS" , 14, 2, 1016, "RO", 0, 0, 0ull, 0ull},
- {"NIWIDX0" , 16, 4, 1016, "RO", 1, 1, 0, 0},
- {"NIRIDX0" , 20, 4, 1016, "RO", 1, 1, 0, 0},
- {"NIWIDX1" , 24, 4, 1016, "RO", 1, 1, 0, 0},
- {"NIRIDX1" , 28, 4, 1016, "RO", 1, 1, 0, 0},
- {"NIRVAL6" , 32, 5, 1016, "RO", 1, 1, 0, 0},
- {"NIRARB6" , 37, 1, 1016, "RO", 1, 1, 0, 0},
- {"NIRQUE6" , 38, 2, 1016, "RO", 1, 1, 0, 0},
- {"NIROPC6" , 40, 3, 1016, "RO", 1, 1, 0, 0},
- {"NIRVAL7" , 43, 5, 1016, "RO", 1, 1, 0, 0},
- {"NIRQUE7" , 48, 2, 1016, "RO", 1, 1, 0, 0},
- {"NIROPC7" , 50, 3, 1016, "RO", 1, 1, 0, 0},
- {"RESERVED_53_63" , 53, 11, 1016, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1017, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 1017, "RO", 1, 1, 0, 0},
- {"CNT" , 56, 8, 1017, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 15, 1018, "RO", 1, 1, 0, 0},
- {"RESERVED_15_63" , 15, 49, 1018, "RAZ", 1, 1, 0, 0},
- {"PTR" , 0, 40, 1019, "RO", 1, 1, 0, 0},
- {"SIZE" , 40, 16, 1019, "RO", 1, 1, 0, 0},
- {"FLAGS" , 56, 8, 1019, "RO", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1020, "RO", 1, 1, 0, 0},
- {"MUL" , 8, 8, 1020, "RO", 1, 1, 0, 0},
- {"P" , 16, 1, 1020, "RO", 1, 1, 0, 0},
- {"Q" , 17, 1, 1020, "RO", 1, 1, 0, 0},
- {"INI" , 18, 1, 1020, "RO", 1, 1, 0, 0},
- {"EOD" , 19, 1, 1020, "RO", 1, 1, 0, 0},
- {"RESERVED_20_63" , 20, 44, 1020, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1021, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1021, "RAZ", 1, 1, 0, 0},
- {"DOORBELL" , 0, 1, 1022, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1022, "RAZ", 1, 1, 0, 0},
- {"COEFFS" , 0, 8, 1023, "R/W", 0, 0, 29ull, 29ull},
- {"RESERVED_8_63" , 8, 56, 1023, "RAZ", 0, 0, 0ull, 0ull},
- {"INDEX" , 0, 16, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 16, 16, 1024, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1024, "RAZ", 1, 1, 0, 0},
- {"MEM" , 0, 1, 1025, "RO", 0, 0, 0ull, 0ull},
- {"RRC" , 1, 1, 1025, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_63" , 2, 62, 1025, "RAZ", 1, 1, 0, 0},
- {"ENT_EN" , 0, 1, 1026, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_EN" , 1, 1, 1026, "R/W", 0, 0, 0ull, 0ull},
- {"RNM_RST" , 2, 1, 1026, "R/W", 0, 0, 0ull, 0ull},
- {"RNG_RST" , 3, 1, 1026, "R/W", 0, 0, 0ull, 0ull},
- {"EXP_ENT" , 4, 1, 1026, "R/W", 0, 0, 0ull, 0ull},
- {"ENT_SEL" , 5, 4, 1026, "R/W", 0, 0, 0ull, 0ull},
- {"EER_VAL" , 9, 1, 1026, "RO", 0, 0, 0ull, 0ull},
- {"EER_LCK" , 10, 1, 1026, "RO", 0, 0, 0ull, 0ull},
- {"DIS_MAK" , 11, 1, 1026, "R/W1", 1, 1, 0, 0},
- {"RESERVED_12_63" , 12, 52, 1026, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 64, 1027, "RO", 1, 1, 0, 0},
- {"KEY" , 0, 64, 1028, "WO", 0, 0, 0ull, 0ull},
- {"DAT" , 0, 64, 1029, "RO", 1, 1, 0, 0},
- {"NCB_CMD" , 0, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"MSI" , 1, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_0" , 2, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"DSI0_1" , 3, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_0" , 4, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"DSI1_1" , 5, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_8" , 6, 3, 1030, "RAZ", 1, 1, 0, 0},
- {"P2N1_P1" , 9, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_P0" , 10, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_N" , 11, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C1" , 12, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"P2N1_C0" , 13, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P1" , 14, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_P0" , 15, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_N" , 16, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C1" , 17, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"P2N0_C0" , 18, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_19_24" , 19, 6, 1030, "RAZ", 1, 1, 0, 0},
- {"CPL_P1" , 25, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"CPL_P0" , 26, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_27_28" , 27, 2, 1030, "RAZ", 1, 1, 0, 0},
- {"N2P0_O" , 29, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"N2P0_C" , 30, 1, 1030, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_31_63" , 31, 33, 1030, "RAZ", 1, 1, 0, 0},
- {"WAIT_COM" , 0, 1, 1031, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_1_4" , 1, 4, 1031, "R/W", 0, 0, 0ull, 0ull},
- {"PTLP_RO" , 5, 1, 1031, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_6" , 6, 1, 1031, "R/W", 0, 0, 0ull, 0ull},
- {"CTLP_RO" , 7, 1, 1031, "R/W", 0, 0, 0ull, 1ull},
- {"INTA_MAP" , 8, 2, 1031, "R/W", 0, 0, 0ull, 0ull},
- {"INTB_MAP" , 10, 2, 1031, "R/W", 0, 0, 1ull, 1ull},
- {"INTC_MAP" , 12, 2, 1031, "R/W", 0, 0, 2ull, 2ull},
- {"INTD_MAP" , 14, 2, 1031, "R/W", 0, 0, 3ull, 3ull},
- {"WAITL_COM" , 16, 1, 1031, "R/W", 0, 1, 0ull, 0},
- {"DIS_PORT" , 17, 1, 1031, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTA" , 18, 1, 1031, "RO", 0, 0, 1ull, 1ull},
- {"INTB" , 19, 1, 1031, "RO", 0, 0, 1ull, 1ull},
- {"INTC" , 20, 1, 1031, "RO", 0, 0, 1ull, 1ull},
- {"INTD" , 21, 1, 1031, "RO", 0, 0, 1ull, 1ull},
- {"RESERVED_22_63" , 22, 42, 1031, "RAZ", 1, 1, 0, 0},
- {"CHIP_REV" , 0, 8, 1032, "RO", 1, 1, 0, 0},
- {"P0_NTAGS" , 8, 6, 1032, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_14_63" , 14, 50, 1032, "R/W", 0, 0, 32ull, 32ull},
- {"P0_FCNT" , 0, 6, 1033, "RO", 0, 1, 0ull, 0},
- {"P0_UCNT" , 6, 16, 1033, "RO", 0, 1, 0ull, 0},
- {"P1_FCNT" , 22, 6, 1033, "RAZ", 0, 1, 0ull, 0},
- {"P1_UCNT" , 28, 16, 1033, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 1033, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 17, 1034, "RO", 0, 1, 0ull, 0},
- {"DSEL_EXT" , 17, 1, 1034, "R/W", 0, 0, 1ull, 0ull},
- {"RESERVED_18_63" , 18, 46, 1034, "RAZ", 1, 1, 0, 0},
- {"DBG_SEL" , 0, 32, 1035, "R/W", 0, 1, 0ull, 0},
- {"ADBG_SEL" , 32, 1, 1035, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_33_63" , 33, 31, 1035, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1036, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1036, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1037, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 32, 1037, "R/W", 0, 1, 0ull, 0},
- {"TIM" , 0, 32, 1038, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1038, "RAZ", 1, 1, 0, 0},
- {"RML_TO" , 0, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 1039, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_18_19" , 18, 2, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UP_B0" , 20, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UP_WI" , 21, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UN_B0" , 22, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UN_WI" , 23, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UP_B0" , 24, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UP_WI" , 25, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UN_B0" , 26, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UN_WI" , 27, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT2_ERR" , 58, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT3_ERR" , 59, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 1039, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_1" , 1, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"BAR0_TO" , 2, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"IOB2BIG" , 3, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"PCNT" , 4, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"PTIME" , 5, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UP_WI" , 9, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_B0" , 10, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"M0_UN_WI" , 11, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_B0" , 12, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UP_WI" , 13, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_B0" , 14, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"M1_UN_WI" , 15, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT0" , 16, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"MIO_INT1" , 17, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"MAC0_INT" , 18, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"MAC1_INT" , 19, 1, 1040, "R/W", 0, 0, 0ull, 1ull},
- {"M2_UP_B0" , 20, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UP_WI" , 21, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UN_B0" , 22, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"M2_UN_WI" , 23, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UP_B0" , 24, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UP_WI" , 25, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UN_B0" , 26, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"M3_UN_WI" , 27, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"DMAFI" , 32, 2, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"PIDBOF" , 48, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT2_ERR" , 58, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"SPRT3_ERR" , 59, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 1040, "R/W", 0, 0, 0ull, 0ull},
- {"RML_TO" , 0, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_1_1" , 1, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"BAR0_TO" , 2, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOB2BIG" , 3, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCNT" , 4, 1, 1041, "RO", 0, 0, 0ull, 0ull},
- {"PTIME" , 5, 1, 1041, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_7" , 6, 2, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_B0" , 8, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UP_WI" , 9, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_B0" , 10, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M0_UN_WI" , 11, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_B0" , 12, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UP_WI" , 13, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_B0" , 14, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M1_UN_WI" , 15, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"MIO_INT0" , 16, 1, 1041, "RO", 0, 0, 0ull, 0ull},
- {"MIO_INT1" , 17, 1, 1041, "RO", 0, 0, 0ull, 0ull},
- {"MAC0_INT" , 18, 1, 1041, "RO", 0, 0, 0ull, 0ull},
- {"MAC1_INT" , 19, 1, 1041, "RO", 0, 0, 0ull, 0ull},
- {"M2_UP_B0" , 20, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M2_UP_WI" , 21, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M2_UN_B0" , 22, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M2_UN_WI" , 23, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UP_B0" , 24, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UP_WI" , 25, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UN_B0" , 26, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"M3_UN_WI" , 27, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_28_31" , 28, 4, 1041, "RAZ", 1, 1, 0, 0},
- {"DMAFI" , 32, 2, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"DCNT" , 34, 2, 1041, "RO", 0, 0, 0ull, 0ull},
- {"DTIME" , 36, 2, 1041, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_38_47" , 38, 10, 1041, "RAZ", 1, 1, 0, 0},
- {"PIDBOF" , 48, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"PSLDBOF" , 49, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"POUT_ERR" , 50, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"PIN_BP" , 51, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"PGL_ERR" , 52, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"PDI_ERR" , 53, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"POP_ERR" , 54, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"PINS_ERR" , 55, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT0_ERR" , 56, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT1_ERR" , 57, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT2_ERR" , 58, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"SPRT3_ERR" , 59, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"ILL_PAD" , 60, 1, 1041, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_61_63" , 61, 3, 1041, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 1042, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 1043, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 1044, "RO", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 1045, "RO", 0, 1, 0ull, 0},
- {"P0_PCNT" , 0, 8, 1046, "R/W", 0, 0, 128ull, 128ull},
- {"P0_NCNT" , 8, 8, 1046, "R/W", 0, 0, 16ull, 16ull},
- {"P0_CCNT" , 16, 8, 1046, "R/W", 0, 0, 128ull, 128ull},
- {"P1_PCNT" , 24, 8, 1046, "R/W", 0, 0, 128ull, 128ull},
- {"P1_NCNT" , 32, 8, 1046, "R/W", 0, 0, 16ull, 16ull},
- {"P1_CCNT" , 40, 8, 1046, "R/W", 0, 0, 128ull, 128ull},
- {"P0_P_D" , 48, 1, 1046, "R/W", 0, 0, 1ull, 1ull},
- {"P0_N_D" , 49, 1, 1046, "R/W", 0, 0, 1ull, 1ull},
- {"P0_C_D" , 50, 1, 1046, "R/W", 0, 0, 1ull, 1ull},
- {"P1_P_D" , 51, 1, 1046, "R/W", 0, 0, 1ull, 1ull},
- {"P1_N_D" , 52, 1, 1046, "R/W", 0, 0, 1ull, 1ull},
- {"P1_C_D" , 53, 1, 1046, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_54_63" , 54, 10, 1046, "RAZ", 1, 1, 0, 0},
- {"P2_PCNT" , 0, 8, 1047, "R/W", 0, 0, 128ull, 128ull},
- {"P2_NCNT" , 8, 8, 1047, "R/W", 0, 0, 16ull, 16ull},
- {"P2_CCNT" , 16, 8, 1047, "R/W", 0, 0, 128ull, 128ull},
- {"P3_PCNT" , 24, 8, 1047, "R/W", 0, 0, 128ull, 128ull},
- {"P3_NCNT" , 32, 8, 1047, "R/W", 0, 0, 16ull, 16ull},
- {"P3_CCNT" , 40, 8, 1047, "R/W", 0, 0, 128ull, 128ull},
- {"P2_P_D" , 48, 1, 1047, "R/W", 0, 0, 1ull, 1ull},
- {"P2_N_D" , 49, 1, 1047, "R/W", 0, 0, 1ull, 1ull},
- {"P2_C_D" , 50, 1, 1047, "R/W", 0, 0, 1ull, 1ull},
- {"P3_P_D" , 51, 1, 1047, "R/W", 0, 0, 1ull, 1ull},
- {"P3_N_D" , 52, 1, 1047, "R/W", 0, 0, 1ull, 1ull},
- {"P3_C_D" , 53, 1, 1047, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_54_63" , 54, 10, 1047, "RAZ", 1, 1, 0, 0},
- {"NUM" , 0, 8, 1048, "RO", 1, 1, 0, 0},
- {"A_MODE" , 8, 1, 1048, "RO", 1, 1, 0, 0},
- {"RESERVED_9_63" , 9, 55, 1048, "RAZ", 1, 1, 0, 0},
- {"TIMER" , 0, 10, 1049, "R/W", 0, 0, 0ull, 50ull},
- {"MAX_WORD" , 10, 4, 1049, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_63" , 14, 50, 1049, "RAZ", 1, 1, 0, 0},
- {"BA" , 0, 30, 1050, "R/W", 0, 1, 0ull, 0},
- {"RTYPE" , 30, 2, 1050, "R/W", 0, 1, 0ull, 0},
- {"WTYPE" , 32, 2, 1050, "R/W", 0, 1, 0ull, 0},
- {"ESW" , 34, 2, 1050, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 36, 2, 1050, "R/W", 0, 1, 0ull, 0},
- {"NMERGE" , 38, 1, 1050, "R/W", 0, 0, 0ull, 0ull},
- {"PORT" , 39, 3, 1050, "R/W", 0, 1, 0ull, 0},
- {"ZERO" , 42, 1, 1050, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 1050, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 64, 1051, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 1052, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 1053, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"ENB" , 0, 64, 1054, "R/W", 0, 0, 0ull, 18446744073709551615ull},
- {"INTR" , 0, 64, 1055, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 1056, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 1057, "R/W1C", 0, 0, 0ull, 0ull},
- {"INTR" , 0, 64, 1058, "R/W1C", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 1059, "R/W", 0, 1, 0ull, 0},
- {"RD_INT" , 8, 8, 1059, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1059, "RAZ", 1, 1, 0, 0},
- {"CLR" , 0, 64, 1060, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 1061, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 1062, "R/W", 0, 0, 0ull, 0ull},
- {"CLR" , 0, 64, 1063, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1064, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1065, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1066, "R/W", 0, 0, 0ull, 0ull},
- {"SET" , 0, 64, 1067, "R/W", 0, 0, 0ull, 0ull},
- {"MSI_INT" , 0, 8, 1068, "R/W", 0, 1, 0ull, 0},
- {"CIU_INT" , 8, 8, 1068, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1068, "RAZ", 1, 1, 0, 0},
- {"INTR" , 0, 8, 1069, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_63" , 8, 56, 1069, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1070, "RAZ", 1, 1, 0, 0},
- {"INTR" , 8, 8, 1070, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_63" , 16, 48, 1070, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_15" , 0, 16, 1071, "RAZ", 1, 1, 0, 0},
- {"INTR" , 16, 8, 1071, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_24_63" , 24, 40, 1071, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_23" , 0, 24, 1072, "RAZ", 1, 1, 0, 0},
- {"INTR" , 24, 8, 1072, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1072, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1073, "R/W", 0, 0, 0ull, 0ull},
- {"TIMER" , 32, 22, 1073, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_54_63" , 54, 10, 1073, "RO", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1074, "R/W", 0, 0, 0ull, 0ull},
- {"WMARK" , 32, 32, 1074, "R/W", 0, 1, 4294967295ull, 0},
- {"RESERVED_0_2" , 0, 3, 1075, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 3, 61, 1075, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 1076, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 1076, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 1077, "R/W", 0, 1, 0ull, 0},
- {"FCNT" , 32, 5, 1077, "RO", 0, 1, 0ull, 0},
- {"WRP" , 37, 9, 1077, "RO", 0, 1, 0ull, 0},
- {"RRP" , 46, 9, 1077, "RO", 0, 1, 0ull, 0},
- {"MAX" , 55, 9, 1077, "RO", 0, 1, 16ull, 0},
- {"NTAG" , 0, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"NTT" , 1, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"NGRP" , 2, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"NQOS" , 3, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_4_5" , 4, 2, 1078, "R/W", 0, 1, 0ull, 0},
- {"SKP_LEN" , 6, 7, 1078, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_13" , 13, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"PAR_MODE" , 14, 2, 1078, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_16_20" , 16, 5, 1078, "R/W", 0, 1, 0ull, 0},
- {"USE_IHDR" , 21, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"RNTAG" , 22, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"RNTT" , 23, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"RNGRP" , 24, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"RNQOS" , 25, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_26_27" , 26, 2, 1078, "R/W", 0, 1, 0ull, 0},
- {"RSKP_LEN" , 28, 7, 1078, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_35_35" , 35, 1, 1078, "RAZ", 0, 1, 0ull, 0},
- {"RPARMODE" , 36, 2, 1078, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_42" , 38, 5, 1078, "RAZ", 0, 1, 0ull, 0},
- {"PBP" , 43, 1, 1078, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_44_63" , 44, 20, 1078, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 16, 1079, "R/W", 0, 1, 0ull, 0},
- {"ISIZE" , 16, 7, 1079, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_23_63" , 23, 41, 1079, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_3" , 0, 4, 1080, "RAZ", 1, 1, 0, 0},
- {"ADDR" , 4, 60, 1080, "R/W", 0, 1, 0ull, 0},
- {"DBELL" , 0, 32, 1081, "R/W", 0, 0, 0ull, 0ull},
- {"AOFF" , 32, 32, 1081, "RO", 0, 1, 0ull, 0},
- {"RSIZE" , 0, 32, 1082, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1082, "RO", 0, 1, 0ull, 0},
- {"PORT" , 0, 32, 1083, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1083, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1084, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1084, "RAZ", 1, 1, 0, 0},
- {"PKT_BP" , 0, 4, 1085, "R/W", 0, 0, 15ull, 15ull},
- {"RING_EN" , 4, 1, 1085, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1085, "RAZ", 1, 1, 0, 0},
- {"ES" , 0, 64, 1086, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 1087, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1087, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 1088, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1088, "RAZ", 1, 1, 0, 0},
- {"DPTR" , 0, 32, 1089, "R/W", 0, 0, 0ull, 4294967295ull},
- {"RESERVED_32_63" , 32, 32, 1089, "RAZ", 1, 1, 0, 0},
- {"BP" , 0, 32, 1090, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1090, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1091, "RO", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1091, "RO", 0, 1, 0ull, 0},
- {"RD_CNT" , 0, 32, 1092, "RO", 0, 1, 0ull, 0},
- {"WR_CNT" , 32, 32, 1092, "RO", 0, 1, 0ull, 0},
- {"PP" , 0, 64, 1093, "R/W", 0, 1, 0ull, 0},
- {"ROR" , 0, 1, 1094, "R/W", 0, 1, 0ull, 0},
- {"ESR" , 1, 2, 1094, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 3, 1, 1094, "R/W", 0, 1, 0ull, 0},
- {"USE_CSR" , 4, 1, 1094, "R/W", 0, 0, 0ull, 1ull},
- {"D_ROR" , 5, 1, 1094, "R/W", 0, 1, 0ull, 0},
- {"D_ESR" , 6, 2, 1094, "R/W", 0, 1, 0ull, 0},
- {"D_NSR" , 8, 1, 1094, "R/W", 0, 1, 0ull, 0},
- {"PBP_DHI" , 9, 13, 1094, "R/W", 0, 0, 0ull, 0ull},
- {"PKT_RR" , 22, 1, 1094, "R/W", 0, 0, 0ull, 1ull},
- {"PIN_RST" , 23, 1, 1094, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_24_39" , 24, 16, 1094, "RAZ", 1, 1, 0, 0},
- {"PRC_IDLE" , 40, 1, 1094, "RO", 0, 1, 0ull, 0},
- {"RESERVED_41_47" , 41, 7, 1094, "RAZ", 1, 1, 0, 0},
- {"GII_RDS" , 48, 7, 1094, "RO", 0, 1, 0ull, 0},
- {"GII_ERST" , 55, 1, 1094, "RO", 0, 1, 0ull, 0},
- {"PRD_RDS" , 56, 7, 1094, "RO", 0, 1, 0ull, 0},
- {"PRD_ERST" , 63, 1, 1094, "RO", 0, 1, 0ull, 0},
- {"ENB" , 0, 32, 1095, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1095, "RAZ", 1, 1, 0, 0},
- {"RDSIZE" , 0, 64, 1096, "R/W", 0, 1, 0ull, 0},
- {"IS_64B" , 0, 32, 1097, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1097, "RAZ", 1, 1, 0, 0},
- {"CNT" , 0, 32, 1098, "R/W", 0, 1, 0ull, 0},
- {"TIME" , 32, 22, 1098, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_54_63" , 54, 10, 1098, "RAZ", 1, 1, 0, 0},
- {"IPTR" , 0, 32, 1099, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1099, "RAZ", 1, 1, 0, 0},
- {"BMODE" , 0, 32, 1100, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1100, "RAZ", 1, 1, 0, 0},
- {"ENB" , 0, 32, 1101, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1101, "RAZ", 1, 1, 0, 0},
- {"WMARK" , 0, 32, 1102, "R/W", 0, 0, 0ull, 14ull},
- {"RESERVED_32_63" , 32, 32, 1102, "RAZ", 1, 1, 0, 0},
- {"PP" , 0, 64, 1103, "R/W", 0, 1, 0ull, 0},
- {"OUT_RST" , 0, 32, 1104, "RO", 0, 1, 0ull, 0},
- {"IN_RST" , 32, 32, 1104, "RO", 0, 1, 0ull, 0},
- {"ES" , 0, 64, 1105, "R/W", 0, 1, 0ull, 0},
- {"NSR" , 0, 32, 1106, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1106, "RAZ", 1, 1, 0, 0},
- {"ROR" , 0, 32, 1107, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1107, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1108, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1108, "RAZ", 1, 1, 0, 0},
- {"PORT" , 0, 32, 1109, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_32_63" , 32, 32, 1109, "RAZ", 1, 1, 0, 0},
- {"MRRS" , 0, 3, 1110, "R/W", 0, 0, 2ull, 2ull},
- {"BAR0_D" , 3, 1, 1110, "R/W", 1, 1, 0, 0},
- {"WIND_D" , 4, 1, 1110, "R/W", 1, 1, 0, 0},
- {"RESERVED_5_63" , 5, 59, 1110, "RAZ", 1, 1, 0, 0},
- {"DATA" , 0, 64, 1111, "R/W", 0, 1, 0ull, 0},
- {"DATA" , 0, 64, 1112, "R/W", 0, 1, 0ull, 0},
- {"CSR" , 0, 39, 1113, "RO", 0, 1, 1ull, 0},
- {"ARB" , 39, 1, 1113, "RO", 0, 1, 0ull, 0},
- {"CPL0" , 40, 12, 1113, "RO", 0, 1, 1ull, 0},
- {"CPL1" , 52, 12, 1113, "RO", 0, 1, 1ull, 0},
- {"NND" , 0, 8, 1114, "RO", 0, 1, 1ull, 0},
- {"NNP0" , 8, 8, 1114, "RO", 0, 1, 1ull, 0},
- {"CSM0" , 16, 15, 1114, "RO", 0, 1, 1ull, 0},
- {"CSM1" , 31, 15, 1114, "RO", 0, 1, 1ull, 0},
- {"RAC" , 46, 1, 1114, "RO", 0, 1, 1ull, 0},
- {"RESERVED_47_47" , 47, 1, 1114, "RAZ", 1, 1, 0, 0},
- {"NNP1" , 48, 8, 1114, "RAZ", 0, 1, 0ull, 0},
- {"RESERVED_56_63" , 56, 8, 1114, "RAZ", 1, 1, 0, 0},
- {"NSM0" , 0, 13, 1115, "RO", 0, 1, 1ull, 0},
- {"NSM1" , 13, 13, 1115, "RO", 0, 1, 1ull, 0},
- {"PSM0" , 26, 15, 1115, "RO", 0, 1, 1ull, 0},
- {"PSM1" , 41, 15, 1115, "RO", 0, 1, 1ull, 0},
- {"RESERVED_56_63" , 56, 8, 1115, "RAZ", 1, 1, 0, 0},
- {"RD_ADDR" , 0, 48, 1116, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 1116, "R/W", 0, 0, 0ull, 0ull},
- {"LD_CMD" , 49, 2, 1116, "R/W", 0, 1, 3ull, 0},
- {"RESERVED_51_63" , 51, 13, 1116, "RAZ", 1, 1, 0, 0},
- {"RD_DATA" , 0, 64, 1117, "RO", 0, 1, 0ull, 0},
- {"RESERVED_0_2" , 0, 3, 1118, "RAZ", 1, 1, 0, 0},
- {"WR_ADDR" , 3, 45, 1118, "R/W", 0, 1, 0ull, 0},
- {"IOBIT" , 48, 1, 1118, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_49_63" , 49, 15, 1118, "RAZ", 1, 1, 0, 0},
- {"WR_DATA" , 0, 64, 1119, "R/W", 0, 1, 0ull, 0},
- {"WR_MASK" , 0, 8, 1120, "R/W", 0, 0, 255ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1120, "RAZ", 1, 1, 0, 0},
- {"TIME" , 0, 32, 1121, "R/W", 0, 0, 0ull, 2097152ull},
- {"RESERVED_32_63" , 32, 32, 1121, "RAZ", 1, 1, 0, 0},
- {"PHASE" , 0, 8, 1122, "R/W", 0, 0, 100ull, 100ull},
- {"SAMPLE" , 8, 4, 1122, "R/W", 0, 0, 2ull, 2ull},
- {"PREAMBLE" , 12, 1, 1122, "R/W", 0, 0, 1ull, 1ull},
- {"CLK_IDLE" , 13, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_14" , 14, 1, 1122, "RAZ", 1, 1, 0, 0},
- {"SAMPLE_MODE" , 15, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"SAMPLE_HI" , 16, 5, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_21_23" , 21, 3, 1122, "RAZ", 1, 1, 0, 0},
- {"MODE" , 24, 1, 1122, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1122, "RAZ", 1, 1, 0, 0},
- {"REG_ADR" , 0, 5, 1123, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1123, "RAZ", 1, 1, 0, 0},
- {"PHY_ADR" , 8, 5, 1123, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_13_15" , 13, 3, 1123, "RAZ", 1, 1, 0, 0},
- {"PHY_OP" , 16, 2, 1123, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1123, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1124, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1124, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 1125, "RO", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 1125, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 1125, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1125, "RAZ", 1, 1, 0, 0},
- {"DAT" , 0, 16, 1126, "R/W", 0, 1, 0ull, 0},
- {"VAL" , 16, 1, 1126, "RO", 0, 1, 0ull, 0},
- {"PENDING" , 17, 1, 1126, "RO", 0, 1, 0ull, 0},
- {"RESERVED_18_63" , 18, 46, 1126, "RAZ", 1, 1, 0, 0},
- {"NCTL" , 0, 6, 1127, "R/W", 0, 0, 15ull, 15ull},
- {"RESERVED_6_7" , 6, 2, 1127, "RAZ", 1, 1, 0, 0},
- {"PCTL" , 8, 6, 1127, "R/W", 0, 0, 19ull, 19ull},
- {"RESERVED_14_63" , 14, 50, 1127, "RAZ", 1, 1, 0, 0},
- {"INTERVAL" , 0, 22, 1128, "RO", 1, 0, 0, 0ull},
- {"RESERVED_22_23" , 22, 2, 1128, "RAZ", 1, 1, 0, 0},
- {"COUNT" , 24, 22, 1128, "RO", 1, 0, 0, 0ull},
- {"RESERVED_46_46" , 46, 1, 1128, "RAZ", 1, 1, 0, 0},
- {"ENA" , 47, 1, 1128, "RO", 1, 0, 0, 0ull},
- {"RESERVED_48_63" , 48, 16, 1128, "RAZ", 1, 1, 0, 0},
- {"BSIZE" , 0, 20, 1129, "RO", 1, 0, 0, 0ull},
- {"BASE" , 20, 31, 1129, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 51, 13, 1129, "RO", 1, 0, 0, 0ull},
- {"BUCKET" , 0, 7, 1130, "RO", 1, 0, 0, 0ull},
- {"RESERVED_7_7" , 7, 1, 1130, "RO", 1, 0, 0, 0ull},
- {"CSIZE" , 8, 13, 1130, "RO", 1, 0, 0, 0ull},
- {"CPOOL" , 21, 3, 1130, "RO", 1, 0, 0, 0ull},
- {"RESERVED_24_63" , 24, 40, 1130, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"NUM_BUCKETS" , 4, 20, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"FIRST_BUCKET" , 24, 31, 1131, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_55_63" , 55, 9, 1131, "RAZ", 1, 1, 0, 0},
- {"RING" , 0, 4, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"INTERVAL" , 4, 22, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"WORDS_PER_CHUNK" , 26, 13, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"POOL" , 39, 3, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE" , 42, 1, 1132, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_43_63" , 43, 21, 1132, "RAZ", 1, 1, 0, 0},
- {"CTL" , 0, 1, 1133, "RO", 1, 0, 0, 0ull},
- {"NCB" , 1, 1, 1133, "RO", 1, 0, 0, 0ull},
- {"STA" , 2, 2, 1133, "RO", 1, 0, 0, 0ull},
- {"RESERVED_4_63" , 4, 60, 1133, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1134, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1134, "RAZ", 1, 1, 0, 0},
- {"ENABLE_TIMERS" , 0, 1, 1135, "R/W", 0, 0, 0ull, 0ull},
- {"ENABLE_DWB" , 1, 1, 1135, "R/W", 0, 0, 0ull, 0ull},
- {"RESET" , 2, 1, 1135, "RAZ", 0, 0, 0ull, 0ull},
- {"RESERVED_3_63" , 3, 61, 1135, "RAZ", 1, 1, 0, 0},
- {"MASK" , 0, 16, 1136, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1136, "RAZ", 1, 1, 0, 0},
- {"INDEX" , 0, 8, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"INC" , 8, 8, 1137, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_16_63" , 16, 48, 1137, "RAZ", 1, 1, 0, 0},
- {"TDF" , 0, 1, 1138, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_1_63" , 1, 63, 1138, "RAZ", 0, 0, 0ull, 0ull},
- {"ENA" , 0, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"WRAP" , 1, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"TRIG_CTL" , 2, 2, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"TIME_GRN" , 4, 3, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"FULL_THR" , 7, 2, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 9, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 10, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 11, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 12, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"MCD0_ENA" , 13, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"IGNORE_O" , 14, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"CLKALWAYS" , 15, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"RDAT_MD" , 16, 1, 1139, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_17_63" , 17, 47, 1139, "RAZ", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 8, 1140, "RO", 0, 0, 0ull, 0ull},
- {"RPTR" , 8, 8, 1140, "RO", 0, 0, 0ull, 0ull},
- {"CYCLES" , 16, 48, 1140, "RO", 0, 0, 0ull, 0ull},
- {"WPTR" , 0, 10, 1141, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_11" , 10, 2, 1141, "RAZ", 1, 1, 0, 0},
- {"RPTR" , 12, 10, 1141, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_22_23" , 22, 2, 1141, "RAZ", 1, 1, 0, 0},
- {"CYCLES" , 24, 40, 1141, "RO", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1142, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1142, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1143, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1143, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1144, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1144, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1145, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1145, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1145, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1145, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1145, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 4, 1146, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1146, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1146, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1146, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1146, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1146, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1146, "R/W", 0, 0, 0ull, 0ull},
- {"CIU_TRG" , 0, 1, 1147, "R/W1C", 0, 0, 0ull, 0ull},
- {"CIU_THR" , 1, 1, 1147, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_TRG" , 2, 1, 1147, "R/W1C", 0, 0, 0ull, 0ull},
- {"MCD0_THR" , 3, 1, 1147, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_4_63" , 4, 60, 1147, "RAZ", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 64, 1148, "RO", 0, 0, 0ull, 0ull},
- {"DATA" , 0, 5, 1149, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_63" , 5, 59, 1149, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1150, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1150, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1151, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1151, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1152, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1152, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1153, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1153, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1153, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1153, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1153, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 4, 1154, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1154, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1154, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1154, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1154, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1154, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1154, "R/W", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1155, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_38_63" , 38, 26, 1155, "RAZ", 0, 0, 0ull, 0ull},
- {"ADR" , 0, 38, 1156, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_38_63" , 38, 26, 1156, "RAZ", 0, 0, 0ull, 0ull},
- {"NOP" , 0, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"LDT" , 1, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"LDI" , 2, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"PL2" , 3, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"RPL2" , 4, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"DWB" , 5, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_6_7" , 6, 2, 1157, "R/W", 0, 0, 0ull, 0ull},
- {"LDD" , 8, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"PSL1" , 9, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_10_14" , 10, 5, 1157, "R/W", 0, 0, 0ull, 0ull},
- {"IOBDMA" , 15, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"STF" , 16, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"STT" , 17, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"STP" , 18, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"STC" , 19, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"STFIL1" , 20, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"STTIL1" , 21, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"FAS32" , 22, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"FAS64" , 23, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2I" , 24, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"LTGL2I" , 25, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"STGL2I" , 26, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_27_27" , 27, 1, 1157, "R/W", 0, 0, 0ull, 0ull},
- {"INVL2" , 28, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"WBIL2" , 29, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"WBL2" , 30, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"LCKL2" , 31, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD8" , 32, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD16" , 33, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD32" , 34, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"IOBLD64" , 35, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST8" , 36, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST16" , 37, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST32" , 38, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"IOBST64" , 39, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"SET8" , 40, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"SET16" , 41, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"SET32" , 42, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"SET64" , 43, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"CLR8" , 44, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"CLR16" , 45, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"CLR32" , 46, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"CLR64" , 47, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"INCR8" , 48, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"INCR16" , 49, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"INCR32" , 50, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"INCR64" , 51, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"DECR8" , 52, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"DECR16" , 53, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"DECR32" , 54, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"DECR64" , 55, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_56_57" , 56, 2, 1157, "R/W", 0, 0, 0ull, 0ull},
- {"FAA32" , 58, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"FAA64" , 59, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_60_61" , 60, 2, 1157, "R/W", 0, 0, 0ull, 0ull},
- {"SAA32" , 62, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"SAA64" , 63, 1, 1157, "R/W", 0, 0, 0ull, 1ull},
- {"MIO" , 0, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL3" , 1, 2, 1158, "R/W", 0, 0, 0ull, 3ull},
- {"SLI" , 3, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"KEY" , 4, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"FPA" , 5, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"DFA" , 6, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"ZIP" , 7, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"RNG" , 8, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"IPD" , 9, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"PKO" , 10, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL2" , 11, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"POW" , 12, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"USB0" , 13, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"RAD" , 14, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL" , 15, 12, 1158, "R/W", 0, 0, 0ull, 4095ull},
- {"DPI" , 27, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL4" , 28, 2, 1158, "R/W", 0, 0, 0ull, 3ull},
- {"FAU" , 30, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"ILLEGAL5" , 31, 1, 1158, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_32_63" , 32, 32, 1158, "RAZ", 0, 0, 0ull, 0ull},
- {"PP" , 0, 4, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"PKI" , 16, 1, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"PKO" , 17, 1, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"IOBREQ" , 18, 1, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"DWB" , 19, 1, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1159, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_4" , 0, 5, 1160, "R/W", 0, 1, 0ull, 0},
- {"LPL" , 5, 27, 1160, "R/W", 0, 1, 0ull, 0},
- {"CF" , 0, 1, 1161, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_31" , 1, 31, 1161, "R/W", 0, 0, 0ull, 0ull},
- {"CTRLDSSEG" , 0, 32, 1162, "R/W", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1163, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_14_31" , 14, 18, 1163, "RO", 0, 0, 0ull, 0ull},
- {"CAPLENGTH" , 0, 8, 1164, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_15" , 8, 8, 1164, "RO", 0, 0, 0ull, 0ull},
- {"HCIVERSION" , 16, 16, 1164, "RO", 0, 0, 256ull, 256ull},
- {"AC64" , 0, 1, 1165, "RO", 0, 0, 1ull, 1ull},
- {"PFLF" , 1, 1, 1165, "RO", 0, 0, 0ull, 0ull},
- {"ASPC" , 2, 1, 1165, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1165, "RO", 0, 0, 0ull, 0ull},
- {"IST" , 4, 4, 1165, "RO", 0, 0, 2ull, 2ull},
- {"EECP" , 8, 8, 1165, "RO", 0, 0, 160ull, 160ull},
- {"RESERVED_16_31" , 16, 16, 1165, "RO", 0, 0, 0ull, 0ull},
- {"N_PORTS" , 0, 4, 1166, "RO", 0, 0, 2ull, 2ull},
- {"PPC" , 4, 1, 1166, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_5_6" , 5, 2, 1166, "RO", 0, 0, 0ull, 0ull},
- {"PRR" , 7, 1, 1166, "RO", 0, 0, 0ull, 0ull},
- {"N_PCC" , 8, 4, 1166, "RO", 0, 0, 2ull, 2ull},
- {"N_CC" , 12, 4, 1166, "RO", 0, 0, 1ull, 1ull},
- {"P_INDICATOR" , 16, 1, 1166, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_17_19" , 17, 3, 1166, "RO", 0, 0, 0ull, 0ull},
- {"DPN" , 20, 4, 1166, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_24_31" , 24, 8, 1166, "RO", 0, 0, 0ull, 0ull},
- {"EN" , 0, 1, 1167, "R/W", 0, 0, 0ull, 0ull},
- {"MFMC" , 1, 13, 1167, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_14_31" , 14, 18, 1167, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_0" , 0, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"TA_OFF" , 1, 8, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"TXTX_TADAO" , 10, 3, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_13_31" , 13, 19, 1168, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_RW" , 0, 1, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"HCP_FW" , 1, 1, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"PESD" , 2, 1, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_3_3" , 3, 1, 1169, "RAZ", 0, 0, 0ull, 0ull},
- {"NAKRF_DIS" , 4, 1, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"AUTO_DIS" , 5, 1, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_6_31" , 6, 26, 1169, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_30" , 0, 31, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1170, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1171, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_11" , 0, 12, 1172, "R/W", 0, 1, 0ull, 0},
- {"BADDR" , 12, 20, 1172, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1173, "RO", 0, 0, 0ull, 0ull},
- {"CSC" , 1, 1, 1173, "R/W1C", 0, 0, 0ull, 0ull},
- {"PED" , 2, 1, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"PEDC" , 3, 1, 1173, "R/W1C", 0, 0, 0ull, 0ull},
- {"OCA" , 4, 1, 1173, "RO", 0, 0, 0ull, 0ull},
- {"OCC" , 5, 1, 1173, "R/W1C", 0, 0, 0ull, 0ull},
- {"FPR" , 6, 1, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"SPD" , 7, 1, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"PRST" , 8, 1, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_9_9" , 9, 1, 1173, "RO", 0, 0, 0ull, 0ull},
- {"LSTS" , 10, 2, 1173, "RO", 0, 1, 0ull, 0},
- {"PP" , 12, 1, 1173, "RO", 0, 0, 1ull, 1ull},
- {"PO" , 13, 1, 1173, "R/W", 0, 0, 1ull, 0ull},
- {"PIC" , 14, 2, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"PTC" , 16, 4, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"WKCNNT_E" , 20, 1, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"WKDSCNNT_E" , 21, 1, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"WKOC_E" , 22, 1, 1173, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_23_31" , 23, 9, 1173, "RO", 0, 0, 0ull, 0ull},
- {"RS" , 0, 1, 1174, "R/W", 0, 0, 0ull, 1ull},
- {"HCRESET" , 1, 1, 1174, "R/W", 0, 0, 0ull, 0ull},
- {"FLS" , 2, 2, 1174, "RO", 0, 0, 0ull, 0ull},
- {"PS_EN" , 4, 1, 1174, "R/W", 0, 0, 0ull, 0ull},
- {"AS_EN" , 5, 1, 1174, "R/W", 0, 0, 0ull, 0ull},
- {"IAA_DB" , 6, 1, 1174, "R/W", 0, 0, 0ull, 0ull},
- {"LHCR" , 7, 1, 1174, "R/W", 0, 0, 0ull, 0ull},
- {"ASPMC" , 8, 2, 1174, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_10" , 10, 1, 1174, "RO", 0, 0, 0ull, 0ull},
- {"ASPM_EN" , 11, 1, 1174, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_12_15" , 12, 4, 1174, "RO", 0, 0, 0ull, 0ull},
- {"ITC" , 16, 8, 1174, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_24_31" , 24, 8, 1174, "RO", 0, 0, 0ull, 0ull},
- {"USBINT_EN" , 0, 1, 1175, "R/W", 0, 1, 0ull, 0},
- {"USBERRINT_EN" , 1, 1, 1175, "R/W", 0, 1, 0ull, 0},
- {"PCI_EN" , 2, 1, 1175, "R/W", 0, 1, 0ull, 0},
- {"FLRO_EN" , 3, 1, 1175, "R/W", 0, 1, 0ull, 0},
- {"HSERR_EN" , 4, 1, 1175, "R/W", 0, 1, 0ull, 0},
- {"IOAA_EN" , 5, 1, 1175, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_6_31" , 6, 26, 1175, "RO", 0, 0, 0ull, 0ull},
- {"USBINT" , 0, 1, 1176, "R/W1C", 0, 0, 0ull, 0ull},
- {"USBERRINT" , 1, 1, 1176, "R/W1C", 0, 0, 0ull, 0ull},
- {"PCD" , 2, 1, 1176, "R/W1C", 0, 0, 0ull, 0ull},
- {"FLRO" , 3, 1, 1176, "R/W1C", 0, 0, 0ull, 0ull},
- {"HSYSERR" , 4, 1, 1176, "R/W1C", 0, 0, 0ull, 0ull},
- {"IOAA" , 5, 1, 1176, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_6_11" , 6, 6, 1176, "RO", 0, 0, 0ull, 0ull},
- {"HCHTD" , 12, 1, 1176, "RO", 0, 0, 1ull, 0ull},
- {"RECLM" , 13, 1, 1176, "RO", 0, 0, 0ull, 0ull},
- {"PSS" , 14, 1, 1176, "RO", 0, 0, 0ull, 0ull},
- {"ASS" , 15, 1, 1176, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_16_31" , 16, 16, 1176, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1177, "R/W", 0, 0, 0ull, 0ull},
- {"BCED" , 4, 28, 1177, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1178, "R/W", 0, 0, 0ull, 0ull},
- {"BHED" , 4, 28, 1178, "R/W", 0, 1, 0ull, 0},
- {"HCR" , 0, 1, 1179, "R/W", 0, 0, 0ull, 0ull},
- {"CLF" , 1, 1, 1179, "R/W", 0, 0, 0ull, 0ull},
- {"BLF" , 2, 1, 1179, "R/W", 0, 0, 0ull, 0ull},
- {"OCR" , 3, 1, 1179, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_15" , 4, 12, 1179, "RO", 0, 0, 0ull, 0ull},
- {"SOC" , 16, 2, 1179, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_18_31" , 18, 14, 1179, "RO", 0, 0, 0ull, 0ull},
- {"CBSR" , 0, 2, 1180, "R/W", 0, 1, 0ull, 0},
- {"PLE" , 2, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"IE" , 3, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"CLE" , 4, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"BLE" , 5, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"HCFS" , 6, 2, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"IR" , 8, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"RWC" , 9, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"RWE" , 10, 1, 1180, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_11_31" , 11, 21, 1180, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1181, "R/W", 0, 0, 0ull, 0ull},
- {"CCED" , 4, 28, 1181, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1182, "R/W", 0, 0, 0ull, 0ull},
- {"CHED" , 4, 28, 1182, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_0_3" , 0, 4, 1183, "RO", 0, 0, 0ull, 0ull},
- {"DH" , 4, 28, 1183, "RO", 0, 1, 0ull, 0},
- {"FI" , 0, 14, 1184, "R/W", 0, 1, 11999ull, 0},
- {"RESERVED_14_15" , 14, 2, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"FSMPS" , 16, 15, 1184, "R/W", 0, 1, 0ull, 0},
- {"FIT" , 31, 1, 1184, "R/W", 0, 0, 0ull, 0ull},
- {"FN" , 0, 16, 1185, "RO", 0, 1, 0ull, 0},
- {"RESERVED_16_31" , 16, 16, 1185, "RO", 0, 0, 0ull, 0ull},
- {"FR" , 0, 14, 1186, "RO", 0, 1, 0ull, 0},
- {"RESERVED_14_30" , 14, 17, 1186, "RO", 0, 0, 0ull, 0ull},
- {"FRT" , 31, 1, 1186, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_0_7" , 0, 8, 1187, "R/W", 0, 0, 0ull, 0ull},
- {"HCCA" , 8, 24, 1187, "R/W", 0, 1, 0ull, 0},
- {"SO" , 0, 1, 1188, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1188, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1188, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1188, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1188, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1188, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1188, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1188, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1188, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1188, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1189, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"MIE" , 31, 1, 1189, "R/W", 0, 0, 0ull, 0ull},
- {"SO" , 0, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"WDH" , 1, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"SF" , 2, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"RD" , 3, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"UE" , 4, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"FNO" , 5, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"RHSC" , 6, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_7_29" , 7, 23, 1190, "RO", 0, 0, 0ull, 0ull},
- {"OC" , 30, 1, 1190, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_31_31" , 31, 1, 1190, "RO", 0, 0, 0ull, 0ull},
- {"LST" , 0, 12, 1191, "R/W", 0, 1, 1576ull, 0},
- {"RESERVED_12_31" , 12, 20, 1191, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_0_3" , 0, 4, 1192, "RO", 0, 0, 0ull, 0ull},
- {"PCED" , 4, 28, 1192, "RO", 0, 1, 0ull, 0},
- {"PS" , 0, 14, 1193, "R/W", 0, 0, 0ull, 15975ull},
- {"RESERVED_14_31" , 14, 18, 1193, "R/W", 0, 0, 0ull, 0ull},
- {"REV" , 0, 8, 1194, "RO", 0, 0, 16ull, 16ull},
- {"RESERVED_8_31" , 8, 24, 1194, "RO", 0, 0, 0ull, 0ull},
- {"NDP" , 0, 8, 1195, "RO", 0, 0, 2ull, 2ull},
- {"NPS" , 8, 1, 1195, "R/W", 0, 0, 0ull, 0ull},
- {"PSM" , 9, 1, 1195, "R/W", 0, 0, 1ull, 1ull},
- {"DT" , 10, 1, 1195, "RO", 0, 0, 0ull, 0ull},
- {"OCPM" , 11, 1, 1195, "R/W", 1, 1, 0, 0},
- {"NOCP" , 12, 1, 1195, "R/W", 0, 0, 1ull, 1ull},
- {"RESERVED_13_23" , 13, 11, 1195, "RO", 0, 0, 0ull, 0ull},
- {"POTPGT" , 24, 8, 1195, "R/W", 0, 0, 1ull, 1ull},
- {"DR" , 0, 16, 1196, "R/W", 0, 0, 0ull, 0ull},
- {"PPCM" , 16, 16, 1196, "R/W", 0, 1, 0ull, 0},
- {"CCS" , 0, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"PES" , 1, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"PSS" , 2, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"POCI" , 3, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"PRS" , 4, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_5_7" , 5, 3, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"PPS" , 8, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"LSDA" , 9, 1, 1197, "R/W", 1, 1, 0, 0},
- {"RESERVED_10_15" , 10, 6, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"CSC" , 16, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"PESC" , 17, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"PSSC" , 18, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"OCIC" , 19, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"PRSC" , 20, 1, 1197, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_21_31" , 21, 11, 1197, "R/W", 0, 0, 0ull, 0ull},
- {"LPS" , 0, 1, 1198, "R/W", 0, 0, 0ull, 0ull},
- {"OCI" , 1, 1, 1198, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_2_14" , 2, 13, 1198, "RO", 0, 0, 0ull, 0ull},
- {"DRWE" , 15, 1, 1198, "R/W", 0, 1, 0ull, 0},
- {"LPSC" , 16, 1, 1198, "R/W", 0, 1, 0ull, 0},
- {"CCIC" , 17, 1, 1198, "R/W1C", 0, 1, 0ull, 0},
- {"RESERVED_18_30" , 18, 13, 1198, "RO", 0, 0, 0ull, 0ull},
- {"CRWE" , 31, 1, 1198, "WO", 1, 1, 0, 0},
- {"RESERVED_0_30" , 0, 31, 1199, "R/W", 0, 0, 0ull, 0ull},
- {"VLD" , 31, 1, 1199, "R/W", 0, 0, 0ull, 0ull},
- {"ERR_ADDR" , 0, 32, 1200, "RO", 0, 0, 0ull, 0ull},
- {"PPAF_BIS" , 0, 1, 1201, "RO", 0, 0, 0ull, 0ull},
- {"WRBM_BIS" , 1, 1, 1201, "RO", 0, 0, 0ull, 0ull},
- {"ORBM_BIS" , 2, 1, 1201, "RO", 0, 0, 0ull, 0ull},
- {"ERBM_BIS" , 3, 1, 1201, "RO", 0, 0, 0ull, 0ull},
- {"DESC_BIS" , 4, 1, 1201, "RO", 0, 0, 0ull, 0ull},
- {"DATA_BIS" , 5, 1, 1201, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_6_63" , 6, 58, 1201, "RO", 1, 1, 0, 0},
- {"HRST" , 0, 1, 1202, "R/W", 0, 0, 0ull, 1ull},
- {"P_PRST" , 1, 1, 1202, "R/W", 0, 0, 0ull, 1ull},
- {"P_POR" , 2, 1, 1202, "R/W", 0, 0, 1ull, 0ull},
- {"P_COM_ON" , 3, 1, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_4_4" , 4, 1, 1202, "R/W", 0, 1, 0ull, 0},
- {"P_REFCLK_DIV" , 5, 2, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"P_REFCLK_SEL" , 7, 2, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"H_DIV" , 9, 4, 1202, "R/W", 0, 0, 6ull, 6ull},
- {"O_CLKDIV_EN" , 13, 1, 1202, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_EN" , 14, 1, 1202, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_RST" , 15, 1, 1202, "R/W", 0, 0, 0ull, 1ull},
- {"H_CLKDIV_BYP" , 16, 1, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"O_CLKDIV_RST" , 17, 1, 1202, "R/W", 0, 0, 0ull, 1ull},
- {"APP_START_CLK" , 18, 1, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_SUSP_LGCY" , 19, 1, 1202, "R/W", 0, 0, 1ull, 1ull},
- {"OHCI_SM" , 20, 1, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"OHCI_CLKCKTRST" , 21, 1, 1202, "R/W", 0, 0, 1ull, 1ull},
- {"EHCI_SM" , 22, 1, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"START_BIST" , 23, 1, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"CLEAR_BIST" , 24, 1, 1202, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_25_63" , 25, 39, 1202, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1203, "R/W", 0, 1, 0ull, 0},
- {"EHCI_64B_ADDR_EN" , 8, 1, 1203, "R/W", 0, 0, 1ull, 1ull},
- {"INV_REG_A2" , 9, 1, 1203, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1203, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1203, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1203, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1203, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1203, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1203, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1203, "R/W", 0, 0, 0ull, 0ull},
- {"DESC_RBM" , 19, 1, 1203, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_20_63" , 20, 44, 1203, "RAZ", 1, 1, 0, 0},
- {"FLA" , 0, 6, 1204, "R/W", 0, 0, 32ull, 32ull},
- {"RESERVED_6_63" , 6, 58, 1204, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_4" , 0, 5, 1205, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 5, 27, 1205, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1205, "RAZ", 1, 1, 0, 0},
- {"EN" , 0, 1, 1206, "R/W", 0, 0, 0ull, 1ull},
- {"RESERVED_1_63" , 1, 63, 1206, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1207, "R/W", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1207, "R/W", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1207, "R/W", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1207, "R/W", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1207, "R/W", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1207, "R/W", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1207, "R/W", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1207, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1207, "RAZ", 1, 1, 0, 0},
- {"PP_PSH_F" , 0, 1, 1208, "R/W1C", 0, 0, 0ull, 0ull},
- {"ER_PSH_F" , 1, 1, 1208, "R/W1C", 0, 0, 0ull, 0ull},
- {"OR_PSH_F" , 2, 1, 1208, "R/W1C", 0, 0, 0ull, 0ull},
- {"CF_PSH_F" , 3, 1, 1208, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_PSH_F" , 4, 1, 1208, "R/W1C", 0, 0, 0ull, 0ull},
- {"WB_POP_E" , 5, 1, 1208, "R/W1C", 0, 0, 0ull, 0ull},
- {"OC_OVF_E" , 6, 1, 1208, "R/W1C", 0, 0, 0ull, 0ull},
- {"EC_OVF_E" , 7, 1, 1208, "R/W1C", 0, 0, 0ull, 0ull},
- {"RESERVED_8_63" , 8, 56, 1208, "RAZ", 1, 1, 0, 0},
- {"L2C_ADDR_MSB" , 0, 8, 1209, "R/W", 0, 1, 0ull, 0},
- {"RESERVED_8_8" , 8, 1, 1209, "RAZ", 1, 1, 0, 0},
- {"INV_REG_A2" , 9, 1, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DESC_EMOD" , 10, 2, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BUFF_EMOD" , 12, 2, 1209, "R/W", 0, 0, 1ull, 1ull},
- {"L2C_STT" , 14, 1, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_0PAG" , 15, 1, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_BC" , 16, 1, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"L2C_DC" , 17, 1, 1209, "R/W", 0, 0, 1ull, 1ull},
- {"REG_NB" , 18, 1, 1209, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_19_63" , 19, 45, 1209, "RAZ", 1, 1, 0, 0},
- {"RESERVED_0_7" , 0, 8, 1210, "RAZ", 1, 1, 0, 0},
- {"TO_VAL" , 8, 24, 1210, "R/W", 0, 0, 0ull, 0ull},
- {"RESERVED_32_63" , 32, 32, 1210, "RAZ", 1, 1, 0, 0},
- {"WM" , 0, 5, 1211, "R/W", 0, 0, 8ull, 8ull},
- {"RESERVED_5_63" , 5, 59, 1211, "RAZ", 1, 1, 0, 0},
- {"ATE_RESET" , 0, 1, 1212, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_EN" , 1, 1, 1212, "R/W", 0, 0, 0ull, 0ull},
- {"UPHY_BIST" , 2, 1, 1212, "R/W", 0, 0, 0ull, 0ull},
- {"VTEST_EN" , 3, 1, 1212, "R/W", 0, 0, 0ull, 0ull},
- {"SIDDQ" , 4, 1, 1212, "R/W", 0, 0, 0ull, 0ull},
- {"LSBIST" , 5, 1, 1212, "R/W", 0, 0, 0ull, 0ull},
- {"FSBIST" , 6, 1, 1212, "R/W", 0, 0, 0ull, 0ull},
- {"HSBIST" , 7, 1, 1212, "R/W", 0, 0, 0ull, 0ull},
- {"BIST_ERR" , 8, 1, 1212, "RO", 0, 0, 0ull, 0ull},
- {"BIST_DONE" , 9, 1, 1212, "RO", 0, 0, 0ull, 0ull},
- {"RESERVED_10_63" , 10, 54, 1212, "RAZ", 1, 1, 0, 0},
- {"TDATA_IN" , 0, 8, 1213, "R/W", 0, 0, 0ull, 0ull},
- {"TADDR_IN" , 8, 4, 1213, "R/W", 0, 0, 0ull, 0ull},
- {"TDATA_SEL" , 12, 1, 1213, "R/W", 0, 0, 1ull, 0ull},
- {"TCLK" , 13, 1, 1213, "R/W", 0, 0, 0ull, 0ull},
- {"LOOP_EN" , 14, 1, 1213, "R/W", 0, 0, 0ull, 0ull},
- {"COMPDISTUNE" , 15, 3, 1213, "R/W", 0, 0, 4ull, 4ull},
- {"SQRXTUNE" , 18, 3, 1213, "R/W", 0, 0, 4ull, 4ull},
- {"TXFSLSTUNE" , 21, 4, 1213, "R/W", 0, 0, 3ull, 3ull},
- {"TXPREEMPHASISTUNE" , 25, 1, 1213, "R/W", 0, 0, 0ull, 1ull},
- {"TXRISETUNE" , 26, 1, 1213, "R/W", 0, 0, 0ull, 1ull},
- {"TXVREFTUNE" , 27, 4, 1213, "R/W", 0, 0, 5ull, 15ull},
- {"TXHSVXTUNE" , 31, 2, 1213, "R/W", 0, 0, 0ull, 0ull},
- {"PORTRESET" , 33, 1, 1213, "R/W", 0, 0, 0ull, 0ull},
- {"VBUSVLDEXT" , 34, 1, 1213, "R/W", 0, 0, 0ull, 0ull},
- {"DPPULLDOWN" , 35, 1, 1213, "R/W", 0, 0, 1ull, 1ull},
- {"DMPULLDOWN" , 36, 1, 1213, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFEN" , 37, 1, 1213, "R/W", 0, 0, 1ull, 1ull},
- {"TXBISTSTUFFENH" , 38, 1, 1213, "R/W", 0, 0, 1ull, 1ull},
- {"TDATA_OUT" , 39, 4, 1213, "RO", 1, 1, 0, 0},
- {"RESERVED_43_63" , 43, 21, 1213, "RAZ", 1, 1, 0, 0},
- {NULL,0,0,0,0,0,0,0,0}
-};
-
-
-const CVMX_CSR_DB_TYPE *cvmx_csr_db[] = {
- cvmx_csr_db_cn38xxp2,
- cvmx_csr_db_cn31xx,
- cvmx_csr_db_cn30xx,
- cvmx_csr_db_cn38xx,
- cvmx_csr_db_cn58xxp1,
- cvmx_csr_db_cn58xx,
- cvmx_csr_db_cn56xxp1,
- cvmx_csr_db_cn56xx,
- cvmx_csr_db_cn50xx,
- cvmx_csr_db_cn52xxp1,
- cvmx_csr_db_cn52xx,
- cvmx_csr_db_cn61xx,
- cvmx_csr_db_cn63xxp1,
- cvmx_csr_db_cn63xx,
- cvmx_csr_db_cn66xx,
- cvmx_csr_db_cn68xxp1,
- cvmx_csr_db_cn68xx,
- cvmx_csr_db_cnf71xx,
- NULL
-};
-const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_addresses[] = {
- cvmx_csr_db_addresses_cn38xxp2,
- cvmx_csr_db_addresses_cn31xx,
- cvmx_csr_db_addresses_cn30xx,
- cvmx_csr_db_addresses_cn38xx,
- cvmx_csr_db_addresses_cn58xxp1,
- cvmx_csr_db_addresses_cn58xx,
- cvmx_csr_db_addresses_cn56xxp1,
- cvmx_csr_db_addresses_cn56xx,
- cvmx_csr_db_addresses_cn50xx,
- cvmx_csr_db_addresses_cn52xxp1,
- cvmx_csr_db_addresses_cn52xx,
- cvmx_csr_db_addresses_cn61xx,
- cvmx_csr_db_addresses_cn63xxp1,
- cvmx_csr_db_addresses_cn63xx,
- cvmx_csr_db_addresses_cn66xx,
- cvmx_csr_db_addresses_cn68xxp1,
- cvmx_csr_db_addresses_cn68xx,
- cvmx_csr_db_addresses_cnf71xx,
- NULL
-};
-const CVMX_CSR_DB_FIELD_TYPE *cvmx_csr_db_fields[] = {
- cvmx_csr_db_fields_cn38xxp2,
- cvmx_csr_db_fields_cn31xx,
- cvmx_csr_db_fields_cn30xx,
- cvmx_csr_db_fields_cn38xx,
- cvmx_csr_db_fields_cn58xxp1,
- cvmx_csr_db_fields_cn58xx,
- cvmx_csr_db_fields_cn56xxp1,
- cvmx_csr_db_fields_cn56xx,
- cvmx_csr_db_fields_cn50xx,
- cvmx_csr_db_fields_cn52xxp1,
- cvmx_csr_db_fields_cn52xx,
- cvmx_csr_db_fields_cn61xx,
- cvmx_csr_db_fields_cn63xxp1,
- cvmx_csr_db_fields_cn63xx,
- cvmx_csr_db_fields_cn66xx,
- cvmx_csr_db_fields_cn68xxp1,
- cvmx_csr_db_fields_cn68xx,
- cvmx_csr_db_fields_cnf71xx,
- NULL
-};
diff --git a/sys/contrib/octeon-sdk/cvmx-csr-db.h b/sys/contrib/octeon-sdk/cvmx-csr-db.h
deleted file mode 100644
index bc042f3..0000000
--- a/sys/contrib/octeon-sdk/cvmx-csr-db.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-
-
-
-
-#ifndef __CVMX_CSR_DB_H__
-#define __CVMX_CSR_DB_H__
-
-/**
- * @file
- * Interface for the Octeon CSR database.
- *
- *
- * <hr>$Revision: 70030 $<hr>
- *
- */
-#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
-#include "cvmx-platform.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- CVMX_CSR_DB_TYPE_RSL, /**< Octeon internal address, but indirect and slow (not used for addresses) */
- CVMX_CSR_DB_TYPE_NCB, /**< Octeon internal address */
- CVMX_CSR_DB_TYPE_PCI_NCB, /**< Can be accessed through PCI BAR0, also an NCB alias (not used for addresses) */
- CVMX_CSR_DB_TYPE_PCICONFIG, /**< PCI Config, also an NCB alias */
- CVMX_CSR_DB_TYPE_PCI, /**< PCI BAR0 (only) */
- CVMX_CSR_DB_TYPE_PEXP, /**< PCIe BAR 0 address only */
- CVMX_CSR_DB_TYPE_PEXP_NCB, /**< NCB-direct and PCIe BAR0 address */
- CVMX_CSR_DB_TYPE_PCICONFIGEP, /**< PCIe config address (EP mode) + indirect through PESC*_CFG_RD/PESC*_CFG_WR */
- CVMX_CSR_DB_TYPE_PCICONFIGRC, /**< PCICONFIGRC - PCIe config address (RC mode) + indirect through PESC*_CFG_RD/PESC*_CFG_WR */
- CVMX_CSR_DB_TYPE_SRIOMAINT /**< SRIOMAINT - SRIO maintenance registers */
-} CVMX_CSR_DB_TYPE_FIELD;
-
-/**
- * the structure for the cvmx_csr_db_addresses[] array that
- * holds all possible Octeon CSR addresses
- */
-typedef struct {
- char * name; /**< CSR name at the supplied address */
- uint64_t address; /**< Address = octeon internal, PCI BAR0 relative, PCI CONFIG relative */
- CVMX_CSR_DB_TYPE_FIELD type:8; /**< the type */
- uint8_t widthbits; /**< the width of the CSR in bits */
- uint16_t csroff; /**< position of the CSR in cvmx_csr_db[] */
-} __attribute__ ((packed)) CVMX_CSR_DB_ADDRESS_TYPE;
-
-/**
- * the structure for the cvmx_csr_db_fields[] array that
- * holds all possible Octeon CSR fields
- */
-typedef struct {
- char * name; /**< name of the field */
- uint8_t startbit; /**< starting bit position of the field */
- uint8_t sizebits; /**< the size of the field in bits */
- uint16_t csroff; /**< position of the CSR containing the field in cvmx_csr_db[] (get alias from there) */
- char * type; /**< the type of the field R/W, R/W1C, ... */
- uint8_t rst_unp; /**< set if the reset value is unknown */
- uint8_t typ_unp; /**< set if the typical value is unknown */
- uint64_t rst_val; /**< the reset value of the field */
- uint64_t typ_val; /**< the typical value of the field */
-} __attribute__ ((packed)) CVMX_CSR_DB_FIELD_TYPE;
-
-/**
- * the structure for the cvmx_csr_db[] array that holds all
- * possible Octeon CSR forms
- */
-typedef struct {
- char *basename; /**< the base name of the CSR */
- CVMX_CSR_DB_TYPE_FIELD type:8; /**< the type */
- uint8_t widthbits; /**< the width of the CSR in bits */
- uint16_t addoff; /**< the position of the first address in cvmx_csr_db_csr_addresses[] (numblocks*indexnum is #) */
- uint8_t numfields; /**< the number of fields in the CSR (and in cvmx_csr_db_csr_fields[]) */
- uint16_t fieldoff; /**< the position of the first field in cvmx_csr_db_csr_fields[] */
-} __attribute__ ((packed)) CVMX_CSR_DB_TYPE;
-
-
-/**
- * This NULL terminated array contains the CVMX_CSR_DB_TYPE
- * arrays for each chip. Each array entry is another NULL
- * terminated array of CSRs.
- */
-extern const CVMX_CSR_DB_TYPE *cvmx_csr_db[];
-
-/**
- * This NULL terminated array contains the CVMX_CSR_DB_ADDRESS_TYPE
- * arrays for each chip. Each array entry is another NULL
- * terminated array of CSR addresses.
- */
-extern const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_addresses[];
-
-/**
- * This NULL terminated array contains the CVMX_CSR_DB_FIELD_TYPE
- * arrays for each chip. Each array entry is another NULL
- * terminated array of CSR fields.
- */
-extern const CVMX_CSR_DB_FIELD_TYPE *cvmx_csr_db_fields[];
-
-/**
- * Figure out which database to use for this chip. The passed
- * identifier can be a processor ID or a PCI ID.
- *
- * @param identifier processor ID or a PCI ID
- *
- * @return index into the csr db
- */
-extern int cvmx_db_get_chipindex(int identifier);
-
-/**
- * Get the CSR DB entry for the passed Octeon model and CSR name. The
- * model can either be specified as a processor id or PCI id.
- *
- * @param identifier Identifer to choose the CSR DB with
- * @param name CSR name to lookup
- *
- * @return CSR DB entry or NULL on failure
- */
-extern const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_get(int identifier, const char *name);
-
-/**
- * Decode a CSR value into named bitfields. The model can either
- * be specified as a processor id or PCI id.
- *
- * @param identifier Identifer to choose the CSR DB with
- * @param address CSR address being decoded
- * @param value Value to decode
- */
-extern void cvmx_csr_db_decode(int identifier, uint64_t address, uint64_t value);
-
-/**
- * Decode a CSR value into named bitfields. The model can either
- * be specified as a processor id or PCI id.
- *
- * @param identifier Identifer to choose the CSR DB with
- * @param name CSR name to decode
- * @param value Value to decode
- */
-extern void cvmx_csr_db_decode_by_name(int identifier, const char *name, uint64_t value);
-
-/**
- * Print a list of csrs begimning with a prefix. The
- * model can either be specified as a processor id or PCI id.
- *
- * @param identifier Identifer to choose the CSR DB with
- * @param prefix Beginning prefix to look for
- */
-extern void cvmx_csr_db_display_list(int identifier, const char *prefix);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-error-custom.c b/sys/contrib/octeon-sdk/cvmx-error-custom.c
deleted file mode 100644
index 64768a6..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-custom.c
+++ /dev/null
@@ -1,889 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Prototypes for custom error handler function not handled by the default
- * message display error function.
- *
- * <hr>$Revision: 44252 $<hr>
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-helper.h>
-#include <asm/octeon/cvmx-l2c.h>
-#include <asm/octeon/cvmx-pcie.h>
-#include <asm/octeon/cvmx-pexp-defs.h>
-#include <asm/octeon/cvmx-dfa-defs.h>
-#include <asm/octeon/cvmx-gmxx-defs.h>
-#include <asm/octeon/cvmx-lmcx-defs.h>
-#include <asm/octeon/cvmx-pemx-defs.h>
-#include <asm/octeon/cvmx-sriox-defs.h>
-#define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__)
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#include "cvmx-helper.h"
-#include "cvmx-l2c.h"
-#include "cvmx-pcie.h"
-#include "cvmx-interrupt.h"
-#endif
-
-/**
- * @INTERNAL
- * XAUI interfaces need to be reset whenever a local or remote fault
- * is detected. Calling autoconf takes the link through a reset.
- *
- * @param info
- *
- * @return
- */
-static int __cvmx_error_handle_gmxx_rxx_int_reg(const struct cvmx_error_info *info)
-{
-#ifdef CVMX_ENABLE_PKO_FUNCTIONS
- int ipd_port = info->group_index;
- switch(ipd_port)
- {
- case 0x800:
- ipd_port = 0x840;
- break;
- case 0xa00:
- ipd_port = 0xa40;
- break;
- case 0xb00:
- ipd_port = 0xb40;
- break;
- case 0xc00:
- ipd_port = 0xc40;
- break;
- }
- cvmx_helper_link_autoconf(ipd_port);
-#endif
- cvmx_write_csr(info->status_addr, info->status_mask);
- return 1;
-}
-
-/**
- * @INTERNAL
- * When NPEI_INT_SUM[C0_LDWN] is set, the PCIe block requires a shutdown and
- * initialization to bring the link back up. This handler does this for port 0.
- * Note that config space is not enumerated again, so the devices will still be
- * unusable.
- *
- * @param info
- *
- * @return
- */
-static int __cvmx_error_handle_npei_int_sum_c0_ldwn(const struct cvmx_error_info *info)
-{
- cvmx_ciu_soft_prst_t ciu_soft_prst;
- PRINT_ERROR("NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n");
- ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
- if (!ciu_soft_prst.s.soft_prst)
- {
- /* Attempt to automatically bring the link back up */
- cvmx_pcie_rc_shutdown(0);
- cvmx_pcie_rc_initialize(0);
- }
- cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
- return 1;
-}
-
-/**
- * @INTERNAL
- * When NPEI_INT_SUM[C1_LDWN] is set, the PCIe block requires a shutdown and
- * initialization to bring the link back up. This handler does this for port 1.
- * Note that config space is not enumerated again, so the devices will still be
- * unusable.
- *
- * @param info
- *
- * @return
- */
-static int __cvmx_error_handle_npei_int_sum_c1_ldwn(const struct cvmx_error_info *info)
-{
- cvmx_ciu_soft_prst_t ciu_soft_prst;
- PRINT_ERROR("NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n");
- ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
- if (!ciu_soft_prst.s.soft_prst)
- {
- /* Attempt to automatically bring the link back up */
- cvmx_pcie_rc_shutdown(1);
- cvmx_pcie_rc_initialize(1);
- }
- cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
- return 1;
-}
-
-#define DECODE_FAILING_ADDRESS
-//#define DECODE_FAILING_BIT
-
-#ifdef DECODE_FAILING_BIT
-#define _Db(x) (x) /* Data Bit */
-#define _Ec(x) (0x100+x) /* ECC Bit */
-#define _Ad(x) (0x200+x) /* Address Bit */
-#define _Bu(x) (0x400+x) /* Burst */
-#define _Un() (-1) /* Unused */
-/* Use ECC Code as index to lookup corrected bit */
-const static short lmc_syndrome_bits[256] = {
- /* __ 0 __ __ 1 __ __ 2 __ __ 3 __ __ 4 __ __ 5 __ __ 6 __ __ 7 __ __ 8 __ __ 9 __ __ A __ __ B __ __ C __ __ D __ __ E __ __ F __ */
- /* 00: */ _Un( ), _Ec( 0), _Ec( 1), _Un( ), _Ec( 2), _Un( ), _Un( ), _Un( ), _Ec( 3), _Un( ), _Un( ), _Db(17), _Un( ), _Un( ), _Db(16), _Un( ),
- /* 10: */ _Ec( 4), _Un( ), _Un( ), _Db(18), _Un( ), _Db(19), _Db(20), _Un( ), _Un( ), _Db(21), _Db(22), _Un( ), _Db(23), _Un( ), _Un( ), _Un( ),
- /* 20: */ _Ec( 5), _Un( ), _Un( ), _Db( 8), _Un( ), _Db( 9), _Db(10), _Un( ), _Un( ), _Db(11), _Db(12), _Un( ), _Db(13), _Un( ), _Un( ), _Un( ),
- /* 30: */ _Un( ), _Db(14), _Un( ), _Un( ), _Db(15), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Ad(34), _Un( ),
- /* 40: */ _Ec( 6), _Un( ), _Un( ), _Un( ), _Un( ), _Ad( 7), _Ad( 8), _Un( ), _Un( ), _Ad( 9), _Db(33), _Un( ), _Ad(10), _Un( ), _Un( ), _Db(32),
- /* 50: */ _Un( ), _Ad(11), _Db(34), _Un( ), _Db(35), _Un( ), _Un( ), _Db(36), _Db(37), _Un( ), _Un( ), _Db(38), _Un( ), _Db(39), _Ad(12), _Un( ),
- /* 60: */ _Un( ), _Ad(13), _Db(56), _Un( ), _Db(57), _Un( ), _Un( ), _Db(58), _Db(59), _Un( ), _Un( ), _Db(60), _Un( ), _Db(61), _Ad(14), _Un( ),
- /* 70: */ _Db(62), _Un( ), _Un( ), _Ad(15), _Un( ), _Db(63), _Ad(16), _Un( ), _Un( ), _Ad(17), _Ad(18), _Un( ), _Ad(19), _Un( ), _Ad(20), _Un( ),
- /* 80: */ _Ec( 7), _Un( ), _Un( ), _Ad(21), _Un( ), _Ad(22), _Ad(23), _Un( ), _Un( ), _Ad(24), _Db(49), _Un( ), _Ad(25), _Un( ), _Un( ), _Db(48),
- /* 90: */ _Un( ), _Ad(26), _Db(50), _Un( ), _Db(51), _Un( ), _Un( ), _Db(52), _Db(53), _Un( ), _Un( ), _Db(54), _Un( ), _Db(55), _Ad(27), _Un( ),
- /* A0: */ _Un( ), _Ad(28), _Db(40), _Un( ), _Db(41), _Un( ), _Un( ), _Db(42), _Db(43), _Un( ), _Un( ), _Db(44), _Un( ), _Db(45), _Ad(29), _Un( ),
- /* B0: */ _Db(46), _Un( ), _Un( ), _Ad(30), _Un( ), _Db(47), _Ad(31), _Un( ), _Un( ), _Ad(32), _Ad(33), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ),
- /* C0: */ _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Db( 1), _Un( ), _Un( ), _Db( 0), _Un( ),
- /* D0: */ _Un( ), _Un( ), _Un( ), _Db( 2), _Un( ), _Db( 3), _Db( 4), _Un( ), _Un( ), _Db( 5), _Db( 6), _Un( ), _Db( 7), _Un( ), _Un( ), _Un( ),
- /* E0: */ _Un( ), _Un( ), _Un( ), _Db(24), _Un( ), _Db(25), _Db(26), _Un( ), _Un( ), _Db(27), _Db(28), _Un( ), _Db(29), _Un( ), _Un( ), _Un( ),
- /* F0: */ _Un( ), _Db(30), _Un( ), _Un( ), _Db(31), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( ), _Un( )
-};
-#endif
-
-/**
- * @INTERNAL
- * This error bit handler clears the status and prints failure infomation.
- *
- * @param info Error register to check
- *
- * @return
- */
-static int __cvmx_cn6xxx_lmc_ecc_error_display(const cvmx_error_info_t *info)
-{
-#ifdef DECODE_FAILING_ADDRESS
- cvmx_lmcx_config_t lmc_config;
- uint64_t fadr_physical, fadr_data;
-#endif
-
- int ddr_controller = info->group_index;
- cvmx_lmcx_int_t lmc_int;
- cvmx_lmcx_fadr_t fadr;
- cvmx_lmcx_ecc_synd_t ecc_synd;
- int sec_err;
- int ded_err;
- int syndrome = -1;
- int phase;
-
- lmc_int.u64 = cvmx_read_csr(CVMX_LMCX_INT(ddr_controller));
- fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(ddr_controller));
- ecc_synd.u64 = cvmx_read_csr(CVMX_LMCX_ECC_SYND(ddr_controller));
- /* This assumes that all bits in the status register are RO or R/W1C */
- cvmx_write_csr(info->status_addr, info->status_mask);
-
-#ifdef DECODE_FAILING_ADDRESS
- lmc_config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(ddr_controller));
-#endif
-
- sec_err = lmc_int.s.sec_err;
- ded_err = lmc_int.s.ded_err;
-
- phase = ded_err ? ded_err : sec_err; /* Double bit errors take precedence. */
-
- switch (phase) {
- case 1:
- syndrome = ecc_synd.cn63xx.mrdsyn0;
- break;
- case 2:
- syndrome = ecc_synd.cn63xx.mrdsyn1;
- break;
- case 4:
- syndrome = ecc_synd.cn63xx.mrdsyn2;
- break;
- case 8:
- syndrome = ecc_synd.cn63xx.mrdsyn3;
- break;
- }
-
-#ifdef DECODE_FAILING_ADDRESS
- fadr_physical = (uint64_t)fadr.cn63xx.fdimm << (lmc_config.s.pbank_lsb + 28);
- fadr_physical |= (uint64_t)fadr.cn63xx.frow << (lmc_config.s.row_lsb + 14);
- fadr_physical |= (uint64_t)fadr.cn63xx.fbank << 7;
- fadr_physical |= (uint64_t)(fadr.cn63xx.fcol&0xf) << 3;
- fadr_physical |= (uint64_t)(fadr.cn63xx.fcol>>4) << 10;
-
- fadr_data = *(uint64_t*)cvmx_phys_to_ptr(fadr_physical);
-#endif
-
- PRINT_ERROR("LMC%d ECC: sec_err:%d ded_err:%d\n"
- "LMC%d ECC:\tFailing dimm: %u\n"
- "LMC%d ECC:\tFailing rank: %u\n"
- "LMC%d ECC:\tFailing bank: %u\n"
- "LMC%d ECC:\tFailing row: 0x%x\n"
- "LMC%d ECC:\tFailing column: 0x%x\n"
- "LMC%d ECC:\tsyndrome: 0x%x"
-#ifdef DECODE_FAILING_BIT
- ", bit: %d"
-#endif
- "\n"
-#ifdef DECODE_FAILING_ADDRESS
- "Failing Address: 0x%016llx, Data: 0x%016llx\n"
-#endif
- , /* Comma */
- ddr_controller, sec_err, ded_err,
- ddr_controller, fadr.cn63xx.fdimm,
- ddr_controller, fadr.cn63xx.fbunk,
- ddr_controller, fadr.cn63xx.fbank,
- ddr_controller, fadr.cn63xx.frow,
- ddr_controller, fadr.cn63xx.fcol,
- ddr_controller, syndrome
-#ifdef DECODE_FAILING_BIT
- , /* Comma */
- lmc_syndrome_bits[syndrome]
-#endif
-#ifdef DECODE_FAILING_ADDRESS
- , /* Comma */
- (unsigned long long) fadr_physical, (unsigned long long) fadr_data
-#endif
- );
-
- return 1;
-}
-
-/**
- * @INTERNAL
- * Some errors require more complicated error handing functions than the
- * automatically generated functions in cvmx-error-init-*.c. This function
- * replaces these handers with hand coded functions for these special cases.
- *
- * @return Zero on success, negative on failure.
- */
-int __cvmx_error_custom_initialize(void)
-{
- if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
- {
- int lmc;
- for (lmc = 0; lmc < CVMX_L2C_TADS; lmc++)
- {
- if (OCTEON_IS_MODEL(OCTEON_CN68XX))
- {
- cvmx_lmcx_dll_ctl2_t ctl;
- ctl.u64 = cvmx_read_csr(CVMX_LMCX_DLL_CTL2(lmc));
- if (ctl.s.intf_en == 0)
- continue;
- }
- cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
- CVMX_LMCX_INT(lmc), 0xfull<<1 /* sec_err */,
- __cvmx_cn6xxx_lmc_ecc_error_display, 0, NULL, NULL);
- cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
- CVMX_LMCX_INT(lmc), 0xfull<<5 /* ded_err */,
- __cvmx_cn6xxx_lmc_ecc_error_display, 0, NULL, NULL);
- if (!OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
- {
- int i;
-
- for (i = 0; i < 6; i++)
- cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
- CVMX_L2C_TADX_INT(lmc), (1ull << i),
- __cvmx_error_handle_63XX_l2_ecc, 0, NULL, NULL);
- }
- }
- }
- if (OCTEON_IS_MODEL(OCTEON_CN52XX)
- || OCTEON_IS_MODEL(OCTEON_CN56XX)
- || OCTEON_IS_MODEL(OCTEON_CN6XXX)
- || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
- {
- int i;
-
- /* Install special handler for all the interfaces, these are
- specific to XAUI interface */
- for (i = 0; i < CVMX_HELPER_MAX_GMX; i++)
- {
- if ((OCTEON_IS_MODEL(OCTEON_CN63XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX)
- || OCTEON_IS_MODEL(OCTEON_CNF71XX))
- && i == 1)
- continue;
- cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
- CVMX_GMXX_RXX_INT_REG(0,i), 1ull<<21 /* rem_fault */,
- __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
- cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
- CVMX_GMXX_RXX_INT_REG(0,i), 1ull<<20 /* loc_fault */,
- __cvmx_error_handle_gmxx_rxx_int_reg, 0, NULL, NULL);
- }
- }
- if (OCTEON_IS_MODEL(OCTEON_CN56XX))
- {
- cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
- CVMX_PEXP_NPEI_INT_SUM, 1ull<<59 /* c0_ldwn */,
- __cvmx_error_handle_npei_int_sum_c0_ldwn, 0, NULL, NULL);
- cvmx_error_change_handler(CVMX_ERROR_REGISTER_IO64,
- CVMX_PEXP_NPEI_INT_SUM, 1ull<<60 /* c1_ldwn */,
- __cvmx_error_handle_npei_int_sum_c1_ldwn, 0, NULL, NULL);
- }
-
- /* CN63XX pass 1.x has a bug where the PCIe config CRS counter does not
- stop. Disable reporting errors from CRS */
- if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
- {
- cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_PEMX_INT_SUM(0),
- 1ull<<12);
- cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_PEMX_INT_SUM(0),
- 1ull<<13);
- cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_PEMX_INT_SUM(1),
- 1ull<<12);
- cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_PEMX_INT_SUM(1),
- 1ull<<13);
- }
- /* According to the workaround for errata SRIO-15282, clearing
- SRIOx_INT_ENABLE[MAC_BUF]. */
- if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) && OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1))
- {
- cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_SRIOX_INT_ENABLE(0), 1ull<<22);
- cvmx_error_disable(CVMX_ERROR_REGISTER_IO64, CVMX_SRIOX_INT_ENABLE(1), 1ull<<22);
- }
-
- return 0;
-}
-
-/**
- * @INTERNAL
- * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_dfa_err_cp2dbe(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
- PRINT_ERROR("DFA_ERR[CP2DBE]: DFA PP-CP2 Double Bit Error Detected\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_dfa_err_cp2perr(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
- PRINT_ERROR("DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_dfa_err_cp2sbe(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
- PRINT_ERROR("DFA_ERR[CP2SBE]: DFA PP-CP2 Single Bit Error Corrected\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_dfa_err_dblovf(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
- PRINT_ERROR("DFA_ERR[DBLOVF]: Doorbell Overflow detected\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_dfa_err_dtedbe(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
- PRINT_ERROR("DFA_ERR[DTEDBE]: DFA DTE 29b Double Bit Error Detected\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_dfa_err_dteperr(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
- PRINT_ERROR("DFA_ERR[DTEPERR]: DTE Parity Error Detected\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * DFA_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_dfa_err_dtesbe(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_DFA_ERR, cvmx_read_csr(CVMX_DFA_ERR));
- PRINT_ERROR("DFA_ERR[DTESBE]: DFA DTE 29b Single Bit Error Corrected\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * L2D_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_l2d_err_ded_err(const struct cvmx_error_info *info)
-{
- cvmx_l2d_err_t derr;
- cvmx_l2d_fadr_t fadr;
- uint64_t syn0 = cvmx_read_csr(CVMX_L2D_FSYN0);
- uint64_t syn1 = cvmx_read_csr(CVMX_L2D_FSYN1);
- derr.u64 = cvmx_read_csr(CVMX_L2D_ERR);
- fadr.u64 = cvmx_read_csr(CVMX_L2D_FADR);
-
- PRINT_ERROR("L2D_ERR[DED_ERR] ECC double: fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx\n",
- (unsigned long long)fadr.u64, (unsigned long long)syn0, (unsigned long long)syn1);
- /* Flush the line that had the error */
- cvmx_l2c_flush_line(fadr.s.fset, fadr.s.fadr >> 1);
- cvmx_write_csr(CVMX_L2D_ERR, derr.u64);
- return 1;
-}
-
-/**
- * @INTERNAL
- * L2D_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_l2d_err_sec_err(const struct cvmx_error_info *info)
-{
- cvmx_l2d_err_t derr;
- cvmx_l2d_fadr_t fadr;
- uint64_t syn0 = cvmx_read_csr(CVMX_L2D_FSYN0);
- uint64_t syn1 = cvmx_read_csr(CVMX_L2D_FSYN1);
- derr.u64 = cvmx_read_csr(CVMX_L2D_ERR);
- fadr.u64 = cvmx_read_csr(CVMX_L2D_FADR);
-
- PRINT_ERROR("L2D_ERR[SEC_ERR] ECC single: fadr: 0x%llx, syn0:0x%llx, syn1: 0x%llx\n",
- (unsigned long long)fadr.u64, (unsigned long long)syn0, (unsigned long long)syn1);
- /* Flush the line that had the error */
- cvmx_l2c_flush_line(fadr.s.fset, fadr.s.fadr >> 1);
- cvmx_write_csr(CVMX_L2D_ERR, derr.u64);
- return 1;
-}
-
-/**
- * @INTERNAL
- * L2T_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_l2t_err_ded_err(const struct cvmx_error_info *info)
-{
- cvmx_l2t_err_t terr;
- terr.u64 = cvmx_read_csr(CVMX_L2T_ERR);
- cvmx_write_csr(CVMX_L2T_ERR, terr.u64);
- PRINT_ERROR("L2T_ERR[DED_ERR]: double bit:\tfadr: 0x%x, fset: 0x%x, fsyn: 0x%x\n",
- terr.s.fadr, terr.s.fset, terr.s.fsyn);
- if (!terr.s.fsyn)
- {
- /* Syndrome is zero, which means error was in non-hit line,
- so flush all associations */
- int i;
- int l2_assoc = cvmx_l2c_get_num_assoc();
-
- for (i = 0; i < l2_assoc; i++)
- cvmx_l2c_flush_line(i, terr.s.fadr);
- }
- else
- cvmx_l2c_flush_line(terr.s.fset, terr.s.fadr);
- return 1;
-}
-
-/**
- * @INTERNAL
- * L2T_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_l2t_err_lckerr2(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_L2T_ERR, cvmx_read_csr(CVMX_L2T_ERR));
- PRINT_ERROR("L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n could not find an available/unlocked set (for replacement).\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * L2T_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_l2t_err_lckerr(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_L2T_ERR, cvmx_read_csr(CVMX_L2T_ERR));
- PRINT_ERROR("L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of the INDEX (which is ignored by HW - but reported to SW).\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * L2T_ERR contains R/W1C bits along with R/W bits. This means that it requires
- * special handling instead of the normal __cvmx_error_display() function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_l2t_err_sec_err(const struct cvmx_error_info *info)
-{
- cvmx_l2t_err_t terr;
- terr.u64 = cvmx_read_csr(CVMX_L2T_ERR);
- cvmx_write_csr(CVMX_L2T_ERR, terr.u64);
- PRINT_ERROR("L2T_ERR[SEC_ERR]: single bit:\tfadr: 0x%x, fset: 0x%x, fsyn: 0x%x\n",
- terr.s.fadr, terr.s.fset, terr.s.fsyn);
- if (!terr.s.fsyn)
- {
- /* Syndrome is zero, which means error was in non-hit line,
- so flush all associations */
- int i;
- int l2_assoc = cvmx_l2c_get_num_assoc();
-
- for (i = 0; i < l2_assoc; i++)
- cvmx_l2c_flush_line(i, terr.s.fadr);
- }
- else
- cvmx_l2c_flush_line(terr.s.fset, terr.s.fadr);
- return 1;
-}
-
-
-/**
- * @INTERNAL
- * LMCX_MEM_CFG0 contains R/W1C bits along with R/W bits. This means that it
- * requires special handling instead of the normal __cvmx_error_display()
- * function.
- *
- * @param info
- *
- * @return
- */
-static int __cvmx_error_handle_lmcx_mem_cfg0(const struct cvmx_error_info *info)
-{
- int ddr_controller = info->group_index;
- cvmx_lmcx_mem_cfg0_t mem_cfg0;
- cvmx_lmcx_fadr_t fadr;
- int sec_err;
- int ded_err;
-
- mem_cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(ddr_controller));
- fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(ddr_controller));
- cvmx_write_csr(CVMX_LMCX_MEM_CFG0(ddr_controller),mem_cfg0.u64);
-
- sec_err = cvmx_dpop(mem_cfg0.s.sec_err);
- ded_err = cvmx_dpop(mem_cfg0.s.ded_err);
-
- if (ded_err || sec_err)
- {
- PRINT_ERROR("DDR%d ECC: %d Single bit corrections, %d Double bit errors\n"
- "DDR%d ECC:\tFailing dimm: %u\n"
- "DDR%d ECC:\tFailing rank: %u\n"
- "DDR%d ECC:\tFailing bank: %u\n"
- "DDR%d ECC:\tFailing row: 0x%x\n"
- "DDR%d ECC:\tFailing column: 0x%x\n",
- ddr_controller, sec_err, ded_err,
- ddr_controller, fadr.cn38xx.fdimm,
- ddr_controller, fadr.cn38xx.fbunk,
- ddr_controller, fadr.cn38xx.fbank,
- ddr_controller, fadr.cn38xx.frow,
- ddr_controller, fadr.cn38xx.fcol);
- }
- return 1;
-}
-
-/**
- * @INTERNAL
- * LMCX_MEM_CFG0 contains R/W1C bits along with R/W bits. This means that it
- * requires special handling instead of the normal __cvmx_error_display()
- * function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_lmcx_mem_cfg0_ded_err(const struct cvmx_error_info *info)
-{
- return __cvmx_error_handle_lmcx_mem_cfg0(info);
-}
-
-/**
- * @INTERNAL
- * LMCX_MEM_CFG0 contains R/W1C bits along with R/W bits. This means that it
- * requires special handling instead of the normal __cvmx_error_display()
- * function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_lmcx_mem_cfg0_sec_err(const struct cvmx_error_info *info)
-{
- return __cvmx_error_handle_lmcx_mem_cfg0(info);
-}
-
-/**
- * @INTERNAL
- * POW_ECC_ERR contains R/W1C bits along with R/W bits. This means that it
- * requires special handling instead of the normal __cvmx_error_display()
- * function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_pow_ecc_err_dbe(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_POW_ECC_ERR, cvmx_read_csr(CVMX_POW_ECC_ERR));
- PRINT_ERROR("POW_ECC_ERR[DBE]: POW double bit error\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * POW_ECC_ERR contains R/W1C bits along with R/W bits. This means that it
- * requires special handling instead of the normal __cvmx_error_display()
- * function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_pow_ecc_err_iop(const struct cvmx_error_info *info)
-{
- cvmx_pow_ecc_err_t err;
- err.u64 = cvmx_read_csr(CVMX_POW_ECC_ERR);
- cvmx_write_csr(CVMX_POW_ECC_ERR, err.u64);
- if (err.s.iop & (1 << 0))
- PRINT_ERROR("POW_ECC_ERR[IOP0]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state\n");
- if (err.s.iop & (1 << 1))
- PRINT_ERROR("POW_ECC_ERR[IOP1]: Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state\n");
- if (err.s.iop & (1 << 2))
- PRINT_ERROR("POW_ECC_ERR[IOP2]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC\n");
- if (err.s.iop & (1 << 3))
- PRINT_ERROR("POW_ECC_ERR[IOP3]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL\n");
- if (err.s.iop & (1 << 4))
- PRINT_ERROR("POW_ECC_ERR[IOP4]: Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL\n");
- if (err.s.iop & (1 << 5))
- PRINT_ERROR("POW_ECC_ERR[IOP5]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending\n");
- if (err.s.iop & (1 << 6))
- PRINT_ERROR("POW_ECC_ERR[IOP6]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending\n");
- if (err.s.iop & (1 << 7))
- PRINT_ERROR("POW_ECC_ERR[IOP7]: Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending\n");
- if (err.s.iop & (1 << 8))
- PRINT_ERROR("POW_ECC_ERR[IOP8]: Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending\n");
- if (err.s.iop & (1 << 9))
- PRINT_ERROR("POW_ECC_ERR[IOP9]: Received illegal opcode\n");
- if (err.s.iop & (1 << 10))
- PRINT_ERROR("POW_ECC_ERR[IOP10]: Received ADD_WORK with tag specified as NULL_NULL\n");
- if (err.s.iop & (1 << 11))
- PRINT_ERROR("POW_ECC_ERR[IOP11]: Received DBG load from PP with DBG load pending\n");
- if (err.s.iop & (1 << 12))
- PRINT_ERROR("POW_ECC_ERR[IOP12]: Received CSR load from PP with CSR load pending\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * POW_ECC_ERR contains R/W1C bits along with R/W bits. This means that it
- * requires special handling instead of the normal __cvmx_error_display()
- * function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_pow_ecc_err_rpe(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_POW_ECC_ERR, cvmx_read_csr(CVMX_POW_ECC_ERR));
- PRINT_ERROR("POW_ECC_ERR[RPE]: Remote pointer error\n");
- return 1;
-}
-
-/**
- * @INTERNAL
- * POW_ECC_ERR contains R/W1C bits along with R/W bits. This means that it
- * requires special handling instead of the normal __cvmx_error_display()
- * function.
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_pow_ecc_err_sbe(const struct cvmx_error_info *info)
-{
- cvmx_write_csr(CVMX_POW_ECC_ERR, cvmx_read_csr(CVMX_POW_ECC_ERR));
- PRINT_ERROR("POW_ECC_ERR[SBE]: POW single bit error\n");
- return 1;
-}
-
-
-/**
- * @INTERNAL
- *
- * @param info
- *
- * @return
- */
-int __cvmx_error_handle_63XX_l2_ecc(const struct cvmx_error_info *info)
-{
- cvmx_l2c_err_tdtx_t l2c_err_tdt;
- cvmx_l2c_err_ttgx_t l2c_err_ttg;
- cvmx_l2c_err_vbfx_t l2c_err_vbf;
- cvmx_l2c_tadx_int_t tadx_int;
- tadx_int.u64 = cvmx_read_csr(CVMX_L2C_TADX_INT(0));
- l2c_err_tdt.u64 = cvmx_read_csr(CVMX_L2C_ERR_TDTX(0));
- l2c_err_ttg.u64 = cvmx_read_csr(CVMX_L2C_ERR_TTGX(0));
- l2c_err_vbf.u64 = cvmx_read_csr(CVMX_L2C_ERR_VBFX(0));
- cvmx_write_csr(CVMX_L2C_TADX_INT(0), tadx_int.u64);
-
- if (tadx_int.cn63xx.l2ddbe || tadx_int.cn63xx.l2dsbe)
- {
- /* L2 Data error */
-
-
- if (tadx_int.cn63xx.l2dsbe)
- {
- /* l2c_err_tdt.cn63xx.wayidx formated same as CACHE instruction arg */
- CVMX_CACHE_WBIL2I((l2c_err_tdt.u64 & 0x1fff80) | (1ULL << 63), 0);
- CVMX_SYNC;
- PRINT_ERROR("L2C_TADX_INT(0)[L2DSBE]: Data Single-Bit Error\n");
- }
- if (tadx_int.cn63xx.l2ddbe)
- {
- /* TODO - fatal error, for now, flush so error cleared..... */
- CVMX_CACHE_WBIL2I((l2c_err_tdt.u64 & 0x1fff80) | (1ULL << 63), 0);
- CVMX_SYNC;
- PRINT_ERROR("L2C_TADX_INT(0)[L2DDBE]: Data Double-Bit Error\n");
- }
- PRINT_ERROR("CVMX_L2C_ERR_TDT: 0x%llx\n", (unsigned long long)l2c_err_tdt.u64);
- }
- if (tadx_int.cn63xx.tagdbe || tadx_int.cn63xx.tagsbe)
- {
- /* L2 Tag error */
- if (tadx_int.cn63xx.tagsbe)
- {
- CVMX_CACHE_WBIL2I((l2c_err_ttg.u64 & 0x1fff80) | (1ULL << 63), 0);
- CVMX_SYNC;
- PRINT_ERROR("L2C_TADX_INT(0)[TAGSBE]: Tag Single-Bit Error\n");
- }
- if (tadx_int.cn63xx.tagdbe)
- {
- /* TODO - fatal error, for now, flush so error cleared..... */
- CVMX_CACHE_WBIL2I((l2c_err_ttg.u64 & 0x1fff80) | (1ULL << 63), 0);
- CVMX_SYNC;
- PRINT_ERROR("L2C_TADX_INT(0)[TAGDBE]: Tag Double-Bit Error\n");
- }
- PRINT_ERROR("CVMX_L2C_ERR_TTG: 0x%llx\n", (unsigned long long)l2c_err_ttg.u64);
- }
- if (tadx_int.cn63xx.vbfdbe || tadx_int.cn63xx.vbfsbe)
- {
- /* L2 Victim buffer error */
- if (tadx_int.cn63xx.vbfsbe)
- {
- /* No action here, hardware fixed up on write to DRAM */
- PRINT_ERROR("L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n");
- }
- if (tadx_int.cn63xx.vbfdbe)
- {
- /* TODO - fatal error. Bad data written to DRAM. */
- PRINT_ERROR("L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n");
- }
- PRINT_ERROR("CVMX_L2C_ERR_VBF: 0x%llx\n", (unsigned long long)l2c_err_vbf.u64);
- }
-
- return 1;
-}
diff --git a/sys/contrib/octeon-sdk/cvmx-error-custom.h b/sys/contrib/octeon-sdk/cvmx-error-custom.h
deleted file mode 100644
index 019835e..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-custom.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Prototypes for custom error handler function not handled by the default
- * message display error function.
- *
- * <hr>$Revision: 44252 $<hr>
- */
-#ifndef __CVMX_ERROR_CUSTOM_H__
-#define __CVMX_ERROR_CUSTOM_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @INTERNAL
- * Some errors require more complicated error handing functions
- * than the automatically generated functions in cvmx-error-init-*.c.
- * This function replaces these handers with hand coded functions
- * for these special cases.
- *
- * @return Zero on success, negative on failure.
- */
-int __cvmx_error_custom_initialize(void);
-
-int __cvmx_error_handle_dfa_err_cp2dbe(const struct cvmx_error_info *info);
-int __cvmx_error_handle_dfa_err_cp2perr(const struct cvmx_error_info *info);
-int __cvmx_error_handle_dfa_err_cp2sbe(const struct cvmx_error_info *info);
-int __cvmx_error_handle_dfa_err_dblovf(const struct cvmx_error_info *info);
-int __cvmx_error_handle_dfa_err_dtedbe(const struct cvmx_error_info *info);
-int __cvmx_error_handle_dfa_err_dteperr(const struct cvmx_error_info *info);
-int __cvmx_error_handle_dfa_err_dtesbe(const struct cvmx_error_info *info);
-int __cvmx_error_handle_l2d_err_ded_err(const struct cvmx_error_info *info);
-int __cvmx_error_handle_l2d_err_sec_err(const struct cvmx_error_info *info);
-int __cvmx_error_handle_l2t_err_ded_err(const struct cvmx_error_info *info);
-int __cvmx_error_handle_l2t_err_lckerr2(const struct cvmx_error_info *info);
-int __cvmx_error_handle_l2t_err_lckerr(const struct cvmx_error_info *info);
-int __cvmx_error_handle_l2t_err_sec_err(const struct cvmx_error_info *info);
-int __cvmx_error_handle_lmcx_mem_cfg0_ded_err(const struct cvmx_error_info *info);
-int __cvmx_error_handle_lmcx_mem_cfg0_sec_err(const struct cvmx_error_info *info);
-int __cvmx_error_handle_pow_ecc_err_dbe(const struct cvmx_error_info *info);
-int __cvmx_error_handle_pow_ecc_err_iop(const struct cvmx_error_info *info);
-int __cvmx_error_handle_pow_ecc_err_rpe(const struct cvmx_error_info *info);
-int __cvmx_error_handle_pow_ecc_err_sbe(const struct cvmx_error_info *info);
-int __cvmx_error_handle_63XX_l2_ecc(const struct cvmx_error_info *info);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c
deleted file mode 100644
index 6e266740..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn30xx.c
+++ /dev/null
@@ -1,3504 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn30xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN30XX</h2>
- * @dot
- * digraph cn30xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"];
- * cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
- * cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
- * cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
- * cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<fpa>fpa|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<pip>pip|<gmx0>gmx0|<lmc>lmc|<iob>iob|<usb>usb"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<i0_rtout>i0_rtout|<i0_overf>i0_overf|<p0_rtout>p0_rtout|<p0_perr>p0_perr|<g0_rtout>g0_rtout|<p0_pperr>p0_pperr|<p0_ptout>p0_ptout|<i0_pperr>i0_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
- * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
- * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
- * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub"];
- * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"];
- * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
- * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
- * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<n2u_pf>n2u_pf|<n2u_pe>n2u_pe|<u2n_d_pe>u2n_d_pe|<u2n_d_pf>u2n_d_pf|<u2n_c_pf>u2n_c_pf|<u2n_c_pe>u2n_c_pe|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
- * cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn30xx(void);
-
-int cvmx_error_initialize_cn30xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_NPI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is\n"
- " completed successfully, however the address is NOT\n"
- " locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
- " back from a RSL after sending a read command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
- " back from a RSL after sending a write command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<3 /* po0_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<3 /* po0_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<7 /* i0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<7 /* i0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<11 /* i0_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<11 /* i0_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<15 /* p0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<15 /* p0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<19 /* p0_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<19 /* p0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<23 /* g0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<23 /* g0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<27 /* p0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<27 /* p0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<31 /* p0_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<31 /* p0_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<35 /* i0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<35 /* i0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<39 /* win_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<39 /* win_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<40 /* p_dperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<40 /* p_dperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
- " from the PCI this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<41 /* iobdma */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<41 /* iobdma */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<42 /* fcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<42 /* fcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<43 /* fcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<43 /* fcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<44 /* pcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<44 /* pcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<45 /* pcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<45 /* pcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<46 /* q2_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<46 /* q2_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<47 /* q2_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<47 /* q2_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<48 /* q3_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<48 /* q3_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<49 /* q3_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<49 /* q3_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<50 /* com_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<50 /* com_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<51 /* com_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<51 /* com_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<52 /* pnc_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<52 /* pnc_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<53 /* pnc_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<53 /* pnc_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<54 /* rwx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<54 /* rwx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<55 /* rdx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<55 /* rdx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<56 /* pcf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<56 /* pcf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<57 /* pcf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<57 /* pcf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<58 /* pdf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<58 /* pdf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<59 /* pdf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<59 /* pdf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<60 /* q1_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<60 /* q1_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<61 /* q1_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<61 /* q1_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_PCI_INT_SUM2 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<0 /* tr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rtr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<1 /* mr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rmr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<2 /* mr_wtto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* rmr_wtto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<3 /* tr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* rtr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<4 /* mr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* rmr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<5 /* mr_tto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* rmr_tto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<6 /* msi_per */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* rmsi_per */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<7 /* msi_tabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* rmsi_tabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<8 /* msi_mabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<8 /* rmsi_mabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<9 /* msc_msg */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<9 /* rmsc_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<10 /* tsr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<10 /* rtsr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<11 /* serr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<11 /* rserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<12 /* aperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<12 /* raperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<13 /* dperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<13 /* rdperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<14 /* ill_rwr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<14 /* ill_rwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<15 /* ill_rrd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<15 /* ill_rrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<31 /* win_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<31 /* win_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
- " Read-Address Register took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<32 /* ill_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<32 /* ill_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<33 /* ill_rd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* ill_rd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0x7ull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0x7ull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0x7ull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0x7ull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0x7ull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0x7ull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n"
- " (not used in O2P)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0x7ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0x7ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0x7ull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0x7ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " In 16b mode, ecc is calculated on 8 cycle worth of data\n"
- " [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
- " DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
- " [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
- " DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
- " [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
- " DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
- " [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
- " DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " In 16b mode, ecc is calculated on 8 cycle worth of data\n"
- " [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
- " DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
- " [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
- " DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
- " [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
- " DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
- " [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
- " DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_USBNX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* pr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<0 /* pr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* pr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* pr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<2 /* nr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<2 /* nr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<3 /* nr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<3 /* nr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* lr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* lr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* lr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* lr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* pt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* pt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* pt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* pt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* nt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* nt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* nt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* nt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<10 /* lt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<10 /* lt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* lt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* lt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* dcred_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* dcred_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* dcred_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* dcred_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<14 /* l2c_s_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<14 /* l2c_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<15 /* l2c_a_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<15 /* l2c_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<16 /* lt_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<16 /* l2_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<17 /* lt_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<17 /* l2_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<18 /* rg_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<18 /* rg_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<19 /* rg_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<19 /* rg_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<20 /* rq_q2_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<20 /* rq_q2_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<21 /* rq_q2_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<21 /* rq_q2_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<22 /* rq_q3_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<22 /* rq_q3_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<23 /* rq_q3_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<23 /* rq_q3_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<24 /* uod_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<24 /* uod_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<25 /* uod_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<25 /* uod_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<26 /* n2u_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<26 /* n2u_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[N2U_PF]: N2U Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<27 /* n2u_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<27 /* n2u_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[N2U_PE]: N2U Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<28 /* u2n_d_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<28 /* u2n_d_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[U2N_D_PE]: U2N Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<29 /* u2n_d_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<29 /* u2n_d_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[U2N_D_PF]: U2N Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<30 /* u2n_c_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<30 /* u2n_c_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[U2N_C_PF]: U2N Control Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<31 /* u2n_c_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<31 /* u2n_c_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[U2N_C_PE]: U2N Control Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<32 /* ltl_f_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<32 /* ltl_f_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<33 /* ltl_f_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<33 /* ltl_f_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<34 /* nd4o_rpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<34 /* nd4o_rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<35 /* nd4o_rpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<35 /* nd4o_rpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<36 /* nd4o_dpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<36 /* nd4o_dpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<37 /* nd4o_dpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<37 /* nd4o_dpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c
deleted file mode 100644
index 14592f2..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn31xx.c
+++ /dev/null
@@ -1,3835 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn31xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN31XX</h2>
- * @dot
- * digraph cn31xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"];
- * cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
- * cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
- * cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
- * cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<zip>zip|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<usb>usb"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
- * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
- * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
- * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub"];
- * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe"];
- * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"];
- * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
- * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
- * cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
- * cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
- * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<n2u_pf>n2u_pf|<n2u_pe>n2u_pe|<u2n_d_pe>u2n_d_pe|<u2n_d_pf>u2n_d_pf|<u2n_c_pf>u2n_c_pf|<u2n_c_pe>u2n_c_pe|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
- * cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn31xx(void);
-
-int cvmx_error_initialize_cn31xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_NPI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
- " back from a RSL after sending a read command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
- " back from a RSL after sending a write command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<3 /* po0_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<3 /* po0_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<4 /* po1_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<4 /* po1_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<7 /* i0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<7 /* i0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<8 /* i1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<8 /* i1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<11 /* i0_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<11 /* i0_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<12 /* i1_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<12 /* i1_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<15 /* p0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<15 /* p0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<16 /* p1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<16 /* p1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<19 /* p0_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<19 /* p0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<20 /* p1_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<20 /* p1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<23 /* g0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<23 /* g0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<24 /* g1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<24 /* g1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<27 /* p0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<27 /* p0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<28 /* p1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<28 /* p1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<31 /* p0_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<31 /* p0_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<32 /* p1_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<32 /* p1_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<35 /* i0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<35 /* i0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<36 /* i1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<36 /* i1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<39 /* win_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<39 /* win_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<40 /* p_dperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<40 /* p_dperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
- " from the PCI this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<41 /* iobdma */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<41 /* iobdma */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<42 /* fcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<42 /* fcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<43 /* fcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<43 /* fcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<44 /* pcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<44 /* pcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<45 /* pcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<45 /* pcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<46 /* q2_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<46 /* q2_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<47 /* q2_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<47 /* q2_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<48 /* q3_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<48 /* q3_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<49 /* q3_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<49 /* q3_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<50 /* com_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<50 /* com_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<51 /* com_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<51 /* com_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<52 /* pnc_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<52 /* pnc_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<53 /* pnc_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<53 /* pnc_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<54 /* rwx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<54 /* rwx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<55 /* rdx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<55 /* rdx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<56 /* pcf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<56 /* pcf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<57 /* pcf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<57 /* pcf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<58 /* pdf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<58 /* pdf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<59 /* pdf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<59 /* pdf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<60 /* q1_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<60 /* q1_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<61 /* q1_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<61 /* q1_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_PCI_INT_SUM2 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<0 /* tr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rtr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<1 /* mr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rmr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<2 /* mr_wtto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* rmr_wtto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<3 /* tr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* rtr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<4 /* mr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* rmr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<5 /* mr_tto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* rmr_tto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<6 /* msi_per */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* rmsi_per */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<7 /* msi_tabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* rmsi_tabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<8 /* msi_mabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<8 /* rmsi_mabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<9 /* msc_msg */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<9 /* rmsc_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<10 /* tsr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<10 /* rtsr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<11 /* serr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<11 /* rserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<12 /* aperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<12 /* raperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<13 /* dperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<13 /* rdperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<14 /* ill_rwr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<14 /* ill_rwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<15 /* ill_rrd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<15 /* ill_rrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<31 /* win_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<31 /* win_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
- " Read-Address Register took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<32 /* ill_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<32 /* ill_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<33 /* ill_rd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* ill_rd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0x7ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0x7ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0x7ull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0x7ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0x7ull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0x7ull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0x7ull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0x7ull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0x7ull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0x7ull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n"
- " (not used in O2P)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<1 /* cp2sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2sbe;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
- " When set, a single bit error had been detected and\n"
- " corrected for a PP-generated QW Mode read\n"
- " transaction.\n"
- " If the CP2DBE=0, then the CP2SYN contains the\n"
- " failing syndrome (used during correction).\n"
- " Refer to CP2ECCENA.\n"
- " If the CP2SBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n"
- " NOTE: PP-generated LW Mode Read transactions\n"
- " do not participate in ECC check/correct).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<2 /* cp2dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2dbe;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
- " When set, a double bit error had been detected\n"
- " for a PP-generated QW Mode read transaction.\n"
- " The CP2SYN contains the failing syndrome.\n"
- " NOTE: PP-generated LW Mode Read transactions\n"
- " do not participate in ECC check/correct).\n"
- " Refer to CP2ECCENA.\n"
- " If the CP2DBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<14 /* dtesbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dtesbe;
- info.user_info = (long)
- "ERROR DFA_ERR[DTESBE]: DTE 25b Single Bit Error Corrected - Status bit\n"
- " When set, a single bit error had been detected and\n"
- " corrected for a DTE-generated 32b SIMPLE Mode read\n"
- " transaction.\n"
- " If the DTEDBE=0, then the DTESYN contains the\n"
- " failing syndrome (used during correction).\n"
- " NOTE: DTE-generated 16b SIMPLE Mode Read\n"
- " transactions do not participate in ECC check/correct).\n"
- " If the DTESBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<15 /* dtedbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dtedbe;
- info.user_info = (long)
- "ERROR DFA_ERR[DTEDBE]: DTE 25b Double Bit Error Detected - Status bit\n"
- " When set, a double bit error had been detected\n"
- " for a DTE-generated 32b SIMPLE Mode read transaction.\n"
- " The DTESYN contains the failing syndrome.\n"
- " If the DTEDBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n"
- " NOTE: DTE-generated 16b SIMPLE Mode Read transactions\n"
- " do not participate in ECC check/correct).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<26 /* dteperr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dteperr;
- info.user_info = (long)
- "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 16b SIMPLE mode ONLY)\n"
- " When set, all DTE-generated 16b SIMPLE Mode read\n"
- " transactions which encounter a parity error (across\n"
- " the 17b of data) are reported.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<29 /* cp2perr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2perr;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
- " When set, a parity error had been detected for a\n"
- " PP-generated LW Mode read transaction.\n"
- " If the CP2PINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<31 /* dblovf */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dblovf;
- info.user_info = (long)
- "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_USBNX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* pr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<0 /* pr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* pr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* pr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<2 /* nr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<2 /* nr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<3 /* nr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<3 /* nr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* lr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* lr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* lr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* lr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* pt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* pt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* pt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* pt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* nt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* nt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* nt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* nt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<10 /* lt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<10 /* lt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* lt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* lt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* dcred_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* dcred_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* dcred_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* dcred_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<14 /* l2c_s_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<14 /* l2c_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<15 /* l2c_a_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<15 /* l2c_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<16 /* lt_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<16 /* l2_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<17 /* lt_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<17 /* l2_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<18 /* rg_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<18 /* rg_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<19 /* rg_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<19 /* rg_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<20 /* rq_q2_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<20 /* rq_q2_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<21 /* rq_q2_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<21 /* rq_q2_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<22 /* rq_q3_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<22 /* rq_q3_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<23 /* rq_q3_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<23 /* rq_q3_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<24 /* uod_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<24 /* uod_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<25 /* uod_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<25 /* uod_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<26 /* n2u_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<26 /* n2u_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[N2U_PF]: N2U Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<27 /* n2u_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<27 /* n2u_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[N2U_PE]: N2U Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<28 /* u2n_d_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<28 /* u2n_d_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[U2N_D_PE]: U2N Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<29 /* u2n_d_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<29 /* u2n_d_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[U2N_D_PF]: U2N Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<30 /* u2n_c_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<30 /* u2n_c_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[U2N_C_PF]: U2N Control Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<31 /* u2n_c_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<31 /* u2n_c_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[U2N_C_PE]: U2N Control Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<32 /* ltl_f_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<32 /* ltl_f_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<33 /* ltl_f_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<33 /* ltl_f_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<34 /* nd4o_rpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<34 /* nd4o_rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<35 /* nd4o_rpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<35 /* nd4o_rpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<36 /* nd4o_dpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<36 /* nd4o_dpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<37 /* nd4o_dpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<37 /* nd4o_dpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c
deleted file mode 100644
index dd89451..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c
+++ /dev/null
@@ -1,4866 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn38xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN38XX</h2>
- * @dot
- * digraph cn38xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
- * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
- * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
- * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
- * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
- * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
- * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
- * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
- * cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
- * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
- * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
- * cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
- * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
- * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
- * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
- * cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
- * cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
- * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
- * cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
- * cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
- * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
- * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
- * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
- * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
- * cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn38xx(void);
-
-int cvmx_error_initialize_cn38xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_NPI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
- " back from a RSL after sending a read command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
- " back from a RSL after sending a write command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<3 /* po0_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<3 /* po0_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<4 /* po1_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<4 /* po1_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<5 /* po2_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<5 /* po2_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<6 /* po3_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<6 /* po3_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<7 /* i0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<7 /* i0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<8 /* i1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<8 /* i1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<9 /* i2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<9 /* i2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<10 /* i3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<10 /* i3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<11 /* i0_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<11 /* i0_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<12 /* i1_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<12 /* i1_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<13 /* i2_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<13 /* i2_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<14 /* i3_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<14 /* i3_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<15 /* p0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<15 /* p0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<16 /* p1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<16 /* p1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<17 /* p2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<17 /* p2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<18 /* p3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<18 /* p3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<19 /* p0_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<19 /* p0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<20 /* p1_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<20 /* p1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<21 /* p2_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<21 /* p2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<22 /* p3_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<22 /* p3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<23 /* g0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<23 /* g0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<24 /* g1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<24 /* g1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<25 /* g2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<25 /* g2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<26 /* g3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<26 /* g3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<27 /* p0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<27 /* p0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<28 /* p1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<28 /* p1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<29 /* p2_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<29 /* p2_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<30 /* p3_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<30 /* p3_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<31 /* p0_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<31 /* p0_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<32 /* p1_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<32 /* p1_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<33 /* p2_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<33 /* p2_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<34 /* p3_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<34 /* p3_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<35 /* i0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<35 /* i0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<36 /* i1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<36 /* i1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<37 /* i2_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<37 /* i2_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<38 /* i3_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<38 /* i3_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<39 /* win_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<39 /* win_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<40 /* p_dperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<40 /* p_dperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
- " from the PCI this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<41 /* iobdma */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<41 /* iobdma */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<42 /* fcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<42 /* fcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<43 /* fcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<43 /* fcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<44 /* pcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<44 /* pcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<45 /* pcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<45 /* pcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<46 /* q2_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<46 /* q2_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<47 /* q2_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<47 /* q2_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<48 /* q3_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<48 /* q3_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<49 /* q3_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<49 /* q3_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<50 /* com_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<50 /* com_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<51 /* com_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<51 /* com_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<52 /* pnc_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<52 /* pnc_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<53 /* pnc_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<53 /* pnc_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<54 /* rwx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<54 /* rwx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<55 /* rdx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<55 /* rdx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<56 /* pcf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<56 /* pcf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<57 /* pcf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<57 /* pcf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<58 /* pdf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<58 /* pdf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<59 /* pdf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<59 /* pdf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<60 /* q1_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<60 /* q1_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<61 /* q1_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<61 /* q1_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_PCI_INT_SUM2 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<0 /* tr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rtr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<1 /* mr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rmr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<2 /* mr_wtto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* rmr_wtto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<3 /* tr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* rtr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<4 /* mr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* rmr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<5 /* mr_tto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* rmr_tto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<6 /* msi_per */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* rmsi_per */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<7 /* msi_tabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* rmsi_tabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<8 /* msi_mabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<8 /* rmsi_mabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<9 /* msc_msg */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<9 /* rmsc_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<10 /* tsr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<10 /* rtsr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<11 /* serr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<11 /* rserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<12 /* aperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<12 /* raperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<13 /* dperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<13 /* rdperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<14 /* ill_rwr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<14 /* ill_rwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<15 /* ill_rrd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<15 /* ill_rrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<31 /* win_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<31 /* win_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
- " Read-Address Register took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<32 /* ill_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<32 /* ill_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<33 /* ill_rd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* ill_rd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<0 /* out_col */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<1 /* ncb_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xffffull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<1 /* ncb_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* ncb_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<0 /* out_col */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<1 /* ncb_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xffffull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<1 /* ncb_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* ncb_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SPXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* prtnxa */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<0 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* abnorm */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<1 /* abnorm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* spiovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<4 /* spiovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* clserr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<5 /* clserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* drwnng */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<6 /* drwnng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<7 /* rsverr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<7 /* rsverr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* tpaovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<8 /* tpaovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<9 /* diperr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<9 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* syncerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<10 /* syncerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
- " SPX_ERR_CTL[ERRCNT]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<11 /* calerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<11 /* calerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_STXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* calpar0 */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<0 /* calpar0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* calpar1 */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<1 /* calpar1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* ovrbst */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<2 /* ovrbst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* datovr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<3 /* datovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* diperr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<4 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* nosync */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<5 /* nosync */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* unxfrm */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<6 /* unxfrm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<7 /* frmerr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<7 /* frmerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SPXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* prtnxa */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<0 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* abnorm */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<1 /* abnorm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* spiovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<4 /* spiovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* clserr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<5 /* clserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* drwnng */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<6 /* drwnng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<7 /* rsverr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<7 /* rsverr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<8 /* tpaovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<8 /* tpaovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<9 /* diperr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<9 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<10 /* syncerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<10 /* syncerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
- " SPX_ERR_CTL[ERRCNT]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<11 /* calerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<11 /* calerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_STXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* calpar0 */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<0 /* calpar0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* calpar1 */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<1 /* calpar1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<2 /* ovrbst */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<2 /* ovrbst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<3 /* datovr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<3 /* datovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* diperr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<4 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* nosync */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<5 /* nosync */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* unxfrm */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<6 /* unxfrm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<7 /* frmerr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<7 /* frmerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 128b mode, ecc is calulated on 1 cycle worth of data\n"
- " [21] corresponds to DQ[63:0], Phase0\n"
- " [22] corresponds to DQ[127:64], Phase0\n"
- " [23] corresponds to DQ[63:0], Phase1\n"
- " [24] corresponds to DQ[127:64], Phase1\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [21] corresponds to DQ[63:0], Phase0, cycle0\n"
- " [22] corresponds to DQ[63:0], Phase0, cycle1\n"
- " [23] corresponds to DQ[63:0], Phase1, cycle0\n"
- " [24] corresponds to DQ[63:0], Phase1, cycle1\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 128b mode, ecc is calulated on 1 cycle worth of data\n"
- " [25] corresponds to DQ[63:0], Phase0\n"
- " [26] corresponds to DQ[127:64], Phase0\n"
- " [27] corresponds to DQ[63:0], Phase1\n"
- " [28] corresponds to DQ[127:64], Phase1\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [25] corresponds to DQ[63:0], Phase0, cycle0\n"
- " [26] corresponds to DQ[63:0], Phase0, cycle1\n"
- " [27] corresponds to DQ[63:0], Phase1, cycle0\n"
- " [28] corresponds to DQ[63:0], Phase1, cycle1\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<1 /* cp2sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2sbe;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
- " When set, a single bit error had been detected and\n"
- " corrected for a PP-generated QW Mode read\n"
- " transaction.\n"
- " If the CP2DBE=0, then the CP2SYN contains the\n"
- " failing syndrome (used during correction).\n"
- " Refer to CP2ECCENA.\n"
- " If the CP2SBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n"
- " NOTE: PP-generated LW Mode Read transactions\n"
- " do not participate in ECC check/correct).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<2 /* cp2dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2dbe;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
- " When set, a double bit error had been detected\n"
- " for a PP-generated QW Mode read transaction.\n"
- " The CP2SYN contains the failing syndrome.\n"
- " NOTE: PP-generated LW Mode Read transactions\n"
- " do not participate in ECC check/correct).\n"
- " Refer to CP2ECCENA.\n"
- " If the CP2DBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<14 /* dtesbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dtesbe;
- info.user_info = (long)
- "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n"
- " When set, a single bit error had been detected and\n"
- " corrected for a DTE-generated 36b SIMPLE Mode read\n"
- " transaction.\n"
- " If the DTEDBE=0, then the DTESYN contains the\n"
- " failing syndrome (used during correction).\n"
- " NOTE: DTE-generated 18b SIMPLE Mode Read\n"
- " transactions do not participate in ECC check/correct).\n"
- " If the DTESBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<15 /* dtedbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dtedbe;
- info.user_info = (long)
- "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n"
- " When set, a double bit error had been detected\n"
- " for a DTE-generated 36b SIMPLE Mode read transaction.\n"
- " The DTESYN contains the failing syndrome.\n"
- " If the DTEDBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n"
- " NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n"
- " do not participate in ECC check/correct).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<26 /* dteperr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dteperr;
- info.user_info = (long)
- "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n"
- " When set, all DTE-generated 18b SIMPLE Mode read\n"
- " transactions which encounter a parity error (across\n"
- " the 17b of data) are reported.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<29 /* cp2perr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2perr;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
- " When set, a parity error had been detected for a\n"
- " PP-generated LW Mode read transaction.\n"
- " If the CP2PINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<31 /* dblovf */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dblovf;
- info.user_info = (long)
- "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c
deleted file mode 100644
index d4d7244..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn38xxp2.c
+++ /dev/null
@@ -1,4423 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn38xxp2.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN38XXP2</h2>
- * @dot
- * digraph cn38xxp2
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<pci_rsl>pci_rsl"];
- * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
- * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
- * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
- * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
- * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
- * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub"];
- * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
- * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
- * cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
- * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe"];
- * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
- * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
- * cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
- * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
- * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
- * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
- * cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
- * cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
- * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
- * cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
- * cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
- * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
- * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
- * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
- * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
- * cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn38xxp2(void);
-
-int cvmx_error_initialize_cn38xxp2(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_NPI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
- " back from a RSL after sending a read command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
- " back from a RSL after sending a write command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<3 /* po0_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<3 /* po0_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<4 /* po1_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<4 /* po1_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<5 /* po2_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<5 /* po2_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<6 /* po3_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<6 /* po3_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<7 /* i0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<7 /* i0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<8 /* i1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<8 /* i1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<9 /* i2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<9 /* i2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<10 /* i3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<10 /* i3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<11 /* i0_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<11 /* i0_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<12 /* i1_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<12 /* i1_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<13 /* i2_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<13 /* i2_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<14 /* i3_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<14 /* i3_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<15 /* p0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<15 /* p0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<16 /* p1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<16 /* p1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<17 /* p2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<17 /* p2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<18 /* p3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<18 /* p3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<19 /* p0_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<19 /* p0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<20 /* p1_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<20 /* p1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<21 /* p2_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<21 /* p2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<22 /* p3_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<22 /* p3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<23 /* g0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<23 /* g0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<24 /* g1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<24 /* g1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<25 /* g2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<25 /* g2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<26 /* g3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<26 /* g3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<27 /* p0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<27 /* p0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<28 /* p1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<28 /* p1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<29 /* p2_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<29 /* p2_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<30 /* p3_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<30 /* p3_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<31 /* p0_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<31 /* p0_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<32 /* p1_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<32 /* p1_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<33 /* p2_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<33 /* p2_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<34 /* p3_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<34 /* p3_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<35 /* i0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<35 /* i0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<36 /* i1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<36 /* i1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<37 /* i2_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<37 /* i2_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<38 /* i3_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<38 /* i3_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<39 /* win_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<39 /* win_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<40 /* p_dperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<40 /* p_dperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
- " from the PCI this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<41 /* iobdma */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<41 /* iobdma */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_PCI_INT_SUM2 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<0 /* tr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rtr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<1 /* mr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rmr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<2 /* mr_wtto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* rmr_wtto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<3 /* tr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* rtr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<4 /* mr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* rmr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<5 /* mr_tto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* rmr_tto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<6 /* msi_per */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* rmsi_per */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<7 /* msi_tabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* rmsi_tabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<8 /* msi_mabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<8 /* rmsi_mabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<9 /* msc_msg */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<9 /* rmsc_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<10 /* tsr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<10 /* rtsr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<11 /* serr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<11 /* rserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<12 /* aperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<12 /* raperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<13 /* dperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<13 /* rdperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<14 /* ill_rwr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<14 /* ill_rwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<15 /* ill_rrd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<15 /* ill_rrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<31 /* win_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<31 /* win_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
- " Read-Address Register took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<32 /* ill_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<32 /* ill_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<33 /* ill_rd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* ill_rd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<0 /* out_col */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<1 /* ncb_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xffffull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<1 /* ncb_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* ncb_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<0 /* out_col */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<1 /* ncb_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xffffull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<1 /* ncb_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* ncb_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SPXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* prtnxa */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<0 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* abnorm */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<1 /* abnorm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* spiovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<4 /* spiovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* clserr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<5 /* clserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* drwnng */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<6 /* drwnng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<7 /* rsverr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<7 /* rsverr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* tpaovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<8 /* tpaovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<9 /* diperr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<9 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* syncerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<10 /* syncerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
- " SPX_ERR_CTL[ERRCNT]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<11 /* calerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<11 /* calerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_STXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* calpar0 */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<0 /* calpar0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* calpar1 */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<1 /* calpar1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* ovrbst */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<2 /* ovrbst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* datovr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<3 /* datovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* diperr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<4 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* nosync */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<5 /* nosync */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* unxfrm */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<6 /* unxfrm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<7 /* frmerr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<7 /* frmerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SPXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* prtnxa */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<0 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* abnorm */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<1 /* abnorm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* spiovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<4 /* spiovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* clserr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<5 /* clserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* drwnng */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<6 /* drwnng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<7 /* rsverr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<7 /* rsverr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<8 /* tpaovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<8 /* tpaovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<9 /* diperr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<9 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<10 /* syncerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<10 /* syncerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
- " SPX_ERR_CTL[ERRCNT]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<11 /* calerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<11 /* calerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_STXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* calpar0 */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<0 /* calpar0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* calpar1 */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<1 /* calpar1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<2 /* ovrbst */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<2 /* ovrbst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<3 /* datovr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<3 /* datovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* diperr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<4 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* nosync */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<5 /* nosync */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* unxfrm */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<6 /* unxfrm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<7 /* frmerr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<7 /* frmerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 128b mode, ecc is calulated on 1 cycle worth of data\n"
- " [21] corresponds to DQ[63:0], Phase0\n"
- " [22] corresponds to DQ[127:64], Phase0\n"
- " [23] corresponds to DQ[63:0], Phase1\n"
- " [24] corresponds to DQ[127:64], Phase1\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [21] corresponds to DQ[63:0], Phase0, cycle0\n"
- " [22] corresponds to DQ[63:0], Phase0, cycle1\n"
- " [23] corresponds to DQ[63:0], Phase1, cycle0\n"
- " [24] corresponds to DQ[63:0], Phase1, cycle1\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 128b mode, ecc is calulated on 1 cycle worth of data\n"
- " [25] corresponds to DQ[63:0], Phase0\n"
- " [26] corresponds to DQ[127:64], Phase0\n"
- " [27] corresponds to DQ[63:0], Phase1\n"
- " [28] corresponds to DQ[127:64], Phase1\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [25] corresponds to DQ[63:0], Phase0, cycle0\n"
- " [26] corresponds to DQ[63:0], Phase0, cycle1\n"
- " [27] corresponds to DQ[63:0], Phase1, cycle0\n"
- " [28] corresponds to DQ[63:0], Phase1, cycle1\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<1 /* cp2sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2sbe;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
- " When set, a single bit error had been detected and\n"
- " corrected for a PP-generated QW Mode read\n"
- " transaction.\n"
- " If the CP2DBE=0, then the CP2SYN contains the\n"
- " failing syndrome (used during correction).\n"
- " Refer to CP2ECCENA.\n"
- " If the CP2SBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n"
- " NOTE: PP-generated LW Mode Read transactions\n"
- " do not participate in ECC check/correct).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<2 /* cp2dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2dbe;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
- " When set, a double bit error had been detected\n"
- " for a PP-generated QW Mode read transaction.\n"
- " The CP2SYN contains the failing syndrome.\n"
- " NOTE: PP-generated LW Mode Read transactions\n"
- " do not participate in ECC check/correct).\n"
- " Refer to CP2ECCENA.\n"
- " If the CP2DBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<14 /* dtesbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dtesbe;
- info.user_info = (long)
- "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n"
- " When set, a single bit error had been detected and\n"
- " corrected for a DTE-generated 36b SIMPLE Mode read\n"
- " transaction.\n"
- " If the DTEDBE=0, then the DTESYN contains the\n"
- " failing syndrome (used during correction).\n"
- " NOTE: DTE-generated 18b SIMPLE Mode Read\n"
- " transactions do not participate in ECC check/correct).\n"
- " If the DTESBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<15 /* dtedbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dtedbe;
- info.user_info = (long)
- "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n"
- " When set, a double bit error had been detected\n"
- " for a DTE-generated 36b SIMPLE Mode read transaction.\n"
- " The DTESYN contains the failing syndrome.\n"
- " If the DTEDBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n"
- " NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n"
- " do not participate in ECC check/correct).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<26 /* dteperr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dteperr;
- info.user_info = (long)
- "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n"
- " When set, all DTE-generated 18b SIMPLE Mode read\n"
- " transactions which encounter a parity error (across\n"
- " the 17b of data) are reported.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<29 /* cp2perr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2perr;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
- " When set, a parity error had been detected for a\n"
- " PP-generated LW Mode read transaction.\n"
- " If the CP2PINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<31 /* dblovf */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dblovf;
- info.user_info = (long)
- "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c
deleted file mode 100644
index f25fe7b..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn50xx.c
+++ /dev/null
@@ -1,3606 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn50xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN50XX</h2>
- * @dot
- * digraph cn50xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<pcm>pcm"];
- * cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
- * cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
- * cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
- * cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<fpa>fpa|<mio>mio|<ipd>ipd|<pow>pow|<asx0>asx0|<pko>pko|<tim>tim|<pip>pip|<gmx0>gmx0|<lmc>lmc|<iob>iob|<usb>usb"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
- * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
- * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
- * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh"];
- * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
- * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<alnerr>alnerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
- * cvmx_npi_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn50xx(void);
-
-int cvmx_error_initialize_cn50xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_NPI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
- " back from a RSL after sending a read command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
- " back from a RSL after sending a write command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<3 /* po0_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<3 /* po0_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<4 /* po1_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<4 /* po1_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<7 /* i0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<7 /* i0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<8 /* i1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<8 /* i1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<11 /* i0_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<11 /* i0_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<12 /* i1_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<12 /* i1_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<15 /* p0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<15 /* p0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<16 /* p1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<16 /* p1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<19 /* p0_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<19 /* p0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<20 /* p1_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<20 /* p1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<23 /* g0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<23 /* g0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<24 /* g1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<24 /* g1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<27 /* p0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<27 /* p0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<28 /* p1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<28 /* p1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<31 /* p0_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<31 /* p0_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<32 /* p1_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<32 /* p1_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<35 /* i0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<35 /* i0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<36 /* i1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<36 /* i1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<39 /* win_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<39 /* win_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<40 /* p_dperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<40 /* p_dperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
- " from the PCI this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<41 /* iobdma */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<41 /* iobdma */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<42 /* fcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<42 /* fcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<43 /* fcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<43 /* fcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<44 /* pcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<44 /* pcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<45 /* pcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<45 /* pcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<46 /* q2_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<46 /* q2_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<47 /* q2_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<47 /* q2_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<48 /* q3_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<48 /* q3_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<49 /* q3_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<49 /* q3_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<50 /* com_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<50 /* com_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<51 /* com_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<51 /* com_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<52 /* pnc_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<52 /* pnc_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<53 /* pnc_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<53 /* pnc_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<54 /* rwx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<54 /* rwx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<55 /* rdx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<55 /* rdx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<56 /* pcf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<56 /* pcf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<57 /* pcf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<57 /* pcf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<58 /* pdf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<58 /* pdf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<59 /* pdf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<59 /* pdf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<60 /* q1_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<60 /* q1_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<61 /* q1_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<61 /* q1_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_PCI_INT_SUM2 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<0 /* tr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rtr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<1 /* mr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rmr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<2 /* mr_wtto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* rmr_wtto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<3 /* tr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* rtr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<4 /* mr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* rmr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<5 /* mr_tto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* rmr_tto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<6 /* msi_per */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* rmsi_per */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<7 /* msi_tabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* rmsi_tabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<8 /* msi_mabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<8 /* rmsi_mabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<9 /* msc_msg */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<9 /* rmsc_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<10 /* tsr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<10 /* rtsr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<11 /* serr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<11 /* rserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<12 /* aperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<12 /* raperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<13 /* dperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<13 /* rdperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<14 /* ill_rwr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<14 /* ill_rwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<15 /* ill_rrd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<15 /* ill_rrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<31 /* win_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<31 /* win_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
- " Read-Address Register took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<32 /* ill_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<32 /* ill_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<33 /* ill_rd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* ill_rd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0x7ull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0x7ull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0x7ull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0x7ull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0x7ull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0x7ull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0x7ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0x7ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0x7ull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0x7ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " In 16b mode, ecc is calculated on 8 cycle worth of data\n"
- " [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
- " DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
- " [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
- " DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
- " [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
- " DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
- " [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
- " DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " In 16b mode, ecc is calculated on 8 cycle worth of data\n"
- " [0] corresponds to [DQ[15:0]_c1_p1, DQ[15:0]_c1_p0,\n"
- " DQ[15:0]_c0_p1, DQ[15:0]_c0_p0]\n"
- " [1] corresponds to [DQ[15:0]_c3_p1, DQ[15:0]_c3_p0,\n"
- " DQ[15:0]_c2_p1, DQ[15:0]_c2_p0]\n"
- " [2] corresponds to [DQ[15:0]_c5_p1, DQ[15:0]_c5_p0,\n"
- " DQ[15:0]_c4_p1, DQ[15:0]_c4_p0]\n"
- " [3] corresponds to [DQ[15:0]_c7_p1, DQ[15:0]_c7_p0,\n"
- " DQ[15:0]_c6_p1, DQ[15:0]_c6_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [3:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_USBNX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* pr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<0 /* pr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* pr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* pr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<2 /* nr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<2 /* nr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<3 /* nr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<3 /* nr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* lr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* lr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* lr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* lr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* pt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* pt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* pt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* pt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* nt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* nt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* nt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* nt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<10 /* lt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<10 /* lt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* lt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* lt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* dcred_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* dcred_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* dcred_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* dcred_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<14 /* l2c_s_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<14 /* l2c_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<15 /* l2c_a_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<15 /* l2c_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<16 /* lt_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<16 /* l2_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<17 /* lt_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<17 /* l2_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<18 /* rg_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<18 /* rg_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<19 /* rg_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<19 /* rg_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<20 /* rq_q2_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<20 /* rq_q2_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<21 /* rq_q2_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<21 /* rq_q2_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<22 /* rq_q3_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<22 /* rq_q3_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<23 /* rq_q3_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<23 /* rq_q3_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<24 /* uod_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<24 /* uod_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<25 /* uod_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<25 /* uod_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<32 /* ltl_f_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<32 /* ltl_f_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<33 /* ltl_f_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<33 /* ltl_f_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<34 /* nd4o_rpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<34 /* nd4o_rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<35 /* nd4o_rpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<35 /* nd4o_rpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<36 /* nd4o_dpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<36 /* nd4o_dpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<37 /* nd4o_dpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<37 /* nd4o_dpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c
deleted file mode 100644
index 0e83963..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn52xx.c
+++ /dev/null
@@ -1,6665 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn52xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN52XX</h2>
- * @dot
- * digraph cn52xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
- * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
- * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
- * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
- * cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<mio>mio|<ipd>ipd|<tim>tim|<pow>pow|<usb1>usb1|<npei>npei|<rad>rad|<pko>pko|<asxpcs0>asxpcs0|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<usb>usb"];
- * cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
- * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
- * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
- * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
- * cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"];
- * cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
- * cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
- * cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
- * cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
- * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
- * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
- * cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
- * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
- * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
- * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
- * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
- * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn52xx(void);
-
-int cvmx_error_initialize_cn52xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INT_SUM1;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NDF_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<2 /* wdog */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<2 /* wdog */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<3 /* sm_bad */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<3 /* sm_bad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<4 /* ecc_1bit */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<4 /* ecc_1bit */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<5 /* ecc_mult */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<5 /* ecc_mult */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<6 /* ovrf */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<6 /* ovrf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
- " fatal error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_STAT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<3 /* l2tsec */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<3 /* l2tsecen */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<5 /* l2dsec */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<5 /* l2dsecen */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
- " NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<0 /* oob1 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<0 /* oob1en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<1 /* oob2 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<1 /* oob2en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<2 /* oob3 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<2 /* oob3en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<4 /* l2tded */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<4 /* l2tdeden */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<6 /* l2dded */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<6 /* l2ddeden */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
- " NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<7 /* lck */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<7 /* lckena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<8 /* lck2 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<8 /* lck2ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n"
- " NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_BAD_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<32 /* ovrflw */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<33 /* txpop */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<34 /* txpsh */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<35 /* ovrflw1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<36 /* txpop1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<37 /* txpsh1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_TX_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 0x3ull<<2 /* undflw */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 0x3ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_USBNX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<0 /* pr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<0 /* pr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* pr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<1 /* pr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<2 /* nr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<2 /* nr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<3 /* nr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<3 /* nr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<4 /* lr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<4 /* lr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<5 /* lr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<5 /* lr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* pt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<6 /* pt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* pt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<7 /* pt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<8 /* nt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<8 /* nt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<9 /* nt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<9 /* nt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<10 /* lt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<10 /* lt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<11 /* lt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<11 /* lt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<12 /* dcred_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<12 /* dcred_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<13 /* dcred_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<13 /* dcred_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<14 /* l2c_s_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<14 /* l2c_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<15 /* l2c_a_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<15 /* l2c_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[L2C_A_F]: L2C Credit Count Added When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<16 /* lt_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<16 /* l2_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<17 /* lt_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<17 /* l2_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<18 /* rg_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<18 /* rg_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<19 /* rg_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<19 /* rg_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<20 /* rq_q2_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<20 /* rq_q2_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<21 /* rq_q2_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<21 /* rq_q2_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<22 /* rq_q3_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<22 /* rq_q3_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<23 /* rq_q3_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<23 /* rq_q3_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<24 /* uod_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<24 /* uod_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[UOD_PE]: UOD Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<25 /* uod_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<25 /* uod_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[UOD_PF]: UOD Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<32 /* ltl_f_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<32 /* ltl_f_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<33 /* ltl_f_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<33 /* ltl_f_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<34 /* nd4o_rpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<34 /* nd4o_rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<35 /* nd4o_rpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<35 /* nd4o_rpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<36 /* nd4o_dpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<36 /* nd4o_dpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<37 /* nd4o_dpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<37 /* nd4o_dpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_NPEI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<21 /* c0_se */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<21 /* c0_se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
- " Pcie Core 0. (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<38 /* c0_un_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<38 /* c0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<39 /* c0_un_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<39 /* c0_un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<40 /* c0_un_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<40 /* c0_un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<42 /* c0_un_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<42 /* c0_un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<53 /* c0_un_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<53 /* c0_un_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
- " register. Core0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<41 /* c0_un_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<41 /* c0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<33 /* c0_up_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* c0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<34 /* c0_up_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<34 /* c0_up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<35 /* c0_up_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<35 /* c0_up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<37 /* c0_up_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<37 /* c0_up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<55 /* c0_up_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<55 /* c0_up_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
- " register. Core0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<36 /* c0_up_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<36 /* c0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<23 /* c0_wake */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<23 /* c0_wake */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
- " Pcie Core 0. (wake_n)\n"
- " Octeon will never generate this interrupt.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<22 /* crs0_dr */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<22 /* crs0_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<20 /* crs0_er */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<20 /* crs0_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<28 /* c1_se */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<28 /* c1_se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
- " Pcie Core 1. (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<48 /* c1_un_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<48 /* c1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<49 /* c1_un_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<49 /* c1_un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<50 /* c1_un_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<50 /* c1_un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<52 /* c1_un_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<52 /* c1_un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<54 /* c1_un_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<54 /* c1_un_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
- " register. Core1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<51 /* c1_un_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<51 /* c1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<43 /* c1_up_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<43 /* c1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<44 /* c1_up_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<44 /* c1_up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsuppored P-TLP for Bar1.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<45 /* c1_up_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<45 /* c1_up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<47 /* c1_up_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<47 /* c1_up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<56 /* c1_up_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<56 /* c1_up_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
- " register. Core1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<46 /* c1_up_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<46 /* c1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<30 /* c1_wake */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<30 /* c1_wake */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
- " Pcie Core 1. (wake_n)\n"
- " Octeon will never generate this interrupt.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<29 /* crs1_dr */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<29 /* crs1_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<27 /* crs1_er */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<27 /* crs1_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<4 /* dma0dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* dma0dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<5 /* dma1dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* dma1dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<6 /* dma2dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* dma2dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<7 /* dma3dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* dma3dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<8 /* dma4dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<8 /* dma4dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PESCX_DBG_INFO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PESCX_DBG_INFO(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<14 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_USBNX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* pr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<0 /* pr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* pr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* pr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<2 /* nr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<2 /* nr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<3 /* nr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<3 /* nr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* lr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* lr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* lr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* lr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* pt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* pt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* pt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* pt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* nt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* nt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* nt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* nt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<10 /* lt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<10 /* lt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* lt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* lt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* dcred_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* dcred_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* dcred_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* dcred_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<14 /* l2c_s_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<14 /* l2c_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<15 /* l2c_a_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<15 /* l2c_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<16 /* lt_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<16 /* l2_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<17 /* lt_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<17 /* l2_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<18 /* rg_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<18 /* rg_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<19 /* rg_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<19 /* rg_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<20 /* rq_q2_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<20 /* rq_q2_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<21 /* rq_q2_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<21 /* rq_q2_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<22 /* rq_q3_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<22 /* rq_q3_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<23 /* rq_q3_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<23 /* rq_q3_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<24 /* uod_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<24 /* uod_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<25 /* uod_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<25 /* uod_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<32 /* ltl_f_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<32 /* ltl_f_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<33 /* ltl_f_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<33 /* ltl_f_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<34 /* nd4o_rpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<34 /* nd4o_rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<35 /* nd4o_rpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<35 /* nd4o_rpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<36 /* nd4o_dpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<36 /* nd4o_dpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<37 /* nd4o_dpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<37 /* nd4o_dpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c
deleted file mode 100644
index 16ef44e..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn52xxp1.c
+++ /dev/null
@@ -1,6564 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn52xxp1.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN52XXP1</h2>
- * @dot
- * digraph cn52xxp1
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
- * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1"];
- * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<mio>mio|<ipd>ipd|<tim>tim|<pow>pow|<usb1>usb1|<npei>npei|<rad>rad|<pko>pko|<asxpcs0>asxpcs0|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<usb>usb"];
- * cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
- * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
- * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
- * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_usbn1_int_sum [label="USBNX_INT_SUM(1)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
- * cvmx_npei_rsl_int_blocks:usb1:e -> cvmx_usbn1_int_sum [label="usb1"];
- * cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<c0_exc>c0_exc|<c1_exc>c1_exc"];
- * cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
- * cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
- * cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
- * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
- * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
- * cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
- * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
- * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
- * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
- * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
- * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn52xxp1(void);
-
-int cvmx_error_initialize_cn52xxp1(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INT_SUM1;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_STAT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<3 /* l2tsec */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<3 /* l2tsecen */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<5 /* l2dsec */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<5 /* l2dsecen */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
- " NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<0 /* oob1 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<0 /* oob1en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<1 /* oob2 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<1 /* oob2en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<2 /* oob3 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<2 /* oob3en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<4 /* l2tded */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<4 /* l2tdeden */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<6 /* l2dded */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<6 /* l2ddeden */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
- " NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<7 /* lck */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<7 /* lckena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<8 /* lck2 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<8 /* lck2ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n"
- " NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_BAD_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<32 /* ovrflw */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<33 /* txpop */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<34 /* txpsh */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<35 /* ovrflw1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<36 /* txpop1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<37 /* txpsh1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_TX_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 0x3ull<<2 /* undflw */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 0x3ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_USBNX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<0 /* pr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<0 /* pr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* pr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<1 /* pr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<2 /* nr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<2 /* nr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<3 /* nr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<3 /* nr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<4 /* lr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<4 /* lr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<5 /* lr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<5 /* lr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* pt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<6 /* pt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* pt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<7 /* pt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<8 /* nt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<8 /* nt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<9 /* nt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<9 /* nt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<10 /* lt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<10 /* lt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<11 /* lt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<11 /* lt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<12 /* dcred_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<12 /* dcred_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<13 /* dcred_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<13 /* dcred_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<14 /* l2c_s_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<14 /* l2c_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<15 /* l2c_a_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<15 /* l2c_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[L2C_A_F]: L2C Credit Count Added When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<16 /* lt_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<16 /* l2_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<17 /* lt_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<17 /* l2_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<18 /* rg_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<18 /* rg_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<19 /* rg_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<19 /* rg_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<20 /* rq_q2_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<20 /* rq_q2_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<21 /* rq_q2_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<21 /* rq_q2_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<22 /* rq_q3_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<22 /* rq_q3_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<23 /* rq_q3_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<23 /* rq_q3_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<24 /* uod_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<24 /* uod_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[UOD_PE]: UOD Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<25 /* uod_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<25 /* uod_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[UOD_PF]: UOD Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<32 /* ltl_f_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<32 /* ltl_f_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<33 /* ltl_f_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<33 /* ltl_f_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<34 /* nd4o_rpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<34 /* nd4o_rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<35 /* nd4o_rpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<35 /* nd4o_rpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<36 /* nd4o_dpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<36 /* nd4o_dpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(1);
- info.status_mask = 1ull<<37 /* nd4o_dpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(1);
- info.enable_mask = 1ull<<37 /* nd4o_dpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<15 /* usb1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(1)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_NPEI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<21 /* c0_se */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<21 /* c0_se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
- " Pcie Core 0. (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<38 /* c0_un_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<38 /* c0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<39 /* c0_un_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<39 /* c0_un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<40 /* c0_un_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<40 /* c0_un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<42 /* c0_un_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<42 /* c0_un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<53 /* c0_un_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<53 /* c0_un_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
- " register. Core0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<41 /* c0_un_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<41 /* c0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<33 /* c0_up_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* c0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<34 /* c0_up_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<34 /* c0_up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<35 /* c0_up_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<35 /* c0_up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<37 /* c0_up_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<37 /* c0_up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<55 /* c0_up_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<55 /* c0_up_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
- " register. Core0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<36 /* c0_up_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<36 /* c0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<23 /* c0_wake */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<23 /* c0_wake */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
- " Pcie Core 0. (wake_n)\n"
- " Octeon will never generate this interrupt.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<22 /* crs0_dr */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<22 /* crs0_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<20 /* crs0_er */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<20 /* crs0_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<28 /* c1_se */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<28 /* c1_se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
- " Pcie Core 1. (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<48 /* c1_un_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<48 /* c1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<49 /* c1_un_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<49 /* c1_un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<50 /* c1_un_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<50 /* c1_un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<52 /* c1_un_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<52 /* c1_un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<54 /* c1_un_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<54 /* c1_un_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
- " register. Core1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<51 /* c1_un_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<51 /* c1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<43 /* c1_up_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<43 /* c1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<44 /* c1_up_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<44 /* c1_up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<45 /* c1_up_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<45 /* c1_up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<47 /* c1_up_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<47 /* c1_up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<56 /* c1_up_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<56 /* c1_up_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
- " register. Core1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<46 /* c1_up_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<46 /* c1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<30 /* c1_wake */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<30 /* c1_wake */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
- " Pcie Core 1. (wake_n)\n"
- " Octeon will never generate this interrupt.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<29 /* crs1_dr */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<29 /* crs1_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<27 /* crs1_er */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<27 /* crs1_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<4 /* dma0dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* dma0dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell count overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<5 /* dma1dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* dma1dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell count overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<6 /* dma2dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* dma2dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell count overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<7 /* dma3dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* dma3dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell count overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PESCX_DBG_INFO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PESCX_DBG_INFO(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<14 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_USBNX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* pr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<0 /* pr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* pr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* pr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<2 /* nr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<2 /* nr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<3 /* nr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<3 /* nr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* lr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* lr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* lr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* lr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* pt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* pt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* pt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* pt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* nt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* nt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* nt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* nt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<10 /* lt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<10 /* lt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* lt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* lt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* dcred_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* dcred_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* dcred_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* dcred_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<14 /* l2c_s_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<14 /* l2c_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<15 /* l2c_a_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<15 /* l2c_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<16 /* lt_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<16 /* l2_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<17 /* lt_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<17 /* l2_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<18 /* rg_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<18 /* rg_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<19 /* rg_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<19 /* rg_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<20 /* rq_q2_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<20 /* rq_q2_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<21 /* rq_q2_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<21 /* rq_q2_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<22 /* rq_q3_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<22 /* rq_q3_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<23 /* rq_q3_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<23 /* rq_q3_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<24 /* uod_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<24 /* uod_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<25 /* uod_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<25 /* uod_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<32 /* ltl_f_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<32 /* ltl_f_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<33 /* ltl_f_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<33 /* ltl_f_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<34 /* nd4o_rpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<34 /* nd4o_rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<35 /* nd4o_rpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<35 /* nd4o_rpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<36 /* nd4o_dpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<36 /* nd4o_dpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<37 /* nd4o_dpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<37 /* nd4o_dpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c
deleted file mode 100644
index d4ef2ce..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn56xx.c
+++ /dev/null
@@ -1,7659 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn56xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN56XX</h2>
- * @dot
- * digraph cn56xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
- * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<tim>tim|<pko>pko|<pow>pow|<npei>npei|<rad>rad|<lmc1>lmc1|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<zip>zip|<usb>usb"];
- * cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<out_ovr>out_ovr|<loststat>loststat"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
- * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
- * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
- * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
- * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
- * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<crs0_dr>crs0_dr|<crs0_er>crs0_er|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<crs1_dr>crs1_dr|<crs1_er>crs1_er|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
- * cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
- * cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
- * cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_lmc1_mem_cfg0 [label="LMCX_MEM_CFG0(1)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npei_rsl_int_blocks:lmc1:e -> cvmx_lmc1_mem_cfg0 [label="lmc1"];
- * cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
- * cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
- * cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
- * cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
- * cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
- * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
- * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
- * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_npei_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
- * cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
- * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
- * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
- * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
- * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
- * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
- * cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
- * cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
- * cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
- * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
- * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn56xx(void);
-
-int cvmx_error_initialize_cn56xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_STAT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<3 /* l2tsec */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<3 /* l2tsecen */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<5 /* l2dsec */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<5 /* l2dsecen */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
- " NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<0 /* oob1 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<0 /* oob1en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<1 /* oob2 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<1 /* oob2en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<2 /* oob3 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<2 /* oob3en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<4 /* l2tded */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<4 /* l2tdeden */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<6 /* l2dded */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<6 /* l2ddeden */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
- " NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<7 /* lck */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<7 /* lckena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<8 /* lck2 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<8 /* lck2ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n"
- " NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_BAD_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<32 /* ovrflw */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<33 /* txpop */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<34 /* txpsh */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_TX_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<2 /* undflw */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_NPEI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<59 /* c0_ldwn */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<59 /* c0_ldwn */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<21 /* c0_se */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<21 /* c0_se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
- " Pcie Core 0. (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<38 /* c0_un_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<38 /* c0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<39 /* c0_un_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<39 /* c0_un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<40 /* c0_un_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<40 /* c0_un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<42 /* c0_un_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<42 /* c0_un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<53 /* c0_un_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<53 /* c0_un_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
- " register. Core0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<41 /* c0_un_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<41 /* c0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<33 /* c0_up_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* c0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<34 /* c0_up_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<34 /* c0_up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<35 /* c0_up_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<35 /* c0_up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<37 /* c0_up_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<37 /* c0_up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<55 /* c0_up_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<55 /* c0_up_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
- " register. Core0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<36 /* c0_up_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<36 /* c0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<23 /* c0_wake */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<23 /* c0_wake */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
- " Pcie Core 0. (wake_n)\n"
- " Octeon will never generate this interrupt.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<22 /* crs0_dr */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<22 /* crs0_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS0_DR]: Had a CRS when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<20 /* crs0_er */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<20 /* crs0_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS0_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<60 /* c1_ldwn */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<60 /* c1_ldwn */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<28 /* c1_se */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<28 /* c1_se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
- " Pcie Core 1. (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<48 /* c1_un_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<48 /* c1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<49 /* c1_un_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<49 /* c1_un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<50 /* c1_un_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<50 /* c1_un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<52 /* c1_un_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<52 /* c1_un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<54 /* c1_un_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<54 /* c1_un_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
- " register. Core1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<51 /* c1_un_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<51 /* c1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<43 /* c1_up_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<43 /* c1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<44 /* c1_up_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<44 /* c1_up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsuppored P-TLP for Bar1.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<45 /* c1_up_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<45 /* c1_up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<47 /* c1_up_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<47 /* c1_up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<56 /* c1_up_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<56 /* c1_up_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
- " register. Core1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<46 /* c1_up_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<46 /* c1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<30 /* c1_wake */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<30 /* c1_wake */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
- " Pcie Core 1. (wake_n)\n"
- " Octeon will never generate this interrupt.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<29 /* crs1_dr */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<29 /* crs1_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS1_DR]: Had a CRS when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<27 /* crs1_er */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<27 /* crs1_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[CRS1_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<4 /* dma0dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* dma0dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<5 /* dma1dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* dma1dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<6 /* dma2dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* dma2dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<7 /* dma3dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* dma3dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<8 /* dma4dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<8 /* dma4dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PESCX_DBG_INFO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PESCX_DBG_INFO(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<14 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(1);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(1);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<29 /* lmc1 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(1);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(1);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<29 /* lmc1 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_USBNX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* pr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<0 /* pr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* pr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* pr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<2 /* nr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<2 /* nr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<3 /* nr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<3 /* nr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* lr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* lr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* lr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* lr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* pt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* pt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* pt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* pt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* nt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* nt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* nt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* nt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<10 /* lt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<10 /* lt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* lt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* lt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* dcred_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* dcred_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* dcred_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* dcred_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<14 /* l2c_s_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<14 /* l2c_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<15 /* l2c_a_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<15 /* l2c_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<16 /* lt_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<16 /* l2_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<17 /* lt_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<17 /* l2_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<18 /* rg_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<18 /* rg_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<19 /* rg_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<19 /* rg_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<20 /* rq_q2_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<20 /* rq_q2_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<21 /* rq_q2_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<21 /* rq_q2_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<22 /* rq_q3_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<22 /* rq_q3_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<23 /* rq_q3_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<23 /* rq_q3_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<24 /* uod_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<24 /* uod_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<25 /* uod_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<25 /* uod_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<32 /* ltl_f_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<32 /* ltl_f_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<33 /* ltl_f_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<33 /* ltl_f_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<34 /* nd4o_rpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<34 /* nd4o_rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<35 /* nd4o_rpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<35 /* nd4o_rpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<36 /* nd4o_dpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<36 /* nd4o_dpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<37 /* nd4o_dpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<37 /* nd4o_dpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c
deleted file mode 100644
index 557d8ab..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn56xxp1.c
+++ /dev/null
@@ -1,7210 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn56xxp1.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN56XXP1</h2>
- * @dot
- * digraph cn56xxp1
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
- * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npei_rsl_int_blocks [label="PEXP_NPEI_RSL_INT_BLOCKS|<l2c>l2c|<agl>agl|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<tim>tim|<pko>pko|<pow>pow|<npei>npei|<rad>rad|<lmc1>lmc1|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<zip>zip|<usb>usb"];
- * cvmx_l2c_int_stat [label="L2C_INT_STAT|<l2tsec>l2tsec|<l2dsec>l2dsec|<oob1>oob1|<oob2>oob2|<oob3>oob3|<l2tded>l2tded|<l2dded>l2dded|<lck>lck|<lck2>lck2"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2c_int_stat [label="l2c"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npei_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<out_ovr>out_ovr|<loststat>loststat"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
- * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
- * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npei_rsl_int_blocks:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npei_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
- * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
- * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
- * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_npei_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_npei_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npei_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_npei_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_npei_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_npei_int_sum [label="PEXP_NPEI_INT_SUM|<c0_ldwn>c0_ldwn|<c0_se>c0_se|<c0_un_b0>c0_un_b0|<c0_un_b1>c0_un_b1|<c0_un_b2>c0_un_b2|<c0_un_bx>c0_un_bx|<c0_un_wf>c0_un_wf|<c0_un_wi>c0_un_wi|<c0_up_b0>c0_up_b0|<c0_up_b1>c0_up_b1|<c0_up_b2>c0_up_b2|<c0_up_bx>c0_up_bx|<c0_up_wf>c0_up_wf|<c0_up_wi>c0_up_wi|<c0_wake>c0_wake|<c1_ldwn>c1_ldwn|<c1_se>c1_se|<c1_un_b0>c1_un_b0|<c1_un_b1>c1_un_b1|<c1_un_b2>c1_un_b2|<c1_un_bx>c1_un_bx|<c1_un_wf>c1_un_wf|<c1_un_wi>c1_un_wi|<c1_up_b0>c1_up_b0|<c1_up_b1>c1_up_b1|<c1_up_b2>c1_up_b2|<c1_up_bx>c1_up_bx|<c1_up_wf>c1_up_wf|<c1_up_wi>c1_up_wi|<c1_wake>c1_wake|<bar0_to>bar0_to|<dma0dbo>dma0dbo|<dma1dbo>dma1dbo|<dma2dbo>dma2dbo|<dma3dbo>dma3dbo|<iob2big>iob2big|<rml_rto>rml_rto|<rml_wto>rml_wto|<dma4dbo>dma4dbo|<c0_exc>c0_exc|<c1_exc>c1_exc"];
- * cvmx_pesc0_dbg_info [label="PESCX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_npei_int_sum:c0_exc:e -> cvmx_pesc0_dbg_info [label="c0_exc"];
- * cvmx_pesc1_dbg_info [label="PESCX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_npei_int_sum:c1_exc:e -> cvmx_pesc1_dbg_info [label="c1_exc"];
- * cvmx_npei_rsl_int_blocks:npei:e -> cvmx_npei_int_sum [label="npei"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_npei_rsl_int_blocks:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_lmc1_mem_cfg0 [label="LMCX_MEM_CFG0(1)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npei_rsl_int_blocks:lmc1:e -> cvmx_lmc1_mem_cfg0 [label="lmc1"];
- * cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
- * cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
- * cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
- * cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
- * cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
- * cvmx_npei_rsl_int_blocks:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
- * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
- * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos"];
- * cvmx_npei_rsl_int_blocks:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_npei_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npei_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
- * cvmx_npei_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npei_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npei_rsl_int_blocks:lmc0:e -> cvmx_lmc0_mem_cfg0 [label="lmc0"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_npei_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_npei_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_usbn0_int_sum [label="USBNX_INT_SUM(0)|<pr_po_e>pr_po_e|<pr_pu_f>pr_pu_f|<nr_po_e>nr_po_e|<nr_pu_f>nr_pu_f|<lr_po_e>lr_po_e|<lr_pu_f>lr_pu_f|<pt_po_e>pt_po_e|<pt_pu_f>pt_pu_f|<nt_po_e>nt_po_e|<nt_pu_f>nt_pu_f|<lt_po_e>lt_po_e|<lt_pu_f>lt_pu_f|<dcred_e>dcred_e|<dcred_f>dcred_f|<l2c_s_e>l2c_s_e|<l2c_a_f>l2c_a_f|<lt_fi_e>lt_fi_e|<lt_fi_f>lt_fi_f|<rg_fi_e>rg_fi_e|<rg_fi_f>rg_fi_f|<rq_q2_f>rq_q2_f|<rq_q2_e>rq_q2_e|<rq_q3_f>rq_q3_f|<rq_q3_e>rq_q3_e|<uod_pe>uod_pe|<uod_pf>uod_pf|<ltl_f_pe>ltl_f_pe|<ltl_f_pf>ltl_f_pf|<nd4o_rpe>nd4o_rpe|<nd4o_rpf>nd4o_rpf|<nd4o_dpe>nd4o_dpe|<nd4o_dpf>nd4o_dpf"];
- * cvmx_npei_rsl_int_blocks:usb:e -> cvmx_usbn0_int_sum [label="usb"];
- * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
- * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
- * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
- * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
- * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
- * cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
- * cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
- * cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
- * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
- * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npei_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn56xxp1(void);
-
-int cvmx_error_initialize_cn56xxp1(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_PEXP_NPEI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_STAT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<3 /* l2tsec */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<3 /* l2tsecen */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2TSEC]: L2T Single Bit Error corrected (SEC) status\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[SEC_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<5 /* l2dsec */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<5 /* l2dsecen */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2DSEC]: L2D Single Error corrected (SEC)\n"
- " NOTE: This is the 'same' bit as L2D_ERR[SEC_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<0 /* oob1 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<0 /* oob1en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB1]: DMA Out of Bounds Interrupt Status Range#1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<1 /* oob2 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<1 /* oob2en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB2]: DMA Out of Bounds Interrupt Status Range#2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<2 /* oob3 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<2 /* oob3en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[OOB3]: DMA Out of Bounds Interrupt Status Range#3\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<4 /* l2tded */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<4 /* l2tdeden */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2TDED]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[DED_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<6 /* l2dded */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<6 /* l2ddeden */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[L2DDED]: L2D Double Error detected (DED)\n"
- " NOTE: This is the 'same' bit as L2D_ERR[DED_ERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<7 /* lck */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<7 /* lckena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[LCK]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n"
- " NOTE: This is the 'same' bit as L2T_ERR[LCKERR]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_STAT;
- info.status_mask = 1ull<<8 /* lck2 */;
- info.enable_addr = CVMX_L2C_INT_EN;
- info.enable_mask = 1ull<<8 /* lck2ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_STAT[LCK2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n"
- " NOTE: This is the 'same' bit as L2T_ERR[LCKERR2]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_BAD_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<32 /* ovrflw */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<33 /* txpop */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<34 /* txpsh */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_TX_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<2 /* undflw */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow (MII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_NPEI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<59 /* c0_ldwn */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<59 /* c0_ldwn */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_LDWN]: Reset request due to link0 down status.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<21 /* c0_se */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<21 /* c0_se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_SE]: System Error, RC Mode Only.\n"
- " Pcie Core 0. (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<38 /* c0_un_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<38 /* c0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<39 /* c0_un_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<39 /* c0_un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<40 /* c0_un_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<40 /* c0_un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<42 /* c0_un_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<42 /* c0_un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<53 /* c0_un_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<53 /* c0_un_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_WF]: Received Unsupported N-TLP for filtered window\n"
- " register. Core0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<41 /* c0_un_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<41 /* c0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<33 /* c0_up_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* c0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<34 /* c0_up_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<34 /* c0_up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<35 /* c0_up_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<35 /* c0_up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<37 /* c0_up_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<37 /* c0_up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<55 /* c0_up_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<55 /* c0_up_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_WF]: Received Unsupported P-TLP for filtered window\n"
- " register. Core0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<36 /* c0_up_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<36 /* c0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
- " Core 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<23 /* c0_wake */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<23 /* c0_wake */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C0_WAKE]: Wake up from Power Management Unit.\n"
- " Pcie Core 0. (wake_n)\n"
- " Octeon will never generate this interrupt.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<60 /* c1_ldwn */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<60 /* c1_ldwn */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_LDWN]: Reset request due to link1 down status.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<28 /* c1_se */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<28 /* c1_se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_SE]: System Error, RC Mode Only.\n"
- " Pcie Core 1. (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<48 /* c1_un_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<48 /* c1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B0]: Received Unsupported N-TLP for Bar0.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<49 /* c1_un_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<49 /* c1_un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B1]: Received Unsupported N-TLP for Bar1.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<50 /* c1_un_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<50 /* c1_un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_B2]: Received Unsupported N-TLP for Bar2.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<52 /* c1_un_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<52 /* c1_un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_BX]: Received Unsupported N-TLP for unknown Bar.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<54 /* c1_un_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<54 /* c1_un_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_WF]: Received Unsupported N-TLP for filtered window\n"
- " register. Core1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<51 /* c1_un_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<51 /* c1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UN_WI]: Received Unsupported N-TLP for Window Register.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<43 /* c1_up_b0 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<43 /* c1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B0]: Received Unsupported P-TLP for Bar0.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<44 /* c1_up_b1 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<44 /* c1_up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B1]: Received Unsupported P-TLP for Bar1.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<45 /* c1_up_b2 */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<45 /* c1_up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_B2]: Received Unsupported P-TLP for Bar2.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<47 /* c1_up_bx */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<47 /* c1_up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_BX]: Received Unsupported P-TLP for unknown Bar.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<56 /* c1_up_wf */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<56 /* c1_up_wf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_WF]: Received Unsupported P-TLP for filtered window\n"
- " register. Core1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<46 /* c1_up_wi */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<46 /* c1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_UP_WI]: Received Unsupported P-TLP for Window Register.\n"
- " Core 1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<30 /* c1_wake */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<30 /* c1_wake */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[C1_WAKE]: Wake up from Power Management Unit.\n"
- " Pcie Core 1. (wake_n)\n"
- " Octeon will never generate this interrupt.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<4 /* dma0dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* dma0dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA0DBO]: DMA0 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<5 /* dma1dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* dma1dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA1DBO]: DMA1 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<6 /* dma2dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* dma2dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA2DBO]: DMA2 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<7 /* dma3dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* dma3dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA3DBO]: DMA3 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[RML_RTO]: RML read did not return data in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[RML_WTO]: RML write did not get commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 1ull<<8 /* dma4dbo */;
- info.enable_addr = CVMX_PEXP_NPEI_INT_ENB2;
- info.enable_mask = 1ull<<8 /* dma4dbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_NPEI_INT_SUM[DMA4DBO]: DMA4 doorbell overflow.\n"
- " Bit[32] of the doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npei */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PESCX_DBG_INFO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(0);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<57 /* c0_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PESCX_DBG_INFO(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PESCX_DBG_INFO(1);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PESCX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_INT_SUM;
- info.parent.status_mask = 1ull<<58 /* c1_exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PESCX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<14 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(1);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(1);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<29 /* lmc1 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(1);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(1);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<29 /* lmc1 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_USBNX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* pr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<0 /* pr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PO_E]: PP Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* pr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* pr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PR_PU_F]: PP Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<2 /* nr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<2 /* nr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PO_E]: NPI Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<3 /* nr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<3 /* nr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NR_PU_F]: NPI Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* lr_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* lr_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PO_E]: L2C Request Fifo Popped When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* lr_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* lr_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LR_PU_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* pt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* pt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PO_E]: PP Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* pt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* pt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[PT_PU_F]: PP Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* nt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* nt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PO_E]: NPI Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* nt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* nt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[NT_PU_F]: NPI Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<10 /* lt_po_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<10 /* lt_po_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PO_E]: L2C Trasaction Fifo Popped When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* lt_pu_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* lt_pu_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_PU_F]: L2C Trasaction Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* dcred_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* dcred_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_E]: Data Credit Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* dcred_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* dcred_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[DCRED_F]: Data CreditFifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<14 /* l2c_s_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<14 /* l2c_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_S_E]: L2C Credit Count Subtracted When Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<15 /* l2c_a_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<15 /* l2c_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[L2C_A_F]: L2C Credit Count Added When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<16 /* lt_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<16 /* l2_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_E]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<17 /* lt_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<17 /* l2_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LT_FI_F]: L2C Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<18 /* rg_fi_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<18 /* rg_fi_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_E]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<19 /* rg_fi_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<19 /* rg_fi_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RG_FI_F]: Register Request Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<20 /* rq_q2_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<20 /* rq_q2_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_F]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<21 /* rq_q2_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<21 /* rq_q2_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q2_E]: Request Queue-2 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<22 /* rq_q3_f */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<22 /* rq_q3_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_F]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<23 /* rq_q3_e */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<23 /* rq_q3_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[RQ_Q3_E]: Request Queue-3 Fifo Pushed When Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<24 /* uod_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<24 /* uod_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PE]: UOD Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<25 /* uod_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<25 /* uod_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[UOD_PF]: UOD Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<32 /* ltl_f_pe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<32 /* ltl_f_pe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PE]: L2C Transfer Length Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<33 /* ltl_f_pf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<33 /* ltl_f_pf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[LTL_F_PF]: L2C Transfer Length Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<34 /* nd4o_rpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<34 /* nd4o_rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPE]: NCB DMA Out Request Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<35 /* nd4o_rpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<35 /* nd4o_rpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_RPF]: NCB DMA Out Request Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<36 /* nd4o_dpe */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<36 /* nd4o_dpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPE]: NCB DMA Out Data Fifo Pop Empty.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_USBNX_INT_SUM(0);
- info.status_mask = 1ull<<37 /* nd4o_dpf */;
- info.enable_addr = CVMX_USBNX_INT_ENB(0);
- info.enable_mask = 1ull<<37 /* nd4o_dpf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEXP_NPEI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR USBNX_INT_SUM(0)[ND4O_DPF]: NCB DMA Out Data Fifo Push Full.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c
deleted file mode 100644
index d2f6723..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn58xx.c
+++ /dev/null
@@ -1,4939 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn58xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN58XX</h2>
- * @dot
- * digraph cn58xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
- * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
- * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
- * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
- * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
- * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
- * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
- * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
- * cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
- * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
- * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
- * cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
- * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
- * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
- * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
- * cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
- * cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
- * cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
- * cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
- * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
- * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
- * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
- * cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn58xx(void);
-
-int cvmx_error_initialize_cn58xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_NPI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
- " back from a RSL after sending a read command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
- " back from a RSL after sending a write command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<3 /* po0_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<3 /* po0_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<4 /* po1_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<4 /* po1_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<5 /* po2_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<5 /* po2_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<6 /* po3_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<6 /* po3_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<7 /* i0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<7 /* i0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<8 /* i1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<8 /* i1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<9 /* i2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<9 /* i2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<10 /* i3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<10 /* i3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<11 /* i0_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<11 /* i0_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<12 /* i1_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<12 /* i1_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<13 /* i2_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<13 /* i2_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<14 /* i3_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<14 /* i3_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<15 /* p0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<15 /* p0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<16 /* p1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<16 /* p1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<17 /* p2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<17 /* p2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<18 /* p3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<18 /* p3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<19 /* p0_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<19 /* p0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<20 /* p1_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<20 /* p1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<21 /* p2_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<21 /* p2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<22 /* p3_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<22 /* p3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<23 /* g0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<23 /* g0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<24 /* g1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<24 /* g1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<25 /* g2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<25 /* g2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<26 /* g3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<26 /* g3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<27 /* p0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<27 /* p0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<28 /* p1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<28 /* p1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<29 /* p2_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<29 /* p2_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<30 /* p3_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<30 /* p3_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<31 /* p0_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<31 /* p0_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<32 /* p1_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<32 /* p1_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<33 /* p2_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<33 /* p2_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<34 /* p3_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<34 /* p3_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<35 /* i0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<35 /* i0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<36 /* i1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<36 /* i1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<37 /* i2_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<37 /* i2_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<38 /* i3_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<38 /* i3_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<39 /* win_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<39 /* win_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<40 /* p_dperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<40 /* p_dperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
- " from the PCI this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<41 /* iobdma */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<41 /* iobdma */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<42 /* fcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<42 /* fcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<43 /* fcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<43 /* fcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<44 /* pcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<44 /* pcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<45 /* pcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<45 /* pcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<46 /* q2_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<46 /* q2_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<47 /* q2_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<47 /* q2_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<48 /* q3_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<48 /* q3_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<49 /* q3_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<49 /* q3_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<50 /* com_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<50 /* com_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<51 /* com_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<51 /* com_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<52 /* pnc_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<52 /* pnc_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<53 /* pnc_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<53 /* pnc_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<54 /* rwx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<54 /* rwx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<55 /* rdx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<55 /* rdx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<56 /* pcf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<56 /* pcf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<57 /* pcf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<57 /* pcf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<58 /* pdf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<58 /* pdf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<59 /* pdf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<59 /* pdf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<60 /* q1_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<60 /* q1_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<61 /* q1_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<61 /* q1_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_PCI_INT_SUM2 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<0 /* tr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rtr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<1 /* mr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rmr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<2 /* mr_wtto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* rmr_wtto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<3 /* tr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* rtr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<4 /* mr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* rmr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<5 /* mr_tto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* rmr_tto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<6 /* msi_per */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* rmsi_per */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<7 /* msi_tabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* rmsi_tabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<8 /* msi_mabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<8 /* rmsi_mabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<9 /* msc_msg */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<9 /* rmsc_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<10 /* tsr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<10 /* rtsr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<11 /* serr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<11 /* rserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<12 /* aperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<12 /* raperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<13 /* dperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<13 /* rdperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<14 /* ill_rwr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<14 /* ill_rwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<15 /* ill_rrd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<15 /* ill_rrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<31 /* win_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<31 /* win_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
- " Read-Address Register took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<32 /* ill_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<32 /* ill_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<33 /* ill_rd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* ill_rd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<0 /* out_col */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<1 /* ncb_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xffffull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<1 /* ncb_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* ncb_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<0 /* out_col */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<1 /* ncb_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xffffull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<1 /* ncb_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* ncb_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SPXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* prtnxa */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<0 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* abnorm */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<1 /* abnorm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* spiovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<4 /* spiovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* clserr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<5 /* clserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* drwnng */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<6 /* drwnng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<7 /* rsverr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<7 /* rsverr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* tpaovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<8 /* tpaovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<9 /* diperr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<9 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* syncerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<10 /* syncerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
- " SPX_ERR_CTL[ERRCNT]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<11 /* calerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<11 /* calerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_STXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* calpar0 */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<0 /* calpar0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* calpar1 */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<1 /* calpar1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* ovrbst */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<2 /* ovrbst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* datovr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<3 /* datovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* diperr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<4 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* nosync */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<5 /* nosync */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* unxfrm */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<6 /* unxfrm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<7 /* frmerr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<7 /* frmerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SPXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* prtnxa */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<0 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* abnorm */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<1 /* abnorm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* spiovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<4 /* spiovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* clserr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<5 /* clserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* drwnng */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<6 /* drwnng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<7 /* rsverr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<7 /* rsverr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<8 /* tpaovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<8 /* tpaovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<9 /* diperr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<9 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<10 /* syncerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<10 /* syncerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
- " SPX_ERR_CTL[ERRCNT]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<11 /* calerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<11 /* calerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_STXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* calpar0 */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<0 /* calpar0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* calpar1 */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<1 /* calpar1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<2 /* ovrbst */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<2 /* ovrbst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<3 /* datovr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<3 /* datovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* diperr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<4 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* nosync */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<5 /* nosync */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* unxfrm */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<6 /* unxfrm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<7 /* frmerr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<7 /* frmerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 128b mode, ecc is calulated on 1 cycle worth of data\n"
- " [21] corresponds to DQ[63:0], Phase0\n"
- " [22] corresponds to DQ[127:64], Phase0\n"
- " [23] corresponds to DQ[63:0], Phase1\n"
- " [24] corresponds to DQ[127:64], Phase1\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [21] corresponds to DQ[63:0], Phase0, cycle0\n"
- " [22] corresponds to DQ[63:0], Phase0, cycle1\n"
- " [23] corresponds to DQ[63:0], Phase1, cycle0\n"
- " [24] corresponds to DQ[63:0], Phase1, cycle1\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 128b mode, ecc is calulated on 1 cycle worth of data\n"
- " [25] corresponds to DQ[63:0], Phase0\n"
- " [26] corresponds to DQ[127:64], Phase0\n"
- " [27] corresponds to DQ[63:0], Phase1\n"
- " [28] corresponds to DQ[127:64], Phase1\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [25] corresponds to DQ[63:0], Phase0, cycle0\n"
- " [26] corresponds to DQ[63:0], Phase0, cycle1\n"
- " [27] corresponds to DQ[63:0], Phase1, cycle0\n"
- " [28] corresponds to DQ[63:0], Phase1, cycle1\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<1 /* cp2sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2sbe;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
- " When set, a single bit error had been detected and\n"
- " corrected for a PP-generated QW Mode read\n"
- " transaction.\n"
- " If the CP2DBE=0, then the CP2SYN contains the\n"
- " failing syndrome (used during correction).\n"
- " Refer to CP2ECCENA.\n"
- " If the CP2SBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n"
- " NOTE: PP-generated LW Mode Read transactions\n"
- " do not participate in ECC check/correct).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<2 /* cp2dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2dbe;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
- " When set, a double bit error had been detected\n"
- " for a PP-generated QW Mode read transaction.\n"
- " The CP2SYN contains the failing syndrome.\n"
- " NOTE: PP-generated LW Mode Read transactions\n"
- " do not participate in ECC check/correct).\n"
- " Refer to CP2ECCENA.\n"
- " If the CP2DBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<14 /* dtesbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dtesbe;
- info.user_info = (long)
- "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n"
- " When set, a single bit error had been detected and\n"
- " corrected for a DTE-generated 36b SIMPLE Mode read\n"
- " transaction.\n"
- " If the DTEDBE=0, then the DTESYN contains the\n"
- " failing syndrome (used during correction).\n"
- " NOTE: DTE-generated 18b SIMPLE Mode Read\n"
- " transactions do not participate in ECC check/correct).\n"
- " If the DTESBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<15 /* dtedbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dtedbe;
- info.user_info = (long)
- "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n"
- " When set, a double bit error had been detected\n"
- " for a DTE-generated 36b SIMPLE Mode read transaction.\n"
- " The DTESYN contains the failing syndrome.\n"
- " If the DTEDBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n"
- " NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n"
- " do not participate in ECC check/correct).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<26 /* dteperr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dteperr;
- info.user_info = (long)
- "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n"
- " When set, all DTE-generated 18b SIMPLE Mode read\n"
- " transactions which encounter a parity error (across\n"
- " the 17b of data) are reported.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<29 /* cp2perr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2perr;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
- " When set, a parity error had been detected for a\n"
- " PP-generated LW Mode read transaction.\n"
- " If the CP2PINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<31 /* dblovf */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dblovf;
- info.user_info = (long)
- "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c
deleted file mode 100644
index 756526c..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn58xxp1.c
+++ /dev/null
@@ -1,4922 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn58xxp1.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN58XXP1</h2>
- * @dot
- * digraph cn58xxp1
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
- * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
- * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
- * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
- * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
- * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
- * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
- * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
- * cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
- * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
- * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
- * cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
- * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
- * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
- * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
- * cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
- * cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
- * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
- * cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
- * cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
- * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
- * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
- * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
- * cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn58xxp1(void);
-
-int cvmx_error_initialize_cn58xxp1(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_NPI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
- " back from a RSL after sending a read command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
- " back from a RSL after sending a write command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<3 /* po0_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<3 /* po0_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<4 /* po1_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<4 /* po1_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<5 /* po2_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<5 /* po2_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<6 /* po3_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<6 /* po3_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<7 /* i0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<7 /* i0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<8 /* i1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<8 /* i1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<9 /* i2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<9 /* i2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<10 /* i3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<10 /* i3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<11 /* i0_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<11 /* i0_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<12 /* i1_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<12 /* i1_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<13 /* i2_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<13 /* i2_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<14 /* i3_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<14 /* i3_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<15 /* p0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<15 /* p0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<16 /* p1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<16 /* p1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<17 /* p2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<17 /* p2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<18 /* p3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<18 /* p3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<19 /* p0_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<19 /* p0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<20 /* p1_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<20 /* p1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<21 /* p2_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<21 /* p2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<22 /* p3_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<22 /* p3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<23 /* g0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<23 /* g0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<24 /* g1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<24 /* g1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<25 /* g2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<25 /* g2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<26 /* g3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<26 /* g3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<27 /* p0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<27 /* p0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<28 /* p1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<28 /* p1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<29 /* p2_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<29 /* p2_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<30 /* p3_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<30 /* p3_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<31 /* p0_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<31 /* p0_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<32 /* p1_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<32 /* p1_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<33 /* p2_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<33 /* p2_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<34 /* p3_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<34 /* p3_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<35 /* i0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<35 /* i0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<36 /* i1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<36 /* i1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<37 /* i2_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<37 /* i2_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<38 /* i3_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<38 /* i3_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<39 /* win_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<39 /* win_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[WIN_RTO]: Windowed Load Timed Out.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<40 /* p_dperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<40 /* p_dperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P_DPERR]: If a parity error occured on data written to L2C\n"
- " from the PCI this bit may be set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<41 /* iobdma */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<41 /* iobdma */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[IOBDMA]: Requested IOBDMA read size exceeded 128 words.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<42 /* fcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<42 /* fcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_S_E]: Attempted to subtract when FPA Credits is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<43 /* fcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<43 /* fcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[FCR_A_F]: Attempted to add when FPA Credits is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<44 /* pcr_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<44 /* pcr_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_S_E]: Attempted to subtract when POW Credits is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<45 /* pcr_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<45 /* pcr_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCR_A_F]: Attempted to add when POW Credits is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<46 /* q2_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<46 /* q2_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_S_E]: Attempted to subtract when Queue-2 FIFO is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<47 /* q2_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<47 /* q2_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q2_A_F]: Attempted to add when Queue-2 FIFO is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<48 /* q3_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<48 /* q3_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_S_E]: Attempted to subtract when Queue-3 FIFO is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<49 /* q3_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<49 /* q3_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q3_A_F]: Attempted to add when Queue-3 FIFO is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<50 /* com_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<50 /* com_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_S_E]: Attempted to subtract when PCN-Commit Counter is 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<51 /* com_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<51 /* com_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[COM_A_F]: Attempted to add when PCN-Commit Counter is max.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<52 /* pnc_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<52 /* pnc_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_S_E]: Attempted to subtract when PNI-NPI Credits are 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<53 /* pnc_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<53 /* pnc_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PNC_A_F]: Attempted to add when PNI-NPI Credits are max.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<54 /* rwx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<54 /* rwx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RWX_S_E]: Attempted to subtract when RDN-XFR-Wait count is 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<55 /* rdx_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<55 /* rdx_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RDX_S_E]: Attempted to subtract when DPI-XFR-Wait count is 0.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<56 /* pcf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<56 /* pcf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_E]: Attempted to pop an empty PCN-CNT-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<57 /* pcf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<57 /* pcf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PCF_P_F]: Attempted to push a full PCN-CNT-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<58 /* pdf_p_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<58 /* pdf_p_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_E]: Attempted to pop an empty PCN-DATA-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<59 /* pdf_p_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<59 /* pdf_p_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PDF_P_F]: Attempted to push a full PCN-DATA-FIFO.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<60 /* q1_s_e */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<60 /* q1_s_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_S_E]: Attempted to subtract when Queue-1 FIFO is empty.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<61 /* q1_a_f */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<61 /* q1_a_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[Q1_A_F]: Attempted to add when Queue-1 FIFO is full.\n"
- " PASS3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NPI_PCI_INT_SUM2 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<0 /* tr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<0 /* rtr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_WABT]: PCI Target Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<1 /* mr_wabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<1 /* rmr_wabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WABT]: PCI Master Abort detected on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<2 /* mr_wtto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<2 /* rmr_wtto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_WTTO]: PCI Master Retry Timeout on write.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<3 /* tr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<3 /* rtr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TR_ABT]: PCI Target Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<4 /* mr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<4 /* rmr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_ABT]: PCI Master Abort On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<5 /* mr_tto */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<5 /* rmr_tto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MR_TTO]: PCI Master Retry Timeout On Read.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<6 /* msi_per */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<6 /* rmsi_per */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_PER]: PCI MSI Parity Error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<7 /* msi_tabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<7 /* rmsi_tabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_TABT]: PCI MSI Target Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<8 /* msi_mabt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<8 /* rmsi_mabt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSI_MABT]: PCI MSI Master Abort.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<9 /* msc_msg */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<9 /* rmsc_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[MSC_MSG]: Master Split Completion Message Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<10 /* tsr_abt */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<10 /* rtsr_abt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[TSR_ABT]: Target Split-Read Abort Detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<11 /* serr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<11 /* rserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[SERR]: SERR# detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<12 /* aperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<12 /* raperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[APERR]: Address Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<13 /* dperr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<13 /* rdperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[DPERR]: Data Parity Error detected by PCX Core\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<14 /* ill_rwr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<14 /* ill_rwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RWR]: A write to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<15 /* ill_rrd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<15 /* ill_rrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RRD]: A read to the disabled PCI registers took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<31 /* win_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<31 /* win_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[WIN_WR]: A write to the disabled Window Write Data or\n"
- " Read-Address Register took place.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<32 /* ill_wr */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<32 /* ill_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_WR]: A write to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_PCI_INT_SUM2;
- info.status_mask = 1ull<<33 /* ill_rd */;
- info.enable_addr = CVMX_NPI_PCI_INT_ENB2;
- info.enable_mask = 1ull<<33 /* ill_rd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_INT_SUM;
- info.parent.status_mask = 1ull<<2 /* pci_rsl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_PCI_INT_SUM2[ILL_RD]: A read to a disabled area of bar1 or bar2,\n"
- " when the mem area is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<0 /* out_col */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<1 /* ncb_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xffffull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<1 /* ncb_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* ncb_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<0 /* out_col */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_COL]: Outbound collision occured between PKO and NCB\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<1 /* ncb_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[NCB_OVR]: Outbound NCB FIFO Overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xffffull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written (per RGM port)\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: RGMII carrier extend error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<2 /* maxerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<2 /* maxerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[MAXERR]: Frame was received with length > max_length\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<5 /* alnerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<5 /* alnerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[ALNERR]: Frame was received with an alignment error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<6 /* lenerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<6 /* lenerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[LENERR]: Frame was received with length error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<9 /* niberr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<9 /* niberr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[NIBERR]: Nibble error (hi_nibble != lo_nibble)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<1 /* ncb_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* ncb_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[NCB_NXA]: Port address out-of-range from NCB Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow (RGMII mode only)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"
- " This is a PASS-3 Field.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SPXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* prtnxa */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<0 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[PRTNXA]: Port out of range\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* abnorm */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<1 /* abnorm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[ABNORM]: Abnormal packet termination (ERR bit)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* spiovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<4 /* spiovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[SPIOVR]: Spi async FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* clserr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<5 /* clserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* drwnng */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<6 /* drwnng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<7 /* rsverr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<7 /* rsverr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[RSVERR]: Spi4 reserved control word detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* tpaovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<8 /* tpaovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[TPAOVR]: Selected port has hit TPA overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<9 /* diperr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<9 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[DIPERR]: Spi4 DIP4 error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* syncerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<10 /* syncerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
- " SPX_ERR_CTL[ERRCNT]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(0);
- info.status_mask = 1ull<<11 /* calerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(0);
- info.enable_mask = 1ull<<11 /* calerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(0)[CALERR]: Spi4 Calendar table parity error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_STXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* calpar0 */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<0 /* calpar0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* calpar1 */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<1 /* calpar1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* ovrbst */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<2 /* ovrbst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[OVRBST]: Transmit packet burst too big\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* datovr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<3 /* datovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[DATOVR]: Spi4 FIFO overflow error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* diperr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<4 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* nosync */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<5 /* nosync */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* unxfrm */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<6 /* unxfrm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[UNXFRM]: Unexpected framing sequence\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(0);
- info.status_mask = 1ull<<7 /* frmerr */;
- info.enable_addr = CVMX_STXX_INT_MSK(0);
- info.enable_mask = 1ull<<7 /* frmerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<18 /* spx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(0)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SPXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* prtnxa */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<0 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[PRTNXA]: Port out of range\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* abnorm */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<1 /* abnorm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[ABNORM]: Abnormal packet termination (ERR bit)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* spiovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<4 /* spiovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[SPIOVR]: Spi async FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* clserr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<5 /* clserr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[CLSERR]: Spi4 packet closed on non-16B alignment without EOP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* drwnng */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<6 /* drwnng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[DRWNNG]: Spi4 receive FIFO drowning/overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<7 /* rsverr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<7 /* rsverr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[RSVERR]: Spi4 reserved control word detected\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<8 /* tpaovr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<8 /* tpaovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[TPAOVR]: Selected port has hit TPA overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<9 /* diperr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<9 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[DIPERR]: Spi4 DIP4 error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<10 /* syncerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<10 /* syncerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[SYNCERR]: Consecutive Spi4 DIP4 errors have exceeded\n"
- " SPX_ERR_CTL[ERRCNT]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SPXX_INT_REG(1);
- info.status_mask = 1ull<<11 /* calerr */;
- info.enable_addr = CVMX_SPXX_INT_MSK(1);
- info.enable_mask = 1ull<<11 /* calerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SPXX_INT_REG(1)[CALERR]: Spi4 Calendar table parity error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_STXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* calpar0 */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<0 /* calpar0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[CALPAR0]: STX Calendar Table Parity Error Bank0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* calpar1 */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<1 /* calpar1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[CALPAR1]: STX Calendar Table Parity Error Bank1\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<2 /* ovrbst */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<2 /* ovrbst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[OVRBST]: Transmit packet burst too big\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<3 /* datovr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<3 /* datovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[DATOVR]: Spi4 FIFO overflow error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* diperr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<4 /* diperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[DIPERR]: DIP2 error on the Spi4 Status channel\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* nosync */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<5 /* nosync */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[NOSYNC]: ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* unxfrm */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<6 /* unxfrm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[UNXFRM]: Unexpected framing sequence\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_STXX_INT_REG(1);
- info.status_mask = 1ull<<7 /* frmerr */;
- info.enable_addr = CVMX_STXX_INT_MSK(1);
- info.enable_mask = 1ull<<7 /* frmerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<19 /* spx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR STXX_INT_REG(1)[FRMERR]: FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(0);
- info.status_mask = 0xfull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(0);
- info.enable_mask = 0xfull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<22 /* asx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(0)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ASXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<8 /* txpsh */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<8 /* txpsh */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[TXPSH]: TX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<4 /* txpop */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<4 /* txpop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[TXPOP]: TX FIFO underflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ASXX_INT_REG(1);
- info.status_mask = 0xfull<<0 /* ovrflw */;
- info.enable_addr = CVMX_ASXX_INT_EN(1);
- info.enable_mask = 0xfull<<0 /* ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<23 /* asx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ASXX_INT_REG(1)[OVRFLW]: RX FIFO overflow on RMGII port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_MEM_CFG0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<21 /* sec_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<19 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_sec_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " In 128b mode, ecc is calulated on 1 cycle worth of data\n"
- " [21] corresponds to DQ[63:0], Phase0\n"
- " [22] corresponds to DQ[127:64], Phase0\n"
- " [23] corresponds to DQ[63:0], Phase1\n"
- " [24] corresponds to DQ[127:64], Phase1\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [21] corresponds to DQ[63:0], Phase0, cycle0\n"
- " [22] corresponds to DQ[63:0], Phase0, cycle1\n"
- " [23] corresponds to DQ[63:0], Phase1, cycle0\n"
- " [24] corresponds to DQ[63:0], Phase1, cycle1\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_MEM_CFG0(0);
- info.status_mask = 0xfull<<25 /* ded_err */;
- info.enable_addr = CVMX_LMCX_MEM_CFG0(0);
- info.enable_mask = 1ull<<20 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<17 /* lmc */;
- info.func = __cvmx_error_handle_lmcx_mem_cfg0_ded_err;
- info.user_info = (long)
- "ERROR LMCX_MEM_CFG0(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " In 128b mode, ecc is calulated on 1 cycle worth of data\n"
- " [25] corresponds to DQ[63:0], Phase0\n"
- " [26] corresponds to DQ[127:64], Phase0\n"
- " [27] corresponds to DQ[63:0], Phase1\n"
- " [28] corresponds to DQ[127:64], Phase1\n"
- " In 64b mode, ecc is calculated on 2 cycle worth of data\n"
- " [25] corresponds to DQ[63:0], Phase0, cycle0\n"
- " [26] corresponds to DQ[63:0], Phase0, cycle1\n"
- " [27] corresponds to DQ[63:0], Phase1, cycle0\n"
- " [28] corresponds to DQ[63:0], Phase1, cycle1\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<1 /* cp2sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2sbe;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2SBE]: PP-CP2 Single Bit Error Corrected - Status bit\n"
- " When set, a single bit error had been detected and\n"
- " corrected for a PP-generated QW Mode read\n"
- " transaction.\n"
- " If the CP2DBE=0, then the CP2SYN contains the\n"
- " failing syndrome (used during correction).\n"
- " Refer to CP2ECCENA.\n"
- " If the CP2SBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n"
- " NOTE: PP-generated LW Mode Read transactions\n"
- " do not participate in ECC check/correct).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<2 /* cp2dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2dbe;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2DBE]: PP-CP2 Double Bit Error Detected - Status bit\n"
- " When set, a double bit error had been detected\n"
- " for a PP-generated QW Mode read transaction.\n"
- " The CP2SYN contains the failing syndrome.\n"
- " NOTE: PP-generated LW Mode Read transactions\n"
- " do not participate in ECC check/correct).\n"
- " Refer to CP2ECCENA.\n"
- " If the CP2DBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<14 /* dtesbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dtesbe;
- info.user_info = (long)
- "ERROR DFA_ERR[DTESBE]: DTE 29b Single Bit Error Corrected - Status bit\n"
- " When set, a single bit error had been detected and\n"
- " corrected for a DTE-generated 36b SIMPLE Mode read\n"
- " transaction.\n"
- " If the DTEDBE=0, then the DTESYN contains the\n"
- " failing syndrome (used during correction).\n"
- " NOTE: DTE-generated 18b SIMPLE Mode Read\n"
- " transactions do not participate in ECC check/correct).\n"
- " If the DTESBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<15 /* dtedbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dtedbe;
- info.user_info = (long)
- "ERROR DFA_ERR[DTEDBE]: DTE 29b Double Bit Error Detected - Status bit\n"
- " When set, a double bit error had been detected\n"
- " for a DTE-generated 36b SIMPLE Mode read transaction.\n"
- " The DTESYN contains the failing syndrome.\n"
- " If the DTEDBINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n"
- " NOTE: DTE-generated 18b SIMPLE Mode Read transactions\n"
- " do not participate in ECC check/correct).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<26 /* dteperr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dteperr;
- info.user_info = (long)
- "ERROR DFA_ERR[DTEPERR]: DTE Parity Error Detected (for 18b SIMPLE mode ONLY)\n"
- " When set, all DTE-generated 18b SIMPLE Mode read\n"
- " transactions which encounter a parity error (across\n"
- " the 17b of data) are reported.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<29 /* cp2perr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_cp2perr;
- info.user_info = (long)
- "ERROR DFA_ERR[CP2PERR]: PP-CP2 Parity Error Detected - Status bit\n"
- " When set, a parity error had been detected for a\n"
- " PP-generated LW Mode read transaction.\n"
- " If the CP2PINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " See also: DFA_MEMFADR CSR which contains more data\n"
- " about the memory address/control to help isolate\n"
- " the failure.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERR;
- info.status_mask = 1ull<<31 /* dblovf */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_handle_dfa_err_dblovf;
- info.user_info = (long)
- "ERROR DFA_ERR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn61xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn61xx.c
deleted file mode 100644
index 3d488ac..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn61xx.c
+++ /dev/null
@@ -1,9132 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn61xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN61XX</h2>
- * @dot
- * digraph cn61xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<gpio>gpio|<mii>mii|<pcm>pcm"];
- * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
- * cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
- * cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
- * cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
- * cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
- * cvmx_pcm0_int_sum -> cvmx_pcm1_int_sum [style=invis];
- * cvmx_pcm1_int_sum -> cvmx_pcm2_int_sum [style=invis];
- * cvmx_pcm2_int_sum -> cvmx_pcm3_int_sum [style=invis];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1"];
- * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<gmx0>gmx0|<gmx1>gmx1|<mio>mio|<tim>tim|<lmc0>lmc0|<key>key|<fpa>fpa|<iob>iob|<usb>usb|<agl>agl|<zip>zip|<dfa>dfa|<sli>sli|<dpi>dpi"];
- * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
- * cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
- * cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
- * cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
- * cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
- * cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
- * cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
- * cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
- * cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
- * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
- * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
- * cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
- * cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
- * cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
- * cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
- * cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
- * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
- * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
- * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
- * cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<paddr_e>paddr_e"];
- * cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
- * cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
- * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
- * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
- * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
- * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr|<dlc0_ovferr>dlc0_ovferr|<dfanxm>dfanxm|<replerr>replerr"];
- * cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
- * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<m2_up_b0>m2_up_b0|<m2_up_wi>m2_up_wi|<m2_un_b0>m2_un_b0|<m2_un_wi>m2_un_wi|<m3_up_b0>m3_up_b0|<m3_up_wi>m3_up_wi|<m3_un_b0>m3_un_b0|<m3_un_wi>m3_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<sprt2_err>sprt2_err|<sprt3_err>sprt3_err|<ill_pad>ill_pad"];
- * cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
- * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst|<sprt2_rst>sprt2_rst|<sprt3_rst>sprt3_rst"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
- * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
- * cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
- * cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
- * cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
- * cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
- * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
- * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
- * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
- * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
- * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
- * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
- * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
- * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
- * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
- * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
- * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
- * cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn61xx(void);
-
-int cvmx_error_initialize_cn61xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0xffffull<<16 /* gpio */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR CIU_INTX_SUM0(0)[GPIO]: 16 GPIO interrupts\n"
- " When GPIO_MULTI_CAST[EN] == 1\n"
- " Write 1 to clear either the per PP or common GPIO\n"
- " edge-triggered interrupts,depending on mode.\n"
- " See GPIO_MULTI_CAST for all details.\n"
- " When GPIO_MULTI_CAST[EN] == 0\n"
- " Read Only, retain the same behavior as o63.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed | NS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed | NS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed | NS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed | NS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INT_SUM1;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_BLOCK_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_BLOCK_INT;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<0 /* holerd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<0 /* holerd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<1 /* holewr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<1 /* holewr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<2 /* vrtwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<2 /* vrtwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
- " Set when L2C_VRT_MEM blocked a store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<3 /* vrtidrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<3 /* vrtidrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
- " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
- " store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<4 /* vrtadrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<4 /* vrtadrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
- " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
- " store.\n"
- " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<5 /* vrtpe */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<5 /* vrtpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
- " Whenever an L2C_VRT_MEM read finds a parity error,\n"
- " that L2C_VRT_MEM cannot cause stores to be blocked.\n"
- " Software should correct the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<6 /* bigwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<6 /* bigwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<7 /* bigrd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<7 /* bigrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<14 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* se */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
- " (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* up_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* up_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* up_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* un_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* un_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* un_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* rdlk */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* rdlk */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* crs_er */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* crs_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* crs_dr */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* crs_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_DBG_INFO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* se */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<1 /* se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
- " (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<4 /* up_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<4 /* up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<5 /* up_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<5 /* up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* up_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<6 /* up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* un_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<7 /* un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<8 /* un_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<8 /* un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<9 /* un_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<9 /* un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<11 /* rdlk */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<11 /* rdlk */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<12 /* crs_er */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<12 /* crs_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<13 /* crs_dr */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<13 /* crs_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_DBG_INFO(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_RST_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<0 /* rst_link0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<0 /* rst_link0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL0[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<1 /* rst_link1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<1 /* rst_link1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL1[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<8 /* perst0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<8 /* perst0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
- " and MIO_RST_CTL0[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<9 /* perst1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<9 /* perst1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
- " and MIO_RST_CTL1[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<28 /* pool0th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<28 /* pool0th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
- " FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<29 /* pool1th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<29 /* pool1th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
- " FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<30 /* pool2th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<30 /* pool2th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
- " FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<31 /* pool3th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<31 /* pool3th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
- " FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<32 /* pool4th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<32 /* pool4th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
- " FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<33 /* pool5th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<33 /* pool5th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
- " FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<34 /* pool6th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<34 /* pool6th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
- " FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<35 /* pool7th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<35 /* pool7th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
- " FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<36 /* free0 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<36 /* free0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<37 /* free1 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<37 /* free1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<38 /* free2 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<38 /* free2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<39 /* free3 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<39 /* free3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<40 /* free4 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<40 /* free4 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<41 /* free5 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<41 /* free5 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<42 /* free6 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<42 /* free6 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<43 /* free7 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<43 /* free7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<49 /* paddr_e */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<49 /* paddr_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
- " address range for a pool specified by\n"
- " FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_UCTLX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pp_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<0 /* pp_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<1 /* er_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<1 /* er_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<2 /* or_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<2 /* or_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<3 /* cf_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<3 /* cf_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<4 /* wb_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<4 /* wb_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<5 /* wb_pop_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<5 /* wb_pop_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<6 /* oc_ovf_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<6 /* oc_ovf_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
- " When the error happenes, the whole NCB system needs\n"
- " to be reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<7 /* ec_ovf_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<7 /* ec_ovf_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
- " When the error happenes, the whole NCB system needs\n"
- " to be reset.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_BAD_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<32 /* ovrflw */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (RGMII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<33 /* txpop */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (RGMII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<34 /* txpsh */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (RGMII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<35 /* ovrflw1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (RGMII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<36 /* txpop1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (RGMII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<37 /* txpsh1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (RGMII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
- " In RGMII, one bit per port\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_TX_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 0x3ull<<2 /* undflw */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 0x3ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<0 /* dblovf */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<0 /* dblina */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 0x7ull<<1 /* dc0perr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 0x7ull<<1 /* dc0pena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DC0PERR]: Cluster#0 RAM[3:1] Parity Error Detected\n"
- " See also DFA_DTCFADR register which contains the\n"
- " failing addresses for the internal node cache RAMs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<13 /* dlc0_ovferr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<13 /* dlc0_ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DLC0_OVFERR]: DLC0 Fifo Overflow Error Detected\n"
- " This condition should NEVER architecturally occur, and\n"
- " is here in case HW credit/debit scheme is not working.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<17 /* dfanxm */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<17 /* dfanxmena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DFANXM]: DFA Non-existent Memory Access\n"
- " For o68/o61: DTEs (and backdoor CSR DFA Memory REGION reads)\n"
- " have access to the following 38bit L2/DRAM address space\n"
- " which maps to a 37bit physical DDR3 SDRAM address space.\n"
- " see:\n"
- " DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF\n"
- " maps to lower 256MB of physical DDR3 SDRAM\n"
- " DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF\n"
- " maps to upper 127.75GB of DDR3 SDRAM\n"
- " L2/DRAM address space Physical DDR3 SDRAM Address space\n"
- " (38bit address) (37bit address)\n"
- " +-----------+ 0x0020.0FFF.FFFF\n"
- " |\n"
- " === DR1 === +-----------+ 0x001F.FFFF.FFFF\n"
- " (128GB-256MB)| | |\n"
- " | | => | | (128GB-256MB)\n"
- " +-----------+ 0x0000.1FFF.FFFF | DR1\n"
- " 256MB | HOLE | (DO NOT USE) |\n"
- " +-----------+ 0x0000.0FFF.FFFF +-----------+ 0x0000.0FFF.FFFF\n"
- " 256MB | DR0 | | DR0 | (256MB)\n"
- " +-----------+ 0x0000.0000.0000 +-----------+ 0x0000.0000.0000\n"
- " In the event the DFA generates a reference to the L2/DRAM\n"
- " address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to\n"
- " an address above 0x0020.0FFF.FFFF, the DFANXM programmable\n"
- " interrupt bit will be set.\n"
- " SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR\n"
- " accesses to DFA Memory REGION MUST avoid making references\n"
- " to these non-existent memory regions.\n"
- " NOTE: If DFANXM is set during a DFA Graph Walk operation,\n"
- " then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
- " If DFANXM is set during a NCB-Direct CSR read access to DFA\n"
- " Memory REGION, then the CSR read response data is forced to\n"
- " 128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW\n"
- " being accessed, either the upper or lower QW will be returned).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<18 /* replerr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<18 /* replerrena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[REPLERR]: DFA Illegal Replication Factor Error\n"
- " For o68: DFA only supports 1x, 2x, and 4x port replication.\n"
- " Legal configurations for memory are to support 2 port or\n"
- " 4 port configurations.\n"
- " The REPLERR interrupt will be set in the following illegal\n"
- " configuration cases:\n"
- " 1) An 8x replication factor is detected for any memory reference.\n"
- " 2) A 4x replication factor is detected for any memory reference\n"
- " when only 2 memory ports are enabled.\n"
- " NOTE: If REPLERR is set during a DFA Graph Walk operation,\n"
- " then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
- " If REPLERR is set during a NCB-Direct CSR read access to DFA\n"
- " Memory REGION, then the CSR read response data is UNPREDICTABLE.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_SLI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<0 /* rml_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
- " within 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<1 /* reserved_1_1 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<1 /* reserved_1_1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<8 /* m0_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<8 /* m0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<9 /* m0_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<9 /* m0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<10 /* m0_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<10 /* m0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<11 /* m0_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<11 /* m0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<12 /* m1_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<12 /* m1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<13 /* m1_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<13 /* m1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<14 /* m1_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<14 /* m1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<15 /* m1_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<15 /* m1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<20 /* m2_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<20 /* m2_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UP_B0]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<21 /* m2_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<21 /* m2_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UP_WI]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<22 /* m2_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<22 /* m2_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UN_B0]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<23 /* m2_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<23 /* m2_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UN_WI]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<24 /* m3_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<24 /* m3_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UP_B0]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<25 /* m3_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<25 /* m3_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UP_WI]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<26 /* m3_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<26 /* m3_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UN_B0]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<27 /* m3_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<27 /* m3_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UN_WI]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<48 /* pidbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<48 /* pidbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<49 /* psldbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<49 /* psldbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<50 /* pout_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<50 /* pout_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
- " set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<51 /* pin_bp */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<51 /* pin_bp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
- " See SLI_PKT_IN_BP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<52 /* pgl_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<52 /* pgl_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
- " read this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<53 /* pdi_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<53 /* pdi_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<54 /* pop_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<54 /* pop_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
- " pointer pair this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<55 /* pins_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<55 /* pins_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<56 /* sprt0_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<56 /* sprt0_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<57 /* sprt1_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<57 /* sprt1_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<58 /* sprt2_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<58 /* sprt2_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT2_ERR]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<59 /* sprt3_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<59 /* sprt3_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT3_ERR]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<60 /* ill_pad */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<60 /* ill_pad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
- " range of the Packet-CSR, but for an unused\n"
- " address.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<0 /* nderr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<0 /* nderr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
- " DPI received a NCB transaction on the outbound\n"
- " bus to the DPI deviceID, but the command was not\n"
- " recognized.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<1 /* nfovr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<1 /* nfovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
- " DPI can store upto 16 CSR request. The FIFO will\n"
- " overflow if that number is exceeded.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 0xffull<<8 /* dmadbo */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 0xffull<<8 /* dmadbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
- " DPI has a 32-bit counter for each request's queue\n"
- " outstanding doorbell counts. Interrupt will fire\n"
- " if the count overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<16 /* req_badadr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<16 /* req_badadr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch to the NULL pointer.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<17 /* req_badlen */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<17 /* req_badlen */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch with length of zero.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<18 /* req_ovrflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<18 /* req_ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<19 /* req_undflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<19 /* req_undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO underflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<20 /* req_anull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<20 /* req_anull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
- " Fetched instruction word was 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<21 /* req_inull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<21 /* req_inull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
- " Next pointer was NULL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<22 /* req_badfil */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<22 /* req_badfil */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
- " Instruction fill when none outstanding.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<24 /* sprt0_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<24 /* sprt0_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<25 /* sprt1_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<25 /* sprt1_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<26 /* sprt2_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<26 /* sprt2_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT2_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<27 /* sprt3_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<27 /* sprt3_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT3_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_PKT_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_PKT_ERR_RSP;
- info.status_mask = 1ull<<0 /* pkterr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
- " the I/O subsystem.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RSP;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
- " ErrorResponse from the I/O subsystem.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RST */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RST;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
- " instruction because the source or destination\n"
- " was in reset.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c
deleted file mode 100644
index b019ac0..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c
+++ /dev/null
@@ -1,7265 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn63xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN63XX</h2>
- * @dot
- * digraph cn63xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
- * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
- * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
- * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
- * cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"];
- * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
- * cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
- * cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
- * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
- * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
- * cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
- * cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
- * cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
- * cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
- * cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7"];
- * cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
- * cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
- * cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
- * cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
- * cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
- * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
- * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
- * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
- * cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
- * cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
- * cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
- * cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
- * cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"];
- * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"];
- * cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
- * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
- * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
- * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
- * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
- * cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
- * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
- * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
- * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
- * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
- * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
- * cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn63xx(void);
-
-int cvmx_error_initialize_cn63xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INT_SUM1;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NDF_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<2 /* wdog */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<2 /* wdog */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<3 /* sm_bad */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<3 /* sm_bad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<4 /* ecc_1bit */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<4 /* ecc_1bit */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<5 /* ecc_mult */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<5 /* ecc_mult */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<6 /* ovrf */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<6 /* ovrf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
- " fatal error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_BLOCK_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_BLOCK_INT;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<0 /* holerd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<0 /* holerd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<1 /* holewr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<1 /* holewr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<2 /* vrtwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<2 /* vrtwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
- " Set when L2C_VRT_MEM blocked a store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<3 /* vrtidrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<3 /* vrtidrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
- " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
- " store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<4 /* vrtadrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<4 /* vrtadrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
- " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
- " store.\n"
- " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<5 /* vrtpe */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<5 /* vrtpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
- " Whenever an L2C_VRT_MEM read finds a parity error,\n"
- " that L2C_VRT_MEM cannot cause stores to be blocked.\n"
- " Software should correct the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<6 /* bigwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<6 /* bigwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<7 /* bigrd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<7 /* bigrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<14 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* se */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
- " (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* up_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* up_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* up_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* un_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* un_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* un_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* rdlk */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* rdlk */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* crs_er */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* crs_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* crs_dr */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* crs_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_DBG_INFO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* se */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<1 /* se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
- " (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<4 /* up_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<4 /* up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<5 /* up_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<5 /* up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* up_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<6 /* up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* un_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<7 /* un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<8 /* un_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<8 /* un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<9 /* un_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<9 /* un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<11 /* rdlk */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<11 /* rdlk */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<12 /* crs_er */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<12 /* crs_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<13 /* crs_dr */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<13 /* crs_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_DBG_INFO(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<28 /* pool0th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<28 /* pool0th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
- " FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<29 /* pool1th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<29 /* pool1th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
- " FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<30 /* pool2th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<30 /* pool2th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
- " FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<31 /* pool3th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<31 /* pool3th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
- " FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<32 /* pool4th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<32 /* pool4th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
- " FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<33 /* pool5th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<33 /* pool5th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
- " FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<34 /* pool6th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<34 /* pool6th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
- " FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<35 /* pool7th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<35 /* pool7th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
- " FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<36 /* free0 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<36 /* free0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<37 /* free1 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<37 /* free1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<38 /* free2 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<38 /* free2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<39 /* free3 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<39 /* free3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<40 /* free4 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<40 /* free4 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<41 /* free5 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<41 /* free5 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<42 /* free6 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<42 /* free6 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<43 /* free7 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<43 /* free7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_UCTLX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pp_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<0 /* pp_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<1 /* er_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<1 /* er_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<2 /* or_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<2 /* or_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<3 /* cf_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<3 /* cf_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<4 /* wb_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<4 /* wb_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<5 /* wb_pop_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<5 /* wb_pop_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<6 /* oc_ovf_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<6 /* oc_ovf_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
- " When the error happenes, the whole NCB system needs\n"
- " to be reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<7 /* ec_ovf_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<7 /* ec_ovf_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
- " When the error happenes, the whole NCB system needs\n"
- " to be reset.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_RST_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<0 /* rst_link0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<0 /* rst_link0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL0[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<1 /* rst_link1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<1 /* rst_link1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL1[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<8 /* perst0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<8 /* perst0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
- " and MIO_RST_CTL0[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<9 /* perst1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<9 /* perst1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
- " and MIO_RST_CTL1[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFM_FNT_STAT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFM_FNT_STAT;
- info.status_mask = 1ull<<0 /* sbe_err */;
- info.enable_addr = CVMX_DFM_FNT_IENA;
- info.enable_mask = 1ull<<0 /* sbe_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_DFM;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<40 /* dfm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n"
- " Memory Read.\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFM_FNT_STAT;
- info.status_mask = 1ull<<1 /* dbe_err */;
- info.enable_addr = CVMX_DFM_FNT_IENA;
- info.enable_mask = 1ull<<1 /* dbe_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_DFM;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<40 /* dfm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n"
- " Memory Read.\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_BAD_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<32 /* ovrflw */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<33 /* txpop */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<34 /* txpsh */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<35 /* ovrflw1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<36 /* txpop1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<37 /* txpsh1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
- " In MII/RGMII, one bit per port\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_TX_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 0x3ull<<2 /* undflw */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 0x3ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<0 /* dblovf */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<0 /* dblina */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 0x7ull<<1 /* dc0perr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 0x7ull<<1 /* dc0pena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n"
- " See also DFA_DTCFADR register which contains the\n"
- " failing addresses for the internal node cache RAMs.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SRIOX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<4 /* bar_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<4 /* bar_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<5 /* deny_wr */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<5 /* deny_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<6 /* sli_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<6 /* sli_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
- " See SRIO(0..1)_INT_INFO[1:0]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<9 /* mce_rx */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<9 /* mce_rx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<12 /* log_erb */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<12 /* log_erb */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
- " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<13 /* phy_erb */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<13 /* phy_erb */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n"
- " See SRIOMAINT*_ERB_ATTR_CAPT\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<18 /* omsg_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<18 /* omsg_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
- " See SRIO(0..1)_INT_INFO2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<19 /* pko_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<19 /* pko_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<20 /* rtry_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<20 /* rtry_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
- " See SRIO(0..1)_INT_INFO3\n"
- " When one or more of the segments in an outgoing\n"
- " message have a RTRY_ERR, SRIO will not set\n"
- " OMSG* after the message \"transfer\".\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<21 /* f_error */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<21 /* f_error */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<22 /* mac_buf */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<22 /* mac_buf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[MAC_BUF]: SRIO MAC Buffer CRC Error (Pass 2)\n"
- " See SRIO(0..1)_MAC_BUFFERS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<23 /* degrad */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<23 /* degrade */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[DEGRAD]: ERB Error Rate reached Degrade Count (Pass 2)\n"
- " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<24 /* fail */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<24 /* fail */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[FAIL]: ERB Error Rate reached Fail Count (Pass 2)\n"
- " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<25 /* ttl_tout */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<25 /* ttl_tout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[TTL_TOUT]: Outgoing Packet Time to Live Timeout (Pass 2)\n"
- " See SRIOMAINT(0..1)_DROP_PACKET\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<26 /* zero_pkt */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<26 /* zero_pkt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[ZERO_PKT]: Received Incoming SRIO Zero byte packet (Pass 2)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SRIOX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<4 /* bar_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<4 /* bar_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<5 /* deny_wr */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<5 /* deny_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<6 /* sli_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<6 /* sli_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
- " See SRIO(0..1)_INT_INFO[1:0]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<9 /* mce_rx */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<9 /* mce_rx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[MCE_RX]: Incoming Multicast Event Symbol\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<12 /* log_erb */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<12 /* log_erb */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
- " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<13 /* phy_erb */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<13 /* phy_erb */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[PHY_ERB]: Physical Layer Error detected in ERB\n"
- " See SRIOMAINT*_ERB_ATTR_CAPT\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<18 /* omsg_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<18 /* omsg_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
- " See SRIO(0..1)_INT_INFO2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<19 /* pko_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<19 /* pko_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[PKO_ERR]: Outbound Message Received PKO Error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<20 /* rtry_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<20 /* rtry_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
- " See SRIO(0..1)_INT_INFO3\n"
- " When one or more of the segments in an outgoing\n"
- " message have a RTRY_ERR, SRIO will not set\n"
- " OMSG* after the message \"transfer\".\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<21 /* f_error */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<21 /* f_error */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<22 /* mac_buf */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<22 /* mac_buf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[MAC_BUF]: SRIO MAC Buffer CRC Error (Pass 2)\n"
- " See SRIO(0..1)_MAC_BUFFERS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<23 /* degrad */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<23 /* degrade */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[DEGRAD]: ERB Error Rate reached Degrade Count (Pass 2)\n"
- " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<24 /* fail */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<24 /* fail */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[FAIL]: ERB Error Rate reached Fail Count (Pass 2)\n"
- " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<25 /* ttl_tout */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<25 /* ttl_tout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[TTL_TOUT]: Outgoing Packet Time to Live Timeout (Pass 2)\n"
- " See SRIOMAINT(0..1)_DROP_PACKET\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<26 /* zero_pkt */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<26 /* zero_pkt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[ZERO_PKT]: Received Incoming SRIO Zero byte packet (Pass 2)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_SLI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<0 /* rml_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
- " within 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<1 /* reserved_1_1 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<1 /* reserved_1_1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<8 /* m0_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<8 /* m0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<9 /* m0_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<9 /* m0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<10 /* m0_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<10 /* m0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<11 /* m0_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<11 /* m0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<12 /* m1_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<12 /* m1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<13 /* m1_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<13 /* m1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<14 /* m1_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<14 /* m1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<15 /* m1_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<15 /* m1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<48 /* pidbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<48 /* pidbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<49 /* psldbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<49 /* psldbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<50 /* pout_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<50 /* pout_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
- " set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<51 /* pin_bp */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<51 /* pin_bp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
- " See SLI_PKT_IN_BP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<52 /* pgl_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<52 /* pgl_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
- " read this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<53 /* pdi_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<53 /* pdi_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<54 /* pop_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<54 /* pop_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
- " pointer pair this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<55 /* pins_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<55 /* pins_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<56 /* sprt0_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<56 /* sprt0_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<57 /* sprt1_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<57 /* sprt1_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<60 /* ill_pad */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<60 /* ill_pad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
- " range of the Packet-CSR, but for an unused\n"
- " address.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<0 /* nderr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<0 /* nderr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
- " DPI received a NCB transaction on the outbound\n"
- " bus to the DPI deviceID, but the command was not\n"
- " recognized.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<1 /* nfovr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<1 /* nfovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
- " DPI can store upto 16 CSR request. The FIFO will\n"
- " overflow if that number is exceeded.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 0xffull<<8 /* dmadbo */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 0xffull<<8 /* dmadbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
- " DPI has a 32-bit counter for each request's queue\n"
- " outstanding doorbell counts. Interrupt will fire\n"
- " if the count overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<16 /* req_badadr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<16 /* req_badadr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch to the NULL pointer.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<17 /* req_badlen */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<17 /* req_badlen */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch with length of zero.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<18 /* req_ovrflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<18 /* req_ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<19 /* req_undflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<19 /* req_undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO underflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<20 /* req_anull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<20 /* req_anull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
- " Fetched instruction word was 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<21 /* req_inull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<21 /* req_inull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
- " Next pointer was NULL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<22 /* req_badfil */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<22 /* req_badfil */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
- " Instruction fill when none outstanding.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<24 /* sprt0_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<24 /* sprt0_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<25 /* sprt1_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<25 /* sprt1_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_PKT_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_PKT_ERR_RSP;
- info.status_mask = 1ull<<0 /* pkterr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
- " the I/O subsystem.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RSP;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
- " ErrorResponse from the I/O subsystem.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RST */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RST;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
- " instruction because the source or destination\n"
- " was in reset.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c
deleted file mode 100644
index 092669e..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn63xxp1.c
+++ /dev/null
@@ -1,6761 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn63xxp1.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN63XXP1</h2>
- * @dot
- * digraph cn63xxp1
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
- * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
- * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
- * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
- * cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"];
- * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<tad0>tad0"];
- * cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
- * cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
- * cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
- * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
- * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
- * cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
- * cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
- * cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
- * cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
- * cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
- * cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
- * cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
- * cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
- * cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
- * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
- * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
- * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
- * cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
- * cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error"];
- * cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
- * cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error"];
- * cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"];
- * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"];
- * cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
- * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
- * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
- * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
- * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
- * cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
- * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
- * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
- * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
- * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
- * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
- * cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn63xxp1(void);
-
-int cvmx_error_initialize_cn63xxp1(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INT_SUM1;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NDF_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<2 /* wdog */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<2 /* wdog */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<3 /* sm_bad */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<3 /* sm_bad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<4 /* ecc_1bit */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<4 /* ecc_1bit */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<5 /* ecc_mult */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<5 /* ecc_mult */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<6 /* ovrf */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<6 /* ovrf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
- " fatal error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_BLOCK_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_BLOCK_INT;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<0 /* holerd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<0 /* holerd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<1 /* holewr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<1 /* holewr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<2 /* vrtwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<2 /* vrtwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
- " Set when L2C_VRT_MEM blocked a store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<3 /* vrtidrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<3 /* vrtidrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
- " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
- " store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<4 /* vrtadrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<4 /* vrtadrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
- " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
- " store.\n"
- " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<5 /* vrtpe */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<5 /* vrtpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
- " Whenever an L2C_VRT_MEM read finds a parity error,\n"
- " that L2C_VRT_MEM cannot cause stores to be blocked.\n"
- " Software should correct the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<14 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* se */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
- " (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* up_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* up_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* up_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* un_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* un_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* un_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* rdlk */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* rdlk */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* crs_er */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* crs_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* crs_dr */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* crs_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_DBG_INFO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* se */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<1 /* se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
- " (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<4 /* up_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<4 /* up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<5 /* up_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<5 /* up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* up_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<6 /* up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* un_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<7 /* un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<8 /* un_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<8 /* un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<9 /* un_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<9 /* un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<11 /* rdlk */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<11 /* rdlk */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<12 /* crs_er */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<12 /* crs_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<13 /* crs_dr */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<13 /* crs_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_DBG_INFO(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_UCTLX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pp_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<0 /* pp_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<1 /* er_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<1 /* er_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<2 /* or_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<2 /* or_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<3 /* cf_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<3 /* cf_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<4 /* wb_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<4 /* wb_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<5 /* wb_pop_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<5 /* wb_pop_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<6 /* oc_ovf_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<6 /* oc_ovf_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
- " When the error happenes, the whole NCB system needs\n"
- " to be reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<7 /* ec_ovf_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<7 /* ec_ovf_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
- " When the error happenes, the whole NCB system needs\n"
- " to be reset.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_RST_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<0 /* rst_link0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<0 /* rst_link0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL0[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<1 /* rst_link1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<1 /* rst_link1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL1[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<8 /* perst0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<8 /* perst0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
- " and MIO_RST_CTL0[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<9 /* perst1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<9 /* perst1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
- " and MIO_RST_CTL1[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFM_FNT_STAT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFM_FNT_STAT;
- info.status_mask = 1ull<<0 /* sbe_err */;
- info.enable_addr = CVMX_DFM_FNT_IENA;
- info.enable_mask = 1ull<<0 /* sbe_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_DFM;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<40 /* dfm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n"
- " Memory Read.\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFM_FNT_STAT;
- info.status_mask = 1ull<<1 /* dbe_err */;
- info.enable_addr = CVMX_DFM_FNT_IENA;
- info.enable_mask = 1ull<<1 /* dbe_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_DFM;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<40 /* dfm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n"
- " Memory Read.\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_BAD_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<32 /* ovrflw */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<33 /* txpop */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<34 /* txpsh */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<35 /* ovrflw1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<36 /* txpop1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<37 /* txpsh1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
- " In MII/RGMII, one bit per port\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_TX_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 0x3ull<<2 /* undflw */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 0x3ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<0 /* dblovf */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<0 /* dblina */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 0x7ull<<1 /* dc0perr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 0x7ull<<1 /* dc0pena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n"
- " See also DFA_DTCFADR register which contains the\n"
- " failing addresses for the internal node cache RAMs.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SRIOX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<4 /* bar_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<4 /* bar_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<5 /* deny_wr */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<5 /* deny_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<6 /* sli_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<6 /* sli_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
- " See SRIO(0..1)_INT_INFO[1:0]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<9 /* mce_rx */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<9 /* mce_rx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<12 /* log_erb */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<12 /* log_erb */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
- " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<13 /* phy_erb */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<13 /* phy_erb */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n"
- " See SRIOMAINT*_ERB_ATTR_CAPT\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<18 /* omsg_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<18 /* omsg_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
- " See SRIO(0..1)_INT_INFO2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<19 /* pko_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<19 /* pko_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<20 /* rtry_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<20 /* rtry_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
- " See SRIO(0..1)_INT_INFO3\n"
- " When one or more of the segments in an outgoing\n"
- " message have a RTRY_ERR, SRIO will not set\n"
- " OMSG* after the message \"transfer\".\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<21 /* f_error */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<21 /* f_error */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SRIOX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<4 /* bar_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<4 /* bar_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<5 /* deny_wr */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<5 /* deny_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<6 /* sli_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<6 /* sli_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
- " See SRIO(0..1)_INT_INFO[1:0]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<9 /* mce_rx */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<9 /* mce_rx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[MCE_RX]: Incoming Multicast Event Symbol\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<12 /* log_erb */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<12 /* log_erb */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
- " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<13 /* phy_erb */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<13 /* phy_erb */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[PHY_ERB]: Physical Layer Error detected in ERB\n"
- " See SRIOMAINT*_ERB_ATTR_CAPT\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<18 /* omsg_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<18 /* omsg_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
- " See SRIO(0..1)_INT_INFO2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<19 /* pko_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<19 /* pko_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[PKO_ERR]: Outbound Message Received PKO Error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<20 /* rtry_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<20 /* rtry_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
- " See SRIO(0..1)_INT_INFO3\n"
- " When one or more of the segments in an outgoing\n"
- " message have a RTRY_ERR, SRIO will not set\n"
- " OMSG* after the message \"transfer\".\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(1);
- info.status_mask = 1ull<<21 /* f_error */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
- info.enable_mask = 1ull<<21 /* f_error */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<33 /* srio1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(1)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_SLI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<0 /* rml_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
- " within 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<1 /* reserved_1_1 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<1 /* reserved_1_1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<8 /* m0_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<8 /* m0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<9 /* m0_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<9 /* m0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<10 /* m0_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<10 /* m0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<11 /* m0_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<11 /* m0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<12 /* m1_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<12 /* m1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<13 /* m1_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<13 /* m1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<14 /* m1_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<14 /* m1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<15 /* m1_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<15 /* m1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<48 /* pidbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<48 /* pidbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<49 /* psldbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<49 /* psldbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<50 /* pout_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<50 /* pout_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
- " set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<51 /* pin_bp */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<51 /* pin_bp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
- " See SLI_PKT_IN_BP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<52 /* pgl_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<52 /* pgl_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
- " read this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<53 /* pdi_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<53 /* pdi_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<54 /* pop_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<54 /* pop_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
- " pointer pair this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<55 /* pins_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<55 /* pins_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<56 /* sprt0_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<56 /* sprt0_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<57 /* sprt1_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<57 /* sprt1_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<60 /* ill_pad */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<60 /* ill_pad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
- " range of the Packet-CSR, but for an unused\n"
- " address.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<0 /* nderr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<0 /* nderr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
- " DPI received a NCB transaction on the outbound\n"
- " bus to the DPI deviceID, but the command was not\n"
- " recognized.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<1 /* nfovr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<1 /* nfovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
- " DPI can store upto 16 CSR request. The FIFO will\n"
- " overflow if that number is exceeded.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 0xffull<<8 /* dmadbo */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 0xffull<<8 /* dmadbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
- " DPI has a 32-bit counter for each request's queue\n"
- " outstanding doorbell counts. Interrupt will fire\n"
- " if the count overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<16 /* req_badadr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<16 /* req_badadr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch to the NULL pointer.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<17 /* req_badlen */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<17 /* req_badlen */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch with length of zero.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<18 /* req_ovrflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<18 /* req_ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<19 /* req_undflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<19 /* req_undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO underflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<20 /* req_anull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<20 /* req_anull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
- " Fetched instruction word was 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<21 /* req_inull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<21 /* req_inull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
- " Next pointer was NULL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<22 /* req_badfil */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<22 /* req_badfil */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
- " Instruction fill when none outstanding.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<24 /* sprt0_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<24 /* sprt0_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<25 /* sprt1_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<25 /* sprt1_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_PKT_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_PKT_ERR_RSP;
- info.status_mask = 1ull<<0 /* pkterr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
- " the I/O subsystem.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RSP;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
- " ErrorResponse from the I/O subsystem.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RST */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RST;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
- " instruction because the source or destination\n"
- " was in reset.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn66xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn66xx.c
deleted file mode 100644
index b8efcf5..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn66xx.c
+++ /dev/null
@@ -1,9166 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn66xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN66XX</h2>
- * @dot
- * digraph cn66xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
- * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
- * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
- * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
- * cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<gmx1>gmx1|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<usb>usb|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<sli>sli|<dpi>dpi"];
- * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
- * cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
- * cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
- * cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
- * cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
- * cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
- * cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
- * cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
- * cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
- * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
- * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
- * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
- * cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
- * cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
- * cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
- * cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
- * cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<paddr_e>paddr_e"];
- * cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
- * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
- * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
- * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<rst_link2>rst_link2|<rst_link3>rst_link3|<perst0>perst0|<perst1>perst1"];
- * cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
- * cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
- * cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
- * cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
- * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
- * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
- * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
- * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
- * cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
- * cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
- * cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
- * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<m2_up_b0>m2_up_b0|<m2_up_wi>m2_up_wi|<m2_un_b0>m2_un_b0|<m2_un_wi>m2_un_wi|<m3_up_b0>m3_up_b0|<m3_up_wi>m3_up_wi|<m3_un_b0>m3_un_b0|<m3_un_wi>m3_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<sprt2_err>sprt2_err|<sprt3_err>sprt3_err|<ill_pad>ill_pad"];
- * cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
- * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst|<sprt2_rst>sprt2_rst|<sprt3_rst>sprt3_rst"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
- * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
- * cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
- * cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
- * cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
- * cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
- * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
- * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
- * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
- * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
- * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
- * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
- * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
- * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
- * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
- * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
- * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
- * cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn66xx(void);
-
-int cvmx_error_initialize_cn66xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<62 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INT_SUM1;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
- " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU_INTx_SUM0,4[MII] bits are set.\n"
- " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(1);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(1);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<18 /* mii1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NDF_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<2 /* wdog */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<2 /* wdog */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<3 /* sm_bad */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<3 /* sm_bad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<4 /* ecc_1bit */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<4 /* ecc_1bit */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<5 /* ecc_mult */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<5 /* ecc_mult */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<6 /* ovrf */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<6 /* ovrf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INT_SUM1;
- info.parent.status_mask = 1ull<<19 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
- " fatal error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_BLOCK_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_BLOCK_INT;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<0 /* holerd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<0 /* holerd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<1 /* holewr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<1 /* holewr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<2 /* vrtwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<2 /* vrtwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
- " Set when L2C_VRT_MEM blocked a store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<3 /* vrtidrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<3 /* vrtidrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
- " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
- " store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<4 /* vrtadrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<4 /* vrtadrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
- " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
- " store.\n"
- " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<5 /* vrtpe */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<5 /* vrtpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
- " Whenever an L2C_VRT_MEM read finds a parity error,\n"
- " that L2C_VRT_MEM cannot cause stores to be blocked.\n"
- " Software should correct the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<6 /* bigwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<6 /* bigwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<7 /* bigrd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<7 /* bigrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<14 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,1);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,1);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,1)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,1);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,1);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,1)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,1);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,1);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,1)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* se */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
- " (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* up_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* up_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* up_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* un_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* un_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* un_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* rdlk */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* rdlk */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* crs_er */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* crs_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* crs_dr */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* crs_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_DBG_INFO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* se */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<1 /* se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
- " (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<4 /* up_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<4 /* up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<5 /* up_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<5 /* up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* up_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<6 /* up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* un_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<7 /* un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<8 /* un_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<8 /* un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<9 /* un_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<9 /* un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<11 /* rdlk */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<11 /* rdlk */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<12 /* crs_er */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<12 /* crs_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<13 /* crs_dr */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<13 /* crs_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_DBG_INFO(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<28 /* pool0th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<28 /* pool0th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
- " FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<29 /* pool1th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<29 /* pool1th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
- " FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<30 /* pool2th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<30 /* pool2th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
- " FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<31 /* pool3th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<31 /* pool3th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
- " FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<32 /* pool4th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<32 /* pool4th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
- " FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<33 /* pool5th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<33 /* pool5th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
- " FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<34 /* pool6th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<34 /* pool6th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
- " FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<35 /* pool7th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<35 /* pool7th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
- " FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<36 /* free0 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<36 /* free0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<37 /* free1 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<37 /* free1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<38 /* free2 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<38 /* free2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<39 /* free3 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<39 /* free3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<40 /* free4 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<40 /* free4 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<41 /* free5 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<41 /* free5 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<42 /* free6 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<42 /* free6 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<43 /* free7 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<43 /* free7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<49 /* paddr_e */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<49 /* paddr_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
- " address range for a pool specified by\n"
- " FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(1);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 17;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 18;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 19;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 16;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<2 /* gmx1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_RST_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<0 /* rst_link0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<0 /* rst_link0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
- " MIO_RST_CNTL0[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<1 /* rst_link1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<1 /* rst_link1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
- " MIO_RST_CNTL1[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<2 /* rst_link2 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<2 /* rst_link2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK2]: A controller2 link-down/hot-reset occurred while\n"
- " MIO_RST_CNTL2[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST2[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<3 /* rst_link3 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<3 /* rst_link3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK3]: A controller3 link-down/hot-reset occurred while\n"
- " MIO_RST_CNTL3[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST3[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<8 /* perst0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<8 /* perst0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CNTL0[RST_RCV]=1\n"
- " and MIO_RST_CNTL0[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<9 /* perst1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<9 /* perst1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CNTL1[RST_RCV]=1\n"
- " and MIO_RST_CNTL1[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFM_FNT_STAT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFM_FNT_STAT;
- info.status_mask = 1ull<<0 /* sbe_err */;
- info.enable_addr = CVMX_DFM_FNT_IENA;
- info.enable_mask = 1ull<<0 /* sbe_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_DFM;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<40 /* dfm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n"
- " Memory Read.\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFM_FNT_STAT;
- info.status_mask = 1ull<<1 /* dbe_err */;
- info.enable_addr = CVMX_DFM_FNT_IENA;
- info.enable_mask = 1ull<<1 /* dbe_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_DFM;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<40 /* dfm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n"
- " Memory Read.\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_UCTLX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pp_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<0 /* pp_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<1 /* er_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<1 /* er_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<2 /* or_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<2 /* or_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<3 /* cf_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<3 /* cf_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<4 /* wb_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<4 /* wb_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<5 /* wb_pop_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<5 /* wb_pop_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<6 /* oc_ovf_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<6 /* oc_ovf_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
- " When the error happenes, the whole NCB system needs\n"
- " to be reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<7 /* ec_ovf_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<7 /* ec_ovf_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
- " When the error happenes, the whole NCB system needs\n"
- " to be reset.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_BAD_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<32 /* ovrflw */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<33 /* txpop */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<34 /* txpsh */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<35 /* ovrflw1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<36 /* txpop1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<37 /* txpsh1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
- " In MII/RGMII, one bit per port\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_TX_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 0x3ull<<2 /* undflw */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 0x3ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<28 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<7 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<0 /* dblovf */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<0 /* dblina */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 0x7ull<<1 /* dc0perr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 0x7ull<<1 /* dc0pena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<6 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n"
- " See also DFA_DTCFADR register which contains the\n"
- " failing addresses for the internal node cache RAMs.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SRIOX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<4 /* bar_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<4 /* bar_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<5 /* deny_wr */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<5 /* deny_wr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<6 /* sli_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<6 /* sli_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
- " See SRIO(0,2..3)_INT_INFO[1:0]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<9 /* mce_rx */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<9 /* mce_rx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<12 /* log_erb */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<12 /* log_erb */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
- " See SRIOMAINT(0,2..3)_ERB_LT_ERR_DET\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<13 /* phy_erb */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<13 /* phy_erb */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n"
- " See SRIOMAINT*_ERB_ATTR_CAPT\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<18 /* omsg_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<18 /* omsg_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
- " See SRIO(0,2..3)_INT_INFO2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<19 /* pko_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<19 /* pko_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<20 /* rtry_err */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<20 /* rtry_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
- " See SRIO(0,2..3)_INT_INFO3\n"
- " When one or more of the segments in an outgoing\n"
- " message have a RTRY_ERR, SRIO will not set\n"
- " OMSG* after the message \"transfer\".\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<21 /* f_error */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<21 /* f_error */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<22 /* mac_buf */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<22 /* mac_buf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[MAC_BUF]: SRIO MAC Buffer CRC Error\n"
- " See SRIO(0,2..3)_MAC_BUFFERS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<23 /* degrad */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<23 /* degrade */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[DEGRAD]: ERB Error Rate reached Degrade Count\n"
- " See SRIOMAINT(0,2..3)_ERB_ERR_RATE\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<24 /* fail */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<24 /* fail */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[FAIL]: ERB Error Rate reached Fail Count\n"
- " See SRIOMAINT(0,2..3)_ERB_ERR_RATE\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<25 /* ttl_tout */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<25 /* ttl_tout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[TTL_TOUT]: Outgoing Packet Time to Live Timeout\n"
- " See SRIOMAINT(0,2..3)_DROP_PACKET\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SRIOX_INT_REG(0);
- info.status_mask = 1ull<<26 /* zero_pkt */;
- info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
- info.enable_mask = 1ull<<26 /* zero_pkt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_SRIO;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<32 /* srio0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SRIOX_INT_REG(0)[ZERO_PKT]: Received Incoming SRIO Zero byte packet\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_SLI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<0 /* rml_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
- " within 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<1 /* reserved_1_1 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<1 /* reserved_1_1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<8 /* m0_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<8 /* m0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<9 /* m0_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<9 /* m0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<10 /* m0_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<10 /* m0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<11 /* m0_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<11 /* m0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<12 /* m1_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<12 /* m1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<13 /* m1_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<13 /* m1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<14 /* m1_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<14 /* m1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<15 /* m1_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<15 /* m1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<20 /* m2_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<20 /* m2_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 2.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<21 /* m2_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<21 /* m2_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 2. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<22 /* m2_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<22 /* m2_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 2.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<23 /* m2_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<23 /* m2_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 2. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<24 /* m3_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<24 /* m3_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 3.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<25 /* m3_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<25 /* m3_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 3. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<26 /* m3_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<26 /* m3_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 3.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<27 /* m3_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<27 /* m3_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 3. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<48 /* pidbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<48 /* pidbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<49 /* psldbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<49 /* psldbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<50 /* pout_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<50 /* pout_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
- " set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<51 /* pin_bp */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<51 /* pin_bp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
- " See SLI_PKT_IN_BP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<52 /* pgl_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<52 /* pgl_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
- " read this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<53 /* pdi_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<53 /* pdi_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<54 /* pop_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<54 /* pop_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
- " pointer pair this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<55 /* pins_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<55 /* pins_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<56 /* sprt0_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<56 /* sprt0_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<57 /* sprt1_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<57 /* sprt1_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<58 /* sprt2_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<58 /* sprt2_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT2_ERR]: When an error response received on SLI port 2\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<59 /* sprt3_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<59 /* sprt3_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT3_ERR]: When an error response received on SLI port 3\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<60 /* ill_pad */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<60 /* ill_pad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
- " range of the Packet-CSR, but for an unused\n"
- " address.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<0 /* nderr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<0 /* nderr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
- " DPI received a NCB transaction on the outbound\n"
- " bus to the DPI deviceID, but the command was not\n"
- " recognized.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<1 /* nfovr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<1 /* nfovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
- " DPI can store upto 16 CSR request. The FIFO will\n"
- " overflow if that number is exceeded.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 0xffull<<8 /* dmadbo */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 0xffull<<8 /* dmadbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
- " DPI has a 32-bit counter for each request's queue\n"
- " outstanding doorbell counts. Interrupt will fire\n"
- " if the count overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<16 /* req_badadr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<16 /* req_badadr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch to the NULL pointer.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<17 /* req_badlen */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<17 /* req_badlen */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch with length of zero.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<18 /* req_ovrflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<18 /* req_ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<19 /* req_undflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<19 /* req_undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO underflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<20 /* req_anull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<20 /* req_anull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
- " Fetched instruction word was 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<21 /* req_inull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<21 /* req_inull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
- " Next pointer was NULL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<22 /* req_badfil */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<22 /* req_badfil */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
- " Instruction fill when none outstanding.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<24 /* sprt0_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<24 /* sprt0_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<25 /* sprt1_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<25 /* sprt1_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<26 /* sprt2_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<26 /* sprt2_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT2_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<27 /* sprt3_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<27 /* sprt3_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT3_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_PKT_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_PKT_ERR_RSP;
- info.status_mask = 1ull<<0 /* pkterr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
- " the I/O subsystem.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RSP;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
- " ErrorResponse from the I/O subsystem.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RST */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RST;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
- " instruction because the source or destination\n"
- " was in reset.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn68xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn68xx.c
deleted file mode 100644
index aca3fdd..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn68xx.c
+++ /dev/null
@@ -1,14045 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn68xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN68XX</h2>
- * @dot
- * digraph cn68xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu2_src_pp0_ip2_pkt [label="CIU2_SRC_PPX_IP2_PKT(0)|<mii>mii|<agl>agl|<ilk>ilk"];
- * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu2_src_pp0_ip2_pkt:mii:e -> cvmx_mix0_isr [label="mii"];
- * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
- * cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
- * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
- * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
- * cvmx_ilk_gbl_int [label="ILK_GBL_INT|<rxf_lnk0_perr>rxf_lnk0_perr|<rxf_lnk1_perr>rxf_lnk1_perr|<rxf_ctl_perr>rxf_ctl_perr|<rxf_pop_empty>rxf_pop_empty|<rxf_push_full>rxf_push_full"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_gbl_int [label="ilk"];
- * cvmx_ilk_tx0_int [label="ILK_TXX_INT(0)|<txf_err>txf_err|<bad_seq>bad_seq|<bad_pipe>bad_pipe|<stat_cnt_ovfl>stat_cnt_ovfl"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_tx0_int [label="ilk"];
- * cvmx_ilk_tx1_int [label="ILK_TXX_INT(1)|<txf_err>txf_err|<bad_seq>bad_seq|<bad_pipe>bad_pipe|<stat_cnt_ovfl>stat_cnt_ovfl"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_tx1_int [label="ilk"];
- * cvmx_ilk_rx0_int [label="ILK_RXX_INT(0)|<lane_align_fail>lane_align_fail|<crc24_err>crc24_err|<word_sync_done>word_sync_done|<lane_align_done>lane_align_done|<stat_cnt_ovfl>stat_cnt_ovfl|<lane_bad_word>lane_bad_word|<pkt_drop_rxf>pkt_drop_rxf|<pkt_drop_rid>pkt_drop_rid|<pkt_drop_sop>pkt_drop_sop"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx0_int [label="ilk"];
- * cvmx_ilk_rx1_int [label="ILK_RXX_INT(1)|<lane_align_fail>lane_align_fail|<crc24_err>crc24_err|<word_sync_done>word_sync_done|<lane_align_done>lane_align_done|<stat_cnt_ovfl>stat_cnt_ovfl|<lane_bad_word>lane_bad_word|<pkt_drop_rxf>pkt_drop_rxf|<pkt_drop_rid>pkt_drop_rid|<pkt_drop_sop>pkt_drop_sop"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx1_int [label="ilk"];
- * cvmx_ilk_rx_lne0_int [label="ILK_RX_LNEX_INT(0)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne0_int [label="ilk"];
- * cvmx_ilk_rx_lne1_int [label="ILK_RX_LNEX_INT(1)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne1_int [label="ilk"];
- * cvmx_ilk_rx_lne2_int [label="ILK_RX_LNEX_INT(2)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne2_int [label="ilk"];
- * cvmx_ilk_rx_lne3_int [label="ILK_RX_LNEX_INT(3)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne3_int [label="ilk"];
- * cvmx_ilk_rx_lne4_int [label="ILK_RX_LNEX_INT(4)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne4_int [label="ilk"];
- * cvmx_ilk_rx_lne5_int [label="ILK_RX_LNEX_INT(5)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne5_int [label="ilk"];
- * cvmx_ilk_rx_lne6_int [label="ILK_RX_LNEX_INT(6)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne6_int [label="ilk"];
- * cvmx_ilk_rx_lne7_int [label="ILK_RX_LNEX_INT(7)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne7_int [label="ilk"];
- * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
- * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
- * cvmx_ilk_gbl_int -> cvmx_ilk_tx0_int [style=invis];
- * cvmx_ilk_tx0_int -> cvmx_ilk_tx1_int [style=invis];
- * cvmx_ilk_tx1_int -> cvmx_ilk_rx0_int [style=invis];
- * cvmx_ilk_rx0_int -> cvmx_ilk_rx1_int [style=invis];
- * cvmx_ilk_rx1_int -> cvmx_ilk_rx_lne0_int [style=invis];
- * cvmx_ilk_rx_lne0_int -> cvmx_ilk_rx_lne1_int [style=invis];
- * cvmx_ilk_rx_lne1_int -> cvmx_ilk_rx_lne2_int [style=invis];
- * cvmx_ilk_rx_lne2_int -> cvmx_ilk_rx_lne3_int [style=invis];
- * cvmx_ilk_rx_lne3_int -> cvmx_ilk_rx_lne4_int [style=invis];
- * cvmx_ilk_rx_lne4_int -> cvmx_ilk_rx_lne5_int [style=invis];
- * cvmx_ilk_rx_lne5_int -> cvmx_ilk_rx_lne6_int [style=invis];
- * cvmx_ilk_rx_lne6_int -> cvmx_ilk_rx_lne7_int [style=invis];
- * cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_pkt [label="root"];
- * cvmx_ciu2_src_pp0_ip2_rml [label="CIU2_SRC_PPX_IP2_RML(0)|<l2c>l2c|<fpa>fpa|<zip>zip|<ipd>ipd|<rad>rad|<sso>sso|<sli>sli|<key>key|<pip>pip|<dfa>dfa|<pko>pko|<dpi>dpi"];
- * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad1>tad1|<tad0>tad0|<tad3>tad3|<tad2>tad2"];
- * cvmx_l2c_tad1_int [label="L2C_TADX_INT(1)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_tad1_int [label="tad1"];
- * cvmx_l2c_err_tdt1 [label="L2C_ERR_TDTX(1)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_err_tdt1 [label="tad1"];
- * cvmx_l2c_err_ttg1 [label="L2C_ERR_TTGX(1)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_err_ttg1 [label="tad1"];
- * cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
- * cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
- * cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
- * cvmx_l2c_tad3_int [label="L2C_TADX_INT(3)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_tad3_int [label="tad3"];
- * cvmx_l2c_err_tdt3 [label="L2C_ERR_TDTX(3)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_err_tdt3 [label="tad3"];
- * cvmx_l2c_err_ttg3 [label="L2C_ERR_TTGX(3)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_err_ttg3 [label="tad3"];
- * cvmx_l2c_tad2_int [label="L2C_TADX_INT(2)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_tad2_int [label="tad2"];
- * cvmx_l2c_err_tdt2 [label="L2C_ERR_TDTX(2)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_err_tdt2 [label="tad2"];
- * cvmx_l2c_err_ttg2 [label="L2C_ERR_TTGX(2)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_err_ttg2 [label="tad2"];
- * cvmx_l2c_tad0_int -> cvmx_l2c_err_tdt0 [style=invis];
- * cvmx_l2c_err_tdt0 -> cvmx_l2c_err_ttg0 [style=invis];
- * cvmx_l2c_tad3_int -> cvmx_l2c_err_tdt3 [style=invis];
- * cvmx_l2c_err_tdt3 -> cvmx_l2c_err_ttg3 [style=invis];
- * cvmx_l2c_tad2_int -> cvmx_l2c_err_tdt2 [style=invis];
- * cvmx_l2c_err_tdt2 -> cvmx_l2c_err_ttg2 [style=invis];
- * cvmx_ciu2_src_pp0_ip2_rml:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<free8>free8|<q8_und>q8_und|<q8_coff>q8_coff|<q8_perr>q8_perr|<pool8th>pool8th|<paddr_e>paddr_e"];
- * cvmx_ciu2_src_pp0_ip2_rml:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_ciu2_src_pp0_ip2_rml:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr|<sop>sop|<eop>eop|<dat>dat|<pw0_sbe>pw0_sbe|<pw0_dbe>pw0_dbe|<pw1_sbe>pw1_sbe|<pw1_dbe>pw1_dbe|<pw2_sbe>pw2_sbe|<pw2_dbe>pw2_dbe|<pw3_sbe>pw3_sbe|<pw3_dbe>pw3_dbe"];
- * cvmx_ciu2_src_pp0_ip2_rml:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_ciu2_src_pp0_ip2_rml:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_sso_err [label="SSO_ERR|<iop>iop|<fidx_dbe>fidx_dbe|<idx_sbe>idx_sbe|<pnd_dbe0>pnd_dbe0|<oth_sbe1>oth_sbe1|<oth_dbe1>oth_dbe1|<oth_sbe0>oth_sbe0|<oth_dbe0>oth_dbe0|<pnd_sbe1>pnd_sbe1|<pnd_dbe1>pnd_dbe1|<pnd_sbe0>pnd_sbe0|<fpe>fpe|<awe>awe|<bfp>bfp|<idx_dbe>idx_dbe|<fidx_sbe>fidx_sbe"];
- * cvmx_ciu2_src_pp0_ip2_rml:sso:e -> cvmx_sso_err [label="sso"];
- * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad|<pipe_err>pipe_err"];
- * cvmx_ciu2_src_pp0_ip2_rml:sli:e -> cvmx_sli_int_sum [label="sli"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_ciu2_src_pp0_ip2_rml:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_ciu2_src_pp0_ip2_rml:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr|<dc1perr>dc1perr|<dc2perr>dc2perr|<dlc0_ovferr>dlc0_ovferr|<dlc1_ovferr>dlc1_ovferr|<dfanxm>dfanxm|<replerr>replerr"];
- * cvmx_ciu2_src_pp0_ip2_rml:dfa:e -> cvmx_dfa_error [label="dfa"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero|<loopback>loopback"];
- * cvmx_ciu2_src_pp0_ip2_rml:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
- * cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
- * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
- * cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
- * cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
- * cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
- * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
- * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
- * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
- * cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_rml [label="root"];
- * cvmx_ciu2_src_pp0_ip2_mio [label="CIU2_SRC_PPX_IP2_MIO(0)|<rst>rst|<nand>nand|<mio>mio"];
- * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
- * cvmx_ciu2_src_pp0_ip2_mio:rst:e -> cvmx_mio_rst_int [label="rst"];
- * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
- * cvmx_ciu2_src_pp0_ip2_mio:nand:e -> cvmx_ndf_int [label="nand"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_ciu2_src_pp0_ip2_mio:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_mio [label="root"];
- * cvmx_ciu2_sum_pp0_ip2 [label="CIU2_SUM_PPX_IP2(0)|<mem>mem|<pkt>pkt"];
- * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc0_int [label="mem"];
- * cvmx_lmc1_int [label="LMCX_INT(1)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc1_int [label="mem"];
- * cvmx_lmc2_int [label="LMCX_INT(2)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc2_int [label="mem"];
- * cvmx_lmc3_int [label="LMCX_INT(3)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc3_int [label="mem"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx0_int_reg [label="pkt"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx1_int_reg [label="pkt"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx2_int_reg [label="pkt"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx3_int_reg [label="pkt"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx1_rx0_int_reg [label="pkt"];
- * cvmx_gmx2_rx0_int_reg [label="GMXX_RXX_INT_REG(0,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx0_int_reg [label="pkt"];
- * cvmx_gmx2_rx1_int_reg [label="GMXX_RXX_INT_REG(1,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx1_int_reg [label="pkt"];
- * cvmx_gmx2_rx2_int_reg [label="GMXX_RXX_INT_REG(2,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx2_int_reg [label="pkt"];
- * cvmx_gmx2_rx3_int_reg [label="GMXX_RXX_INT_REG(3,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx3_int_reg [label="pkt"];
- * cvmx_gmx3_rx0_int_reg [label="GMXX_RXX_INT_REG(0,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx0_int_reg [label="pkt"];
- * cvmx_gmx3_rx1_int_reg [label="GMXX_RXX_INT_REG(1,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx1_int_reg [label="pkt"];
- * cvmx_gmx3_rx2_int_reg [label="GMXX_RXX_INT_REG(2,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx2_int_reg [label="pkt"];
- * cvmx_gmx3_rx3_int_reg [label="GMXX_RXX_INT_REG(3,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx3_int_reg [label="pkt"];
- * cvmx_gmx4_rx0_int_reg [label="GMXX_RXX_INT_REG(0,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx0_int_reg [label="pkt"];
- * cvmx_gmx4_rx1_int_reg [label="GMXX_RXX_INT_REG(1,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx1_int_reg [label="pkt"];
- * cvmx_gmx4_rx2_int_reg [label="GMXX_RXX_INT_REG(2,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx2_int_reg [label="pkt"];
- * cvmx_gmx4_rx3_int_reg [label="GMXX_RXX_INT_REG(3,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx3_int_reg [label="pkt"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_tx_int_reg [label="pkt"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx1_tx_int_reg [label="pkt"];
- * cvmx_gmx2_tx_int_reg [label="GMXX_TX_INT_REG(2)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_tx_int_reg [label="pkt"];
- * cvmx_gmx3_tx_int_reg [label="GMXX_TX_INT_REG(3)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_tx_int_reg [label="pkt"];
- * cvmx_gmx4_tx_int_reg [label="GMXX_TX_INT_REG(4)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_tx_int_reg [label="pkt"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int0_reg [label="pkt"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int1_reg [label="pkt"];
- * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int2_reg [label="pkt"];
- * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int3_reg [label="pkt"];
- * cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs1_int0_reg [label="pkt"];
- * cvmx_pcs2_int0_reg [label="PCSX_INTX_REG(0,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int0_reg [label="pkt"];
- * cvmx_pcs2_int1_reg [label="PCSX_INTX_REG(1,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int1_reg [label="pkt"];
- * cvmx_pcs2_int2_reg [label="PCSX_INTX_REG(2,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int2_reg [label="pkt"];
- * cvmx_pcs2_int3_reg [label="PCSX_INTX_REG(3,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int3_reg [label="pkt"];
- * cvmx_pcs3_int0_reg [label="PCSX_INTX_REG(0,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int0_reg [label="pkt"];
- * cvmx_pcs3_int1_reg [label="PCSX_INTX_REG(1,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int1_reg [label="pkt"];
- * cvmx_pcs3_int2_reg [label="PCSX_INTX_REG(2,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int2_reg [label="pkt"];
- * cvmx_pcs3_int3_reg [label="PCSX_INTX_REG(3,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int3_reg [label="pkt"];
- * cvmx_pcs4_int0_reg [label="PCSX_INTX_REG(0,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int0_reg [label="pkt"];
- * cvmx_pcs4_int1_reg [label="PCSX_INTX_REG(1,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int1_reg [label="pkt"];
- * cvmx_pcs4_int2_reg [label="PCSX_INTX_REG(2,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int2_reg [label="pkt"];
- * cvmx_pcs4_int3_reg [label="PCSX_INTX_REG(3,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int3_reg [label="pkt"];
- * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx0_int_reg [label="pkt"];
- * cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx1_int_reg [label="pkt"];
- * cvmx_pcsx2_int_reg [label="PCSXX_INT_REG(2)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx2_int_reg [label="pkt"];
- * cvmx_pcsx3_int_reg [label="PCSXX_INT_REG(3)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx3_int_reg [label="pkt"];
- * cvmx_pcsx4_int_reg [label="PCSXX_INT_REG(4)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx4_int_reg [label="pkt"];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx2_rx0_int_reg [style=invis];
- * cvmx_gmx2_rx0_int_reg -> cvmx_gmx2_rx1_int_reg [style=invis];
- * cvmx_gmx2_rx1_int_reg -> cvmx_gmx2_rx2_int_reg [style=invis];
- * cvmx_gmx2_rx2_int_reg -> cvmx_gmx2_rx3_int_reg [style=invis];
- * cvmx_gmx2_rx3_int_reg -> cvmx_gmx3_rx0_int_reg [style=invis];
- * cvmx_gmx3_rx0_int_reg -> cvmx_gmx3_rx1_int_reg [style=invis];
- * cvmx_gmx3_rx1_int_reg -> cvmx_gmx3_rx2_int_reg [style=invis];
- * cvmx_gmx3_rx2_int_reg -> cvmx_gmx3_rx3_int_reg [style=invis];
- * cvmx_gmx3_rx3_int_reg -> cvmx_gmx4_rx0_int_reg [style=invis];
- * cvmx_gmx4_rx0_int_reg -> cvmx_gmx4_rx1_int_reg [style=invis];
- * cvmx_gmx4_rx1_int_reg -> cvmx_gmx4_rx2_int_reg [style=invis];
- * cvmx_gmx4_rx2_int_reg -> cvmx_gmx4_rx3_int_reg [style=invis];
- * cvmx_gmx4_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_gmx0_tx_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_gmx1_tx_int_reg -> cvmx_gmx2_tx_int_reg [style=invis];
- * cvmx_gmx2_tx_int_reg -> cvmx_gmx3_tx_int_reg [style=invis];
- * cvmx_gmx3_tx_int_reg -> cvmx_gmx4_tx_int_reg [style=invis];
- * cvmx_gmx4_tx_int_reg -> cvmx_pcs0_int0_reg [style=invis];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
- * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
- * cvmx_pcs0_int3_reg -> cvmx_pcs1_int0_reg [style=invis];
- * cvmx_pcs1_int0_reg -> cvmx_pcs2_int0_reg [style=invis];
- * cvmx_pcs2_int0_reg -> cvmx_pcs2_int1_reg [style=invis];
- * cvmx_pcs2_int1_reg -> cvmx_pcs2_int2_reg [style=invis];
- * cvmx_pcs2_int2_reg -> cvmx_pcs2_int3_reg [style=invis];
- * cvmx_pcs2_int3_reg -> cvmx_pcs3_int0_reg [style=invis];
- * cvmx_pcs3_int0_reg -> cvmx_pcs3_int1_reg [style=invis];
- * cvmx_pcs3_int1_reg -> cvmx_pcs3_int2_reg [style=invis];
- * cvmx_pcs3_int2_reg -> cvmx_pcs3_int3_reg [style=invis];
- * cvmx_pcs3_int3_reg -> cvmx_pcs4_int0_reg [style=invis];
- * cvmx_pcs4_int0_reg -> cvmx_pcs4_int1_reg [style=invis];
- * cvmx_pcs4_int1_reg -> cvmx_pcs4_int2_reg [style=invis];
- * cvmx_pcs4_int2_reg -> cvmx_pcs4_int3_reg [style=invis];
- * cvmx_pcs4_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
- * cvmx_pcsx0_int_reg -> cvmx_pcsx1_int_reg [style=invis];
- * cvmx_pcsx1_int_reg -> cvmx_pcsx2_int_reg [style=invis];
- * cvmx_pcsx2_int_reg -> cvmx_pcsx3_int_reg [style=invis];
- * cvmx_pcsx3_int_reg -> cvmx_pcsx4_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_ciu2_sum_pp0_ip2 [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn68xx(void);
-
-int cvmx_error_initialize_cn68xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU2_SRC_PPX_IP2_PKT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<40 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]\n"
- " bit is set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<40 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]\n"
- " bit is set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<40 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU2_RAW_PKT[MII] bit is set.\n"
- " If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<40 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<40 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_BAD_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<32 /* ovrflw */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<33 /* txpop */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<34 /* txpsh */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<35 /* ovrflw1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<36 /* txpop1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<37 /* txpsh1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
- " In MII/RGMII, one bit per port\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_TX_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 0x3ull<<2 /* undflw */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 0x3ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_GBL_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_GBL_INT;
- info.status_mask = 1ull<<0 /* rxf_lnk0_perr */;
- info.enable_addr = CVMX_ILK_GBL_INT_EN;
- info.enable_mask = 1ull<<0 /* rxf_lnk0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_GBL_INT[RXF_LNK0_PERR]: RXF parity error occurred on RxLink0 packet data. Packet will\n"
- " be marked with error at eop\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_GBL_INT;
- info.status_mask = 1ull<<1 /* rxf_lnk1_perr */;
- info.enable_addr = CVMX_ILK_GBL_INT_EN;
- info.enable_mask = 1ull<<1 /* rxf_lnk1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_GBL_INT[RXF_LNK1_PERR]: RXF parity error occurred on RxLink1 packet data\n"
- " Packet will be marked with error at eop\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_GBL_INT;
- info.status_mask = 1ull<<2 /* rxf_ctl_perr */;
- info.enable_addr = CVMX_ILK_GBL_INT_EN;
- info.enable_mask = 1ull<<2 /* rxf_ctl_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_GBL_INT[RXF_CTL_PERR]: RXF parity error occurred on sideband control signals. Data\n"
- " cycle will be dropped.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_GBL_INT;
- info.status_mask = 1ull<<3 /* rxf_pop_empty */;
- info.enable_addr = CVMX_ILK_GBL_INT_EN;
- info.enable_mask = 1ull<<3 /* rxf_pop_empty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_GBL_INT[RXF_POP_EMPTY]: RXF underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_GBL_INT;
- info.status_mask = 1ull<<4 /* rxf_push_full */;
- info.enable_addr = CVMX_ILK_GBL_INT_EN;
- info.enable_mask = 1ull<<4 /* rxf_push_full */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_GBL_INT[RXF_PUSH_FULL]: RXF overflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_TXX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(0);
- info.status_mask = 1ull<<0 /* txf_err */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* txf_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(0)[TXF_ERR]: TX fifo parity error occurred. At EOP time, EOP_Format will\n"
- " reflect the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(0);
- info.status_mask = 1ull<<1 /* bad_seq */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(0)[BAD_SEQ]: Received sequence is not SOP followed by 0 or more data cycles\n"
- " followed by EOP. PKO config assigned multiple engines to the\n"
- " same ILK Tx Link.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(0);
- info.status_mask = 1ull<<2 /* bad_pipe */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* bad_pipe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(0)[BAD_PIPE]: Received a PKO port-pipe out of the range specified by\n"
- " ILK_TXX_PIPE\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(0);
- info.status_mask = 1ull<<3 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(0);
- info.enable_mask = 1ull<<3 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(0)[STAT_CNT_OVFL]: Statistics counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_TXX_INT(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(1);
- info.status_mask = 1ull<<0 /* txf_err */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* txf_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(1)[TXF_ERR]: TX fifo parity error occurred. At EOP time, EOP_Format will\n"
- " reflect the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(1);
- info.status_mask = 1ull<<1 /* bad_seq */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(1)[BAD_SEQ]: Received sequence is not SOP followed by 0 or more data cycles\n"
- " followed by EOP. PKO config assigned multiple engines to the\n"
- " same ILK Tx Link.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(1);
- info.status_mask = 1ull<<2 /* bad_pipe */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(1);
- info.enable_mask = 1ull<<2 /* bad_pipe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(1)[BAD_PIPE]: Received a PKO port-pipe out of the range specified by\n"
- " ILK_TXX_PIPE\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(1);
- info.status_mask = 1ull<<3 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(1);
- info.enable_mask = 1ull<<3 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(1)[STAT_CNT_OVFL]: Statistics counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RXX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<0 /* lane_align_fail */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* lane_align_fail */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[LANE_ALIGN_FAIL]: Lane Alignment fails (4 tries). Hardware will repeat lane\n"
- " alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA]\n"
- " is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<1 /* crc24_err */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* crc24_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[CRC24_ERR]: Burst CRC24 error. All open packets will be receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<2 /* word_sync_done */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* word_sync_done */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[WORD_SYNC_DONE]: All enabled lanes have achieved word boundary lock and\n"
- " scrambler synchronization. Lane alignment may now be enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<3 /* lane_align_done */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<3 /* lane_align_done */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[LANE_ALIGN_DONE]: Lane alignment successful\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<4 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<4 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[STAT_CNT_OVFL]: Statistics counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<5 /* lane_bad_word */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<5 /* lane_bad_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[LANE_BAD_WORD]: A lane encountered either a bad 64B/67B codeword or an unknown\n"
- " control word type.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<6 /* pkt_drop_rxf */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<6 /* pkt_drop_rxf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[PKT_DROP_RXF]: Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<7 /* pkt_drop_rid */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<7 /* pkt_drop_rid */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[PKT_DROP_RID]: Entire packet dropped due to the lack of reassembly-ids or\n"
- " because ILK_RXX_CFG1[PKT_ENA]=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<8 /* pkt_drop_sop */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* pkt_drop_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[PKT_DROP_SOP]: Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX,\n"
- " lack of reassembly-ids or because ILK_RXX_CFG1[PKT_ENA]=0 | $RW\n"
- " because ILK_RXX_CFG1[PKT_ENA]=0\n"
- " ***NOTE: Added in pass 2.0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RXX_INT(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<0 /* lane_align_fail */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* lane_align_fail */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[LANE_ALIGN_FAIL]: Lane Alignment fails (4 tries). Hardware will repeat lane\n"
- " alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA]\n"
- " is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<1 /* crc24_err */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* crc24_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[CRC24_ERR]: Burst CRC24 error. All open packets will be receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<2 /* word_sync_done */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<2 /* word_sync_done */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[WORD_SYNC_DONE]: All enabled lanes have achieved word boundary lock and\n"
- " scrambler synchronization. Lane alignment may now be enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<3 /* lane_align_done */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<3 /* lane_align_done */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[LANE_ALIGN_DONE]: Lane alignment successful\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<4 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<4 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[STAT_CNT_OVFL]: Statistics counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<5 /* lane_bad_word */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<5 /* lane_bad_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[LANE_BAD_WORD]: A lane encountered either a bad 64B/67B codeword or an unknown\n"
- " control word type.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<6 /* pkt_drop_rxf */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<6 /* pkt_drop_rxf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[PKT_DROP_RXF]: Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<7 /* pkt_drop_rid */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<7 /* pkt_drop_rid */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[PKT_DROP_RID]: Entire packet dropped due to the lack of reassembly-ids or\n"
- " because ILK_RXX_CFG1[PKT_ENA]=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<8 /* pkt_drop_sop */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<8 /* pkt_drop_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[PKT_DROP_SOP]: Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX,\n"
- " lack of reassembly-ids or because ILK_RXX_CFG1[PKT_ENA]=0 | $RW\n"
- " because ILK_RXX_CFG1[PKT_ENA]=0\n"
- " ***NOTE: Added in pass 2.0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(5) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(6) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(7) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU2_SRC_PPX_IP2_RML(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<0 /* holerd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<0 /* holerd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<1 /* holewr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<1 /* holewr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<2 /* vrtwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<2 /* vrtwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
- " Set when L2C_VRT_MEM blocked a store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<3 /* vrtidrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<3 /* vrtidrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
- " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
- " store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<4 /* vrtadrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<4 /* vrtadrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
- " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
- " store.\n"
- " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<5 /* vrtpe */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<5 /* vrtpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
- " Whenever an L2C_VRT_MEM read finds a parity error,\n"
- " that L2C_VRT_MEM cannot cause stores to be blocked.\n"
- " Software should correct the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<6 /* bigwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<6 /* bigwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<7 /* bigrd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<7 /* bigrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(1);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(1)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(1);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(1)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(1);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(1)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(1);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(1)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(1);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(1)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(1);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(1)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(1);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(1)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(3);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(3)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(3);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(3)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(3);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(3)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(3);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(3)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(3);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(3)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(3);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(3)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(3);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(3)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(2);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(2)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(2);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(2)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(2);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(2)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(2);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(2)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(2);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(2)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(2);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(2)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(2);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(2)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<28 /* pool0th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<28 /* pool0th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
- " FPA_POOL0_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<29 /* pool1th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<29 /* pool1th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
- " FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<30 /* pool2th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<30 /* pool2th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
- " FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<31 /* pool3th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<31 /* pool3th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
- " FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<32 /* pool4th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<32 /* pool4th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
- " FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<33 /* pool5th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<33 /* pool5th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
- " FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<34 /* pool6th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<34 /* pool6th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
- " FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<35 /* pool7th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<35 /* pool7th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
- " FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<36 /* free0 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<36 /* free0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<37 /* free1 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<37 /* free1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<38 /* free2 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<38 /* free2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<39 /* free3 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<39 /* free3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<40 /* free4 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<40 /* free4 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<41 /* free5 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<41 /* free5 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<42 /* free6 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<42 /* free6 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<43 /* free7 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<43 /* free7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<44 /* free8 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<44 /* free8 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE8]: When a pointer for POOL8 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<45 /* q8_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<45 /* q8_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q8_UND]: Set when a Queue8 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<46 /* q8_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<46 /* q8_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q8_COFF]: Set when a Queue8 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<47 /* q8_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<47 /* q8_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q8_PERR]: Set when a Queue8 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<48 /* pool8th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<48 /* pool8th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL8TH]: Set when FPA_QUE8_AVAILABLE is equal to\n"
- " FPA_POOL8_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<49 /* paddr_e */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<49 /* paddr_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
- " address range for a pool specified by\n"
- " FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<24 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n"
- " NOT USED ON o68.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n"
- " NOT USED ON o68.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n"
- " NOT USED ON o68.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n"
- " NOT USED ON o68.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<12 /* sop */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<12 /* sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[SOP]: Set when a SOP is followed by an SOP for the same\n"
- " reasm-id for a packet.\n"
- " The first detected error associated with bits [14:12]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n"
- " Also see IPD_PKT_ERR.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<13 /* eop */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<13 /* eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[EOP]: Set when a EOP is followed by an EOP for the same\n"
- " reasm-id for a packet.\n"
- " The first detected error associated with bits [14:12]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n"
- " Also see IPD_PKT_ERR.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<14 /* dat */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<14 /* dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DAT]: Set when a data arrives before a SOP for the same\n"
- " reasm-id for a packet.\n"
- " The first detected error associated with bits [14:12]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n"
- " Also see IPD_PKT_ERR.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<15 /* pw0_sbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<15 /* pw0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW0_SBE]: Packet memory 0 had ECC SBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<16 /* pw0_dbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<16 /* pw0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW0_DBE]: Packet memory 0 had ECC DBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<17 /* pw1_sbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<17 /* pw1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW1_SBE]: Packet memory 1 had ECC SBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<18 /* pw1_dbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<18 /* pw1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW1_DBE]: Packet memory 1 had ECC DBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<19 /* pw2_sbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<19 /* pw2_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW2_SBE]: Packet memory 2 had ECC SBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<20 /* pw2_dbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<20 /* pw2_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW2_DBE]: Packet memory 2 had ECC DBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<21 /* pw3_sbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<21 /* pw3_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW3_SBE]: Packet memory 3 had ECC SBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<22 /* pw3_dbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<22 /* pw3_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW3_DBE]: Packet memory 3 had ECC DBE.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<29 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SSO_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 0x7ffull<<32 /* iop */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 0x7ffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<1 /* fidx_dbe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<1 /* fidx_dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[FIDX_DBE]: Double bit error for FIDX RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<2 /* idx_sbe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<2 /* idx_sbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[IDX_SBE]: Single bit error for IDX RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<11 /* pnd_dbe0 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<11 /* pnd_dbe0_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[PND_DBE0]: Double bit error for even PND RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<4 /* oth_sbe1 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<4 /* oth_sbe1_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[OTH_SBE1]: Single bit error for odd OTH RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<5 /* oth_dbe1 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<5 /* oth_dbe1_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[OTH_DBE1]: Double bit error for odd OTH RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<6 /* oth_sbe0 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<6 /* oth_sbe0_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[OTH_SBE0]: Single bit error for even OTH RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<7 /* oth_dbe0 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<7 /* oth_dbe0_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[OTH_DBE0]: Double bit error for even OTH RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<8 /* pnd_sbe1 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<8 /* pnd_sbe1_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[PND_SBE1]: Single bit error for odd PND RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<9 /* pnd_dbe1 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<9 /* pnd_dbe1_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[PND_DBE1]: Double bit error for odd PND RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<10 /* pnd_sbe0 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<10 /* pnd_sbe0_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[PND_SBE0]: Single bit error for even PND RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<45 /* fpe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<45 /* fpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[FPE]: Free page error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<46 /* awe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<46 /* awe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[AWE]: Out-of-memory error (ADDWQ Request is dropped)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<47 /* bfp */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<47 /* bfp_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[BFP]: Bad Fill Packet error\n"
- " Last byte of the fill packet did not match 8'h1a\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<3 /* idx_dbe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<3 /* idx_dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[IDX_DBE]: Double bit error for IDX RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<0 /* fidx_sbe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<0 /* fidx_sbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[FIDX_SBE]: Single bit error for FIDX RAM\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_SLI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<0 /* rml_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
- " within 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<1 /* reserved_1_1 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<1 /* reserved_1_1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<8 /* m0_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<8 /* m0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<9 /* m0_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<9 /* m0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<10 /* m0_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<10 /* m0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<11 /* m0_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<11 /* m0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<12 /* m1_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<12 /* m1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<13 /* m1_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<13 /* m1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<14 /* m1_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<14 /* m1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<15 /* m1_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<15 /* m1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<48 /* pidbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<48 /* pidbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<49 /* psldbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<49 /* psldbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<50 /* pout_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<50 /* pout_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
- " set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<52 /* pgl_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<52 /* pgl_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
- " read this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<53 /* pdi_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<53 /* pdi_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<54 /* pop_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<54 /* pop_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
- " pointer pair this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<55 /* pins_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<55 /* pins_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<56 /* sprt0_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<56 /* sprt0_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<57 /* sprt1_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<57 /* sprt1_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<60 /* ill_pad */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<60 /* ill_pad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
- " range of the Packet-CSR, but for an unused\n"
- " address.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<61 /* pipe_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<61 /* pipe_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIPE_ERR]: Set when a PIPE value outside range is received.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<30 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<30 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<30 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<30 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<0 /* dblovf */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<0 /* dblina */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 0x7ull<<1 /* dc0perr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 0x7ull<<1 /* dc0pena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DC0PERR]: Cluster#0 RAM[3:1] Parity Error Detected\n"
- " See also DFA_DTCFADR register which contains the\n"
- " failing addresses for the internal node cache RAMs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 0x7ull<<4 /* dc1perr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 0x7ull<<4 /* dc1pena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DC1PERR]: Cluster#1 RAM[3:1] Parity Error Detected\n"
- " See also DFA_DTCFADR register which contains the\n"
- " failing addresses for the internal node cache RAMs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 0x7ull<<7 /* dc2perr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 0x7ull<<7 /* dc2pena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DC2PERR]: Cluster#2 RAM[3:1] Parity Error Detected\n"
- " See also DFA_DTCFADR register which contains the\n"
- " failing addresses for the internal node cache RAMs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<13 /* dlc0_ovferr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<13 /* dlc0_ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DLC0_OVFERR]: DLC0 Fifo Overflow Error Detected\n"
- " This condition should NEVER architecturally occur, and\n"
- " is here in case HW credit/debit scheme is not working.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<14 /* dlc1_ovferr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<14 /* dlc1_ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DLC1_OVFERR]: DLC1 Fifo Overflow Error Detected\n"
- " This condition should NEVER architecturally occur, and\n"
- " is here in case HW credit/debit scheme is not working.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<17 /* dfanxm */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<17 /* dfanxmena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DFANXM]: DFA Non-existent Memory Access\n"
- " For o68: DTEs (and backdoor CSR DFA Memory REGION reads)\n"
- " have access to the following 38bit L2/DRAM address space\n"
- " which maps to a 37bit physical DDR3 SDRAM address space.\n"
- " see:\n"
- " DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF\n"
- " maps to lower 256MB of physical DDR3 SDRAM\n"
- " DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF\n"
- " maps to upper 127.75GB of DDR3 SDRAM\n"
- " L2/DRAM address space Physical DDR3 SDRAM Address space\n"
- " (38bit address) (37bit address)\n"
- " +-----------+ 0x0020.0FFF.FFFF\n"
- " |\n"
- " === DR1 === +-----------+ 0x001F.FFFF.FFFF\n"
- " (128GB-256MB)| | |\n"
- " | | => | | (128GB-256MB)\n"
- " +-----------+ 0x0000.1FFF.FFFF | DR1\n"
- " 256MB | HOLE | (DO NOT USE) |\n"
- " +-----------+ 0x0000.0FFF.FFFF +-----------+ 0x0000.0FFF.FFFF\n"
- " 256MB | DR0 | | DR0 | (256MB)\n"
- " +-----------+ 0x0000.0000.0000 +-----------+ 0x0000.0000.0000\n"
- " In the event the DFA generates a reference to the L2/DRAM\n"
- " address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to\n"
- " an address above 0x0020.0FFF.FFFF, the DFANXM programmable\n"
- " interrupt bit will be set.\n"
- " SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR\n"
- " accesses to DFA Memory REGION MUST avoid making references\n"
- " to these non-existent memory regions.\n"
- " NOTE: If DFANXM is set during a DFA Graph Walk operation,\n"
- " then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
- " If DFANXM is set during a NCB-Direct CSR read access to DFA\n"
- " Memory REGION, then the CSR read response data is forced to\n"
- " 128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW\n"
- " being accessed, either the upper or lower QW will be returned).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<18 /* replerr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<18 /* replerrena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[REPLERR]: DFA Illegal Replication Factor Error\n"
- " For o68: DFA only supports 1x, 2x, and 4x port replication.\n"
- " Legal configurations for memory are to support 2 port or\n"
- " 4 port configurations.\n"
- " The REPLERR interrupt will be set in the following illegal\n"
- " configuration cases:\n"
- " 1) An 8x replication factor is detected for any memory reference.\n"
- " 2) A 4x replication factor is detected for any memory reference\n"
- " when only 2 memory ports are enabled.\n"
- " NOTE: If REPLERR is set during a DFA Graph Walk operation,\n"
- " then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
- " If REPLERR is set during a NCB-Direct CSR read access to DFA\n"
- " Memory REGION, then the CSR read response data is UNPREDICTABLE.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<7 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<7 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<7 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<3 /* loopback */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<3 /* loopback */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<7 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[LOOPBACK]: A packet was sent to an illegal loopback port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<0 /* nderr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<0 /* nderr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
- " DPI received a NCB transaction on the outbound\n"
- " bus to the DPI deviceID, but the command was not\n"
- " recognized.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<1 /* nfovr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<1 /* nfovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
- " DPI can store upto 16 CSR request. The FIFO will\n"
- " overflow if that number is exceeded.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 0xffull<<8 /* dmadbo */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 0xffull<<8 /* dmadbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
- " DPI has a 32-bit counter for each request's queue\n"
- " outstanding doorbell counts. Interrupt will fire\n"
- " if the count overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<16 /* req_badadr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<16 /* req_badadr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch to the NULL pointer.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<17 /* req_badlen */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<17 /* req_badlen */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch with length of zero.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<18 /* req_ovrflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<18 /* req_ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<19 /* req_undflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<19 /* req_undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO underflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<20 /* req_anull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<20 /* req_anull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
- " Fetched instruction word was 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<21 /* req_inull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<21 /* req_inull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
- " Next pointer was NULL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<22 /* req_badfil */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<22 /* req_badfil */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
- " Instruction fill when none outstanding.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<24 /* sprt0_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<24 /* sprt0_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<25 /* sprt1_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<25 /* sprt1_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_PKT_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_PKT_ERR_RSP;
- info.status_mask = 1ull<<0 /* pkterr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
- " the I/O subsystem.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RSP;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
- " ErrorResponse from the I/O subsystem.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RST */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RST;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
- " instruction because the source or destination\n"
- " was in reset.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU2_SRC_PPX_IP2_MIO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_RST_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<0 /* rst_link0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<0 /* rst_link0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<63 /* rst */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL0[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<1 /* rst_link1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<1 /* rst_link1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<63 /* rst */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL1[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<8 /* perst0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<8 /* perst0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<63 /* rst */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
- " and MIO_RST_CTL0[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<9 /* perst1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<9 /* perst1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<63 /* rst */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
- " and MIO_RST_CTL1[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NDF_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<2 /* wdog */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<2 /* wdog */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<16 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<3 /* sm_bad */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<3 /* sm_bad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<16 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<4 /* ecc_1bit */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<4 /* ecc_1bit */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<16 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<5 /* ecc_mult */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<5 /* ecc_mult */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<16 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<6 /* ovrf */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<6 /* ovrf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<16 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
- " fatal error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<17 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<17 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU2_SUM_PPX_IP2(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(1);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(1);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(1)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(1);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(1);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(2);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(2);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(2)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(2);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(2);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(2)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(2);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(2);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(2)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(3);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(3);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(3)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(3);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(3);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(3)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(3);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(3);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(3)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(2);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(2);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(2)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(2);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(2);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(2)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(2);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(2);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(2)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(3);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(3);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(3)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(3);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(3);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(3)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(3);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(3);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(3)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(4);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(4);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(4)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(4);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(4);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(4)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(4);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(4);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(4)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cn68xxp1.c b/sys/contrib/octeon-sdk/cvmx-error-init-cn68xxp1.c
deleted file mode 100644
index 282c9d1..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cn68xxp1.c
+++ /dev/null
@@ -1,14007 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cn68xxp1.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN68XXP1</h2>
- * @dot
- * digraph cn68xxp1
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu2_src_pp0_ip2_pkt [label="CIU2_SRC_PPX_IP2_PKT(0)|<mii>mii|<agl>agl|<ilk>ilk"];
- * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
- * cvmx_ciu2_src_pp0_ip2_pkt:mii:e -> cvmx_mix0_isr [label="mii"];
- * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
- * cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
- * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
- * cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
- * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
- * cvmx_ciu2_src_pp0_ip2_pkt:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
- * cvmx_ilk_gbl_int [label="ILK_GBL_INT|<rxf_lnk0_perr>rxf_lnk0_perr|<rxf_lnk1_perr>rxf_lnk1_perr|<rxf_ctl_perr>rxf_ctl_perr|<rxf_pop_empty>rxf_pop_empty|<rxf_push_full>rxf_push_full"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_gbl_int [label="ilk"];
- * cvmx_ilk_tx0_int [label="ILK_TXX_INT(0)|<txf_err>txf_err|<bad_seq>bad_seq|<bad_pipe>bad_pipe|<stat_cnt_ovfl>stat_cnt_ovfl"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_tx0_int [label="ilk"];
- * cvmx_ilk_tx1_int [label="ILK_TXX_INT(1)|<txf_err>txf_err|<bad_seq>bad_seq|<bad_pipe>bad_pipe|<stat_cnt_ovfl>stat_cnt_ovfl"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_tx1_int [label="ilk"];
- * cvmx_ilk_rx0_int [label="ILK_RXX_INT(0)|<lane_align_fail>lane_align_fail|<crc24_err>crc24_err|<word_sync_done>word_sync_done|<lane_align_done>lane_align_done|<stat_cnt_ovfl>stat_cnt_ovfl|<lane_bad_word>lane_bad_word|<pkt_drop_rxf>pkt_drop_rxf|<pkt_drop_rid>pkt_drop_rid"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx0_int [label="ilk"];
- * cvmx_ilk_rx1_int [label="ILK_RXX_INT(1)|<lane_align_fail>lane_align_fail|<crc24_err>crc24_err|<word_sync_done>word_sync_done|<lane_align_done>lane_align_done|<stat_cnt_ovfl>stat_cnt_ovfl|<lane_bad_word>lane_bad_word|<pkt_drop_rxf>pkt_drop_rxf|<pkt_drop_rid>pkt_drop_rid"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx1_int [label="ilk"];
- * cvmx_ilk_rx_lne0_int [label="ILK_RX_LNEX_INT(0)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne0_int [label="ilk"];
- * cvmx_ilk_rx_lne1_int [label="ILK_RX_LNEX_INT(1)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne1_int [label="ilk"];
- * cvmx_ilk_rx_lne2_int [label="ILK_RX_LNEX_INT(2)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne2_int [label="ilk"];
- * cvmx_ilk_rx_lne3_int [label="ILK_RX_LNEX_INT(3)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne3_int [label="ilk"];
- * cvmx_ilk_rx_lne4_int [label="ILK_RX_LNEX_INT(4)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne4_int [label="ilk"];
- * cvmx_ilk_rx_lne5_int [label="ILK_RX_LNEX_INT(5)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne5_int [label="ilk"];
- * cvmx_ilk_rx_lne6_int [label="ILK_RX_LNEX_INT(6)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne6_int [label="ilk"];
- * cvmx_ilk_rx_lne7_int [label="ILK_RX_LNEX_INT(7)|<serdes_lock_loss>serdes_lock_loss|<bdry_sync_loss>bdry_sync_loss|<crc32_err>crc32_err|<ukwn_cntl_word>ukwn_cntl_word|<scrm_sync_loss>scrm_sync_loss|<dskew_fifo_ovfl>dskew_fifo_ovfl|<stat_msg>stat_msg|<stat_cnt_ovfl>stat_cnt_ovfl|<bad_64b67b>bad_64b67b"];
- * cvmx_ciu2_src_pp0_ip2_pkt:ilk:e -> cvmx_ilk_rx_lne7_int [label="ilk"];
- * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
- * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
- * cvmx_ilk_gbl_int -> cvmx_ilk_tx0_int [style=invis];
- * cvmx_ilk_tx0_int -> cvmx_ilk_tx1_int [style=invis];
- * cvmx_ilk_tx1_int -> cvmx_ilk_rx0_int [style=invis];
- * cvmx_ilk_rx0_int -> cvmx_ilk_rx1_int [style=invis];
- * cvmx_ilk_rx1_int -> cvmx_ilk_rx_lne0_int [style=invis];
- * cvmx_ilk_rx_lne0_int -> cvmx_ilk_rx_lne1_int [style=invis];
- * cvmx_ilk_rx_lne1_int -> cvmx_ilk_rx_lne2_int [style=invis];
- * cvmx_ilk_rx_lne2_int -> cvmx_ilk_rx_lne3_int [style=invis];
- * cvmx_ilk_rx_lne3_int -> cvmx_ilk_rx_lne4_int [style=invis];
- * cvmx_ilk_rx_lne4_int -> cvmx_ilk_rx_lne5_int [style=invis];
- * cvmx_ilk_rx_lne5_int -> cvmx_ilk_rx_lne6_int [style=invis];
- * cvmx_ilk_rx_lne6_int -> cvmx_ilk_rx_lne7_int [style=invis];
- * cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_pkt [label="root"];
- * cvmx_ciu2_src_pp0_ip2_rml [label="CIU2_SRC_PPX_IP2_RML(0)|<l2c>l2c|<fpa>fpa|<zip>zip|<ipd>ipd|<rad>rad|<sso>sso|<sli>sli|<key>key|<pip>pip|<dfa>dfa|<pko>pko|<dpi>dpi"];
- * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad1>tad1|<tad0>tad0|<tad3>tad3|<tad2>tad2"];
- * cvmx_l2c_tad1_int [label="L2C_TADX_INT(1)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_tad1_int [label="tad1"];
- * cvmx_l2c_err_tdt1 [label="L2C_ERR_TDTX(1)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_err_tdt1 [label="tad1"];
- * cvmx_l2c_err_ttg1 [label="L2C_ERR_TTGX(1)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad1:e -> cvmx_l2c_err_ttg1 [label="tad1"];
- * cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
- * cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
- * cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
- * cvmx_l2c_tad3_int [label="L2C_TADX_INT(3)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_tad3_int [label="tad3"];
- * cvmx_l2c_err_tdt3 [label="L2C_ERR_TDTX(3)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_err_tdt3 [label="tad3"];
- * cvmx_l2c_err_ttg3 [label="L2C_ERR_TTGX(3)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad3:e -> cvmx_l2c_err_ttg3 [label="tad3"];
- * cvmx_l2c_tad2_int [label="L2C_TADX_INT(2)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_tad2_int [label="tad2"];
- * cvmx_l2c_err_tdt2 [label="L2C_ERR_TDTX(2)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_err_tdt2 [label="tad2"];
- * cvmx_l2c_err_ttg2 [label="L2C_ERR_TTGX(2)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad2:e -> cvmx_l2c_err_ttg2 [label="tad2"];
- * cvmx_l2c_tad0_int -> cvmx_l2c_err_tdt0 [style=invis];
- * cvmx_l2c_err_tdt0 -> cvmx_l2c_err_ttg0 [style=invis];
- * cvmx_l2c_tad3_int -> cvmx_l2c_err_tdt3 [style=invis];
- * cvmx_l2c_err_tdt3 -> cvmx_l2c_err_ttg3 [style=invis];
- * cvmx_l2c_tad2_int -> cvmx_l2c_err_tdt2 [style=invis];
- * cvmx_l2c_err_tdt2 -> cvmx_l2c_err_ttg2 [style=invis];
- * cvmx_ciu2_src_pp0_ip2_rml:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<free8>free8|<q8_und>q8_und|<q8_coff>q8_coff|<q8_perr>q8_perr|<pool8th>pool8th|<paddr_e>paddr_e"];
- * cvmx_ciu2_src_pp0_ip2_rml:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_ciu2_src_pp0_ip2_rml:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr|<sop>sop|<eop>eop|<dat>dat|<pw0_sbe>pw0_sbe|<pw0_dbe>pw0_dbe|<pw1_sbe>pw1_sbe|<pw1_dbe>pw1_dbe|<pw2_sbe>pw2_sbe|<pw2_dbe>pw2_dbe|<pw3_sbe>pw3_sbe|<pw3_dbe>pw3_dbe"];
- * cvmx_ciu2_src_pp0_ip2_rml:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_ciu2_src_pp0_ip2_rml:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_sso_err [label="SSO_ERR|<iop>iop|<fidx_dbe>fidx_dbe|<idx_sbe>idx_sbe|<pnd_dbe0>pnd_dbe0|<oth_sbe1>oth_sbe1|<oth_dbe1>oth_dbe1|<oth_sbe0>oth_sbe0|<oth_dbe0>oth_dbe0|<pnd_sbe1>pnd_sbe1|<pnd_dbe1>pnd_dbe1|<pnd_sbe0>pnd_sbe0|<fpe>fpe|<awe>awe|<bfp>bfp|<idx_dbe>idx_dbe|<fidx_sbe>fidx_sbe"];
- * cvmx_ciu2_src_pp0_ip2_rml:sso:e -> cvmx_sso_err [label="sso"];
- * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad|<pipe_err>pipe_err"];
- * cvmx_ciu2_src_pp0_ip2_rml:sli:e -> cvmx_sli_int_sum [label="sli"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_ciu2_src_pp0_ip2_rml:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_ciu2_src_pp0_ip2_rml:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr|<dc1perr>dc1perr|<dc2perr>dc2perr|<dlc0_ovferr>dlc0_ovferr|<dlc1_ovferr>dlc1_ovferr|<dfanxm>dfanxm|<replerr>replerr"];
- * cvmx_ciu2_src_pp0_ip2_rml:dfa:e -> cvmx_dfa_error [label="dfa"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero|<loopback>loopback"];
- * cvmx_ciu2_src_pp0_ip2_rml:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
- * cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
- * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
- * cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
- * cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
- * cvmx_ciu2_src_pp0_ip2_rml:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
- * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
- * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
- * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
- * cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_rml [label="root"];
- * cvmx_ciu2_src_pp0_ip2_mio [label="CIU2_SRC_PPX_IP2_MIO(0)|<rst>rst|<nand>nand|<mio>mio"];
- * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
- * cvmx_ciu2_src_pp0_ip2_mio:rst:e -> cvmx_mio_rst_int [label="rst"];
- * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
- * cvmx_ciu2_src_pp0_ip2_mio:nand:e -> cvmx_ndf_int [label="nand"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_ciu2_src_pp0_ip2_mio:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_root:root:e -> cvmx_ciu2_src_pp0_ip2_mio [label="root"];
- * cvmx_ciu2_sum_pp0_ip2 [label="CIU2_SUM_PPX_IP2(0)|<mem>mem|<pkt>pkt"];
- * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc0_int [label="mem"];
- * cvmx_lmc1_int [label="LMCX_INT(1)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc1_int [label="mem"];
- * cvmx_lmc2_int [label="LMCX_INT(2)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc2_int [label="mem"];
- * cvmx_lmc3_int [label="LMCX_INT(3)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu2_sum_pp0_ip2:mem:e -> cvmx_lmc3_int [label="mem"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx0_int_reg [label="pkt"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx1_int_reg [label="pkt"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx2_int_reg [label="pkt"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_rx3_int_reg [label="pkt"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx1_rx0_int_reg [label="pkt"];
- * cvmx_gmx2_rx0_int_reg [label="GMXX_RXX_INT_REG(0,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx0_int_reg [label="pkt"];
- * cvmx_gmx2_rx1_int_reg [label="GMXX_RXX_INT_REG(1,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx1_int_reg [label="pkt"];
- * cvmx_gmx2_rx2_int_reg [label="GMXX_RXX_INT_REG(2,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx2_int_reg [label="pkt"];
- * cvmx_gmx2_rx3_int_reg [label="GMXX_RXX_INT_REG(3,2)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_rx3_int_reg [label="pkt"];
- * cvmx_gmx3_rx0_int_reg [label="GMXX_RXX_INT_REG(0,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx0_int_reg [label="pkt"];
- * cvmx_gmx3_rx1_int_reg [label="GMXX_RXX_INT_REG(1,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx1_int_reg [label="pkt"];
- * cvmx_gmx3_rx2_int_reg [label="GMXX_RXX_INT_REG(2,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx2_int_reg [label="pkt"];
- * cvmx_gmx3_rx3_int_reg [label="GMXX_RXX_INT_REG(3,3)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_rx3_int_reg [label="pkt"];
- * cvmx_gmx4_rx0_int_reg [label="GMXX_RXX_INT_REG(0,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx0_int_reg [label="pkt"];
- * cvmx_gmx4_rx1_int_reg [label="GMXX_RXX_INT_REG(1,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx1_int_reg [label="pkt"];
- * cvmx_gmx4_rx2_int_reg [label="GMXX_RXX_INT_REG(2,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx2_int_reg [label="pkt"];
- * cvmx_gmx4_rx3_int_reg [label="GMXX_RXX_INT_REG(3,4)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_rx3_int_reg [label="pkt"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx0_tx_int_reg [label="pkt"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx1_tx_int_reg [label="pkt"];
- * cvmx_gmx2_tx_int_reg [label="GMXX_TX_INT_REG(2)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx2_tx_int_reg [label="pkt"];
- * cvmx_gmx3_tx_int_reg [label="GMXX_TX_INT_REG(3)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx3_tx_int_reg [label="pkt"];
- * cvmx_gmx4_tx_int_reg [label="GMXX_TX_INT_REG(4)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_gmx4_tx_int_reg [label="pkt"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int0_reg [label="pkt"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int1_reg [label="pkt"];
- * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int2_reg [label="pkt"];
- * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs0_int3_reg [label="pkt"];
- * cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs1_int0_reg [label="pkt"];
- * cvmx_pcs2_int0_reg [label="PCSX_INTX_REG(0,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int0_reg [label="pkt"];
- * cvmx_pcs2_int1_reg [label="PCSX_INTX_REG(1,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int1_reg [label="pkt"];
- * cvmx_pcs2_int2_reg [label="PCSX_INTX_REG(2,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int2_reg [label="pkt"];
- * cvmx_pcs2_int3_reg [label="PCSX_INTX_REG(3,2)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs2_int3_reg [label="pkt"];
- * cvmx_pcs3_int0_reg [label="PCSX_INTX_REG(0,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int0_reg [label="pkt"];
- * cvmx_pcs3_int1_reg [label="PCSX_INTX_REG(1,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int1_reg [label="pkt"];
- * cvmx_pcs3_int2_reg [label="PCSX_INTX_REG(2,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int2_reg [label="pkt"];
- * cvmx_pcs3_int3_reg [label="PCSX_INTX_REG(3,3)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs3_int3_reg [label="pkt"];
- * cvmx_pcs4_int0_reg [label="PCSX_INTX_REG(0,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int0_reg [label="pkt"];
- * cvmx_pcs4_int1_reg [label="PCSX_INTX_REG(1,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int1_reg [label="pkt"];
- * cvmx_pcs4_int2_reg [label="PCSX_INTX_REG(2,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int2_reg [label="pkt"];
- * cvmx_pcs4_int3_reg [label="PCSX_INTX_REG(3,4)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcs4_int3_reg [label="pkt"];
- * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx0_int_reg [label="pkt"];
- * cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx1_int_reg [label="pkt"];
- * cvmx_pcsx2_int_reg [label="PCSXX_INT_REG(2)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx2_int_reg [label="pkt"];
- * cvmx_pcsx3_int_reg [label="PCSXX_INT_REG(3)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx3_int_reg [label="pkt"];
- * cvmx_pcsx4_int_reg [label="PCSXX_INT_REG(4)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
- * cvmx_ciu2_sum_pp0_ip2:pkt:e -> cvmx_pcsx4_int_reg [label="pkt"];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx2_rx0_int_reg [style=invis];
- * cvmx_gmx2_rx0_int_reg -> cvmx_gmx2_rx1_int_reg [style=invis];
- * cvmx_gmx2_rx1_int_reg -> cvmx_gmx2_rx2_int_reg [style=invis];
- * cvmx_gmx2_rx2_int_reg -> cvmx_gmx2_rx3_int_reg [style=invis];
- * cvmx_gmx2_rx3_int_reg -> cvmx_gmx3_rx0_int_reg [style=invis];
- * cvmx_gmx3_rx0_int_reg -> cvmx_gmx3_rx1_int_reg [style=invis];
- * cvmx_gmx3_rx1_int_reg -> cvmx_gmx3_rx2_int_reg [style=invis];
- * cvmx_gmx3_rx2_int_reg -> cvmx_gmx3_rx3_int_reg [style=invis];
- * cvmx_gmx3_rx3_int_reg -> cvmx_gmx4_rx0_int_reg [style=invis];
- * cvmx_gmx4_rx0_int_reg -> cvmx_gmx4_rx1_int_reg [style=invis];
- * cvmx_gmx4_rx1_int_reg -> cvmx_gmx4_rx2_int_reg [style=invis];
- * cvmx_gmx4_rx2_int_reg -> cvmx_gmx4_rx3_int_reg [style=invis];
- * cvmx_gmx4_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_gmx0_tx_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_gmx1_tx_int_reg -> cvmx_gmx2_tx_int_reg [style=invis];
- * cvmx_gmx2_tx_int_reg -> cvmx_gmx3_tx_int_reg [style=invis];
- * cvmx_gmx3_tx_int_reg -> cvmx_gmx4_tx_int_reg [style=invis];
- * cvmx_gmx4_tx_int_reg -> cvmx_pcs0_int0_reg [style=invis];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
- * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
- * cvmx_pcs0_int3_reg -> cvmx_pcs1_int0_reg [style=invis];
- * cvmx_pcs1_int0_reg -> cvmx_pcs2_int0_reg [style=invis];
- * cvmx_pcs2_int0_reg -> cvmx_pcs2_int1_reg [style=invis];
- * cvmx_pcs2_int1_reg -> cvmx_pcs2_int2_reg [style=invis];
- * cvmx_pcs2_int2_reg -> cvmx_pcs2_int3_reg [style=invis];
- * cvmx_pcs2_int3_reg -> cvmx_pcs3_int0_reg [style=invis];
- * cvmx_pcs3_int0_reg -> cvmx_pcs3_int1_reg [style=invis];
- * cvmx_pcs3_int1_reg -> cvmx_pcs3_int2_reg [style=invis];
- * cvmx_pcs3_int2_reg -> cvmx_pcs3_int3_reg [style=invis];
- * cvmx_pcs3_int3_reg -> cvmx_pcs4_int0_reg [style=invis];
- * cvmx_pcs4_int0_reg -> cvmx_pcs4_int1_reg [style=invis];
- * cvmx_pcs4_int1_reg -> cvmx_pcs4_int2_reg [style=invis];
- * cvmx_pcs4_int2_reg -> cvmx_pcs4_int3_reg [style=invis];
- * cvmx_pcs4_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
- * cvmx_pcsx0_int_reg -> cvmx_pcsx1_int_reg [style=invis];
- * cvmx_pcsx1_int_reg -> cvmx_pcsx2_int_reg [style=invis];
- * cvmx_pcsx2_int_reg -> cvmx_pcsx3_int_reg [style=invis];
- * cvmx_pcsx3_int_reg -> cvmx_pcsx4_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_ciu2_sum_pp0_ip2 [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cn68xxp1(void);
-
-int cvmx_error_initialize_cn68xxp1(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU2_SRC_PPX_IP2_PKT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIXX_ISR(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<0 /* odblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<0 /* ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<40 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
- " with a value greater than the remaining #of\n"
- " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]\n"
- " bit is set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
- " and the local interrupt mask bit(OVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of ODBELL writes), and ensure that\n"
- " future ODBELL writes don't exceed the size of the\n"
- " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
- " SW must reclaim O-Ring Entries by writing to the\n"
- " MIX_ORCNT[ORCNT]. .\n"
- " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the O-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<1 /* idblovf */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<1 /* ivfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<40 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
- " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
- " with a value greater than the remaining #of\n"
- " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
- " the following occurs:\n"
- " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
- " 2) The ODBLOVF is set and the CIU2_RAW_PKT[MII]\n"
- " bit is set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
- " If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
- " and the local interrupt mask bit(IVFENA) is set, than an\n"
- " interrupt is reported for this event.\n"
- " SW should keep track of the #I-Ring Entries in use\n"
- " (ie: cumulative # of IDBELL writes), and ensure that\n"
- " future IDBELL writes don't exceed the size of the\n"
- " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
- " SW must reclaim I-Ring Entries by keeping track of the\n"
- " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
- " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
- " total #packets(not IRing Entries) and SW must further\n"
- " keep track of the # of I-Ring Entries associated with\n"
- " each packet as they are processed.\n"
- " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
- " If it occurs, it's an indication that SW has\n"
- " overwritten the I-Ring buffer, and the only recourse\n"
- " is a HW reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<4 /* data_drp */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<4 /* data_drpena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<40 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
- " If this does occur, the DATA_DRP is set and the\n"
- " CIU2_RAW_PKT[MII] bit is set.\n"
- " If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII])\n"
- " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
- " interrupt is reported for this event.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<5 /* irun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<5 /* irunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<40 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_IRCNT[IRCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
- " NOTE: If an IRUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIXX_ISR(0);
- info.status_mask = 1ull<<6 /* orun */;
- info.enable_addr = CVMX_MIXX_INTENA(0);
- info.enable_mask = 1ull<<6 /* orunena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<40 /* mii */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
- " If SW writes a larger value than what is currently\n"
- " in the MIX_ORCNT[ORCNT], then HW will report the\n"
- " underflow condition.\n"
- " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
- " NOTE: If an ORUN underflow condition is detected,\n"
- " the integrity of the MIX/AGL HW state has\n"
- " been compromised. To recover, SW must issue a\n"
- " software reset sequence (see: MIX_CTL[RESET]\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_BAD_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<32 /* ovrflw */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<33 /* txpop */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<34 /* txpsh */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<35 /* ovrflw1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<36 /* txpop1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 1ull<<37 /* txpsh1 */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_BAD_REG;
- info.status_mask = 0x3ull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
- " In MII/RGMII, one bit per port\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_RXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_AGL_GMX_TX_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
- info.status_mask = 0x3ull<<2 /* undflw */;
- info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
- info.enable_mask = 0x3ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_MGMT_PORT;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<32 /* agl */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_GBL_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_GBL_INT;
- info.status_mask = 1ull<<0 /* rxf_lnk0_perr */;
- info.enable_addr = CVMX_ILK_GBL_INT_EN;
- info.enable_mask = 1ull<<0 /* rxf_lnk0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_GBL_INT[RXF_LNK0_PERR]: RXF parity error occurred on RxLink0 packet data. Packet will\n"
- " be marked with error at eop\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_GBL_INT;
- info.status_mask = 1ull<<1 /* rxf_lnk1_perr */;
- info.enable_addr = CVMX_ILK_GBL_INT_EN;
- info.enable_mask = 1ull<<1 /* rxf_lnk1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_GBL_INT[RXF_LNK1_PERR]: RXF parity error occurred on RxLink1 packet data\n"
- " Packet will be marked with error at eop\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_GBL_INT;
- info.status_mask = 1ull<<2 /* rxf_ctl_perr */;
- info.enable_addr = CVMX_ILK_GBL_INT_EN;
- info.enable_mask = 1ull<<2 /* rxf_ctl_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_GBL_INT[RXF_CTL_PERR]: RXF parity error occurred on sideband control signals. Data\n"
- " cycle will be dropped.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_GBL_INT;
- info.status_mask = 1ull<<3 /* rxf_pop_empty */;
- info.enable_addr = CVMX_ILK_GBL_INT_EN;
- info.enable_mask = 1ull<<3 /* rxf_pop_empty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_GBL_INT[RXF_POP_EMPTY]: RXF underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_GBL_INT;
- info.status_mask = 1ull<<4 /* rxf_push_full */;
- info.enable_addr = CVMX_ILK_GBL_INT_EN;
- info.enable_mask = 1ull<<4 /* rxf_push_full */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_GBL_INT[RXF_PUSH_FULL]: RXF overflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_TXX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(0);
- info.status_mask = 1ull<<0 /* txf_err */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* txf_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(0)[TXF_ERR]: TX fifo parity error occurred. At EOP time, EOP_Format will\n"
- " reflect the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(0);
- info.status_mask = 1ull<<1 /* bad_seq */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(0)[BAD_SEQ]: Received sequence is not SOP followed by 0 or more data cycles\n"
- " followed by EOP. PKO config assigned multiple engines to the\n"
- " same ILK Tx Link.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(0);
- info.status_mask = 1ull<<2 /* bad_pipe */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* bad_pipe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(0)[BAD_PIPE]: Received a PKO port-pipe out of the range specified by\n"
- " ILK_TXX_PIPE\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(0);
- info.status_mask = 1ull<<3 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(0);
- info.enable_mask = 1ull<<3 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(0)[STAT_CNT_OVFL]: Statistics counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_TXX_INT(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(1);
- info.status_mask = 1ull<<0 /* txf_err */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* txf_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(1)[TXF_ERR]: TX fifo parity error occurred. At EOP time, EOP_Format will\n"
- " reflect the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(1);
- info.status_mask = 1ull<<1 /* bad_seq */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(1)[BAD_SEQ]: Received sequence is not SOP followed by 0 or more data cycles\n"
- " followed by EOP. PKO config assigned multiple engines to the\n"
- " same ILK Tx Link.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(1);
- info.status_mask = 1ull<<2 /* bad_pipe */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(1);
- info.enable_mask = 1ull<<2 /* bad_pipe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(1)[BAD_PIPE]: Received a PKO port-pipe out of the range specified by\n"
- " ILK_TXX_PIPE\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_TXX_INT(1);
- info.status_mask = 1ull<<3 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_TXX_INT_EN(1);
- info.enable_mask = 1ull<<3 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_TXX_INT(1)[STAT_CNT_OVFL]: Statistics counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RXX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<0 /* lane_align_fail */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* lane_align_fail */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[LANE_ALIGN_FAIL]: Lane Alignment fails (4 tries). Hardware will repeat lane\n"
- " alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA]\n"
- " is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<1 /* crc24_err */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* crc24_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[CRC24_ERR]: Burst CRC24 error. All open packets will be receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<2 /* word_sync_done */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* word_sync_done */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[WORD_SYNC_DONE]: All enabled lanes have achieved word boundary lock and\n"
- " scrambler synchronization. Lane alignment may now be enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<3 /* lane_align_done */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<3 /* lane_align_done */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[LANE_ALIGN_DONE]: Lane alignment successful\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<4 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<4 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[STAT_CNT_OVFL]: Statistics counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<5 /* lane_bad_word */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<5 /* lane_bad_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[LANE_BAD_WORD]: A lane encountered either a bad 64B/67B codeword or an unknown\n"
- " control word type.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<6 /* pkt_drop_rxf */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<6 /* pkt_drop_rxf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[PKT_DROP_RXF]: Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(0);
- info.status_mask = 1ull<<7 /* pkt_drop_rid */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(0);
- info.enable_mask = 1ull<<7 /* pkt_drop_rid */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(0)[PKT_DROP_RID]: Entire packet dropped due to the lack of reassembly-ids or\n"
- " because ILK_RXX_CFG1[PKT_ENA]=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RXX_INT(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<0 /* lane_align_fail */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* lane_align_fail */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[LANE_ALIGN_FAIL]: Lane Alignment fails (4 tries). Hardware will repeat lane\n"
- " alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA]\n"
- " is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<1 /* crc24_err */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* crc24_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[CRC24_ERR]: Burst CRC24 error. All open packets will be receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<2 /* word_sync_done */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<2 /* word_sync_done */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[WORD_SYNC_DONE]: All enabled lanes have achieved word boundary lock and\n"
- " scrambler synchronization. Lane alignment may now be enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<3 /* lane_align_done */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<3 /* lane_align_done */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[LANE_ALIGN_DONE]: Lane alignment successful\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<4 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<4 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[STAT_CNT_OVFL]: Statistics counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<5 /* lane_bad_word */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<5 /* lane_bad_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[LANE_BAD_WORD]: A lane encountered either a bad 64B/67B codeword or an unknown\n"
- " control word type.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<6 /* pkt_drop_rxf */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<6 /* pkt_drop_rxf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[PKT_DROP_RXF]: Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RXX_INT(1);
- info.status_mask = 1ull<<7 /* pkt_drop_rid */;
- info.enable_addr = CVMX_ILK_RXX_INT_EN(1);
- info.enable_mask = 1ull<<7 /* pkt_drop_rid */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RXX_INT(1)[PKT_DROP_RID]: Entire packet dropped due to the lack of reassembly-ids or\n"
- " because ILK_RXX_CFG1[PKT_ENA]=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(0);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(0);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(0)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(1);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(1);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(1)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(2);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(2);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(2)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(3);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(3);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(3)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(4);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(4);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 4;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(4)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(5) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(5);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(5);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 5;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(5)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(6) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(6);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(6);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 6;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(6)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ILK_RX_LNEX_INT(7) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<0 /* serdes_lock_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<0 /* serdes_lock_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[SERDES_LOCK_LOSS]: Rx SERDES loses lock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<1 /* bdry_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<1 /* bdry_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[BDRY_SYNC_LOSS]: Rx logic loses word boundary sync (16 tries). Hardware will\n"
- " automatically attempt to regain word boundary sync\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<2 /* crc32_err */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<2 /* crc32_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[CRC32_ERR]: Diagnostic CRC32 errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<3 /* ukwn_cntl_word */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[UKWN_CNTL_WORD]: Unknown framing control word. Block type does not match any of\n"
- " (SYNC,SCRAM,SKIP,DIAG)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<4 /* scrm_sync_loss */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<4 /* scrm_sync_loss */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[SCRM_SYNC_LOSS]: 4 consecutive bad sync words or 3 consecutive scramble state\n"
- " mismatches\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<5 /* dskew_fifo_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[DSKEW_FIFO_OVFL]: Rx deskew fifo overflow occurred.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<6 /* stat_msg */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<6 /* stat_msg */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[STAT_MSG]: Status bits for the link or a lane transitioned from a '1'\n"
- " (healthy) to a '0' (problem)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<7 /* stat_cnt_ovfl */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[STAT_CNT_OVFL]: Rx lane statistic counter overflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ILK_RX_LNEX_INT(7);
- info.status_mask = 1ull<<8 /* bad_64b67b */;
- info.enable_addr = CVMX_ILK_RX_LNEX_INT_EN(7);
- info.enable_mask = 1ull<<8 /* bad_64b67b */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ILK;
- info.group_index = 7;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_PKT(0);
- info.parent.status_mask = 1ull<<48 /* ilk */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ILK_RX_LNEX_INT(7)[BAD_64B67B]: Bad 64B/67B codeword encountered. Once the bad word reaches\n"
- " the burst control unit (as deonted by\n"
- " ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open\n"
- " packets will receive an error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU2_SRC_PPX_IP2_RML(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<0 /* holerd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<0 /* holerd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<1 /* holewr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<1 /* holewr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<2 /* vrtwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<2 /* vrtwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
- " Set when L2C_VRT_MEM blocked a store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<3 /* vrtidrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<3 /* vrtidrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
- " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
- " store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<4 /* vrtadrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<4 /* vrtadrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
- " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
- " store.\n"
- " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<5 /* vrtpe */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<5 /* vrtpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
- " Whenever an L2C_VRT_MEM read finds a parity error,\n"
- " that L2C_VRT_MEM cannot cause stores to be blocked.\n"
- " Software should correct the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<6 /* bigwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<6 /* bigwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<7 /* bigrd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<7 /* bigrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<48 /* l2c */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(1);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(1);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(1)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(1);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(1)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(1);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(1)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(1);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(1)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(1);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(1)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(1);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(1)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(1);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(1)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(1);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<17 /* tad1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(1)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(3);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(3);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(3)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(3);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(3)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(3);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(3)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(3);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(3)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(3);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(3)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(3);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(3)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(3);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(3)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(3);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<19 /* tad3 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(3)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(2);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(2);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(2)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(2);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(2)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(2);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(2)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(2);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(2)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(2);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(2)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(2);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(2)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(2);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(2)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(2);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<18 /* tad2 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(2)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<28 /* pool0th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<28 /* pool0th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
- " FPA_POOL0_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<29 /* pool1th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<29 /* pool1th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
- " FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<30 /* pool2th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<30 /* pool2th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
- " FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<31 /* pool3th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<31 /* pool3th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
- " FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<32 /* pool4th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<32 /* pool4th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
- " FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<33 /* pool5th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<33 /* pool5th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
- " FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<34 /* pool6th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<34 /* pool6th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
- " FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<35 /* pool7th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<35 /* pool7th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
- " FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<36 /* free0 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<36 /* free0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<37 /* free1 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<37 /* free1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<38 /* free2 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<38 /* free2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<39 /* free3 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<39 /* free3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<40 /* free4 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<40 /* free4 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<41 /* free5 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<41 /* free5 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<42 /* free6 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<42 /* free6 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<43 /* free7 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<43 /* free7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<44 /* free8 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<44 /* free8 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE8]: When a pointer for POOL8 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<45 /* q8_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<45 /* q8_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q8_UND]: Set when a Queue8 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<46 /* q8_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<46 /* q8_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q8_COFF]: Set when a Queue8 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<47 /* q8_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<47 /* q8_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q8_PERR]: Set when a Queue8 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<48 /* pool8th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<48 /* pool8th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL8TH]: Set when FPA_QUE8_AVAILABLE is equal to\n"
- " FPA_POOL8_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<49 /* paddr_e */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<49 /* paddr_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<4 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
- " address range for a pool specified by\n"
- " FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_ZIP_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_ZIP_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_ZIP_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<24 /* zip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n"
- " NOT USED ON o68.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n"
- " NOT USED ON o68.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n"
- " NOT USED ON o68.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n"
- " NOT USED ON o68.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<12 /* sop */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<12 /* sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[SOP]: Set when a SOP is followed by an SOP for the same\n"
- " reasm-id for a packet.\n"
- " The first detected error associated with bits [14:12]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n"
- " Also see IPD_PKT_ERR.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<13 /* eop */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<13 /* eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[EOP]: Set when a EOP is followed by an EOP for the same\n"
- " reasm-id for a packet.\n"
- " The first detected error associated with bits [14:12]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n"
- " Also see IPD_PKT_ERR.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<14 /* dat */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<14 /* dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DAT]: Set when a data arrives before a SOP for the same\n"
- " reasm-id for a packet.\n"
- " The first detected error associated with bits [14:12]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n"
- " Also see IPD_PKT_ERR.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<15 /* pw0_sbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<15 /* pw0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW0_SBE]: Packet memory 0 had ECC SBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<16 /* pw0_dbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<16 /* pw0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW0_DBE]: Packet memory 0 had ECC DBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<17 /* pw1_sbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<17 /* pw1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW1_SBE]: Packet memory 1 had ECC SBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<18 /* pw1_dbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<18 /* pw1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW1_DBE]: Packet memory 1 had ECC DBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<19 /* pw2_sbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<19 /* pw2_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW2_SBE]: Packet memory 2 had ECC SBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<20 /* pw2_dbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<20 /* pw2_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW2_DBE]: Packet memory 2 had ECC DBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<21 /* pw3_sbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<21 /* pw3_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW3_SBE]: Packet memory 3 had ECC SBE.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<22 /* pw3_dbe */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<22 /* pw3_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<5 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PW3_DBE]: Packet memory 3 had ECC DBE.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<29 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_SSO_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 0x7ffull<<32 /* iop */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 0x7ffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<1 /* fidx_dbe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<1 /* fidx_dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[FIDX_DBE]: Double bit error for FIDX RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<2 /* idx_sbe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<2 /* idx_sbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[IDX_SBE]: Single bit error for IDX RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<11 /* pnd_dbe0 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<11 /* pnd_dbe0_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[PND_DBE0]: Double bit error for even PND RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<4 /* oth_sbe1 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<4 /* oth_sbe1_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[OTH_SBE1]: Single bit error for odd OTH RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<5 /* oth_dbe1 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<5 /* oth_dbe1_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[OTH_DBE1]: Double bit error for odd OTH RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<6 /* oth_sbe0 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<6 /* oth_sbe0_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[OTH_SBE0]: Single bit error for even OTH RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<7 /* oth_dbe0 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<7 /* oth_dbe0_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[OTH_DBE0]: Double bit error for even OTH RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<8 /* pnd_sbe1 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<8 /* pnd_sbe1_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[PND_SBE1]: Single bit error for odd PND RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<9 /* pnd_dbe1 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<9 /* pnd_dbe1_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[PND_DBE1]: Double bit error for odd PND RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<10 /* pnd_sbe0 */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<10 /* pnd_sbe0_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[PND_SBE0]: Single bit error for even PND RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<45 /* fpe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<45 /* fpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[FPE]: Free page error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<46 /* awe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<46 /* awe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[AWE]: Out-of-memory error (ADDWQ Request is dropped)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<47 /* bfp */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<47 /* bfp_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[BFP]: Bad Fill Packet error\n"
- " Last byte of the fill packet did not match 8'h1a\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<3 /* idx_dbe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<3 /* idx_dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[IDX_DBE]: Double bit error for IDX RAM\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_SSO_ERR;
- info.status_mask = 1ull<<0 /* fidx_sbe */;
- info.enable_addr = CVMX_SSO_ERR_ENB;
- info.enable_mask = 1ull<<0 /* fidx_sbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<16 /* sso */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR SSO_ERR[FIDX_SBE]: Single bit error for FIDX RAM\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_SLI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<0 /* rml_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
- " within 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<1 /* reserved_1_1 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<1 /* reserved_1_1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<8 /* m0_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<8 /* m0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<9 /* m0_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<9 /* m0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<10 /* m0_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<10 /* m0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<11 /* m0_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<11 /* m0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<12 /* m1_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<12 /* m1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<13 /* m1_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<13 /* m1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<14 /* m1_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<14 /* m1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<15 /* m1_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<15 /* m1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<48 /* pidbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<48 /* pidbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<49 /* psldbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<49 /* psldbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<50 /* pout_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<50 /* pout_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
- " set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<52 /* pgl_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<52 /* pgl_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
- " read this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<53 /* pdi_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<53 /* pdi_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<54 /* pop_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<54 /* pop_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
- " pointer pair this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<55 /* pins_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<55 /* pins_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<56 /* sprt0_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<56 /* sprt0_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<57 /* sprt1_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<57 /* sprt1_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<60 /* ill_pad */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<60 /* ill_pad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
- " range of the Packet-CSR, but for an unused\n"
- " address.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<61 /* pipe_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<61 /* pipe_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<32 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIPE_ERR]: Set when a PIPE value outside range is received.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<30 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<30 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<30 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<30 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<6 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DFA_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<0 /* dblovf */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<0 /* dblina */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
- " When set, the 20b accumulated doorbell register\n"
- " had overflowed (SW wrote too many doorbell requests).\n"
- " If the DBLINA had previously been enabled(set),\n"
- " an interrupt will be posted. Software can clear\n"
- " the interrupt by writing a 1 to this register bit.\n"
- " NOTE: Detection of a Doorbell Register overflow\n"
- " is a catastrophic error which may leave the DFA\n"
- " HW in an unrecoverable state.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 0x7ull<<1 /* dc0perr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 0x7ull<<1 /* dc0pena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DC0PERR]: Cluster#0 RAM[3:1] Parity Error Detected\n"
- " See also DFA_DTCFADR register which contains the\n"
- " failing addresses for the internal node cache RAMs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 0x7ull<<4 /* dc1perr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 0x7ull<<4 /* dc1pena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DC1PERR]: Cluster#1 RAM[3:1] Parity Error Detected\n"
- " See also DFA_DTCFADR register which contains the\n"
- " failing addresses for the internal node cache RAMs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 0x7ull<<7 /* dc2perr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 0x7ull<<7 /* dc2pena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DC2PERR]: Cluster#2 RAM[3:1] Parity Error Detected\n"
- " See also DFA_DTCFADR register which contains the\n"
- " failing addresses for the internal node cache RAMs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<13 /* dlc0_ovferr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<13 /* dlc0_ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DLC0_OVFERR]: DLC0 Fifo Overflow Error Detected\n"
- " This condition should NEVER architecturally occur, and\n"
- " is here in case HW credit/debit scheme is not working.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<14 /* dlc1_ovferr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<14 /* dlc1_ovfena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DLC1_OVFERR]: DLC1 Fifo Overflow Error Detected\n"
- " This condition should NEVER architecturally occur, and\n"
- " is here in case HW credit/debit scheme is not working.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<17 /* dfanxm */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<17 /* dfanxmena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[DFANXM]: DFA Non-existent Memory Access\n"
- " For o68: DTEs (and backdoor CSR DFA Memory REGION reads)\n"
- " have access to the following 38bit L2/DRAM address space\n"
- " which maps to a 37bit physical DDR3 SDRAM address space.\n"
- " see:\n"
- " DR0: 0x0 0000 0000 0000 to 0x0 0000 0FFF FFFF\n"
- " maps to lower 256MB of physical DDR3 SDRAM\n"
- " DR1: 0x0 0000 2000 0000 to 0x0 0020 0FFF FFFF\n"
- " maps to upper 127.75GB of DDR3 SDRAM\n"
- " L2/DRAM address space Physical DDR3 SDRAM Address space\n"
- " (38bit address) (37bit address)\n"
- " +-----------+ 0x0020.0FFF.FFFF\n"
- " |\n"
- " === DR1 === +-----------+ 0x001F.FFFF.FFFF\n"
- " (128GB-256MB)| | |\n"
- " | | => | | (128GB-256MB)\n"
- " +-----------+ 0x0000.1FFF.FFFF | DR1\n"
- " 256MB | HOLE | (DO NOT USE) |\n"
- " +-----------+ 0x0000.0FFF.FFFF +-----------+ 0x0000.0FFF.FFFF\n"
- " 256MB | DR0 | | DR0 | (256MB)\n"
- " +-----------+ 0x0000.0000.0000 +-----------+ 0x0000.0000.0000\n"
- " In the event the DFA generates a reference to the L2/DRAM\n"
- " address hole (0x0000.0FFF.FFFF - 0x0000.1FFF.FFFF) or to\n"
- " an address above 0x0020.0FFF.FFFF, the DFANXM programmable\n"
- " interrupt bit will be set.\n"
- " SWNOTE: Both the 1) SW DFA Graph compiler and the 2) SW NCB-Direct CSR\n"
- " accesses to DFA Memory REGION MUST avoid making references\n"
- " to these non-existent memory regions.\n"
- " NOTE: If DFANXM is set during a DFA Graph Walk operation,\n"
- " then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
- " If DFANXM is set during a NCB-Direct CSR read access to DFA\n"
- " Memory REGION, then the CSR read response data is forced to\n"
- " 128'hBADE_FEED_DEAD_BEEF_FACE_CAFE_BEAD_C0DE. (NOTE: the QW\n"
- " being accessed, either the upper or lower QW will be returned).\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DFA_ERROR;
- info.status_mask = 1ull<<18 /* replerr */;
- info.enable_addr = CVMX_DFA_INTMSK;
- info.enable_mask = 1ull<<18 /* replerrena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<40 /* dfa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DFA_ERROR[REPLERR]: DFA Illegal Replication Factor Error\n"
- " For o68: DFA only supports 1x, 2x, and 4x port replication.\n"
- " Legal configurations for memory are to support 2 port or\n"
- " 4 port configurations.\n"
- " The REPLERR interrupt will be set in the following illegal\n"
- " configuration cases:\n"
- " 1) An 8x replication factor is detected for any memory reference.\n"
- " 2) A 4x replication factor is detected for any memory reference\n"
- " when only 2 memory ports are enabled.\n"
- " NOTE: If REPLERR is set during a DFA Graph Walk operation,\n"
- " then the walk will prematurely terminate with RWORD0[REA]=ERR.\n"
- " If REPLERR is set during a NCB-Direct CSR read access to DFA\n"
- " Memory REGION, then the CSR read response data is UNPREDICTABLE.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<7 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<7 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<7 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<3 /* loopback */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<3 /* loopback */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<7 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[LOOPBACK]: A packet was sent to an illegal loopback port\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<0 /* nderr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<0 /* nderr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
- " DPI received a NCB transaction on the outbound\n"
- " bus to the DPI deviceID, but the command was not\n"
- " recognized.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<1 /* nfovr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<1 /* nfovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
- " DPI can store upto 16 CSR request. The FIFO will\n"
- " overflow if that number is exceeded.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 0xffull<<8 /* dmadbo */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 0xffull<<8 /* dmadbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
- " DPI has a 32-bit counter for each request's queue\n"
- " outstanding doorbell counts. Interrupt will fire\n"
- " if the count overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<16 /* req_badadr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<16 /* req_badadr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch to the NULL pointer.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<17 /* req_badlen */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<17 /* req_badlen */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch with length of zero.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<18 /* req_ovrflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<18 /* req_ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<19 /* req_undflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<19 /* req_undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO underflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<20 /* req_anull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<20 /* req_anull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
- " Fetched instruction word was 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<21 /* req_inull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<21 /* req_inull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
- " Next pointer was NULL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<22 /* req_badfil */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<22 /* req_badfil */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
- " Instruction fill when none outstanding.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<24 /* sprt0_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<24 /* sprt0_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<25 /* sprt1_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<25 /* sprt1_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_PKT_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_PKT_ERR_RSP;
- info.status_mask = 1ull<<0 /* pkterr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
- " the I/O subsystem.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RSP;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
- " ErrorResponse from the I/O subsystem.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RST */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RST;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_RML(0);
- info.parent.status_mask = 1ull<<33 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
- " instruction because the source or destination\n"
- " was in reset.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU2_SRC_PPX_IP2_MIO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_RST_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<0 /* rst_link0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<0 /* rst_link0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<63 /* rst */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL0[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<1 /* rst_link1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<1 /* rst_link1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<63 /* rst */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL1[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<8 /* perst0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<8 /* perst0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<63 /* rst */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
- " and MIO_RST_CTL0[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<9 /* perst1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<9 /* perst1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<63 /* rst */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
- " and MIO_RST_CTL1[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_NDF_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<2 /* wdog */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<2 /* wdog */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<16 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<3 /* sm_bad */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<3 /* sm_bad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<16 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<4 /* ecc_1bit */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<4 /* ecc_1bit */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<16 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<5 /* ecc_mult */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<5 /* ecc_mult */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<16 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NDF_INT;
- info.status_mask = 1ull<<6 /* ovrf */;
- info.enable_addr = CVMX_NDF_INT_EN;
- info.enable_mask = 1ull<<6 /* ovrf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<16 /* nand */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
- " fatal error.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<17 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SRC_PPX_IP2_MIO(0);
- info.parent.status_mask = 1ull<<17 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU2_SUM_PPX_IP2(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(1);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(1);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(1)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(1);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(1)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(1);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(1);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(1)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(2);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(2);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(2)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(2);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(2);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(2)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(2);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(2);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 2;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(2)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(3);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(3);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(3)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(3);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(3);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(3)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(3);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(3);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 3;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<5 /* mem */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(3)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,1);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,1);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,2);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,2);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,2)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,2);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,2);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,2)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,2);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,2);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,2)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,2);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,2);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,2)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,3);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,3);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,3)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,3);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,3);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,3)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,3);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,3);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,3)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,3);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,3);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2864;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,3)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,4);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,4);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,4)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,4);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,4);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,4)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(2,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(2,4);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,4);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(2,4)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(3,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[UNSOP]: Unexpected SOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[UNEOP]: Unexpected EOP\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[UNDAT]: Unexpected Data\n"
- " (XAUI/RXAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(3,4);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,4);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(3,4)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(1);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(1);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(2);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(2);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(2)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(2);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(2);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(2)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(2);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(2);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(2)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(3);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(3);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(3)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(3);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(3);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(3)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(3);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(3);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(3)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(4);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(4);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(4)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(4);
- info.status_mask = 0xfull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(4);
- info.enable_mask = 0xfull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(4)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(4);
- info.status_mask = 0xfull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(4);
- info.enable_mask = 0xfull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(4)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2064;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2080;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2096;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,1);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,1);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,2);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,2);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,2)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,2);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,2);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2576;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,2)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,2);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,2);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2592;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,2)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,2);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,2);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2608;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,2)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,3);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,3);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,3)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,3);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,3);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2832;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,3)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,3);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,3);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2848;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,3)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,3);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,3);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2664;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,3)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,4);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,4);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,4)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,4);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,4);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3088;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,4)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(2,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(2,4);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,4);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3104;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(2,4)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(3,4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(3,4);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,4);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3120;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(3,4)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(0);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2048;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(1);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(1);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2368;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(2);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(2);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2560;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(2)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(3);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(3);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 2816;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(3)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSXX_INT_REG(4) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<0 /* txflt */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<0 /* txflt_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[TXFLT]: None defined at this time, always 0x0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<1 /* rxbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<1 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[RXBAD]: Set when RX state machine in bad state\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<2 /* rxsynbad */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<2 /* rxsynbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
- " in one of the 4 xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<3 /* bitlckls */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<3 /* bitlckls_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<4 /* synlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<4 /* synlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<5 /* algnlos */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<5 /* algnlos_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSXX_INT_REG(4);
- info.status_mask = 1ull<<6 /* dbg_sync */;
- info.enable_addr = CVMX_PCSXX_INT_EN_REG(4);
- info.enable_mask = 1ull<<6 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 3072;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU2_SUM_PPX_IP2(0);
- info.parent.status_mask = 1ull<<6 /* pkt */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSXX_INT_REG(4)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error-init-cnf71xx.c b/sys/contrib/octeon-sdk/cvmx-error-init-cnf71xx.c
deleted file mode 100644
index 6af2248..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error-init-cnf71xx.c
+++ /dev/null
@@ -1,5784 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Automatically generated error messages for cnf71xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision: 69515 $<hr>
- *
- * <hr><h2>Error tree for CNF71XX</h2>
- * @dot
- * digraph cnf71xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<gpio>gpio|<pcm>pcm"];
- * cvmx_pcm0_int_sum [label="PCMX_INT_SUM(0)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm0_int_sum [label="pcm"];
- * cvmx_pcm1_int_sum [label="PCMX_INT_SUM(1)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm1_int_sum [label="pcm"];
- * cvmx_pcm2_int_sum [label="PCMX_INT_SUM(2)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm2_int_sum [label="pcm"];
- * cvmx_pcm3_int_sum [label="PCMX_INT_SUM(3)|<fsyncmissed>fsyncmissed|<fsyncextra>fsyncextra|<txempty>txempty|<rxovf>rxovf"];
- * cvmx_ciu_int0_sum0:pcm:e -> cvmx_pcm3_int_sum [label="pcm"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<pem1>pem1|<gmx0>gmx0|<mio>mio|<ipd>ipd|<tim>tim|<pow>pow|<pem0>pem0|<pko>pko|<asxpcs0>asxpcs0|<sli>sli|<key>key|<usb>usb|<pip>pip|<fpa>fpa|<lmc0>lmc0|<iob>iob|<dpi>dpi|<rad>rad"];
- * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
- * cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
- * cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
- * cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
- * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
- * cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
- * cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
- * cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
- * cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
- * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
- * cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
- * cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
- * cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
- * cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
- * cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
- * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
- * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
- * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<m2_up_b0>m2_up_b0|<m2_up_wi>m2_up_wi|<m2_un_b0>m2_un_b0|<m2_un_wi>m2_un_wi|<m3_up_b0>m3_up_b0|<m3_up_wi>m3_up_wi|<m3_un_b0>m3_un_b0|<m3_un_wi>m3_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<sprt2_err>sprt2_err|<sprt3_err>sprt3_err|<ill_pad>ill_pad"];
- * cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
- * cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
- * cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<paddr_e>paddr_e"];
- * cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
- * cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
- * cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst|<sprt2_rst>sprt2_rst|<sprt3_rst>sprt3_rst"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
- * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
- * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
- * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
- * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
- * cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
- * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
- * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
- * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
- * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
- * cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
- * }
- * @enddot
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-csr-typedefs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#endif
-
-int cvmx_error_initialize_cnf71xx(void);
-
-int cvmx_error_initialize_cnf71xx(void)
-{
- cvmx_error_info_t info;
- int fail = 0;
-
- /* CVMX_CIU_INTX_SUM0(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0xffffull<<16 /* gpio */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR CIU_INTX_SUM0(0)[GPIO]: 16 GPIO interrupts\n"
- " When GPIO_MULTI_CAST[EN] == 1\n"
- " Write 1 to clear either the per PP or common GPIO\n"
- " edge-triggered interrupts,depending on mode.\n"
- " See GPIO_MULTI_CAST for all details.\n"
- " When GPIO_MULTI_CAST[EN] == 0\n"
- " Read Only, retain the same behavior as o63.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[FSYNCMISSED]: FSYNC missed interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[FSYNCEXTRA]: FSYNC extra interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[TXEMPTY]: TX byte was empty when sampled | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(0);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(0)[RXOVF]: RX byte overflowed | NS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[FSYNCMISSED]: FSYNC missed interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[FSYNCEXTRA]: FSYNC extra interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[TXEMPTY]: TX byte was empty when sampled | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(1);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(1)[RXOVF]: RX byte overflowed | NS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(2) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[FSYNCMISSED]: FSYNC missed interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[FSYNCEXTRA]: FSYNC extra interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[TXEMPTY]: TX byte was empty when sampled | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(2);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(2);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(2)[RXOVF]: RX byte overflowed | NS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCMX_INT_SUM(3) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<0 /* fsyncmissed */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<0 /* fsyncmissed */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[FSYNCMISSED]: FSYNC missed interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<1 /* fsyncextra */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<1 /* fsyncextra */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[FSYNCEXTRA]: FSYNC extra interrupt occurred | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<6 /* txempty */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<6 /* txempty */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[TXEMPTY]: TX byte was empty when sampled | NS\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCMX_INT_SUM(3);
- info.status_mask = 1ull<<7 /* rxovf */;
- info.enable_addr = CVMX_PCMX_INT_ENA(3);
- info.enable_mask = 1ull<<7 /* rxovf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
- info.parent.status_mask = 1ull<<57 /* pcm */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCMX_INT_SUM(3)[RXOVF]: RX byte overflowed | NS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_CIU_BLOCK_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_CIU_BLOCK_INT;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<0 /* holerd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<0 /* holerd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<1 /* holewr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<1 /* holewr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<2 /* vrtwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<2 /* vrtwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
- " Set when L2C_VRT_MEM blocked a store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<3 /* vrtidrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<3 /* vrtidrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
- " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
- " store.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<4 /* vrtadrng */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<4 /* vrtadrng */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
- " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
- " store.\n"
- " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<5 /* vrtpe */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<5 /* vrtpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
- " Whenever an L2C_VRT_MEM read finds a parity error,\n"
- " that L2C_VRT_MEM cannot cause stores to be blocked.\n"
- " Software should correct the error.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<6 /* bigwr */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<6 /* bigwr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 1ull<<7 /* bigrd */;
- info.enable_addr = CVMX_L2C_INT_ENA;
- info.enable_mask = 1ull<<7 /* bigrd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_INT_REG;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_TADX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<0 /* l2dsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<0 /* l2dsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<1 /* l2ddbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<1 /* l2ddbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<2 /* tagsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<2 /* tagsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[SBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<3 /* tagdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<3 /* tagdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TTGX[DBE]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<4 /* vbfsbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<4 /* vbfsbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<5 /* vbfdbe */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<5 /* vbfdbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
- " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
- " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<6 /* noway */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<6 /* noway */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
- " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
- " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<7 /* rddislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<7 /* rddislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
- " A DRAM read arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_TADX_INT(0);
- info.status_mask = 1ull<<8 /* wrdislmc */;
- info.enable_addr = CVMX_L2C_TADX_IEN(0);
- info.enable_mask = 1ull<<8 /* wrdislmc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
- " A DRAM write arrived before the LMC(s) were enabled\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TDTX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<60 /* vsbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<61 /* vdbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TDTX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_L2C_ERR_TTGX(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<61 /* noway */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
- " L2C sets NOWAY during its processing of a\n"
- " transaction whenever it needed/wanted to allocate\n"
- " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
- " is (generally) not an indication that L2C failed to\n"
- " complete transactions. Rather, it is a hint of\n"
- " possible performance degradation. (For example, L2C\n"
- " must read-modify-write DRAM for every transaction\n"
- " that updates some, but not all, of the bytes in a\n"
- " cache block, misses in the L2 cache, and cannot\n"
- " allocate a WAY.) There is one \"failure\" case where\n"
- " L2C will set NOWAY: when it cannot leave a block\n"
- " locked in the L2 cache as part of a LCKL2\n"
- " transaction.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<62 /* sbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2C_ERR_TTGX(0);
- info.status_mask = 1ull<<63 /* dbe */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_L2C_INT_REG;
- info.parent.status_mask = 1ull<<16 /* tad0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_INT_SUM(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<1 /* se */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<1 /* se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
- " (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<4 /* up_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<4 /* up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<5 /* up_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<5 /* up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<6 /* up_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<6 /* up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<7 /* un_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<7 /* un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<8 /* un_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<8 /* un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<9 /* un_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<9 /* un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<11 /* rdlk */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<11 /* rdlk */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<12 /* crs_er */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<12 /* crs_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 1ull<<13 /* crs_dr */;
- info.enable_addr = CVMX_PEMX_INT_ENB(1);
- info.enable_mask = 1ull<<13 /* crs_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(1);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<26 /* pem1 */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_DBG_INFO(1) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(1);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_BAD_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<2 /* out_ovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<22 /* loststat */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
- " In SGMII, one bit per port\n"
- " In XAUI, only port0 is used\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 1ull<<26 /* statovr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
- " The common FIFO to SGMII and XAUI had an overflow\n"
- " TX Stats are corrupted\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_BAD_REG(0);
- info.status_mask = 0xfull<<27 /* inb_nxa */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_RXX_INT_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<1 /* carext */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<1 /* carext */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<8 /* skperr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<8 /* skperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<10 /* ovrerr */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<10 /* ovrerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
- " This interrupt should never assert\n"
- " (SGMII/1000Base-X only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<20 /* loc_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<20 /* loc_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<21 /* rem_fault */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<21 /* rem_fault */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<22 /* bad_seq */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<22 /* bad_seq */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<23 /* bad_term */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<23 /* bad_term */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
- " than /T/. The error propagation control\n"
- " character /E/ will be included as part of the\n"
- " frame and does not cause a frame termination.\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<24 /* unsop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<24 /* unsop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<25 /* uneop */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<25 /* uneop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<26 /* undat */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<26 /* undat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
- " (XAUI Mode only)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<27 /* hg2fld */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<27 /* hg2fld */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
- " 1) MSG_TYPE field not 6'b00_0000\n"
- " i.e. it is not a FLOW CONTROL message, which\n"
- " is the only defined type for HiGig2\n"
- " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
- " which is the only defined type for HiGig2\n"
- " 3) FC_OBJECT field is neither 4'b0000 for\n"
- " Physical Link nor 4'b0010 for Logical Link.\n"
- " Those are the only two defined types in HiGig2\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
- info.status_mask = 1ull<<28 /* hg2cc */;
- info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
- info.enable_mask = 1ull<<28 /* hg2cc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
- " Set when either CRC8 error detected or when\n"
- " a Control Character is found in the message\n"
- " bytes after the K.SOM\n"
- " NOTE: HG2CC has higher priority than HG2FLD\n"
- " i.e. a HiGig2 message that results in HG2CC\n"
- " getting set, will never set HG2FLD.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_GMXX_TX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pko_nxa */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* pko_nxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0x3ull<<2 /* undflw */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0x3ull<<2 /* undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_GMXX_TX_INT_REG(0);
- info.status_mask = 0x3ull<<20 /* ptp_lost */;
- info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
- info.enable_mask = 0x3ull<<20 /* ptp_lost */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<1 /* gmx0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
- " sent due to XSCOL\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_BOOT_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<0 /* adr_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<0 /* adr_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_BOOT_ERR;
- info.status_mask = 1ull<<1 /* wait_err */;
- info.enable_addr = CVMX_MIO_BOOT_INT;
- info.enable_mask = 1ull<<1 /* wait_int */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_MIO_RST_INT */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<0 /* rst_link0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<0 /* rst_link0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL0[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<1 /* rst_link1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<1 /* rst_link1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
- " MIO_RST_CTL1[RST_LINK]=0. Software must assert\n"
- " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<8 /* perst0 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<8 /* perst0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
- " and MIO_RST_CTL0[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_MIO_RST_INT;
- info.status_mask = 1ull<<9 /* perst1 */;
- info.enable_addr = CVMX_MIO_RST_INT_EN;
- info.enable_mask = 1ull<<9 /* perst1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<0 /* mio */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
- " and MIO_RST_CTL1[RST_CHIP]=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IPD_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<0 /* prc_par0 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<0 /* prc_par0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
- " [31:0] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<1 /* prc_par1 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<1 /* prc_par1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
- " [63:32] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<2 /* prc_par2 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<2 /* prc_par2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
- " [95:64] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<3 /* prc_par3 */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<3 /* prc_par3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
- " [127:96] of the PBM memory.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<4 /* bp_sub */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<4 /* bp_sub */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
- " supplied illegal value.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<5 /* dc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<5 /* dc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<6 /* cc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<6 /* cc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<7 /* c_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<7 /* c_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<8 /* d_coll */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<8 /* d_coll */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
- " collides.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IPD_INT_SUM;
- info.status_mask = 1ull<<9 /* bc_ovr */;
- info.enable_addr = CVMX_IPD_INT_ENB;
- info.enable_mask = 1ull<<9 /* bc_ovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<9 /* ipd */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_TIM_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_TIM_REG_ERROR;
- info.status_mask = 0xffffull<<0 /* mask */;
- info.enable_addr = CVMX_TIM_REG_INT_MASK;
- info.enable_mask = 0xffffull<<0 /* mask */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<11 /* tim */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_POW_ECC_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<0 /* sbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<2 /* sbe_ie */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_sbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<1 /* dbe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<3 /* dbe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_dbe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 1ull<<12 /* rpe */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 1ull<<13 /* rpe_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_rpe;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_POW_ECC_ERR;
- info.status_mask = 0x1fffull<<16 /* iop */;
- info.enable_addr = CVMX_POW_ECC_ERR;
- info.enable_mask = 0x1fffull<<32 /* iop_ie */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<12 /* pow */;
- info.func = __cvmx_error_handle_pow_ecc_err_iop;
- info.user_info = (long)
- "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_INT_SUM(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<1 /* se */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<1 /* se */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
- " (cfg_sys_err_rc)\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<4 /* up_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<4 /* up_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<5 /* up_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<5 /* up_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<6 /* up_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<6 /* up_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<7 /* un_b1 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<7 /* un_b1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
- " is not set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<8 /* un_b2 */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<8 /* un_b2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<9 /* un_bx */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<9 /* un_bx */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<11 /* rdlk */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<11 /* rdlk */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<12 /* crs_er */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<12 /* crs_er */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 1ull<<13 /* crs_dr */;
- info.enable_addr = CVMX_PEMX_INT_ENB(0);
- info.enable_mask = 1ull<<13 /* crs_dr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_INT_SUM(0);
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<25 /* pem0 */;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEMX_DBG_INFO(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<0 /* spoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<0 /* spoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
- " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<2 /* rtlplle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<2 /* rtlplle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
- " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<3 /* recrce */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<3 /* recrce */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
- " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<4 /* rpoison */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<4 /* rpoison */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
- " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<5 /* rcemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<5 /* rcemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
- " pedc_radm_correctable_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<6 /* rnfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<6 /* rnfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
- " pedc_radm_nonfatal_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<7 /* rfemrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<7 /* rfemrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
- " pedc_radm_fatal_err\n"
- " Bit set when a message with ERR_FATAL is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<8 /* rpmerc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<8 /* rpmerc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
- " pedc_radm_pm_pme\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<9 /* rptamrc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<9 /* rptamrc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
- " (RC Mode only)\n"
- " pedc_radm_pm_to_ack\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<10 /* rumep */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<10 /* rumep */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
- " pedc_radm_msg_unlock\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<11 /* rvdm */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<11 /* rvdm */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
- " pedc_radm_vendor_msg\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<12 /* acto */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<12 /* acto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
- " pedc_radm_cpl_timeout\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<13 /* rte */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<13 /* rte */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
- " xdlh_replay_timeout_err\n"
- " This bit is set when the REPLAY_TIMER expires in\n"
- " the PCIE core. The probability of this bit being\n"
- " set will increase with the traffic load.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<14 /* mre */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<14 /* mre */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
- " xdlh_replay_num_rlover_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<15 /* rdwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<15 /* rdwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
- " rdlh_bad_dllp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<16 /* rtwdle */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<16 /* rtwdle */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
- " rdlh_bad_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<17 /* dpeoosd */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<17 /* dpeoosd */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
- " rdlh_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<18 /* fcpvwt */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<18 /* fcpvwt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
- " rtlh_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<19 /* rpe */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<19 /* rpe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
- " (RxStatus = 3b100) or disparity error\n"
- " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
- " be asserted.\n"
- " rmlh_rcvd_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<20 /* fcuv */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<20 /* fcuv */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
- " int_xadm_fc_prot_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<21 /* rqo */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<21 /* rqo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
- " flow control advertisements are ignored\n"
- " radm_qoverflow\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<22 /* rauc */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<22 /* rauc */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
- " radm_unexp_cpl_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<23 /* racur */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<23 /* racur */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
- " radm_rcvd_cpl_ur\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<24 /* racca */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<24 /* racca */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
- " radm_rcvd_cpl_ca\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<25 /* caar */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<25 /* caar */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
- " radm_rcvd_ca_req\n"
- " This bit will never be set because Octeon does\n"
- " not generate Completer Aborts.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<26 /* rarwdns */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<26 /* rarwdns */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
- " radm_rcvd_ur_req\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<27 /* ramtlp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<27 /* ramtlp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
- " radm_mlf_tlp_err\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<28 /* racpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<28 /* racpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
- " radm_rcvd_cpl_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<29 /* rawwpp */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<29 /* rawwpp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
- " radm_rcvd_wreq_poisoned\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEMX_DBG_INFO(0);
- info.status_mask = 1ull<<30 /* ecrc_e */;
- info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
- info.enable_mask = 1ull<<30 /* ecrc_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
- info.parent.status_mask = 1ull<<10 /* exc */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
- " radm_ecrc_err\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PKO_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<0 /* parity */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* parity */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<1 /* doorbell */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<1 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PKO_REG_ERROR;
- info.status_mask = 1ull<<2 /* currzero */;
- info.enable_addr = CVMX_PKO_REG_INT_MASK;
- info.enable_mask = 1ull<<2 /* currzero */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<10 /* pko */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(0,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(0,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PCSX_INTX_REG(1,0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<2 /* an_err */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<2 /* an_err_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<3 /* txfifu */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<3 /* txfifu_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<4 /* txfifo */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<4 /* txfifo_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
- " condition\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<5 /* txbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<5 /* txbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<7 /* rxbad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<7 /* rxbad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<8 /* rxlock */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<8 /* rxlock_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
- " failure occurs\n"
- " Cannot fire in loopback1 mode\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<9 /* an_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<9 /* an_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<10 /* sync_bad */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<10 /* sync_bad_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
- " state. Should never be set during normal operation\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PCSX_INTX_REG(1,0);
- info.status_mask = 1ull<<12 /* dbg_sync */;
- info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
- info.enable_mask = 1ull<<12 /* dbg_sync_en */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_ETHERNET;
- info.group_index = 1;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PEXP_SLI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<0 /* rml_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
- " within 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<1 /* reserved_1_1 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<1 /* reserved_1_1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<2 /* bar0_to */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<2 /* bar0_to */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
- " read-data/commit in 0xffff core clocks.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<3 /* iob2big */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<3 /* iob2big */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 0x3ull<<6 /* reserved_6_7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<8 /* m0_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<8 /* m0_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<9 /* m0_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<9 /* m0_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<10 /* m0_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<10 /* m0_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<11 /* m0_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<11 /* m0_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 0. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<12 /* m1_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<12 /* m1_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<13 /* m1_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<13 /* m1_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<14 /* m1_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<14 /* m1_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
- " This occurs when the BAR 0 address space is\n"
- " disabeled.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<15 /* m1_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<15 /* m1_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
- " from MAC 1. This occurs when the window registers\n"
- " are disabeld and a window register access occurs.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<20 /* m2_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<20 /* m2_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UP_B0]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<21 /* m2_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<21 /* m2_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UP_WI]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<22 /* m2_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<22 /* m2_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UN_B0]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<23 /* m2_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<23 /* m2_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M2_UN_WI]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<24 /* m3_up_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<24 /* m3_up_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UP_B0]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<25 /* m3_up_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<25 /* m3_up_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UP_WI]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<26 /* m3_un_b0 */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<26 /* m3_un_b0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UN_B0]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<27 /* m3_un_wi */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<27 /* m3_un_wi */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[M3_UN_WI]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<48 /* pidbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<48 /* pidbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<49 /* psldbof */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<49 /* psldbof */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
- " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<50 /* pout_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<50 /* pout_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
- " set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<51 /* pin_bp */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<51 /* pin_bp */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
- " See SLI_PKT_IN_BP\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<52 /* pgl_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<52 /* pgl_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
- " read this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<53 /* pdi_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<53 /* pdi_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<54 /* pop_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<54 /* pop_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
- " pointer pair this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<55 /* pins_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<55 /* pins_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<56 /* sprt0_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<56 /* sprt0_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<57 /* sprt1_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<57 /* sprt1_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<58 /* sprt2_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<58 /* sprt2_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT2_ERR]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<59 /* sprt3_err */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<59 /* sprt3_err */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[SPRT3_ERR]: Reserved.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PEXP_SLI_INT_SUM;
- info.status_mask = 1ull<<60 /* ill_pad */;
- info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
- info.enable_mask = 1ull<<60 /* ill_pad */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<3 /* sli */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
- " range of the Packet-CSR, but for an unused\n"
- " address.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_KEY_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<0 /* ked0_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<0 /* ked0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<1 /* ked0_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<1 /* ked0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<2 /* ked1_sbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<2 /* ked1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_KEY_INT_SUM;
- info.status_mask = 1ull<<3 /* ked1_dbe */;
- info.enable_addr = CVMX_KEY_INT_ENB;
- info.enable_mask = 1ull<<3 /* ked1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<4 /* key */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
-;
- fail |= cvmx_error_add(&info);
-
- /* CVMX_UCTLX_INT_REG(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<0 /* pp_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<0 /* pp_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<1 /* er_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<1 /* er_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<2 /* or_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<2 /* or_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<3 /* cf_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<3 /* cf_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<4 /* wb_psh_f */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<4 /* wb_psh_f */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<5 /* wb_pop_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<5 /* wb_pop_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<6 /* oc_ovf_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<6 /* oc_ovf_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
- " When the error happenes, the whole NCB system needs\n"
- " to be reset.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_UCTLX_INT_REG(0);
- info.status_mask = 1ull<<7 /* ec_ovf_e */;
- info.enable_addr = CVMX_UCTLX_INT_ENA(0);
- info.enable_mask = 1ull<<7 /* ec_ovf_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_USB;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<13 /* usb */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
- " When the error happenes, the whole NCB system needs\n"
- " to be reset.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_PIP_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<3 /* prtnxa */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<3 /* prtnxa */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<4 /* badtag */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<4 /* badtag */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<5 /* skprunt */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<5 /* skprunt */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
- " This interrupt can occur with received PARTIAL\n"
- " packets that are truncated to SKIP bytes or\n"
- " smaller.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<6 /* todoovr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<6 /* todoovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<7 /* feperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<7 /* feperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<8 /* beperr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<8 /* beperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_PIP_INT_REG;
- info.status_mask = 1ull<<12 /* punyerr */;
- info.enable_addr = CVMX_PIP_INT_EN;
- info.enable_mask = 1ull<<12 /* punyerr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<20 /* pip */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
- " stripping in IPD is enable\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_FPA_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<0 /* fed0_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<0 /* fed0_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<1 /* fed0_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<1 /* fed0_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<2 /* fed1_sbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<2 /* fed1_sbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<3 /* fed1_dbe */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<3 /* fed1_dbe */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<4 /* q0_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<4 /* q0_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<5 /* q0_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<5 /* q0_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<6 /* q0_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<6 /* q0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<7 /* q1_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<7 /* q1_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<8 /* q1_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<8 /* q1_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<9 /* q1_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<9 /* q1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<10 /* q2_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<10 /* q2_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<11 /* q2_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<11 /* q2_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<12 /* q2_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<12 /* q2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<13 /* q3_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<13 /* q3_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<14 /* q3_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<14 /* q3_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<15 /* q3_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<15 /* q3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<16 /* q4_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<16 /* q4_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<17 /* q4_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<17 /* q4_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<18 /* q4_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<18 /* q4_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<19 /* q5_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<19 /* q5_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<20 /* q5_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<20 /* q5_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<21 /* q5_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<21 /* q5_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<22 /* q6_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<22 /* q6_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<23 /* q6_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<23 /* q6_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<24 /* q6_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<24 /* q6_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<25 /* q7_und */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<25 /* q7_und */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
- " negative.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<26 /* q7_coff */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<26 /* q7_coff */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
- " the count available is greater than than pointers\n"
- " present in the FPA.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<27 /* q7_perr */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<27 /* q7_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
- " the L2C does not have the FPA owner ship bit set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<28 /* pool0th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<28 /* pool0th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
- " FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<29 /* pool1th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<29 /* pool1th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
- " FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<30 /* pool2th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<30 /* pool2th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
- " FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<31 /* pool3th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<31 /* pool3th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
- " FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<32 /* pool4th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<32 /* pool4th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
- " FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<33 /* pool5th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<33 /* pool5th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
- " FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<34 /* pool6th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<34 /* pool6th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
- " FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<35 /* pool7th */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<35 /* pool7th */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
- " FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
- " allocated or de-allocated.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<36 /* free0 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<36 /* free0 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<37 /* free1 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<37 /* free1 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<38 /* free2 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<38 /* free2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<39 /* free3 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<39 /* free3 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<40 /* free4 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<40 /* free4 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<41 /* free5 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<41 /* free5 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<42 /* free6 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<42 /* free6 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<43 /* free7 */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<43 /* free7 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_FPA_INT_SUM;
- info.status_mask = 1ull<<49 /* paddr_e */;
- info.enable_addr = CVMX_FPA_INT_ENB;
- info.enable_mask = 1ull<<49 /* paddr_e */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<5 /* fpa */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
- " address range for a pool specified by\n"
- " FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_LMCX_INT(0) */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<1 /* sec_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<1 /* intr_sec_ena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 1ull<<0 /* nxm_wr_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_LMCX_INT(0);
- info.status_mask = 0xfull<<5 /* ded_err */;
- info.enable_addr = CVMX_LMCX_INT_EN(0);
- info.enable_mask = 1ull<<2 /* intr_ded_ena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_LMC;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<17 /* lmc0 */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
- " [0] corresponds to DQ[63:0]_c0_p0\n"
- " [1] corresponds to DQ[63:0]_c0_p1\n"
- " [2] corresponds to DQ[63:0]_c1_p0\n"
- " [3] corresponds to DQ[63:0]_c1_p1\n"
- " In 32b mode, ecc is calculated on 4 cycle worth of data\n"
- " [0] corresponds to [DQ[31:0]_c0_p1, DQ[31:0]_c0_p0]\n"
- " [1] corresponds to [DQ[31:0]_c1_p1, DQ[31:0]_c1_p0]\n"
- " [2] corresponds to [DQ[31:0]_c2_p1, DQ[31:0]_c2_p0]\n"
- " [3] corresponds to [DQ[31:0]_c3_p1, DQ[31:0]_c3_p0]\n"
- " where _cC_pP denotes cycle C and phase P\n"
- " Write of 1 will clear the corresponding error bit\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_IOB_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<0 /* np_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<0 /* np_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<1 /* np_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<1 /* np_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<2 /* p_sop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<2 /* p_sop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<3 /* p_eop */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<3 /* p_eop */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<4 /* np_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<4 /* np_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a non-passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_IOB_INT_SUM;
- info.status_mask = 1ull<<5 /* p_dat */;
- info.enable_addr = CVMX_IOB_INT_ENB;
- info.enable_mask = 1ull<<5 /* p_dat */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<30 /* iob */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
- " port for a passthrough packet.\n"
- " The first detected error associated with bits [5:0]\n"
- " of this register will only be set here. A new bit\n"
- " can be set when the previous reported bit is cleared.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_INT_REG */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<0 /* nderr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<0 /* nderr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
- " DPI received a NCB transaction on the outbound\n"
- " bus to the DPI deviceID, but the command was not\n"
- " recognized.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<1 /* nfovr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<1 /* nfovr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
- " DPI can store upto 16 CSR request. The FIFO will\n"
- " overflow if that number is exceeded.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 0xffull<<8 /* dmadbo */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 0xffull<<8 /* dmadbo */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
- " DPI has a 32-bit counter for each request's queue\n"
- " outstanding doorbell counts. Interrupt will fire\n"
- " if the count overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<16 /* req_badadr */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<16 /* req_badadr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch to the NULL pointer.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<17 /* req_badlen */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<17 /* req_badlen */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
- " Interrupt will fire if DPI forms an instruction\n"
- " fetch with length of zero.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<18 /* req_ovrflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<18 /* req_ovrflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO overflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<19 /* req_undflw */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<19 /* req_undflw */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
- " DPI tracks outstanding instructions fetches.\n"
- " Interrupt will fire when FIFO underflows.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<20 /* req_anull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<20 /* req_anull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
- " Fetched instruction word was 0.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<21 /* req_inull */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<21 /* req_inull */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
- " Next pointer was NULL.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<22 /* req_badfil */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<22 /* req_badfil */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
- " Instruction fill when none outstanding.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<24 /* sprt0_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<24 /* sprt0_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<25 /* sprt1_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<25 /* sprt1_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<26 /* sprt2_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<26 /* sprt2_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT2_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_INT_REG;
- info.status_mask = 1ull<<27 /* sprt3_rst */;
- info.enable_addr = CVMX_DPI_INT_EN;
- info.enable_mask = 1ull<<27 /* sprt3_rst */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_INT_REG[SPRT3_RST]: DMA instruction was dropped because the source or\n"
- " destination port was in reset.\n"
- " this bit is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_PKT_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_PKT_ERR_RSP;
- info.status_mask = 1ull<<0 /* pkterr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
- " the I/O subsystem.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RSP */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RSP;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
- " ErrorResponse from the I/O subsystem.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_DPI_REQ_ERR_RST */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_DPI_REQ_ERR_RST;
- info.status_mask = 0xffull<<0 /* qerr */;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<41 /* dpi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
- " instruction because the source or destination\n"
- " was in reset.\n"
- " SW must clear the bit before the the cooresponding\n"
- " instruction queue will continue processing\n"
- " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
- fail |= cvmx_error_add(&info);
-
- /* CVMX_RAD_REG_ERROR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_RAD_REG_ERROR;
- info.status_mask = 1ull<<0 /* doorbell */;
- info.enable_addr = CVMX_RAD_REG_INT_MASK;
- info.enable_mask = 1ull<<0 /* doorbell */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_CIU_BLOCK_INT;
- info.parent.status_mask = 1ull<<14 /* rad */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
- fail |= cvmx_error_add(&info);
-
- return fail;
-}
-
diff --git a/sys/contrib/octeon-sdk/cvmx-error.c b/sys/contrib/octeon-sdk/cvmx-error.c
deleted file mode 100644
index 5f13632..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error.c
+++ /dev/null
@@ -1,773 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Interface to the Octeon extended error status.
- *
- * <hr>$Revision: 44252 $<hr>
- */
-#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
-#include <asm/octeon/cvmx.h>
-#include <asm/octeon/cvmx-error.h>
-#include <asm/octeon/cvmx-error-custom.h>
-#include <asm/octeon/cvmx-pcie.h>
-#include <asm/octeon/cvmx-srio.h>
-#include <asm/octeon/cvmx-ciu2-defs.h>
-#include <asm/octeon/cvmx-dfm-defs.h>
-#include <asm/octeon/cvmx-lmcx-defs.h>
-#include <asm/octeon/cvmx-pexp-defs.h>
-#else
-#include "cvmx.h"
-#include "cvmx-error.h"
-#include "cvmx-error-custom.h"
-#include "cvmx-pcie.h"
-#include "cvmx-srio.h"
-#include "cvmx-interrupt.h"
-#endif
-
-#define MAX_TABLE_SIZE 1024 /* Max number of error status bits we can support */
-
-extern int cvmx_error_initialize_cnf71xx(void);
-extern int cvmx_error_initialize_cn68xx(void);
-extern int cvmx_error_initialize_cn68xxp1(void);
-extern int cvmx_error_initialize_cn66xx(void);
-extern int cvmx_error_initialize_cn63xx(void);
-extern int cvmx_error_initialize_cn63xxp1(void);
-extern int cvmx_error_initialize_cn61xx(void);
-extern int cvmx_error_initialize_cn58xxp1(void);
-extern int cvmx_error_initialize_cn58xx(void);
-extern int cvmx_error_initialize_cn56xxp1(void);
-extern int cvmx_error_initialize_cn56xx(void);
-extern int cvmx_error_initialize_cn50xx(void);
-extern int cvmx_error_initialize_cn52xxp1(void);
-extern int cvmx_error_initialize_cn52xx(void);
-extern int cvmx_error_initialize_cn38xxp2(void);
-extern int cvmx_error_initialize_cn38xx(void);
-extern int cvmx_error_initialize_cn31xx(void);
-extern int cvmx_error_initialize_cn30xx(void);
-
-/* Each entry in this array represents a status bit function or chain */
-static CVMX_SHARED cvmx_error_info_t __cvmx_error_table[MAX_TABLE_SIZE];
-static CVMX_SHARED int __cvmx_error_table_size = 0;
-static CVMX_SHARED cvmx_error_flags_t __cvmx_error_flags;
-
-#define REG_MATCH(h, reg_type, status_addr, status_mask) \
- ((h->reg_type == reg_type) && (h->status_addr == status_addr) && (h->status_mask == status_mask))
-
-/**
- * @INTERNAL
- * Read a status or enable register from the hardware
- *
- * @param reg_type Register type to read
- * @param addr Address to read
- *
- * @return Result of the read
- */
-static uint64_t __cvmx_error_read_hw(cvmx_error_register_t reg_type, uint64_t addr)
-{
- switch (reg_type)
- {
- case __CVMX_ERROR_REGISTER_NONE:
- return 0;
- case CVMX_ERROR_REGISTER_IO64:
- return cvmx_read_csr(addr);
- case CVMX_ERROR_REGISTER_IO32:
- return cvmx_read64_uint32(addr ^ 4);
- case CVMX_ERROR_REGISTER_PCICONFIG:
- return cvmx_pcie_cfgx_read(addr>>32, addr&0xffffffffull);
- case CVMX_ERROR_REGISTER_SRIOMAINT:
- {
- uint32_t r;
- if (cvmx_srio_config_read32(addr>>32, 0, -1, 0, 0, addr&0xffffffffull, &r))
- return 0;
- else
- return r;
- }
- }
- return 0;
-}
-
-/**
- * @INTERNAL
- * Write a status or enable register to the hardware
- *
- * @param reg_type Register type to write
- * @param addr Address to write
- * @param value Value to write
- */
-static void __cvmx_error_write_hw(cvmx_error_register_t reg_type, uint64_t addr, uint64_t value)
-{
- switch (reg_type)
- {
- case __CVMX_ERROR_REGISTER_NONE:
- return;
- case CVMX_ERROR_REGISTER_IO64:
- cvmx_write_csr(addr, value);
- return;
- case CVMX_ERROR_REGISTER_IO32:
- cvmx_write64_uint32(addr ^ 4, value);
- return;
- case CVMX_ERROR_REGISTER_PCICONFIG:
- cvmx_pcie_cfgx_write(addr>>32, addr&0xffffffffull, value);
- return;
- case CVMX_ERROR_REGISTER_SRIOMAINT:
- {
- cvmx_srio_config_write32(addr>>32, 0, -1, 0, 0, addr&0xffffffffull, value);
- return;
- }
- }
-}
-
-/**
- * @INTERNAL
- * Function for processing non leaf error status registers. This function
- * calls all handlers for this passed register and all children linked
- * to it.
- *
- * @param info Error register to check
- *
- * @return Number of error status bits found or zero if no bits were set.
- */
-int __cvmx_error_decode(const cvmx_error_info_t *info)
-{
- uint64_t status;
- uint64_t enable;
- int i;
- int handled = 0;
-
- /* Read the status and enable state */
- status = __cvmx_error_read_hw(info->reg_type, info->status_addr);
- if (info->enable_addr)
- enable = __cvmx_error_read_hw(info->reg_type, info->enable_addr);
- else
- enable = 0;
-
- for (i = 0; i < __cvmx_error_table_size; i++)
- {
- const cvmx_error_info_t *h = &__cvmx_error_table[i];
- uint64_t masked_status = status;
-
- /* If this is a child of the current register then recurse and process
- the child */
- if ((h->parent.reg_type == info->reg_type) &&
- (h->parent.status_addr == info->status_addr) &&
- (status & h->parent.status_mask))
- handled += __cvmx_error_decode(h);
-
- if ((h->reg_type != info->reg_type) || (h->status_addr != info->status_addr))
- continue;
-
- /* If the corresponding enable bit is not set then we have nothing to do */
- if (h->enable_addr && h->enable_mask)
- {
- if (!(enable & h->enable_mask))
- continue;
- }
-
- /* Apply the mask to eliminate irrelevant bits */
- if (h->status_mask)
- masked_status &= h->status_mask;
-
- /* Finally call the handler function unless it is this function */
- if (masked_status && h->func && (h->func != __cvmx_error_decode))
- handled += h->func(h);
- }
- /* Ths should be the total errors found */
- return handled;
-}
-
-/**
- * @INTERNAL
- * This error bit handler simply prints a message and clears the status bit
- *
- * @param info Error register to check
- *
- * @return
- */
-int __cvmx_error_display(const cvmx_error_info_t *info)
-{
- const char *message = (const char *)(long)info->user_info;
- /* This assumes that all bits in the status register are RO or R/W1C */
- __cvmx_error_write_hw(info->reg_type, info->status_addr, info->status_mask);
- cvmx_safe_printf("%s", message);
-
- /* Clear the source to reduce the chance for spurious interrupts. */
-
- /* CN68XX has an CIU-15786 errata that accessing the ACK registers
- * can stop interrupts from propagating
- */
- if (OCTEON_IS_MODEL(OCTEON_CN68XX))
- cvmx_read_csr(CVMX_CIU2_INTR_CIU_READY);
- else if (OCTEON_IS_MODEL(OCTEON_CN68XX))
- cvmx_read_csr(CVMX_CIU2_ACK_PPX_IP4(cvmx_get_core_num()));
-
- return 1;
-}
-
-/**
- * Initalize the error status system. This should be called once
- * before any other functions are called. This function adds default
- * handlers for most all error events but does not enable them. Later
- * calls to cvmx_error_enable() are needed.
- *
- * @param flags Optional flags.
- *
- * @return Zero on success, negative on failure.
- */
-int cvmx_error_initialize(cvmx_error_flags_t flags)
-{
- __cvmx_error_flags = flags;
- if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
- {
- if (cvmx_error_initialize_cnf71xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN68XX))
- {
- if (cvmx_error_initialize_cn68xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X))
- {
- if (cvmx_error_initialize_cn68xxp1())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
- {
- if (cvmx_error_initialize_cn66xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
- {
- if (cvmx_error_initialize_cn63xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
- {
- if (cvmx_error_initialize_cn63xxp1())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
- {
- if (cvmx_error_initialize_cn61xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS1_X))
- {
- if (cvmx_error_initialize_cn58xxp1())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN58XX))
- {
- if (cvmx_error_initialize_cn58xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
- {
- if (cvmx_error_initialize_cn56xxp1())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN56XX))
- {
- if (cvmx_error_initialize_cn56xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
- {
- if (cvmx_error_initialize_cn50xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
- {
- if (cvmx_error_initialize_cn52xxp1())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
- {
- if (cvmx_error_initialize_cn52xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
- {
- if (cvmx_error_initialize_cn38xxp2())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
- {
- if (cvmx_error_initialize_cn38xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
- {
- if (cvmx_error_initialize_cn31xx())
- return -1;
- }
- else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
- {
- if (cvmx_error_initialize_cn30xx())
- return -1;
- }
- else
- {
- cvmx_warn("cvmx_error_initialize() needs update for this Octeon model\n");
- return -1;
- }
-
- if (__cvmx_error_custom_initialize())
- return -1;
-
- /* Enable all of the purely internal error sources by default */
- cvmx_error_enable_group(CVMX_ERROR_GROUP_INTERNAL, 0);
-
- /* According to workaround for errata KEY-14814 in cn63xx, clearing
- SLI_INT_SUM[RML_TO] after enabling KEY interrupts */
- if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
- cvmx_write_csr(CVMX_PEXP_SLI_INT_SUM, 1);
-
- /* Enable DDR error reporting based on the memory controllers */
- if (OCTEON_IS_MODEL(OCTEON_CN56XX))
- {
- cvmx_l2c_cfg_t l2c_cfg;
- l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
- if (l2c_cfg.s.dpres0)
- cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, 0);
- if (l2c_cfg.s.dpres1)
- cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, 1);
- }
- else
- cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, 0);
-
- /* Enable error interrupts for other LMC only if it is
- available. */
- if (OCTEON_IS_MODEL(OCTEON_CN68XX))
- {
- int i;
- for (i = 1; i < 4; i++)
- {
- cvmx_lmcx_dll_ctl2_t ctl2;
- ctl2.u64 = cvmx_read_csr(CVMX_LMCX_DLL_CTL2(i));
- if (ctl2.s.intf_en)
- cvmx_error_enable_group(CVMX_ERROR_GROUP_LMC, i);
- }
- }
-
- /* Enable DFM error reporting based on feature availablility */
- if (octeon_has_feature(OCTEON_FEATURE_DFM))
- {
- /* Only configure interrupts if DFM clock is enabled. */
- cvmx_dfm_fnt_sclk_t dfm_fnt_sclk;
- dfm_fnt_sclk.u64 = cvmx_read_csr(CVMX_DFM_FNT_SCLK);
- if (!dfm_fnt_sclk.s.sclkdis)
- {
- cvmx_error_enable_group(CVMX_ERROR_GROUP_DFM, 0);
- }
- }
-
- /* Old PCI parts don't have a common PCI init, so enable error
- reporting if the bootloader told us we are a PCI host. PCIe
- is handled when cvmx_pcie_rc_initialize is called */
- if (!octeon_has_feature(OCTEON_FEATURE_PCIE) &&
- (cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST))
- cvmx_error_enable_group(CVMX_ERROR_GROUP_PCI, 0);
-
- /* Call poll once to clear out any pending interrupts */
- cvmx_error_poll();
-
- return 0;
-}
-
-/**
- * Poll the error status registers and call the appropriate error
- * handlers. This should be called in the RSL interrupt handler
- * for your application or operating system.
- *
- * @return Number of error handlers called. Zero means this call
- * found no errors and was spurious.
- */
-int cvmx_error_poll(void)
-{
- int i;
- int count = 0;
- /* Call all handlers that don't have a parent */
- for (i = 0; i < __cvmx_error_table_size; i++)
- if (__cvmx_error_table[i].parent.reg_type == __CVMX_ERROR_REGISTER_NONE)
- count += __cvmx_error_decode(&__cvmx_error_table[i]);
- return count;
-}
-
-/**
- * Register to be called when an error status bit is set. Most users
- * will not need to call this function as cvmx_error_initialize()
- * registers default handlers for most error conditions. This function
- * is normally used to add more handlers without changing the existing
- * handlers.
- *
- * @param new_info Information about the handler for a error register. The
- * structure passed is copied and can be destroyed after the
- * call. All members of the structure must be populated, even the
- * parent information.
- *
- * @return Zero on success, negative on failure.
- */
-int cvmx_error_add(const cvmx_error_info_t *new_info)
-{
- if (__cvmx_error_table_size >= MAX_TABLE_SIZE)
- {
- cvmx_warn("cvmx-error table full\n");
- return -1;
- }
- __cvmx_error_table[__cvmx_error_table_size] = *new_info;
- __cvmx_error_table_size++;
- return 0;
-}
-
-/**
- * Remove all handlers for a status register and mask. Normally
- * this function should not be called. Instead a new handler should be
- * installed to replace the existing handler. In the even that all
- * reporting of a error bit should be removed, then use this
- * function.
- *
- * @param reg_type Type of the status register to remove
- * @param status_addr
- * Status register to remove.
- * @param status_mask
- * All handlers for this status register with this mask will be
- * removed.
- * @param old_info If not NULL, this is filled with information about the handler
- * that was removed.
- *
- * @return Zero on success, negative on failure (not found).
- */
-int cvmx_error_remove(cvmx_error_register_t reg_type,
- uint64_t status_addr, uint64_t status_mask,
- cvmx_error_info_t *old_info)
-{
- int found = 0;
- int i;
- for (i = 0; i < __cvmx_error_table_size; i++)
- {
- cvmx_error_info_t *h = &__cvmx_error_table[i];
- if (!REG_MATCH(h, reg_type, status_addr, status_mask))
- continue;
- if (old_info)
- *old_info = *h;
- memset(h, 0, sizeof(*h));
- found = 1;
- }
- if (found)
- return 0;
- else
- {
- cvmx_warn("cvmx-error remove couldn't find requested register\n");
- return -1;
- }
-}
-
-/**
- * Change the function and user_info for an existing error status
- * register. This function should be used to replace the default
- * handler with an application specific version as needed.
- *
- * @param reg_type Type of the status register to change
- * @param status_addr
- * Status register to change.
- * @param status_mask
- * All handlers for this status register with this mask will be
- * changed.
- * @param new_func New function to use to handle the error status
- * @param new_user_info
- * New user info parameter for the function
- * @param old_func If not NULL, the old function is returned. Useful for restoring
- * the old handler.
- * @param old_user_info
- * If not NULL, the old user info parameter.
- *
- * @return Zero on success, negative on failure
- */
-int cvmx_error_change_handler(cvmx_error_register_t reg_type,
- uint64_t status_addr, uint64_t status_mask,
- cvmx_error_func_t new_func, uint64_t new_user_info,
- cvmx_error_func_t *old_func, uint64_t *old_user_info)
-{
- int found = 0;
- int i;
- for (i = 0; i < __cvmx_error_table_size; i++)
- {
- cvmx_error_info_t *h = &__cvmx_error_table[i];
- if (!REG_MATCH(h, reg_type, status_addr, status_mask))
- continue;
- if (old_func)
- *old_func = h->func;
- if (old_user_info)
- *old_user_info = h->user_info;
- h->func = new_func;
- h->user_info = new_user_info;
- found = 1;
- }
- if (found)
- return 0;
- else
- {
- cvmx_warn("cvmx-error change couldn't find requested register\n");
- return -1;
- }
-}
-
-/**
- * Enable all error registers for a logical group. This should be
- * called whenever a logical group is brought online.
- *
- * @param group Logical group to enable
- * @param group_index
- * Index for the group as defined in the cvmx_error_group_t
- * comments.
- *
- * @return Zero on success, negative on failure.
- */
-int cvmx_error_enable_group(cvmx_error_group_t group, int group_index)
-{
- int i;
- uint64_t enable;
-
- if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
- return 0;
-
- for (i = 0; i < __cvmx_error_table_size; i++)
- {
- const cvmx_error_info_t *h = &__cvmx_error_table[i];
- /* SGMII and XAUI has different ipd_port, use the same group_index
- for both the interfaces */
- switch(group_index)
- {
- case 0x840:
- group_index = 0x800;
- break;
- case 0xa40:
- group_index = 0xa00;
- break;
- case 0xb40:
- group_index = 0xb00;
- break;
- case 0xc40:
- group_index = 0xc00;
- break;
- }
-
- /* Skip entries that have a different group or group index. We
- also skip entries that don't have an enable */
- if ((h->group != group) || (h->group_index != group_index) || (!h->enable_addr))
- continue;
- /* Skip entries that have flags that don't match the user's
- selected flags */
- if (h->flags && (h->flags != (h->flags & __cvmx_error_flags)))
- continue;
- /* Update the enables for this entry */
- enable = __cvmx_error_read_hw(h->reg_type, h->enable_addr);
- if (h->reg_type == CVMX_ERROR_REGISTER_PCICONFIG)
- enable &= ~h->enable_mask; /* PCI bits have reversed polarity */
- else
- enable |= h->enable_mask;
- __cvmx_error_write_hw(h->reg_type, h->enable_addr, enable);
- }
- return 0;
-}
-
-/**
- * Disable all error registers for a logical group. This should be
- * called whenever a logical group is brought offline. Many blocks
- * will report spurious errors when offline unless this function
- * is called.
- *
- * @param group Logical group to disable
- * @param group_index
- * Index for the group as defined in the cvmx_error_group_t
- * comments.
- *
- * @return Zero on success, negative on failure.
- */
-int cvmx_error_disable_group(cvmx_error_group_t group, int group_index)
-{
- int i;
- uint64_t enable;
-
- if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
- return 0;
-
- for (i = 0; i < __cvmx_error_table_size; i++)
- {
- const cvmx_error_info_t *h = &__cvmx_error_table[i];
-
- /* SGMII and XAUI has different ipd_port, use the same group_index
- for both the interfaces */
- switch(group_index)
- {
- case 0x840:
- group_index = 0x800;
- break;
- case 0xa40:
- group_index = 0xa00;
- break;
- case 0xb40:
- group_index = 0xb00;
- break;
- case 0xc40:
- group_index = 0xc00;
- break;
- }
- /* Skip entries that have a different group or group index. We
- also skip entries that don't have an enable */
- if ((h->group != group) || (h->group_index != group_index) || (!h->enable_addr))
- continue;
- /* Update the enables for this entry */
- enable = __cvmx_error_read_hw(h->reg_type, h->enable_addr);
- if (h->reg_type == CVMX_ERROR_REGISTER_PCICONFIG)
- enable |= h->enable_mask; /* PCI bits have reversed polarity */
- else
- enable &= ~h->enable_mask;
- __cvmx_error_write_hw(h->reg_type, h->enable_addr, enable);
- }
- return 0;
-}
-
-/**
- * Enable all handlers for a specific status register mask.
- *
- * @param reg_type Type of the status register
- * @param status_addr
- * Status register address
- * @param status_mask
- * All handlers for this status register with this mask will be
- * enabled.
- *
- * @return Zero on success, negative on failure.
- */
-int cvmx_error_enable(cvmx_error_register_t reg_type,
- uint64_t status_addr, uint64_t status_mask)
-{
- int found = 0;
- int i;
- uint64_t enable;
- for (i = 0; i < __cvmx_error_table_size; i++)
- {
- cvmx_error_info_t *h = &__cvmx_error_table[i];
- if (!REG_MATCH(h, reg_type, status_addr, status_mask) || !h->enable_addr)
- continue;
- enable = __cvmx_error_read_hw(h->reg_type, h->enable_addr);
- if (h->reg_type == CVMX_ERROR_REGISTER_PCICONFIG)
- enable &= ~h->enable_mask; /* PCI bits have reversed polarity */
- else
- enable |= h->enable_mask;
- __cvmx_error_write_hw(h->reg_type, h->enable_addr, enable);
- h->flags &= ~CVMX_ERROR_FLAGS_DISABLED;
- found = 1;
- }
- if (found)
- return 0;
- else
- {
- cvmx_warn("cvmx-error enable couldn't find requested register\n");
- return -1;
- }
-}
-
-/**
- * Disable all handlers for a specific status register and mask.
- *
- * @param reg_type Type of the status register
- * @param status_addr
- * Status register address
- * @param status_mask
- * All handlers for this status register with this mask will be
- * disabled.
- *
- * @return Zero on success, negative on failure.
- */
-int cvmx_error_disable(cvmx_error_register_t reg_type,
- uint64_t status_addr, uint64_t status_mask)
-{
- int found = 0;
- int i;
- uint64_t enable;
- for (i = 0; i < __cvmx_error_table_size; i++)
- {
- cvmx_error_info_t *h = &__cvmx_error_table[i];
- if (!REG_MATCH(h, reg_type, status_addr, status_mask) || !h->enable_addr)
- continue;
- enable = __cvmx_error_read_hw(h->reg_type, h->enable_addr);
- if (h->reg_type == CVMX_ERROR_REGISTER_PCICONFIG)
- enable |= h->enable_mask; /* PCI bits have reversed polarity */
- else
- enable &= ~h->enable_mask;
- __cvmx_error_write_hw(h->reg_type, h->enable_addr, enable);
- h->flags |= CVMX_ERROR_FLAGS_DISABLED;
- found = 1;
- }
- if (found)
- return 0;
- else
- {
- cvmx_warn("cvmx-error disable couldn't find requested register\n");
- return -1;
- }
-}
-
-
-/**
- * Find the handler for a specific status register and mask
- *
- * @param status_addr
- * Status register address
- *
- * @return Return the handler on success or null on failure.
- */
-cvmx_error_info_t *cvmx_error_get_index(uint64_t status_addr)
-{
- int i;
- for (i = 0; i < __cvmx_error_table_size; i++)
- {
- if (__cvmx_error_table[i].status_addr == status_addr)
- return &__cvmx_error_table[i];
- }
-
- return NULL;
-}
diff --git a/sys/contrib/octeon-sdk/cvmx-error.h b/sys/contrib/octeon-sdk/cvmx-error.h
deleted file mode 100644
index f1ce492..0000000
--- a/sys/contrib/octeon-sdk/cvmx-error.h
+++ /dev/null
@@ -1,330 +0,0 @@
-/***********************license start***************
- * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
-
- * * Neither the name of Cavium Inc. nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
-
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
-
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
-
-
-/**
- * @file
- *
- * Interface to the Octeon extended error status.
- *
- * <hr>$Revision: 44252 $<hr>
- */
-#ifndef __CVMX_ERROR_H__
-#define __CVMX_ERROR_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * There are generally many error status bits associated with a
- * single logical group. The enumeration below is used to
- * communicate high level groups to the error infastructure so
- * error status bits can be enable or disabled in large groups.
- */
-typedef enum
-{
- CVMX_ERROR_GROUP_INTERNAL, /* All internal blocks that can always be enabled */
- CVMX_ERROR_GROUP_ETHERNET, /* All errors related to network traffic that should be enabled when a port is up. Indexed by IPD number */
- CVMX_ERROR_GROUP_MGMT_PORT, /* All errors related to the management ethernet ports that should be enabled when a port is up. Indexed by port number (0-1) */
- CVMX_ERROR_GROUP_PCI, /* All errors related to PCI/PCIe when the bus is up. Index by port number (0-1) */
- CVMX_ERROR_GROUP_SRIO, /* All errors related to SRIO when the bus is up. Index by port number (0-1) */
- CVMX_ERROR_GROUP_USB, /* All errors related to USB when the port is enabled. Index by port number (0-1) */
- CVMX_ERROR_GROUP_LMC, /* All errors related to LMC when the controller is enabled. Index by controller number (0-1) */
- CVMX_ERROR_GROUP_ILK, /* All errors related to ILK when the controller is enabled. Index by controller number (0-1) */
- CVMX_ERROR_GROUP_DFM, /* All errors related to DFM when the controller is enabled. */
-} cvmx_error_group_t;
-
-/**
- * When registering for interest in an error status register, the
- * type of the register needs to be known by cvmx-error. Most
- * registers are either IO64 or IO32, but some blocks contain
- * registers that can't be directly accessed. A good example of
- * would be PCIe extended error state stored in config space.
- */
-typedef enum
-{
- __CVMX_ERROR_REGISTER_NONE, /* Used internally */
- CVMX_ERROR_REGISTER_IO64, /* Status and enable registers are Octeon 64bit CSRs */
- CVMX_ERROR_REGISTER_IO32, /* Status and enable registers are Octeon 32bit CSRs */
- CVMX_ERROR_REGISTER_PCICONFIG, /* Status and enable registers are in PCI config space */
- CVMX_ERROR_REGISTER_SRIOMAINT, /* Status and enable registers are in SRIO maintenance space */
-} cvmx_error_register_t;
-
-/**
- * Flags representing special handling for some error registers.
- * These flags are passed to cvmx_error_initialize() to control
- * the handling of bits where the same flags were passed to the
- * added cvmx_error_info_t.
- */
-typedef enum
-{
- CVMX_ERROR_FLAGS_ECC_SINGLE_BIT = 1<<0, /* This is a ECC single bit error. Normally these can be ignored */
- CVMX_ERROR_FLAGS_CORRECTABLE = 1<<1, /* Some blocks have errors that can be silently corrected. This flags reports these */
- CVMX_ERROR_FLAGS_DISABLED = 1<<2, /* Flag used to signal a register should not be enable as part of the groups */
-} cvmx_error_flags_t;
-
-struct cvmx_error_info;
-/**
- * Error handling functions must have the following prototype.
- */
-typedef int (*cvmx_error_func_t)(const struct cvmx_error_info *info);
-
-/**
- * This structure is passed to all error handling functions.
- */
-typedef struct cvmx_error_info
-{
- cvmx_error_register_t reg_type; /* Type of registers used for the error */
- uint64_t status_addr; /* The address of the status register */
- uint64_t status_mask; /* Mask to apply to status register to detect asserted error */
- uint64_t enable_addr; /* The address of the enable register */
- uint64_t enable_mask; /* Mask to apply to enable register to allow error detection */
- cvmx_error_flags_t flags; /* Flags indicating special handling of this error */
- cvmx_error_group_t group; /* Group to associate this error register with */
- int group_index; /* Group index to associate this error register with */
- cvmx_error_func_t func; /* Function to call when the error is detected */
- uint64_t user_info; /* User supplied information for the error handler */
- struct
- {
- cvmx_error_register_t reg_type; /* Type of parent's register */
- uint64_t status_addr; /* The address of the parent's register */
- uint64_t status_mask; /* Mask to apply to parent's register */
- } parent;
-} cvmx_error_info_t;
-
-/**
- * Initalize the error status system. This should be called once
- * before any other functions are called. This function adds default
- * handlers for most all error events but does not enable them. Later
- * calls to cvmx_error_enable() are needed.
- *
- * @param flags Optional flags.
- *
- * @return Zero on success, negative on failure.
- */
-int cvmx_error_initialize(cvmx_error_flags_t flags);
-
-/**
- * Poll the error status registers and call the appropriate error
- * handlers. This should be called in the RSL interrupt handler
- * for your application or operating system.
- *
- * @return Number of error handlers called. Zero means this call
- * found no errors and was spurious.
- */
-int cvmx_error_poll(void);
-
-/**
- * Register to be called when an error status bit is set. Most users
- * will not need to call this function as cvmx_error_initialize()
- * registers default handlers for most error conditions. This function
- * is normally used to add more handlers without changing the existing
- * handlers.
- *
- * @param new_info Information about the handler for a error register. The
- * structure passed is copied and can be destroyed after the
- * call. All members of the structure must be populated, even the
- * parent information.
- *
- * @return Zero on success, negative on failure.
- */
-int cvmx_error_add(const cvmx_error_info_t *new_info);
-
-/**
- * Remove all handlers for a status register and mask. Normally
- * this function should not be called. Instead a new handler should be
- * installed to replace the existing handler. In the even that all
- * reporting of a error bit should be removed, then use this
- * function.
- *
- * @param reg_type Type of the status register to remove
- * @param status_addr
- * Status register to remove.
- * @param status_mask
- * All handlers for this status register with this mask will be
- * removed.
- * @param old_info If not NULL, this is filled with information about the handler
- * that was removed.
- *
- * @return Zero on success, negative on failure (not found).
- */
-int cvmx_error_remove(cvmx_error_register_t reg_type,
- uint64_t status_addr, uint64_t status_mask,
- cvmx_error_info_t *old_info);
-
-/**
- * Change the function and user_info for an existing error status
- * register. This function should be used to replace the default
- * handler with an application specific version as needed.
- *
- * @param reg_type Type of the status register to change
- * @param status_addr
- * Status register to change.
- * @param status_mask
- * All handlers for this status register with this mask will be
- * changed.
- * @param new_func New function to use to handle the error status
- * @param new_user_info
- * New user info parameter for the function
- * @param old_func If not NULL, the old function is returned. Useful for restoring
- * the old handler.
- * @param old_user_info
- * If not NULL, the old user info parameter.
- *
- * @return Zero on success, negative on failure
- */
-int cvmx_error_change_handler(cvmx_error_register_t reg_type,
- uint64_t status_addr, uint64_t status_mask,
- cvmx_error_func_t new_func, uint64_t new_user_info,
- cvmx_error_func_t *old_func, uint64_t *old_user_info);
-
-/**
- * Enable all error registers for a logical group. This should be
- * called whenever a logical group is brought online.
- *
- * @param group Logical group to enable
- * @param group_index
- * Index for the group as defined in the cvmx_error_group_t
- * comments.
- *
- * @return Zero on success, negative on failure.
- */
-#ifndef CVMX_BUILD_FOR_UBOOT
-int cvmx_error_enable_group(cvmx_error_group_t group, int group_index);
-#else
-/* Rather than conditionalize the calls throughout the executive to not enable
- interrupts in Uboot, simply make the enable function do nothing */
-static inline int cvmx_error_enable_group(cvmx_error_group_t group, int group_index)
-{
- return 0;
-}
-#endif
-
-/**
- * Disable all error registers for a logical group. This should be
- * called whenever a logical group is brought offline. Many blocks
- * will report spurious errors when offline unless this function
- * is called.
- *
- * @param group Logical group to disable
- * @param group_index
- * Index for the group as defined in the cvmx_error_group_t
- * comments.
- *
- * @return Zero on success, negative on failure.
- */
-#ifndef CVMX_BUILD_FOR_UBOOT
-int cvmx_error_disable_group(cvmx_error_group_t group, int group_index);
-#else
-/* Rather than conditionalize the calls throughout the executive to not disable
- interrupts in Uboot, simply make the enable function do nothing */
-static inline int cvmx_error_disable_group(cvmx_error_group_t group, int group_index)
-{
- return 0;
-}
-#endif
-
-/**
- * Enable all handlers for a specific status register mask.
- *
- * @param reg_type Type of the status register
- * @param status_addr
- * Status register address
- * @param status_mask
- * All handlers for this status register with this mask will be
- * enabled.
- *
- * @return Zero on success, negative on failure.
- */
-int cvmx_error_enable(cvmx_error_register_t reg_type,
- uint64_t status_addr, uint64_t status_mask);
-
-/**
- * Disable all handlers for a specific status register and mask.
- *
- * @param reg_type Type of the status register
- * @param status_addr
- * Status register address
- * @param status_mask
- * All handlers for this status register with this mask will be
- * disabled.
- *
- * @return Zero on success, negative on failure.
- */
-int cvmx_error_disable(cvmx_error_register_t reg_type,
- uint64_t status_addr, uint64_t status_mask);
-
-/**
- * @INTERNAL
- * Function for processing non leaf error status registers. This function
- * calls all handlers for this passed register and all children linked
- * to it.
- *
- * @param info Error register to check
- *
- * @return Number of error status bits found or zero if no bits were set.
- */
-int __cvmx_error_decode(const cvmx_error_info_t *info);
-
-/**
- * @INTERNAL
- * This error bit handler simply prints a message and clears the status bit
- *
- * @param info Error register to check
- *
- * @return
- */
-int __cvmx_error_display(const cvmx_error_info_t *info);
-
-/**
- * Find the handler for a specific status register and mask
- *
- * @param status_addr
- * Status register address
- *
- * @return Return the handler on success or null on failure.
- */
-cvmx_error_info_t *cvmx_error_get_index(uint64_t status_addr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/sys/contrib/octeon-sdk/cvmx-pcie.c b/sys/contrib/octeon-sdk/cvmx-pcie.c
index 38764de..088efcb 100644
--- a/sys/contrib/octeon-sdk/cvmx-pcie.c
+++ b/sys/contrib/octeon-sdk/cvmx-pcie.c
@@ -76,7 +76,9 @@
#include <asm/octeon/cvmx-wqe.h>
#else
#include "cvmx.h"
+#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
#include "cvmx-csr-db.h"
+#endif
#include "cvmx-pcie.h"
#include "cvmx-sysinfo.h"
#include "cvmx-swap.h"
diff --git a/sys/contrib/octeon-sdk/cvmx-twsi.c b/sys/contrib/octeon-sdk/cvmx-twsi.c
index 4b41ace..7824b98 100644
--- a/sys/contrib/octeon-sdk/cvmx-twsi.c
+++ b/sys/contrib/octeon-sdk/cvmx-twsi.c
@@ -59,8 +59,10 @@
#else
#include "cvmx.h"
#include "cvmx-twsi.h"
+#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
#include "cvmx-csr-db.h"
#endif
+#endif
//#define PRINT_TWSI_CONFIG
#ifdef PRINT_TWSI_CONFIG
diff --git a/sys/contrib/octeon-sdk/cvmx-usb.c b/sys/contrib/octeon-sdk/cvmx-usb.c
index 6c692b9..4124ac8 100644
--- a/sys/contrib/octeon-sdk/cvmx-usb.c
+++ b/sys/contrib/octeon-sdk/cvmx-usb.c
@@ -72,7 +72,9 @@
#include "cvmx-usb.h"
#include "cvmx-helper.h"
#include "cvmx-helper-board.h"
+#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
#include "cvmx-csr-db.h"
+#endif
#include "cvmx-swap.h"
#if !defined(CVMX_BUILD_FOR_FREEBSD_KERNEL)
#include "cvmx-error.h"
OpenPOWER on IntegriCloud